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igb: Cleanups to fix braces location warnings
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
74cfb2e1 4 Copyright(c) 2007-2014 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
74cfb2e1 16 this program; if not, see <http://www.gnu.org/licenses/>.
9d5c8243
AK		 17
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
20
21 Contact Information:
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25*******************************************************************************/
26
876d2d6f
JK		 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28
9d5c8243
AK		 29#include <linux/module.h>
30#include <linux/types.h>
31#include <linux/init.h>
b2cb09b1 32#include <linux/bitops.h>
9d5c8243
AK		 33#include <linux/vmalloc.h>
34#include <linux/pagemap.h>
35#include <linux/netdevice.h>
9d5c8243 36#include <linux/ipv6.h>
5a0e3ad6 37#include <linux/slab.h>
9d5c8243
AK		 38#include <net/checksum.h>
39#include <net/ip6_checksum.h>
c6cb090b 40#include <linux/net_tstamp.h>
9d5c8243
AK		 41#include <linux/mii.h>
42#include <linux/ethtool.h>
01789349 43#include <linux/if.h>
9d5c8243
AK		 44#include <linux/if_vlan.h>
45#include <linux/pci.h>
c54106bb 46#include <linux/pci-aspm.h>
9d5c8243
AK		 47#include <linux/delay.h>
48#include <linux/interrupt.h>
7d13a7d0
AD		 49#include <linux/ip.h>
50#include <linux/tcp.h>
51#include <linux/sctp.h>
9d5c8243 52#include <linux/if_ether.h>
40a914fa 53#include <linux/aer.h>
70c71606 54#include <linux/prefetch.h>
749ab2cd 55#include <linux/pm_runtime.h>
421e02f0 56#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 57#include <linux/dca.h>
58#endif
441fc6fd 59#include <linux/i2c.h>
9d5c8243
AK		 60#include "igb.h"
61
67b1b903
CW		 62#define MAJ 5
63#define MIN 0
66f40b8a 64#define BUILD 5
0d1fe82d 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 66__stringify(BUILD) "-k"
9d5c8243
AK		 67char igb_driver_name[] = "igb";
68char igb_driver_version[] = DRV_VERSION;
69static const char igb_driver_string[] =
70 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 71static const char igb_copyright[] =
74cfb2e1 72 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 73
9d5c8243
AK		 74static const struct e1000_info *igb_info_tbl[] = {
75 [board_82575] = &e1000_82575_info,
76};
77
a3aa1884 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
114 /* required last entry */
115 {0, }
116};
117
118MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
119
120void igb_reset(struct igb_adapter *);
121static int igb_setup_all_tx_resources(struct igb_adapter *);
122static int igb_setup_all_rx_resources(struct igb_adapter *);
123static void igb_free_all_tx_resources(struct igb_adapter *);
124static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 125static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 126static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 127static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 128static int igb_sw_init(struct igb_adapter *);
129static int igb_open(struct net_device *);
130static int igb_close(struct net_device *);
53c7d064 131static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 132static void igb_configure_tx(struct igb_adapter *);
133static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 134static void igb_clean_all_tx_rings(struct igb_adapter *);
135static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 136static void igb_clean_tx_ring(struct igb_ring *);
137static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 138static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 139static void igb_update_phy_info(unsigned long);
140static void igb_watchdog(unsigned long);
141static void igb_watchdog_task(struct work_struct *);
cd392f5c 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
144 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 145static int igb_change_mtu(struct net_device *, int);
146static int igb_set_mac(struct net_device *, void *);
68d480c4 147static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 148static irqreturn_t igb_intr(int irq, void *);
149static irqreturn_t igb_intr_msi(int irq, void *);
150static irqreturn_t igb_msix_other(int irq, void *);
047e0030 151static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 152#ifdef CONFIG_IGB_DCA
047e0030 153static void igb_update_dca(struct igb_q_vector *);
fe4506b6 154static void igb_setup_dca(struct igb_adapter *);
421e02f0 155#endif /* CONFIG_IGB_DCA */
661086df 156static int igb_poll(struct napi_struct *, int);
13fde97a 157static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 158static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
160static void igb_tx_timeout(struct net_device *);
161static void igb_reset_task(struct work_struct *);
c8f44aff 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 165static void igb_restore_vlan(struct igb_adapter *);
26ad9178 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 167static void igb_ping_all_vfs(struct igb_adapter *);
168static void igb_msg_task(struct igb_adapter *);
4ae196df 169static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
173static int igb_ndo_set_vf_vlan(struct net_device *netdev,
174 int vf, u16 vlan, u8 qos);
175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
177 bool setting);
8151d294
WM		 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
179 struct ifla_vf_info *ivi);
17dc566c 180static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 181
182#ifdef CONFIG_PCI_IOV
0224d663 183static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 185#endif
9d5c8243 186
9d5c8243 187#ifdef CONFIG_PM
d9dd966d 188#ifdef CONFIG_PM_SLEEP
749ab2cd 189static int igb_suspend(struct device *);
d9dd966d 190#endif
749ab2cd
YZ		 191static int igb_resume(struct device *);
192#ifdef CONFIG_PM_RUNTIME
193static int igb_runtime_suspend(struct device *dev);
194static int igb_runtime_resume(struct device *dev);
195static int igb_runtime_idle(struct device *dev);
196#endif
197static const struct dev_pm_ops igb_pm_ops = {
198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
200 igb_runtime_idle)
201};
9d5c8243
AK		 202#endif
203static void igb_shutdown(struct pci_dev *);
fa44f2f1 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 205#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
207static struct notifier_block dca_notifier = {
208 .notifier_call = igb_notify_dca,
209 .next = NULL,
210 .priority = 0
211};
212#endif
9d5c8243
AK		 213#ifdef CONFIG_NET_POLL_CONTROLLER
214/* for netdump / net console */
215static void igb_netpoll(struct net_device *);
216#endif
37680117 217#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 218static unsigned int max_vfs = 0;
219module_param(max_vfs, uint, 0);
c75c4edf 220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 221#endif /* CONFIG_PCI_IOV */
222
9d5c8243
AK		 223static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
224 pci_channel_state_t);
225static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
226static void igb_io_resume(struct pci_dev *);
227
3646f0e5 228static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 229 .error_detected = igb_io_error_detected,
230 .slot_reset = igb_io_slot_reset,
231 .resume = igb_io_resume,
232};
233
b6e0c419 234static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 235
236static struct pci_driver igb_driver = {
237 .name = igb_driver_name,
238 .id_table = igb_pci_tbl,
239 .probe = igb_probe,
9f9a12f8 240 .remove = igb_remove,
9d5c8243 241#ifdef CONFIG_PM
749ab2cd 242 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 243#endif
244 .shutdown = igb_shutdown,
fa44f2f1 245 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 246 .err_handler = &igb_err_handler
247};
248
249MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
250MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
251MODULE_LICENSE("GPL");
252MODULE_VERSION(DRV_VERSION);
253
b3f4d599 254#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
255static int debug = -1;
256module_param(debug, int, 0);
257MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
258
c97ec42a
TI		 259struct igb_reg_info {
260 u32 ofs;
261 char *name;
262};
263
264static const struct igb_reg_info igb_reg_info_tbl[] = {
265
266 /* General Registers */
267 {E1000_CTRL, "CTRL"},
268 {E1000_STATUS, "STATUS"},
269 {E1000_CTRL_EXT, "CTRL_EXT"},
270
271 /* Interrupt Registers */
272 {E1000_ICR, "ICR"},
273
274 /* RX Registers */
275 {E1000_RCTL, "RCTL"},
276 {E1000_RDLEN(0), "RDLEN"},
277 {E1000_RDH(0), "RDH"},
278 {E1000_RDT(0), "RDT"},
279 {E1000_RXDCTL(0), "RXDCTL"},
280 {E1000_RDBAL(0), "RDBAL"},
281 {E1000_RDBAH(0), "RDBAH"},
282
283 /* TX Registers */
284 {E1000_TCTL, "TCTL"},
285 {E1000_TDBAL(0), "TDBAL"},
286 {E1000_TDBAH(0), "TDBAH"},
287 {E1000_TDLEN(0), "TDLEN"},
288 {E1000_TDH(0), "TDH"},
289 {E1000_TDT(0), "TDT"},
290 {E1000_TXDCTL(0), "TXDCTL"},
291 {E1000_TDFH, "TDFH"},
292 {E1000_TDFT, "TDFT"},
293 {E1000_TDFHS, "TDFHS"},
294 {E1000_TDFPC, "TDFPC"},
295
296 /* List Terminator */
297 {}
298};
299
b980ac18 300/* igb_regdump - register printout routine */
c97ec42a
TI		 301static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
302{
303 int n = 0;
304 char rname[16];
305 u32 regs[8];
306
307 switch (reginfo->ofs) {
308 case E1000_RDLEN(0):
309 for (n = 0; n < 4; n++)
310 regs[n] = rd32(E1000_RDLEN(n));
311 break;
312 case E1000_RDH(0):
313 for (n = 0; n < 4; n++)
314 regs[n] = rd32(E1000_RDH(n));
315 break;
316 case E1000_RDT(0):
317 for (n = 0; n < 4; n++)
318 regs[n] = rd32(E1000_RDT(n));
319 break;
320 case E1000_RXDCTL(0):
321 for (n = 0; n < 4; n++)
322 regs[n] = rd32(E1000_RXDCTL(n));
323 break;
324 case E1000_RDBAL(0):
325 for (n = 0; n < 4; n++)
326 regs[n] = rd32(E1000_RDBAL(n));
327 break;
328 case E1000_RDBAH(0):
329 for (n = 0; n < 4; n++)
330 regs[n] = rd32(E1000_RDBAH(n));
331 break;
332 case E1000_TDBAL(0):
333 for (n = 0; n < 4; n++)
334 regs[n] = rd32(E1000_RDBAL(n));
335 break;
336 case E1000_TDBAH(0):
337 for (n = 0; n < 4; n++)
338 regs[n] = rd32(E1000_TDBAH(n));
339 break;
340 case E1000_TDLEN(0):
341 for (n = 0; n < 4; n++)
342 regs[n] = rd32(E1000_TDLEN(n));
343 break;
344 case E1000_TDH(0):
345 for (n = 0; n < 4; n++)
346 regs[n] = rd32(E1000_TDH(n));
347 break;
348 case E1000_TDT(0):
349 for (n = 0; n < 4; n++)
350 regs[n] = rd32(E1000_TDT(n));
351 break;
352 case E1000_TXDCTL(0):
353 for (n = 0; n < 4; n++)
354 regs[n] = rd32(E1000_TXDCTL(n));
355 break;
356 default:
876d2d6f 357 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 358 return;
359 }
360
361 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 362 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
363 regs[2], regs[3]);
c97ec42a
TI		 364}
365
b980ac18 366/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 367static void igb_dump(struct igb_adapter *adapter)
368{
369 struct net_device *netdev = adapter->netdev;
370 struct e1000_hw *hw = &adapter->hw;
371 struct igb_reg_info *reginfo;
c97ec42a
TI		 372 struct igb_ring *tx_ring;
373 union e1000_adv_tx_desc *tx_desc;
374 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 375 struct igb_ring *rx_ring;
376 union e1000_adv_rx_desc *rx_desc;
377 u32 staterr;
6ad4edfc 378 u16 i, n;
c97ec42a
TI		 379
380 if (!netif_msg_hw(adapter))
381 return;
382
383 /* Print netdevice Info */
384 if (netdev) {
385 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 386 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
388 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 389 }
390
391 /* Print Registers */
392 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 393 pr_info(" Register Name Value\n");
c97ec42a
TI		 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
395 reginfo->name; reginfo++) {
396 igb_regdump(hw, reginfo);
397 }
398
399 /* Print TX Ring Summary */
400 if (!netdev || !netif_running(netdev))
401 goto exit;
402
403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 405 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 406 struct igb_tx_buffer *buffer_info;
c97ec42a 407 tx_ring = adapter->tx_ring[n];
06034649 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
410 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 411 (u64)dma_unmap_addr(buffer_info, dma),
412 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 413 buffer_info->next_to_watch,
414 (u64)buffer_info->time_stamp);
c97ec42a
TI		 415 }
416
417 /* Print TX Rings */
418 if (!netif_msg_tx_done(adapter))
419 goto rx_ring_summary;
420
421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
422
423 /* Transmit Descriptor Formats
424 *
425 * Advanced Transmit Descriptor
426 * +--------------------------------------------------------------+
427 * 0 | Buffer Address [63:0] |
428 * +--------------------------------------------------------------+
429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
430 * +--------------------------------------------------------------+
431 * 63 46 45 40 39 38 36 35 32 31 24 15 0
432 */
433
434 for (n = 0; n < adapter->num_tx_queues; n++) {
435 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 436 pr_info("------------------------------------\n");
437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
438 pr_info("------------------------------------\n");
c75c4edf 439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 440
441 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 442 const char *next_desc;
06034649 443 struct igb_tx_buffer *buffer_info;
60136906 444 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 445 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 446 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 447 if (i == tx_ring->next_to_use &&
448 i == tx_ring->next_to_clean)
449 next_desc = " NTC/U";
450 else if (i == tx_ring->next_to_use)
451 next_desc = " NTU";
452 else if (i == tx_ring->next_to_clean)
453 next_desc = " NTC";
454 else
455 next_desc = "";
456
c75c4edf
CW		 457 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
458 i, le64_to_cpu(u0->a),
c97ec42a 459 le64_to_cpu(u0->b),
c9f14bf3
AD		 460 (u64)dma_unmap_addr(buffer_info, dma),
461 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 462 buffer_info->next_to_watch,
463 (u64)buffer_info->time_stamp,
876d2d6f 464 buffer_info->skb, next_desc);
c97ec42a 465
b669588a 466 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 467 print_hex_dump(KERN_INFO, "",
468 DUMP_PREFIX_ADDRESS,
b669588a 469 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 470 dma_unmap_len(buffer_info, len),
471 true);
c97ec42a
TI		 472 }
473 }
474
475 /* Print RX Rings Summary */
476rx_ring_summary:
477 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 478 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 479 for (n = 0; n < adapter->num_rx_queues; n++) {
480 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 481 pr_info(" %5d %5X %5X\n",
482 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 483 }
484
485 /* Print RX Rings */
486 if (!netif_msg_rx_status(adapter))
487 goto exit;
488
489 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
490
491 /* Advanced Receive Descriptor (Read) Format
492 * 63 1 0
493 * +-----------------------------------------------------+
494 * 0 | Packet Buffer Address [63:1] |A0/NSE|
495 * +----------------------------------------------+------+
496 * 8 | Header Buffer Address [63:1] | DD |
497 * +-----------------------------------------------------+
498 *
499 *
500 * Advanced Receive Descriptor (Write-Back) Format
501 *
502 * 63 48 47 32 31 30 21 20 17 16 4 3 0
503 * +------------------------------------------------------+
504 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
505 * | Checksum Ident | | | | Type | Type |
506 * +------------------------------------------------------+
507 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
508 * +------------------------------------------------------+
509 * 63 48 47 32 31 20 19 0
510 */
511
512 for (n = 0; n < adapter->num_rx_queues; n++) {
513 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 514 pr_info("------------------------------------\n");
515 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
516 pr_info("------------------------------------\n");
c75c4edf
CW		 517 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 519
520 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 521 const char *next_desc;
06034649
AD		 522 struct igb_rx_buffer *buffer_info;
523 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 524 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 525 u0 = (struct my_u0 *)rx_desc;
526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 527
528 if (i == rx_ring->next_to_use)
529 next_desc = " NTU";
530 else if (i == rx_ring->next_to_clean)
531 next_desc = " NTC";
532 else
533 next_desc = "";
534
c97ec42a
TI		 535 if (staterr & E1000_RXD_STAT_DD) {
536 /* Descriptor Done */
1a1c225b
AD		 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
538 "RWB", i,
c97ec42a
TI		 539 le64_to_cpu(u0->a),
540 le64_to_cpu(u0->b),
1a1c225b 541 next_desc);
c97ec42a 542 } else {
1a1c225b
AD		 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
544 "R ", i,
c97ec42a
TI		 545 le64_to_cpu(u0->a),
546 le64_to_cpu(u0->b),
547 (u64)buffer_info->dma,
1a1c225b 548 next_desc);
c97ec42a 549
b669588a 550 if (netif_msg_pktdata(adapter) &&
1a1c225b 551 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 552 print_hex_dump(KERN_INFO, "",
553 DUMP_PREFIX_ADDRESS,
554 16, 1,
b669588a
ET		 555 page_address(buffer_info->page) +
556 buffer_info->page_offset,
de78d1f9 557 IGB_RX_BUFSZ, true);
c97ec42a
TI		 558 }
559 }
c97ec42a
TI		 560 }
561 }
562
563exit:
564 return;
565}
566
b980ac18
JK		 567/**
568 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 569 * @hw: pointer to hardware structure
570 * @i2cctl: Current value of I2CCTL register
571 *
572 * Returns the I2C data bit value
b980ac18 573 **/
441fc6fd
CW		 574static int igb_get_i2c_data(void *data)
575{
576 struct igb_adapter *adapter = (struct igb_adapter *)data;
577 struct e1000_hw *hw = &adapter->hw;
578 s32 i2cctl = rd32(E1000_I2CPARAMS);
579
580 return ((i2cctl & E1000_I2C_DATA_IN) != 0);
581}
582
b980ac18
JK		 583/**
584 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 585 * @data: pointer to hardware structure
586 * @state: I2C data value (0 or 1) to set
587 *
588 * Sets the I2C data bit
b980ac18 589 **/
441fc6fd
CW		 590static void igb_set_i2c_data(void *data, int state)
591{
592 struct igb_adapter *adapter = (struct igb_adapter *)data;
593 struct e1000_hw *hw = &adapter->hw;
594 s32 i2cctl = rd32(E1000_I2CPARAMS);
595
596 if (state)
597 i2cctl |= E1000_I2C_DATA_OUT;
598 else
599 i2cctl &= ~E1000_I2C_DATA_OUT;
600
601 i2cctl &= ~E1000_I2C_DATA_OE_N;
602 i2cctl |= E1000_I2C_CLK_OE_N;
603 wr32(E1000_I2CPARAMS, i2cctl);
604 wrfl();
605
606}
607
b980ac18
JK		 608/**
609 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 610 * @data: pointer to hardware structure
611 * @state: state to set clock
612 *
613 * Sets the I2C clock line to state
b980ac18 614 **/
441fc6fd
CW		 615static void igb_set_i2c_clk(void *data, int state)
616{
617 struct igb_adapter *adapter = (struct igb_adapter *)data;
618 struct e1000_hw *hw = &adapter->hw;
619 s32 i2cctl = rd32(E1000_I2CPARAMS);
620
621 if (state) {
622 i2cctl |= E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 } else {
625 i2cctl &= ~E1000_I2C_CLK_OUT;
626 i2cctl &= ~E1000_I2C_CLK_OE_N;
627 }
628 wr32(E1000_I2CPARAMS, i2cctl);
629 wrfl();
630}
631
b980ac18
JK		 632/**
633 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 634 * @data: pointer to hardware structure
635 *
636 * Gets the I2C clock state
b980ac18 637 **/
441fc6fd
CW		 638static int igb_get_i2c_clk(void *data)
639{
640 struct igb_adapter *adapter = (struct igb_adapter *)data;
641 struct e1000_hw *hw = &adapter->hw;
642 s32 i2cctl = rd32(E1000_I2CPARAMS);
643
644 return ((i2cctl & E1000_I2C_CLK_IN) != 0);
645}
646
647static const struct i2c_algo_bit_data igb_i2c_algo = {
648 .setsda = igb_set_i2c_data,
649 .setscl = igb_set_i2c_clk,
650 .getsda = igb_get_i2c_data,
651 .getscl = igb_get_i2c_clk,
652 .udelay = 5,
653 .timeout = 20,
654};
655
9d5c8243 656/**
b980ac18
JK		 657 * igb_get_hw_dev - return device
658 * @hw: pointer to hardware structure
659 *
660 * used by hardware layer to print debugging information
9d5c8243 661 **/
c041076a 662struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 663{
664 struct igb_adapter *adapter = hw->back;
c041076a 665 return adapter->netdev;
9d5c8243 666}
38c845c7 667
9d5c8243 668/**
b980ac18 669 * igb_init_module - Driver Registration Routine
9d5c8243 670 *
b980ac18
JK		 671 * igb_init_module is the first routine called when the driver is
672 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 673 **/
674static int __init igb_init_module(void)
675{
676 int ret;
876d2d6f 677 pr_info("%s - version %s\n",
9d5c8243
AK		 678 igb_driver_string, igb_driver_version);
679
876d2d6f 680 pr_info("%s\n", igb_copyright);
9d5c8243 681
421e02f0 682#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 683 dca_register_notify(&dca_notifier);
684#endif
bbd98fe4 685 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 686 return ret;
687}
688
689module_init(igb_init_module);
690
691/**
b980ac18 692 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 693 *
b980ac18
JK		 694 * igb_exit_module is called just before the driver is removed
695 * from memory.
9d5c8243
AK		 696 **/
697static void __exit igb_exit_module(void)
698{
421e02f0 699#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 700 dca_unregister_notify(&dca_notifier);
701#endif
9d5c8243
AK		 702 pci_unregister_driver(&igb_driver);
703}
704
705module_exit(igb_exit_module);
706
26bc19ec
AD		 707#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
708/**
b980ac18
JK		 709 * igb_cache_ring_register - Descriptor ring to register mapping
710 * @adapter: board private structure to initialize
26bc19ec 711 *
b980ac18
JK		 712 * Once we know the feature-set enabled for the device, we'll cache
713 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 714 **/
715static void igb_cache_ring_register(struct igb_adapter *adapter)
716{
ee1b9f06 717 int i = 0, j = 0;
047e0030 718 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 719
720 switch (adapter->hw.mac.type) {
721 case e1000_82576:
722 /* The queues are allocated for virtualization such that VF 0
723 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
724 * In order to avoid collision we start at the first free queue
725 * and continue consuming queues in the same sequence
726 */
ee1b9f06 727 if (adapter->vfs_allocated_count) {
a99955fc 728 for (; i < adapter->rss_queues; i++)
3025a446 729 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 730 Q_IDX_82576(i);
ee1b9f06 731 }
26bc19ec 732 case e1000_82575:
55cac248 733 case e1000_82580:
d2ba2ed8 734 case e1000_i350:
ceb5f13b 735 case e1000_i354:
f96a8a0b
CW		 736 case e1000_i210:
737 case e1000_i211:
26bc19ec 738 default:
ee1b9f06 739 for (; i < adapter->num_rx_queues; i++)
3025a446 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 741 for (; j < adapter->num_tx_queues; j++)
3025a446 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 743 break;
744 }
745}
746
22a8b291
FT		 747u32 igb_rd32(struct e1000_hw *hw, u32 reg)
748{
749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
751 u32 value = 0;
752
753 if (E1000_REMOVED(hw_addr))
754 return ~value;
755
756 value = readl(&hw_addr[reg]);
757
758 /* reads should not return all F's */
759 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
760 struct net_device *netdev = igb->netdev;
761 hw->hw_addr = NULL;
762 netif_device_detach(netdev);
763 netdev_err(netdev, "PCIe link lost, device now detached\n");
764 }
765
766 return value;
767}
768
4be000c8
AD		 769/**
770 * igb_write_ivar - configure ivar for given MSI-X vector
771 * @hw: pointer to the HW structure
772 * @msix_vector: vector number we are allocating to a given ring
773 * @index: row index of IVAR register to write within IVAR table
774 * @offset: column offset of in IVAR, should be multiple of 8
775 *
776 * This function is intended to handle the writing of the IVAR register
777 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
778 * each containing an cause allocation for an Rx and Tx ring, and a
779 * variable number of rows depending on the number of queues supported.
780 **/
781static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
782 int index, int offset)
783{
784 u32 ivar = array_rd32(E1000_IVAR0, index);
785
786 /* clear any bits that are currently set */
787 ivar &= ~((u32)0xFF << offset);
788
789 /* write vector and valid bit */
790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
791
792 array_wr32(E1000_IVAR0, index, ivar);
793}
794
9d5c8243 795#define IGB_N0_QUEUE -1
047e0030 796static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 797{
047e0030 798 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 799 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 800 int rx_queue = IGB_N0_QUEUE;
801 int tx_queue = IGB_N0_QUEUE;
4be000c8 802 u32 msixbm = 0;
047e0030 803
0ba82994
AD		 804 if (q_vector->rx.ring)
805 rx_queue = q_vector->rx.ring->reg_idx;
806 if (q_vector->tx.ring)
807 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 808
809 switch (hw->mac.type) {
810 case e1000_82575:
9d5c8243 811 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one
813 * or more queues to a vector, we write the appropriate bits
814 * into the MSIXBM register for that vector.
815 */
047e0030 816 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 818 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 821 msixbm |= E1000_EIMS_OTHER;
9d5c8243 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 823 q_vector->eims_value = msixbm;
2d064c06
AD		 824 break;
825 case e1000_82576:
b980ac18 826 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 827 * with 8 rows. The ordering is column-major so we use the
828 * lower 3 bits as the row index, and the 4th bit as the
829 * column offset.
830 */
831 if (rx_queue > IGB_N0_QUEUE)
832 igb_write_ivar(hw, msix_vector,
833 rx_queue & 0x7,
834 (rx_queue & 0x8) << 1);
835 if (tx_queue > IGB_N0_QUEUE)
836 igb_write_ivar(hw, msix_vector,
837 tx_queue & 0x7,
838 ((tx_queue & 0x8) << 1) + 8);
047e0030 839 q_vector->eims_value = 1 << msix_vector;
2d064c06 840 break;
55cac248 841 case e1000_82580:
d2ba2ed8 842 case e1000_i350:
ceb5f13b 843 case e1000_i354:
f96a8a0b
CW		 844 case e1000_i210:
845 case e1000_i211:
b980ac18 846 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 847 * however instead of ordering column-major we have things
848 * ordered row-major. So we traverse the table by using
849 * bit 0 as the column offset, and the remaining bits as the
850 * row index.
851 */
852 if (rx_queue > IGB_N0_QUEUE)
853 igb_write_ivar(hw, msix_vector,
854 rx_queue >> 1,
855 (rx_queue & 0x1) << 4);
856 if (tx_queue > IGB_N0_QUEUE)
857 igb_write_ivar(hw, msix_vector,
858 tx_queue >> 1,
859 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 860 q_vector->eims_value = 1 << msix_vector;
861 break;
2d064c06
AD		 862 default:
863 BUG();
864 break;
865 }
26b39276
AD		 866
867 /* add q_vector eims value to global eims_enable_mask */
868 adapter->eims_enable_mask |= q_vector->eims_value;
869
870 /* configure q_vector to set itr on first interrupt */
871 q_vector->set_itr = 1;
9d5c8243
AK		 872}
873
874/**
b980ac18
JK		 875 * igb_configure_msix - Configure MSI-X hardware
876 * @adapter: board private structure to initialize
9d5c8243 877 *
b980ac18
JK		 878 * igb_configure_msix sets up the hardware to properly
879 * generate MSI-X interrupts.
9d5c8243
AK		 880 **/
881static void igb_configure_msix(struct igb_adapter *adapter)
882{
883 u32 tmp;
884 int i, vector = 0;
885 struct e1000_hw *hw = &adapter->hw;
886
887 adapter->eims_enable_mask = 0;
9d5c8243
AK		 888
889 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 890 switch (hw->mac.type) {
891 case e1000_82575:
9d5c8243
AK		 892 tmp = rd32(E1000_CTRL_EXT);
893 /* enable MSI-X PBA support*/
894 tmp |= E1000_CTRL_EXT_PBA_CLR;
895
896 /* Auto-Mask interrupts upon ICR read. */
897 tmp |= E1000_CTRL_EXT_EIAME;
898 tmp |= E1000_CTRL_EXT_IRCA;
899
900 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 901
902 /* enable msix_other interrupt */
b980ac18 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 904 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 905
2d064c06
AD		 906 break;
907
908 case e1000_82576:
55cac248 909 case e1000_82580:
d2ba2ed8 910 case e1000_i350:
ceb5f13b 911 case e1000_i354:
f96a8a0b
CW		 912 case e1000_i210:
913 case e1000_i211:
047e0030 914 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 915 * won't stick. And it will take days to debug.
916 */
047e0030 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 918 E1000_GPIE_PBA | E1000_GPIE_EIAME |
919 E1000_GPIE_NSICR);
047e0030
AD		 920
921 /* enable msix_other interrupt */
922 adapter->eims_other = 1 << vector;
2d064c06 923 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 924
047e0030 925 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 926 break;
927 default:
928 /* do nothing, since nothing else supports MSI-X */
929 break;
930 } /* switch (hw->mac.type) */
047e0030
AD		 931
932 adapter->eims_enable_mask |= adapter->eims_other;
933
26b39276
AD		 934 for (i = 0; i < adapter->num_q_vectors; i++)
935 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 936
9d5c8243
AK		 937 wrfl();
938}
939
940/**
b980ac18
JK		 941 * igb_request_msix - Initialize MSI-X interrupts
942 * @adapter: board private structure to initialize
9d5c8243 943 *
b980ac18
JK		 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
945 * kernel.
9d5c8243
AK		 946 **/
947static int igb_request_msix(struct igb_adapter *adapter)
948{
949 struct net_device *netdev = adapter->netdev;
047e0030 950 struct e1000_hw *hw = &adapter->hw;
52285b76 951 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 952
047e0030 953 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 954 igb_msix_other, 0, netdev->name, adapter);
047e0030 955 if (err)
52285b76 956 goto err_out;
047e0030
AD		 957
958 for (i = 0; i < adapter->num_q_vectors; i++) {
959 struct igb_q_vector *q_vector = adapter->q_vector[i];
960
52285b76
SA		 961 vector++;
962
047e0030
AD		 963 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
964
0ba82994 965 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 966 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 967 q_vector->rx.ring->queue_index);
968 else if (q_vector->tx.ring)
047e0030 969 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 970 q_vector->tx.ring->queue_index);
971 else if (q_vector->rx.ring)
047e0030 972 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 973 q_vector->rx.ring->queue_index);
9d5c8243 974 else
047e0030
AD		 975 sprintf(q_vector->name, "%s-unused", netdev->name);
976
9d5c8243 977 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 978 igb_msix_ring, 0, q_vector->name,
979 q_vector);
9d5c8243 980 if (err)
52285b76 981 goto err_free;
9d5c8243
AK		 982 }
983
9d5c8243
AK		 984 igb_configure_msix(adapter);
985 return 0;
52285b76
SA		 986
987err_free:
988 /* free already assigned IRQs */
989 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
990
991 vector--;
992 for (i = 0; i < vector; i++) {
993 free_irq(adapter->msix_entries[free_vector++].vector,
994 adapter->q_vector[i]);
995 }
996err_out:
9d5c8243
AK		 997 return err;
998}
999
5536d210 1000/**
b980ac18
JK		 1001 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1002 * @adapter: board private structure to initialize
1003 * @v_idx: Index of vector to be freed
5536d210 1004 *
02ef6e1d 1005 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1006 **/
1007static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1008{
1009 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1010
02ef6e1d
CW		 1011 adapter->q_vector[v_idx] = NULL;
1012
1013 /* igb_get_stats64() might access the rings on this vector,
1014 * we must wait a grace period before freeing it.
1015 */
1016 kfree_rcu(q_vector, rcu);
1017}
1018
1019/**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
cb06d102
CP		 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
5536d210
AD		 1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
1041 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1042
5536d210
AD		 1043 netif_napi_del(&q_vector->napi);
1044
02ef6e1d
CW		 1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
cd14ef54 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1052 pci_disable_msix(adapter->pdev);
cd14ef54 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1054 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1058}
1059
047e0030 1060/**
b980ac18
JK		 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
047e0030 1063 *
b980ac18
JK		 1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
047e0030
AD		 1067 **/
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
5536d210
AD		 1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
047e0030 1074 adapter->num_q_vectors = 0;
5536d210 1075
02ef6e1d
CW		 1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
5536d210 1078 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1079 }
047e0030
AD		 1080}
1081
1082/**
b980ac18
JK		 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
047e0030 1085 *
b980ac18
JK		 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
047e0030
AD		 1088 */
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
047e0030
AD		 1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
9d5c8243
AK		 1094
1095/**
b980ac18
JK		 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
9d5c8243 1099 *
b980ac18
JK		 1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
9d5c8243 1102 **/
53c7d064 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1104{
1105 int err;
1106 int numvecs, i;
1107
53c7d064
SA		 1108 if (!msix)
1109 goto msi_only;
cd14ef54 1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1111
83b7180d 1112 /* Number of supported queues. */
a99955fc 1113 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1118
b980ac18 1119 /* start with one vector for every Rx queue */
047e0030
AD		 1120 numvecs = adapter->num_rx_queues;
1121
b980ac18 1122 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
047e0030
AD		 1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
9d5c8243
AK		 1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
479d02df
AG		 1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
0c2cc02e 1139 return;
9d5c8243
AK		 1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144msi_only:
b709323d 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1146#ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1157 wrfl();
2a3abf6d
AD		 1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
4fc82adf 1162 adapter->vfs_allocated_count = 0;
a99955fc 1163 adapter->rss_queues = 1;
4fc82adf 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1165 adapter->num_rx_queues = 1;
661086df 1166 adapter->num_tx_queues = 1;
047e0030 1167 adapter->num_q_vectors = 1;
9d5c8243 1168 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1169 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1170}
1171
5536d210
AD		 1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
047e0030 1179/**
b980ac18
JK		 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
047e0030 1188 *
b980ac18 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1190 **/
5536d210
AD		 1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
047e0030
AD		 1195{
1196 struct igb_q_vector *q_vector;
5536d210
AD		 1197 struct igb_ring *ring;
1198 int ring_count, size;
047e0030 1199
5536d210
AD		 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
02ef6e1d
CW		 1209 q_vector = adapter->q_vector[v_idx];
1210 if (!q_vector)
1211 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1212 if (!q_vector)
1213 return -ENOMEM;
1214
1215 /* initialize NAPI */
1216 netif_napi_add(adapter->netdev, &q_vector->napi,
1217 igb_poll, 64);
1218
1219 /* tie q_vector and adapter together */
1220 adapter->q_vector[v_idx] = q_vector;
1221 q_vector->adapter = adapter;
1222
1223 /* initialize work limits */
1224 q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226 /* initialize ITR configuration */
1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1228 q_vector->itr_val = IGB_START_ITR;
1229
1230 /* initialize pointer to rings */
1231 ring = q_vector->ring;
1232
4e227667
AD		 1233 /* intialize ITR */
1234 if (rxr_count) {
1235 /* rx or rx/tx vector */
1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237 q_vector->itr_val = adapter->rx_itr_setting;
1238 } else {
1239 /* tx only vector */
1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241 q_vector->itr_val = adapter->tx_itr_setting;
1242 }
1243
5536d210
AD		 1244 if (txr_count) {
1245 /* assign generic ring traits */
1246 ring->dev = &adapter->pdev->dev;
1247 ring->netdev = adapter->netdev;
1248
1249 /* configure backlink on ring */
1250 ring->q_vector = q_vector;
1251
1252 /* update q_vector Tx values */
1253 igb_add_ring(ring, &q_vector->tx);
1254
1255 /* For 82575, context index must be unique per ring. */
1256 if (adapter->hw.mac.type == e1000_82575)
1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259 /* apply Tx specific ring traits */
1260 ring->count = adapter->tx_ring_count;
1261 ring->queue_index = txr_idx;
1262
827da44c
JS		 1263 u64_stats_init(&ring->tx_syncp);
1264 u64_stats_init(&ring->tx_syncp2);
1265
5536d210
AD		 1266 /* assign ring to adapter */
1267 adapter->tx_ring[txr_idx] = ring;
1268
1269 /* push pointer to next ring */
1270 ring++;
047e0030 1271 }
81c2fc22 1272
5536d210
AD		 1273 if (rxr_count) {
1274 /* assign generic ring traits */
1275 ring->dev = &adapter->pdev->dev;
1276 ring->netdev = adapter->netdev;
047e0030 1277
5536d210
AD		 1278 /* configure backlink on ring */
1279 ring->q_vector = q_vector;
047e0030 1280
5536d210
AD		 1281 /* update q_vector Rx values */
1282 igb_add_ring(ring, &q_vector->rx);
047e0030 1283
5536d210
AD		 1284 /* set flag indicating ring supports SCTP checksum offload */
1285 if (adapter->hw.mac.type >= e1000_82576)
1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1287
ceb5f13b
CW		 1288 /*
1289 * On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1290 * have the tag byte-swapped.
b980ac18 1291 */
5536d210
AD		 1292 if (adapter->hw.mac.type >= e1000_i350)
1293 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1294
5536d210
AD		 1295 /* apply Rx specific ring traits */
1296 ring->count = adapter->rx_ring_count;
1297 ring->queue_index = rxr_idx;
1298
827da44c
JS		 1299 u64_stats_init(&ring->rx_syncp);
1300
5536d210
AD		 1301 /* assign ring to adapter */
1302 adapter->rx_ring[rxr_idx] = ring;
1303 }
1304
1305 return 0;
047e0030
AD		 1306}
1307
5536d210 1308
047e0030 1309/**
b980ac18
JK		 1310 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1311 * @adapter: board private structure to initialize
047e0030 1312 *
b980ac18
JK		 1313 * We allocate one q_vector per queue interrupt. If allocation fails we
1314 * return -ENOMEM.
047e0030 1315 **/
5536d210 1316static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1317{
5536d210
AD		 1318 int q_vectors = adapter->num_q_vectors;
1319 int rxr_remaining = adapter->num_rx_queues;
1320 int txr_remaining = adapter->num_tx_queues;
1321 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1322 int err;
047e0030 1323
5536d210
AD		 1324 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1325 for (; rxr_remaining; v_idx++) {
1326 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1327 0, 0, 1, rxr_idx);
047e0030 1328
5536d210
AD		 1329 if (err)
1330 goto err_out;
1331
1332 /* update counts and index */
1333 rxr_remaining--;
1334 rxr_idx++;
047e0030 1335 }
047e0030 1336 }
5536d210
AD		 1337
1338 for (; v_idx < q_vectors; v_idx++) {
1339 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1340 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1342 tqpv, txr_idx, rqpv, rxr_idx);
1343
1344 if (err)
1345 goto err_out;
1346
1347 /* update counts and index */
1348 rxr_remaining -= rqpv;
1349 txr_remaining -= tqpv;
1350 rxr_idx++;
1351 txr_idx++;
1352 }
1353
047e0030 1354 return 0;
5536d210
AD		 1355
1356err_out:
1357 adapter->num_tx_queues = 0;
1358 adapter->num_rx_queues = 0;
1359 adapter->num_q_vectors = 0;
1360
1361 while (v_idx--)
1362 igb_free_q_vector(adapter, v_idx);
1363
1364 return -ENOMEM;
047e0030
AD		 1365}
1366
1367/**
b980ac18
JK		 1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1369 * @adapter: board private structure to initialize
1370 * @msix: boolean value of MSIX capability
047e0030 1371 *
b980ac18 1372 * This function initializes the interrupts and allocates all of the queues.
047e0030 1373 **/
53c7d064 1374static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1375{
1376 struct pci_dev *pdev = adapter->pdev;
1377 int err;
1378
53c7d064 1379 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1380
1381 err = igb_alloc_q_vectors(adapter);
1382 if (err) {
1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1384 goto err_alloc_q_vectors;
1385 }
1386
5536d210 1387 igb_cache_ring_register(adapter);
047e0030
AD		 1388
1389 return 0;
5536d210 1390
047e0030
AD		 1391err_alloc_q_vectors:
1392 igb_reset_interrupt_capability(adapter);
1393 return err;
1394}
1395
9d5c8243 1396/**
b980ac18
JK		 1397 * igb_request_irq - initialize interrupts
1398 * @adapter: board private structure to initialize
9d5c8243 1399 *
b980ac18
JK		 1400 * Attempts to configure interrupts using the best available
1401 * capabilities of the hardware and kernel.
9d5c8243
AK		 1402 **/
1403static int igb_request_irq(struct igb_adapter *adapter)
1404{
1405 struct net_device *netdev = adapter->netdev;
047e0030 1406 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1407 int err = 0;
1408
cd14ef54 1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1410 err = igb_request_msix(adapter);
844290e5 1411 if (!err)
9d5c8243 1412 goto request_done;
9d5c8243 1413 /* fall back to MSI */
5536d210
AD		 1414 igb_free_all_tx_resources(adapter);
1415 igb_free_all_rx_resources(adapter);
53c7d064 1416
047e0030 1417 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1418 err = igb_init_interrupt_scheme(adapter, false);
1419 if (err)
047e0030 1420 goto request_done;
53c7d064 1421
047e0030
AD		 1422 igb_setup_all_tx_resources(adapter);
1423 igb_setup_all_rx_resources(adapter);
53c7d064 1424 igb_configure(adapter);
9d5c8243 1425 }
844290e5 1426
c74d588e
AD		 1427 igb_assign_vector(adapter->q_vector[0], 0);
1428
7dfc16fa 1429 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1430 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1431 netdev->name, adapter);
9d5c8243
AK		 1432 if (!err)
1433 goto request_done;
047e0030 1434
9d5c8243
AK		 1435 /* fall back to legacy interrupts */
1436 igb_reset_interrupt_capability(adapter);
7dfc16fa 1437 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1438 }
1439
c74d588e 1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1441 netdev->name, adapter);
9d5c8243 1442
6cb5e577 1443 if (err)
c74d588e 1444 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1445 err);
9d5c8243
AK		 1446
1447request_done:
1448 return err;
1449}
1450
1451static void igb_free_irq(struct igb_adapter *adapter)
1452{
cd14ef54 1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1454 int vector = 0, i;
1455
047e0030 1456 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1457
0d1ae7f4 1458 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1459 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1460 adapter->q_vector[i]);
047e0030
AD		 1461 } else {
1462 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1463 }
9d5c8243
AK		 1464}
1465
1466/**
b980ac18
JK		 1467 * igb_irq_disable - Mask off interrupt generation on the NIC
1468 * @adapter: board private structure
9d5c8243
AK		 1469 **/
1470static void igb_irq_disable(struct igb_adapter *adapter)
1471{
1472 struct e1000_hw *hw = &adapter->hw;
1473
b980ac18 1474 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1475 * mapped into these registers and so clearing the bits can cause
1476 * issues on the VF drivers so we only need to clear what we set
1477 */
cd14ef54 1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212
AD		 1479 u32 regval = rd32(E1000_EIAM);
1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1481 wr32(E1000_EIMC, adapter->eims_enable_mask);
1482 regval = rd32(E1000_EIAC);
1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1484 }
844290e5
PW		 1485
1486 wr32(E1000_IAM, 0);
9d5c8243
AK		 1487 wr32(E1000_IMC, ~0);
1488 wrfl();
cd14ef54 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859
ET		 1490 int i;
1491 for (i = 0; i < adapter->num_q_vectors; i++)
1492 synchronize_irq(adapter->msix_entries[i].vector);
1493 } else {
1494 synchronize_irq(adapter->pdev->irq);
1495 }
9d5c8243
AK		 1496}
1497
1498/**
b980ac18
JK		 1499 * igb_irq_enable - Enable default interrupt generation settings
1500 * @adapter: board private structure
9d5c8243
AK		 1501 **/
1502static void igb_irq_enable(struct igb_adapter *adapter)
1503{
1504 struct e1000_hw *hw = &adapter->hw;
1505
cd14ef54 1506 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1507 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212
AD		 1508 u32 regval = rd32(E1000_EIAC);
1509 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1510 regval = rd32(E1000_EIAM);
1511 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1512 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1513 if (adapter->vfs_allocated_count) {
4ae196df 1514 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1515 ims |= E1000_IMS_VMMB;
1516 }
1517 wr32(E1000_IMS, ims);
844290e5 1518 } else {
55cac248
AD		 1519 wr32(E1000_IMS, IMS_ENABLE_MASK |
1520 E1000_IMS_DRSTA);
1521 wr32(E1000_IAM, IMS_ENABLE_MASK |
1522 E1000_IMS_DRSTA);
844290e5 1523 }
9d5c8243
AK		 1524}
1525
1526static void igb_update_mng_vlan(struct igb_adapter *adapter)
1527{
51466239 1528 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1529 u16 vid = adapter->hw.mng_cookie.vlan_id;
1530 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1531
1532 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1533 /* add VID to filter table */
1534 igb_vfta_set(hw, vid, true);
1535 adapter->mng_vlan_id = vid;
1536 } else {
1537 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1538 }
1539
1540 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1541 (vid != old_vid) &&
b2cb09b1 1542 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1543 /* remove VID from filter table */
1544 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1545 }
1546}
1547
1548/**
b980ac18
JK		 1549 * igb_release_hw_control - release control of the h/w to f/w
1550 * @adapter: address of board private structure
9d5c8243 1551 *
b980ac18
JK		 1552 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1553 * For ASF and Pass Through versions of f/w this means that the
1554 * driver is no longer loaded.
9d5c8243
AK		 1555 **/
1556static void igb_release_hw_control(struct igb_adapter *adapter)
1557{
1558 struct e1000_hw *hw = &adapter->hw;
1559 u32 ctrl_ext;
1560
1561 /* Let firmware take over control of h/w */
1562 ctrl_ext = rd32(E1000_CTRL_EXT);
1563 wr32(E1000_CTRL_EXT,
1564 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1565}
1566
9d5c8243 1567/**
b980ac18
JK		 1568 * igb_get_hw_control - get control of the h/w from f/w
1569 * @adapter: address of board private structure
9d5c8243 1570 *
b980ac18
JK		 1571 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1572 * For ASF and Pass Through versions of f/w this means that
1573 * the driver is loaded.
9d5c8243
AK		 1574 **/
1575static void igb_get_hw_control(struct igb_adapter *adapter)
1576{
1577 struct e1000_hw *hw = &adapter->hw;
1578 u32 ctrl_ext;
1579
1580 /* Let firmware know the driver has taken over */
1581 ctrl_ext = rd32(E1000_CTRL_EXT);
1582 wr32(E1000_CTRL_EXT,
1583 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1584}
1585
9d5c8243 1586/**
b980ac18
JK		 1587 * igb_configure - configure the hardware for RX and TX
1588 * @adapter: private board structure
9d5c8243
AK		 1589 **/
1590static void igb_configure(struct igb_adapter *adapter)
1591{
1592 struct net_device *netdev = adapter->netdev;
1593 int i;
1594
1595 igb_get_hw_control(adapter);
ff41f8dc 1596 igb_set_rx_mode(netdev);
9d5c8243
AK		 1597
1598 igb_restore_vlan(adapter);
9d5c8243 1599
85b430b4 1600 igb_setup_tctl(adapter);
06cf2666 1601 igb_setup_mrqc(adapter);
9d5c8243 1602 igb_setup_rctl(adapter);
85b430b4
AD		 1603
1604 igb_configure_tx(adapter);
9d5c8243 1605 igb_configure_rx(adapter);
662d7205
AD		 1606
1607 igb_rx_fifo_flush_82575(&adapter->hw);
1608
c493ea45 1609 /* call igb_desc_unused which always leaves
9d5c8243 1610 * at least 1 descriptor unused to make sure
b980ac18
JK		 1611 * next_to_use != next_to_clean
1612 */
9d5c8243 1613 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1614 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1615 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1616 }
9d5c8243
AK		 1617}
1618
88a268c1 1619/**
b980ac18
JK		 1620 * igb_power_up_link - Power up the phy/serdes link
1621 * @adapter: address of board private structure
88a268c1
NN		 1622 **/
1623void igb_power_up_link(struct igb_adapter *adapter)
1624{
76886596
AA		 1625 igb_reset_phy(&adapter->hw);
1626
88a268c1
NN		 1627 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1628 igb_power_up_phy_copper(&adapter->hw);
1629 else
1630 igb_power_up_serdes_link_82575(&adapter->hw);
1631}
1632
1633/**
b980ac18
JK		 1634 * igb_power_down_link - Power down the phy/serdes link
1635 * @adapter: address of board private structure
88a268c1
NN		 1636 */
1637static void igb_power_down_link(struct igb_adapter *adapter)
1638{
1639 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1640 igb_power_down_phy_copper_82575(&adapter->hw);
1641 else
1642 igb_shutdown_serdes_link_82575(&adapter->hw);
1643}
9d5c8243 1644
56cec249
CW		 1645/**
1646 * Detect and switch function for Media Auto Sense
1647 * @adapter: address of the board private structure
1648 **/
1649static void igb_check_swap_media(struct igb_adapter *adapter)
1650{
1651 struct e1000_hw *hw = &adapter->hw;
1652 u32 ctrl_ext, connsw;
1653 bool swap_now = false;
1654
1655 ctrl_ext = rd32(E1000_CTRL_EXT);
1656 connsw = rd32(E1000_CONNSW);
1657
1658 /* need to live swap if current media is copper and we have fiber/serdes
1659 * to go to.
1660 */
1661
1662 if ((hw->phy.media_type == e1000_media_type_copper) &&
1663 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1664 swap_now = true;
1665 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1666 /* copper signal takes time to appear */
1667 if (adapter->copper_tries < 4) {
1668 adapter->copper_tries++;
1669 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1670 wr32(E1000_CONNSW, connsw);
1671 return;
1672 } else {
1673 adapter->copper_tries = 0;
1674 if ((connsw & E1000_CONNSW_PHYSD) &&
1675 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1676 swap_now = true;
1677 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1678 wr32(E1000_CONNSW, connsw);
1679 }
1680 }
1681 }
1682
1683 if (!swap_now)
1684 return;
1685
1686 switch (hw->phy.media_type) {
1687 case e1000_media_type_copper:
1688 netdev_info(adapter->netdev,
1689 "MAS: changing media to fiber/serdes\n");
1690 ctrl_ext |=
1691 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1692 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1693 adapter->copper_tries = 0;
1694 break;
1695 case e1000_media_type_internal_serdes:
1696 case e1000_media_type_fiber:
1697 netdev_info(adapter->netdev,
1698 "MAS: changing media to copper\n");
1699 ctrl_ext &=
1700 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1701 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1702 break;
1703 default:
1704 /* shouldn't get here during regular operation */
1705 netdev_err(adapter->netdev,
1706 "AMS: Invalid media type found, returning\n");
1707 break;
1708 }
1709 wr32(E1000_CTRL_EXT, ctrl_ext);
1710}
1711
9d5c8243 1712/**
b980ac18
JK		 1713 * igb_up - Open the interface and prepare it to handle traffic
1714 * @adapter: board private structure
9d5c8243 1715 **/
9d5c8243
AK		 1716int igb_up(struct igb_adapter *adapter)
1717{
1718 struct e1000_hw *hw = &adapter->hw;
1719 int i;
1720
1721 /* hardware has been reset, we need to reload some things */
1722 igb_configure(adapter);
1723
1724 clear_bit(__IGB_DOWN, &adapter->state);
1725
0d1ae7f4
AD		 1726 for (i = 0; i < adapter->num_q_vectors; i++)
1727 napi_enable(&(adapter->q_vector[i]->napi));
1728
cd14ef54 1729 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1730 igb_configure_msix(adapter);
feeb2721
AD		 1731 else
1732 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1733
1734 /* Clear any pending interrupts. */
1735 rd32(E1000_ICR);
1736 igb_irq_enable(adapter);
1737
d4960307
AD		 1738 /* notify VFs that reset has been completed */
1739 if (adapter->vfs_allocated_count) {
1740 u32 reg_data = rd32(E1000_CTRL_EXT);
1741 reg_data |= E1000_CTRL_EXT_PFRSTD;
1742 wr32(E1000_CTRL_EXT, reg_data);
1743 }
1744
4cb9be7a
JB		 1745 netif_tx_start_all_queues(adapter->netdev);
1746
25568a53
AD		 1747 /* start the watchdog. */
1748 hw->mac.get_link_status = 1;
1749 schedule_work(&adapter->watchdog_task);
1750
f4c01e96
CW		 1751 if ((adapter->flags & IGB_FLAG_EEE) &&
1752 (!hw->dev_spec._82575.eee_disable))
1753 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1754
9d5c8243
AK		 1755 return 0;
1756}
1757
1758void igb_down(struct igb_adapter *adapter)
1759{
9d5c8243 1760 struct net_device *netdev = adapter->netdev;
330a6d6a 1761 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1762 u32 tctl, rctl;
1763 int i;
1764
1765 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1766 * reschedule our watchdog timer
1767 */
9d5c8243
AK		 1768 set_bit(__IGB_DOWN, &adapter->state);
1769
1770 /* disable receives in the hardware */
1771 rctl = rd32(E1000_RCTL);
1772 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1773 /* flush and sleep below */
1774
fd2ea0a7 1775 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1776
1777 /* disable transmits in the hardware */
1778 tctl = rd32(E1000_TCTL);
1779 tctl &= ~E1000_TCTL_EN;
1780 wr32(E1000_TCTL, tctl);
1781 /* flush both disables and wait for them to finish */
1782 wrfl();
1783 msleep(10);
1784
41f149a2
CW		 1785 igb_irq_disable(adapter);
1786
aa9b8cc4
AA		 1787 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1788
41f149a2
CW		 1789 for (i = 0; i < adapter->num_q_vectors; i++) {
1790 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1791 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1792 }
9d5c8243 1793
9d5c8243
AK		 1794
1795 del_timer_sync(&adapter->watchdog_timer);
1796 del_timer_sync(&adapter->phy_info_timer);
1797
9d5c8243 1798 netif_carrier_off(netdev);
04fe6358
AD		 1799
1800 /* record the stats before reset*/
12dcd86b
ED		 1801 spin_lock(&adapter->stats64_lock);
1802 igb_update_stats(adapter, &adapter->stats64);
1803 spin_unlock(&adapter->stats64_lock);
04fe6358 1804
9d5c8243
AK		 1805 adapter->link_speed = 0;
1806 adapter->link_duplex = 0;
1807
3023682e
JK		 1808 if (!pci_channel_offline(adapter->pdev))
1809 igb_reset(adapter);
9d5c8243
AK		 1810 igb_clean_all_tx_rings(adapter);
1811 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1812#ifdef CONFIG_IGB_DCA
1813
1814 /* since we reset the hardware DCA settings were cleared */
1815 igb_setup_dca(adapter);
1816#endif
9d5c8243
AK		 1817}
1818
1819void igb_reinit_locked(struct igb_adapter *adapter)
1820{
1821 WARN_ON(in_interrupt());
1822 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1823 msleep(1);
1824 igb_down(adapter);
1825 igb_up(adapter);
1826 clear_bit(__IGB_RESETTING, &adapter->state);
1827}
1828
56cec249
CW		 1829/** igb_enable_mas - Media Autosense re-enable after swap
1830 *
1831 * @adapter: adapter struct
1832 **/
1833static s32 igb_enable_mas(struct igb_adapter *adapter)
1834{
1835 struct e1000_hw *hw = &adapter->hw;
1836 u32 connsw;
1837 s32 ret_val = 0;
1838
1839 connsw = rd32(E1000_CONNSW);
1840 if (!(hw->phy.media_type == e1000_media_type_copper))
1841 return ret_val;
1842
1843 /* configure for SerDes media detect */
1844 if (!(connsw & E1000_CONNSW_SERDESD)) {
1845 connsw |= E1000_CONNSW_ENRGSRC;
1846 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1847 wr32(E1000_CONNSW, connsw);
1848 wrfl();
1849 } else if (connsw & E1000_CONNSW_SERDESD) {
1850 /* already SerDes, no need to enable anything */
1851 return ret_val;
1852 } else {
1853 netdev_info(adapter->netdev,
1854 "MAS: Unable to configure feature, disabling..\n");
1855 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1856 }
1857 return ret_val;
1858}
1859
9d5c8243
AK		 1860void igb_reset(struct igb_adapter *adapter)
1861{
090b1795 1862 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1863 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1864 struct e1000_mac_info *mac = &hw->mac;
1865 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1866 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1867
1868 /* Repartition Pba for greater than 9k mtu
1869 * To take effect CTRL.RST is required.
1870 */
fa4dfae0 1871 switch (mac->type) {
d2ba2ed8 1872 case e1000_i350:
ceb5f13b 1873 case e1000_i354:
55cac248
AD		 1874 case e1000_82580:
1875 pba = rd32(E1000_RXPBS);
1876 pba = igb_rxpbs_adjust_82580(pba);
1877 break;
fa4dfae0 1878 case e1000_82576:
d249be54
AD		 1879 pba = rd32(E1000_RXPBS);
1880 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1881 break;
1882 case e1000_82575:
f96a8a0b
CW		 1883 case e1000_i210:
1884 case e1000_i211:
fa4dfae0
AD		 1885 default:
1886 pba = E1000_PBA_34K;
1887 break;
2d064c06 1888 }
9d5c8243 1889
2d064c06
AD		 1890 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1891 (mac->type < e1000_82576)) {
9d5c8243
AK		 1892 /* adjust PBA for jumbo frames */
1893 wr32(E1000_PBA, pba);
1894
1895 /* To maintain wire speed transmits, the Tx FIFO should be
1896 * large enough to accommodate two full transmit packets,
1897 * rounded up to the next 1KB and expressed in KB. Likewise,
1898 * the Rx FIFO should be large enough to accommodate at least
1899 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1900 * expressed in KB.
1901 */
9d5c8243
AK		 1902 pba = rd32(E1000_PBA);
1903 /* upper 16 bits has Tx packet buffer allocation size in KB */
1904 tx_space = pba >> 16;
1905 /* lower 16 bits has Rx packet buffer allocation size in KB */
1906 pba &= 0xffff;
b980ac18
JK		 1907 /* the Tx fifo also stores 16 bytes of information about the Tx
1908 * but don't include ethernet FCS because hardware appends it
1909 */
9d5c8243 1910 min_tx_space = (adapter->max_frame_size +
85e8d004 1911 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1912 ETH_FCS_LEN) * 2;
1913 min_tx_space = ALIGN(min_tx_space, 1024);
1914 min_tx_space >>= 10;
1915 /* software strips receive CRC, so leave room for it */
1916 min_rx_space = adapter->max_frame_size;
1917 min_rx_space = ALIGN(min_rx_space, 1024);
1918 min_rx_space >>= 10;
1919
1920 /* If current Tx allocation is less than the min Tx FIFO size,
1921 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1922 * allocation, take space away from current Rx allocation
1923 */
9d5c8243
AK		 1924 if (tx_space < min_tx_space &&
1925 ((min_tx_space - tx_space) < pba)) {
1926 pba = pba - (min_tx_space - tx_space);
1927
b980ac18
JK		 1928 /* if short on Rx space, Rx wins and must trump Tx
1929 * adjustment
1930 */
9d5c8243
AK		 1931 if (pba < min_rx_space)
1932 pba = min_rx_space;
1933 }
2d064c06 1934 wr32(E1000_PBA, pba);
9d5c8243 1935 }
9d5c8243
AK		 1936
1937 /* flow control settings */
1938 /* The high water mark must be low enough to fit one full frame
1939 * (or the size used for early receive) above it in the Rx FIFO.
1940 * Set it to the lower of:
1941 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1942 * - the full Rx FIFO size minus one full frame
1943 */
9d5c8243 1944 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1945 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1946
d48507fe 1947 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1948 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1949 fc->pause_time = 0xFFFF;
1950 fc->send_xon = 1;
0cce119a 1951 fc->current_mode = fc->requested_mode;
9d5c8243 1952
4ae196df
AD		 1953 /* disable receive for all VFs and wait one second */
1954 if (adapter->vfs_allocated_count) {
1955 int i;
1956 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1957 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1958
1959 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1960 igb_ping_all_vfs(adapter);
4ae196df
AD		 1961
1962 /* disable transmits and receives */
1963 wr32(E1000_VFRE, 0);
1964 wr32(E1000_VFTE, 0);
1965 }
1966
9d5c8243 1967 /* Allow time for pending master requests to run */
330a6d6a 1968 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1969 wr32(E1000_WUC, 0);
1970
56cec249
CW		 1971 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1972 /* need to resetup here after media swap */
1973 adapter->ei.get_invariants(hw);
1974 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1975 }
1976 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1977 if (igb_enable_mas(adapter))
1978 dev_err(&pdev->dev,
1979 "Error enabling Media Auto Sense\n");
1980 }
330a6d6a 1981 if (hw->mac.ops.init_hw(hw))
090b1795 1982 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1983
b980ac18 1984 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1985 * control is off when forcing speed.
1986 */
1987 if (!hw->mac.autoneg)
1988 igb_force_mac_fc(hw);
1989
b6e0c419 1990 igb_init_dmac(adapter, pba);
e428893b
CW		 1991#ifdef CONFIG_IGB_HWMON
1992 /* Re-initialize the thermal sensor on i350 devices. */
1993 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1994 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1995 /* If present, re-initialize the external thermal sensor
1996 * interface.
1997 */
1998 if (adapter->ets)
1999 mac->ops.init_thermal_sensor_thresh(hw);
2000 }
2001 }
2002#endif
b936136d 2003 /* Re-establish EEE setting */
f4c01e96
CW		 2004 if (hw->phy.media_type == e1000_media_type_copper) {
2005 switch (mac->type) {
2006 case e1000_i350:
2007 case e1000_i210:
2008 case e1000_i211:
2009 igb_set_eee_i350(hw);
2010 break;
2011 case e1000_i354:
2012 igb_set_eee_i354(hw);
2013 break;
2014 default:
2015 break;
2016 }
2017 }
88a268c1
NN		 2018 if (!netif_running(adapter->netdev))
2019 igb_power_down_link(adapter);
2020
9d5c8243
AK		 2021 igb_update_mng_vlan(adapter);
2022
2023 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2024 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2025
1f6e8178
MV		 2026 /* Re-enable PTP, where applicable. */
2027 igb_ptp_reset(adapter);
1f6e8178 2028
330a6d6a 2029 igb_get_phy_info(hw);
9d5c8243
AK		 2030}
2031
c8f44aff
MM		 2032static netdev_features_t igb_fix_features(struct net_device *netdev,
2033 netdev_features_t features)
b2cb09b1 2034{
b980ac18
JK		 2035 /* Since there is no support for separate Rx/Tx vlan accel
2036 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2037 */
f646968f
PM		 2038 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2039 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2040 else
f646968f 2041 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2042
2043 return features;
2044}
2045
c8f44aff
MM		 2046static int igb_set_features(struct net_device *netdev,
2047 netdev_features_t features)
ac52caa3 2048{
c8f44aff 2049 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2050 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2051
f646968f 2052 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2053 igb_vlan_mode(netdev, features);
2054
89eaefb6
BG		 2055 if (!(changed & NETIF_F_RXALL))
2056 return 0;
2057
2058 netdev->features = features;
2059
2060 if (netif_running(netdev))
2061 igb_reinit_locked(adapter);
2062 else
2063 igb_reset(adapter);
2064
ac52caa3
MM		 2065 return 0;
2066}
2067
2e5c6922 2068static const struct net_device_ops igb_netdev_ops = {
559e9c49 2069 .ndo_open = igb_open,
2e5c6922 2070 .ndo_stop = igb_close,
cd392f5c 2071 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2072 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2073 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2074 .ndo_set_mac_address = igb_set_mac,
2075 .ndo_change_mtu = igb_change_mtu,
2076 .ndo_do_ioctl = igb_ioctl,
2077 .ndo_tx_timeout = igb_tx_timeout,
2078 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2079 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2080 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2081 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2082 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2083 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 2084 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2085 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2086#ifdef CONFIG_NET_POLL_CONTROLLER
2087 .ndo_poll_controller = igb_netpoll,
2088#endif
b2cb09b1
JP		 2089 .ndo_fix_features = igb_fix_features,
2090 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2091};
2092
d67974f0
CW		 2093/**
2094 * igb_set_fw_version - Configure version string for ethtool
2095 * @adapter: adapter struct
d67974f0
CW		 2096 **/
2097void igb_set_fw_version(struct igb_adapter *adapter)
2098{
2099 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2100 struct e1000_fw_version fw;
2101
2102 igb_get_fw_version(hw, &fw);
2103
2104 switch (hw->mac.type) {
7dc98a62 2105 case e1000_i210:
0b1a6f2e 2106 case e1000_i211:
7dc98a62
CW		 2107 if (!(igb_get_flash_presence_i210(hw))) {
2108 snprintf(adapter->fw_version,
2109 sizeof(adapter->fw_version),
2110 "%2d.%2d-%d",
2111 fw.invm_major, fw.invm_minor,
2112 fw.invm_img_type);
2113 break;
2114 }
2115 /* fall through */
0b1a6f2e
CW		 2116 default:
2117 /* if option is rom valid, display its version too */
2118 if (fw.or_valid) {
2119 snprintf(adapter->fw_version,
2120 sizeof(adapter->fw_version),
2121 "%d.%d, 0x%08x, %d.%d.%d",
2122 fw.eep_major, fw.eep_minor, fw.etrack_id,
2123 fw.or_major, fw.or_build, fw.or_patch);
2124 /* no option rom */
7dc98a62 2125 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2126 snprintf(adapter->fw_version,
7dc98a62
CW		 2127 sizeof(adapter->fw_version),
2128 "%d.%d, 0x%08x",
2129 fw.eep_major, fw.eep_minor, fw.etrack_id);
2130 } else {
2131 snprintf(adapter->fw_version,
2132 sizeof(adapter->fw_version),
2133 "%d.%d.%d",
2134 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2135 }
2136 break;
d67974f0 2137 }
d67974f0
CW		 2138 return;
2139}
2140
56cec249
CW		 2141/**
2142 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2143 *
2144 * @adapter: adapter struct
2145 **/
2146static void igb_init_mas(struct igb_adapter *adapter)
2147{
2148 struct e1000_hw *hw = &adapter->hw;
2149 u16 eeprom_data;
2150
2151 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2152 switch (hw->bus.func) {
2153 case E1000_FUNC_0:
2154 if (eeprom_data & IGB_MAS_ENABLE_0) {
2155 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2156 netdev_info(adapter->netdev,
2157 "MAS: Enabling Media Autosense for port %d\n",
2158 hw->bus.func);
2159 }
2160 break;
2161 case E1000_FUNC_1:
2162 if (eeprom_data & IGB_MAS_ENABLE_1) {
2163 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2164 netdev_info(adapter->netdev,
2165 "MAS: Enabling Media Autosense for port %d\n",
2166 hw->bus.func);
2167 }
2168 break;
2169 case E1000_FUNC_2:
2170 if (eeprom_data & IGB_MAS_ENABLE_2) {
2171 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2172 netdev_info(adapter->netdev,
2173 "MAS: Enabling Media Autosense for port %d\n",
2174 hw->bus.func);
2175 }
2176 break;
2177 case E1000_FUNC_3:
2178 if (eeprom_data & IGB_MAS_ENABLE_3) {
2179 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2180 netdev_info(adapter->netdev,
2181 "MAS: Enabling Media Autosense for port %d\n",
2182 hw->bus.func);
2183 }
2184 break;
2185 default:
2186 /* Shouldn't get here */
2187 netdev_err(adapter->netdev,
2188 "MAS: Invalid port configuration, returning\n");
2189 break;
2190 }
2191}
2192
b980ac18
JK		 2193/**
2194 * igb_init_i2c - Init I2C interface
441fc6fd 2195 * @adapter: pointer to adapter structure
b980ac18 2196 **/
441fc6fd
CW		 2197static s32 igb_init_i2c(struct igb_adapter *adapter)
2198{
2199 s32 status = E1000_SUCCESS;
2200
2201 /* I2C interface supported on i350 devices */
2202 if (adapter->hw.mac.type != e1000_i350)
2203 return E1000_SUCCESS;
2204
2205 /* Initialize the i2c bus which is controlled by the registers.
2206 * This bus will use the i2c_algo_bit structue that implements
2207 * the protocol through toggling of the 4 bits in the register.
2208 */
2209 adapter->i2c_adap.owner = THIS_MODULE;
2210 adapter->i2c_algo = igb_i2c_algo;
2211 adapter->i2c_algo.data = adapter;
2212 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2213 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2214 strlcpy(adapter->i2c_adap.name, "igb BB",
2215 sizeof(adapter->i2c_adap.name));
2216 status = i2c_bit_add_bus(&adapter->i2c_adap);
2217 return status;
2218}
2219
9d5c8243 2220/**
b980ac18
JK		 2221 * igb_probe - Device Initialization Routine
2222 * @pdev: PCI device information struct
2223 * @ent: entry in igb_pci_tbl
9d5c8243 2224 *
b980ac18 2225 * Returns 0 on success, negative on failure
9d5c8243 2226 *
b980ac18
JK		 2227 * igb_probe initializes an adapter identified by a pci_dev structure.
2228 * The OS initialization, configuring of the adapter private structure,
2229 * and a hardware reset occur.
9d5c8243 2230 **/
1dd06ae8 2231static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2232{
2233 struct net_device *netdev;
2234 struct igb_adapter *adapter;
2235 struct e1000_hw *hw;
4337e993 2236 u16 eeprom_data = 0;
9835fd73 2237 s32 ret_val;
4337e993 2238 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2239 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2240 int err, pci_using_dac;
9835fd73 2241 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2242
bded64a7
AG		 2243 /* Catch broken hardware that put the wrong VF device ID in
2244 * the PCIe SR-IOV capability.
2245 */
2246 if (pdev->is_virtfn) {
2247 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2248 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2249 return -EINVAL;
2250 }
2251
aed5dec3 2252 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2253 if (err)
2254 return err;
2255
2256 pci_using_dac = 0;
dc4ff9bb 2257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2258 if (!err) {
dc4ff9bb 2259 pci_using_dac = 1;
9d5c8243 2260 } else {
dc4ff9bb 2261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2262 if (err) {
dc4ff9bb
RK		 2263 dev_err(&pdev->dev,
2264 "No usable DMA configuration, aborting\n");
2265 goto err_dma;
9d5c8243
AK		 2266 }
2267 }
2268
aed5dec3 2269 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2270 IORESOURCE_MEM),
2271 igb_driver_name);
9d5c8243
AK		 2272 if (err)
2273 goto err_pci_reg;
2274
19d5afd4 2275 pci_enable_pcie_error_reporting(pdev);
40a914fa 2276
9d5c8243 2277 pci_set_master(pdev);
c682fc23 2278 pci_save_state(pdev);
9d5c8243
AK		 2279
2280 err = -ENOMEM;
1bfaf07b 2281 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2282 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2283 if (!netdev)
2284 goto err_alloc_etherdev;
2285
2286 SET_NETDEV_DEV(netdev, &pdev->dev);
2287
2288 pci_set_drvdata(pdev, netdev);
2289 adapter = netdev_priv(netdev);
2290 adapter->netdev = netdev;
2291 adapter->pdev = pdev;
2292 hw = &adapter->hw;
2293 hw->back = adapter;
b3f4d599 2294 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2295
9d5c8243 2296 err = -EIO;
89dbefb2 2297 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2298 if (!hw->hw_addr)
9d5c8243
AK		 2299 goto err_ioremap;
2300
2e5c6922 2301 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2302 igb_set_ethtool_ops(netdev);
9d5c8243 2303 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2304
2305 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2306
89dbefb2
AS		 2307 netdev->mem_start = pci_resource_start(pdev, 0);
2308 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2309
9d5c8243
AK		 2310 /* PCI config space info */
2311 hw->vendor_id = pdev->vendor;
2312 hw->device_id = pdev->device;
2313 hw->revision_id = pdev->revision;
2314 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2315 hw->subsystem_device_id = pdev->subsystem_device;
2316
9d5c8243
AK		 2317 /* Copy the default MAC, PHY and NVM function pointers */
2318 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2319 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2320 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2321 /* Initialize skew-specific constants */
2322 err = ei->get_invariants(hw);
2323 if (err)
450c87c8 2324 goto err_sw_init;
9d5c8243 2325
450c87c8 2326 /* setup the private structure */
9d5c8243
AK		 2327 err = igb_sw_init(adapter);
2328 if (err)
2329 goto err_sw_init;
2330
2331 igb_get_bus_info_pcie(hw);
2332
2333 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2334
2335 /* Copper options */
2336 if (hw->phy.media_type == e1000_media_type_copper) {
2337 hw->phy.mdix = AUTO_ALL_MODES;
2338 hw->phy.disable_polarity_correction = false;
2339 hw->phy.ms_type = e1000_ms_hw_default;
2340 }
2341
2342 if (igb_check_reset_block(hw))
2343 dev_info(&pdev->dev,
2344 "PHY reset is blocked due to SOL/IDER session.\n");
2345
b980ac18 2346 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2347 * set by igb_sw_init so we should use an or instead of an
2348 * assignment.
2349 */
2350 netdev->features |= NETIF_F_SG |
2351 NETIF_F_IP_CSUM |
2352 NETIF_F_IPV6_CSUM |
2353 NETIF_F_TSO |
2354 NETIF_F_TSO6 |
2355 NETIF_F_RXHASH |
2356 NETIF_F_RXCSUM |
f646968f
PM		 2357 NETIF_F_HW_VLAN_CTAG_RX |
2358 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2359
2360 /* copy netdev features into list of user selectable features */
2361 netdev->hw_features |= netdev->features;
89eaefb6 2362 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2363
2364 /* set this bit last since it cannot be part of hw_features */
f646968f 2365 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2366
2367 netdev->vlan_features |= NETIF_F_TSO |
2368 NETIF_F_TSO6 |
2369 NETIF_F_IP_CSUM |
2370 NETIF_F_IPV6_CSUM |
2371 NETIF_F_SG;
48f29ffc 2372
6b8f0922
BG		 2373 netdev->priv_flags |= IFF_SUPP_NOFCS;
2374
7b872a55 2375 if (pci_using_dac) {
9d5c8243 2376 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2377 netdev->vlan_features |= NETIF_F_HIGHDMA;
2378 }
9d5c8243 2379
ac52caa3
MM		 2380 if (hw->mac.type >= e1000_82576) {
2381 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2382 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2383 }
b9473560 2384
01789349
JP		 2385 netdev->priv_flags |= IFF_UNICAST_FLT;
2386
330a6d6a 2387 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2388
2389 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2390 * known good starting state
2391 */
9d5c8243
AK		 2392 hw->mac.ops.reset_hw(hw);
2393
ef3a0092
CW		 2394 /* make sure the NVM is good , i211/i210 parts can have special NVM
2395 * that doesn't contain a checksum
f96a8a0b 2396 */
ef3a0092
CW		 2397 switch (hw->mac.type) {
2398 case e1000_i210:
2399 case e1000_i211:
2400 if (igb_get_flash_presence_i210(hw)) {
2401 if (hw->nvm.ops.validate(hw) < 0) {
2402 dev_err(&pdev->dev,
2403 "The NVM Checksum Is Not Valid\n");
2404 err = -EIO;
2405 goto err_eeprom;
2406 }
2407 }
2408 break;
2409 default:
f96a8a0b
CW		 2410 if (hw->nvm.ops.validate(hw) < 0) {
2411 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2412 err = -EIO;
2413 goto err_eeprom;
2414 }
ef3a0092 2415 break;
9d5c8243
AK		 2416 }
2417
2418 /* copy the MAC address out of the NVM */
2419 if (hw->mac.ops.read_mac_addr(hw))
2420 dev_err(&pdev->dev, "NVM Read Error\n");
2421
2422 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2423
aaeb6cdf 2424 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2425 dev_err(&pdev->dev, "Invalid MAC Address\n");
2426 err = -EIO;
2427 goto err_eeprom;
2428 }
2429
d67974f0
CW		 2430 /* get firmware version for ethtool -i */
2431 igb_set_fw_version(adapter);
2432
c061b18d 2433 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2434 (unsigned long) adapter);
c061b18d 2435 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2436 (unsigned long) adapter);
9d5c8243
AK		 2437
2438 INIT_WORK(&adapter->reset_task, igb_reset_task);
2439 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2440
450c87c8 2441 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2442 adapter->fc_autoneg = true;
2443 hw->mac.autoneg = true;
2444 hw->phy.autoneg_advertised = 0x2f;
2445
0cce119a
AD		 2446 hw->fc.requested_mode = e1000_fc_default;
2447 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2448
9d5c8243
AK		 2449 igb_validate_mdi_setting(hw);
2450
63d4a8f9 2451 /* By default, support wake on port A */
a2cf8b6c 2452 if (hw->bus.func == 0)
63d4a8f9
MV		 2453 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2454
2455 /* Check the NVM for wake support on non-port A ports */
2456 if (hw->mac.type >= e1000_82580)
55cac248 2457 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2458 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2459 &eeprom_data);
a2cf8b6c
AD		 2460 else if (hw->bus.func == 1)
2461 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2462
63d4a8f9
MV		 2463 if (eeprom_data & IGB_EEPROM_APME)
2464 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2465
2466 /* now that we have the eeprom settings, apply the special cases where
2467 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2468 * lan on a particular port
2469 */
9d5c8243
AK		 2470 switch (pdev->device) {
2471 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2473 break;
2474 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2475 case E1000_DEV_ID_82576_FIBER:
2476 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2477 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2478 * regardless of eeprom setting
2479 */
9d5c8243 2480 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2481 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2482 break;
c8ea5ea9 2483 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2484 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2485 /* if quad port adapter, disable WoL on all but port A */
2486 if (global_quad_port_a != 0)
63d4a8f9 2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2488 else
2489 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2490 /* Reset for multiple quad port adapters */
2491 if (++global_quad_port_a == 4)
2492 global_quad_port_a = 0;
2493 break;
63d4a8f9
MV		 2494 default:
2495 /* If the device can't wake, don't set software support */
2496 if (!device_can_wakeup(&adapter->pdev->dev))
2497 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2498 }
2499
2500 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2501 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2502 adapter->wol |= E1000_WUFC_MAG;
2503
2504 /* Some vendors want WoL disabled by default, but still supported */
2505 if ((hw->mac.type == e1000_i350) &&
2506 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2507 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2508 adapter->wol = 0;
2509 }
2510
2511 device_set_wakeup_enable(&adapter->pdev->dev,
2512 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2513
2514 /* reset the hardware with the new settings */
2515 igb_reset(adapter);
2516
441fc6fd
CW		 2517 /* Init the I2C interface */
2518 err = igb_init_i2c(adapter);
2519 if (err) {
2520 dev_err(&pdev->dev, "failed to init i2c interface\n");
2521 goto err_eeprom;
2522 }
2523
9d5c8243
AK		 2524 /* let the f/w know that the h/w is now under the control of the
2525 * driver. */
2526 igb_get_hw_control(adapter);
2527
9d5c8243
AK		 2528 strcpy(netdev->name, "eth%d");
2529 err = register_netdev(netdev);
2530 if (err)
2531 goto err_register;
2532
b168dfc5
JB		 2533 /* carrier off reporting is important to ethtool even BEFORE open */
2534 netif_carrier_off(netdev);
2535
421e02f0 2536#ifdef CONFIG_IGB_DCA
bbd98fe4 2537 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2538 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2539 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2540 igb_setup_dca(adapter);
2541 }
fe4506b6 2542
38c845c7 2543#endif
e428893b
CW		 2544#ifdef CONFIG_IGB_HWMON
2545 /* Initialize the thermal sensor on i350 devices. */
2546 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2547 u16 ets_word;
3c89f6d0 2548
b980ac18 2549 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2550 * external thermal sensor.
2551 */
2552 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2553 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2554 adapter->ets = true;
2555 else
2556 adapter->ets = false;
2557 if (igb_sysfs_init(adapter))
2558 dev_err(&pdev->dev,
2559 "failed to allocate sysfs resources\n");
2560 } else {
2561 adapter->ets = false;
2562 }
2563#endif
56cec249
CW		 2564 /* Check if Media Autosense is enabled */
2565 adapter->ei = *ei;
2566 if (hw->dev_spec._82575.mas_capable)
2567 igb_init_mas(adapter);
2568
673b8b70 2569 /* do hw tstamp init after resetting */
7ebae817 2570 igb_ptp_init(adapter);
673b8b70 2571
9d5c8243 2572 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2573 /* print bus type/speed/width info, not applicable to i354 */
2574 if (hw->mac.type != e1000_i354) {
2575 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2576 netdev->name,
2577 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2578 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2579 "unknown"),
2580 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2581 "Width x4" :
2582 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2583 "Width x2" :
2584 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2585 "Width x1" : "unknown"), netdev->dev_addr);
2586 }
9d5c8243 2587
53ea6c7e
TF		 2588 if ((hw->mac.type >= e1000_i210 ||
2589 igb_get_flash_presence_i210(hw))) {
2590 ret_val = igb_read_part_string(hw, part_str,
2591 E1000_PBANUM_LENGTH);
2592 } else {
2593 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2594 }
2595
9835fd73
CW		 2596 if (ret_val)
2597 strcpy(part_str, "Unknown");
2598 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2599 dev_info(&pdev->dev,
2600 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2601 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2602 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2603 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2604 if (hw->phy.media_type == e1000_media_type_copper) {
2605 switch (hw->mac.type) {
2606 case e1000_i350:
2607 case e1000_i210:
2608 case e1000_i211:
2609 /* Enable EEE for internal copper PHY devices */
2610 err = igb_set_eee_i350(hw);
2611 if ((!err) &&
2612 (!hw->dev_spec._82575.eee_disable)) {
2613 adapter->eee_advert =
2614 MDIO_EEE_100TX | MDIO_EEE_1000T;
2615 adapter->flags |= IGB_FLAG_EEE;
2616 }
2617 break;
2618 case e1000_i354:
ceb5f13b 2619 if ((rd32(E1000_CTRL_EXT) &
f4c01e96
CW		 2620 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2621 err = igb_set_eee_i354(hw);
2622 if ((!err) &&
2623 (!hw->dev_spec._82575.eee_disable)) {
2624 adapter->eee_advert =
2625 MDIO_EEE_100TX | MDIO_EEE_1000T;
2626 adapter->flags |= IGB_FLAG_EEE;
2627 }
2628 }
2629 break;
2630 default:
2631 break;
ceb5f13b 2632 }
09b068d4 2633 }
749ab2cd 2634 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2635 return 0;
2636
2637err_register:
2638 igb_release_hw_control(adapter);
441fc6fd 2639 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2640err_eeprom:
2641 if (!igb_check_reset_block(hw))
f5f4cf08 2642 igb_reset_phy(hw);
9d5c8243
AK		 2643
2644 if (hw->flash_address)
2645 iounmap(hw->flash_address);
9d5c8243 2646err_sw_init:
047e0030 2647 igb_clear_interrupt_scheme(adapter);
75009b3a 2648 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2649err_ioremap:
2650 free_netdev(netdev);
2651err_alloc_etherdev:
559e9c49 2652 pci_release_selected_regions(pdev,
b980ac18 2653 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2654err_pci_reg:
2655err_dma:
2656 pci_disable_device(pdev);
2657 return err;
2658}
2659
fa44f2f1 2660#ifdef CONFIG_PCI_IOV
781798a1 2661static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2662{
2663 struct net_device *netdev = pci_get_drvdata(pdev);
2664 struct igb_adapter *adapter = netdev_priv(netdev);
2665 struct e1000_hw *hw = &adapter->hw;
2666
2667 /* reclaim resources allocated to VFs */
2668 if (adapter->vf_data) {
2669 /* disable iov and allow time for transactions to clear */
b09186d2 2670 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2671 dev_warn(&pdev->dev,
2672 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2673 return -EPERM;
2674 } else {
2675 pci_disable_sriov(pdev);
2676 msleep(500);
2677 }
2678
2679 kfree(adapter->vf_data);
2680 adapter->vf_data = NULL;
2681 adapter->vfs_allocated_count = 0;
2682 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2683 wrfl();
2684 msleep(100);
2685 dev_info(&pdev->dev, "IOV Disabled\n");
2686
2687 /* Re-enable DMA Coalescing flag since IOV is turned off */
2688 adapter->flags |= IGB_FLAG_DMAC;
2689 }
2690
2691 return 0;
2692}
2693
2694static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2695{
2696 struct net_device *netdev = pci_get_drvdata(pdev);
2697 struct igb_adapter *adapter = netdev_priv(netdev);
2698 int old_vfs = pci_num_vf(pdev);
2699 int err = 0;
2700 int i;
2701
cd14ef54 2702 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2703 err = -EPERM;
2704 goto out;
2705 }
fa44f2f1
GR		 2706 if (!num_vfs)
2707 goto out;
fa44f2f1 2708
781798a1
SA		 2709 if (old_vfs) {
2710 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2711 old_vfs, max_vfs);
2712 adapter->vfs_allocated_count = old_vfs;
2713 } else
2714 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2715
2716 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2717 sizeof(struct vf_data_storage), GFP_KERNEL);
2718
2719 /* if allocation failed then we do not support SR-IOV */
2720 if (!adapter->vf_data) {
2721 adapter->vfs_allocated_count = 0;
2722 dev_err(&pdev->dev,
2723 "Unable to allocate memory for VF Data Storage\n");
2724 err = -ENOMEM;
2725 goto out;
2726 }
2727
781798a1
SA		 2728 /* only call pci_enable_sriov() if no VFs are allocated already */
2729 if (!old_vfs) {
2730 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2731 if (err)
2732 goto err_out;
2733 }
fa44f2f1
GR		 2734 dev_info(&pdev->dev, "%d VFs allocated\n",
2735 adapter->vfs_allocated_count);
2736 for (i = 0; i < adapter->vfs_allocated_count; i++)
2737 igb_vf_configure(adapter, i);
2738
2739 /* DMA Coalescing is not supported in IOV mode. */
2740 adapter->flags &= ~IGB_FLAG_DMAC;
2741 goto out;
2742
2743err_out:
2744 kfree(adapter->vf_data);
2745 adapter->vf_data = NULL;
2746 adapter->vfs_allocated_count = 0;
2747out:
2748 return err;
2749}
2750
2751#endif
b980ac18 2752/**
441fc6fd
CW		 2753 * igb_remove_i2c - Cleanup I2C interface
2754 * @adapter: pointer to adapter structure
b980ac18 2755 **/
441fc6fd
CW		 2756static void igb_remove_i2c(struct igb_adapter *adapter)
2757{
441fc6fd
CW		 2758 /* free the adapter bus structure */
2759 i2c_del_adapter(&adapter->i2c_adap);
2760}
2761
9d5c8243 2762/**
b980ac18
JK		 2763 * igb_remove - Device Removal Routine
2764 * @pdev: PCI device information struct
9d5c8243 2765 *
b980ac18
JK		 2766 * igb_remove is called by the PCI subsystem to alert the driver
2767 * that it should release a PCI device. The could be caused by a
2768 * Hot-Plug event, or because the driver is going to be removed from
2769 * memory.
9d5c8243 2770 **/
9f9a12f8 2771static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2772{
2773 struct net_device *netdev = pci_get_drvdata(pdev);
2774 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2775 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2776
749ab2cd 2777 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2778#ifdef CONFIG_IGB_HWMON
2779 igb_sysfs_exit(adapter);
2780#endif
441fc6fd 2781 igb_remove_i2c(adapter);
a79f4f88 2782 igb_ptp_stop(adapter);
b980ac18 2783 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2784 * disable watchdog from being rescheduled.
2785 */
9d5c8243
AK		 2786 set_bit(__IGB_DOWN, &adapter->state);
2787 del_timer_sync(&adapter->watchdog_timer);
2788 del_timer_sync(&adapter->phy_info_timer);
2789
760141a5
TH		 2790 cancel_work_sync(&adapter->reset_task);
2791 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2792
421e02f0 2793#ifdef CONFIG_IGB_DCA
7dfc16fa 2794 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2795 dev_info(&pdev->dev, "DCA disabled\n");
2796 dca_remove_requester(&pdev->dev);
7dfc16fa 2797 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2798 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2799 }
2800#endif
2801
9d5c8243 2802 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2803 * would have already happened in close and is redundant.
2804 */
9d5c8243
AK		 2805 igb_release_hw_control(adapter);
2806
2807 unregister_netdev(netdev);
2808
047e0030 2809 igb_clear_interrupt_scheme(adapter);
9d5c8243 2810
37680117 2811#ifdef CONFIG_PCI_IOV
fa44f2f1 2812 igb_disable_sriov(pdev);
37680117 2813#endif
559e9c49 2814
75009b3a 2815 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2816 if (hw->flash_address)
2817 iounmap(hw->flash_address);
559e9c49 2818 pci_release_selected_regions(pdev,
b980ac18 2819 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2820
1128c756 2821 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2822 free_netdev(netdev);
2823
19d5afd4 2824 pci_disable_pcie_error_reporting(pdev);
40a914fa 2825
9d5c8243
AK		 2826 pci_disable_device(pdev);
2827}
2828
a6b623e0 2829/**
b980ac18
JK		 2830 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2831 * @adapter: board private structure to initialize
a6b623e0 2832 *
b980ac18
JK		 2833 * This function initializes the vf specific data storage and then attempts to
2834 * allocate the VFs. The reason for ordering it this way is because it is much
2835 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2836 * the memory for the VFs.
a6b623e0 2837 **/
9f9a12f8 2838static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2839{
2840#ifdef CONFIG_PCI_IOV
2841 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2842 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2843
f96a8a0b
CW		 2844 /* Virtualization features not supported on i210 family. */
2845 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2846 return;
2847
fa44f2f1 2848 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2849 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2850
a6b623e0
AD		 2851#endif /* CONFIG_PCI_IOV */
2852}
2853
fa44f2f1 2854static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2855{
2856 struct e1000_hw *hw = &adapter->hw;
374a542d 2857 u32 max_rss_queues;
9d5c8243 2858
374a542d 2859 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2860 switch (hw->mac.type) {
374a542d
MV		 2861 case e1000_i211:
2862 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2863 break;
2864 case e1000_82575:
f96a8a0b 2865 case e1000_i210:
374a542d
MV		 2866 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2867 break;
2868 case e1000_i350:
2869 /* I350 cannot do RSS and SR-IOV at the same time */
2870 if (!!adapter->vfs_allocated_count) {
2871 max_rss_queues = 1;
2872 break;
2873 }
2874 /* fall through */
2875 case e1000_82576:
2876 if (!!adapter->vfs_allocated_count) {
2877 max_rss_queues = 2;
2878 break;
2879 }
2880 /* fall through */
2881 case e1000_82580:
ceb5f13b 2882 case e1000_i354:
374a542d
MV		 2883 default:
2884 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2885 break;
374a542d
MV		 2886 }
2887
2888 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2889
2890 /* Determine if we need to pair queues. */
2891 switch (hw->mac.type) {
2892 case e1000_82575:
f96a8a0b 2893 case e1000_i211:
374a542d 2894 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2895 break;
374a542d 2896 case e1000_82576:
b980ac18 2897 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2898 * should pair the queues in order to conserve interrupts due
2899 * to limited supply.
2900 */
2901 if ((adapter->rss_queues > 1) &&
2902 (adapter->vfs_allocated_count > 6))
2903 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2904 /* fall through */
2905 case e1000_82580:
2906 case e1000_i350:
ceb5f13b 2907 case e1000_i354:
374a542d 2908 case e1000_i210:
f96a8a0b 2909 default:
b980ac18 2910 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2911 * order to conserve interrupts due to limited supply.
2912 */
2913 if (adapter->rss_queues > (max_rss_queues / 2))
2914 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2915 break;
2916 }
fa44f2f1
GR		 2917}
2918
2919/**
b980ac18
JK		 2920 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2921 * @adapter: board private structure to initialize
fa44f2f1 2922 *
b980ac18
JK		 2923 * igb_sw_init initializes the Adapter private data structure.
2924 * Fields are initialized based on PCI device information and
2925 * OS network device settings (MTU size).
fa44f2f1
GR		 2926 **/
2927static int igb_sw_init(struct igb_adapter *adapter)
2928{
2929 struct e1000_hw *hw = &adapter->hw;
2930 struct net_device *netdev = adapter->netdev;
2931 struct pci_dev *pdev = adapter->pdev;
2932
2933 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2934
2935 /* set default ring sizes */
2936 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2937 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2938
2939 /* set default ITR values */
2940 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2941 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2942
2943 /* set default work limits */
2944 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2945
2946 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2947 VLAN_HLEN;
2948 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2949
2950 spin_lock_init(&adapter->stats64_lock);
2951#ifdef CONFIG_PCI_IOV
2952 switch (hw->mac.type) {
2953 case e1000_82576:
2954 case e1000_i350:
2955 if (max_vfs > 7) {
2956 dev_warn(&pdev->dev,
2957 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2958 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2959 } else
2960 adapter->vfs_allocated_count = max_vfs;
2961 if (adapter->vfs_allocated_count)
2962 dev_warn(&pdev->dev,
2963 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2964 break;
2965 default:
2966 break;
2967 }
2968#endif /* CONFIG_PCI_IOV */
2969
2970 igb_init_queue_configuration(adapter);
a99955fc 2971
1128c756 2972 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2973 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2974 GFP_ATOMIC);
1128c756 2975
a6b623e0 2976 /* This call may decrease the number of queues */
53c7d064 2977 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2978 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2979 return -ENOMEM;
2980 }
2981
a6b623e0
AD		 2982 igb_probe_vfs(adapter);
2983
9d5c8243
AK		 2984 /* Explicitly disable IRQ since the NIC can be in any state. */
2985 igb_irq_disable(adapter);
2986
f96a8a0b 2987 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2988 adapter->flags &= ~IGB_FLAG_DMAC;
2989
9d5c8243
AK		 2990 set_bit(__IGB_DOWN, &adapter->state);
2991 return 0;
2992}
2993
2994/**
b980ac18
JK		 2995 * igb_open - Called when a network interface is made active
2996 * @netdev: network interface device structure
9d5c8243 2997 *
b980ac18 2998 * Returns 0 on success, negative value on failure
9d5c8243 2999 *
b980ac18
JK		 3000 * The open entry point is called when a network interface is made
3001 * active by the system (IFF_UP). At this point all resources needed
3002 * for transmit and receive operations are allocated, the interrupt
3003 * handler is registered with the OS, the watchdog timer is started,
3004 * and the stack is notified that the interface is ready.
9d5c8243 3005 **/
749ab2cd 3006static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3007{
3008 struct igb_adapter *adapter = netdev_priv(netdev);
3009 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3010 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3011 int err;
3012 int i;
3013
3014 /* disallow open during test */
749ab2cd
YZ		 3015 if (test_bit(__IGB_TESTING, &adapter->state)) {
3016 WARN_ON(resuming);
9d5c8243 3017 return -EBUSY;
749ab2cd
YZ		 3018 }
3019
3020 if (!resuming)
3021 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3022
b168dfc5
JB		 3023 netif_carrier_off(netdev);
3024
9d5c8243
AK		 3025 /* allocate transmit descriptors */
3026 err = igb_setup_all_tx_resources(adapter);
3027 if (err)
3028 goto err_setup_tx;
3029
3030 /* allocate receive descriptors */
3031 err = igb_setup_all_rx_resources(adapter);
3032 if (err)
3033 goto err_setup_rx;
3034
88a268c1 3035 igb_power_up_link(adapter);
9d5c8243 3036
9d5c8243
AK		 3037 /* before we allocate an interrupt, we must be ready to handle it.
3038 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3039 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3040 * clean_rx handler before we do so.
3041 */
9d5c8243
AK		 3042 igb_configure(adapter);
3043
3044 err = igb_request_irq(adapter);
3045 if (err)
3046 goto err_req_irq;
3047
0c2cc02e
AD		 3048 /* Notify the stack of the actual queue counts. */
3049 err = netif_set_real_num_tx_queues(adapter->netdev,
3050 adapter->num_tx_queues);
3051 if (err)
3052 goto err_set_queues;
3053
3054 err = netif_set_real_num_rx_queues(adapter->netdev,
3055 adapter->num_rx_queues);
3056 if (err)
3057 goto err_set_queues;
3058
9d5c8243
AK		 3059 /* From here on the code is the same as igb_up() */
3060 clear_bit(__IGB_DOWN, &adapter->state);
3061
0d1ae7f4
AD		 3062 for (i = 0; i < adapter->num_q_vectors; i++)
3063 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3064
3065 /* Clear any pending interrupts. */
3066 rd32(E1000_ICR);
844290e5
PW		 3067
3068 igb_irq_enable(adapter);
3069
d4960307
AD		 3070 /* notify VFs that reset has been completed */
3071 if (adapter->vfs_allocated_count) {
3072 u32 reg_data = rd32(E1000_CTRL_EXT);
3073 reg_data |= E1000_CTRL_EXT_PFRSTD;
3074 wr32(E1000_CTRL_EXT, reg_data);
3075 }
3076
d55b53ff
JK		 3077 netif_tx_start_all_queues(netdev);
3078
749ab2cd
YZ		 3079 if (!resuming)
3080 pm_runtime_put(&pdev->dev);
3081
25568a53
AD		 3082 /* start the watchdog. */
3083 hw->mac.get_link_status = 1;
3084 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3085
3086 return 0;
3087
0c2cc02e
AD		 3088err_set_queues:
3089 igb_free_irq(adapter);
9d5c8243
AK		 3090err_req_irq:
3091 igb_release_hw_control(adapter);
88a268c1 3092 igb_power_down_link(adapter);
9d5c8243
AK		 3093 igb_free_all_rx_resources(adapter);
3094err_setup_rx:
3095 igb_free_all_tx_resources(adapter);
3096err_setup_tx:
3097 igb_reset(adapter);
749ab2cd
YZ		 3098 if (!resuming)
3099 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3100
3101 return err;
3102}
3103
749ab2cd
YZ		 3104static int igb_open(struct net_device *netdev)
3105{
3106 return __igb_open(netdev, false);
3107}
3108
9d5c8243 3109/**
b980ac18
JK		 3110 * igb_close - Disables a network interface
3111 * @netdev: network interface device structure
9d5c8243 3112 *
b980ac18 3113 * Returns 0, this is not allowed to fail
9d5c8243 3114 *
b980ac18
JK		 3115 * The close entry point is called when an interface is de-activated
3116 * by the OS. The hardware is still under the driver's control, but
3117 * needs to be disabled. A global MAC reset is issued to stop the
3118 * hardware, and all transmit and receive resources are freed.
9d5c8243 3119 **/
749ab2cd 3120static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3121{
3122 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3123 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3124
3125 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3126
749ab2cd
YZ		 3127 if (!suspending)
3128 pm_runtime_get_sync(&pdev->dev);
3129
3130 igb_down(adapter);
9d5c8243
AK		 3131 igb_free_irq(adapter);
3132
3133 igb_free_all_tx_resources(adapter);
3134 igb_free_all_rx_resources(adapter);
3135
749ab2cd
YZ		 3136 if (!suspending)
3137 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3138 return 0;
3139}
3140
749ab2cd
YZ		 3141static int igb_close(struct net_device *netdev)
3142{
3143 return __igb_close(netdev, false);
3144}
3145
9d5c8243 3146/**
b980ac18
JK		 3147 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3148 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3149 *
b980ac18 3150 * Return 0 on success, negative on failure
9d5c8243 3151 **/
80785298 3152int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3153{
59d71989 3154 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3155 int size;
3156
06034649 3157 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3158
3159 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3160 if (!tx_ring->tx_buffer_info)
9d5c8243 3161 goto err;
9d5c8243
AK		 3162
3163 /* round up to nearest 4K */
85e8d004 3164 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3165 tx_ring->size = ALIGN(tx_ring->size, 4096);
3166
5536d210
AD		 3167 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3168 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3169 if (!tx_ring->desc)
3170 goto err;
3171
9d5c8243
AK		 3172 tx_ring->next_to_use = 0;
3173 tx_ring->next_to_clean = 0;
81c2fc22 3174
9d5c8243
AK		 3175 return 0;
3176
3177err:
06034649 3178 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3179 tx_ring->tx_buffer_info = NULL;
3180 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3181 return -ENOMEM;
3182}
3183
3184/**
b980ac18
JK		 3185 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3186 * (Descriptors) for all queues
3187 * @adapter: board private structure
9d5c8243 3188 *
b980ac18 3189 * Return 0 on success, negative on failure
9d5c8243
AK		 3190 **/
3191static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3192{
439705e1 3193 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3194 int i, err = 0;
3195
3196 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3197 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3198 if (err) {
439705e1 3199 dev_err(&pdev->dev,
9d5c8243
AK		 3200 "Allocation for Tx Queue %u failed\n", i);
3201 for (i--; i >= 0; i--)
3025a446 3202 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3203 break;
3204 }
3205 }
3206
3207 return err;
3208}
3209
3210/**
b980ac18
JK		 3211 * igb_setup_tctl - configure the transmit control registers
3212 * @adapter: Board private structure
9d5c8243 3213 **/
d7ee5b3a 3214void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3215{
9d5c8243
AK		 3216 struct e1000_hw *hw = &adapter->hw;
3217 u32 tctl;
9d5c8243 3218
85b430b4
AD		 3219 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3220 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3221
3222 /* Program the Transmit Control Register */
9d5c8243
AK		 3223 tctl = rd32(E1000_TCTL);
3224 tctl &= ~E1000_TCTL_CT;
3225 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3226 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3227
3228 igb_config_collision_dist(hw);
3229
9d5c8243
AK		 3230 /* Enable transmits */
3231 tctl |= E1000_TCTL_EN;
3232
3233 wr32(E1000_TCTL, tctl);
3234}
3235
85b430b4 3236/**
b980ac18
JK		 3237 * igb_configure_tx_ring - Configure transmit ring after Reset
3238 * @adapter: board private structure
3239 * @ring: tx ring to configure
85b430b4 3240 *
b980ac18 3241 * Configure a transmit ring after a reset.
85b430b4 3242 **/
d7ee5b3a
AD		 3243void igb_configure_tx_ring(struct igb_adapter *adapter,
3244 struct igb_ring *ring)
85b430b4
AD		 3245{
3246 struct e1000_hw *hw = &adapter->hw;
a74420e0 3247 u32 txdctl = 0;
85b430b4
AD		 3248 u64 tdba = ring->dma;
3249 int reg_idx = ring->reg_idx;
3250
3251 /* disable the queue */
a74420e0 3252 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3253 wrfl();
3254 mdelay(10);
3255
3256 wr32(E1000_TDLEN(reg_idx),
b980ac18 3257 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3258 wr32(E1000_TDBAL(reg_idx),
b980ac18 3259 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3260 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3261
fce99e34 3262 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3263 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3264 writel(0, ring->tail);
85b430b4
AD		 3265
3266 txdctl |= IGB_TX_PTHRESH;
3267 txdctl |= IGB_TX_HTHRESH << 8;
3268 txdctl |= IGB_TX_WTHRESH << 16;
3269
3270 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3271 wr32(E1000_TXDCTL(reg_idx), txdctl);
3272}
3273
3274/**
b980ac18
JK		 3275 * igb_configure_tx - Configure transmit Unit after Reset
3276 * @adapter: board private structure
85b430b4 3277 *
b980ac18 3278 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3279 **/
3280static void igb_configure_tx(struct igb_adapter *adapter)
3281{
3282 int i;
3283
3284 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3285 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3286}
3287
9d5c8243 3288/**
b980ac18
JK		 3289 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3290 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3291 *
b980ac18 3292 * Returns 0 on success, negative on failure
9d5c8243 3293 **/
80785298 3294int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3295{
59d71989 3296 struct device *dev = rx_ring->dev;
f33005a6 3297 int size;
9d5c8243 3298
06034649 3299 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3300
3301 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3302 if (!rx_ring->rx_buffer_info)
9d5c8243 3303 goto err;
9d5c8243 3304
9d5c8243 3305 /* Round up to nearest 4K */
f33005a6 3306 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3307 rx_ring->size = ALIGN(rx_ring->size, 4096);
3308
5536d210
AD		 3309 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3310 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3311 if (!rx_ring->desc)
3312 goto err;
3313
cbc8e55f 3314 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3315 rx_ring->next_to_clean = 0;
3316 rx_ring->next_to_use = 0;
9d5c8243 3317
9d5c8243
AK		 3318 return 0;
3319
3320err:
06034649
AD		 3321 vfree(rx_ring->rx_buffer_info);
3322 rx_ring->rx_buffer_info = NULL;
f33005a6 3323 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3324 return -ENOMEM;
3325}
3326
3327/**
b980ac18
JK		 3328 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3329 * (Descriptors) for all queues
3330 * @adapter: board private structure
9d5c8243 3331 *
b980ac18 3332 * Return 0 on success, negative on failure
9d5c8243
AK		 3333 **/
3334static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3335{
439705e1 3336 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3337 int i, err = 0;
3338
3339 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3340 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3341 if (err) {
439705e1 3342 dev_err(&pdev->dev,
9d5c8243
AK		 3343 "Allocation for Rx Queue %u failed\n", i);
3344 for (i--; i >= 0; i--)
3025a446 3345 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3346 break;
3347 }
3348 }
3349
3350 return err;
3351}
3352
06cf2666 3353/**
b980ac18
JK		 3354 * igb_setup_mrqc - configure the multiple receive queue control registers
3355 * @adapter: Board private structure
06cf2666
AD		 3356 **/
3357static void igb_setup_mrqc(struct igb_adapter *adapter)
3358{
3359 struct e1000_hw *hw = &adapter->hw;
3360 u32 mrqc, rxcsum;
ed12cc9a 3361 u32 j, num_rx_queues;
a57fe23e
AD		 3362 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3363 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3364 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3365 0xFA01ACBE };
06cf2666
AD		 3366
3367 /* Fill out hash function seeds */
a57fe23e
AD		 3368 for (j = 0; j < 10; j++)
3369 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3370
a99955fc 3371 num_rx_queues = adapter->rss_queues;
06cf2666 3372
797fd4be 3373 switch (hw->mac.type) {
797fd4be
AD		 3374 case e1000_82576:
3375 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3376 if (adapter->vfs_allocated_count)
06cf2666 3377 num_rx_queues = 2;
797fd4be
AD		 3378 break;
3379 default:
3380 break;
06cf2666
AD		 3381 }
3382
ed12cc9a
LMV		 3383 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3384 for (j = 0; j < IGB_RETA_SIZE; j++)
3385 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3386 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3387 }
ed12cc9a 3388 igb_write_rss_indir_tbl(adapter);
06cf2666 3389
b980ac18 3390 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3391 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3392 * offloads as they are enabled by default
3393 */
3394 rxcsum = rd32(E1000_RXCSUM);
3395 rxcsum |= E1000_RXCSUM_PCSD;
3396
3397 if (adapter->hw.mac.type >= e1000_82576)
3398 /* Enable Receive Checksum Offload for SCTP */
3399 rxcsum |= E1000_RXCSUM_CRCOFL;
3400
3401 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3402 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3403
039454a8
AA		 3404 /* Generate RSS hash based on packet types, TCP/UDP
3405 * port numbers and/or IPv4/v6 src and dst addresses
3406 */
f96a8a0b
CW		 3407 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3408 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3409 E1000_MRQC_RSS_FIELD_IPV6 |
3410 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3411 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3412
039454a8
AA		 3413 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3414 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3415 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3416 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3417
06cf2666
AD		 3418 /* If VMDq is enabled then we set the appropriate mode for that, else
3419 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3420 * if we are only using one queue
3421 */
06cf2666
AD		 3422 if (adapter->vfs_allocated_count) {
3423 if (hw->mac.type > e1000_82575) {
3424 /* Set the default pool for the PF's first queue */
3425 u32 vtctl = rd32(E1000_VT_CTL);
3426 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3427 E1000_VT_CTL_DISABLE_DEF_POOL);
3428 vtctl |= adapter->vfs_allocated_count <<
3429 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3430 wr32(E1000_VT_CTL, vtctl);
3431 }
a99955fc 3432 if (adapter->rss_queues > 1)
f96a8a0b 3433 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3434 else
f96a8a0b 3435 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3436 } else {
f96a8a0b
CW		 3437 if (hw->mac.type != e1000_i211)
3438 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3439 }
3440 igb_vmm_control(adapter);
3441
06cf2666
AD		 3442 wr32(E1000_MRQC, mrqc);
3443}
3444
9d5c8243 3445/**
b980ac18
JK		 3446 * igb_setup_rctl - configure the receive control registers
3447 * @adapter: Board private structure
9d5c8243 3448 **/
d7ee5b3a 3449void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3450{
3451 struct e1000_hw *hw = &adapter->hw;
3452 u32 rctl;
9d5c8243
AK		 3453
3454 rctl = rd32(E1000_RCTL);
3455
3456 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3457 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3458
69d728ba 3459 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3460 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3461
b980ac18 3462 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3463 * redirection as it did with e1000. Newer features require
3464 * that the HW strips the CRC.
73cd78f1 3465 */
87cb7e8c 3466 rctl |= E1000_RCTL_SECRC;
9d5c8243 3467
559e9c49 3468 /* disable store bad packets and clear size bits. */
ec54d7d6 3469 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3470
6ec43fe6
AD		 3471 /* enable LPE to prevent packets larger than max_frame_size */
3472 rctl |= E1000_RCTL_LPE;
9d5c8243 3473
952f72a8
AD		 3474 /* disable queue 0 to prevent tail write w/o re-config */
3475 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3476
e1739522
AD		 3477 /* Attention!!! For SR-IOV PF driver operations you must enable
3478 * queue drop for all VF and PF queues to prevent head of line blocking
3479 * if an un-trusted VF does not provide descriptors to hardware.
3480 */
3481 if (adapter->vfs_allocated_count) {
e1739522
AD		 3482 /* set all queue drop enable bits */
3483 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3484 }
3485
89eaefb6
BG		 3486 /* This is useful for sniffing bad packets. */
3487 if (adapter->netdev->features & NETIF_F_RXALL) {
3488 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3489 * in e1000e_set_rx_mode
3490 */
89eaefb6
BG		 3491 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3492 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3493 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3494
3495 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3496 E1000_RCTL_DPF | /* Allow filtered pause */
3497 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3498 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3499 * and that breaks VLANs.
3500 */
3501 }
3502
9d5c8243
AK		 3503 wr32(E1000_RCTL, rctl);
3504}
3505
7d5753f0
AD		 3506static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3507 int vfn)
3508{
3509 struct e1000_hw *hw = &adapter->hw;
3510 u32 vmolr;
3511
3512 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3513 * increase the size to support vlan tags
3514 */
7d5753f0
AD		 3515 if (vfn < adapter->vfs_allocated_count &&
3516 adapter->vf_data[vfn].vlans_enabled)
3517 size += VLAN_TAG_SIZE;
3518
3519 vmolr = rd32(E1000_VMOLR(vfn));
3520 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3521 vmolr |= size | E1000_VMOLR_LPE;
3522 wr32(E1000_VMOLR(vfn), vmolr);
3523
3524 return 0;
3525}
3526
e1739522 3527/**
b980ac18
JK		 3528 * igb_rlpml_set - set maximum receive packet size
3529 * @adapter: board private structure
e1739522 3530 *
b980ac18 3531 * Configure maximum receivable packet size.
e1739522
AD		 3532 **/
3533static void igb_rlpml_set(struct igb_adapter *adapter)
3534{
153285f9 3535 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3536 struct e1000_hw *hw = &adapter->hw;
3537 u16 pf_id = adapter->vfs_allocated_count;
3538
e1739522
AD		 3539 if (pf_id) {
3540 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3541 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3542 * to our max jumbo frame size, in case we need to enable
3543 * jumbo frames on one of the rings later.
3544 * This will not pass over-length frames into the default
3545 * queue because it's gated by the VMOLR.RLPML.
3546 */
7d5753f0 3547 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3548 }
3549
3550 wr32(E1000_RLPML, max_frame_size);
3551}
3552
8151d294
WM		 3553static inline void igb_set_vmolr(struct igb_adapter *adapter,
3554 int vfn, bool aupe)
7d5753f0
AD		 3555{
3556 struct e1000_hw *hw = &adapter->hw;
3557 u32 vmolr;
3558
b980ac18 3559 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3560 * we should exit and do nothing
3561 */
3562 if (hw->mac.type < e1000_82576)
3563 return;
3564
3565 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3566 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3567 if (hw->mac.type == e1000_i350) {
3568 u32 dvmolr;
3569
3570 dvmolr = rd32(E1000_DVMOLR(vfn));
3571 dvmolr |= E1000_DVMOLR_STRVLAN;
3572 wr32(E1000_DVMOLR(vfn), dvmolr);
3573 }
8151d294 3574 if (aupe)
b980ac18 3575 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3576 else
3577 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3578
3579 /* clear all bits that might not be set */
3580 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3581
a99955fc 3582 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3583 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3584 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3585 * multicast packets
3586 */
3587 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3588 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3589
3590 wr32(E1000_VMOLR(vfn), vmolr);
3591}
3592
85b430b4 3593/**
b980ac18
JK		 3594 * igb_configure_rx_ring - Configure a receive ring after Reset
3595 * @adapter: board private structure
3596 * @ring: receive ring to be configured
85b430b4 3597 *
b980ac18 3598 * Configure the Rx unit of the MAC after a reset.
85b430b4 3599 **/
d7ee5b3a 3600void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3601 struct igb_ring *ring)
85b430b4
AD		 3602{
3603 struct e1000_hw *hw = &adapter->hw;
3604 u64 rdba = ring->dma;
3605 int reg_idx = ring->reg_idx;
a74420e0 3606 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3607
3608 /* disable the queue */
a74420e0 3609 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3610
3611 /* Set DMA base address registers */
3612 wr32(E1000_RDBAL(reg_idx),
3613 rdba & 0x00000000ffffffffULL);
3614 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3615 wr32(E1000_RDLEN(reg_idx),
b980ac18 3616 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3617
3618 /* initialize head and tail */
fce99e34 3619 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3620 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3621 writel(0, ring->tail);
85b430b4 3622
952f72a8 3623 /* set descriptor configuration */
44390ca6 3624 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3625 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3626 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3627 if (hw->mac.type >= e1000_82580)
757b77e2 3628 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3629 /* Only set Drop Enable if we are supporting multiple queues */
3630 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3631 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3632
3633 wr32(E1000_SRRCTL(reg_idx), srrctl);
3634
7d5753f0 3635 /* set filtering for VMDQ pools */
8151d294 3636 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3637
85b430b4
AD		 3638 rxdctl |= IGB_RX_PTHRESH;
3639 rxdctl |= IGB_RX_HTHRESH << 8;
3640 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3641
3642 /* enable receive descriptor fetching */
3643 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3644 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3645}
3646
9d5c8243 3647/**
b980ac18
JK		 3648 * igb_configure_rx - Configure receive Unit after Reset
3649 * @adapter: board private structure
9d5c8243 3650 *
b980ac18 3651 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3652 **/
3653static void igb_configure_rx(struct igb_adapter *adapter)
3654{
9107584e 3655 int i;
9d5c8243 3656
68d480c4
AD		 3657 /* set UTA to appropriate mode */
3658 igb_set_uta(adapter);
3659
26ad9178
AD		 3660 /* set the correct pool for the PF default MAC address in entry 0 */
3661 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3662 adapter->vfs_allocated_count);
26ad9178 3663
06cf2666 3664 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3665 * the Base and Length of the Rx Descriptor Ring
3666 */
f9d40f6a
AD		 3667 for (i = 0; i < adapter->num_rx_queues; i++)
3668 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3669}
3670
3671/**
b980ac18
JK		 3672 * igb_free_tx_resources - Free Tx Resources per Queue
3673 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3674 *
b980ac18 3675 * Free all transmit software resources
9d5c8243 3676 **/
68fd9910 3677void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3678{
3b644cf6 3679 igb_clean_tx_ring(tx_ring);
9d5c8243 3680
06034649
AD		 3681 vfree(tx_ring->tx_buffer_info);
3682 tx_ring->tx_buffer_info = NULL;
9d5c8243 3683
439705e1
AD		 3684 /* if not set, then don't free */
3685 if (!tx_ring->desc)
3686 return;
3687
59d71989
AD		 3688 dma_free_coherent(tx_ring->dev, tx_ring->size,
3689 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3690
3691 tx_ring->desc = NULL;
3692}
3693
3694/**
b980ac18
JK		 3695 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3696 * @adapter: board private structure
9d5c8243 3697 *
b980ac18 3698 * Free all transmit software resources
9d5c8243
AK		 3699 **/
3700static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3701{
3702 int i;
3703
3704 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3705 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3706}
3707
ebe42d16
AD		 3708void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3709 struct igb_tx_buffer *tx_buffer)
3710{
3711 if (tx_buffer->skb) {
3712 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3713 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3714 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3715 dma_unmap_addr(tx_buffer, dma),
3716 dma_unmap_len(tx_buffer, len),
ebe42d16 3717 DMA_TO_DEVICE);
c9f14bf3 3718 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3719 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3720 dma_unmap_addr(tx_buffer, dma),
3721 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3722 DMA_TO_DEVICE);
3723 }
3724 tx_buffer->next_to_watch = NULL;
3725 tx_buffer->skb = NULL;
c9f14bf3 3726 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3727 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3728}
3729
3730/**
b980ac18
JK		 3731 * igb_clean_tx_ring - Free Tx Buffers
3732 * @tx_ring: ring to be cleaned
9d5c8243 3733 **/
3b644cf6 3734static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3735{
06034649 3736 struct igb_tx_buffer *buffer_info;
9d5c8243 3737 unsigned long size;
6ad4edfc 3738 u16 i;
9d5c8243 3739
06034649 3740 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3741 return;
3742 /* Free all the Tx ring sk_buffs */
3743
3744 for (i = 0; i < tx_ring->count; i++) {
06034649 3745 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3746 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3747 }
3748
dad8a3b3
JF		 3749 netdev_tx_reset_queue(txring_txq(tx_ring));
3750
06034649
AD		 3751 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3752 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3753
3754 /* Zero out the descriptor ring */
9d5c8243
AK		 3755 memset(tx_ring->desc, 0, tx_ring->size);
3756
3757 tx_ring->next_to_use = 0;
3758 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3759}
3760
3761/**
b980ac18
JK		 3762 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3763 * @adapter: board private structure
9d5c8243
AK		 3764 **/
3765static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3766{
3767 int i;
3768
3769 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3770 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3771}
3772
3773/**
b980ac18
JK		 3774 * igb_free_rx_resources - Free Rx Resources
3775 * @rx_ring: ring to clean the resources from
9d5c8243 3776 *
b980ac18 3777 * Free all receive software resources
9d5c8243 3778 **/
68fd9910 3779void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3780{
3b644cf6 3781 igb_clean_rx_ring(rx_ring);
9d5c8243 3782
06034649
AD		 3783 vfree(rx_ring->rx_buffer_info);
3784 rx_ring->rx_buffer_info = NULL;
9d5c8243 3785
439705e1
AD		 3786 /* if not set, then don't free */
3787 if (!rx_ring->desc)
3788 return;
3789
59d71989
AD		 3790 dma_free_coherent(rx_ring->dev, rx_ring->size,
3791 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3792
3793 rx_ring->desc = NULL;
3794}
3795
3796/**
b980ac18
JK		 3797 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3798 * @adapter: board private structure
9d5c8243 3799 *
b980ac18 3800 * Free all receive software resources
9d5c8243
AK		 3801 **/
3802static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3803{
3804 int i;
3805
3806 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3807 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3808}
3809
3810/**
b980ac18
JK		 3811 * igb_clean_rx_ring - Free Rx Buffers per Queue
3812 * @rx_ring: ring to free buffers from
9d5c8243 3813 **/
3b644cf6 3814static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3815{
9d5c8243 3816 unsigned long size;
c023cd88 3817 u16 i;
9d5c8243 3818
1a1c225b
AD		 3819 if (rx_ring->skb)
3820 dev_kfree_skb(rx_ring->skb);
3821 rx_ring->skb = NULL;
3822
06034649 3823 if (!rx_ring->rx_buffer_info)
9d5c8243 3824 return;
439705e1 3825
9d5c8243
AK		 3826 /* Free all the Rx ring sk_buffs */
3827 for (i = 0; i < rx_ring->count; i++) {
06034649 3828 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3829
cbc8e55f
AD		 3830 if (!buffer_info->page)
3831 continue;
3832
3833 dma_unmap_page(rx_ring->dev,
3834 buffer_info->dma,
3835 PAGE_SIZE,
3836 DMA_FROM_DEVICE);
3837 __free_page(buffer_info->page);
3838
1a1c225b 3839 buffer_info->page = NULL;
9d5c8243
AK		 3840 }
3841
06034649
AD		 3842 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3843 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3844
3845 /* Zero out the descriptor ring */
3846 memset(rx_ring->desc, 0, rx_ring->size);
3847
cbc8e55f 3848 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3849 rx_ring->next_to_clean = 0;
3850 rx_ring->next_to_use = 0;
9d5c8243
AK		 3851}
3852
3853/**
b980ac18
JK		 3854 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3855 * @adapter: board private structure
9d5c8243
AK		 3856 **/
3857static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3858{
3859 int i;
3860
3861 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3862 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3863}
3864
3865/**
b980ac18
JK		 3866 * igb_set_mac - Change the Ethernet Address of the NIC
3867 * @netdev: network interface device structure
3868 * @p: pointer to an address structure
9d5c8243 3869 *
b980ac18 3870 * Returns 0 on success, negative on failure
9d5c8243
AK		 3871 **/
3872static int igb_set_mac(struct net_device *netdev, void *p)
3873{
3874 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3875 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3876 struct sockaddr *addr = p;
3877
3878 if (!is_valid_ether_addr(addr->sa_data))
3879 return -EADDRNOTAVAIL;
3880
3881 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3882 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3883
26ad9178
AD		 3884 /* set the correct pool for the new PF MAC address in entry 0 */
3885 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3886 adapter->vfs_allocated_count);
e1739522 3887
9d5c8243
AK		 3888 return 0;
3889}
3890
3891/**
b980ac18
JK		 3892 * igb_write_mc_addr_list - write multicast addresses to MTA
3893 * @netdev: network interface device structure
9d5c8243 3894 *
b980ac18
JK		 3895 * Writes multicast address list to the MTA hash table.
3896 * Returns: -ENOMEM on failure
3897 * 0 on no addresses written
3898 * X on writing X addresses to MTA
9d5c8243 3899 **/
68d480c4 3900static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3901{
3902 struct igb_adapter *adapter = netdev_priv(netdev);
3903 struct e1000_hw *hw = &adapter->hw;
22bedad3 3904 struct netdev_hw_addr *ha;
68d480c4 3905 u8 *mta_list;
9d5c8243
AK		 3906 int i;
3907
4cd24eaf 3908 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3909 /* nothing to program, so clear mc list */
3910 igb_update_mc_addr_list(hw, NULL, 0);
3911 igb_restore_vf_multicasts(adapter);
3912 return 0;
3913 }
9d5c8243 3914
4cd24eaf 3915 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3916 if (!mta_list)
3917 return -ENOMEM;
ff41f8dc 3918
68d480c4 3919 /* The shared function expects a packed array of only addresses. */
48e2f183 3920 i = 0;
22bedad3
JP		 3921 netdev_for_each_mc_addr(ha, netdev)
3922 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3923
68d480c4
AD		 3924 igb_update_mc_addr_list(hw, mta_list, i);
3925 kfree(mta_list);
3926
4cd24eaf 3927 return netdev_mc_count(netdev);
68d480c4
AD		 3928}
3929
3930/**
b980ac18
JK		 3931 * igb_write_uc_addr_list - write unicast addresses to RAR table
3932 * @netdev: network interface device structure
68d480c4 3933 *
b980ac18
JK		 3934 * Writes unicast address list to the RAR table.
3935 * Returns: -ENOMEM on failure/insufficient address space
3936 * 0 on no addresses written
3937 * X on writing X addresses to the RAR table
68d480c4
AD		 3938 **/
3939static int igb_write_uc_addr_list(struct net_device *netdev)
3940{
3941 struct igb_adapter *adapter = netdev_priv(netdev);
3942 struct e1000_hw *hw = &adapter->hw;
3943 unsigned int vfn = adapter->vfs_allocated_count;
3944 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3945 int count = 0;
3946
3947 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3948 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3949 return -ENOMEM;
9d5c8243 3950
32e7bfc4 3951 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3952 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3953
3954 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3955 if (!rar_entries)
3956 break;
26ad9178 3957 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3958 rar_entries--,
3959 vfn);
68d480c4 3960 count++;
ff41f8dc
AD		 3961 }
3962 }
3963 /* write the addresses in reverse order to avoid write combining */
3964 for (; rar_entries > 0 ; rar_entries--) {
3965 wr32(E1000_RAH(rar_entries), 0);
3966 wr32(E1000_RAL(rar_entries), 0);
3967 }
3968 wrfl();
3969
68d480c4
AD		 3970 return count;
3971}
3972
3973/**
b980ac18
JK		 3974 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3975 * @netdev: network interface device structure
68d480c4 3976 *
b980ac18
JK		 3977 * The set_rx_mode entry point is called whenever the unicast or multicast
3978 * address lists or the network interface flags are updated. This routine is
3979 * responsible for configuring the hardware for proper unicast, multicast,
3980 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3981 **/
3982static void igb_set_rx_mode(struct net_device *netdev)
3983{
3984 struct igb_adapter *adapter = netdev_priv(netdev);
3985 struct e1000_hw *hw = &adapter->hw;
3986 unsigned int vfn = adapter->vfs_allocated_count;
3987 u32 rctl, vmolr = 0;
3988 int count;
3989
3990 /* Check for Promiscuous and All Multicast modes */
3991 rctl = rd32(E1000_RCTL);
3992
3993 /* clear the effected bits */
3994 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3995
3996 if (netdev->flags & IFF_PROMISC) {
6f3dc319 3997 /* retain VLAN HW filtering if in VT mode */
7e44892c 3998 if (adapter->vfs_allocated_count)
6f3dc319 3999 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4000 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4001 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4002 } else {
4003 if (netdev->flags & IFF_ALLMULTI) {
4004 rctl |= E1000_RCTL_MPE;
4005 vmolr |= E1000_VMOLR_MPME;
4006 } else {
b980ac18 4007 /* Write addresses to the MTA, if the attempt fails
25985edc 4008 * then we should just turn on promiscuous mode so
68d480c4
AD		 4009 * that we can at least receive multicast traffic
4010 */
4011 count = igb_write_mc_addr_list(netdev);
4012 if (count < 0) {
4013 rctl |= E1000_RCTL_MPE;
4014 vmolr |= E1000_VMOLR_MPME;
4015 } else if (count) {
4016 vmolr |= E1000_VMOLR_ROMPE;
4017 }
4018 }
b980ac18 4019 /* Write addresses to available RAR registers, if there is not
68d480c4 4020 * sufficient space to store all the addresses then enable
25985edc 4021 * unicast promiscuous mode
68d480c4
AD		 4022 */
4023 count = igb_write_uc_addr_list(netdev);
4024 if (count < 0) {
4025 rctl |= E1000_RCTL_UPE;
4026 vmolr |= E1000_VMOLR_ROPE;
4027 }
4028 rctl |= E1000_RCTL_VFE;
28fc06f5 4029 }
68d480c4 4030 wr32(E1000_RCTL, rctl);
28fc06f5 4031
b980ac18 4032 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4033 * the VMOLR to enable the appropriate modes. Without this workaround
4034 * we will have issues with VLAN tag stripping not being done for frames
4035 * that are only arriving because we are the default pool
4036 */
f96a8a0b 4037 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4038 return;
9d5c8243 4039
68d480c4 4040 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4041 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4042 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4043 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4044}
4045
13800469
GR		 4046static void igb_check_wvbr(struct igb_adapter *adapter)
4047{
4048 struct e1000_hw *hw = &adapter->hw;
4049 u32 wvbr = 0;
4050
4051 switch (hw->mac.type) {
4052 case e1000_82576:
4053 case e1000_i350:
4054 if (!(wvbr = rd32(E1000_WVBR)))
4055 return;
4056 break;
4057 default:
4058 break;
4059 }
4060
4061 adapter->wvbr |= wvbr;
4062}
4063
4064#define IGB_STAGGERED_QUEUE_OFFSET 8
4065
4066static void igb_spoof_check(struct igb_adapter *adapter)
4067{
4068 int j;
4069
4070 if (!adapter->wvbr)
4071 return;
4072
4073 for(j = 0; j < adapter->vfs_allocated_count; j++) {
4074 if (adapter->wvbr & (1 << j) ||
4075 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4076 dev_warn(&adapter->pdev->dev,
4077 "Spoof event(s) detected on VF %d\n", j);
4078 adapter->wvbr &=
4079 ~((1 << j) |
4080 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4081 }
4082 }
4083}
4084
9d5c8243 4085/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4086 * the phy
4087 */
9d5c8243
AK		 4088static void igb_update_phy_info(unsigned long data)
4089{
4090 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4091 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4092}
4093
4d6b725e 4094/**
b980ac18
JK		 4095 * igb_has_link - check shared code for link and determine up/down
4096 * @adapter: pointer to driver private info
4d6b725e 4097 **/
3145535a 4098bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4099{
4100 struct e1000_hw *hw = &adapter->hw;
4101 bool link_active = false;
4d6b725e
AD		 4102
4103 /* get_link_status is set on LSC (link status) interrupt or
4104 * rx sequence error interrupt. get_link_status will stay
4105 * false until the e1000_check_for_link establishes link
4106 * for copper adapters ONLY
4107 */
4108 switch (hw->phy.media_type) {
4109 case e1000_media_type_copper:
e5c3370f
AA		 4110 if (!hw->mac.get_link_status)
4111 return true;
4d6b725e 4112 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4113 hw->mac.ops.check_for_link(hw);
4114 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4115 break;
4116 default:
4117 case e1000_media_type_unknown:
4118 break;
4119 }
4120
aa9b8cc4
AA		 4121 if (((hw->mac.type == e1000_i210) ||
4122 (hw->mac.type == e1000_i211)) &&
4123 (hw->phy.id == I210_I_PHY_ID)) {
4124 if (!netif_carrier_ok(adapter->netdev)) {
4125 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4126 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4127 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4128 adapter->link_check_timeout = jiffies;
4129 }
4130 }
4131
4d6b725e
AD		 4132 return link_active;
4133}
4134
563988dc
SA		 4135static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4136{
4137 bool ret = false;
4138 u32 ctrl_ext, thstat;
4139
f96a8a0b 4140 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4141 if (hw->mac.type == e1000_i350) {
4142 thstat = rd32(E1000_THSTAT);
4143 ctrl_ext = rd32(E1000_CTRL_EXT);
4144
4145 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4146 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4147 ret = !!(thstat & event);
563988dc
SA		 4148 }
4149
4150 return ret;
4151}
4152
9d5c8243 4153/**
b980ac18
JK		 4154 * igb_watchdog - Timer Call-back
4155 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4156 **/
4157static void igb_watchdog(unsigned long data)
4158{
4159 struct igb_adapter *adapter = (struct igb_adapter *)data;
4160 /* Do the rest outside of interrupt context */
4161 schedule_work(&adapter->watchdog_task);
4162}
4163
4164static void igb_watchdog_task(struct work_struct *work)
4165{
4166 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4167 struct igb_adapter,
4168 watchdog_task);
9d5c8243 4169 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4170 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4171 struct net_device *netdev = adapter->netdev;
563988dc 4172 u32 link;
7a6ea550 4173 int i;
56cec249 4174 u32 connsw;
9d5c8243 4175
4d6b725e 4176 link = igb_has_link(adapter);
aa9b8cc4
AA		 4177
4178 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4179 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4180 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4181 else
4182 link = false;
4183 }
4184
56cec249
CW		 4185 /* Force link down if we have fiber to swap to */
4186 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4187 if (hw->phy.media_type == e1000_media_type_copper) {
4188 connsw = rd32(E1000_CONNSW);
4189 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4190 link = 0;
4191 }
4192 }
9d5c8243 4193 if (link) {
2bdfc4e2
CW		 4194 /* Perform a reset if the media type changed. */
4195 if (hw->dev_spec._82575.media_changed) {
4196 hw->dev_spec._82575.media_changed = false;
4197 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4198 igb_reset(adapter);
4199 }
749ab2cd
YZ		 4200 /* Cancel scheduled suspend requests. */
4201 pm_runtime_resume(netdev->dev.parent);
4202
9d5c8243
AK		 4203 if (!netif_carrier_ok(netdev)) {
4204 u32 ctrl;
330a6d6a 4205 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4206 &adapter->link_speed,
4207 &adapter->link_duplex);
9d5c8243
AK		 4208
4209 ctrl = rd32(E1000_CTRL);
527d47c1 4210 /* Links status message must follow this format */
c75c4edf
CW		 4211 netdev_info(netdev,
4212 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4213 netdev->name,
4214 adapter->link_speed,
4215 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4216 "Full" : "Half",
4217 (ctrl & E1000_CTRL_TFCE) &&
4218 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4219 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4220 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4221
f4c01e96
CW		 4222 /* disable EEE if enabled */
4223 if ((adapter->flags & IGB_FLAG_EEE) &&
4224 (adapter->link_duplex == HALF_DUPLEX)) {
4225 dev_info(&adapter->pdev->dev,
4226 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4227 adapter->hw.dev_spec._82575.eee_disable = true;
4228 adapter->flags &= ~IGB_FLAG_EEE;
4229 }
4230
c0ba4778
KS		 4231 /* check if SmartSpeed worked */
4232 igb_check_downshift(hw);
4233 if (phy->speed_downgraded)
4234 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4235
563988dc 4236 /* check for thermal sensor event */
876d2d6f 4237 if (igb_thermal_sensor_event(hw,
d34a15ab 4238 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4239 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4240
d07f3e37 4241 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4242 adapter->tx_timeout_factor = 1;
4243 switch (adapter->link_speed) {
4244 case SPEED_10:
9d5c8243
AK		 4245 adapter->tx_timeout_factor = 14;
4246 break;
4247 case SPEED_100:
9d5c8243
AK		 4248 /* maybe add some timeout factor ? */
4249 break;
4250 }
4251
4252 netif_carrier_on(netdev);
9d5c8243 4253
4ae196df 4254 igb_ping_all_vfs(adapter);
17dc566c 4255 igb_check_vf_rate_limit(adapter);
4ae196df 4256
4b1a9877 4257 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4258 if (!test_bit(__IGB_DOWN, &adapter->state))
4259 mod_timer(&adapter->phy_info_timer,
4260 round_jiffies(jiffies + 2 * HZ));
4261 }
4262 } else {
4263 if (netif_carrier_ok(netdev)) {
4264 adapter->link_speed = 0;
4265 adapter->link_duplex = 0;
563988dc
SA		 4266
4267 /* check for thermal sensor event */
876d2d6f
JK		 4268 if (igb_thermal_sensor_event(hw,
4269 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4270 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4271 }
563988dc 4272
527d47c1 4273 /* Links status message must follow this format */
c75c4edf 4274 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4275 netdev->name);
9d5c8243 4276 netif_carrier_off(netdev);
4b1a9877 4277
4ae196df
AD		 4278 igb_ping_all_vfs(adapter);
4279
4b1a9877 4280 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4281 if (!test_bit(__IGB_DOWN, &adapter->state))
4282 mod_timer(&adapter->phy_info_timer,
4283 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4284
56cec249
CW		 4285 /* link is down, time to check for alternate media */
4286 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4287 igb_check_swap_media(adapter);
4288 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4289 schedule_work(&adapter->reset_task);
4290 /* return immediately */
4291 return;
4292 }
4293 }
749ab2cd
YZ		 4294 pm_schedule_suspend(netdev->dev.parent,
4295 MSEC_PER_SEC * 5);
56cec249
CW		 4296
4297 /* also check for alternate media here */
4298 } else if (!netif_carrier_ok(netdev) &&
4299 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4300 igb_check_swap_media(adapter);
4301 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4302 schedule_work(&adapter->reset_task);
4303 /* return immediately */
4304 return;
4305 }
9d5c8243
AK		 4306 }
4307 }
4308
12dcd86b
ED		 4309 spin_lock(&adapter->stats64_lock);
4310 igb_update_stats(adapter, &adapter->stats64);
4311 spin_unlock(&adapter->stats64_lock);
9d5c8243 4312
dbabb065 4313 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4314 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4315 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4316 /* We've lost link, so the controller stops DMA,
4317 * but we've got queued Tx work that's never going
4318 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4319 * (Do the reset outside of interrupt context).
4320 */
dbabb065
AD		 4321 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4322 adapter->tx_timeout_count++;
4323 schedule_work(&adapter->reset_task);
4324 /* return immediately since reset is imminent */
4325 return;
4326 }
9d5c8243 4327 }
9d5c8243 4328
dbabb065 4329 /* Force detection of hung controller every watchdog period */
6d095fa8 4330 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4331 }
f7ba205e 4332
b980ac18 4333 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4334 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4335 u32 eics = 0;
0d1ae7f4
AD		 4336 for (i = 0; i < adapter->num_q_vectors; i++)
4337 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4338 wr32(E1000_EICS, eics);
4339 } else {
4340 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4341 }
9d5c8243 4342
13800469 4343 igb_spoof_check(adapter);
fc580751 4344 igb_ptp_rx_hang(adapter);
13800469 4345
9d5c8243 4346 /* Reset the timer */
aa9b8cc4
AA		 4347 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4348 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4349 mod_timer(&adapter->watchdog_timer,
4350 round_jiffies(jiffies + HZ));
4351 else
4352 mod_timer(&adapter->watchdog_timer,
4353 round_jiffies(jiffies + 2 * HZ));
4354 }
9d5c8243
AK		 4355}
4356
4357enum latency_range {
4358 lowest_latency = 0,
4359 low_latency = 1,
4360 bulk_latency = 2,
4361 latency_invalid = 255
4362};
4363
6eb5a7f1 4364/**
b980ac18
JK		 4365 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4366 * @q_vector: pointer to q_vector
6eb5a7f1 4367 *
b980ac18
JK		 4368 * Stores a new ITR value based on strictly on packet size. This
4369 * algorithm is less sophisticated than that used in igb_update_itr,
4370 * due to the difficulty of synchronizing statistics across multiple
4371 * receive rings. The divisors and thresholds used by this function
4372 * were determined based on theoretical maximum wire speed and testing
4373 * data, in order to minimize response time while increasing bulk
4374 * throughput.
406d4965 4375 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4376 * NOTE: This function is called only when operating in a multiqueue
4377 * receive environment.
6eb5a7f1 4378 **/
047e0030 4379static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4380{
047e0030 4381 int new_val = q_vector->itr_val;
6eb5a7f1 4382 int avg_wire_size = 0;
047e0030 4383 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4384 unsigned int packets;
9d5c8243 4385
6eb5a7f1
AD		 4386 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4387 * ints/sec - ITR timer value of 120 ticks.
4388 */
4389 if (adapter->link_speed != SPEED_1000) {
0ba82994 4390 new_val = IGB_4K_ITR;
6eb5a7f1 4391 goto set_itr_val;
9d5c8243 4392 }
047e0030 4393
0ba82994
AD		 4394 packets = q_vector->rx.total_packets;
4395 if (packets)
4396 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4397
0ba82994
AD		 4398 packets = q_vector->tx.total_packets;
4399 if (packets)
4400 avg_wire_size = max_t(u32, avg_wire_size,
4401 q_vector->tx.total_bytes / packets);
047e0030
AD		 4402
4403 /* if avg_wire_size isn't set no work was done */
4404 if (!avg_wire_size)
4405 goto clear_counts;
9d5c8243 4406
6eb5a7f1
AD		 4407 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4408 avg_wire_size += 24;
4409
4410 /* Don't starve jumbo frames */
4411 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4412
6eb5a7f1
AD		 4413 /* Give a little boost to mid-size frames */
4414 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4415 new_val = avg_wire_size / 3;
4416 else
4417 new_val = avg_wire_size / 2;
9d5c8243 4418
0ba82994
AD		 4419 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4420 if (new_val < IGB_20K_ITR &&
4421 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4422 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4423 new_val = IGB_20K_ITR;
abe1c363 4424
6eb5a7f1 4425set_itr_val:
047e0030
AD		 4426 if (new_val != q_vector->itr_val) {
4427 q_vector->itr_val = new_val;
4428 q_vector->set_itr = 1;
9d5c8243 4429 }
6eb5a7f1 4430clear_counts:
0ba82994
AD		 4431 q_vector->rx.total_bytes = 0;
4432 q_vector->rx.total_packets = 0;
4433 q_vector->tx.total_bytes = 0;
4434 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4435}
4436
4437/**
b980ac18
JK		 4438 * igb_update_itr - update the dynamic ITR value based on statistics
4439 * @q_vector: pointer to q_vector
4440 * @ring_container: ring info to update the itr for
4441 *
4442 * Stores a new ITR value based on packets and byte
4443 * counts during the last interrupt. The advantage of per interrupt
4444 * computation is faster updates and more accurate ITR for the current
4445 * traffic pattern. Constants in this function were computed
4446 * based on theoretical maximum wire speed and thresholds were set based
4447 * on testing data as well as attempting to minimize response time
4448 * while increasing bulk throughput.
406d4965 4449 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4450 * NOTE: These calculations are only valid when operating in a single-
4451 * queue environment.
9d5c8243 4452 **/
0ba82994
AD		 4453static void igb_update_itr(struct igb_q_vector *q_vector,
4454 struct igb_ring_container *ring_container)
9d5c8243 4455{
0ba82994
AD		 4456 unsigned int packets = ring_container->total_packets;
4457 unsigned int bytes = ring_container->total_bytes;
4458 u8 itrval = ring_container->itr;
9d5c8243 4459
0ba82994 4460 /* no packets, exit with status unchanged */
9d5c8243 4461 if (packets == 0)
0ba82994 4462 return;
9d5c8243 4463
0ba82994 4464 switch (itrval) {
9d5c8243
AK		 4465 case lowest_latency:
4466 /* handle TSO and jumbo frames */
4467 if (bytes/packets > 8000)
0ba82994 4468 itrval = bulk_latency;
9d5c8243 4469 else if ((packets < 5) && (bytes > 512))
0ba82994 4470 itrval = low_latency;
9d5c8243
AK		 4471 break;
4472 case low_latency: /* 50 usec aka 20000 ints/s */
4473 if (bytes > 10000) {
4474 /* this if handles the TSO accounting */
d34a15ab 4475 if (bytes/packets > 8000)
0ba82994 4476 itrval = bulk_latency;
d34a15ab 4477 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4478 itrval = bulk_latency;
d34a15ab 4479 else if ((packets > 35))
0ba82994 4480 itrval = lowest_latency;
9d5c8243 4481 } else if (bytes/packets > 2000) {
0ba82994 4482 itrval = bulk_latency;
9d5c8243 4483 } else if (packets <= 2 && bytes < 512) {
0ba82994 4484 itrval = lowest_latency;
9d5c8243
AK		 4485 }
4486 break;
4487 case bulk_latency: /* 250 usec aka 4000 ints/s */
4488 if (bytes > 25000) {
4489 if (packets > 35)
0ba82994 4490 itrval = low_latency;
1e5c3d21 4491 } else if (bytes < 1500) {
0ba82994 4492 itrval = low_latency;
9d5c8243
AK		 4493 }
4494 break;
4495 }
4496
0ba82994
AD		 4497 /* clear work counters since we have the values we need */
4498 ring_container->total_bytes = 0;
4499 ring_container->total_packets = 0;
4500
4501 /* write updated itr to ring container */
4502 ring_container->itr = itrval;
9d5c8243
AK		 4503}
4504
0ba82994 4505static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4506{
0ba82994 4507 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4508 u32 new_itr = q_vector->itr_val;
0ba82994 4509 u8 current_itr = 0;
9d5c8243
AK		 4510
4511 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4512 if (adapter->link_speed != SPEED_1000) {
4513 current_itr = 0;
0ba82994 4514 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4515 goto set_itr_now;
4516 }
4517
0ba82994
AD		 4518 igb_update_itr(q_vector, &q_vector->tx);
4519 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4520
0ba82994 4521 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4522
6eb5a7f1 4523 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4524 if (current_itr == lowest_latency &&
4525 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4526 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4527 current_itr = low_latency;
4528
9d5c8243
AK		 4529 switch (current_itr) {
4530 /* counts and packets in update_itr are dependent on these numbers */
4531 case lowest_latency:
0ba82994 4532 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4533 break;
4534 case low_latency:
0ba82994 4535 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4536 break;
4537 case bulk_latency:
0ba82994 4538 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4539 break;
4540 default:
4541 break;
4542 }
4543
4544set_itr_now:
047e0030 4545 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4546 /* this attempts to bias the interrupt rate towards Bulk
4547 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4548 * increasing
4549 */
047e0030 4550 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4551 max((new_itr * q_vector->itr_val) /
4552 (new_itr + (q_vector->itr_val >> 2)),
4553 new_itr) : new_itr;
9d5c8243
AK		 4554 /* Don't write the value here; it resets the adapter's
4555 * internal timer, and causes us to delay far longer than
4556 * we should between interrupts. Instead, we write the ITR
4557 * value at the beginning of the next interrupt so the timing
4558 * ends up being correct.
4559 */
047e0030
AD		 4560 q_vector->itr_val = new_itr;
4561 q_vector->set_itr = 1;
9d5c8243 4562 }
9d5c8243
AK		 4563}
4564
c50b52a0
SH		 4565static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4566 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4567{
4568 struct e1000_adv_tx_context_desc *context_desc;
4569 u16 i = tx_ring->next_to_use;
4570
4571 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4572
4573 i++;
4574 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4575
4576 /* set bits to identify this as an advanced context descriptor */
4577 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4578
4579 /* For 82575, context index must be unique per ring. */
866cff06 4580 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4581 mss_l4len_idx |= tx_ring->reg_idx << 4;
4582
4583 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4584 context_desc->seqnum_seed = 0;
4585 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4586 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4587}
4588
7af40ad9
AD		 4589static int igb_tso(struct igb_ring *tx_ring,
4590 struct igb_tx_buffer *first,
4591 u8 *hdr_len)
9d5c8243 4592{
7af40ad9 4593 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4594 u32 vlan_macip_lens, type_tucmd;
4595 u32 mss_l4len_idx, l4len;
06c14e5a 4596 int err;
7d13a7d0 4597
ed6aa105
AD		 4598 if (skb->ip_summed != CHECKSUM_PARTIAL)
4599 return 0;
4600
7d13a7d0
AD		 4601 if (!skb_is_gso(skb))
4602 return 0;
9d5c8243 4603
06c14e5a
FR		 4604 err = skb_cow_head(skb, 0);
4605 if (err < 0)
4606 return err;
9d5c8243 4607
7d13a7d0
AD		 4608 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4609 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4610
7c4d16ff 4611 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4612 struct iphdr *iph = ip_hdr(skb);
4613 iph->tot_len = 0;
4614 iph->check = 0;
4615 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4616 iph->daddr, 0,
4617 IPPROTO_TCP,
4618 0);
7d13a7d0 4619 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4620 first->tx_flags |= IGB_TX_FLAGS_TSO |
4621 IGB_TX_FLAGS_CSUM |
4622 IGB_TX_FLAGS_IPV4;
8e1e8a47 4623 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4624 ipv6_hdr(skb)->payload_len = 0;
4625 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4626 &ipv6_hdr(skb)->daddr,
4627 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4628 first->tx_flags |= IGB_TX_FLAGS_TSO |
4629 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4630 }
4631
7af40ad9 4632 /* compute header lengths */
7d13a7d0
AD		 4633 l4len = tcp_hdrlen(skb);
4634 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4635
7af40ad9
AD		 4636 /* update gso size and bytecount with header size */
4637 first->gso_segs = skb_shinfo(skb)->gso_segs;
4638 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4639
9d5c8243 4640 /* MSS L4LEN IDX */
7d13a7d0
AD		 4641 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4642 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4643
7d13a7d0
AD		 4644 /* VLAN MACLEN IPLEN */
4645 vlan_macip_lens = skb_network_header_len(skb);
4646 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4647 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4648
7d13a7d0 4649 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4650
7d13a7d0 4651 return 1;
9d5c8243
AK		 4652}
4653
7af40ad9 4654static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4655{
7af40ad9 4656 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4657 u32 vlan_macip_lens = 0;
4658 u32 mss_l4len_idx = 0;
4659 u32 type_tucmd = 0;
9d5c8243 4660
7d13a7d0 4661 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4662 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4663 return;
7d13a7d0
AD		 4664 } else {
4665 u8 l4_hdr = 0;
7af40ad9 4666 switch (first->protocol) {
7c4d16ff 4667 case htons(ETH_P_IP):
7d13a7d0
AD		 4668 vlan_macip_lens |= skb_network_header_len(skb);
4669 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4670 l4_hdr = ip_hdr(skb)->protocol;
4671 break;
7c4d16ff 4672 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4673 vlan_macip_lens |= skb_network_header_len(skb);
4674 l4_hdr = ipv6_hdr(skb)->nexthdr;
4675 break;
4676 default:
4677 if (unlikely(net_ratelimit())) {
4678 dev_warn(tx_ring->dev,
b980ac18
JK		 4679 "partial checksum but proto=%x!\n",
4680 first->protocol);
fa4a7ef3 4681 }
7d13a7d0
AD		 4682 break;
4683 }
fa4a7ef3 4684
7d13a7d0
AD		 4685 switch (l4_hdr) {
4686 case IPPROTO_TCP:
4687 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4688 mss_l4len_idx = tcp_hdrlen(skb) <<
4689 E1000_ADVTXD_L4LEN_SHIFT;
4690 break;
4691 case IPPROTO_SCTP:
4692 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4693 mss_l4len_idx = sizeof(struct sctphdr) <<
4694 E1000_ADVTXD_L4LEN_SHIFT;
4695 break;
4696 case IPPROTO_UDP:
4697 mss_l4len_idx = sizeof(struct udphdr) <<
4698 E1000_ADVTXD_L4LEN_SHIFT;
4699 break;
4700 default:
4701 if (unlikely(net_ratelimit())) {
4702 dev_warn(tx_ring->dev,
b980ac18
JK		 4703 "partial checksum but l4 proto=%x!\n",
4704 l4_hdr);
44b0cda3 4705 }
7d13a7d0 4706 break;
9d5c8243 4707 }
7af40ad9
AD		 4708
4709 /* update TX checksum flag */
4710 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4711 }
9d5c8243 4712
7d13a7d0 4713 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4714 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4715
7d13a7d0 4716 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4717}
4718
1d9daf45
AD		 4719#define IGB_SET_FLAG(_input, _flag, _result) \
4720 ((_flag <= _result) ? \
4721 ((u32)(_input & _flag) * (_result / _flag)) : \
4722 ((u32)(_input & _flag) / (_flag / _result)))
4723
4724static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4725{
4726 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4727 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4728 E1000_ADVTXD_DCMD_DEXT |
4729 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4730
4731 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4732 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4733 (E1000_ADVTXD_DCMD_VLE));
4734
4735 /* set segmentation bits for TSO */
4736 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4737 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4738
4739 /* set timestamp bit if present */
1d9daf45
AD		 4740 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4741 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4742
1d9daf45
AD		 4743 /* insert frame checksum */
4744 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4745
4746 return cmd_type;
4747}
4748
7af40ad9
AD		 4749static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4750 union e1000_adv_tx_desc *tx_desc,
4751 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4752{
4753 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4754
1d9daf45
AD		 4755 /* 82575 requires a unique index per ring */
4756 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4757 olinfo_status |= tx_ring->reg_idx << 4;
4758
4759 /* insert L4 checksum */
1d9daf45
AD		 4760 olinfo_status |= IGB_SET_FLAG(tx_flags,
4761 IGB_TX_FLAGS_CSUM,
4762 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4763
1d9daf45
AD		 4764 /* insert IPv4 checksum */
4765 olinfo_status |= IGB_SET_FLAG(tx_flags,
4766 IGB_TX_FLAGS_IPV4,
4767 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4768
7af40ad9 4769 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4770}
4771
7af40ad9
AD		 4772static void igb_tx_map(struct igb_ring *tx_ring,
4773 struct igb_tx_buffer *first,
ebe42d16 4774 const u8 hdr_len)
9d5c8243 4775{
7af40ad9 4776 struct sk_buff *skb = first->skb;
c9f14bf3 4777 struct igb_tx_buffer *tx_buffer;
ebe42d16 4778 union e1000_adv_tx_desc *tx_desc;
80d0759e 4779 struct skb_frag_struct *frag;
ebe42d16 4780 dma_addr_t dma;
80d0759e 4781 unsigned int data_len, size;
7af40ad9 4782 u32 tx_flags = first->tx_flags;
1d9daf45 4783 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4784 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4785
4786 tx_desc = IGB_TX_DESC(tx_ring, i);
4787
80d0759e
AD		 4788 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4789
4790 size = skb_headlen(skb);
4791 data_len = skb->data_len;
ebe42d16
AD		 4792
4793 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4794
80d0759e
AD		 4795 tx_buffer = first;
4796
4797 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4798 if (dma_mapping_error(tx_ring->dev, dma))
4799 goto dma_error;
4800
4801 /* record length, and DMA address */
4802 dma_unmap_len_set(tx_buffer, len, size);
4803 dma_unmap_addr_set(tx_buffer, dma, dma);
4804
4805 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4806
ebe42d16
AD		 4807 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4808 tx_desc->read.cmd_type_len =
1d9daf45 4809 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4810
4811 i++;
4812 tx_desc++;
4813 if (i == tx_ring->count) {
4814 tx_desc = IGB_TX_DESC(tx_ring, 0);
4815 i = 0;
4816 }
80d0759e 4817 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4818
4819 dma += IGB_MAX_DATA_PER_TXD;
4820 size -= IGB_MAX_DATA_PER_TXD;
4821
ebe42d16
AD		 4822 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4823 }
4824
4825 if (likely(!data_len))
4826 break;
2bbfebe2 4827
1d9daf45 4828 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4829
65689fef 4830 i++;
ebe42d16
AD		 4831 tx_desc++;
4832 if (i == tx_ring->count) {
4833 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4834 i = 0;
ebe42d16 4835 }
80d0759e 4836 tx_desc->read.olinfo_status = 0;
65689fef 4837
9e903e08 4838 size = skb_frag_size(frag);
ebe42d16
AD		 4839 data_len -= size;
4840
4841 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4842 size, DMA_TO_DEVICE);
6366ad33 4843
c9f14bf3 4844 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4845 }
4846
ebe42d16 4847 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4848 cmd_type |= size | IGB_TXD_DCMD;
4849 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4850
80d0759e
AD		 4851 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4852
8542db05
AD		 4853 /* set the timestamp */
4854 first->time_stamp = jiffies;
4855
b980ac18 4856 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4857 * are new descriptors to fetch. (Only applicable for weak-ordered
4858 * memory model archs, such as IA-64).
4859 *
4860 * We also need this memory barrier to make certain all of the
4861 * status bits have been updated before next_to_watch is written.
4862 */
4863 wmb();
4864
8542db05 4865 /* set next_to_watch value indicating a packet is present */
ebe42d16 4866 first->next_to_watch = tx_desc;
9d5c8243 4867
ebe42d16
AD		 4868 i++;
4869 if (i == tx_ring->count)
4870 i = 0;
6366ad33 4871
ebe42d16 4872 tx_ring->next_to_use = i;
6366ad33 4873
ebe42d16 4874 writel(i, tx_ring->tail);
6366ad33 4875
ebe42d16 4876 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4877 * at a time, it synchronizes IO on IA64/Altix systems
4878 */
ebe42d16
AD		 4879 mmiowb();
4880
4881 return;
4882
4883dma_error:
4884 dev_err(tx_ring->dev, "TX DMA map failed\n");
4885
4886 /* clear dma mappings for failed tx_buffer_info map */
4887 for (;;) {
c9f14bf3
AD		 4888 tx_buffer = &tx_ring->tx_buffer_info[i];
4889 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4890 if (tx_buffer == first)
ebe42d16 4891 break;
a77ff709
NN		 4892 if (i == 0)
4893 i = tx_ring->count;
6366ad33 4894 i--;
6366ad33
AD		 4895 }
4896
9d5c8243 4897 tx_ring->next_to_use = i;
9d5c8243
AK		 4898}
4899
6ad4edfc 4900static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4901{
e694e964
AD		 4902 struct net_device *netdev = tx_ring->netdev;
4903
661086df 4904 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4905
9d5c8243
AK		 4906 /* Herbert's original patch had:
4907 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4908 * but since that doesn't exist yet, just open code it.
4909 */
9d5c8243
AK		 4910 smp_mb();
4911
4912 /* We need to check again in a case another CPU has just
b980ac18
JK		 4913 * made room available.
4914 */
c493ea45 4915 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4916 return -EBUSY;
4917
4918 /* A reprieve! */
661086df 4919 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4920
4921 u64_stats_update_begin(&tx_ring->tx_syncp2);
4922 tx_ring->tx_stats.restart_queue2++;
4923 u64_stats_update_end(&tx_ring->tx_syncp2);
4924
9d5c8243
AK		 4925 return 0;
4926}
4927
6ad4edfc 4928static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4929{
c493ea45 4930 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4931 return 0;
e694e964 4932 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4933}
4934
cd392f5c
AD		 4935netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4936 struct igb_ring *tx_ring)
9d5c8243 4937{
8542db05 4938 struct igb_tx_buffer *first;
ebe42d16 4939 int tso;
91d4ee33 4940 u32 tx_flags = 0;
21ba6fe1 4941 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4942 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4943 u8 hdr_len = 0;
9d5c8243 4944
21ba6fe1
AD		 4945 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4946 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4947 * + 2 desc gap to keep tail from touching head,
9d5c8243 4948 * + 1 desc for context descriptor,
21ba6fe1
AD		 4949 * otherwise try next time
4950 */
4951 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4952 unsigned short f;
4953 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4954 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4955 } else {
4956 count += skb_shinfo(skb)->nr_frags;
4957 }
4958
4959 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4960 /* this is a hard error */
9d5c8243
AK		 4961 return NETDEV_TX_BUSY;
4962 }
33af6bcc 4963
7af40ad9
AD		 4964 /* record the location of the first descriptor for this packet */
4965 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4966 first->skb = skb;
4967 first->bytecount = skb->len;
4968 first->gso_segs = 1;
4969
b646c22e
AD		 4970 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4971 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4972
ed4420a3
JK		 4973 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
4974 &adapter->state)) {
b646c22e
AD		 4975 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4976 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4977
4978 adapter->ptp_tx_skb = skb_get(skb);
4979 adapter->ptp_tx_start = jiffies;
4980 if (adapter->hw.mac.type == e1000_82576)
4981 schedule_work(&adapter->ptp_tx_work);
4982 }
33af6bcc 4983 }
9d5c8243 4984
afc835d1
JK		 4985 skb_tx_timestamp(skb);
4986
eab6d18d 4987 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 4988 tx_flags |= IGB_TX_FLAGS_VLAN;
4989 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4990 }
4991
7af40ad9
AD		 4992 /* record initial flags and protocol */
4993 first->tx_flags = tx_flags;
4994 first->protocol = protocol;
cdfd01fc 4995
7af40ad9
AD		 4996 tso = igb_tso(tx_ring, first, &hdr_len);
4997 if (tso < 0)
7d13a7d0 4998 goto out_drop;
7af40ad9
AD		 4999 else if (!tso)
5000 igb_tx_csum(tx_ring, first);
9d5c8243 5001
7af40ad9 5002 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 5003
5004 /* Make sure there is space in the ring for the next send. */
21ba6fe1 5005 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 5006
9d5c8243 5007 return NETDEV_TX_OK;
7d13a7d0
AD		 5008
5009out_drop:
7af40ad9
AD		 5010 igb_unmap_and_free_tx_resource(tx_ring, first);
5011
7d13a7d0 5012 return NETDEV_TX_OK;
9d5c8243
AK		 5013}
5014
1cc3bd87
AD		 5015static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5016 struct sk_buff *skb)
5017{
5018 unsigned int r_idx = skb->queue_mapping;
5019
5020 if (r_idx >= adapter->num_tx_queues)
5021 r_idx = r_idx % adapter->num_tx_queues;
5022
5023 return adapter->tx_ring[r_idx];
5024}
5025
cd392f5c
AD		 5026static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5027 struct net_device *netdev)
9d5c8243
AK		 5028{
5029 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5030
5031 if (test_bit(__IGB_DOWN, &adapter->state)) {
5032 dev_kfree_skb_any(skb);
5033 return NETDEV_TX_OK;
5034 }
5035
5036 if (skb->len <= 0) {
5037 dev_kfree_skb_any(skb);
5038 return NETDEV_TX_OK;
5039 }
5040
b980ac18 5041 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5042 * in order to meet this minimum size requirement.
5043 */
ea5ceeab
TD		 5044 if (unlikely(skb->len < 17)) {
5045 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 5046 return NETDEV_TX_OK;
5047 skb->len = 17;
ea5ceeab 5048 skb_set_tail_pointer(skb, 17);
1cc3bd87 5049 }
9d5c8243 5050
1cc3bd87 5051 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5052}
5053
5054/**
b980ac18
JK		 5055 * igb_tx_timeout - Respond to a Tx Hang
5056 * @netdev: network interface device structure
9d5c8243
AK		 5057 **/
5058static void igb_tx_timeout(struct net_device *netdev)
5059{
5060 struct igb_adapter *adapter = netdev_priv(netdev);
5061 struct e1000_hw *hw = &adapter->hw;
5062
5063 /* Do the reset outside of interrupt context */
5064 adapter->tx_timeout_count++;
f7ba205e 5065
06218a8d 5066 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5067 hw->dev_spec._82575.global_device_reset = true;
5068
9d5c8243 5069 schedule_work(&adapter->reset_task);
265de409
AD		 5070 wr32(E1000_EICS,
5071 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5072}
5073
5074static void igb_reset_task(struct work_struct *work)
5075{
5076 struct igb_adapter *adapter;
5077 adapter = container_of(work, struct igb_adapter, reset_task);
5078
c97ec42a
TI		 5079 igb_dump(adapter);
5080 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5081 igb_reinit_locked(adapter);
5082}
5083
5084/**
b980ac18
JK		 5085 * igb_get_stats64 - Get System Network Statistics
5086 * @netdev: network interface device structure
5087 * @stats: rtnl_link_stats64 pointer
9d5c8243 5088 **/
12dcd86b 5089static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5090 struct rtnl_link_stats64 *stats)
9d5c8243 5091{
12dcd86b
ED		 5092 struct igb_adapter *adapter = netdev_priv(netdev);
5093
5094 spin_lock(&adapter->stats64_lock);
5095 igb_update_stats(adapter, &adapter->stats64);
5096 memcpy(stats, &adapter->stats64, sizeof(*stats));
5097 spin_unlock(&adapter->stats64_lock);
5098
5099 return stats;
9d5c8243
AK		 5100}
5101
5102/**
b980ac18
JK		 5103 * igb_change_mtu - Change the Maximum Transfer Unit
5104 * @netdev: network interface device structure
5105 * @new_mtu: new value for maximum frame size
9d5c8243 5106 *
b980ac18 5107 * Returns 0 on success, negative on failure
9d5c8243
AK		 5108 **/
5109static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5110{
5111 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5112 struct pci_dev *pdev = adapter->pdev;
153285f9 5113 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5114
c809d227 5115 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5116 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5117 return -EINVAL;
5118 }
5119
153285f9 5120#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5121 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5122 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5123 return -EINVAL;
5124 }
5125
2ccd994c
AD		 5126 /* adjust max frame to be at least the size of a standard frame */
5127 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5128 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5129
9d5c8243
AK		 5130 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5131 msleep(1);
73cd78f1 5132
9d5c8243
AK		 5133 /* igb_down has a dependency on max_frame_size */
5134 adapter->max_frame_size = max_frame;
559e9c49 5135
4c844851
AD		 5136 if (netif_running(netdev))
5137 igb_down(adapter);
9d5c8243 5138
090b1795 5139 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5140 netdev->mtu, new_mtu);
5141 netdev->mtu = new_mtu;
5142
5143 if (netif_running(netdev))
5144 igb_up(adapter);
5145 else
5146 igb_reset(adapter);
5147
5148 clear_bit(__IGB_RESETTING, &adapter->state);
5149
5150 return 0;
5151}
5152
5153/**
b980ac18
JK		 5154 * igb_update_stats - Update the board statistics counters
5155 * @adapter: board private structure
9d5c8243 5156 **/
12dcd86b
ED		 5157void igb_update_stats(struct igb_adapter *adapter,
5158 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5159{
5160 struct e1000_hw *hw = &adapter->hw;
5161 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5162 u32 reg, mpc;
9d5c8243 5163 u16 phy_tmp;
3f9c0164
AD		 5164 int i;
5165 u64 bytes, packets;
12dcd86b
ED		 5166 unsigned int start;
5167 u64 _bytes, _packets;
9d5c8243
AK		 5168
5169#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
5170
b980ac18 5171 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5172 * connection is down.
5173 */
5174 if (adapter->link_speed == 0)
5175 return;
5176 if (pci_channel_offline(pdev))
5177 return;
5178
3f9c0164
AD		 5179 bytes = 0;
5180 packets = 0;
7f90128e
AA		 5181
5182 rcu_read_lock();
3f9c0164 5183 for (i = 0; i < adapter->num_rx_queues; i++) {
ae1c07a6 5184 u32 rqdpc = rd32(E1000_RQDPC(i));
3025a446 5185 struct igb_ring *ring = adapter->rx_ring[i];
12dcd86b 5186
ae1c07a6
AD		 5187 if (rqdpc) {
5188 ring->rx_stats.drops += rqdpc;
5189 net_stats->rx_fifo_errors += rqdpc;
5190 }
12dcd86b
ED		 5191
5192 do {
57a7744e 5193 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5194 _bytes = ring->rx_stats.bytes;
5195 _packets = ring->rx_stats.packets;
57a7744e 5196 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5197 bytes += _bytes;
5198 packets += _packets;
3f9c0164
AD		 5199 }
5200
128e45eb
AD		 5201 net_stats->rx_bytes = bytes;
5202 net_stats->rx_packets = packets;
3f9c0164
AD		 5203
5204 bytes = 0;
5205 packets = 0;
5206 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5207 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5208 do {
57a7744e 5209 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5210 _bytes = ring->tx_stats.bytes;
5211 _packets = ring->tx_stats.packets;
57a7744e 5212 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5213 bytes += _bytes;
5214 packets += _packets;
3f9c0164 5215 }
128e45eb
AD		 5216 net_stats->tx_bytes = bytes;
5217 net_stats->tx_packets = packets;
7f90128e 5218 rcu_read_unlock();
3f9c0164
AD		 5219
5220 /* read stats registers */
9d5c8243
AK		 5221 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5222 adapter->stats.gprc += rd32(E1000_GPRC);
5223 adapter->stats.gorc += rd32(E1000_GORCL);
5224 rd32(E1000_GORCH); /* clear GORCL */
5225 adapter->stats.bprc += rd32(E1000_BPRC);
5226 adapter->stats.mprc += rd32(E1000_MPRC);
5227 adapter->stats.roc += rd32(E1000_ROC);
5228
5229 adapter->stats.prc64 += rd32(E1000_PRC64);
5230 adapter->stats.prc127 += rd32(E1000_PRC127);
5231 adapter->stats.prc255 += rd32(E1000_PRC255);
5232 adapter->stats.prc511 += rd32(E1000_PRC511);
5233 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5234 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5235 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5236 adapter->stats.sec += rd32(E1000_SEC);
5237
fa3d9a6d
MW		 5238 mpc = rd32(E1000_MPC);
5239 adapter->stats.mpc += mpc;
5240 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5241 adapter->stats.scc += rd32(E1000_SCC);
5242 adapter->stats.ecol += rd32(E1000_ECOL);
5243 adapter->stats.mcc += rd32(E1000_MCC);
5244 adapter->stats.latecol += rd32(E1000_LATECOL);
5245 adapter->stats.dc += rd32(E1000_DC);
5246 adapter->stats.rlec += rd32(E1000_RLEC);
5247 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5248 adapter->stats.xontxc += rd32(E1000_XONTXC);
5249 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5250 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5251 adapter->stats.fcruc += rd32(E1000_FCRUC);
5252 adapter->stats.gptc += rd32(E1000_GPTC);
5253 adapter->stats.gotc += rd32(E1000_GOTCL);
5254 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5255 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5256 adapter->stats.ruc += rd32(E1000_RUC);
5257 adapter->stats.rfc += rd32(E1000_RFC);
5258 adapter->stats.rjc += rd32(E1000_RJC);
5259 adapter->stats.tor += rd32(E1000_TORH);
5260 adapter->stats.tot += rd32(E1000_TOTH);
5261 adapter->stats.tpr += rd32(E1000_TPR);
5262
5263 adapter->stats.ptc64 += rd32(E1000_PTC64);
5264 adapter->stats.ptc127 += rd32(E1000_PTC127);
5265 adapter->stats.ptc255 += rd32(E1000_PTC255);
5266 adapter->stats.ptc511 += rd32(E1000_PTC511);
5267 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5268 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5269
5270 adapter->stats.mptc += rd32(E1000_MPTC);
5271 adapter->stats.bptc += rd32(E1000_BPTC);
5272
2d0b0f69
NN		 5273 adapter->stats.tpt += rd32(E1000_TPT);
5274 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5275
5276 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5277 /* read internal phy specific stats */
5278 reg = rd32(E1000_CTRL_EXT);
5279 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5280 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5281
5282 /* this stat has invalid values on i210/i211 */
5283 if ((hw->mac.type != e1000_i210) &&
5284 (hw->mac.type != e1000_i211))
5285 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5286 }
5287
9d5c8243
AK		 5288 adapter->stats.tsctc += rd32(E1000_TSCTC);
5289 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5290
5291 adapter->stats.iac += rd32(E1000_IAC);
5292 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5293 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5294 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5295 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5296 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5297 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5298 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5299 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5300
5301 /* Fill out the OS statistics structure */
128e45eb
AD		 5302 net_stats->multicast = adapter->stats.mprc;
5303 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5304
5305 /* Rx Errors */
5306
5307 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5308 * our own version based on RUC and ROC
5309 */
128e45eb 5310 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5311 adapter->stats.crcerrs + adapter->stats.algnerrc +
5312 adapter->stats.ruc + adapter->stats.roc +
5313 adapter->stats.cexterr;
128e45eb
AD		 5314 net_stats->rx_length_errors = adapter->stats.ruc +
5315 adapter->stats.roc;
5316 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5317 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5318 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5319
5320 /* Tx Errors */
128e45eb
AD		 5321 net_stats->tx_errors = adapter->stats.ecol +
5322 adapter->stats.latecol;
5323 net_stats->tx_aborted_errors = adapter->stats.ecol;
5324 net_stats->tx_window_errors = adapter->stats.latecol;
5325 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5326
5327 /* Tx Dropped needs to be maintained elsewhere */
5328
5329 /* Phy Stats */
5330 if (hw->phy.media_type == e1000_media_type_copper) {
5331 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5332 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5333 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5334 adapter->phy_stats.idle_errors += phy_tmp;
5335 }
5336 }
5337
5338 /* Management Stats */
5339 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5340 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5341 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5342
5343 /* OS2BMC Stats */
5344 reg = rd32(E1000_MANC);
5345 if (reg & E1000_MANC_EN_BMC2OS) {
5346 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5347 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5348 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5349 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5350 }
9d5c8243
AK		 5351}
5352
9d5c8243
AK		 5353static irqreturn_t igb_msix_other(int irq, void *data)
5354{
047e0030 5355 struct igb_adapter *adapter = data;
9d5c8243 5356 struct e1000_hw *hw = &adapter->hw;
844290e5 5357 u32 icr = rd32(E1000_ICR);
844290e5 5358 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5359
7f081d40
AD		 5360 if (icr & E1000_ICR_DRSTA)
5361 schedule_work(&adapter->reset_task);
5362
047e0030 5363 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5364 /* HW is reporting DMA is out of sync */
5365 adapter->stats.doosync++;
13800469
GR		 5366 /* The DMA Out of Sync is also indication of a spoof event
5367 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5368 * see if it is really a spoof event.
5369 */
13800469 5370 igb_check_wvbr(adapter);
dda0e083 5371 }
eebbbdba 5372
4ae196df
AD		 5373 /* Check for a mailbox event */
5374 if (icr & E1000_ICR_VMMB)
5375 igb_msg_task(adapter);
5376
5377 if (icr & E1000_ICR_LSC) {
5378 hw->mac.get_link_status = 1;
5379 /* guard against interrupt when we're going down */
5380 if (!test_bit(__IGB_DOWN, &adapter->state))
5381 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5382 }
5383
1f6e8178
MV		 5384 if (icr & E1000_ICR_TS) {
5385 u32 tsicr = rd32(E1000_TSICR);
5386
5387 if (tsicr & E1000_TSICR_TXTS) {
5388 /* acknowledge the interrupt */
5389 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5390 /* retrieve hardware timestamp */
5391 schedule_work(&adapter->ptp_tx_work);
5392 }
5393 }
1f6e8178 5394
844290e5 5395 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5396
5397 return IRQ_HANDLED;
5398}
5399
047e0030 5400static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5401{
26b39276 5402 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5403 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5404
047e0030
AD		 5405 if (!q_vector->set_itr)
5406 return;
73cd78f1 5407
047e0030
AD		 5408 if (!itr_val)
5409 itr_val = 0x4;
661086df 5410
26b39276
AD		 5411 if (adapter->hw.mac.type == e1000_82575)
5412 itr_val |= itr_val << 16;
661086df 5413 else
0ba82994 5414 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5415
047e0030
AD		 5416 writel(itr_val, q_vector->itr_register);
5417 q_vector->set_itr = 0;
6eb5a7f1
AD		 5418}
5419
047e0030 5420static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5421{
047e0030 5422 struct igb_q_vector *q_vector = data;
9d5c8243 5423
047e0030
AD		 5424 /* Write the ITR value calculated from the previous interrupt. */
5425 igb_write_itr(q_vector);
9d5c8243 5426
047e0030 5427 napi_schedule(&q_vector->napi);
844290e5 5428
047e0030 5429 return IRQ_HANDLED;
fe4506b6
JC		 5430}
5431
421e02f0 5432#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5433static void igb_update_tx_dca(struct igb_adapter *adapter,
5434 struct igb_ring *tx_ring,
5435 int cpu)
5436{
5437 struct e1000_hw *hw = &adapter->hw;
5438 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5439
5440 if (hw->mac.type != e1000_82575)
5441 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5442
b980ac18 5443 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5444 * DCA is enabled. This is due to a known issue in some chipsets
5445 * which will cause the DCA tag to be cleared.
5446 */
5447 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5448 E1000_DCA_TXCTRL_DATA_RRO_EN |
5449 E1000_DCA_TXCTRL_DESC_DCA_EN;
5450
5451 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5452}
5453
5454static void igb_update_rx_dca(struct igb_adapter *adapter,
5455 struct igb_ring *rx_ring,
5456 int cpu)
5457{
5458 struct e1000_hw *hw = &adapter->hw;
5459 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5460
5461 if (hw->mac.type != e1000_82575)
5462 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5463
b980ac18 5464 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5465 * DCA is enabled. This is due to a known issue in some chipsets
5466 * which will cause the DCA tag to be cleared.
5467 */
5468 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5469 E1000_DCA_RXCTRL_DESC_DCA_EN;
5470
5471 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5472}
5473
047e0030 5474static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5475{
047e0030 5476 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5477 int cpu = get_cpu();
fe4506b6 5478
047e0030
AD		 5479 if (q_vector->cpu == cpu)
5480 goto out_no_update;
5481
6a05004a
AD		 5482 if (q_vector->tx.ring)
5483 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5484
5485 if (q_vector->rx.ring)
5486 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5487
047e0030
AD		 5488 q_vector->cpu = cpu;
5489out_no_update:
fe4506b6
JC		 5490 put_cpu();
5491}
5492
5493static void igb_setup_dca(struct igb_adapter *adapter)
5494{
7e0e99ef 5495 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5496 int i;
5497
7dfc16fa 5498 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5499 return;
5500
7e0e99ef
AD		 5501 /* Always use CB2 mode, difference is masked in the CB driver. */
5502 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5503
047e0030 5504 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5505 adapter->q_vector[i]->cpu = -1;
5506 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5507 }
5508}
5509
5510static int __igb_notify_dca(struct device *dev, void *data)
5511{
5512 struct net_device *netdev = dev_get_drvdata(dev);
5513 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5514 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5515 struct e1000_hw *hw = &adapter->hw;
5516 unsigned long event = *(unsigned long *)data;
5517
5518 switch (event) {
5519 case DCA_PROVIDER_ADD:
5520 /* if already enabled, don't do it again */
7dfc16fa 5521 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5522 break;
fe4506b6 5523 if (dca_add_requester(dev) == 0) {
bbd98fe4 5524 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5525 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5526 igb_setup_dca(adapter);
5527 break;
5528 }
5529 /* Fall Through since DCA is disabled. */
5530 case DCA_PROVIDER_REMOVE:
7dfc16fa 5531 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5532 /* without this a class_device is left
b980ac18
JK		 5533 * hanging around in the sysfs model
5534 */
fe4506b6 5535 dca_remove_requester(dev);
090b1795 5536 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5537 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5538 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5539 }
5540 break;
5541 }
bbd98fe4 5542
fe4506b6 5543 return 0;
9d5c8243
AK		 5544}
5545
fe4506b6 5546static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5547 void *p)
fe4506b6
JC		 5548{
5549 int ret_val;
5550
5551 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5552 __igb_notify_dca);
fe4506b6
JC		 5553
5554 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5555}
421e02f0 5556#endif /* CONFIG_IGB_DCA */
9d5c8243 5557
0224d663
GR		 5558#ifdef CONFIG_PCI_IOV
5559static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5560{
5561 unsigned char mac_addr[ETH_ALEN];
0224d663 5562
5ac6f91d 5563 eth_zero_addr(mac_addr);
0224d663
GR		 5564 igb_set_vf_mac(adapter, vf, mac_addr);
5565
70ea4783
LL		 5566 /* By default spoof check is enabled for all VFs */
5567 adapter->vf_data[vf].spoofchk_enabled = true;
5568
f557147c 5569 return 0;
0224d663
GR		 5570}
5571
0224d663 5572#endif
4ae196df
AD		 5573static void igb_ping_all_vfs(struct igb_adapter *adapter)
5574{
5575 struct e1000_hw *hw = &adapter->hw;
5576 u32 ping;
5577 int i;
5578
5579 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5580 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5581 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5582 ping |= E1000_VT_MSGTYPE_CTS;
5583 igb_write_mbx(hw, &ping, 1, i);
5584 }
5585}
5586
7d5753f0
AD		 5587static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5588{
5589 struct e1000_hw *hw = &adapter->hw;
5590 u32 vmolr = rd32(E1000_VMOLR(vf));
5591 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5592
d85b9004 5593 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5594 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5595 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5596
5597 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5598 vmolr |= E1000_VMOLR_MPME;
d85b9004 5599 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5600 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5601 } else {
b980ac18 5602 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5603 * flag we need to write the hashes to the MTA as this step
5604 * was previously skipped
5605 */
5606 if (vf_data->num_vf_mc_hashes > 30) {
5607 vmolr |= E1000_VMOLR_MPME;
5608 } else if (vf_data->num_vf_mc_hashes) {
5609 int j;
5610 vmolr |= E1000_VMOLR_ROMPE;
5611 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5612 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5613 }
5614 }
5615
5616 wr32(E1000_VMOLR(vf), vmolr);
5617
5618 /* there are flags left unprocessed, likely not supported */
5619 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5620 return -EINVAL;
5621
5622 return 0;
7d5753f0
AD		 5623}
5624
4ae196df
AD		 5625static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5626 u32 *msgbuf, u32 vf)
5627{
5628 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5629 u16 *hash_list = (u16 *)&msgbuf[1];
5630 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5631 int i;
5632
7d5753f0 5633 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5634 * to this VF for later use to restore when the PF multi cast
5635 * list changes
5636 */
5637 vf_data->num_vf_mc_hashes = n;
5638
7d5753f0
AD		 5639 /* only up to 30 hash values supported */
5640 if (n > 30)
5641 n = 30;
5642
5643 /* store the hashes for later use */
4ae196df 5644 for (i = 0; i < n; i++)
a419aef8 5645 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5646
5647 /* Flush and reset the mta with the new values */
ff41f8dc 5648 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5649
5650 return 0;
5651}
5652
5653static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5654{
5655 struct e1000_hw *hw = &adapter->hw;
5656 struct vf_data_storage *vf_data;
5657 int i, j;
5658
5659 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0
AD		 5660 u32 vmolr = rd32(E1000_VMOLR(i));
5661 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5662
4ae196df 5663 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5664
5665 if ((vf_data->num_vf_mc_hashes > 30) ||
5666 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5667 vmolr |= E1000_VMOLR_MPME;
5668 } else if (vf_data->num_vf_mc_hashes) {
5669 vmolr |= E1000_VMOLR_ROMPE;
5670 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5671 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5672 }
5673 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5674 }
5675}
5676
5677static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5678{
5679 struct e1000_hw *hw = &adapter->hw;
5680 u32 pool_mask, reg, vid;
5681 int i;
5682
5683 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5684
5685 /* Find the vlan filter for this id */
5686 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5687 reg = rd32(E1000_VLVF(i));
5688
5689 /* remove the vf from the pool */
5690 reg &= ~pool_mask;
5691
5692 /* if pool is empty then remove entry from vfta */
5693 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5694 (reg & E1000_VLVF_VLANID_ENABLE)) {
5695 reg = 0;
5696 vid = reg & E1000_VLVF_VLANID_MASK;
5697 igb_vfta_set(hw, vid, false);
5698 }
5699
5700 wr32(E1000_VLVF(i), reg);
5701 }
ae641bdc
AD		 5702
5703 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5704}
5705
5706static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5707{
5708 struct e1000_hw *hw = &adapter->hw;
5709 u32 reg, i;
5710
51466239
AD		 5711 /* The vlvf table only exists on 82576 hardware and newer */
5712 if (hw->mac.type < e1000_82576)
5713 return -1;
5714
5715 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5716 if (!adapter->vfs_allocated_count)
5717 return -1;
5718
5719 /* Find the vlan filter for this id */
5720 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5721 reg = rd32(E1000_VLVF(i));
5722 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5723 vid == (reg & E1000_VLVF_VLANID_MASK))
5724 break;
5725 }
5726
5727 if (add) {
5728 if (i == E1000_VLVF_ARRAY_SIZE) {
5729 /* Did not find a matching VLAN ID entry that was
5730 * enabled. Search for a free filter entry, i.e.
5731 * one without the enable bit set
5732 */
5733 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5734 reg = rd32(E1000_VLVF(i));
5735 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5736 break;
5737 }
5738 }
5739 if (i < E1000_VLVF_ARRAY_SIZE) {
5740 /* Found an enabled/available entry */
5741 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5742
5743 /* if !enabled we need to set this up in vfta */
5744 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5745 /* add VID to filter table */
5746 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5747 reg |= E1000_VLVF_VLANID_ENABLE;
5748 }
cad6d05f
AD		 5749 reg &= ~E1000_VLVF_VLANID_MASK;
5750 reg |= vid;
4ae196df 5751 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5752
5753 /* do not modify RLPML for PF devices */
5754 if (vf >= adapter->vfs_allocated_count)
5755 return 0;
5756
5757 if (!adapter->vf_data[vf].vlans_enabled) {
5758 u32 size;
5759 reg = rd32(E1000_VMOLR(vf));
5760 size = reg & E1000_VMOLR_RLPML_MASK;
5761 size += 4;
5762 reg &= ~E1000_VMOLR_RLPML_MASK;
5763 reg |= size;
5764 wr32(E1000_VMOLR(vf), reg);
5765 }
ae641bdc 5766
51466239 5767 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5768 }
5769 } else {
5770 if (i < E1000_VLVF_ARRAY_SIZE) {
5771 /* remove vf from the pool */
5772 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5773 /* if pool is empty then remove entry from vfta */
5774 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5775 reg = 0;
5776 igb_vfta_set(hw, vid, false);
5777 }
5778 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5779
5780 /* do not modify RLPML for PF devices */
5781 if (vf >= adapter->vfs_allocated_count)
5782 return 0;
5783
5784 adapter->vf_data[vf].vlans_enabled--;
5785 if (!adapter->vf_data[vf].vlans_enabled) {
5786 u32 size;
5787 reg = rd32(E1000_VMOLR(vf));
5788 size = reg & E1000_VMOLR_RLPML_MASK;
5789 size -= 4;
5790 reg &= ~E1000_VMOLR_RLPML_MASK;
5791 reg |= size;
5792 wr32(E1000_VMOLR(vf), reg);
5793 }
4ae196df
AD		 5794 }
5795 }
8151d294
WM		 5796 return 0;
5797}
5798
5799static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5800{
5801 struct e1000_hw *hw = &adapter->hw;
5802
5803 if (vid)
5804 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5805 else
5806 wr32(E1000_VMVIR(vf), 0);
5807}
5808
5809static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5810 int vf, u16 vlan, u8 qos)
5811{
5812 int err = 0;
5813 struct igb_adapter *adapter = netdev_priv(netdev);
5814
5815 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5816 return -EINVAL;
5817 if (vlan || qos) {
5818 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5819 if (err)
5820 goto out;
5821 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5822 igb_set_vmolr(adapter, vf, !vlan);
5823 adapter->vf_data[vf].pf_vlan = vlan;
5824 adapter->vf_data[vf].pf_qos = qos;
5825 dev_info(&adapter->pdev->dev,
5826 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5827 if (test_bit(__IGB_DOWN, &adapter->state)) {
5828 dev_warn(&adapter->pdev->dev,
b980ac18 5829 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5830 dev_warn(&adapter->pdev->dev,
b980ac18 5831 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5832 }
5833 } else {
5834 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5835 false, vf);
8151d294
WM		 5836 igb_set_vmvir(adapter, vlan, vf);
5837 igb_set_vmolr(adapter, vf, true);
5838 adapter->vf_data[vf].pf_vlan = 0;
5839 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5840 }
8151d294 5841out:
b980ac18 5842 return err;
4ae196df
AD		 5843}
5844
6f3dc319
GR		 5845static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5846{
5847 struct e1000_hw *hw = &adapter->hw;
5848 int i;
5849 u32 reg;
5850
5851 /* Find the vlan filter for this id */
5852 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5853 reg = rd32(E1000_VLVF(i));
5854 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5855 vid == (reg & E1000_VLVF_VLANID_MASK))
5856 break;
5857 }
5858
5859 if (i >= E1000_VLVF_ARRAY_SIZE)
5860 i = -1;
5861
5862 return i;
5863}
5864
4ae196df
AD		 5865static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5866{
6f3dc319 5867 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5868 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5869 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5870 int err = 0;
4ae196df 5871
6f3dc319
GR		 5872 /* If in promiscuous mode we need to make sure the PF also has
5873 * the VLAN filter set.
5874 */
5875 if (add && (adapter->netdev->flags & IFF_PROMISC))
5876 err = igb_vlvf_set(adapter, vid, add,
5877 adapter->vfs_allocated_count);
5878 if (err)
5879 goto out;
5880
5881 err = igb_vlvf_set(adapter, vid, add, vf);
5882
5883 if (err)
5884 goto out;
5885
5886 /* Go through all the checks to see if the VLAN filter should
5887 * be wiped completely.
5888 */
5889 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5890 u32 vlvf, bits;
5891
5892 int regndx = igb_find_vlvf_entry(adapter, vid);
5893 if (regndx < 0)
5894 goto out;
5895 /* See if any other pools are set for this VLAN filter
5896 * entry other than the PF.
5897 */
5898 vlvf = bits = rd32(E1000_VLVF(regndx));
5899 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5900 adapter->vfs_allocated_count);
5901 /* If the filter was removed then ensure PF pool bit
5902 * is cleared if the PF only added itself to the pool
5903 * because the PF is in promiscuous mode.
5904 */
5905 if ((vlvf & VLAN_VID_MASK) == vid &&
5906 !test_bit(vid, adapter->active_vlans) &&
5907 !bits)
5908 igb_vlvf_set(adapter, vid, add,
5909 adapter->vfs_allocated_count);
5910 }
5911
5912out:
5913 return err;
4ae196df
AD		 5914}
5915
f2ca0dbe 5916static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5917{
8fa7e0f7
GR		 5918 /* clear flags - except flag that indicates PF has set the MAC */
5919 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5920 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5921
5922 /* reset offloads to defaults */
8151d294 5923 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5924
5925 /* reset vlans for device */
5926 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5927 if (adapter->vf_data[vf].pf_vlan)
5928 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5929 adapter->vf_data[vf].pf_vlan,
5930 adapter->vf_data[vf].pf_qos);
5931 else
5932 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5933
5934 /* reset multicast table array for vf */
5935 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5936
5937 /* Flush and reset the mta with the new values */
ff41f8dc 5938 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5939}
5940
f2ca0dbe
AD		 5941static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5942{
5943 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5944
5ac6f91d 5945 /* clear mac address as we were hotplug removed/added */
8151d294 5946 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5947 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5948
5949 /* process remaining reset events */
5950 igb_vf_reset(adapter, vf);
5951}
5952
5953static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5954{
5955 struct e1000_hw *hw = &adapter->hw;
5956 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5957 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5958 u32 reg, msgbuf[3];
5959 u8 *addr = (u8 *)(&msgbuf[1]);
5960
5961 /* process all the same items cleared in a function level reset */
f2ca0dbe 5962 igb_vf_reset(adapter, vf);
4ae196df
AD		 5963
5964 /* set vf mac address */
26ad9178 5965 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5966
5967 /* enable transmit and receive for vf */
5968 reg = rd32(E1000_VFTE);
5969 wr32(E1000_VFTE, reg | (1 << vf));
5970 reg = rd32(E1000_VFRE);
5971 wr32(E1000_VFRE, reg | (1 << vf));
5972
8fa7e0f7 5973 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5974
5975 /* reply to reset with ack and vf mac address */
5976 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5977 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5978 igb_write_mbx(hw, msgbuf, 3, vf);
5979}
5980
5981static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5982{
b980ac18 5983 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 5984 * starting at the second 32 bit word of the msg array
5985 */
f2ca0dbe
AD		 5986 unsigned char *addr = (char *)&msg[1];
5987 int err = -1;
4ae196df 5988
f2ca0dbe
AD		 5989 if (is_valid_ether_addr(addr))
5990 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 5991
f2ca0dbe 5992 return err;
4ae196df
AD		 5993}
5994
5995static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5996{
5997 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 5998 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 5999 u32 msg = E1000_VT_MSGTYPE_NACK;
6000
6001 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6002 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6003 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6004 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6005 vf_data->last_nack = jiffies;
4ae196df
AD		 6006 }
6007}
6008
f2ca0dbe 6009static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6010{
f2ca0dbe
AD		 6011 struct pci_dev *pdev = adapter->pdev;
6012 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6013 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6014 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6015 s32 retval;
6016
f2ca0dbe 6017 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6018
fef45f4c
AD		 6019 if (retval) {
6020 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6021 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6022 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6023 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6024 return;
6025 goto out;
6026 }
4ae196df
AD		 6027
6028 /* this is a message we already processed, do nothing */
6029 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6030 return;
4ae196df 6031
b980ac18 6032 /* until the vf completes a reset it should not be
4ae196df
AD		 6033 * allowed to start any configuration.
6034 */
4ae196df
AD		 6035 if (msgbuf[0] == E1000_VF_RESET) {
6036 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6037 return;
4ae196df
AD		 6038 }
6039
f2ca0dbe 6040 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6041 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6042 return;
6043 retval = -1;
6044 goto out;
4ae196df
AD		 6045 }
6046
6047 switch ((msgbuf[0] & 0xFFFF)) {
6048 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6049 retval = -EINVAL;
6050 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6051 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6052 else
6053 dev_warn(&pdev->dev,
b980ac18
JK		 6054 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6055 vf);
4ae196df 6056 break;
7d5753f0
AD		 6057 case E1000_VF_SET_PROMISC:
6058 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6059 break;
4ae196df
AD		 6060 case E1000_VF_SET_MULTICAST:
6061 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6062 break;
6063 case E1000_VF_SET_LPE:
6064 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6065 break;
6066 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6067 retval = -1;
6068 if (vf_data->pf_vlan)
6069 dev_warn(&pdev->dev,
b980ac18
JK		 6070 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6071 vf);
8151d294
WM		 6072 else
6073 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6074 break;
6075 default:
090b1795 6076 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6077 retval = -1;
6078 break;
6079 }
6080
fef45f4c
AD		 6081 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6082out:
4ae196df
AD		 6083 /* notify the VF of the results of what it sent us */
6084 if (retval)
6085 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6086 else
6087 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6088
4ae196df 6089 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6090}
4ae196df 6091
f2ca0dbe
AD		 6092static void igb_msg_task(struct igb_adapter *adapter)
6093{
6094 struct e1000_hw *hw = &adapter->hw;
6095 u32 vf;
6096
6097 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6098 /* process any reset requests */
6099 if (!igb_check_for_rst(hw, vf))
6100 igb_vf_reset_event(adapter, vf);
6101
6102 /* process any messages pending */
6103 if (!igb_check_for_msg(hw, vf))
6104 igb_rcv_msg_from_vf(adapter, vf);
6105
6106 /* process any acks */
6107 if (!igb_check_for_ack(hw, vf))
6108 igb_rcv_ack_from_vf(adapter, vf);
6109 }
4ae196df
AD		 6110}
6111
68d480c4
AD		 6112/**
6113 * igb_set_uta - Set unicast filter table address
6114 * @adapter: board private structure
6115 *
6116 * The unicast table address is a register array of 32-bit registers.
6117 * The table is meant to be used in a way similar to how the MTA is used
6118 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6119 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6120 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6121 **/
6122static void igb_set_uta(struct igb_adapter *adapter)
6123{
6124 struct e1000_hw *hw = &adapter->hw;
6125 int i;
6126
6127 /* The UTA table only exists on 82576 hardware and newer */
6128 if (hw->mac.type < e1000_82576)
6129 return;
6130
6131 /* we only need to do this if VMDq is enabled */
6132 if (!adapter->vfs_allocated_count)
6133 return;
6134
6135 for (i = 0; i < hw->mac.uta_reg_count; i++)
6136 array_wr32(E1000_UTA, i, ~0);
6137}
6138
9d5c8243 6139/**
b980ac18
JK		 6140 * igb_intr_msi - Interrupt Handler
6141 * @irq: interrupt number
6142 * @data: pointer to a network interface device structure
9d5c8243
AK		 6143 **/
6144static irqreturn_t igb_intr_msi(int irq, void *data)
6145{
047e0030
AD		 6146 struct igb_adapter *adapter = data;
6147 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6148 struct e1000_hw *hw = &adapter->hw;
6149 /* read ICR disables interrupts using IAM */
6150 u32 icr = rd32(E1000_ICR);
6151
047e0030 6152 igb_write_itr(q_vector);
9d5c8243 6153
7f081d40
AD		 6154 if (icr & E1000_ICR_DRSTA)
6155 schedule_work(&adapter->reset_task);
6156
047e0030 6157 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6158 /* HW is reporting DMA is out of sync */
6159 adapter->stats.doosync++;
6160 }
6161
9d5c8243
AK		 6162 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6163 hw->mac.get_link_status = 1;
6164 if (!test_bit(__IGB_DOWN, &adapter->state))
6165 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6166 }
6167
1f6e8178
MV		 6168 if (icr & E1000_ICR_TS) {
6169 u32 tsicr = rd32(E1000_TSICR);
6170
6171 if (tsicr & E1000_TSICR_TXTS) {
6172 /* acknowledge the interrupt */
6173 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6174 /* retrieve hardware timestamp */
6175 schedule_work(&adapter->ptp_tx_work);
6176 }
6177 }
1f6e8178 6178
047e0030 6179 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6180
6181 return IRQ_HANDLED;
6182}
6183
6184/**
b980ac18
JK		 6185 * igb_intr - Legacy Interrupt Handler
6186 * @irq: interrupt number
6187 * @data: pointer to a network interface device structure
9d5c8243
AK		 6188 **/
6189static irqreturn_t igb_intr(int irq, void *data)
6190{
047e0030
AD		 6191 struct igb_adapter *adapter = data;
6192 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6193 struct e1000_hw *hw = &adapter->hw;
6194 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6195 * need for the IMC write
6196 */
9d5c8243 6197 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6198
6199 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6200 * not set, then the adapter didn't send an interrupt
6201 */
9d5c8243
AK		 6202 if (!(icr & E1000_ICR_INT_ASSERTED))
6203 return IRQ_NONE;
6204
0ba82994
AD		 6205 igb_write_itr(q_vector);
6206
7f081d40
AD		 6207 if (icr & E1000_ICR_DRSTA)
6208 schedule_work(&adapter->reset_task);
6209
047e0030 6210 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6211 /* HW is reporting DMA is out of sync */
6212 adapter->stats.doosync++;
6213 }
6214
9d5c8243
AK		 6215 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6216 hw->mac.get_link_status = 1;
6217 /* guard against interrupt when we're going down */
6218 if (!test_bit(__IGB_DOWN, &adapter->state))
6219 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6220 }
6221
1f6e8178
MV		 6222 if (icr & E1000_ICR_TS) {
6223 u32 tsicr = rd32(E1000_TSICR);
6224
6225 if (tsicr & E1000_TSICR_TXTS) {
6226 /* acknowledge the interrupt */
6227 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6228 /* retrieve hardware timestamp */
6229 schedule_work(&adapter->ptp_tx_work);
6230 }
6231 }
1f6e8178 6232
047e0030 6233 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6234
6235 return IRQ_HANDLED;
6236}
6237
c50b52a0 6238static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6239{
047e0030 6240 struct igb_adapter *adapter = q_vector->adapter;
46544258 6241 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6242
0ba82994
AD		 6243 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6244 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6245 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6246 igb_set_itr(q_vector);
46544258 6247 else
047e0030 6248 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6249 }
6250
46544258 6251 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6252 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6253 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6254 else
6255 igb_irq_enable(adapter);
6256 }
9d5c8243
AK		 6257}
6258
46544258 6259/**
b980ac18
JK		 6260 * igb_poll - NAPI Rx polling callback
6261 * @napi: napi polling structure
6262 * @budget: count of how many packets we should handle
46544258
AD		 6263 **/
6264static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6265{
047e0030 6266 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6267 struct igb_q_vector,
6268 napi);
16eb8815 6269 bool clean_complete = true;
9d5c8243 6270
421e02f0 6271#ifdef CONFIG_IGB_DCA
047e0030
AD		 6272 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6273 igb_update_dca(q_vector);
fe4506b6 6274#endif
0ba82994 6275 if (q_vector->tx.ring)
13fde97a 6276 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6277
0ba82994 6278 if (q_vector->rx.ring)
cd392f5c 6279 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6280
16eb8815
AD		 6281 /* If all work not completed, return budget and keep polling */
6282 if (!clean_complete)
6283 return budget;
46544258 6284
9d5c8243 6285 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6286 napi_complete(napi);
6287 igb_ring_irq_enable(q_vector);
9d5c8243 6288
16eb8815 6289 return 0;
9d5c8243 6290}
6d8126f9 6291
9d5c8243 6292/**
b980ac18
JK		 6293 * igb_clean_tx_irq - Reclaim resources after transmit completes
6294 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6295 *
b980ac18 6296 * returns true if ring is completely cleaned
9d5c8243 6297 **/
047e0030 6298static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6299{
047e0030 6300 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6301 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6302 struct igb_tx_buffer *tx_buffer;
f4128785 6303 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6304 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6305 unsigned int budget = q_vector->tx.work_limit;
8542db05 6306 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6307
13fde97a
AD		 6308 if (test_bit(__IGB_DOWN, &adapter->state))
6309 return true;
0e014cb1 6310
06034649 6311 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6312 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6313 i -= tx_ring->count;
9d5c8243 6314
f4128785
AD		 6315 do {
6316 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6317
6318 /* if next_to_watch is not set then there is no work pending */
6319 if (!eop_desc)
6320 break;
13fde97a 6321
f4128785 6322 /* prevent any other reads prior to eop_desc */
70d289bc 6323 read_barrier_depends();
f4128785 6324
13fde97a
AD		 6325 /* if DD is not set pending work has not been completed */
6326 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6327 break;
6328
8542db05
AD		 6329 /* clear next_to_watch to prevent false hangs */
6330 tx_buffer->next_to_watch = NULL;
9d5c8243 6331
ebe42d16
AD		 6332 /* update the statistics for this packet */
6333 total_bytes += tx_buffer->bytecount;
6334 total_packets += tx_buffer->gso_segs;
13fde97a 6335
ebe42d16
AD		 6336 /* free the skb */
6337 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6338
ebe42d16
AD		 6339 /* unmap skb header data */
6340 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6341 dma_unmap_addr(tx_buffer, dma),
6342 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6343 DMA_TO_DEVICE);
6344
c9f14bf3
AD		 6345 /* clear tx_buffer data */
6346 tx_buffer->skb = NULL;
6347 dma_unmap_len_set(tx_buffer, len, 0);
6348
ebe42d16
AD		 6349 /* clear last DMA location and unmap remaining buffers */
6350 while (tx_desc != eop_desc) {
13fde97a
AD		 6351 tx_buffer++;
6352 tx_desc++;
9d5c8243 6353 i++;
8542db05
AD		 6354 if (unlikely(!i)) {
6355 i -= tx_ring->count;
06034649 6356 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6357 tx_desc = IGB_TX_DESC(tx_ring, 0);
6358 }
ebe42d16
AD		 6359
6360 /* unmap any remaining paged data */
c9f14bf3 6361 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6362 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6363 dma_unmap_addr(tx_buffer, dma),
6364 dma_unmap_len(tx_buffer, len),
ebe42d16 6365 DMA_TO_DEVICE);
c9f14bf3 6366 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6367 }
6368 }
6369
ebe42d16
AD		 6370 /* move us one more past the eop_desc for start of next pkt */
6371 tx_buffer++;
6372 tx_desc++;
6373 i++;
6374 if (unlikely(!i)) {
6375 i -= tx_ring->count;
6376 tx_buffer = tx_ring->tx_buffer_info;
6377 tx_desc = IGB_TX_DESC(tx_ring, 0);
6378 }
f4128785
AD		 6379
6380 /* issue prefetch for next Tx descriptor */
6381 prefetch(tx_desc);
6382
6383 /* update budget accounting */
6384 budget--;
6385 } while (likely(budget));
0e014cb1 6386
bdbc0631
ED		 6387 netdev_tx_completed_queue(txring_txq(tx_ring),
6388 total_packets, total_bytes);
8542db05 6389 i += tx_ring->count;
9d5c8243 6390 tx_ring->next_to_clean = i;
13fde97a
AD		 6391 u64_stats_update_begin(&tx_ring->tx_syncp);
6392 tx_ring->tx_stats.bytes += total_bytes;
6393 tx_ring->tx_stats.packets += total_packets;
6394 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6395 q_vector->tx.total_bytes += total_bytes;
6396 q_vector->tx.total_packets += total_packets;
9d5c8243 6397
6d095fa8 6398 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6399 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6400
9d5c8243 6401 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6402 * check with the clearing of time_stamp and movement of i
6403 */
6d095fa8 6404 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6405 if (tx_buffer->next_to_watch &&
8542db05 6406 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6407 (adapter->tx_timeout_factor * HZ)) &&
6408 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6409
9d5c8243 6410 /* detected Tx unit hang */
59d71989 6411 dev_err(tx_ring->dev,
9d5c8243 6412 "Detected Tx Unit Hang\n"
2d064c06 6413 " Tx Queue <%d>\n"
9d5c8243
AK		 6414 " TDH <%x>\n"
6415 " TDT <%x>\n"
6416 " next_to_use <%x>\n"
6417 " next_to_clean <%x>\n"
9d5c8243
AK		 6418 "buffer_info[next_to_clean]\n"
6419 " time_stamp <%lx>\n"
8542db05 6420 " next_to_watch <%p>\n"
9d5c8243
AK		 6421 " jiffies <%lx>\n"
6422 " desc.status <%x>\n",
2d064c06 6423 tx_ring->queue_index,
238ac817 6424 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6425 readl(tx_ring->tail),
9d5c8243
AK		 6426 tx_ring->next_to_use,
6427 tx_ring->next_to_clean,
8542db05 6428 tx_buffer->time_stamp,
f4128785 6429 tx_buffer->next_to_watch,
9d5c8243 6430 jiffies,
f4128785 6431 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6432 netif_stop_subqueue(tx_ring->netdev,
6433 tx_ring->queue_index);
6434
6435 /* we are about to reset, no point in enabling stuff */
6436 return true;
9d5c8243
AK		 6437 }
6438 }
13fde97a 6439
21ba6fe1 6440#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6441 if (unlikely(total_packets &&
b980ac18
JK		 6442 netif_carrier_ok(tx_ring->netdev) &&
6443 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6444 /* Make sure that anybody stopping the queue after this
6445 * sees the new next_to_clean.
6446 */
6447 smp_mb();
6448 if (__netif_subqueue_stopped(tx_ring->netdev,
6449 tx_ring->queue_index) &&
6450 !(test_bit(__IGB_DOWN, &adapter->state))) {
6451 netif_wake_subqueue(tx_ring->netdev,
6452 tx_ring->queue_index);
6453
6454 u64_stats_update_begin(&tx_ring->tx_syncp);
6455 tx_ring->tx_stats.restart_queue++;
6456 u64_stats_update_end(&tx_ring->tx_syncp);
6457 }
6458 }
6459
6460 return !!budget;
9d5c8243
AK		 6461}
6462
cbc8e55f 6463/**
b980ac18
JK		 6464 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6465 * @rx_ring: rx descriptor ring to store buffers on
6466 * @old_buff: donor buffer to have page reused
cbc8e55f 6467 *
b980ac18 6468 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6469 **/
6470static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6471 struct igb_rx_buffer *old_buff)
6472{
6473 struct igb_rx_buffer *new_buff;
6474 u16 nta = rx_ring->next_to_alloc;
6475
6476 new_buff = &rx_ring->rx_buffer_info[nta];
6477
6478 /* update, and store next to alloc */
6479 nta++;
6480 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6481
6482 /* transfer page from old buffer to new buffer */
6483 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6484
6485 /* sync the buffer for use by the device */
6486 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6487 old_buff->page_offset,
de78d1f9 6488 IGB_RX_BUFSZ,
cbc8e55f
AD		 6489 DMA_FROM_DEVICE);
6490}
6491
74e238ea
AD		 6492static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6493 struct page *page,
6494 unsigned int truesize)
6495{
6496 /* avoid re-using remote pages */
6497 if (unlikely(page_to_nid(page) != numa_node_id()))
6498 return false;
6499
6500#if (PAGE_SIZE < 8192)
6501 /* if we are only owner of page we can reuse it */
6502 if (unlikely(page_count(page) != 1))
6503 return false;
6504
6505 /* flip page offset to other buffer */
6506 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6507
6508 /* since we are the only owner of the page and we need to
6509 * increment it, just set the value to 2 in order to avoid
6510 * an unnecessary locked operation
6511 */
6512 atomic_set(&page->_count, 2);
6513#else
6514 /* move offset up to the next cache line */
6515 rx_buffer->page_offset += truesize;
6516
6517 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6518 return false;
6519
6520 /* bump ref count on page before it is given to the stack */
6521 get_page(page);
6522#endif
6523
6524 return true;
6525}
6526
cbc8e55f 6527/**
b980ac18
JK		 6528 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6529 * @rx_ring: rx descriptor ring to transact packets on
6530 * @rx_buffer: buffer containing page to add
6531 * @rx_desc: descriptor containing length of buffer written by hardware
6532 * @skb: sk_buff to place the data into
cbc8e55f 6533 *
b980ac18
JK		 6534 * This function will add the data contained in rx_buffer->page to the skb.
6535 * This is done either through a direct copy if the data in the buffer is
6536 * less than the skb header size, otherwise it will just attach the page as
6537 * a frag to the skb.
cbc8e55f 6538 *
b980ac18
JK		 6539 * The function will then update the page offset if necessary and return
6540 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6541 **/
6542static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6543 struct igb_rx_buffer *rx_buffer,
6544 union e1000_adv_rx_desc *rx_desc,
6545 struct sk_buff *skb)
6546{
6547 struct page *page = rx_buffer->page;
6548 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6549#if (PAGE_SIZE < 8192)
6550 unsigned int truesize = IGB_RX_BUFSZ;
6551#else
6552 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6553#endif
cbc8e55f
AD		 6554
6555 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6556 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6557
cbc8e55f
AD		 6558 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6559 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6560 va += IGB_TS_HDR_LEN;
6561 size -= IGB_TS_HDR_LEN;
6562 }
6563
cbc8e55f
AD		 6564 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6565
6566 /* we can reuse buffer as-is, just make sure it is local */
6567 if (likely(page_to_nid(page) == numa_node_id()))
6568 return true;
6569
6570 /* this page cannot be reused so discard it */
6571 put_page(page);
6572 return false;
6573 }
6574
6575 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6576 rx_buffer->page_offset, size, truesize);
cbc8e55f 6577
74e238ea
AD		 6578 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6579}
cbc8e55f 6580
2e334eee
AD		 6581static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6582 union e1000_adv_rx_desc *rx_desc,
6583 struct sk_buff *skb)
6584{
6585 struct igb_rx_buffer *rx_buffer;
6586 struct page *page;
6587
6588 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6589
2e334eee
AD		 6590 page = rx_buffer->page;
6591 prefetchw(page);
6592
6593 if (likely(!skb)) {
6594 void *page_addr = page_address(page) +
6595 rx_buffer->page_offset;
6596
6597 /* prefetch first cache line of first page */
6598 prefetch(page_addr);
6599#if L1_CACHE_BYTES < 128
6600 prefetch(page_addr + L1_CACHE_BYTES);
6601#endif
6602
6603 /* allocate a skb to store the frags */
6604 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6605 IGB_RX_HDR_LEN);
6606 if (unlikely(!skb)) {
6607 rx_ring->rx_stats.alloc_failed++;
6608 return NULL;
6609 }
6610
b980ac18 6611 /* we will be copying header into skb->data in
2e334eee
AD		 6612 * pskb_may_pull so it is in our interest to prefetch
6613 * it now to avoid a possible cache miss
6614 */
6615 prefetchw(skb->data);
6616 }
6617
6618 /* we are reusing so sync this buffer for CPU use */
6619 dma_sync_single_range_for_cpu(rx_ring->dev,
6620 rx_buffer->dma,
6621 rx_buffer->page_offset,
de78d1f9 6622 IGB_RX_BUFSZ,
2e334eee
AD		 6623 DMA_FROM_DEVICE);
6624
6625 /* pull page into skb */
6626 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6627 /* hand second half of page back to the ring */
6628 igb_reuse_rx_page(rx_ring, rx_buffer);
6629 } else {
6630 /* we are not reusing the buffer so unmap it */
6631 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6632 PAGE_SIZE, DMA_FROM_DEVICE);
6633 }
6634
6635 /* clear contents of rx_buffer */
6636 rx_buffer->page = NULL;
6637
6638 return skb;
6639}
6640
cd392f5c 6641static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6642 union e1000_adv_rx_desc *rx_desc,
6643 struct sk_buff *skb)
9d5c8243 6644{
bc8acf2c 6645 skb_checksum_none_assert(skb);
9d5c8243 6646
294e7d78 6647 /* Ignore Checksum bit is set */
3ceb90fd 6648 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6649 return;
6650
6651 /* Rx checksum disabled via ethtool */
6652 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6653 return;
85ad76b2 6654
9d5c8243 6655 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6656 if (igb_test_staterr(rx_desc,
6657 E1000_RXDEXT_STATERR_TCPE |
6658 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6659 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6660 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6661 * packets, (aka let the stack check the crc32c)
6662 */
866cff06
AD		 6663 if (!((skb->len == 60) &&
6664 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6665 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6666 ring->rx_stats.csum_err++;
12dcd86b
ED		 6667 u64_stats_update_end(&ring->rx_syncp);
6668 }
9d5c8243 6669 /* let the stack verify checksum errors */
9d5c8243
AK		 6670 return;
6671 }
6672 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6673 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6674 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6675 skb->ip_summed = CHECKSUM_UNNECESSARY;
6676
3ceb90fd
AD		 6677 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6678 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6679}
6680
077887c3
AD		 6681static inline void igb_rx_hash(struct igb_ring *ring,
6682 union e1000_adv_rx_desc *rx_desc,
6683 struct sk_buff *skb)
6684{
6685 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6686 skb_set_hash(skb,
6687 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6688 PKT_HASH_TYPE_L3);
077887c3
AD		 6689}
6690
2e334eee 6691/**
b980ac18
JK		 6692 * igb_is_non_eop - process handling of non-EOP buffers
6693 * @rx_ring: Rx ring being processed
6694 * @rx_desc: Rx descriptor for current buffer
6695 * @skb: current socket buffer containing buffer in progress
2e334eee 6696 *
b980ac18
JK		 6697 * This function updates next to clean. If the buffer is an EOP buffer
6698 * this function exits returning false, otherwise it will place the
6699 * sk_buff in the next buffer to be chained and return true indicating
6700 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6701 **/
6702static bool igb_is_non_eop(struct igb_ring *rx_ring,
6703 union e1000_adv_rx_desc *rx_desc)
6704{
6705 u32 ntc = rx_ring->next_to_clean + 1;
6706
6707 /* fetch, update, and store next to clean */
6708 ntc = (ntc < rx_ring->count) ? ntc : 0;
6709 rx_ring->next_to_clean = ntc;
6710
6711 prefetch(IGB_RX_DESC(rx_ring, ntc));
6712
6713 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6714 return false;
6715
6716 return true;
6717}
6718
1a1c225b 6719/**
b980ac18
JK		 6720 * igb_get_headlen - determine size of header for LRO/GRO
6721 * @data: pointer to the start of the headers
6722 * @max_len: total length of section to find headers in
1a1c225b 6723 *
b980ac18
JK		 6724 * This function is meant to determine the length of headers that will
6725 * be recognized by hardware for LRO, and GRO offloads. The main
6726 * motivation of doing this is to only perform one pull for IPv4 TCP
6727 * packets so that we can do basic things like calculating the gso_size
6728 * based on the average data per packet.
1a1c225b
AD		 6729 **/
6730static unsigned int igb_get_headlen(unsigned char *data,
6731 unsigned int max_len)
6732{
6733 union {
6734 unsigned char *network;
6735 /* l2 headers */
6736 struct ethhdr *eth;
6737 struct vlan_hdr *vlan;
6738 /* l3 headers */
6739 struct iphdr *ipv4;
6740 struct ipv6hdr *ipv6;
6741 } hdr;
6742 __be16 protocol;
6743 u8 nexthdr = 0; /* default to not TCP */
6744 u8 hlen;
6745
6746 /* this should never happen, but better safe than sorry */
6747 if (max_len < ETH_HLEN)
6748 return max_len;
6749
6750 /* initialize network frame pointer */
6751 hdr.network = data;
6752
6753 /* set first protocol and move network header forward */
6754 protocol = hdr.eth->h_proto;
6755 hdr.network += ETH_HLEN;
6756
6757 /* handle any vlan tag if present */
7c4d16ff 6758 if (protocol == htons(ETH_P_8021Q)) {
1a1c225b
AD		 6759 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6760 return max_len;
6761
6762 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6763 hdr.network += VLAN_HLEN;
6764 }
6765
6766 /* handle L3 protocols */
7c4d16ff 6767 if (protocol == htons(ETH_P_IP)) {
1a1c225b
AD		 6768 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6769 return max_len;
6770
6771 /* access ihl as a u8 to avoid unaligned access on ia64 */
6772 hlen = (hdr.network[0] & 0x0F) << 2;
6773
6774 /* verify hlen meets minimum size requirements */
6775 if (hlen < sizeof(struct iphdr))
6776 return hdr.network - data;
6777
f2fb4ab2 6778 /* record next protocol if header is present */
b9555f66 6779 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6780 nexthdr = hdr.ipv4->protocol;
7c4d16ff 6781 } else if (protocol == htons(ETH_P_IPV6)) {
1a1c225b
AD		 6782 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6783 return max_len;
6784
6785 /* record next protocol */
6786 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6787 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6788 } else {
6789 return hdr.network - data;
6790 }
6791
f2fb4ab2
AD		 6792 /* relocate pointer to start of L4 header */
6793 hdr.network += hlen;
6794
1a1c225b
AD		 6795 /* finally sort out TCP */
6796 if (nexthdr == IPPROTO_TCP) {
6797 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6798 return max_len;
6799
6800 /* access doff as a u8 to avoid unaligned access on ia64 */
6801 hlen = (hdr.network[12] & 0xF0) >> 2;
6802
6803 /* verify hlen meets minimum size requirements */
6804 if (hlen < sizeof(struct tcphdr))
6805 return hdr.network - data;
6806
6807 hdr.network += hlen;
6808 } else if (nexthdr == IPPROTO_UDP) {
6809 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6810 return max_len;
6811
6812 hdr.network += sizeof(struct udphdr);
6813 }
6814
b980ac18 6815 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6816 * data section of the packet and will be the end of the header.
6817 * If not then it probably represents the end of the last recognized
6818 * header.
6819 */
6820 if ((hdr.network - data) < max_len)
6821 return hdr.network - data;
6822 else
6823 return max_len;
6824}
6825
6826/**
b980ac18
JK		 6827 * igb_pull_tail - igb specific version of skb_pull_tail
6828 * @rx_ring: rx descriptor ring packet is being transacted on
6829 * @rx_desc: pointer to the EOP Rx descriptor
6830 * @skb: pointer to current skb being adjusted
1a1c225b 6831 *
b980ac18
JK		 6832 * This function is an igb specific version of __pskb_pull_tail. The
6833 * main difference between this version and the original function is that
6834 * this function can make several assumptions about the state of things
6835 * that allow for significant optimizations versus the standard function.
6836 * As a result we can do things like drop a frag and maintain an accurate
6837 * truesize for the skb.
1a1c225b
AD		 6838 */
6839static void igb_pull_tail(struct igb_ring *rx_ring,
6840 union e1000_adv_rx_desc *rx_desc,
6841 struct sk_buff *skb)
2d94d8ab 6842{
1a1c225b
AD		 6843 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6844 unsigned char *va;
6845 unsigned int pull_len;
6846
b980ac18 6847 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6848 * working with pages allocated out of the lomem pool per
6849 * alloc_page(GFP_ATOMIC)
2d94d8ab 6850 */
1a1c225b
AD		 6851 va = skb_frag_address(frag);
6852
1a1c225b
AD		 6853 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6854 /* retrieve timestamp from buffer */
6855 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6856
6857 /* update pointers to remove timestamp header */
6858 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6859 frag->page_offset += IGB_TS_HDR_LEN;
6860 skb->data_len -= IGB_TS_HDR_LEN;
6861 skb->len -= IGB_TS_HDR_LEN;
6862
6863 /* move va to start of packet data */
6864 va += IGB_TS_HDR_LEN;
6865 }
6866
b980ac18 6867 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6868 * 60 bytes if the skb->len is less than 60 for skb_pad.
6869 */
6870 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6871
6872 /* align pull length to size of long to optimize memcpy performance */
6873 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6874
6875 /* update all of the pointers */
6876 skb_frag_size_sub(frag, pull_len);
6877 frag->page_offset += pull_len;
6878 skb->data_len -= pull_len;
6879 skb->tail += pull_len;
6880}
6881
6882/**
b980ac18
JK		 6883 * igb_cleanup_headers - Correct corrupted or empty headers
6884 * @rx_ring: rx descriptor ring packet is being transacted on
6885 * @rx_desc: pointer to the EOP Rx descriptor
6886 * @skb: pointer to current skb being fixed
1a1c225b 6887 *
b980ac18
JK		 6888 * Address the case where we are pulling data in on pages only
6889 * and as such no data is present in the skb header.
1a1c225b 6890 *
b980ac18
JK		 6891 * In addition if skb is not at least 60 bytes we need to pad it so that
6892 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6893 *
b980ac18 6894 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6895 **/
6896static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6897 union e1000_adv_rx_desc *rx_desc,
6898 struct sk_buff *skb)
6899{
1a1c225b
AD		 6900 if (unlikely((igb_test_staterr(rx_desc,
6901 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6902 struct net_device *netdev = rx_ring->netdev;
6903 if (!(netdev->features & NETIF_F_RXALL)) {
6904 dev_kfree_skb_any(skb);
6905 return true;
6906 }
6907 }
6908
6909 /* place header in linear portion of buffer */
6910 if (skb_is_nonlinear(skb))
6911 igb_pull_tail(rx_ring, rx_desc, skb);
6912
6913 /* if skb_pad returns an error the skb was freed */
6914 if (unlikely(skb->len < 60)) {
6915 int pad_len = 60 - skb->len;
6916
6917 if (skb_pad(skb, pad_len))
6918 return true;
6919 __skb_put(skb, pad_len);
6920 }
6921
6922 return false;
2d94d8ab
AD		 6923}
6924
db2ee5bd 6925/**
b980ac18
JK		 6926 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6927 * @rx_ring: rx descriptor ring packet is being transacted on
6928 * @rx_desc: pointer to the EOP Rx descriptor
6929 * @skb: pointer to current skb being populated
db2ee5bd 6930 *
b980ac18
JK		 6931 * This function checks the ring, descriptor, and packet information in
6932 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6933 * other fields within the skb.
db2ee5bd
AD		 6934 **/
6935static void igb_process_skb_fields(struct igb_ring *rx_ring,
6936 union e1000_adv_rx_desc *rx_desc,
6937 struct sk_buff *skb)
6938{
6939 struct net_device *dev = rx_ring->netdev;
6940
6941 igb_rx_hash(rx_ring, rx_desc, skb);
6942
6943 igb_rx_checksum(rx_ring, rx_desc, skb);
6944
5499a968
JK		 6945 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6946 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6947 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6948
f646968f 6949 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6950 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6951 u16 vid;
6952 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6953 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6954 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6955 else
6956 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6957
86a9bad3 6958 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6959 }
6960
6961 skb_record_rx_queue(skb, rx_ring->queue_index);
6962
6963 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6964}
6965
2e334eee 6966static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6967{
0ba82994 6968 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6969 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6970 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6971 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6972
57ba34c9 6973 while (likely(total_packets < budget)) {
2e334eee 6974 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6975
2e334eee
AD		 6976 /* return some buffers to hardware, one at a time is too slow */
6977 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6978 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6979 cleaned_count = 0;
6980 }
bf36c1a0 6981
2e334eee 6982 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6983
2e334eee
AD		 6984 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6985 break;
9d5c8243 6986
74e238ea
AD		 6987 /* This memory barrier is needed to keep us from reading
6988 * any other fields out of the rx_desc until we know the
6989 * RXD_STAT_DD bit is set
6990 */
6991 rmb();
6992
2e334eee 6993 /* retrieve a buffer from the ring */
f9d40f6a 6994 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6995
2e334eee
AD		 6996 /* exit if we failed to retrieve a buffer */
6997 if (!skb)
6998 break;
1a1c225b 6999
2e334eee 7000 cleaned_count++;
1a1c225b 7001
2e334eee
AD		 7002 /* fetch next buffer in frame if non-eop */
7003 if (igb_is_non_eop(rx_ring, rx_desc))
7004 continue;
1a1c225b
AD		 7005
7006 /* verify the packet layout is correct */
7007 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7008 skb = NULL;
7009 continue;
9d5c8243 7010 }
9d5c8243 7011
db2ee5bd 7012 /* probably a little skewed due to removing CRC */
3ceb90fd 7013 total_bytes += skb->len;
3ceb90fd 7014
db2ee5bd
AD		 7015 /* populate checksum, timestamp, VLAN, and protocol */
7016 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7017
b2cb09b1 7018 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7019
1a1c225b
AD		 7020 /* reset skb pointer */
7021 skb = NULL;
7022
2e334eee
AD		 7023 /* update budget accounting */
7024 total_packets++;
57ba34c9 7025 }
bf36c1a0 7026
1a1c225b
AD		 7027 /* place incomplete frames back on ring for completion */
7028 rx_ring->skb = skb;
7029
12dcd86b 7030 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7031 rx_ring->rx_stats.packets += total_packets;
7032 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7033 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7034 q_vector->rx.total_packets += total_packets;
7035 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7036
7037 if (cleaned_count)
cd392f5c 7038 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7039
2e334eee 7040 return (total_packets < budget);
9d5c8243
AK		 7041}
7042
c023cd88 7043static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7044 struct igb_rx_buffer *bi)
c023cd88
AD		 7045{
7046 struct page *page = bi->page;
cbc8e55f 7047 dma_addr_t dma;
c023cd88 7048
cbc8e55f
AD		 7049 /* since we are recycling buffers we should seldom need to alloc */
7050 if (likely(page))
c023cd88
AD		 7051 return true;
7052
cbc8e55f
AD		 7053 /* alloc new page for storage */
7054 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
7055 if (unlikely(!page)) {
7056 rx_ring->rx_stats.alloc_failed++;
7057 return false;
c023cd88
AD		 7058 }
7059
cbc8e55f
AD		 7060 /* map page for use */
7061 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7062
b980ac18 7063 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7064 * there isn't much point in holding memory we can't use
7065 */
1a1c225b 7066 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7067 __free_page(page);
7068
c023cd88
AD		 7069 rx_ring->rx_stats.alloc_failed++;
7070 return false;
7071 }
7072
1a1c225b 7073 bi->dma = dma;
cbc8e55f
AD		 7074 bi->page = page;
7075 bi->page_offset = 0;
1a1c225b 7076
c023cd88
AD		 7077 return true;
7078}
7079
9d5c8243 7080/**
b980ac18
JK		 7081 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7082 * @adapter: address of board private structure
9d5c8243 7083 **/
cd392f5c 7084void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7085{
9d5c8243 7086 union e1000_adv_rx_desc *rx_desc;
06034649 7087 struct igb_rx_buffer *bi;
c023cd88 7088 u16 i = rx_ring->next_to_use;
9d5c8243 7089
cbc8e55f
AD		 7090 /* nothing to do */
7091 if (!cleaned_count)
7092 return;
7093
60136906 7094 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7095 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7096 i -= rx_ring->count;
9d5c8243 7097
cbc8e55f 7098 do {
1a1c225b 7099 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7100 break;
9d5c8243 7101
b980ac18 7102 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7103 * because each write-back erases this info.
7104 */
f9d40f6a 7105 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7106
c023cd88
AD		 7107 rx_desc++;
7108 bi++;
9d5c8243 7109 i++;
c023cd88 7110 if (unlikely(!i)) {
60136906 7111 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7112 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7113 i -= rx_ring->count;
7114 }
7115
7116 /* clear the hdr_addr for the next_to_use descriptor */
7117 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7118
7119 cleaned_count--;
7120 } while (cleaned_count);
9d5c8243 7121
c023cd88
AD		 7122 i += rx_ring->count;
7123
9d5c8243 7124 if (rx_ring->next_to_use != i) {
cbc8e55f 7125 /* record the next descriptor to use */
9d5c8243 7126 rx_ring->next_to_use = i;
9d5c8243 7127
cbc8e55f
AD		 7128 /* update next to alloc since we have filled the ring */
7129 rx_ring->next_to_alloc = i;
7130
b980ac18 7131 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7132 * know there are new descriptors to fetch. (Only
7133 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7134 * such as IA-64).
7135 */
9d5c8243 7136 wmb();
fce99e34 7137 writel(i, rx_ring->tail);
9d5c8243
AK		 7138 }
7139}
7140
7141/**
7142 * igb_mii_ioctl -
7143 * @netdev:
7144 * @ifreq:
7145 * @cmd:
7146 **/
7147static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7148{
7149 struct igb_adapter *adapter = netdev_priv(netdev);
7150 struct mii_ioctl_data *data = if_mii(ifr);
7151
7152 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7153 return -EOPNOTSUPP;
7154
7155 switch (cmd) {
7156 case SIOCGMIIPHY:
7157 data->phy_id = adapter->hw.phy.addr;
7158 break;
7159 case SIOCGMIIREG:
f5f4cf08
AD		 7160 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
7161 &data->val_out))
9d5c8243
AK		 7162 return -EIO;
7163 break;
7164 case SIOCSMIIREG:
7165 default:
7166 return -EOPNOTSUPP;
7167 }
7168 return 0;
7169}
7170
7171/**
7172 * igb_ioctl -
7173 * @netdev:
7174 * @ifreq:
7175 * @cmd:
7176 **/
7177static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7178{
7179 switch (cmd) {
7180 case SIOCGMIIPHY:
7181 case SIOCGMIIREG:
7182 case SIOCSMIIREG:
7183 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7184 case SIOCGHWTSTAMP:
7185 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7186 case SIOCSHWTSTAMP:
6ab5f7b2 7187 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7188 default:
7189 return -EOPNOTSUPP;
7190 }
7191}
7192
009bc06e
AD		 7193s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7194{
7195 struct igb_adapter *adapter = hw->back;
009bc06e 7196
23d028cc 7197 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7198 return -E1000_ERR_CONFIG;
7199
009bc06e
AD		 7200 return 0;
7201}
7202
7203s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7204{
7205 struct igb_adapter *adapter = hw->back;
009bc06e 7206
23d028cc 7207 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7208 return -E1000_ERR_CONFIG;
7209
009bc06e
AD		 7210 return 0;
7211}
7212
c8f44aff 7213static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7214{
7215 struct igb_adapter *adapter = netdev_priv(netdev);
7216 struct e1000_hw *hw = &adapter->hw;
7217 u32 ctrl, rctl;
f646968f 7218 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7219
5faf030c 7220 if (enable) {
9d5c8243
AK		 7221 /* enable VLAN tag insert/strip */
7222 ctrl = rd32(E1000_CTRL);
7223 ctrl |= E1000_CTRL_VME;
7224 wr32(E1000_CTRL, ctrl);
7225
51466239 7226 /* Disable CFI check */
9d5c8243 7227 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7228 rctl &= ~E1000_RCTL_CFIEN;
7229 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7230 } else {
7231 /* disable VLAN tag insert/strip */
7232 ctrl = rd32(E1000_CTRL);
7233 ctrl &= ~E1000_CTRL_VME;
7234 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7235 }
7236
e1739522 7237 igb_rlpml_set(adapter);
9d5c8243
AK		 7238}
7239
80d5c368
PM		 7240static int igb_vlan_rx_add_vid(struct net_device *netdev,
7241 __be16 proto, u16 vid)
9d5c8243
AK		 7242{
7243 struct igb_adapter *adapter = netdev_priv(netdev);
7244 struct e1000_hw *hw = &adapter->hw;
4ae196df 7245 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7246
51466239
AD		 7247 /* attempt to add filter to vlvf array */
7248 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7249
51466239
AD		 7250 /* add the filter since PF can receive vlans w/o entry in vlvf */
7251 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7252
7253 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7254
7255 return 0;
9d5c8243
AK		 7256}
7257
80d5c368
PM		 7258static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7259 __be16 proto, u16 vid)
9d5c8243
AK		 7260{
7261 struct igb_adapter *adapter = netdev_priv(netdev);
7262 struct e1000_hw *hw = &adapter->hw;
4ae196df 7263 int pf_id = adapter->vfs_allocated_count;
51466239 7264 s32 err;
9d5c8243 7265
51466239
AD		 7266 /* remove vlan from VLVF table array */
7267 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7268
51466239
AD		 7269 /* if vid was not present in VLVF just remove it from table */
7270 if (err)
4ae196df 7271 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7272
7273 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7274
7275 return 0;
9d5c8243
AK		 7276}
7277
7278static void igb_restore_vlan(struct igb_adapter *adapter)
7279{
b2cb09b1 7280 u16 vid;
9d5c8243 7281
5faf030c
AD		 7282 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7283
b2cb09b1 7284 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7285 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7286}
7287
14ad2513 7288int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7289{
090b1795 7290 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7291 struct e1000_mac_info *mac = &adapter->hw.mac;
7292
7293 mac->autoneg = 0;
7294
14ad2513 7295 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7296 * for the switch() below to work
7297 */
14ad2513
DD		 7298 if ((spd & 1) || (dplx & ~1))
7299 goto err_inval;
7300
f502ef7d
AA		 7301 /* Fiber NIC's only allow 1000 gbps Full duplex
7302 * and 100Mbps Full duplex for 100baseFx sfp
7303 */
7304 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7305 switch (spd + dplx) {
7306 case SPEED_10 + DUPLEX_HALF:
7307 case SPEED_10 + DUPLEX_FULL:
7308 case SPEED_100 + DUPLEX_HALF:
7309 goto err_inval;
7310 default:
7311 break;
7312 }
7313 }
cd2638a8 7314
14ad2513 7315 switch (spd + dplx) {
9d5c8243
AK		 7316 case SPEED_10 + DUPLEX_HALF:
7317 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7318 break;
7319 case SPEED_10 + DUPLEX_FULL:
7320 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7321 break;
7322 case SPEED_100 + DUPLEX_HALF:
7323 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7324 break;
7325 case SPEED_100 + DUPLEX_FULL:
7326 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7327 break;
7328 case SPEED_1000 + DUPLEX_FULL:
7329 mac->autoneg = 1;
7330 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7331 break;
7332 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7333 default:
14ad2513 7334 goto err_inval;
9d5c8243 7335 }
8376dad0
JB		 7336
7337 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7338 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7339
9d5c8243 7340 return 0;
14ad2513
DD		 7341
7342err_inval:
7343 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7344 return -EINVAL;
9d5c8243
AK		 7345}
7346
749ab2cd
YZ		 7347static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7348 bool runtime)
9d5c8243
AK		 7349{
7350 struct net_device *netdev = pci_get_drvdata(pdev);
7351 struct igb_adapter *adapter = netdev_priv(netdev);
7352 struct e1000_hw *hw = &adapter->hw;
2d064c06 7353 u32 ctrl, rctl, status;
749ab2cd 7354 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7355#ifdef CONFIG_PM
7356 int retval = 0;
7357#endif
7358
7359 netif_device_detach(netdev);
7360
a88f10ec 7361 if (netif_running(netdev))
749ab2cd 7362 __igb_close(netdev, true);
a88f10ec 7363
047e0030 7364 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7365
7366#ifdef CONFIG_PM
7367 retval = pci_save_state(pdev);
7368 if (retval)
7369 return retval;
7370#endif
7371
7372 status = rd32(E1000_STATUS);
7373 if (status & E1000_STATUS_LU)
7374 wufc &= ~E1000_WUFC_LNKC;
7375
7376 if (wufc) {
7377 igb_setup_rctl(adapter);
ff41f8dc 7378 igb_set_rx_mode(netdev);
9d5c8243
AK		 7379
7380 /* turn on all-multi mode if wake on multicast is enabled */
7381 if (wufc & E1000_WUFC_MC) {
7382 rctl = rd32(E1000_RCTL);
7383 rctl |= E1000_RCTL_MPE;
7384 wr32(E1000_RCTL, rctl);
7385 }
7386
7387 ctrl = rd32(E1000_CTRL);
7388 /* advertise wake from D3Cold */
7389 #define E1000_CTRL_ADVD3WUC 0x00100000
7390 /* phy power management enable */
7391 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7392 ctrl |= E1000_CTRL_ADVD3WUC;
7393 wr32(E1000_CTRL, ctrl);
7394
9d5c8243 7395 /* Allow time for pending master requests to run */
330a6d6a 7396 igb_disable_pcie_master(hw);
9d5c8243
AK		 7397
7398 wr32(E1000_WUC, E1000_WUC_PME_EN);
7399 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7400 } else {
7401 wr32(E1000_WUC, 0);
7402 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7403 }
7404
3fe7c4c9
RW		 7405 *enable_wake = wufc || adapter->en_mng_pt;
7406 if (!*enable_wake)
88a268c1
NN		 7407 igb_power_down_link(adapter);
7408 else
7409 igb_power_up_link(adapter);
9d5c8243
AK		 7410
7411 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7412 * would have already happened in close and is redundant.
7413 */
9d5c8243
AK		 7414 igb_release_hw_control(adapter);
7415
7416 pci_disable_device(pdev);
7417
9d5c8243
AK		 7418 return 0;
7419}
7420
7421#ifdef CONFIG_PM
d9dd966d 7422#ifdef CONFIG_PM_SLEEP
749ab2cd 7423static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7424{
7425 int retval;
7426 bool wake;
749ab2cd 7427 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7428
749ab2cd 7429 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7430 if (retval)
7431 return retval;
7432
7433 if (wake) {
7434 pci_prepare_to_sleep(pdev);
7435 } else {
7436 pci_wake_from_d3(pdev, false);
7437 pci_set_power_state(pdev, PCI_D3hot);
7438 }
7439
7440 return 0;
7441}
d9dd966d 7442#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7443
749ab2cd 7444static int igb_resume(struct device *dev)
9d5c8243 7445{
749ab2cd 7446 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7447 struct net_device *netdev = pci_get_drvdata(pdev);
7448 struct igb_adapter *adapter = netdev_priv(netdev);
7449 struct e1000_hw *hw = &adapter->hw;
7450 u32 err;
7451
7452 pci_set_power_state(pdev, PCI_D0);
7453 pci_restore_state(pdev);
b94f2d77 7454 pci_save_state(pdev);
42bfd33a 7455
aed5dec3 7456 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7457 if (err) {
7458 dev_err(&pdev->dev,
7459 "igb: Cannot enable PCI device from suspend\n");
7460 return err;
7461 }
7462 pci_set_master(pdev);
7463
7464 pci_enable_wake(pdev, PCI_D3hot, 0);
7465 pci_enable_wake(pdev, PCI_D3cold, 0);
7466
53c7d064 7467 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7468 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7469 return -ENOMEM;
9d5c8243
AK		 7470 }
7471
9d5c8243 7472 igb_reset(adapter);
a8564f03
AD		 7473
7474 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7475 * driver.
7476 */
a8564f03
AD		 7477 igb_get_hw_control(adapter);
7478
9d5c8243
AK		 7479 wr32(E1000_WUS, ~0);
7480
749ab2cd 7481 if (netdev->flags & IFF_UP) {
0c2cc02e 7482 rtnl_lock();
749ab2cd 7483 err = __igb_open(netdev, true);
0c2cc02e 7484 rtnl_unlock();
a88f10ec
AD		 7485 if (err)
7486 return err;
7487 }
9d5c8243
AK		 7488
7489 netif_device_attach(netdev);
749ab2cd
YZ		 7490 return 0;
7491}
7492
7493#ifdef CONFIG_PM_RUNTIME
7494static int igb_runtime_idle(struct device *dev)
7495{
7496 struct pci_dev *pdev = to_pci_dev(dev);
7497 struct net_device *netdev = pci_get_drvdata(pdev);
7498 struct igb_adapter *adapter = netdev_priv(netdev);
7499
7500 if (!igb_has_link(adapter))
7501 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7502
7503 return -EBUSY;
7504}
7505
7506static int igb_runtime_suspend(struct device *dev)
7507{
7508 struct pci_dev *pdev = to_pci_dev(dev);
7509 int retval;
7510 bool wake;
7511
7512 retval = __igb_shutdown(pdev, &wake, 1);
7513 if (retval)
7514 return retval;
7515
7516 if (wake) {
7517 pci_prepare_to_sleep(pdev);
7518 } else {
7519 pci_wake_from_d3(pdev, false);
7520 pci_set_power_state(pdev, PCI_D3hot);
7521 }
9d5c8243 7522
9d5c8243
AK		 7523 return 0;
7524}
749ab2cd
YZ		 7525
7526static int igb_runtime_resume(struct device *dev)
7527{
7528 return igb_resume(dev);
7529}
7530#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7531#endif
7532
7533static void igb_shutdown(struct pci_dev *pdev)
7534{
3fe7c4c9
RW		 7535 bool wake;
7536
749ab2cd 7537 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7538
7539 if (system_state == SYSTEM_POWER_OFF) {
7540 pci_wake_from_d3(pdev, wake);
7541 pci_set_power_state(pdev, PCI_D3hot);
7542 }
9d5c8243
AK		 7543}
7544
fa44f2f1
GR		 7545#ifdef CONFIG_PCI_IOV
7546static int igb_sriov_reinit(struct pci_dev *dev)
7547{
7548 struct net_device *netdev = pci_get_drvdata(dev);
7549 struct igb_adapter *adapter = netdev_priv(netdev);
7550 struct pci_dev *pdev = adapter->pdev;
7551
7552 rtnl_lock();
7553
7554 if (netif_running(netdev))
7555 igb_close(netdev);
7556
7557 igb_clear_interrupt_scheme(adapter);
7558
7559 igb_init_queue_configuration(adapter);
7560
7561 if (igb_init_interrupt_scheme(adapter, true)) {
7562 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7563 return -ENOMEM;
7564 }
7565
7566 if (netif_running(netdev))
7567 igb_open(netdev);
7568
7569 rtnl_unlock();
7570
7571 return 0;
7572}
7573
7574static int igb_pci_disable_sriov(struct pci_dev *dev)
7575{
7576 int err = igb_disable_sriov(dev);
7577
7578 if (!err)
7579 err = igb_sriov_reinit(dev);
7580
7581 return err;
7582}
7583
7584static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7585{
7586 int err = igb_enable_sriov(dev, num_vfs);
7587
7588 if (err)
7589 goto out;
7590
7591 err = igb_sriov_reinit(dev);
7592 if (!err)
7593 return num_vfs;
7594
7595out:
7596 return err;
7597}
7598
7599#endif
7600static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7601{
7602#ifdef CONFIG_PCI_IOV
7603 if (num_vfs == 0)
7604 return igb_pci_disable_sriov(dev);
7605 else
7606 return igb_pci_enable_sriov(dev, num_vfs);
7607#endif
7608 return 0;
7609}
7610
9d5c8243 7611#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7612/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7613 * without having to re-enable interrupts. It's not called while
7614 * the interrupt routine is executing.
7615 */
7616static void igb_netpoll(struct net_device *netdev)
7617{
7618 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7619 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7620 struct igb_q_vector *q_vector;
9d5c8243 7621 int i;
9d5c8243 7622
047e0030 7623 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7624 q_vector = adapter->q_vector[i];
cd14ef54 7625 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7626 wr32(E1000_EIMC, q_vector->eims_value);
7627 else
7628 igb_irq_disable(adapter);
047e0030 7629 napi_schedule(&q_vector->napi);
eebbbdba 7630 }
9d5c8243
AK		 7631}
7632#endif /* CONFIG_NET_POLL_CONTROLLER */
7633
7634/**
b980ac18
JK		 7635 * igb_io_error_detected - called when PCI error is detected
7636 * @pdev: Pointer to PCI device
7637 * @state: The current pci connection state
9d5c8243 7638 *
b980ac18
JK		 7639 * This function is called after a PCI bus error affecting
7640 * this device has been detected.
7641 **/
9d5c8243
AK		 7642static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7643 pci_channel_state_t state)
7644{
7645 struct net_device *netdev = pci_get_drvdata(pdev);
7646 struct igb_adapter *adapter = netdev_priv(netdev);
7647
7648 netif_device_detach(netdev);
7649
59ed6eec
AD		 7650 if (state == pci_channel_io_perm_failure)
7651 return PCI_ERS_RESULT_DISCONNECT;
7652
9d5c8243
AK		 7653 if (netif_running(netdev))
7654 igb_down(adapter);
7655 pci_disable_device(pdev);
7656
7657 /* Request a slot slot reset. */
7658 return PCI_ERS_RESULT_NEED_RESET;
7659}
7660
7661/**
b980ac18
JK		 7662 * igb_io_slot_reset - called after the pci bus has been reset.
7663 * @pdev: Pointer to PCI device
9d5c8243 7664 *
b980ac18
JK		 7665 * Restart the card from scratch, as if from a cold-boot. Implementation
7666 * resembles the first-half of the igb_resume routine.
7667 **/
9d5c8243
AK		 7668static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7669{
7670 struct net_device *netdev = pci_get_drvdata(pdev);
7671 struct igb_adapter *adapter = netdev_priv(netdev);
7672 struct e1000_hw *hw = &adapter->hw;
40a914fa 7673 pci_ers_result_t result;
42bfd33a 7674 int err;
9d5c8243 7675
aed5dec3 7676 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7677 dev_err(&pdev->dev,
7678 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7679 result = PCI_ERS_RESULT_DISCONNECT;
7680 } else {
7681 pci_set_master(pdev);
7682 pci_restore_state(pdev);
b94f2d77 7683 pci_save_state(pdev);
9d5c8243 7684
40a914fa
AD		 7685 pci_enable_wake(pdev, PCI_D3hot, 0);
7686 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7687
40a914fa
AD		 7688 igb_reset(adapter);
7689 wr32(E1000_WUS, ~0);
7690 result = PCI_ERS_RESULT_RECOVERED;
7691 }
9d5c8243 7692
ea943d41
JK		 7693 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7694 if (err) {
b980ac18
JK		 7695 dev_err(&pdev->dev,
7696 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7697 err);
ea943d41
JK		 7698 /* non-fatal, continue */
7699 }
40a914fa
AD		 7700
7701 return result;
9d5c8243
AK		 7702}
7703
7704/**
b980ac18
JK		 7705 * igb_io_resume - called when traffic can start flowing again.
7706 * @pdev: Pointer to PCI device
9d5c8243 7707 *
b980ac18
JK		 7708 * This callback is called when the error recovery driver tells us that
7709 * its OK to resume normal operation. Implementation resembles the
7710 * second-half of the igb_resume routine.
9d5c8243
AK		 7711 */
7712static void igb_io_resume(struct pci_dev *pdev)
7713{
7714 struct net_device *netdev = pci_get_drvdata(pdev);
7715 struct igb_adapter *adapter = netdev_priv(netdev);
7716
9d5c8243
AK		 7717 if (netif_running(netdev)) {
7718 if (igb_up(adapter)) {
7719 dev_err(&pdev->dev, "igb_up failed after reset\n");
7720 return;
7721 }
7722 }
7723
7724 netif_device_attach(netdev);
7725
7726 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7727 * driver.
7728 */
9d5c8243 7729 igb_get_hw_control(adapter);
9d5c8243
AK		 7730}
7731
26ad9178 7732static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7733 u8 qsel)
26ad9178
AD		 7734{
7735 u32 rar_low, rar_high;
7736 struct e1000_hw *hw = &adapter->hw;
7737
7738 /* HW expects these in little endian so we reverse the byte order
7739 * from network order (big endian) to little endian
7740 */
7741 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7742 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7743 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7744
7745 /* Indicate to hardware the Address is Valid. */
7746 rar_high |= E1000_RAH_AV;
7747
7748 if (hw->mac.type == e1000_82575)
7749 rar_high |= E1000_RAH_POOL_1 * qsel;
7750 else
7751 rar_high |= E1000_RAH_POOL_1 << qsel;
7752
7753 wr32(E1000_RAL(index), rar_low);
7754 wrfl();
7755 wr32(E1000_RAH(index), rar_high);
7756 wrfl();
7757}
7758
4ae196df 7759static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7760 int vf, unsigned char *mac_addr)
4ae196df
AD		 7761{
7762 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7763 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7764 * towards the first, as a result a collision should not be possible
7765 */
ff41f8dc 7766 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7767
37680117 7768 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7769
26ad9178 7770 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7771
7772 return 0;
7773}
7774
8151d294
WM		 7775static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7776{
7777 struct igb_adapter *adapter = netdev_priv(netdev);
7778 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7779 return -EINVAL;
7780 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7781 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7782 dev_info(&adapter->pdev->dev,
7783 "Reload the VF driver to make this change effective.");
8151d294 7784 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7785 dev_warn(&adapter->pdev->dev,
7786 "The VF MAC address has been set, but the PF device is not up.\n");
7787 dev_warn(&adapter->pdev->dev,
7788 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7789 }
7790 return igb_set_vf_mac(adapter, vf, mac);
7791}
7792
17dc566c
LL		 7793static int igb_link_mbps(int internal_link_speed)
7794{
7795 switch (internal_link_speed) {
7796 case SPEED_100:
7797 return 100;
7798 case SPEED_1000:
7799 return 1000;
7800 default:
7801 return 0;
7802 }
7803}
7804
7805static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7806 int link_speed)
7807{
7808 int rf_dec, rf_int;
7809 u32 bcnrc_val;
7810
7811 if (tx_rate != 0) {
7812 /* Calculate the rate factor values to set */
7813 rf_int = link_speed / tx_rate;
7814 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7815 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7816 tx_rate;
17dc566c
LL		 7817
7818 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7819 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7820 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7821 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7822 } else {
7823 bcnrc_val = 0;
7824 }
7825
7826 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7827 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7828 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7829 */
7830 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7831 wr32(E1000_RTTBCNRC, bcnrc_val);
7832}
7833
7834static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7835{
7836 int actual_link_speed, i;
7837 bool reset_rate = false;
7838
7839 /* VF TX rate limit was not set or not supported */
7840 if ((adapter->vf_rate_link_speed == 0) ||
7841 (adapter->hw.mac.type != e1000_82576))
7842 return;
7843
7844 actual_link_speed = igb_link_mbps(adapter->link_speed);
7845 if (actual_link_speed != adapter->vf_rate_link_speed) {
7846 reset_rate = true;
7847 adapter->vf_rate_link_speed = 0;
7848 dev_info(&adapter->pdev->dev,
b980ac18 7849 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7850 }
7851
7852 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7853 if (reset_rate)
7854 adapter->vf_data[i].tx_rate = 0;
7855
7856 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7857 adapter->vf_data[i].tx_rate,
7858 actual_link_speed);
17dc566c
LL		 7859 }
7860}
7861
8151d294
WM		 7862static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7863{
17dc566c
LL		 7864 struct igb_adapter *adapter = netdev_priv(netdev);
7865 struct e1000_hw *hw = &adapter->hw;
7866 int actual_link_speed;
7867
7868 if (hw->mac.type != e1000_82576)
7869 return -EOPNOTSUPP;
7870
7871 actual_link_speed = igb_link_mbps(adapter->link_speed);
7872 if ((vf >= adapter->vfs_allocated_count) ||
7873 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7874 (tx_rate < 0) || (tx_rate > actual_link_speed))
7875 return -EINVAL;
7876
7877 adapter->vf_rate_link_speed = actual_link_speed;
7878 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7879 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7880
7881 return 0;
8151d294
WM		 7882}
7883
70ea4783
LL		 7884static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7885 bool setting)
7886{
7887 struct igb_adapter *adapter = netdev_priv(netdev);
7888 struct e1000_hw *hw = &adapter->hw;
7889 u32 reg_val, reg_offset;
7890
7891 if (!adapter->vfs_allocated_count)
7892 return -EOPNOTSUPP;
7893
7894 if (vf >= adapter->vfs_allocated_count)
7895 return -EINVAL;
7896
7897 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7898 reg_val = rd32(reg_offset);
7899 if (setting)
7900 reg_val |= ((1 << vf) |
7901 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7902 else
7903 reg_val &= ~((1 << vf) |
7904 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7905 wr32(reg_offset, reg_val);
7906
7907 adapter->vf_data[vf].spoofchk_enabled = setting;
7908 return E1000_SUCCESS;
7909}
7910
8151d294
WM		 7911static int igb_ndo_get_vf_config(struct net_device *netdev,
7912 int vf, struct ifla_vf_info *ivi)
7913{
7914 struct igb_adapter *adapter = netdev_priv(netdev);
7915 if (vf >= adapter->vfs_allocated_count)
7916 return -EINVAL;
7917 ivi->vf = vf;
7918 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7919 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7920 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7921 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7922 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7923 return 0;
7924}
7925
4ae196df
AD		 7926static void igb_vmm_control(struct igb_adapter *adapter)
7927{
7928 struct e1000_hw *hw = &adapter->hw;
10d8e907 7929 u32 reg;
4ae196df 7930
52a1dd4d
AD		 7931 switch (hw->mac.type) {
7932 case e1000_82575:
f96a8a0b
CW		 7933 case e1000_i210:
7934 case e1000_i211:
ceb5f13b 7935 case e1000_i354:
52a1dd4d
AD		 7936 default:
7937 /* replication is not supported for 82575 */
4ae196df 7938 return;
52a1dd4d
AD		 7939 case e1000_82576:
7940 /* notify HW that the MAC is adding vlan tags */
7941 reg = rd32(E1000_DTXCTL);
7942 reg |= E1000_DTXCTL_VLAN_ADDED;
7943 wr32(E1000_DTXCTL, reg);
7944 case e1000_82580:
7945 /* enable replication vlan tag stripping */
7946 reg = rd32(E1000_RPLOLR);
7947 reg |= E1000_RPLOLR_STRVLAN;
7948 wr32(E1000_RPLOLR, reg);
d2ba2ed8
AD		 7949 case e1000_i350:
7950 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7951 break;
7952 }
10d8e907 7953
d4960307
AD		 7954 if (adapter->vfs_allocated_count) {
7955 igb_vmdq_set_loopback_pf(hw, true);
7956 igb_vmdq_set_replication_pf(hw, true);
13800469 7957 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7958 adapter->vfs_allocated_count);
d4960307
AD		 7959 } else {
7960 igb_vmdq_set_loopback_pf(hw, false);
7961 igb_vmdq_set_replication_pf(hw, false);
7962 }
4ae196df
AD		 7963}
7964
b6e0c419
CW		 7965static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7966{
7967 struct e1000_hw *hw = &adapter->hw;
7968 u32 dmac_thr;
7969 u16 hwm;
7970
7971 if (hw->mac.type > e1000_82580) {
7972 if (adapter->flags & IGB_FLAG_DMAC) {
7973 u32 reg;
7974
7975 /* force threshold to 0. */
7976 wr32(E1000_DMCTXTH, 0);
7977
b980ac18 7978 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7979 * than the Rx threshold. Set hwm to PBA - max frame
7980 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7981 */
e8c626e9
MV		 7982 hwm = 64 * pba - adapter->max_frame_size / 16;
7983 if (hwm < 64 * (pba - 6))
7984 hwm = 64 * (pba - 6);
7985 reg = rd32(E1000_FCRTC);
7986 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7987 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7988 & E1000_FCRTC_RTH_COAL_MASK);
7989 wr32(E1000_FCRTC, reg);
7990
b980ac18 7991 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7992 * frame size, capping it at PBA - 10KB.
7993 */
7994 dmac_thr = pba - adapter->max_frame_size / 512;
7995 if (dmac_thr < pba - 10)
7996 dmac_thr = pba - 10;
b6e0c419
CW		 7997 reg = rd32(E1000_DMACR);
7998 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7999 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8000 & E1000_DMACR_DMACTHR_MASK);
8001
8002 /* transition to L0x or L1 if available..*/
8003 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8004
8005 /* watchdog timer= +-1000 usec in 32usec intervals */
8006 reg |= (1000 >> 5);
0c02dd98
MV		 8007
8008 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8009 if (hw->mac.type != e1000_i354)
8010 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8011
b6e0c419
CW		 8012 wr32(E1000_DMACR, reg);
8013
b980ac18 8014 /* no lower threshold to disable
b6e0c419
CW		 8015 * coalescing(smart fifb)-UTRESH=0
8016 */
8017 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8018
8019 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8020
8021 wr32(E1000_DMCTLX, reg);
8022
b980ac18 8023 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8024 * DMA coal
8025 */
8026 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8027 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8028
b980ac18 8029 /* make low power state decision controlled
b6e0c419
CW		 8030 * by DMA coal
8031 */
8032 reg = rd32(E1000_PCIEMISC);
8033 reg &= ~E1000_PCIEMISC_LX_DECISION;
8034 wr32(E1000_PCIEMISC, reg);
8035 } /* endif adapter->dmac is not disabled */
8036 } else if (hw->mac.type == e1000_82580) {
8037 u32 reg = rd32(E1000_PCIEMISC);
8038 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8039 wr32(E1000_DMACR, 0);
8040 }
8041}
8042
b980ac18
JK		 8043/**
8044 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8045 * @hw: pointer to hardware structure
8046 * @byte_offset: byte offset to read
8047 * @dev_addr: device address
8048 * @data: value read
8049 *
8050 * Performs byte read operation over I2C interface at
8051 * a specified device address.
b980ac18 8052 **/
441fc6fd 8053s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8054 u8 dev_addr, u8 *data)
441fc6fd
CW		 8055{
8056 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8057 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8058 s32 status;
8059 u16 swfw_mask = 0;
8060
8061 if (!this_client)
8062 return E1000_ERR_I2C;
8063
8064 swfw_mask = E1000_SWFW_PHY0_SM;
8065
8066 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
8067 != E1000_SUCCESS)
8068 return E1000_ERR_SWFW_SYNC;
8069
8070 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8071 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8072
8073 if (status < 0)
8074 return E1000_ERR_I2C;
8075 else {
8076 *data = status;
8077 return E1000_SUCCESS;
8078 }
8079}
8080
b980ac18
JK		 8081/**
8082 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8083 * @hw: pointer to hardware structure
8084 * @byte_offset: byte offset to write
8085 * @dev_addr: device address
8086 * @data: value to write
8087 *
8088 * Performs byte write operation over I2C interface at
8089 * a specified device address.
b980ac18 8090 **/
441fc6fd 8091s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8092 u8 dev_addr, u8 data)
441fc6fd
CW		 8093{
8094 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8095 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8096 s32 status;
8097 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8098
8099 if (!this_client)
8100 return E1000_ERR_I2C;
8101
8102 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
8103 return E1000_ERR_SWFW_SYNC;
8104 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8105 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8106
8107 if (status)
8108 return E1000_ERR_I2C;
8109 else
8110 return E1000_SUCCESS;
8111
8112}
907b7835
LMV		 8113
8114int igb_reinit_queues(struct igb_adapter *adapter)
8115{
8116 struct net_device *netdev = adapter->netdev;
8117 struct pci_dev *pdev = adapter->pdev;
8118 int err = 0;
8119
8120 if (netif_running(netdev))
8121 igb_close(netdev);
8122
02ef6e1d 8123 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8124
8125 if (igb_init_interrupt_scheme(adapter, true)) {
8126 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8127 return -ENOMEM;
8128 }
8129
8130 if (netif_running(netdev))
8131 err = igb_open(netdev);
8132
8133 return err;
8134}
9d5c8243 8135/* igb_main.c */
Linux kernel - Deliverables
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