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e1000e / igb / PM: Eliminate CONFIG_PM_RUNTIME
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
bf22a6bd 60#define MIN 2
b5d130c4 61#define BUILD 15
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 182#endif
9d5c8243 183
9d5c8243 184#ifdef CONFIG_PM
d9dd966d 185#ifdef CONFIG_PM_SLEEP
749ab2cd 186static int igb_suspend(struct device *);
d9dd966d 187#endif
749ab2cd 188static int igb_resume(struct device *);
749ab2cd
YZ		 189static int igb_runtime_suspend(struct device *dev);
190static int igb_runtime_resume(struct device *dev);
191static int igb_runtime_idle(struct device *dev);
749ab2cd
YZ		 192static const struct dev_pm_ops igb_pm_ops = {
193 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
194 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
195 igb_runtime_idle)
196};
9d5c8243
AK		 197#endif
198static void igb_shutdown(struct pci_dev *);
fa44f2f1 199static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 200#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 201static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
202static struct notifier_block dca_notifier = {
203 .notifier_call = igb_notify_dca,
204 .next = NULL,
205 .priority = 0
206};
207#endif
9d5c8243
AK		 208#ifdef CONFIG_NET_POLL_CONTROLLER
209/* for netdump / net console */
210static void igb_netpoll(struct net_device *);
211#endif
37680117 212#ifdef CONFIG_PCI_IOV
6dd6d2b7 213static unsigned int max_vfs;
2a3abf6d 214module_param(max_vfs, uint, 0);
c75c4edf 215MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 216#endif /* CONFIG_PCI_IOV */
217
9d5c8243
AK		 218static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
219 pci_channel_state_t);
220static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
221static void igb_io_resume(struct pci_dev *);
222
3646f0e5 223static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 224 .error_detected = igb_io_error_detected,
225 .slot_reset = igb_io_slot_reset,
226 .resume = igb_io_resume,
227};
228
b6e0c419 229static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 230
231static struct pci_driver igb_driver = {
232 .name = igb_driver_name,
233 .id_table = igb_pci_tbl,
234 .probe = igb_probe,
9f9a12f8 235 .remove = igb_remove,
9d5c8243 236#ifdef CONFIG_PM
749ab2cd 237 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 238#endif
239 .shutdown = igb_shutdown,
fa44f2f1 240 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 241 .err_handler = &igb_err_handler
242};
243
244MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
245MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
246MODULE_LICENSE("GPL");
247MODULE_VERSION(DRV_VERSION);
248
b3f4d599 249#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
250static int debug = -1;
251module_param(debug, int, 0);
252MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
253
c97ec42a
TI		 254struct igb_reg_info {
255 u32 ofs;
256 char *name;
257};
258
259static const struct igb_reg_info igb_reg_info_tbl[] = {
260
261 /* General Registers */
262 {E1000_CTRL, "CTRL"},
263 {E1000_STATUS, "STATUS"},
264 {E1000_CTRL_EXT, "CTRL_EXT"},
265
266 /* Interrupt Registers */
267 {E1000_ICR, "ICR"},
268
269 /* RX Registers */
270 {E1000_RCTL, "RCTL"},
271 {E1000_RDLEN(0), "RDLEN"},
272 {E1000_RDH(0), "RDH"},
273 {E1000_RDT(0), "RDT"},
274 {E1000_RXDCTL(0), "RXDCTL"},
275 {E1000_RDBAL(0), "RDBAL"},
276 {E1000_RDBAH(0), "RDBAH"},
277
278 /* TX Registers */
279 {E1000_TCTL, "TCTL"},
280 {E1000_TDBAL(0), "TDBAL"},
281 {E1000_TDBAH(0), "TDBAH"},
282 {E1000_TDLEN(0), "TDLEN"},
283 {E1000_TDH(0), "TDH"},
284 {E1000_TDT(0), "TDT"},
285 {E1000_TXDCTL(0), "TXDCTL"},
286 {E1000_TDFH, "TDFH"},
287 {E1000_TDFT, "TDFT"},
288 {E1000_TDFHS, "TDFHS"},
289 {E1000_TDFPC, "TDFPC"},
290
291 /* List Terminator */
292 {}
293};
294
b980ac18 295/* igb_regdump - register printout routine */
c97ec42a
TI		 296static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
297{
298 int n = 0;
299 char rname[16];
300 u32 regs[8];
301
302 switch (reginfo->ofs) {
303 case E1000_RDLEN(0):
304 for (n = 0; n < 4; n++)
305 regs[n] = rd32(E1000_RDLEN(n));
306 break;
307 case E1000_RDH(0):
308 for (n = 0; n < 4; n++)
309 regs[n] = rd32(E1000_RDH(n));
310 break;
311 case E1000_RDT(0):
312 for (n = 0; n < 4; n++)
313 regs[n] = rd32(E1000_RDT(n));
314 break;
315 case E1000_RXDCTL(0):
316 for (n = 0; n < 4; n++)
317 regs[n] = rd32(E1000_RXDCTL(n));
318 break;
319 case E1000_RDBAL(0):
320 for (n = 0; n < 4; n++)
321 regs[n] = rd32(E1000_RDBAL(n));
322 break;
323 case E1000_RDBAH(0):
324 for (n = 0; n < 4; n++)
325 regs[n] = rd32(E1000_RDBAH(n));
326 break;
327 case E1000_TDBAL(0):
328 for (n = 0; n < 4; n++)
329 regs[n] = rd32(E1000_RDBAL(n));
330 break;
331 case E1000_TDBAH(0):
332 for (n = 0; n < 4; n++)
333 regs[n] = rd32(E1000_TDBAH(n));
334 break;
335 case E1000_TDLEN(0):
336 for (n = 0; n < 4; n++)
337 regs[n] = rd32(E1000_TDLEN(n));
338 break;
339 case E1000_TDH(0):
340 for (n = 0; n < 4; n++)
341 regs[n] = rd32(E1000_TDH(n));
342 break;
343 case E1000_TDT(0):
344 for (n = 0; n < 4; n++)
345 regs[n] = rd32(E1000_TDT(n));
346 break;
347 case E1000_TXDCTL(0):
348 for (n = 0; n < 4; n++)
349 regs[n] = rd32(E1000_TXDCTL(n));
350 break;
351 default:
876d2d6f 352 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 353 return;
354 }
355
356 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 357 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
358 regs[2], regs[3]);
c97ec42a
TI		 359}
360
b980ac18 361/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 362static void igb_dump(struct igb_adapter *adapter)
363{
364 struct net_device *netdev = adapter->netdev;
365 struct e1000_hw *hw = &adapter->hw;
366 struct igb_reg_info *reginfo;
c97ec42a
TI		 367 struct igb_ring *tx_ring;
368 union e1000_adv_tx_desc *tx_desc;
369 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 370 struct igb_ring *rx_ring;
371 union e1000_adv_rx_desc *rx_desc;
372 u32 staterr;
6ad4edfc 373 u16 i, n;
c97ec42a
TI		 374
375 if (!netif_msg_hw(adapter))
376 return;
377
378 /* Print netdevice Info */
379 if (netdev) {
380 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 381 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
383 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 384 }
385
386 /* Print Registers */
387 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 388 pr_info(" Register Name Value\n");
c97ec42a
TI		 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
390 reginfo->name; reginfo++) {
391 igb_regdump(hw, reginfo);
392 }
393
394 /* Print TX Ring Summary */
395 if (!netdev || !netif_running(netdev))
396 goto exit;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 400 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 401 struct igb_tx_buffer *buffer_info;
c97ec42a 402 tx_ring = adapter->tx_ring[n];
06034649 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
405 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 406 (u64)dma_unmap_addr(buffer_info, dma),
407 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 408 buffer_info->next_to_watch,
409 (u64)buffer_info->time_stamp);
c97ec42a
TI		 410 }
411
412 /* Print TX Rings */
413 if (!netif_msg_tx_done(adapter))
414 goto rx_ring_summary;
415
416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
417
418 /* Transmit Descriptor Formats
419 *
420 * Advanced Transmit Descriptor
421 * +--------------------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +--------------------------------------------------------------+
424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
425 * +--------------------------------------------------------------+
426 * 63 46 45 40 39 38 36 35 32 31 24 15 0
427 */
428
429 for (n = 0; n < adapter->num_tx_queues; n++) {
430 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 431 pr_info("------------------------------------\n");
432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
433 pr_info("------------------------------------\n");
c75c4edf 434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 435
436 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 437 const char *next_desc;
06034649 438 struct igb_tx_buffer *buffer_info;
60136906 439 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 440 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 441 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 442 if (i == tx_ring->next_to_use &&
443 i == tx_ring->next_to_clean)
444 next_desc = " NTC/U";
445 else if (i == tx_ring->next_to_use)
446 next_desc = " NTU";
447 else if (i == tx_ring->next_to_clean)
448 next_desc = " NTC";
449 else
450 next_desc = "";
451
c75c4edf
CW		 452 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
453 i, le64_to_cpu(u0->a),
c97ec42a 454 le64_to_cpu(u0->b),
c9f14bf3
AD		 455 (u64)dma_unmap_addr(buffer_info, dma),
456 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 457 buffer_info->next_to_watch,
458 (u64)buffer_info->time_stamp,
876d2d6f 459 buffer_info->skb, next_desc);
c97ec42a 460
b669588a 461 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 462 print_hex_dump(KERN_INFO, "",
463 DUMP_PREFIX_ADDRESS,
b669588a 464 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 465 dma_unmap_len(buffer_info, len),
466 true);
c97ec42a
TI		 467 }
468 }
469
470 /* Print RX Rings Summary */
471rx_ring_summary:
472 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 473 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 474 for (n = 0; n < adapter->num_rx_queues; n++) {
475 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 476 pr_info(" %5d %5X %5X\n",
477 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 478 }
479
480 /* Print RX Rings */
481 if (!netif_msg_rx_status(adapter))
482 goto exit;
483
484 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
485
486 /* Advanced Receive Descriptor (Read) Format
487 * 63 1 0
488 * +-----------------------------------------------------+
489 * 0 | Packet Buffer Address [63:1] |A0/NSE|
490 * +----------------------------------------------+------+
491 * 8 | Header Buffer Address [63:1] | DD |
492 * +-----------------------------------------------------+
493 *
494 *
495 * Advanced Receive Descriptor (Write-Back) Format
496 *
497 * 63 48 47 32 31 30 21 20 17 16 4 3 0
498 * +------------------------------------------------------+
499 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
500 * | Checksum Ident | | | | Type | Type |
501 * +------------------------------------------------------+
502 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
503 * +------------------------------------------------------+
504 * 63 48 47 32 31 20 19 0
505 */
506
507 for (n = 0; n < adapter->num_rx_queues; n++) {
508 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 509 pr_info("------------------------------------\n");
510 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
511 pr_info("------------------------------------\n");
c75c4edf
CW		 512 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
513 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 514
515 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 516 const char *next_desc;
06034649
AD		 517 struct igb_rx_buffer *buffer_info;
518 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 519 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 520 u0 = (struct my_u0 *)rx_desc;
521 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 522
523 if (i == rx_ring->next_to_use)
524 next_desc = " NTU";
525 else if (i == rx_ring->next_to_clean)
526 next_desc = " NTC";
527 else
528 next_desc = "";
529
c97ec42a
TI		 530 if (staterr & E1000_RXD_STAT_DD) {
531 /* Descriptor Done */
1a1c225b
AD		 532 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
533 "RWB", i,
c97ec42a
TI		 534 le64_to_cpu(u0->a),
535 le64_to_cpu(u0->b),
1a1c225b 536 next_desc);
c97ec42a 537 } else {
1a1c225b
AD		 538 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
539 "R ", i,
c97ec42a
TI		 540 le64_to_cpu(u0->a),
541 le64_to_cpu(u0->b),
542 (u64)buffer_info->dma,
1a1c225b 543 next_desc);
c97ec42a 544
b669588a 545 if (netif_msg_pktdata(adapter) &&
1a1c225b 546 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 547 print_hex_dump(KERN_INFO, "",
548 DUMP_PREFIX_ADDRESS,
549 16, 1,
b669588a
ET		 550 page_address(buffer_info->page) +
551 buffer_info->page_offset,
de78d1f9 552 IGB_RX_BUFSZ, true);
c97ec42a
TI		 553 }
554 }
c97ec42a
TI		 555 }
556 }
557
558exit:
559 return;
560}
561
b980ac18
JK		 562/**
563 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 564 * @hw: pointer to hardware structure
565 * @i2cctl: Current value of I2CCTL register
566 *
567 * Returns the I2C data bit value
b980ac18 568 **/
441fc6fd
CW		 569static int igb_get_i2c_data(void *data)
570{
571 struct igb_adapter *adapter = (struct igb_adapter *)data;
572 struct e1000_hw *hw = &adapter->hw;
573 s32 i2cctl = rd32(E1000_I2CPARAMS);
574
da1f1dfe 575 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 576}
577
b980ac18
JK		 578/**
579 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 580 * @data: pointer to hardware structure
581 * @state: I2C data value (0 or 1) to set
582 *
583 * Sets the I2C data bit
b980ac18 584 **/
441fc6fd
CW		 585static void igb_set_i2c_data(void *data, int state)
586{
587 struct igb_adapter *adapter = (struct igb_adapter *)data;
588 struct e1000_hw *hw = &adapter->hw;
589 s32 i2cctl = rd32(E1000_I2CPARAMS);
590
591 if (state)
592 i2cctl |= E1000_I2C_DATA_OUT;
593 else
594 i2cctl &= ~E1000_I2C_DATA_OUT;
595
596 i2cctl &= ~E1000_I2C_DATA_OE_N;
597 i2cctl |= E1000_I2C_CLK_OE_N;
598 wr32(E1000_I2CPARAMS, i2cctl);
599 wrfl();
600
601}
602
b980ac18
JK		 603/**
604 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 605 * @data: pointer to hardware structure
606 * @state: state to set clock
607 *
608 * Sets the I2C clock line to state
b980ac18 609 **/
441fc6fd
CW		 610static void igb_set_i2c_clk(void *data, int state)
611{
612 struct igb_adapter *adapter = (struct igb_adapter *)data;
613 struct e1000_hw *hw = &adapter->hw;
614 s32 i2cctl = rd32(E1000_I2CPARAMS);
615
616 if (state) {
617 i2cctl |= E1000_I2C_CLK_OUT;
618 i2cctl &= ~E1000_I2C_CLK_OE_N;
619 } else {
620 i2cctl &= ~E1000_I2C_CLK_OUT;
621 i2cctl &= ~E1000_I2C_CLK_OE_N;
622 }
623 wr32(E1000_I2CPARAMS, i2cctl);
624 wrfl();
625}
626
b980ac18
JK		 627/**
628 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 629 * @data: pointer to hardware structure
630 *
631 * Gets the I2C clock state
b980ac18 632 **/
441fc6fd
CW		 633static int igb_get_i2c_clk(void *data)
634{
635 struct igb_adapter *adapter = (struct igb_adapter *)data;
636 struct e1000_hw *hw = &adapter->hw;
637 s32 i2cctl = rd32(E1000_I2CPARAMS);
638
da1f1dfe 639 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 640}
641
642static const struct i2c_algo_bit_data igb_i2c_algo = {
643 .setsda = igb_set_i2c_data,
644 .setscl = igb_set_i2c_clk,
645 .getsda = igb_get_i2c_data,
646 .getscl = igb_get_i2c_clk,
647 .udelay = 5,
648 .timeout = 20,
649};
650
9d5c8243 651/**
b980ac18
JK		 652 * igb_get_hw_dev - return device
653 * @hw: pointer to hardware structure
654 *
655 * used by hardware layer to print debugging information
9d5c8243 656 **/
c041076a 657struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 658{
659 struct igb_adapter *adapter = hw->back;
c041076a 660 return adapter->netdev;
9d5c8243 661}
38c845c7 662
9d5c8243 663/**
b980ac18 664 * igb_init_module - Driver Registration Routine
9d5c8243 665 *
b980ac18
JK		 666 * igb_init_module is the first routine called when the driver is
667 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 668 **/
669static int __init igb_init_module(void)
670{
671 int ret;
9005df38 672
876d2d6f 673 pr_info("%s - version %s\n",
9d5c8243 674 igb_driver_string, igb_driver_version);
876d2d6f 675 pr_info("%s\n", igb_copyright);
9d5c8243 676
421e02f0 677#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 678 dca_register_notify(&dca_notifier);
679#endif
bbd98fe4 680 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 681 return ret;
682}
683
684module_init(igb_init_module);
685
686/**
b980ac18 687 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 688 *
b980ac18
JK		 689 * igb_exit_module is called just before the driver is removed
690 * from memory.
9d5c8243
AK		 691 **/
692static void __exit igb_exit_module(void)
693{
421e02f0 694#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 695 dca_unregister_notify(&dca_notifier);
696#endif
9d5c8243
AK		 697 pci_unregister_driver(&igb_driver);
698}
699
700module_exit(igb_exit_module);
701
26bc19ec
AD		 702#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
703/**
b980ac18
JK		 704 * igb_cache_ring_register - Descriptor ring to register mapping
705 * @adapter: board private structure to initialize
26bc19ec 706 *
b980ac18
JK		 707 * Once we know the feature-set enabled for the device, we'll cache
708 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 709 **/
710static void igb_cache_ring_register(struct igb_adapter *adapter)
711{
ee1b9f06 712 int i = 0, j = 0;
047e0030 713 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 714
715 switch (adapter->hw.mac.type) {
716 case e1000_82576:
717 /* The queues are allocated for virtualization such that VF 0
718 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
719 * In order to avoid collision we start at the first free queue
720 * and continue consuming queues in the same sequence
721 */
ee1b9f06 722 if (adapter->vfs_allocated_count) {
a99955fc 723 for (; i < adapter->rss_queues; i++)
3025a446 724 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 725 Q_IDX_82576(i);
ee1b9f06 726 }
b26141d4 727 /* Fall through */
26bc19ec 728 case e1000_82575:
55cac248 729 case e1000_82580:
d2ba2ed8 730 case e1000_i350:
ceb5f13b 731 case e1000_i354:
f96a8a0b
CW		 732 case e1000_i210:
733 case e1000_i211:
b26141d4 734 /* Fall through */
26bc19ec 735 default:
ee1b9f06 736 for (; i < adapter->num_rx_queues; i++)
3025a446 737 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 738 for (; j < adapter->num_tx_queues; j++)
3025a446 739 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 740 break;
741 }
742}
743
22a8b291
FT		 744u32 igb_rd32(struct e1000_hw *hw, u32 reg)
745{
746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
748 u32 value = 0;
749
750 if (E1000_REMOVED(hw_addr))
751 return ~value;
752
753 value = readl(&hw_addr[reg]);
754
755 /* reads should not return all F's */
756 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
757 struct net_device *netdev = igb->netdev;
758 hw->hw_addr = NULL;
759 netif_device_detach(netdev);
760 netdev_err(netdev, "PCIe link lost, device now detached\n");
761 }
762
763 return value;
764}
765
4be000c8
AD		 766/**
767 * igb_write_ivar - configure ivar for given MSI-X vector
768 * @hw: pointer to the HW structure
769 * @msix_vector: vector number we are allocating to a given ring
770 * @index: row index of IVAR register to write within IVAR table
771 * @offset: column offset of in IVAR, should be multiple of 8
772 *
773 * This function is intended to handle the writing of the IVAR register
774 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
775 * each containing an cause allocation for an Rx and Tx ring, and a
776 * variable number of rows depending on the number of queues supported.
777 **/
778static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
779 int index, int offset)
780{
781 u32 ivar = array_rd32(E1000_IVAR0, index);
782
783 /* clear any bits that are currently set */
784 ivar &= ~((u32)0xFF << offset);
785
786 /* write vector and valid bit */
787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
788
789 array_wr32(E1000_IVAR0, index, ivar);
790}
791
9d5c8243 792#define IGB_N0_QUEUE -1
047e0030 793static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 794{
047e0030 795 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 796 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 797 int rx_queue = IGB_N0_QUEUE;
798 int tx_queue = IGB_N0_QUEUE;
4be000c8 799 u32 msixbm = 0;
047e0030 800
0ba82994
AD		 801 if (q_vector->rx.ring)
802 rx_queue = q_vector->rx.ring->reg_idx;
803 if (q_vector->tx.ring)
804 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 805
806 switch (hw->mac.type) {
807 case e1000_82575:
9d5c8243 808 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 809 * bitmask for the EICR/EIMS/EIMC registers. To assign one
810 * or more queues to a vector, we write the appropriate bits
811 * into the MSIXBM register for that vector.
812 */
047e0030 813 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 815 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 818 msixbm |= E1000_EIMS_OTHER;
9d5c8243 819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 820 q_vector->eims_value = msixbm;
2d064c06
AD		 821 break;
822 case e1000_82576:
b980ac18 823 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 824 * with 8 rows. The ordering is column-major so we use the
825 * lower 3 bits as the row index, and the 4th bit as the
826 * column offset.
827 */
828 if (rx_queue > IGB_N0_QUEUE)
829 igb_write_ivar(hw, msix_vector,
830 rx_queue & 0x7,
831 (rx_queue & 0x8) << 1);
832 if (tx_queue > IGB_N0_QUEUE)
833 igb_write_ivar(hw, msix_vector,
834 tx_queue & 0x7,
835 ((tx_queue & 0x8) << 1) + 8);
047e0030 836 q_vector->eims_value = 1 << msix_vector;
2d064c06 837 break;
55cac248 838 case e1000_82580:
d2ba2ed8 839 case e1000_i350:
ceb5f13b 840 case e1000_i354:
f96a8a0b
CW		 841 case e1000_i210:
842 case e1000_i211:
b980ac18 843 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 844 * however instead of ordering column-major we have things
845 * ordered row-major. So we traverse the table by using
846 * bit 0 as the column offset, and the remaining bits as the
847 * row index.
848 */
849 if (rx_queue > IGB_N0_QUEUE)
850 igb_write_ivar(hw, msix_vector,
851 rx_queue >> 1,
852 (rx_queue & 0x1) << 4);
853 if (tx_queue > IGB_N0_QUEUE)
854 igb_write_ivar(hw, msix_vector,
855 tx_queue >> 1,
856 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 857 q_vector->eims_value = 1 << msix_vector;
858 break;
2d064c06
AD		 859 default:
860 BUG();
861 break;
862 }
26b39276
AD		 863
864 /* add q_vector eims value to global eims_enable_mask */
865 adapter->eims_enable_mask |= q_vector->eims_value;
866
867 /* configure q_vector to set itr on first interrupt */
868 q_vector->set_itr = 1;
9d5c8243
AK		 869}
870
871/**
b980ac18
JK		 872 * igb_configure_msix - Configure MSI-X hardware
873 * @adapter: board private structure to initialize
9d5c8243 874 *
b980ac18
JK		 875 * igb_configure_msix sets up the hardware to properly
876 * generate MSI-X interrupts.
9d5c8243
AK		 877 **/
878static void igb_configure_msix(struct igb_adapter *adapter)
879{
880 u32 tmp;
881 int i, vector = 0;
882 struct e1000_hw *hw = &adapter->hw;
883
884 adapter->eims_enable_mask = 0;
9d5c8243
AK		 885
886 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 887 switch (hw->mac.type) {
888 case e1000_82575:
9d5c8243
AK		 889 tmp = rd32(E1000_CTRL_EXT);
890 /* enable MSI-X PBA support*/
891 tmp |= E1000_CTRL_EXT_PBA_CLR;
892
893 /* Auto-Mask interrupts upon ICR read. */
894 tmp |= E1000_CTRL_EXT_EIAME;
895 tmp |= E1000_CTRL_EXT_IRCA;
896
897 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 898
899 /* enable msix_other interrupt */
b980ac18 900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 901 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 902
2d064c06
AD		 903 break;
904
905 case e1000_82576:
55cac248 906 case e1000_82580:
d2ba2ed8 907 case e1000_i350:
ceb5f13b 908 case e1000_i354:
f96a8a0b
CW		 909 case e1000_i210:
910 case e1000_i211:
047e0030 911 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 912 * won't stick. And it will take days to debug.
913 */
047e0030 914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 915 E1000_GPIE_PBA | E1000_GPIE_EIAME |
916 E1000_GPIE_NSICR);
047e0030
AD		 917
918 /* enable msix_other interrupt */
919 adapter->eims_other = 1 << vector;
2d064c06 920 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 921
047e0030 922 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 923 break;
924 default:
925 /* do nothing, since nothing else supports MSI-X */
926 break;
927 } /* switch (hw->mac.type) */
047e0030
AD		 928
929 adapter->eims_enable_mask |= adapter->eims_other;
930
26b39276
AD		 931 for (i = 0; i < adapter->num_q_vectors; i++)
932 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 933
9d5c8243
AK		 934 wrfl();
935}
936
937/**
b980ac18
JK		 938 * igb_request_msix - Initialize MSI-X interrupts
939 * @adapter: board private structure to initialize
9d5c8243 940 *
b980ac18
JK		 941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
942 * kernel.
9d5c8243
AK		 943 **/
944static int igb_request_msix(struct igb_adapter *adapter)
945{
946 struct net_device *netdev = adapter->netdev;
047e0030 947 struct e1000_hw *hw = &adapter->hw;
52285b76 948 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 949
047e0030 950 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 951 igb_msix_other, 0, netdev->name, adapter);
047e0030 952 if (err)
52285b76 953 goto err_out;
047e0030
AD		 954
955 for (i = 0; i < adapter->num_q_vectors; i++) {
956 struct igb_q_vector *q_vector = adapter->q_vector[i];
957
52285b76
SA		 958 vector++;
959
047e0030
AD		 960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
961
0ba82994 962 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 964 q_vector->rx.ring->queue_index);
965 else if (q_vector->tx.ring)
047e0030 966 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 967 q_vector->tx.ring->queue_index);
968 else if (q_vector->rx.ring)
047e0030 969 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 970 q_vector->rx.ring->queue_index);
9d5c8243 971 else
047e0030
AD		 972 sprintf(q_vector->name, "%s-unused", netdev->name);
973
9d5c8243 974 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 975 igb_msix_ring, 0, q_vector->name,
976 q_vector);
9d5c8243 977 if (err)
52285b76 978 goto err_free;
9d5c8243
AK		 979 }
980
9d5c8243
AK		 981 igb_configure_msix(adapter);
982 return 0;
52285b76
SA		 983
984err_free:
985 /* free already assigned IRQs */
986 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
987
988 vector--;
989 for (i = 0; i < vector; i++) {
990 free_irq(adapter->msix_entries[free_vector++].vector,
991 adapter->q_vector[i]);
992 }
993err_out:
9d5c8243
AK		 994 return err;
995}
996
5536d210 997/**
b980ac18
JK		 998 * igb_free_q_vector - Free memory allocated for specific interrupt vector
999 * @adapter: board private structure to initialize
1000 * @v_idx: Index of vector to be freed
5536d210 1001 *
02ef6e1d 1002 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1003 **/
1004static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1005{
1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1007
02ef6e1d
CW		 1008 adapter->q_vector[v_idx] = NULL;
1009
1010 /* igb_get_stats64() might access the rings on this vector,
1011 * we must wait a grace period before freeing it.
1012 */
1013 kfree_rcu(q_vector, rcu);
1014}
1015
1016/**
1017 * igb_reset_q_vector - Reset config for interrupt vector
1018 * @adapter: board private structure to initialize
1019 * @v_idx: Index of vector to be reset
1020 *
1021 * If NAPI is enabled it will delete any references to the
1022 * NAPI struct. This is preparation for igb_free_q_vector.
1023 **/
1024static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1025{
1026 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1027
cb06d102
CP		 1028 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1029 * allocated. So, q_vector is NULL so we should stop here.
1030 */
1031 if (!q_vector)
1032 return;
1033
5536d210
AD		 1034 if (q_vector->tx.ring)
1035 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1036
1037 if (q_vector->rx.ring)
1038 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1039
5536d210
AD		 1040 netif_napi_del(&q_vector->napi);
1041
02ef6e1d
CW		 1042}
1043
1044static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1045{
1046 int v_idx = adapter->num_q_vectors;
1047
cd14ef54 1048 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1049 pci_disable_msix(adapter->pdev);
cd14ef54 1050 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1051 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1052
1053 while (v_idx--)
1054 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1055}
1056
047e0030 1057/**
b980ac18
JK		 1058 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1059 * @adapter: board private structure to initialize
047e0030 1060 *
b980ac18
JK		 1061 * This function frees the memory allocated to the q_vectors. In addition if
1062 * NAPI is enabled it will delete any references to the NAPI struct prior
1063 * to freeing the q_vector.
047e0030
AD		 1064 **/
1065static void igb_free_q_vectors(struct igb_adapter *adapter)
1066{
5536d210
AD		 1067 int v_idx = adapter->num_q_vectors;
1068
1069 adapter->num_tx_queues = 0;
1070 adapter->num_rx_queues = 0;
047e0030 1071 adapter->num_q_vectors = 0;
5536d210 1072
02ef6e1d
CW		 1073 while (v_idx--) {
1074 igb_reset_q_vector(adapter, v_idx);
5536d210 1075 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1076 }
047e0030
AD		 1077}
1078
1079/**
b980ac18
JK		 1080 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1081 * @adapter: board private structure to initialize
047e0030 1082 *
b980ac18
JK		 1083 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1084 * MSI-X interrupts allocated.
047e0030
AD		 1085 */
1086static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1087{
047e0030
AD		 1088 igb_free_q_vectors(adapter);
1089 igb_reset_interrupt_capability(adapter);
1090}
9d5c8243
AK		 1091
1092/**
b980ac18
JK		 1093 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1094 * @adapter: board private structure to initialize
1095 * @msix: boolean value of MSIX capability
9d5c8243 1096 *
b980ac18
JK		 1097 * Attempt to configure interrupts using the best available
1098 * capabilities of the hardware and kernel.
9d5c8243 1099 **/
53c7d064 1100static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1101{
1102 int err;
1103 int numvecs, i;
1104
53c7d064
SA		 1105 if (!msix)
1106 goto msi_only;
cd14ef54 1107 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1108
83b7180d 1109 /* Number of supported queues. */
a99955fc 1110 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1111 if (adapter->vfs_allocated_count)
1112 adapter->num_tx_queues = 1;
1113 else
1114 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1115
b980ac18 1116 /* start with one vector for every Rx queue */
047e0030
AD		 1117 numvecs = adapter->num_rx_queues;
1118
b980ac18 1119 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1120 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1121 numvecs += adapter->num_tx_queues;
047e0030
AD		 1122
1123 /* store the number of vectors reserved for queues */
1124 adapter->num_q_vectors = numvecs;
1125
1126 /* add 1 vector for link status interrupts */
1127 numvecs++;
9d5c8243
AK		 1128 for (i = 0; i < numvecs; i++)
1129 adapter->msix_entries[i].entry = i;
1130
479d02df
AG		 1131 err = pci_enable_msix_range(adapter->pdev,
1132 adapter->msix_entries,
1133 numvecs,
1134 numvecs);
1135 if (err > 0)
0c2cc02e 1136 return;
9d5c8243
AK		 1137
1138 igb_reset_interrupt_capability(adapter);
1139
1140 /* If we can't do MSI-X, try MSI */
1141msi_only:
b709323d 1142 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1143#ifdef CONFIG_PCI_IOV
1144 /* disable SR-IOV for non MSI-X configurations */
1145 if (adapter->vf_data) {
1146 struct e1000_hw *hw = &adapter->hw;
1147 /* disable iov and allow time for transactions to clear */
1148 pci_disable_sriov(adapter->pdev);
1149 msleep(500);
1150
1151 kfree(adapter->vf_data);
1152 adapter->vf_data = NULL;
1153 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1154 wrfl();
2a3abf6d
AD		 1155 msleep(100);
1156 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1157 }
1158#endif
4fc82adf 1159 adapter->vfs_allocated_count = 0;
a99955fc 1160 adapter->rss_queues = 1;
4fc82adf 1161 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1162 adapter->num_rx_queues = 1;
661086df 1163 adapter->num_tx_queues = 1;
047e0030 1164 adapter->num_q_vectors = 1;
9d5c8243 1165 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1166 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1167}
1168
5536d210
AD		 1169static void igb_add_ring(struct igb_ring *ring,
1170 struct igb_ring_container *head)
1171{
1172 head->ring = ring;
1173 head->count++;
1174}
1175
047e0030 1176/**
b980ac18
JK		 1177 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1178 * @adapter: board private structure to initialize
1179 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1180 * @v_idx: index of vector in adapter struct
1181 * @txr_count: total number of Tx rings to allocate
1182 * @txr_idx: index of first Tx ring to allocate
1183 * @rxr_count: total number of Rx rings to allocate
1184 * @rxr_idx: index of first Rx ring to allocate
047e0030 1185 *
b980ac18 1186 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1187 **/
5536d210
AD		 1188static int igb_alloc_q_vector(struct igb_adapter *adapter,
1189 int v_count, int v_idx,
1190 int txr_count, int txr_idx,
1191 int rxr_count, int rxr_idx)
047e0030
AD		 1192{
1193 struct igb_q_vector *q_vector;
5536d210
AD		 1194 struct igb_ring *ring;
1195 int ring_count, size;
047e0030 1196
5536d210
AD		 1197 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1198 if (txr_count > 1 || rxr_count > 1)
1199 return -ENOMEM;
1200
1201 ring_count = txr_count + rxr_count;
1202 size = sizeof(struct igb_q_vector) +
1203 (sizeof(struct igb_ring) * ring_count);
1204
1205 /* allocate q_vector and rings */
02ef6e1d
CW		 1206 q_vector = adapter->q_vector[v_idx];
1207 if (!q_vector)
1208 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1209 if (!q_vector)
1210 return -ENOMEM;
1211
1212 /* initialize NAPI */
1213 netif_napi_add(adapter->netdev, &q_vector->napi,
1214 igb_poll, 64);
1215
1216 /* tie q_vector and adapter together */
1217 adapter->q_vector[v_idx] = q_vector;
1218 q_vector->adapter = adapter;
1219
1220 /* initialize work limits */
1221 q_vector->tx.work_limit = adapter->tx_work_limit;
1222
1223 /* initialize ITR configuration */
1224 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1225 q_vector->itr_val = IGB_START_ITR;
1226
1227 /* initialize pointer to rings */
1228 ring = q_vector->ring;
1229
4e227667
AD		 1230 /* intialize ITR */
1231 if (rxr_count) {
1232 /* rx or rx/tx vector */
1233 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1234 q_vector->itr_val = adapter->rx_itr_setting;
1235 } else {
1236 /* tx only vector */
1237 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1238 q_vector->itr_val = adapter->tx_itr_setting;
1239 }
1240
5536d210
AD		 1241 if (txr_count) {
1242 /* assign generic ring traits */
1243 ring->dev = &adapter->pdev->dev;
1244 ring->netdev = adapter->netdev;
1245
1246 /* configure backlink on ring */
1247 ring->q_vector = q_vector;
1248
1249 /* update q_vector Tx values */
1250 igb_add_ring(ring, &q_vector->tx);
1251
1252 /* For 82575, context index must be unique per ring. */
1253 if (adapter->hw.mac.type == e1000_82575)
1254 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1255
1256 /* apply Tx specific ring traits */
1257 ring->count = adapter->tx_ring_count;
1258 ring->queue_index = txr_idx;
1259
827da44c
JS		 1260 u64_stats_init(&ring->tx_syncp);
1261 u64_stats_init(&ring->tx_syncp2);
1262
5536d210
AD		 1263 /* assign ring to adapter */
1264 adapter->tx_ring[txr_idx] = ring;
1265
1266 /* push pointer to next ring */
1267 ring++;
047e0030 1268 }
81c2fc22 1269
5536d210
AD		 1270 if (rxr_count) {
1271 /* assign generic ring traits */
1272 ring->dev = &adapter->pdev->dev;
1273 ring->netdev = adapter->netdev;
047e0030 1274
5536d210
AD		 1275 /* configure backlink on ring */
1276 ring->q_vector = q_vector;
047e0030 1277
5536d210
AD		 1278 /* update q_vector Rx values */
1279 igb_add_ring(ring, &q_vector->rx);
047e0030 1280
5536d210
AD		 1281 /* set flag indicating ring supports SCTP checksum offload */
1282 if (adapter->hw.mac.type >= e1000_82576)
1283 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1284
e52c0f96 1285 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1286 * have the tag byte-swapped.
b980ac18 1287 */
5536d210
AD		 1288 if (adapter->hw.mac.type >= e1000_i350)
1289 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1290
5536d210
AD		 1291 /* apply Rx specific ring traits */
1292 ring->count = adapter->rx_ring_count;
1293 ring->queue_index = rxr_idx;
1294
827da44c
JS		 1295 u64_stats_init(&ring->rx_syncp);
1296
5536d210
AD		 1297 /* assign ring to adapter */
1298 adapter->rx_ring[rxr_idx] = ring;
1299 }
1300
1301 return 0;
047e0030
AD		 1302}
1303
5536d210 1304
047e0030 1305/**
b980ac18
JK		 1306 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1307 * @adapter: board private structure to initialize
047e0030 1308 *
b980ac18
JK		 1309 * We allocate one q_vector per queue interrupt. If allocation fails we
1310 * return -ENOMEM.
047e0030 1311 **/
5536d210 1312static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1313{
5536d210
AD		 1314 int q_vectors = adapter->num_q_vectors;
1315 int rxr_remaining = adapter->num_rx_queues;
1316 int txr_remaining = adapter->num_tx_queues;
1317 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1318 int err;
047e0030 1319
5536d210
AD		 1320 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1321 for (; rxr_remaining; v_idx++) {
1322 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1323 0, 0, 1, rxr_idx);
047e0030 1324
5536d210
AD		 1325 if (err)
1326 goto err_out;
1327
1328 /* update counts and index */
1329 rxr_remaining--;
1330 rxr_idx++;
047e0030 1331 }
047e0030 1332 }
5536d210
AD		 1333
1334 for (; v_idx < q_vectors; v_idx++) {
1335 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1336 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1337
5536d210
AD		 1338 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1339 tqpv, txr_idx, rqpv, rxr_idx);
1340
1341 if (err)
1342 goto err_out;
1343
1344 /* update counts and index */
1345 rxr_remaining -= rqpv;
1346 txr_remaining -= tqpv;
1347 rxr_idx++;
1348 txr_idx++;
1349 }
1350
047e0030 1351 return 0;
5536d210
AD		 1352
1353err_out:
1354 adapter->num_tx_queues = 0;
1355 adapter->num_rx_queues = 0;
1356 adapter->num_q_vectors = 0;
1357
1358 while (v_idx--)
1359 igb_free_q_vector(adapter, v_idx);
1360
1361 return -ENOMEM;
047e0030
AD		 1362}
1363
1364/**
b980ac18
JK		 1365 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1366 * @adapter: board private structure to initialize
1367 * @msix: boolean value of MSIX capability
047e0030 1368 *
b980ac18 1369 * This function initializes the interrupts and allocates all of the queues.
047e0030 1370 **/
53c7d064 1371static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1372{
1373 struct pci_dev *pdev = adapter->pdev;
1374 int err;
1375
53c7d064 1376 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1377
1378 err = igb_alloc_q_vectors(adapter);
1379 if (err) {
1380 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1381 goto err_alloc_q_vectors;
1382 }
1383
5536d210 1384 igb_cache_ring_register(adapter);
047e0030
AD		 1385
1386 return 0;
5536d210 1387
047e0030
AD		 1388err_alloc_q_vectors:
1389 igb_reset_interrupt_capability(adapter);
1390 return err;
1391}
1392
9d5c8243 1393/**
b980ac18
JK		 1394 * igb_request_irq - initialize interrupts
1395 * @adapter: board private structure to initialize
9d5c8243 1396 *
b980ac18
JK		 1397 * Attempts to configure interrupts using the best available
1398 * capabilities of the hardware and kernel.
9d5c8243
AK		 1399 **/
1400static int igb_request_irq(struct igb_adapter *adapter)
1401{
1402 struct net_device *netdev = adapter->netdev;
047e0030 1403 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1404 int err = 0;
1405
cd14ef54 1406 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1407 err = igb_request_msix(adapter);
844290e5 1408 if (!err)
9d5c8243 1409 goto request_done;
9d5c8243 1410 /* fall back to MSI */
5536d210
AD		 1411 igb_free_all_tx_resources(adapter);
1412 igb_free_all_rx_resources(adapter);
53c7d064 1413
047e0030 1414 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1415 err = igb_init_interrupt_scheme(adapter, false);
1416 if (err)
047e0030 1417 goto request_done;
53c7d064 1418
047e0030
AD		 1419 igb_setup_all_tx_resources(adapter);
1420 igb_setup_all_rx_resources(adapter);
53c7d064 1421 igb_configure(adapter);
9d5c8243 1422 }
844290e5 1423
c74d588e
AD		 1424 igb_assign_vector(adapter->q_vector[0], 0);
1425
7dfc16fa 1426 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1427 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1428 netdev->name, adapter);
9d5c8243
AK		 1429 if (!err)
1430 goto request_done;
047e0030 1431
9d5c8243
AK		 1432 /* fall back to legacy interrupts */
1433 igb_reset_interrupt_capability(adapter);
7dfc16fa 1434 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1435 }
1436
c74d588e 1437 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1438 netdev->name, adapter);
9d5c8243 1439
6cb5e577 1440 if (err)
c74d588e 1441 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1442 err);
9d5c8243
AK		 1443
1444request_done:
1445 return err;
1446}
1447
1448static void igb_free_irq(struct igb_adapter *adapter)
1449{
cd14ef54 1450 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1451 int vector = 0, i;
1452
047e0030 1453 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1454
0d1ae7f4 1455 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1456 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1457 adapter->q_vector[i]);
047e0030
AD		 1458 } else {
1459 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1460 }
9d5c8243
AK		 1461}
1462
1463/**
b980ac18
JK		 1464 * igb_irq_disable - Mask off interrupt generation on the NIC
1465 * @adapter: board private structure
9d5c8243
AK		 1466 **/
1467static void igb_irq_disable(struct igb_adapter *adapter)
1468{
1469 struct e1000_hw *hw = &adapter->hw;
1470
b980ac18 1471 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1472 * mapped into these registers and so clearing the bits can cause
1473 * issues on the VF drivers so we only need to clear what we set
1474 */
cd14ef54 1475 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1476 u32 regval = rd32(E1000_EIAM);
9005df38 1477
2dfd1212
AD		 1478 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1479 wr32(E1000_EIMC, adapter->eims_enable_mask);
1480 regval = rd32(E1000_EIAC);
1481 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1482 }
844290e5
PW		 1483
1484 wr32(E1000_IAM, 0);
9d5c8243
AK		 1485 wr32(E1000_IMC, ~0);
1486 wrfl();
cd14ef54 1487 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1488 int i;
9005df38 1489
81a61859
ET		 1490 for (i = 0; i < adapter->num_q_vectors; i++)
1491 synchronize_irq(adapter->msix_entries[i].vector);
1492 } else {
1493 synchronize_irq(adapter->pdev->irq);
1494 }
9d5c8243
AK		 1495}
1496
1497/**
b980ac18
JK		 1498 * igb_irq_enable - Enable default interrupt generation settings
1499 * @adapter: board private structure
9d5c8243
AK		 1500 **/
1501static void igb_irq_enable(struct igb_adapter *adapter)
1502{
1503 struct e1000_hw *hw = &adapter->hw;
1504
cd14ef54 1505 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1506 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1507 u32 regval = rd32(E1000_EIAC);
9005df38 1508
2dfd1212
AD		 1509 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1510 regval = rd32(E1000_EIAM);
1511 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1512 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1513 if (adapter->vfs_allocated_count) {
4ae196df 1514 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1515 ims |= E1000_IMS_VMMB;
1516 }
1517 wr32(E1000_IMS, ims);
844290e5 1518 } else {
55cac248
AD		 1519 wr32(E1000_IMS, IMS_ENABLE_MASK |
1520 E1000_IMS_DRSTA);
1521 wr32(E1000_IAM, IMS_ENABLE_MASK |
1522 E1000_IMS_DRSTA);
844290e5 1523 }
9d5c8243
AK		 1524}
1525
1526static void igb_update_mng_vlan(struct igb_adapter *adapter)
1527{
51466239 1528 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1529 u16 vid = adapter->hw.mng_cookie.vlan_id;
1530 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1531
1532 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1533 /* add VID to filter table */
1534 igb_vfta_set(hw, vid, true);
1535 adapter->mng_vlan_id = vid;
1536 } else {
1537 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1538 }
1539
1540 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1541 (vid != old_vid) &&
b2cb09b1 1542 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1543 /* remove VID from filter table */
1544 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1545 }
1546}
1547
1548/**
b980ac18
JK		 1549 * igb_release_hw_control - release control of the h/w to f/w
1550 * @adapter: address of board private structure
9d5c8243 1551 *
b980ac18
JK		 1552 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1553 * For ASF and Pass Through versions of f/w this means that the
1554 * driver is no longer loaded.
9d5c8243
AK		 1555 **/
1556static void igb_release_hw_control(struct igb_adapter *adapter)
1557{
1558 struct e1000_hw *hw = &adapter->hw;
1559 u32 ctrl_ext;
1560
1561 /* Let firmware take over control of h/w */
1562 ctrl_ext = rd32(E1000_CTRL_EXT);
1563 wr32(E1000_CTRL_EXT,
1564 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1565}
1566
9d5c8243 1567/**
b980ac18
JK		 1568 * igb_get_hw_control - get control of the h/w from f/w
1569 * @adapter: address of board private structure
9d5c8243 1570 *
b980ac18
JK		 1571 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1572 * For ASF and Pass Through versions of f/w this means that
1573 * the driver is loaded.
9d5c8243
AK		 1574 **/
1575static void igb_get_hw_control(struct igb_adapter *adapter)
1576{
1577 struct e1000_hw *hw = &adapter->hw;
1578 u32 ctrl_ext;
1579
1580 /* Let firmware know the driver has taken over */
1581 ctrl_ext = rd32(E1000_CTRL_EXT);
1582 wr32(E1000_CTRL_EXT,
1583 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1584}
1585
9d5c8243 1586/**
b980ac18
JK		 1587 * igb_configure - configure the hardware for RX and TX
1588 * @adapter: private board structure
9d5c8243
AK		 1589 **/
1590static void igb_configure(struct igb_adapter *adapter)
1591{
1592 struct net_device *netdev = adapter->netdev;
1593 int i;
1594
1595 igb_get_hw_control(adapter);
ff41f8dc 1596 igb_set_rx_mode(netdev);
9d5c8243
AK		 1597
1598 igb_restore_vlan(adapter);
9d5c8243 1599
85b430b4 1600 igb_setup_tctl(adapter);
06cf2666 1601 igb_setup_mrqc(adapter);
9d5c8243 1602 igb_setup_rctl(adapter);
85b430b4
AD		 1603
1604 igb_configure_tx(adapter);
9d5c8243 1605 igb_configure_rx(adapter);
662d7205
AD		 1606
1607 igb_rx_fifo_flush_82575(&adapter->hw);
1608
c493ea45 1609 /* call igb_desc_unused which always leaves
9d5c8243 1610 * at least 1 descriptor unused to make sure
b980ac18
JK		 1611 * next_to_use != next_to_clean
1612 */
9d5c8243 1613 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1614 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1615 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1616 }
9d5c8243
AK		 1617}
1618
88a268c1 1619/**
b980ac18
JK		 1620 * igb_power_up_link - Power up the phy/serdes link
1621 * @adapter: address of board private structure
88a268c1
NN		 1622 **/
1623void igb_power_up_link(struct igb_adapter *adapter)
1624{
76886596
AA		 1625 igb_reset_phy(&adapter->hw);
1626
88a268c1
NN		 1627 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1628 igb_power_up_phy_copper(&adapter->hw);
1629 else
1630 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1631
1632 igb_setup_link(&adapter->hw);
88a268c1
NN		 1633}
1634
1635/**
b980ac18
JK		 1636 * igb_power_down_link - Power down the phy/serdes link
1637 * @adapter: address of board private structure
88a268c1
NN		 1638 */
1639static void igb_power_down_link(struct igb_adapter *adapter)
1640{
1641 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1642 igb_power_down_phy_copper_82575(&adapter->hw);
1643 else
1644 igb_shutdown_serdes_link_82575(&adapter->hw);
1645}
9d5c8243 1646
56cec249
CW		 1647/**
1648 * Detect and switch function for Media Auto Sense
1649 * @adapter: address of the board private structure
1650 **/
1651static void igb_check_swap_media(struct igb_adapter *adapter)
1652{
1653 struct e1000_hw *hw = &adapter->hw;
1654 u32 ctrl_ext, connsw;
1655 bool swap_now = false;
1656
1657 ctrl_ext = rd32(E1000_CTRL_EXT);
1658 connsw = rd32(E1000_CONNSW);
1659
1660 /* need to live swap if current media is copper and we have fiber/serdes
1661 * to go to.
1662 */
1663
1664 if ((hw->phy.media_type == e1000_media_type_copper) &&
1665 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1666 swap_now = true;
1667 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1668 /* copper signal takes time to appear */
1669 if (adapter->copper_tries < 4) {
1670 adapter->copper_tries++;
1671 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1672 wr32(E1000_CONNSW, connsw);
1673 return;
1674 } else {
1675 adapter->copper_tries = 0;
1676 if ((connsw & E1000_CONNSW_PHYSD) &&
1677 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1678 swap_now = true;
1679 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1680 wr32(E1000_CONNSW, connsw);
1681 }
1682 }
1683 }
1684
1685 if (!swap_now)
1686 return;
1687
1688 switch (hw->phy.media_type) {
1689 case e1000_media_type_copper:
1690 netdev_info(adapter->netdev,
1691 "MAS: changing media to fiber/serdes\n");
1692 ctrl_ext |=
1693 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1694 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1695 adapter->copper_tries = 0;
1696 break;
1697 case e1000_media_type_internal_serdes:
1698 case e1000_media_type_fiber:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to copper\n");
1701 ctrl_ext &=
1702 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 break;
1705 default:
1706 /* shouldn't get here during regular operation */
1707 netdev_err(adapter->netdev,
1708 "AMS: Invalid media type found, returning\n");
1709 break;
1710 }
1711 wr32(E1000_CTRL_EXT, ctrl_ext);
1712}
1713
9d5c8243 1714/**
b980ac18
JK		 1715 * igb_up - Open the interface and prepare it to handle traffic
1716 * @adapter: board private structure
9d5c8243 1717 **/
9d5c8243
AK		 1718int igb_up(struct igb_adapter *adapter)
1719{
1720 struct e1000_hw *hw = &adapter->hw;
1721 int i;
1722
1723 /* hardware has been reset, we need to reload some things */
1724 igb_configure(adapter);
1725
1726 clear_bit(__IGB_DOWN, &adapter->state);
1727
0d1ae7f4
AD		 1728 for (i = 0; i < adapter->num_q_vectors; i++)
1729 napi_enable(&(adapter->q_vector[i]->napi));
1730
cd14ef54 1731 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1732 igb_configure_msix(adapter);
feeb2721
AD		 1733 else
1734 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1735
1736 /* Clear any pending interrupts. */
1737 rd32(E1000_ICR);
1738 igb_irq_enable(adapter);
1739
d4960307
AD		 1740 /* notify VFs that reset has been completed */
1741 if (adapter->vfs_allocated_count) {
1742 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1743
d4960307
AD		 1744 reg_data |= E1000_CTRL_EXT_PFRSTD;
1745 wr32(E1000_CTRL_EXT, reg_data);
1746 }
1747
4cb9be7a
JB		 1748 netif_tx_start_all_queues(adapter->netdev);
1749
25568a53
AD		 1750 /* start the watchdog. */
1751 hw->mac.get_link_status = 1;
1752 schedule_work(&adapter->watchdog_task);
1753
f4c01e96
CW		 1754 if ((adapter->flags & IGB_FLAG_EEE) &&
1755 (!hw->dev_spec._82575.eee_disable))
1756 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1757
9d5c8243
AK		 1758 return 0;
1759}
1760
1761void igb_down(struct igb_adapter *adapter)
1762{
9d5c8243 1763 struct net_device *netdev = adapter->netdev;
330a6d6a 1764 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1765 u32 tctl, rctl;
1766 int i;
1767
1768 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1769 * reschedule our watchdog timer
1770 */
9d5c8243
AK		 1771 set_bit(__IGB_DOWN, &adapter->state);
1772
1773 /* disable receives in the hardware */
1774 rctl = rd32(E1000_RCTL);
1775 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1776 /* flush and sleep below */
1777
fd2ea0a7 1778 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1779
1780 /* disable transmits in the hardware */
1781 tctl = rd32(E1000_TCTL);
1782 tctl &= ~E1000_TCTL_EN;
1783 wr32(E1000_TCTL, tctl);
1784 /* flush both disables and wait for them to finish */
1785 wrfl();
0d451e79 1786 usleep_range(10000, 11000);
9d5c8243 1787
41f149a2
CW		 1788 igb_irq_disable(adapter);
1789
aa9b8cc4
AA		 1790 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1791
41f149a2
CW		 1792 for (i = 0; i < adapter->num_q_vectors; i++) {
1793 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1794 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1795 }
9d5c8243 1796
9d5c8243
AK		 1797
1798 del_timer_sync(&adapter->watchdog_timer);
1799 del_timer_sync(&adapter->phy_info_timer);
1800
9d5c8243 1801 netif_carrier_off(netdev);
04fe6358
AD		 1802
1803 /* record the stats before reset*/
12dcd86b
ED		 1804 spin_lock(&adapter->stats64_lock);
1805 igb_update_stats(adapter, &adapter->stats64);
1806 spin_unlock(&adapter->stats64_lock);
04fe6358 1807
9d5c8243
AK		 1808 adapter->link_speed = 0;
1809 adapter->link_duplex = 0;
1810
3023682e
JK		 1811 if (!pci_channel_offline(adapter->pdev))
1812 igb_reset(adapter);
9d5c8243
AK		 1813 igb_clean_all_tx_rings(adapter);
1814 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1815#ifdef CONFIG_IGB_DCA
1816
1817 /* since we reset the hardware DCA settings were cleared */
1818 igb_setup_dca(adapter);
1819#endif
9d5c8243
AK		 1820}
1821
1822void igb_reinit_locked(struct igb_adapter *adapter)
1823{
1824 WARN_ON(in_interrupt());
1825 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1826 usleep_range(1000, 2000);
9d5c8243
AK		 1827 igb_down(adapter);
1828 igb_up(adapter);
1829 clear_bit(__IGB_RESETTING, &adapter->state);
1830}
1831
56cec249
CW		 1832/** igb_enable_mas - Media Autosense re-enable after swap
1833 *
1834 * @adapter: adapter struct
1835 **/
1836static s32 igb_enable_mas(struct igb_adapter *adapter)
1837{
1838 struct e1000_hw *hw = &adapter->hw;
1839 u32 connsw;
1840 s32 ret_val = 0;
1841
1842 connsw = rd32(E1000_CONNSW);
1843 if (!(hw->phy.media_type == e1000_media_type_copper))
1844 return ret_val;
1845
1846 /* configure for SerDes media detect */
1847 if (!(connsw & E1000_CONNSW_SERDESD)) {
1848 connsw |= E1000_CONNSW_ENRGSRC;
1849 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1850 wr32(E1000_CONNSW, connsw);
1851 wrfl();
1852 } else if (connsw & E1000_CONNSW_SERDESD) {
1853 /* already SerDes, no need to enable anything */
1854 return ret_val;
1855 } else {
1856 netdev_info(adapter->netdev,
1857 "MAS: Unable to configure feature, disabling..\n");
1858 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1859 }
1860 return ret_val;
1861}
1862
9d5c8243
AK		 1863void igb_reset(struct igb_adapter *adapter)
1864{
090b1795 1865 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1866 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1867 struct e1000_mac_info *mac = &hw->mac;
1868 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1869 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1870
1871 /* Repartition Pba for greater than 9k mtu
1872 * To take effect CTRL.RST is required.
1873 */
fa4dfae0 1874 switch (mac->type) {
d2ba2ed8 1875 case e1000_i350:
ceb5f13b 1876 case e1000_i354:
55cac248
AD		 1877 case e1000_82580:
1878 pba = rd32(E1000_RXPBS);
1879 pba = igb_rxpbs_adjust_82580(pba);
1880 break;
fa4dfae0 1881 case e1000_82576:
d249be54
AD		 1882 pba = rd32(E1000_RXPBS);
1883 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1884 break;
1885 case e1000_82575:
f96a8a0b
CW		 1886 case e1000_i210:
1887 case e1000_i211:
fa4dfae0
AD		 1888 default:
1889 pba = E1000_PBA_34K;
1890 break;
2d064c06 1891 }
9d5c8243 1892
2d064c06
AD		 1893 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1894 (mac->type < e1000_82576)) {
9d5c8243
AK		 1895 /* adjust PBA for jumbo frames */
1896 wr32(E1000_PBA, pba);
1897
1898 /* To maintain wire speed transmits, the Tx FIFO should be
1899 * large enough to accommodate two full transmit packets,
1900 * rounded up to the next 1KB and expressed in KB. Likewise,
1901 * the Rx FIFO should be large enough to accommodate at least
1902 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1903 * expressed in KB.
1904 */
9d5c8243
AK		 1905 pba = rd32(E1000_PBA);
1906 /* upper 16 bits has Tx packet buffer allocation size in KB */
1907 tx_space = pba >> 16;
1908 /* lower 16 bits has Rx packet buffer allocation size in KB */
1909 pba &= 0xffff;
b980ac18
JK		 1910 /* the Tx fifo also stores 16 bytes of information about the Tx
1911 * but don't include ethernet FCS because hardware appends it
1912 */
9d5c8243 1913 min_tx_space = (adapter->max_frame_size +
85e8d004 1914 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1915 ETH_FCS_LEN) * 2;
1916 min_tx_space = ALIGN(min_tx_space, 1024);
1917 min_tx_space >>= 10;
1918 /* software strips receive CRC, so leave room for it */
1919 min_rx_space = adapter->max_frame_size;
1920 min_rx_space = ALIGN(min_rx_space, 1024);
1921 min_rx_space >>= 10;
1922
1923 /* If current Tx allocation is less than the min Tx FIFO size,
1924 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1925 * allocation, take space away from current Rx allocation
1926 */
9d5c8243
AK		 1927 if (tx_space < min_tx_space &&
1928 ((min_tx_space - tx_space) < pba)) {
1929 pba = pba - (min_tx_space - tx_space);
1930
b980ac18
JK		 1931 /* if short on Rx space, Rx wins and must trump Tx
1932 * adjustment
1933 */
9d5c8243
AK		 1934 if (pba < min_rx_space)
1935 pba = min_rx_space;
1936 }
2d064c06 1937 wr32(E1000_PBA, pba);
9d5c8243 1938 }
9d5c8243
AK		 1939
1940 /* flow control settings */
1941 /* The high water mark must be low enough to fit one full frame
1942 * (or the size used for early receive) above it in the Rx FIFO.
1943 * Set it to the lower of:
1944 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1945 * - the full Rx FIFO size minus one full frame
1946 */
9d5c8243 1947 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1948 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1949
d48507fe 1950 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1951 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1952 fc->pause_time = 0xFFFF;
1953 fc->send_xon = 1;
0cce119a 1954 fc->current_mode = fc->requested_mode;
9d5c8243 1955
4ae196df
AD		 1956 /* disable receive for all VFs and wait one second */
1957 if (adapter->vfs_allocated_count) {
1958 int i;
9005df38 1959
4ae196df 1960 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1961 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1962
1963 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1964 igb_ping_all_vfs(adapter);
4ae196df
AD		 1965
1966 /* disable transmits and receives */
1967 wr32(E1000_VFRE, 0);
1968 wr32(E1000_VFTE, 0);
1969 }
1970
9d5c8243 1971 /* Allow time for pending master requests to run */
330a6d6a 1972 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1973 wr32(E1000_WUC, 0);
1974
56cec249
CW		 1975 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1976 /* need to resetup here after media swap */
1977 adapter->ei.get_invariants(hw);
1978 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1979 }
1980 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1981 if (igb_enable_mas(adapter))
1982 dev_err(&pdev->dev,
1983 "Error enabling Media Auto Sense\n");
1984 }
330a6d6a 1985 if (hw->mac.ops.init_hw(hw))
090b1795 1986 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1987
b980ac18 1988 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1989 * control is off when forcing speed.
1990 */
1991 if (!hw->mac.autoneg)
1992 igb_force_mac_fc(hw);
1993
b6e0c419 1994 igb_init_dmac(adapter, pba);
e428893b
CW		 1995#ifdef CONFIG_IGB_HWMON
1996 /* Re-initialize the thermal sensor on i350 devices. */
1997 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1998 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1999 /* If present, re-initialize the external thermal sensor
2000 * interface.
2001 */
2002 if (adapter->ets)
2003 mac->ops.init_thermal_sensor_thresh(hw);
2004 }
2005 }
2006#endif
b936136d 2007 /* Re-establish EEE setting */
f4c01e96
CW		 2008 if (hw->phy.media_type == e1000_media_type_copper) {
2009 switch (mac->type) {
2010 case e1000_i350:
2011 case e1000_i210:
2012 case e1000_i211:
c4c112f1 2013 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2014 break;
2015 case e1000_i354:
c4c112f1 2016 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2017 break;
2018 default:
2019 break;
2020 }
2021 }
88a268c1
NN		 2022 if (!netif_running(adapter->netdev))
2023 igb_power_down_link(adapter);
2024
9d5c8243
AK		 2025 igb_update_mng_vlan(adapter);
2026
2027 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2028 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2029
1f6e8178
MV		 2030 /* Re-enable PTP, where applicable. */
2031 igb_ptp_reset(adapter);
1f6e8178 2032
330a6d6a 2033 igb_get_phy_info(hw);
9d5c8243
AK		 2034}
2035
c8f44aff
MM		 2036static netdev_features_t igb_fix_features(struct net_device *netdev,
2037 netdev_features_t features)
b2cb09b1 2038{
b980ac18
JK		 2039 /* Since there is no support for separate Rx/Tx vlan accel
2040 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2041 */
f646968f
PM		 2042 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2043 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2044 else
f646968f 2045 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2046
2047 return features;
2048}
2049
c8f44aff
MM		 2050static int igb_set_features(struct net_device *netdev,
2051 netdev_features_t features)
ac52caa3 2052{
c8f44aff 2053 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2054 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2055
f646968f 2056 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2057 igb_vlan_mode(netdev, features);
2058
89eaefb6
BG		 2059 if (!(changed & NETIF_F_RXALL))
2060 return 0;
2061
2062 netdev->features = features;
2063
2064 if (netif_running(netdev))
2065 igb_reinit_locked(adapter);
2066 else
2067 igb_reset(adapter);
2068
ac52caa3
MM		 2069 return 0;
2070}
2071
2e5c6922 2072static const struct net_device_ops igb_netdev_ops = {
559e9c49 2073 .ndo_open = igb_open,
2e5c6922 2074 .ndo_stop = igb_close,
cd392f5c 2075 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2076 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2077 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2078 .ndo_set_mac_address = igb_set_mac,
2079 .ndo_change_mtu = igb_change_mtu,
2080 .ndo_do_ioctl = igb_ioctl,
2081 .ndo_tx_timeout = igb_tx_timeout,
2082 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2083 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2084 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2085 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2086 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2087 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2088 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2089 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2090#ifdef CONFIG_NET_POLL_CONTROLLER
2091 .ndo_poll_controller = igb_netpoll,
2092#endif
b2cb09b1
JP		 2093 .ndo_fix_features = igb_fix_features,
2094 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2095};
2096
d67974f0
CW		 2097/**
2098 * igb_set_fw_version - Configure version string for ethtool
2099 * @adapter: adapter struct
d67974f0
CW		 2100 **/
2101void igb_set_fw_version(struct igb_adapter *adapter)
2102{
2103 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2104 struct e1000_fw_version fw;
2105
2106 igb_get_fw_version(hw, &fw);
2107
2108 switch (hw->mac.type) {
7dc98a62 2109 case e1000_i210:
0b1a6f2e 2110 case e1000_i211:
7dc98a62
CW		 2111 if (!(igb_get_flash_presence_i210(hw))) {
2112 snprintf(adapter->fw_version,
2113 sizeof(adapter->fw_version),
2114 "%2d.%2d-%d",
2115 fw.invm_major, fw.invm_minor,
2116 fw.invm_img_type);
2117 break;
2118 }
2119 /* fall through */
0b1a6f2e
CW		 2120 default:
2121 /* if option is rom valid, display its version too */
2122 if (fw.or_valid) {
2123 snprintf(adapter->fw_version,
2124 sizeof(adapter->fw_version),
2125 "%d.%d, 0x%08x, %d.%d.%d",
2126 fw.eep_major, fw.eep_minor, fw.etrack_id,
2127 fw.or_major, fw.or_build, fw.or_patch);
2128 /* no option rom */
7dc98a62 2129 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2130 snprintf(adapter->fw_version,
7dc98a62
CW		 2131 sizeof(adapter->fw_version),
2132 "%d.%d, 0x%08x",
2133 fw.eep_major, fw.eep_minor, fw.etrack_id);
2134 } else {
2135 snprintf(adapter->fw_version,
2136 sizeof(adapter->fw_version),
2137 "%d.%d.%d",
2138 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2139 }
2140 break;
d67974f0 2141 }
d67974f0
CW		 2142}
2143
56cec249
CW		 2144/**
2145 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2146 *
2147 * @adapter: adapter struct
2148 **/
2149static void igb_init_mas(struct igb_adapter *adapter)
2150{
2151 struct e1000_hw *hw = &adapter->hw;
2152 u16 eeprom_data;
2153
2154 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2155 switch (hw->bus.func) {
2156 case E1000_FUNC_0:
2157 if (eeprom_data & IGB_MAS_ENABLE_0) {
2158 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2159 netdev_info(adapter->netdev,
2160 "MAS: Enabling Media Autosense for port %d\n",
2161 hw->bus.func);
2162 }
2163 break;
2164 case E1000_FUNC_1:
2165 if (eeprom_data & IGB_MAS_ENABLE_1) {
2166 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2167 netdev_info(adapter->netdev,
2168 "MAS: Enabling Media Autosense for port %d\n",
2169 hw->bus.func);
2170 }
2171 break;
2172 case E1000_FUNC_2:
2173 if (eeprom_data & IGB_MAS_ENABLE_2) {
2174 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2175 netdev_info(adapter->netdev,
2176 "MAS: Enabling Media Autosense for port %d\n",
2177 hw->bus.func);
2178 }
2179 break;
2180 case E1000_FUNC_3:
2181 if (eeprom_data & IGB_MAS_ENABLE_3) {
2182 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2183 netdev_info(adapter->netdev,
2184 "MAS: Enabling Media Autosense for port %d\n",
2185 hw->bus.func);
2186 }
2187 break;
2188 default:
2189 /* Shouldn't get here */
2190 netdev_err(adapter->netdev,
2191 "MAS: Invalid port configuration, returning\n");
2192 break;
2193 }
2194}
2195
b980ac18
JK		 2196/**
2197 * igb_init_i2c - Init I2C interface
441fc6fd 2198 * @adapter: pointer to adapter structure
b980ac18 2199 **/
441fc6fd
CW		 2200static s32 igb_init_i2c(struct igb_adapter *adapter)
2201{
23d87824 2202 s32 status = 0;
441fc6fd
CW		 2203
2204 /* I2C interface supported on i350 devices */
2205 if (adapter->hw.mac.type != e1000_i350)
23d87824 2206 return 0;
441fc6fd
CW		 2207
2208 /* Initialize the i2c bus which is controlled by the registers.
2209 * This bus will use the i2c_algo_bit structue that implements
2210 * the protocol through toggling of the 4 bits in the register.
2211 */
2212 adapter->i2c_adap.owner = THIS_MODULE;
2213 adapter->i2c_algo = igb_i2c_algo;
2214 adapter->i2c_algo.data = adapter;
2215 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2216 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2217 strlcpy(adapter->i2c_adap.name, "igb BB",
2218 sizeof(adapter->i2c_adap.name));
2219 status = i2c_bit_add_bus(&adapter->i2c_adap);
2220 return status;
2221}
2222
9d5c8243 2223/**
b980ac18
JK		 2224 * igb_probe - Device Initialization Routine
2225 * @pdev: PCI device information struct
2226 * @ent: entry in igb_pci_tbl
9d5c8243 2227 *
b980ac18 2228 * Returns 0 on success, negative on failure
9d5c8243 2229 *
b980ac18
JK		 2230 * igb_probe initializes an adapter identified by a pci_dev structure.
2231 * The OS initialization, configuring of the adapter private structure,
2232 * and a hardware reset occur.
9d5c8243 2233 **/
1dd06ae8 2234static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2235{
2236 struct net_device *netdev;
2237 struct igb_adapter *adapter;
2238 struct e1000_hw *hw;
4337e993 2239 u16 eeprom_data = 0;
9835fd73 2240 s32 ret_val;
4337e993 2241 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2242 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2243 int err, pci_using_dac;
9835fd73 2244 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2245
bded64a7
AG		 2246 /* Catch broken hardware that put the wrong VF device ID in
2247 * the PCIe SR-IOV capability.
2248 */
2249 if (pdev->is_virtfn) {
2250 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2251 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2252 return -EINVAL;
2253 }
2254
aed5dec3 2255 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2256 if (err)
2257 return err;
2258
2259 pci_using_dac = 0;
dc4ff9bb 2260 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2261 if (!err) {
dc4ff9bb 2262 pci_using_dac = 1;
9d5c8243 2263 } else {
dc4ff9bb 2264 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2265 if (err) {
dc4ff9bb
RK		 2266 dev_err(&pdev->dev,
2267 "No usable DMA configuration, aborting\n");
2268 goto err_dma;
9d5c8243
AK		 2269 }
2270 }
2271
aed5dec3 2272 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2273 IORESOURCE_MEM),
2274 igb_driver_name);
9d5c8243
AK		 2275 if (err)
2276 goto err_pci_reg;
2277
19d5afd4 2278 pci_enable_pcie_error_reporting(pdev);
40a914fa 2279
9d5c8243 2280 pci_set_master(pdev);
c682fc23 2281 pci_save_state(pdev);
9d5c8243
AK		 2282
2283 err = -ENOMEM;
1bfaf07b 2284 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2285 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2286 if (!netdev)
2287 goto err_alloc_etherdev;
2288
2289 SET_NETDEV_DEV(netdev, &pdev->dev);
2290
2291 pci_set_drvdata(pdev, netdev);
2292 adapter = netdev_priv(netdev);
2293 adapter->netdev = netdev;
2294 adapter->pdev = pdev;
2295 hw = &adapter->hw;
2296 hw->back = adapter;
b3f4d599 2297 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2298
9d5c8243 2299 err = -EIO;
89dbefb2 2300 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2301 if (!hw->hw_addr)
9d5c8243
AK		 2302 goto err_ioremap;
2303
2e5c6922 2304 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2305 igb_set_ethtool_ops(netdev);
9d5c8243 2306 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2307
2308 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2309
89dbefb2
AS		 2310 netdev->mem_start = pci_resource_start(pdev, 0);
2311 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2312
9d5c8243
AK		 2313 /* PCI config space info */
2314 hw->vendor_id = pdev->vendor;
2315 hw->device_id = pdev->device;
2316 hw->revision_id = pdev->revision;
2317 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2318 hw->subsystem_device_id = pdev->subsystem_device;
2319
9d5c8243
AK		 2320 /* Copy the default MAC, PHY and NVM function pointers */
2321 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2322 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2323 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2324 /* Initialize skew-specific constants */
2325 err = ei->get_invariants(hw);
2326 if (err)
450c87c8 2327 goto err_sw_init;
9d5c8243 2328
450c87c8 2329 /* setup the private structure */
9d5c8243
AK		 2330 err = igb_sw_init(adapter);
2331 if (err)
2332 goto err_sw_init;
2333
2334 igb_get_bus_info_pcie(hw);
2335
2336 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2337
2338 /* Copper options */
2339 if (hw->phy.media_type == e1000_media_type_copper) {
2340 hw->phy.mdix = AUTO_ALL_MODES;
2341 hw->phy.disable_polarity_correction = false;
2342 hw->phy.ms_type = e1000_ms_hw_default;
2343 }
2344
2345 if (igb_check_reset_block(hw))
2346 dev_info(&pdev->dev,
2347 "PHY reset is blocked due to SOL/IDER session.\n");
2348
b980ac18 2349 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2350 * set by igb_sw_init so we should use an or instead of an
2351 * assignment.
2352 */
2353 netdev->features |= NETIF_F_SG |
2354 NETIF_F_IP_CSUM |
2355 NETIF_F_IPV6_CSUM |
2356 NETIF_F_TSO |
2357 NETIF_F_TSO6 |
2358 NETIF_F_RXHASH |
2359 NETIF_F_RXCSUM |
f646968f
PM		 2360 NETIF_F_HW_VLAN_CTAG_RX |
2361 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2362
2363 /* copy netdev features into list of user selectable features */
2364 netdev->hw_features |= netdev->features;
89eaefb6 2365 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2366
2367 /* set this bit last since it cannot be part of hw_features */
f646968f 2368 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2369
2370 netdev->vlan_features |= NETIF_F_TSO |
2371 NETIF_F_TSO6 |
2372 NETIF_F_IP_CSUM |
2373 NETIF_F_IPV6_CSUM |
2374 NETIF_F_SG;
48f29ffc 2375
6b8f0922
BG		 2376 netdev->priv_flags |= IFF_SUPP_NOFCS;
2377
7b872a55 2378 if (pci_using_dac) {
9d5c8243 2379 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2380 netdev->vlan_features |= NETIF_F_HIGHDMA;
2381 }
9d5c8243 2382
ac52caa3
MM		 2383 if (hw->mac.type >= e1000_82576) {
2384 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2385 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2386 }
b9473560 2387
01789349
JP		 2388 netdev->priv_flags |= IFF_UNICAST_FLT;
2389
330a6d6a 2390 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2391
2392 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2393 * known good starting state
2394 */
9d5c8243
AK		 2395 hw->mac.ops.reset_hw(hw);
2396
ef3a0092
CW		 2397 /* make sure the NVM is good , i211/i210 parts can have special NVM
2398 * that doesn't contain a checksum
f96a8a0b 2399 */
ef3a0092
CW		 2400 switch (hw->mac.type) {
2401 case e1000_i210:
2402 case e1000_i211:
2403 if (igb_get_flash_presence_i210(hw)) {
2404 if (hw->nvm.ops.validate(hw) < 0) {
2405 dev_err(&pdev->dev,
2406 "The NVM Checksum Is Not Valid\n");
2407 err = -EIO;
2408 goto err_eeprom;
2409 }
2410 }
2411 break;
2412 default:
f96a8a0b
CW		 2413 if (hw->nvm.ops.validate(hw) < 0) {
2414 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2415 err = -EIO;
2416 goto err_eeprom;
2417 }
ef3a0092 2418 break;
9d5c8243
AK		 2419 }
2420
2421 /* copy the MAC address out of the NVM */
2422 if (hw->mac.ops.read_mac_addr(hw))
2423 dev_err(&pdev->dev, "NVM Read Error\n");
2424
2425 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2426
aaeb6cdf 2427 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2428 dev_err(&pdev->dev, "Invalid MAC Address\n");
2429 err = -EIO;
2430 goto err_eeprom;
2431 }
2432
d67974f0
CW		 2433 /* get firmware version for ethtool -i */
2434 igb_set_fw_version(adapter);
2435
27dff8b2
TF		 2436 /* configure RXPBSIZE and TXPBSIZE */
2437 if (hw->mac.type == e1000_i210) {
2438 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2439 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2440 }
2441
c061b18d 2442 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2443 (unsigned long) adapter);
c061b18d 2444 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2445 (unsigned long) adapter);
9d5c8243
AK		 2446
2447 INIT_WORK(&adapter->reset_task, igb_reset_task);
2448 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2449
450c87c8 2450 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2451 adapter->fc_autoneg = true;
2452 hw->mac.autoneg = true;
2453 hw->phy.autoneg_advertised = 0x2f;
2454
0cce119a
AD		 2455 hw->fc.requested_mode = e1000_fc_default;
2456 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2457
9d5c8243
AK		 2458 igb_validate_mdi_setting(hw);
2459
63d4a8f9 2460 /* By default, support wake on port A */
a2cf8b6c 2461 if (hw->bus.func == 0)
63d4a8f9
MV		 2462 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2463
2464 /* Check the NVM for wake support on non-port A ports */
2465 if (hw->mac.type >= e1000_82580)
55cac248 2466 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2467 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2468 &eeprom_data);
a2cf8b6c
AD		 2469 else if (hw->bus.func == 1)
2470 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2471
63d4a8f9
MV		 2472 if (eeprom_data & IGB_EEPROM_APME)
2473 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2474
2475 /* now that we have the eeprom settings, apply the special cases where
2476 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2477 * lan on a particular port
2478 */
9d5c8243
AK		 2479 switch (pdev->device) {
2480 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2481 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2482 break;
2483 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2484 case E1000_DEV_ID_82576_FIBER:
2485 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2486 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2487 * regardless of eeprom setting
2488 */
9d5c8243 2489 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2490 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2491 break;
c8ea5ea9 2492 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2493 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2494 /* if quad port adapter, disable WoL on all but port A */
2495 if (global_quad_port_a != 0)
63d4a8f9 2496 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2497 else
2498 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2499 /* Reset for multiple quad port adapters */
2500 if (++global_quad_port_a == 4)
2501 global_quad_port_a = 0;
2502 break;
63d4a8f9
MV		 2503 default:
2504 /* If the device can't wake, don't set software support */
2505 if (!device_can_wakeup(&adapter->pdev->dev))
2506 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2507 }
2508
2509 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2510 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2511 adapter->wol |= E1000_WUFC_MAG;
2512
2513 /* Some vendors want WoL disabled by default, but still supported */
2514 if ((hw->mac.type == e1000_i350) &&
2515 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2516 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2517 adapter->wol = 0;
2518 }
2519
2520 device_set_wakeup_enable(&adapter->pdev->dev,
2521 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2522
2523 /* reset the hardware with the new settings */
2524 igb_reset(adapter);
2525
441fc6fd
CW		 2526 /* Init the I2C interface */
2527 err = igb_init_i2c(adapter);
2528 if (err) {
2529 dev_err(&pdev->dev, "failed to init i2c interface\n");
2530 goto err_eeprom;
2531 }
2532
9d5c8243 2533 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2534 * driver.
2535 */
9d5c8243
AK		 2536 igb_get_hw_control(adapter);
2537
9d5c8243
AK		 2538 strcpy(netdev->name, "eth%d");
2539 err = register_netdev(netdev);
2540 if (err)
2541 goto err_register;
2542
b168dfc5
JB		 2543 /* carrier off reporting is important to ethtool even BEFORE open */
2544 netif_carrier_off(netdev);
2545
421e02f0 2546#ifdef CONFIG_IGB_DCA
bbd98fe4 2547 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2548 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2549 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2550 igb_setup_dca(adapter);
2551 }
fe4506b6 2552
38c845c7 2553#endif
e428893b
CW		 2554#ifdef CONFIG_IGB_HWMON
2555 /* Initialize the thermal sensor on i350 devices. */
2556 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2557 u16 ets_word;
3c89f6d0 2558
b980ac18 2559 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2560 * external thermal sensor.
2561 */
2562 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2563 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2564 adapter->ets = true;
2565 else
2566 adapter->ets = false;
2567 if (igb_sysfs_init(adapter))
2568 dev_err(&pdev->dev,
2569 "failed to allocate sysfs resources\n");
2570 } else {
2571 adapter->ets = false;
2572 }
2573#endif
56cec249
CW		 2574 /* Check if Media Autosense is enabled */
2575 adapter->ei = *ei;
2576 if (hw->dev_spec._82575.mas_capable)
2577 igb_init_mas(adapter);
2578
673b8b70 2579 /* do hw tstamp init after resetting */
7ebae817 2580 igb_ptp_init(adapter);
673b8b70 2581
9d5c8243 2582 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2583 /* print bus type/speed/width info, not applicable to i354 */
2584 if (hw->mac.type != e1000_i354) {
2585 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2586 netdev->name,
2587 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2588 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2589 "unknown"),
2590 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2591 "Width x4" :
2592 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2593 "Width x2" :
2594 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2595 "Width x1" : "unknown"), netdev->dev_addr);
2596 }
9d5c8243 2597
53ea6c7e
TF		 2598 if ((hw->mac.type >= e1000_i210 ||
2599 igb_get_flash_presence_i210(hw))) {
2600 ret_val = igb_read_part_string(hw, part_str,
2601 E1000_PBANUM_LENGTH);
2602 } else {
2603 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2604 }
2605
9835fd73
CW		 2606 if (ret_val)
2607 strcpy(part_str, "Unknown");
2608 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2609 dev_info(&pdev->dev,
2610 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2611 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2612 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2613 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2614 if (hw->phy.media_type == e1000_media_type_copper) {
2615 switch (hw->mac.type) {
2616 case e1000_i350:
2617 case e1000_i210:
2618 case e1000_i211:
2619 /* Enable EEE for internal copper PHY devices */
c4c112f1 2620 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2621 if ((!err) &&
2622 (!hw->dev_spec._82575.eee_disable)) {
2623 adapter->eee_advert =
2624 MDIO_EEE_100TX | MDIO_EEE_1000T;
2625 adapter->flags |= IGB_FLAG_EEE;
2626 }
2627 break;
2628 case e1000_i354:
ceb5f13b 2629 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2630 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2631 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2632 if ((!err) &&
2633 (!hw->dev_spec._82575.eee_disable)) {
2634 adapter->eee_advert =
2635 MDIO_EEE_100TX | MDIO_EEE_1000T;
2636 adapter->flags |= IGB_FLAG_EEE;
2637 }
2638 }
2639 break;
2640 default:
2641 break;
ceb5f13b 2642 }
09b068d4 2643 }
749ab2cd 2644 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2645 return 0;
2646
2647err_register:
2648 igb_release_hw_control(adapter);
441fc6fd 2649 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2650err_eeprom:
2651 if (!igb_check_reset_block(hw))
f5f4cf08 2652 igb_reset_phy(hw);
9d5c8243
AK		 2653
2654 if (hw->flash_address)
2655 iounmap(hw->flash_address);
9d5c8243 2656err_sw_init:
047e0030 2657 igb_clear_interrupt_scheme(adapter);
75009b3a 2658 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2659err_ioremap:
2660 free_netdev(netdev);
2661err_alloc_etherdev:
559e9c49 2662 pci_release_selected_regions(pdev,
b980ac18 2663 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2664err_pci_reg:
2665err_dma:
2666 pci_disable_device(pdev);
2667 return err;
2668}
2669
fa44f2f1 2670#ifdef CONFIG_PCI_IOV
781798a1 2671static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2672{
2673 struct net_device *netdev = pci_get_drvdata(pdev);
2674 struct igb_adapter *adapter = netdev_priv(netdev);
2675 struct e1000_hw *hw = &adapter->hw;
2676
2677 /* reclaim resources allocated to VFs */
2678 if (adapter->vf_data) {
2679 /* disable iov and allow time for transactions to clear */
b09186d2 2680 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2681 dev_warn(&pdev->dev,
2682 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2683 return -EPERM;
2684 } else {
2685 pci_disable_sriov(pdev);
2686 msleep(500);
2687 }
2688
2689 kfree(adapter->vf_data);
2690 adapter->vf_data = NULL;
2691 adapter->vfs_allocated_count = 0;
2692 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2693 wrfl();
2694 msleep(100);
2695 dev_info(&pdev->dev, "IOV Disabled\n");
2696
2697 /* Re-enable DMA Coalescing flag since IOV is turned off */
2698 adapter->flags |= IGB_FLAG_DMAC;
2699 }
2700
2701 return 0;
2702}
2703
2704static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2705{
2706 struct net_device *netdev = pci_get_drvdata(pdev);
2707 struct igb_adapter *adapter = netdev_priv(netdev);
2708 int old_vfs = pci_num_vf(pdev);
2709 int err = 0;
2710 int i;
2711
cd14ef54 2712 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2713 err = -EPERM;
2714 goto out;
2715 }
fa44f2f1
GR		 2716 if (!num_vfs)
2717 goto out;
fa44f2f1 2718
781798a1
SA		 2719 if (old_vfs) {
2720 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2721 old_vfs, max_vfs);
2722 adapter->vfs_allocated_count = old_vfs;
2723 } else
2724 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2725
2726 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2727 sizeof(struct vf_data_storage), GFP_KERNEL);
2728
2729 /* if allocation failed then we do not support SR-IOV */
2730 if (!adapter->vf_data) {
2731 adapter->vfs_allocated_count = 0;
2732 dev_err(&pdev->dev,
2733 "Unable to allocate memory for VF Data Storage\n");
2734 err = -ENOMEM;
2735 goto out;
2736 }
2737
781798a1
SA		 2738 /* only call pci_enable_sriov() if no VFs are allocated already */
2739 if (!old_vfs) {
2740 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2741 if (err)
2742 goto err_out;
2743 }
fa44f2f1
GR		 2744 dev_info(&pdev->dev, "%d VFs allocated\n",
2745 adapter->vfs_allocated_count);
2746 for (i = 0; i < adapter->vfs_allocated_count; i++)
2747 igb_vf_configure(adapter, i);
2748
2749 /* DMA Coalescing is not supported in IOV mode. */
2750 adapter->flags &= ~IGB_FLAG_DMAC;
2751 goto out;
2752
2753err_out:
2754 kfree(adapter->vf_data);
2755 adapter->vf_data = NULL;
2756 adapter->vfs_allocated_count = 0;
2757out:
2758 return err;
2759}
2760
2761#endif
b980ac18 2762/**
441fc6fd
CW		 2763 * igb_remove_i2c - Cleanup I2C interface
2764 * @adapter: pointer to adapter structure
b980ac18 2765 **/
441fc6fd
CW		 2766static void igb_remove_i2c(struct igb_adapter *adapter)
2767{
441fc6fd
CW		 2768 /* free the adapter bus structure */
2769 i2c_del_adapter(&adapter->i2c_adap);
2770}
2771
9d5c8243 2772/**
b980ac18
JK		 2773 * igb_remove - Device Removal Routine
2774 * @pdev: PCI device information struct
9d5c8243 2775 *
b980ac18
JK		 2776 * igb_remove is called by the PCI subsystem to alert the driver
2777 * that it should release a PCI device. The could be caused by a
2778 * Hot-Plug event, or because the driver is going to be removed from
2779 * memory.
9d5c8243 2780 **/
9f9a12f8 2781static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2782{
2783 struct net_device *netdev = pci_get_drvdata(pdev);
2784 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2785 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2786
749ab2cd 2787 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2788#ifdef CONFIG_IGB_HWMON
2789 igb_sysfs_exit(adapter);
2790#endif
441fc6fd 2791 igb_remove_i2c(adapter);
a79f4f88 2792 igb_ptp_stop(adapter);
b980ac18 2793 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2794 * disable watchdog from being rescheduled.
2795 */
9d5c8243
AK		 2796 set_bit(__IGB_DOWN, &adapter->state);
2797 del_timer_sync(&adapter->watchdog_timer);
2798 del_timer_sync(&adapter->phy_info_timer);
2799
760141a5
TH		 2800 cancel_work_sync(&adapter->reset_task);
2801 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2802
421e02f0 2803#ifdef CONFIG_IGB_DCA
7dfc16fa 2804 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2805 dev_info(&pdev->dev, "DCA disabled\n");
2806 dca_remove_requester(&pdev->dev);
7dfc16fa 2807 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2808 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2809 }
2810#endif
2811
9d5c8243 2812 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2813 * would have already happened in close and is redundant.
2814 */
9d5c8243
AK		 2815 igb_release_hw_control(adapter);
2816
2817 unregister_netdev(netdev);
2818
047e0030 2819 igb_clear_interrupt_scheme(adapter);
9d5c8243 2820
37680117 2821#ifdef CONFIG_PCI_IOV
fa44f2f1 2822 igb_disable_sriov(pdev);
37680117 2823#endif
559e9c49 2824
75009b3a 2825 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2826 if (hw->flash_address)
2827 iounmap(hw->flash_address);
559e9c49 2828 pci_release_selected_regions(pdev,
b980ac18 2829 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2830
1128c756 2831 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2832 free_netdev(netdev);
2833
19d5afd4 2834 pci_disable_pcie_error_reporting(pdev);
40a914fa 2835
9d5c8243
AK		 2836 pci_disable_device(pdev);
2837}
2838
a6b623e0 2839/**
b980ac18
JK		 2840 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2841 * @adapter: board private structure to initialize
a6b623e0 2842 *
b980ac18
JK		 2843 * This function initializes the vf specific data storage and then attempts to
2844 * allocate the VFs. The reason for ordering it this way is because it is much
2845 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2846 * the memory for the VFs.
a6b623e0 2847 **/
9f9a12f8 2848static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2849{
2850#ifdef CONFIG_PCI_IOV
2851 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2852 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2853
f96a8a0b
CW		 2854 /* Virtualization features not supported on i210 family. */
2855 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2856 return;
2857
fa44f2f1 2858 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2859 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2860
a6b623e0
AD		 2861#endif /* CONFIG_PCI_IOV */
2862}
2863
fa44f2f1 2864static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2865{
2866 struct e1000_hw *hw = &adapter->hw;
374a542d 2867 u32 max_rss_queues;
9d5c8243 2868
374a542d 2869 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2870 switch (hw->mac.type) {
374a542d
MV		 2871 case e1000_i211:
2872 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2873 break;
2874 case e1000_82575:
f96a8a0b 2875 case e1000_i210:
374a542d
MV		 2876 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2877 break;
2878 case e1000_i350:
2879 /* I350 cannot do RSS and SR-IOV at the same time */
2880 if (!!adapter->vfs_allocated_count) {
2881 max_rss_queues = 1;
2882 break;
2883 }
2884 /* fall through */
2885 case e1000_82576:
2886 if (!!adapter->vfs_allocated_count) {
2887 max_rss_queues = 2;
2888 break;
2889 }
2890 /* fall through */
2891 case e1000_82580:
ceb5f13b 2892 case e1000_i354:
374a542d
MV		 2893 default:
2894 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2895 break;
374a542d
MV		 2896 }
2897
2898 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2899
2900 /* Determine if we need to pair queues. */
2901 switch (hw->mac.type) {
2902 case e1000_82575:
f96a8a0b 2903 case e1000_i211:
374a542d 2904 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2905 break;
374a542d 2906 case e1000_82576:
b980ac18 2907 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2908 * should pair the queues in order to conserve interrupts due
2909 * to limited supply.
2910 */
2911 if ((adapter->rss_queues > 1) &&
2912 (adapter->vfs_allocated_count > 6))
2913 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2914 /* fall through */
2915 case e1000_82580:
2916 case e1000_i350:
ceb5f13b 2917 case e1000_i354:
374a542d 2918 case e1000_i210:
f96a8a0b 2919 default:
b980ac18 2920 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2921 * order to conserve interrupts due to limited supply.
2922 */
2923 if (adapter->rss_queues > (max_rss_queues / 2))
2924 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2925 break;
2926 }
fa44f2f1
GR		 2927}
2928
2929/**
b980ac18
JK		 2930 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2931 * @adapter: board private structure to initialize
fa44f2f1 2932 *
b980ac18
JK		 2933 * igb_sw_init initializes the Adapter private data structure.
2934 * Fields are initialized based on PCI device information and
2935 * OS network device settings (MTU size).
fa44f2f1
GR		 2936 **/
2937static int igb_sw_init(struct igb_adapter *adapter)
2938{
2939 struct e1000_hw *hw = &adapter->hw;
2940 struct net_device *netdev = adapter->netdev;
2941 struct pci_dev *pdev = adapter->pdev;
2942
2943 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2944
2945 /* set default ring sizes */
2946 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2947 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2948
2949 /* set default ITR values */
2950 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2951 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2952
2953 /* set default work limits */
2954 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2955
2956 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2957 VLAN_HLEN;
2958 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2959
2960 spin_lock_init(&adapter->stats64_lock);
2961#ifdef CONFIG_PCI_IOV
2962 switch (hw->mac.type) {
2963 case e1000_82576:
2964 case e1000_i350:
2965 if (max_vfs > 7) {
2966 dev_warn(&pdev->dev,
2967 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2968 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2969 } else
2970 adapter->vfs_allocated_count = max_vfs;
2971 if (adapter->vfs_allocated_count)
2972 dev_warn(&pdev->dev,
2973 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2974 break;
2975 default:
2976 break;
2977 }
2978#endif /* CONFIG_PCI_IOV */
2979
2980 igb_init_queue_configuration(adapter);
a99955fc 2981
1128c756 2982 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2983 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2984 GFP_ATOMIC);
1128c756 2985
a6b623e0 2986 /* This call may decrease the number of queues */
53c7d064 2987 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2988 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2989 return -ENOMEM;
2990 }
2991
a6b623e0
AD		 2992 igb_probe_vfs(adapter);
2993
9d5c8243
AK		 2994 /* Explicitly disable IRQ since the NIC can be in any state. */
2995 igb_irq_disable(adapter);
2996
f96a8a0b 2997 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2998 adapter->flags &= ~IGB_FLAG_DMAC;
2999
9d5c8243
AK		 3000 set_bit(__IGB_DOWN, &adapter->state);
3001 return 0;
3002}
3003
3004/**
b980ac18
JK		 3005 * igb_open - Called when a network interface is made active
3006 * @netdev: network interface device structure
9d5c8243 3007 *
b980ac18 3008 * Returns 0 on success, negative value on failure
9d5c8243 3009 *
b980ac18
JK		 3010 * The open entry point is called when a network interface is made
3011 * active by the system (IFF_UP). At this point all resources needed
3012 * for transmit and receive operations are allocated, the interrupt
3013 * handler is registered with the OS, the watchdog timer is started,
3014 * and the stack is notified that the interface is ready.
9d5c8243 3015 **/
749ab2cd 3016static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3017{
3018 struct igb_adapter *adapter = netdev_priv(netdev);
3019 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3020 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3021 int err;
3022 int i;
3023
3024 /* disallow open during test */
749ab2cd
YZ		 3025 if (test_bit(__IGB_TESTING, &adapter->state)) {
3026 WARN_ON(resuming);
9d5c8243 3027 return -EBUSY;
749ab2cd
YZ		 3028 }
3029
3030 if (!resuming)
3031 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3032
b168dfc5
JB		 3033 netif_carrier_off(netdev);
3034
9d5c8243
AK		 3035 /* allocate transmit descriptors */
3036 err = igb_setup_all_tx_resources(adapter);
3037 if (err)
3038 goto err_setup_tx;
3039
3040 /* allocate receive descriptors */
3041 err = igb_setup_all_rx_resources(adapter);
3042 if (err)
3043 goto err_setup_rx;
3044
88a268c1 3045 igb_power_up_link(adapter);
9d5c8243 3046
9d5c8243
AK		 3047 /* before we allocate an interrupt, we must be ready to handle it.
3048 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3049 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3050 * clean_rx handler before we do so.
3051 */
9d5c8243
AK		 3052 igb_configure(adapter);
3053
3054 err = igb_request_irq(adapter);
3055 if (err)
3056 goto err_req_irq;
3057
0c2cc02e
AD		 3058 /* Notify the stack of the actual queue counts. */
3059 err = netif_set_real_num_tx_queues(adapter->netdev,
3060 adapter->num_tx_queues);
3061 if (err)
3062 goto err_set_queues;
3063
3064 err = netif_set_real_num_rx_queues(adapter->netdev,
3065 adapter->num_rx_queues);
3066 if (err)
3067 goto err_set_queues;
3068
9d5c8243
AK		 3069 /* From here on the code is the same as igb_up() */
3070 clear_bit(__IGB_DOWN, &adapter->state);
3071
0d1ae7f4
AD		 3072 for (i = 0; i < adapter->num_q_vectors; i++)
3073 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3074
3075 /* Clear any pending interrupts. */
3076 rd32(E1000_ICR);
844290e5
PW		 3077
3078 igb_irq_enable(adapter);
3079
d4960307
AD		 3080 /* notify VFs that reset has been completed */
3081 if (adapter->vfs_allocated_count) {
3082 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3083
d4960307
AD		 3084 reg_data |= E1000_CTRL_EXT_PFRSTD;
3085 wr32(E1000_CTRL_EXT, reg_data);
3086 }
3087
d55b53ff
JK		 3088 netif_tx_start_all_queues(netdev);
3089
749ab2cd
YZ		 3090 if (!resuming)
3091 pm_runtime_put(&pdev->dev);
3092
25568a53
AD		 3093 /* start the watchdog. */
3094 hw->mac.get_link_status = 1;
3095 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3096
3097 return 0;
3098
0c2cc02e
AD		 3099err_set_queues:
3100 igb_free_irq(adapter);
9d5c8243
AK		 3101err_req_irq:
3102 igb_release_hw_control(adapter);
88a268c1 3103 igb_power_down_link(adapter);
9d5c8243
AK		 3104 igb_free_all_rx_resources(adapter);
3105err_setup_rx:
3106 igb_free_all_tx_resources(adapter);
3107err_setup_tx:
3108 igb_reset(adapter);
749ab2cd
YZ		 3109 if (!resuming)
3110 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3111
3112 return err;
3113}
3114
749ab2cd
YZ		 3115static int igb_open(struct net_device *netdev)
3116{
3117 return __igb_open(netdev, false);
3118}
3119
9d5c8243 3120/**
b980ac18
JK		 3121 * igb_close - Disables a network interface
3122 * @netdev: network interface device structure
9d5c8243 3123 *
b980ac18 3124 * Returns 0, this is not allowed to fail
9d5c8243 3125 *
b980ac18
JK		 3126 * The close entry point is called when an interface is de-activated
3127 * by the OS. The hardware is still under the driver's control, but
3128 * needs to be disabled. A global MAC reset is issued to stop the
3129 * hardware, and all transmit and receive resources are freed.
9d5c8243 3130 **/
749ab2cd 3131static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3132{
3133 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3134 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3135
3136 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3137
749ab2cd
YZ		 3138 if (!suspending)
3139 pm_runtime_get_sync(&pdev->dev);
3140
3141 igb_down(adapter);
9d5c8243
AK		 3142 igb_free_irq(adapter);
3143
3144 igb_free_all_tx_resources(adapter);
3145 igb_free_all_rx_resources(adapter);
3146
749ab2cd
YZ		 3147 if (!suspending)
3148 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3149 return 0;
3150}
3151
749ab2cd
YZ		 3152static int igb_close(struct net_device *netdev)
3153{
3154 return __igb_close(netdev, false);
3155}
3156
9d5c8243 3157/**
b980ac18
JK		 3158 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3159 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3160 *
b980ac18 3161 * Return 0 on success, negative on failure
9d5c8243 3162 **/
80785298 3163int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3164{
59d71989 3165 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3166 int size;
3167
06034649 3168 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3169
3170 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3171 if (!tx_ring->tx_buffer_info)
9d5c8243 3172 goto err;
9d5c8243
AK		 3173
3174 /* round up to nearest 4K */
85e8d004 3175 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3176 tx_ring->size = ALIGN(tx_ring->size, 4096);
3177
5536d210
AD		 3178 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3179 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3180 if (!tx_ring->desc)
3181 goto err;
3182
9d5c8243
AK		 3183 tx_ring->next_to_use = 0;
3184 tx_ring->next_to_clean = 0;
81c2fc22 3185
9d5c8243
AK		 3186 return 0;
3187
3188err:
06034649 3189 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3190 tx_ring->tx_buffer_info = NULL;
3191 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3192 return -ENOMEM;
3193}
3194
3195/**
b980ac18
JK		 3196 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3197 * (Descriptors) for all queues
3198 * @adapter: board private structure
9d5c8243 3199 *
b980ac18 3200 * Return 0 on success, negative on failure
9d5c8243
AK		 3201 **/
3202static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3203{
439705e1 3204 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3205 int i, err = 0;
3206
3207 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3208 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3209 if (err) {
439705e1 3210 dev_err(&pdev->dev,
9d5c8243
AK		 3211 "Allocation for Tx Queue %u failed\n", i);
3212 for (i--; i >= 0; i--)
3025a446 3213 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3214 break;
3215 }
3216 }
3217
3218 return err;
3219}
3220
3221/**
b980ac18
JK		 3222 * igb_setup_tctl - configure the transmit control registers
3223 * @adapter: Board private structure
9d5c8243 3224 **/
d7ee5b3a 3225void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3226{
9d5c8243
AK		 3227 struct e1000_hw *hw = &adapter->hw;
3228 u32 tctl;
9d5c8243 3229
85b430b4
AD		 3230 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3231 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3232
3233 /* Program the Transmit Control Register */
9d5c8243
AK		 3234 tctl = rd32(E1000_TCTL);
3235 tctl &= ~E1000_TCTL_CT;
3236 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3237 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3238
3239 igb_config_collision_dist(hw);
3240
9d5c8243
AK		 3241 /* Enable transmits */
3242 tctl |= E1000_TCTL_EN;
3243
3244 wr32(E1000_TCTL, tctl);
3245}
3246
85b430b4 3247/**
b980ac18
JK		 3248 * igb_configure_tx_ring - Configure transmit ring after Reset
3249 * @adapter: board private structure
3250 * @ring: tx ring to configure
85b430b4 3251 *
b980ac18 3252 * Configure a transmit ring after a reset.
85b430b4 3253 **/
d7ee5b3a 3254void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3255 struct igb_ring *ring)
85b430b4
AD		 3256{
3257 struct e1000_hw *hw = &adapter->hw;
a74420e0 3258 u32 txdctl = 0;
85b430b4
AD		 3259 u64 tdba = ring->dma;
3260 int reg_idx = ring->reg_idx;
3261
3262 /* disable the queue */
a74420e0 3263 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3264 wrfl();
3265 mdelay(10);
3266
3267 wr32(E1000_TDLEN(reg_idx),
b980ac18 3268 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3269 wr32(E1000_TDBAL(reg_idx),
b980ac18 3270 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3271 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3272
fce99e34 3273 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3274 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3275 writel(0, ring->tail);
85b430b4
AD		 3276
3277 txdctl |= IGB_TX_PTHRESH;
3278 txdctl |= IGB_TX_HTHRESH << 8;
3279 txdctl |= IGB_TX_WTHRESH << 16;
3280
3281 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3282 wr32(E1000_TXDCTL(reg_idx), txdctl);
3283}
3284
3285/**
b980ac18
JK		 3286 * igb_configure_tx - Configure transmit Unit after Reset
3287 * @adapter: board private structure
85b430b4 3288 *
b980ac18 3289 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3290 **/
3291static void igb_configure_tx(struct igb_adapter *adapter)
3292{
3293 int i;
3294
3295 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3296 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3297}
3298
9d5c8243 3299/**
b980ac18
JK		 3300 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3301 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3302 *
b980ac18 3303 * Returns 0 on success, negative on failure
9d5c8243 3304 **/
80785298 3305int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3306{
59d71989 3307 struct device *dev = rx_ring->dev;
f33005a6 3308 int size;
9d5c8243 3309
06034649 3310 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3311
3312 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3313 if (!rx_ring->rx_buffer_info)
9d5c8243 3314 goto err;
9d5c8243 3315
9d5c8243 3316 /* Round up to nearest 4K */
f33005a6 3317 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3318 rx_ring->size = ALIGN(rx_ring->size, 4096);
3319
5536d210
AD		 3320 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3321 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3322 if (!rx_ring->desc)
3323 goto err;
3324
cbc8e55f 3325 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3326 rx_ring->next_to_clean = 0;
3327 rx_ring->next_to_use = 0;
9d5c8243 3328
9d5c8243
AK		 3329 return 0;
3330
3331err:
06034649
AD		 3332 vfree(rx_ring->rx_buffer_info);
3333 rx_ring->rx_buffer_info = NULL;
f33005a6 3334 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3335 return -ENOMEM;
3336}
3337
3338/**
b980ac18
JK		 3339 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3340 * (Descriptors) for all queues
3341 * @adapter: board private structure
9d5c8243 3342 *
b980ac18 3343 * Return 0 on success, negative on failure
9d5c8243
AK		 3344 **/
3345static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3346{
439705e1 3347 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3348 int i, err = 0;
3349
3350 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3351 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3352 if (err) {
439705e1 3353 dev_err(&pdev->dev,
9d5c8243
AK		 3354 "Allocation for Rx Queue %u failed\n", i);
3355 for (i--; i >= 0; i--)
3025a446 3356 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3357 break;
3358 }
3359 }
3360
3361 return err;
3362}
3363
06cf2666 3364/**
b980ac18
JK		 3365 * igb_setup_mrqc - configure the multiple receive queue control registers
3366 * @adapter: Board private structure
06cf2666
AD		 3367 **/
3368static void igb_setup_mrqc(struct igb_adapter *adapter)
3369{
3370 struct e1000_hw *hw = &adapter->hw;
3371 u32 mrqc, rxcsum;
ed12cc9a 3372 u32 j, num_rx_queues;
a57fe23e
AD		 3373 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3374 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3375 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3376 0xFA01ACBE };
06cf2666
AD		 3377
3378 /* Fill out hash function seeds */
a57fe23e
AD		 3379 for (j = 0; j < 10; j++)
3380 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3381
a99955fc 3382 num_rx_queues = adapter->rss_queues;
06cf2666 3383
797fd4be 3384 switch (hw->mac.type) {
797fd4be
AD		 3385 case e1000_82576:
3386 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3387 if (adapter->vfs_allocated_count)
06cf2666 3388 num_rx_queues = 2;
797fd4be
AD		 3389 break;
3390 default:
3391 break;
06cf2666
AD		 3392 }
3393
ed12cc9a
LMV		 3394 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3395 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3396 adapter->rss_indir_tbl[j] =
3397 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3398 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3399 }
ed12cc9a 3400 igb_write_rss_indir_tbl(adapter);
06cf2666 3401
b980ac18 3402 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3403 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3404 * offloads as they are enabled by default
3405 */
3406 rxcsum = rd32(E1000_RXCSUM);
3407 rxcsum |= E1000_RXCSUM_PCSD;
3408
3409 if (adapter->hw.mac.type >= e1000_82576)
3410 /* Enable Receive Checksum Offload for SCTP */
3411 rxcsum |= E1000_RXCSUM_CRCOFL;
3412
3413 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3414 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3415
039454a8
AA		 3416 /* Generate RSS hash based on packet types, TCP/UDP
3417 * port numbers and/or IPv4/v6 src and dst addresses
3418 */
f96a8a0b
CW		 3419 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3420 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3421 E1000_MRQC_RSS_FIELD_IPV6 |
3422 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3424
039454a8
AA		 3425 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3426 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3427 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3428 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3429
06cf2666
AD		 3430 /* If VMDq is enabled then we set the appropriate mode for that, else
3431 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3432 * if we are only using one queue
3433 */
06cf2666
AD		 3434 if (adapter->vfs_allocated_count) {
3435 if (hw->mac.type > e1000_82575) {
3436 /* Set the default pool for the PF's first queue */
3437 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3438
06cf2666
AD		 3439 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3440 E1000_VT_CTL_DISABLE_DEF_POOL);
3441 vtctl |= adapter->vfs_allocated_count <<
3442 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3443 wr32(E1000_VT_CTL, vtctl);
3444 }
a99955fc 3445 if (adapter->rss_queues > 1)
f96a8a0b 3446 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3447 else
f96a8a0b 3448 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3449 } else {
f96a8a0b
CW		 3450 if (hw->mac.type != e1000_i211)
3451 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3452 }
3453 igb_vmm_control(adapter);
3454
06cf2666
AD		 3455 wr32(E1000_MRQC, mrqc);
3456}
3457
9d5c8243 3458/**
b980ac18
JK		 3459 * igb_setup_rctl - configure the receive control registers
3460 * @adapter: Board private structure
9d5c8243 3461 **/
d7ee5b3a 3462void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3463{
3464 struct e1000_hw *hw = &adapter->hw;
3465 u32 rctl;
9d5c8243
AK		 3466
3467 rctl = rd32(E1000_RCTL);
3468
3469 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3470 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3471
69d728ba 3472 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3473 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3474
b980ac18 3475 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3476 * redirection as it did with e1000. Newer features require
3477 * that the HW strips the CRC.
73cd78f1 3478 */
87cb7e8c 3479 rctl |= E1000_RCTL_SECRC;
9d5c8243 3480
559e9c49 3481 /* disable store bad packets and clear size bits. */
ec54d7d6 3482 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3483
6ec43fe6
AD		 3484 /* enable LPE to prevent packets larger than max_frame_size */
3485 rctl |= E1000_RCTL_LPE;
9d5c8243 3486
952f72a8
AD		 3487 /* disable queue 0 to prevent tail write w/o re-config */
3488 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3489
e1739522
AD		 3490 /* Attention!!! For SR-IOV PF driver operations you must enable
3491 * queue drop for all VF and PF queues to prevent head of line blocking
3492 * if an un-trusted VF does not provide descriptors to hardware.
3493 */
3494 if (adapter->vfs_allocated_count) {
e1739522
AD		 3495 /* set all queue drop enable bits */
3496 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3497 }
3498
89eaefb6
BG		 3499 /* This is useful for sniffing bad packets. */
3500 if (adapter->netdev->features & NETIF_F_RXALL) {
3501 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3502 * in e1000e_set_rx_mode
3503 */
89eaefb6
BG		 3504 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3505 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3506 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3507
3508 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3509 E1000_RCTL_DPF | /* Allow filtered pause */
3510 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3511 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3512 * and that breaks VLANs.
3513 */
3514 }
3515
9d5c8243
AK		 3516 wr32(E1000_RCTL, rctl);
3517}
3518
7d5753f0 3519static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3520 int vfn)
7d5753f0
AD		 3521{
3522 struct e1000_hw *hw = &adapter->hw;
3523 u32 vmolr;
3524
3525 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3526 * increase the size to support vlan tags
3527 */
7d5753f0
AD		 3528 if (vfn < adapter->vfs_allocated_count &&
3529 adapter->vf_data[vfn].vlans_enabled)
3530 size += VLAN_TAG_SIZE;
3531
3532 vmolr = rd32(E1000_VMOLR(vfn));
3533 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3534 vmolr |= size | E1000_VMOLR_LPE;
3535 wr32(E1000_VMOLR(vfn), vmolr);
3536
3537 return 0;
3538}
3539
e1739522 3540/**
b980ac18
JK		 3541 * igb_rlpml_set - set maximum receive packet size
3542 * @adapter: board private structure
e1739522 3543 *
b980ac18 3544 * Configure maximum receivable packet size.
e1739522
AD		 3545 **/
3546static void igb_rlpml_set(struct igb_adapter *adapter)
3547{
153285f9 3548 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3549 struct e1000_hw *hw = &adapter->hw;
3550 u16 pf_id = adapter->vfs_allocated_count;
3551
e1739522
AD		 3552 if (pf_id) {
3553 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3554 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3555 * to our max jumbo frame size, in case we need to enable
3556 * jumbo frames on one of the rings later.
3557 * This will not pass over-length frames into the default
3558 * queue because it's gated by the VMOLR.RLPML.
3559 */
7d5753f0 3560 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3561 }
3562
3563 wr32(E1000_RLPML, max_frame_size);
3564}
3565
8151d294
WM		 3566static inline void igb_set_vmolr(struct igb_adapter *adapter,
3567 int vfn, bool aupe)
7d5753f0
AD		 3568{
3569 struct e1000_hw *hw = &adapter->hw;
3570 u32 vmolr;
3571
b980ac18 3572 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3573 * we should exit and do nothing
3574 */
3575 if (hw->mac.type < e1000_82576)
3576 return;
3577
3578 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3579 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3580 if (hw->mac.type == e1000_i350) {
3581 u32 dvmolr;
3582
3583 dvmolr = rd32(E1000_DVMOLR(vfn));
3584 dvmolr |= E1000_DVMOLR_STRVLAN;
3585 wr32(E1000_DVMOLR(vfn), dvmolr);
3586 }
8151d294 3587 if (aupe)
b980ac18 3588 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3589 else
3590 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3591
3592 /* clear all bits that might not be set */
3593 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3594
a99955fc 3595 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3596 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3597 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3598 * multicast packets
3599 */
3600 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3601 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3602
3603 wr32(E1000_VMOLR(vfn), vmolr);
3604}
3605
85b430b4 3606/**
b980ac18
JK		 3607 * igb_configure_rx_ring - Configure a receive ring after Reset
3608 * @adapter: board private structure
3609 * @ring: receive ring to be configured
85b430b4 3610 *
b980ac18 3611 * Configure the Rx unit of the MAC after a reset.
85b430b4 3612 **/
d7ee5b3a 3613void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3614 struct igb_ring *ring)
85b430b4
AD		 3615{
3616 struct e1000_hw *hw = &adapter->hw;
3617 u64 rdba = ring->dma;
3618 int reg_idx = ring->reg_idx;
a74420e0 3619 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3620
3621 /* disable the queue */
a74420e0 3622 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3623
3624 /* Set DMA base address registers */
3625 wr32(E1000_RDBAL(reg_idx),
3626 rdba & 0x00000000ffffffffULL);
3627 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3628 wr32(E1000_RDLEN(reg_idx),
b980ac18 3629 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3630
3631 /* initialize head and tail */
fce99e34 3632 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3633 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3634 writel(0, ring->tail);
85b430b4 3635
952f72a8 3636 /* set descriptor configuration */
44390ca6 3637 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3638 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3639 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3640 if (hw->mac.type >= e1000_82580)
757b77e2 3641 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3642 /* Only set Drop Enable if we are supporting multiple queues */
3643 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3644 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3645
3646 wr32(E1000_SRRCTL(reg_idx), srrctl);
3647
7d5753f0 3648 /* set filtering for VMDQ pools */
8151d294 3649 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3650
85b430b4
AD		 3651 rxdctl |= IGB_RX_PTHRESH;
3652 rxdctl |= IGB_RX_HTHRESH << 8;
3653 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3654
3655 /* enable receive descriptor fetching */
3656 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3657 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3658}
3659
9d5c8243 3660/**
b980ac18
JK		 3661 * igb_configure_rx - Configure receive Unit after Reset
3662 * @adapter: board private structure
9d5c8243 3663 *
b980ac18 3664 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3665 **/
3666static void igb_configure_rx(struct igb_adapter *adapter)
3667{
9107584e 3668 int i;
9d5c8243 3669
68d480c4
AD		 3670 /* set UTA to appropriate mode */
3671 igb_set_uta(adapter);
3672
26ad9178
AD		 3673 /* set the correct pool for the PF default MAC address in entry 0 */
3674 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3675 adapter->vfs_allocated_count);
26ad9178 3676
06cf2666 3677 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3678 * the Base and Length of the Rx Descriptor Ring
3679 */
f9d40f6a
AD		 3680 for (i = 0; i < adapter->num_rx_queues; i++)
3681 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3682}
3683
3684/**
b980ac18
JK		 3685 * igb_free_tx_resources - Free Tx Resources per Queue
3686 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3687 *
b980ac18 3688 * Free all transmit software resources
9d5c8243 3689 **/
68fd9910 3690void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3691{
3b644cf6 3692 igb_clean_tx_ring(tx_ring);
9d5c8243 3693
06034649
AD		 3694 vfree(tx_ring->tx_buffer_info);
3695 tx_ring->tx_buffer_info = NULL;
9d5c8243 3696
439705e1
AD		 3697 /* if not set, then don't free */
3698 if (!tx_ring->desc)
3699 return;
3700
59d71989
AD		 3701 dma_free_coherent(tx_ring->dev, tx_ring->size,
3702 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3703
3704 tx_ring->desc = NULL;
3705}
3706
3707/**
b980ac18
JK		 3708 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3709 * @adapter: board private structure
9d5c8243 3710 *
b980ac18 3711 * Free all transmit software resources
9d5c8243
AK		 3712 **/
3713static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3714{
3715 int i;
3716
3717 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3718 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3719}
3720
ebe42d16
AD		 3721void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3722 struct igb_tx_buffer *tx_buffer)
3723{
3724 if (tx_buffer->skb) {
3725 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3726 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3727 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3728 dma_unmap_addr(tx_buffer, dma),
3729 dma_unmap_len(tx_buffer, len),
ebe42d16 3730 DMA_TO_DEVICE);
c9f14bf3 3731 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3732 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3733 dma_unmap_addr(tx_buffer, dma),
3734 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3735 DMA_TO_DEVICE);
3736 }
3737 tx_buffer->next_to_watch = NULL;
3738 tx_buffer->skb = NULL;
c9f14bf3 3739 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3740 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3741}
3742
3743/**
b980ac18
JK		 3744 * igb_clean_tx_ring - Free Tx Buffers
3745 * @tx_ring: ring to be cleaned
9d5c8243 3746 **/
3b644cf6 3747static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3748{
06034649 3749 struct igb_tx_buffer *buffer_info;
9d5c8243 3750 unsigned long size;
6ad4edfc 3751 u16 i;
9d5c8243 3752
06034649 3753 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3754 return;
3755 /* Free all the Tx ring sk_buffs */
3756
3757 for (i = 0; i < tx_ring->count; i++) {
06034649 3758 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3759 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3760 }
3761
dad8a3b3
JF		 3762 netdev_tx_reset_queue(txring_txq(tx_ring));
3763
06034649
AD		 3764 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3765 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3766
3767 /* Zero out the descriptor ring */
9d5c8243
AK		 3768 memset(tx_ring->desc, 0, tx_ring->size);
3769
3770 tx_ring->next_to_use = 0;
3771 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3772}
3773
3774/**
b980ac18
JK		 3775 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3776 * @adapter: board private structure
9d5c8243
AK		 3777 **/
3778static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3779{
3780 int i;
3781
3782 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3783 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3784}
3785
3786/**
b980ac18
JK		 3787 * igb_free_rx_resources - Free Rx Resources
3788 * @rx_ring: ring to clean the resources from
9d5c8243 3789 *
b980ac18 3790 * Free all receive software resources
9d5c8243 3791 **/
68fd9910 3792void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3793{
3b644cf6 3794 igb_clean_rx_ring(rx_ring);
9d5c8243 3795
06034649
AD		 3796 vfree(rx_ring->rx_buffer_info);
3797 rx_ring->rx_buffer_info = NULL;
9d5c8243 3798
439705e1
AD		 3799 /* if not set, then don't free */
3800 if (!rx_ring->desc)
3801 return;
3802
59d71989
AD		 3803 dma_free_coherent(rx_ring->dev, rx_ring->size,
3804 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3805
3806 rx_ring->desc = NULL;
3807}
3808
3809/**
b980ac18
JK		 3810 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3811 * @adapter: board private structure
9d5c8243 3812 *
b980ac18 3813 * Free all receive software resources
9d5c8243
AK		 3814 **/
3815static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3816{
3817 int i;
3818
3819 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3820 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3821}
3822
3823/**
b980ac18
JK		 3824 * igb_clean_rx_ring - Free Rx Buffers per Queue
3825 * @rx_ring: ring to free buffers from
9d5c8243 3826 **/
3b644cf6 3827static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3828{
9d5c8243 3829 unsigned long size;
c023cd88 3830 u16 i;
9d5c8243 3831
1a1c225b
AD		 3832 if (rx_ring->skb)
3833 dev_kfree_skb(rx_ring->skb);
3834 rx_ring->skb = NULL;
3835
06034649 3836 if (!rx_ring->rx_buffer_info)
9d5c8243 3837 return;
439705e1 3838
9d5c8243
AK		 3839 /* Free all the Rx ring sk_buffs */
3840 for (i = 0; i < rx_ring->count; i++) {
06034649 3841 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3842
cbc8e55f
AD		 3843 if (!buffer_info->page)
3844 continue;
3845
3846 dma_unmap_page(rx_ring->dev,
3847 buffer_info->dma,
3848 PAGE_SIZE,
3849 DMA_FROM_DEVICE);
3850 __free_page(buffer_info->page);
3851
1a1c225b 3852 buffer_info->page = NULL;
9d5c8243
AK		 3853 }
3854
06034649
AD		 3855 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3856 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3857
3858 /* Zero out the descriptor ring */
3859 memset(rx_ring->desc, 0, rx_ring->size);
3860
cbc8e55f 3861 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3862 rx_ring->next_to_clean = 0;
3863 rx_ring->next_to_use = 0;
9d5c8243
AK		 3864}
3865
3866/**
b980ac18
JK		 3867 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3868 * @adapter: board private structure
9d5c8243
AK		 3869 **/
3870static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3871{
3872 int i;
3873
3874 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3875 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3876}
3877
3878/**
b980ac18
JK		 3879 * igb_set_mac - Change the Ethernet Address of the NIC
3880 * @netdev: network interface device structure
3881 * @p: pointer to an address structure
9d5c8243 3882 *
b980ac18 3883 * Returns 0 on success, negative on failure
9d5c8243
AK		 3884 **/
3885static int igb_set_mac(struct net_device *netdev, void *p)
3886{
3887 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3888 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3889 struct sockaddr *addr = p;
3890
3891 if (!is_valid_ether_addr(addr->sa_data))
3892 return -EADDRNOTAVAIL;
3893
3894 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3895 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3896
26ad9178
AD		 3897 /* set the correct pool for the new PF MAC address in entry 0 */
3898 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3899 adapter->vfs_allocated_count);
e1739522 3900
9d5c8243
AK		 3901 return 0;
3902}
3903
3904/**
b980ac18
JK		 3905 * igb_write_mc_addr_list - write multicast addresses to MTA
3906 * @netdev: network interface device structure
9d5c8243 3907 *
b980ac18
JK		 3908 * Writes multicast address list to the MTA hash table.
3909 * Returns: -ENOMEM on failure
3910 * 0 on no addresses written
3911 * X on writing X addresses to MTA
9d5c8243 3912 **/
68d480c4 3913static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3914{
3915 struct igb_adapter *adapter = netdev_priv(netdev);
3916 struct e1000_hw *hw = &adapter->hw;
22bedad3 3917 struct netdev_hw_addr *ha;
68d480c4 3918 u8 *mta_list;
9d5c8243
AK		 3919 int i;
3920
4cd24eaf 3921 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3922 /* nothing to program, so clear mc list */
3923 igb_update_mc_addr_list(hw, NULL, 0);
3924 igb_restore_vf_multicasts(adapter);
3925 return 0;
3926 }
9d5c8243 3927
4cd24eaf 3928 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3929 if (!mta_list)
3930 return -ENOMEM;
ff41f8dc 3931
68d480c4 3932 /* The shared function expects a packed array of only addresses. */
48e2f183 3933 i = 0;
22bedad3
JP		 3934 netdev_for_each_mc_addr(ha, netdev)
3935 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3936
68d480c4
AD		 3937 igb_update_mc_addr_list(hw, mta_list, i);
3938 kfree(mta_list);
3939
4cd24eaf 3940 return netdev_mc_count(netdev);
68d480c4
AD		 3941}
3942
3943/**
b980ac18
JK		 3944 * igb_write_uc_addr_list - write unicast addresses to RAR table
3945 * @netdev: network interface device structure
68d480c4 3946 *
b980ac18
JK		 3947 * Writes unicast address list to the RAR table.
3948 * Returns: -ENOMEM on failure/insufficient address space
3949 * 0 on no addresses written
3950 * X on writing X addresses to the RAR table
68d480c4
AD		 3951 **/
3952static int igb_write_uc_addr_list(struct net_device *netdev)
3953{
3954 struct igb_adapter *adapter = netdev_priv(netdev);
3955 struct e1000_hw *hw = &adapter->hw;
3956 unsigned int vfn = adapter->vfs_allocated_count;
3957 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3958 int count = 0;
3959
3960 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3961 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3962 return -ENOMEM;
9d5c8243 3963
32e7bfc4 3964 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3965 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3966
3967 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3968 if (!rar_entries)
3969 break;
26ad9178 3970 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3971 rar_entries--,
3972 vfn);
68d480c4 3973 count++;
ff41f8dc
AD		 3974 }
3975 }
3976 /* write the addresses in reverse order to avoid write combining */
3977 for (; rar_entries > 0 ; rar_entries--) {
3978 wr32(E1000_RAH(rar_entries), 0);
3979 wr32(E1000_RAL(rar_entries), 0);
3980 }
3981 wrfl();
3982
68d480c4
AD		 3983 return count;
3984}
3985
3986/**
b980ac18
JK		 3987 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3988 * @netdev: network interface device structure
68d480c4 3989 *
b980ac18
JK		 3990 * The set_rx_mode entry point is called whenever the unicast or multicast
3991 * address lists or the network interface flags are updated. This routine is
3992 * responsible for configuring the hardware for proper unicast, multicast,
3993 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3994 **/
3995static void igb_set_rx_mode(struct net_device *netdev)
3996{
3997 struct igb_adapter *adapter = netdev_priv(netdev);
3998 struct e1000_hw *hw = &adapter->hw;
3999 unsigned int vfn = adapter->vfs_allocated_count;
4000 u32 rctl, vmolr = 0;
4001 int count;
4002
4003 /* Check for Promiscuous and All Multicast modes */
4004 rctl = rd32(E1000_RCTL);
4005
4006 /* clear the effected bits */
4007 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4008
4009 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4010 /* retain VLAN HW filtering if in VT mode */
7e44892c 4011 if (adapter->vfs_allocated_count)
6f3dc319 4012 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4013 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4014 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4015 } else {
4016 if (netdev->flags & IFF_ALLMULTI) {
4017 rctl |= E1000_RCTL_MPE;
4018 vmolr |= E1000_VMOLR_MPME;
4019 } else {
b980ac18 4020 /* Write addresses to the MTA, if the attempt fails
25985edc 4021 * then we should just turn on promiscuous mode so
68d480c4
AD		 4022 * that we can at least receive multicast traffic
4023 */
4024 count = igb_write_mc_addr_list(netdev);
4025 if (count < 0) {
4026 rctl |= E1000_RCTL_MPE;
4027 vmolr |= E1000_VMOLR_MPME;
4028 } else if (count) {
4029 vmolr |= E1000_VMOLR_ROMPE;
4030 }
4031 }
b980ac18 4032 /* Write addresses to available RAR registers, if there is not
68d480c4 4033 * sufficient space to store all the addresses then enable
25985edc 4034 * unicast promiscuous mode
68d480c4
AD		 4035 */
4036 count = igb_write_uc_addr_list(netdev);
4037 if (count < 0) {
4038 rctl |= E1000_RCTL_UPE;
4039 vmolr |= E1000_VMOLR_ROPE;
4040 }
4041 rctl |= E1000_RCTL_VFE;
28fc06f5 4042 }
68d480c4 4043 wr32(E1000_RCTL, rctl);
28fc06f5 4044
b980ac18 4045 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4046 * the VMOLR to enable the appropriate modes. Without this workaround
4047 * we will have issues with VLAN tag stripping not being done for frames
4048 * that are only arriving because we are the default pool
4049 */
f96a8a0b 4050 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4051 return;
9d5c8243 4052
68d480c4 4053 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4054 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4055 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4056 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4057}
4058
13800469
GR		 4059static void igb_check_wvbr(struct igb_adapter *adapter)
4060{
4061 struct e1000_hw *hw = &adapter->hw;
4062 u32 wvbr = 0;
4063
4064 switch (hw->mac.type) {
4065 case e1000_82576:
4066 case e1000_i350:
81ad807b
CW		 4067 wvbr = rd32(E1000_WVBR);
4068 if (!wvbr)
13800469
GR		 4069 return;
4070 break;
4071 default:
4072 break;
4073 }
4074
4075 adapter->wvbr |= wvbr;
4076}
4077
4078#define IGB_STAGGERED_QUEUE_OFFSET 8
4079
4080static void igb_spoof_check(struct igb_adapter *adapter)
4081{
4082 int j;
4083
4084 if (!adapter->wvbr)
4085 return;
4086
9005df38 4087 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4088 if (adapter->wvbr & (1 << j) ||
4089 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4090 dev_warn(&adapter->pdev->dev,
4091 "Spoof event(s) detected on VF %d\n", j);
4092 adapter->wvbr &=
4093 ~((1 << j) |
4094 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4095 }
4096 }
4097}
4098
9d5c8243 4099/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4100 * the phy
4101 */
9d5c8243
AK		 4102static void igb_update_phy_info(unsigned long data)
4103{
4104 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4105 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4106}
4107
4d6b725e 4108/**
b980ac18
JK		 4109 * igb_has_link - check shared code for link and determine up/down
4110 * @adapter: pointer to driver private info
4d6b725e 4111 **/
3145535a 4112bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4113{
4114 struct e1000_hw *hw = &adapter->hw;
4115 bool link_active = false;
4d6b725e
AD		 4116
4117 /* get_link_status is set on LSC (link status) interrupt or
4118 * rx sequence error interrupt. get_link_status will stay
4119 * false until the e1000_check_for_link establishes link
4120 * for copper adapters ONLY
4121 */
4122 switch (hw->phy.media_type) {
4123 case e1000_media_type_copper:
e5c3370f
AA		 4124 if (!hw->mac.get_link_status)
4125 return true;
4d6b725e 4126 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4127 hw->mac.ops.check_for_link(hw);
4128 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4129 break;
4130 default:
4131 case e1000_media_type_unknown:
4132 break;
4133 }
4134
aa9b8cc4
AA		 4135 if (((hw->mac.type == e1000_i210) ||
4136 (hw->mac.type == e1000_i211)) &&
4137 (hw->phy.id == I210_I_PHY_ID)) {
4138 if (!netif_carrier_ok(adapter->netdev)) {
4139 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4140 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4141 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4142 adapter->link_check_timeout = jiffies;
4143 }
4144 }
4145
4d6b725e
AD		 4146 return link_active;
4147}
4148
563988dc
SA		 4149static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4150{
4151 bool ret = false;
4152 u32 ctrl_ext, thstat;
4153
f96a8a0b 4154 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4155 if (hw->mac.type == e1000_i350) {
4156 thstat = rd32(E1000_THSTAT);
4157 ctrl_ext = rd32(E1000_CTRL_EXT);
4158
4159 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4160 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4161 ret = !!(thstat & event);
563988dc
SA		 4162 }
4163
4164 return ret;
4165}
4166
1516f0a6
CW		 4167/**
4168 * igb_check_lvmmc - check for malformed packets received
4169 * and indicated in LVMMC register
4170 * @adapter: pointer to adapter
4171 **/
4172static void igb_check_lvmmc(struct igb_adapter *adapter)
4173{
4174 struct e1000_hw *hw = &adapter->hw;
4175 u32 lvmmc;
4176
4177 lvmmc = rd32(E1000_LVMMC);
4178 if (lvmmc) {
4179 if (unlikely(net_ratelimit())) {
4180 netdev_warn(adapter->netdev,
4181 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4182 lvmmc);
4183 }
4184 }
4185}
4186
9d5c8243 4187/**
b980ac18
JK		 4188 * igb_watchdog - Timer Call-back
4189 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4190 **/
4191static void igb_watchdog(unsigned long data)
4192{
4193 struct igb_adapter *adapter = (struct igb_adapter *)data;
4194 /* Do the rest outside of interrupt context */
4195 schedule_work(&adapter->watchdog_task);
4196}
4197
4198static void igb_watchdog_task(struct work_struct *work)
4199{
4200 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4201 struct igb_adapter,
4202 watchdog_task);
9d5c8243 4203 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4204 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4205 struct net_device *netdev = adapter->netdev;
563988dc 4206 u32 link;
7a6ea550 4207 int i;
56cec249 4208 u32 connsw;
9d5c8243 4209
4d6b725e 4210 link = igb_has_link(adapter);
aa9b8cc4
AA		 4211
4212 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4213 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4214 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4215 else
4216 link = false;
4217 }
4218
56cec249
CW		 4219 /* Force link down if we have fiber to swap to */
4220 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4221 if (hw->phy.media_type == e1000_media_type_copper) {
4222 connsw = rd32(E1000_CONNSW);
4223 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4224 link = 0;
4225 }
4226 }
9d5c8243 4227 if (link) {
2bdfc4e2
CW		 4228 /* Perform a reset if the media type changed. */
4229 if (hw->dev_spec._82575.media_changed) {
4230 hw->dev_spec._82575.media_changed = false;
4231 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4232 igb_reset(adapter);
4233 }
749ab2cd
YZ		 4234 /* Cancel scheduled suspend requests. */
4235 pm_runtime_resume(netdev->dev.parent);
4236
9d5c8243
AK		 4237 if (!netif_carrier_ok(netdev)) {
4238 u32 ctrl;
9005df38 4239
330a6d6a 4240 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4241 &adapter->link_speed,
4242 &adapter->link_duplex);
9d5c8243
AK		 4243
4244 ctrl = rd32(E1000_CTRL);
527d47c1 4245 /* Links status message must follow this format */
c75c4edf
CW		 4246 netdev_info(netdev,
4247 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4248 netdev->name,
4249 adapter->link_speed,
4250 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4251 "Full" : "Half",
4252 (ctrl & E1000_CTRL_TFCE) &&
4253 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4254 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4255 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4256
f4c01e96
CW		 4257 /* disable EEE if enabled */
4258 if ((adapter->flags & IGB_FLAG_EEE) &&
4259 (adapter->link_duplex == HALF_DUPLEX)) {
4260 dev_info(&adapter->pdev->dev,
4261 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4262 adapter->hw.dev_spec._82575.eee_disable = true;
4263 adapter->flags &= ~IGB_FLAG_EEE;
4264 }
4265
c0ba4778
KS		 4266 /* check if SmartSpeed worked */
4267 igb_check_downshift(hw);
4268 if (phy->speed_downgraded)
4269 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4270
563988dc 4271 /* check for thermal sensor event */
876d2d6f 4272 if (igb_thermal_sensor_event(hw,
d34a15ab 4273 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4274 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4275
d07f3e37 4276 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4277 adapter->tx_timeout_factor = 1;
4278 switch (adapter->link_speed) {
4279 case SPEED_10:
9d5c8243
AK		 4280 adapter->tx_timeout_factor = 14;
4281 break;
4282 case SPEED_100:
9d5c8243
AK		 4283 /* maybe add some timeout factor ? */
4284 break;
4285 }
4286
4287 netif_carrier_on(netdev);
9d5c8243 4288
4ae196df 4289 igb_ping_all_vfs(adapter);
17dc566c 4290 igb_check_vf_rate_limit(adapter);
4ae196df 4291
4b1a9877 4292 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4293 if (!test_bit(__IGB_DOWN, &adapter->state))
4294 mod_timer(&adapter->phy_info_timer,
4295 round_jiffies(jiffies + 2 * HZ));
4296 }
4297 } else {
4298 if (netif_carrier_ok(netdev)) {
4299 adapter->link_speed = 0;
4300 adapter->link_duplex = 0;
563988dc
SA		 4301
4302 /* check for thermal sensor event */
876d2d6f
JK		 4303 if (igb_thermal_sensor_event(hw,
4304 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4305 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4306 }
563988dc 4307
527d47c1 4308 /* Links status message must follow this format */
c75c4edf 4309 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4310 netdev->name);
9d5c8243 4311 netif_carrier_off(netdev);
4b1a9877 4312
4ae196df
AD		 4313 igb_ping_all_vfs(adapter);
4314
4b1a9877 4315 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4316 if (!test_bit(__IGB_DOWN, &adapter->state))
4317 mod_timer(&adapter->phy_info_timer,
4318 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4319
56cec249
CW		 4320 /* link is down, time to check for alternate media */
4321 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4322 igb_check_swap_media(adapter);
4323 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4324 schedule_work(&adapter->reset_task);
4325 /* return immediately */
4326 return;
4327 }
4328 }
749ab2cd
YZ		 4329 pm_schedule_suspend(netdev->dev.parent,
4330 MSEC_PER_SEC * 5);
56cec249
CW		 4331
4332 /* also check for alternate media here */
4333 } else if (!netif_carrier_ok(netdev) &&
4334 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4335 igb_check_swap_media(adapter);
4336 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4337 schedule_work(&adapter->reset_task);
4338 /* return immediately */
4339 return;
4340 }
9d5c8243
AK		 4341 }
4342 }
4343
12dcd86b
ED		 4344 spin_lock(&adapter->stats64_lock);
4345 igb_update_stats(adapter, &adapter->stats64);
4346 spin_unlock(&adapter->stats64_lock);
9d5c8243 4347
dbabb065 4348 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4349 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4350 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4351 /* We've lost link, so the controller stops DMA,
4352 * but we've got queued Tx work that's never going
4353 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4354 * (Do the reset outside of interrupt context).
4355 */
dbabb065
AD		 4356 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4357 adapter->tx_timeout_count++;
4358 schedule_work(&adapter->reset_task);
4359 /* return immediately since reset is imminent */
4360 return;
4361 }
9d5c8243 4362 }
9d5c8243 4363
dbabb065 4364 /* Force detection of hung controller every watchdog period */
6d095fa8 4365 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4366 }
f7ba205e 4367
b980ac18 4368 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4369 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4370 u32 eics = 0;
9005df38 4371
0d1ae7f4
AD		 4372 for (i = 0; i < adapter->num_q_vectors; i++)
4373 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4374 wr32(E1000_EICS, eics);
4375 } else {
4376 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4377 }
9d5c8243 4378
13800469 4379 igb_spoof_check(adapter);
fc580751 4380 igb_ptp_rx_hang(adapter);
13800469 4381
1516f0a6
CW		 4382 /* Check LVMMC register on i350/i354 only */
4383 if ((adapter->hw.mac.type == e1000_i350) ||
4384 (adapter->hw.mac.type == e1000_i354))
4385 igb_check_lvmmc(adapter);
4386
9d5c8243 4387 /* Reset the timer */
aa9b8cc4
AA		 4388 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4389 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4390 mod_timer(&adapter->watchdog_timer,
4391 round_jiffies(jiffies + HZ));
4392 else
4393 mod_timer(&adapter->watchdog_timer,
4394 round_jiffies(jiffies + 2 * HZ));
4395 }
9d5c8243
AK		 4396}
4397
4398enum latency_range {
4399 lowest_latency = 0,
4400 low_latency = 1,
4401 bulk_latency = 2,
4402 latency_invalid = 255
4403};
4404
6eb5a7f1 4405/**
b980ac18
JK		 4406 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4407 * @q_vector: pointer to q_vector
6eb5a7f1 4408 *
b980ac18
JK		 4409 * Stores a new ITR value based on strictly on packet size. This
4410 * algorithm is less sophisticated than that used in igb_update_itr,
4411 * due to the difficulty of synchronizing statistics across multiple
4412 * receive rings. The divisors and thresholds used by this function
4413 * were determined based on theoretical maximum wire speed and testing
4414 * data, in order to minimize response time while increasing bulk
4415 * throughput.
406d4965 4416 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4417 * NOTE: This function is called only when operating in a multiqueue
4418 * receive environment.
6eb5a7f1 4419 **/
047e0030 4420static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4421{
047e0030 4422 int new_val = q_vector->itr_val;
6eb5a7f1 4423 int avg_wire_size = 0;
047e0030 4424 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4425 unsigned int packets;
9d5c8243 4426
6eb5a7f1
AD		 4427 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4428 * ints/sec - ITR timer value of 120 ticks.
4429 */
4430 if (adapter->link_speed != SPEED_1000) {
0ba82994 4431 new_val = IGB_4K_ITR;
6eb5a7f1 4432 goto set_itr_val;
9d5c8243 4433 }
047e0030 4434
0ba82994
AD		 4435 packets = q_vector->rx.total_packets;
4436 if (packets)
4437 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4438
0ba82994
AD		 4439 packets = q_vector->tx.total_packets;
4440 if (packets)
4441 avg_wire_size = max_t(u32, avg_wire_size,
4442 q_vector->tx.total_bytes / packets);
047e0030
AD		 4443
4444 /* if avg_wire_size isn't set no work was done */
4445 if (!avg_wire_size)
4446 goto clear_counts;
9d5c8243 4447
6eb5a7f1
AD		 4448 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4449 avg_wire_size += 24;
4450
4451 /* Don't starve jumbo frames */
4452 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4453
6eb5a7f1
AD		 4454 /* Give a little boost to mid-size frames */
4455 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4456 new_val = avg_wire_size / 3;
4457 else
4458 new_val = avg_wire_size / 2;
9d5c8243 4459
0ba82994
AD		 4460 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4461 if (new_val < IGB_20K_ITR &&
4462 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4463 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4464 new_val = IGB_20K_ITR;
abe1c363 4465
6eb5a7f1 4466set_itr_val:
047e0030
AD		 4467 if (new_val != q_vector->itr_val) {
4468 q_vector->itr_val = new_val;
4469 q_vector->set_itr = 1;
9d5c8243 4470 }
6eb5a7f1 4471clear_counts:
0ba82994
AD		 4472 q_vector->rx.total_bytes = 0;
4473 q_vector->rx.total_packets = 0;
4474 q_vector->tx.total_bytes = 0;
4475 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4476}
4477
4478/**
b980ac18
JK		 4479 * igb_update_itr - update the dynamic ITR value based on statistics
4480 * @q_vector: pointer to q_vector
4481 * @ring_container: ring info to update the itr for
4482 *
4483 * Stores a new ITR value based on packets and byte
4484 * counts during the last interrupt. The advantage of per interrupt
4485 * computation is faster updates and more accurate ITR for the current
4486 * traffic pattern. Constants in this function were computed
4487 * based on theoretical maximum wire speed and thresholds were set based
4488 * on testing data as well as attempting to minimize response time
4489 * while increasing bulk throughput.
406d4965 4490 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4491 * NOTE: These calculations are only valid when operating in a single-
4492 * queue environment.
9d5c8243 4493 **/
0ba82994
AD		 4494static void igb_update_itr(struct igb_q_vector *q_vector,
4495 struct igb_ring_container *ring_container)
9d5c8243 4496{
0ba82994
AD		 4497 unsigned int packets = ring_container->total_packets;
4498 unsigned int bytes = ring_container->total_bytes;
4499 u8 itrval = ring_container->itr;
9d5c8243 4500
0ba82994 4501 /* no packets, exit with status unchanged */
9d5c8243 4502 if (packets == 0)
0ba82994 4503 return;
9d5c8243 4504
0ba82994 4505 switch (itrval) {
9d5c8243
AK		 4506 case lowest_latency:
4507 /* handle TSO and jumbo frames */
4508 if (bytes/packets > 8000)
0ba82994 4509 itrval = bulk_latency;
9d5c8243 4510 else if ((packets < 5) && (bytes > 512))
0ba82994 4511 itrval = low_latency;
9d5c8243
AK		 4512 break;
4513 case low_latency: /* 50 usec aka 20000 ints/s */
4514 if (bytes > 10000) {
4515 /* this if handles the TSO accounting */
d34a15ab 4516 if (bytes/packets > 8000)
0ba82994 4517 itrval = bulk_latency;
d34a15ab 4518 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4519 itrval = bulk_latency;
d34a15ab 4520 else if ((packets > 35))
0ba82994 4521 itrval = lowest_latency;
9d5c8243 4522 } else if (bytes/packets > 2000) {
0ba82994 4523 itrval = bulk_latency;
9d5c8243 4524 } else if (packets <= 2 && bytes < 512) {
0ba82994 4525 itrval = lowest_latency;
9d5c8243
AK		 4526 }
4527 break;
4528 case bulk_latency: /* 250 usec aka 4000 ints/s */
4529 if (bytes > 25000) {
4530 if (packets > 35)
0ba82994 4531 itrval = low_latency;
1e5c3d21 4532 } else if (bytes < 1500) {
0ba82994 4533 itrval = low_latency;
9d5c8243
AK		 4534 }
4535 break;
4536 }
4537
0ba82994
AD		 4538 /* clear work counters since we have the values we need */
4539 ring_container->total_bytes = 0;
4540 ring_container->total_packets = 0;
4541
4542 /* write updated itr to ring container */
4543 ring_container->itr = itrval;
9d5c8243
AK		 4544}
4545
0ba82994 4546static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4547{
0ba82994 4548 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4549 u32 new_itr = q_vector->itr_val;
0ba82994 4550 u8 current_itr = 0;
9d5c8243
AK		 4551
4552 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4553 if (adapter->link_speed != SPEED_1000) {
4554 current_itr = 0;
0ba82994 4555 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4556 goto set_itr_now;
4557 }
4558
0ba82994
AD		 4559 igb_update_itr(q_vector, &q_vector->tx);
4560 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4561
0ba82994 4562 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4563
6eb5a7f1 4564 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4565 if (current_itr == lowest_latency &&
4566 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4567 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4568 current_itr = low_latency;
4569
9d5c8243
AK		 4570 switch (current_itr) {
4571 /* counts and packets in update_itr are dependent on these numbers */
4572 case lowest_latency:
0ba82994 4573 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4574 break;
4575 case low_latency:
0ba82994 4576 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4577 break;
4578 case bulk_latency:
0ba82994 4579 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4580 break;
4581 default:
4582 break;
4583 }
4584
4585set_itr_now:
047e0030 4586 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4587 /* this attempts to bias the interrupt rate towards Bulk
4588 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4589 * increasing
4590 */
047e0030 4591 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4592 max((new_itr * q_vector->itr_val) /
4593 (new_itr + (q_vector->itr_val >> 2)),
4594 new_itr) : new_itr;
9d5c8243
AK		 4595 /* Don't write the value here; it resets the adapter's
4596 * internal timer, and causes us to delay far longer than
4597 * we should between interrupts. Instead, we write the ITR
4598 * value at the beginning of the next interrupt so the timing
4599 * ends up being correct.
4600 */
047e0030
AD		 4601 q_vector->itr_val = new_itr;
4602 q_vector->set_itr = 1;
9d5c8243 4603 }
9d5c8243
AK		 4604}
4605
c50b52a0
SH		 4606static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4607 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4608{
4609 struct e1000_adv_tx_context_desc *context_desc;
4610 u16 i = tx_ring->next_to_use;
4611
4612 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4613
4614 i++;
4615 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4616
4617 /* set bits to identify this as an advanced context descriptor */
4618 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4619
4620 /* For 82575, context index must be unique per ring. */
866cff06 4621 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4622 mss_l4len_idx |= tx_ring->reg_idx << 4;
4623
4624 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4625 context_desc->seqnum_seed = 0;
4626 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4627 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4628}
4629
7af40ad9
AD		 4630static int igb_tso(struct igb_ring *tx_ring,
4631 struct igb_tx_buffer *first,
4632 u8 *hdr_len)
9d5c8243 4633{
7af40ad9 4634 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4635 u32 vlan_macip_lens, type_tucmd;
4636 u32 mss_l4len_idx, l4len;
06c14e5a 4637 int err;
7d13a7d0 4638
ed6aa105
AD		 4639 if (skb->ip_summed != CHECKSUM_PARTIAL)
4640 return 0;
4641
7d13a7d0
AD		 4642 if (!skb_is_gso(skb))
4643 return 0;
9d5c8243 4644
06c14e5a
FR		 4645 err = skb_cow_head(skb, 0);
4646 if (err < 0)
4647 return err;
9d5c8243 4648
7d13a7d0
AD		 4649 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4650 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4651
7c4d16ff 4652 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4653 struct iphdr *iph = ip_hdr(skb);
4654 iph->tot_len = 0;
4655 iph->check = 0;
4656 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4657 iph->daddr, 0,
4658 IPPROTO_TCP,
4659 0);
7d13a7d0 4660 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4661 first->tx_flags |= IGB_TX_FLAGS_TSO |
4662 IGB_TX_FLAGS_CSUM |
4663 IGB_TX_FLAGS_IPV4;
8e1e8a47 4664 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4665 ipv6_hdr(skb)->payload_len = 0;
4666 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4667 &ipv6_hdr(skb)->daddr,
4668 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4669 first->tx_flags |= IGB_TX_FLAGS_TSO |
4670 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4671 }
4672
7af40ad9 4673 /* compute header lengths */
7d13a7d0
AD		 4674 l4len = tcp_hdrlen(skb);
4675 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4676
7af40ad9
AD		 4677 /* update gso size and bytecount with header size */
4678 first->gso_segs = skb_shinfo(skb)->gso_segs;
4679 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4680
9d5c8243 4681 /* MSS L4LEN IDX */
7d13a7d0
AD		 4682 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4683 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4684
7d13a7d0
AD		 4685 /* VLAN MACLEN IPLEN */
4686 vlan_macip_lens = skb_network_header_len(skb);
4687 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4688 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4689
7d13a7d0 4690 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4691
7d13a7d0 4692 return 1;
9d5c8243
AK		 4693}
4694
7af40ad9 4695static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4696{
7af40ad9 4697 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4698 u32 vlan_macip_lens = 0;
4699 u32 mss_l4len_idx = 0;
4700 u32 type_tucmd = 0;
9d5c8243 4701
7d13a7d0 4702 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4703 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4704 return;
7d13a7d0
AD		 4705 } else {
4706 u8 l4_hdr = 0;
9005df38 4707
7af40ad9 4708 switch (first->protocol) {
7c4d16ff 4709 case htons(ETH_P_IP):
7d13a7d0
AD		 4710 vlan_macip_lens |= skb_network_header_len(skb);
4711 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4712 l4_hdr = ip_hdr(skb)->protocol;
4713 break;
7c4d16ff 4714 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4715 vlan_macip_lens |= skb_network_header_len(skb);
4716 l4_hdr = ipv6_hdr(skb)->nexthdr;
4717 break;
4718 default:
4719 if (unlikely(net_ratelimit())) {
4720 dev_warn(tx_ring->dev,
b980ac18
JK		 4721 "partial checksum but proto=%x!\n",
4722 first->protocol);
fa4a7ef3 4723 }
7d13a7d0
AD		 4724 break;
4725 }
fa4a7ef3 4726
7d13a7d0
AD		 4727 switch (l4_hdr) {
4728 case IPPROTO_TCP:
4729 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4730 mss_l4len_idx = tcp_hdrlen(skb) <<
4731 E1000_ADVTXD_L4LEN_SHIFT;
4732 break;
4733 case IPPROTO_SCTP:
4734 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4735 mss_l4len_idx = sizeof(struct sctphdr) <<
4736 E1000_ADVTXD_L4LEN_SHIFT;
4737 break;
4738 case IPPROTO_UDP:
4739 mss_l4len_idx = sizeof(struct udphdr) <<
4740 E1000_ADVTXD_L4LEN_SHIFT;
4741 break;
4742 default:
4743 if (unlikely(net_ratelimit())) {
4744 dev_warn(tx_ring->dev,
b980ac18
JK		 4745 "partial checksum but l4 proto=%x!\n",
4746 l4_hdr);
44b0cda3 4747 }
7d13a7d0 4748 break;
9d5c8243 4749 }
7af40ad9
AD		 4750
4751 /* update TX checksum flag */
4752 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4753 }
9d5c8243 4754
7d13a7d0 4755 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4756 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4757
7d13a7d0 4758 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4759}
4760
1d9daf45
AD		 4761#define IGB_SET_FLAG(_input, _flag, _result) \
4762 ((_flag <= _result) ? \
4763 ((u32)(_input & _flag) * (_result / _flag)) : \
4764 ((u32)(_input & _flag) / (_flag / _result)))
4765
4766static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4767{
4768 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4769 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4770 E1000_ADVTXD_DCMD_DEXT |
4771 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4772
4773 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4774 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4775 (E1000_ADVTXD_DCMD_VLE));
4776
4777 /* set segmentation bits for TSO */
4778 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4779 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4780
4781 /* set timestamp bit if present */
1d9daf45
AD		 4782 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4783 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4784
1d9daf45
AD		 4785 /* insert frame checksum */
4786 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4787
4788 return cmd_type;
4789}
4790
7af40ad9
AD		 4791static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4792 union e1000_adv_tx_desc *tx_desc,
4793 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4794{
4795 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4796
1d9daf45
AD		 4797 /* 82575 requires a unique index per ring */
4798 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4799 olinfo_status |= tx_ring->reg_idx << 4;
4800
4801 /* insert L4 checksum */
1d9daf45
AD		 4802 olinfo_status |= IGB_SET_FLAG(tx_flags,
4803 IGB_TX_FLAGS_CSUM,
4804 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4805
1d9daf45
AD		 4806 /* insert IPv4 checksum */
4807 olinfo_status |= IGB_SET_FLAG(tx_flags,
4808 IGB_TX_FLAGS_IPV4,
4809 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4810
7af40ad9 4811 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4812}
4813
6f19e12f
DM		 4814static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4815{
4816 struct net_device *netdev = tx_ring->netdev;
4817
4818 netif_stop_subqueue(netdev, tx_ring->queue_index);
4819
4820 /* Herbert's original patch had:
4821 * smp_mb__after_netif_stop_queue();
4822 * but since that doesn't exist yet, just open code it.
4823 */
4824 smp_mb();
4825
4826 /* We need to check again in a case another CPU has just
4827 * made room available.
4828 */
4829 if (igb_desc_unused(tx_ring) < size)
4830 return -EBUSY;
4831
4832 /* A reprieve! */
4833 netif_wake_subqueue(netdev, tx_ring->queue_index);
4834
4835 u64_stats_update_begin(&tx_ring->tx_syncp2);
4836 tx_ring->tx_stats.restart_queue2++;
4837 u64_stats_update_end(&tx_ring->tx_syncp2);
4838
4839 return 0;
4840}
4841
4842static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4843{
4844 if (igb_desc_unused(tx_ring) >= size)
4845 return 0;
4846 return __igb_maybe_stop_tx(tx_ring, size);
4847}
4848
7af40ad9
AD		 4849static void igb_tx_map(struct igb_ring *tx_ring,
4850 struct igb_tx_buffer *first,
ebe42d16 4851 const u8 hdr_len)
9d5c8243 4852{
7af40ad9 4853 struct sk_buff *skb = first->skb;
c9f14bf3 4854 struct igb_tx_buffer *tx_buffer;
ebe42d16 4855 union e1000_adv_tx_desc *tx_desc;
80d0759e 4856 struct skb_frag_struct *frag;
ebe42d16 4857 dma_addr_t dma;
80d0759e 4858 unsigned int data_len, size;
7af40ad9 4859 u32 tx_flags = first->tx_flags;
1d9daf45 4860 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4861 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4862
4863 tx_desc = IGB_TX_DESC(tx_ring, i);
4864
80d0759e
AD		 4865 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4866
4867 size = skb_headlen(skb);
4868 data_len = skb->data_len;
ebe42d16
AD		 4869
4870 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4871
80d0759e
AD		 4872 tx_buffer = first;
4873
4874 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4875 if (dma_mapping_error(tx_ring->dev, dma))
4876 goto dma_error;
4877
4878 /* record length, and DMA address */
4879 dma_unmap_len_set(tx_buffer, len, size);
4880 dma_unmap_addr_set(tx_buffer, dma, dma);
4881
4882 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4883
ebe42d16
AD		 4884 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4885 tx_desc->read.cmd_type_len =
1d9daf45 4886 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4887
4888 i++;
4889 tx_desc++;
4890 if (i == tx_ring->count) {
4891 tx_desc = IGB_TX_DESC(tx_ring, 0);
4892 i = 0;
4893 }
80d0759e 4894 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4895
4896 dma += IGB_MAX_DATA_PER_TXD;
4897 size -= IGB_MAX_DATA_PER_TXD;
4898
ebe42d16
AD		 4899 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4900 }
4901
4902 if (likely(!data_len))
4903 break;
2bbfebe2 4904
1d9daf45 4905 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4906
65689fef 4907 i++;
ebe42d16
AD		 4908 tx_desc++;
4909 if (i == tx_ring->count) {
4910 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4911 i = 0;
ebe42d16 4912 }
80d0759e 4913 tx_desc->read.olinfo_status = 0;
65689fef 4914
9e903e08 4915 size = skb_frag_size(frag);
ebe42d16
AD		 4916 data_len -= size;
4917
4918 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4919 size, DMA_TO_DEVICE);
6366ad33 4920
c9f14bf3 4921 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4922 }
4923
ebe42d16 4924 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4925 cmd_type |= size | IGB_TXD_DCMD;
4926 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4927
80d0759e
AD		 4928 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4929
8542db05
AD		 4930 /* set the timestamp */
4931 first->time_stamp = jiffies;
4932
b980ac18 4933 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4934 * are new descriptors to fetch. (Only applicable for weak-ordered
4935 * memory model archs, such as IA-64).
4936 *
4937 * We also need this memory barrier to make certain all of the
4938 * status bits have been updated before next_to_watch is written.
4939 */
4940 wmb();
4941
8542db05 4942 /* set next_to_watch value indicating a packet is present */
ebe42d16 4943 first->next_to_watch = tx_desc;
9d5c8243 4944
ebe42d16
AD		 4945 i++;
4946 if (i == tx_ring->count)
4947 i = 0;
6366ad33 4948
ebe42d16 4949 tx_ring->next_to_use = i;
6366ad33 4950
6f19e12f
DM		 4951 /* Make sure there is space in the ring for the next send. */
4952 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4953
4954 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 4955 writel(i, tx_ring->tail);
4956
4957 /* we need this if more than one processor can write to our tail
4958 * at a time, it synchronizes IO on IA64/Altix systems
4959 */
4960 mmiowb();
4961 }
ebe42d16
AD		 4962 return;
4963
4964dma_error:
4965 dev_err(tx_ring->dev, "TX DMA map failed\n");
4966
4967 /* clear dma mappings for failed tx_buffer_info map */
4968 for (;;) {
c9f14bf3
AD		 4969 tx_buffer = &tx_ring->tx_buffer_info[i];
4970 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4971 if (tx_buffer == first)
ebe42d16 4972 break;
a77ff709
NN		 4973 if (i == 0)
4974 i = tx_ring->count;
6366ad33 4975 i--;
6366ad33
AD		 4976 }
4977
9d5c8243 4978 tx_ring->next_to_use = i;
9d5c8243
AK		 4979}
4980
cd392f5c
AD		 4981netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4982 struct igb_ring *tx_ring)
9d5c8243 4983{
8542db05 4984 struct igb_tx_buffer *first;
ebe42d16 4985 int tso;
91d4ee33 4986 u32 tx_flags = 0;
21ba6fe1 4987 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4988 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4989 u8 hdr_len = 0;
9d5c8243 4990
21ba6fe1
AD		 4991 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4992 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4993 * + 2 desc gap to keep tail from touching head,
9d5c8243 4994 * + 1 desc for context descriptor,
21ba6fe1
AD		 4995 * otherwise try next time
4996 */
4997 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4998 unsigned short f;
9005df38 4999
21ba6fe1
AD		 5000 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5001 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5002 } else {
5003 count += skb_shinfo(skb)->nr_frags;
5004 }
5005
5006 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5007 /* this is a hard error */
9d5c8243
AK		 5008 return NETDEV_TX_BUSY;
5009 }
33af6bcc 5010
7af40ad9
AD		 5011 /* record the location of the first descriptor for this packet */
5012 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5013 first->skb = skb;
5014 first->bytecount = skb->len;
5015 first->gso_segs = 1;
5016
b646c22e
AD		 5017 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5018 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5019
ed4420a3
JK		 5020 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5021 &adapter->state)) {
b646c22e
AD		 5022 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5023 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5024
5025 adapter->ptp_tx_skb = skb_get(skb);
5026 adapter->ptp_tx_start = jiffies;
5027 if (adapter->hw.mac.type == e1000_82576)
5028 schedule_work(&adapter->ptp_tx_work);
5029 }
33af6bcc 5030 }
9d5c8243 5031
afc835d1
JK		 5032 skb_tx_timestamp(skb);
5033
eab6d18d 5034 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 5035 tx_flags |= IGB_TX_FLAGS_VLAN;
5036 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5037 }
5038
7af40ad9
AD		 5039 /* record initial flags and protocol */
5040 first->tx_flags = tx_flags;
5041 first->protocol = protocol;
cdfd01fc 5042
7af40ad9
AD		 5043 tso = igb_tso(tx_ring, first, &hdr_len);
5044 if (tso < 0)
7d13a7d0 5045 goto out_drop;
7af40ad9
AD		 5046 else if (!tso)
5047 igb_tx_csum(tx_ring, first);
9d5c8243 5048
7af40ad9 5049 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5050
9d5c8243 5051 return NETDEV_TX_OK;
7d13a7d0
AD		 5052
5053out_drop:
7af40ad9
AD		 5054 igb_unmap_and_free_tx_resource(tx_ring, first);
5055
7d13a7d0 5056 return NETDEV_TX_OK;
9d5c8243
AK		 5057}
5058
0b725a2c
DM		 5059static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5060 struct sk_buff *skb)
1cc3bd87 5061{
0b725a2c
DM		 5062 unsigned int r_idx = skb->queue_mapping;
5063
1cc3bd87
AD		 5064 if (r_idx >= adapter->num_tx_queues)
5065 r_idx = r_idx % adapter->num_tx_queues;
5066
5067 return adapter->tx_ring[r_idx];
5068}
5069
cd392f5c
AD		 5070static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5071 struct net_device *netdev)
9d5c8243
AK		 5072{
5073 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5074
5075 if (test_bit(__IGB_DOWN, &adapter->state)) {
5076 dev_kfree_skb_any(skb);
5077 return NETDEV_TX_OK;
5078 }
5079
5080 if (skb->len <= 0) {
5081 dev_kfree_skb_any(skb);
5082 return NETDEV_TX_OK;
5083 }
5084
b980ac18 5085 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5086 * in order to meet this minimum size requirement.
5087 */
ea5ceeab
TD		 5088 if (unlikely(skb->len < 17)) {
5089 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 5090 return NETDEV_TX_OK;
5091 skb->len = 17;
ea5ceeab 5092 skb_set_tail_pointer(skb, 17);
1cc3bd87 5093 }
9d5c8243 5094
1cc3bd87 5095 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5096}
5097
5098/**
b980ac18
JK		 5099 * igb_tx_timeout - Respond to a Tx Hang
5100 * @netdev: network interface device structure
9d5c8243
AK		 5101 **/
5102static void igb_tx_timeout(struct net_device *netdev)
5103{
5104 struct igb_adapter *adapter = netdev_priv(netdev);
5105 struct e1000_hw *hw = &adapter->hw;
5106
5107 /* Do the reset outside of interrupt context */
5108 adapter->tx_timeout_count++;
f7ba205e 5109
06218a8d 5110 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5111 hw->dev_spec._82575.global_device_reset = true;
5112
9d5c8243 5113 schedule_work(&adapter->reset_task);
265de409
AD		 5114 wr32(E1000_EICS,
5115 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5116}
5117
5118static void igb_reset_task(struct work_struct *work)
5119{
5120 struct igb_adapter *adapter;
5121 adapter = container_of(work, struct igb_adapter, reset_task);
5122
c97ec42a
TI		 5123 igb_dump(adapter);
5124 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5125 igb_reinit_locked(adapter);
5126}
5127
5128/**
b980ac18
JK		 5129 * igb_get_stats64 - Get System Network Statistics
5130 * @netdev: network interface device structure
5131 * @stats: rtnl_link_stats64 pointer
9d5c8243 5132 **/
12dcd86b 5133static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5134 struct rtnl_link_stats64 *stats)
9d5c8243 5135{
12dcd86b
ED		 5136 struct igb_adapter *adapter = netdev_priv(netdev);
5137
5138 spin_lock(&adapter->stats64_lock);
5139 igb_update_stats(adapter, &adapter->stats64);
5140 memcpy(stats, &adapter->stats64, sizeof(*stats));
5141 spin_unlock(&adapter->stats64_lock);
5142
5143 return stats;
9d5c8243
AK		 5144}
5145
5146/**
b980ac18
JK		 5147 * igb_change_mtu - Change the Maximum Transfer Unit
5148 * @netdev: network interface device structure
5149 * @new_mtu: new value for maximum frame size
9d5c8243 5150 *
b980ac18 5151 * Returns 0 on success, negative on failure
9d5c8243
AK		 5152 **/
5153static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5154{
5155 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5156 struct pci_dev *pdev = adapter->pdev;
153285f9 5157 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5158
c809d227 5159 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5160 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5161 return -EINVAL;
5162 }
5163
153285f9 5164#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5165 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5166 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5167 return -EINVAL;
5168 }
5169
2ccd994c
AD		 5170 /* adjust max frame to be at least the size of a standard frame */
5171 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5172 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5173
9d5c8243 5174 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5175 usleep_range(1000, 2000);
73cd78f1 5176
9d5c8243
AK		 5177 /* igb_down has a dependency on max_frame_size */
5178 adapter->max_frame_size = max_frame;
559e9c49 5179
4c844851
AD		 5180 if (netif_running(netdev))
5181 igb_down(adapter);
9d5c8243 5182
090b1795 5183 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5184 netdev->mtu, new_mtu);
5185 netdev->mtu = new_mtu;
5186
5187 if (netif_running(netdev))
5188 igb_up(adapter);
5189 else
5190 igb_reset(adapter);
5191
5192 clear_bit(__IGB_RESETTING, &adapter->state);
5193
5194 return 0;
5195}
5196
5197/**
b980ac18
JK		 5198 * igb_update_stats - Update the board statistics counters
5199 * @adapter: board private structure
9d5c8243 5200 **/
12dcd86b
ED		 5201void igb_update_stats(struct igb_adapter *adapter,
5202 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5203{
5204 struct e1000_hw *hw = &adapter->hw;
5205 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5206 u32 reg, mpc;
3f9c0164
AD		 5207 int i;
5208 u64 bytes, packets;
12dcd86b
ED		 5209 unsigned int start;
5210 u64 _bytes, _packets;
9d5c8243 5211
b980ac18 5212 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5213 * connection is down.
5214 */
5215 if (adapter->link_speed == 0)
5216 return;
5217 if (pci_channel_offline(pdev))
5218 return;
5219
3f9c0164
AD		 5220 bytes = 0;
5221 packets = 0;
7f90128e
AA		 5222
5223 rcu_read_lock();
3f9c0164 5224 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5225 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5226 u32 rqdpc = rd32(E1000_RQDPC(i));
5227 if (hw->mac.type >= e1000_i210)
5228 wr32(E1000_RQDPC(i), 0);
12dcd86b 5229
ae1c07a6
AD		 5230 if (rqdpc) {
5231 ring->rx_stats.drops += rqdpc;
5232 net_stats->rx_fifo_errors += rqdpc;
5233 }
12dcd86b
ED		 5234
5235 do {
57a7744e 5236 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5237 _bytes = ring->rx_stats.bytes;
5238 _packets = ring->rx_stats.packets;
57a7744e 5239 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5240 bytes += _bytes;
5241 packets += _packets;
3f9c0164
AD		 5242 }
5243
128e45eb
AD		 5244 net_stats->rx_bytes = bytes;
5245 net_stats->rx_packets = packets;
3f9c0164
AD		 5246
5247 bytes = 0;
5248 packets = 0;
5249 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5250 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5251 do {
57a7744e 5252 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5253 _bytes = ring->tx_stats.bytes;
5254 _packets = ring->tx_stats.packets;
57a7744e 5255 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5256 bytes += _bytes;
5257 packets += _packets;
3f9c0164 5258 }
128e45eb
AD		 5259 net_stats->tx_bytes = bytes;
5260 net_stats->tx_packets = packets;
7f90128e 5261 rcu_read_unlock();
3f9c0164
AD		 5262
5263 /* read stats registers */
9d5c8243
AK		 5264 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5265 adapter->stats.gprc += rd32(E1000_GPRC);
5266 adapter->stats.gorc += rd32(E1000_GORCL);
5267 rd32(E1000_GORCH); /* clear GORCL */
5268 adapter->stats.bprc += rd32(E1000_BPRC);
5269 adapter->stats.mprc += rd32(E1000_MPRC);
5270 adapter->stats.roc += rd32(E1000_ROC);
5271
5272 adapter->stats.prc64 += rd32(E1000_PRC64);
5273 adapter->stats.prc127 += rd32(E1000_PRC127);
5274 adapter->stats.prc255 += rd32(E1000_PRC255);
5275 adapter->stats.prc511 += rd32(E1000_PRC511);
5276 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5277 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5278 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5279 adapter->stats.sec += rd32(E1000_SEC);
5280
fa3d9a6d
MW		 5281 mpc = rd32(E1000_MPC);
5282 adapter->stats.mpc += mpc;
5283 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5284 adapter->stats.scc += rd32(E1000_SCC);
5285 adapter->stats.ecol += rd32(E1000_ECOL);
5286 adapter->stats.mcc += rd32(E1000_MCC);
5287 adapter->stats.latecol += rd32(E1000_LATECOL);
5288 adapter->stats.dc += rd32(E1000_DC);
5289 adapter->stats.rlec += rd32(E1000_RLEC);
5290 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5291 adapter->stats.xontxc += rd32(E1000_XONTXC);
5292 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5293 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5294 adapter->stats.fcruc += rd32(E1000_FCRUC);
5295 adapter->stats.gptc += rd32(E1000_GPTC);
5296 adapter->stats.gotc += rd32(E1000_GOTCL);
5297 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5298 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5299 adapter->stats.ruc += rd32(E1000_RUC);
5300 adapter->stats.rfc += rd32(E1000_RFC);
5301 adapter->stats.rjc += rd32(E1000_RJC);
5302 adapter->stats.tor += rd32(E1000_TORH);
5303 adapter->stats.tot += rd32(E1000_TOTH);
5304 adapter->stats.tpr += rd32(E1000_TPR);
5305
5306 adapter->stats.ptc64 += rd32(E1000_PTC64);
5307 adapter->stats.ptc127 += rd32(E1000_PTC127);
5308 adapter->stats.ptc255 += rd32(E1000_PTC255);
5309 adapter->stats.ptc511 += rd32(E1000_PTC511);
5310 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5311 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5312
5313 adapter->stats.mptc += rd32(E1000_MPTC);
5314 adapter->stats.bptc += rd32(E1000_BPTC);
5315
2d0b0f69
NN		 5316 adapter->stats.tpt += rd32(E1000_TPT);
5317 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5318
5319 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5320 /* read internal phy specific stats */
5321 reg = rd32(E1000_CTRL_EXT);
5322 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5323 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5324
5325 /* this stat has invalid values on i210/i211 */
5326 if ((hw->mac.type != e1000_i210) &&
5327 (hw->mac.type != e1000_i211))
5328 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5329 }
5330
9d5c8243
AK		 5331 adapter->stats.tsctc += rd32(E1000_TSCTC);
5332 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5333
5334 adapter->stats.iac += rd32(E1000_IAC);
5335 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5336 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5337 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5338 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5339 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5340 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5341 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5342 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5343
5344 /* Fill out the OS statistics structure */
128e45eb
AD		 5345 net_stats->multicast = adapter->stats.mprc;
5346 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5347
5348 /* Rx Errors */
5349
5350 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5351 * our own version based on RUC and ROC
5352 */
128e45eb 5353 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5354 adapter->stats.crcerrs + adapter->stats.algnerrc +
5355 adapter->stats.ruc + adapter->stats.roc +
5356 adapter->stats.cexterr;
128e45eb
AD		 5357 net_stats->rx_length_errors = adapter->stats.ruc +
5358 adapter->stats.roc;
5359 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5360 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5361 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5362
5363 /* Tx Errors */
128e45eb
AD		 5364 net_stats->tx_errors = adapter->stats.ecol +
5365 adapter->stats.latecol;
5366 net_stats->tx_aborted_errors = adapter->stats.ecol;
5367 net_stats->tx_window_errors = adapter->stats.latecol;
5368 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5369
5370 /* Tx Dropped needs to be maintained elsewhere */
5371
9d5c8243
AK		 5372 /* Management Stats */
5373 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5374 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5375 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5376
5377 /* OS2BMC Stats */
5378 reg = rd32(E1000_MANC);
5379 if (reg & E1000_MANC_EN_BMC2OS) {
5380 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5381 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5382 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5383 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5384 }
9d5c8243
AK		 5385}
5386
9d5c8243
AK		 5387static irqreturn_t igb_msix_other(int irq, void *data)
5388{
047e0030 5389 struct igb_adapter *adapter = data;
9d5c8243 5390 struct e1000_hw *hw = &adapter->hw;
844290e5 5391 u32 icr = rd32(E1000_ICR);
844290e5 5392 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5393
7f081d40
AD		 5394 if (icr & E1000_ICR_DRSTA)
5395 schedule_work(&adapter->reset_task);
5396
047e0030 5397 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5398 /* HW is reporting DMA is out of sync */
5399 adapter->stats.doosync++;
13800469
GR		 5400 /* The DMA Out of Sync is also indication of a spoof event
5401 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5402 * see if it is really a spoof event.
5403 */
13800469 5404 igb_check_wvbr(adapter);
dda0e083 5405 }
eebbbdba 5406
4ae196df
AD		 5407 /* Check for a mailbox event */
5408 if (icr & E1000_ICR_VMMB)
5409 igb_msg_task(adapter);
5410
5411 if (icr & E1000_ICR_LSC) {
5412 hw->mac.get_link_status = 1;
5413 /* guard against interrupt when we're going down */
5414 if (!test_bit(__IGB_DOWN, &adapter->state))
5415 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5416 }
5417
1f6e8178
MV		 5418 if (icr & E1000_ICR_TS) {
5419 u32 tsicr = rd32(E1000_TSICR);
5420
5421 if (tsicr & E1000_TSICR_TXTS) {
5422 /* acknowledge the interrupt */
5423 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5424 /* retrieve hardware timestamp */
5425 schedule_work(&adapter->ptp_tx_work);
5426 }
5427 }
1f6e8178 5428
844290e5 5429 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5430
5431 return IRQ_HANDLED;
5432}
5433
047e0030 5434static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5435{
26b39276 5436 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5437 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5438
047e0030
AD		 5439 if (!q_vector->set_itr)
5440 return;
73cd78f1 5441
047e0030
AD		 5442 if (!itr_val)
5443 itr_val = 0x4;
661086df 5444
26b39276
AD		 5445 if (adapter->hw.mac.type == e1000_82575)
5446 itr_val |= itr_val << 16;
661086df 5447 else
0ba82994 5448 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5449
047e0030
AD		 5450 writel(itr_val, q_vector->itr_register);
5451 q_vector->set_itr = 0;
6eb5a7f1
AD		 5452}
5453
047e0030 5454static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5455{
047e0030 5456 struct igb_q_vector *q_vector = data;
9d5c8243 5457
047e0030
AD		 5458 /* Write the ITR value calculated from the previous interrupt. */
5459 igb_write_itr(q_vector);
9d5c8243 5460
047e0030 5461 napi_schedule(&q_vector->napi);
844290e5 5462
047e0030 5463 return IRQ_HANDLED;
fe4506b6
JC		 5464}
5465
421e02f0 5466#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5467static void igb_update_tx_dca(struct igb_adapter *adapter,
5468 struct igb_ring *tx_ring,
5469 int cpu)
5470{
5471 struct e1000_hw *hw = &adapter->hw;
5472 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5473
5474 if (hw->mac.type != e1000_82575)
5475 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5476
b980ac18 5477 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5478 * DCA is enabled. This is due to a known issue in some chipsets
5479 * which will cause the DCA tag to be cleared.
5480 */
5481 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5482 E1000_DCA_TXCTRL_DATA_RRO_EN |
5483 E1000_DCA_TXCTRL_DESC_DCA_EN;
5484
5485 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5486}
5487
5488static void igb_update_rx_dca(struct igb_adapter *adapter,
5489 struct igb_ring *rx_ring,
5490 int cpu)
5491{
5492 struct e1000_hw *hw = &adapter->hw;
5493 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5494
5495 if (hw->mac.type != e1000_82575)
5496 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5497
b980ac18 5498 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5499 * DCA is enabled. This is due to a known issue in some chipsets
5500 * which will cause the DCA tag to be cleared.
5501 */
5502 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5503 E1000_DCA_RXCTRL_DESC_DCA_EN;
5504
5505 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5506}
5507
047e0030 5508static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5509{
047e0030 5510 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5511 int cpu = get_cpu();
fe4506b6 5512
047e0030
AD		 5513 if (q_vector->cpu == cpu)
5514 goto out_no_update;
5515
6a05004a
AD		 5516 if (q_vector->tx.ring)
5517 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5518
5519 if (q_vector->rx.ring)
5520 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5521
047e0030
AD		 5522 q_vector->cpu = cpu;
5523out_no_update:
fe4506b6
JC		 5524 put_cpu();
5525}
5526
5527static void igb_setup_dca(struct igb_adapter *adapter)
5528{
7e0e99ef 5529 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5530 int i;
5531
7dfc16fa 5532 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5533 return;
5534
7e0e99ef
AD		 5535 /* Always use CB2 mode, difference is masked in the CB driver. */
5536 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5537
047e0030 5538 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5539 adapter->q_vector[i]->cpu = -1;
5540 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5541 }
5542}
5543
5544static int __igb_notify_dca(struct device *dev, void *data)
5545{
5546 struct net_device *netdev = dev_get_drvdata(dev);
5547 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5548 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5549 struct e1000_hw *hw = &adapter->hw;
5550 unsigned long event = *(unsigned long *)data;
5551
5552 switch (event) {
5553 case DCA_PROVIDER_ADD:
5554 /* if already enabled, don't do it again */
7dfc16fa 5555 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5556 break;
fe4506b6 5557 if (dca_add_requester(dev) == 0) {
bbd98fe4 5558 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5559 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5560 igb_setup_dca(adapter);
5561 break;
5562 }
5563 /* Fall Through since DCA is disabled. */
5564 case DCA_PROVIDER_REMOVE:
7dfc16fa 5565 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5566 /* without this a class_device is left
b980ac18
JK		 5567 * hanging around in the sysfs model
5568 */
fe4506b6 5569 dca_remove_requester(dev);
090b1795 5570 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5571 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5572 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5573 }
5574 break;
5575 }
bbd98fe4 5576
fe4506b6 5577 return 0;
9d5c8243
AK		 5578}
5579
fe4506b6 5580static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5581 void *p)
fe4506b6
JC		 5582{
5583 int ret_val;
5584
5585 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5586 __igb_notify_dca);
fe4506b6
JC		 5587
5588 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5589}
421e02f0 5590#endif /* CONFIG_IGB_DCA */
9d5c8243 5591
0224d663
GR		 5592#ifdef CONFIG_PCI_IOV
5593static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5594{
5595 unsigned char mac_addr[ETH_ALEN];
0224d663 5596
5ac6f91d 5597 eth_zero_addr(mac_addr);
0224d663
GR		 5598 igb_set_vf_mac(adapter, vf, mac_addr);
5599
70ea4783
LL		 5600 /* By default spoof check is enabled for all VFs */
5601 adapter->vf_data[vf].spoofchk_enabled = true;
5602
f557147c 5603 return 0;
0224d663
GR		 5604}
5605
0224d663 5606#endif
4ae196df
AD		 5607static void igb_ping_all_vfs(struct igb_adapter *adapter)
5608{
5609 struct e1000_hw *hw = &adapter->hw;
5610 u32 ping;
5611 int i;
5612
5613 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5614 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5615 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5616 ping |= E1000_VT_MSGTYPE_CTS;
5617 igb_write_mbx(hw, &ping, 1, i);
5618 }
5619}
5620
7d5753f0
AD		 5621static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5622{
5623 struct e1000_hw *hw = &adapter->hw;
5624 u32 vmolr = rd32(E1000_VMOLR(vf));
5625 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5626
d85b9004 5627 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5628 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5629 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5630
5631 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5632 vmolr |= E1000_VMOLR_MPME;
d85b9004 5633 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5634 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5635 } else {
b980ac18 5636 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5637 * flag we need to write the hashes to the MTA as this step
5638 * was previously skipped
5639 */
5640 if (vf_data->num_vf_mc_hashes > 30) {
5641 vmolr |= E1000_VMOLR_MPME;
5642 } else if (vf_data->num_vf_mc_hashes) {
5643 int j;
9005df38 5644
7d5753f0
AD		 5645 vmolr |= E1000_VMOLR_ROMPE;
5646 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5647 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5648 }
5649 }
5650
5651 wr32(E1000_VMOLR(vf), vmolr);
5652
5653 /* there are flags left unprocessed, likely not supported */
5654 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5655 return -EINVAL;
5656
5657 return 0;
7d5753f0
AD		 5658}
5659
4ae196df
AD		 5660static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5661 u32 *msgbuf, u32 vf)
5662{
5663 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5664 u16 *hash_list = (u16 *)&msgbuf[1];
5665 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5666 int i;
5667
7d5753f0 5668 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5669 * to this VF for later use to restore when the PF multi cast
5670 * list changes
5671 */
5672 vf_data->num_vf_mc_hashes = n;
5673
7d5753f0
AD		 5674 /* only up to 30 hash values supported */
5675 if (n > 30)
5676 n = 30;
5677
5678 /* store the hashes for later use */
4ae196df 5679 for (i = 0; i < n; i++)
a419aef8 5680 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5681
5682 /* Flush and reset the mta with the new values */
ff41f8dc 5683 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5684
5685 return 0;
5686}
5687
5688static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5689{
5690 struct e1000_hw *hw = &adapter->hw;
5691 struct vf_data_storage *vf_data;
5692 int i, j;
5693
5694 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5695 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5696
7d5753f0
AD		 5697 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5698
4ae196df 5699 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5700
5701 if ((vf_data->num_vf_mc_hashes > 30) ||
5702 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5703 vmolr |= E1000_VMOLR_MPME;
5704 } else if (vf_data->num_vf_mc_hashes) {
5705 vmolr |= E1000_VMOLR_ROMPE;
5706 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5707 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5708 }
5709 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5710 }
5711}
5712
5713static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5714{
5715 struct e1000_hw *hw = &adapter->hw;
5716 u32 pool_mask, reg, vid;
5717 int i;
5718
5719 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5720
5721 /* Find the vlan filter for this id */
5722 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5723 reg = rd32(E1000_VLVF(i));
5724
5725 /* remove the vf from the pool */
5726 reg &= ~pool_mask;
5727
5728 /* if pool is empty then remove entry from vfta */
5729 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5730 (reg & E1000_VLVF_VLANID_ENABLE)) {
5731 reg = 0;
5732 vid = reg & E1000_VLVF_VLANID_MASK;
5733 igb_vfta_set(hw, vid, false);
5734 }
5735
5736 wr32(E1000_VLVF(i), reg);
5737 }
ae641bdc
AD		 5738
5739 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5740}
5741
5742static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5743{
5744 struct e1000_hw *hw = &adapter->hw;
5745 u32 reg, i;
5746
51466239
AD		 5747 /* The vlvf table only exists on 82576 hardware and newer */
5748 if (hw->mac.type < e1000_82576)
5749 return -1;
5750
5751 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5752 if (!adapter->vfs_allocated_count)
5753 return -1;
5754
5755 /* Find the vlan filter for this id */
5756 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5757 reg = rd32(E1000_VLVF(i));
5758 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5759 vid == (reg & E1000_VLVF_VLANID_MASK))
5760 break;
5761 }
5762
5763 if (add) {
5764 if (i == E1000_VLVF_ARRAY_SIZE) {
5765 /* Did not find a matching VLAN ID entry that was
5766 * enabled. Search for a free filter entry, i.e.
5767 * one without the enable bit set
5768 */
5769 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5770 reg = rd32(E1000_VLVF(i));
5771 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5772 break;
5773 }
5774 }
5775 if (i < E1000_VLVF_ARRAY_SIZE) {
5776 /* Found an enabled/available entry */
5777 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5778
5779 /* if !enabled we need to set this up in vfta */
5780 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5781 /* add VID to filter table */
5782 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5783 reg |= E1000_VLVF_VLANID_ENABLE;
5784 }
cad6d05f
AD		 5785 reg &= ~E1000_VLVF_VLANID_MASK;
5786 reg |= vid;
4ae196df 5787 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5788
5789 /* do not modify RLPML for PF devices */
5790 if (vf >= adapter->vfs_allocated_count)
5791 return 0;
5792
5793 if (!adapter->vf_data[vf].vlans_enabled) {
5794 u32 size;
9005df38 5795
ae641bdc
AD		 5796 reg = rd32(E1000_VMOLR(vf));
5797 size = reg & E1000_VMOLR_RLPML_MASK;
5798 size += 4;
5799 reg &= ~E1000_VMOLR_RLPML_MASK;
5800 reg |= size;
5801 wr32(E1000_VMOLR(vf), reg);
5802 }
ae641bdc 5803
51466239 5804 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5805 }
5806 } else {
5807 if (i < E1000_VLVF_ARRAY_SIZE) {
5808 /* remove vf from the pool */
5809 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5810 /* if pool is empty then remove entry from vfta */
5811 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5812 reg = 0;
5813 igb_vfta_set(hw, vid, false);
5814 }
5815 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5816
5817 /* do not modify RLPML for PF devices */
5818 if (vf >= adapter->vfs_allocated_count)
5819 return 0;
5820
5821 adapter->vf_data[vf].vlans_enabled--;
5822 if (!adapter->vf_data[vf].vlans_enabled) {
5823 u32 size;
9005df38 5824
ae641bdc
AD		 5825 reg = rd32(E1000_VMOLR(vf));
5826 size = reg & E1000_VMOLR_RLPML_MASK;
5827 size -= 4;
5828 reg &= ~E1000_VMOLR_RLPML_MASK;
5829 reg |= size;
5830 wr32(E1000_VMOLR(vf), reg);
5831 }
4ae196df
AD		 5832 }
5833 }
8151d294
WM		 5834 return 0;
5835}
5836
5837static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5838{
5839 struct e1000_hw *hw = &adapter->hw;
5840
5841 if (vid)
5842 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5843 else
5844 wr32(E1000_VMVIR(vf), 0);
5845}
5846
5847static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5848 int vf, u16 vlan, u8 qos)
5849{
5850 int err = 0;
5851 struct igb_adapter *adapter = netdev_priv(netdev);
5852
5853 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5854 return -EINVAL;
5855 if (vlan || qos) {
5856 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5857 if (err)
5858 goto out;
5859 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5860 igb_set_vmolr(adapter, vf, !vlan);
5861 adapter->vf_data[vf].pf_vlan = vlan;
5862 adapter->vf_data[vf].pf_qos = qos;
5863 dev_info(&adapter->pdev->dev,
5864 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5865 if (test_bit(__IGB_DOWN, &adapter->state)) {
5866 dev_warn(&adapter->pdev->dev,
b980ac18 5867 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5868 dev_warn(&adapter->pdev->dev,
b980ac18 5869 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5870 }
5871 } else {
5872 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5873 false, vf);
8151d294
WM		 5874 igb_set_vmvir(adapter, vlan, vf);
5875 igb_set_vmolr(adapter, vf, true);
5876 adapter->vf_data[vf].pf_vlan = 0;
5877 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5878 }
8151d294 5879out:
b980ac18 5880 return err;
4ae196df
AD		 5881}
5882
6f3dc319
GR		 5883static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5884{
5885 struct e1000_hw *hw = &adapter->hw;
5886 int i;
5887 u32 reg;
5888
5889 /* Find the vlan filter for this id */
5890 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5891 reg = rd32(E1000_VLVF(i));
5892 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5893 vid == (reg & E1000_VLVF_VLANID_MASK))
5894 break;
5895 }
5896
5897 if (i >= E1000_VLVF_ARRAY_SIZE)
5898 i = -1;
5899
5900 return i;
5901}
5902
4ae196df
AD		 5903static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5904{
6f3dc319 5905 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5906 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5907 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5908 int err = 0;
4ae196df 5909
6f3dc319
GR		 5910 /* If in promiscuous mode we need to make sure the PF also has
5911 * the VLAN filter set.
5912 */
5913 if (add && (adapter->netdev->flags & IFF_PROMISC))
5914 err = igb_vlvf_set(adapter, vid, add,
5915 adapter->vfs_allocated_count);
5916 if (err)
5917 goto out;
5918
5919 err = igb_vlvf_set(adapter, vid, add, vf);
5920
5921 if (err)
5922 goto out;
5923
5924 /* Go through all the checks to see if the VLAN filter should
5925 * be wiped completely.
5926 */
5927 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5928 u32 vlvf, bits;
6f3dc319 5929 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 5930
6f3dc319
GR		 5931 if (regndx < 0)
5932 goto out;
5933 /* See if any other pools are set for this VLAN filter
5934 * entry other than the PF.
5935 */
5936 vlvf = bits = rd32(E1000_VLVF(regndx));
5937 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5938 adapter->vfs_allocated_count);
5939 /* If the filter was removed then ensure PF pool bit
5940 * is cleared if the PF only added itself to the pool
5941 * because the PF is in promiscuous mode.
5942 */
5943 if ((vlvf & VLAN_VID_MASK) == vid &&
5944 !test_bit(vid, adapter->active_vlans) &&
5945 !bits)
5946 igb_vlvf_set(adapter, vid, add,
5947 adapter->vfs_allocated_count);
5948 }
5949
5950out:
5951 return err;
4ae196df
AD		 5952}
5953
f2ca0dbe 5954static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5955{
8fa7e0f7
GR		 5956 /* clear flags - except flag that indicates PF has set the MAC */
5957 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5958 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5959
5960 /* reset offloads to defaults */
8151d294 5961 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5962
5963 /* reset vlans for device */
5964 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5965 if (adapter->vf_data[vf].pf_vlan)
5966 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5967 adapter->vf_data[vf].pf_vlan,
5968 adapter->vf_data[vf].pf_qos);
5969 else
5970 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5971
5972 /* reset multicast table array for vf */
5973 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5974
5975 /* Flush and reset the mta with the new values */
ff41f8dc 5976 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5977}
5978
f2ca0dbe
AD		 5979static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5980{
5981 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5982
5ac6f91d 5983 /* clear mac address as we were hotplug removed/added */
8151d294 5984 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5985 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5986
5987 /* process remaining reset events */
5988 igb_vf_reset(adapter, vf);
5989}
5990
5991static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5992{
5993 struct e1000_hw *hw = &adapter->hw;
5994 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5995 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5996 u32 reg, msgbuf[3];
5997 u8 *addr = (u8 *)(&msgbuf[1]);
5998
5999 /* process all the same items cleared in a function level reset */
f2ca0dbe 6000 igb_vf_reset(adapter, vf);
4ae196df
AD		 6001
6002 /* set vf mac address */
26ad9178 6003 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6004
6005 /* enable transmit and receive for vf */
6006 reg = rd32(E1000_VFTE);
6007 wr32(E1000_VFTE, reg | (1 << vf));
6008 reg = rd32(E1000_VFRE);
6009 wr32(E1000_VFRE, reg | (1 << vf));
6010
8fa7e0f7 6011 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6012
6013 /* reply to reset with ack and vf mac address */
6014 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 6015 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 6016 igb_write_mbx(hw, msgbuf, 3, vf);
6017}
6018
6019static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6020{
b980ac18 6021 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6022 * starting at the second 32 bit word of the msg array
6023 */
f2ca0dbe
AD		 6024 unsigned char *addr = (char *)&msg[1];
6025 int err = -1;
4ae196df 6026
f2ca0dbe
AD		 6027 if (is_valid_ether_addr(addr))
6028 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6029
f2ca0dbe 6030 return err;
4ae196df
AD		 6031}
6032
6033static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6034{
6035 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6036 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6037 u32 msg = E1000_VT_MSGTYPE_NACK;
6038
6039 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6040 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6041 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6042 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6043 vf_data->last_nack = jiffies;
4ae196df
AD		 6044 }
6045}
6046
f2ca0dbe 6047static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6048{
f2ca0dbe
AD		 6049 struct pci_dev *pdev = adapter->pdev;
6050 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6051 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6052 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6053 s32 retval;
6054
f2ca0dbe 6055 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6056
fef45f4c
AD		 6057 if (retval) {
6058 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6059 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6060 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6061 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6062 return;
6063 goto out;
6064 }
4ae196df
AD		 6065
6066 /* this is a message we already processed, do nothing */
6067 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6068 return;
4ae196df 6069
b980ac18 6070 /* until the vf completes a reset it should not be
4ae196df
AD		 6071 * allowed to start any configuration.
6072 */
4ae196df
AD		 6073 if (msgbuf[0] == E1000_VF_RESET) {
6074 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6075 return;
4ae196df
AD		 6076 }
6077
f2ca0dbe 6078 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6079 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6080 return;
6081 retval = -1;
6082 goto out;
4ae196df
AD		 6083 }
6084
6085 switch ((msgbuf[0] & 0xFFFF)) {
6086 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6087 retval = -EINVAL;
6088 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6089 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6090 else
6091 dev_warn(&pdev->dev,
b980ac18
JK		 6092 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6093 vf);
4ae196df 6094 break;
7d5753f0
AD		 6095 case E1000_VF_SET_PROMISC:
6096 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6097 break;
4ae196df
AD		 6098 case E1000_VF_SET_MULTICAST:
6099 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6100 break;
6101 case E1000_VF_SET_LPE:
6102 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6103 break;
6104 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6105 retval = -1;
6106 if (vf_data->pf_vlan)
6107 dev_warn(&pdev->dev,
b980ac18
JK		 6108 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6109 vf);
8151d294
WM		 6110 else
6111 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6112 break;
6113 default:
090b1795 6114 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6115 retval = -1;
6116 break;
6117 }
6118
fef45f4c
AD		 6119 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6120out:
4ae196df
AD		 6121 /* notify the VF of the results of what it sent us */
6122 if (retval)
6123 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6124 else
6125 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6126
4ae196df 6127 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6128}
4ae196df 6129
f2ca0dbe
AD		 6130static void igb_msg_task(struct igb_adapter *adapter)
6131{
6132 struct e1000_hw *hw = &adapter->hw;
6133 u32 vf;
6134
6135 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6136 /* process any reset requests */
6137 if (!igb_check_for_rst(hw, vf))
6138 igb_vf_reset_event(adapter, vf);
6139
6140 /* process any messages pending */
6141 if (!igb_check_for_msg(hw, vf))
6142 igb_rcv_msg_from_vf(adapter, vf);
6143
6144 /* process any acks */
6145 if (!igb_check_for_ack(hw, vf))
6146 igb_rcv_ack_from_vf(adapter, vf);
6147 }
4ae196df
AD		 6148}
6149
68d480c4
AD		 6150/**
6151 * igb_set_uta - Set unicast filter table address
6152 * @adapter: board private structure
6153 *
6154 * The unicast table address is a register array of 32-bit registers.
6155 * The table is meant to be used in a way similar to how the MTA is used
6156 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6157 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6158 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6159 **/
6160static void igb_set_uta(struct igb_adapter *adapter)
6161{
6162 struct e1000_hw *hw = &adapter->hw;
6163 int i;
6164
6165 /* The UTA table only exists on 82576 hardware and newer */
6166 if (hw->mac.type < e1000_82576)
6167 return;
6168
6169 /* we only need to do this if VMDq is enabled */
6170 if (!adapter->vfs_allocated_count)
6171 return;
6172
6173 for (i = 0; i < hw->mac.uta_reg_count; i++)
6174 array_wr32(E1000_UTA, i, ~0);
6175}
6176
9d5c8243 6177/**
b980ac18
JK		 6178 * igb_intr_msi - Interrupt Handler
6179 * @irq: interrupt number
6180 * @data: pointer to a network interface device structure
9d5c8243
AK		 6181 **/
6182static irqreturn_t igb_intr_msi(int irq, void *data)
6183{
047e0030
AD		 6184 struct igb_adapter *adapter = data;
6185 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6186 struct e1000_hw *hw = &adapter->hw;
6187 /* read ICR disables interrupts using IAM */
6188 u32 icr = rd32(E1000_ICR);
6189
047e0030 6190 igb_write_itr(q_vector);
9d5c8243 6191
7f081d40
AD		 6192 if (icr & E1000_ICR_DRSTA)
6193 schedule_work(&adapter->reset_task);
6194
047e0030 6195 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6196 /* HW is reporting DMA is out of sync */
6197 adapter->stats.doosync++;
6198 }
6199
9d5c8243
AK		 6200 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6201 hw->mac.get_link_status = 1;
6202 if (!test_bit(__IGB_DOWN, &adapter->state))
6203 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6204 }
6205
1f6e8178
MV		 6206 if (icr & E1000_ICR_TS) {
6207 u32 tsicr = rd32(E1000_TSICR);
6208
6209 if (tsicr & E1000_TSICR_TXTS) {
6210 /* acknowledge the interrupt */
6211 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6212 /* retrieve hardware timestamp */
6213 schedule_work(&adapter->ptp_tx_work);
6214 }
6215 }
1f6e8178 6216
047e0030 6217 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6218
6219 return IRQ_HANDLED;
6220}
6221
6222/**
b980ac18
JK		 6223 * igb_intr - Legacy Interrupt Handler
6224 * @irq: interrupt number
6225 * @data: pointer to a network interface device structure
9d5c8243
AK		 6226 **/
6227static irqreturn_t igb_intr(int irq, void *data)
6228{
047e0030
AD		 6229 struct igb_adapter *adapter = data;
6230 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6231 struct e1000_hw *hw = &adapter->hw;
6232 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6233 * need for the IMC write
6234 */
9d5c8243 6235 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6236
6237 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6238 * not set, then the adapter didn't send an interrupt
6239 */
9d5c8243
AK		 6240 if (!(icr & E1000_ICR_INT_ASSERTED))
6241 return IRQ_NONE;
6242
0ba82994
AD		 6243 igb_write_itr(q_vector);
6244
7f081d40
AD		 6245 if (icr & E1000_ICR_DRSTA)
6246 schedule_work(&adapter->reset_task);
6247
047e0030 6248 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6249 /* HW is reporting DMA is out of sync */
6250 adapter->stats.doosync++;
6251 }
6252
9d5c8243
AK		 6253 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6254 hw->mac.get_link_status = 1;
6255 /* guard against interrupt when we're going down */
6256 if (!test_bit(__IGB_DOWN, &adapter->state))
6257 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6258 }
6259
1f6e8178
MV		 6260 if (icr & E1000_ICR_TS) {
6261 u32 tsicr = rd32(E1000_TSICR);
6262
6263 if (tsicr & E1000_TSICR_TXTS) {
6264 /* acknowledge the interrupt */
6265 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6266 /* retrieve hardware timestamp */
6267 schedule_work(&adapter->ptp_tx_work);
6268 }
6269 }
1f6e8178 6270
047e0030 6271 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6272
6273 return IRQ_HANDLED;
6274}
6275
c50b52a0 6276static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6277{
047e0030 6278 struct igb_adapter *adapter = q_vector->adapter;
46544258 6279 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6280
0ba82994
AD		 6281 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6282 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6283 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6284 igb_set_itr(q_vector);
46544258 6285 else
047e0030 6286 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6287 }
6288
46544258 6289 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6290 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6291 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6292 else
6293 igb_irq_enable(adapter);
6294 }
9d5c8243
AK		 6295}
6296
46544258 6297/**
b980ac18
JK		 6298 * igb_poll - NAPI Rx polling callback
6299 * @napi: napi polling structure
6300 * @budget: count of how many packets we should handle
46544258
AD		 6301 **/
6302static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6303{
047e0030 6304 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6305 struct igb_q_vector,
6306 napi);
16eb8815 6307 bool clean_complete = true;
9d5c8243 6308
421e02f0 6309#ifdef CONFIG_IGB_DCA
047e0030
AD		 6310 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6311 igb_update_dca(q_vector);
fe4506b6 6312#endif
0ba82994 6313 if (q_vector->tx.ring)
13fde97a 6314 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6315
0ba82994 6316 if (q_vector->rx.ring)
cd392f5c 6317 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6318
16eb8815
AD		 6319 /* If all work not completed, return budget and keep polling */
6320 if (!clean_complete)
6321 return budget;
46544258 6322
9d5c8243 6323 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6324 napi_complete(napi);
6325 igb_ring_irq_enable(q_vector);
9d5c8243 6326
16eb8815 6327 return 0;
9d5c8243 6328}
6d8126f9 6329
9d5c8243 6330/**
b980ac18
JK		 6331 * igb_clean_tx_irq - Reclaim resources after transmit completes
6332 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6333 *
b980ac18 6334 * returns true if ring is completely cleaned
9d5c8243 6335 **/
047e0030 6336static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6337{
047e0030 6338 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6339 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6340 struct igb_tx_buffer *tx_buffer;
f4128785 6341 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6342 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6343 unsigned int budget = q_vector->tx.work_limit;
8542db05 6344 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6345
13fde97a
AD		 6346 if (test_bit(__IGB_DOWN, &adapter->state))
6347 return true;
0e014cb1 6348
06034649 6349 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6350 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6351 i -= tx_ring->count;
9d5c8243 6352
f4128785
AD		 6353 do {
6354 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6355
6356 /* if next_to_watch is not set then there is no work pending */
6357 if (!eop_desc)
6358 break;
13fde97a 6359
f4128785 6360 /* prevent any other reads prior to eop_desc */
70d289bc 6361 read_barrier_depends();
f4128785 6362
13fde97a
AD		 6363 /* if DD is not set pending work has not been completed */
6364 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6365 break;
6366
8542db05
AD		 6367 /* clear next_to_watch to prevent false hangs */
6368 tx_buffer->next_to_watch = NULL;
9d5c8243 6369
ebe42d16
AD		 6370 /* update the statistics for this packet */
6371 total_bytes += tx_buffer->bytecount;
6372 total_packets += tx_buffer->gso_segs;
13fde97a 6373
ebe42d16 6374 /* free the skb */
a81fb049 6375 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6376
ebe42d16
AD		 6377 /* unmap skb header data */
6378 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6379 dma_unmap_addr(tx_buffer, dma),
6380 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6381 DMA_TO_DEVICE);
6382
c9f14bf3
AD		 6383 /* clear tx_buffer data */
6384 tx_buffer->skb = NULL;
6385 dma_unmap_len_set(tx_buffer, len, 0);
6386
ebe42d16
AD		 6387 /* clear last DMA location and unmap remaining buffers */
6388 while (tx_desc != eop_desc) {
13fde97a
AD		 6389 tx_buffer++;
6390 tx_desc++;
9d5c8243 6391 i++;
8542db05
AD		 6392 if (unlikely(!i)) {
6393 i -= tx_ring->count;
06034649 6394 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6395 tx_desc = IGB_TX_DESC(tx_ring, 0);
6396 }
ebe42d16
AD		 6397
6398 /* unmap any remaining paged data */
c9f14bf3 6399 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6400 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6401 dma_unmap_addr(tx_buffer, dma),
6402 dma_unmap_len(tx_buffer, len),
ebe42d16 6403 DMA_TO_DEVICE);
c9f14bf3 6404 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6405 }
6406 }
6407
ebe42d16
AD		 6408 /* move us one more past the eop_desc for start of next pkt */
6409 tx_buffer++;
6410 tx_desc++;
6411 i++;
6412 if (unlikely(!i)) {
6413 i -= tx_ring->count;
6414 tx_buffer = tx_ring->tx_buffer_info;
6415 tx_desc = IGB_TX_DESC(tx_ring, 0);
6416 }
f4128785
AD		 6417
6418 /* issue prefetch for next Tx descriptor */
6419 prefetch(tx_desc);
6420
6421 /* update budget accounting */
6422 budget--;
6423 } while (likely(budget));
0e014cb1 6424
bdbc0631
ED		 6425 netdev_tx_completed_queue(txring_txq(tx_ring),
6426 total_packets, total_bytes);
8542db05 6427 i += tx_ring->count;
9d5c8243 6428 tx_ring->next_to_clean = i;
13fde97a
AD		 6429 u64_stats_update_begin(&tx_ring->tx_syncp);
6430 tx_ring->tx_stats.bytes += total_bytes;
6431 tx_ring->tx_stats.packets += total_packets;
6432 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6433 q_vector->tx.total_bytes += total_bytes;
6434 q_vector->tx.total_packets += total_packets;
9d5c8243 6435
6d095fa8 6436 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6437 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6438
9d5c8243 6439 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6440 * check with the clearing of time_stamp and movement of i
6441 */
6d095fa8 6442 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6443 if (tx_buffer->next_to_watch &&
8542db05 6444 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6445 (adapter->tx_timeout_factor * HZ)) &&
6446 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6447
9d5c8243 6448 /* detected Tx unit hang */
59d71989 6449 dev_err(tx_ring->dev,
9d5c8243 6450 "Detected Tx Unit Hang\n"
2d064c06 6451 " Tx Queue <%d>\n"
9d5c8243
AK		 6452 " TDH <%x>\n"
6453 " TDT <%x>\n"
6454 " next_to_use <%x>\n"
6455 " next_to_clean <%x>\n"
9d5c8243
AK		 6456 "buffer_info[next_to_clean]\n"
6457 " time_stamp <%lx>\n"
8542db05 6458 " next_to_watch <%p>\n"
9d5c8243
AK		 6459 " jiffies <%lx>\n"
6460 " desc.status <%x>\n",
2d064c06 6461 tx_ring->queue_index,
238ac817 6462 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6463 readl(tx_ring->tail),
9d5c8243
AK		 6464 tx_ring->next_to_use,
6465 tx_ring->next_to_clean,
8542db05 6466 tx_buffer->time_stamp,
f4128785 6467 tx_buffer->next_to_watch,
9d5c8243 6468 jiffies,
f4128785 6469 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6470 netif_stop_subqueue(tx_ring->netdev,
6471 tx_ring->queue_index);
6472
6473 /* we are about to reset, no point in enabling stuff */
6474 return true;
9d5c8243
AK		 6475 }
6476 }
13fde97a 6477
21ba6fe1 6478#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6479 if (unlikely(total_packets &&
b980ac18
JK		 6480 netif_carrier_ok(tx_ring->netdev) &&
6481 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6482 /* Make sure that anybody stopping the queue after this
6483 * sees the new next_to_clean.
6484 */
6485 smp_mb();
6486 if (__netif_subqueue_stopped(tx_ring->netdev,
6487 tx_ring->queue_index) &&
6488 !(test_bit(__IGB_DOWN, &adapter->state))) {
6489 netif_wake_subqueue(tx_ring->netdev,
6490 tx_ring->queue_index);
6491
6492 u64_stats_update_begin(&tx_ring->tx_syncp);
6493 tx_ring->tx_stats.restart_queue++;
6494 u64_stats_update_end(&tx_ring->tx_syncp);
6495 }
6496 }
6497
6498 return !!budget;
9d5c8243
AK		 6499}
6500
cbc8e55f 6501/**
b980ac18
JK		 6502 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6503 * @rx_ring: rx descriptor ring to store buffers on
6504 * @old_buff: donor buffer to have page reused
cbc8e55f 6505 *
b980ac18 6506 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6507 **/
6508static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6509 struct igb_rx_buffer *old_buff)
6510{
6511 struct igb_rx_buffer *new_buff;
6512 u16 nta = rx_ring->next_to_alloc;
6513
6514 new_buff = &rx_ring->rx_buffer_info[nta];
6515
6516 /* update, and store next to alloc */
6517 nta++;
6518 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6519
6520 /* transfer page from old buffer to new buffer */
a1f63473 6521 *new_buff = *old_buff;
cbc8e55f
AD		 6522
6523 /* sync the buffer for use by the device */
6524 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6525 old_buff->page_offset,
de78d1f9 6526 IGB_RX_BUFSZ,
cbc8e55f
AD		 6527 DMA_FROM_DEVICE);
6528}
6529
74e238ea
AD		 6530static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6531 struct page *page,
6532 unsigned int truesize)
6533{
6534 /* avoid re-using remote pages */
6535 if (unlikely(page_to_nid(page) != numa_node_id()))
6536 return false;
6537
bc16e47f
RG		 6538 if (unlikely(page->pfmemalloc))
6539 return false;
6540
74e238ea
AD		 6541#if (PAGE_SIZE < 8192)
6542 /* if we are only owner of page we can reuse it */
6543 if (unlikely(page_count(page) != 1))
6544 return false;
6545
6546 /* flip page offset to other buffer */
6547 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6548
00cd5adb
ED		 6549 /* Even if we own the page, we are not allowed to use atomic_set()
6550 * This would break get_page_unless_zero() users.
74e238ea 6551 */
00cd5adb 6552 atomic_inc(&page->_count);
74e238ea
AD		 6553#else
6554 /* move offset up to the next cache line */
6555 rx_buffer->page_offset += truesize;
6556
6557 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6558 return false;
6559
6560 /* bump ref count on page before it is given to the stack */
6561 get_page(page);
6562#endif
6563
6564 return true;
6565}
6566
cbc8e55f 6567/**
b980ac18
JK		 6568 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6569 * @rx_ring: rx descriptor ring to transact packets on
6570 * @rx_buffer: buffer containing page to add
6571 * @rx_desc: descriptor containing length of buffer written by hardware
6572 * @skb: sk_buff to place the data into
cbc8e55f 6573 *
b980ac18
JK		 6574 * This function will add the data contained in rx_buffer->page to the skb.
6575 * This is done either through a direct copy if the data in the buffer is
6576 * less than the skb header size, otherwise it will just attach the page as
6577 * a frag to the skb.
cbc8e55f 6578 *
b980ac18
JK		 6579 * The function will then update the page offset if necessary and return
6580 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6581 **/
6582static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6583 struct igb_rx_buffer *rx_buffer,
6584 union e1000_adv_rx_desc *rx_desc,
6585 struct sk_buff *skb)
6586{
6587 struct page *page = rx_buffer->page;
6588 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6589#if (PAGE_SIZE < 8192)
6590 unsigned int truesize = IGB_RX_BUFSZ;
6591#else
6592 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6593#endif
cbc8e55f
AD		 6594
6595 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6596 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6597
cbc8e55f
AD		 6598 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6599 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6600 va += IGB_TS_HDR_LEN;
6601 size -= IGB_TS_HDR_LEN;
6602 }
6603
cbc8e55f
AD		 6604 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6605
6606 /* we can reuse buffer as-is, just make sure it is local */
bc16e47f
RG		 6607 if (likely((page_to_nid(page) == numa_node_id()) &&
6608 !page->pfmemalloc))
cbc8e55f
AD		 6609 return true;
6610
6611 /* this page cannot be reused so discard it */
6612 put_page(page);
6613 return false;
6614 }
6615
6616 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6617 rx_buffer->page_offset, size, truesize);
cbc8e55f 6618
74e238ea
AD		 6619 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6620}
cbc8e55f 6621
2e334eee
AD		 6622static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6623 union e1000_adv_rx_desc *rx_desc,
6624 struct sk_buff *skb)
6625{
6626 struct igb_rx_buffer *rx_buffer;
6627 struct page *page;
6628
6629 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6630
2e334eee
AD		 6631 page = rx_buffer->page;
6632 prefetchw(page);
6633
6634 if (likely(!skb)) {
6635 void *page_addr = page_address(page) +
6636 rx_buffer->page_offset;
6637
6638 /* prefetch first cache line of first page */
6639 prefetch(page_addr);
6640#if L1_CACHE_BYTES < 128
6641 prefetch(page_addr + L1_CACHE_BYTES);
6642#endif
6643
6644 /* allocate a skb to store the frags */
6645 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6646 IGB_RX_HDR_LEN);
6647 if (unlikely(!skb)) {
6648 rx_ring->rx_stats.alloc_failed++;
6649 return NULL;
6650 }
6651
b980ac18 6652 /* we will be copying header into skb->data in
2e334eee
AD		 6653 * pskb_may_pull so it is in our interest to prefetch
6654 * it now to avoid a possible cache miss
6655 */
6656 prefetchw(skb->data);
6657 }
6658
6659 /* we are reusing so sync this buffer for CPU use */
6660 dma_sync_single_range_for_cpu(rx_ring->dev,
6661 rx_buffer->dma,
6662 rx_buffer->page_offset,
de78d1f9 6663 IGB_RX_BUFSZ,
2e334eee
AD		 6664 DMA_FROM_DEVICE);
6665
6666 /* pull page into skb */
6667 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6668 /* hand second half of page back to the ring */
6669 igb_reuse_rx_page(rx_ring, rx_buffer);
6670 } else {
6671 /* we are not reusing the buffer so unmap it */
6672 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6673 PAGE_SIZE, DMA_FROM_DEVICE);
6674 }
6675
6676 /* clear contents of rx_buffer */
6677 rx_buffer->page = NULL;
6678
6679 return skb;
6680}
6681
cd392f5c 6682static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6683 union e1000_adv_rx_desc *rx_desc,
6684 struct sk_buff *skb)
9d5c8243 6685{
bc8acf2c 6686 skb_checksum_none_assert(skb);
9d5c8243 6687
294e7d78 6688 /* Ignore Checksum bit is set */
3ceb90fd 6689 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6690 return;
6691
6692 /* Rx checksum disabled via ethtool */
6693 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6694 return;
85ad76b2 6695
9d5c8243 6696 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6697 if (igb_test_staterr(rx_desc,
6698 E1000_RXDEXT_STATERR_TCPE |
6699 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6700 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6701 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6702 * packets, (aka let the stack check the crc32c)
6703 */
866cff06
AD		 6704 if (!((skb->len == 60) &&
6705 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6706 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6707 ring->rx_stats.csum_err++;
12dcd86b
ED		 6708 u64_stats_update_end(&ring->rx_syncp);
6709 }
9d5c8243 6710 /* let the stack verify checksum errors */
9d5c8243
AK		 6711 return;
6712 }
6713 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6714 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6715 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6716 skb->ip_summed = CHECKSUM_UNNECESSARY;
6717
3ceb90fd
AD		 6718 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6719 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6720}
6721
077887c3
AD		 6722static inline void igb_rx_hash(struct igb_ring *ring,
6723 union e1000_adv_rx_desc *rx_desc,
6724 struct sk_buff *skb)
6725{
6726 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6727 skb_set_hash(skb,
6728 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6729 PKT_HASH_TYPE_L3);
077887c3
AD		 6730}
6731
2e334eee 6732/**
b980ac18
JK		 6733 * igb_is_non_eop - process handling of non-EOP buffers
6734 * @rx_ring: Rx ring being processed
6735 * @rx_desc: Rx descriptor for current buffer
6736 * @skb: current socket buffer containing buffer in progress
2e334eee 6737 *
b980ac18
JK		 6738 * This function updates next to clean. If the buffer is an EOP buffer
6739 * this function exits returning false, otherwise it will place the
6740 * sk_buff in the next buffer to be chained and return true indicating
6741 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6742 **/
6743static bool igb_is_non_eop(struct igb_ring *rx_ring,
6744 union e1000_adv_rx_desc *rx_desc)
6745{
6746 u32 ntc = rx_ring->next_to_clean + 1;
6747
6748 /* fetch, update, and store next to clean */
6749 ntc = (ntc < rx_ring->count) ? ntc : 0;
6750 rx_ring->next_to_clean = ntc;
6751
6752 prefetch(IGB_RX_DESC(rx_ring, ntc));
6753
6754 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6755 return false;
6756
6757 return true;
6758}
6759
1a1c225b 6760/**
b980ac18
JK		 6761 * igb_pull_tail - igb specific version of skb_pull_tail
6762 * @rx_ring: rx descriptor ring packet is being transacted on
6763 * @rx_desc: pointer to the EOP Rx descriptor
6764 * @skb: pointer to current skb being adjusted
1a1c225b 6765 *
b980ac18
JK		 6766 * This function is an igb specific version of __pskb_pull_tail. The
6767 * main difference between this version and the original function is that
6768 * this function can make several assumptions about the state of things
6769 * that allow for significant optimizations versus the standard function.
6770 * As a result we can do things like drop a frag and maintain an accurate
6771 * truesize for the skb.
1a1c225b
AD		 6772 */
6773static void igb_pull_tail(struct igb_ring *rx_ring,
6774 union e1000_adv_rx_desc *rx_desc,
6775 struct sk_buff *skb)
2d94d8ab 6776{
1a1c225b
AD		 6777 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6778 unsigned char *va;
6779 unsigned int pull_len;
6780
b980ac18 6781 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6782 * working with pages allocated out of the lomem pool per
6783 * alloc_page(GFP_ATOMIC)
2d94d8ab 6784 */
1a1c225b
AD		 6785 va = skb_frag_address(frag);
6786
1a1c225b
AD		 6787 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6788 /* retrieve timestamp from buffer */
6789 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6790
6791 /* update pointers to remove timestamp header */
6792 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6793 frag->page_offset += IGB_TS_HDR_LEN;
6794 skb->data_len -= IGB_TS_HDR_LEN;
6795 skb->len -= IGB_TS_HDR_LEN;
6796
6797 /* move va to start of packet data */
6798 va += IGB_TS_HDR_LEN;
6799 }
6800
b980ac18 6801 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6802 * 60 bytes if the skb->len is less than 60 for skb_pad.
6803 */
24cd23d3 6804 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
1a1c225b
AD		 6805
6806 /* align pull length to size of long to optimize memcpy performance */
6807 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6808
6809 /* update all of the pointers */
6810 skb_frag_size_sub(frag, pull_len);
6811 frag->page_offset += pull_len;
6812 skb->data_len -= pull_len;
6813 skb->tail += pull_len;
6814}
6815
6816/**
b980ac18
JK		 6817 * igb_cleanup_headers - Correct corrupted or empty headers
6818 * @rx_ring: rx descriptor ring packet is being transacted on
6819 * @rx_desc: pointer to the EOP Rx descriptor
6820 * @skb: pointer to current skb being fixed
1a1c225b 6821 *
b980ac18
JK		 6822 * Address the case where we are pulling data in on pages only
6823 * and as such no data is present in the skb header.
1a1c225b 6824 *
b980ac18
JK		 6825 * In addition if skb is not at least 60 bytes we need to pad it so that
6826 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6827 *
b980ac18 6828 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6829 **/
6830static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6831 union e1000_adv_rx_desc *rx_desc,
6832 struct sk_buff *skb)
6833{
1a1c225b
AD		 6834 if (unlikely((igb_test_staterr(rx_desc,
6835 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6836 struct net_device *netdev = rx_ring->netdev;
6837 if (!(netdev->features & NETIF_F_RXALL)) {
6838 dev_kfree_skb_any(skb);
6839 return true;
6840 }
6841 }
6842
6843 /* place header in linear portion of buffer */
6844 if (skb_is_nonlinear(skb))
6845 igb_pull_tail(rx_ring, rx_desc, skb);
6846
6847 /* if skb_pad returns an error the skb was freed */
6848 if (unlikely(skb->len < 60)) {
6849 int pad_len = 60 - skb->len;
6850
6851 if (skb_pad(skb, pad_len))
6852 return true;
6853 __skb_put(skb, pad_len);
6854 }
6855
6856 return false;
2d94d8ab
AD		 6857}
6858
db2ee5bd 6859/**
b980ac18
JK		 6860 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6861 * @rx_ring: rx descriptor ring packet is being transacted on
6862 * @rx_desc: pointer to the EOP Rx descriptor
6863 * @skb: pointer to current skb being populated
db2ee5bd 6864 *
b980ac18
JK		 6865 * This function checks the ring, descriptor, and packet information in
6866 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6867 * other fields within the skb.
db2ee5bd
AD		 6868 **/
6869static void igb_process_skb_fields(struct igb_ring *rx_ring,
6870 union e1000_adv_rx_desc *rx_desc,
6871 struct sk_buff *skb)
6872{
6873 struct net_device *dev = rx_ring->netdev;
6874
6875 igb_rx_hash(rx_ring, rx_desc, skb);
6876
6877 igb_rx_checksum(rx_ring, rx_desc, skb);
6878
5499a968
JK		 6879 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6880 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6881 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6882
f646968f 6883 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6884 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6885 u16 vid;
9005df38 6886
db2ee5bd
AD		 6887 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6888 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6889 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6890 else
6891 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6892
86a9bad3 6893 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6894 }
6895
6896 skb_record_rx_queue(skb, rx_ring->queue_index);
6897
6898 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6899}
6900
2e334eee 6901static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6902{
0ba82994 6903 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6904 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6905 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6906 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6907
57ba34c9 6908 while (likely(total_packets < budget)) {
2e334eee 6909 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6910
2e334eee
AD		 6911 /* return some buffers to hardware, one at a time is too slow */
6912 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6913 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6914 cleaned_count = 0;
6915 }
bf36c1a0 6916
2e334eee 6917 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6918
2e334eee
AD		 6919 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6920 break;
9d5c8243 6921
74e238ea
AD		 6922 /* This memory barrier is needed to keep us from reading
6923 * any other fields out of the rx_desc until we know the
6924 * RXD_STAT_DD bit is set
6925 */
6926 rmb();
6927
2e334eee 6928 /* retrieve a buffer from the ring */
f9d40f6a 6929 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6930
2e334eee
AD		 6931 /* exit if we failed to retrieve a buffer */
6932 if (!skb)
6933 break;
1a1c225b 6934
2e334eee 6935 cleaned_count++;
1a1c225b 6936
2e334eee
AD		 6937 /* fetch next buffer in frame if non-eop */
6938 if (igb_is_non_eop(rx_ring, rx_desc))
6939 continue;
1a1c225b
AD		 6940
6941 /* verify the packet layout is correct */
6942 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6943 skb = NULL;
6944 continue;
9d5c8243 6945 }
9d5c8243 6946
db2ee5bd 6947 /* probably a little skewed due to removing CRC */
3ceb90fd 6948 total_bytes += skb->len;
3ceb90fd 6949
db2ee5bd
AD		 6950 /* populate checksum, timestamp, VLAN, and protocol */
6951 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6952
b2cb09b1 6953 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6954
1a1c225b
AD		 6955 /* reset skb pointer */
6956 skb = NULL;
6957
2e334eee
AD		 6958 /* update budget accounting */
6959 total_packets++;
57ba34c9 6960 }
bf36c1a0 6961
1a1c225b
AD		 6962 /* place incomplete frames back on ring for completion */
6963 rx_ring->skb = skb;
6964
12dcd86b 6965 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6966 rx_ring->rx_stats.packets += total_packets;
6967 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6968 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6969 q_vector->rx.total_packets += total_packets;
6970 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6971
6972 if (cleaned_count)
cd392f5c 6973 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6974
da1f1dfe 6975 return total_packets < budget;
9d5c8243
AK		 6976}
6977
c023cd88 6978static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6979 struct igb_rx_buffer *bi)
c023cd88
AD		 6980{
6981 struct page *page = bi->page;
cbc8e55f 6982 dma_addr_t dma;
c023cd88 6983
cbc8e55f
AD		 6984 /* since we are recycling buffers we should seldom need to alloc */
6985 if (likely(page))
c023cd88
AD		 6986 return true;
6987
cbc8e55f
AD		 6988 /* alloc new page for storage */
6989 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6990 if (unlikely(!page)) {
6991 rx_ring->rx_stats.alloc_failed++;
6992 return false;
c023cd88
AD		 6993 }
6994
cbc8e55f
AD		 6995 /* map page for use */
6996 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6997
b980ac18 6998 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6999 * there isn't much point in holding memory we can't use
7000 */
1a1c225b 7001 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7002 __free_page(page);
7003
c023cd88
AD		 7004 rx_ring->rx_stats.alloc_failed++;
7005 return false;
7006 }
7007
1a1c225b 7008 bi->dma = dma;
cbc8e55f
AD		 7009 bi->page = page;
7010 bi->page_offset = 0;
1a1c225b 7011
c023cd88
AD		 7012 return true;
7013}
7014
9d5c8243 7015/**
b980ac18
JK		 7016 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7017 * @adapter: address of board private structure
9d5c8243 7018 **/
cd392f5c 7019void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7020{
9d5c8243 7021 union e1000_adv_rx_desc *rx_desc;
06034649 7022 struct igb_rx_buffer *bi;
c023cd88 7023 u16 i = rx_ring->next_to_use;
9d5c8243 7024
cbc8e55f
AD		 7025 /* nothing to do */
7026 if (!cleaned_count)
7027 return;
7028
60136906 7029 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7030 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7031 i -= rx_ring->count;
9d5c8243 7032
cbc8e55f 7033 do {
1a1c225b 7034 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7035 break;
9d5c8243 7036
b980ac18 7037 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7038 * because each write-back erases this info.
7039 */
f9d40f6a 7040 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7041
c023cd88
AD		 7042 rx_desc++;
7043 bi++;
9d5c8243 7044 i++;
c023cd88 7045 if (unlikely(!i)) {
60136906 7046 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7047 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7048 i -= rx_ring->count;
7049 }
7050
7051 /* clear the hdr_addr for the next_to_use descriptor */
7052 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7053
7054 cleaned_count--;
7055 } while (cleaned_count);
9d5c8243 7056
c023cd88
AD		 7057 i += rx_ring->count;
7058
9d5c8243 7059 if (rx_ring->next_to_use != i) {
cbc8e55f 7060 /* record the next descriptor to use */
9d5c8243 7061 rx_ring->next_to_use = i;
9d5c8243 7062
cbc8e55f
AD		 7063 /* update next to alloc since we have filled the ring */
7064 rx_ring->next_to_alloc = i;
7065
b980ac18 7066 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7067 * know there are new descriptors to fetch. (Only
7068 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7069 * such as IA-64).
7070 */
9d5c8243 7071 wmb();
fce99e34 7072 writel(i, rx_ring->tail);
9d5c8243
AK		 7073 }
7074}
7075
7076/**
7077 * igb_mii_ioctl -
7078 * @netdev:
7079 * @ifreq:
7080 * @cmd:
7081 **/
7082static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7083{
7084 struct igb_adapter *adapter = netdev_priv(netdev);
7085 struct mii_ioctl_data *data = if_mii(ifr);
7086
7087 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7088 return -EOPNOTSUPP;
7089
7090 switch (cmd) {
7091 case SIOCGMIIPHY:
7092 data->phy_id = adapter->hw.phy.addr;
7093 break;
7094 case SIOCGMIIREG:
f5f4cf08 7095 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7096 &data->val_out))
9d5c8243
AK		 7097 return -EIO;
7098 break;
7099 case SIOCSMIIREG:
7100 default:
7101 return -EOPNOTSUPP;
7102 }
7103 return 0;
7104}
7105
7106/**
7107 * igb_ioctl -
7108 * @netdev:
7109 * @ifreq:
7110 * @cmd:
7111 **/
7112static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7113{
7114 switch (cmd) {
7115 case SIOCGMIIPHY:
7116 case SIOCGMIIREG:
7117 case SIOCSMIIREG:
7118 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7119 case SIOCGHWTSTAMP:
7120 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7121 case SIOCSHWTSTAMP:
6ab5f7b2 7122 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7123 default:
7124 return -EOPNOTSUPP;
7125 }
7126}
7127
94826487
TF		 7128void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7129{
7130 struct igb_adapter *adapter = hw->back;
7131
7132 pci_read_config_word(adapter->pdev, reg, value);
7133}
7134
7135void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7136{
7137 struct igb_adapter *adapter = hw->back;
7138
7139 pci_write_config_word(adapter->pdev, reg, *value);
7140}
7141
009bc06e
AD		 7142s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7143{
7144 struct igb_adapter *adapter = hw->back;
009bc06e 7145
23d028cc 7146 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7147 return -E1000_ERR_CONFIG;
7148
009bc06e
AD		 7149 return 0;
7150}
7151
7152s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7153{
7154 struct igb_adapter *adapter = hw->back;
009bc06e 7155
23d028cc 7156 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7157 return -E1000_ERR_CONFIG;
7158
009bc06e
AD		 7159 return 0;
7160}
7161
c8f44aff 7162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7163{
7164 struct igb_adapter *adapter = netdev_priv(netdev);
7165 struct e1000_hw *hw = &adapter->hw;
7166 u32 ctrl, rctl;
f646968f 7167 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7168
5faf030c 7169 if (enable) {
9d5c8243
AK		 7170 /* enable VLAN tag insert/strip */
7171 ctrl = rd32(E1000_CTRL);
7172 ctrl |= E1000_CTRL_VME;
7173 wr32(E1000_CTRL, ctrl);
7174
51466239 7175 /* Disable CFI check */
9d5c8243 7176 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7177 rctl &= ~E1000_RCTL_CFIEN;
7178 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7179 } else {
7180 /* disable VLAN tag insert/strip */
7181 ctrl = rd32(E1000_CTRL);
7182 ctrl &= ~E1000_CTRL_VME;
7183 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7184 }
7185
e1739522 7186 igb_rlpml_set(adapter);
9d5c8243
AK		 7187}
7188
80d5c368
PM		 7189static int igb_vlan_rx_add_vid(struct net_device *netdev,
7190 __be16 proto, u16 vid)
9d5c8243
AK		 7191{
7192 struct igb_adapter *adapter = netdev_priv(netdev);
7193 struct e1000_hw *hw = &adapter->hw;
4ae196df 7194 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7195
51466239
AD		 7196 /* attempt to add filter to vlvf array */
7197 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7198
51466239
AD		 7199 /* add the filter since PF can receive vlans w/o entry in vlvf */
7200 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7201
7202 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7203
7204 return 0;
9d5c8243
AK		 7205}
7206
80d5c368
PM		 7207static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7208 __be16 proto, u16 vid)
9d5c8243
AK		 7209{
7210 struct igb_adapter *adapter = netdev_priv(netdev);
7211 struct e1000_hw *hw = &adapter->hw;
4ae196df 7212 int pf_id = adapter->vfs_allocated_count;
51466239 7213 s32 err;
9d5c8243 7214
51466239
AD		 7215 /* remove vlan from VLVF table array */
7216 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7217
51466239
AD		 7218 /* if vid was not present in VLVF just remove it from table */
7219 if (err)
4ae196df 7220 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7221
7222 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7223
7224 return 0;
9d5c8243
AK		 7225}
7226
7227static void igb_restore_vlan(struct igb_adapter *adapter)
7228{
b2cb09b1 7229 u16 vid;
9d5c8243 7230
5faf030c
AD		 7231 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7232
b2cb09b1 7233 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7234 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7235}
7236
14ad2513 7237int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7238{
090b1795 7239 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7240 struct e1000_mac_info *mac = &adapter->hw.mac;
7241
7242 mac->autoneg = 0;
7243
14ad2513 7244 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7245 * for the switch() below to work
7246 */
14ad2513
DD		 7247 if ((spd & 1) || (dplx & ~1))
7248 goto err_inval;
7249
f502ef7d
AA		 7250 /* Fiber NIC's only allow 1000 gbps Full duplex
7251 * and 100Mbps Full duplex for 100baseFx sfp
7252 */
7253 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7254 switch (spd + dplx) {
7255 case SPEED_10 + DUPLEX_HALF:
7256 case SPEED_10 + DUPLEX_FULL:
7257 case SPEED_100 + DUPLEX_HALF:
7258 goto err_inval;
7259 default:
7260 break;
7261 }
7262 }
cd2638a8 7263
14ad2513 7264 switch (spd + dplx) {
9d5c8243
AK		 7265 case SPEED_10 + DUPLEX_HALF:
7266 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7267 break;
7268 case SPEED_10 + DUPLEX_FULL:
7269 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7270 break;
7271 case SPEED_100 + DUPLEX_HALF:
7272 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7273 break;
7274 case SPEED_100 + DUPLEX_FULL:
7275 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7276 break;
7277 case SPEED_1000 + DUPLEX_FULL:
7278 mac->autoneg = 1;
7279 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7280 break;
7281 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7282 default:
14ad2513 7283 goto err_inval;
9d5c8243 7284 }
8376dad0
JB		 7285
7286 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7287 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7288
9d5c8243 7289 return 0;
14ad2513
DD		 7290
7291err_inval:
7292 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7293 return -EINVAL;
9d5c8243
AK		 7294}
7295
749ab2cd
YZ		 7296static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7297 bool runtime)
9d5c8243
AK		 7298{
7299 struct net_device *netdev = pci_get_drvdata(pdev);
7300 struct igb_adapter *adapter = netdev_priv(netdev);
7301 struct e1000_hw *hw = &adapter->hw;
2d064c06 7302 u32 ctrl, rctl, status;
749ab2cd 7303 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7304#ifdef CONFIG_PM
7305 int retval = 0;
7306#endif
7307
7308 netif_device_detach(netdev);
7309
a88f10ec 7310 if (netif_running(netdev))
749ab2cd 7311 __igb_close(netdev, true);
a88f10ec 7312
047e0030 7313 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7314
7315#ifdef CONFIG_PM
7316 retval = pci_save_state(pdev);
7317 if (retval)
7318 return retval;
7319#endif
7320
7321 status = rd32(E1000_STATUS);
7322 if (status & E1000_STATUS_LU)
7323 wufc &= ~E1000_WUFC_LNKC;
7324
7325 if (wufc) {
7326 igb_setup_rctl(adapter);
ff41f8dc 7327 igb_set_rx_mode(netdev);
9d5c8243
AK		 7328
7329 /* turn on all-multi mode if wake on multicast is enabled */
7330 if (wufc & E1000_WUFC_MC) {
7331 rctl = rd32(E1000_RCTL);
7332 rctl |= E1000_RCTL_MPE;
7333 wr32(E1000_RCTL, rctl);
7334 }
7335
7336 ctrl = rd32(E1000_CTRL);
7337 /* advertise wake from D3Cold */
7338 #define E1000_CTRL_ADVD3WUC 0x00100000
7339 /* phy power management enable */
7340 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7341 ctrl |= E1000_CTRL_ADVD3WUC;
7342 wr32(E1000_CTRL, ctrl);
7343
9d5c8243 7344 /* Allow time for pending master requests to run */
330a6d6a 7345 igb_disable_pcie_master(hw);
9d5c8243
AK		 7346
7347 wr32(E1000_WUC, E1000_WUC_PME_EN);
7348 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7349 } else {
7350 wr32(E1000_WUC, 0);
7351 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7352 }
7353
3fe7c4c9
RW		 7354 *enable_wake = wufc || adapter->en_mng_pt;
7355 if (!*enable_wake)
88a268c1
NN		 7356 igb_power_down_link(adapter);
7357 else
7358 igb_power_up_link(adapter);
9d5c8243
AK		 7359
7360 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7361 * would have already happened in close and is redundant.
7362 */
9d5c8243
AK		 7363 igb_release_hw_control(adapter);
7364
7365 pci_disable_device(pdev);
7366
9d5c8243
AK		 7367 return 0;
7368}
7369
7370#ifdef CONFIG_PM
d9dd966d 7371#ifdef CONFIG_PM_SLEEP
749ab2cd 7372static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7373{
7374 int retval;
7375 bool wake;
749ab2cd 7376 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7377
749ab2cd 7378 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7379 if (retval)
7380 return retval;
7381
7382 if (wake) {
7383 pci_prepare_to_sleep(pdev);
7384 } else {
7385 pci_wake_from_d3(pdev, false);
7386 pci_set_power_state(pdev, PCI_D3hot);
7387 }
7388
7389 return 0;
7390}
d9dd966d 7391#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7392
749ab2cd 7393static int igb_resume(struct device *dev)
9d5c8243 7394{
749ab2cd 7395 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7396 struct net_device *netdev = pci_get_drvdata(pdev);
7397 struct igb_adapter *adapter = netdev_priv(netdev);
7398 struct e1000_hw *hw = &adapter->hw;
7399 u32 err;
7400
7401 pci_set_power_state(pdev, PCI_D0);
7402 pci_restore_state(pdev);
b94f2d77 7403 pci_save_state(pdev);
42bfd33a 7404
aed5dec3 7405 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7406 if (err) {
7407 dev_err(&pdev->dev,
7408 "igb: Cannot enable PCI device from suspend\n");
7409 return err;
7410 }
7411 pci_set_master(pdev);
7412
7413 pci_enable_wake(pdev, PCI_D3hot, 0);
7414 pci_enable_wake(pdev, PCI_D3cold, 0);
7415
53c7d064 7416 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7417 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7418 return -ENOMEM;
9d5c8243
AK		 7419 }
7420
9d5c8243 7421 igb_reset(adapter);
a8564f03
AD		 7422
7423 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7424 * driver.
7425 */
a8564f03
AD		 7426 igb_get_hw_control(adapter);
7427
9d5c8243
AK		 7428 wr32(E1000_WUS, ~0);
7429
749ab2cd 7430 if (netdev->flags & IFF_UP) {
0c2cc02e 7431 rtnl_lock();
749ab2cd 7432 err = __igb_open(netdev, true);
0c2cc02e 7433 rtnl_unlock();
a88f10ec
AD		 7434 if (err)
7435 return err;
7436 }
9d5c8243
AK		 7437
7438 netif_device_attach(netdev);
749ab2cd
YZ		 7439 return 0;
7440}
7441
749ab2cd
YZ		 7442static int igb_runtime_idle(struct device *dev)
7443{
7444 struct pci_dev *pdev = to_pci_dev(dev);
7445 struct net_device *netdev = pci_get_drvdata(pdev);
7446 struct igb_adapter *adapter = netdev_priv(netdev);
7447
7448 if (!igb_has_link(adapter))
7449 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7450
7451 return -EBUSY;
7452}
7453
7454static int igb_runtime_suspend(struct device *dev)
7455{
7456 struct pci_dev *pdev = to_pci_dev(dev);
7457 int retval;
7458 bool wake;
7459
7460 retval = __igb_shutdown(pdev, &wake, 1);
7461 if (retval)
7462 return retval;
7463
7464 if (wake) {
7465 pci_prepare_to_sleep(pdev);
7466 } else {
7467 pci_wake_from_d3(pdev, false);
7468 pci_set_power_state(pdev, PCI_D3hot);
7469 }
9d5c8243 7470
9d5c8243
AK		 7471 return 0;
7472}
749ab2cd
YZ		 7473
7474static int igb_runtime_resume(struct device *dev)
7475{
7476 return igb_resume(dev);
7477}
d61c81cb 7478#endif /* CONFIG_PM */
9d5c8243
AK		 7479
7480static void igb_shutdown(struct pci_dev *pdev)
7481{
3fe7c4c9
RW		 7482 bool wake;
7483
749ab2cd 7484 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7485
7486 if (system_state == SYSTEM_POWER_OFF) {
7487 pci_wake_from_d3(pdev, wake);
7488 pci_set_power_state(pdev, PCI_D3hot);
7489 }
9d5c8243
AK		 7490}
7491
fa44f2f1
GR		 7492#ifdef CONFIG_PCI_IOV
7493static int igb_sriov_reinit(struct pci_dev *dev)
7494{
7495 struct net_device *netdev = pci_get_drvdata(dev);
7496 struct igb_adapter *adapter = netdev_priv(netdev);
7497 struct pci_dev *pdev = adapter->pdev;
7498
7499 rtnl_lock();
7500
7501 if (netif_running(netdev))
7502 igb_close(netdev);
76252723
SA		 7503 else
7504 igb_reset(adapter);
fa44f2f1
GR		 7505
7506 igb_clear_interrupt_scheme(adapter);
7507
7508 igb_init_queue_configuration(adapter);
7509
7510 if (igb_init_interrupt_scheme(adapter, true)) {
7511 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7512 return -ENOMEM;
7513 }
7514
7515 if (netif_running(netdev))
7516 igb_open(netdev);
7517
7518 rtnl_unlock();
7519
7520 return 0;
7521}
7522
7523static int igb_pci_disable_sriov(struct pci_dev *dev)
7524{
7525 int err = igb_disable_sriov(dev);
7526
7527 if (!err)
7528 err = igb_sriov_reinit(dev);
7529
7530 return err;
7531}
7532
7533static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7534{
7535 int err = igb_enable_sriov(dev, num_vfs);
7536
7537 if (err)
7538 goto out;
7539
7540 err = igb_sriov_reinit(dev);
7541 if (!err)
7542 return num_vfs;
7543
7544out:
7545 return err;
7546}
7547
7548#endif
7549static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7550{
7551#ifdef CONFIG_PCI_IOV
7552 if (num_vfs == 0)
7553 return igb_pci_disable_sriov(dev);
7554 else
7555 return igb_pci_enable_sriov(dev, num_vfs);
7556#endif
7557 return 0;
7558}
7559
9d5c8243 7560#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7561/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7562 * without having to re-enable interrupts. It's not called while
7563 * the interrupt routine is executing.
7564 */
7565static void igb_netpoll(struct net_device *netdev)
7566{
7567 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7568 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7569 struct igb_q_vector *q_vector;
9d5c8243 7570 int i;
9d5c8243 7571
047e0030 7572 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7573 q_vector = adapter->q_vector[i];
cd14ef54 7574 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7575 wr32(E1000_EIMC, q_vector->eims_value);
7576 else
7577 igb_irq_disable(adapter);
047e0030 7578 napi_schedule(&q_vector->napi);
eebbbdba 7579 }
9d5c8243
AK		 7580}
7581#endif /* CONFIG_NET_POLL_CONTROLLER */
7582
7583/**
b980ac18
JK		 7584 * igb_io_error_detected - called when PCI error is detected
7585 * @pdev: Pointer to PCI device
7586 * @state: The current pci connection state
9d5c8243 7587 *
b980ac18
JK		 7588 * This function is called after a PCI bus error affecting
7589 * this device has been detected.
7590 **/
9d5c8243
AK		 7591static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7592 pci_channel_state_t state)
7593{
7594 struct net_device *netdev = pci_get_drvdata(pdev);
7595 struct igb_adapter *adapter = netdev_priv(netdev);
7596
7597 netif_device_detach(netdev);
7598
59ed6eec
AD		 7599 if (state == pci_channel_io_perm_failure)
7600 return PCI_ERS_RESULT_DISCONNECT;
7601
9d5c8243
AK		 7602 if (netif_running(netdev))
7603 igb_down(adapter);
7604 pci_disable_device(pdev);
7605
7606 /* Request a slot slot reset. */
7607 return PCI_ERS_RESULT_NEED_RESET;
7608}
7609
7610/**
b980ac18
JK		 7611 * igb_io_slot_reset - called after the pci bus has been reset.
7612 * @pdev: Pointer to PCI device
9d5c8243 7613 *
b980ac18
JK		 7614 * Restart the card from scratch, as if from a cold-boot. Implementation
7615 * resembles the first-half of the igb_resume routine.
7616 **/
9d5c8243
AK		 7617static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7618{
7619 struct net_device *netdev = pci_get_drvdata(pdev);
7620 struct igb_adapter *adapter = netdev_priv(netdev);
7621 struct e1000_hw *hw = &adapter->hw;
40a914fa 7622 pci_ers_result_t result;
42bfd33a 7623 int err;
9d5c8243 7624
aed5dec3 7625 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7626 dev_err(&pdev->dev,
7627 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7628 result = PCI_ERS_RESULT_DISCONNECT;
7629 } else {
7630 pci_set_master(pdev);
7631 pci_restore_state(pdev);
b94f2d77 7632 pci_save_state(pdev);
9d5c8243 7633
40a914fa
AD		 7634 pci_enable_wake(pdev, PCI_D3hot, 0);
7635 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7636
40a914fa
AD		 7637 igb_reset(adapter);
7638 wr32(E1000_WUS, ~0);
7639 result = PCI_ERS_RESULT_RECOVERED;
7640 }
9d5c8243 7641
ea943d41
JK		 7642 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7643 if (err) {
b980ac18
JK		 7644 dev_err(&pdev->dev,
7645 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7646 err);
ea943d41
JK		 7647 /* non-fatal, continue */
7648 }
40a914fa
AD		 7649
7650 return result;
9d5c8243
AK		 7651}
7652
7653/**
b980ac18
JK		 7654 * igb_io_resume - called when traffic can start flowing again.
7655 * @pdev: Pointer to PCI device
9d5c8243 7656 *
b980ac18
JK		 7657 * This callback is called when the error recovery driver tells us that
7658 * its OK to resume normal operation. Implementation resembles the
7659 * second-half of the igb_resume routine.
9d5c8243
AK		 7660 */
7661static void igb_io_resume(struct pci_dev *pdev)
7662{
7663 struct net_device *netdev = pci_get_drvdata(pdev);
7664 struct igb_adapter *adapter = netdev_priv(netdev);
7665
9d5c8243
AK		 7666 if (netif_running(netdev)) {
7667 if (igb_up(adapter)) {
7668 dev_err(&pdev->dev, "igb_up failed after reset\n");
7669 return;
7670 }
7671 }
7672
7673 netif_device_attach(netdev);
7674
7675 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7676 * driver.
7677 */
9d5c8243 7678 igb_get_hw_control(adapter);
9d5c8243
AK		 7679}
7680
26ad9178 7681static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7682 u8 qsel)
26ad9178
AD		 7683{
7684 u32 rar_low, rar_high;
7685 struct e1000_hw *hw = &adapter->hw;
7686
7687 /* HW expects these in little endian so we reverse the byte order
7688 * from network order (big endian) to little endian
7689 */
7690 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7691 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7692 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7693
7694 /* Indicate to hardware the Address is Valid. */
7695 rar_high |= E1000_RAH_AV;
7696
7697 if (hw->mac.type == e1000_82575)
7698 rar_high |= E1000_RAH_POOL_1 * qsel;
7699 else
7700 rar_high |= E1000_RAH_POOL_1 << qsel;
7701
7702 wr32(E1000_RAL(index), rar_low);
7703 wrfl();
7704 wr32(E1000_RAH(index), rar_high);
7705 wrfl();
7706}
7707
4ae196df 7708static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7709 int vf, unsigned char *mac_addr)
4ae196df
AD		 7710{
7711 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7712 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7713 * towards the first, as a result a collision should not be possible
7714 */
ff41f8dc 7715 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7716
37680117 7717 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7718
26ad9178 7719 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7720
7721 return 0;
7722}
7723
8151d294
WM		 7724static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7725{
7726 struct igb_adapter *adapter = netdev_priv(netdev);
7727 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7728 return -EINVAL;
7729 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7730 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7731 dev_info(&adapter->pdev->dev,
7732 "Reload the VF driver to make this change effective.");
8151d294 7733 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7734 dev_warn(&adapter->pdev->dev,
7735 "The VF MAC address has been set, but the PF device is not up.\n");
7736 dev_warn(&adapter->pdev->dev,
7737 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7738 }
7739 return igb_set_vf_mac(adapter, vf, mac);
7740}
7741
17dc566c
LL		 7742static int igb_link_mbps(int internal_link_speed)
7743{
7744 switch (internal_link_speed) {
7745 case SPEED_100:
7746 return 100;
7747 case SPEED_1000:
7748 return 1000;
7749 default:
7750 return 0;
7751 }
7752}
7753
7754static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7755 int link_speed)
7756{
7757 int rf_dec, rf_int;
7758 u32 bcnrc_val;
7759
7760 if (tx_rate != 0) {
7761 /* Calculate the rate factor values to set */
7762 rf_int = link_speed / tx_rate;
7763 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7764 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7765 tx_rate;
17dc566c
LL		 7766
7767 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7768 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7769 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7770 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7771 } else {
7772 bcnrc_val = 0;
7773 }
7774
7775 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7776 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7777 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7778 */
7779 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7780 wr32(E1000_RTTBCNRC, bcnrc_val);
7781}
7782
7783static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7784{
7785 int actual_link_speed, i;
7786 bool reset_rate = false;
7787
7788 /* VF TX rate limit was not set or not supported */
7789 if ((adapter->vf_rate_link_speed == 0) ||
7790 (adapter->hw.mac.type != e1000_82576))
7791 return;
7792
7793 actual_link_speed = igb_link_mbps(adapter->link_speed);
7794 if (actual_link_speed != adapter->vf_rate_link_speed) {
7795 reset_rate = true;
7796 adapter->vf_rate_link_speed = 0;
7797 dev_info(&adapter->pdev->dev,
b980ac18 7798 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7799 }
7800
7801 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7802 if (reset_rate)
7803 adapter->vf_data[i].tx_rate = 0;
7804
7805 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7806 adapter->vf_data[i].tx_rate,
7807 actual_link_speed);
17dc566c
LL		 7808 }
7809}
7810
ed616689
SC		 7811static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7812 int min_tx_rate, int max_tx_rate)
8151d294 7813{
17dc566c
LL		 7814 struct igb_adapter *adapter = netdev_priv(netdev);
7815 struct e1000_hw *hw = &adapter->hw;
7816 int actual_link_speed;
7817
7818 if (hw->mac.type != e1000_82576)
7819 return -EOPNOTSUPP;
7820
ed616689
SC		 7821 if (min_tx_rate)
7822 return -EINVAL;
7823
17dc566c
LL		 7824 actual_link_speed = igb_link_mbps(adapter->link_speed);
7825 if ((vf >= adapter->vfs_allocated_count) ||
7826 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7827 (max_tx_rate < 0) ||
7828 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7829 return -EINVAL;
7830
7831 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7832 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7833 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7834
7835 return 0;
8151d294
WM		 7836}
7837
70ea4783
LL		 7838static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7839 bool setting)
7840{
7841 struct igb_adapter *adapter = netdev_priv(netdev);
7842 struct e1000_hw *hw = &adapter->hw;
7843 u32 reg_val, reg_offset;
7844
7845 if (!adapter->vfs_allocated_count)
7846 return -EOPNOTSUPP;
7847
7848 if (vf >= adapter->vfs_allocated_count)
7849 return -EINVAL;
7850
7851 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7852 reg_val = rd32(reg_offset);
7853 if (setting)
7854 reg_val |= ((1 << vf) |
7855 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7856 else
7857 reg_val &= ~((1 << vf) |
7858 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7859 wr32(reg_offset, reg_val);
7860
7861 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7862 return 0;
70ea4783
LL		 7863}
7864
8151d294
WM		 7865static int igb_ndo_get_vf_config(struct net_device *netdev,
7866 int vf, struct ifla_vf_info *ivi)
7867{
7868 struct igb_adapter *adapter = netdev_priv(netdev);
7869 if (vf >= adapter->vfs_allocated_count)
7870 return -EINVAL;
7871 ivi->vf = vf;
7872 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7873 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7874 ivi->min_tx_rate = 0;
8151d294
WM		 7875 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7876 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7877 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7878 return 0;
7879}
7880
4ae196df
AD		 7881static void igb_vmm_control(struct igb_adapter *adapter)
7882{
7883 struct e1000_hw *hw = &adapter->hw;
10d8e907 7884 u32 reg;
4ae196df 7885
52a1dd4d
AD		 7886 switch (hw->mac.type) {
7887 case e1000_82575:
f96a8a0b
CW		 7888 case e1000_i210:
7889 case e1000_i211:
ceb5f13b 7890 case e1000_i354:
52a1dd4d
AD		 7891 default:
7892 /* replication is not supported for 82575 */
4ae196df 7893 return;
52a1dd4d
AD		 7894 case e1000_82576:
7895 /* notify HW that the MAC is adding vlan tags */
7896 reg = rd32(E1000_DTXCTL);
7897 reg |= E1000_DTXCTL_VLAN_ADDED;
7898 wr32(E1000_DTXCTL, reg);
b26141d4 7899 /* Fall through */
52a1dd4d
AD		 7900 case e1000_82580:
7901 /* enable replication vlan tag stripping */
7902 reg = rd32(E1000_RPLOLR);
7903 reg |= E1000_RPLOLR_STRVLAN;
7904 wr32(E1000_RPLOLR, reg);
b26141d4 7905 /* Fall through */
d2ba2ed8
AD		 7906 case e1000_i350:
7907 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7908 break;
7909 }
10d8e907 7910
d4960307
AD		 7911 if (adapter->vfs_allocated_count) {
7912 igb_vmdq_set_loopback_pf(hw, true);
7913 igb_vmdq_set_replication_pf(hw, true);
13800469 7914 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7915 adapter->vfs_allocated_count);
d4960307
AD		 7916 } else {
7917 igb_vmdq_set_loopback_pf(hw, false);
7918 igb_vmdq_set_replication_pf(hw, false);
7919 }
4ae196df
AD		 7920}
7921
b6e0c419
CW		 7922static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7923{
7924 struct e1000_hw *hw = &adapter->hw;
7925 u32 dmac_thr;
7926 u16 hwm;
7927
7928 if (hw->mac.type > e1000_82580) {
7929 if (adapter->flags & IGB_FLAG_DMAC) {
7930 u32 reg;
7931
7932 /* force threshold to 0. */
7933 wr32(E1000_DMCTXTH, 0);
7934
b980ac18 7935 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7936 * than the Rx threshold. Set hwm to PBA - max frame
7937 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7938 */
e8c626e9
MV		 7939 hwm = 64 * pba - adapter->max_frame_size / 16;
7940 if (hwm < 64 * (pba - 6))
7941 hwm = 64 * (pba - 6);
7942 reg = rd32(E1000_FCRTC);
7943 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7944 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7945 & E1000_FCRTC_RTH_COAL_MASK);
7946 wr32(E1000_FCRTC, reg);
7947
b980ac18 7948 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7949 * frame size, capping it at PBA - 10KB.
7950 */
7951 dmac_thr = pba - adapter->max_frame_size / 512;
7952 if (dmac_thr < pba - 10)
7953 dmac_thr = pba - 10;
b6e0c419
CW		 7954 reg = rd32(E1000_DMACR);
7955 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7956 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7957 & E1000_DMACR_DMACTHR_MASK);
7958
7959 /* transition to L0x or L1 if available..*/
7960 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7961
7962 /* watchdog timer= +-1000 usec in 32usec intervals */
7963 reg |= (1000 >> 5);
0c02dd98
MV		 7964
7965 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7966 if (hw->mac.type != e1000_i354)
7967 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7968
b6e0c419
CW		 7969 wr32(E1000_DMACR, reg);
7970
b980ac18 7971 /* no lower threshold to disable
b6e0c419
CW		 7972 * coalescing(smart fifb)-UTRESH=0
7973 */
7974 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7975
7976 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7977
7978 wr32(E1000_DMCTLX, reg);
7979
b980ac18 7980 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7981 * DMA coal
7982 */
7983 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7984 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7985
b980ac18 7986 /* make low power state decision controlled
b6e0c419
CW		 7987 * by DMA coal
7988 */
7989 reg = rd32(E1000_PCIEMISC);
7990 reg &= ~E1000_PCIEMISC_LX_DECISION;
7991 wr32(E1000_PCIEMISC, reg);
7992 } /* endif adapter->dmac is not disabled */
7993 } else if (hw->mac.type == e1000_82580) {
7994 u32 reg = rd32(E1000_PCIEMISC);
9005df38 7995
b6e0c419
CW		 7996 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7997 wr32(E1000_DMACR, 0);
7998 }
7999}
8000
b980ac18
JK		 8001/**
8002 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8003 * @hw: pointer to hardware structure
8004 * @byte_offset: byte offset to read
8005 * @dev_addr: device address
8006 * @data: value read
8007 *
8008 * Performs byte read operation over I2C interface at
8009 * a specified device address.
b980ac18 8010 **/
441fc6fd 8011s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8012 u8 dev_addr, u8 *data)
441fc6fd
CW		 8013{
8014 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8015 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8016 s32 status;
8017 u16 swfw_mask = 0;
8018
8019 if (!this_client)
8020 return E1000_ERR_I2C;
8021
8022 swfw_mask = E1000_SWFW_PHY0_SM;
8023
23d87824 8024 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8025 return E1000_ERR_SWFW_SYNC;
8026
8027 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8028 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8029
8030 if (status < 0)
8031 return E1000_ERR_I2C;
8032 else {
8033 *data = status;
23d87824 8034 return 0;
441fc6fd
CW		 8035 }
8036}
8037
b980ac18
JK		 8038/**
8039 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8040 * @hw: pointer to hardware structure
8041 * @byte_offset: byte offset to write
8042 * @dev_addr: device address
8043 * @data: value to write
8044 *
8045 * Performs byte write operation over I2C interface at
8046 * a specified device address.
b980ac18 8047 **/
441fc6fd 8048s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8049 u8 dev_addr, u8 data)
441fc6fd
CW		 8050{
8051 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8052 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8053 s32 status;
8054 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8055
8056 if (!this_client)
8057 return E1000_ERR_I2C;
8058
23d87824 8059 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8060 return E1000_ERR_SWFW_SYNC;
8061 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8062 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8063
8064 if (status)
8065 return E1000_ERR_I2C;
8066 else
23d87824 8067 return 0;
441fc6fd
CW		 8068
8069}
907b7835
LMV		 8070
8071int igb_reinit_queues(struct igb_adapter *adapter)
8072{
8073 struct net_device *netdev = adapter->netdev;
8074 struct pci_dev *pdev = adapter->pdev;
8075 int err = 0;
8076
8077 if (netif_running(netdev))
8078 igb_close(netdev);
8079
02ef6e1d 8080 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8081
8082 if (igb_init_interrupt_scheme(adapter, true)) {
8083 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8084 return -ENOMEM;
8085 }
8086
8087 if (netif_running(netdev))
8088 err = igb_open(netdev);
8089
8090 return err;
8091}
9d5c8243 8092/* igb_main.c */
Linux kernel - Deliverables
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