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igb: Cleanups to remove return parentheses
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903
CW		 59#define MAJ 5
60#define MIN 0
66f40b8a 61#define BUILD 5
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
a3aa1884 75static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
117void igb_reset(struct igb_adapter *);
118static int igb_setup_all_tx_resources(struct igb_adapter *);
119static int igb_setup_all_rx_resources(struct igb_adapter *);
120static void igb_free_all_tx_resources(struct igb_adapter *);
121static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 122static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 123static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 124static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 125static int igb_sw_init(struct igb_adapter *);
126static int igb_open(struct net_device *);
127static int igb_close(struct net_device *);
53c7d064 128static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 129static void igb_configure_tx(struct igb_adapter *);
130static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 131static void igb_clean_all_tx_rings(struct igb_adapter *);
132static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 133static void igb_clean_tx_ring(struct igb_ring *);
134static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 135static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 136static void igb_update_phy_info(unsigned long);
137static void igb_watchdog(unsigned long);
138static void igb_watchdog_task(struct work_struct *);
cd392f5c 139static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b
ED		 140static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
141 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 142static int igb_change_mtu(struct net_device *, int);
143static int igb_set_mac(struct net_device *, void *);
68d480c4 144static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 145static irqreturn_t igb_intr(int irq, void *);
146static irqreturn_t igb_intr_msi(int irq, void *);
147static irqreturn_t igb_msix_other(int irq, void *);
047e0030 148static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 149#ifdef CONFIG_IGB_DCA
047e0030 150static void igb_update_dca(struct igb_q_vector *);
fe4506b6 151static void igb_setup_dca(struct igb_adapter *);
421e02f0 152#endif /* CONFIG_IGB_DCA */
661086df 153static int igb_poll(struct napi_struct *, int);
13fde97a 154static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 155static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 156static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
157static void igb_tx_timeout(struct net_device *);
158static void igb_reset_task(struct work_struct *);
c8f44aff 159static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
172static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 182#endif
9d5c8243 183
9d5c8243 184#ifdef CONFIG_PM
d9dd966d 185#ifdef CONFIG_PM_SLEEP
749ab2cd 186static int igb_suspend(struct device *);
d9dd966d 187#endif
749ab2cd
YZ		 188static int igb_resume(struct device *);
189#ifdef CONFIG_PM_RUNTIME
190static int igb_runtime_suspend(struct device *dev);
191static int igb_runtime_resume(struct device *dev);
192static int igb_runtime_idle(struct device *dev);
193#endif
194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
2a3abf6d
AD		 215static unsigned int max_vfs = 0;
216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
047e0030 949 struct e1000_hw *hw = &adapter->hw;
52285b76 950 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 951
047e0030 952 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 953 igb_msix_other, 0, netdev->name, adapter);
047e0030 954 if (err)
52285b76 955 goto err_out;
047e0030
AD		 956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
52285b76
SA		 960 vector++;
961
047e0030
AD		 962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
963
0ba82994 964 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
047e0030 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
047e0030 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 972 q_vector->rx.ring->queue_index);
9d5c8243 973 else
047e0030
AD		 974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
9d5c8243 976 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
9d5c8243 979 if (err)
52285b76 980 goto err_free;
9d5c8243
AK		 981 }
982
9d5c8243
AK		 983 igb_configure_msix(adapter);
984 return 0;
52285b76
SA		 985
986err_free:
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995err_out:
9d5c8243
AK		 996 return err;
997}
998
5536d210 999/**
b980ac18
JK		 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
5536d210 1003 *
02ef6e1d 1004 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
02ef6e1d
CW		 1010 adapter->q_vector[v_idx] = NULL;
1011
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
1015 kfree_rcu(q_vector, rcu);
1016}
1017
1018/**
1019 * igb_reset_q_vector - Reset config for interrupt vector
1020 * @adapter: board private structure to initialize
1021 * @v_idx: Index of vector to be reset
1022 *
1023 * If NAPI is enabled it will delete any references to the
1024 * NAPI struct. This is preparation for igb_free_q_vector.
1025 **/
1026static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1027{
1028 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1029
cb06d102
CP		 1030 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1031 * allocated. So, q_vector is NULL so we should stop here.
1032 */
1033 if (!q_vector)
1034 return;
1035
5536d210
AD		 1036 if (q_vector->tx.ring)
1037 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1038
1039 if (q_vector->rx.ring)
1040 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1041
5536d210
AD		 1042 netif_napi_del(&q_vector->napi);
1043
02ef6e1d
CW		 1044}
1045
1046static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1047{
1048 int v_idx = adapter->num_q_vectors;
1049
cd14ef54 1050 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1051 pci_disable_msix(adapter->pdev);
cd14ef54 1052 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1053 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1054
1055 while (v_idx--)
1056 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1057}
1058
047e0030 1059/**
b980ac18
JK		 1060 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1061 * @adapter: board private structure to initialize
047e0030 1062 *
b980ac18
JK		 1063 * This function frees the memory allocated to the q_vectors. In addition if
1064 * NAPI is enabled it will delete any references to the NAPI struct prior
1065 * to freeing the q_vector.
047e0030
AD		 1066 **/
1067static void igb_free_q_vectors(struct igb_adapter *adapter)
1068{
5536d210
AD		 1069 int v_idx = adapter->num_q_vectors;
1070
1071 adapter->num_tx_queues = 0;
1072 adapter->num_rx_queues = 0;
047e0030 1073 adapter->num_q_vectors = 0;
5536d210 1074
02ef6e1d
CW		 1075 while (v_idx--) {
1076 igb_reset_q_vector(adapter, v_idx);
5536d210 1077 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1078 }
047e0030
AD		 1079}
1080
1081/**
b980ac18
JK		 1082 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1083 * @adapter: board private structure to initialize
047e0030 1084 *
b980ac18
JK		 1085 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1086 * MSI-X interrupts allocated.
047e0030
AD		 1087 */
1088static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1089{
047e0030
AD		 1090 igb_free_q_vectors(adapter);
1091 igb_reset_interrupt_capability(adapter);
1092}
9d5c8243
AK		 1093
1094/**
b980ac18
JK		 1095 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1096 * @adapter: board private structure to initialize
1097 * @msix: boolean value of MSIX capability
9d5c8243 1098 *
b980ac18
JK		 1099 * Attempt to configure interrupts using the best available
1100 * capabilities of the hardware and kernel.
9d5c8243 1101 **/
53c7d064 1102static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1103{
1104 int err;
1105 int numvecs, i;
1106
53c7d064
SA		 1107 if (!msix)
1108 goto msi_only;
cd14ef54 1109 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1110
83b7180d 1111 /* Number of supported queues. */
a99955fc 1112 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1113 if (adapter->vfs_allocated_count)
1114 adapter->num_tx_queues = 1;
1115 else
1116 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1117
b980ac18 1118 /* start with one vector for every Rx queue */
047e0030
AD		 1119 numvecs = adapter->num_rx_queues;
1120
b980ac18 1121 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1122 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1123 numvecs += adapter->num_tx_queues;
047e0030
AD		 1124
1125 /* store the number of vectors reserved for queues */
1126 adapter->num_q_vectors = numvecs;
1127
1128 /* add 1 vector for link status interrupts */
1129 numvecs++;
9d5c8243
AK		 1130 for (i = 0; i < numvecs; i++)
1131 adapter->msix_entries[i].entry = i;
1132
479d02df
AG		 1133 err = pci_enable_msix_range(adapter->pdev,
1134 adapter->msix_entries,
1135 numvecs,
1136 numvecs);
1137 if (err > 0)
0c2cc02e 1138 return;
9d5c8243
AK		 1139
1140 igb_reset_interrupt_capability(adapter);
1141
1142 /* If we can't do MSI-X, try MSI */
1143msi_only:
b709323d 1144 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1145#ifdef CONFIG_PCI_IOV
1146 /* disable SR-IOV for non MSI-X configurations */
1147 if (adapter->vf_data) {
1148 struct e1000_hw *hw = &adapter->hw;
1149 /* disable iov and allow time for transactions to clear */
1150 pci_disable_sriov(adapter->pdev);
1151 msleep(500);
1152
1153 kfree(adapter->vf_data);
1154 adapter->vf_data = NULL;
1155 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1156 wrfl();
2a3abf6d
AD		 1157 msleep(100);
1158 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1159 }
1160#endif
4fc82adf 1161 adapter->vfs_allocated_count = 0;
a99955fc 1162 adapter->rss_queues = 1;
4fc82adf 1163 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1164 adapter->num_rx_queues = 1;
661086df 1165 adapter->num_tx_queues = 1;
047e0030 1166 adapter->num_q_vectors = 1;
9d5c8243 1167 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1168 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1169}
1170
5536d210
AD		 1171static void igb_add_ring(struct igb_ring *ring,
1172 struct igb_ring_container *head)
1173{
1174 head->ring = ring;
1175 head->count++;
1176}
1177
047e0030 1178/**
b980ac18
JK		 1179 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1180 * @adapter: board private structure to initialize
1181 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1182 * @v_idx: index of vector in adapter struct
1183 * @txr_count: total number of Tx rings to allocate
1184 * @txr_idx: index of first Tx ring to allocate
1185 * @rxr_count: total number of Rx rings to allocate
1186 * @rxr_idx: index of first Rx ring to allocate
047e0030 1187 *
b980ac18 1188 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1189 **/
5536d210
AD		 1190static int igb_alloc_q_vector(struct igb_adapter *adapter,
1191 int v_count, int v_idx,
1192 int txr_count, int txr_idx,
1193 int rxr_count, int rxr_idx)
047e0030
AD		 1194{
1195 struct igb_q_vector *q_vector;
5536d210
AD		 1196 struct igb_ring *ring;
1197 int ring_count, size;
047e0030 1198
5536d210
AD		 1199 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1200 if (txr_count > 1 || rxr_count > 1)
1201 return -ENOMEM;
1202
1203 ring_count = txr_count + rxr_count;
1204 size = sizeof(struct igb_q_vector) +
1205 (sizeof(struct igb_ring) * ring_count);
1206
1207 /* allocate q_vector and rings */
02ef6e1d
CW		 1208 q_vector = adapter->q_vector[v_idx];
1209 if (!q_vector)
1210 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1211 if (!q_vector)
1212 return -ENOMEM;
1213
1214 /* initialize NAPI */
1215 netif_napi_add(adapter->netdev, &q_vector->napi,
1216 igb_poll, 64);
1217
1218 /* tie q_vector and adapter together */
1219 adapter->q_vector[v_idx] = q_vector;
1220 q_vector->adapter = adapter;
1221
1222 /* initialize work limits */
1223 q_vector->tx.work_limit = adapter->tx_work_limit;
1224
1225 /* initialize ITR configuration */
1226 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1227 q_vector->itr_val = IGB_START_ITR;
1228
1229 /* initialize pointer to rings */
1230 ring = q_vector->ring;
1231
4e227667
AD		 1232 /* intialize ITR */
1233 if (rxr_count) {
1234 /* rx or rx/tx vector */
1235 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1236 q_vector->itr_val = adapter->rx_itr_setting;
1237 } else {
1238 /* tx only vector */
1239 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1240 q_vector->itr_val = adapter->tx_itr_setting;
1241 }
1242
5536d210
AD		 1243 if (txr_count) {
1244 /* assign generic ring traits */
1245 ring->dev = &adapter->pdev->dev;
1246 ring->netdev = adapter->netdev;
1247
1248 /* configure backlink on ring */
1249 ring->q_vector = q_vector;
1250
1251 /* update q_vector Tx values */
1252 igb_add_ring(ring, &q_vector->tx);
1253
1254 /* For 82575, context index must be unique per ring. */
1255 if (adapter->hw.mac.type == e1000_82575)
1256 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1257
1258 /* apply Tx specific ring traits */
1259 ring->count = adapter->tx_ring_count;
1260 ring->queue_index = txr_idx;
1261
827da44c
JS		 1262 u64_stats_init(&ring->tx_syncp);
1263 u64_stats_init(&ring->tx_syncp2);
1264
5536d210
AD		 1265 /* assign ring to adapter */
1266 adapter->tx_ring[txr_idx] = ring;
1267
1268 /* push pointer to next ring */
1269 ring++;
047e0030 1270 }
81c2fc22 1271
5536d210
AD		 1272 if (rxr_count) {
1273 /* assign generic ring traits */
1274 ring->dev = &adapter->pdev->dev;
1275 ring->netdev = adapter->netdev;
047e0030 1276
5536d210
AD		 1277 /* configure backlink on ring */
1278 ring->q_vector = q_vector;
047e0030 1279
5536d210
AD		 1280 /* update q_vector Rx values */
1281 igb_add_ring(ring, &q_vector->rx);
047e0030 1282
5536d210
AD		 1283 /* set flag indicating ring supports SCTP checksum offload */
1284 if (adapter->hw.mac.type >= e1000_82576)
1285 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1286
e52c0f96 1287 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1288 * have the tag byte-swapped.
b980ac18 1289 */
5536d210
AD		 1290 if (adapter->hw.mac.type >= e1000_i350)
1291 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1292
5536d210
AD		 1293 /* apply Rx specific ring traits */
1294 ring->count = adapter->rx_ring_count;
1295 ring->queue_index = rxr_idx;
1296
827da44c
JS		 1297 u64_stats_init(&ring->rx_syncp);
1298
5536d210
AD		 1299 /* assign ring to adapter */
1300 adapter->rx_ring[rxr_idx] = ring;
1301 }
1302
1303 return 0;
047e0030
AD		 1304}
1305
5536d210 1306
047e0030 1307/**
b980ac18
JK		 1308 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1309 * @adapter: board private structure to initialize
047e0030 1310 *
b980ac18
JK		 1311 * We allocate one q_vector per queue interrupt. If allocation fails we
1312 * return -ENOMEM.
047e0030 1313 **/
5536d210 1314static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1315{
5536d210
AD		 1316 int q_vectors = adapter->num_q_vectors;
1317 int rxr_remaining = adapter->num_rx_queues;
1318 int txr_remaining = adapter->num_tx_queues;
1319 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1320 int err;
047e0030 1321
5536d210
AD		 1322 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1323 for (; rxr_remaining; v_idx++) {
1324 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1325 0, 0, 1, rxr_idx);
047e0030 1326
5536d210
AD		 1327 if (err)
1328 goto err_out;
1329
1330 /* update counts and index */
1331 rxr_remaining--;
1332 rxr_idx++;
047e0030 1333 }
047e0030 1334 }
5536d210
AD		 1335
1336 for (; v_idx < q_vectors; v_idx++) {
1337 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1338 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1339
5536d210
AD		 1340 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1341 tqpv, txr_idx, rqpv, rxr_idx);
1342
1343 if (err)
1344 goto err_out;
1345
1346 /* update counts and index */
1347 rxr_remaining -= rqpv;
1348 txr_remaining -= tqpv;
1349 rxr_idx++;
1350 txr_idx++;
1351 }
1352
047e0030 1353 return 0;
5536d210
AD		 1354
1355err_out:
1356 adapter->num_tx_queues = 0;
1357 adapter->num_rx_queues = 0;
1358 adapter->num_q_vectors = 0;
1359
1360 while (v_idx--)
1361 igb_free_q_vector(adapter, v_idx);
1362
1363 return -ENOMEM;
047e0030
AD		 1364}
1365
1366/**
b980ac18
JK		 1367 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1368 * @adapter: board private structure to initialize
1369 * @msix: boolean value of MSIX capability
047e0030 1370 *
b980ac18 1371 * This function initializes the interrupts and allocates all of the queues.
047e0030 1372 **/
53c7d064 1373static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1374{
1375 struct pci_dev *pdev = adapter->pdev;
1376 int err;
1377
53c7d064 1378 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1379
1380 err = igb_alloc_q_vectors(adapter);
1381 if (err) {
1382 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1383 goto err_alloc_q_vectors;
1384 }
1385
5536d210 1386 igb_cache_ring_register(adapter);
047e0030
AD		 1387
1388 return 0;
5536d210 1389
047e0030
AD		 1390err_alloc_q_vectors:
1391 igb_reset_interrupt_capability(adapter);
1392 return err;
1393}
1394
9d5c8243 1395/**
b980ac18
JK		 1396 * igb_request_irq - initialize interrupts
1397 * @adapter: board private structure to initialize
9d5c8243 1398 *
b980ac18
JK		 1399 * Attempts to configure interrupts using the best available
1400 * capabilities of the hardware and kernel.
9d5c8243
AK		 1401 **/
1402static int igb_request_irq(struct igb_adapter *adapter)
1403{
1404 struct net_device *netdev = adapter->netdev;
047e0030 1405 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1406 int err = 0;
1407
cd14ef54 1408 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1409 err = igb_request_msix(adapter);
844290e5 1410 if (!err)
9d5c8243 1411 goto request_done;
9d5c8243 1412 /* fall back to MSI */
5536d210
AD		 1413 igb_free_all_tx_resources(adapter);
1414 igb_free_all_rx_resources(adapter);
53c7d064 1415
047e0030 1416 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1417 err = igb_init_interrupt_scheme(adapter, false);
1418 if (err)
047e0030 1419 goto request_done;
53c7d064 1420
047e0030
AD		 1421 igb_setup_all_tx_resources(adapter);
1422 igb_setup_all_rx_resources(adapter);
53c7d064 1423 igb_configure(adapter);
9d5c8243 1424 }
844290e5 1425
c74d588e
AD		 1426 igb_assign_vector(adapter->q_vector[0], 0);
1427
7dfc16fa 1428 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1429 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1430 netdev->name, adapter);
9d5c8243
AK		 1431 if (!err)
1432 goto request_done;
047e0030 1433
9d5c8243
AK		 1434 /* fall back to legacy interrupts */
1435 igb_reset_interrupt_capability(adapter);
7dfc16fa 1436 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1437 }
1438
c74d588e 1439 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1440 netdev->name, adapter);
9d5c8243 1441
6cb5e577 1442 if (err)
c74d588e 1443 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1444 err);
9d5c8243
AK		 1445
1446request_done:
1447 return err;
1448}
1449
1450static void igb_free_irq(struct igb_adapter *adapter)
1451{
cd14ef54 1452 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1453 int vector = 0, i;
1454
047e0030 1455 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1456
0d1ae7f4 1457 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1458 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1459 adapter->q_vector[i]);
047e0030
AD		 1460 } else {
1461 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1462 }
9d5c8243
AK		 1463}
1464
1465/**
b980ac18
JK		 1466 * igb_irq_disable - Mask off interrupt generation on the NIC
1467 * @adapter: board private structure
9d5c8243
AK		 1468 **/
1469static void igb_irq_disable(struct igb_adapter *adapter)
1470{
1471 struct e1000_hw *hw = &adapter->hw;
1472
b980ac18 1473 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1474 * mapped into these registers and so clearing the bits can cause
1475 * issues on the VF drivers so we only need to clear what we set
1476 */
cd14ef54 1477 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1478 u32 regval = rd32(E1000_EIAM);
9005df38 1479
2dfd1212
AD		 1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1481 wr32(E1000_EIMC, adapter->eims_enable_mask);
1482 regval = rd32(E1000_EIAC);
1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1484 }
844290e5
PW		 1485
1486 wr32(E1000_IAM, 0);
9d5c8243
AK		 1487 wr32(E1000_IMC, ~0);
1488 wrfl();
cd14ef54 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1490 int i;
9005df38 1491
81a61859
ET		 1492 for (i = 0; i < adapter->num_q_vectors; i++)
1493 synchronize_irq(adapter->msix_entries[i].vector);
1494 } else {
1495 synchronize_irq(adapter->pdev->irq);
1496 }
9d5c8243
AK		 1497}
1498
1499/**
b980ac18
JK		 1500 * igb_irq_enable - Enable default interrupt generation settings
1501 * @adapter: board private structure
9d5c8243
AK		 1502 **/
1503static void igb_irq_enable(struct igb_adapter *adapter)
1504{
1505 struct e1000_hw *hw = &adapter->hw;
1506
cd14ef54 1507 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1508 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1509 u32 regval = rd32(E1000_EIAC);
9005df38 1510
2dfd1212
AD		 1511 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1512 regval = rd32(E1000_EIAM);
1513 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1514 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1515 if (adapter->vfs_allocated_count) {
4ae196df 1516 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1517 ims |= E1000_IMS_VMMB;
1518 }
1519 wr32(E1000_IMS, ims);
844290e5 1520 } else {
55cac248
AD		 1521 wr32(E1000_IMS, IMS_ENABLE_MASK |
1522 E1000_IMS_DRSTA);
1523 wr32(E1000_IAM, IMS_ENABLE_MASK |
1524 E1000_IMS_DRSTA);
844290e5 1525 }
9d5c8243
AK		 1526}
1527
1528static void igb_update_mng_vlan(struct igb_adapter *adapter)
1529{
51466239 1530 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1531 u16 vid = adapter->hw.mng_cookie.vlan_id;
1532 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1533
1534 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1535 /* add VID to filter table */
1536 igb_vfta_set(hw, vid, true);
1537 adapter->mng_vlan_id = vid;
1538 } else {
1539 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1540 }
1541
1542 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1543 (vid != old_vid) &&
b2cb09b1 1544 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1545 /* remove VID from filter table */
1546 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1547 }
1548}
1549
1550/**
b980ac18
JK		 1551 * igb_release_hw_control - release control of the h/w to f/w
1552 * @adapter: address of board private structure
9d5c8243 1553 *
b980ac18
JK		 1554 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1555 * For ASF and Pass Through versions of f/w this means that the
1556 * driver is no longer loaded.
9d5c8243
AK		 1557 **/
1558static void igb_release_hw_control(struct igb_adapter *adapter)
1559{
1560 struct e1000_hw *hw = &adapter->hw;
1561 u32 ctrl_ext;
1562
1563 /* Let firmware take over control of h/w */
1564 ctrl_ext = rd32(E1000_CTRL_EXT);
1565 wr32(E1000_CTRL_EXT,
1566 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1567}
1568
9d5c8243 1569/**
b980ac18
JK		 1570 * igb_get_hw_control - get control of the h/w from f/w
1571 * @adapter: address of board private structure
9d5c8243 1572 *
b980ac18
JK		 1573 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1574 * For ASF and Pass Through versions of f/w this means that
1575 * the driver is loaded.
9d5c8243
AK		 1576 **/
1577static void igb_get_hw_control(struct igb_adapter *adapter)
1578{
1579 struct e1000_hw *hw = &adapter->hw;
1580 u32 ctrl_ext;
1581
1582 /* Let firmware know the driver has taken over */
1583 ctrl_ext = rd32(E1000_CTRL_EXT);
1584 wr32(E1000_CTRL_EXT,
1585 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1586}
1587
9d5c8243 1588/**
b980ac18
JK		 1589 * igb_configure - configure the hardware for RX and TX
1590 * @adapter: private board structure
9d5c8243
AK		 1591 **/
1592static void igb_configure(struct igb_adapter *adapter)
1593{
1594 struct net_device *netdev = adapter->netdev;
1595 int i;
1596
1597 igb_get_hw_control(adapter);
ff41f8dc 1598 igb_set_rx_mode(netdev);
9d5c8243
AK		 1599
1600 igb_restore_vlan(adapter);
9d5c8243 1601
85b430b4 1602 igb_setup_tctl(adapter);
06cf2666 1603 igb_setup_mrqc(adapter);
9d5c8243 1604 igb_setup_rctl(adapter);
85b430b4
AD		 1605
1606 igb_configure_tx(adapter);
9d5c8243 1607 igb_configure_rx(adapter);
662d7205
AD		 1608
1609 igb_rx_fifo_flush_82575(&adapter->hw);
1610
c493ea45 1611 /* call igb_desc_unused which always leaves
9d5c8243 1612 * at least 1 descriptor unused to make sure
b980ac18
JK		 1613 * next_to_use != next_to_clean
1614 */
9d5c8243 1615 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1616 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1617 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1618 }
9d5c8243
AK		 1619}
1620
88a268c1 1621/**
b980ac18
JK		 1622 * igb_power_up_link - Power up the phy/serdes link
1623 * @adapter: address of board private structure
88a268c1
NN		 1624 **/
1625void igb_power_up_link(struct igb_adapter *adapter)
1626{
76886596
AA		 1627 igb_reset_phy(&adapter->hw);
1628
88a268c1
NN		 1629 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1630 igb_power_up_phy_copper(&adapter->hw);
1631 else
1632 igb_power_up_serdes_link_82575(&adapter->hw);
1633}
1634
1635/**
b980ac18
JK		 1636 * igb_power_down_link - Power down the phy/serdes link
1637 * @adapter: address of board private structure
88a268c1
NN		 1638 */
1639static void igb_power_down_link(struct igb_adapter *adapter)
1640{
1641 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1642 igb_power_down_phy_copper_82575(&adapter->hw);
1643 else
1644 igb_shutdown_serdes_link_82575(&adapter->hw);
1645}
9d5c8243 1646
56cec249
CW		 1647/**
1648 * Detect and switch function for Media Auto Sense
1649 * @adapter: address of the board private structure
1650 **/
1651static void igb_check_swap_media(struct igb_adapter *adapter)
1652{
1653 struct e1000_hw *hw = &adapter->hw;
1654 u32 ctrl_ext, connsw;
1655 bool swap_now = false;
1656
1657 ctrl_ext = rd32(E1000_CTRL_EXT);
1658 connsw = rd32(E1000_CONNSW);
1659
1660 /* need to live swap if current media is copper and we have fiber/serdes
1661 * to go to.
1662 */
1663
1664 if ((hw->phy.media_type == e1000_media_type_copper) &&
1665 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1666 swap_now = true;
1667 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1668 /* copper signal takes time to appear */
1669 if (adapter->copper_tries < 4) {
1670 adapter->copper_tries++;
1671 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1672 wr32(E1000_CONNSW, connsw);
1673 return;
1674 } else {
1675 adapter->copper_tries = 0;
1676 if ((connsw & E1000_CONNSW_PHYSD) &&
1677 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1678 swap_now = true;
1679 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1680 wr32(E1000_CONNSW, connsw);
1681 }
1682 }
1683 }
1684
1685 if (!swap_now)
1686 return;
1687
1688 switch (hw->phy.media_type) {
1689 case e1000_media_type_copper:
1690 netdev_info(adapter->netdev,
1691 "MAS: changing media to fiber/serdes\n");
1692 ctrl_ext |=
1693 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1694 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1695 adapter->copper_tries = 0;
1696 break;
1697 case e1000_media_type_internal_serdes:
1698 case e1000_media_type_fiber:
1699 netdev_info(adapter->netdev,
1700 "MAS: changing media to copper\n");
1701 ctrl_ext &=
1702 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1703 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1704 break;
1705 default:
1706 /* shouldn't get here during regular operation */
1707 netdev_err(adapter->netdev,
1708 "AMS: Invalid media type found, returning\n");
1709 break;
1710 }
1711 wr32(E1000_CTRL_EXT, ctrl_ext);
1712}
1713
9d5c8243 1714/**
b980ac18
JK		 1715 * igb_up - Open the interface and prepare it to handle traffic
1716 * @adapter: board private structure
9d5c8243 1717 **/
9d5c8243
AK		 1718int igb_up(struct igb_adapter *adapter)
1719{
1720 struct e1000_hw *hw = &adapter->hw;
1721 int i;
1722
1723 /* hardware has been reset, we need to reload some things */
1724 igb_configure(adapter);
1725
1726 clear_bit(__IGB_DOWN, &adapter->state);
1727
0d1ae7f4
AD		 1728 for (i = 0; i < adapter->num_q_vectors; i++)
1729 napi_enable(&(adapter->q_vector[i]->napi));
1730
cd14ef54 1731 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1732 igb_configure_msix(adapter);
feeb2721
AD		 1733 else
1734 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1735
1736 /* Clear any pending interrupts. */
1737 rd32(E1000_ICR);
1738 igb_irq_enable(adapter);
1739
d4960307
AD		 1740 /* notify VFs that reset has been completed */
1741 if (adapter->vfs_allocated_count) {
1742 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1743
d4960307
AD		 1744 reg_data |= E1000_CTRL_EXT_PFRSTD;
1745 wr32(E1000_CTRL_EXT, reg_data);
1746 }
1747
4cb9be7a
JB		 1748 netif_tx_start_all_queues(adapter->netdev);
1749
25568a53
AD		 1750 /* start the watchdog. */
1751 hw->mac.get_link_status = 1;
1752 schedule_work(&adapter->watchdog_task);
1753
f4c01e96
CW		 1754 if ((adapter->flags & IGB_FLAG_EEE) &&
1755 (!hw->dev_spec._82575.eee_disable))
1756 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1757
9d5c8243
AK		 1758 return 0;
1759}
1760
1761void igb_down(struct igb_adapter *adapter)
1762{
9d5c8243 1763 struct net_device *netdev = adapter->netdev;
330a6d6a 1764 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1765 u32 tctl, rctl;
1766 int i;
1767
1768 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1769 * reschedule our watchdog timer
1770 */
9d5c8243
AK		 1771 set_bit(__IGB_DOWN, &adapter->state);
1772
1773 /* disable receives in the hardware */
1774 rctl = rd32(E1000_RCTL);
1775 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1776 /* flush and sleep below */
1777
fd2ea0a7 1778 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1779
1780 /* disable transmits in the hardware */
1781 tctl = rd32(E1000_TCTL);
1782 tctl &= ~E1000_TCTL_EN;
1783 wr32(E1000_TCTL, tctl);
1784 /* flush both disables and wait for them to finish */
1785 wrfl();
1786 msleep(10);
1787
41f149a2
CW		 1788 igb_irq_disable(adapter);
1789
aa9b8cc4
AA		 1790 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1791
41f149a2
CW		 1792 for (i = 0; i < adapter->num_q_vectors; i++) {
1793 napi_synchronize(&(adapter->q_vector[i]->napi));
0d1ae7f4 1794 napi_disable(&(adapter->q_vector[i]->napi));
41f149a2 1795 }
9d5c8243 1796
9d5c8243
AK		 1797
1798 del_timer_sync(&adapter->watchdog_timer);
1799 del_timer_sync(&adapter->phy_info_timer);
1800
9d5c8243 1801 netif_carrier_off(netdev);
04fe6358
AD		 1802
1803 /* record the stats before reset*/
12dcd86b
ED		 1804 spin_lock(&adapter->stats64_lock);
1805 igb_update_stats(adapter, &adapter->stats64);
1806 spin_unlock(&adapter->stats64_lock);
04fe6358 1807
9d5c8243
AK		 1808 adapter->link_speed = 0;
1809 adapter->link_duplex = 0;
1810
3023682e
JK		 1811 if (!pci_channel_offline(adapter->pdev))
1812 igb_reset(adapter);
9d5c8243
AK		 1813 igb_clean_all_tx_rings(adapter);
1814 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1815#ifdef CONFIG_IGB_DCA
1816
1817 /* since we reset the hardware DCA settings were cleared */
1818 igb_setup_dca(adapter);
1819#endif
9d5c8243
AK		 1820}
1821
1822void igb_reinit_locked(struct igb_adapter *adapter)
1823{
1824 WARN_ON(in_interrupt());
1825 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1826 msleep(1);
1827 igb_down(adapter);
1828 igb_up(adapter);
1829 clear_bit(__IGB_RESETTING, &adapter->state);
1830}
1831
56cec249
CW		 1832/** igb_enable_mas - Media Autosense re-enable after swap
1833 *
1834 * @adapter: adapter struct
1835 **/
1836static s32 igb_enable_mas(struct igb_adapter *adapter)
1837{
1838 struct e1000_hw *hw = &adapter->hw;
1839 u32 connsw;
1840 s32 ret_val = 0;
1841
1842 connsw = rd32(E1000_CONNSW);
1843 if (!(hw->phy.media_type == e1000_media_type_copper))
1844 return ret_val;
1845
1846 /* configure for SerDes media detect */
1847 if (!(connsw & E1000_CONNSW_SERDESD)) {
1848 connsw |= E1000_CONNSW_ENRGSRC;
1849 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1850 wr32(E1000_CONNSW, connsw);
1851 wrfl();
1852 } else if (connsw & E1000_CONNSW_SERDESD) {
1853 /* already SerDes, no need to enable anything */
1854 return ret_val;
1855 } else {
1856 netdev_info(adapter->netdev,
1857 "MAS: Unable to configure feature, disabling..\n");
1858 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1859 }
1860 return ret_val;
1861}
1862
9d5c8243
AK		 1863void igb_reset(struct igb_adapter *adapter)
1864{
090b1795 1865 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1866 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1867 struct e1000_mac_info *mac = &hw->mac;
1868 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1869 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1870
1871 /* Repartition Pba for greater than 9k mtu
1872 * To take effect CTRL.RST is required.
1873 */
fa4dfae0 1874 switch (mac->type) {
d2ba2ed8 1875 case e1000_i350:
ceb5f13b 1876 case e1000_i354:
55cac248
AD		 1877 case e1000_82580:
1878 pba = rd32(E1000_RXPBS);
1879 pba = igb_rxpbs_adjust_82580(pba);
1880 break;
fa4dfae0 1881 case e1000_82576:
d249be54
AD		 1882 pba = rd32(E1000_RXPBS);
1883 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1884 break;
1885 case e1000_82575:
f96a8a0b
CW		 1886 case e1000_i210:
1887 case e1000_i211:
fa4dfae0
AD		 1888 default:
1889 pba = E1000_PBA_34K;
1890 break;
2d064c06 1891 }
9d5c8243 1892
2d064c06
AD		 1893 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1894 (mac->type < e1000_82576)) {
9d5c8243
AK		 1895 /* adjust PBA for jumbo frames */
1896 wr32(E1000_PBA, pba);
1897
1898 /* To maintain wire speed transmits, the Tx FIFO should be
1899 * large enough to accommodate two full transmit packets,
1900 * rounded up to the next 1KB and expressed in KB. Likewise,
1901 * the Rx FIFO should be large enough to accommodate at least
1902 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1903 * expressed in KB.
1904 */
9d5c8243
AK		 1905 pba = rd32(E1000_PBA);
1906 /* upper 16 bits has Tx packet buffer allocation size in KB */
1907 tx_space = pba >> 16;
1908 /* lower 16 bits has Rx packet buffer allocation size in KB */
1909 pba &= 0xffff;
b980ac18
JK		 1910 /* the Tx fifo also stores 16 bytes of information about the Tx
1911 * but don't include ethernet FCS because hardware appends it
1912 */
9d5c8243 1913 min_tx_space = (adapter->max_frame_size +
85e8d004 1914 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1915 ETH_FCS_LEN) * 2;
1916 min_tx_space = ALIGN(min_tx_space, 1024);
1917 min_tx_space >>= 10;
1918 /* software strips receive CRC, so leave room for it */
1919 min_rx_space = adapter->max_frame_size;
1920 min_rx_space = ALIGN(min_rx_space, 1024);
1921 min_rx_space >>= 10;
1922
1923 /* If current Tx allocation is less than the min Tx FIFO size,
1924 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1925 * allocation, take space away from current Rx allocation
1926 */
9d5c8243
AK		 1927 if (tx_space < min_tx_space &&
1928 ((min_tx_space - tx_space) < pba)) {
1929 pba = pba - (min_tx_space - tx_space);
1930
b980ac18
JK		 1931 /* if short on Rx space, Rx wins and must trump Tx
1932 * adjustment
1933 */
9d5c8243
AK		 1934 if (pba < min_rx_space)
1935 pba = min_rx_space;
1936 }
2d064c06 1937 wr32(E1000_PBA, pba);
9d5c8243 1938 }
9d5c8243
AK		 1939
1940 /* flow control settings */
1941 /* The high water mark must be low enough to fit one full frame
1942 * (or the size used for early receive) above it in the Rx FIFO.
1943 * Set it to the lower of:
1944 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1945 * - the full Rx FIFO size minus one full frame
1946 */
9d5c8243 1947 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1948 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1949
d48507fe 1950 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1951 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1952 fc->pause_time = 0xFFFF;
1953 fc->send_xon = 1;
0cce119a 1954 fc->current_mode = fc->requested_mode;
9d5c8243 1955
4ae196df
AD		 1956 /* disable receive for all VFs and wait one second */
1957 if (adapter->vfs_allocated_count) {
1958 int i;
9005df38 1959
4ae196df 1960 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1961 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1962
1963 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1964 igb_ping_all_vfs(adapter);
4ae196df
AD		 1965
1966 /* disable transmits and receives */
1967 wr32(E1000_VFRE, 0);
1968 wr32(E1000_VFTE, 0);
1969 }
1970
9d5c8243 1971 /* Allow time for pending master requests to run */
330a6d6a 1972 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1973 wr32(E1000_WUC, 0);
1974
56cec249
CW		 1975 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1976 /* need to resetup here after media swap */
1977 adapter->ei.get_invariants(hw);
1978 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1979 }
1980 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1981 if (igb_enable_mas(adapter))
1982 dev_err(&pdev->dev,
1983 "Error enabling Media Auto Sense\n");
1984 }
330a6d6a 1985 if (hw->mac.ops.init_hw(hw))
090b1795 1986 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1987
b980ac18 1988 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1989 * control is off when forcing speed.
1990 */
1991 if (!hw->mac.autoneg)
1992 igb_force_mac_fc(hw);
1993
b6e0c419 1994 igb_init_dmac(adapter, pba);
e428893b
CW		 1995#ifdef CONFIG_IGB_HWMON
1996 /* Re-initialize the thermal sensor on i350 devices. */
1997 if (!test_bit(__IGB_DOWN, &adapter->state)) {
1998 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1999 /* If present, re-initialize the external thermal sensor
2000 * interface.
2001 */
2002 if (adapter->ets)
2003 mac->ops.init_thermal_sensor_thresh(hw);
2004 }
2005 }
2006#endif
b936136d 2007 /* Re-establish EEE setting */
f4c01e96
CW		 2008 if (hw->phy.media_type == e1000_media_type_copper) {
2009 switch (mac->type) {
2010 case e1000_i350:
2011 case e1000_i210:
2012 case e1000_i211:
2013 igb_set_eee_i350(hw);
2014 break;
2015 case e1000_i354:
2016 igb_set_eee_i354(hw);
2017 break;
2018 default:
2019 break;
2020 }
2021 }
88a268c1
NN		 2022 if (!netif_running(adapter->netdev))
2023 igb_power_down_link(adapter);
2024
9d5c8243
AK		 2025 igb_update_mng_vlan(adapter);
2026
2027 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2028 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2029
1f6e8178
MV		 2030 /* Re-enable PTP, where applicable. */
2031 igb_ptp_reset(adapter);
1f6e8178 2032
330a6d6a 2033 igb_get_phy_info(hw);
9d5c8243
AK		 2034}
2035
c8f44aff
MM		 2036static netdev_features_t igb_fix_features(struct net_device *netdev,
2037 netdev_features_t features)
b2cb09b1 2038{
b980ac18
JK		 2039 /* Since there is no support for separate Rx/Tx vlan accel
2040 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2041 */
f646968f
PM		 2042 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2043 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2044 else
f646968f 2045 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2046
2047 return features;
2048}
2049
c8f44aff
MM		 2050static int igb_set_features(struct net_device *netdev,
2051 netdev_features_t features)
ac52caa3 2052{
c8f44aff 2053 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2054 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2055
f646968f 2056 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2057 igb_vlan_mode(netdev, features);
2058
89eaefb6
BG		 2059 if (!(changed & NETIF_F_RXALL))
2060 return 0;
2061
2062 netdev->features = features;
2063
2064 if (netif_running(netdev))
2065 igb_reinit_locked(adapter);
2066 else
2067 igb_reset(adapter);
2068
ac52caa3
MM		 2069 return 0;
2070}
2071
2e5c6922 2072static const struct net_device_ops igb_netdev_ops = {
559e9c49 2073 .ndo_open = igb_open,
2e5c6922 2074 .ndo_stop = igb_close,
cd392f5c 2075 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2076 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2077 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2078 .ndo_set_mac_address = igb_set_mac,
2079 .ndo_change_mtu = igb_change_mtu,
2080 .ndo_do_ioctl = igb_ioctl,
2081 .ndo_tx_timeout = igb_tx_timeout,
2082 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2083 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2084 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2085 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2086 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
2087 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw,
70ea4783 2088 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2089 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2090#ifdef CONFIG_NET_POLL_CONTROLLER
2091 .ndo_poll_controller = igb_netpoll,
2092#endif
b2cb09b1
JP		 2093 .ndo_fix_features = igb_fix_features,
2094 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2095};
2096
d67974f0
CW		 2097/**
2098 * igb_set_fw_version - Configure version string for ethtool
2099 * @adapter: adapter struct
d67974f0
CW		 2100 **/
2101void igb_set_fw_version(struct igb_adapter *adapter)
2102{
2103 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2104 struct e1000_fw_version fw;
2105
2106 igb_get_fw_version(hw, &fw);
2107
2108 switch (hw->mac.type) {
7dc98a62 2109 case e1000_i210:
0b1a6f2e 2110 case e1000_i211:
7dc98a62
CW		 2111 if (!(igb_get_flash_presence_i210(hw))) {
2112 snprintf(adapter->fw_version,
2113 sizeof(adapter->fw_version),
2114 "%2d.%2d-%d",
2115 fw.invm_major, fw.invm_minor,
2116 fw.invm_img_type);
2117 break;
2118 }
2119 /* fall through */
0b1a6f2e
CW		 2120 default:
2121 /* if option is rom valid, display its version too */
2122 if (fw.or_valid) {
2123 snprintf(adapter->fw_version,
2124 sizeof(adapter->fw_version),
2125 "%d.%d, 0x%08x, %d.%d.%d",
2126 fw.eep_major, fw.eep_minor, fw.etrack_id,
2127 fw.or_major, fw.or_build, fw.or_patch);
2128 /* no option rom */
7dc98a62 2129 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2130 snprintf(adapter->fw_version,
7dc98a62
CW		 2131 sizeof(adapter->fw_version),
2132 "%d.%d, 0x%08x",
2133 fw.eep_major, fw.eep_minor, fw.etrack_id);
2134 } else {
2135 snprintf(adapter->fw_version,
2136 sizeof(adapter->fw_version),
2137 "%d.%d.%d",
2138 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2139 }
2140 break;
d67974f0 2141 }
d67974f0
CW		 2142 return;
2143}
2144
56cec249
CW		 2145/**
2146 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2147 *
2148 * @adapter: adapter struct
2149 **/
2150static void igb_init_mas(struct igb_adapter *adapter)
2151{
2152 struct e1000_hw *hw = &adapter->hw;
2153 u16 eeprom_data;
2154
2155 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2156 switch (hw->bus.func) {
2157 case E1000_FUNC_0:
2158 if (eeprom_data & IGB_MAS_ENABLE_0) {
2159 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2160 netdev_info(adapter->netdev,
2161 "MAS: Enabling Media Autosense for port %d\n",
2162 hw->bus.func);
2163 }
2164 break;
2165 case E1000_FUNC_1:
2166 if (eeprom_data & IGB_MAS_ENABLE_1) {
2167 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2168 netdev_info(adapter->netdev,
2169 "MAS: Enabling Media Autosense for port %d\n",
2170 hw->bus.func);
2171 }
2172 break;
2173 case E1000_FUNC_2:
2174 if (eeprom_data & IGB_MAS_ENABLE_2) {
2175 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2176 netdev_info(adapter->netdev,
2177 "MAS: Enabling Media Autosense for port %d\n",
2178 hw->bus.func);
2179 }
2180 break;
2181 case E1000_FUNC_3:
2182 if (eeprom_data & IGB_MAS_ENABLE_3) {
2183 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2184 netdev_info(adapter->netdev,
2185 "MAS: Enabling Media Autosense for port %d\n",
2186 hw->bus.func);
2187 }
2188 break;
2189 default:
2190 /* Shouldn't get here */
2191 netdev_err(adapter->netdev,
2192 "MAS: Invalid port configuration, returning\n");
2193 break;
2194 }
2195}
2196
b980ac18
JK		 2197/**
2198 * igb_init_i2c - Init I2C interface
441fc6fd 2199 * @adapter: pointer to adapter structure
b980ac18 2200 **/
441fc6fd
CW		 2201static s32 igb_init_i2c(struct igb_adapter *adapter)
2202{
2203 s32 status = E1000_SUCCESS;
2204
2205 /* I2C interface supported on i350 devices */
2206 if (adapter->hw.mac.type != e1000_i350)
2207 return E1000_SUCCESS;
2208
2209 /* Initialize the i2c bus which is controlled by the registers.
2210 * This bus will use the i2c_algo_bit structue that implements
2211 * the protocol through toggling of the 4 bits in the register.
2212 */
2213 adapter->i2c_adap.owner = THIS_MODULE;
2214 adapter->i2c_algo = igb_i2c_algo;
2215 adapter->i2c_algo.data = adapter;
2216 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2217 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2218 strlcpy(adapter->i2c_adap.name, "igb BB",
2219 sizeof(adapter->i2c_adap.name));
2220 status = i2c_bit_add_bus(&adapter->i2c_adap);
2221 return status;
2222}
2223
9d5c8243 2224/**
b980ac18
JK		 2225 * igb_probe - Device Initialization Routine
2226 * @pdev: PCI device information struct
2227 * @ent: entry in igb_pci_tbl
9d5c8243 2228 *
b980ac18 2229 * Returns 0 on success, negative on failure
9d5c8243 2230 *
b980ac18
JK		 2231 * igb_probe initializes an adapter identified by a pci_dev structure.
2232 * The OS initialization, configuring of the adapter private structure,
2233 * and a hardware reset occur.
9d5c8243 2234 **/
1dd06ae8 2235static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2236{
2237 struct net_device *netdev;
2238 struct igb_adapter *adapter;
2239 struct e1000_hw *hw;
4337e993 2240 u16 eeprom_data = 0;
9835fd73 2241 s32 ret_val;
4337e993 2242 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2243 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2244 int err, pci_using_dac;
9835fd73 2245 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2246
bded64a7
AG		 2247 /* Catch broken hardware that put the wrong VF device ID in
2248 * the PCIe SR-IOV capability.
2249 */
2250 if (pdev->is_virtfn) {
2251 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2252 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2253 return -EINVAL;
2254 }
2255
aed5dec3 2256 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2257 if (err)
2258 return err;
2259
2260 pci_using_dac = 0;
dc4ff9bb 2261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2262 if (!err) {
dc4ff9bb 2263 pci_using_dac = 1;
9d5c8243 2264 } else {
dc4ff9bb 2265 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2266 if (err) {
dc4ff9bb
RK		 2267 dev_err(&pdev->dev,
2268 "No usable DMA configuration, aborting\n");
2269 goto err_dma;
9d5c8243
AK		 2270 }
2271 }
2272
aed5dec3 2273 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2274 IORESOURCE_MEM),
2275 igb_driver_name);
9d5c8243
AK		 2276 if (err)
2277 goto err_pci_reg;
2278
19d5afd4 2279 pci_enable_pcie_error_reporting(pdev);
40a914fa 2280
9d5c8243 2281 pci_set_master(pdev);
c682fc23 2282 pci_save_state(pdev);
9d5c8243
AK		 2283
2284 err = -ENOMEM;
1bfaf07b 2285 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2286 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2287 if (!netdev)
2288 goto err_alloc_etherdev;
2289
2290 SET_NETDEV_DEV(netdev, &pdev->dev);
2291
2292 pci_set_drvdata(pdev, netdev);
2293 adapter = netdev_priv(netdev);
2294 adapter->netdev = netdev;
2295 adapter->pdev = pdev;
2296 hw = &adapter->hw;
2297 hw->back = adapter;
b3f4d599 2298 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2299
9d5c8243 2300 err = -EIO;
89dbefb2 2301 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2302 if (!hw->hw_addr)
9d5c8243
AK		 2303 goto err_ioremap;
2304
2e5c6922 2305 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2306 igb_set_ethtool_ops(netdev);
9d5c8243 2307 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2308
2309 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2310
89dbefb2
AS		 2311 netdev->mem_start = pci_resource_start(pdev, 0);
2312 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2313
9d5c8243
AK		 2314 /* PCI config space info */
2315 hw->vendor_id = pdev->vendor;
2316 hw->device_id = pdev->device;
2317 hw->revision_id = pdev->revision;
2318 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2319 hw->subsystem_device_id = pdev->subsystem_device;
2320
9d5c8243
AK		 2321 /* Copy the default MAC, PHY and NVM function pointers */
2322 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2323 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2324 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2325 /* Initialize skew-specific constants */
2326 err = ei->get_invariants(hw);
2327 if (err)
450c87c8 2328 goto err_sw_init;
9d5c8243 2329
450c87c8 2330 /* setup the private structure */
9d5c8243
AK		 2331 err = igb_sw_init(adapter);
2332 if (err)
2333 goto err_sw_init;
2334
2335 igb_get_bus_info_pcie(hw);
2336
2337 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2338
2339 /* Copper options */
2340 if (hw->phy.media_type == e1000_media_type_copper) {
2341 hw->phy.mdix = AUTO_ALL_MODES;
2342 hw->phy.disable_polarity_correction = false;
2343 hw->phy.ms_type = e1000_ms_hw_default;
2344 }
2345
2346 if (igb_check_reset_block(hw))
2347 dev_info(&pdev->dev,
2348 "PHY reset is blocked due to SOL/IDER session.\n");
2349
b980ac18 2350 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2351 * set by igb_sw_init so we should use an or instead of an
2352 * assignment.
2353 */
2354 netdev->features |= NETIF_F_SG |
2355 NETIF_F_IP_CSUM |
2356 NETIF_F_IPV6_CSUM |
2357 NETIF_F_TSO |
2358 NETIF_F_TSO6 |
2359 NETIF_F_RXHASH |
2360 NETIF_F_RXCSUM |
f646968f
PM		 2361 NETIF_F_HW_VLAN_CTAG_RX |
2362 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2363
2364 /* copy netdev features into list of user selectable features */
2365 netdev->hw_features |= netdev->features;
89eaefb6 2366 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2367
2368 /* set this bit last since it cannot be part of hw_features */
f646968f 2369 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2370
2371 netdev->vlan_features |= NETIF_F_TSO |
2372 NETIF_F_TSO6 |
2373 NETIF_F_IP_CSUM |
2374 NETIF_F_IPV6_CSUM |
2375 NETIF_F_SG;
48f29ffc 2376
6b8f0922
BG		 2377 netdev->priv_flags |= IFF_SUPP_NOFCS;
2378
7b872a55 2379 if (pci_using_dac) {
9d5c8243 2380 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2381 netdev->vlan_features |= NETIF_F_HIGHDMA;
2382 }
9d5c8243 2383
ac52caa3
MM		 2384 if (hw->mac.type >= e1000_82576) {
2385 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2386 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2387 }
b9473560 2388
01789349
JP		 2389 netdev->priv_flags |= IFF_UNICAST_FLT;
2390
330a6d6a 2391 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2392
2393 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2394 * known good starting state
2395 */
9d5c8243
AK		 2396 hw->mac.ops.reset_hw(hw);
2397
ef3a0092
CW		 2398 /* make sure the NVM is good , i211/i210 parts can have special NVM
2399 * that doesn't contain a checksum
f96a8a0b 2400 */
ef3a0092
CW		 2401 switch (hw->mac.type) {
2402 case e1000_i210:
2403 case e1000_i211:
2404 if (igb_get_flash_presence_i210(hw)) {
2405 if (hw->nvm.ops.validate(hw) < 0) {
2406 dev_err(&pdev->dev,
2407 "The NVM Checksum Is Not Valid\n");
2408 err = -EIO;
2409 goto err_eeprom;
2410 }
2411 }
2412 break;
2413 default:
f96a8a0b
CW		 2414 if (hw->nvm.ops.validate(hw) < 0) {
2415 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2416 err = -EIO;
2417 goto err_eeprom;
2418 }
ef3a0092 2419 break;
9d5c8243
AK		 2420 }
2421
2422 /* copy the MAC address out of the NVM */
2423 if (hw->mac.ops.read_mac_addr(hw))
2424 dev_err(&pdev->dev, "NVM Read Error\n");
2425
2426 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2427
aaeb6cdf 2428 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2429 dev_err(&pdev->dev, "Invalid MAC Address\n");
2430 err = -EIO;
2431 goto err_eeprom;
2432 }
2433
d67974f0
CW		 2434 /* get firmware version for ethtool -i */
2435 igb_set_fw_version(adapter);
2436
c061b18d 2437 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2438 (unsigned long) adapter);
c061b18d 2439 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2440 (unsigned long) adapter);
9d5c8243
AK		 2441
2442 INIT_WORK(&adapter->reset_task, igb_reset_task);
2443 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2444
450c87c8 2445 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2446 adapter->fc_autoneg = true;
2447 hw->mac.autoneg = true;
2448 hw->phy.autoneg_advertised = 0x2f;
2449
0cce119a
AD		 2450 hw->fc.requested_mode = e1000_fc_default;
2451 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2452
9d5c8243
AK		 2453 igb_validate_mdi_setting(hw);
2454
63d4a8f9 2455 /* By default, support wake on port A */
a2cf8b6c 2456 if (hw->bus.func == 0)
63d4a8f9
MV		 2457 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2458
2459 /* Check the NVM for wake support on non-port A ports */
2460 if (hw->mac.type >= e1000_82580)
55cac248 2461 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2462 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2463 &eeprom_data);
a2cf8b6c
AD		 2464 else if (hw->bus.func == 1)
2465 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2466
63d4a8f9
MV		 2467 if (eeprom_data & IGB_EEPROM_APME)
2468 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2469
2470 /* now that we have the eeprom settings, apply the special cases where
2471 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2472 * lan on a particular port
2473 */
9d5c8243
AK		 2474 switch (pdev->device) {
2475 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2476 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2477 break;
2478 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2479 case E1000_DEV_ID_82576_FIBER:
2480 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2481 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2482 * regardless of eeprom setting
2483 */
9d5c8243 2484 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2485 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2486 break;
c8ea5ea9 2487 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2488 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2489 /* if quad port adapter, disable WoL on all but port A */
2490 if (global_quad_port_a != 0)
63d4a8f9 2491 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2492 else
2493 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2494 /* Reset for multiple quad port adapters */
2495 if (++global_quad_port_a == 4)
2496 global_quad_port_a = 0;
2497 break;
63d4a8f9
MV		 2498 default:
2499 /* If the device can't wake, don't set software support */
2500 if (!device_can_wakeup(&adapter->pdev->dev))
2501 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2502 }
2503
2504 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2505 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2506 adapter->wol |= E1000_WUFC_MAG;
2507
2508 /* Some vendors want WoL disabled by default, but still supported */
2509 if ((hw->mac.type == e1000_i350) &&
2510 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2511 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2512 adapter->wol = 0;
2513 }
2514
2515 device_set_wakeup_enable(&adapter->pdev->dev,
2516 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2517
2518 /* reset the hardware with the new settings */
2519 igb_reset(adapter);
2520
441fc6fd
CW		 2521 /* Init the I2C interface */
2522 err = igb_init_i2c(adapter);
2523 if (err) {
2524 dev_err(&pdev->dev, "failed to init i2c interface\n");
2525 goto err_eeprom;
2526 }
2527
9d5c8243 2528 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2529 * driver.
2530 */
9d5c8243
AK		 2531 igb_get_hw_control(adapter);
2532
9d5c8243
AK		 2533 strcpy(netdev->name, "eth%d");
2534 err = register_netdev(netdev);
2535 if (err)
2536 goto err_register;
2537
b168dfc5
JB		 2538 /* carrier off reporting is important to ethtool even BEFORE open */
2539 netif_carrier_off(netdev);
2540
421e02f0 2541#ifdef CONFIG_IGB_DCA
bbd98fe4 2542 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2543 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2544 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2545 igb_setup_dca(adapter);
2546 }
fe4506b6 2547
38c845c7 2548#endif
e428893b
CW		 2549#ifdef CONFIG_IGB_HWMON
2550 /* Initialize the thermal sensor on i350 devices. */
2551 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2552 u16 ets_word;
3c89f6d0 2553
b980ac18 2554 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2555 * external thermal sensor.
2556 */
2557 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2558 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2559 adapter->ets = true;
2560 else
2561 adapter->ets = false;
2562 if (igb_sysfs_init(adapter))
2563 dev_err(&pdev->dev,
2564 "failed to allocate sysfs resources\n");
2565 } else {
2566 adapter->ets = false;
2567 }
2568#endif
56cec249
CW		 2569 /* Check if Media Autosense is enabled */
2570 adapter->ei = *ei;
2571 if (hw->dev_spec._82575.mas_capable)
2572 igb_init_mas(adapter);
2573
673b8b70 2574 /* do hw tstamp init after resetting */
7ebae817 2575 igb_ptp_init(adapter);
673b8b70 2576
9d5c8243 2577 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2578 /* print bus type/speed/width info, not applicable to i354 */
2579 if (hw->mac.type != e1000_i354) {
2580 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2581 netdev->name,
2582 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2583 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2584 "unknown"),
2585 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2586 "Width x4" :
2587 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2588 "Width x2" :
2589 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2590 "Width x1" : "unknown"), netdev->dev_addr);
2591 }
9d5c8243 2592
53ea6c7e
TF		 2593 if ((hw->mac.type >= e1000_i210 ||
2594 igb_get_flash_presence_i210(hw))) {
2595 ret_val = igb_read_part_string(hw, part_str,
2596 E1000_PBANUM_LENGTH);
2597 } else {
2598 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2599 }
2600
9835fd73
CW		 2601 if (ret_val)
2602 strcpy(part_str, "Unknown");
2603 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2604 dev_info(&pdev->dev,
2605 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2606 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2607 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2608 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2609 if (hw->phy.media_type == e1000_media_type_copper) {
2610 switch (hw->mac.type) {
2611 case e1000_i350:
2612 case e1000_i210:
2613 case e1000_i211:
2614 /* Enable EEE for internal copper PHY devices */
2615 err = igb_set_eee_i350(hw);
2616 if ((!err) &&
2617 (!hw->dev_spec._82575.eee_disable)) {
2618 adapter->eee_advert =
2619 MDIO_EEE_100TX | MDIO_EEE_1000T;
2620 adapter->flags |= IGB_FLAG_EEE;
2621 }
2622 break;
2623 case e1000_i354:
ceb5f13b 2624 if ((rd32(E1000_CTRL_EXT) &
f4c01e96
CW		 2625 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2626 err = igb_set_eee_i354(hw);
2627 if ((!err) &&
2628 (!hw->dev_spec._82575.eee_disable)) {
2629 adapter->eee_advert =
2630 MDIO_EEE_100TX | MDIO_EEE_1000T;
2631 adapter->flags |= IGB_FLAG_EEE;
2632 }
2633 }
2634 break;
2635 default:
2636 break;
ceb5f13b 2637 }
09b068d4 2638 }
749ab2cd 2639 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2640 return 0;
2641
2642err_register:
2643 igb_release_hw_control(adapter);
441fc6fd 2644 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2645err_eeprom:
2646 if (!igb_check_reset_block(hw))
f5f4cf08 2647 igb_reset_phy(hw);
9d5c8243
AK		 2648
2649 if (hw->flash_address)
2650 iounmap(hw->flash_address);
9d5c8243 2651err_sw_init:
047e0030 2652 igb_clear_interrupt_scheme(adapter);
75009b3a 2653 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2654err_ioremap:
2655 free_netdev(netdev);
2656err_alloc_etherdev:
559e9c49 2657 pci_release_selected_regions(pdev,
b980ac18 2658 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2659err_pci_reg:
2660err_dma:
2661 pci_disable_device(pdev);
2662 return err;
2663}
2664
fa44f2f1 2665#ifdef CONFIG_PCI_IOV
781798a1 2666static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2667{
2668 struct net_device *netdev = pci_get_drvdata(pdev);
2669 struct igb_adapter *adapter = netdev_priv(netdev);
2670 struct e1000_hw *hw = &adapter->hw;
2671
2672 /* reclaim resources allocated to VFs */
2673 if (adapter->vf_data) {
2674 /* disable iov and allow time for transactions to clear */
b09186d2 2675 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2676 dev_warn(&pdev->dev,
2677 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2678 return -EPERM;
2679 } else {
2680 pci_disable_sriov(pdev);
2681 msleep(500);
2682 }
2683
2684 kfree(adapter->vf_data);
2685 adapter->vf_data = NULL;
2686 adapter->vfs_allocated_count = 0;
2687 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2688 wrfl();
2689 msleep(100);
2690 dev_info(&pdev->dev, "IOV Disabled\n");
2691
2692 /* Re-enable DMA Coalescing flag since IOV is turned off */
2693 adapter->flags |= IGB_FLAG_DMAC;
2694 }
2695
2696 return 0;
2697}
2698
2699static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2700{
2701 struct net_device *netdev = pci_get_drvdata(pdev);
2702 struct igb_adapter *adapter = netdev_priv(netdev);
2703 int old_vfs = pci_num_vf(pdev);
2704 int err = 0;
2705 int i;
2706
cd14ef54 2707 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2708 err = -EPERM;
2709 goto out;
2710 }
fa44f2f1
GR		 2711 if (!num_vfs)
2712 goto out;
fa44f2f1 2713
781798a1
SA		 2714 if (old_vfs) {
2715 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2716 old_vfs, max_vfs);
2717 adapter->vfs_allocated_count = old_vfs;
2718 } else
2719 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2720
2721 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2722 sizeof(struct vf_data_storage), GFP_KERNEL);
2723
2724 /* if allocation failed then we do not support SR-IOV */
2725 if (!adapter->vf_data) {
2726 adapter->vfs_allocated_count = 0;
2727 dev_err(&pdev->dev,
2728 "Unable to allocate memory for VF Data Storage\n");
2729 err = -ENOMEM;
2730 goto out;
2731 }
2732
781798a1
SA		 2733 /* only call pci_enable_sriov() if no VFs are allocated already */
2734 if (!old_vfs) {
2735 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2736 if (err)
2737 goto err_out;
2738 }
fa44f2f1
GR		 2739 dev_info(&pdev->dev, "%d VFs allocated\n",
2740 adapter->vfs_allocated_count);
2741 for (i = 0; i < adapter->vfs_allocated_count; i++)
2742 igb_vf_configure(adapter, i);
2743
2744 /* DMA Coalescing is not supported in IOV mode. */
2745 adapter->flags &= ~IGB_FLAG_DMAC;
2746 goto out;
2747
2748err_out:
2749 kfree(adapter->vf_data);
2750 adapter->vf_data = NULL;
2751 adapter->vfs_allocated_count = 0;
2752out:
2753 return err;
2754}
2755
2756#endif
b980ac18 2757/**
441fc6fd
CW		 2758 * igb_remove_i2c - Cleanup I2C interface
2759 * @adapter: pointer to adapter structure
b980ac18 2760 **/
441fc6fd
CW		 2761static void igb_remove_i2c(struct igb_adapter *adapter)
2762{
441fc6fd
CW		 2763 /* free the adapter bus structure */
2764 i2c_del_adapter(&adapter->i2c_adap);
2765}
2766
9d5c8243 2767/**
b980ac18
JK		 2768 * igb_remove - Device Removal Routine
2769 * @pdev: PCI device information struct
9d5c8243 2770 *
b980ac18
JK		 2771 * igb_remove is called by the PCI subsystem to alert the driver
2772 * that it should release a PCI device. The could be caused by a
2773 * Hot-Plug event, or because the driver is going to be removed from
2774 * memory.
9d5c8243 2775 **/
9f9a12f8 2776static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2777{
2778 struct net_device *netdev = pci_get_drvdata(pdev);
2779 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2780 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2781
749ab2cd 2782 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2783#ifdef CONFIG_IGB_HWMON
2784 igb_sysfs_exit(adapter);
2785#endif
441fc6fd 2786 igb_remove_i2c(adapter);
a79f4f88 2787 igb_ptp_stop(adapter);
b980ac18 2788 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2789 * disable watchdog from being rescheduled.
2790 */
9d5c8243
AK		 2791 set_bit(__IGB_DOWN, &adapter->state);
2792 del_timer_sync(&adapter->watchdog_timer);
2793 del_timer_sync(&adapter->phy_info_timer);
2794
760141a5
TH		 2795 cancel_work_sync(&adapter->reset_task);
2796 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2797
421e02f0 2798#ifdef CONFIG_IGB_DCA
7dfc16fa 2799 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2800 dev_info(&pdev->dev, "DCA disabled\n");
2801 dca_remove_requester(&pdev->dev);
7dfc16fa 2802 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2803 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2804 }
2805#endif
2806
9d5c8243 2807 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2808 * would have already happened in close and is redundant.
2809 */
9d5c8243
AK		 2810 igb_release_hw_control(adapter);
2811
2812 unregister_netdev(netdev);
2813
047e0030 2814 igb_clear_interrupt_scheme(adapter);
9d5c8243 2815
37680117 2816#ifdef CONFIG_PCI_IOV
fa44f2f1 2817 igb_disable_sriov(pdev);
37680117 2818#endif
559e9c49 2819
75009b3a 2820 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2821 if (hw->flash_address)
2822 iounmap(hw->flash_address);
559e9c49 2823 pci_release_selected_regions(pdev,
b980ac18 2824 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2825
1128c756 2826 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2827 free_netdev(netdev);
2828
19d5afd4 2829 pci_disable_pcie_error_reporting(pdev);
40a914fa 2830
9d5c8243
AK		 2831 pci_disable_device(pdev);
2832}
2833
a6b623e0 2834/**
b980ac18
JK		 2835 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2836 * @adapter: board private structure to initialize
a6b623e0 2837 *
b980ac18
JK		 2838 * This function initializes the vf specific data storage and then attempts to
2839 * allocate the VFs. The reason for ordering it this way is because it is much
2840 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2841 * the memory for the VFs.
a6b623e0 2842 **/
9f9a12f8 2843static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2844{
2845#ifdef CONFIG_PCI_IOV
2846 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2847 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2848
f96a8a0b
CW		 2849 /* Virtualization features not supported on i210 family. */
2850 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2851 return;
2852
fa44f2f1 2853 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2854 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2855
a6b623e0
AD		 2856#endif /* CONFIG_PCI_IOV */
2857}
2858
fa44f2f1 2859static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2860{
2861 struct e1000_hw *hw = &adapter->hw;
374a542d 2862 u32 max_rss_queues;
9d5c8243 2863
374a542d 2864 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2865 switch (hw->mac.type) {
374a542d
MV		 2866 case e1000_i211:
2867 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2868 break;
2869 case e1000_82575:
f96a8a0b 2870 case e1000_i210:
374a542d
MV		 2871 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2872 break;
2873 case e1000_i350:
2874 /* I350 cannot do RSS and SR-IOV at the same time */
2875 if (!!adapter->vfs_allocated_count) {
2876 max_rss_queues = 1;
2877 break;
2878 }
2879 /* fall through */
2880 case e1000_82576:
2881 if (!!adapter->vfs_allocated_count) {
2882 max_rss_queues = 2;
2883 break;
2884 }
2885 /* fall through */
2886 case e1000_82580:
ceb5f13b 2887 case e1000_i354:
374a542d
MV		 2888 default:
2889 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2890 break;
374a542d
MV		 2891 }
2892
2893 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2894
2895 /* Determine if we need to pair queues. */
2896 switch (hw->mac.type) {
2897 case e1000_82575:
f96a8a0b 2898 case e1000_i211:
374a542d 2899 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2900 break;
374a542d 2901 case e1000_82576:
b980ac18 2902 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2903 * should pair the queues in order to conserve interrupts due
2904 * to limited supply.
2905 */
2906 if ((adapter->rss_queues > 1) &&
2907 (adapter->vfs_allocated_count > 6))
2908 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2909 /* fall through */
2910 case e1000_82580:
2911 case e1000_i350:
ceb5f13b 2912 case e1000_i354:
374a542d 2913 case e1000_i210:
f96a8a0b 2914 default:
b980ac18 2915 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2916 * order to conserve interrupts due to limited supply.
2917 */
2918 if (adapter->rss_queues > (max_rss_queues / 2))
2919 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2920 break;
2921 }
fa44f2f1
GR		 2922}
2923
2924/**
b980ac18
JK		 2925 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2926 * @adapter: board private structure to initialize
fa44f2f1 2927 *
b980ac18
JK		 2928 * igb_sw_init initializes the Adapter private data structure.
2929 * Fields are initialized based on PCI device information and
2930 * OS network device settings (MTU size).
fa44f2f1
GR		 2931 **/
2932static int igb_sw_init(struct igb_adapter *adapter)
2933{
2934 struct e1000_hw *hw = &adapter->hw;
2935 struct net_device *netdev = adapter->netdev;
2936 struct pci_dev *pdev = adapter->pdev;
2937
2938 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2939
2940 /* set default ring sizes */
2941 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2942 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2943
2944 /* set default ITR values */
2945 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2946 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2947
2948 /* set default work limits */
2949 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2950
2951 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2952 VLAN_HLEN;
2953 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2954
2955 spin_lock_init(&adapter->stats64_lock);
2956#ifdef CONFIG_PCI_IOV
2957 switch (hw->mac.type) {
2958 case e1000_82576:
2959 case e1000_i350:
2960 if (max_vfs > 7) {
2961 dev_warn(&pdev->dev,
2962 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2963 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2964 } else
2965 adapter->vfs_allocated_count = max_vfs;
2966 if (adapter->vfs_allocated_count)
2967 dev_warn(&pdev->dev,
2968 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2969 break;
2970 default:
2971 break;
2972 }
2973#endif /* CONFIG_PCI_IOV */
2974
2975 igb_init_queue_configuration(adapter);
a99955fc 2976
1128c756 2977 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2978 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2979 GFP_ATOMIC);
1128c756 2980
a6b623e0 2981 /* This call may decrease the number of queues */
53c7d064 2982 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2983 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2984 return -ENOMEM;
2985 }
2986
a6b623e0
AD		 2987 igb_probe_vfs(adapter);
2988
9d5c8243
AK		 2989 /* Explicitly disable IRQ since the NIC can be in any state. */
2990 igb_irq_disable(adapter);
2991
f96a8a0b 2992 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 2993 adapter->flags &= ~IGB_FLAG_DMAC;
2994
9d5c8243
AK		 2995 set_bit(__IGB_DOWN, &adapter->state);
2996 return 0;
2997}
2998
2999/**
b980ac18
JK		 3000 * igb_open - Called when a network interface is made active
3001 * @netdev: network interface device structure
9d5c8243 3002 *
b980ac18 3003 * Returns 0 on success, negative value on failure
9d5c8243 3004 *
b980ac18
JK		 3005 * The open entry point is called when a network interface is made
3006 * active by the system (IFF_UP). At this point all resources needed
3007 * for transmit and receive operations are allocated, the interrupt
3008 * handler is registered with the OS, the watchdog timer is started,
3009 * and the stack is notified that the interface is ready.
9d5c8243 3010 **/
749ab2cd 3011static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3012{
3013 struct igb_adapter *adapter = netdev_priv(netdev);
3014 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3015 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3016 int err;
3017 int i;
3018
3019 /* disallow open during test */
749ab2cd
YZ		 3020 if (test_bit(__IGB_TESTING, &adapter->state)) {
3021 WARN_ON(resuming);
9d5c8243 3022 return -EBUSY;
749ab2cd
YZ		 3023 }
3024
3025 if (!resuming)
3026 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3027
b168dfc5
JB		 3028 netif_carrier_off(netdev);
3029
9d5c8243
AK		 3030 /* allocate transmit descriptors */
3031 err = igb_setup_all_tx_resources(adapter);
3032 if (err)
3033 goto err_setup_tx;
3034
3035 /* allocate receive descriptors */
3036 err = igb_setup_all_rx_resources(adapter);
3037 if (err)
3038 goto err_setup_rx;
3039
88a268c1 3040 igb_power_up_link(adapter);
9d5c8243 3041
9d5c8243
AK		 3042 /* before we allocate an interrupt, we must be ready to handle it.
3043 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3044 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3045 * clean_rx handler before we do so.
3046 */
9d5c8243
AK		 3047 igb_configure(adapter);
3048
3049 err = igb_request_irq(adapter);
3050 if (err)
3051 goto err_req_irq;
3052
0c2cc02e
AD		 3053 /* Notify the stack of the actual queue counts. */
3054 err = netif_set_real_num_tx_queues(adapter->netdev,
3055 adapter->num_tx_queues);
3056 if (err)
3057 goto err_set_queues;
3058
3059 err = netif_set_real_num_rx_queues(adapter->netdev,
3060 adapter->num_rx_queues);
3061 if (err)
3062 goto err_set_queues;
3063
9d5c8243
AK		 3064 /* From here on the code is the same as igb_up() */
3065 clear_bit(__IGB_DOWN, &adapter->state);
3066
0d1ae7f4
AD		 3067 for (i = 0; i < adapter->num_q_vectors; i++)
3068 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3069
3070 /* Clear any pending interrupts. */
3071 rd32(E1000_ICR);
844290e5
PW		 3072
3073 igb_irq_enable(adapter);
3074
d4960307
AD		 3075 /* notify VFs that reset has been completed */
3076 if (adapter->vfs_allocated_count) {
3077 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3078
d4960307
AD		 3079 reg_data |= E1000_CTRL_EXT_PFRSTD;
3080 wr32(E1000_CTRL_EXT, reg_data);
3081 }
3082
d55b53ff
JK		 3083 netif_tx_start_all_queues(netdev);
3084
749ab2cd
YZ		 3085 if (!resuming)
3086 pm_runtime_put(&pdev->dev);
3087
25568a53
AD		 3088 /* start the watchdog. */
3089 hw->mac.get_link_status = 1;
3090 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3091
3092 return 0;
3093
0c2cc02e
AD		 3094err_set_queues:
3095 igb_free_irq(adapter);
9d5c8243
AK		 3096err_req_irq:
3097 igb_release_hw_control(adapter);
88a268c1 3098 igb_power_down_link(adapter);
9d5c8243
AK		 3099 igb_free_all_rx_resources(adapter);
3100err_setup_rx:
3101 igb_free_all_tx_resources(adapter);
3102err_setup_tx:
3103 igb_reset(adapter);
749ab2cd
YZ		 3104 if (!resuming)
3105 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3106
3107 return err;
3108}
3109
749ab2cd
YZ		 3110static int igb_open(struct net_device *netdev)
3111{
3112 return __igb_open(netdev, false);
3113}
3114
9d5c8243 3115/**
b980ac18
JK		 3116 * igb_close - Disables a network interface
3117 * @netdev: network interface device structure
9d5c8243 3118 *
b980ac18 3119 * Returns 0, this is not allowed to fail
9d5c8243 3120 *
b980ac18
JK		 3121 * The close entry point is called when an interface is de-activated
3122 * by the OS. The hardware is still under the driver's control, but
3123 * needs to be disabled. A global MAC reset is issued to stop the
3124 * hardware, and all transmit and receive resources are freed.
9d5c8243 3125 **/
749ab2cd 3126static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3127{
3128 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3129 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3130
3131 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3132
749ab2cd
YZ		 3133 if (!suspending)
3134 pm_runtime_get_sync(&pdev->dev);
3135
3136 igb_down(adapter);
9d5c8243
AK		 3137 igb_free_irq(adapter);
3138
3139 igb_free_all_tx_resources(adapter);
3140 igb_free_all_rx_resources(adapter);
3141
749ab2cd
YZ		 3142 if (!suspending)
3143 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3144 return 0;
3145}
3146
749ab2cd
YZ		 3147static int igb_close(struct net_device *netdev)
3148{
3149 return __igb_close(netdev, false);
3150}
3151
9d5c8243 3152/**
b980ac18
JK		 3153 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3154 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3155 *
b980ac18 3156 * Return 0 on success, negative on failure
9d5c8243 3157 **/
80785298 3158int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3159{
59d71989 3160 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3161 int size;
3162
06034649 3163 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3164
3165 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3166 if (!tx_ring->tx_buffer_info)
9d5c8243 3167 goto err;
9d5c8243
AK		 3168
3169 /* round up to nearest 4K */
85e8d004 3170 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3171 tx_ring->size = ALIGN(tx_ring->size, 4096);
3172
5536d210
AD		 3173 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3174 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3175 if (!tx_ring->desc)
3176 goto err;
3177
9d5c8243
AK		 3178 tx_ring->next_to_use = 0;
3179 tx_ring->next_to_clean = 0;
81c2fc22 3180
9d5c8243
AK		 3181 return 0;
3182
3183err:
06034649 3184 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3185 tx_ring->tx_buffer_info = NULL;
3186 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3187 return -ENOMEM;
3188}
3189
3190/**
b980ac18
JK		 3191 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3192 * (Descriptors) for all queues
3193 * @adapter: board private structure
9d5c8243 3194 *
b980ac18 3195 * Return 0 on success, negative on failure
9d5c8243
AK		 3196 **/
3197static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3198{
439705e1 3199 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3200 int i, err = 0;
3201
3202 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3203 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3204 if (err) {
439705e1 3205 dev_err(&pdev->dev,
9d5c8243
AK		 3206 "Allocation for Tx Queue %u failed\n", i);
3207 for (i--; i >= 0; i--)
3025a446 3208 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3209 break;
3210 }
3211 }
3212
3213 return err;
3214}
3215
3216/**
b980ac18
JK		 3217 * igb_setup_tctl - configure the transmit control registers
3218 * @adapter: Board private structure
9d5c8243 3219 **/
d7ee5b3a 3220void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3221{
9d5c8243
AK		 3222 struct e1000_hw *hw = &adapter->hw;
3223 u32 tctl;
9d5c8243 3224
85b430b4
AD		 3225 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3226 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3227
3228 /* Program the Transmit Control Register */
9d5c8243
AK		 3229 tctl = rd32(E1000_TCTL);
3230 tctl &= ~E1000_TCTL_CT;
3231 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3232 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3233
3234 igb_config_collision_dist(hw);
3235
9d5c8243
AK		 3236 /* Enable transmits */
3237 tctl |= E1000_TCTL_EN;
3238
3239 wr32(E1000_TCTL, tctl);
3240}
3241
85b430b4 3242/**
b980ac18
JK		 3243 * igb_configure_tx_ring - Configure transmit ring after Reset
3244 * @adapter: board private structure
3245 * @ring: tx ring to configure
85b430b4 3246 *
b980ac18 3247 * Configure a transmit ring after a reset.
85b430b4 3248 **/
d7ee5b3a 3249void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3250 struct igb_ring *ring)
85b430b4
AD		 3251{
3252 struct e1000_hw *hw = &adapter->hw;
a74420e0 3253 u32 txdctl = 0;
85b430b4
AD		 3254 u64 tdba = ring->dma;
3255 int reg_idx = ring->reg_idx;
3256
3257 /* disable the queue */
a74420e0 3258 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3259 wrfl();
3260 mdelay(10);
3261
3262 wr32(E1000_TDLEN(reg_idx),
b980ac18 3263 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3264 wr32(E1000_TDBAL(reg_idx),
b980ac18 3265 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3266 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3267
fce99e34 3268 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3269 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3270 writel(0, ring->tail);
85b430b4
AD		 3271
3272 txdctl |= IGB_TX_PTHRESH;
3273 txdctl |= IGB_TX_HTHRESH << 8;
3274 txdctl |= IGB_TX_WTHRESH << 16;
3275
3276 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3277 wr32(E1000_TXDCTL(reg_idx), txdctl);
3278}
3279
3280/**
b980ac18
JK		 3281 * igb_configure_tx - Configure transmit Unit after Reset
3282 * @adapter: board private structure
85b430b4 3283 *
b980ac18 3284 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3285 **/
3286static void igb_configure_tx(struct igb_adapter *adapter)
3287{
3288 int i;
3289
3290 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3291 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3292}
3293
9d5c8243 3294/**
b980ac18
JK		 3295 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3296 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3297 *
b980ac18 3298 * Returns 0 on success, negative on failure
9d5c8243 3299 **/
80785298 3300int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3301{
59d71989 3302 struct device *dev = rx_ring->dev;
f33005a6 3303 int size;
9d5c8243 3304
06034649 3305 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3306
3307 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3308 if (!rx_ring->rx_buffer_info)
9d5c8243 3309 goto err;
9d5c8243 3310
9d5c8243 3311 /* Round up to nearest 4K */
f33005a6 3312 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3313 rx_ring->size = ALIGN(rx_ring->size, 4096);
3314
5536d210
AD		 3315 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3316 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3317 if (!rx_ring->desc)
3318 goto err;
3319
cbc8e55f 3320 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3321 rx_ring->next_to_clean = 0;
3322 rx_ring->next_to_use = 0;
9d5c8243 3323
9d5c8243
AK		 3324 return 0;
3325
3326err:
06034649
AD		 3327 vfree(rx_ring->rx_buffer_info);
3328 rx_ring->rx_buffer_info = NULL;
f33005a6 3329 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3330 return -ENOMEM;
3331}
3332
3333/**
b980ac18
JK		 3334 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3335 * (Descriptors) for all queues
3336 * @adapter: board private structure
9d5c8243 3337 *
b980ac18 3338 * Return 0 on success, negative on failure
9d5c8243
AK		 3339 **/
3340static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3341{
439705e1 3342 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3343 int i, err = 0;
3344
3345 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3346 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3347 if (err) {
439705e1 3348 dev_err(&pdev->dev,
9d5c8243
AK		 3349 "Allocation for Rx Queue %u failed\n", i);
3350 for (i--; i >= 0; i--)
3025a446 3351 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3352 break;
3353 }
3354 }
3355
3356 return err;
3357}
3358
06cf2666 3359/**
b980ac18
JK		 3360 * igb_setup_mrqc - configure the multiple receive queue control registers
3361 * @adapter: Board private structure
06cf2666
AD		 3362 **/
3363static void igb_setup_mrqc(struct igb_adapter *adapter)
3364{
3365 struct e1000_hw *hw = &adapter->hw;
3366 u32 mrqc, rxcsum;
ed12cc9a 3367 u32 j, num_rx_queues;
a57fe23e
AD		 3368 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3369 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3370 0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3371 0xFA01ACBE };
06cf2666
AD		 3372
3373 /* Fill out hash function seeds */
a57fe23e
AD		 3374 for (j = 0; j < 10; j++)
3375 wr32(E1000_RSSRK(j), rsskey[j]);
06cf2666 3376
a99955fc 3377 num_rx_queues = adapter->rss_queues;
06cf2666 3378
797fd4be 3379 switch (hw->mac.type) {
797fd4be
AD		 3380 case e1000_82576:
3381 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3382 if (adapter->vfs_allocated_count)
06cf2666 3383 num_rx_queues = 2;
797fd4be
AD		 3384 break;
3385 default:
3386 break;
06cf2666
AD		 3387 }
3388
ed12cc9a
LMV		 3389 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3390 for (j = 0; j < IGB_RETA_SIZE; j++)
3391 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE;
3392 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3393 }
ed12cc9a 3394 igb_write_rss_indir_tbl(adapter);
06cf2666 3395
b980ac18 3396 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3397 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3398 * offloads as they are enabled by default
3399 */
3400 rxcsum = rd32(E1000_RXCSUM);
3401 rxcsum |= E1000_RXCSUM_PCSD;
3402
3403 if (adapter->hw.mac.type >= e1000_82576)
3404 /* Enable Receive Checksum Offload for SCTP */
3405 rxcsum |= E1000_RXCSUM_CRCOFL;
3406
3407 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3408 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3409
039454a8
AA		 3410 /* Generate RSS hash based on packet types, TCP/UDP
3411 * port numbers and/or IPv4/v6 src and dst addresses
3412 */
f96a8a0b
CW		 3413 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3414 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3415 E1000_MRQC_RSS_FIELD_IPV6 |
3416 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3417 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3418
039454a8
AA		 3419 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3420 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3421 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3422 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3423
06cf2666
AD		 3424 /* If VMDq is enabled then we set the appropriate mode for that, else
3425 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3426 * if we are only using one queue
3427 */
06cf2666
AD		 3428 if (adapter->vfs_allocated_count) {
3429 if (hw->mac.type > e1000_82575) {
3430 /* Set the default pool for the PF's first queue */
3431 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3432
06cf2666
AD		 3433 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3434 E1000_VT_CTL_DISABLE_DEF_POOL);
3435 vtctl |= adapter->vfs_allocated_count <<
3436 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3437 wr32(E1000_VT_CTL, vtctl);
3438 }
a99955fc 3439 if (adapter->rss_queues > 1)
f96a8a0b 3440 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3441 else
f96a8a0b 3442 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3443 } else {
f96a8a0b
CW		 3444 if (hw->mac.type != e1000_i211)
3445 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3446 }
3447 igb_vmm_control(adapter);
3448
06cf2666
AD		 3449 wr32(E1000_MRQC, mrqc);
3450}
3451
9d5c8243 3452/**
b980ac18
JK		 3453 * igb_setup_rctl - configure the receive control registers
3454 * @adapter: Board private structure
9d5c8243 3455 **/
d7ee5b3a 3456void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3457{
3458 struct e1000_hw *hw = &adapter->hw;
3459 u32 rctl;
9d5c8243
AK		 3460
3461 rctl = rd32(E1000_RCTL);
3462
3463 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3464 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3465
69d728ba 3466 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3467 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3468
b980ac18 3469 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3470 * redirection as it did with e1000. Newer features require
3471 * that the HW strips the CRC.
73cd78f1 3472 */
87cb7e8c 3473 rctl |= E1000_RCTL_SECRC;
9d5c8243 3474
559e9c49 3475 /* disable store bad packets and clear size bits. */
ec54d7d6 3476 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3477
6ec43fe6
AD		 3478 /* enable LPE to prevent packets larger than max_frame_size */
3479 rctl |= E1000_RCTL_LPE;
9d5c8243 3480
952f72a8
AD		 3481 /* disable queue 0 to prevent tail write w/o re-config */
3482 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3483
e1739522
AD		 3484 /* Attention!!! For SR-IOV PF driver operations you must enable
3485 * queue drop for all VF and PF queues to prevent head of line blocking
3486 * if an un-trusted VF does not provide descriptors to hardware.
3487 */
3488 if (adapter->vfs_allocated_count) {
e1739522
AD		 3489 /* set all queue drop enable bits */
3490 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3491 }
3492
89eaefb6
BG		 3493 /* This is useful for sniffing bad packets. */
3494 if (adapter->netdev->features & NETIF_F_RXALL) {
3495 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3496 * in e1000e_set_rx_mode
3497 */
89eaefb6
BG		 3498 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3499 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3500 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3501
3502 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3503 E1000_RCTL_DPF | /* Allow filtered pause */
3504 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3505 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3506 * and that breaks VLANs.
3507 */
3508 }
3509
9d5c8243
AK		 3510 wr32(E1000_RCTL, rctl);
3511}
3512
7d5753f0 3513static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3514 int vfn)
7d5753f0
AD		 3515{
3516 struct e1000_hw *hw = &adapter->hw;
3517 u32 vmolr;
3518
3519 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3520 * increase the size to support vlan tags
3521 */
7d5753f0
AD		 3522 if (vfn < adapter->vfs_allocated_count &&
3523 adapter->vf_data[vfn].vlans_enabled)
3524 size += VLAN_TAG_SIZE;
3525
3526 vmolr = rd32(E1000_VMOLR(vfn));
3527 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3528 vmolr |= size | E1000_VMOLR_LPE;
3529 wr32(E1000_VMOLR(vfn), vmolr);
3530
3531 return 0;
3532}
3533
e1739522 3534/**
b980ac18
JK		 3535 * igb_rlpml_set - set maximum receive packet size
3536 * @adapter: board private structure
e1739522 3537 *
b980ac18 3538 * Configure maximum receivable packet size.
e1739522
AD		 3539 **/
3540static void igb_rlpml_set(struct igb_adapter *adapter)
3541{
153285f9 3542 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3543 struct e1000_hw *hw = &adapter->hw;
3544 u16 pf_id = adapter->vfs_allocated_count;
3545
e1739522
AD		 3546 if (pf_id) {
3547 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3548 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3549 * to our max jumbo frame size, in case we need to enable
3550 * jumbo frames on one of the rings later.
3551 * This will not pass over-length frames into the default
3552 * queue because it's gated by the VMOLR.RLPML.
3553 */
7d5753f0 3554 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3555 }
3556
3557 wr32(E1000_RLPML, max_frame_size);
3558}
3559
8151d294
WM		 3560static inline void igb_set_vmolr(struct igb_adapter *adapter,
3561 int vfn, bool aupe)
7d5753f0
AD		 3562{
3563 struct e1000_hw *hw = &adapter->hw;
3564 u32 vmolr;
3565
b980ac18 3566 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3567 * we should exit and do nothing
3568 */
3569 if (hw->mac.type < e1000_82576)
3570 return;
3571
3572 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3573 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3574 if (hw->mac.type == e1000_i350) {
3575 u32 dvmolr;
3576
3577 dvmolr = rd32(E1000_DVMOLR(vfn));
3578 dvmolr |= E1000_DVMOLR_STRVLAN;
3579 wr32(E1000_DVMOLR(vfn), dvmolr);
3580 }
8151d294 3581 if (aupe)
b980ac18 3582 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3583 else
3584 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3585
3586 /* clear all bits that might not be set */
3587 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3588
a99955fc 3589 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3590 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3591 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3592 * multicast packets
3593 */
3594 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3595 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3596
3597 wr32(E1000_VMOLR(vfn), vmolr);
3598}
3599
85b430b4 3600/**
b980ac18
JK		 3601 * igb_configure_rx_ring - Configure a receive ring after Reset
3602 * @adapter: board private structure
3603 * @ring: receive ring to be configured
85b430b4 3604 *
b980ac18 3605 * Configure the Rx unit of the MAC after a reset.
85b430b4 3606 **/
d7ee5b3a 3607void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3608 struct igb_ring *ring)
85b430b4
AD		 3609{
3610 struct e1000_hw *hw = &adapter->hw;
3611 u64 rdba = ring->dma;
3612 int reg_idx = ring->reg_idx;
a74420e0 3613 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3614
3615 /* disable the queue */
a74420e0 3616 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3617
3618 /* Set DMA base address registers */
3619 wr32(E1000_RDBAL(reg_idx),
3620 rdba & 0x00000000ffffffffULL);
3621 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3622 wr32(E1000_RDLEN(reg_idx),
b980ac18 3623 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3624
3625 /* initialize head and tail */
fce99e34 3626 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3627 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3628 writel(0, ring->tail);
85b430b4 3629
952f72a8 3630 /* set descriptor configuration */
44390ca6 3631 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3632 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3633 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3634 if (hw->mac.type >= e1000_82580)
757b77e2 3635 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3636 /* Only set Drop Enable if we are supporting multiple queues */
3637 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3638 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3639
3640 wr32(E1000_SRRCTL(reg_idx), srrctl);
3641
7d5753f0 3642 /* set filtering for VMDQ pools */
8151d294 3643 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3644
85b430b4
AD		 3645 rxdctl |= IGB_RX_PTHRESH;
3646 rxdctl |= IGB_RX_HTHRESH << 8;
3647 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3648
3649 /* enable receive descriptor fetching */
3650 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3651 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3652}
3653
9d5c8243 3654/**
b980ac18
JK		 3655 * igb_configure_rx - Configure receive Unit after Reset
3656 * @adapter: board private structure
9d5c8243 3657 *
b980ac18 3658 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3659 **/
3660static void igb_configure_rx(struct igb_adapter *adapter)
3661{
9107584e 3662 int i;
9d5c8243 3663
68d480c4
AD		 3664 /* set UTA to appropriate mode */
3665 igb_set_uta(adapter);
3666
26ad9178
AD		 3667 /* set the correct pool for the PF default MAC address in entry 0 */
3668 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3669 adapter->vfs_allocated_count);
26ad9178 3670
06cf2666 3671 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3672 * the Base and Length of the Rx Descriptor Ring
3673 */
f9d40f6a
AD		 3674 for (i = 0; i < adapter->num_rx_queues; i++)
3675 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3676}
3677
3678/**
b980ac18
JK		 3679 * igb_free_tx_resources - Free Tx Resources per Queue
3680 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3681 *
b980ac18 3682 * Free all transmit software resources
9d5c8243 3683 **/
68fd9910 3684void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3685{
3b644cf6 3686 igb_clean_tx_ring(tx_ring);
9d5c8243 3687
06034649
AD		 3688 vfree(tx_ring->tx_buffer_info);
3689 tx_ring->tx_buffer_info = NULL;
9d5c8243 3690
439705e1
AD		 3691 /* if not set, then don't free */
3692 if (!tx_ring->desc)
3693 return;
3694
59d71989
AD		 3695 dma_free_coherent(tx_ring->dev, tx_ring->size,
3696 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3697
3698 tx_ring->desc = NULL;
3699}
3700
3701/**
b980ac18
JK		 3702 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3703 * @adapter: board private structure
9d5c8243 3704 *
b980ac18 3705 * Free all transmit software resources
9d5c8243
AK		 3706 **/
3707static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3708{
3709 int i;
3710
3711 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3712 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3713}
3714
ebe42d16
AD		 3715void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3716 struct igb_tx_buffer *tx_buffer)
3717{
3718 if (tx_buffer->skb) {
3719 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3720 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3721 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3722 dma_unmap_addr(tx_buffer, dma),
3723 dma_unmap_len(tx_buffer, len),
ebe42d16 3724 DMA_TO_DEVICE);
c9f14bf3 3725 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3726 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3727 dma_unmap_addr(tx_buffer, dma),
3728 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3729 DMA_TO_DEVICE);
3730 }
3731 tx_buffer->next_to_watch = NULL;
3732 tx_buffer->skb = NULL;
c9f14bf3 3733 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3734 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3735}
3736
3737/**
b980ac18
JK		 3738 * igb_clean_tx_ring - Free Tx Buffers
3739 * @tx_ring: ring to be cleaned
9d5c8243 3740 **/
3b644cf6 3741static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3742{
06034649 3743 struct igb_tx_buffer *buffer_info;
9d5c8243 3744 unsigned long size;
6ad4edfc 3745 u16 i;
9d5c8243 3746
06034649 3747 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3748 return;
3749 /* Free all the Tx ring sk_buffs */
3750
3751 for (i = 0; i < tx_ring->count; i++) {
06034649 3752 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3753 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3754 }
3755
dad8a3b3
JF		 3756 netdev_tx_reset_queue(txring_txq(tx_ring));
3757
06034649
AD		 3758 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3759 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3760
3761 /* Zero out the descriptor ring */
9d5c8243
AK		 3762 memset(tx_ring->desc, 0, tx_ring->size);
3763
3764 tx_ring->next_to_use = 0;
3765 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3766}
3767
3768/**
b980ac18
JK		 3769 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3770 * @adapter: board private structure
9d5c8243
AK		 3771 **/
3772static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3773{
3774 int i;
3775
3776 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3777 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3778}
3779
3780/**
b980ac18
JK		 3781 * igb_free_rx_resources - Free Rx Resources
3782 * @rx_ring: ring to clean the resources from
9d5c8243 3783 *
b980ac18 3784 * Free all receive software resources
9d5c8243 3785 **/
68fd9910 3786void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3787{
3b644cf6 3788 igb_clean_rx_ring(rx_ring);
9d5c8243 3789
06034649
AD		 3790 vfree(rx_ring->rx_buffer_info);
3791 rx_ring->rx_buffer_info = NULL;
9d5c8243 3792
439705e1
AD		 3793 /* if not set, then don't free */
3794 if (!rx_ring->desc)
3795 return;
3796
59d71989
AD		 3797 dma_free_coherent(rx_ring->dev, rx_ring->size,
3798 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3799
3800 rx_ring->desc = NULL;
3801}
3802
3803/**
b980ac18
JK		 3804 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3805 * @adapter: board private structure
9d5c8243 3806 *
b980ac18 3807 * Free all receive software resources
9d5c8243
AK		 3808 **/
3809static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3810{
3811 int i;
3812
3813 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3814 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3815}
3816
3817/**
b980ac18
JK		 3818 * igb_clean_rx_ring - Free Rx Buffers per Queue
3819 * @rx_ring: ring to free buffers from
9d5c8243 3820 **/
3b644cf6 3821static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3822{
9d5c8243 3823 unsigned long size;
c023cd88 3824 u16 i;
9d5c8243 3825
1a1c225b
AD		 3826 if (rx_ring->skb)
3827 dev_kfree_skb(rx_ring->skb);
3828 rx_ring->skb = NULL;
3829
06034649 3830 if (!rx_ring->rx_buffer_info)
9d5c8243 3831 return;
439705e1 3832
9d5c8243
AK		 3833 /* Free all the Rx ring sk_buffs */
3834 for (i = 0; i < rx_ring->count; i++) {
06034649 3835 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3836
cbc8e55f
AD		 3837 if (!buffer_info->page)
3838 continue;
3839
3840 dma_unmap_page(rx_ring->dev,
3841 buffer_info->dma,
3842 PAGE_SIZE,
3843 DMA_FROM_DEVICE);
3844 __free_page(buffer_info->page);
3845
1a1c225b 3846 buffer_info->page = NULL;
9d5c8243
AK		 3847 }
3848
06034649
AD		 3849 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3850 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3851
3852 /* Zero out the descriptor ring */
3853 memset(rx_ring->desc, 0, rx_ring->size);
3854
cbc8e55f 3855 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3856 rx_ring->next_to_clean = 0;
3857 rx_ring->next_to_use = 0;
9d5c8243
AK		 3858}
3859
3860/**
b980ac18
JK		 3861 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3862 * @adapter: board private structure
9d5c8243
AK		 3863 **/
3864static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3865{
3866 int i;
3867
3868 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 3869 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3870}
3871
3872/**
b980ac18
JK		 3873 * igb_set_mac - Change the Ethernet Address of the NIC
3874 * @netdev: network interface device structure
3875 * @p: pointer to an address structure
9d5c8243 3876 *
b980ac18 3877 * Returns 0 on success, negative on failure
9d5c8243
AK		 3878 **/
3879static int igb_set_mac(struct net_device *netdev, void *p)
3880{
3881 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3882 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3883 struct sockaddr *addr = p;
3884
3885 if (!is_valid_ether_addr(addr->sa_data))
3886 return -EADDRNOTAVAIL;
3887
3888 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3889 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3890
26ad9178
AD		 3891 /* set the correct pool for the new PF MAC address in entry 0 */
3892 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3893 adapter->vfs_allocated_count);
e1739522 3894
9d5c8243
AK		 3895 return 0;
3896}
3897
3898/**
b980ac18
JK		 3899 * igb_write_mc_addr_list - write multicast addresses to MTA
3900 * @netdev: network interface device structure
9d5c8243 3901 *
b980ac18
JK		 3902 * Writes multicast address list to the MTA hash table.
3903 * Returns: -ENOMEM on failure
3904 * 0 on no addresses written
3905 * X on writing X addresses to MTA
9d5c8243 3906 **/
68d480c4 3907static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3908{
3909 struct igb_adapter *adapter = netdev_priv(netdev);
3910 struct e1000_hw *hw = &adapter->hw;
22bedad3 3911 struct netdev_hw_addr *ha;
68d480c4 3912 u8 *mta_list;
9d5c8243
AK		 3913 int i;
3914
4cd24eaf 3915 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3916 /* nothing to program, so clear mc list */
3917 igb_update_mc_addr_list(hw, NULL, 0);
3918 igb_restore_vf_multicasts(adapter);
3919 return 0;
3920 }
9d5c8243 3921
4cd24eaf 3922 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3923 if (!mta_list)
3924 return -ENOMEM;
ff41f8dc 3925
68d480c4 3926 /* The shared function expects a packed array of only addresses. */
48e2f183 3927 i = 0;
22bedad3
JP		 3928 netdev_for_each_mc_addr(ha, netdev)
3929 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3930
68d480c4
AD		 3931 igb_update_mc_addr_list(hw, mta_list, i);
3932 kfree(mta_list);
3933
4cd24eaf 3934 return netdev_mc_count(netdev);
68d480c4
AD		 3935}
3936
3937/**
b980ac18
JK		 3938 * igb_write_uc_addr_list - write unicast addresses to RAR table
3939 * @netdev: network interface device structure
68d480c4 3940 *
b980ac18
JK		 3941 * Writes unicast address list to the RAR table.
3942 * Returns: -ENOMEM on failure/insufficient address space
3943 * 0 on no addresses written
3944 * X on writing X addresses to the RAR table
68d480c4
AD		 3945 **/
3946static int igb_write_uc_addr_list(struct net_device *netdev)
3947{
3948 struct igb_adapter *adapter = netdev_priv(netdev);
3949 struct e1000_hw *hw = &adapter->hw;
3950 unsigned int vfn = adapter->vfs_allocated_count;
3951 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3952 int count = 0;
3953
3954 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3955 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3956 return -ENOMEM;
9d5c8243 3957
32e7bfc4 3958 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3959 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3960
3961 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3962 if (!rar_entries)
3963 break;
26ad9178 3964 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3965 rar_entries--,
3966 vfn);
68d480c4 3967 count++;
ff41f8dc
AD		 3968 }
3969 }
3970 /* write the addresses in reverse order to avoid write combining */
3971 for (; rar_entries > 0 ; rar_entries--) {
3972 wr32(E1000_RAH(rar_entries), 0);
3973 wr32(E1000_RAL(rar_entries), 0);
3974 }
3975 wrfl();
3976
68d480c4
AD		 3977 return count;
3978}
3979
3980/**
b980ac18
JK		 3981 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3982 * @netdev: network interface device structure
68d480c4 3983 *
b980ac18
JK		 3984 * The set_rx_mode entry point is called whenever the unicast or multicast
3985 * address lists or the network interface flags are updated. This routine is
3986 * responsible for configuring the hardware for proper unicast, multicast,
3987 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 3988 **/
3989static void igb_set_rx_mode(struct net_device *netdev)
3990{
3991 struct igb_adapter *adapter = netdev_priv(netdev);
3992 struct e1000_hw *hw = &adapter->hw;
3993 unsigned int vfn = adapter->vfs_allocated_count;
3994 u32 rctl, vmolr = 0;
3995 int count;
3996
3997 /* Check for Promiscuous and All Multicast modes */
3998 rctl = rd32(E1000_RCTL);
3999
4000 /* clear the effected bits */
4001 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4002
4003 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4004 /* retain VLAN HW filtering if in VT mode */
7e44892c 4005 if (adapter->vfs_allocated_count)
6f3dc319 4006 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4007 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4008 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4009 } else {
4010 if (netdev->flags & IFF_ALLMULTI) {
4011 rctl |= E1000_RCTL_MPE;
4012 vmolr |= E1000_VMOLR_MPME;
4013 } else {
b980ac18 4014 /* Write addresses to the MTA, if the attempt fails
25985edc 4015 * then we should just turn on promiscuous mode so
68d480c4
AD		 4016 * that we can at least receive multicast traffic
4017 */
4018 count = igb_write_mc_addr_list(netdev);
4019 if (count < 0) {
4020 rctl |= E1000_RCTL_MPE;
4021 vmolr |= E1000_VMOLR_MPME;
4022 } else if (count) {
4023 vmolr |= E1000_VMOLR_ROMPE;
4024 }
4025 }
b980ac18 4026 /* Write addresses to available RAR registers, if there is not
68d480c4 4027 * sufficient space to store all the addresses then enable
25985edc 4028 * unicast promiscuous mode
68d480c4
AD		 4029 */
4030 count = igb_write_uc_addr_list(netdev);
4031 if (count < 0) {
4032 rctl |= E1000_RCTL_UPE;
4033 vmolr |= E1000_VMOLR_ROPE;
4034 }
4035 rctl |= E1000_RCTL_VFE;
28fc06f5 4036 }
68d480c4 4037 wr32(E1000_RCTL, rctl);
28fc06f5 4038
b980ac18 4039 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4040 * the VMOLR to enable the appropriate modes. Without this workaround
4041 * we will have issues with VLAN tag stripping not being done for frames
4042 * that are only arriving because we are the default pool
4043 */
f96a8a0b 4044 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4045 return;
9d5c8243 4046
68d480c4 4047 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4048 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4049 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4050 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4051}
4052
13800469
GR		 4053static void igb_check_wvbr(struct igb_adapter *adapter)
4054{
4055 struct e1000_hw *hw = &adapter->hw;
4056 u32 wvbr = 0;
4057
4058 switch (hw->mac.type) {
4059 case e1000_82576:
4060 case e1000_i350:
81ad807b
CW		 4061 wvbr = rd32(E1000_WVBR);
4062 if (!wvbr)
13800469
GR		 4063 return;
4064 break;
4065 default:
4066 break;
4067 }
4068
4069 adapter->wvbr |= wvbr;
4070}
4071
4072#define IGB_STAGGERED_QUEUE_OFFSET 8
4073
4074static void igb_spoof_check(struct igb_adapter *adapter)
4075{
4076 int j;
4077
4078 if (!adapter->wvbr)
4079 return;
4080
9005df38 4081 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4082 if (adapter->wvbr & (1 << j) ||
4083 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4084 dev_warn(&adapter->pdev->dev,
4085 "Spoof event(s) detected on VF %d\n", j);
4086 adapter->wvbr &=
4087 ~((1 << j) |
4088 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4089 }
4090 }
4091}
4092
9d5c8243 4093/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4094 * the phy
4095 */
9d5c8243
AK		 4096static void igb_update_phy_info(unsigned long data)
4097{
4098 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4099 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4100}
4101
4d6b725e 4102/**
b980ac18
JK		 4103 * igb_has_link - check shared code for link and determine up/down
4104 * @adapter: pointer to driver private info
4d6b725e 4105 **/
3145535a 4106bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4107{
4108 struct e1000_hw *hw = &adapter->hw;
4109 bool link_active = false;
4d6b725e
AD		 4110
4111 /* get_link_status is set on LSC (link status) interrupt or
4112 * rx sequence error interrupt. get_link_status will stay
4113 * false until the e1000_check_for_link establishes link
4114 * for copper adapters ONLY
4115 */
4116 switch (hw->phy.media_type) {
4117 case e1000_media_type_copper:
e5c3370f
AA		 4118 if (!hw->mac.get_link_status)
4119 return true;
4d6b725e 4120 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4121 hw->mac.ops.check_for_link(hw);
4122 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4123 break;
4124 default:
4125 case e1000_media_type_unknown:
4126 break;
4127 }
4128
aa9b8cc4
AA		 4129 if (((hw->mac.type == e1000_i210) ||
4130 (hw->mac.type == e1000_i211)) &&
4131 (hw->phy.id == I210_I_PHY_ID)) {
4132 if (!netif_carrier_ok(adapter->netdev)) {
4133 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4134 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4135 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4136 adapter->link_check_timeout = jiffies;
4137 }
4138 }
4139
4d6b725e
AD		 4140 return link_active;
4141}
4142
563988dc
SA		 4143static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4144{
4145 bool ret = false;
4146 u32 ctrl_ext, thstat;
4147
f96a8a0b 4148 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4149 if (hw->mac.type == e1000_i350) {
4150 thstat = rd32(E1000_THSTAT);
4151 ctrl_ext = rd32(E1000_CTRL_EXT);
4152
4153 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4154 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4155 ret = !!(thstat & event);
563988dc
SA		 4156 }
4157
4158 return ret;
4159}
4160
9d5c8243 4161/**
b980ac18
JK		 4162 * igb_watchdog - Timer Call-back
4163 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4164 **/
4165static void igb_watchdog(unsigned long data)
4166{
4167 struct igb_adapter *adapter = (struct igb_adapter *)data;
4168 /* Do the rest outside of interrupt context */
4169 schedule_work(&adapter->watchdog_task);
4170}
4171
4172static void igb_watchdog_task(struct work_struct *work)
4173{
4174 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4175 struct igb_adapter,
4176 watchdog_task);
9d5c8243 4177 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4178 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4179 struct net_device *netdev = adapter->netdev;
563988dc 4180 u32 link;
7a6ea550 4181 int i;
56cec249 4182 u32 connsw;
9d5c8243 4183
4d6b725e 4184 link = igb_has_link(adapter);
aa9b8cc4
AA		 4185
4186 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4187 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4188 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4189 else
4190 link = false;
4191 }
4192
56cec249
CW		 4193 /* Force link down if we have fiber to swap to */
4194 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4195 if (hw->phy.media_type == e1000_media_type_copper) {
4196 connsw = rd32(E1000_CONNSW);
4197 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4198 link = 0;
4199 }
4200 }
9d5c8243 4201 if (link) {
2bdfc4e2
CW		 4202 /* Perform a reset if the media type changed. */
4203 if (hw->dev_spec._82575.media_changed) {
4204 hw->dev_spec._82575.media_changed = false;
4205 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4206 igb_reset(adapter);
4207 }
749ab2cd
YZ		 4208 /* Cancel scheduled suspend requests. */
4209 pm_runtime_resume(netdev->dev.parent);
4210
9d5c8243
AK		 4211 if (!netif_carrier_ok(netdev)) {
4212 u32 ctrl;
9005df38 4213
330a6d6a 4214 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4215 &adapter->link_speed,
4216 &adapter->link_duplex);
9d5c8243
AK		 4217
4218 ctrl = rd32(E1000_CTRL);
527d47c1 4219 /* Links status message must follow this format */
c75c4edf
CW		 4220 netdev_info(netdev,
4221 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4222 netdev->name,
4223 adapter->link_speed,
4224 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4225 "Full" : "Half",
4226 (ctrl & E1000_CTRL_TFCE) &&
4227 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4228 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4229 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4230
f4c01e96
CW		 4231 /* disable EEE if enabled */
4232 if ((adapter->flags & IGB_FLAG_EEE) &&
4233 (adapter->link_duplex == HALF_DUPLEX)) {
4234 dev_info(&adapter->pdev->dev,
4235 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4236 adapter->hw.dev_spec._82575.eee_disable = true;
4237 adapter->flags &= ~IGB_FLAG_EEE;
4238 }
4239
c0ba4778
KS		 4240 /* check if SmartSpeed worked */
4241 igb_check_downshift(hw);
4242 if (phy->speed_downgraded)
4243 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4244
563988dc 4245 /* check for thermal sensor event */
876d2d6f 4246 if (igb_thermal_sensor_event(hw,
d34a15ab 4247 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4248 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4249
d07f3e37 4250 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4251 adapter->tx_timeout_factor = 1;
4252 switch (adapter->link_speed) {
4253 case SPEED_10:
9d5c8243
AK		 4254 adapter->tx_timeout_factor = 14;
4255 break;
4256 case SPEED_100:
9d5c8243
AK		 4257 /* maybe add some timeout factor ? */
4258 break;
4259 }
4260
4261 netif_carrier_on(netdev);
9d5c8243 4262
4ae196df 4263 igb_ping_all_vfs(adapter);
17dc566c 4264 igb_check_vf_rate_limit(adapter);
4ae196df 4265
4b1a9877 4266 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4267 if (!test_bit(__IGB_DOWN, &adapter->state))
4268 mod_timer(&adapter->phy_info_timer,
4269 round_jiffies(jiffies + 2 * HZ));
4270 }
4271 } else {
4272 if (netif_carrier_ok(netdev)) {
4273 adapter->link_speed = 0;
4274 adapter->link_duplex = 0;
563988dc
SA		 4275
4276 /* check for thermal sensor event */
876d2d6f
JK		 4277 if (igb_thermal_sensor_event(hw,
4278 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4279 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4280 }
563988dc 4281
527d47c1 4282 /* Links status message must follow this format */
c75c4edf 4283 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4284 netdev->name);
9d5c8243 4285 netif_carrier_off(netdev);
4b1a9877 4286
4ae196df
AD		 4287 igb_ping_all_vfs(adapter);
4288
4b1a9877 4289 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4290 if (!test_bit(__IGB_DOWN, &adapter->state))
4291 mod_timer(&adapter->phy_info_timer,
4292 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4293
56cec249
CW		 4294 /* link is down, time to check for alternate media */
4295 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4296 igb_check_swap_media(adapter);
4297 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4298 schedule_work(&adapter->reset_task);
4299 /* return immediately */
4300 return;
4301 }
4302 }
749ab2cd
YZ		 4303 pm_schedule_suspend(netdev->dev.parent,
4304 MSEC_PER_SEC * 5);
56cec249
CW		 4305
4306 /* also check for alternate media here */
4307 } else if (!netif_carrier_ok(netdev) &&
4308 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4309 igb_check_swap_media(adapter);
4310 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4311 schedule_work(&adapter->reset_task);
4312 /* return immediately */
4313 return;
4314 }
9d5c8243
AK		 4315 }
4316 }
4317
12dcd86b
ED		 4318 spin_lock(&adapter->stats64_lock);
4319 igb_update_stats(adapter, &adapter->stats64);
4320 spin_unlock(&adapter->stats64_lock);
9d5c8243 4321
dbabb065 4322 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4323 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4324 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4325 /* We've lost link, so the controller stops DMA,
4326 * but we've got queued Tx work that's never going
4327 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4328 * (Do the reset outside of interrupt context).
4329 */
dbabb065
AD		 4330 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4331 adapter->tx_timeout_count++;
4332 schedule_work(&adapter->reset_task);
4333 /* return immediately since reset is imminent */
4334 return;
4335 }
9d5c8243 4336 }
9d5c8243 4337
dbabb065 4338 /* Force detection of hung controller every watchdog period */
6d095fa8 4339 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4340 }
f7ba205e 4341
b980ac18 4342 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4343 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4344 u32 eics = 0;
9005df38 4345
0d1ae7f4
AD		 4346 for (i = 0; i < adapter->num_q_vectors; i++)
4347 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4348 wr32(E1000_EICS, eics);
4349 } else {
4350 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4351 }
9d5c8243 4352
13800469 4353 igb_spoof_check(adapter);
fc580751 4354 igb_ptp_rx_hang(adapter);
13800469 4355
9d5c8243 4356 /* Reset the timer */
aa9b8cc4
AA		 4357 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4358 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4359 mod_timer(&adapter->watchdog_timer,
4360 round_jiffies(jiffies + HZ));
4361 else
4362 mod_timer(&adapter->watchdog_timer,
4363 round_jiffies(jiffies + 2 * HZ));
4364 }
9d5c8243
AK		 4365}
4366
4367enum latency_range {
4368 lowest_latency = 0,
4369 low_latency = 1,
4370 bulk_latency = 2,
4371 latency_invalid = 255
4372};
4373
6eb5a7f1 4374/**
b980ac18
JK		 4375 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4376 * @q_vector: pointer to q_vector
6eb5a7f1 4377 *
b980ac18
JK		 4378 * Stores a new ITR value based on strictly on packet size. This
4379 * algorithm is less sophisticated than that used in igb_update_itr,
4380 * due to the difficulty of synchronizing statistics across multiple
4381 * receive rings. The divisors and thresholds used by this function
4382 * were determined based on theoretical maximum wire speed and testing
4383 * data, in order to minimize response time while increasing bulk
4384 * throughput.
406d4965 4385 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4386 * NOTE: This function is called only when operating in a multiqueue
4387 * receive environment.
6eb5a7f1 4388 **/
047e0030 4389static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4390{
047e0030 4391 int new_val = q_vector->itr_val;
6eb5a7f1 4392 int avg_wire_size = 0;
047e0030 4393 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4394 unsigned int packets;
9d5c8243 4395
6eb5a7f1
AD		 4396 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4397 * ints/sec - ITR timer value of 120 ticks.
4398 */
4399 if (adapter->link_speed != SPEED_1000) {
0ba82994 4400 new_val = IGB_4K_ITR;
6eb5a7f1 4401 goto set_itr_val;
9d5c8243 4402 }
047e0030 4403
0ba82994
AD		 4404 packets = q_vector->rx.total_packets;
4405 if (packets)
4406 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4407
0ba82994
AD		 4408 packets = q_vector->tx.total_packets;
4409 if (packets)
4410 avg_wire_size = max_t(u32, avg_wire_size,
4411 q_vector->tx.total_bytes / packets);
047e0030
AD		 4412
4413 /* if avg_wire_size isn't set no work was done */
4414 if (!avg_wire_size)
4415 goto clear_counts;
9d5c8243 4416
6eb5a7f1
AD		 4417 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4418 avg_wire_size += 24;
4419
4420 /* Don't starve jumbo frames */
4421 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4422
6eb5a7f1
AD		 4423 /* Give a little boost to mid-size frames */
4424 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4425 new_val = avg_wire_size / 3;
4426 else
4427 new_val = avg_wire_size / 2;
9d5c8243 4428
0ba82994
AD		 4429 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4430 if (new_val < IGB_20K_ITR &&
4431 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4432 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4433 new_val = IGB_20K_ITR;
abe1c363 4434
6eb5a7f1 4435set_itr_val:
047e0030
AD		 4436 if (new_val != q_vector->itr_val) {
4437 q_vector->itr_val = new_val;
4438 q_vector->set_itr = 1;
9d5c8243 4439 }
6eb5a7f1 4440clear_counts:
0ba82994
AD		 4441 q_vector->rx.total_bytes = 0;
4442 q_vector->rx.total_packets = 0;
4443 q_vector->tx.total_bytes = 0;
4444 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4445}
4446
4447/**
b980ac18
JK		 4448 * igb_update_itr - update the dynamic ITR value based on statistics
4449 * @q_vector: pointer to q_vector
4450 * @ring_container: ring info to update the itr for
4451 *
4452 * Stores a new ITR value based on packets and byte
4453 * counts during the last interrupt. The advantage of per interrupt
4454 * computation is faster updates and more accurate ITR for the current
4455 * traffic pattern. Constants in this function were computed
4456 * based on theoretical maximum wire speed and thresholds were set based
4457 * on testing data as well as attempting to minimize response time
4458 * while increasing bulk throughput.
406d4965 4459 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4460 * NOTE: These calculations are only valid when operating in a single-
4461 * queue environment.
9d5c8243 4462 **/
0ba82994
AD		 4463static void igb_update_itr(struct igb_q_vector *q_vector,
4464 struct igb_ring_container *ring_container)
9d5c8243 4465{
0ba82994
AD		 4466 unsigned int packets = ring_container->total_packets;
4467 unsigned int bytes = ring_container->total_bytes;
4468 u8 itrval = ring_container->itr;
9d5c8243 4469
0ba82994 4470 /* no packets, exit with status unchanged */
9d5c8243 4471 if (packets == 0)
0ba82994 4472 return;
9d5c8243 4473
0ba82994 4474 switch (itrval) {
9d5c8243
AK		 4475 case lowest_latency:
4476 /* handle TSO and jumbo frames */
4477 if (bytes/packets > 8000)
0ba82994 4478 itrval = bulk_latency;
9d5c8243 4479 else if ((packets < 5) && (bytes > 512))
0ba82994 4480 itrval = low_latency;
9d5c8243
AK		 4481 break;
4482 case low_latency: /* 50 usec aka 20000 ints/s */
4483 if (bytes > 10000) {
4484 /* this if handles the TSO accounting */
d34a15ab 4485 if (bytes/packets > 8000)
0ba82994 4486 itrval = bulk_latency;
d34a15ab 4487 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4488 itrval = bulk_latency;
d34a15ab 4489 else if ((packets > 35))
0ba82994 4490 itrval = lowest_latency;
9d5c8243 4491 } else if (bytes/packets > 2000) {
0ba82994 4492 itrval = bulk_latency;
9d5c8243 4493 } else if (packets <= 2 && bytes < 512) {
0ba82994 4494 itrval = lowest_latency;
9d5c8243
AK		 4495 }
4496 break;
4497 case bulk_latency: /* 250 usec aka 4000 ints/s */
4498 if (bytes > 25000) {
4499 if (packets > 35)
0ba82994 4500 itrval = low_latency;
1e5c3d21 4501 } else if (bytes < 1500) {
0ba82994 4502 itrval = low_latency;
9d5c8243
AK		 4503 }
4504 break;
4505 }
4506
0ba82994
AD		 4507 /* clear work counters since we have the values we need */
4508 ring_container->total_bytes = 0;
4509 ring_container->total_packets = 0;
4510
4511 /* write updated itr to ring container */
4512 ring_container->itr = itrval;
9d5c8243
AK		 4513}
4514
0ba82994 4515static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4516{
0ba82994 4517 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4518 u32 new_itr = q_vector->itr_val;
0ba82994 4519 u8 current_itr = 0;
9d5c8243
AK		 4520
4521 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4522 if (adapter->link_speed != SPEED_1000) {
4523 current_itr = 0;
0ba82994 4524 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4525 goto set_itr_now;
4526 }
4527
0ba82994
AD		 4528 igb_update_itr(q_vector, &q_vector->tx);
4529 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4530
0ba82994 4531 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4532
6eb5a7f1 4533 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4534 if (current_itr == lowest_latency &&
4535 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4536 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4537 current_itr = low_latency;
4538
9d5c8243
AK		 4539 switch (current_itr) {
4540 /* counts and packets in update_itr are dependent on these numbers */
4541 case lowest_latency:
0ba82994 4542 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4543 break;
4544 case low_latency:
0ba82994 4545 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4546 break;
4547 case bulk_latency:
0ba82994 4548 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4549 break;
4550 default:
4551 break;
4552 }
4553
4554set_itr_now:
047e0030 4555 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4556 /* this attempts to bias the interrupt rate towards Bulk
4557 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4558 * increasing
4559 */
047e0030 4560 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4561 max((new_itr * q_vector->itr_val) /
4562 (new_itr + (q_vector->itr_val >> 2)),
4563 new_itr) : new_itr;
9d5c8243
AK		 4564 /* Don't write the value here; it resets the adapter's
4565 * internal timer, and causes us to delay far longer than
4566 * we should between interrupts. Instead, we write the ITR
4567 * value at the beginning of the next interrupt so the timing
4568 * ends up being correct.
4569 */
047e0030
AD		 4570 q_vector->itr_val = new_itr;
4571 q_vector->set_itr = 1;
9d5c8243 4572 }
9d5c8243
AK		 4573}
4574
c50b52a0
SH		 4575static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4576 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4577{
4578 struct e1000_adv_tx_context_desc *context_desc;
4579 u16 i = tx_ring->next_to_use;
4580
4581 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4582
4583 i++;
4584 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4585
4586 /* set bits to identify this as an advanced context descriptor */
4587 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4588
4589 /* For 82575, context index must be unique per ring. */
866cff06 4590 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4591 mss_l4len_idx |= tx_ring->reg_idx << 4;
4592
4593 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4594 context_desc->seqnum_seed = 0;
4595 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4596 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4597}
4598
7af40ad9
AD		 4599static int igb_tso(struct igb_ring *tx_ring,
4600 struct igb_tx_buffer *first,
4601 u8 *hdr_len)
9d5c8243 4602{
7af40ad9 4603 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4604 u32 vlan_macip_lens, type_tucmd;
4605 u32 mss_l4len_idx, l4len;
06c14e5a 4606 int err;
7d13a7d0 4607
ed6aa105
AD		 4608 if (skb->ip_summed != CHECKSUM_PARTIAL)
4609 return 0;
4610
7d13a7d0
AD		 4611 if (!skb_is_gso(skb))
4612 return 0;
9d5c8243 4613
06c14e5a
FR		 4614 err = skb_cow_head(skb, 0);
4615 if (err < 0)
4616 return err;
9d5c8243 4617
7d13a7d0
AD		 4618 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4619 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4620
7c4d16ff 4621 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4622 struct iphdr *iph = ip_hdr(skb);
4623 iph->tot_len = 0;
4624 iph->check = 0;
4625 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4626 iph->daddr, 0,
4627 IPPROTO_TCP,
4628 0);
7d13a7d0 4629 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4630 first->tx_flags |= IGB_TX_FLAGS_TSO |
4631 IGB_TX_FLAGS_CSUM |
4632 IGB_TX_FLAGS_IPV4;
8e1e8a47 4633 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4634 ipv6_hdr(skb)->payload_len = 0;
4635 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4636 &ipv6_hdr(skb)->daddr,
4637 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4638 first->tx_flags |= IGB_TX_FLAGS_TSO |
4639 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4640 }
4641
7af40ad9 4642 /* compute header lengths */
7d13a7d0
AD		 4643 l4len = tcp_hdrlen(skb);
4644 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4645
7af40ad9
AD		 4646 /* update gso size and bytecount with header size */
4647 first->gso_segs = skb_shinfo(skb)->gso_segs;
4648 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4649
9d5c8243 4650 /* MSS L4LEN IDX */
7d13a7d0
AD		 4651 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4652 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4653
7d13a7d0
AD		 4654 /* VLAN MACLEN IPLEN */
4655 vlan_macip_lens = skb_network_header_len(skb);
4656 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4657 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4658
7d13a7d0 4659 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4660
7d13a7d0 4661 return 1;
9d5c8243
AK		 4662}
4663
7af40ad9 4664static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4665{
7af40ad9 4666 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4667 u32 vlan_macip_lens = 0;
4668 u32 mss_l4len_idx = 0;
4669 u32 type_tucmd = 0;
9d5c8243 4670
7d13a7d0 4671 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4672 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4673 return;
7d13a7d0
AD		 4674 } else {
4675 u8 l4_hdr = 0;
9005df38 4676
7af40ad9 4677 switch (first->protocol) {
7c4d16ff 4678 case htons(ETH_P_IP):
7d13a7d0
AD		 4679 vlan_macip_lens |= skb_network_header_len(skb);
4680 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4681 l4_hdr = ip_hdr(skb)->protocol;
4682 break;
7c4d16ff 4683 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4684 vlan_macip_lens |= skb_network_header_len(skb);
4685 l4_hdr = ipv6_hdr(skb)->nexthdr;
4686 break;
4687 default:
4688 if (unlikely(net_ratelimit())) {
4689 dev_warn(tx_ring->dev,
b980ac18
JK		 4690 "partial checksum but proto=%x!\n",
4691 first->protocol);
fa4a7ef3 4692 }
7d13a7d0
AD		 4693 break;
4694 }
fa4a7ef3 4695
7d13a7d0
AD		 4696 switch (l4_hdr) {
4697 case IPPROTO_TCP:
4698 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4699 mss_l4len_idx = tcp_hdrlen(skb) <<
4700 E1000_ADVTXD_L4LEN_SHIFT;
4701 break;
4702 case IPPROTO_SCTP:
4703 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4704 mss_l4len_idx = sizeof(struct sctphdr) <<
4705 E1000_ADVTXD_L4LEN_SHIFT;
4706 break;
4707 case IPPROTO_UDP:
4708 mss_l4len_idx = sizeof(struct udphdr) <<
4709 E1000_ADVTXD_L4LEN_SHIFT;
4710 break;
4711 default:
4712 if (unlikely(net_ratelimit())) {
4713 dev_warn(tx_ring->dev,
b980ac18
JK		 4714 "partial checksum but l4 proto=%x!\n",
4715 l4_hdr);
44b0cda3 4716 }
7d13a7d0 4717 break;
9d5c8243 4718 }
7af40ad9
AD		 4719
4720 /* update TX checksum flag */
4721 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4722 }
9d5c8243 4723
7d13a7d0 4724 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4725 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4726
7d13a7d0 4727 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4728}
4729
1d9daf45
AD		 4730#define IGB_SET_FLAG(_input, _flag, _result) \
4731 ((_flag <= _result) ? \
4732 ((u32)(_input & _flag) * (_result / _flag)) : \
4733 ((u32)(_input & _flag) / (_flag / _result)))
4734
4735static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4736{
4737 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4738 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4739 E1000_ADVTXD_DCMD_DEXT |
4740 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4741
4742 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4743 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4744 (E1000_ADVTXD_DCMD_VLE));
4745
4746 /* set segmentation bits for TSO */
4747 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4748 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4749
4750 /* set timestamp bit if present */
1d9daf45
AD		 4751 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4752 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4753
1d9daf45
AD		 4754 /* insert frame checksum */
4755 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4756
4757 return cmd_type;
4758}
4759
7af40ad9
AD		 4760static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4761 union e1000_adv_tx_desc *tx_desc,
4762 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4763{
4764 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4765
1d9daf45
AD		 4766 /* 82575 requires a unique index per ring */
4767 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4768 olinfo_status |= tx_ring->reg_idx << 4;
4769
4770 /* insert L4 checksum */
1d9daf45
AD		 4771 olinfo_status |= IGB_SET_FLAG(tx_flags,
4772 IGB_TX_FLAGS_CSUM,
4773 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4774
1d9daf45
AD		 4775 /* insert IPv4 checksum */
4776 olinfo_status |= IGB_SET_FLAG(tx_flags,
4777 IGB_TX_FLAGS_IPV4,
4778 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4779
7af40ad9 4780 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4781}
4782
7af40ad9
AD		 4783static void igb_tx_map(struct igb_ring *tx_ring,
4784 struct igb_tx_buffer *first,
ebe42d16 4785 const u8 hdr_len)
9d5c8243 4786{
7af40ad9 4787 struct sk_buff *skb = first->skb;
c9f14bf3 4788 struct igb_tx_buffer *tx_buffer;
ebe42d16 4789 union e1000_adv_tx_desc *tx_desc;
80d0759e 4790 struct skb_frag_struct *frag;
ebe42d16 4791 dma_addr_t dma;
80d0759e 4792 unsigned int data_len, size;
7af40ad9 4793 u32 tx_flags = first->tx_flags;
1d9daf45 4794 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4795 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4796
4797 tx_desc = IGB_TX_DESC(tx_ring, i);
4798
80d0759e
AD		 4799 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4800
4801 size = skb_headlen(skb);
4802 data_len = skb->data_len;
ebe42d16
AD		 4803
4804 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4805
80d0759e
AD		 4806 tx_buffer = first;
4807
4808 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4809 if (dma_mapping_error(tx_ring->dev, dma))
4810 goto dma_error;
4811
4812 /* record length, and DMA address */
4813 dma_unmap_len_set(tx_buffer, len, size);
4814 dma_unmap_addr_set(tx_buffer, dma, dma);
4815
4816 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4817
ebe42d16
AD		 4818 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4819 tx_desc->read.cmd_type_len =
1d9daf45 4820 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4821
4822 i++;
4823 tx_desc++;
4824 if (i == tx_ring->count) {
4825 tx_desc = IGB_TX_DESC(tx_ring, 0);
4826 i = 0;
4827 }
80d0759e 4828 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4829
4830 dma += IGB_MAX_DATA_PER_TXD;
4831 size -= IGB_MAX_DATA_PER_TXD;
4832
ebe42d16
AD		 4833 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4834 }
4835
4836 if (likely(!data_len))
4837 break;
2bbfebe2 4838
1d9daf45 4839 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4840
65689fef 4841 i++;
ebe42d16
AD		 4842 tx_desc++;
4843 if (i == tx_ring->count) {
4844 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4845 i = 0;
ebe42d16 4846 }
80d0759e 4847 tx_desc->read.olinfo_status = 0;
65689fef 4848
9e903e08 4849 size = skb_frag_size(frag);
ebe42d16
AD		 4850 data_len -= size;
4851
4852 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4853 size, DMA_TO_DEVICE);
6366ad33 4854
c9f14bf3 4855 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4856 }
4857
ebe42d16 4858 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4859 cmd_type |= size | IGB_TXD_DCMD;
4860 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4861
80d0759e
AD		 4862 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4863
8542db05
AD		 4864 /* set the timestamp */
4865 first->time_stamp = jiffies;
4866
b980ac18 4867 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4868 * are new descriptors to fetch. (Only applicable for weak-ordered
4869 * memory model archs, such as IA-64).
4870 *
4871 * We also need this memory barrier to make certain all of the
4872 * status bits have been updated before next_to_watch is written.
4873 */
4874 wmb();
4875
8542db05 4876 /* set next_to_watch value indicating a packet is present */
ebe42d16 4877 first->next_to_watch = tx_desc;
9d5c8243 4878
ebe42d16
AD		 4879 i++;
4880 if (i == tx_ring->count)
4881 i = 0;
6366ad33 4882
ebe42d16 4883 tx_ring->next_to_use = i;
6366ad33 4884
ebe42d16 4885 writel(i, tx_ring->tail);
6366ad33 4886
ebe42d16 4887 /* we need this if more than one processor can write to our tail
b980ac18
JK		 4888 * at a time, it synchronizes IO on IA64/Altix systems
4889 */
ebe42d16
AD		 4890 mmiowb();
4891
4892 return;
4893
4894dma_error:
4895 dev_err(tx_ring->dev, "TX DMA map failed\n");
4896
4897 /* clear dma mappings for failed tx_buffer_info map */
4898 for (;;) {
c9f14bf3
AD		 4899 tx_buffer = &tx_ring->tx_buffer_info[i];
4900 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4901 if (tx_buffer == first)
ebe42d16 4902 break;
a77ff709
NN		 4903 if (i == 0)
4904 i = tx_ring->count;
6366ad33 4905 i--;
6366ad33
AD		 4906 }
4907
9d5c8243 4908 tx_ring->next_to_use = i;
9d5c8243
AK		 4909}
4910
6ad4edfc 4911static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4912{
e694e964
AD		 4913 struct net_device *netdev = tx_ring->netdev;
4914
661086df 4915 netif_stop_subqueue(netdev, tx_ring->queue_index);
661086df 4916
9d5c8243
AK		 4917 /* Herbert's original patch had:
4918 * smp_mb__after_netif_stop_queue();
b980ac18
JK		 4919 * but since that doesn't exist yet, just open code it.
4920 */
9d5c8243
AK		 4921 smp_mb();
4922
4923 /* We need to check again in a case another CPU has just
b980ac18
JK		 4924 * made room available.
4925 */
c493ea45 4926 if (igb_desc_unused(tx_ring) < size)
9d5c8243
AK		 4927 return -EBUSY;
4928
4929 /* A reprieve! */
661086df 4930 netif_wake_subqueue(netdev, tx_ring->queue_index);
12dcd86b
ED		 4931
4932 u64_stats_update_begin(&tx_ring->tx_syncp2);
4933 tx_ring->tx_stats.restart_queue2++;
4934 u64_stats_update_end(&tx_ring->tx_syncp2);
4935
9d5c8243
AK		 4936 return 0;
4937}
4938
6ad4edfc 4939static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
9d5c8243 4940{
c493ea45 4941 if (igb_desc_unused(tx_ring) >= size)
9d5c8243 4942 return 0;
e694e964 4943 return __igb_maybe_stop_tx(tx_ring, size);
9d5c8243
AK		 4944}
4945
cd392f5c
AD		 4946netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4947 struct igb_ring *tx_ring)
9d5c8243 4948{
8542db05 4949 struct igb_tx_buffer *first;
ebe42d16 4950 int tso;
91d4ee33 4951 u32 tx_flags = 0;
21ba6fe1 4952 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4953 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4954 u8 hdr_len = 0;
9d5c8243 4955
21ba6fe1
AD		 4956 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4957 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4958 * + 2 desc gap to keep tail from touching head,
9d5c8243 4959 * + 1 desc for context descriptor,
21ba6fe1
AD		 4960 * otherwise try next time
4961 */
4962 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4963 unsigned short f;
9005df38 4964
21ba6fe1
AD		 4965 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4966 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4967 } else {
4968 count += skb_shinfo(skb)->nr_frags;
4969 }
4970
4971 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 4972 /* this is a hard error */
9d5c8243
AK		 4973 return NETDEV_TX_BUSY;
4974 }
33af6bcc 4975
7af40ad9
AD		 4976 /* record the location of the first descriptor for this packet */
4977 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4978 first->skb = skb;
4979 first->bytecount = skb->len;
4980 first->gso_segs = 1;
4981
b646c22e
AD		 4982 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
4983 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 4984
ed4420a3
JK		 4985 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
4986 &adapter->state)) {
b646c22e
AD		 4987 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4988 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4989
4990 adapter->ptp_tx_skb = skb_get(skb);
4991 adapter->ptp_tx_start = jiffies;
4992 if (adapter->hw.mac.type == e1000_82576)
4993 schedule_work(&adapter->ptp_tx_work);
4994 }
33af6bcc 4995 }
9d5c8243 4996
afc835d1
JK		 4997 skb_tx_timestamp(skb);
4998
eab6d18d 4999 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 5000 tx_flags |= IGB_TX_FLAGS_VLAN;
5001 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5002 }
5003
7af40ad9
AD		 5004 /* record initial flags and protocol */
5005 first->tx_flags = tx_flags;
5006 first->protocol = protocol;
cdfd01fc 5007
7af40ad9
AD		 5008 tso = igb_tso(tx_ring, first, &hdr_len);
5009 if (tso < 0)
7d13a7d0 5010 goto out_drop;
7af40ad9
AD		 5011 else if (!tso)
5012 igb_tx_csum(tx_ring, first);
9d5c8243 5013
7af40ad9 5014 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2
AD		 5015
5016 /* Make sure there is space in the ring for the next send. */
21ba6fe1 5017 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
85ad76b2 5018
9d5c8243 5019 return NETDEV_TX_OK;
7d13a7d0
AD		 5020
5021out_drop:
7af40ad9
AD		 5022 igb_unmap_and_free_tx_resource(tx_ring, first);
5023
7d13a7d0 5024 return NETDEV_TX_OK;
9d5c8243
AK		 5025}
5026
1cc3bd87
AD		 5027static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5028 struct sk_buff *skb)
5029{
5030 unsigned int r_idx = skb->queue_mapping;
5031
5032 if (r_idx >= adapter->num_tx_queues)
5033 r_idx = r_idx % adapter->num_tx_queues;
5034
5035 return adapter->tx_ring[r_idx];
5036}
5037
cd392f5c
AD		 5038static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5039 struct net_device *netdev)
9d5c8243
AK		 5040{
5041 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5042
5043 if (test_bit(__IGB_DOWN, &adapter->state)) {
5044 dev_kfree_skb_any(skb);
5045 return NETDEV_TX_OK;
5046 }
5047
5048 if (skb->len <= 0) {
5049 dev_kfree_skb_any(skb);
5050 return NETDEV_TX_OK;
5051 }
5052
b980ac18 5053 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5054 * in order to meet this minimum size requirement.
5055 */
ea5ceeab
TD		 5056 if (unlikely(skb->len < 17)) {
5057 if (skb_pad(skb, 17 - skb->len))
1cc3bd87
AD		 5058 return NETDEV_TX_OK;
5059 skb->len = 17;
ea5ceeab 5060 skb_set_tail_pointer(skb, 17);
1cc3bd87 5061 }
9d5c8243 5062
1cc3bd87 5063 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5064}
5065
5066/**
b980ac18
JK		 5067 * igb_tx_timeout - Respond to a Tx Hang
5068 * @netdev: network interface device structure
9d5c8243
AK		 5069 **/
5070static void igb_tx_timeout(struct net_device *netdev)
5071{
5072 struct igb_adapter *adapter = netdev_priv(netdev);
5073 struct e1000_hw *hw = &adapter->hw;
5074
5075 /* Do the reset outside of interrupt context */
5076 adapter->tx_timeout_count++;
f7ba205e 5077
06218a8d 5078 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5079 hw->dev_spec._82575.global_device_reset = true;
5080
9d5c8243 5081 schedule_work(&adapter->reset_task);
265de409
AD		 5082 wr32(E1000_EICS,
5083 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5084}
5085
5086static void igb_reset_task(struct work_struct *work)
5087{
5088 struct igb_adapter *adapter;
5089 adapter = container_of(work, struct igb_adapter, reset_task);
5090
c97ec42a
TI		 5091 igb_dump(adapter);
5092 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5093 igb_reinit_locked(adapter);
5094}
5095
5096/**
b980ac18
JK		 5097 * igb_get_stats64 - Get System Network Statistics
5098 * @netdev: network interface device structure
5099 * @stats: rtnl_link_stats64 pointer
9d5c8243 5100 **/
12dcd86b 5101static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5102 struct rtnl_link_stats64 *stats)
9d5c8243 5103{
12dcd86b
ED		 5104 struct igb_adapter *adapter = netdev_priv(netdev);
5105
5106 spin_lock(&adapter->stats64_lock);
5107 igb_update_stats(adapter, &adapter->stats64);
5108 memcpy(stats, &adapter->stats64, sizeof(*stats));
5109 spin_unlock(&adapter->stats64_lock);
5110
5111 return stats;
9d5c8243
AK		 5112}
5113
5114/**
b980ac18
JK		 5115 * igb_change_mtu - Change the Maximum Transfer Unit
5116 * @netdev: network interface device structure
5117 * @new_mtu: new value for maximum frame size
9d5c8243 5118 *
b980ac18 5119 * Returns 0 on success, negative on failure
9d5c8243
AK		 5120 **/
5121static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5122{
5123 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5124 struct pci_dev *pdev = adapter->pdev;
153285f9 5125 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5126
c809d227 5127 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5128 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5129 return -EINVAL;
5130 }
5131
153285f9 5132#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5133 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5134 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5135 return -EINVAL;
5136 }
5137
2ccd994c
AD		 5138 /* adjust max frame to be at least the size of a standard frame */
5139 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5140 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5141
9d5c8243
AK		 5142 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
5143 msleep(1);
73cd78f1 5144
9d5c8243
AK		 5145 /* igb_down has a dependency on max_frame_size */
5146 adapter->max_frame_size = max_frame;
559e9c49 5147
4c844851
AD		 5148 if (netif_running(netdev))
5149 igb_down(adapter);
9d5c8243 5150
090b1795 5151 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5152 netdev->mtu, new_mtu);
5153 netdev->mtu = new_mtu;
5154
5155 if (netif_running(netdev))
5156 igb_up(adapter);
5157 else
5158 igb_reset(adapter);
5159
5160 clear_bit(__IGB_RESETTING, &adapter->state);
5161
5162 return 0;
5163}
5164
5165/**
b980ac18
JK		 5166 * igb_update_stats - Update the board statistics counters
5167 * @adapter: board private structure
9d5c8243 5168 **/
12dcd86b
ED		 5169void igb_update_stats(struct igb_adapter *adapter,
5170 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5171{
5172 struct e1000_hw *hw = &adapter->hw;
5173 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5174 u32 reg, mpc;
9d5c8243 5175 u16 phy_tmp;
3f9c0164
AD		 5176 int i;
5177 u64 bytes, packets;
12dcd86b
ED		 5178 unsigned int start;
5179 u64 _bytes, _packets;
9d5c8243
AK		 5180
5181#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
5182
b980ac18 5183 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5184 * connection is down.
5185 */
5186 if (adapter->link_speed == 0)
5187 return;
5188 if (pci_channel_offline(pdev))
5189 return;
5190
3f9c0164
AD		 5191 bytes = 0;
5192 packets = 0;
7f90128e
AA		 5193
5194 rcu_read_lock();
3f9c0164 5195 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5196 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5197 u32 rqdpc = rd32(E1000_RQDPC(i));
5198 if (hw->mac.type >= e1000_i210)
5199 wr32(E1000_RQDPC(i), 0);
12dcd86b 5200
ae1c07a6
AD		 5201 if (rqdpc) {
5202 ring->rx_stats.drops += rqdpc;
5203 net_stats->rx_fifo_errors += rqdpc;
5204 }
12dcd86b
ED		 5205
5206 do {
57a7744e 5207 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5208 _bytes = ring->rx_stats.bytes;
5209 _packets = ring->rx_stats.packets;
57a7744e 5210 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5211 bytes += _bytes;
5212 packets += _packets;
3f9c0164
AD		 5213 }
5214
128e45eb
AD		 5215 net_stats->rx_bytes = bytes;
5216 net_stats->rx_packets = packets;
3f9c0164
AD		 5217
5218 bytes = 0;
5219 packets = 0;
5220 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5221 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5222 do {
57a7744e 5223 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5224 _bytes = ring->tx_stats.bytes;
5225 _packets = ring->tx_stats.packets;
57a7744e 5226 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5227 bytes += _bytes;
5228 packets += _packets;
3f9c0164 5229 }
128e45eb
AD		 5230 net_stats->tx_bytes = bytes;
5231 net_stats->tx_packets = packets;
7f90128e 5232 rcu_read_unlock();
3f9c0164
AD		 5233
5234 /* read stats registers */
9d5c8243
AK		 5235 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5236 adapter->stats.gprc += rd32(E1000_GPRC);
5237 adapter->stats.gorc += rd32(E1000_GORCL);
5238 rd32(E1000_GORCH); /* clear GORCL */
5239 adapter->stats.bprc += rd32(E1000_BPRC);
5240 adapter->stats.mprc += rd32(E1000_MPRC);
5241 adapter->stats.roc += rd32(E1000_ROC);
5242
5243 adapter->stats.prc64 += rd32(E1000_PRC64);
5244 adapter->stats.prc127 += rd32(E1000_PRC127);
5245 adapter->stats.prc255 += rd32(E1000_PRC255);
5246 adapter->stats.prc511 += rd32(E1000_PRC511);
5247 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5248 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5249 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5250 adapter->stats.sec += rd32(E1000_SEC);
5251
fa3d9a6d
MW		 5252 mpc = rd32(E1000_MPC);
5253 adapter->stats.mpc += mpc;
5254 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5255 adapter->stats.scc += rd32(E1000_SCC);
5256 adapter->stats.ecol += rd32(E1000_ECOL);
5257 adapter->stats.mcc += rd32(E1000_MCC);
5258 adapter->stats.latecol += rd32(E1000_LATECOL);
5259 adapter->stats.dc += rd32(E1000_DC);
5260 adapter->stats.rlec += rd32(E1000_RLEC);
5261 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5262 adapter->stats.xontxc += rd32(E1000_XONTXC);
5263 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5264 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5265 adapter->stats.fcruc += rd32(E1000_FCRUC);
5266 adapter->stats.gptc += rd32(E1000_GPTC);
5267 adapter->stats.gotc += rd32(E1000_GOTCL);
5268 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5269 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5270 adapter->stats.ruc += rd32(E1000_RUC);
5271 adapter->stats.rfc += rd32(E1000_RFC);
5272 adapter->stats.rjc += rd32(E1000_RJC);
5273 adapter->stats.tor += rd32(E1000_TORH);
5274 adapter->stats.tot += rd32(E1000_TOTH);
5275 adapter->stats.tpr += rd32(E1000_TPR);
5276
5277 adapter->stats.ptc64 += rd32(E1000_PTC64);
5278 adapter->stats.ptc127 += rd32(E1000_PTC127);
5279 adapter->stats.ptc255 += rd32(E1000_PTC255);
5280 adapter->stats.ptc511 += rd32(E1000_PTC511);
5281 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5282 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5283
5284 adapter->stats.mptc += rd32(E1000_MPTC);
5285 adapter->stats.bptc += rd32(E1000_BPTC);
5286
2d0b0f69
NN		 5287 adapter->stats.tpt += rd32(E1000_TPT);
5288 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5289
5290 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5291 /* read internal phy specific stats */
5292 reg = rd32(E1000_CTRL_EXT);
5293 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5294 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5295
5296 /* this stat has invalid values on i210/i211 */
5297 if ((hw->mac.type != e1000_i210) &&
5298 (hw->mac.type != e1000_i211))
5299 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5300 }
5301
9d5c8243
AK		 5302 adapter->stats.tsctc += rd32(E1000_TSCTC);
5303 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5304
5305 adapter->stats.iac += rd32(E1000_IAC);
5306 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5307 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5308 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5309 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5310 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5311 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5312 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5313 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5314
5315 /* Fill out the OS statistics structure */
128e45eb
AD		 5316 net_stats->multicast = adapter->stats.mprc;
5317 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5318
5319 /* Rx Errors */
5320
5321 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5322 * our own version based on RUC and ROC
5323 */
128e45eb 5324 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5325 adapter->stats.crcerrs + adapter->stats.algnerrc +
5326 adapter->stats.ruc + adapter->stats.roc +
5327 adapter->stats.cexterr;
128e45eb
AD		 5328 net_stats->rx_length_errors = adapter->stats.ruc +
5329 adapter->stats.roc;
5330 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5331 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5332 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5333
5334 /* Tx Errors */
128e45eb
AD		 5335 net_stats->tx_errors = adapter->stats.ecol +
5336 adapter->stats.latecol;
5337 net_stats->tx_aborted_errors = adapter->stats.ecol;
5338 net_stats->tx_window_errors = adapter->stats.latecol;
5339 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5340
5341 /* Tx Dropped needs to be maintained elsewhere */
5342
5343 /* Phy Stats */
5344 if (hw->phy.media_type == e1000_media_type_copper) {
5345 if ((adapter->link_speed == SPEED_1000) &&
73cd78f1 5346 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
9d5c8243
AK		 5347 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
5348 adapter->phy_stats.idle_errors += phy_tmp;
5349 }
5350 }
5351
5352 /* Management Stats */
5353 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5354 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5355 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5356
5357 /* OS2BMC Stats */
5358 reg = rd32(E1000_MANC);
5359 if (reg & E1000_MANC_EN_BMC2OS) {
5360 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5361 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5362 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5363 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5364 }
9d5c8243
AK		 5365}
5366
9d5c8243
AK		 5367static irqreturn_t igb_msix_other(int irq, void *data)
5368{
047e0030 5369 struct igb_adapter *adapter = data;
9d5c8243 5370 struct e1000_hw *hw = &adapter->hw;
844290e5 5371 u32 icr = rd32(E1000_ICR);
844290e5 5372 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5373
7f081d40
AD		 5374 if (icr & E1000_ICR_DRSTA)
5375 schedule_work(&adapter->reset_task);
5376
047e0030 5377 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5378 /* HW is reporting DMA is out of sync */
5379 adapter->stats.doosync++;
13800469
GR		 5380 /* The DMA Out of Sync is also indication of a spoof event
5381 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5382 * see if it is really a spoof event.
5383 */
13800469 5384 igb_check_wvbr(adapter);
dda0e083 5385 }
eebbbdba 5386
4ae196df
AD		 5387 /* Check for a mailbox event */
5388 if (icr & E1000_ICR_VMMB)
5389 igb_msg_task(adapter);
5390
5391 if (icr & E1000_ICR_LSC) {
5392 hw->mac.get_link_status = 1;
5393 /* guard against interrupt when we're going down */
5394 if (!test_bit(__IGB_DOWN, &adapter->state))
5395 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5396 }
5397
1f6e8178
MV		 5398 if (icr & E1000_ICR_TS) {
5399 u32 tsicr = rd32(E1000_TSICR);
5400
5401 if (tsicr & E1000_TSICR_TXTS) {
5402 /* acknowledge the interrupt */
5403 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5404 /* retrieve hardware timestamp */
5405 schedule_work(&adapter->ptp_tx_work);
5406 }
5407 }
1f6e8178 5408
844290e5 5409 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5410
5411 return IRQ_HANDLED;
5412}
5413
047e0030 5414static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5415{
26b39276 5416 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5417 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5418
047e0030
AD		 5419 if (!q_vector->set_itr)
5420 return;
73cd78f1 5421
047e0030
AD		 5422 if (!itr_val)
5423 itr_val = 0x4;
661086df 5424
26b39276
AD		 5425 if (adapter->hw.mac.type == e1000_82575)
5426 itr_val |= itr_val << 16;
661086df 5427 else
0ba82994 5428 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5429
047e0030
AD		 5430 writel(itr_val, q_vector->itr_register);
5431 q_vector->set_itr = 0;
6eb5a7f1
AD		 5432}
5433
047e0030 5434static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5435{
047e0030 5436 struct igb_q_vector *q_vector = data;
9d5c8243 5437
047e0030
AD		 5438 /* Write the ITR value calculated from the previous interrupt. */
5439 igb_write_itr(q_vector);
9d5c8243 5440
047e0030 5441 napi_schedule(&q_vector->napi);
844290e5 5442
047e0030 5443 return IRQ_HANDLED;
fe4506b6
JC		 5444}
5445
421e02f0 5446#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5447static void igb_update_tx_dca(struct igb_adapter *adapter,
5448 struct igb_ring *tx_ring,
5449 int cpu)
5450{
5451 struct e1000_hw *hw = &adapter->hw;
5452 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5453
5454 if (hw->mac.type != e1000_82575)
5455 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5456
b980ac18 5457 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5458 * DCA is enabled. This is due to a known issue in some chipsets
5459 * which will cause the DCA tag to be cleared.
5460 */
5461 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5462 E1000_DCA_TXCTRL_DATA_RRO_EN |
5463 E1000_DCA_TXCTRL_DESC_DCA_EN;
5464
5465 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5466}
5467
5468static void igb_update_rx_dca(struct igb_adapter *adapter,
5469 struct igb_ring *rx_ring,
5470 int cpu)
5471{
5472 struct e1000_hw *hw = &adapter->hw;
5473 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5474
5475 if (hw->mac.type != e1000_82575)
5476 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5477
b980ac18 5478 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5479 * DCA is enabled. This is due to a known issue in some chipsets
5480 * which will cause the DCA tag to be cleared.
5481 */
5482 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5483 E1000_DCA_RXCTRL_DESC_DCA_EN;
5484
5485 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5486}
5487
047e0030 5488static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5489{
047e0030 5490 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5491 int cpu = get_cpu();
fe4506b6 5492
047e0030
AD		 5493 if (q_vector->cpu == cpu)
5494 goto out_no_update;
5495
6a05004a
AD		 5496 if (q_vector->tx.ring)
5497 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5498
5499 if (q_vector->rx.ring)
5500 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5501
047e0030
AD		 5502 q_vector->cpu = cpu;
5503out_no_update:
fe4506b6
JC		 5504 put_cpu();
5505}
5506
5507static void igb_setup_dca(struct igb_adapter *adapter)
5508{
7e0e99ef 5509 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5510 int i;
5511
7dfc16fa 5512 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5513 return;
5514
7e0e99ef
AD		 5515 /* Always use CB2 mode, difference is masked in the CB driver. */
5516 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5517
047e0030 5518 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5519 adapter->q_vector[i]->cpu = -1;
5520 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5521 }
5522}
5523
5524static int __igb_notify_dca(struct device *dev, void *data)
5525{
5526 struct net_device *netdev = dev_get_drvdata(dev);
5527 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5528 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5529 struct e1000_hw *hw = &adapter->hw;
5530 unsigned long event = *(unsigned long *)data;
5531
5532 switch (event) {
5533 case DCA_PROVIDER_ADD:
5534 /* if already enabled, don't do it again */
7dfc16fa 5535 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5536 break;
fe4506b6 5537 if (dca_add_requester(dev) == 0) {
bbd98fe4 5538 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5539 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5540 igb_setup_dca(adapter);
5541 break;
5542 }
5543 /* Fall Through since DCA is disabled. */
5544 case DCA_PROVIDER_REMOVE:
7dfc16fa 5545 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5546 /* without this a class_device is left
b980ac18
JK		 5547 * hanging around in the sysfs model
5548 */
fe4506b6 5549 dca_remove_requester(dev);
090b1795 5550 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5551 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5552 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5553 }
5554 break;
5555 }
bbd98fe4 5556
fe4506b6 5557 return 0;
9d5c8243
AK		 5558}
5559
fe4506b6 5560static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5561 void *p)
fe4506b6
JC		 5562{
5563 int ret_val;
5564
5565 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5566 __igb_notify_dca);
fe4506b6
JC		 5567
5568 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5569}
421e02f0 5570#endif /* CONFIG_IGB_DCA */
9d5c8243 5571
0224d663
GR		 5572#ifdef CONFIG_PCI_IOV
5573static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5574{
5575 unsigned char mac_addr[ETH_ALEN];
0224d663 5576
5ac6f91d 5577 eth_zero_addr(mac_addr);
0224d663
GR		 5578 igb_set_vf_mac(adapter, vf, mac_addr);
5579
70ea4783
LL		 5580 /* By default spoof check is enabled for all VFs */
5581 adapter->vf_data[vf].spoofchk_enabled = true;
5582
f557147c 5583 return 0;
0224d663
GR		 5584}
5585
0224d663 5586#endif
4ae196df
AD		 5587static void igb_ping_all_vfs(struct igb_adapter *adapter)
5588{
5589 struct e1000_hw *hw = &adapter->hw;
5590 u32 ping;
5591 int i;
5592
5593 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5594 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5595 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5596 ping |= E1000_VT_MSGTYPE_CTS;
5597 igb_write_mbx(hw, &ping, 1, i);
5598 }
5599}
5600
7d5753f0
AD		 5601static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5602{
5603 struct e1000_hw *hw = &adapter->hw;
5604 u32 vmolr = rd32(E1000_VMOLR(vf));
5605 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5606
d85b9004 5607 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5608 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5609 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5610
5611 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5612 vmolr |= E1000_VMOLR_MPME;
d85b9004 5613 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5614 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5615 } else {
b980ac18 5616 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5617 * flag we need to write the hashes to the MTA as this step
5618 * was previously skipped
5619 */
5620 if (vf_data->num_vf_mc_hashes > 30) {
5621 vmolr |= E1000_VMOLR_MPME;
5622 } else if (vf_data->num_vf_mc_hashes) {
5623 int j;
9005df38 5624
7d5753f0
AD		 5625 vmolr |= E1000_VMOLR_ROMPE;
5626 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5627 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5628 }
5629 }
5630
5631 wr32(E1000_VMOLR(vf), vmolr);
5632
5633 /* there are flags left unprocessed, likely not supported */
5634 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5635 return -EINVAL;
5636
5637 return 0;
7d5753f0
AD		 5638}
5639
4ae196df
AD		 5640static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5641 u32 *msgbuf, u32 vf)
5642{
5643 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5644 u16 *hash_list = (u16 *)&msgbuf[1];
5645 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5646 int i;
5647
7d5753f0 5648 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5649 * to this VF for later use to restore when the PF multi cast
5650 * list changes
5651 */
5652 vf_data->num_vf_mc_hashes = n;
5653
7d5753f0
AD		 5654 /* only up to 30 hash values supported */
5655 if (n > 30)
5656 n = 30;
5657
5658 /* store the hashes for later use */
4ae196df 5659 for (i = 0; i < n; i++)
a419aef8 5660 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5661
5662 /* Flush and reset the mta with the new values */
ff41f8dc 5663 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5664
5665 return 0;
5666}
5667
5668static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5669{
5670 struct e1000_hw *hw = &adapter->hw;
5671 struct vf_data_storage *vf_data;
5672 int i, j;
5673
5674 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5675 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5676
7d5753f0
AD		 5677 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5678
4ae196df 5679 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5680
5681 if ((vf_data->num_vf_mc_hashes > 30) ||
5682 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5683 vmolr |= E1000_VMOLR_MPME;
5684 } else if (vf_data->num_vf_mc_hashes) {
5685 vmolr |= E1000_VMOLR_ROMPE;
5686 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5687 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5688 }
5689 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5690 }
5691}
5692
5693static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5694{
5695 struct e1000_hw *hw = &adapter->hw;
5696 u32 pool_mask, reg, vid;
5697 int i;
5698
5699 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5700
5701 /* Find the vlan filter for this id */
5702 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5703 reg = rd32(E1000_VLVF(i));
5704
5705 /* remove the vf from the pool */
5706 reg &= ~pool_mask;
5707
5708 /* if pool is empty then remove entry from vfta */
5709 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5710 (reg & E1000_VLVF_VLANID_ENABLE)) {
5711 reg = 0;
5712 vid = reg & E1000_VLVF_VLANID_MASK;
5713 igb_vfta_set(hw, vid, false);
5714 }
5715
5716 wr32(E1000_VLVF(i), reg);
5717 }
ae641bdc
AD		 5718
5719 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5720}
5721
5722static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5723{
5724 struct e1000_hw *hw = &adapter->hw;
5725 u32 reg, i;
5726
51466239
AD		 5727 /* The vlvf table only exists on 82576 hardware and newer */
5728 if (hw->mac.type < e1000_82576)
5729 return -1;
5730
5731 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5732 if (!adapter->vfs_allocated_count)
5733 return -1;
5734
5735 /* Find the vlan filter for this id */
5736 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5737 reg = rd32(E1000_VLVF(i));
5738 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5739 vid == (reg & E1000_VLVF_VLANID_MASK))
5740 break;
5741 }
5742
5743 if (add) {
5744 if (i == E1000_VLVF_ARRAY_SIZE) {
5745 /* Did not find a matching VLAN ID entry that was
5746 * enabled. Search for a free filter entry, i.e.
5747 * one without the enable bit set
5748 */
5749 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5750 reg = rd32(E1000_VLVF(i));
5751 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5752 break;
5753 }
5754 }
5755 if (i < E1000_VLVF_ARRAY_SIZE) {
5756 /* Found an enabled/available entry */
5757 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5758
5759 /* if !enabled we need to set this up in vfta */
5760 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5761 /* add VID to filter table */
5762 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5763 reg |= E1000_VLVF_VLANID_ENABLE;
5764 }
cad6d05f
AD		 5765 reg &= ~E1000_VLVF_VLANID_MASK;
5766 reg |= vid;
4ae196df 5767 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5768
5769 /* do not modify RLPML for PF devices */
5770 if (vf >= adapter->vfs_allocated_count)
5771 return 0;
5772
5773 if (!adapter->vf_data[vf].vlans_enabled) {
5774 u32 size;
9005df38 5775
ae641bdc
AD		 5776 reg = rd32(E1000_VMOLR(vf));
5777 size = reg & E1000_VMOLR_RLPML_MASK;
5778 size += 4;
5779 reg &= ~E1000_VMOLR_RLPML_MASK;
5780 reg |= size;
5781 wr32(E1000_VMOLR(vf), reg);
5782 }
ae641bdc 5783
51466239 5784 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5785 }
5786 } else {
5787 if (i < E1000_VLVF_ARRAY_SIZE) {
5788 /* remove vf from the pool */
5789 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5790 /* if pool is empty then remove entry from vfta */
5791 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5792 reg = 0;
5793 igb_vfta_set(hw, vid, false);
5794 }
5795 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5796
5797 /* do not modify RLPML for PF devices */
5798 if (vf >= adapter->vfs_allocated_count)
5799 return 0;
5800
5801 adapter->vf_data[vf].vlans_enabled--;
5802 if (!adapter->vf_data[vf].vlans_enabled) {
5803 u32 size;
9005df38 5804
ae641bdc
AD		 5805 reg = rd32(E1000_VMOLR(vf));
5806 size = reg & E1000_VMOLR_RLPML_MASK;
5807 size -= 4;
5808 reg &= ~E1000_VMOLR_RLPML_MASK;
5809 reg |= size;
5810 wr32(E1000_VMOLR(vf), reg);
5811 }
4ae196df
AD		 5812 }
5813 }
8151d294
WM		 5814 return 0;
5815}
5816
5817static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5818{
5819 struct e1000_hw *hw = &adapter->hw;
5820
5821 if (vid)
5822 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5823 else
5824 wr32(E1000_VMVIR(vf), 0);
5825}
5826
5827static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5828 int vf, u16 vlan, u8 qos)
5829{
5830 int err = 0;
5831 struct igb_adapter *adapter = netdev_priv(netdev);
5832
5833 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5834 return -EINVAL;
5835 if (vlan || qos) {
5836 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5837 if (err)
5838 goto out;
5839 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5840 igb_set_vmolr(adapter, vf, !vlan);
5841 adapter->vf_data[vf].pf_vlan = vlan;
5842 adapter->vf_data[vf].pf_qos = qos;
5843 dev_info(&adapter->pdev->dev,
5844 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5845 if (test_bit(__IGB_DOWN, &adapter->state)) {
5846 dev_warn(&adapter->pdev->dev,
b980ac18 5847 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5848 dev_warn(&adapter->pdev->dev,
b980ac18 5849 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5850 }
5851 } else {
5852 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5853 false, vf);
8151d294
WM		 5854 igb_set_vmvir(adapter, vlan, vf);
5855 igb_set_vmolr(adapter, vf, true);
5856 adapter->vf_data[vf].pf_vlan = 0;
5857 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5858 }
8151d294 5859out:
b980ac18 5860 return err;
4ae196df
AD		 5861}
5862
6f3dc319
GR		 5863static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5864{
5865 struct e1000_hw *hw = &adapter->hw;
5866 int i;
5867 u32 reg;
5868
5869 /* Find the vlan filter for this id */
5870 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5871 reg = rd32(E1000_VLVF(i));
5872 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5873 vid == (reg & E1000_VLVF_VLANID_MASK))
5874 break;
5875 }
5876
5877 if (i >= E1000_VLVF_ARRAY_SIZE)
5878 i = -1;
5879
5880 return i;
5881}
5882
4ae196df
AD		 5883static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5884{
6f3dc319 5885 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5886 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5887 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5888 int err = 0;
4ae196df 5889
6f3dc319
GR		 5890 /* If in promiscuous mode we need to make sure the PF also has
5891 * the VLAN filter set.
5892 */
5893 if (add && (adapter->netdev->flags & IFF_PROMISC))
5894 err = igb_vlvf_set(adapter, vid, add,
5895 adapter->vfs_allocated_count);
5896 if (err)
5897 goto out;
5898
5899 err = igb_vlvf_set(adapter, vid, add, vf);
5900
5901 if (err)
5902 goto out;
5903
5904 /* Go through all the checks to see if the VLAN filter should
5905 * be wiped completely.
5906 */
5907 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5908 u32 vlvf, bits;
6f3dc319 5909 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 5910
6f3dc319
GR		 5911 if (regndx < 0)
5912 goto out;
5913 /* See if any other pools are set for this VLAN filter
5914 * entry other than the PF.
5915 */
5916 vlvf = bits = rd32(E1000_VLVF(regndx));
5917 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5918 adapter->vfs_allocated_count);
5919 /* If the filter was removed then ensure PF pool bit
5920 * is cleared if the PF only added itself to the pool
5921 * because the PF is in promiscuous mode.
5922 */
5923 if ((vlvf & VLAN_VID_MASK) == vid &&
5924 !test_bit(vid, adapter->active_vlans) &&
5925 !bits)
5926 igb_vlvf_set(adapter, vid, add,
5927 adapter->vfs_allocated_count);
5928 }
5929
5930out:
5931 return err;
4ae196df
AD		 5932}
5933
f2ca0dbe 5934static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5935{
8fa7e0f7
GR		 5936 /* clear flags - except flag that indicates PF has set the MAC */
5937 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5938 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5939
5940 /* reset offloads to defaults */
8151d294 5941 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5942
5943 /* reset vlans for device */
5944 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5945 if (adapter->vf_data[vf].pf_vlan)
5946 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5947 adapter->vf_data[vf].pf_vlan,
5948 adapter->vf_data[vf].pf_qos);
5949 else
5950 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5951
5952 /* reset multicast table array for vf */
5953 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5954
5955 /* Flush and reset the mta with the new values */
ff41f8dc 5956 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5957}
5958
f2ca0dbe
AD		 5959static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5960{
5961 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5962
5ac6f91d 5963 /* clear mac address as we were hotplug removed/added */
8151d294 5964 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5965 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5966
5967 /* process remaining reset events */
5968 igb_vf_reset(adapter, vf);
5969}
5970
5971static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5972{
5973 struct e1000_hw *hw = &adapter->hw;
5974 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5975 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5976 u32 reg, msgbuf[3];
5977 u8 *addr = (u8 *)(&msgbuf[1]);
5978
5979 /* process all the same items cleared in a function level reset */
f2ca0dbe 5980 igb_vf_reset(adapter, vf);
4ae196df
AD		 5981
5982 /* set vf mac address */
26ad9178 5983 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 5984
5985 /* enable transmit and receive for vf */
5986 reg = rd32(E1000_VFTE);
5987 wr32(E1000_VFTE, reg | (1 << vf));
5988 reg = rd32(E1000_VFRE);
5989 wr32(E1000_VFRE, reg | (1 << vf));
5990
8fa7e0f7 5991 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 5992
5993 /* reply to reset with ack and vf mac address */
5994 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 5995 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 5996 igb_write_mbx(hw, msgbuf, 3, vf);
5997}
5998
5999static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6000{
b980ac18 6001 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6002 * starting at the second 32 bit word of the msg array
6003 */
f2ca0dbe
AD		 6004 unsigned char *addr = (char *)&msg[1];
6005 int err = -1;
4ae196df 6006
f2ca0dbe
AD		 6007 if (is_valid_ether_addr(addr))
6008 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6009
f2ca0dbe 6010 return err;
4ae196df
AD		 6011}
6012
6013static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6014{
6015 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6016 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6017 u32 msg = E1000_VT_MSGTYPE_NACK;
6018
6019 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6020 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6021 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6022 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6023 vf_data->last_nack = jiffies;
4ae196df
AD		 6024 }
6025}
6026
f2ca0dbe 6027static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6028{
f2ca0dbe
AD		 6029 struct pci_dev *pdev = adapter->pdev;
6030 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6031 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6032 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6033 s32 retval;
6034
f2ca0dbe 6035 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6036
fef45f4c
AD		 6037 if (retval) {
6038 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6039 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6040 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6041 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6042 return;
6043 goto out;
6044 }
4ae196df
AD		 6045
6046 /* this is a message we already processed, do nothing */
6047 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6048 return;
4ae196df 6049
b980ac18 6050 /* until the vf completes a reset it should not be
4ae196df
AD		 6051 * allowed to start any configuration.
6052 */
4ae196df
AD		 6053 if (msgbuf[0] == E1000_VF_RESET) {
6054 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6055 return;
4ae196df
AD		 6056 }
6057
f2ca0dbe 6058 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6059 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6060 return;
6061 retval = -1;
6062 goto out;
4ae196df
AD		 6063 }
6064
6065 switch ((msgbuf[0] & 0xFFFF)) {
6066 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6067 retval = -EINVAL;
6068 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6069 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6070 else
6071 dev_warn(&pdev->dev,
b980ac18
JK		 6072 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6073 vf);
4ae196df 6074 break;
7d5753f0
AD		 6075 case E1000_VF_SET_PROMISC:
6076 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6077 break;
4ae196df
AD		 6078 case E1000_VF_SET_MULTICAST:
6079 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6080 break;
6081 case E1000_VF_SET_LPE:
6082 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6083 break;
6084 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6085 retval = -1;
6086 if (vf_data->pf_vlan)
6087 dev_warn(&pdev->dev,
b980ac18
JK		 6088 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6089 vf);
8151d294
WM		 6090 else
6091 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6092 break;
6093 default:
090b1795 6094 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6095 retval = -1;
6096 break;
6097 }
6098
fef45f4c
AD		 6099 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6100out:
4ae196df
AD		 6101 /* notify the VF of the results of what it sent us */
6102 if (retval)
6103 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6104 else
6105 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6106
4ae196df 6107 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6108}
4ae196df 6109
f2ca0dbe
AD		 6110static void igb_msg_task(struct igb_adapter *adapter)
6111{
6112 struct e1000_hw *hw = &adapter->hw;
6113 u32 vf;
6114
6115 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6116 /* process any reset requests */
6117 if (!igb_check_for_rst(hw, vf))
6118 igb_vf_reset_event(adapter, vf);
6119
6120 /* process any messages pending */
6121 if (!igb_check_for_msg(hw, vf))
6122 igb_rcv_msg_from_vf(adapter, vf);
6123
6124 /* process any acks */
6125 if (!igb_check_for_ack(hw, vf))
6126 igb_rcv_ack_from_vf(adapter, vf);
6127 }
4ae196df
AD		 6128}
6129
68d480c4
AD		 6130/**
6131 * igb_set_uta - Set unicast filter table address
6132 * @adapter: board private structure
6133 *
6134 * The unicast table address is a register array of 32-bit registers.
6135 * The table is meant to be used in a way similar to how the MTA is used
6136 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6137 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6138 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6139 **/
6140static void igb_set_uta(struct igb_adapter *adapter)
6141{
6142 struct e1000_hw *hw = &adapter->hw;
6143 int i;
6144
6145 /* The UTA table only exists on 82576 hardware and newer */
6146 if (hw->mac.type < e1000_82576)
6147 return;
6148
6149 /* we only need to do this if VMDq is enabled */
6150 if (!adapter->vfs_allocated_count)
6151 return;
6152
6153 for (i = 0; i < hw->mac.uta_reg_count; i++)
6154 array_wr32(E1000_UTA, i, ~0);
6155}
6156
9d5c8243 6157/**
b980ac18
JK		 6158 * igb_intr_msi - Interrupt Handler
6159 * @irq: interrupt number
6160 * @data: pointer to a network interface device structure
9d5c8243
AK		 6161 **/
6162static irqreturn_t igb_intr_msi(int irq, void *data)
6163{
047e0030
AD		 6164 struct igb_adapter *adapter = data;
6165 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6166 struct e1000_hw *hw = &adapter->hw;
6167 /* read ICR disables interrupts using IAM */
6168 u32 icr = rd32(E1000_ICR);
6169
047e0030 6170 igb_write_itr(q_vector);
9d5c8243 6171
7f081d40
AD		 6172 if (icr & E1000_ICR_DRSTA)
6173 schedule_work(&adapter->reset_task);
6174
047e0030 6175 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6176 /* HW is reporting DMA is out of sync */
6177 adapter->stats.doosync++;
6178 }
6179
9d5c8243
AK		 6180 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6181 hw->mac.get_link_status = 1;
6182 if (!test_bit(__IGB_DOWN, &adapter->state))
6183 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6184 }
6185
1f6e8178
MV		 6186 if (icr & E1000_ICR_TS) {
6187 u32 tsicr = rd32(E1000_TSICR);
6188
6189 if (tsicr & E1000_TSICR_TXTS) {
6190 /* acknowledge the interrupt */
6191 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6192 /* retrieve hardware timestamp */
6193 schedule_work(&adapter->ptp_tx_work);
6194 }
6195 }
1f6e8178 6196
047e0030 6197 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6198
6199 return IRQ_HANDLED;
6200}
6201
6202/**
b980ac18
JK		 6203 * igb_intr - Legacy Interrupt Handler
6204 * @irq: interrupt number
6205 * @data: pointer to a network interface device structure
9d5c8243
AK		 6206 **/
6207static irqreturn_t igb_intr(int irq, void *data)
6208{
047e0030
AD		 6209 struct igb_adapter *adapter = data;
6210 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6211 struct e1000_hw *hw = &adapter->hw;
6212 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6213 * need for the IMC write
6214 */
9d5c8243 6215 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6216
6217 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6218 * not set, then the adapter didn't send an interrupt
6219 */
9d5c8243
AK		 6220 if (!(icr & E1000_ICR_INT_ASSERTED))
6221 return IRQ_NONE;
6222
0ba82994
AD		 6223 igb_write_itr(q_vector);
6224
7f081d40
AD		 6225 if (icr & E1000_ICR_DRSTA)
6226 schedule_work(&adapter->reset_task);
6227
047e0030 6228 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6229 /* HW is reporting DMA is out of sync */
6230 adapter->stats.doosync++;
6231 }
6232
9d5c8243
AK		 6233 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6234 hw->mac.get_link_status = 1;
6235 /* guard against interrupt when we're going down */
6236 if (!test_bit(__IGB_DOWN, &adapter->state))
6237 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6238 }
6239
1f6e8178
MV		 6240 if (icr & E1000_ICR_TS) {
6241 u32 tsicr = rd32(E1000_TSICR);
6242
6243 if (tsicr & E1000_TSICR_TXTS) {
6244 /* acknowledge the interrupt */
6245 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6246 /* retrieve hardware timestamp */
6247 schedule_work(&adapter->ptp_tx_work);
6248 }
6249 }
1f6e8178 6250
047e0030 6251 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6252
6253 return IRQ_HANDLED;
6254}
6255
c50b52a0 6256static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6257{
047e0030 6258 struct igb_adapter *adapter = q_vector->adapter;
46544258 6259 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6260
0ba82994
AD		 6261 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6262 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6263 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6264 igb_set_itr(q_vector);
46544258 6265 else
047e0030 6266 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6267 }
6268
46544258 6269 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6270 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6271 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6272 else
6273 igb_irq_enable(adapter);
6274 }
9d5c8243
AK		 6275}
6276
46544258 6277/**
b980ac18
JK		 6278 * igb_poll - NAPI Rx polling callback
6279 * @napi: napi polling structure
6280 * @budget: count of how many packets we should handle
46544258
AD		 6281 **/
6282static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6283{
047e0030 6284 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6285 struct igb_q_vector,
6286 napi);
16eb8815 6287 bool clean_complete = true;
9d5c8243 6288
421e02f0 6289#ifdef CONFIG_IGB_DCA
047e0030
AD		 6290 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6291 igb_update_dca(q_vector);
fe4506b6 6292#endif
0ba82994 6293 if (q_vector->tx.ring)
13fde97a 6294 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6295
0ba82994 6296 if (q_vector->rx.ring)
cd392f5c 6297 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6298
16eb8815
AD		 6299 /* If all work not completed, return budget and keep polling */
6300 if (!clean_complete)
6301 return budget;
46544258 6302
9d5c8243 6303 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6304 napi_complete(napi);
6305 igb_ring_irq_enable(q_vector);
9d5c8243 6306
16eb8815 6307 return 0;
9d5c8243 6308}
6d8126f9 6309
9d5c8243 6310/**
b980ac18
JK		 6311 * igb_clean_tx_irq - Reclaim resources after transmit completes
6312 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6313 *
b980ac18 6314 * returns true if ring is completely cleaned
9d5c8243 6315 **/
047e0030 6316static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6317{
047e0030 6318 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6319 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6320 struct igb_tx_buffer *tx_buffer;
f4128785 6321 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6322 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6323 unsigned int budget = q_vector->tx.work_limit;
8542db05 6324 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6325
13fde97a
AD		 6326 if (test_bit(__IGB_DOWN, &adapter->state))
6327 return true;
0e014cb1 6328
06034649 6329 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6330 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6331 i -= tx_ring->count;
9d5c8243 6332
f4128785
AD		 6333 do {
6334 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6335
6336 /* if next_to_watch is not set then there is no work pending */
6337 if (!eop_desc)
6338 break;
13fde97a 6339
f4128785 6340 /* prevent any other reads prior to eop_desc */
70d289bc 6341 read_barrier_depends();
f4128785 6342
13fde97a
AD		 6343 /* if DD is not set pending work has not been completed */
6344 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6345 break;
6346
8542db05
AD		 6347 /* clear next_to_watch to prevent false hangs */
6348 tx_buffer->next_to_watch = NULL;
9d5c8243 6349
ebe42d16
AD		 6350 /* update the statistics for this packet */
6351 total_bytes += tx_buffer->bytecount;
6352 total_packets += tx_buffer->gso_segs;
13fde97a 6353
ebe42d16
AD		 6354 /* free the skb */
6355 dev_kfree_skb_any(tx_buffer->skb);
13fde97a 6356
ebe42d16
AD		 6357 /* unmap skb header data */
6358 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6359 dma_unmap_addr(tx_buffer, dma),
6360 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6361 DMA_TO_DEVICE);
6362
c9f14bf3
AD		 6363 /* clear tx_buffer data */
6364 tx_buffer->skb = NULL;
6365 dma_unmap_len_set(tx_buffer, len, 0);
6366
ebe42d16
AD		 6367 /* clear last DMA location and unmap remaining buffers */
6368 while (tx_desc != eop_desc) {
13fde97a
AD		 6369 tx_buffer++;
6370 tx_desc++;
9d5c8243 6371 i++;
8542db05
AD		 6372 if (unlikely(!i)) {
6373 i -= tx_ring->count;
06034649 6374 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6375 tx_desc = IGB_TX_DESC(tx_ring, 0);
6376 }
ebe42d16
AD		 6377
6378 /* unmap any remaining paged data */
c9f14bf3 6379 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6380 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6381 dma_unmap_addr(tx_buffer, dma),
6382 dma_unmap_len(tx_buffer, len),
ebe42d16 6383 DMA_TO_DEVICE);
c9f14bf3 6384 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6385 }
6386 }
6387
ebe42d16
AD		 6388 /* move us one more past the eop_desc for start of next pkt */
6389 tx_buffer++;
6390 tx_desc++;
6391 i++;
6392 if (unlikely(!i)) {
6393 i -= tx_ring->count;
6394 tx_buffer = tx_ring->tx_buffer_info;
6395 tx_desc = IGB_TX_DESC(tx_ring, 0);
6396 }
f4128785
AD		 6397
6398 /* issue prefetch for next Tx descriptor */
6399 prefetch(tx_desc);
6400
6401 /* update budget accounting */
6402 budget--;
6403 } while (likely(budget));
0e014cb1 6404
bdbc0631
ED		 6405 netdev_tx_completed_queue(txring_txq(tx_ring),
6406 total_packets, total_bytes);
8542db05 6407 i += tx_ring->count;
9d5c8243 6408 tx_ring->next_to_clean = i;
13fde97a
AD		 6409 u64_stats_update_begin(&tx_ring->tx_syncp);
6410 tx_ring->tx_stats.bytes += total_bytes;
6411 tx_ring->tx_stats.packets += total_packets;
6412 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6413 q_vector->tx.total_bytes += total_bytes;
6414 q_vector->tx.total_packets += total_packets;
9d5c8243 6415
6d095fa8 6416 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6417 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6418
9d5c8243 6419 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6420 * check with the clearing of time_stamp and movement of i
6421 */
6d095fa8 6422 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6423 if (tx_buffer->next_to_watch &&
8542db05 6424 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6425 (adapter->tx_timeout_factor * HZ)) &&
6426 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6427
9d5c8243 6428 /* detected Tx unit hang */
59d71989 6429 dev_err(tx_ring->dev,
9d5c8243 6430 "Detected Tx Unit Hang\n"
2d064c06 6431 " Tx Queue <%d>\n"
9d5c8243
AK		 6432 " TDH <%x>\n"
6433 " TDT <%x>\n"
6434 " next_to_use <%x>\n"
6435 " next_to_clean <%x>\n"
9d5c8243
AK		 6436 "buffer_info[next_to_clean]\n"
6437 " time_stamp <%lx>\n"
8542db05 6438 " next_to_watch <%p>\n"
9d5c8243
AK		 6439 " jiffies <%lx>\n"
6440 " desc.status <%x>\n",
2d064c06 6441 tx_ring->queue_index,
238ac817 6442 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6443 readl(tx_ring->tail),
9d5c8243
AK		 6444 tx_ring->next_to_use,
6445 tx_ring->next_to_clean,
8542db05 6446 tx_buffer->time_stamp,
f4128785 6447 tx_buffer->next_to_watch,
9d5c8243 6448 jiffies,
f4128785 6449 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6450 netif_stop_subqueue(tx_ring->netdev,
6451 tx_ring->queue_index);
6452
6453 /* we are about to reset, no point in enabling stuff */
6454 return true;
9d5c8243
AK		 6455 }
6456 }
13fde97a 6457
21ba6fe1 6458#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6459 if (unlikely(total_packets &&
b980ac18
JK		 6460 netif_carrier_ok(tx_ring->netdev) &&
6461 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6462 /* Make sure that anybody stopping the queue after this
6463 * sees the new next_to_clean.
6464 */
6465 smp_mb();
6466 if (__netif_subqueue_stopped(tx_ring->netdev,
6467 tx_ring->queue_index) &&
6468 !(test_bit(__IGB_DOWN, &adapter->state))) {
6469 netif_wake_subqueue(tx_ring->netdev,
6470 tx_ring->queue_index);
6471
6472 u64_stats_update_begin(&tx_ring->tx_syncp);
6473 tx_ring->tx_stats.restart_queue++;
6474 u64_stats_update_end(&tx_ring->tx_syncp);
6475 }
6476 }
6477
6478 return !!budget;
9d5c8243
AK		 6479}
6480
cbc8e55f 6481/**
b980ac18
JK		 6482 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6483 * @rx_ring: rx descriptor ring to store buffers on
6484 * @old_buff: donor buffer to have page reused
cbc8e55f 6485 *
b980ac18 6486 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6487 **/
6488static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6489 struct igb_rx_buffer *old_buff)
6490{
6491 struct igb_rx_buffer *new_buff;
6492 u16 nta = rx_ring->next_to_alloc;
6493
6494 new_buff = &rx_ring->rx_buffer_info[nta];
6495
6496 /* update, and store next to alloc */
6497 nta++;
6498 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6499
6500 /* transfer page from old buffer to new buffer */
6501 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6502
6503 /* sync the buffer for use by the device */
6504 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6505 old_buff->page_offset,
de78d1f9 6506 IGB_RX_BUFSZ,
cbc8e55f
AD		 6507 DMA_FROM_DEVICE);
6508}
6509
74e238ea
AD		 6510static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6511 struct page *page,
6512 unsigned int truesize)
6513{
6514 /* avoid re-using remote pages */
6515 if (unlikely(page_to_nid(page) != numa_node_id()))
6516 return false;
6517
6518#if (PAGE_SIZE < 8192)
6519 /* if we are only owner of page we can reuse it */
6520 if (unlikely(page_count(page) != 1))
6521 return false;
6522
6523 /* flip page offset to other buffer */
6524 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6525
6526 /* since we are the only owner of the page and we need to
6527 * increment it, just set the value to 2 in order to avoid
6528 * an unnecessary locked operation
6529 */
6530 atomic_set(&page->_count, 2);
6531#else
6532 /* move offset up to the next cache line */
6533 rx_buffer->page_offset += truesize;
6534
6535 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6536 return false;
6537
6538 /* bump ref count on page before it is given to the stack */
6539 get_page(page);
6540#endif
6541
6542 return true;
6543}
6544
cbc8e55f 6545/**
b980ac18
JK		 6546 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6547 * @rx_ring: rx descriptor ring to transact packets on
6548 * @rx_buffer: buffer containing page to add
6549 * @rx_desc: descriptor containing length of buffer written by hardware
6550 * @skb: sk_buff to place the data into
cbc8e55f 6551 *
b980ac18
JK		 6552 * This function will add the data contained in rx_buffer->page to the skb.
6553 * This is done either through a direct copy if the data in the buffer is
6554 * less than the skb header size, otherwise it will just attach the page as
6555 * a frag to the skb.
cbc8e55f 6556 *
b980ac18
JK		 6557 * The function will then update the page offset if necessary and return
6558 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6559 **/
6560static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6561 struct igb_rx_buffer *rx_buffer,
6562 union e1000_adv_rx_desc *rx_desc,
6563 struct sk_buff *skb)
6564{
6565 struct page *page = rx_buffer->page;
6566 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6567#if (PAGE_SIZE < 8192)
6568 unsigned int truesize = IGB_RX_BUFSZ;
6569#else
6570 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6571#endif
cbc8e55f
AD		 6572
6573 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6574 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6575
cbc8e55f
AD		 6576 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6577 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6578 va += IGB_TS_HDR_LEN;
6579 size -= IGB_TS_HDR_LEN;
6580 }
6581
cbc8e55f
AD		 6582 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6583
6584 /* we can reuse buffer as-is, just make sure it is local */
6585 if (likely(page_to_nid(page) == numa_node_id()))
6586 return true;
6587
6588 /* this page cannot be reused so discard it */
6589 put_page(page);
6590 return false;
6591 }
6592
6593 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6594 rx_buffer->page_offset, size, truesize);
cbc8e55f 6595
74e238ea
AD		 6596 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6597}
cbc8e55f 6598
2e334eee
AD		 6599static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6600 union e1000_adv_rx_desc *rx_desc,
6601 struct sk_buff *skb)
6602{
6603 struct igb_rx_buffer *rx_buffer;
6604 struct page *page;
6605
6606 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6607
2e334eee
AD		 6608 page = rx_buffer->page;
6609 prefetchw(page);
6610
6611 if (likely(!skb)) {
6612 void *page_addr = page_address(page) +
6613 rx_buffer->page_offset;
6614
6615 /* prefetch first cache line of first page */
6616 prefetch(page_addr);
6617#if L1_CACHE_BYTES < 128
6618 prefetch(page_addr + L1_CACHE_BYTES);
6619#endif
6620
6621 /* allocate a skb to store the frags */
6622 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6623 IGB_RX_HDR_LEN);
6624 if (unlikely(!skb)) {
6625 rx_ring->rx_stats.alloc_failed++;
6626 return NULL;
6627 }
6628
b980ac18 6629 /* we will be copying header into skb->data in
2e334eee
AD		 6630 * pskb_may_pull so it is in our interest to prefetch
6631 * it now to avoid a possible cache miss
6632 */
6633 prefetchw(skb->data);
6634 }
6635
6636 /* we are reusing so sync this buffer for CPU use */
6637 dma_sync_single_range_for_cpu(rx_ring->dev,
6638 rx_buffer->dma,
6639 rx_buffer->page_offset,
de78d1f9 6640 IGB_RX_BUFSZ,
2e334eee
AD		 6641 DMA_FROM_DEVICE);
6642
6643 /* pull page into skb */
6644 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6645 /* hand second half of page back to the ring */
6646 igb_reuse_rx_page(rx_ring, rx_buffer);
6647 } else {
6648 /* we are not reusing the buffer so unmap it */
6649 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6650 PAGE_SIZE, DMA_FROM_DEVICE);
6651 }
6652
6653 /* clear contents of rx_buffer */
6654 rx_buffer->page = NULL;
6655
6656 return skb;
6657}
6658
cd392f5c 6659static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6660 union e1000_adv_rx_desc *rx_desc,
6661 struct sk_buff *skb)
9d5c8243 6662{
bc8acf2c 6663 skb_checksum_none_assert(skb);
9d5c8243 6664
294e7d78 6665 /* Ignore Checksum bit is set */
3ceb90fd 6666 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6667 return;
6668
6669 /* Rx checksum disabled via ethtool */
6670 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6671 return;
85ad76b2 6672
9d5c8243 6673 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6674 if (igb_test_staterr(rx_desc,
6675 E1000_RXDEXT_STATERR_TCPE |
6676 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6677 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6678 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6679 * packets, (aka let the stack check the crc32c)
6680 */
866cff06
AD		 6681 if (!((skb->len == 60) &&
6682 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6683 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6684 ring->rx_stats.csum_err++;
12dcd86b
ED		 6685 u64_stats_update_end(&ring->rx_syncp);
6686 }
9d5c8243 6687 /* let the stack verify checksum errors */
9d5c8243
AK		 6688 return;
6689 }
6690 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6691 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6692 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6693 skb->ip_summed = CHECKSUM_UNNECESSARY;
6694
3ceb90fd
AD		 6695 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6696 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6697}
6698
077887c3
AD		 6699static inline void igb_rx_hash(struct igb_ring *ring,
6700 union e1000_adv_rx_desc *rx_desc,
6701 struct sk_buff *skb)
6702{
6703 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6704 skb_set_hash(skb,
6705 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6706 PKT_HASH_TYPE_L3);
077887c3
AD		 6707}
6708
2e334eee 6709/**
b980ac18
JK		 6710 * igb_is_non_eop - process handling of non-EOP buffers
6711 * @rx_ring: Rx ring being processed
6712 * @rx_desc: Rx descriptor for current buffer
6713 * @skb: current socket buffer containing buffer in progress
2e334eee 6714 *
b980ac18
JK		 6715 * This function updates next to clean. If the buffer is an EOP buffer
6716 * this function exits returning false, otherwise it will place the
6717 * sk_buff in the next buffer to be chained and return true indicating
6718 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6719 **/
6720static bool igb_is_non_eop(struct igb_ring *rx_ring,
6721 union e1000_adv_rx_desc *rx_desc)
6722{
6723 u32 ntc = rx_ring->next_to_clean + 1;
6724
6725 /* fetch, update, and store next to clean */
6726 ntc = (ntc < rx_ring->count) ? ntc : 0;
6727 rx_ring->next_to_clean = ntc;
6728
6729 prefetch(IGB_RX_DESC(rx_ring, ntc));
6730
6731 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6732 return false;
6733
6734 return true;
6735}
6736
1a1c225b 6737/**
b980ac18
JK		 6738 * igb_get_headlen - determine size of header for LRO/GRO
6739 * @data: pointer to the start of the headers
6740 * @max_len: total length of section to find headers in
1a1c225b 6741 *
b980ac18
JK		 6742 * This function is meant to determine the length of headers that will
6743 * be recognized by hardware for LRO, and GRO offloads. The main
6744 * motivation of doing this is to only perform one pull for IPv4 TCP
6745 * packets so that we can do basic things like calculating the gso_size
6746 * based on the average data per packet.
1a1c225b
AD		 6747 **/
6748static unsigned int igb_get_headlen(unsigned char *data,
6749 unsigned int max_len)
6750{
6751 union {
6752 unsigned char *network;
6753 /* l2 headers */
6754 struct ethhdr *eth;
6755 struct vlan_hdr *vlan;
6756 /* l3 headers */
6757 struct iphdr *ipv4;
6758 struct ipv6hdr *ipv6;
6759 } hdr;
6760 __be16 protocol;
6761 u8 nexthdr = 0; /* default to not TCP */
6762 u8 hlen;
6763
6764 /* this should never happen, but better safe than sorry */
6765 if (max_len < ETH_HLEN)
6766 return max_len;
6767
6768 /* initialize network frame pointer */
6769 hdr.network = data;
6770
6771 /* set first protocol and move network header forward */
6772 protocol = hdr.eth->h_proto;
6773 hdr.network += ETH_HLEN;
6774
6775 /* handle any vlan tag if present */
7c4d16ff 6776 if (protocol == htons(ETH_P_8021Q)) {
1a1c225b
AD		 6777 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6778 return max_len;
6779
6780 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6781 hdr.network += VLAN_HLEN;
6782 }
6783
6784 /* handle L3 protocols */
7c4d16ff 6785 if (protocol == htons(ETH_P_IP)) {
1a1c225b
AD		 6786 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6787 return max_len;
6788
6789 /* access ihl as a u8 to avoid unaligned access on ia64 */
6790 hlen = (hdr.network[0] & 0x0F) << 2;
6791
6792 /* verify hlen meets minimum size requirements */
6793 if (hlen < sizeof(struct iphdr))
6794 return hdr.network - data;
6795
f2fb4ab2 6796 /* record next protocol if header is present */
b9555f66 6797 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
f2fb4ab2 6798 nexthdr = hdr.ipv4->protocol;
7c4d16ff 6799 } else if (protocol == htons(ETH_P_IPV6)) {
1a1c225b
AD		 6800 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6801 return max_len;
6802
6803 /* record next protocol */
6804 nexthdr = hdr.ipv6->nexthdr;
f2fb4ab2 6805 hlen = sizeof(struct ipv6hdr);
1a1c225b
AD		 6806 } else {
6807 return hdr.network - data;
6808 }
6809
f2fb4ab2
AD		 6810 /* relocate pointer to start of L4 header */
6811 hdr.network += hlen;
6812
1a1c225b
AD		 6813 /* finally sort out TCP */
6814 if (nexthdr == IPPROTO_TCP) {
6815 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6816 return max_len;
6817
6818 /* access doff as a u8 to avoid unaligned access on ia64 */
6819 hlen = (hdr.network[12] & 0xF0) >> 2;
6820
6821 /* verify hlen meets minimum size requirements */
6822 if (hlen < sizeof(struct tcphdr))
6823 return hdr.network - data;
6824
6825 hdr.network += hlen;
6826 } else if (nexthdr == IPPROTO_UDP) {
6827 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6828 return max_len;
6829
6830 hdr.network += sizeof(struct udphdr);
6831 }
6832
b980ac18 6833 /* If everything has gone correctly hdr.network should be the
1a1c225b
AD		 6834 * data section of the packet and will be the end of the header.
6835 * If not then it probably represents the end of the last recognized
6836 * header.
6837 */
6838 if ((hdr.network - data) < max_len)
6839 return hdr.network - data;
6840 else
6841 return max_len;
6842}
6843
6844/**
b980ac18
JK		 6845 * igb_pull_tail - igb specific version of skb_pull_tail
6846 * @rx_ring: rx descriptor ring packet is being transacted on
6847 * @rx_desc: pointer to the EOP Rx descriptor
6848 * @skb: pointer to current skb being adjusted
1a1c225b 6849 *
b980ac18
JK		 6850 * This function is an igb specific version of __pskb_pull_tail. The
6851 * main difference between this version and the original function is that
6852 * this function can make several assumptions about the state of things
6853 * that allow for significant optimizations versus the standard function.
6854 * As a result we can do things like drop a frag and maintain an accurate
6855 * truesize for the skb.
1a1c225b
AD		 6856 */
6857static void igb_pull_tail(struct igb_ring *rx_ring,
6858 union e1000_adv_rx_desc *rx_desc,
6859 struct sk_buff *skb)
2d94d8ab 6860{
1a1c225b
AD		 6861 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6862 unsigned char *va;
6863 unsigned int pull_len;
6864
b980ac18 6865 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6866 * working with pages allocated out of the lomem pool per
6867 * alloc_page(GFP_ATOMIC)
2d94d8ab 6868 */
1a1c225b
AD		 6869 va = skb_frag_address(frag);
6870
1a1c225b
AD		 6871 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6872 /* retrieve timestamp from buffer */
6873 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6874
6875 /* update pointers to remove timestamp header */
6876 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6877 frag->page_offset += IGB_TS_HDR_LEN;
6878 skb->data_len -= IGB_TS_HDR_LEN;
6879 skb->len -= IGB_TS_HDR_LEN;
6880
6881 /* move va to start of packet data */
6882 va += IGB_TS_HDR_LEN;
6883 }
6884
b980ac18 6885 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6886 * 60 bytes if the skb->len is less than 60 for skb_pad.
6887 */
6888 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6889
6890 /* align pull length to size of long to optimize memcpy performance */
6891 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6892
6893 /* update all of the pointers */
6894 skb_frag_size_sub(frag, pull_len);
6895 frag->page_offset += pull_len;
6896 skb->data_len -= pull_len;
6897 skb->tail += pull_len;
6898}
6899
6900/**
b980ac18
JK		 6901 * igb_cleanup_headers - Correct corrupted or empty headers
6902 * @rx_ring: rx descriptor ring packet is being transacted on
6903 * @rx_desc: pointer to the EOP Rx descriptor
6904 * @skb: pointer to current skb being fixed
1a1c225b 6905 *
b980ac18
JK		 6906 * Address the case where we are pulling data in on pages only
6907 * and as such no data is present in the skb header.
1a1c225b 6908 *
b980ac18
JK		 6909 * In addition if skb is not at least 60 bytes we need to pad it so that
6910 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6911 *
b980ac18 6912 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6913 **/
6914static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6915 union e1000_adv_rx_desc *rx_desc,
6916 struct sk_buff *skb)
6917{
1a1c225b
AD		 6918 if (unlikely((igb_test_staterr(rx_desc,
6919 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6920 struct net_device *netdev = rx_ring->netdev;
6921 if (!(netdev->features & NETIF_F_RXALL)) {
6922 dev_kfree_skb_any(skb);
6923 return true;
6924 }
6925 }
6926
6927 /* place header in linear portion of buffer */
6928 if (skb_is_nonlinear(skb))
6929 igb_pull_tail(rx_ring, rx_desc, skb);
6930
6931 /* if skb_pad returns an error the skb was freed */
6932 if (unlikely(skb->len < 60)) {
6933 int pad_len = 60 - skb->len;
6934
6935 if (skb_pad(skb, pad_len))
6936 return true;
6937 __skb_put(skb, pad_len);
6938 }
6939
6940 return false;
2d94d8ab
AD		 6941}
6942
db2ee5bd 6943/**
b980ac18
JK		 6944 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6945 * @rx_ring: rx descriptor ring packet is being transacted on
6946 * @rx_desc: pointer to the EOP Rx descriptor
6947 * @skb: pointer to current skb being populated
db2ee5bd 6948 *
b980ac18
JK		 6949 * This function checks the ring, descriptor, and packet information in
6950 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6951 * other fields within the skb.
db2ee5bd
AD		 6952 **/
6953static void igb_process_skb_fields(struct igb_ring *rx_ring,
6954 union e1000_adv_rx_desc *rx_desc,
6955 struct sk_buff *skb)
6956{
6957 struct net_device *dev = rx_ring->netdev;
6958
6959 igb_rx_hash(rx_ring, rx_desc, skb);
6960
6961 igb_rx_checksum(rx_ring, rx_desc, skb);
6962
5499a968
JK		 6963 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6964 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6965 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6966
f646968f 6967 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6968 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6969 u16 vid;
9005df38 6970
db2ee5bd
AD		 6971 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6972 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6973 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6974 else
6975 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6976
86a9bad3 6977 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6978 }
6979
6980 skb_record_rx_queue(skb, rx_ring->queue_index);
6981
6982 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6983}
6984
2e334eee 6985static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6986{
0ba82994 6987 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6988 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6989 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6990 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6991
57ba34c9 6992 while (likely(total_packets < budget)) {
2e334eee 6993 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6994
2e334eee
AD		 6995 /* return some buffers to hardware, one at a time is too slow */
6996 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6997 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6998 cleaned_count = 0;
6999 }
bf36c1a0 7000
2e334eee 7001 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 7002
2e334eee
AD		 7003 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
7004 break;
9d5c8243 7005
74e238ea
AD		 7006 /* This memory barrier is needed to keep us from reading
7007 * any other fields out of the rx_desc until we know the
7008 * RXD_STAT_DD bit is set
7009 */
7010 rmb();
7011
2e334eee 7012 /* retrieve a buffer from the ring */
f9d40f6a 7013 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 7014
2e334eee
AD		 7015 /* exit if we failed to retrieve a buffer */
7016 if (!skb)
7017 break;
1a1c225b 7018
2e334eee 7019 cleaned_count++;
1a1c225b 7020
2e334eee
AD		 7021 /* fetch next buffer in frame if non-eop */
7022 if (igb_is_non_eop(rx_ring, rx_desc))
7023 continue;
1a1c225b
AD		 7024
7025 /* verify the packet layout is correct */
7026 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
7027 skb = NULL;
7028 continue;
9d5c8243 7029 }
9d5c8243 7030
db2ee5bd 7031 /* probably a little skewed due to removing CRC */
3ceb90fd 7032 total_bytes += skb->len;
3ceb90fd 7033
db2ee5bd
AD		 7034 /* populate checksum, timestamp, VLAN, and protocol */
7035 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 7036
b2cb09b1 7037 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 7038
1a1c225b
AD		 7039 /* reset skb pointer */
7040 skb = NULL;
7041
2e334eee
AD		 7042 /* update budget accounting */
7043 total_packets++;
57ba34c9 7044 }
bf36c1a0 7045
1a1c225b
AD		 7046 /* place incomplete frames back on ring for completion */
7047 rx_ring->skb = skb;
7048
12dcd86b 7049 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 7050 rx_ring->rx_stats.packets += total_packets;
7051 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 7052 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 7053 q_vector->rx.total_packets += total_packets;
7054 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 7055
7056 if (cleaned_count)
cd392f5c 7057 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 7058
da1f1dfe 7059 return total_packets < budget;
9d5c8243
AK		 7060}
7061
c023cd88 7062static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 7063 struct igb_rx_buffer *bi)
c023cd88
AD		 7064{
7065 struct page *page = bi->page;
cbc8e55f 7066 dma_addr_t dma;
c023cd88 7067
cbc8e55f
AD		 7068 /* since we are recycling buffers we should seldom need to alloc */
7069 if (likely(page))
c023cd88
AD		 7070 return true;
7071
cbc8e55f
AD		 7072 /* alloc new page for storage */
7073 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
7074 if (unlikely(!page)) {
7075 rx_ring->rx_stats.alloc_failed++;
7076 return false;
c023cd88
AD		 7077 }
7078
cbc8e55f
AD		 7079 /* map page for use */
7080 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 7081
b980ac18 7082 /* if mapping failed free memory back to system since
cbc8e55f
AD		 7083 * there isn't much point in holding memory we can't use
7084 */
1a1c225b 7085 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 7086 __free_page(page);
7087
c023cd88
AD		 7088 rx_ring->rx_stats.alloc_failed++;
7089 return false;
7090 }
7091
1a1c225b 7092 bi->dma = dma;
cbc8e55f
AD		 7093 bi->page = page;
7094 bi->page_offset = 0;
1a1c225b 7095
c023cd88
AD		 7096 return true;
7097}
7098
9d5c8243 7099/**
b980ac18
JK		 7100 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7101 * @adapter: address of board private structure
9d5c8243 7102 **/
cd392f5c 7103void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7104{
9d5c8243 7105 union e1000_adv_rx_desc *rx_desc;
06034649 7106 struct igb_rx_buffer *bi;
c023cd88 7107 u16 i = rx_ring->next_to_use;
9d5c8243 7108
cbc8e55f
AD		 7109 /* nothing to do */
7110 if (!cleaned_count)
7111 return;
7112
60136906 7113 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7114 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7115 i -= rx_ring->count;
9d5c8243 7116
cbc8e55f 7117 do {
1a1c225b 7118 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7119 break;
9d5c8243 7120
b980ac18 7121 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7122 * because each write-back erases this info.
7123 */
f9d40f6a 7124 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7125
c023cd88
AD		 7126 rx_desc++;
7127 bi++;
9d5c8243 7128 i++;
c023cd88 7129 if (unlikely(!i)) {
60136906 7130 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7131 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7132 i -= rx_ring->count;
7133 }
7134
7135 /* clear the hdr_addr for the next_to_use descriptor */
7136 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7137
7138 cleaned_count--;
7139 } while (cleaned_count);
9d5c8243 7140
c023cd88
AD		 7141 i += rx_ring->count;
7142
9d5c8243 7143 if (rx_ring->next_to_use != i) {
cbc8e55f 7144 /* record the next descriptor to use */
9d5c8243 7145 rx_ring->next_to_use = i;
9d5c8243 7146
cbc8e55f
AD		 7147 /* update next to alloc since we have filled the ring */
7148 rx_ring->next_to_alloc = i;
7149
b980ac18 7150 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7151 * know there are new descriptors to fetch. (Only
7152 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7153 * such as IA-64).
7154 */
9d5c8243 7155 wmb();
fce99e34 7156 writel(i, rx_ring->tail);
9d5c8243
AK		 7157 }
7158}
7159
7160/**
7161 * igb_mii_ioctl -
7162 * @netdev:
7163 * @ifreq:
7164 * @cmd:
7165 **/
7166static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7167{
7168 struct igb_adapter *adapter = netdev_priv(netdev);
7169 struct mii_ioctl_data *data = if_mii(ifr);
7170
7171 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7172 return -EOPNOTSUPP;
7173
7174 switch (cmd) {
7175 case SIOCGMIIPHY:
7176 data->phy_id = adapter->hw.phy.addr;
7177 break;
7178 case SIOCGMIIREG:
f5f4cf08 7179 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7180 &data->val_out))
9d5c8243
AK		 7181 return -EIO;
7182 break;
7183 case SIOCSMIIREG:
7184 default:
7185 return -EOPNOTSUPP;
7186 }
7187 return 0;
7188}
7189
7190/**
7191 * igb_ioctl -
7192 * @netdev:
7193 * @ifreq:
7194 * @cmd:
7195 **/
7196static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7197{
7198 switch (cmd) {
7199 case SIOCGMIIPHY:
7200 case SIOCGMIIREG:
7201 case SIOCSMIIREG:
7202 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7203 case SIOCGHWTSTAMP:
7204 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7205 case SIOCSHWTSTAMP:
6ab5f7b2 7206 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7207 default:
7208 return -EOPNOTSUPP;
7209 }
7210}
7211
009bc06e
AD		 7212s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7213{
7214 struct igb_adapter *adapter = hw->back;
009bc06e 7215
23d028cc 7216 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7217 return -E1000_ERR_CONFIG;
7218
009bc06e
AD		 7219 return 0;
7220}
7221
7222s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7223{
7224 struct igb_adapter *adapter = hw->back;
009bc06e 7225
23d028cc 7226 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7227 return -E1000_ERR_CONFIG;
7228
009bc06e
AD		 7229 return 0;
7230}
7231
c8f44aff 7232static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7233{
7234 struct igb_adapter *adapter = netdev_priv(netdev);
7235 struct e1000_hw *hw = &adapter->hw;
7236 u32 ctrl, rctl;
f646968f 7237 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7238
5faf030c 7239 if (enable) {
9d5c8243
AK		 7240 /* enable VLAN tag insert/strip */
7241 ctrl = rd32(E1000_CTRL);
7242 ctrl |= E1000_CTRL_VME;
7243 wr32(E1000_CTRL, ctrl);
7244
51466239 7245 /* Disable CFI check */
9d5c8243 7246 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7247 rctl &= ~E1000_RCTL_CFIEN;
7248 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7249 } else {
7250 /* disable VLAN tag insert/strip */
7251 ctrl = rd32(E1000_CTRL);
7252 ctrl &= ~E1000_CTRL_VME;
7253 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7254 }
7255
e1739522 7256 igb_rlpml_set(adapter);
9d5c8243
AK		 7257}
7258
80d5c368
PM		 7259static int igb_vlan_rx_add_vid(struct net_device *netdev,
7260 __be16 proto, u16 vid)
9d5c8243
AK		 7261{
7262 struct igb_adapter *adapter = netdev_priv(netdev);
7263 struct e1000_hw *hw = &adapter->hw;
4ae196df 7264 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7265
51466239
AD		 7266 /* attempt to add filter to vlvf array */
7267 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7268
51466239
AD		 7269 /* add the filter since PF can receive vlans w/o entry in vlvf */
7270 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7271
7272 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7273
7274 return 0;
9d5c8243
AK		 7275}
7276
80d5c368
PM		 7277static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7278 __be16 proto, u16 vid)
9d5c8243
AK		 7279{
7280 struct igb_adapter *adapter = netdev_priv(netdev);
7281 struct e1000_hw *hw = &adapter->hw;
4ae196df 7282 int pf_id = adapter->vfs_allocated_count;
51466239 7283 s32 err;
9d5c8243 7284
51466239
AD		 7285 /* remove vlan from VLVF table array */
7286 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7287
51466239
AD		 7288 /* if vid was not present in VLVF just remove it from table */
7289 if (err)
4ae196df 7290 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7291
7292 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7293
7294 return 0;
9d5c8243
AK		 7295}
7296
7297static void igb_restore_vlan(struct igb_adapter *adapter)
7298{
b2cb09b1 7299 u16 vid;
9d5c8243 7300
5faf030c
AD		 7301 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7302
b2cb09b1 7303 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7304 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7305}
7306
14ad2513 7307int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7308{
090b1795 7309 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7310 struct e1000_mac_info *mac = &adapter->hw.mac;
7311
7312 mac->autoneg = 0;
7313
14ad2513 7314 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7315 * for the switch() below to work
7316 */
14ad2513
DD		 7317 if ((spd & 1) || (dplx & ~1))
7318 goto err_inval;
7319
f502ef7d
AA		 7320 /* Fiber NIC's only allow 1000 gbps Full duplex
7321 * and 100Mbps Full duplex for 100baseFx sfp
7322 */
7323 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7324 switch (spd + dplx) {
7325 case SPEED_10 + DUPLEX_HALF:
7326 case SPEED_10 + DUPLEX_FULL:
7327 case SPEED_100 + DUPLEX_HALF:
7328 goto err_inval;
7329 default:
7330 break;
7331 }
7332 }
cd2638a8 7333
14ad2513 7334 switch (spd + dplx) {
9d5c8243
AK		 7335 case SPEED_10 + DUPLEX_HALF:
7336 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7337 break;
7338 case SPEED_10 + DUPLEX_FULL:
7339 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7340 break;
7341 case SPEED_100 + DUPLEX_HALF:
7342 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7343 break;
7344 case SPEED_100 + DUPLEX_FULL:
7345 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7346 break;
7347 case SPEED_1000 + DUPLEX_FULL:
7348 mac->autoneg = 1;
7349 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7350 break;
7351 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7352 default:
14ad2513 7353 goto err_inval;
9d5c8243 7354 }
8376dad0
JB		 7355
7356 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7357 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7358
9d5c8243 7359 return 0;
14ad2513
DD		 7360
7361err_inval:
7362 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7363 return -EINVAL;
9d5c8243
AK		 7364}
7365
749ab2cd
YZ		 7366static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7367 bool runtime)
9d5c8243
AK		 7368{
7369 struct net_device *netdev = pci_get_drvdata(pdev);
7370 struct igb_adapter *adapter = netdev_priv(netdev);
7371 struct e1000_hw *hw = &adapter->hw;
2d064c06 7372 u32 ctrl, rctl, status;
749ab2cd 7373 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7374#ifdef CONFIG_PM
7375 int retval = 0;
7376#endif
7377
7378 netif_device_detach(netdev);
7379
a88f10ec 7380 if (netif_running(netdev))
749ab2cd 7381 __igb_close(netdev, true);
a88f10ec 7382
047e0030 7383 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7384
7385#ifdef CONFIG_PM
7386 retval = pci_save_state(pdev);
7387 if (retval)
7388 return retval;
7389#endif
7390
7391 status = rd32(E1000_STATUS);
7392 if (status & E1000_STATUS_LU)
7393 wufc &= ~E1000_WUFC_LNKC;
7394
7395 if (wufc) {
7396 igb_setup_rctl(adapter);
ff41f8dc 7397 igb_set_rx_mode(netdev);
9d5c8243
AK		 7398
7399 /* turn on all-multi mode if wake on multicast is enabled */
7400 if (wufc & E1000_WUFC_MC) {
7401 rctl = rd32(E1000_RCTL);
7402 rctl |= E1000_RCTL_MPE;
7403 wr32(E1000_RCTL, rctl);
7404 }
7405
7406 ctrl = rd32(E1000_CTRL);
7407 /* advertise wake from D3Cold */
7408 #define E1000_CTRL_ADVD3WUC 0x00100000
7409 /* phy power management enable */
7410 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7411 ctrl |= E1000_CTRL_ADVD3WUC;
7412 wr32(E1000_CTRL, ctrl);
7413
9d5c8243 7414 /* Allow time for pending master requests to run */
330a6d6a 7415 igb_disable_pcie_master(hw);
9d5c8243
AK		 7416
7417 wr32(E1000_WUC, E1000_WUC_PME_EN);
7418 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7419 } else {
7420 wr32(E1000_WUC, 0);
7421 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7422 }
7423
3fe7c4c9
RW		 7424 *enable_wake = wufc || adapter->en_mng_pt;
7425 if (!*enable_wake)
88a268c1
NN		 7426 igb_power_down_link(adapter);
7427 else
7428 igb_power_up_link(adapter);
9d5c8243
AK		 7429
7430 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7431 * would have already happened in close and is redundant.
7432 */
9d5c8243
AK		 7433 igb_release_hw_control(adapter);
7434
7435 pci_disable_device(pdev);
7436
9d5c8243
AK		 7437 return 0;
7438}
7439
7440#ifdef CONFIG_PM
d9dd966d 7441#ifdef CONFIG_PM_SLEEP
749ab2cd 7442static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7443{
7444 int retval;
7445 bool wake;
749ab2cd 7446 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7447
749ab2cd 7448 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7449 if (retval)
7450 return retval;
7451
7452 if (wake) {
7453 pci_prepare_to_sleep(pdev);
7454 } else {
7455 pci_wake_from_d3(pdev, false);
7456 pci_set_power_state(pdev, PCI_D3hot);
7457 }
7458
7459 return 0;
7460}
d9dd966d 7461#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7462
749ab2cd 7463static int igb_resume(struct device *dev)
9d5c8243 7464{
749ab2cd 7465 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7466 struct net_device *netdev = pci_get_drvdata(pdev);
7467 struct igb_adapter *adapter = netdev_priv(netdev);
7468 struct e1000_hw *hw = &adapter->hw;
7469 u32 err;
7470
7471 pci_set_power_state(pdev, PCI_D0);
7472 pci_restore_state(pdev);
b94f2d77 7473 pci_save_state(pdev);
42bfd33a 7474
aed5dec3 7475 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7476 if (err) {
7477 dev_err(&pdev->dev,
7478 "igb: Cannot enable PCI device from suspend\n");
7479 return err;
7480 }
7481 pci_set_master(pdev);
7482
7483 pci_enable_wake(pdev, PCI_D3hot, 0);
7484 pci_enable_wake(pdev, PCI_D3cold, 0);
7485
53c7d064 7486 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7487 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7488 return -ENOMEM;
9d5c8243
AK		 7489 }
7490
9d5c8243 7491 igb_reset(adapter);
a8564f03
AD		 7492
7493 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7494 * driver.
7495 */
a8564f03
AD		 7496 igb_get_hw_control(adapter);
7497
9d5c8243
AK		 7498 wr32(E1000_WUS, ~0);
7499
749ab2cd 7500 if (netdev->flags & IFF_UP) {
0c2cc02e 7501 rtnl_lock();
749ab2cd 7502 err = __igb_open(netdev, true);
0c2cc02e 7503 rtnl_unlock();
a88f10ec
AD		 7504 if (err)
7505 return err;
7506 }
9d5c8243
AK		 7507
7508 netif_device_attach(netdev);
749ab2cd
YZ		 7509 return 0;
7510}
7511
7512#ifdef CONFIG_PM_RUNTIME
7513static int igb_runtime_idle(struct device *dev)
7514{
7515 struct pci_dev *pdev = to_pci_dev(dev);
7516 struct net_device *netdev = pci_get_drvdata(pdev);
7517 struct igb_adapter *adapter = netdev_priv(netdev);
7518
7519 if (!igb_has_link(adapter))
7520 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7521
7522 return -EBUSY;
7523}
7524
7525static int igb_runtime_suspend(struct device *dev)
7526{
7527 struct pci_dev *pdev = to_pci_dev(dev);
7528 int retval;
7529 bool wake;
7530
7531 retval = __igb_shutdown(pdev, &wake, 1);
7532 if (retval)
7533 return retval;
7534
7535 if (wake) {
7536 pci_prepare_to_sleep(pdev);
7537 } else {
7538 pci_wake_from_d3(pdev, false);
7539 pci_set_power_state(pdev, PCI_D3hot);
7540 }
9d5c8243 7541
9d5c8243
AK		 7542 return 0;
7543}
749ab2cd
YZ		 7544
7545static int igb_runtime_resume(struct device *dev)
7546{
7547 return igb_resume(dev);
7548}
7549#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7550#endif
7551
7552static void igb_shutdown(struct pci_dev *pdev)
7553{
3fe7c4c9
RW		 7554 bool wake;
7555
749ab2cd 7556 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7557
7558 if (system_state == SYSTEM_POWER_OFF) {
7559 pci_wake_from_d3(pdev, wake);
7560 pci_set_power_state(pdev, PCI_D3hot);
7561 }
9d5c8243
AK		 7562}
7563
fa44f2f1
GR		 7564#ifdef CONFIG_PCI_IOV
7565static int igb_sriov_reinit(struct pci_dev *dev)
7566{
7567 struct net_device *netdev = pci_get_drvdata(dev);
7568 struct igb_adapter *adapter = netdev_priv(netdev);
7569 struct pci_dev *pdev = adapter->pdev;
7570
7571 rtnl_lock();
7572
7573 if (netif_running(netdev))
7574 igb_close(netdev);
7575
7576 igb_clear_interrupt_scheme(adapter);
7577
7578 igb_init_queue_configuration(adapter);
7579
7580 if (igb_init_interrupt_scheme(adapter, true)) {
7581 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7582 return -ENOMEM;
7583 }
7584
7585 if (netif_running(netdev))
7586 igb_open(netdev);
7587
7588 rtnl_unlock();
7589
7590 return 0;
7591}
7592
7593static int igb_pci_disable_sriov(struct pci_dev *dev)
7594{
7595 int err = igb_disable_sriov(dev);
7596
7597 if (!err)
7598 err = igb_sriov_reinit(dev);
7599
7600 return err;
7601}
7602
7603static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7604{
7605 int err = igb_enable_sriov(dev, num_vfs);
7606
7607 if (err)
7608 goto out;
7609
7610 err = igb_sriov_reinit(dev);
7611 if (!err)
7612 return num_vfs;
7613
7614out:
7615 return err;
7616}
7617
7618#endif
7619static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7620{
7621#ifdef CONFIG_PCI_IOV
7622 if (num_vfs == 0)
7623 return igb_pci_disable_sriov(dev);
7624 else
7625 return igb_pci_enable_sriov(dev, num_vfs);
7626#endif
7627 return 0;
7628}
7629
9d5c8243 7630#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7631/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7632 * without having to re-enable interrupts. It's not called while
7633 * the interrupt routine is executing.
7634 */
7635static void igb_netpoll(struct net_device *netdev)
7636{
7637 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7638 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7639 struct igb_q_vector *q_vector;
9d5c8243 7640 int i;
9d5c8243 7641
047e0030 7642 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7643 q_vector = adapter->q_vector[i];
cd14ef54 7644 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7645 wr32(E1000_EIMC, q_vector->eims_value);
7646 else
7647 igb_irq_disable(adapter);
047e0030 7648 napi_schedule(&q_vector->napi);
eebbbdba 7649 }
9d5c8243
AK		 7650}
7651#endif /* CONFIG_NET_POLL_CONTROLLER */
7652
7653/**
b980ac18
JK		 7654 * igb_io_error_detected - called when PCI error is detected
7655 * @pdev: Pointer to PCI device
7656 * @state: The current pci connection state
9d5c8243 7657 *
b980ac18
JK		 7658 * This function is called after a PCI bus error affecting
7659 * this device has been detected.
7660 **/
9d5c8243
AK		 7661static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7662 pci_channel_state_t state)
7663{
7664 struct net_device *netdev = pci_get_drvdata(pdev);
7665 struct igb_adapter *adapter = netdev_priv(netdev);
7666
7667 netif_device_detach(netdev);
7668
59ed6eec
AD		 7669 if (state == pci_channel_io_perm_failure)
7670 return PCI_ERS_RESULT_DISCONNECT;
7671
9d5c8243
AK		 7672 if (netif_running(netdev))
7673 igb_down(adapter);
7674 pci_disable_device(pdev);
7675
7676 /* Request a slot slot reset. */
7677 return PCI_ERS_RESULT_NEED_RESET;
7678}
7679
7680/**
b980ac18
JK		 7681 * igb_io_slot_reset - called after the pci bus has been reset.
7682 * @pdev: Pointer to PCI device
9d5c8243 7683 *
b980ac18
JK		 7684 * Restart the card from scratch, as if from a cold-boot. Implementation
7685 * resembles the first-half of the igb_resume routine.
7686 **/
9d5c8243
AK		 7687static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7688{
7689 struct net_device *netdev = pci_get_drvdata(pdev);
7690 struct igb_adapter *adapter = netdev_priv(netdev);
7691 struct e1000_hw *hw = &adapter->hw;
40a914fa 7692 pci_ers_result_t result;
42bfd33a 7693 int err;
9d5c8243 7694
aed5dec3 7695 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7696 dev_err(&pdev->dev,
7697 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7698 result = PCI_ERS_RESULT_DISCONNECT;
7699 } else {
7700 pci_set_master(pdev);
7701 pci_restore_state(pdev);
b94f2d77 7702 pci_save_state(pdev);
9d5c8243 7703
40a914fa
AD		 7704 pci_enable_wake(pdev, PCI_D3hot, 0);
7705 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7706
40a914fa
AD		 7707 igb_reset(adapter);
7708 wr32(E1000_WUS, ~0);
7709 result = PCI_ERS_RESULT_RECOVERED;
7710 }
9d5c8243 7711
ea943d41
JK		 7712 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7713 if (err) {
b980ac18
JK		 7714 dev_err(&pdev->dev,
7715 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7716 err);
ea943d41
JK		 7717 /* non-fatal, continue */
7718 }
40a914fa
AD		 7719
7720 return result;
9d5c8243
AK		 7721}
7722
7723/**
b980ac18
JK		 7724 * igb_io_resume - called when traffic can start flowing again.
7725 * @pdev: Pointer to PCI device
9d5c8243 7726 *
b980ac18
JK		 7727 * This callback is called when the error recovery driver tells us that
7728 * its OK to resume normal operation. Implementation resembles the
7729 * second-half of the igb_resume routine.
9d5c8243
AK		 7730 */
7731static void igb_io_resume(struct pci_dev *pdev)
7732{
7733 struct net_device *netdev = pci_get_drvdata(pdev);
7734 struct igb_adapter *adapter = netdev_priv(netdev);
7735
9d5c8243
AK		 7736 if (netif_running(netdev)) {
7737 if (igb_up(adapter)) {
7738 dev_err(&pdev->dev, "igb_up failed after reset\n");
7739 return;
7740 }
7741 }
7742
7743 netif_device_attach(netdev);
7744
7745 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7746 * driver.
7747 */
9d5c8243 7748 igb_get_hw_control(adapter);
9d5c8243
AK		 7749}
7750
26ad9178 7751static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7752 u8 qsel)
26ad9178
AD		 7753{
7754 u32 rar_low, rar_high;
7755 struct e1000_hw *hw = &adapter->hw;
7756
7757 /* HW expects these in little endian so we reverse the byte order
7758 * from network order (big endian) to little endian
7759 */
7760 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7761 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7762 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7763
7764 /* Indicate to hardware the Address is Valid. */
7765 rar_high |= E1000_RAH_AV;
7766
7767 if (hw->mac.type == e1000_82575)
7768 rar_high |= E1000_RAH_POOL_1 * qsel;
7769 else
7770 rar_high |= E1000_RAH_POOL_1 << qsel;
7771
7772 wr32(E1000_RAL(index), rar_low);
7773 wrfl();
7774 wr32(E1000_RAH(index), rar_high);
7775 wrfl();
7776}
7777
4ae196df 7778static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7779 int vf, unsigned char *mac_addr)
4ae196df
AD		 7780{
7781 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7782 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7783 * towards the first, as a result a collision should not be possible
7784 */
ff41f8dc 7785 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7786
37680117 7787 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7788
26ad9178 7789 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7790
7791 return 0;
7792}
7793
8151d294
WM		 7794static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7795{
7796 struct igb_adapter *adapter = netdev_priv(netdev);
7797 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7798 return -EINVAL;
7799 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7800 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7801 dev_info(&adapter->pdev->dev,
7802 "Reload the VF driver to make this change effective.");
8151d294 7803 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7804 dev_warn(&adapter->pdev->dev,
7805 "The VF MAC address has been set, but the PF device is not up.\n");
7806 dev_warn(&adapter->pdev->dev,
7807 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7808 }
7809 return igb_set_vf_mac(adapter, vf, mac);
7810}
7811
17dc566c
LL		 7812static int igb_link_mbps(int internal_link_speed)
7813{
7814 switch (internal_link_speed) {
7815 case SPEED_100:
7816 return 100;
7817 case SPEED_1000:
7818 return 1000;
7819 default:
7820 return 0;
7821 }
7822}
7823
7824static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7825 int link_speed)
7826{
7827 int rf_dec, rf_int;
7828 u32 bcnrc_val;
7829
7830 if (tx_rate != 0) {
7831 /* Calculate the rate factor values to set */
7832 rf_int = link_speed / tx_rate;
7833 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7834 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7835 tx_rate;
17dc566c
LL		 7836
7837 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7838 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7839 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7840 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7841 } else {
7842 bcnrc_val = 0;
7843 }
7844
7845 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7846 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7847 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7848 */
7849 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7850 wr32(E1000_RTTBCNRC, bcnrc_val);
7851}
7852
7853static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7854{
7855 int actual_link_speed, i;
7856 bool reset_rate = false;
7857
7858 /* VF TX rate limit was not set or not supported */
7859 if ((adapter->vf_rate_link_speed == 0) ||
7860 (adapter->hw.mac.type != e1000_82576))
7861 return;
7862
7863 actual_link_speed = igb_link_mbps(adapter->link_speed);
7864 if (actual_link_speed != adapter->vf_rate_link_speed) {
7865 reset_rate = true;
7866 adapter->vf_rate_link_speed = 0;
7867 dev_info(&adapter->pdev->dev,
b980ac18 7868 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7869 }
7870
7871 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7872 if (reset_rate)
7873 adapter->vf_data[i].tx_rate = 0;
7874
7875 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7876 adapter->vf_data[i].tx_rate,
7877 actual_link_speed);
17dc566c
LL		 7878 }
7879}
7880
8151d294
WM		 7881static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7882{
17dc566c
LL		 7883 struct igb_adapter *adapter = netdev_priv(netdev);
7884 struct e1000_hw *hw = &adapter->hw;
7885 int actual_link_speed;
7886
7887 if (hw->mac.type != e1000_82576)
7888 return -EOPNOTSUPP;
7889
7890 actual_link_speed = igb_link_mbps(adapter->link_speed);
7891 if ((vf >= adapter->vfs_allocated_count) ||
7892 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7893 (tx_rate < 0) || (tx_rate > actual_link_speed))
7894 return -EINVAL;
7895
7896 adapter->vf_rate_link_speed = actual_link_speed;
7897 adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7898 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7899
7900 return 0;
8151d294
WM		 7901}
7902
70ea4783
LL		 7903static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7904 bool setting)
7905{
7906 struct igb_adapter *adapter = netdev_priv(netdev);
7907 struct e1000_hw *hw = &adapter->hw;
7908 u32 reg_val, reg_offset;
7909
7910 if (!adapter->vfs_allocated_count)
7911 return -EOPNOTSUPP;
7912
7913 if (vf >= adapter->vfs_allocated_count)
7914 return -EINVAL;
7915
7916 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7917 reg_val = rd32(reg_offset);
7918 if (setting)
7919 reg_val |= ((1 << vf) |
7920 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7921 else
7922 reg_val &= ~((1 << vf) |
7923 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7924 wr32(reg_offset, reg_val);
7925
7926 adapter->vf_data[vf].spoofchk_enabled = setting;
7927 return E1000_SUCCESS;
7928}
7929
8151d294
WM		 7930static int igb_ndo_get_vf_config(struct net_device *netdev,
7931 int vf, struct ifla_vf_info *ivi)
7932{
7933 struct igb_adapter *adapter = netdev_priv(netdev);
7934 if (vf >= adapter->vfs_allocated_count)
7935 return -EINVAL;
7936 ivi->vf = vf;
7937 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
17dc566c 7938 ivi->tx_rate = adapter->vf_data[vf].tx_rate;
8151d294
WM		 7939 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7940 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7941 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7942 return 0;
7943}
7944
4ae196df
AD		 7945static void igb_vmm_control(struct igb_adapter *adapter)
7946{
7947 struct e1000_hw *hw = &adapter->hw;
10d8e907 7948 u32 reg;
4ae196df 7949
52a1dd4d
AD		 7950 switch (hw->mac.type) {
7951 case e1000_82575:
f96a8a0b
CW		 7952 case e1000_i210:
7953 case e1000_i211:
ceb5f13b 7954 case e1000_i354:
52a1dd4d
AD		 7955 default:
7956 /* replication is not supported for 82575 */
4ae196df 7957 return;
52a1dd4d
AD		 7958 case e1000_82576:
7959 /* notify HW that the MAC is adding vlan tags */
7960 reg = rd32(E1000_DTXCTL);
7961 reg |= E1000_DTXCTL_VLAN_ADDED;
7962 wr32(E1000_DTXCTL, reg);
b26141d4 7963 /* Fall through */
52a1dd4d
AD		 7964 case e1000_82580:
7965 /* enable replication vlan tag stripping */
7966 reg = rd32(E1000_RPLOLR);
7967 reg |= E1000_RPLOLR_STRVLAN;
7968 wr32(E1000_RPLOLR, reg);
b26141d4 7969 /* Fall through */
d2ba2ed8
AD		 7970 case e1000_i350:
7971 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7972 break;
7973 }
10d8e907 7974
d4960307
AD		 7975 if (adapter->vfs_allocated_count) {
7976 igb_vmdq_set_loopback_pf(hw, true);
7977 igb_vmdq_set_replication_pf(hw, true);
13800469 7978 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7979 adapter->vfs_allocated_count);
d4960307
AD		 7980 } else {
7981 igb_vmdq_set_loopback_pf(hw, false);
7982 igb_vmdq_set_replication_pf(hw, false);
7983 }
4ae196df
AD		 7984}
7985
b6e0c419
CW		 7986static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7987{
7988 struct e1000_hw *hw = &adapter->hw;
7989 u32 dmac_thr;
7990 u16 hwm;
7991
7992 if (hw->mac.type > e1000_82580) {
7993 if (adapter->flags & IGB_FLAG_DMAC) {
7994 u32 reg;
7995
7996 /* force threshold to 0. */
7997 wr32(E1000_DMCTXTH, 0);
7998
b980ac18 7999 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 8000 * than the Rx threshold. Set hwm to PBA - max frame
8001 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 8002 */
e8c626e9
MV		 8003 hwm = 64 * pba - adapter->max_frame_size / 16;
8004 if (hwm < 64 * (pba - 6))
8005 hwm = 64 * (pba - 6);
8006 reg = rd32(E1000_FCRTC);
8007 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
8008 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
8009 & E1000_FCRTC_RTH_COAL_MASK);
8010 wr32(E1000_FCRTC, reg);
8011
b980ac18 8012 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 8013 * frame size, capping it at PBA - 10KB.
8014 */
8015 dmac_thr = pba - adapter->max_frame_size / 512;
8016 if (dmac_thr < pba - 10)
8017 dmac_thr = pba - 10;
b6e0c419
CW		 8018 reg = rd32(E1000_DMACR);
8019 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 8020 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
8021 & E1000_DMACR_DMACTHR_MASK);
8022
8023 /* transition to L0x or L1 if available..*/
8024 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
8025
8026 /* watchdog timer= +-1000 usec in 32usec intervals */
8027 reg |= (1000 >> 5);
0c02dd98
MV		 8028
8029 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 8030 if (hw->mac.type != e1000_i354)
8031 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
8032
b6e0c419
CW		 8033 wr32(E1000_DMACR, reg);
8034
b980ac18 8035 /* no lower threshold to disable
b6e0c419
CW		 8036 * coalescing(smart fifb)-UTRESH=0
8037 */
8038 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 8039
8040 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
8041
8042 wr32(E1000_DMCTLX, reg);
8043
b980ac18 8044 /* free space in tx packet buffer to wake from
b6e0c419
CW		 8045 * DMA coal
8046 */
8047 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
8048 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
8049
b980ac18 8050 /* make low power state decision controlled
b6e0c419
CW		 8051 * by DMA coal
8052 */
8053 reg = rd32(E1000_PCIEMISC);
8054 reg &= ~E1000_PCIEMISC_LX_DECISION;
8055 wr32(E1000_PCIEMISC, reg);
8056 } /* endif adapter->dmac is not disabled */
8057 } else if (hw->mac.type == e1000_82580) {
8058 u32 reg = rd32(E1000_PCIEMISC);
9005df38 8059
b6e0c419
CW		 8060 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
8061 wr32(E1000_DMACR, 0);
8062 }
8063}
8064
b980ac18
JK		 8065/**
8066 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8067 * @hw: pointer to hardware structure
8068 * @byte_offset: byte offset to read
8069 * @dev_addr: device address
8070 * @data: value read
8071 *
8072 * Performs byte read operation over I2C interface at
8073 * a specified device address.
b980ac18 8074 **/
441fc6fd 8075s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8076 u8 dev_addr, u8 *data)
441fc6fd
CW		 8077{
8078 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8079 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8080 s32 status;
8081 u16 swfw_mask = 0;
8082
8083 if (!this_client)
8084 return E1000_ERR_I2C;
8085
8086 swfw_mask = E1000_SWFW_PHY0_SM;
8087
8088 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
8089 != E1000_SUCCESS)
8090 return E1000_ERR_SWFW_SYNC;
8091
8092 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8093 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8094
8095 if (status < 0)
8096 return E1000_ERR_I2C;
8097 else {
8098 *data = status;
8099 return E1000_SUCCESS;
8100 }
8101}
8102
b980ac18
JK		 8103/**
8104 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8105 * @hw: pointer to hardware structure
8106 * @byte_offset: byte offset to write
8107 * @dev_addr: device address
8108 * @data: value to write
8109 *
8110 * Performs byte write operation over I2C interface at
8111 * a specified device address.
b980ac18 8112 **/
441fc6fd 8113s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8114 u8 dev_addr, u8 data)
441fc6fd
CW		 8115{
8116 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8117 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8118 s32 status;
8119 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8120
8121 if (!this_client)
8122 return E1000_ERR_I2C;
8123
8124 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
8125 return E1000_ERR_SWFW_SYNC;
8126 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8127 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8128
8129 if (status)
8130 return E1000_ERR_I2C;
8131 else
8132 return E1000_SUCCESS;
8133
8134}
907b7835
LMV		 8135
8136int igb_reinit_queues(struct igb_adapter *adapter)
8137{
8138 struct net_device *netdev = adapter->netdev;
8139 struct pci_dev *pdev = adapter->pdev;
8140 int err = 0;
8141
8142 if (netif_running(netdev))
8143 igb_close(netdev);
8144
02ef6e1d 8145 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8146
8147 if (igb_init_interrupt_scheme(adapter, true)) {
8148 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8149 return -ENOMEM;
8150 }
8151
8152 if (netif_running(netdev))
8153 err = igb_open(netdev);
8154
8155 return err;
8156}
9d5c8243 8157/* igb_main.c */
Linux kernel - Deliverables
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