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net: Pull out core bits of __netdev_alloc_skb and add __napi_alloc_skb
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_main.c
CommitLineData
e52c0f96
CW		 1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
9d5c8243 23
876d2d6f
JK		 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
9d5c8243
AK		 26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/init.h>
b2cb09b1 29#include <linux/bitops.h>
9d5c8243
AK		 30#include <linux/vmalloc.h>
31#include <linux/pagemap.h>
32#include <linux/netdevice.h>
9d5c8243 33#include <linux/ipv6.h>
5a0e3ad6 34#include <linux/slab.h>
9d5c8243
AK		 35#include <net/checksum.h>
36#include <net/ip6_checksum.h>
c6cb090b 37#include <linux/net_tstamp.h>
9d5c8243
AK		 38#include <linux/mii.h>
39#include <linux/ethtool.h>
01789349 40#include <linux/if.h>
9d5c8243
AK		 41#include <linux/if_vlan.h>
42#include <linux/pci.h>
c54106bb 43#include <linux/pci-aspm.h>
9d5c8243
AK		 44#include <linux/delay.h>
45#include <linux/interrupt.h>
7d13a7d0
AD		 46#include <linux/ip.h>
47#include <linux/tcp.h>
48#include <linux/sctp.h>
9d5c8243 49#include <linux/if_ether.h>
40a914fa 50#include <linux/aer.h>
70c71606 51#include <linux/prefetch.h>
749ab2cd 52#include <linux/pm_runtime.h>
421e02f0 53#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 54#include <linux/dca.h>
55#endif
441fc6fd 56#include <linux/i2c.h>
9d5c8243
AK		 57#include "igb.h"
58
67b1b903 59#define MAJ 5
bf22a6bd 60#define MIN 2
b5d130c4 61#define BUILD 15
0d1fe82d 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
929dd047 63__stringify(BUILD) "-k"
9d5c8243
AK		 64char igb_driver_name[] = "igb";
65char igb_driver_version[] = DRV_VERSION;
66static const char igb_driver_string[] =
67 "Intel(R) Gigabit Ethernet Network Driver";
4b9ea462 68static const char igb_copyright[] =
74cfb2e1 69 "Copyright (c) 2007-2014 Intel Corporation.";
9d5c8243 70
9d5c8243
AK		 71static const struct e1000_info *igb_info_tbl[] = {
72 [board_82575] = &e1000_82575_info,
73};
74
cd1631ce 75static const struct pci_device_id igb_pci_tbl[] = {
ceb5f13b
CW		 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
f96a8a0b
CW		 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
53b87ce3
CW		 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
d2ba2ed8
AD		 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
55cac248
AD		 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
6493d24f 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
55cac248
AD		 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
308fb39a
JG		 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
1b5dda33
GJ		 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
2d064c06 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
9eb2341d 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
747d49ba 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
2d064c06
AD		 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
4703bf73 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
b894fa26 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
c8ea5ea9 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
9d5c8243
AK		 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
111 /* required last entry */
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
116
9d5c8243
AK		 117static int igb_setup_all_tx_resources(struct igb_adapter *);
118static int igb_setup_all_rx_resources(struct igb_adapter *);
119static void igb_free_all_tx_resources(struct igb_adapter *);
120static void igb_free_all_rx_resources(struct igb_adapter *);
06cf2666 121static void igb_setup_mrqc(struct igb_adapter *);
9d5c8243 122static int igb_probe(struct pci_dev *, const struct pci_device_id *);
9f9a12f8 123static void igb_remove(struct pci_dev *pdev);
9d5c8243
AK		 124static int igb_sw_init(struct igb_adapter *);
125static int igb_open(struct net_device *);
126static int igb_close(struct net_device *);
53c7d064 127static void igb_configure(struct igb_adapter *);
9d5c8243
AK		 128static void igb_configure_tx(struct igb_adapter *);
129static void igb_configure_rx(struct igb_adapter *);
9d5c8243
AK		 130static void igb_clean_all_tx_rings(struct igb_adapter *);
131static void igb_clean_all_rx_rings(struct igb_adapter *);
3b644cf6
MW		 132static void igb_clean_tx_ring(struct igb_ring *);
133static void igb_clean_rx_ring(struct igb_ring *);
ff41f8dc 134static void igb_set_rx_mode(struct net_device *);
9d5c8243
AK		 135static void igb_update_phy_info(unsigned long);
136static void igb_watchdog(unsigned long);
137static void igb_watchdog_task(struct work_struct *);
cd392f5c 138static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
12dcd86b 139static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
c502ea2e 140 struct rtnl_link_stats64 *stats);
9d5c8243
AK		 141static int igb_change_mtu(struct net_device *, int);
142static int igb_set_mac(struct net_device *, void *);
68d480c4 143static void igb_set_uta(struct igb_adapter *adapter);
9d5c8243
AK		 144static irqreturn_t igb_intr(int irq, void *);
145static irqreturn_t igb_intr_msi(int irq, void *);
146static irqreturn_t igb_msix_other(int irq, void *);
047e0030 147static irqreturn_t igb_msix_ring(int irq, void *);
421e02f0 148#ifdef CONFIG_IGB_DCA
047e0030 149static void igb_update_dca(struct igb_q_vector *);
fe4506b6 150static void igb_setup_dca(struct igb_adapter *);
421e02f0 151#endif /* CONFIG_IGB_DCA */
661086df 152static int igb_poll(struct napi_struct *, int);
13fde97a 153static bool igb_clean_tx_irq(struct igb_q_vector *);
cd392f5c 154static bool igb_clean_rx_irq(struct igb_q_vector *, int);
9d5c8243
AK		 155static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
156static void igb_tx_timeout(struct net_device *);
157static void igb_reset_task(struct work_struct *);
c502ea2e
CW		 158static void igb_vlan_mode(struct net_device *netdev,
159 netdev_features_t features);
80d5c368
PM		 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
9d5c8243 162static void igb_restore_vlan(struct igb_adapter *);
26ad9178 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
4ae196df
AD		 164static void igb_ping_all_vfs(struct igb_adapter *);
165static void igb_msg_task(struct igb_adapter *);
4ae196df 166static void igb_vmm_control(struct igb_adapter *);
f2ca0dbe 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
4ae196df 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
8151d294
WM		 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
170static int igb_ndo_set_vf_vlan(struct net_device *netdev,
171 int vf, u16 vlan, u8 qos);
ed616689 172static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
70ea4783
LL		 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
174 bool setting);
8151d294
WM		 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
176 struct ifla_vf_info *ivi);
17dc566c 177static void igb_check_vf_rate_limit(struct igb_adapter *);
46a01698
RL		 178
179#ifdef CONFIG_PCI_IOV
0224d663 180static int igb_vf_configure(struct igb_adapter *adapter, int vf);
781798a1 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
46a01698 182#endif
9d5c8243 183
9d5c8243 184#ifdef CONFIG_PM
d9dd966d 185#ifdef CONFIG_PM_SLEEP
749ab2cd 186static int igb_suspend(struct device *);
d9dd966d 187#endif
749ab2cd
YZ		 188static int igb_resume(struct device *);
189#ifdef CONFIG_PM_RUNTIME
190static int igb_runtime_suspend(struct device *dev);
191static int igb_runtime_resume(struct device *dev);
192static int igb_runtime_idle(struct device *dev);
193#endif
194static const struct dev_pm_ops igb_pm_ops = {
195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
197 igb_runtime_idle)
198};
9d5c8243
AK		 199#endif
200static void igb_shutdown(struct pci_dev *);
fa44f2f1 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
421e02f0 202#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
204static struct notifier_block dca_notifier = {
205 .notifier_call = igb_notify_dca,
206 .next = NULL,
207 .priority = 0
208};
209#endif
9d5c8243
AK		 210#ifdef CONFIG_NET_POLL_CONTROLLER
211/* for netdump / net console */
212static void igb_netpoll(struct net_device *);
213#endif
37680117 214#ifdef CONFIG_PCI_IOV
6dd6d2b7 215static unsigned int max_vfs;
2a3abf6d 216module_param(max_vfs, uint, 0);
c75c4edf 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
2a3abf6d
AD		 218#endif /* CONFIG_PCI_IOV */
219
9d5c8243
AK		 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
221 pci_channel_state_t);
222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
223static void igb_io_resume(struct pci_dev *);
224
3646f0e5 225static const struct pci_error_handlers igb_err_handler = {
9d5c8243
AK		 226 .error_detected = igb_io_error_detected,
227 .slot_reset = igb_io_slot_reset,
228 .resume = igb_io_resume,
229};
230
b6e0c419 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
9d5c8243
AK		 232
233static struct pci_driver igb_driver = {
234 .name = igb_driver_name,
235 .id_table = igb_pci_tbl,
236 .probe = igb_probe,
9f9a12f8 237 .remove = igb_remove,
9d5c8243 238#ifdef CONFIG_PM
749ab2cd 239 .driver.pm = &igb_pm_ops,
9d5c8243
AK		 240#endif
241 .shutdown = igb_shutdown,
fa44f2f1 242 .sriov_configure = igb_pci_sriov_configure,
9d5c8243
AK		 243 .err_handler = &igb_err_handler
244};
245
246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
248MODULE_LICENSE("GPL");
249MODULE_VERSION(DRV_VERSION);
250
b3f4d599 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
252static int debug = -1;
253module_param(debug, int, 0);
254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
255
c97ec42a
TI		 256struct igb_reg_info {
257 u32 ofs;
258 char *name;
259};
260
261static const struct igb_reg_info igb_reg_info_tbl[] = {
262
263 /* General Registers */
264 {E1000_CTRL, "CTRL"},
265 {E1000_STATUS, "STATUS"},
266 {E1000_CTRL_EXT, "CTRL_EXT"},
267
268 /* Interrupt Registers */
269 {E1000_ICR, "ICR"},
270
271 /* RX Registers */
272 {E1000_RCTL, "RCTL"},
273 {E1000_RDLEN(0), "RDLEN"},
274 {E1000_RDH(0), "RDH"},
275 {E1000_RDT(0), "RDT"},
276 {E1000_RXDCTL(0), "RXDCTL"},
277 {E1000_RDBAL(0), "RDBAL"},
278 {E1000_RDBAH(0), "RDBAH"},
279
280 /* TX Registers */
281 {E1000_TCTL, "TCTL"},
282 {E1000_TDBAL(0), "TDBAL"},
283 {E1000_TDBAH(0), "TDBAH"},
284 {E1000_TDLEN(0), "TDLEN"},
285 {E1000_TDH(0), "TDH"},
286 {E1000_TDT(0), "TDT"},
287 {E1000_TXDCTL(0), "TXDCTL"},
288 {E1000_TDFH, "TDFH"},
289 {E1000_TDFT, "TDFT"},
290 {E1000_TDFHS, "TDFHS"},
291 {E1000_TDFPC, "TDFPC"},
292
293 /* List Terminator */
294 {}
295};
296
b980ac18 297/* igb_regdump - register printout routine */
c97ec42a
TI		 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
299{
300 int n = 0;
301 char rname[16];
302 u32 regs[8];
303
304 switch (reginfo->ofs) {
305 case E1000_RDLEN(0):
306 for (n = 0; n < 4; n++)
307 regs[n] = rd32(E1000_RDLEN(n));
308 break;
309 case E1000_RDH(0):
310 for (n = 0; n < 4; n++)
311 regs[n] = rd32(E1000_RDH(n));
312 break;
313 case E1000_RDT(0):
314 for (n = 0; n < 4; n++)
315 regs[n] = rd32(E1000_RDT(n));
316 break;
317 case E1000_RXDCTL(0):
318 for (n = 0; n < 4; n++)
319 regs[n] = rd32(E1000_RXDCTL(n));
320 break;
321 case E1000_RDBAL(0):
322 for (n = 0; n < 4; n++)
323 regs[n] = rd32(E1000_RDBAL(n));
324 break;
325 case E1000_RDBAH(0):
326 for (n = 0; n < 4; n++)
327 regs[n] = rd32(E1000_RDBAH(n));
328 break;
329 case E1000_TDBAL(0):
330 for (n = 0; n < 4; n++)
331 regs[n] = rd32(E1000_RDBAL(n));
332 break;
333 case E1000_TDBAH(0):
334 for (n = 0; n < 4; n++)
335 regs[n] = rd32(E1000_TDBAH(n));
336 break;
337 case E1000_TDLEN(0):
338 for (n = 0; n < 4; n++)
339 regs[n] = rd32(E1000_TDLEN(n));
340 break;
341 case E1000_TDH(0):
342 for (n = 0; n < 4; n++)
343 regs[n] = rd32(E1000_TDH(n));
344 break;
345 case E1000_TDT(0):
346 for (n = 0; n < 4; n++)
347 regs[n] = rd32(E1000_TDT(n));
348 break;
349 case E1000_TXDCTL(0):
350 for (n = 0; n < 4; n++)
351 regs[n] = rd32(E1000_TXDCTL(n));
352 break;
353 default:
876d2d6f 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
c97ec42a
TI		 355 return;
356 }
357
358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
876d2d6f
JK		 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
360 regs[2], regs[3]);
c97ec42a
TI		 361}
362
b980ac18 363/* igb_dump - Print registers, Tx-rings and Rx-rings */
c97ec42a
TI		 364static void igb_dump(struct igb_adapter *adapter)
365{
366 struct net_device *netdev = adapter->netdev;
367 struct e1000_hw *hw = &adapter->hw;
368 struct igb_reg_info *reginfo;
c97ec42a
TI		 369 struct igb_ring *tx_ring;
370 union e1000_adv_tx_desc *tx_desc;
371 struct my_u0 { u64 a; u64 b; } *u0;
c97ec42a
TI		 372 struct igb_ring *rx_ring;
373 union e1000_adv_rx_desc *rx_desc;
374 u32 staterr;
6ad4edfc 375 u16 i, n;
c97ec42a
TI		 376
377 if (!netif_msg_hw(adapter))
378 return;
379
380 /* Print netdevice Info */
381 if (netdev) {
382 dev_info(&adapter->pdev->dev, "Net device Info\n");
c75c4edf 383 pr_info("Device Name state trans_start last_rx\n");
876d2d6f
JK		 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
385 netdev->state, netdev->trans_start, netdev->last_rx);
c97ec42a
TI		 386 }
387
388 /* Print Registers */
389 dev_info(&adapter->pdev->dev, "Register Dump\n");
876d2d6f 390 pr_info(" Register Name Value\n");
c97ec42a
TI		 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
392 reginfo->name; reginfo++) {
393 igb_regdump(hw, reginfo);
394 }
395
396 /* Print TX Ring Summary */
397 if (!netdev || !netif_running(netdev))
398 goto exit;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
876d2d6f 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
c97ec42a 402 for (n = 0; n < adapter->num_tx_queues; n++) {
06034649 403 struct igb_tx_buffer *buffer_info;
c97ec42a 404 tx_ring = adapter->tx_ring[n];
06034649 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
876d2d6f
JK		 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
407 n, tx_ring->next_to_use, tx_ring->next_to_clean,
c9f14bf3
AD		 408 (u64)dma_unmap_addr(buffer_info, dma),
409 dma_unmap_len(buffer_info, len),
876d2d6f
JK		 410 buffer_info->next_to_watch,
411 (u64)buffer_info->time_stamp);
c97ec42a
TI		 412 }
413
414 /* Print TX Rings */
415 if (!netif_msg_tx_done(adapter))
416 goto rx_ring_summary;
417
418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
419
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
430
431 for (n = 0; n < adapter->num_tx_queues; n++) {
432 tx_ring = adapter->tx_ring[n];
876d2d6f
JK		 433 pr_info("------------------------------------\n");
434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
435 pr_info("------------------------------------\n");
c75c4edf 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n");
c97ec42a
TI		 437
438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
876d2d6f 439 const char *next_desc;
06034649 440 struct igb_tx_buffer *buffer_info;
60136906 441 tx_desc = IGB_TX_DESC(tx_ring, i);
06034649 442 buffer_info = &tx_ring->tx_buffer_info[i];
c97ec42a 443 u0 = (struct my_u0 *)tx_desc;
876d2d6f
JK		 444 if (i == tx_ring->next_to_use &&
445 i == tx_ring->next_to_clean)
446 next_desc = " NTC/U";
447 else if (i == tx_ring->next_to_use)
448 next_desc = " NTU";
449 else if (i == tx_ring->next_to_clean)
450 next_desc = " NTC";
451 else
452 next_desc = "";
453
c75c4edf
CW		 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n",
455 i, le64_to_cpu(u0->a),
c97ec42a 456 le64_to_cpu(u0->b),
c9f14bf3
AD		 457 (u64)dma_unmap_addr(buffer_info, dma),
458 dma_unmap_len(buffer_info, len),
c97ec42a
TI		 459 buffer_info->next_to_watch,
460 (u64)buffer_info->time_stamp,
876d2d6f 461 buffer_info->skb, next_desc);
c97ec42a 462
b669588a 463 if (netif_msg_pktdata(adapter) && buffer_info->skb)
c97ec42a
TI		 464 print_hex_dump(KERN_INFO, "",
465 DUMP_PREFIX_ADDRESS,
b669588a 466 16, 1, buffer_info->skb->data,
c9f14bf3
AD		 467 dma_unmap_len(buffer_info, len),
468 true);
c97ec42a
TI		 469 }
470 }
471
472 /* Print RX Rings Summary */
473rx_ring_summary:
474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
876d2d6f 475 pr_info("Queue [NTU] [NTC]\n");
c97ec42a
TI		 476 for (n = 0; n < adapter->num_rx_queues; n++) {
477 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 478 pr_info(" %5d %5X %5X\n",
479 n, rx_ring->next_to_use, rx_ring->next_to_clean);
c97ec42a
TI		 480 }
481
482 /* Print RX Rings */
483 if (!netif_msg_rx_status(adapter))
484 goto exit;
485
486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
487
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
508
509 for (n = 0; n < adapter->num_rx_queues; n++) {
510 rx_ring = adapter->rx_ring[n];
876d2d6f
JK		 511 pr_info("------------------------------------\n");
512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
513 pr_info("------------------------------------\n");
c75c4edf
CW		 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n");
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
c97ec42a
TI		 516
517 for (i = 0; i < rx_ring->count; i++) {
876d2d6f 518 const char *next_desc;
06034649
AD		 519 struct igb_rx_buffer *buffer_info;
520 buffer_info = &rx_ring->rx_buffer_info[i];
60136906 521 rx_desc = IGB_RX_DESC(rx_ring, i);
c97ec42a
TI		 522 u0 = (struct my_u0 *)rx_desc;
523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
876d2d6f
JK		 524
525 if (i == rx_ring->next_to_use)
526 next_desc = " NTU";
527 else if (i == rx_ring->next_to_clean)
528 next_desc = " NTC";
529 else
530 next_desc = "";
531
c97ec42a
TI		 532 if (staterr & E1000_RXD_STAT_DD) {
533 /* Descriptor Done */
1a1c225b
AD		 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n",
535 "RWB", i,
c97ec42a
TI		 536 le64_to_cpu(u0->a),
537 le64_to_cpu(u0->b),
1a1c225b 538 next_desc);
c97ec42a 539 } else {
1a1c225b
AD		 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n",
541 "R ", i,
c97ec42a
TI		 542 le64_to_cpu(u0->a),
543 le64_to_cpu(u0->b),
544 (u64)buffer_info->dma,
1a1c225b 545 next_desc);
c97ec42a 546
b669588a 547 if (netif_msg_pktdata(adapter) &&
1a1c225b 548 buffer_info->dma && buffer_info->page) {
44390ca6
AD		 549 print_hex_dump(KERN_INFO, "",
550 DUMP_PREFIX_ADDRESS,
551 16, 1,
b669588a
ET		 552 page_address(buffer_info->page) +
553 buffer_info->page_offset,
de78d1f9 554 IGB_RX_BUFSZ, true);
c97ec42a
TI		 555 }
556 }
c97ec42a
TI		 557 }
558 }
559
560exit:
561 return;
562}
563
b980ac18
JK		 564/**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
441fc6fd
CW		 566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
b980ac18 570 **/
441fc6fd
CW		 571static int igb_get_i2c_data(void *data)
572{
573 struct igb_adapter *adapter = (struct igb_adapter *)data;
574 struct e1000_hw *hw = &adapter->hw;
575 s32 i2cctl = rd32(E1000_I2CPARAMS);
576
da1f1dfe 577 return !!(i2cctl & E1000_I2C_DATA_IN);
441fc6fd
CW		 578}
579
b980ac18
JK		 580/**
581 * igb_set_i2c_data - Sets the I2C data bit
441fc6fd
CW		 582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
b980ac18 586 **/
441fc6fd
CW		 587static void igb_set_i2c_data(void *data, int state)
588{
589 struct igb_adapter *adapter = (struct igb_adapter *)data;
590 struct e1000_hw *hw = &adapter->hw;
591 s32 i2cctl = rd32(E1000_I2CPARAMS);
592
593 if (state)
594 i2cctl |= E1000_I2C_DATA_OUT;
595 else
596 i2cctl &= ~E1000_I2C_DATA_OUT;
597
598 i2cctl &= ~E1000_I2C_DATA_OE_N;
599 i2cctl |= E1000_I2C_CLK_OE_N;
600 wr32(E1000_I2CPARAMS, i2cctl);
601 wrfl();
602
603}
604
b980ac18
JK		 605/**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
441fc6fd
CW		 607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
b980ac18 611 **/
441fc6fd
CW		 612static void igb_set_i2c_clk(void *data, int state)
613{
614 struct igb_adapter *adapter = (struct igb_adapter *)data;
615 struct e1000_hw *hw = &adapter->hw;
616 s32 i2cctl = rd32(E1000_I2CPARAMS);
617
618 if (state) {
619 i2cctl |= E1000_I2C_CLK_OUT;
620 i2cctl &= ~E1000_I2C_CLK_OE_N;
621 } else {
622 i2cctl &= ~E1000_I2C_CLK_OUT;
623 i2cctl &= ~E1000_I2C_CLK_OE_N;
624 }
625 wr32(E1000_I2CPARAMS, i2cctl);
626 wrfl();
627}
628
b980ac18
JK		 629/**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
441fc6fd
CW		 631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
b980ac18 634 **/
441fc6fd
CW		 635static int igb_get_i2c_clk(void *data)
636{
637 struct igb_adapter *adapter = (struct igb_adapter *)data;
638 struct e1000_hw *hw = &adapter->hw;
639 s32 i2cctl = rd32(E1000_I2CPARAMS);
640
da1f1dfe 641 return !!(i2cctl & E1000_I2C_CLK_IN);
441fc6fd
CW		 642}
643
644static const struct i2c_algo_bit_data igb_i2c_algo = {
645 .setsda = igb_set_i2c_data,
646 .setscl = igb_set_i2c_clk,
647 .getsda = igb_get_i2c_data,
648 .getscl = igb_get_i2c_clk,
649 .udelay = 5,
650 .timeout = 20,
651};
652
9d5c8243 653/**
b980ac18
JK		 654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
9d5c8243 658 **/
c041076a 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
9d5c8243
AK		 660{
661 struct igb_adapter *adapter = hw->back;
c041076a 662 return adapter->netdev;
9d5c8243 663}
38c845c7 664
9d5c8243 665/**
b980ac18 666 * igb_init_module - Driver Registration Routine
9d5c8243 667 *
b980ac18
JK		 668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
9d5c8243
AK		 670 **/
671static int __init igb_init_module(void)
672{
673 int ret;
9005df38 674
876d2d6f 675 pr_info("%s - version %s\n",
9d5c8243 676 igb_driver_string, igb_driver_version);
876d2d6f 677 pr_info("%s\n", igb_copyright);
9d5c8243 678
421e02f0 679#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 680 dca_register_notify(&dca_notifier);
681#endif
bbd98fe4 682 ret = pci_register_driver(&igb_driver);
9d5c8243
AK		 683 return ret;
684}
685
686module_init(igb_init_module);
687
688/**
b980ac18 689 * igb_exit_module - Driver Exit Cleanup Routine
9d5c8243 690 *
b980ac18
JK		 691 * igb_exit_module is called just before the driver is removed
692 * from memory.
9d5c8243
AK		 693 **/
694static void __exit igb_exit_module(void)
695{
421e02f0 696#ifdef CONFIG_IGB_DCA
fe4506b6
JC		 697 dca_unregister_notify(&dca_notifier);
698#endif
9d5c8243
AK		 699 pci_unregister_driver(&igb_driver);
700}
701
702module_exit(igb_exit_module);
703
26bc19ec
AD		 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705/**
b980ac18
JK		 706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
26bc19ec 708 *
b980ac18
JK		 709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
26bc19ec
AD		 711 **/
712static void igb_cache_ring_register(struct igb_adapter *adapter)
713{
ee1b9f06 714 int i = 0, j = 0;
047e0030 715 u32 rbase_offset = adapter->vfs_allocated_count;
26bc19ec
AD		 716
717 switch (adapter->hw.mac.type) {
718 case e1000_82576:
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
ee1b9f06 724 if (adapter->vfs_allocated_count) {
a99955fc 725 for (; i < adapter->rss_queues; i++)
3025a446 726 adapter->rx_ring[i]->reg_idx = rbase_offset +
b980ac18 727 Q_IDX_82576(i);
ee1b9f06 728 }
b26141d4 729 /* Fall through */
26bc19ec 730 case e1000_82575:
55cac248 731 case e1000_82580:
d2ba2ed8 732 case e1000_i350:
ceb5f13b 733 case e1000_i354:
f96a8a0b
CW		 734 case e1000_i210:
735 case e1000_i211:
b26141d4 736 /* Fall through */
26bc19ec 737 default:
ee1b9f06 738 for (; i < adapter->num_rx_queues; i++)
3025a446 739 adapter->rx_ring[i]->reg_idx = rbase_offset + i;
ee1b9f06 740 for (; j < adapter->num_tx_queues; j++)
3025a446 741 adapter->tx_ring[j]->reg_idx = rbase_offset + j;
26bc19ec
AD		 742 break;
743 }
744}
745
22a8b291
FT		 746u32 igb_rd32(struct e1000_hw *hw, u32 reg)
747{
748 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
749 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr);
750 u32 value = 0;
751
752 if (E1000_REMOVED(hw_addr))
753 return ~value;
754
755 value = readl(&hw_addr[reg]);
756
757 /* reads should not return all F's */
758 if (!(~value) && (!reg || !(~readl(hw_addr)))) {
759 struct net_device *netdev = igb->netdev;
760 hw->hw_addr = NULL;
761 netif_device_detach(netdev);
762 netdev_err(netdev, "PCIe link lost, device now detached\n");
763 }
764
765 return value;
766}
767
4be000c8
AD		 768/**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
780static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
781 int index, int offset)
782{
783 u32 ivar = array_rd32(E1000_IVAR0, index);
784
785 /* clear any bits that are currently set */
786 ivar &= ~((u32)0xFF << offset);
787
788 /* write vector and valid bit */
789 ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
790
791 array_wr32(E1000_IVAR0, index, ivar);
792}
793
9d5c8243 794#define IGB_N0_QUEUE -1
047e0030 795static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
9d5c8243 796{
047e0030 797 struct igb_adapter *adapter = q_vector->adapter;
9d5c8243 798 struct e1000_hw *hw = &adapter->hw;
047e0030
AD		 799 int rx_queue = IGB_N0_QUEUE;
800 int tx_queue = IGB_N0_QUEUE;
4be000c8 801 u32 msixbm = 0;
047e0030 802
0ba82994
AD		 803 if (q_vector->rx.ring)
804 rx_queue = q_vector->rx.ring->reg_idx;
805 if (q_vector->tx.ring)
806 tx_queue = q_vector->tx.ring->reg_idx;
2d064c06
AD		 807
808 switch (hw->mac.type) {
809 case e1000_82575:
9d5c8243 810 /* The 82575 assigns vectors using a bitmask, which matches the
b980ac18
JK		 811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
047e0030 815 if (rx_queue > IGB_N0_QUEUE)
9d5c8243 816 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
047e0030 817 if (tx_queue > IGB_N0_QUEUE)
9d5c8243 818 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
cd14ef54 819 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
feeb2721 820 msixbm |= E1000_EIMS_OTHER;
9d5c8243 821 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
047e0030 822 q_vector->eims_value = msixbm;
2d064c06
AD		 823 break;
824 case e1000_82576:
b980ac18 825 /* 82576 uses a table that essentially consists of 2 columns
4be000c8
AD		 826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
830 if (rx_queue > IGB_N0_QUEUE)
831 igb_write_ivar(hw, msix_vector,
832 rx_queue & 0x7,
833 (rx_queue & 0x8) << 1);
834 if (tx_queue > IGB_N0_QUEUE)
835 igb_write_ivar(hw, msix_vector,
836 tx_queue & 0x7,
837 ((tx_queue & 0x8) << 1) + 8);
047e0030 838 q_vector->eims_value = 1 << msix_vector;
2d064c06 839 break;
55cac248 840 case e1000_82580:
d2ba2ed8 841 case e1000_i350:
ceb5f13b 842 case e1000_i354:
f96a8a0b
CW		 843 case e1000_i210:
844 case e1000_i211:
b980ac18 845 /* On 82580 and newer adapters the scheme is similar to 82576
4be000c8
AD		 846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
851 if (rx_queue > IGB_N0_QUEUE)
852 igb_write_ivar(hw, msix_vector,
853 rx_queue >> 1,
854 (rx_queue & 0x1) << 4);
855 if (tx_queue > IGB_N0_QUEUE)
856 igb_write_ivar(hw, msix_vector,
857 tx_queue >> 1,
858 ((tx_queue & 0x1) << 4) + 8);
55cac248
AD		 859 q_vector->eims_value = 1 << msix_vector;
860 break;
2d064c06
AD		 861 default:
862 BUG();
863 break;
864 }
26b39276
AD		 865
866 /* add q_vector eims value to global eims_enable_mask */
867 adapter->eims_enable_mask |= q_vector->eims_value;
868
869 /* configure q_vector to set itr on first interrupt */
870 q_vector->set_itr = 1;
9d5c8243
AK		 871}
872
873/**
b980ac18
JK		 874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
9d5c8243 876 *
b980ac18
JK		 877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
9d5c8243
AK		 879 **/
880static void igb_configure_msix(struct igb_adapter *adapter)
881{
882 u32 tmp;
883 int i, vector = 0;
884 struct e1000_hw *hw = &adapter->hw;
885
886 adapter->eims_enable_mask = 0;
9d5c8243
AK		 887
888 /* set vector for other causes, i.e. link changes */
2d064c06
AD		 889 switch (hw->mac.type) {
890 case e1000_82575:
9d5c8243
AK		 891 tmp = rd32(E1000_CTRL_EXT);
892 /* enable MSI-X PBA support*/
893 tmp |= E1000_CTRL_EXT_PBA_CLR;
894
895 /* Auto-Mask interrupts upon ICR read. */
896 tmp |= E1000_CTRL_EXT_EIAME;
897 tmp |= E1000_CTRL_EXT_IRCA;
898
899 wr32(E1000_CTRL_EXT, tmp);
047e0030
AD		 900
901 /* enable msix_other interrupt */
b980ac18 902 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
844290e5 903 adapter->eims_other = E1000_EIMS_OTHER;
9d5c8243 904
2d064c06
AD		 905 break;
906
907 case e1000_82576:
55cac248 908 case e1000_82580:
d2ba2ed8 909 case e1000_i350:
ceb5f13b 910 case e1000_i354:
f96a8a0b
CW		 911 case e1000_i210:
912 case e1000_i211:
047e0030 913 /* Turn on MSI-X capability first, or our settings
b980ac18
JK		 914 * won't stick. And it will take days to debug.
915 */
047e0030 916 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
b980ac18
JK		 917 E1000_GPIE_PBA | E1000_GPIE_EIAME |
918 E1000_GPIE_NSICR);
047e0030
AD		 919
920 /* enable msix_other interrupt */
921 adapter->eims_other = 1 << vector;
2d064c06 922 tmp = (vector++ | E1000_IVAR_VALID) << 8;
2d064c06 923
047e0030 924 wr32(E1000_IVAR_MISC, tmp);
2d064c06
AD		 925 break;
926 default:
927 /* do nothing, since nothing else supports MSI-X */
928 break;
929 } /* switch (hw->mac.type) */
047e0030
AD		 930
931 adapter->eims_enable_mask |= adapter->eims_other;
932
26b39276
AD		 933 for (i = 0; i < adapter->num_q_vectors; i++)
934 igb_assign_vector(adapter->q_vector[i], vector++);
047e0030 935
9d5c8243
AK		 936 wrfl();
937}
938
939/**
b980ac18
JK		 940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
9d5c8243 942 *
b980ac18
JK		 943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
9d5c8243
AK		 945 **/
946static int igb_request_msix(struct igb_adapter *adapter)
947{
948 struct net_device *netdev = adapter->netdev;
047e0030 949 struct e1000_hw *hw = &adapter->hw;
52285b76 950 int i, err = 0, vector = 0, free_vector = 0;
9d5c8243 951
047e0030 952 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18 953 igb_msix_other, 0, netdev->name, adapter);
047e0030 954 if (err)
52285b76 955 goto err_out;
047e0030
AD		 956
957 for (i = 0; i < adapter->num_q_vectors; i++) {
958 struct igb_q_vector *q_vector = adapter->q_vector[i];
959
52285b76
SA		 960 vector++;
961
047e0030
AD		 962 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
963
0ba82994 964 if (q_vector->rx.ring && q_vector->tx.ring)
047e0030 965 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
0ba82994
AD		 966 q_vector->rx.ring->queue_index);
967 else if (q_vector->tx.ring)
047e0030 968 sprintf(q_vector->name, "%s-tx-%u", netdev->name,
0ba82994
AD		 969 q_vector->tx.ring->queue_index);
970 else if (q_vector->rx.ring)
047e0030 971 sprintf(q_vector->name, "%s-rx-%u", netdev->name,
0ba82994 972 q_vector->rx.ring->queue_index);
9d5c8243 973 else
047e0030
AD		 974 sprintf(q_vector->name, "%s-unused", netdev->name);
975
9d5c8243 976 err = request_irq(adapter->msix_entries[vector].vector,
b980ac18
JK		 977 igb_msix_ring, 0, q_vector->name,
978 q_vector);
9d5c8243 979 if (err)
52285b76 980 goto err_free;
9d5c8243
AK		 981 }
982
9d5c8243
AK		 983 igb_configure_msix(adapter);
984 return 0;
52285b76
SA		 985
986err_free:
987 /* free already assigned IRQs */
988 free_irq(adapter->msix_entries[free_vector++].vector, adapter);
989
990 vector--;
991 for (i = 0; i < vector; i++) {
992 free_irq(adapter->msix_entries[free_vector++].vector,
993 adapter->q_vector[i]);
994 }
995err_out:
9d5c8243
AK		 996 return err;
997}
998
5536d210 999/**
b980ac18
JK		 1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
5536d210 1003 *
02ef6e1d 1004 * This function frees the memory allocated to the q_vector.
5536d210
AD		 1005 **/
1006static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
1007{
1008 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1009
02ef6e1d
CW		 1010 adapter->q_vector[v_idx] = NULL;
1011
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
17a402a0
CW		 1015 if (q_vector)
1016 kfree_rcu(q_vector, rcu);
02ef6e1d
CW		 1017}
1018
1019/**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1028{
1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1030
cb06d102
CP		 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1034 if (!q_vector)
1035 return;
1036
5536d210
AD		 1037 if (q_vector->tx.ring)
1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1039
1040 if (q_vector->rx.ring)
1041 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1042
5536d210
AD		 1043 netif_napi_del(&q_vector->napi);
1044
02ef6e1d
CW		 1045}
1046
1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1048{
1049 int v_idx = adapter->num_q_vectors;
1050
cd14ef54 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX)
02ef6e1d 1052 pci_disable_msix(adapter->pdev);
cd14ef54 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI)
02ef6e1d 1054 pci_disable_msi(adapter->pdev);
02ef6e1d
CW		 1055
1056 while (v_idx--)
1057 igb_reset_q_vector(adapter, v_idx);
5536d210
AD		 1058}
1059
047e0030 1060/**
b980ac18
JK		 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
047e0030 1063 *
b980ac18
JK		 1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
047e0030
AD		 1067 **/
1068static void igb_free_q_vectors(struct igb_adapter *adapter)
1069{
5536d210
AD		 1070 int v_idx = adapter->num_q_vectors;
1071
1072 adapter->num_tx_queues = 0;
1073 adapter->num_rx_queues = 0;
047e0030 1074 adapter->num_q_vectors = 0;
5536d210 1075
02ef6e1d
CW		 1076 while (v_idx--) {
1077 igb_reset_q_vector(adapter, v_idx);
5536d210 1078 igb_free_q_vector(adapter, v_idx);
02ef6e1d 1079 }
047e0030
AD		 1080}
1081
1082/**
b980ac18
JK		 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
047e0030 1085 *
b980ac18
JK		 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
047e0030
AD		 1088 */
1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1090{
047e0030
AD		 1091 igb_free_q_vectors(adapter);
1092 igb_reset_interrupt_capability(adapter);
1093}
9d5c8243
AK		 1094
1095/**
b980ac18
JK		 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
9d5c8243 1099 *
b980ac18
JK		 1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
9d5c8243 1102 **/
53c7d064 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
9d5c8243
AK		 1104{
1105 int err;
1106 int numvecs, i;
1107
53c7d064
SA		 1108 if (!msix)
1109 goto msi_only;
cd14ef54 1110 adapter->flags |= IGB_FLAG_HAS_MSIX;
53c7d064 1111
83b7180d 1112 /* Number of supported queues. */
a99955fc 1113 adapter->num_rx_queues = adapter->rss_queues;
5fa8517f
GR		 1114 if (adapter->vfs_allocated_count)
1115 adapter->num_tx_queues = 1;
1116 else
1117 adapter->num_tx_queues = adapter->rss_queues;
83b7180d 1118
b980ac18 1119 /* start with one vector for every Rx queue */
047e0030
AD		 1120 numvecs = adapter->num_rx_queues;
1121
b980ac18 1122 /* if Tx handler is separate add 1 for every Tx queue */
a99955fc
AD		 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1124 numvecs += adapter->num_tx_queues;
047e0030
AD		 1125
1126 /* store the number of vectors reserved for queues */
1127 adapter->num_q_vectors = numvecs;
1128
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
9d5c8243
AK		 1131 for (i = 0; i < numvecs; i++)
1132 adapter->msix_entries[i].entry = i;
1133
479d02df
AG		 1134 err = pci_enable_msix_range(adapter->pdev,
1135 adapter->msix_entries,
1136 numvecs,
1137 numvecs);
1138 if (err > 0)
0c2cc02e 1139 return;
9d5c8243
AK		 1140
1141 igb_reset_interrupt_capability(adapter);
1142
1143 /* If we can't do MSI-X, try MSI */
1144msi_only:
b709323d 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX;
2a3abf6d
AD		 1146#ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1148 if (adapter->vf_data) {
1149 struct e1000_hw *hw = &adapter->hw;
1150 /* disable iov and allow time for transactions to clear */
1151 pci_disable_sriov(adapter->pdev);
1152 msleep(500);
1153
1154 kfree(adapter->vf_data);
1155 adapter->vf_data = NULL;
1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
945a5151 1157 wrfl();
2a3abf6d
AD		 1158 msleep(100);
1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1160 }
1161#endif
4fc82adf 1162 adapter->vfs_allocated_count = 0;
a99955fc 1163 adapter->rss_queues = 1;
4fc82adf 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
9d5c8243 1165 adapter->num_rx_queues = 1;
661086df 1166 adapter->num_tx_queues = 1;
047e0030 1167 adapter->num_q_vectors = 1;
9d5c8243 1168 if (!pci_enable_msi(adapter->pdev))
7dfc16fa 1169 adapter->flags |= IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1170}
1171
5536d210
AD		 1172static void igb_add_ring(struct igb_ring *ring,
1173 struct igb_ring_container *head)
1174{
1175 head->ring = ring;
1176 head->count++;
1177}
1178
047e0030 1179/**
b980ac18
JK		 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
047e0030 1188 *
b980ac18 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
047e0030 1190 **/
5536d210
AD		 1191static int igb_alloc_q_vector(struct igb_adapter *adapter,
1192 int v_count, int v_idx,
1193 int txr_count, int txr_idx,
1194 int rxr_count, int rxr_idx)
047e0030
AD		 1195{
1196 struct igb_q_vector *q_vector;
5536d210
AD		 1197 struct igb_ring *ring;
1198 int ring_count, size;
047e0030 1199
5536d210
AD		 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1201 if (txr_count > 1 || rxr_count > 1)
1202 return -ENOMEM;
1203
1204 ring_count = txr_count + rxr_count;
1205 size = sizeof(struct igb_q_vector) +
1206 (sizeof(struct igb_ring) * ring_count);
1207
1208 /* allocate q_vector and rings */
02ef6e1d
CW		 1209 q_vector = adapter->q_vector[v_idx];
1210 if (!q_vector)
1211 q_vector = kzalloc(size, GFP_KERNEL);
5536d210
AD		 1212 if (!q_vector)
1213 return -ENOMEM;
1214
1215 /* initialize NAPI */
1216 netif_napi_add(adapter->netdev, &q_vector->napi,
1217 igb_poll, 64);
1218
1219 /* tie q_vector and adapter together */
1220 adapter->q_vector[v_idx] = q_vector;
1221 q_vector->adapter = adapter;
1222
1223 /* initialize work limits */
1224 q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226 /* initialize ITR configuration */
1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1228 q_vector->itr_val = IGB_START_ITR;
1229
1230 /* initialize pointer to rings */
1231 ring = q_vector->ring;
1232
4e227667
AD		 1233 /* intialize ITR */
1234 if (rxr_count) {
1235 /* rx or rx/tx vector */
1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237 q_vector->itr_val = adapter->rx_itr_setting;
1238 } else {
1239 /* tx only vector */
1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241 q_vector->itr_val = adapter->tx_itr_setting;
1242 }
1243
5536d210
AD		 1244 if (txr_count) {
1245 /* assign generic ring traits */
1246 ring->dev = &adapter->pdev->dev;
1247 ring->netdev = adapter->netdev;
1248
1249 /* configure backlink on ring */
1250 ring->q_vector = q_vector;
1251
1252 /* update q_vector Tx values */
1253 igb_add_ring(ring, &q_vector->tx);
1254
1255 /* For 82575, context index must be unique per ring. */
1256 if (adapter->hw.mac.type == e1000_82575)
1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259 /* apply Tx specific ring traits */
1260 ring->count = adapter->tx_ring_count;
1261 ring->queue_index = txr_idx;
1262
827da44c
JS		 1263 u64_stats_init(&ring->tx_syncp);
1264 u64_stats_init(&ring->tx_syncp2);
1265
5536d210
AD		 1266 /* assign ring to adapter */
1267 adapter->tx_ring[txr_idx] = ring;
1268
1269 /* push pointer to next ring */
1270 ring++;
047e0030 1271 }
81c2fc22 1272
5536d210
AD		 1273 if (rxr_count) {
1274 /* assign generic ring traits */
1275 ring->dev = &adapter->pdev->dev;
1276 ring->netdev = adapter->netdev;
047e0030 1277
5536d210
AD		 1278 /* configure backlink on ring */
1279 ring->q_vector = q_vector;
047e0030 1280
5536d210
AD		 1281 /* update q_vector Rx values */
1282 igb_add_ring(ring, &q_vector->rx);
047e0030 1283
5536d210
AD		 1284 /* set flag indicating ring supports SCTP checksum offload */
1285 if (adapter->hw.mac.type >= e1000_82576)
1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
047e0030 1287
e52c0f96 1288 /* On i350, i354, i210, and i211, loopback VLAN packets
5536d210 1289 * have the tag byte-swapped.
b980ac18 1290 */
5536d210
AD		 1291 if (adapter->hw.mac.type >= e1000_i350)
1292 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
047e0030 1293
5536d210
AD		 1294 /* apply Rx specific ring traits */
1295 ring->count = adapter->rx_ring_count;
1296 ring->queue_index = rxr_idx;
1297
827da44c
JS		 1298 u64_stats_init(&ring->rx_syncp);
1299
5536d210
AD		 1300 /* assign ring to adapter */
1301 adapter->rx_ring[rxr_idx] = ring;
1302 }
1303
1304 return 0;
047e0030
AD		 1305}
1306
5536d210 1307
047e0030 1308/**
b980ac18
JK		 1309 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1310 * @adapter: board private structure to initialize
047e0030 1311 *
b980ac18
JK		 1312 * We allocate one q_vector per queue interrupt. If allocation fails we
1313 * return -ENOMEM.
047e0030 1314 **/
5536d210 1315static int igb_alloc_q_vectors(struct igb_adapter *adapter)
047e0030 1316{
5536d210
AD		 1317 int q_vectors = adapter->num_q_vectors;
1318 int rxr_remaining = adapter->num_rx_queues;
1319 int txr_remaining = adapter->num_tx_queues;
1320 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1321 int err;
047e0030 1322
5536d210
AD		 1323 if (q_vectors >= (rxr_remaining + txr_remaining)) {
1324 for (; rxr_remaining; v_idx++) {
1325 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1326 0, 0, 1, rxr_idx);
047e0030 1327
5536d210
AD		 1328 if (err)
1329 goto err_out;
1330
1331 /* update counts and index */
1332 rxr_remaining--;
1333 rxr_idx++;
047e0030 1334 }
047e0030 1335 }
5536d210
AD		 1336
1337 for (; v_idx < q_vectors; v_idx++) {
1338 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1339 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
9005df38 1340
5536d210
AD		 1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1342 tqpv, txr_idx, rqpv, rxr_idx);
1343
1344 if (err)
1345 goto err_out;
1346
1347 /* update counts and index */
1348 rxr_remaining -= rqpv;
1349 txr_remaining -= tqpv;
1350 rxr_idx++;
1351 txr_idx++;
1352 }
1353
047e0030 1354 return 0;
5536d210
AD		 1355
1356err_out:
1357 adapter->num_tx_queues = 0;
1358 adapter->num_rx_queues = 0;
1359 adapter->num_q_vectors = 0;
1360
1361 while (v_idx--)
1362 igb_free_q_vector(adapter, v_idx);
1363
1364 return -ENOMEM;
047e0030
AD		 1365}
1366
1367/**
b980ac18
JK		 1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1369 * @adapter: board private structure to initialize
1370 * @msix: boolean value of MSIX capability
047e0030 1371 *
b980ac18 1372 * This function initializes the interrupts and allocates all of the queues.
047e0030 1373 **/
53c7d064 1374static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
047e0030
AD		 1375{
1376 struct pci_dev *pdev = adapter->pdev;
1377 int err;
1378
53c7d064 1379 igb_set_interrupt_capability(adapter, msix);
047e0030
AD		 1380
1381 err = igb_alloc_q_vectors(adapter);
1382 if (err) {
1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1384 goto err_alloc_q_vectors;
1385 }
1386
5536d210 1387 igb_cache_ring_register(adapter);
047e0030
AD		 1388
1389 return 0;
5536d210 1390
047e0030
AD		 1391err_alloc_q_vectors:
1392 igb_reset_interrupt_capability(adapter);
1393 return err;
1394}
1395
9d5c8243 1396/**
b980ac18
JK		 1397 * igb_request_irq - initialize interrupts
1398 * @adapter: board private structure to initialize
9d5c8243 1399 *
b980ac18
JK		 1400 * Attempts to configure interrupts using the best available
1401 * capabilities of the hardware and kernel.
9d5c8243
AK		 1402 **/
1403static int igb_request_irq(struct igb_adapter *adapter)
1404{
1405 struct net_device *netdev = adapter->netdev;
047e0030 1406 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 1407 int err = 0;
1408
cd14ef54 1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243 1410 err = igb_request_msix(adapter);
844290e5 1411 if (!err)
9d5c8243 1412 goto request_done;
9d5c8243 1413 /* fall back to MSI */
5536d210
AD		 1414 igb_free_all_tx_resources(adapter);
1415 igb_free_all_rx_resources(adapter);
53c7d064 1416
047e0030 1417 igb_clear_interrupt_scheme(adapter);
53c7d064
SA		 1418 err = igb_init_interrupt_scheme(adapter, false);
1419 if (err)
047e0030 1420 goto request_done;
53c7d064 1421
047e0030
AD		 1422 igb_setup_all_tx_resources(adapter);
1423 igb_setup_all_rx_resources(adapter);
53c7d064 1424 igb_configure(adapter);
9d5c8243 1425 }
844290e5 1426
c74d588e
AD		 1427 igb_assign_vector(adapter->q_vector[0], 0);
1428
7dfc16fa 1429 if (adapter->flags & IGB_FLAG_HAS_MSI) {
c74d588e 1430 err = request_irq(pdev->irq, igb_intr_msi, 0,
047e0030 1431 netdev->name, adapter);
9d5c8243
AK		 1432 if (!err)
1433 goto request_done;
047e0030 1434
9d5c8243
AK		 1435 /* fall back to legacy interrupts */
1436 igb_reset_interrupt_capability(adapter);
7dfc16fa 1437 adapter->flags &= ~IGB_FLAG_HAS_MSI;
9d5c8243
AK		 1438 }
1439
c74d588e 1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
047e0030 1441 netdev->name, adapter);
9d5c8243 1442
6cb5e577 1443 if (err)
c74d588e 1444 dev_err(&pdev->dev, "Error %d getting interrupt\n",
9d5c8243 1445 err);
9d5c8243
AK		 1446
1447request_done:
1448 return err;
1449}
1450
1451static void igb_free_irq(struct igb_adapter *adapter)
1452{
cd14ef54 1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
9d5c8243
AK		 1454 int vector = 0, i;
1455
047e0030 1456 free_irq(adapter->msix_entries[vector++].vector, adapter);
9d5c8243 1457
0d1ae7f4 1458 for (i = 0; i < adapter->num_q_vectors; i++)
047e0030 1459 free_irq(adapter->msix_entries[vector++].vector,
0d1ae7f4 1460 adapter->q_vector[i]);
047e0030
AD		 1461 } else {
1462 free_irq(adapter->pdev->irq, adapter);
9d5c8243 1463 }
9d5c8243
AK		 1464}
1465
1466/**
b980ac18
JK		 1467 * igb_irq_disable - Mask off interrupt generation on the NIC
1468 * @adapter: board private structure
9d5c8243
AK		 1469 **/
1470static void igb_irq_disable(struct igb_adapter *adapter)
1471{
1472 struct e1000_hw *hw = &adapter->hw;
1473
b980ac18 1474 /* we need to be careful when disabling interrupts. The VFs are also
25568a53
AD		 1475 * mapped into these registers and so clearing the bits can cause
1476 * issues on the VF drivers so we only need to clear what we set
1477 */
cd14ef54 1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
2dfd1212 1479 u32 regval = rd32(E1000_EIAM);
9005df38 1480
2dfd1212
AD		 1481 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1482 wr32(E1000_EIMC, adapter->eims_enable_mask);
1483 regval = rd32(E1000_EIAC);
1484 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
9d5c8243 1485 }
844290e5
PW		 1486
1487 wr32(E1000_IAM, 0);
9d5c8243
AK		 1488 wr32(E1000_IMC, ~0);
1489 wrfl();
cd14ef54 1490 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
81a61859 1491 int i;
9005df38 1492
81a61859
ET		 1493 for (i = 0; i < adapter->num_q_vectors; i++)
1494 synchronize_irq(adapter->msix_entries[i].vector);
1495 } else {
1496 synchronize_irq(adapter->pdev->irq);
1497 }
9d5c8243
AK		 1498}
1499
1500/**
b980ac18
JK		 1501 * igb_irq_enable - Enable default interrupt generation settings
1502 * @adapter: board private structure
9d5c8243
AK		 1503 **/
1504static void igb_irq_enable(struct igb_adapter *adapter)
1505{
1506 struct e1000_hw *hw = &adapter->hw;
1507
cd14ef54 1508 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
06218a8d 1509 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
2dfd1212 1510 u32 regval = rd32(E1000_EIAC);
9005df38 1511
2dfd1212
AD		 1512 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1513 regval = rd32(E1000_EIAM);
1514 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
844290e5 1515 wr32(E1000_EIMS, adapter->eims_enable_mask);
25568a53 1516 if (adapter->vfs_allocated_count) {
4ae196df 1517 wr32(E1000_MBVFIMR, 0xFF);
25568a53
AD		 1518 ims |= E1000_IMS_VMMB;
1519 }
1520 wr32(E1000_IMS, ims);
844290e5 1521 } else {
55cac248
AD		 1522 wr32(E1000_IMS, IMS_ENABLE_MASK |
1523 E1000_IMS_DRSTA);
1524 wr32(E1000_IAM, IMS_ENABLE_MASK |
1525 E1000_IMS_DRSTA);
844290e5 1526 }
9d5c8243
AK		 1527}
1528
1529static void igb_update_mng_vlan(struct igb_adapter *adapter)
1530{
51466239 1531 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1532 u16 vid = adapter->hw.mng_cookie.vlan_id;
1533 u16 old_vid = adapter->mng_vlan_id;
51466239
AD		 1534
1535 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1536 /* add VID to filter table */
1537 igb_vfta_set(hw, vid, true);
1538 adapter->mng_vlan_id = vid;
1539 } else {
1540 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1541 }
1542
1543 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1544 (vid != old_vid) &&
b2cb09b1 1545 !test_bit(old_vid, adapter->active_vlans)) {
51466239
AD		 1546 /* remove VID from filter table */
1547 igb_vfta_set(hw, old_vid, false);
9d5c8243
AK		 1548 }
1549}
1550
1551/**
b980ac18
JK		 1552 * igb_release_hw_control - release control of the h/w to f/w
1553 * @adapter: address of board private structure
9d5c8243 1554 *
b980ac18
JK		 1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1556 * For ASF and Pass Through versions of f/w this means that the
1557 * driver is no longer loaded.
9d5c8243
AK		 1558 **/
1559static void igb_release_hw_control(struct igb_adapter *adapter)
1560{
1561 struct e1000_hw *hw = &adapter->hw;
1562 u32 ctrl_ext;
1563
1564 /* Let firmware take over control of h/w */
1565 ctrl_ext = rd32(E1000_CTRL_EXT);
1566 wr32(E1000_CTRL_EXT,
1567 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1568}
1569
9d5c8243 1570/**
b980ac18
JK		 1571 * igb_get_hw_control - get control of the h/w from f/w
1572 * @adapter: address of board private structure
9d5c8243 1573 *
b980ac18
JK		 1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1575 * For ASF and Pass Through versions of f/w this means that
1576 * the driver is loaded.
9d5c8243
AK		 1577 **/
1578static void igb_get_hw_control(struct igb_adapter *adapter)
1579{
1580 struct e1000_hw *hw = &adapter->hw;
1581 u32 ctrl_ext;
1582
1583 /* Let firmware know the driver has taken over */
1584 ctrl_ext = rd32(E1000_CTRL_EXT);
1585 wr32(E1000_CTRL_EXT,
1586 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1587}
1588
9d5c8243 1589/**
b980ac18
JK		 1590 * igb_configure - configure the hardware for RX and TX
1591 * @adapter: private board structure
9d5c8243
AK		 1592 **/
1593static void igb_configure(struct igb_adapter *adapter)
1594{
1595 struct net_device *netdev = adapter->netdev;
1596 int i;
1597
1598 igb_get_hw_control(adapter);
ff41f8dc 1599 igb_set_rx_mode(netdev);
9d5c8243
AK		 1600
1601 igb_restore_vlan(adapter);
9d5c8243 1602
85b430b4 1603 igb_setup_tctl(adapter);
06cf2666 1604 igb_setup_mrqc(adapter);
9d5c8243 1605 igb_setup_rctl(adapter);
85b430b4
AD		 1606
1607 igb_configure_tx(adapter);
9d5c8243 1608 igb_configure_rx(adapter);
662d7205
AD		 1609
1610 igb_rx_fifo_flush_82575(&adapter->hw);
1611
c493ea45 1612 /* call igb_desc_unused which always leaves
9d5c8243 1613 * at least 1 descriptor unused to make sure
b980ac18
JK		 1614 * next_to_use != next_to_clean
1615 */
9d5c8243 1616 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 1617 struct igb_ring *ring = adapter->rx_ring[i];
cd392f5c 1618 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
9d5c8243 1619 }
9d5c8243
AK		 1620}
1621
88a268c1 1622/**
b980ac18
JK		 1623 * igb_power_up_link - Power up the phy/serdes link
1624 * @adapter: address of board private structure
88a268c1
NN		 1625 **/
1626void igb_power_up_link(struct igb_adapter *adapter)
1627{
76886596
AA		 1628 igb_reset_phy(&adapter->hw);
1629
88a268c1
NN		 1630 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1631 igb_power_up_phy_copper(&adapter->hw);
1632 else
1633 igb_power_up_serdes_link_82575(&adapter->hw);
aec653c4
TF		 1634
1635 igb_setup_link(&adapter->hw);
88a268c1
NN		 1636}
1637
1638/**
b980ac18
JK		 1639 * igb_power_down_link - Power down the phy/serdes link
1640 * @adapter: address of board private structure
88a268c1
NN		 1641 */
1642static void igb_power_down_link(struct igb_adapter *adapter)
1643{
1644 if (adapter->hw.phy.media_type == e1000_media_type_copper)
1645 igb_power_down_phy_copper_82575(&adapter->hw);
1646 else
1647 igb_shutdown_serdes_link_82575(&adapter->hw);
1648}
9d5c8243 1649
56cec249
CW		 1650/**
1651 * Detect and switch function for Media Auto Sense
1652 * @adapter: address of the board private structure
1653 **/
1654static void igb_check_swap_media(struct igb_adapter *adapter)
1655{
1656 struct e1000_hw *hw = &adapter->hw;
1657 u32 ctrl_ext, connsw;
1658 bool swap_now = false;
1659
1660 ctrl_ext = rd32(E1000_CTRL_EXT);
1661 connsw = rd32(E1000_CONNSW);
1662
1663 /* need to live swap if current media is copper and we have fiber/serdes
1664 * to go to.
1665 */
1666
1667 if ((hw->phy.media_type == e1000_media_type_copper) &&
1668 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
1669 swap_now = true;
1670 } else if (!(connsw & E1000_CONNSW_SERDESD)) {
1671 /* copper signal takes time to appear */
1672 if (adapter->copper_tries < 4) {
1673 adapter->copper_tries++;
1674 connsw |= E1000_CONNSW_AUTOSENSE_CONF;
1675 wr32(E1000_CONNSW, connsw);
1676 return;
1677 } else {
1678 adapter->copper_tries = 0;
1679 if ((connsw & E1000_CONNSW_PHYSD) &&
1680 (!(connsw & E1000_CONNSW_PHY_PDN))) {
1681 swap_now = true;
1682 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
1683 wr32(E1000_CONNSW, connsw);
1684 }
1685 }
1686 }
1687
1688 if (!swap_now)
1689 return;
1690
1691 switch (hw->phy.media_type) {
1692 case e1000_media_type_copper:
1693 netdev_info(adapter->netdev,
1694 "MAS: changing media to fiber/serdes\n");
1695 ctrl_ext |=
1696 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1697 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1698 adapter->copper_tries = 0;
1699 break;
1700 case e1000_media_type_internal_serdes:
1701 case e1000_media_type_fiber:
1702 netdev_info(adapter->netdev,
1703 "MAS: changing media to copper\n");
1704 ctrl_ext &=
1705 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1706 adapter->flags |= IGB_FLAG_MEDIA_RESET;
1707 break;
1708 default:
1709 /* shouldn't get here during regular operation */
1710 netdev_err(adapter->netdev,
1711 "AMS: Invalid media type found, returning\n");
1712 break;
1713 }
1714 wr32(E1000_CTRL_EXT, ctrl_ext);
1715}
1716
9d5c8243 1717/**
b980ac18
JK		 1718 * igb_up - Open the interface and prepare it to handle traffic
1719 * @adapter: board private structure
9d5c8243 1720 **/
9d5c8243
AK		 1721int igb_up(struct igb_adapter *adapter)
1722{
1723 struct e1000_hw *hw = &adapter->hw;
1724 int i;
1725
1726 /* hardware has been reset, we need to reload some things */
1727 igb_configure(adapter);
1728
1729 clear_bit(__IGB_DOWN, &adapter->state);
1730
0d1ae7f4
AD		 1731 for (i = 0; i < adapter->num_q_vectors; i++)
1732 napi_enable(&(adapter->q_vector[i]->napi));
1733
cd14ef54 1734 if (adapter->flags & IGB_FLAG_HAS_MSIX)
9d5c8243 1735 igb_configure_msix(adapter);
feeb2721
AD		 1736 else
1737 igb_assign_vector(adapter->q_vector[0], 0);
9d5c8243
AK		 1738
1739 /* Clear any pending interrupts. */
1740 rd32(E1000_ICR);
1741 igb_irq_enable(adapter);
1742
d4960307
AD		 1743 /* notify VFs that reset has been completed */
1744 if (adapter->vfs_allocated_count) {
1745 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 1746
d4960307
AD		 1747 reg_data |= E1000_CTRL_EXT_PFRSTD;
1748 wr32(E1000_CTRL_EXT, reg_data);
1749 }
1750
4cb9be7a
JB		 1751 netif_tx_start_all_queues(adapter->netdev);
1752
25568a53
AD		 1753 /* start the watchdog. */
1754 hw->mac.get_link_status = 1;
1755 schedule_work(&adapter->watchdog_task);
1756
f4c01e96
CW		 1757 if ((adapter->flags & IGB_FLAG_EEE) &&
1758 (!hw->dev_spec._82575.eee_disable))
1759 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
1760
9d5c8243
AK		 1761 return 0;
1762}
1763
1764void igb_down(struct igb_adapter *adapter)
1765{
9d5c8243 1766 struct net_device *netdev = adapter->netdev;
330a6d6a 1767 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 1768 u32 tctl, rctl;
1769 int i;
1770
1771 /* signal that we're down so the interrupt handler does not
b980ac18
JK		 1772 * reschedule our watchdog timer
1773 */
9d5c8243
AK		 1774 set_bit(__IGB_DOWN, &adapter->state);
1775
1776 /* disable receives in the hardware */
1777 rctl = rd32(E1000_RCTL);
1778 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1779 /* flush and sleep below */
1780
fd2ea0a7 1781 netif_tx_stop_all_queues(netdev);
9d5c8243
AK		 1782
1783 /* disable transmits in the hardware */
1784 tctl = rd32(E1000_TCTL);
1785 tctl &= ~E1000_TCTL_EN;
1786 wr32(E1000_TCTL, tctl);
1787 /* flush both disables and wait for them to finish */
1788 wrfl();
0d451e79 1789 usleep_range(10000, 11000);
9d5c8243 1790
41f149a2
CW		 1791 igb_irq_disable(adapter);
1792
aa9b8cc4
AA		 1793 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
1794
41f149a2 1795 for (i = 0; i < adapter->num_q_vectors; i++) {
17a402a0
CW		 1796 if (adapter->q_vector[i]) {
1797 napi_synchronize(&adapter->q_vector[i]->napi);
1798 napi_disable(&adapter->q_vector[i]->napi);
1799 }
41f149a2 1800 }
9d5c8243 1801
9d5c8243
AK		 1802
1803 del_timer_sync(&adapter->watchdog_timer);
1804 del_timer_sync(&adapter->phy_info_timer);
1805
9d5c8243 1806 netif_carrier_off(netdev);
04fe6358
AD		 1807
1808 /* record the stats before reset*/
12dcd86b
ED		 1809 spin_lock(&adapter->stats64_lock);
1810 igb_update_stats(adapter, &adapter->stats64);
1811 spin_unlock(&adapter->stats64_lock);
04fe6358 1812
9d5c8243
AK		 1813 adapter->link_speed = 0;
1814 adapter->link_duplex = 0;
1815
3023682e
JK		 1816 if (!pci_channel_offline(adapter->pdev))
1817 igb_reset(adapter);
9d5c8243
AK		 1818 igb_clean_all_tx_rings(adapter);
1819 igb_clean_all_rx_rings(adapter);
7e0e99ef
AD		 1820#ifdef CONFIG_IGB_DCA
1821
1822 /* since we reset the hardware DCA settings were cleared */
1823 igb_setup_dca(adapter);
1824#endif
9d5c8243
AK		 1825}
1826
1827void igb_reinit_locked(struct igb_adapter *adapter)
1828{
1829 WARN_ON(in_interrupt());
1830 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 1831 usleep_range(1000, 2000);
9d5c8243
AK		 1832 igb_down(adapter);
1833 igb_up(adapter);
1834 clear_bit(__IGB_RESETTING, &adapter->state);
1835}
1836
56cec249
CW		 1837/** igb_enable_mas - Media Autosense re-enable after swap
1838 *
1839 * @adapter: adapter struct
1840 **/
1841static s32 igb_enable_mas(struct igb_adapter *adapter)
1842{
1843 struct e1000_hw *hw = &adapter->hw;
1844 u32 connsw;
1845 s32 ret_val = 0;
1846
1847 connsw = rd32(E1000_CONNSW);
1848 if (!(hw->phy.media_type == e1000_media_type_copper))
1849 return ret_val;
1850
1851 /* configure for SerDes media detect */
1852 if (!(connsw & E1000_CONNSW_SERDESD)) {
1853 connsw |= E1000_CONNSW_ENRGSRC;
1854 connsw |= E1000_CONNSW_AUTOSENSE_EN;
1855 wr32(E1000_CONNSW, connsw);
1856 wrfl();
1857 } else if (connsw & E1000_CONNSW_SERDESD) {
1858 /* already SerDes, no need to enable anything */
1859 return ret_val;
1860 } else {
1861 netdev_info(adapter->netdev,
1862 "MAS: Unable to configure feature, disabling..\n");
1863 adapter->flags &= ~IGB_FLAG_MAS_ENABLE;
1864 }
1865 return ret_val;
1866}
1867
9d5c8243
AK		 1868void igb_reset(struct igb_adapter *adapter)
1869{
090b1795 1870 struct pci_dev *pdev = adapter->pdev;
9d5c8243 1871 struct e1000_hw *hw = &adapter->hw;
2d064c06
AD		 1872 struct e1000_mac_info *mac = &hw->mac;
1873 struct e1000_fc_info *fc = &hw->fc;
d48507fe 1874 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
9d5c8243
AK		 1875
1876 /* Repartition Pba for greater than 9k mtu
1877 * To take effect CTRL.RST is required.
1878 */
fa4dfae0 1879 switch (mac->type) {
d2ba2ed8 1880 case e1000_i350:
ceb5f13b 1881 case e1000_i354:
55cac248
AD		 1882 case e1000_82580:
1883 pba = rd32(E1000_RXPBS);
1884 pba = igb_rxpbs_adjust_82580(pba);
1885 break;
fa4dfae0 1886 case e1000_82576:
d249be54
AD		 1887 pba = rd32(E1000_RXPBS);
1888 pba &= E1000_RXPBS_SIZE_MASK_82576;
fa4dfae0
AD		 1889 break;
1890 case e1000_82575:
f96a8a0b
CW		 1891 case e1000_i210:
1892 case e1000_i211:
fa4dfae0
AD		 1893 default:
1894 pba = E1000_PBA_34K;
1895 break;
2d064c06 1896 }
9d5c8243 1897
2d064c06
AD		 1898 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1899 (mac->type < e1000_82576)) {
9d5c8243
AK		 1900 /* adjust PBA for jumbo frames */
1901 wr32(E1000_PBA, pba);
1902
1903 /* To maintain wire speed transmits, the Tx FIFO should be
1904 * large enough to accommodate two full transmit packets,
1905 * rounded up to the next 1KB and expressed in KB. Likewise,
1906 * the Rx FIFO should be large enough to accommodate at least
1907 * one full receive packet and is similarly rounded up and
b980ac18
JK		 1908 * expressed in KB.
1909 */
9d5c8243
AK		 1910 pba = rd32(E1000_PBA);
1911 /* upper 16 bits has Tx packet buffer allocation size in KB */
1912 tx_space = pba >> 16;
1913 /* lower 16 bits has Rx packet buffer allocation size in KB */
1914 pba &= 0xffff;
b980ac18
JK		 1915 /* the Tx fifo also stores 16 bytes of information about the Tx
1916 * but don't include ethernet FCS because hardware appends it
1917 */
9d5c8243 1918 min_tx_space = (adapter->max_frame_size +
85e8d004 1919 sizeof(union e1000_adv_tx_desc) -
9d5c8243
AK		 1920 ETH_FCS_LEN) * 2;
1921 min_tx_space = ALIGN(min_tx_space, 1024);
1922 min_tx_space >>= 10;
1923 /* software strips receive CRC, so leave room for it */
1924 min_rx_space = adapter->max_frame_size;
1925 min_rx_space = ALIGN(min_rx_space, 1024);
1926 min_rx_space >>= 10;
1927
1928 /* If current Tx allocation is less than the min Tx FIFO size,
1929 * and the min Tx FIFO size is less than the current Rx FIFO
b980ac18
JK		 1930 * allocation, take space away from current Rx allocation
1931 */
9d5c8243
AK		 1932 if (tx_space < min_tx_space &&
1933 ((min_tx_space - tx_space) < pba)) {
1934 pba = pba - (min_tx_space - tx_space);
1935
b980ac18
JK		 1936 /* if short on Rx space, Rx wins and must trump Tx
1937 * adjustment
1938 */
9d5c8243
AK		 1939 if (pba < min_rx_space)
1940 pba = min_rx_space;
1941 }
2d064c06 1942 wr32(E1000_PBA, pba);
9d5c8243 1943 }
9d5c8243
AK		 1944
1945 /* flow control settings */
1946 /* The high water mark must be low enough to fit one full frame
1947 * (or the size used for early receive) above it in the Rx FIFO.
1948 * Set it to the lower of:
1949 * - 90% of the Rx FIFO size, or
b980ac18
JK		 1950 * - the full Rx FIFO size minus one full frame
1951 */
9d5c8243 1952 hwm = min(((pba << 10) * 9 / 10),
2d064c06 1953 ((pba << 10) - 2 * adapter->max_frame_size));
9d5c8243 1954
d48507fe 1955 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */
d405ea3e 1956 fc->low_water = fc->high_water - 16;
9d5c8243
AK		 1957 fc->pause_time = 0xFFFF;
1958 fc->send_xon = 1;
0cce119a 1959 fc->current_mode = fc->requested_mode;
9d5c8243 1960
4ae196df
AD		 1961 /* disable receive for all VFs and wait one second */
1962 if (adapter->vfs_allocated_count) {
1963 int i;
9005df38 1964
4ae196df 1965 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
8fa7e0f7 1966 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
4ae196df
AD		 1967
1968 /* ping all the active vfs to let them know we are going down */
f2ca0dbe 1969 igb_ping_all_vfs(adapter);
4ae196df
AD		 1970
1971 /* disable transmits and receives */
1972 wr32(E1000_VFRE, 0);
1973 wr32(E1000_VFTE, 0);
1974 }
1975
9d5c8243 1976 /* Allow time for pending master requests to run */
330a6d6a 1977 hw->mac.ops.reset_hw(hw);
9d5c8243
AK		 1978 wr32(E1000_WUC, 0);
1979
56cec249
CW		 1980 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
1981 /* need to resetup here after media swap */
1982 adapter->ei.get_invariants(hw);
1983 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
1984 }
1985 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
1986 if (igb_enable_mas(adapter))
1987 dev_err(&pdev->dev,
1988 "Error enabling Media Auto Sense\n");
1989 }
330a6d6a 1990 if (hw->mac.ops.init_hw(hw))
090b1795 1991 dev_err(&pdev->dev, "Hardware Error\n");
831ec0b4 1992
b980ac18 1993 /* Flow control settings reset on hardware reset, so guarantee flow
a27416bb
MV		 1994 * control is off when forcing speed.
1995 */
1996 if (!hw->mac.autoneg)
1997 igb_force_mac_fc(hw);
1998
b6e0c419 1999 igb_init_dmac(adapter, pba);
e428893b
CW		 2000#ifdef CONFIG_IGB_HWMON
2001 /* Re-initialize the thermal sensor on i350 devices. */
2002 if (!test_bit(__IGB_DOWN, &adapter->state)) {
2003 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2004 /* If present, re-initialize the external thermal sensor
2005 * interface.
2006 */
2007 if (adapter->ets)
2008 mac->ops.init_thermal_sensor_thresh(hw);
2009 }
2010 }
2011#endif
b936136d 2012 /* Re-establish EEE setting */
f4c01e96
CW		 2013 if (hw->phy.media_type == e1000_media_type_copper) {
2014 switch (mac->type) {
2015 case e1000_i350:
2016 case e1000_i210:
2017 case e1000_i211:
c4c112f1 2018 igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2019 break;
2020 case e1000_i354:
c4c112f1 2021 igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2022 break;
2023 default:
2024 break;
2025 }
2026 }
88a268c1
NN		 2027 if (!netif_running(adapter->netdev))
2028 igb_power_down_link(adapter);
2029
9d5c8243
AK		 2030 igb_update_mng_vlan(adapter);
2031
2032 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2033 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2034
1f6e8178
MV		 2035 /* Re-enable PTP, where applicable. */
2036 igb_ptp_reset(adapter);
1f6e8178 2037
330a6d6a 2038 igb_get_phy_info(hw);
9d5c8243
AK		 2039}
2040
c8f44aff
MM		 2041static netdev_features_t igb_fix_features(struct net_device *netdev,
2042 netdev_features_t features)
b2cb09b1 2043{
b980ac18
JK		 2044 /* Since there is no support for separate Rx/Tx vlan accel
2045 * enable/disable make sure Tx flag is always in same state as Rx.
b2cb09b1 2046 */
f646968f
PM		 2047 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2048 features |= NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1 2049 else
f646968f 2050 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
b2cb09b1
JP		 2051
2052 return features;
2053}
2054
c8f44aff
MM		 2055static int igb_set_features(struct net_device *netdev,
2056 netdev_features_t features)
ac52caa3 2057{
c8f44aff 2058 netdev_features_t changed = netdev->features ^ features;
89eaefb6 2059 struct igb_adapter *adapter = netdev_priv(netdev);
ac52caa3 2060
f646968f 2061 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
b2cb09b1
JP		 2062 igb_vlan_mode(netdev, features);
2063
89eaefb6
BG		 2064 if (!(changed & NETIF_F_RXALL))
2065 return 0;
2066
2067 netdev->features = features;
2068
2069 if (netif_running(netdev))
2070 igb_reinit_locked(adapter);
2071 else
2072 igb_reset(adapter);
2073
ac52caa3
MM		 2074 return 0;
2075}
2076
2e5c6922 2077static const struct net_device_ops igb_netdev_ops = {
559e9c49 2078 .ndo_open = igb_open,
2e5c6922 2079 .ndo_stop = igb_close,
cd392f5c 2080 .ndo_start_xmit = igb_xmit_frame,
12dcd86b 2081 .ndo_get_stats64 = igb_get_stats64,
ff41f8dc 2082 .ndo_set_rx_mode = igb_set_rx_mode,
2e5c6922
SH		 2083 .ndo_set_mac_address = igb_set_mac,
2084 .ndo_change_mtu = igb_change_mtu,
2085 .ndo_do_ioctl = igb_ioctl,
2086 .ndo_tx_timeout = igb_tx_timeout,
2087 .ndo_validate_addr = eth_validate_addr,
2e5c6922
SH		 2088 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid,
2089 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid,
8151d294
WM		 2090 .ndo_set_vf_mac = igb_ndo_set_vf_mac,
2091 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan,
ed616689 2092 .ndo_set_vf_rate = igb_ndo_set_vf_bw,
70ea4783 2093 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk,
8151d294 2094 .ndo_get_vf_config = igb_ndo_get_vf_config,
2e5c6922
SH		 2095#ifdef CONFIG_NET_POLL_CONTROLLER
2096 .ndo_poll_controller = igb_netpoll,
2097#endif
b2cb09b1
JP		 2098 .ndo_fix_features = igb_fix_features,
2099 .ndo_set_features = igb_set_features,
2e5c6922
SH		 2100};
2101
d67974f0
CW		 2102/**
2103 * igb_set_fw_version - Configure version string for ethtool
2104 * @adapter: adapter struct
d67974f0
CW		 2105 **/
2106void igb_set_fw_version(struct igb_adapter *adapter)
2107{
2108 struct e1000_hw *hw = &adapter->hw;
0b1a6f2e
CW		 2109 struct e1000_fw_version fw;
2110
2111 igb_get_fw_version(hw, &fw);
2112
2113 switch (hw->mac.type) {
7dc98a62 2114 case e1000_i210:
0b1a6f2e 2115 case e1000_i211:
7dc98a62
CW		 2116 if (!(igb_get_flash_presence_i210(hw))) {
2117 snprintf(adapter->fw_version,
2118 sizeof(adapter->fw_version),
2119 "%2d.%2d-%d",
2120 fw.invm_major, fw.invm_minor,
2121 fw.invm_img_type);
2122 break;
2123 }
2124 /* fall through */
0b1a6f2e
CW		 2125 default:
2126 /* if option is rom valid, display its version too */
2127 if (fw.or_valid) {
2128 snprintf(adapter->fw_version,
2129 sizeof(adapter->fw_version),
2130 "%d.%d, 0x%08x, %d.%d.%d",
2131 fw.eep_major, fw.eep_minor, fw.etrack_id,
2132 fw.or_major, fw.or_build, fw.or_patch);
2133 /* no option rom */
7dc98a62 2134 } else if (fw.etrack_id != 0X0000) {
0b1a6f2e 2135 snprintf(adapter->fw_version,
7dc98a62
CW		 2136 sizeof(adapter->fw_version),
2137 "%d.%d, 0x%08x",
2138 fw.eep_major, fw.eep_minor, fw.etrack_id);
2139 } else {
2140 snprintf(adapter->fw_version,
2141 sizeof(adapter->fw_version),
2142 "%d.%d.%d",
2143 fw.eep_major, fw.eep_minor, fw.eep_build);
0b1a6f2e
CW		 2144 }
2145 break;
d67974f0 2146 }
d67974f0
CW		 2147}
2148
56cec249
CW		 2149/**
2150 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2151 *
2152 * @adapter: adapter struct
2153 **/
2154static void igb_init_mas(struct igb_adapter *adapter)
2155{
2156 struct e1000_hw *hw = &adapter->hw;
2157 u16 eeprom_data;
2158
2159 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2160 switch (hw->bus.func) {
2161 case E1000_FUNC_0:
2162 if (eeprom_data & IGB_MAS_ENABLE_0) {
2163 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2164 netdev_info(adapter->netdev,
2165 "MAS: Enabling Media Autosense for port %d\n",
2166 hw->bus.func);
2167 }
2168 break;
2169 case E1000_FUNC_1:
2170 if (eeprom_data & IGB_MAS_ENABLE_1) {
2171 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2172 netdev_info(adapter->netdev,
2173 "MAS: Enabling Media Autosense for port %d\n",
2174 hw->bus.func);
2175 }
2176 break;
2177 case E1000_FUNC_2:
2178 if (eeprom_data & IGB_MAS_ENABLE_2) {
2179 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2180 netdev_info(adapter->netdev,
2181 "MAS: Enabling Media Autosense for port %d\n",
2182 hw->bus.func);
2183 }
2184 break;
2185 case E1000_FUNC_3:
2186 if (eeprom_data & IGB_MAS_ENABLE_3) {
2187 adapter->flags |= IGB_FLAG_MAS_ENABLE;
2188 netdev_info(adapter->netdev,
2189 "MAS: Enabling Media Autosense for port %d\n",
2190 hw->bus.func);
2191 }
2192 break;
2193 default:
2194 /* Shouldn't get here */
2195 netdev_err(adapter->netdev,
2196 "MAS: Invalid port configuration, returning\n");
2197 break;
2198 }
2199}
2200
b980ac18
JK		 2201/**
2202 * igb_init_i2c - Init I2C interface
441fc6fd 2203 * @adapter: pointer to adapter structure
b980ac18 2204 **/
441fc6fd
CW		 2205static s32 igb_init_i2c(struct igb_adapter *adapter)
2206{
23d87824 2207 s32 status = 0;
441fc6fd
CW		 2208
2209 /* I2C interface supported on i350 devices */
2210 if (adapter->hw.mac.type != e1000_i350)
23d87824 2211 return 0;
441fc6fd
CW		 2212
2213 /* Initialize the i2c bus which is controlled by the registers.
2214 * This bus will use the i2c_algo_bit structue that implements
2215 * the protocol through toggling of the 4 bits in the register.
2216 */
2217 adapter->i2c_adap.owner = THIS_MODULE;
2218 adapter->i2c_algo = igb_i2c_algo;
2219 adapter->i2c_algo.data = adapter;
2220 adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2221 adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2222 strlcpy(adapter->i2c_adap.name, "igb BB",
2223 sizeof(adapter->i2c_adap.name));
2224 status = i2c_bit_add_bus(&adapter->i2c_adap);
2225 return status;
2226}
2227
9d5c8243 2228/**
b980ac18
JK		 2229 * igb_probe - Device Initialization Routine
2230 * @pdev: PCI device information struct
2231 * @ent: entry in igb_pci_tbl
9d5c8243 2232 *
b980ac18 2233 * Returns 0 on success, negative on failure
9d5c8243 2234 *
b980ac18
JK		 2235 * igb_probe initializes an adapter identified by a pci_dev structure.
2236 * The OS initialization, configuring of the adapter private structure,
2237 * and a hardware reset occur.
9d5c8243 2238 **/
1dd06ae8 2239static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9d5c8243
AK		 2240{
2241 struct net_device *netdev;
2242 struct igb_adapter *adapter;
2243 struct e1000_hw *hw;
4337e993 2244 u16 eeprom_data = 0;
9835fd73 2245 s32 ret_val;
4337e993 2246 static int global_quad_port_a; /* global quad port a indication */
9d5c8243 2247 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
2d6a5e95 2248 int err, pci_using_dac;
9835fd73 2249 u8 part_str[E1000_PBANUM_LENGTH];
9d5c8243 2250
bded64a7
AG		 2251 /* Catch broken hardware that put the wrong VF device ID in
2252 * the PCIe SR-IOV capability.
2253 */
2254 if (pdev->is_virtfn) {
2255 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
f96a8a0b 2256 pci_name(pdev), pdev->vendor, pdev->device);
bded64a7
AG		 2257 return -EINVAL;
2258 }
2259
aed5dec3 2260 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 2261 if (err)
2262 return err;
2263
2264 pci_using_dac = 0;
dc4ff9bb 2265 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
9d5c8243 2266 if (!err) {
dc4ff9bb 2267 pci_using_dac = 1;
9d5c8243 2268 } else {
dc4ff9bb 2269 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9d5c8243 2270 if (err) {
dc4ff9bb
RK		 2271 dev_err(&pdev->dev,
2272 "No usable DMA configuration, aborting\n");
2273 goto err_dma;
9d5c8243
AK		 2274 }
2275 }
2276
aed5dec3 2277 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
b980ac18
JK		 2278 IORESOURCE_MEM),
2279 igb_driver_name);
9d5c8243
AK		 2280 if (err)
2281 goto err_pci_reg;
2282
19d5afd4 2283 pci_enable_pcie_error_reporting(pdev);
40a914fa 2284
9d5c8243 2285 pci_set_master(pdev);
c682fc23 2286 pci_save_state(pdev);
9d5c8243
AK		 2287
2288 err = -ENOMEM;
1bfaf07b 2289 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1cc3bd87 2290 IGB_MAX_TX_QUEUES);
9d5c8243
AK		 2291 if (!netdev)
2292 goto err_alloc_etherdev;
2293
2294 SET_NETDEV_DEV(netdev, &pdev->dev);
2295
2296 pci_set_drvdata(pdev, netdev);
2297 adapter = netdev_priv(netdev);
2298 adapter->netdev = netdev;
2299 adapter->pdev = pdev;
2300 hw = &adapter->hw;
2301 hw->back = adapter;
b3f4d599 2302 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9d5c8243 2303
9d5c8243 2304 err = -EIO;
89dbefb2 2305 hw->hw_addr = pci_iomap(pdev, 0, 0);
28b0759c 2306 if (!hw->hw_addr)
9d5c8243
AK		 2307 goto err_ioremap;
2308
2e5c6922 2309 netdev->netdev_ops = &igb_netdev_ops;
9d5c8243 2310 igb_set_ethtool_ops(netdev);
9d5c8243 2311 netdev->watchdog_timeo = 5 * HZ;
9d5c8243
AK		 2312
2313 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2314
89dbefb2
AS		 2315 netdev->mem_start = pci_resource_start(pdev, 0);
2316 netdev->mem_end = pci_resource_end(pdev, 0);
9d5c8243 2317
9d5c8243
AK		 2318 /* PCI config space info */
2319 hw->vendor_id = pdev->vendor;
2320 hw->device_id = pdev->device;
2321 hw->revision_id = pdev->revision;
2322 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2323 hw->subsystem_device_id = pdev->subsystem_device;
2324
9d5c8243
AK		 2325 /* Copy the default MAC, PHY and NVM function pointers */
2326 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2327 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2328 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2329 /* Initialize skew-specific constants */
2330 err = ei->get_invariants(hw);
2331 if (err)
450c87c8 2332 goto err_sw_init;
9d5c8243 2333
450c87c8 2334 /* setup the private structure */
9d5c8243
AK		 2335 err = igb_sw_init(adapter);
2336 if (err)
2337 goto err_sw_init;
2338
2339 igb_get_bus_info_pcie(hw);
2340
2341 hw->phy.autoneg_wait_to_complete = false;
9d5c8243
AK		 2342
2343 /* Copper options */
2344 if (hw->phy.media_type == e1000_media_type_copper) {
2345 hw->phy.mdix = AUTO_ALL_MODES;
2346 hw->phy.disable_polarity_correction = false;
2347 hw->phy.ms_type = e1000_ms_hw_default;
2348 }
2349
2350 if (igb_check_reset_block(hw))
2351 dev_info(&pdev->dev,
2352 "PHY reset is blocked due to SOL/IDER session.\n");
2353
b980ac18 2354 /* features is initialized to 0 in allocation, it might have bits
077887c3
AD		 2355 * set by igb_sw_init so we should use an or instead of an
2356 * assignment.
2357 */
2358 netdev->features |= NETIF_F_SG |
2359 NETIF_F_IP_CSUM |
2360 NETIF_F_IPV6_CSUM |
2361 NETIF_F_TSO |
2362 NETIF_F_TSO6 |
2363 NETIF_F_RXHASH |
2364 NETIF_F_RXCSUM |
f646968f
PM		 2365 NETIF_F_HW_VLAN_CTAG_RX |
2366 NETIF_F_HW_VLAN_CTAG_TX;
077887c3
AD		 2367
2368 /* copy netdev features into list of user selectable features */
2369 netdev->hw_features |= netdev->features;
89eaefb6 2370 netdev->hw_features |= NETIF_F_RXALL;
077887c3
AD		 2371
2372 /* set this bit last since it cannot be part of hw_features */
f646968f 2373 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
077887c3
AD		 2374
2375 netdev->vlan_features |= NETIF_F_TSO |
2376 NETIF_F_TSO6 |
2377 NETIF_F_IP_CSUM |
2378 NETIF_F_IPV6_CSUM |
2379 NETIF_F_SG;
48f29ffc 2380
6b8f0922
BG		 2381 netdev->priv_flags |= IFF_SUPP_NOFCS;
2382
7b872a55 2383 if (pci_using_dac) {
9d5c8243 2384 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 2385 netdev->vlan_features |= NETIF_F_HIGHDMA;
2386 }
9d5c8243 2387
ac52caa3
MM		 2388 if (hw->mac.type >= e1000_82576) {
2389 netdev->hw_features |= NETIF_F_SCTP_CSUM;
b9473560 2390 netdev->features |= NETIF_F_SCTP_CSUM;
ac52caa3 2391 }
b9473560 2392
01789349
JP		 2393 netdev->priv_flags |= IFF_UNICAST_FLT;
2394
330a6d6a 2395 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
9d5c8243
AK		 2396
2397 /* before reading the NVM, reset the controller to put the device in a
b980ac18
JK		 2398 * known good starting state
2399 */
9d5c8243
AK		 2400 hw->mac.ops.reset_hw(hw);
2401
ef3a0092
CW		 2402 /* make sure the NVM is good , i211/i210 parts can have special NVM
2403 * that doesn't contain a checksum
f96a8a0b 2404 */
ef3a0092
CW		 2405 switch (hw->mac.type) {
2406 case e1000_i210:
2407 case e1000_i211:
2408 if (igb_get_flash_presence_i210(hw)) {
2409 if (hw->nvm.ops.validate(hw) < 0) {
2410 dev_err(&pdev->dev,
2411 "The NVM Checksum Is Not Valid\n");
2412 err = -EIO;
2413 goto err_eeprom;
2414 }
2415 }
2416 break;
2417 default:
f96a8a0b
CW		 2418 if (hw->nvm.ops.validate(hw) < 0) {
2419 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2420 err = -EIO;
2421 goto err_eeprom;
2422 }
ef3a0092 2423 break;
9d5c8243
AK		 2424 }
2425
2426 /* copy the MAC address out of the NVM */
2427 if (hw->mac.ops.read_mac_addr(hw))
2428 dev_err(&pdev->dev, "NVM Read Error\n");
2429
2430 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
9d5c8243 2431
aaeb6cdf 2432 if (!is_valid_ether_addr(netdev->dev_addr)) {
9d5c8243
AK		 2433 dev_err(&pdev->dev, "Invalid MAC Address\n");
2434 err = -EIO;
2435 goto err_eeprom;
2436 }
2437
d67974f0
CW		 2438 /* get firmware version for ethtool -i */
2439 igb_set_fw_version(adapter);
2440
27dff8b2
TF		 2441 /* configure RXPBSIZE and TXPBSIZE */
2442 if (hw->mac.type == e1000_i210) {
2443 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
2444 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
2445 }
2446
c061b18d 2447 setup_timer(&adapter->watchdog_timer, igb_watchdog,
b980ac18 2448 (unsigned long) adapter);
c061b18d 2449 setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
b980ac18 2450 (unsigned long) adapter);
9d5c8243
AK		 2451
2452 INIT_WORK(&adapter->reset_task, igb_reset_task);
2453 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2454
450c87c8 2455 /* Initialize link properties that are user-changeable */
9d5c8243
AK		 2456 adapter->fc_autoneg = true;
2457 hw->mac.autoneg = true;
2458 hw->phy.autoneg_advertised = 0x2f;
2459
0cce119a
AD		 2460 hw->fc.requested_mode = e1000_fc_default;
2461 hw->fc.current_mode = e1000_fc_default;
9d5c8243 2462
9d5c8243
AK		 2463 igb_validate_mdi_setting(hw);
2464
63d4a8f9 2465 /* By default, support wake on port A */
a2cf8b6c 2466 if (hw->bus.func == 0)
63d4a8f9
MV		 2467 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2468
2469 /* Check the NVM for wake support on non-port A ports */
2470 if (hw->mac.type >= e1000_82580)
55cac248 2471 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
b980ac18
JK		 2472 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2473 &eeprom_data);
a2cf8b6c
AD		 2474 else if (hw->bus.func == 1)
2475 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
9d5c8243 2476
63d4a8f9
MV		 2477 if (eeprom_data & IGB_EEPROM_APME)
2478 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2479
2480 /* now that we have the eeprom settings, apply the special cases where
2481 * the eeprom may be wrong or the board simply won't support wake on
b980ac18
JK		 2482 * lan on a particular port
2483 */
9d5c8243
AK		 2484 switch (pdev->device) {
2485 case E1000_DEV_ID_82575GB_QUAD_COPPER:
63d4a8f9 2486 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2487 break;
2488 case E1000_DEV_ID_82575EB_FIBER_SERDES:
2d064c06
AD		 2489 case E1000_DEV_ID_82576_FIBER:
2490 case E1000_DEV_ID_82576_SERDES:
9d5c8243 2491 /* Wake events only supported on port A for dual fiber
b980ac18
JK		 2492 * regardless of eeprom setting
2493 */
9d5c8243 2494 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
63d4a8f9 2495 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243 2496 break;
c8ea5ea9 2497 case E1000_DEV_ID_82576_QUAD_COPPER:
d5aa2252 2498 case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
c8ea5ea9
AD		 2499 /* if quad port adapter, disable WoL on all but port A */
2500 if (global_quad_port_a != 0)
63d4a8f9 2501 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
c8ea5ea9
AD		 2502 else
2503 adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2504 /* Reset for multiple quad port adapters */
2505 if (++global_quad_port_a == 4)
2506 global_quad_port_a = 0;
2507 break;
63d4a8f9
MV		 2508 default:
2509 /* If the device can't wake, don't set software support */
2510 if (!device_can_wakeup(&adapter->pdev->dev))
2511 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
9d5c8243
AK		 2512 }
2513
2514 /* initialize the wol settings based on the eeprom settings */
63d4a8f9
MV		 2515 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2516 adapter->wol |= E1000_WUFC_MAG;
2517
2518 /* Some vendors want WoL disabled by default, but still supported */
2519 if ((hw->mac.type == e1000_i350) &&
2520 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2521 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2522 adapter->wol = 0;
2523 }
2524
2525 device_set_wakeup_enable(&adapter->pdev->dev,
2526 adapter->flags & IGB_FLAG_WOL_SUPPORTED);
9d5c8243
AK		 2527
2528 /* reset the hardware with the new settings */
2529 igb_reset(adapter);
2530
441fc6fd
CW		 2531 /* Init the I2C interface */
2532 err = igb_init_i2c(adapter);
2533 if (err) {
2534 dev_err(&pdev->dev, "failed to init i2c interface\n");
2535 goto err_eeprom;
2536 }
2537
9d5c8243 2538 /* let the f/w know that the h/w is now under the control of the
e52c0f96
CW		 2539 * driver.
2540 */
9d5c8243
AK		 2541 igb_get_hw_control(adapter);
2542
9d5c8243
AK		 2543 strcpy(netdev->name, "eth%d");
2544 err = register_netdev(netdev);
2545 if (err)
2546 goto err_register;
2547
b168dfc5
JB		 2548 /* carrier off reporting is important to ethtool even BEFORE open */
2549 netif_carrier_off(netdev);
2550
421e02f0 2551#ifdef CONFIG_IGB_DCA
bbd98fe4 2552 if (dca_add_requester(&pdev->dev) == 0) {
7dfc16fa 2553 adapter->flags |= IGB_FLAG_DCA_ENABLED;
fe4506b6 2554 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 2555 igb_setup_dca(adapter);
2556 }
fe4506b6 2557
38c845c7 2558#endif
e428893b
CW		 2559#ifdef CONFIG_IGB_HWMON
2560 /* Initialize the thermal sensor on i350 devices. */
2561 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2562 u16 ets_word;
3c89f6d0 2563
b980ac18 2564 /* Read the NVM to determine if this i350 device supports an
e428893b
CW		 2565 * external thermal sensor.
2566 */
2567 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2568 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2569 adapter->ets = true;
2570 else
2571 adapter->ets = false;
2572 if (igb_sysfs_init(adapter))
2573 dev_err(&pdev->dev,
2574 "failed to allocate sysfs resources\n");
2575 } else {
2576 adapter->ets = false;
2577 }
2578#endif
56cec249
CW		 2579 /* Check if Media Autosense is enabled */
2580 adapter->ei = *ei;
2581 if (hw->dev_spec._82575.mas_capable)
2582 igb_init_mas(adapter);
2583
673b8b70 2584 /* do hw tstamp init after resetting */
7ebae817 2585 igb_ptp_init(adapter);
673b8b70 2586
9d5c8243 2587 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
ceb5f13b
CW		 2588 /* print bus type/speed/width info, not applicable to i354 */
2589 if (hw->mac.type != e1000_i354) {
2590 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2591 netdev->name,
2592 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2593 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2594 "unknown"),
2595 ((hw->bus.width == e1000_bus_width_pcie_x4) ?
2596 "Width x4" :
2597 (hw->bus.width == e1000_bus_width_pcie_x2) ?
2598 "Width x2" :
2599 (hw->bus.width == e1000_bus_width_pcie_x1) ?
2600 "Width x1" : "unknown"), netdev->dev_addr);
2601 }
9d5c8243 2602
53ea6c7e
TF		 2603 if ((hw->mac.type >= e1000_i210 ||
2604 igb_get_flash_presence_i210(hw))) {
2605 ret_val = igb_read_part_string(hw, part_str,
2606 E1000_PBANUM_LENGTH);
2607 } else {
2608 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
2609 }
2610
9835fd73
CW		 2611 if (ret_val)
2612 strcpy(part_str, "Unknown");
2613 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
9d5c8243
AK		 2614 dev_info(&pdev->dev,
2615 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
cd14ef54 2616 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
7dfc16fa 2617 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
9d5c8243 2618 adapter->num_rx_queues, adapter->num_tx_queues);
f4c01e96
CW		 2619 if (hw->phy.media_type == e1000_media_type_copper) {
2620 switch (hw->mac.type) {
2621 case e1000_i350:
2622 case e1000_i210:
2623 case e1000_i211:
2624 /* Enable EEE for internal copper PHY devices */
c4c112f1 2625 err = igb_set_eee_i350(hw, true, true);
f4c01e96
CW		 2626 if ((!err) &&
2627 (!hw->dev_spec._82575.eee_disable)) {
2628 adapter->eee_advert =
2629 MDIO_EEE_100TX | MDIO_EEE_1000T;
2630 adapter->flags |= IGB_FLAG_EEE;
2631 }
2632 break;
2633 case e1000_i354:
ceb5f13b 2634 if ((rd32(E1000_CTRL_EXT) &
f4c01e96 2635 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
c4c112f1 2636 err = igb_set_eee_i354(hw, true, true);
f4c01e96
CW		 2637 if ((!err) &&
2638 (!hw->dev_spec._82575.eee_disable)) {
2639 adapter->eee_advert =
2640 MDIO_EEE_100TX | MDIO_EEE_1000T;
2641 adapter->flags |= IGB_FLAG_EEE;
2642 }
2643 }
2644 break;
2645 default:
2646 break;
ceb5f13b 2647 }
09b068d4 2648 }
749ab2cd 2649 pm_runtime_put_noidle(&pdev->dev);
9d5c8243
AK		 2650 return 0;
2651
2652err_register:
2653 igb_release_hw_control(adapter);
441fc6fd 2654 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
9d5c8243
AK		 2655err_eeprom:
2656 if (!igb_check_reset_block(hw))
f5f4cf08 2657 igb_reset_phy(hw);
9d5c8243
AK		 2658
2659 if (hw->flash_address)
2660 iounmap(hw->flash_address);
9d5c8243 2661err_sw_init:
047e0030 2662 igb_clear_interrupt_scheme(adapter);
75009b3a 2663 pci_iounmap(pdev, hw->hw_addr);
9d5c8243
AK		 2664err_ioremap:
2665 free_netdev(netdev);
2666err_alloc_etherdev:
559e9c49 2667 pci_release_selected_regions(pdev,
b980ac18 2668 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243
AK		 2669err_pci_reg:
2670err_dma:
2671 pci_disable_device(pdev);
2672 return err;
2673}
2674
fa44f2f1 2675#ifdef CONFIG_PCI_IOV
781798a1 2676static int igb_disable_sriov(struct pci_dev *pdev)
fa44f2f1
GR		 2677{
2678 struct net_device *netdev = pci_get_drvdata(pdev);
2679 struct igb_adapter *adapter = netdev_priv(netdev);
2680 struct e1000_hw *hw = &adapter->hw;
2681
2682 /* reclaim resources allocated to VFs */
2683 if (adapter->vf_data) {
2684 /* disable iov and allow time for transactions to clear */
b09186d2 2685 if (pci_vfs_assigned(pdev)) {
fa44f2f1
GR		 2686 dev_warn(&pdev->dev,
2687 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2688 return -EPERM;
2689 } else {
2690 pci_disable_sriov(pdev);
2691 msleep(500);
2692 }
2693
2694 kfree(adapter->vf_data);
2695 adapter->vf_data = NULL;
2696 adapter->vfs_allocated_count = 0;
2697 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2698 wrfl();
2699 msleep(100);
2700 dev_info(&pdev->dev, "IOV Disabled\n");
2701
2702 /* Re-enable DMA Coalescing flag since IOV is turned off */
2703 adapter->flags |= IGB_FLAG_DMAC;
2704 }
2705
2706 return 0;
2707}
2708
2709static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2710{
2711 struct net_device *netdev = pci_get_drvdata(pdev);
2712 struct igb_adapter *adapter = netdev_priv(netdev);
2713 int old_vfs = pci_num_vf(pdev);
2714 int err = 0;
2715 int i;
2716
cd14ef54 2717 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
50267196
MW		 2718 err = -EPERM;
2719 goto out;
2720 }
fa44f2f1
GR		 2721 if (!num_vfs)
2722 goto out;
fa44f2f1 2723
781798a1
SA		 2724 if (old_vfs) {
2725 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
2726 old_vfs, max_vfs);
2727 adapter->vfs_allocated_count = old_vfs;
2728 } else
2729 adapter->vfs_allocated_count = num_vfs;
fa44f2f1
GR		 2730
2731 adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2732 sizeof(struct vf_data_storage), GFP_KERNEL);
2733
2734 /* if allocation failed then we do not support SR-IOV */
2735 if (!adapter->vf_data) {
2736 adapter->vfs_allocated_count = 0;
2737 dev_err(&pdev->dev,
2738 "Unable to allocate memory for VF Data Storage\n");
2739 err = -ENOMEM;
2740 goto out;
2741 }
2742
781798a1
SA		 2743 /* only call pci_enable_sriov() if no VFs are allocated already */
2744 if (!old_vfs) {
2745 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2746 if (err)
2747 goto err_out;
2748 }
fa44f2f1
GR		 2749 dev_info(&pdev->dev, "%d VFs allocated\n",
2750 adapter->vfs_allocated_count);
2751 for (i = 0; i < adapter->vfs_allocated_count; i++)
2752 igb_vf_configure(adapter, i);
2753
2754 /* DMA Coalescing is not supported in IOV mode. */
2755 adapter->flags &= ~IGB_FLAG_DMAC;
2756 goto out;
2757
2758err_out:
2759 kfree(adapter->vf_data);
2760 adapter->vf_data = NULL;
2761 adapter->vfs_allocated_count = 0;
2762out:
2763 return err;
2764}
2765
2766#endif
b980ac18 2767/**
441fc6fd
CW		 2768 * igb_remove_i2c - Cleanup I2C interface
2769 * @adapter: pointer to adapter structure
b980ac18 2770 **/
441fc6fd
CW		 2771static void igb_remove_i2c(struct igb_adapter *adapter)
2772{
441fc6fd
CW		 2773 /* free the adapter bus structure */
2774 i2c_del_adapter(&adapter->i2c_adap);
2775}
2776
9d5c8243 2777/**
b980ac18
JK		 2778 * igb_remove - Device Removal Routine
2779 * @pdev: PCI device information struct
9d5c8243 2780 *
b980ac18
JK		 2781 * igb_remove is called by the PCI subsystem to alert the driver
2782 * that it should release a PCI device. The could be caused by a
2783 * Hot-Plug event, or because the driver is going to be removed from
2784 * memory.
9d5c8243 2785 **/
9f9a12f8 2786static void igb_remove(struct pci_dev *pdev)
9d5c8243
AK		 2787{
2788 struct net_device *netdev = pci_get_drvdata(pdev);
2789 struct igb_adapter *adapter = netdev_priv(netdev);
fe4506b6 2790 struct e1000_hw *hw = &adapter->hw;
9d5c8243 2791
749ab2cd 2792 pm_runtime_get_noresume(&pdev->dev);
e428893b
CW		 2793#ifdef CONFIG_IGB_HWMON
2794 igb_sysfs_exit(adapter);
2795#endif
441fc6fd 2796 igb_remove_i2c(adapter);
a79f4f88 2797 igb_ptp_stop(adapter);
b980ac18 2798 /* The watchdog timer may be rescheduled, so explicitly
760141a5
TH		 2799 * disable watchdog from being rescheduled.
2800 */
9d5c8243
AK		 2801 set_bit(__IGB_DOWN, &adapter->state);
2802 del_timer_sync(&adapter->watchdog_timer);
2803 del_timer_sync(&adapter->phy_info_timer);
2804
760141a5
TH		 2805 cancel_work_sync(&adapter->reset_task);
2806 cancel_work_sync(&adapter->watchdog_task);
9d5c8243 2807
421e02f0 2808#ifdef CONFIG_IGB_DCA
7dfc16fa 2809 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6
JC		 2810 dev_info(&pdev->dev, "DCA disabled\n");
2811 dca_remove_requester(&pdev->dev);
7dfc16fa 2812 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 2813 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 2814 }
2815#endif
2816
9d5c8243 2817 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 2818 * would have already happened in close and is redundant.
2819 */
9d5c8243
AK		 2820 igb_release_hw_control(adapter);
2821
2822 unregister_netdev(netdev);
2823
047e0030 2824 igb_clear_interrupt_scheme(adapter);
9d5c8243 2825
37680117 2826#ifdef CONFIG_PCI_IOV
fa44f2f1 2827 igb_disable_sriov(pdev);
37680117 2828#endif
559e9c49 2829
75009b3a 2830 pci_iounmap(pdev, hw->hw_addr);
28b0759c
AD		 2831 if (hw->flash_address)
2832 iounmap(hw->flash_address);
559e9c49 2833 pci_release_selected_regions(pdev,
b980ac18 2834 pci_select_bars(pdev, IORESOURCE_MEM));
9d5c8243 2835
1128c756 2836 kfree(adapter->shadow_vfta);
9d5c8243
AK		 2837 free_netdev(netdev);
2838
19d5afd4 2839 pci_disable_pcie_error_reporting(pdev);
40a914fa 2840
9d5c8243
AK		 2841 pci_disable_device(pdev);
2842}
2843
a6b623e0 2844/**
b980ac18
JK		 2845 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2846 * @adapter: board private structure to initialize
a6b623e0 2847 *
b980ac18
JK		 2848 * This function initializes the vf specific data storage and then attempts to
2849 * allocate the VFs. The reason for ordering it this way is because it is much
2850 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2851 * the memory for the VFs.
a6b623e0 2852 **/
9f9a12f8 2853static void igb_probe_vfs(struct igb_adapter *adapter)
a6b623e0
AD		 2854{
2855#ifdef CONFIG_PCI_IOV
2856 struct pci_dev *pdev = adapter->pdev;
f96a8a0b 2857 struct e1000_hw *hw = &adapter->hw;
a6b623e0 2858
f96a8a0b
CW		 2859 /* Virtualization features not supported on i210 family. */
2860 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2861 return;
2862
fa44f2f1 2863 pci_sriov_set_totalvfs(pdev, 7);
781798a1 2864 igb_pci_enable_sriov(pdev, max_vfs);
0224d663 2865
a6b623e0
AD		 2866#endif /* CONFIG_PCI_IOV */
2867}
2868
fa44f2f1 2869static void igb_init_queue_configuration(struct igb_adapter *adapter)
9d5c8243
AK		 2870{
2871 struct e1000_hw *hw = &adapter->hw;
374a542d 2872 u32 max_rss_queues;
9d5c8243 2873
374a542d 2874 /* Determine the maximum number of RSS queues supported. */
f96a8a0b 2875 switch (hw->mac.type) {
374a542d
MV		 2876 case e1000_i211:
2877 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2878 break;
2879 case e1000_82575:
f96a8a0b 2880 case e1000_i210:
374a542d
MV		 2881 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2882 break;
2883 case e1000_i350:
2884 /* I350 cannot do RSS and SR-IOV at the same time */
2885 if (!!adapter->vfs_allocated_count) {
2886 max_rss_queues = 1;
2887 break;
2888 }
2889 /* fall through */
2890 case e1000_82576:
2891 if (!!adapter->vfs_allocated_count) {
2892 max_rss_queues = 2;
2893 break;
2894 }
2895 /* fall through */
2896 case e1000_82580:
ceb5f13b 2897 case e1000_i354:
374a542d
MV		 2898 default:
2899 max_rss_queues = IGB_MAX_RX_QUEUES;
f96a8a0b 2900 break;
374a542d
MV		 2901 }
2902
2903 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2904
2905 /* Determine if we need to pair queues. */
2906 switch (hw->mac.type) {
2907 case e1000_82575:
f96a8a0b 2908 case e1000_i211:
374a542d 2909 /* Device supports enough interrupts without queue pairing. */
f96a8a0b 2910 break;
374a542d 2911 case e1000_82576:
b980ac18 2912 /* If VFs are going to be allocated with RSS queues then we
374a542d
MV		 2913 * should pair the queues in order to conserve interrupts due
2914 * to limited supply.
2915 */
2916 if ((adapter->rss_queues > 1) &&
2917 (adapter->vfs_allocated_count > 6))
2918 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2919 /* fall through */
2920 case e1000_82580:
2921 case e1000_i350:
ceb5f13b 2922 case e1000_i354:
374a542d 2923 case e1000_i210:
f96a8a0b 2924 default:
b980ac18 2925 /* If rss_queues > half of max_rss_queues, pair the queues in
374a542d
MV		 2926 * order to conserve interrupts due to limited supply.
2927 */
2928 if (adapter->rss_queues > (max_rss_queues / 2))
2929 adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
f96a8a0b
CW		 2930 break;
2931 }
fa44f2f1
GR		 2932}
2933
2934/**
b980ac18
JK		 2935 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2936 * @adapter: board private structure to initialize
fa44f2f1 2937 *
b980ac18
JK		 2938 * igb_sw_init initializes the Adapter private data structure.
2939 * Fields are initialized based on PCI device information and
2940 * OS network device settings (MTU size).
fa44f2f1
GR		 2941 **/
2942static int igb_sw_init(struct igb_adapter *adapter)
2943{
2944 struct e1000_hw *hw = &adapter->hw;
2945 struct net_device *netdev = adapter->netdev;
2946 struct pci_dev *pdev = adapter->pdev;
2947
2948 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2949
2950 /* set default ring sizes */
2951 adapter->tx_ring_count = IGB_DEFAULT_TXD;
2952 adapter->rx_ring_count = IGB_DEFAULT_RXD;
2953
2954 /* set default ITR values */
2955 adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2956 adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2957
2958 /* set default work limits */
2959 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2960
2961 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2962 VLAN_HLEN;
2963 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2964
2965 spin_lock_init(&adapter->stats64_lock);
2966#ifdef CONFIG_PCI_IOV
2967 switch (hw->mac.type) {
2968 case e1000_82576:
2969 case e1000_i350:
2970 if (max_vfs > 7) {
2971 dev_warn(&pdev->dev,
2972 "Maximum of 7 VFs per PF, using max\n");
d0f63acc 2973 max_vfs = adapter->vfs_allocated_count = 7;
fa44f2f1
GR		 2974 } else
2975 adapter->vfs_allocated_count = max_vfs;
2976 if (adapter->vfs_allocated_count)
2977 dev_warn(&pdev->dev,
2978 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2979 break;
2980 default:
2981 break;
2982 }
2983#endif /* CONFIG_PCI_IOV */
2984
2985 igb_init_queue_configuration(adapter);
a99955fc 2986
1128c756 2987 /* Setup and initialize a copy of the hw vlan table array */
b2adaca9
JP		 2988 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2989 GFP_ATOMIC);
1128c756 2990
a6b623e0 2991 /* This call may decrease the number of queues */
53c7d064 2992 if (igb_init_interrupt_scheme(adapter, true)) {
9d5c8243
AK		 2993 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2994 return -ENOMEM;
2995 }
2996
a6b623e0
AD		 2997 igb_probe_vfs(adapter);
2998
9d5c8243
AK		 2999 /* Explicitly disable IRQ since the NIC can be in any state. */
3000 igb_irq_disable(adapter);
3001
f96a8a0b 3002 if (hw->mac.type >= e1000_i350)
831ec0b4
CW		 3003 adapter->flags &= ~IGB_FLAG_DMAC;
3004
9d5c8243
AK		 3005 set_bit(__IGB_DOWN, &adapter->state);
3006 return 0;
3007}
3008
3009/**
b980ac18
JK		 3010 * igb_open - Called when a network interface is made active
3011 * @netdev: network interface device structure
9d5c8243 3012 *
b980ac18 3013 * Returns 0 on success, negative value on failure
9d5c8243 3014 *
b980ac18
JK		 3015 * The open entry point is called when a network interface is made
3016 * active by the system (IFF_UP). At this point all resources needed
3017 * for transmit and receive operations are allocated, the interrupt
3018 * handler is registered with the OS, the watchdog timer is started,
3019 * and the stack is notified that the interface is ready.
9d5c8243 3020 **/
749ab2cd 3021static int __igb_open(struct net_device *netdev, bool resuming)
9d5c8243
AK		 3022{
3023 struct igb_adapter *adapter = netdev_priv(netdev);
3024 struct e1000_hw *hw = &adapter->hw;
749ab2cd 3025 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3026 int err;
3027 int i;
3028
3029 /* disallow open during test */
749ab2cd
YZ		 3030 if (test_bit(__IGB_TESTING, &adapter->state)) {
3031 WARN_ON(resuming);
9d5c8243 3032 return -EBUSY;
749ab2cd
YZ		 3033 }
3034
3035 if (!resuming)
3036 pm_runtime_get_sync(&pdev->dev);
9d5c8243 3037
b168dfc5
JB		 3038 netif_carrier_off(netdev);
3039
9d5c8243
AK		 3040 /* allocate transmit descriptors */
3041 err = igb_setup_all_tx_resources(adapter);
3042 if (err)
3043 goto err_setup_tx;
3044
3045 /* allocate receive descriptors */
3046 err = igb_setup_all_rx_resources(adapter);
3047 if (err)
3048 goto err_setup_rx;
3049
88a268c1 3050 igb_power_up_link(adapter);
9d5c8243 3051
9d5c8243
AK		 3052 /* before we allocate an interrupt, we must be ready to handle it.
3053 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3054 * as soon as we call pci_request_irq, so we have to setup our
b980ac18
JK		 3055 * clean_rx handler before we do so.
3056 */
9d5c8243
AK		 3057 igb_configure(adapter);
3058
3059 err = igb_request_irq(adapter);
3060 if (err)
3061 goto err_req_irq;
3062
0c2cc02e
AD		 3063 /* Notify the stack of the actual queue counts. */
3064 err = netif_set_real_num_tx_queues(adapter->netdev,
3065 adapter->num_tx_queues);
3066 if (err)
3067 goto err_set_queues;
3068
3069 err = netif_set_real_num_rx_queues(adapter->netdev,
3070 adapter->num_rx_queues);
3071 if (err)
3072 goto err_set_queues;
3073
9d5c8243
AK		 3074 /* From here on the code is the same as igb_up() */
3075 clear_bit(__IGB_DOWN, &adapter->state);
3076
0d1ae7f4
AD		 3077 for (i = 0; i < adapter->num_q_vectors; i++)
3078 napi_enable(&(adapter->q_vector[i]->napi));
9d5c8243
AK		 3079
3080 /* Clear any pending interrupts. */
3081 rd32(E1000_ICR);
844290e5
PW		 3082
3083 igb_irq_enable(adapter);
3084
d4960307
AD		 3085 /* notify VFs that reset has been completed */
3086 if (adapter->vfs_allocated_count) {
3087 u32 reg_data = rd32(E1000_CTRL_EXT);
9005df38 3088
d4960307
AD		 3089 reg_data |= E1000_CTRL_EXT_PFRSTD;
3090 wr32(E1000_CTRL_EXT, reg_data);
3091 }
3092
d55b53ff
JK		 3093 netif_tx_start_all_queues(netdev);
3094
749ab2cd
YZ		 3095 if (!resuming)
3096 pm_runtime_put(&pdev->dev);
3097
25568a53
AD		 3098 /* start the watchdog. */
3099 hw->mac.get_link_status = 1;
3100 schedule_work(&adapter->watchdog_task);
9d5c8243
AK		 3101
3102 return 0;
3103
0c2cc02e
AD		 3104err_set_queues:
3105 igb_free_irq(adapter);
9d5c8243
AK		 3106err_req_irq:
3107 igb_release_hw_control(adapter);
88a268c1 3108 igb_power_down_link(adapter);
9d5c8243
AK		 3109 igb_free_all_rx_resources(adapter);
3110err_setup_rx:
3111 igb_free_all_tx_resources(adapter);
3112err_setup_tx:
3113 igb_reset(adapter);
749ab2cd
YZ		 3114 if (!resuming)
3115 pm_runtime_put(&pdev->dev);
9d5c8243
AK		 3116
3117 return err;
3118}
3119
749ab2cd
YZ		 3120static int igb_open(struct net_device *netdev)
3121{
3122 return __igb_open(netdev, false);
3123}
3124
9d5c8243 3125/**
b980ac18
JK		 3126 * igb_close - Disables a network interface
3127 * @netdev: network interface device structure
9d5c8243 3128 *
b980ac18 3129 * Returns 0, this is not allowed to fail
9d5c8243 3130 *
b980ac18
JK		 3131 * The close entry point is called when an interface is de-activated
3132 * by the OS. The hardware is still under the driver's control, but
3133 * needs to be disabled. A global MAC reset is issued to stop the
3134 * hardware, and all transmit and receive resources are freed.
9d5c8243 3135 **/
749ab2cd 3136static int __igb_close(struct net_device *netdev, bool suspending)
9d5c8243
AK		 3137{
3138 struct igb_adapter *adapter = netdev_priv(netdev);
749ab2cd 3139 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3140
3141 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
9d5c8243 3142
749ab2cd
YZ		 3143 if (!suspending)
3144 pm_runtime_get_sync(&pdev->dev);
3145
3146 igb_down(adapter);
9d5c8243
AK		 3147 igb_free_irq(adapter);
3148
3149 igb_free_all_tx_resources(adapter);
3150 igb_free_all_rx_resources(adapter);
3151
749ab2cd
YZ		 3152 if (!suspending)
3153 pm_runtime_put_sync(&pdev->dev);
9d5c8243
AK		 3154 return 0;
3155}
3156
749ab2cd
YZ		 3157static int igb_close(struct net_device *netdev)
3158{
3159 return __igb_close(netdev, false);
3160}
3161
9d5c8243 3162/**
b980ac18
JK		 3163 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3164 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9d5c8243 3165 *
b980ac18 3166 * Return 0 on success, negative on failure
9d5c8243 3167 **/
80785298 3168int igb_setup_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3169{
59d71989 3170 struct device *dev = tx_ring->dev;
9d5c8243
AK		 3171 int size;
3172
06034649 3173 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
f33005a6
AD		 3174
3175 tx_ring->tx_buffer_info = vzalloc(size);
06034649 3176 if (!tx_ring->tx_buffer_info)
9d5c8243 3177 goto err;
9d5c8243
AK		 3178
3179 /* round up to nearest 4K */
85e8d004 3180 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
9d5c8243
AK		 3181 tx_ring->size = ALIGN(tx_ring->size, 4096);
3182
5536d210
AD		 3183 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
3184 &tx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3185 if (!tx_ring->desc)
3186 goto err;
3187
9d5c8243
AK		 3188 tx_ring->next_to_use = 0;
3189 tx_ring->next_to_clean = 0;
81c2fc22 3190
9d5c8243
AK		 3191 return 0;
3192
3193err:
06034649 3194 vfree(tx_ring->tx_buffer_info);
f33005a6
AD		 3195 tx_ring->tx_buffer_info = NULL;
3196 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
9d5c8243
AK		 3197 return -ENOMEM;
3198}
3199
3200/**
b980ac18
JK		 3201 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3202 * (Descriptors) for all queues
3203 * @adapter: board private structure
9d5c8243 3204 *
b980ac18 3205 * Return 0 on success, negative on failure
9d5c8243
AK		 3206 **/
3207static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
3208{
439705e1 3209 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3210 int i, err = 0;
3211
3212 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 3213 err = igb_setup_tx_resources(adapter->tx_ring[i]);
9d5c8243 3214 if (err) {
439705e1 3215 dev_err(&pdev->dev,
9d5c8243
AK		 3216 "Allocation for Tx Queue %u failed\n", i);
3217 for (i--; i >= 0; i--)
3025a446 3218 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3219 break;
3220 }
3221 }
3222
3223 return err;
3224}
3225
3226/**
b980ac18
JK		 3227 * igb_setup_tctl - configure the transmit control registers
3228 * @adapter: Board private structure
9d5c8243 3229 **/
d7ee5b3a 3230void igb_setup_tctl(struct igb_adapter *adapter)
9d5c8243 3231{
9d5c8243
AK		 3232 struct e1000_hw *hw = &adapter->hw;
3233 u32 tctl;
9d5c8243 3234
85b430b4
AD		 3235 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3236 wr32(E1000_TXDCTL(0), 0);
9d5c8243
AK		 3237
3238 /* Program the Transmit Control Register */
9d5c8243
AK		 3239 tctl = rd32(E1000_TCTL);
3240 tctl &= ~E1000_TCTL_CT;
3241 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
3242 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3243
3244 igb_config_collision_dist(hw);
3245
9d5c8243
AK		 3246 /* Enable transmits */
3247 tctl |= E1000_TCTL_EN;
3248
3249 wr32(E1000_TCTL, tctl);
3250}
3251
85b430b4 3252/**
b980ac18
JK		 3253 * igb_configure_tx_ring - Configure transmit ring after Reset
3254 * @adapter: board private structure
3255 * @ring: tx ring to configure
85b430b4 3256 *
b980ac18 3257 * Configure a transmit ring after a reset.
85b430b4 3258 **/
d7ee5b3a 3259void igb_configure_tx_ring(struct igb_adapter *adapter,
9005df38 3260 struct igb_ring *ring)
85b430b4
AD		 3261{
3262 struct e1000_hw *hw = &adapter->hw;
a74420e0 3263 u32 txdctl = 0;
85b430b4
AD		 3264 u64 tdba = ring->dma;
3265 int reg_idx = ring->reg_idx;
3266
3267 /* disable the queue */
a74420e0 3268 wr32(E1000_TXDCTL(reg_idx), 0);
85b430b4
AD		 3269 wrfl();
3270 mdelay(10);
3271
3272 wr32(E1000_TDLEN(reg_idx),
b980ac18 3273 ring->count * sizeof(union e1000_adv_tx_desc));
85b430b4 3274 wr32(E1000_TDBAL(reg_idx),
b980ac18 3275 tdba & 0x00000000ffffffffULL);
85b430b4
AD		 3276 wr32(E1000_TDBAH(reg_idx), tdba >> 32);
3277
fce99e34 3278 ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
a74420e0 3279 wr32(E1000_TDH(reg_idx), 0);
fce99e34 3280 writel(0, ring->tail);
85b430b4
AD		 3281
3282 txdctl |= IGB_TX_PTHRESH;
3283 txdctl |= IGB_TX_HTHRESH << 8;
3284 txdctl |= IGB_TX_WTHRESH << 16;
3285
3286 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
3287 wr32(E1000_TXDCTL(reg_idx), txdctl);
3288}
3289
3290/**
b980ac18
JK		 3291 * igb_configure_tx - Configure transmit Unit after Reset
3292 * @adapter: board private structure
85b430b4 3293 *
b980ac18 3294 * Configure the Tx unit of the MAC after a reset.
85b430b4
AD		 3295 **/
3296static void igb_configure_tx(struct igb_adapter *adapter)
3297{
3298 int i;
3299
3300 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 3301 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
85b430b4
AD		 3302}
3303
9d5c8243 3304/**
b980ac18
JK		 3305 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3306 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
9d5c8243 3307 *
b980ac18 3308 * Returns 0 on success, negative on failure
9d5c8243 3309 **/
80785298 3310int igb_setup_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3311{
59d71989 3312 struct device *dev = rx_ring->dev;
f33005a6 3313 int size;
9d5c8243 3314
06034649 3315 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
f33005a6
AD		 3316
3317 rx_ring->rx_buffer_info = vzalloc(size);
06034649 3318 if (!rx_ring->rx_buffer_info)
9d5c8243 3319 goto err;
9d5c8243 3320
9d5c8243 3321 /* Round up to nearest 4K */
f33005a6 3322 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
9d5c8243
AK		 3323 rx_ring->size = ALIGN(rx_ring->size, 4096);
3324
5536d210
AD		 3325 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3326 &rx_ring->dma, GFP_KERNEL);
9d5c8243
AK		 3327 if (!rx_ring->desc)
3328 goto err;
3329
cbc8e55f 3330 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3331 rx_ring->next_to_clean = 0;
3332 rx_ring->next_to_use = 0;
9d5c8243 3333
9d5c8243
AK		 3334 return 0;
3335
3336err:
06034649
AD		 3337 vfree(rx_ring->rx_buffer_info);
3338 rx_ring->rx_buffer_info = NULL;
f33005a6 3339 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
9d5c8243
AK		 3340 return -ENOMEM;
3341}
3342
3343/**
b980ac18
JK		 3344 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3345 * (Descriptors) for all queues
3346 * @adapter: board private structure
9d5c8243 3347 *
b980ac18 3348 * Return 0 on success, negative on failure
9d5c8243
AK		 3349 **/
3350static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3351{
439705e1 3352 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 3353 int i, err = 0;
3354
3355 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 3356 err = igb_setup_rx_resources(adapter->rx_ring[i]);
9d5c8243 3357 if (err) {
439705e1 3358 dev_err(&pdev->dev,
9d5c8243
AK		 3359 "Allocation for Rx Queue %u failed\n", i);
3360 for (i--; i >= 0; i--)
3025a446 3361 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3362 break;
3363 }
3364 }
3365
3366 return err;
3367}
3368
06cf2666 3369/**
b980ac18
JK		 3370 * igb_setup_mrqc - configure the multiple receive queue control registers
3371 * @adapter: Board private structure
06cf2666
AD		 3372 **/
3373static void igb_setup_mrqc(struct igb_adapter *adapter)
3374{
3375 struct e1000_hw *hw = &adapter->hw;
3376 u32 mrqc, rxcsum;
ed12cc9a 3377 u32 j, num_rx_queues;
eb31f849 3378 u32 rss_key[10];
06cf2666 3379
eb31f849 3380 netdev_rss_key_fill(rss_key, sizeof(rss_key));
a57fe23e 3381 for (j = 0; j < 10; j++)
eb31f849 3382 wr32(E1000_RSSRK(j), rss_key[j]);
06cf2666 3383
a99955fc 3384 num_rx_queues = adapter->rss_queues;
06cf2666 3385
797fd4be 3386 switch (hw->mac.type) {
797fd4be
AD		 3387 case e1000_82576:
3388 /* 82576 supports 2 RSS queues for SR-IOV */
ed12cc9a 3389 if (adapter->vfs_allocated_count)
06cf2666 3390 num_rx_queues = 2;
797fd4be
AD		 3391 break;
3392 default:
3393 break;
06cf2666
AD		 3394 }
3395
ed12cc9a
LMV		 3396 if (adapter->rss_indir_tbl_init != num_rx_queues) {
3397 for (j = 0; j < IGB_RETA_SIZE; j++)
c502ea2e
CW		 3398 adapter->rss_indir_tbl[j] =
3399 (j * num_rx_queues) / IGB_RETA_SIZE;
ed12cc9a 3400 adapter->rss_indir_tbl_init = num_rx_queues;
06cf2666 3401 }
ed12cc9a 3402 igb_write_rss_indir_tbl(adapter);
06cf2666 3403
b980ac18 3404 /* Disable raw packet checksumming so that RSS hash is placed in
06cf2666
AD		 3405 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3406 * offloads as they are enabled by default
3407 */
3408 rxcsum = rd32(E1000_RXCSUM);
3409 rxcsum |= E1000_RXCSUM_PCSD;
3410
3411 if (adapter->hw.mac.type >= e1000_82576)
3412 /* Enable Receive Checksum Offload for SCTP */
3413 rxcsum |= E1000_RXCSUM_CRCOFL;
3414
3415 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3416 wr32(E1000_RXCSUM, rxcsum);
f96a8a0b 3417
039454a8
AA		 3418 /* Generate RSS hash based on packet types, TCP/UDP
3419 * port numbers and/or IPv4/v6 src and dst addresses
3420 */
f96a8a0b
CW		 3421 mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3422 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6 |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3425 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
06cf2666 3426
039454a8
AA		 3427 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3428 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3429 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3430 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3431
06cf2666
AD		 3432 /* If VMDq is enabled then we set the appropriate mode for that, else
3433 * we default to RSS so that an RSS hash is calculated per packet even
b980ac18
JK		 3434 * if we are only using one queue
3435 */
06cf2666
AD		 3436 if (adapter->vfs_allocated_count) {
3437 if (hw->mac.type > e1000_82575) {
3438 /* Set the default pool for the PF's first queue */
3439 u32 vtctl = rd32(E1000_VT_CTL);
9005df38 3440
06cf2666
AD		 3441 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3442 E1000_VT_CTL_DISABLE_DEF_POOL);
3443 vtctl |= adapter->vfs_allocated_count <<
3444 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3445 wr32(E1000_VT_CTL, vtctl);
3446 }
a99955fc 3447 if (adapter->rss_queues > 1)
f96a8a0b 3448 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
06cf2666 3449 else
f96a8a0b 3450 mrqc |= E1000_MRQC_ENABLE_VMDQ;
06cf2666 3451 } else {
f96a8a0b
CW		 3452 if (hw->mac.type != e1000_i211)
3453 mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
06cf2666
AD		 3454 }
3455 igb_vmm_control(adapter);
3456
06cf2666
AD		 3457 wr32(E1000_MRQC, mrqc);
3458}
3459
9d5c8243 3460/**
b980ac18
JK		 3461 * igb_setup_rctl - configure the receive control registers
3462 * @adapter: Board private structure
9d5c8243 3463 **/
d7ee5b3a 3464void igb_setup_rctl(struct igb_adapter *adapter)
9d5c8243
AK		 3465{
3466 struct e1000_hw *hw = &adapter->hw;
3467 u32 rctl;
9d5c8243
AK		 3468
3469 rctl = rd32(E1000_RCTL);
3470
3471 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
69d728ba 3472 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
9d5c8243 3473
69d728ba 3474 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
28b0759c 3475 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
9d5c8243 3476
b980ac18 3477 /* enable stripping of CRC. It's unlikely this will break BMC
87cb7e8c
AK		 3478 * redirection as it did with e1000. Newer features require
3479 * that the HW strips the CRC.
73cd78f1 3480 */
87cb7e8c 3481 rctl |= E1000_RCTL_SECRC;
9d5c8243 3482
559e9c49 3483 /* disable store bad packets and clear size bits. */
ec54d7d6 3484 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
9d5c8243 3485
6ec43fe6
AD		 3486 /* enable LPE to prevent packets larger than max_frame_size */
3487 rctl |= E1000_RCTL_LPE;
9d5c8243 3488
952f72a8
AD		 3489 /* disable queue 0 to prevent tail write w/o re-config */
3490 wr32(E1000_RXDCTL(0), 0);
9d5c8243 3491
e1739522
AD		 3492 /* Attention!!! For SR-IOV PF driver operations you must enable
3493 * queue drop for all VF and PF queues to prevent head of line blocking
3494 * if an un-trusted VF does not provide descriptors to hardware.
3495 */
3496 if (adapter->vfs_allocated_count) {
e1739522
AD		 3497 /* set all queue drop enable bits */
3498 wr32(E1000_QDE, ALL_QUEUES);
e1739522
AD		 3499 }
3500
89eaefb6
BG		 3501 /* This is useful for sniffing bad packets. */
3502 if (adapter->netdev->features & NETIF_F_RXALL) {
3503 /* UPE and MPE will be handled by normal PROMISC logic
b980ac18
JK		 3504 * in e1000e_set_rx_mode
3505 */
89eaefb6
BG		 3506 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3507 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3508 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3509
3510 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3511 E1000_RCTL_DPF | /* Allow filtered pause */
3512 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3513 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3514 * and that breaks VLANs.
3515 */
3516 }
3517
9d5c8243
AK		 3518 wr32(E1000_RCTL, rctl);
3519}
3520
7d5753f0 3521static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
9005df38 3522 int vfn)
7d5753f0
AD		 3523{
3524 struct e1000_hw *hw = &adapter->hw;
3525 u32 vmolr;
3526
3527 /* if it isn't the PF check to see if VFs are enabled and
b980ac18
JK		 3528 * increase the size to support vlan tags
3529 */
7d5753f0
AD		 3530 if (vfn < adapter->vfs_allocated_count &&
3531 adapter->vf_data[vfn].vlans_enabled)
3532 size += VLAN_TAG_SIZE;
3533
3534 vmolr = rd32(E1000_VMOLR(vfn));
3535 vmolr &= ~E1000_VMOLR_RLPML_MASK;
3536 vmolr |= size | E1000_VMOLR_LPE;
3537 wr32(E1000_VMOLR(vfn), vmolr);
3538
3539 return 0;
3540}
3541
e1739522 3542/**
b980ac18
JK		 3543 * igb_rlpml_set - set maximum receive packet size
3544 * @adapter: board private structure
e1739522 3545 *
b980ac18 3546 * Configure maximum receivable packet size.
e1739522
AD		 3547 **/
3548static void igb_rlpml_set(struct igb_adapter *adapter)
3549{
153285f9 3550 u32 max_frame_size = adapter->max_frame_size;
e1739522
AD		 3551 struct e1000_hw *hw = &adapter->hw;
3552 u16 pf_id = adapter->vfs_allocated_count;
3553
e1739522
AD		 3554 if (pf_id) {
3555 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
b980ac18 3556 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
153285f9
AD		 3557 * to our max jumbo frame size, in case we need to enable
3558 * jumbo frames on one of the rings later.
3559 * This will not pass over-length frames into the default
3560 * queue because it's gated by the VMOLR.RLPML.
3561 */
7d5753f0 3562 max_frame_size = MAX_JUMBO_FRAME_SIZE;
e1739522
AD		 3563 }
3564
3565 wr32(E1000_RLPML, max_frame_size);
3566}
3567
8151d294
WM		 3568static inline void igb_set_vmolr(struct igb_adapter *adapter,
3569 int vfn, bool aupe)
7d5753f0
AD		 3570{
3571 struct e1000_hw *hw = &adapter->hw;
3572 u32 vmolr;
3573
b980ac18 3574 /* This register exists only on 82576 and newer so if we are older then
7d5753f0
AD		 3575 * we should exit and do nothing
3576 */
3577 if (hw->mac.type < e1000_82576)
3578 return;
3579
3580 vmolr = rd32(E1000_VMOLR(vfn));
b980ac18 3581 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */
dc1edc67
SA		 3582 if (hw->mac.type == e1000_i350) {
3583 u32 dvmolr;
3584
3585 dvmolr = rd32(E1000_DVMOLR(vfn));
3586 dvmolr |= E1000_DVMOLR_STRVLAN;
3587 wr32(E1000_DVMOLR(vfn), dvmolr);
3588 }
8151d294 3589 if (aupe)
b980ac18 3590 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
8151d294
WM		 3591 else
3592 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
7d5753f0
AD		 3593
3594 /* clear all bits that might not be set */
3595 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3596
a99955fc 3597 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
7d5753f0 3598 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
b980ac18 3599 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
7d5753f0
AD		 3600 * multicast packets
3601 */
3602 if (vfn <= adapter->vfs_allocated_count)
b980ac18 3603 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
7d5753f0
AD		 3604
3605 wr32(E1000_VMOLR(vfn), vmolr);
3606}
3607
85b430b4 3608/**
b980ac18
JK		 3609 * igb_configure_rx_ring - Configure a receive ring after Reset
3610 * @adapter: board private structure
3611 * @ring: receive ring to be configured
85b430b4 3612 *
b980ac18 3613 * Configure the Rx unit of the MAC after a reset.
85b430b4 3614 **/
d7ee5b3a 3615void igb_configure_rx_ring(struct igb_adapter *adapter,
b980ac18 3616 struct igb_ring *ring)
85b430b4
AD		 3617{
3618 struct e1000_hw *hw = &adapter->hw;
3619 u64 rdba = ring->dma;
3620 int reg_idx = ring->reg_idx;
a74420e0 3621 u32 srrctl = 0, rxdctl = 0;
85b430b4
AD		 3622
3623 /* disable the queue */
a74420e0 3624 wr32(E1000_RXDCTL(reg_idx), 0);
85b430b4
AD		 3625
3626 /* Set DMA base address registers */
3627 wr32(E1000_RDBAL(reg_idx),
3628 rdba & 0x00000000ffffffffULL);
3629 wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3630 wr32(E1000_RDLEN(reg_idx),
b980ac18 3631 ring->count * sizeof(union e1000_adv_rx_desc));
85b430b4
AD		 3632
3633 /* initialize head and tail */
fce99e34 3634 ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
a74420e0 3635 wr32(E1000_RDH(reg_idx), 0);
fce99e34 3636 writel(0, ring->tail);
85b430b4 3637
952f72a8 3638 /* set descriptor configuration */
44390ca6 3639 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
de78d1f9 3640 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1a1c225b 3641 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
06218a8d 3642 if (hw->mac.type >= e1000_82580)
757b77e2 3643 srrctl |= E1000_SRRCTL_TIMESTAMP;
e6bdb6fe
NN		 3644 /* Only set Drop Enable if we are supporting multiple queues */
3645 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3646 srrctl |= E1000_SRRCTL_DROP_EN;
952f72a8
AD		 3647
3648 wr32(E1000_SRRCTL(reg_idx), srrctl);
3649
7d5753f0 3650 /* set filtering for VMDQ pools */
8151d294 3651 igb_set_vmolr(adapter, reg_idx & 0x7, true);
7d5753f0 3652
85b430b4
AD		 3653 rxdctl |= IGB_RX_PTHRESH;
3654 rxdctl |= IGB_RX_HTHRESH << 8;
3655 rxdctl |= IGB_RX_WTHRESH << 16;
a74420e0
AD		 3656
3657 /* enable receive descriptor fetching */
3658 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
85b430b4
AD		 3659 wr32(E1000_RXDCTL(reg_idx), rxdctl);
3660}
3661
9d5c8243 3662/**
b980ac18
JK		 3663 * igb_configure_rx - Configure receive Unit after Reset
3664 * @adapter: board private structure
9d5c8243 3665 *
b980ac18 3666 * Configure the Rx unit of the MAC after a reset.
9d5c8243
AK		 3667 **/
3668static void igb_configure_rx(struct igb_adapter *adapter)
3669{
9107584e 3670 int i;
9d5c8243 3671
68d480c4
AD		 3672 /* set UTA to appropriate mode */
3673 igb_set_uta(adapter);
3674
26ad9178
AD		 3675 /* set the correct pool for the PF default MAC address in entry 0 */
3676 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
b980ac18 3677 adapter->vfs_allocated_count);
26ad9178 3678
06cf2666 3679 /* Setup the HW Rx Head and Tail Descriptor Pointers and
b980ac18
JK		 3680 * the Base and Length of the Rx Descriptor Ring
3681 */
f9d40f6a
AD		 3682 for (i = 0; i < adapter->num_rx_queues; i++)
3683 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
9d5c8243
AK		 3684}
3685
3686/**
b980ac18
JK		 3687 * igb_free_tx_resources - Free Tx Resources per Queue
3688 * @tx_ring: Tx descriptor ring for a specific queue
9d5c8243 3689 *
b980ac18 3690 * Free all transmit software resources
9d5c8243 3691 **/
68fd9910 3692void igb_free_tx_resources(struct igb_ring *tx_ring)
9d5c8243 3693{
3b644cf6 3694 igb_clean_tx_ring(tx_ring);
9d5c8243 3695
06034649
AD		 3696 vfree(tx_ring->tx_buffer_info);
3697 tx_ring->tx_buffer_info = NULL;
9d5c8243 3698
439705e1
AD		 3699 /* if not set, then don't free */
3700 if (!tx_ring->desc)
3701 return;
3702
59d71989
AD		 3703 dma_free_coherent(tx_ring->dev, tx_ring->size,
3704 tx_ring->desc, tx_ring->dma);
9d5c8243
AK		 3705
3706 tx_ring->desc = NULL;
3707}
3708
3709/**
b980ac18
JK		 3710 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3711 * @adapter: board private structure
9d5c8243 3712 *
b980ac18 3713 * Free all transmit software resources
9d5c8243
AK		 3714 **/
3715static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3716{
3717 int i;
3718
3719 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3720 if (adapter->tx_ring[i])
3721 igb_free_tx_resources(adapter->tx_ring[i]);
9d5c8243
AK		 3722}
3723
ebe42d16
AD		 3724void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3725 struct igb_tx_buffer *tx_buffer)
3726{
3727 if (tx_buffer->skb) {
3728 dev_kfree_skb_any(tx_buffer->skb);
c9f14bf3 3729 if (dma_unmap_len(tx_buffer, len))
ebe42d16 3730 dma_unmap_single(ring->dev,
c9f14bf3
AD		 3731 dma_unmap_addr(tx_buffer, dma),
3732 dma_unmap_len(tx_buffer, len),
ebe42d16 3733 DMA_TO_DEVICE);
c9f14bf3 3734 } else if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 3735 dma_unmap_page(ring->dev,
c9f14bf3
AD		 3736 dma_unmap_addr(tx_buffer, dma),
3737 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 3738 DMA_TO_DEVICE);
3739 }
3740 tx_buffer->next_to_watch = NULL;
3741 tx_buffer->skb = NULL;
c9f14bf3 3742 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16 3743 /* buffer_info must be completely set up in the transmit path */
9d5c8243
AK		 3744}
3745
3746/**
b980ac18
JK		 3747 * igb_clean_tx_ring - Free Tx Buffers
3748 * @tx_ring: ring to be cleaned
9d5c8243 3749 **/
3b644cf6 3750static void igb_clean_tx_ring(struct igb_ring *tx_ring)
9d5c8243 3751{
06034649 3752 struct igb_tx_buffer *buffer_info;
9d5c8243 3753 unsigned long size;
6ad4edfc 3754 u16 i;
9d5c8243 3755
06034649 3756 if (!tx_ring->tx_buffer_info)
9d5c8243
AK		 3757 return;
3758 /* Free all the Tx ring sk_buffs */
3759
3760 for (i = 0; i < tx_ring->count; i++) {
06034649 3761 buffer_info = &tx_ring->tx_buffer_info[i];
80785298 3762 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
9d5c8243
AK		 3763 }
3764
dad8a3b3
JF		 3765 netdev_tx_reset_queue(txring_txq(tx_ring));
3766
06034649
AD		 3767 size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3768 memset(tx_ring->tx_buffer_info, 0, size);
9d5c8243
AK		 3769
3770 /* Zero out the descriptor ring */
9d5c8243
AK		 3771 memset(tx_ring->desc, 0, tx_ring->size);
3772
3773 tx_ring->next_to_use = 0;
3774 tx_ring->next_to_clean = 0;
9d5c8243
AK		 3775}
3776
3777/**
b980ac18
JK		 3778 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3779 * @adapter: board private structure
9d5c8243
AK		 3780 **/
3781static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3782{
3783 int i;
3784
3785 for (i = 0; i < adapter->num_tx_queues; i++)
17a402a0
CW		 3786 if (adapter->tx_ring[i])
3787 igb_clean_tx_ring(adapter->tx_ring[i]);
9d5c8243
AK		 3788}
3789
3790/**
b980ac18
JK		 3791 * igb_free_rx_resources - Free Rx Resources
3792 * @rx_ring: ring to clean the resources from
9d5c8243 3793 *
b980ac18 3794 * Free all receive software resources
9d5c8243 3795 **/
68fd9910 3796void igb_free_rx_resources(struct igb_ring *rx_ring)
9d5c8243 3797{
3b644cf6 3798 igb_clean_rx_ring(rx_ring);
9d5c8243 3799
06034649
AD		 3800 vfree(rx_ring->rx_buffer_info);
3801 rx_ring->rx_buffer_info = NULL;
9d5c8243 3802
439705e1
AD		 3803 /* if not set, then don't free */
3804 if (!rx_ring->desc)
3805 return;
3806
59d71989
AD		 3807 dma_free_coherent(rx_ring->dev, rx_ring->size,
3808 rx_ring->desc, rx_ring->dma);
9d5c8243
AK		 3809
3810 rx_ring->desc = NULL;
3811}
3812
3813/**
b980ac18
JK		 3814 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3815 * @adapter: board private structure
9d5c8243 3816 *
b980ac18 3817 * Free all receive software resources
9d5c8243
AK		 3818 **/
3819static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3820{
3821 int i;
3822
3823 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3824 if (adapter->rx_ring[i])
3825 igb_free_rx_resources(adapter->rx_ring[i]);
9d5c8243
AK		 3826}
3827
3828/**
b980ac18
JK		 3829 * igb_clean_rx_ring - Free Rx Buffers per Queue
3830 * @rx_ring: ring to free buffers from
9d5c8243 3831 **/
3b644cf6 3832static void igb_clean_rx_ring(struct igb_ring *rx_ring)
9d5c8243 3833{
9d5c8243 3834 unsigned long size;
c023cd88 3835 u16 i;
9d5c8243 3836
1a1c225b
AD		 3837 if (rx_ring->skb)
3838 dev_kfree_skb(rx_ring->skb);
3839 rx_ring->skb = NULL;
3840
06034649 3841 if (!rx_ring->rx_buffer_info)
9d5c8243 3842 return;
439705e1 3843
9d5c8243
AK		 3844 /* Free all the Rx ring sk_buffs */
3845 for (i = 0; i < rx_ring->count; i++) {
06034649 3846 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
9d5c8243 3847
cbc8e55f
AD		 3848 if (!buffer_info->page)
3849 continue;
3850
3851 dma_unmap_page(rx_ring->dev,
3852 buffer_info->dma,
3853 PAGE_SIZE,
3854 DMA_FROM_DEVICE);
3855 __free_page(buffer_info->page);
3856
1a1c225b 3857 buffer_info->page = NULL;
9d5c8243
AK		 3858 }
3859
06034649
AD		 3860 size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3861 memset(rx_ring->rx_buffer_info, 0, size);
9d5c8243
AK		 3862
3863 /* Zero out the descriptor ring */
3864 memset(rx_ring->desc, 0, rx_ring->size);
3865
cbc8e55f 3866 rx_ring->next_to_alloc = 0;
9d5c8243
AK		 3867 rx_ring->next_to_clean = 0;
3868 rx_ring->next_to_use = 0;
9d5c8243
AK		 3869}
3870
3871/**
b980ac18
JK		 3872 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3873 * @adapter: board private structure
9d5c8243
AK		 3874 **/
3875static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3876{
3877 int i;
3878
3879 for (i = 0; i < adapter->num_rx_queues; i++)
17a402a0
CW		 3880 if (adapter->rx_ring[i])
3881 igb_clean_rx_ring(adapter->rx_ring[i]);
9d5c8243
AK		 3882}
3883
3884/**
b980ac18
JK		 3885 * igb_set_mac - Change the Ethernet Address of the NIC
3886 * @netdev: network interface device structure
3887 * @p: pointer to an address structure
9d5c8243 3888 *
b980ac18 3889 * Returns 0 on success, negative on failure
9d5c8243
AK		 3890 **/
3891static int igb_set_mac(struct net_device *netdev, void *p)
3892{
3893 struct igb_adapter *adapter = netdev_priv(netdev);
28b0759c 3894 struct e1000_hw *hw = &adapter->hw;
9d5c8243
AK		 3895 struct sockaddr *addr = p;
3896
3897 if (!is_valid_ether_addr(addr->sa_data))
3898 return -EADDRNOTAVAIL;
3899
3900 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
28b0759c 3901 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9d5c8243 3902
26ad9178
AD		 3903 /* set the correct pool for the new PF MAC address in entry 0 */
3904 igb_rar_set_qsel(adapter, hw->mac.addr, 0,
b980ac18 3905 adapter->vfs_allocated_count);
e1739522 3906
9d5c8243
AK		 3907 return 0;
3908}
3909
3910/**
b980ac18
JK		 3911 * igb_write_mc_addr_list - write multicast addresses to MTA
3912 * @netdev: network interface device structure
9d5c8243 3913 *
b980ac18
JK		 3914 * Writes multicast address list to the MTA hash table.
3915 * Returns: -ENOMEM on failure
3916 * 0 on no addresses written
3917 * X on writing X addresses to MTA
9d5c8243 3918 **/
68d480c4 3919static int igb_write_mc_addr_list(struct net_device *netdev)
9d5c8243
AK		 3920{
3921 struct igb_adapter *adapter = netdev_priv(netdev);
3922 struct e1000_hw *hw = &adapter->hw;
22bedad3 3923 struct netdev_hw_addr *ha;
68d480c4 3924 u8 *mta_list;
9d5c8243
AK		 3925 int i;
3926
4cd24eaf 3927 if (netdev_mc_empty(netdev)) {
68d480c4
AD		 3928 /* nothing to program, so clear mc list */
3929 igb_update_mc_addr_list(hw, NULL, 0);
3930 igb_restore_vf_multicasts(adapter);
3931 return 0;
3932 }
9d5c8243 3933
4cd24eaf 3934 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
68d480c4
AD		 3935 if (!mta_list)
3936 return -ENOMEM;
ff41f8dc 3937
68d480c4 3938 /* The shared function expects a packed array of only addresses. */
48e2f183 3939 i = 0;
22bedad3
JP		 3940 netdev_for_each_mc_addr(ha, netdev)
3941 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
68d480c4 3942
68d480c4
AD		 3943 igb_update_mc_addr_list(hw, mta_list, i);
3944 kfree(mta_list);
3945
4cd24eaf 3946 return netdev_mc_count(netdev);
68d480c4
AD		 3947}
3948
3949/**
b980ac18
JK		 3950 * igb_write_uc_addr_list - write unicast addresses to RAR table
3951 * @netdev: network interface device structure
68d480c4 3952 *
b980ac18
JK		 3953 * Writes unicast address list to the RAR table.
3954 * Returns: -ENOMEM on failure/insufficient address space
3955 * 0 on no addresses written
3956 * X on writing X addresses to the RAR table
68d480c4
AD		 3957 **/
3958static int igb_write_uc_addr_list(struct net_device *netdev)
3959{
3960 struct igb_adapter *adapter = netdev_priv(netdev);
3961 struct e1000_hw *hw = &adapter->hw;
3962 unsigned int vfn = adapter->vfs_allocated_count;
3963 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3964 int count = 0;
3965
3966 /* return ENOMEM indicating insufficient memory for addresses */
32e7bfc4 3967 if (netdev_uc_count(netdev) > rar_entries)
68d480c4 3968 return -ENOMEM;
9d5c8243 3969
32e7bfc4 3970 if (!netdev_uc_empty(netdev) && rar_entries) {
ff41f8dc 3971 struct netdev_hw_addr *ha;
32e7bfc4
JP		 3972
3973 netdev_for_each_uc_addr(ha, netdev) {
ff41f8dc
AD		 3974 if (!rar_entries)
3975 break;
26ad9178 3976 igb_rar_set_qsel(adapter, ha->addr,
b980ac18
JK		 3977 rar_entries--,
3978 vfn);
68d480c4 3979 count++;
ff41f8dc
AD		 3980 }
3981 }
3982 /* write the addresses in reverse order to avoid write combining */
3983 for (; rar_entries > 0 ; rar_entries--) {
3984 wr32(E1000_RAH(rar_entries), 0);
3985 wr32(E1000_RAL(rar_entries), 0);
3986 }
3987 wrfl();
3988
68d480c4
AD		 3989 return count;
3990}
3991
3992/**
b980ac18
JK		 3993 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3994 * @netdev: network interface device structure
68d480c4 3995 *
b980ac18
JK		 3996 * The set_rx_mode entry point is called whenever the unicast or multicast
3997 * address lists or the network interface flags are updated. This routine is
3998 * responsible for configuring the hardware for proper unicast, multicast,
3999 * promiscuous mode, and all-multi behavior.
68d480c4
AD		 4000 **/
4001static void igb_set_rx_mode(struct net_device *netdev)
4002{
4003 struct igb_adapter *adapter = netdev_priv(netdev);
4004 struct e1000_hw *hw = &adapter->hw;
4005 unsigned int vfn = adapter->vfs_allocated_count;
4006 u32 rctl, vmolr = 0;
4007 int count;
4008
4009 /* Check for Promiscuous and All Multicast modes */
4010 rctl = rd32(E1000_RCTL);
4011
4012 /* clear the effected bits */
4013 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
4014
4015 if (netdev->flags & IFF_PROMISC) {
6f3dc319 4016 /* retain VLAN HW filtering if in VT mode */
7e44892c 4017 if (adapter->vfs_allocated_count)
6f3dc319 4018 rctl |= E1000_RCTL_VFE;
68d480c4
AD		 4019 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
4020 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
4021 } else {
4022 if (netdev->flags & IFF_ALLMULTI) {
4023 rctl |= E1000_RCTL_MPE;
4024 vmolr |= E1000_VMOLR_MPME;
4025 } else {
b980ac18 4026 /* Write addresses to the MTA, if the attempt fails
25985edc 4027 * then we should just turn on promiscuous mode so
68d480c4
AD		 4028 * that we can at least receive multicast traffic
4029 */
4030 count = igb_write_mc_addr_list(netdev);
4031 if (count < 0) {
4032 rctl |= E1000_RCTL_MPE;
4033 vmolr |= E1000_VMOLR_MPME;
4034 } else if (count) {
4035 vmolr |= E1000_VMOLR_ROMPE;
4036 }
4037 }
b980ac18 4038 /* Write addresses to available RAR registers, if there is not
68d480c4 4039 * sufficient space to store all the addresses then enable
25985edc 4040 * unicast promiscuous mode
68d480c4
AD		 4041 */
4042 count = igb_write_uc_addr_list(netdev);
4043 if (count < 0) {
4044 rctl |= E1000_RCTL_UPE;
4045 vmolr |= E1000_VMOLR_ROPE;
4046 }
4047 rctl |= E1000_RCTL_VFE;
28fc06f5 4048 }
68d480c4 4049 wr32(E1000_RCTL, rctl);
28fc06f5 4050
b980ac18 4051 /* In order to support SR-IOV and eventually VMDq it is necessary to set
68d480c4
AD		 4052 * the VMOLR to enable the appropriate modes. Without this workaround
4053 * we will have issues with VLAN tag stripping not being done for frames
4054 * that are only arriving because we are the default pool
4055 */
f96a8a0b 4056 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
28fc06f5 4057 return;
9d5c8243 4058
68d480c4 4059 vmolr |= rd32(E1000_VMOLR(vfn)) &
b980ac18 4060 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
68d480c4 4061 wr32(E1000_VMOLR(vfn), vmolr);
28fc06f5 4062 igb_restore_vf_multicasts(adapter);
9d5c8243
AK		 4063}
4064
13800469
GR		 4065static void igb_check_wvbr(struct igb_adapter *adapter)
4066{
4067 struct e1000_hw *hw = &adapter->hw;
4068 u32 wvbr = 0;
4069
4070 switch (hw->mac.type) {
4071 case e1000_82576:
4072 case e1000_i350:
81ad807b
CW		 4073 wvbr = rd32(E1000_WVBR);
4074 if (!wvbr)
13800469
GR		 4075 return;
4076 break;
4077 default:
4078 break;
4079 }
4080
4081 adapter->wvbr |= wvbr;
4082}
4083
4084#define IGB_STAGGERED_QUEUE_OFFSET 8
4085
4086static void igb_spoof_check(struct igb_adapter *adapter)
4087{
4088 int j;
4089
4090 if (!adapter->wvbr)
4091 return;
4092
9005df38 4093 for (j = 0; j < adapter->vfs_allocated_count; j++) {
13800469
GR		 4094 if (adapter->wvbr & (1 << j) ||
4095 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
4096 dev_warn(&adapter->pdev->dev,
4097 "Spoof event(s) detected on VF %d\n", j);
4098 adapter->wvbr &=
4099 ~((1 << j) |
4100 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
4101 }
4102 }
4103}
4104
9d5c8243 4105/* Need to wait a few seconds after link up to get diagnostic information from
b980ac18
JK		 4106 * the phy
4107 */
9d5c8243
AK		 4108static void igb_update_phy_info(unsigned long data)
4109{
4110 struct igb_adapter *adapter = (struct igb_adapter *) data;
f5f4cf08 4111 igb_get_phy_info(&adapter->hw);
9d5c8243
AK		 4112}
4113
4d6b725e 4114/**
b980ac18
JK		 4115 * igb_has_link - check shared code for link and determine up/down
4116 * @adapter: pointer to driver private info
4d6b725e 4117 **/
3145535a 4118bool igb_has_link(struct igb_adapter *adapter)
4d6b725e
AD		 4119{
4120 struct e1000_hw *hw = &adapter->hw;
4121 bool link_active = false;
4d6b725e
AD		 4122
4123 /* get_link_status is set on LSC (link status) interrupt or
4124 * rx sequence error interrupt. get_link_status will stay
4125 * false until the e1000_check_for_link establishes link
4126 * for copper adapters ONLY
4127 */
4128 switch (hw->phy.media_type) {
4129 case e1000_media_type_copper:
e5c3370f
AA		 4130 if (!hw->mac.get_link_status)
4131 return true;
4d6b725e 4132 case e1000_media_type_internal_serdes:
e5c3370f
AA		 4133 hw->mac.ops.check_for_link(hw);
4134 link_active = !hw->mac.get_link_status;
4d6b725e
AD		 4135 break;
4136 default:
4137 case e1000_media_type_unknown:
4138 break;
4139 }
4140
aa9b8cc4
AA		 4141 if (((hw->mac.type == e1000_i210) ||
4142 (hw->mac.type == e1000_i211)) &&
4143 (hw->phy.id == I210_I_PHY_ID)) {
4144 if (!netif_carrier_ok(adapter->netdev)) {
4145 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4146 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
4147 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
4148 adapter->link_check_timeout = jiffies;
4149 }
4150 }
4151
4d6b725e
AD		 4152 return link_active;
4153}
4154
563988dc
SA		 4155static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
4156{
4157 bool ret = false;
4158 u32 ctrl_ext, thstat;
4159
f96a8a0b 4160 /* check for thermal sensor event on i350 copper only */
563988dc
SA		 4161 if (hw->mac.type == e1000_i350) {
4162 thstat = rd32(E1000_THSTAT);
4163 ctrl_ext = rd32(E1000_CTRL_EXT);
4164
4165 if ((hw->phy.media_type == e1000_media_type_copper) &&
5c17a203 4166 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
563988dc 4167 ret = !!(thstat & event);
563988dc
SA		 4168 }
4169
4170 return ret;
4171}
4172
1516f0a6
CW		 4173/**
4174 * igb_check_lvmmc - check for malformed packets received
4175 * and indicated in LVMMC register
4176 * @adapter: pointer to adapter
4177 **/
4178static void igb_check_lvmmc(struct igb_adapter *adapter)
4179{
4180 struct e1000_hw *hw = &adapter->hw;
4181 u32 lvmmc;
4182
4183 lvmmc = rd32(E1000_LVMMC);
4184 if (lvmmc) {
4185 if (unlikely(net_ratelimit())) {
4186 netdev_warn(adapter->netdev,
4187 "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
4188 lvmmc);
4189 }
4190 }
4191}
4192
9d5c8243 4193/**
b980ac18
JK		 4194 * igb_watchdog - Timer Call-back
4195 * @data: pointer to adapter cast into an unsigned long
9d5c8243
AK		 4196 **/
4197static void igb_watchdog(unsigned long data)
4198{
4199 struct igb_adapter *adapter = (struct igb_adapter *)data;
4200 /* Do the rest outside of interrupt context */
4201 schedule_work(&adapter->watchdog_task);
4202}
4203
4204static void igb_watchdog_task(struct work_struct *work)
4205{
4206 struct igb_adapter *adapter = container_of(work,
b980ac18
JK		 4207 struct igb_adapter,
4208 watchdog_task);
9d5c8243 4209 struct e1000_hw *hw = &adapter->hw;
c0ba4778 4210 struct e1000_phy_info *phy = &hw->phy;
9d5c8243 4211 struct net_device *netdev = adapter->netdev;
563988dc 4212 u32 link;
7a6ea550 4213 int i;
56cec249 4214 u32 connsw;
9d5c8243 4215
4d6b725e 4216 link = igb_has_link(adapter);
aa9b8cc4
AA		 4217
4218 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
4219 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
4220 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
4221 else
4222 link = false;
4223 }
4224
56cec249
CW		 4225 /* Force link down if we have fiber to swap to */
4226 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4227 if (hw->phy.media_type == e1000_media_type_copper) {
4228 connsw = rd32(E1000_CONNSW);
4229 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
4230 link = 0;
4231 }
4232 }
9d5c8243 4233 if (link) {
2bdfc4e2
CW		 4234 /* Perform a reset if the media type changed. */
4235 if (hw->dev_spec._82575.media_changed) {
4236 hw->dev_spec._82575.media_changed = false;
4237 adapter->flags |= IGB_FLAG_MEDIA_RESET;
4238 igb_reset(adapter);
4239 }
749ab2cd
YZ		 4240 /* Cancel scheduled suspend requests. */
4241 pm_runtime_resume(netdev->dev.parent);
4242
9d5c8243
AK		 4243 if (!netif_carrier_ok(netdev)) {
4244 u32 ctrl;
9005df38 4245
330a6d6a 4246 hw->mac.ops.get_speed_and_duplex(hw,
b980ac18
JK		 4247 &adapter->link_speed,
4248 &adapter->link_duplex);
9d5c8243
AK		 4249
4250 ctrl = rd32(E1000_CTRL);
527d47c1 4251 /* Links status message must follow this format */
c75c4edf
CW		 4252 netdev_info(netdev,
4253 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
559e9c49
AD		 4254 netdev->name,
4255 adapter->link_speed,
4256 adapter->link_duplex == FULL_DUPLEX ?
876d2d6f
JK		 4257 "Full" : "Half",
4258 (ctrl & E1000_CTRL_TFCE) &&
4259 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
4260 (ctrl & E1000_CTRL_RFCE) ? "RX" :
4261 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None");
9d5c8243 4262
f4c01e96
CW		 4263 /* disable EEE if enabled */
4264 if ((adapter->flags & IGB_FLAG_EEE) &&
4265 (adapter->link_duplex == HALF_DUPLEX)) {
4266 dev_info(&adapter->pdev->dev,
4267 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
4268 adapter->hw.dev_spec._82575.eee_disable = true;
4269 adapter->flags &= ~IGB_FLAG_EEE;
4270 }
4271
c0ba4778
KS		 4272 /* check if SmartSpeed worked */
4273 igb_check_downshift(hw);
4274 if (phy->speed_downgraded)
4275 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
4276
563988dc 4277 /* check for thermal sensor event */
876d2d6f 4278 if (igb_thermal_sensor_event(hw,
d34a15ab 4279 E1000_THSTAT_LINK_THROTTLE))
c75c4edf 4280 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
563988dc 4281
d07f3e37 4282 /* adjust timeout factor according to speed/duplex */
9d5c8243
AK		 4283 adapter->tx_timeout_factor = 1;
4284 switch (adapter->link_speed) {
4285 case SPEED_10:
9d5c8243
AK		 4286 adapter->tx_timeout_factor = 14;
4287 break;
4288 case SPEED_100:
9d5c8243
AK		 4289 /* maybe add some timeout factor ? */
4290 break;
4291 }
4292
4293 netif_carrier_on(netdev);
9d5c8243 4294
4ae196df 4295 igb_ping_all_vfs(adapter);
17dc566c 4296 igb_check_vf_rate_limit(adapter);
4ae196df 4297
4b1a9877 4298 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4299 if (!test_bit(__IGB_DOWN, &adapter->state))
4300 mod_timer(&adapter->phy_info_timer,
4301 round_jiffies(jiffies + 2 * HZ));
4302 }
4303 } else {
4304 if (netif_carrier_ok(netdev)) {
4305 adapter->link_speed = 0;
4306 adapter->link_duplex = 0;
563988dc
SA		 4307
4308 /* check for thermal sensor event */
876d2d6f
JK		 4309 if (igb_thermal_sensor_event(hw,
4310 E1000_THSTAT_PWR_DOWN)) {
c75c4edf 4311 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
7ef5ed1c 4312 }
563988dc 4313
527d47c1 4314 /* Links status message must follow this format */
c75c4edf 4315 netdev_info(netdev, "igb: %s NIC Link is Down\n",
527d47c1 4316 netdev->name);
9d5c8243 4317 netif_carrier_off(netdev);
4b1a9877 4318
4ae196df
AD		 4319 igb_ping_all_vfs(adapter);
4320
4b1a9877 4321 /* link state has changed, schedule phy info update */
9d5c8243
AK		 4322 if (!test_bit(__IGB_DOWN, &adapter->state))
4323 mod_timer(&adapter->phy_info_timer,
4324 round_jiffies(jiffies + 2 * HZ));
749ab2cd 4325
56cec249
CW		 4326 /* link is down, time to check for alternate media */
4327 if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
4328 igb_check_swap_media(adapter);
4329 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4330 schedule_work(&adapter->reset_task);
4331 /* return immediately */
4332 return;
4333 }
4334 }
749ab2cd
YZ		 4335 pm_schedule_suspend(netdev->dev.parent,
4336 MSEC_PER_SEC * 5);
56cec249
CW		 4337
4338 /* also check for alternate media here */
4339 } else if (!netif_carrier_ok(netdev) &&
4340 (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
4341 igb_check_swap_media(adapter);
4342 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
4343 schedule_work(&adapter->reset_task);
4344 /* return immediately */
4345 return;
4346 }
9d5c8243
AK		 4347 }
4348 }
4349
12dcd86b
ED		 4350 spin_lock(&adapter->stats64_lock);
4351 igb_update_stats(adapter, &adapter->stats64);
4352 spin_unlock(&adapter->stats64_lock);
9d5c8243 4353
dbabb065 4354 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 4355 struct igb_ring *tx_ring = adapter->tx_ring[i];
dbabb065 4356 if (!netif_carrier_ok(netdev)) {
9d5c8243
AK		 4357 /* We've lost link, so the controller stops DMA,
4358 * but we've got queued Tx work that's never going
4359 * to get done, so reset controller to flush Tx.
b980ac18
JK		 4360 * (Do the reset outside of interrupt context).
4361 */
dbabb065
AD		 4362 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
4363 adapter->tx_timeout_count++;
4364 schedule_work(&adapter->reset_task);
4365 /* return immediately since reset is imminent */
4366 return;
4367 }
9d5c8243 4368 }
9d5c8243 4369
dbabb065 4370 /* Force detection of hung controller every watchdog period */
6d095fa8 4371 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
dbabb065 4372 }
f7ba205e 4373
b980ac18 4374 /* Cause software interrupt to ensure Rx ring is cleaned */
cd14ef54 4375 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
047e0030 4376 u32 eics = 0;
9005df38 4377
0d1ae7f4
AD		 4378 for (i = 0; i < adapter->num_q_vectors; i++)
4379 eics |= adapter->q_vector[i]->eims_value;
7a6ea550
AD		 4380 wr32(E1000_EICS, eics);
4381 } else {
4382 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4383 }
9d5c8243 4384
13800469 4385 igb_spoof_check(adapter);
fc580751 4386 igb_ptp_rx_hang(adapter);
13800469 4387
1516f0a6
CW		 4388 /* Check LVMMC register on i350/i354 only */
4389 if ((adapter->hw.mac.type == e1000_i350) ||
4390 (adapter->hw.mac.type == e1000_i354))
4391 igb_check_lvmmc(adapter);
4392
9d5c8243 4393 /* Reset the timer */
aa9b8cc4
AA		 4394 if (!test_bit(__IGB_DOWN, &adapter->state)) {
4395 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
4396 mod_timer(&adapter->watchdog_timer,
4397 round_jiffies(jiffies + HZ));
4398 else
4399 mod_timer(&adapter->watchdog_timer,
4400 round_jiffies(jiffies + 2 * HZ));
4401 }
9d5c8243
AK		 4402}
4403
4404enum latency_range {
4405 lowest_latency = 0,
4406 low_latency = 1,
4407 bulk_latency = 2,
4408 latency_invalid = 255
4409};
4410
6eb5a7f1 4411/**
b980ac18
JK		 4412 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4413 * @q_vector: pointer to q_vector
6eb5a7f1 4414 *
b980ac18
JK		 4415 * Stores a new ITR value based on strictly on packet size. This
4416 * algorithm is less sophisticated than that used in igb_update_itr,
4417 * due to the difficulty of synchronizing statistics across multiple
4418 * receive rings. The divisors and thresholds used by this function
4419 * were determined based on theoretical maximum wire speed and testing
4420 * data, in order to minimize response time while increasing bulk
4421 * throughput.
406d4965 4422 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4423 * NOTE: This function is called only when operating in a multiqueue
4424 * receive environment.
6eb5a7f1 4425 **/
047e0030 4426static void igb_update_ring_itr(struct igb_q_vector *q_vector)
9d5c8243 4427{
047e0030 4428 int new_val = q_vector->itr_val;
6eb5a7f1 4429 int avg_wire_size = 0;
047e0030 4430 struct igb_adapter *adapter = q_vector->adapter;
12dcd86b 4431 unsigned int packets;
9d5c8243 4432
6eb5a7f1
AD		 4433 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4434 * ints/sec - ITR timer value of 120 ticks.
4435 */
4436 if (adapter->link_speed != SPEED_1000) {
0ba82994 4437 new_val = IGB_4K_ITR;
6eb5a7f1 4438 goto set_itr_val;
9d5c8243 4439 }
047e0030 4440
0ba82994
AD		 4441 packets = q_vector->rx.total_packets;
4442 if (packets)
4443 avg_wire_size = q_vector->rx.total_bytes / packets;
047e0030 4444
0ba82994
AD		 4445 packets = q_vector->tx.total_packets;
4446 if (packets)
4447 avg_wire_size = max_t(u32, avg_wire_size,
4448 q_vector->tx.total_bytes / packets);
047e0030
AD		 4449
4450 /* if avg_wire_size isn't set no work was done */
4451 if (!avg_wire_size)
4452 goto clear_counts;
9d5c8243 4453
6eb5a7f1
AD		 4454 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4455 avg_wire_size += 24;
4456
4457 /* Don't starve jumbo frames */
4458 avg_wire_size = min(avg_wire_size, 3000);
9d5c8243 4459
6eb5a7f1
AD		 4460 /* Give a little boost to mid-size frames */
4461 if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4462 new_val = avg_wire_size / 3;
4463 else
4464 new_val = avg_wire_size / 2;
9d5c8243 4465
0ba82994
AD		 4466 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4467 if (new_val < IGB_20K_ITR &&
4468 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4469 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4470 new_val = IGB_20K_ITR;
abe1c363 4471
6eb5a7f1 4472set_itr_val:
047e0030
AD		 4473 if (new_val != q_vector->itr_val) {
4474 q_vector->itr_val = new_val;
4475 q_vector->set_itr = 1;
9d5c8243 4476 }
6eb5a7f1 4477clear_counts:
0ba82994
AD		 4478 q_vector->rx.total_bytes = 0;
4479 q_vector->rx.total_packets = 0;
4480 q_vector->tx.total_bytes = 0;
4481 q_vector->tx.total_packets = 0;
9d5c8243
AK		 4482}
4483
4484/**
b980ac18
JK		 4485 * igb_update_itr - update the dynamic ITR value based on statistics
4486 * @q_vector: pointer to q_vector
4487 * @ring_container: ring info to update the itr for
4488 *
4489 * Stores a new ITR value based on packets and byte
4490 * counts during the last interrupt. The advantage of per interrupt
4491 * computation is faster updates and more accurate ITR for the current
4492 * traffic pattern. Constants in this function were computed
4493 * based on theoretical maximum wire speed and thresholds were set based
4494 * on testing data as well as attempting to minimize response time
4495 * while increasing bulk throughput.
406d4965 4496 * This functionality is controlled by ethtool's coalescing settings.
b980ac18
JK		 4497 * NOTE: These calculations are only valid when operating in a single-
4498 * queue environment.
9d5c8243 4499 **/
0ba82994
AD		 4500static void igb_update_itr(struct igb_q_vector *q_vector,
4501 struct igb_ring_container *ring_container)
9d5c8243 4502{
0ba82994
AD		 4503 unsigned int packets = ring_container->total_packets;
4504 unsigned int bytes = ring_container->total_bytes;
4505 u8 itrval = ring_container->itr;
9d5c8243 4506
0ba82994 4507 /* no packets, exit with status unchanged */
9d5c8243 4508 if (packets == 0)
0ba82994 4509 return;
9d5c8243 4510
0ba82994 4511 switch (itrval) {
9d5c8243
AK		 4512 case lowest_latency:
4513 /* handle TSO and jumbo frames */
4514 if (bytes/packets > 8000)
0ba82994 4515 itrval = bulk_latency;
9d5c8243 4516 else if ((packets < 5) && (bytes > 512))
0ba82994 4517 itrval = low_latency;
9d5c8243
AK		 4518 break;
4519 case low_latency: /* 50 usec aka 20000 ints/s */
4520 if (bytes > 10000) {
4521 /* this if handles the TSO accounting */
d34a15ab 4522 if (bytes/packets > 8000)
0ba82994 4523 itrval = bulk_latency;
d34a15ab 4524 else if ((packets < 10) || ((bytes/packets) > 1200))
0ba82994 4525 itrval = bulk_latency;
d34a15ab 4526 else if ((packets > 35))
0ba82994 4527 itrval = lowest_latency;
9d5c8243 4528 } else if (bytes/packets > 2000) {
0ba82994 4529 itrval = bulk_latency;
9d5c8243 4530 } else if (packets <= 2 && bytes < 512) {
0ba82994 4531 itrval = lowest_latency;
9d5c8243
AK		 4532 }
4533 break;
4534 case bulk_latency: /* 250 usec aka 4000 ints/s */
4535 if (bytes > 25000) {
4536 if (packets > 35)
0ba82994 4537 itrval = low_latency;
1e5c3d21 4538 } else if (bytes < 1500) {
0ba82994 4539 itrval = low_latency;
9d5c8243
AK		 4540 }
4541 break;
4542 }
4543
0ba82994
AD		 4544 /* clear work counters since we have the values we need */
4545 ring_container->total_bytes = 0;
4546 ring_container->total_packets = 0;
4547
4548 /* write updated itr to ring container */
4549 ring_container->itr = itrval;
9d5c8243
AK		 4550}
4551
0ba82994 4552static void igb_set_itr(struct igb_q_vector *q_vector)
9d5c8243 4553{
0ba82994 4554 struct igb_adapter *adapter = q_vector->adapter;
047e0030 4555 u32 new_itr = q_vector->itr_val;
0ba82994 4556 u8 current_itr = 0;
9d5c8243
AK		 4557
4558 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4559 if (adapter->link_speed != SPEED_1000) {
4560 current_itr = 0;
0ba82994 4561 new_itr = IGB_4K_ITR;
9d5c8243
AK		 4562 goto set_itr_now;
4563 }
4564
0ba82994
AD		 4565 igb_update_itr(q_vector, &q_vector->tx);
4566 igb_update_itr(q_vector, &q_vector->rx);
9d5c8243 4567
0ba82994 4568 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
9d5c8243 4569
6eb5a7f1 4570 /* conservative mode (itr 3) eliminates the lowest_latency setting */
0ba82994
AD		 4571 if (current_itr == lowest_latency &&
4572 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4573 (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
6eb5a7f1
AD		 4574 current_itr = low_latency;
4575
9d5c8243
AK		 4576 switch (current_itr) {
4577 /* counts and packets in update_itr are dependent on these numbers */
4578 case lowest_latency:
0ba82994 4579 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
9d5c8243
AK		 4580 break;
4581 case low_latency:
0ba82994 4582 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
9d5c8243
AK		 4583 break;
4584 case bulk_latency:
0ba82994 4585 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */
9d5c8243
AK		 4586 break;
4587 default:
4588 break;
4589 }
4590
4591set_itr_now:
047e0030 4592 if (new_itr != q_vector->itr_val) {
9d5c8243
AK		 4593 /* this attempts to bias the interrupt rate towards Bulk
4594 * by adding intermediate steps when interrupt rate is
b980ac18
JK		 4595 * increasing
4596 */
047e0030 4597 new_itr = new_itr > q_vector->itr_val ?
b980ac18
JK		 4598 max((new_itr * q_vector->itr_val) /
4599 (new_itr + (q_vector->itr_val >> 2)),
4600 new_itr) : new_itr;
9d5c8243
AK		 4601 /* Don't write the value here; it resets the adapter's
4602 * internal timer, and causes us to delay far longer than
4603 * we should between interrupts. Instead, we write the ITR
4604 * value at the beginning of the next interrupt so the timing
4605 * ends up being correct.
4606 */
047e0030
AD		 4607 q_vector->itr_val = new_itr;
4608 q_vector->set_itr = 1;
9d5c8243 4609 }
9d5c8243
AK		 4610}
4611
c50b52a0
SH		 4612static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4613 u32 type_tucmd, u32 mss_l4len_idx)
7d13a7d0
AD		 4614{
4615 struct e1000_adv_tx_context_desc *context_desc;
4616 u16 i = tx_ring->next_to_use;
4617
4618 context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4619
4620 i++;
4621 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4622
4623 /* set bits to identify this as an advanced context descriptor */
4624 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4625
4626 /* For 82575, context index must be unique per ring. */
866cff06 4627 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
7d13a7d0
AD		 4628 mss_l4len_idx |= tx_ring->reg_idx << 4;
4629
4630 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4631 context_desc->seqnum_seed = 0;
4632 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
4633 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4634}
4635
7af40ad9
AD		 4636static int igb_tso(struct igb_ring *tx_ring,
4637 struct igb_tx_buffer *first,
4638 u8 *hdr_len)
9d5c8243 4639{
7af40ad9 4640 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4641 u32 vlan_macip_lens, type_tucmd;
4642 u32 mss_l4len_idx, l4len;
06c14e5a 4643 int err;
7d13a7d0 4644
ed6aa105
AD		 4645 if (skb->ip_summed != CHECKSUM_PARTIAL)
4646 return 0;
4647
7d13a7d0
AD		 4648 if (!skb_is_gso(skb))
4649 return 0;
9d5c8243 4650
06c14e5a
FR		 4651 err = skb_cow_head(skb, 0);
4652 if (err < 0)
4653 return err;
9d5c8243 4654
7d13a7d0
AD		 4655 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4656 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
9d5c8243 4657
7c4d16ff 4658 if (first->protocol == htons(ETH_P_IP)) {
9d5c8243
AK		 4659 struct iphdr *iph = ip_hdr(skb);
4660 iph->tot_len = 0;
4661 iph->check = 0;
4662 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4663 iph->daddr, 0,
4664 IPPROTO_TCP,
4665 0);
7d13a7d0 4666 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
7af40ad9
AD		 4667 first->tx_flags |= IGB_TX_FLAGS_TSO |
4668 IGB_TX_FLAGS_CSUM |
4669 IGB_TX_FLAGS_IPV4;
8e1e8a47 4670 } else if (skb_is_gso_v6(skb)) {
9d5c8243
AK		 4671 ipv6_hdr(skb)->payload_len = 0;
4672 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4673 &ipv6_hdr(skb)->daddr,
4674 0, IPPROTO_TCP, 0);
7af40ad9
AD		 4675 first->tx_flags |= IGB_TX_FLAGS_TSO |
4676 IGB_TX_FLAGS_CSUM;
9d5c8243
AK		 4677 }
4678
7af40ad9 4679 /* compute header lengths */
7d13a7d0
AD		 4680 l4len = tcp_hdrlen(skb);
4681 *hdr_len = skb_transport_offset(skb) + l4len;
9d5c8243 4682
7af40ad9
AD		 4683 /* update gso size and bytecount with header size */
4684 first->gso_segs = skb_shinfo(skb)->gso_segs;
4685 first->bytecount += (first->gso_segs - 1) * *hdr_len;
4686
9d5c8243 4687 /* MSS L4LEN IDX */
7d13a7d0
AD		 4688 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4689 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
9d5c8243 4690
7d13a7d0
AD		 4691 /* VLAN MACLEN IPLEN */
4692 vlan_macip_lens = skb_network_header_len(skb);
4693 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4694 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4695
7d13a7d0 4696 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243 4697
7d13a7d0 4698 return 1;
9d5c8243
AK		 4699}
4700
7af40ad9 4701static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
9d5c8243 4702{
7af40ad9 4703 struct sk_buff *skb = first->skb;
7d13a7d0
AD		 4704 u32 vlan_macip_lens = 0;
4705 u32 mss_l4len_idx = 0;
4706 u32 type_tucmd = 0;
9d5c8243 4707
7d13a7d0 4708 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7af40ad9
AD		 4709 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4710 return;
7d13a7d0
AD		 4711 } else {
4712 u8 l4_hdr = 0;
9005df38 4713
7af40ad9 4714 switch (first->protocol) {
7c4d16ff 4715 case htons(ETH_P_IP):
7d13a7d0
AD		 4716 vlan_macip_lens |= skb_network_header_len(skb);
4717 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4718 l4_hdr = ip_hdr(skb)->protocol;
4719 break;
7c4d16ff 4720 case htons(ETH_P_IPV6):
7d13a7d0
AD		 4721 vlan_macip_lens |= skb_network_header_len(skb);
4722 l4_hdr = ipv6_hdr(skb)->nexthdr;
4723 break;
4724 default:
4725 if (unlikely(net_ratelimit())) {
4726 dev_warn(tx_ring->dev,
b980ac18
JK		 4727 "partial checksum but proto=%x!\n",
4728 first->protocol);
fa4a7ef3 4729 }
7d13a7d0
AD		 4730 break;
4731 }
fa4a7ef3 4732
7d13a7d0
AD		 4733 switch (l4_hdr) {
4734 case IPPROTO_TCP:
4735 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4736 mss_l4len_idx = tcp_hdrlen(skb) <<
4737 E1000_ADVTXD_L4LEN_SHIFT;
4738 break;
4739 case IPPROTO_SCTP:
4740 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4741 mss_l4len_idx = sizeof(struct sctphdr) <<
4742 E1000_ADVTXD_L4LEN_SHIFT;
4743 break;
4744 case IPPROTO_UDP:
4745 mss_l4len_idx = sizeof(struct udphdr) <<
4746 E1000_ADVTXD_L4LEN_SHIFT;
4747 break;
4748 default:
4749 if (unlikely(net_ratelimit())) {
4750 dev_warn(tx_ring->dev,
b980ac18
JK		 4751 "partial checksum but l4 proto=%x!\n",
4752 l4_hdr);
44b0cda3 4753 }
7d13a7d0 4754 break;
9d5c8243 4755 }
7af40ad9
AD		 4756
4757 /* update TX checksum flag */
4758 first->tx_flags |= IGB_TX_FLAGS_CSUM;
7d13a7d0 4759 }
9d5c8243 4760
7d13a7d0 4761 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
7af40ad9 4762 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
9d5c8243 4763
7d13a7d0 4764 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
9d5c8243
AK		 4765}
4766
1d9daf45
AD		 4767#define IGB_SET_FLAG(_input, _flag, _result) \
4768 ((_flag <= _result) ? \
4769 ((u32)(_input & _flag) * (_result / _flag)) : \
4770 ((u32)(_input & _flag) / (_flag / _result)))
4771
4772static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
e032afc8
AD		 4773{
4774 /* set type for advanced descriptor with frame checksum insertion */
1d9daf45
AD		 4775 u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4776 E1000_ADVTXD_DCMD_DEXT |
4777 E1000_ADVTXD_DCMD_IFCS;
e032afc8
AD		 4778
4779 /* set HW vlan bit if vlan is present */
1d9daf45
AD		 4780 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4781 (E1000_ADVTXD_DCMD_VLE));
4782
4783 /* set segmentation bits for TSO */
4784 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4785 (E1000_ADVTXD_DCMD_TSE));
e032afc8
AD		 4786
4787 /* set timestamp bit if present */
1d9daf45
AD		 4788 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4789 (E1000_ADVTXD_MAC_TSTAMP));
e032afc8 4790
1d9daf45
AD		 4791 /* insert frame checksum */
4792 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
e032afc8
AD		 4793
4794 return cmd_type;
4795}
4796
7af40ad9
AD		 4797static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4798 union e1000_adv_tx_desc *tx_desc,
4799 u32 tx_flags, unsigned int paylen)
e032afc8
AD		 4800{
4801 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4802
1d9daf45
AD		 4803 /* 82575 requires a unique index per ring */
4804 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
e032afc8
AD		 4805 olinfo_status |= tx_ring->reg_idx << 4;
4806
4807 /* insert L4 checksum */
1d9daf45
AD		 4808 olinfo_status |= IGB_SET_FLAG(tx_flags,
4809 IGB_TX_FLAGS_CSUM,
4810 (E1000_TXD_POPTS_TXSM << 8));
e032afc8 4811
1d9daf45
AD		 4812 /* insert IPv4 checksum */
4813 olinfo_status |= IGB_SET_FLAG(tx_flags,
4814 IGB_TX_FLAGS_IPV4,
4815 (E1000_TXD_POPTS_IXSM << 8));
e032afc8 4816
7af40ad9 4817 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
e032afc8
AD		 4818}
4819
6f19e12f
DM		 4820static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4821{
4822 struct net_device *netdev = tx_ring->netdev;
4823
4824 netif_stop_subqueue(netdev, tx_ring->queue_index);
4825
4826 /* Herbert's original patch had:
4827 * smp_mb__after_netif_stop_queue();
4828 * but since that doesn't exist yet, just open code it.
4829 */
4830 smp_mb();
4831
4832 /* We need to check again in a case another CPU has just
4833 * made room available.
4834 */
4835 if (igb_desc_unused(tx_ring) < size)
4836 return -EBUSY;
4837
4838 /* A reprieve! */
4839 netif_wake_subqueue(netdev, tx_ring->queue_index);
4840
4841 u64_stats_update_begin(&tx_ring->tx_syncp2);
4842 tx_ring->tx_stats.restart_queue2++;
4843 u64_stats_update_end(&tx_ring->tx_syncp2);
4844
4845 return 0;
4846}
4847
4848static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4849{
4850 if (igb_desc_unused(tx_ring) >= size)
4851 return 0;
4852 return __igb_maybe_stop_tx(tx_ring, size);
4853}
4854
7af40ad9
AD		 4855static void igb_tx_map(struct igb_ring *tx_ring,
4856 struct igb_tx_buffer *first,
ebe42d16 4857 const u8 hdr_len)
9d5c8243 4858{
7af40ad9 4859 struct sk_buff *skb = first->skb;
c9f14bf3 4860 struct igb_tx_buffer *tx_buffer;
ebe42d16 4861 union e1000_adv_tx_desc *tx_desc;
80d0759e 4862 struct skb_frag_struct *frag;
ebe42d16 4863 dma_addr_t dma;
80d0759e 4864 unsigned int data_len, size;
7af40ad9 4865 u32 tx_flags = first->tx_flags;
1d9daf45 4866 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
ebe42d16 4867 u16 i = tx_ring->next_to_use;
ebe42d16
AD		 4868
4869 tx_desc = IGB_TX_DESC(tx_ring, i);
4870
80d0759e
AD		 4871 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4872
4873 size = skb_headlen(skb);
4874 data_len = skb->data_len;
ebe42d16
AD		 4875
4876 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
9d5c8243 4877
80d0759e
AD		 4878 tx_buffer = first;
4879
4880 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4881 if (dma_mapping_error(tx_ring->dev, dma))
4882 goto dma_error;
4883
4884 /* record length, and DMA address */
4885 dma_unmap_len_set(tx_buffer, len, size);
4886 dma_unmap_addr_set(tx_buffer, dma, dma);
4887
4888 tx_desc->read.buffer_addr = cpu_to_le64(dma);
ebe42d16 4889
ebe42d16
AD		 4890 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4891 tx_desc->read.cmd_type_len =
1d9daf45 4892 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
ebe42d16
AD		 4893
4894 i++;
4895 tx_desc++;
4896 if (i == tx_ring->count) {
4897 tx_desc = IGB_TX_DESC(tx_ring, 0);
4898 i = 0;
4899 }
80d0759e 4900 tx_desc->read.olinfo_status = 0;
ebe42d16
AD		 4901
4902 dma += IGB_MAX_DATA_PER_TXD;
4903 size -= IGB_MAX_DATA_PER_TXD;
4904
ebe42d16
AD		 4905 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4906 }
4907
4908 if (likely(!data_len))
4909 break;
2bbfebe2 4910
1d9daf45 4911 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9d5c8243 4912
65689fef 4913 i++;
ebe42d16
AD		 4914 tx_desc++;
4915 if (i == tx_ring->count) {
4916 tx_desc = IGB_TX_DESC(tx_ring, 0);
65689fef 4917 i = 0;
ebe42d16 4918 }
80d0759e 4919 tx_desc->read.olinfo_status = 0;
65689fef 4920
9e903e08 4921 size = skb_frag_size(frag);
ebe42d16
AD		 4922 data_len -= size;
4923
4924 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
80d0759e 4925 size, DMA_TO_DEVICE);
6366ad33 4926
c9f14bf3 4927 tx_buffer = &tx_ring->tx_buffer_info[i];
9d5c8243
AK		 4928 }
4929
ebe42d16 4930 /* write last descriptor with RS and EOP bits */
1d9daf45
AD		 4931 cmd_type |= size | IGB_TXD_DCMD;
4932 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8542db05 4933
80d0759e
AD		 4934 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4935
8542db05
AD		 4936 /* set the timestamp */
4937 first->time_stamp = jiffies;
4938
b980ac18 4939 /* Force memory writes to complete before letting h/w know there
ebe42d16
AD		 4940 * are new descriptors to fetch. (Only applicable for weak-ordered
4941 * memory model archs, such as IA-64).
4942 *
4943 * We also need this memory barrier to make certain all of the
4944 * status bits have been updated before next_to_watch is written.
4945 */
4946 wmb();
4947
8542db05 4948 /* set next_to_watch value indicating a packet is present */
ebe42d16 4949 first->next_to_watch = tx_desc;
9d5c8243 4950
ebe42d16
AD		 4951 i++;
4952 if (i == tx_ring->count)
4953 i = 0;
6366ad33 4954
ebe42d16 4955 tx_ring->next_to_use = i;
6366ad33 4956
6f19e12f
DM		 4957 /* Make sure there is space in the ring for the next send. */
4958 igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4959
4960 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
0b725a2c
DM		 4961 writel(i, tx_ring->tail);
4962
4963 /* we need this if more than one processor can write to our tail
4964 * at a time, it synchronizes IO on IA64/Altix systems
4965 */
4966 mmiowb();
4967 }
ebe42d16
AD		 4968 return;
4969
4970dma_error:
4971 dev_err(tx_ring->dev, "TX DMA map failed\n");
4972
4973 /* clear dma mappings for failed tx_buffer_info map */
4974 for (;;) {
c9f14bf3
AD		 4975 tx_buffer = &tx_ring->tx_buffer_info[i];
4976 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4977 if (tx_buffer == first)
ebe42d16 4978 break;
a77ff709
NN		 4979 if (i == 0)
4980 i = tx_ring->count;
6366ad33 4981 i--;
6366ad33
AD		 4982 }
4983
9d5c8243 4984 tx_ring->next_to_use = i;
9d5c8243
AK		 4985}
4986
cd392f5c
AD		 4987netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4988 struct igb_ring *tx_ring)
9d5c8243 4989{
8542db05 4990 struct igb_tx_buffer *first;
ebe42d16 4991 int tso;
91d4ee33 4992 u32 tx_flags = 0;
21ba6fe1 4993 u16 count = TXD_USE_COUNT(skb_headlen(skb));
31f6adbb 4994 __be16 protocol = vlan_get_protocol(skb);
91d4ee33 4995 u8 hdr_len = 0;
9d5c8243 4996
21ba6fe1
AD		 4997 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4998 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
9d5c8243 4999 * + 2 desc gap to keep tail from touching head,
9d5c8243 5000 * + 1 desc for context descriptor,
21ba6fe1
AD		 5001 * otherwise try next time
5002 */
5003 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
5004 unsigned short f;
9005df38 5005
21ba6fe1
AD		 5006 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5007 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5008 } else {
5009 count += skb_shinfo(skb)->nr_frags;
5010 }
5011
5012 if (igb_maybe_stop_tx(tx_ring, count + 3)) {
9d5c8243 5013 /* this is a hard error */
9d5c8243
AK		 5014 return NETDEV_TX_BUSY;
5015 }
33af6bcc 5016
7af40ad9
AD		 5017 /* record the location of the first descriptor for this packet */
5018 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
5019 first->skb = skb;
5020 first->bytecount = skb->len;
5021 first->gso_segs = 1;
5022
b646c22e
AD		 5023 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
5024 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
1f6e8178 5025
ed4420a3
JK		 5026 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
5027 &adapter->state)) {
b646c22e
AD		 5028 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5029 tx_flags |= IGB_TX_FLAGS_TSTAMP;
5030
5031 adapter->ptp_tx_skb = skb_get(skb);
5032 adapter->ptp_tx_start = jiffies;
5033 if (adapter->hw.mac.type == e1000_82576)
5034 schedule_work(&adapter->ptp_tx_work);
5035 }
33af6bcc 5036 }
9d5c8243 5037
afc835d1
JK		 5038 skb_tx_timestamp(skb);
5039
eab6d18d 5040 if (vlan_tx_tag_present(skb)) {
9d5c8243
AK		 5041 tx_flags |= IGB_TX_FLAGS_VLAN;
5042 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
5043 }
5044
7af40ad9
AD		 5045 /* record initial flags and protocol */
5046 first->tx_flags = tx_flags;
5047 first->protocol = protocol;
cdfd01fc 5048
7af40ad9
AD		 5049 tso = igb_tso(tx_ring, first, &hdr_len);
5050 if (tso < 0)
7d13a7d0 5051 goto out_drop;
7af40ad9
AD		 5052 else if (!tso)
5053 igb_tx_csum(tx_ring, first);
9d5c8243 5054
7af40ad9 5055 igb_tx_map(tx_ring, first, hdr_len);
85ad76b2 5056
9d5c8243 5057 return NETDEV_TX_OK;
7d13a7d0
AD		 5058
5059out_drop:
7af40ad9
AD		 5060 igb_unmap_and_free_tx_resource(tx_ring, first);
5061
7d13a7d0 5062 return NETDEV_TX_OK;
9d5c8243
AK		 5063}
5064
0b725a2c
DM		 5065static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
5066 struct sk_buff *skb)
1cc3bd87 5067{
0b725a2c
DM		 5068 unsigned int r_idx = skb->queue_mapping;
5069
1cc3bd87
AD		 5070 if (r_idx >= adapter->num_tx_queues)
5071 r_idx = r_idx % adapter->num_tx_queues;
5072
5073 return adapter->tx_ring[r_idx];
5074}
5075
cd392f5c
AD		 5076static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
5077 struct net_device *netdev)
9d5c8243
AK		 5078{
5079 struct igb_adapter *adapter = netdev_priv(netdev);
b1a436c3
AD		 5080
5081 if (test_bit(__IGB_DOWN, &adapter->state)) {
5082 dev_kfree_skb_any(skb);
5083 return NETDEV_TX_OK;
5084 }
5085
5086 if (skb->len <= 0) {
5087 dev_kfree_skb_any(skb);
5088 return NETDEV_TX_OK;
5089 }
5090
b980ac18 5091 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
1cc3bd87
AD		 5092 * in order to meet this minimum size requirement.
5093 */
a94d9e22
AD		 5094 if (skb_put_padto(skb, 17))
5095 return NETDEV_TX_OK;
9d5c8243 5096
1cc3bd87 5097 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
9d5c8243
AK		 5098}
5099
5100/**
b980ac18
JK		 5101 * igb_tx_timeout - Respond to a Tx Hang
5102 * @netdev: network interface device structure
9d5c8243
AK		 5103 **/
5104static void igb_tx_timeout(struct net_device *netdev)
5105{
5106 struct igb_adapter *adapter = netdev_priv(netdev);
5107 struct e1000_hw *hw = &adapter->hw;
5108
5109 /* Do the reset outside of interrupt context */
5110 adapter->tx_timeout_count++;
f7ba205e 5111
06218a8d 5112 if (hw->mac.type >= e1000_82580)
55cac248
AD		 5113 hw->dev_spec._82575.global_device_reset = true;
5114
9d5c8243 5115 schedule_work(&adapter->reset_task);
265de409
AD		 5116 wr32(E1000_EICS,
5117 (adapter->eims_enable_mask & ~adapter->eims_other));
9d5c8243
AK		 5118}
5119
5120static void igb_reset_task(struct work_struct *work)
5121{
5122 struct igb_adapter *adapter;
5123 adapter = container_of(work, struct igb_adapter, reset_task);
5124
c97ec42a
TI		 5125 igb_dump(adapter);
5126 netdev_err(adapter->netdev, "Reset adapter\n");
9d5c8243
AK		 5127 igb_reinit_locked(adapter);
5128}
5129
5130/**
b980ac18
JK		 5131 * igb_get_stats64 - Get System Network Statistics
5132 * @netdev: network interface device structure
5133 * @stats: rtnl_link_stats64 pointer
9d5c8243 5134 **/
12dcd86b 5135static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
b980ac18 5136 struct rtnl_link_stats64 *stats)
9d5c8243 5137{
12dcd86b
ED		 5138 struct igb_adapter *adapter = netdev_priv(netdev);
5139
5140 spin_lock(&adapter->stats64_lock);
5141 igb_update_stats(adapter, &adapter->stats64);
5142 memcpy(stats, &adapter->stats64, sizeof(*stats));
5143 spin_unlock(&adapter->stats64_lock);
5144
5145 return stats;
9d5c8243
AK		 5146}
5147
5148/**
b980ac18
JK		 5149 * igb_change_mtu - Change the Maximum Transfer Unit
5150 * @netdev: network interface device structure
5151 * @new_mtu: new value for maximum frame size
9d5c8243 5152 *
b980ac18 5153 * Returns 0 on success, negative on failure
9d5c8243
AK		 5154 **/
5155static int igb_change_mtu(struct net_device *netdev, int new_mtu)
5156{
5157 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5158 struct pci_dev *pdev = adapter->pdev;
153285f9 5159 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
9d5c8243 5160
c809d227 5161 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
090b1795 5162 dev_err(&pdev->dev, "Invalid MTU setting\n");
9d5c8243
AK		 5163 return -EINVAL;
5164 }
5165
153285f9 5166#define MAX_STD_JUMBO_FRAME_SIZE 9238
9d5c8243 5167 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
090b1795 5168 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
9d5c8243
AK		 5169 return -EINVAL;
5170 }
5171
2ccd994c
AD		 5172 /* adjust max frame to be at least the size of a standard frame */
5173 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
5174 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
5175
9d5c8243 5176 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
0d451e79 5177 usleep_range(1000, 2000);
73cd78f1 5178
9d5c8243
AK		 5179 /* igb_down has a dependency on max_frame_size */
5180 adapter->max_frame_size = max_frame;
559e9c49 5181
4c844851
AD		 5182 if (netif_running(netdev))
5183 igb_down(adapter);
9d5c8243 5184
090b1795 5185 dev_info(&pdev->dev, "changing MTU from %d to %d\n",
9d5c8243
AK		 5186 netdev->mtu, new_mtu);
5187 netdev->mtu = new_mtu;
5188
5189 if (netif_running(netdev))
5190 igb_up(adapter);
5191 else
5192 igb_reset(adapter);
5193
5194 clear_bit(__IGB_RESETTING, &adapter->state);
5195
5196 return 0;
5197}
5198
5199/**
b980ac18
JK		 5200 * igb_update_stats - Update the board statistics counters
5201 * @adapter: board private structure
9d5c8243 5202 **/
12dcd86b
ED		 5203void igb_update_stats(struct igb_adapter *adapter,
5204 struct rtnl_link_stats64 *net_stats)
9d5c8243
AK		 5205{
5206 struct e1000_hw *hw = &adapter->hw;
5207 struct pci_dev *pdev = adapter->pdev;
fa3d9a6d 5208 u32 reg, mpc;
3f9c0164
AD		 5209 int i;
5210 u64 bytes, packets;
12dcd86b
ED		 5211 unsigned int start;
5212 u64 _bytes, _packets;
9d5c8243 5213
b980ac18 5214 /* Prevent stats update while adapter is being reset, or if the pci
9d5c8243
AK		 5215 * connection is down.
5216 */
5217 if (adapter->link_speed == 0)
5218 return;
5219 if (pci_channel_offline(pdev))
5220 return;
5221
3f9c0164
AD		 5222 bytes = 0;
5223 packets = 0;
7f90128e
AA		 5224
5225 rcu_read_lock();
3f9c0164 5226 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446 5227 struct igb_ring *ring = adapter->rx_ring[i];
e66c083a
TF		 5228 u32 rqdpc = rd32(E1000_RQDPC(i));
5229 if (hw->mac.type >= e1000_i210)
5230 wr32(E1000_RQDPC(i), 0);
12dcd86b 5231
ae1c07a6
AD		 5232 if (rqdpc) {
5233 ring->rx_stats.drops += rqdpc;
5234 net_stats->rx_fifo_errors += rqdpc;
5235 }
12dcd86b
ED		 5236
5237 do {
57a7744e 5238 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
12dcd86b
ED		 5239 _bytes = ring->rx_stats.bytes;
5240 _packets = ring->rx_stats.packets;
57a7744e 5241 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
12dcd86b
ED		 5242 bytes += _bytes;
5243 packets += _packets;
3f9c0164
AD		 5244 }
5245
128e45eb
AD		 5246 net_stats->rx_bytes = bytes;
5247 net_stats->rx_packets = packets;
3f9c0164
AD		 5248
5249 bytes = 0;
5250 packets = 0;
5251 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446 5252 struct igb_ring *ring = adapter->tx_ring[i];
12dcd86b 5253 do {
57a7744e 5254 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
12dcd86b
ED		 5255 _bytes = ring->tx_stats.bytes;
5256 _packets = ring->tx_stats.packets;
57a7744e 5257 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
12dcd86b
ED		 5258 bytes += _bytes;
5259 packets += _packets;
3f9c0164 5260 }
128e45eb
AD		 5261 net_stats->tx_bytes = bytes;
5262 net_stats->tx_packets = packets;
7f90128e 5263 rcu_read_unlock();
3f9c0164
AD		 5264
5265 /* read stats registers */
9d5c8243
AK		 5266 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
5267 adapter->stats.gprc += rd32(E1000_GPRC);
5268 adapter->stats.gorc += rd32(E1000_GORCL);
5269 rd32(E1000_GORCH); /* clear GORCL */
5270 adapter->stats.bprc += rd32(E1000_BPRC);
5271 adapter->stats.mprc += rd32(E1000_MPRC);
5272 adapter->stats.roc += rd32(E1000_ROC);
5273
5274 adapter->stats.prc64 += rd32(E1000_PRC64);
5275 adapter->stats.prc127 += rd32(E1000_PRC127);
5276 adapter->stats.prc255 += rd32(E1000_PRC255);
5277 adapter->stats.prc511 += rd32(E1000_PRC511);
5278 adapter->stats.prc1023 += rd32(E1000_PRC1023);
5279 adapter->stats.prc1522 += rd32(E1000_PRC1522);
5280 adapter->stats.symerrs += rd32(E1000_SYMERRS);
5281 adapter->stats.sec += rd32(E1000_SEC);
5282
fa3d9a6d
MW		 5283 mpc = rd32(E1000_MPC);
5284 adapter->stats.mpc += mpc;
5285 net_stats->rx_fifo_errors += mpc;
9d5c8243
AK		 5286 adapter->stats.scc += rd32(E1000_SCC);
5287 adapter->stats.ecol += rd32(E1000_ECOL);
5288 adapter->stats.mcc += rd32(E1000_MCC);
5289 adapter->stats.latecol += rd32(E1000_LATECOL);
5290 adapter->stats.dc += rd32(E1000_DC);
5291 adapter->stats.rlec += rd32(E1000_RLEC);
5292 adapter->stats.xonrxc += rd32(E1000_XONRXC);
5293 adapter->stats.xontxc += rd32(E1000_XONTXC);
5294 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
5295 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
5296 adapter->stats.fcruc += rd32(E1000_FCRUC);
5297 adapter->stats.gptc += rd32(E1000_GPTC);
5298 adapter->stats.gotc += rd32(E1000_GOTCL);
5299 rd32(E1000_GOTCH); /* clear GOTCL */
fa3d9a6d 5300 adapter->stats.rnbc += rd32(E1000_RNBC);
9d5c8243
AK		 5301 adapter->stats.ruc += rd32(E1000_RUC);
5302 adapter->stats.rfc += rd32(E1000_RFC);
5303 adapter->stats.rjc += rd32(E1000_RJC);
5304 adapter->stats.tor += rd32(E1000_TORH);
5305 adapter->stats.tot += rd32(E1000_TOTH);
5306 adapter->stats.tpr += rd32(E1000_TPR);
5307
5308 adapter->stats.ptc64 += rd32(E1000_PTC64);
5309 adapter->stats.ptc127 += rd32(E1000_PTC127);
5310 adapter->stats.ptc255 += rd32(E1000_PTC255);
5311 adapter->stats.ptc511 += rd32(E1000_PTC511);
5312 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
5313 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
5314
5315 adapter->stats.mptc += rd32(E1000_MPTC);
5316 adapter->stats.bptc += rd32(E1000_BPTC);
5317
2d0b0f69
NN		 5318 adapter->stats.tpt += rd32(E1000_TPT);
5319 adapter->stats.colc += rd32(E1000_COLC);
9d5c8243
AK		 5320
5321 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
43915c7c
NN		 5322 /* read internal phy specific stats */
5323 reg = rd32(E1000_CTRL_EXT);
5324 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
5325 adapter->stats.rxerrc += rd32(E1000_RXERRC);
3dbdf969
CW		 5326
5327 /* this stat has invalid values on i210/i211 */
5328 if ((hw->mac.type != e1000_i210) &&
5329 (hw->mac.type != e1000_i211))
5330 adapter->stats.tncrs += rd32(E1000_TNCRS);
43915c7c
NN		 5331 }
5332
9d5c8243
AK		 5333 adapter->stats.tsctc += rd32(E1000_TSCTC);
5334 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
5335
5336 adapter->stats.iac += rd32(E1000_IAC);
5337 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
5338 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
5339 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
5340 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
5341 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
5342 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
5343 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
5344 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
5345
5346 /* Fill out the OS statistics structure */
128e45eb
AD		 5347 net_stats->multicast = adapter->stats.mprc;
5348 net_stats->collisions = adapter->stats.colc;
9d5c8243
AK		 5349
5350 /* Rx Errors */
5351
5352 /* RLEC on some newer hardware can be incorrect so build
b980ac18
JK		 5353 * our own version based on RUC and ROC
5354 */
128e45eb 5355 net_stats->rx_errors = adapter->stats.rxerrc +
9d5c8243
AK		 5356 adapter->stats.crcerrs + adapter->stats.algnerrc +
5357 adapter->stats.ruc + adapter->stats.roc +
5358 adapter->stats.cexterr;
128e45eb
AD		 5359 net_stats->rx_length_errors = adapter->stats.ruc +
5360 adapter->stats.roc;
5361 net_stats->rx_crc_errors = adapter->stats.crcerrs;
5362 net_stats->rx_frame_errors = adapter->stats.algnerrc;
5363 net_stats->rx_missed_errors = adapter->stats.mpc;
9d5c8243
AK		 5364
5365 /* Tx Errors */
128e45eb
AD		 5366 net_stats->tx_errors = adapter->stats.ecol +
5367 adapter->stats.latecol;
5368 net_stats->tx_aborted_errors = adapter->stats.ecol;
5369 net_stats->tx_window_errors = adapter->stats.latecol;
5370 net_stats->tx_carrier_errors = adapter->stats.tncrs;
9d5c8243
AK		 5371
5372 /* Tx Dropped needs to be maintained elsewhere */
5373
9d5c8243
AK		 5374 /* Management Stats */
5375 adapter->stats.mgptc += rd32(E1000_MGTPTC);
5376 adapter->stats.mgprc += rd32(E1000_MGTPRC);
5377 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
0a915b95
CW		 5378
5379 /* OS2BMC Stats */
5380 reg = rd32(E1000_MANC);
5381 if (reg & E1000_MANC_EN_BMC2OS) {
5382 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5383 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5384 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5385 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5386 }
9d5c8243
AK		 5387}
5388
9d5c8243
AK		 5389static irqreturn_t igb_msix_other(int irq, void *data)
5390{
047e0030 5391 struct igb_adapter *adapter = data;
9d5c8243 5392 struct e1000_hw *hw = &adapter->hw;
844290e5 5393 u32 icr = rd32(E1000_ICR);
844290e5 5394 /* reading ICR causes bit 31 of EICR to be cleared */
dda0e083 5395
7f081d40
AD		 5396 if (icr & E1000_ICR_DRSTA)
5397 schedule_work(&adapter->reset_task);
5398
047e0030 5399 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 5400 /* HW is reporting DMA is out of sync */
5401 adapter->stats.doosync++;
13800469
GR		 5402 /* The DMA Out of Sync is also indication of a spoof event
5403 * in IOV mode. Check the Wrong VM Behavior register to
b980ac18
JK		 5404 * see if it is really a spoof event.
5405 */
13800469 5406 igb_check_wvbr(adapter);
dda0e083 5407 }
eebbbdba 5408
4ae196df
AD		 5409 /* Check for a mailbox event */
5410 if (icr & E1000_ICR_VMMB)
5411 igb_msg_task(adapter);
5412
5413 if (icr & E1000_ICR_LSC) {
5414 hw->mac.get_link_status = 1;
5415 /* guard against interrupt when we're going down */
5416 if (!test_bit(__IGB_DOWN, &adapter->state))
5417 mod_timer(&adapter->watchdog_timer, jiffies + 1);
5418 }
5419
1f6e8178
MV		 5420 if (icr & E1000_ICR_TS) {
5421 u32 tsicr = rd32(E1000_TSICR);
5422
5423 if (tsicr & E1000_TSICR_TXTS) {
5424 /* acknowledge the interrupt */
5425 wr32(E1000_TSICR, E1000_TSICR_TXTS);
5426 /* retrieve hardware timestamp */
5427 schedule_work(&adapter->ptp_tx_work);
5428 }
5429 }
1f6e8178 5430
844290e5 5431 wr32(E1000_EIMS, adapter->eims_other);
9d5c8243
AK		 5432
5433 return IRQ_HANDLED;
5434}
5435
047e0030 5436static void igb_write_itr(struct igb_q_vector *q_vector)
9d5c8243 5437{
26b39276 5438 struct igb_adapter *adapter = q_vector->adapter;
047e0030 5439 u32 itr_val = q_vector->itr_val & 0x7FFC;
9d5c8243 5440
047e0030
AD		 5441 if (!q_vector->set_itr)
5442 return;
73cd78f1 5443
047e0030
AD		 5444 if (!itr_val)
5445 itr_val = 0x4;
661086df 5446
26b39276
AD		 5447 if (adapter->hw.mac.type == e1000_82575)
5448 itr_val |= itr_val << 16;
661086df 5449 else
0ba82994 5450 itr_val |= E1000_EITR_CNT_IGNR;
661086df 5451
047e0030
AD		 5452 writel(itr_val, q_vector->itr_register);
5453 q_vector->set_itr = 0;
6eb5a7f1
AD		 5454}
5455
047e0030 5456static irqreturn_t igb_msix_ring(int irq, void *data)
9d5c8243 5457{
047e0030 5458 struct igb_q_vector *q_vector = data;
9d5c8243 5459
047e0030
AD		 5460 /* Write the ITR value calculated from the previous interrupt. */
5461 igb_write_itr(q_vector);
9d5c8243 5462
047e0030 5463 napi_schedule(&q_vector->napi);
844290e5 5464
047e0030 5465 return IRQ_HANDLED;
fe4506b6
JC		 5466}
5467
421e02f0 5468#ifdef CONFIG_IGB_DCA
6a05004a
AD		 5469static void igb_update_tx_dca(struct igb_adapter *adapter,
5470 struct igb_ring *tx_ring,
5471 int cpu)
5472{
5473 struct e1000_hw *hw = &adapter->hw;
5474 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5475
5476 if (hw->mac.type != e1000_82575)
5477 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5478
b980ac18 5479 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5480 * DCA is enabled. This is due to a known issue in some chipsets
5481 * which will cause the DCA tag to be cleared.
5482 */
5483 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5484 E1000_DCA_TXCTRL_DATA_RRO_EN |
5485 E1000_DCA_TXCTRL_DESC_DCA_EN;
5486
5487 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5488}
5489
5490static void igb_update_rx_dca(struct igb_adapter *adapter,
5491 struct igb_ring *rx_ring,
5492 int cpu)
5493{
5494 struct e1000_hw *hw = &adapter->hw;
5495 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5496
5497 if (hw->mac.type != e1000_82575)
5498 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5499
b980ac18 5500 /* We can enable relaxed ordering for reads, but not writes when
6a05004a
AD		 5501 * DCA is enabled. This is due to a known issue in some chipsets
5502 * which will cause the DCA tag to be cleared.
5503 */
5504 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5505 E1000_DCA_RXCTRL_DESC_DCA_EN;
5506
5507 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5508}
5509
047e0030 5510static void igb_update_dca(struct igb_q_vector *q_vector)
fe4506b6 5511{
047e0030 5512 struct igb_adapter *adapter = q_vector->adapter;
fe4506b6 5513 int cpu = get_cpu();
fe4506b6 5514
047e0030
AD		 5515 if (q_vector->cpu == cpu)
5516 goto out_no_update;
5517
6a05004a
AD		 5518 if (q_vector->tx.ring)
5519 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5520
5521 if (q_vector->rx.ring)
5522 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5523
047e0030
AD		 5524 q_vector->cpu = cpu;
5525out_no_update:
fe4506b6
JC		 5526 put_cpu();
5527}
5528
5529static void igb_setup_dca(struct igb_adapter *adapter)
5530{
7e0e99ef 5531 struct e1000_hw *hw = &adapter->hw;
fe4506b6
JC		 5532 int i;
5533
7dfc16fa 5534 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
fe4506b6
JC		 5535 return;
5536
7e0e99ef
AD		 5537 /* Always use CB2 mode, difference is masked in the CB driver. */
5538 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5539
047e0030 5540 for (i = 0; i < adapter->num_q_vectors; i++) {
26b39276
AD		 5541 adapter->q_vector[i]->cpu = -1;
5542 igb_update_dca(adapter->q_vector[i]);
fe4506b6
JC		 5543 }
5544}
5545
5546static int __igb_notify_dca(struct device *dev, void *data)
5547{
5548 struct net_device *netdev = dev_get_drvdata(dev);
5549 struct igb_adapter *adapter = netdev_priv(netdev);
090b1795 5550 struct pci_dev *pdev = adapter->pdev;
fe4506b6
JC		 5551 struct e1000_hw *hw = &adapter->hw;
5552 unsigned long event = *(unsigned long *)data;
5553
5554 switch (event) {
5555 case DCA_PROVIDER_ADD:
5556 /* if already enabled, don't do it again */
7dfc16fa 5557 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
fe4506b6 5558 break;
fe4506b6 5559 if (dca_add_requester(dev) == 0) {
bbd98fe4 5560 adapter->flags |= IGB_FLAG_DCA_ENABLED;
090b1795 5561 dev_info(&pdev->dev, "DCA enabled\n");
fe4506b6
JC		 5562 igb_setup_dca(adapter);
5563 break;
5564 }
5565 /* Fall Through since DCA is disabled. */
5566 case DCA_PROVIDER_REMOVE:
7dfc16fa 5567 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
fe4506b6 5568 /* without this a class_device is left
b980ac18
JK		 5569 * hanging around in the sysfs model
5570 */
fe4506b6 5571 dca_remove_requester(dev);
090b1795 5572 dev_info(&pdev->dev, "DCA disabled\n");
7dfc16fa 5573 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
cbd347ad 5574 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
fe4506b6
JC		 5575 }
5576 break;
5577 }
bbd98fe4 5578
fe4506b6 5579 return 0;
9d5c8243
AK		 5580}
5581
fe4506b6 5582static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
b980ac18 5583 void *p)
fe4506b6
JC		 5584{
5585 int ret_val;
5586
5587 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
b980ac18 5588 __igb_notify_dca);
fe4506b6
JC		 5589
5590 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5591}
421e02f0 5592#endif /* CONFIG_IGB_DCA */
9d5c8243 5593
0224d663
GR		 5594#ifdef CONFIG_PCI_IOV
5595static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5596{
5597 unsigned char mac_addr[ETH_ALEN];
0224d663 5598
5ac6f91d 5599 eth_zero_addr(mac_addr);
0224d663
GR		 5600 igb_set_vf_mac(adapter, vf, mac_addr);
5601
70ea4783
LL		 5602 /* By default spoof check is enabled for all VFs */
5603 adapter->vf_data[vf].spoofchk_enabled = true;
5604
f557147c 5605 return 0;
0224d663
GR		 5606}
5607
0224d663 5608#endif
4ae196df
AD		 5609static void igb_ping_all_vfs(struct igb_adapter *adapter)
5610{
5611 struct e1000_hw *hw = &adapter->hw;
5612 u32 ping;
5613 int i;
5614
5615 for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5616 ping = E1000_PF_CONTROL_MSG;
f2ca0dbe 5617 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4ae196df
AD		 5618 ping |= E1000_VT_MSGTYPE_CTS;
5619 igb_write_mbx(hw, &ping, 1, i);
5620 }
5621}
5622
7d5753f0
AD		 5623static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5624{
5625 struct e1000_hw *hw = &adapter->hw;
5626 u32 vmolr = rd32(E1000_VMOLR(vf));
5627 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5628
d85b9004 5629 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
b980ac18 5630 IGB_VF_FLAG_MULTI_PROMISC);
7d5753f0
AD		 5631 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5632
5633 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5634 vmolr |= E1000_VMOLR_MPME;
d85b9004 5635 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
7d5753f0
AD		 5636 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5637 } else {
b980ac18 5638 /* if we have hashes and we are clearing a multicast promisc
7d5753f0
AD		 5639 * flag we need to write the hashes to the MTA as this step
5640 * was previously skipped
5641 */
5642 if (vf_data->num_vf_mc_hashes > 30) {
5643 vmolr |= E1000_VMOLR_MPME;
5644 } else if (vf_data->num_vf_mc_hashes) {
5645 int j;
9005df38 5646
7d5753f0
AD		 5647 vmolr |= E1000_VMOLR_ROMPE;
5648 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5649 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5650 }
5651 }
5652
5653 wr32(E1000_VMOLR(vf), vmolr);
5654
5655 /* there are flags left unprocessed, likely not supported */
5656 if (*msgbuf & E1000_VT_MSGINFO_MASK)
5657 return -EINVAL;
5658
5659 return 0;
7d5753f0
AD		 5660}
5661
4ae196df
AD		 5662static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5663 u32 *msgbuf, u32 vf)
5664{
5665 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5666 u16 *hash_list = (u16 *)&msgbuf[1];
5667 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5668 int i;
5669
7d5753f0 5670 /* salt away the number of multicast addresses assigned
4ae196df
AD		 5671 * to this VF for later use to restore when the PF multi cast
5672 * list changes
5673 */
5674 vf_data->num_vf_mc_hashes = n;
5675
7d5753f0
AD		 5676 /* only up to 30 hash values supported */
5677 if (n > 30)
5678 n = 30;
5679
5680 /* store the hashes for later use */
4ae196df 5681 for (i = 0; i < n; i++)
a419aef8 5682 vf_data->vf_mc_hashes[i] = hash_list[i];
4ae196df
AD		 5683
5684 /* Flush and reset the mta with the new values */
ff41f8dc 5685 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5686
5687 return 0;
5688}
5689
5690static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5691{
5692 struct e1000_hw *hw = &adapter->hw;
5693 struct vf_data_storage *vf_data;
5694 int i, j;
5695
5696 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7d5753f0 5697 u32 vmolr = rd32(E1000_VMOLR(i));
9005df38 5698
7d5753f0
AD		 5699 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5700
4ae196df 5701 vf_data = &adapter->vf_data[i];
7d5753f0
AD		 5702
5703 if ((vf_data->num_vf_mc_hashes > 30) ||
5704 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5705 vmolr |= E1000_VMOLR_MPME;
5706 } else if (vf_data->num_vf_mc_hashes) {
5707 vmolr |= E1000_VMOLR_ROMPE;
5708 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5709 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5710 }
5711 wr32(E1000_VMOLR(i), vmolr);
4ae196df
AD		 5712 }
5713}
5714
5715static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5716{
5717 struct e1000_hw *hw = &adapter->hw;
5718 u32 pool_mask, reg, vid;
5719 int i;
5720
5721 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5722
5723 /* Find the vlan filter for this id */
5724 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5725 reg = rd32(E1000_VLVF(i));
5726
5727 /* remove the vf from the pool */
5728 reg &= ~pool_mask;
5729
5730 /* if pool is empty then remove entry from vfta */
5731 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5732 (reg & E1000_VLVF_VLANID_ENABLE)) {
5733 reg = 0;
5734 vid = reg & E1000_VLVF_VLANID_MASK;
5735 igb_vfta_set(hw, vid, false);
5736 }
5737
5738 wr32(E1000_VLVF(i), reg);
5739 }
ae641bdc
AD		 5740
5741 adapter->vf_data[vf].vlans_enabled = 0;
4ae196df
AD		 5742}
5743
5744static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5745{
5746 struct e1000_hw *hw = &adapter->hw;
5747 u32 reg, i;
5748
51466239
AD		 5749 /* The vlvf table only exists on 82576 hardware and newer */
5750 if (hw->mac.type < e1000_82576)
5751 return -1;
5752
5753 /* we only need to do this if VMDq is enabled */
4ae196df
AD		 5754 if (!adapter->vfs_allocated_count)
5755 return -1;
5756
5757 /* Find the vlan filter for this id */
5758 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5759 reg = rd32(E1000_VLVF(i));
5760 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5761 vid == (reg & E1000_VLVF_VLANID_MASK))
5762 break;
5763 }
5764
5765 if (add) {
5766 if (i == E1000_VLVF_ARRAY_SIZE) {
5767 /* Did not find a matching VLAN ID entry that was
5768 * enabled. Search for a free filter entry, i.e.
5769 * one without the enable bit set
5770 */
5771 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5772 reg = rd32(E1000_VLVF(i));
5773 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5774 break;
5775 }
5776 }
5777 if (i < E1000_VLVF_ARRAY_SIZE) {
5778 /* Found an enabled/available entry */
5779 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5780
5781 /* if !enabled we need to set this up in vfta */
5782 if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
51466239
AD		 5783 /* add VID to filter table */
5784 igb_vfta_set(hw, vid, true);
4ae196df
AD		 5785 reg |= E1000_VLVF_VLANID_ENABLE;
5786 }
cad6d05f
AD		 5787 reg &= ~E1000_VLVF_VLANID_MASK;
5788 reg |= vid;
4ae196df 5789 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5790
5791 /* do not modify RLPML for PF devices */
5792 if (vf >= adapter->vfs_allocated_count)
5793 return 0;
5794
5795 if (!adapter->vf_data[vf].vlans_enabled) {
5796 u32 size;
9005df38 5797
ae641bdc
AD		 5798 reg = rd32(E1000_VMOLR(vf));
5799 size = reg & E1000_VMOLR_RLPML_MASK;
5800 size += 4;
5801 reg &= ~E1000_VMOLR_RLPML_MASK;
5802 reg |= size;
5803 wr32(E1000_VMOLR(vf), reg);
5804 }
ae641bdc 5805
51466239 5806 adapter->vf_data[vf].vlans_enabled++;
4ae196df
AD		 5807 }
5808 } else {
5809 if (i < E1000_VLVF_ARRAY_SIZE) {
5810 /* remove vf from the pool */
5811 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5812 /* if pool is empty then remove entry from vfta */
5813 if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5814 reg = 0;
5815 igb_vfta_set(hw, vid, false);
5816 }
5817 wr32(E1000_VLVF(i), reg);
ae641bdc
AD		 5818
5819 /* do not modify RLPML for PF devices */
5820 if (vf >= adapter->vfs_allocated_count)
5821 return 0;
5822
5823 adapter->vf_data[vf].vlans_enabled--;
5824 if (!adapter->vf_data[vf].vlans_enabled) {
5825 u32 size;
9005df38 5826
ae641bdc
AD		 5827 reg = rd32(E1000_VMOLR(vf));
5828 size = reg & E1000_VMOLR_RLPML_MASK;
5829 size -= 4;
5830 reg &= ~E1000_VMOLR_RLPML_MASK;
5831 reg |= size;
5832 wr32(E1000_VMOLR(vf), reg);
5833 }
4ae196df
AD		 5834 }
5835 }
8151d294
WM		 5836 return 0;
5837}
5838
5839static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5840{
5841 struct e1000_hw *hw = &adapter->hw;
5842
5843 if (vid)
5844 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5845 else
5846 wr32(E1000_VMVIR(vf), 0);
5847}
5848
5849static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5850 int vf, u16 vlan, u8 qos)
5851{
5852 int err = 0;
5853 struct igb_adapter *adapter = netdev_priv(netdev);
5854
5855 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5856 return -EINVAL;
5857 if (vlan || qos) {
5858 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5859 if (err)
5860 goto out;
5861 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5862 igb_set_vmolr(adapter, vf, !vlan);
5863 adapter->vf_data[vf].pf_vlan = vlan;
5864 adapter->vf_data[vf].pf_qos = qos;
5865 dev_info(&adapter->pdev->dev,
5866 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5867 if (test_bit(__IGB_DOWN, &adapter->state)) {
5868 dev_warn(&adapter->pdev->dev,
b980ac18 5869 "The VF VLAN has been set, but the PF device is not up.\n");
8151d294 5870 dev_warn(&adapter->pdev->dev,
b980ac18 5871 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 5872 }
5873 } else {
5874 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
b980ac18 5875 false, vf);
8151d294
WM		 5876 igb_set_vmvir(adapter, vlan, vf);
5877 igb_set_vmolr(adapter, vf, true);
5878 adapter->vf_data[vf].pf_vlan = 0;
5879 adapter->vf_data[vf].pf_qos = 0;
b980ac18 5880 }
8151d294 5881out:
b980ac18 5882 return err;
4ae196df
AD		 5883}
5884
6f3dc319
GR		 5885static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid)
5886{
5887 struct e1000_hw *hw = &adapter->hw;
5888 int i;
5889 u32 reg;
5890
5891 /* Find the vlan filter for this id */
5892 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5893 reg = rd32(E1000_VLVF(i));
5894 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5895 vid == (reg & E1000_VLVF_VLANID_MASK))
5896 break;
5897 }
5898
5899 if (i >= E1000_VLVF_ARRAY_SIZE)
5900 i = -1;
5901
5902 return i;
5903}
5904
4ae196df
AD		 5905static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5906{
6f3dc319 5907 struct e1000_hw *hw = &adapter->hw;
4ae196df
AD		 5908 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5909 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
6f3dc319 5910 int err = 0;
4ae196df 5911
6f3dc319
GR		 5912 /* If in promiscuous mode we need to make sure the PF also has
5913 * the VLAN filter set.
5914 */
5915 if (add && (adapter->netdev->flags & IFF_PROMISC))
5916 err = igb_vlvf_set(adapter, vid, add,
5917 adapter->vfs_allocated_count);
5918 if (err)
5919 goto out;
5920
5921 err = igb_vlvf_set(adapter, vid, add, vf);
5922
5923 if (err)
5924 goto out;
5925
5926 /* Go through all the checks to see if the VLAN filter should
5927 * be wiped completely.
5928 */
5929 if (!add && (adapter->netdev->flags & IFF_PROMISC)) {
5930 u32 vlvf, bits;
6f3dc319 5931 int regndx = igb_find_vlvf_entry(adapter, vid);
9005df38 5932
6f3dc319
GR		 5933 if (regndx < 0)
5934 goto out;
5935 /* See if any other pools are set for this VLAN filter
5936 * entry other than the PF.
5937 */
5938 vlvf = bits = rd32(E1000_VLVF(regndx));
5939 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT +
5940 adapter->vfs_allocated_count);
5941 /* If the filter was removed then ensure PF pool bit
5942 * is cleared if the PF only added itself to the pool
5943 * because the PF is in promiscuous mode.
5944 */
5945 if ((vlvf & VLAN_VID_MASK) == vid &&
5946 !test_bit(vid, adapter->active_vlans) &&
5947 !bits)
5948 igb_vlvf_set(adapter, vid, add,
5949 adapter->vfs_allocated_count);
5950 }
5951
5952out:
5953 return err;
4ae196df
AD		 5954}
5955
f2ca0dbe 5956static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
4ae196df 5957{
8fa7e0f7
GR		 5958 /* clear flags - except flag that indicates PF has set the MAC */
5959 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
f2ca0dbe 5960 adapter->vf_data[vf].last_nack = jiffies;
4ae196df
AD		 5961
5962 /* reset offloads to defaults */
8151d294 5963 igb_set_vmolr(adapter, vf, true);
4ae196df
AD		 5964
5965 /* reset vlans for device */
5966 igb_clear_vf_vfta(adapter, vf);
8151d294
WM		 5967 if (adapter->vf_data[vf].pf_vlan)
5968 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5969 adapter->vf_data[vf].pf_vlan,
5970 adapter->vf_data[vf].pf_qos);
5971 else
5972 igb_clear_vf_vfta(adapter, vf);
4ae196df
AD		 5973
5974 /* reset multicast table array for vf */
5975 adapter->vf_data[vf].num_vf_mc_hashes = 0;
5976
5977 /* Flush and reset the mta with the new values */
ff41f8dc 5978 igb_set_rx_mode(adapter->netdev);
4ae196df
AD		 5979}
5980
f2ca0dbe
AD		 5981static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5982{
5983 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5984
5ac6f91d 5985 /* clear mac address as we were hotplug removed/added */
8151d294 5986 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5ac6f91d 5987 eth_zero_addr(vf_mac);
f2ca0dbe
AD		 5988
5989 /* process remaining reset events */
5990 igb_vf_reset(adapter, vf);
5991}
5992
5993static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4ae196df
AD		 5994{
5995 struct e1000_hw *hw = &adapter->hw;
5996 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
ff41f8dc 5997 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df
AD		 5998 u32 reg, msgbuf[3];
5999 u8 *addr = (u8 *)(&msgbuf[1]);
6000
6001 /* process all the same items cleared in a function level reset */
f2ca0dbe 6002 igb_vf_reset(adapter, vf);
4ae196df
AD		 6003
6004 /* set vf mac address */
26ad9178 6005 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
4ae196df
AD		 6006
6007 /* enable transmit and receive for vf */
6008 reg = rd32(E1000_VFTE);
6009 wr32(E1000_VFTE, reg | (1 << vf));
6010 reg = rd32(E1000_VFRE);
6011 wr32(E1000_VFRE, reg | (1 << vf));
6012
8fa7e0f7 6013 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
4ae196df
AD		 6014
6015 /* reply to reset with ack and vf mac address */
6016 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
d458cdf7 6017 memcpy(addr, vf_mac, ETH_ALEN);
4ae196df
AD		 6018 igb_write_mbx(hw, msgbuf, 3, vf);
6019}
6020
6021static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
6022{
b980ac18 6023 /* The VF MAC Address is stored in a packed array of bytes
de42edde
GR		 6024 * starting at the second 32 bit word of the msg array
6025 */
f2ca0dbe
AD		 6026 unsigned char *addr = (char *)&msg[1];
6027 int err = -1;
4ae196df 6028
f2ca0dbe
AD		 6029 if (is_valid_ether_addr(addr))
6030 err = igb_set_vf_mac(adapter, vf, addr);
4ae196df 6031
f2ca0dbe 6032 return err;
4ae196df
AD		 6033}
6034
6035static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
6036{
6037 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6038 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6039 u32 msg = E1000_VT_MSGTYPE_NACK;
6040
6041 /* if device isn't clear to send it shouldn't be reading either */
f2ca0dbe
AD		 6042 if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
6043 time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
4ae196df 6044 igb_write_mbx(hw, &msg, 1, vf);
f2ca0dbe 6045 vf_data->last_nack = jiffies;
4ae196df
AD		 6046 }
6047}
6048
f2ca0dbe 6049static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4ae196df 6050{
f2ca0dbe
AD		 6051 struct pci_dev *pdev = adapter->pdev;
6052 u32 msgbuf[E1000_VFMAILBOX_SIZE];
4ae196df 6053 struct e1000_hw *hw = &adapter->hw;
f2ca0dbe 6054 struct vf_data_storage *vf_data = &adapter->vf_data[vf];
4ae196df
AD		 6055 s32 retval;
6056
f2ca0dbe 6057 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
4ae196df 6058
fef45f4c
AD		 6059 if (retval) {
6060 /* if receive failed revoke VF CTS stats and restart init */
f2ca0dbe 6061 dev_err(&pdev->dev, "Error receiving message from VF\n");
fef45f4c
AD		 6062 vf_data->flags &= ~IGB_VF_FLAG_CTS;
6063 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6064 return;
6065 goto out;
6066 }
4ae196df
AD		 6067
6068 /* this is a message we already processed, do nothing */
6069 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
f2ca0dbe 6070 return;
4ae196df 6071
b980ac18 6072 /* until the vf completes a reset it should not be
4ae196df
AD		 6073 * allowed to start any configuration.
6074 */
4ae196df
AD		 6075 if (msgbuf[0] == E1000_VF_RESET) {
6076 igb_vf_reset_msg(adapter, vf);
f2ca0dbe 6077 return;
4ae196df
AD		 6078 }
6079
f2ca0dbe 6080 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
fef45f4c
AD		 6081 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
6082 return;
6083 retval = -1;
6084 goto out;
4ae196df
AD		 6085 }
6086
6087 switch ((msgbuf[0] & 0xFFFF)) {
6088 case E1000_VF_SET_MAC_ADDR:
a6b5ea35
GR		 6089 retval = -EINVAL;
6090 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
6091 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
6092 else
6093 dev_warn(&pdev->dev,
b980ac18
JK		 6094 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6095 vf);
4ae196df 6096 break;
7d5753f0
AD		 6097 case E1000_VF_SET_PROMISC:
6098 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
6099 break;
4ae196df
AD		 6100 case E1000_VF_SET_MULTICAST:
6101 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
6102 break;
6103 case E1000_VF_SET_LPE:
6104 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
6105 break;
6106 case E1000_VF_SET_VLAN:
a6b5ea35
GR		 6107 retval = -1;
6108 if (vf_data->pf_vlan)
6109 dev_warn(&pdev->dev,
b980ac18
JK		 6110 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6111 vf);
8151d294
WM		 6112 else
6113 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4ae196df
AD		 6114 break;
6115 default:
090b1795 6116 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4ae196df
AD		 6117 retval = -1;
6118 break;
6119 }
6120
fef45f4c
AD		 6121 msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
6122out:
4ae196df
AD		 6123 /* notify the VF of the results of what it sent us */
6124 if (retval)
6125 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
6126 else
6127 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
6128
4ae196df 6129 igb_write_mbx(hw, msgbuf, 1, vf);
f2ca0dbe 6130}
4ae196df 6131
f2ca0dbe
AD		 6132static void igb_msg_task(struct igb_adapter *adapter)
6133{
6134 struct e1000_hw *hw = &adapter->hw;
6135 u32 vf;
6136
6137 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
6138 /* process any reset requests */
6139 if (!igb_check_for_rst(hw, vf))
6140 igb_vf_reset_event(adapter, vf);
6141
6142 /* process any messages pending */
6143 if (!igb_check_for_msg(hw, vf))
6144 igb_rcv_msg_from_vf(adapter, vf);
6145
6146 /* process any acks */
6147 if (!igb_check_for_ack(hw, vf))
6148 igb_rcv_ack_from_vf(adapter, vf);
6149 }
4ae196df
AD		 6150}
6151
68d480c4
AD		 6152/**
6153 * igb_set_uta - Set unicast filter table address
6154 * @adapter: board private structure
6155 *
6156 * The unicast table address is a register array of 32-bit registers.
6157 * The table is meant to be used in a way similar to how the MTA is used
6158 * however due to certain limitations in the hardware it is necessary to
25985edc
LDM		 6159 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6160 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
68d480c4
AD		 6161 **/
6162static void igb_set_uta(struct igb_adapter *adapter)
6163{
6164 struct e1000_hw *hw = &adapter->hw;
6165 int i;
6166
6167 /* The UTA table only exists on 82576 hardware and newer */
6168 if (hw->mac.type < e1000_82576)
6169 return;
6170
6171 /* we only need to do this if VMDq is enabled */
6172 if (!adapter->vfs_allocated_count)
6173 return;
6174
6175 for (i = 0; i < hw->mac.uta_reg_count; i++)
6176 array_wr32(E1000_UTA, i, ~0);
6177}
6178
9d5c8243 6179/**
b980ac18
JK		 6180 * igb_intr_msi - Interrupt Handler
6181 * @irq: interrupt number
6182 * @data: pointer to a network interface device structure
9d5c8243
AK		 6183 **/
6184static irqreturn_t igb_intr_msi(int irq, void *data)
6185{
047e0030
AD		 6186 struct igb_adapter *adapter = data;
6187 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6188 struct e1000_hw *hw = &adapter->hw;
6189 /* read ICR disables interrupts using IAM */
6190 u32 icr = rd32(E1000_ICR);
6191
047e0030 6192 igb_write_itr(q_vector);
9d5c8243 6193
7f081d40
AD		 6194 if (icr & E1000_ICR_DRSTA)
6195 schedule_work(&adapter->reset_task);
6196
047e0030 6197 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6198 /* HW is reporting DMA is out of sync */
6199 adapter->stats.doosync++;
6200 }
6201
9d5c8243
AK		 6202 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6203 hw->mac.get_link_status = 1;
6204 if (!test_bit(__IGB_DOWN, &adapter->state))
6205 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6206 }
6207
1f6e8178
MV		 6208 if (icr & E1000_ICR_TS) {
6209 u32 tsicr = rd32(E1000_TSICR);
6210
6211 if (tsicr & E1000_TSICR_TXTS) {
6212 /* acknowledge the interrupt */
6213 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6214 /* retrieve hardware timestamp */
6215 schedule_work(&adapter->ptp_tx_work);
6216 }
6217 }
1f6e8178 6218
047e0030 6219 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6220
6221 return IRQ_HANDLED;
6222}
6223
6224/**
b980ac18
JK		 6225 * igb_intr - Legacy Interrupt Handler
6226 * @irq: interrupt number
6227 * @data: pointer to a network interface device structure
9d5c8243
AK		 6228 **/
6229static irqreturn_t igb_intr(int irq, void *data)
6230{
047e0030
AD		 6231 struct igb_adapter *adapter = data;
6232 struct igb_q_vector *q_vector = adapter->q_vector[0];
9d5c8243
AK		 6233 struct e1000_hw *hw = &adapter->hw;
6234 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
b980ac18
JK		 6235 * need for the IMC write
6236 */
9d5c8243 6237 u32 icr = rd32(E1000_ICR);
9d5c8243
AK		 6238
6239 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
b980ac18
JK		 6240 * not set, then the adapter didn't send an interrupt
6241 */
9d5c8243
AK		 6242 if (!(icr & E1000_ICR_INT_ASSERTED))
6243 return IRQ_NONE;
6244
0ba82994
AD		 6245 igb_write_itr(q_vector);
6246
7f081d40
AD		 6247 if (icr & E1000_ICR_DRSTA)
6248 schedule_work(&adapter->reset_task);
6249
047e0030 6250 if (icr & E1000_ICR_DOUTSYNC) {
dda0e083
AD		 6251 /* HW is reporting DMA is out of sync */
6252 adapter->stats.doosync++;
6253 }
6254
9d5c8243
AK		 6255 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
6256 hw->mac.get_link_status = 1;
6257 /* guard against interrupt when we're going down */
6258 if (!test_bit(__IGB_DOWN, &adapter->state))
6259 mod_timer(&adapter->watchdog_timer, jiffies + 1);
6260 }
6261
1f6e8178
MV		 6262 if (icr & E1000_ICR_TS) {
6263 u32 tsicr = rd32(E1000_TSICR);
6264
6265 if (tsicr & E1000_TSICR_TXTS) {
6266 /* acknowledge the interrupt */
6267 wr32(E1000_TSICR, E1000_TSICR_TXTS);
6268 /* retrieve hardware timestamp */
6269 schedule_work(&adapter->ptp_tx_work);
6270 }
6271 }
1f6e8178 6272
047e0030 6273 napi_schedule(&q_vector->napi);
9d5c8243
AK		 6274
6275 return IRQ_HANDLED;
6276}
6277
c50b52a0 6278static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
9d5c8243 6279{
047e0030 6280 struct igb_adapter *adapter = q_vector->adapter;
46544258 6281 struct e1000_hw *hw = &adapter->hw;
9d5c8243 6282
0ba82994
AD		 6283 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
6284 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
6285 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
6286 igb_set_itr(q_vector);
46544258 6287 else
047e0030 6288 igb_update_ring_itr(q_vector);
9d5c8243
AK		 6289 }
6290
46544258 6291 if (!test_bit(__IGB_DOWN, &adapter->state)) {
cd14ef54 6292 if (adapter->flags & IGB_FLAG_HAS_MSIX)
047e0030 6293 wr32(E1000_EIMS, q_vector->eims_value);
46544258
AD		 6294 else
6295 igb_irq_enable(adapter);
6296 }
9d5c8243
AK		 6297}
6298
46544258 6299/**
b980ac18
JK		 6300 * igb_poll - NAPI Rx polling callback
6301 * @napi: napi polling structure
6302 * @budget: count of how many packets we should handle
46544258
AD		 6303 **/
6304static int igb_poll(struct napi_struct *napi, int budget)
9d5c8243 6305{
047e0030 6306 struct igb_q_vector *q_vector = container_of(napi,
b980ac18
JK		 6307 struct igb_q_vector,
6308 napi);
16eb8815 6309 bool clean_complete = true;
9d5c8243 6310
421e02f0 6311#ifdef CONFIG_IGB_DCA
047e0030
AD		 6312 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
6313 igb_update_dca(q_vector);
fe4506b6 6314#endif
0ba82994 6315 if (q_vector->tx.ring)
13fde97a 6316 clean_complete = igb_clean_tx_irq(q_vector);
9d5c8243 6317
0ba82994 6318 if (q_vector->rx.ring)
cd392f5c 6319 clean_complete &= igb_clean_rx_irq(q_vector, budget);
047e0030 6320
16eb8815
AD		 6321 /* If all work not completed, return budget and keep polling */
6322 if (!clean_complete)
6323 return budget;
46544258 6324
9d5c8243 6325 /* If not enough Rx work done, exit the polling mode */
16eb8815
AD		 6326 napi_complete(napi);
6327 igb_ring_irq_enable(q_vector);
9d5c8243 6328
16eb8815 6329 return 0;
9d5c8243 6330}
6d8126f9 6331
9d5c8243 6332/**
b980ac18
JK		 6333 * igb_clean_tx_irq - Reclaim resources after transmit completes
6334 * @q_vector: pointer to q_vector containing needed info
49ce9c2c 6335 *
b980ac18 6336 * returns true if ring is completely cleaned
9d5c8243 6337 **/
047e0030 6338static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
9d5c8243 6339{
047e0030 6340 struct igb_adapter *adapter = q_vector->adapter;
0ba82994 6341 struct igb_ring *tx_ring = q_vector->tx.ring;
06034649 6342 struct igb_tx_buffer *tx_buffer;
f4128785 6343 union e1000_adv_tx_desc *tx_desc;
9d5c8243 6344 unsigned int total_bytes = 0, total_packets = 0;
0ba82994 6345 unsigned int budget = q_vector->tx.work_limit;
8542db05 6346 unsigned int i = tx_ring->next_to_clean;
9d5c8243 6347
13fde97a
AD		 6348 if (test_bit(__IGB_DOWN, &adapter->state))
6349 return true;
0e014cb1 6350
06034649 6351 tx_buffer = &tx_ring->tx_buffer_info[i];
13fde97a 6352 tx_desc = IGB_TX_DESC(tx_ring, i);
8542db05 6353 i -= tx_ring->count;
9d5c8243 6354
f4128785
AD		 6355 do {
6356 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
8542db05
AD		 6357
6358 /* if next_to_watch is not set then there is no work pending */
6359 if (!eop_desc)
6360 break;
13fde97a 6361
f4128785 6362 /* prevent any other reads prior to eop_desc */
70d289bc 6363 read_barrier_depends();
f4128785 6364
13fde97a
AD		 6365 /* if DD is not set pending work has not been completed */
6366 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
6367 break;
6368
8542db05
AD		 6369 /* clear next_to_watch to prevent false hangs */
6370 tx_buffer->next_to_watch = NULL;
9d5c8243 6371
ebe42d16
AD		 6372 /* update the statistics for this packet */
6373 total_bytes += tx_buffer->bytecount;
6374 total_packets += tx_buffer->gso_segs;
13fde97a 6375
ebe42d16 6376 /* free the skb */
a81fb049 6377 dev_consume_skb_any(tx_buffer->skb);
13fde97a 6378
ebe42d16
AD		 6379 /* unmap skb header data */
6380 dma_unmap_single(tx_ring->dev,
c9f14bf3
AD		 6381 dma_unmap_addr(tx_buffer, dma),
6382 dma_unmap_len(tx_buffer, len),
ebe42d16
AD		 6383 DMA_TO_DEVICE);
6384
c9f14bf3
AD		 6385 /* clear tx_buffer data */
6386 tx_buffer->skb = NULL;
6387 dma_unmap_len_set(tx_buffer, len, 0);
6388
ebe42d16
AD		 6389 /* clear last DMA location and unmap remaining buffers */
6390 while (tx_desc != eop_desc) {
13fde97a
AD		 6391 tx_buffer++;
6392 tx_desc++;
9d5c8243 6393 i++;
8542db05
AD		 6394 if (unlikely(!i)) {
6395 i -= tx_ring->count;
06034649 6396 tx_buffer = tx_ring->tx_buffer_info;
13fde97a
AD		 6397 tx_desc = IGB_TX_DESC(tx_ring, 0);
6398 }
ebe42d16
AD		 6399
6400 /* unmap any remaining paged data */
c9f14bf3 6401 if (dma_unmap_len(tx_buffer, len)) {
ebe42d16 6402 dma_unmap_page(tx_ring->dev,
c9f14bf3
AD		 6403 dma_unmap_addr(tx_buffer, dma),
6404 dma_unmap_len(tx_buffer, len),
ebe42d16 6405 DMA_TO_DEVICE);
c9f14bf3 6406 dma_unmap_len_set(tx_buffer, len, 0);
ebe42d16
AD		 6407 }
6408 }
6409
ebe42d16
AD		 6410 /* move us one more past the eop_desc for start of next pkt */
6411 tx_buffer++;
6412 tx_desc++;
6413 i++;
6414 if (unlikely(!i)) {
6415 i -= tx_ring->count;
6416 tx_buffer = tx_ring->tx_buffer_info;
6417 tx_desc = IGB_TX_DESC(tx_ring, 0);
6418 }
f4128785
AD		 6419
6420 /* issue prefetch for next Tx descriptor */
6421 prefetch(tx_desc);
6422
6423 /* update budget accounting */
6424 budget--;
6425 } while (likely(budget));
0e014cb1 6426
bdbc0631
ED		 6427 netdev_tx_completed_queue(txring_txq(tx_ring),
6428 total_packets, total_bytes);
8542db05 6429 i += tx_ring->count;
9d5c8243 6430 tx_ring->next_to_clean = i;
13fde97a
AD		 6431 u64_stats_update_begin(&tx_ring->tx_syncp);
6432 tx_ring->tx_stats.bytes += total_bytes;
6433 tx_ring->tx_stats.packets += total_packets;
6434 u64_stats_update_end(&tx_ring->tx_syncp);
0ba82994
AD		 6435 q_vector->tx.total_bytes += total_bytes;
6436 q_vector->tx.total_packets += total_packets;
9d5c8243 6437
6d095fa8 6438 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
13fde97a 6439 struct e1000_hw *hw = &adapter->hw;
12dcd86b 6440
9d5c8243 6441 /* Detect a transmit hang in hardware, this serializes the
b980ac18
JK		 6442 * check with the clearing of time_stamp and movement of i
6443 */
6d095fa8 6444 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
f4128785 6445 if (tx_buffer->next_to_watch &&
8542db05 6446 time_after(jiffies, tx_buffer->time_stamp +
8e95a202
JP		 6447 (adapter->tx_timeout_factor * HZ)) &&
6448 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
9d5c8243 6449
9d5c8243 6450 /* detected Tx unit hang */
59d71989 6451 dev_err(tx_ring->dev,
9d5c8243 6452 "Detected Tx Unit Hang\n"
2d064c06 6453 " Tx Queue <%d>\n"
9d5c8243
AK		 6454 " TDH <%x>\n"
6455 " TDT <%x>\n"
6456 " next_to_use <%x>\n"
6457 " next_to_clean <%x>\n"
9d5c8243
AK		 6458 "buffer_info[next_to_clean]\n"
6459 " time_stamp <%lx>\n"
8542db05 6460 " next_to_watch <%p>\n"
9d5c8243
AK		 6461 " jiffies <%lx>\n"
6462 " desc.status <%x>\n",
2d064c06 6463 tx_ring->queue_index,
238ac817 6464 rd32(E1000_TDH(tx_ring->reg_idx)),
fce99e34 6465 readl(tx_ring->tail),
9d5c8243
AK		 6466 tx_ring->next_to_use,
6467 tx_ring->next_to_clean,
8542db05 6468 tx_buffer->time_stamp,
f4128785 6469 tx_buffer->next_to_watch,
9d5c8243 6470 jiffies,
f4128785 6471 tx_buffer->next_to_watch->wb.status);
13fde97a
AD		 6472 netif_stop_subqueue(tx_ring->netdev,
6473 tx_ring->queue_index);
6474
6475 /* we are about to reset, no point in enabling stuff */
6476 return true;
9d5c8243
AK		 6477 }
6478 }
13fde97a 6479
21ba6fe1 6480#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
13fde97a 6481 if (unlikely(total_packets &&
b980ac18
JK		 6482 netif_carrier_ok(tx_ring->netdev) &&
6483 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
13fde97a
AD		 6484 /* Make sure that anybody stopping the queue after this
6485 * sees the new next_to_clean.
6486 */
6487 smp_mb();
6488 if (__netif_subqueue_stopped(tx_ring->netdev,
6489 tx_ring->queue_index) &&
6490 !(test_bit(__IGB_DOWN, &adapter->state))) {
6491 netif_wake_subqueue(tx_ring->netdev,
6492 tx_ring->queue_index);
6493
6494 u64_stats_update_begin(&tx_ring->tx_syncp);
6495 tx_ring->tx_stats.restart_queue++;
6496 u64_stats_update_end(&tx_ring->tx_syncp);
6497 }
6498 }
6499
6500 return !!budget;
9d5c8243
AK		 6501}
6502
cbc8e55f 6503/**
b980ac18
JK		 6504 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6505 * @rx_ring: rx descriptor ring to store buffers on
6506 * @old_buff: donor buffer to have page reused
cbc8e55f 6507 *
b980ac18 6508 * Synchronizes page for reuse by the adapter
cbc8e55f
AD		 6509 **/
6510static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6511 struct igb_rx_buffer *old_buff)
6512{
6513 struct igb_rx_buffer *new_buff;
6514 u16 nta = rx_ring->next_to_alloc;
6515
6516 new_buff = &rx_ring->rx_buffer_info[nta];
6517
6518 /* update, and store next to alloc */
6519 nta++;
6520 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6521
6522 /* transfer page from old buffer to new buffer */
a1f63473 6523 *new_buff = *old_buff;
cbc8e55f
AD		 6524
6525 /* sync the buffer for use by the device */
6526 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6527 old_buff->page_offset,
de78d1f9 6528 IGB_RX_BUFSZ,
cbc8e55f
AD		 6529 DMA_FROM_DEVICE);
6530}
6531
74e238ea
AD		 6532static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6533 struct page *page,
6534 unsigned int truesize)
6535{
6536 /* avoid re-using remote pages */
6537 if (unlikely(page_to_nid(page) != numa_node_id()))
6538 return false;
6539
bc16e47f
RG		 6540 if (unlikely(page->pfmemalloc))
6541 return false;
6542
74e238ea
AD		 6543#if (PAGE_SIZE < 8192)
6544 /* if we are only owner of page we can reuse it */
6545 if (unlikely(page_count(page) != 1))
6546 return false;
6547
6548 /* flip page offset to other buffer */
6549 rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6550
00cd5adb
ED		 6551 /* Even if we own the page, we are not allowed to use atomic_set()
6552 * This would break get_page_unless_zero() users.
74e238ea 6553 */
00cd5adb 6554 atomic_inc(&page->_count);
74e238ea
AD		 6555#else
6556 /* move offset up to the next cache line */
6557 rx_buffer->page_offset += truesize;
6558
6559 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6560 return false;
6561
6562 /* bump ref count on page before it is given to the stack */
6563 get_page(page);
6564#endif
6565
6566 return true;
6567}
6568
cbc8e55f 6569/**
b980ac18
JK		 6570 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6571 * @rx_ring: rx descriptor ring to transact packets on
6572 * @rx_buffer: buffer containing page to add
6573 * @rx_desc: descriptor containing length of buffer written by hardware
6574 * @skb: sk_buff to place the data into
cbc8e55f 6575 *
b980ac18
JK		 6576 * This function will add the data contained in rx_buffer->page to the skb.
6577 * This is done either through a direct copy if the data in the buffer is
6578 * less than the skb header size, otherwise it will just attach the page as
6579 * a frag to the skb.
cbc8e55f 6580 *
b980ac18
JK		 6581 * The function will then update the page offset if necessary and return
6582 * true if the buffer can be reused by the adapter.
cbc8e55f
AD		 6583 **/
6584static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6585 struct igb_rx_buffer *rx_buffer,
6586 union e1000_adv_rx_desc *rx_desc,
6587 struct sk_buff *skb)
6588{
6589 struct page *page = rx_buffer->page;
6590 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
74e238ea
AD		 6591#if (PAGE_SIZE < 8192)
6592 unsigned int truesize = IGB_RX_BUFSZ;
6593#else
6594 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6595#endif
cbc8e55f
AD		 6596
6597 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6598 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6599
cbc8e55f
AD		 6600 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6601 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6602 va += IGB_TS_HDR_LEN;
6603 size -= IGB_TS_HDR_LEN;
6604 }
6605
cbc8e55f
AD		 6606 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6607
6608 /* we can reuse buffer as-is, just make sure it is local */
bc16e47f
RG		 6609 if (likely((page_to_nid(page) == numa_node_id()) &&
6610 !page->pfmemalloc))
cbc8e55f
AD		 6611 return true;
6612
6613 /* this page cannot be reused so discard it */
6614 put_page(page);
6615 return false;
6616 }
6617
6618 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
74e238ea 6619 rx_buffer->page_offset, size, truesize);
cbc8e55f 6620
74e238ea
AD		 6621 return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6622}
cbc8e55f 6623
2e334eee
AD		 6624static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6625 union e1000_adv_rx_desc *rx_desc,
6626 struct sk_buff *skb)
6627{
6628 struct igb_rx_buffer *rx_buffer;
6629 struct page *page;
6630
6631 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6632
2e334eee
AD		 6633 page = rx_buffer->page;
6634 prefetchw(page);
6635
6636 if (likely(!skb)) {
6637 void *page_addr = page_address(page) +
6638 rx_buffer->page_offset;
6639
6640 /* prefetch first cache line of first page */
6641 prefetch(page_addr);
6642#if L1_CACHE_BYTES < 128
6643 prefetch(page_addr + L1_CACHE_BYTES);
6644#endif
6645
6646 /* allocate a skb to store the frags */
6647 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6648 IGB_RX_HDR_LEN);
6649 if (unlikely(!skb)) {
6650 rx_ring->rx_stats.alloc_failed++;
6651 return NULL;
6652 }
6653
b980ac18 6654 /* we will be copying header into skb->data in
2e334eee
AD		 6655 * pskb_may_pull so it is in our interest to prefetch
6656 * it now to avoid a possible cache miss
6657 */
6658 prefetchw(skb->data);
6659 }
6660
6661 /* we are reusing so sync this buffer for CPU use */
6662 dma_sync_single_range_for_cpu(rx_ring->dev,
6663 rx_buffer->dma,
6664 rx_buffer->page_offset,
de78d1f9 6665 IGB_RX_BUFSZ,
2e334eee
AD		 6666 DMA_FROM_DEVICE);
6667
6668 /* pull page into skb */
6669 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6670 /* hand second half of page back to the ring */
6671 igb_reuse_rx_page(rx_ring, rx_buffer);
6672 } else {
6673 /* we are not reusing the buffer so unmap it */
6674 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6675 PAGE_SIZE, DMA_FROM_DEVICE);
6676 }
6677
6678 /* clear contents of rx_buffer */
6679 rx_buffer->page = NULL;
6680
6681 return skb;
6682}
6683
cd392f5c 6684static inline void igb_rx_checksum(struct igb_ring *ring,
3ceb90fd
AD		 6685 union e1000_adv_rx_desc *rx_desc,
6686 struct sk_buff *skb)
9d5c8243 6687{
bc8acf2c 6688 skb_checksum_none_assert(skb);
9d5c8243 6689
294e7d78 6690 /* Ignore Checksum bit is set */
3ceb90fd 6691 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
294e7d78
AD		 6692 return;
6693
6694 /* Rx checksum disabled via ethtool */
6695 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9d5c8243 6696 return;
85ad76b2 6697
9d5c8243 6698 /* TCP/UDP checksum error bit is set */
3ceb90fd
AD		 6699 if (igb_test_staterr(rx_desc,
6700 E1000_RXDEXT_STATERR_TCPE |
6701 E1000_RXDEXT_STATERR_IPE)) {
b980ac18 6702 /* work around errata with sctp packets where the TCPE aka
b9473560
JB		 6703 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6704 * packets, (aka let the stack check the crc32c)
6705 */
866cff06
AD		 6706 if (!((skb->len == 60) &&
6707 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
12dcd86b 6708 u64_stats_update_begin(&ring->rx_syncp);
04a5fcaa 6709 ring->rx_stats.csum_err++;
12dcd86b
ED		 6710 u64_stats_update_end(&ring->rx_syncp);
6711 }
9d5c8243 6712 /* let the stack verify checksum errors */
9d5c8243
AK		 6713 return;
6714 }
6715 /* It must be a TCP or UDP packet with a valid checksum */
3ceb90fd
AD		 6716 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6717 E1000_RXD_STAT_UDPCS))
9d5c8243
AK		 6718 skb->ip_summed = CHECKSUM_UNNECESSARY;
6719
3ceb90fd
AD		 6720 dev_dbg(ring->dev, "cksum success: bits %08X\n",
6721 le32_to_cpu(rx_desc->wb.upper.status_error));
9d5c8243
AK		 6722}
6723
077887c3
AD		 6724static inline void igb_rx_hash(struct igb_ring *ring,
6725 union e1000_adv_rx_desc *rx_desc,
6726 struct sk_buff *skb)
6727{
6728 if (ring->netdev->features & NETIF_F_RXHASH)
42bdf083
TH		 6729 skb_set_hash(skb,
6730 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
6731 PKT_HASH_TYPE_L3);
077887c3
AD		 6732}
6733
2e334eee 6734/**
b980ac18
JK		 6735 * igb_is_non_eop - process handling of non-EOP buffers
6736 * @rx_ring: Rx ring being processed
6737 * @rx_desc: Rx descriptor for current buffer
6738 * @skb: current socket buffer containing buffer in progress
2e334eee 6739 *
b980ac18
JK		 6740 * This function updates next to clean. If the buffer is an EOP buffer
6741 * this function exits returning false, otherwise it will place the
6742 * sk_buff in the next buffer to be chained and return true indicating
6743 * that this is in fact a non-EOP buffer.
2e334eee
AD		 6744 **/
6745static bool igb_is_non_eop(struct igb_ring *rx_ring,
6746 union e1000_adv_rx_desc *rx_desc)
6747{
6748 u32 ntc = rx_ring->next_to_clean + 1;
6749
6750 /* fetch, update, and store next to clean */
6751 ntc = (ntc < rx_ring->count) ? ntc : 0;
6752 rx_ring->next_to_clean = ntc;
6753
6754 prefetch(IGB_RX_DESC(rx_ring, ntc));
6755
6756 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6757 return false;
6758
6759 return true;
6760}
6761
1a1c225b 6762/**
b980ac18
JK		 6763 * igb_pull_tail - igb specific version of skb_pull_tail
6764 * @rx_ring: rx descriptor ring packet is being transacted on
6765 * @rx_desc: pointer to the EOP Rx descriptor
6766 * @skb: pointer to current skb being adjusted
1a1c225b 6767 *
b980ac18
JK		 6768 * This function is an igb specific version of __pskb_pull_tail. The
6769 * main difference between this version and the original function is that
6770 * this function can make several assumptions about the state of things
6771 * that allow for significant optimizations versus the standard function.
6772 * As a result we can do things like drop a frag and maintain an accurate
6773 * truesize for the skb.
1a1c225b
AD		 6774 */
6775static void igb_pull_tail(struct igb_ring *rx_ring,
6776 union e1000_adv_rx_desc *rx_desc,
6777 struct sk_buff *skb)
2d94d8ab 6778{
1a1c225b
AD		 6779 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6780 unsigned char *va;
6781 unsigned int pull_len;
6782
b980ac18 6783 /* it is valid to use page_address instead of kmap since we are
1a1c225b
AD		 6784 * working with pages allocated out of the lomem pool per
6785 * alloc_page(GFP_ATOMIC)
2d94d8ab 6786 */
1a1c225b
AD		 6787 va = skb_frag_address(frag);
6788
1a1c225b
AD		 6789 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6790 /* retrieve timestamp from buffer */
6791 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6792
6793 /* update pointers to remove timestamp header */
6794 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6795 frag->page_offset += IGB_TS_HDR_LEN;
6796 skb->data_len -= IGB_TS_HDR_LEN;
6797 skb->len -= IGB_TS_HDR_LEN;
6798
6799 /* move va to start of packet data */
6800 va += IGB_TS_HDR_LEN;
6801 }
6802
b980ac18 6803 /* we need the header to contain the greater of either ETH_HLEN or
1a1c225b
AD		 6804 * 60 bytes if the skb->len is less than 60 for skb_pad.
6805 */
24cd23d3 6806 pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
1a1c225b
AD		 6807
6808 /* align pull length to size of long to optimize memcpy performance */
6809 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6810
6811 /* update all of the pointers */
6812 skb_frag_size_sub(frag, pull_len);
6813 frag->page_offset += pull_len;
6814 skb->data_len -= pull_len;
6815 skb->tail += pull_len;
6816}
6817
6818/**
b980ac18
JK		 6819 * igb_cleanup_headers - Correct corrupted or empty headers
6820 * @rx_ring: rx descriptor ring packet is being transacted on
6821 * @rx_desc: pointer to the EOP Rx descriptor
6822 * @skb: pointer to current skb being fixed
1a1c225b 6823 *
b980ac18
JK		 6824 * Address the case where we are pulling data in on pages only
6825 * and as such no data is present in the skb header.
1a1c225b 6826 *
b980ac18
JK		 6827 * In addition if skb is not at least 60 bytes we need to pad it so that
6828 * it is large enough to qualify as a valid Ethernet frame.
1a1c225b 6829 *
b980ac18 6830 * Returns true if an error was encountered and skb was freed.
1a1c225b
AD		 6831 **/
6832static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6833 union e1000_adv_rx_desc *rx_desc,
6834 struct sk_buff *skb)
6835{
1a1c225b
AD		 6836 if (unlikely((igb_test_staterr(rx_desc,
6837 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6838 struct net_device *netdev = rx_ring->netdev;
6839 if (!(netdev->features & NETIF_F_RXALL)) {
6840 dev_kfree_skb_any(skb);
6841 return true;
6842 }
6843 }
6844
6845 /* place header in linear portion of buffer */
6846 if (skb_is_nonlinear(skb))
6847 igb_pull_tail(rx_ring, rx_desc, skb);
6848
a94d9e22
AD		 6849 /* if eth_skb_pad returns an error the skb was freed */
6850 if (eth_skb_pad(skb))
6851 return true;
1a1c225b
AD		 6852
6853 return false;
2d94d8ab
AD		 6854}
6855
db2ee5bd 6856/**
b980ac18
JK		 6857 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6858 * @rx_ring: rx descriptor ring packet is being transacted on
6859 * @rx_desc: pointer to the EOP Rx descriptor
6860 * @skb: pointer to current skb being populated
db2ee5bd 6861 *
b980ac18
JK		 6862 * This function checks the ring, descriptor, and packet information in
6863 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6864 * other fields within the skb.
db2ee5bd
AD		 6865 **/
6866static void igb_process_skb_fields(struct igb_ring *rx_ring,
6867 union e1000_adv_rx_desc *rx_desc,
6868 struct sk_buff *skb)
6869{
6870 struct net_device *dev = rx_ring->netdev;
6871
6872 igb_rx_hash(rx_ring, rx_desc, skb);
6873
6874 igb_rx_checksum(rx_ring, rx_desc, skb);
6875
5499a968
JK		 6876 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
6877 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
6878 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
db2ee5bd 6879
f646968f 6880 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
db2ee5bd
AD		 6881 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6882 u16 vid;
9005df38 6883
db2ee5bd
AD		 6884 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6885 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6886 vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6887 else
6888 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6889
86a9bad3 6890 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
db2ee5bd
AD		 6891 }
6892
6893 skb_record_rx_queue(skb, rx_ring->queue_index);
6894
6895 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6896}
6897
2e334eee 6898static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
9d5c8243 6899{
0ba82994 6900 struct igb_ring *rx_ring = q_vector->rx.ring;
1a1c225b 6901 struct sk_buff *skb = rx_ring->skb;
9d5c8243 6902 unsigned int total_bytes = 0, total_packets = 0;
16eb8815 6903 u16 cleaned_count = igb_desc_unused(rx_ring);
9d5c8243 6904
57ba34c9 6905 while (likely(total_packets < budget)) {
2e334eee 6906 union e1000_adv_rx_desc *rx_desc;
bf36c1a0 6907
2e334eee
AD		 6908 /* return some buffers to hardware, one at a time is too slow */
6909 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6910 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6911 cleaned_count = 0;
6912 }
bf36c1a0 6913
2e334eee 6914 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
16eb8815 6915
2e334eee
AD		 6916 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6917 break;
9d5c8243 6918
74e238ea
AD		 6919 /* This memory barrier is needed to keep us from reading
6920 * any other fields out of the rx_desc until we know the
6921 * RXD_STAT_DD bit is set
6922 */
6923 rmb();
6924
2e334eee 6925 /* retrieve a buffer from the ring */
f9d40f6a 6926 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
9d5c8243 6927
2e334eee
AD		 6928 /* exit if we failed to retrieve a buffer */
6929 if (!skb)
6930 break;
1a1c225b 6931
2e334eee 6932 cleaned_count++;
1a1c225b 6933
2e334eee
AD		 6934 /* fetch next buffer in frame if non-eop */
6935 if (igb_is_non_eop(rx_ring, rx_desc))
6936 continue;
1a1c225b
AD		 6937
6938 /* verify the packet layout is correct */
6939 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6940 skb = NULL;
6941 continue;
9d5c8243 6942 }
9d5c8243 6943
db2ee5bd 6944 /* probably a little skewed due to removing CRC */
3ceb90fd 6945 total_bytes += skb->len;
3ceb90fd 6946
db2ee5bd
AD		 6947 /* populate checksum, timestamp, VLAN, and protocol */
6948 igb_process_skb_fields(rx_ring, rx_desc, skb);
3ceb90fd 6949
b2cb09b1 6950 napi_gro_receive(&q_vector->napi, skb);
9d5c8243 6951
1a1c225b
AD		 6952 /* reset skb pointer */
6953 skb = NULL;
6954
2e334eee
AD		 6955 /* update budget accounting */
6956 total_packets++;
57ba34c9 6957 }
bf36c1a0 6958
1a1c225b
AD		 6959 /* place incomplete frames back on ring for completion */
6960 rx_ring->skb = skb;
6961
12dcd86b 6962 u64_stats_update_begin(&rx_ring->rx_syncp);
9d5c8243
AK		 6963 rx_ring->rx_stats.packets += total_packets;
6964 rx_ring->rx_stats.bytes += total_bytes;
12dcd86b 6965 u64_stats_update_end(&rx_ring->rx_syncp);
0ba82994
AD		 6966 q_vector->rx.total_packets += total_packets;
6967 q_vector->rx.total_bytes += total_bytes;
c023cd88
AD		 6968
6969 if (cleaned_count)
cd392f5c 6970 igb_alloc_rx_buffers(rx_ring, cleaned_count);
c023cd88 6971
da1f1dfe 6972 return total_packets < budget;
9d5c8243
AK		 6973}
6974
c023cd88 6975static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
06034649 6976 struct igb_rx_buffer *bi)
c023cd88
AD		 6977{
6978 struct page *page = bi->page;
cbc8e55f 6979 dma_addr_t dma;
c023cd88 6980
cbc8e55f
AD		 6981 /* since we are recycling buffers we should seldom need to alloc */
6982 if (likely(page))
c023cd88
AD		 6983 return true;
6984
cbc8e55f 6985 /* alloc new page for storage */
42b17f09 6986 page = dev_alloc_page();
cbc8e55f
AD		 6987 if (unlikely(!page)) {
6988 rx_ring->rx_stats.alloc_failed++;
6989 return false;
c023cd88
AD		 6990 }
6991
cbc8e55f
AD		 6992 /* map page for use */
6993 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
c023cd88 6994
b980ac18 6995 /* if mapping failed free memory back to system since
cbc8e55f
AD		 6996 * there isn't much point in holding memory we can't use
6997 */
1a1c225b 6998 if (dma_mapping_error(rx_ring->dev, dma)) {
cbc8e55f
AD		 6999 __free_page(page);
7000
c023cd88
AD		 7001 rx_ring->rx_stats.alloc_failed++;
7002 return false;
7003 }
7004
1a1c225b 7005 bi->dma = dma;
cbc8e55f
AD		 7006 bi->page = page;
7007 bi->page_offset = 0;
1a1c225b 7008
c023cd88
AD		 7009 return true;
7010}
7011
9d5c8243 7012/**
b980ac18
JK		 7013 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7014 * @adapter: address of board private structure
9d5c8243 7015 **/
cd392f5c 7016void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
9d5c8243 7017{
9d5c8243 7018 union e1000_adv_rx_desc *rx_desc;
06034649 7019 struct igb_rx_buffer *bi;
c023cd88 7020 u16 i = rx_ring->next_to_use;
9d5c8243 7021
cbc8e55f
AD		 7022 /* nothing to do */
7023 if (!cleaned_count)
7024 return;
7025
60136906 7026 rx_desc = IGB_RX_DESC(rx_ring, i);
06034649 7027 bi = &rx_ring->rx_buffer_info[i];
c023cd88 7028 i -= rx_ring->count;
9d5c8243 7029
cbc8e55f 7030 do {
1a1c225b 7031 if (!igb_alloc_mapped_page(rx_ring, bi))
c023cd88 7032 break;
9d5c8243 7033
b980ac18 7034 /* Refresh the desc even if buffer_addrs didn't change
cbc8e55f
AD		 7035 * because each write-back erases this info.
7036 */
f9d40f6a 7037 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9d5c8243 7038
c023cd88
AD		 7039 rx_desc++;
7040 bi++;
9d5c8243 7041 i++;
c023cd88 7042 if (unlikely(!i)) {
60136906 7043 rx_desc = IGB_RX_DESC(rx_ring, 0);
06034649 7044 bi = rx_ring->rx_buffer_info;
c023cd88
AD		 7045 i -= rx_ring->count;
7046 }
7047
7048 /* clear the hdr_addr for the next_to_use descriptor */
7049 rx_desc->read.hdr_addr = 0;
cbc8e55f
AD		 7050
7051 cleaned_count--;
7052 } while (cleaned_count);
9d5c8243 7053
c023cd88
AD		 7054 i += rx_ring->count;
7055
9d5c8243 7056 if (rx_ring->next_to_use != i) {
cbc8e55f 7057 /* record the next descriptor to use */
9d5c8243 7058 rx_ring->next_to_use = i;
9d5c8243 7059
cbc8e55f
AD		 7060 /* update next to alloc since we have filled the ring */
7061 rx_ring->next_to_alloc = i;
7062
b980ac18 7063 /* Force memory writes to complete before letting h/w
9d5c8243
AK		 7064 * know there are new descriptors to fetch. (Only
7065 * applicable for weak-ordered memory model archs,
cbc8e55f
AD		 7066 * such as IA-64).
7067 */
9d5c8243 7068 wmb();
fce99e34 7069 writel(i, rx_ring->tail);
9d5c8243
AK		 7070 }
7071}
7072
7073/**
7074 * igb_mii_ioctl -
7075 * @netdev:
7076 * @ifreq:
7077 * @cmd:
7078 **/
7079static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7080{
7081 struct igb_adapter *adapter = netdev_priv(netdev);
7082 struct mii_ioctl_data *data = if_mii(ifr);
7083
7084 if (adapter->hw.phy.media_type != e1000_media_type_copper)
7085 return -EOPNOTSUPP;
7086
7087 switch (cmd) {
7088 case SIOCGMIIPHY:
7089 data->phy_id = adapter->hw.phy.addr;
7090 break;
7091 case SIOCGMIIREG:
f5f4cf08 7092 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
9005df38 7093 &data->val_out))
9d5c8243
AK		 7094 return -EIO;
7095 break;
7096 case SIOCSMIIREG:
7097 default:
7098 return -EOPNOTSUPP;
7099 }
7100 return 0;
7101}
7102
7103/**
7104 * igb_ioctl -
7105 * @netdev:
7106 * @ifreq:
7107 * @cmd:
7108 **/
7109static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
7110{
7111 switch (cmd) {
7112 case SIOCGMIIPHY:
7113 case SIOCGMIIREG:
7114 case SIOCSMIIREG:
7115 return igb_mii_ioctl(netdev, ifr, cmd);
6ab5f7b2
JK		 7116 case SIOCGHWTSTAMP:
7117 return igb_ptp_get_ts_config(netdev, ifr);
c6cb090b 7118 case SIOCSHWTSTAMP:
6ab5f7b2 7119 return igb_ptp_set_ts_config(netdev, ifr);
9d5c8243
AK		 7120 default:
7121 return -EOPNOTSUPP;
7122 }
7123}
7124
94826487
TF		 7125void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7126{
7127 struct igb_adapter *adapter = hw->back;
7128
7129 pci_read_config_word(adapter->pdev, reg, value);
7130}
7131
7132void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
7133{
7134 struct igb_adapter *adapter = hw->back;
7135
7136 pci_write_config_word(adapter->pdev, reg, *value);
7137}
7138
009bc06e
AD		 7139s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7140{
7141 struct igb_adapter *adapter = hw->back;
009bc06e 7142
23d028cc 7143 if (pcie_capability_read_word(adapter->pdev, reg, value))
009bc06e
AD		 7144 return -E1000_ERR_CONFIG;
7145
009bc06e
AD		 7146 return 0;
7147}
7148
7149s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
7150{
7151 struct igb_adapter *adapter = hw->back;
009bc06e 7152
23d028cc 7153 if (pcie_capability_write_word(adapter->pdev, reg, *value))
009bc06e
AD		 7154 return -E1000_ERR_CONFIG;
7155
009bc06e
AD		 7156 return 0;
7157}
7158
c8f44aff 7159static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
9d5c8243
AK		 7160{
7161 struct igb_adapter *adapter = netdev_priv(netdev);
7162 struct e1000_hw *hw = &adapter->hw;
7163 u32 ctrl, rctl;
f646968f 7164 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
9d5c8243 7165
5faf030c 7166 if (enable) {
9d5c8243
AK		 7167 /* enable VLAN tag insert/strip */
7168 ctrl = rd32(E1000_CTRL);
7169 ctrl |= E1000_CTRL_VME;
7170 wr32(E1000_CTRL, ctrl);
7171
51466239 7172 /* Disable CFI check */
9d5c8243 7173 rctl = rd32(E1000_RCTL);
9d5c8243
AK		 7174 rctl &= ~E1000_RCTL_CFIEN;
7175 wr32(E1000_RCTL, rctl);
9d5c8243
AK		 7176 } else {
7177 /* disable VLAN tag insert/strip */
7178 ctrl = rd32(E1000_CTRL);
7179 ctrl &= ~E1000_CTRL_VME;
7180 wr32(E1000_CTRL, ctrl);
9d5c8243
AK		 7181 }
7182
e1739522 7183 igb_rlpml_set(adapter);
9d5c8243
AK		 7184}
7185
80d5c368
PM		 7186static int igb_vlan_rx_add_vid(struct net_device *netdev,
7187 __be16 proto, u16 vid)
9d5c8243
AK		 7188{
7189 struct igb_adapter *adapter = netdev_priv(netdev);
7190 struct e1000_hw *hw = &adapter->hw;
4ae196df 7191 int pf_id = adapter->vfs_allocated_count;
9d5c8243 7192
51466239
AD		 7193 /* attempt to add filter to vlvf array */
7194 igb_vlvf_set(adapter, vid, true, pf_id);
4ae196df 7195
51466239
AD		 7196 /* add the filter since PF can receive vlans w/o entry in vlvf */
7197 igb_vfta_set(hw, vid, true);
b2cb09b1
JP		 7198
7199 set_bit(vid, adapter->active_vlans);
8e586137
JP		 7200
7201 return 0;
9d5c8243
AK		 7202}
7203
80d5c368
PM		 7204static int igb_vlan_rx_kill_vid(struct net_device *netdev,
7205 __be16 proto, u16 vid)
9d5c8243
AK		 7206{
7207 struct igb_adapter *adapter = netdev_priv(netdev);
7208 struct e1000_hw *hw = &adapter->hw;
4ae196df 7209 int pf_id = adapter->vfs_allocated_count;
51466239 7210 s32 err;
9d5c8243 7211
51466239
AD		 7212 /* remove vlan from VLVF table array */
7213 err = igb_vlvf_set(adapter, vid, false, pf_id);
9d5c8243 7214
51466239
AD		 7215 /* if vid was not present in VLVF just remove it from table */
7216 if (err)
4ae196df 7217 igb_vfta_set(hw, vid, false);
b2cb09b1
JP		 7218
7219 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 7220
7221 return 0;
9d5c8243
AK		 7222}
7223
7224static void igb_restore_vlan(struct igb_adapter *adapter)
7225{
b2cb09b1 7226 u16 vid;
9d5c8243 7227
5faf030c
AD		 7228 igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7229
b2cb09b1 7230 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 7231 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9d5c8243
AK		 7232}
7233
14ad2513 7234int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
9d5c8243 7235{
090b1795 7236 struct pci_dev *pdev = adapter->pdev;
9d5c8243
AK		 7237 struct e1000_mac_info *mac = &adapter->hw.mac;
7238
7239 mac->autoneg = 0;
7240
14ad2513 7241 /* Make sure dplx is at most 1 bit and lsb of speed is not set
b980ac18
JK		 7242 * for the switch() below to work
7243 */
14ad2513
DD		 7244 if ((spd & 1) || (dplx & ~1))
7245 goto err_inval;
7246
f502ef7d
AA		 7247 /* Fiber NIC's only allow 1000 gbps Full duplex
7248 * and 100Mbps Full duplex for 100baseFx sfp
7249 */
7250 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
7251 switch (spd + dplx) {
7252 case SPEED_10 + DUPLEX_HALF:
7253 case SPEED_10 + DUPLEX_FULL:
7254 case SPEED_100 + DUPLEX_HALF:
7255 goto err_inval;
7256 default:
7257 break;
7258 }
7259 }
cd2638a8 7260
14ad2513 7261 switch (spd + dplx) {
9d5c8243
AK		 7262 case SPEED_10 + DUPLEX_HALF:
7263 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7264 break;
7265 case SPEED_10 + DUPLEX_FULL:
7266 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7267 break;
7268 case SPEED_100 + DUPLEX_HALF:
7269 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7270 break;
7271 case SPEED_100 + DUPLEX_FULL:
7272 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7273 break;
7274 case SPEED_1000 + DUPLEX_FULL:
7275 mac->autoneg = 1;
7276 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7277 break;
7278 case SPEED_1000 + DUPLEX_HALF: /* not supported */
7279 default:
14ad2513 7280 goto err_inval;
9d5c8243 7281 }
8376dad0
JB		 7282
7283 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7284 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7285
9d5c8243 7286 return 0;
14ad2513
DD		 7287
7288err_inval:
7289 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7290 return -EINVAL;
9d5c8243
AK		 7291}
7292
749ab2cd
YZ		 7293static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7294 bool runtime)
9d5c8243
AK		 7295{
7296 struct net_device *netdev = pci_get_drvdata(pdev);
7297 struct igb_adapter *adapter = netdev_priv(netdev);
7298 struct e1000_hw *hw = &adapter->hw;
2d064c06 7299 u32 ctrl, rctl, status;
749ab2cd 7300 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
9d5c8243
AK		 7301#ifdef CONFIG_PM
7302 int retval = 0;
7303#endif
7304
7305 netif_device_detach(netdev);
7306
a88f10ec 7307 if (netif_running(netdev))
749ab2cd 7308 __igb_close(netdev, true);
a88f10ec 7309
047e0030 7310 igb_clear_interrupt_scheme(adapter);
9d5c8243
AK		 7311
7312#ifdef CONFIG_PM
7313 retval = pci_save_state(pdev);
7314 if (retval)
7315 return retval;
7316#endif
7317
7318 status = rd32(E1000_STATUS);
7319 if (status & E1000_STATUS_LU)
7320 wufc &= ~E1000_WUFC_LNKC;
7321
7322 if (wufc) {
7323 igb_setup_rctl(adapter);
ff41f8dc 7324 igb_set_rx_mode(netdev);
9d5c8243
AK		 7325
7326 /* turn on all-multi mode if wake on multicast is enabled */
7327 if (wufc & E1000_WUFC_MC) {
7328 rctl = rd32(E1000_RCTL);
7329 rctl |= E1000_RCTL_MPE;
7330 wr32(E1000_RCTL, rctl);
7331 }
7332
7333 ctrl = rd32(E1000_CTRL);
7334 /* advertise wake from D3Cold */
7335 #define E1000_CTRL_ADVD3WUC 0x00100000
7336 /* phy power management enable */
7337 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7338 ctrl |= E1000_CTRL_ADVD3WUC;
7339 wr32(E1000_CTRL, ctrl);
7340
9d5c8243 7341 /* Allow time for pending master requests to run */
330a6d6a 7342 igb_disable_pcie_master(hw);
9d5c8243
AK		 7343
7344 wr32(E1000_WUC, E1000_WUC_PME_EN);
7345 wr32(E1000_WUFC, wufc);
9d5c8243
AK		 7346 } else {
7347 wr32(E1000_WUC, 0);
7348 wr32(E1000_WUFC, 0);
9d5c8243
AK		 7349 }
7350
3fe7c4c9
RW		 7351 *enable_wake = wufc || adapter->en_mng_pt;
7352 if (!*enable_wake)
88a268c1
NN		 7353 igb_power_down_link(adapter);
7354 else
7355 igb_power_up_link(adapter);
9d5c8243
AK		 7356
7357 /* Release control of h/w to f/w. If f/w is AMT enabled, this
b980ac18
JK		 7358 * would have already happened in close and is redundant.
7359 */
9d5c8243
AK		 7360 igb_release_hw_control(adapter);
7361
7362 pci_disable_device(pdev);
7363
9d5c8243
AK		 7364 return 0;
7365}
7366
7367#ifdef CONFIG_PM
d9dd966d 7368#ifdef CONFIG_PM_SLEEP
749ab2cd 7369static int igb_suspend(struct device *dev)
3fe7c4c9
RW		 7370{
7371 int retval;
7372 bool wake;
749ab2cd 7373 struct pci_dev *pdev = to_pci_dev(dev);
3fe7c4c9 7374
749ab2cd 7375 retval = __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7376 if (retval)
7377 return retval;
7378
7379 if (wake) {
7380 pci_prepare_to_sleep(pdev);
7381 } else {
7382 pci_wake_from_d3(pdev, false);
7383 pci_set_power_state(pdev, PCI_D3hot);
7384 }
7385
7386 return 0;
7387}
d9dd966d 7388#endif /* CONFIG_PM_SLEEP */
3fe7c4c9 7389
749ab2cd 7390static int igb_resume(struct device *dev)
9d5c8243 7391{
749ab2cd 7392 struct pci_dev *pdev = to_pci_dev(dev);
9d5c8243
AK		 7393 struct net_device *netdev = pci_get_drvdata(pdev);
7394 struct igb_adapter *adapter = netdev_priv(netdev);
7395 struct e1000_hw *hw = &adapter->hw;
7396 u32 err;
7397
7398 pci_set_power_state(pdev, PCI_D0);
7399 pci_restore_state(pdev);
b94f2d77 7400 pci_save_state(pdev);
42bfd33a 7401
17a402a0
CW		 7402 if (!pci_device_is_present(pdev))
7403 return -ENODEV;
aed5dec3 7404 err = pci_enable_device_mem(pdev);
9d5c8243
AK		 7405 if (err) {
7406 dev_err(&pdev->dev,
7407 "igb: Cannot enable PCI device from suspend\n");
7408 return err;
7409 }
7410 pci_set_master(pdev);
7411
7412 pci_enable_wake(pdev, PCI_D3hot, 0);
7413 pci_enable_wake(pdev, PCI_D3cold, 0);
7414
53c7d064 7415 if (igb_init_interrupt_scheme(adapter, true)) {
a88f10ec
AD		 7416 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7417 return -ENOMEM;
9d5c8243
AK		 7418 }
7419
9d5c8243 7420 igb_reset(adapter);
a8564f03
AD		 7421
7422 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7423 * driver.
7424 */
a8564f03
AD		 7425 igb_get_hw_control(adapter);
7426
9d5c8243
AK		 7427 wr32(E1000_WUS, ~0);
7428
749ab2cd 7429 if (netdev->flags & IFF_UP) {
0c2cc02e 7430 rtnl_lock();
749ab2cd 7431 err = __igb_open(netdev, true);
0c2cc02e 7432 rtnl_unlock();
a88f10ec
AD		 7433 if (err)
7434 return err;
7435 }
9d5c8243
AK		 7436
7437 netif_device_attach(netdev);
749ab2cd
YZ		 7438 return 0;
7439}
7440
7441#ifdef CONFIG_PM_RUNTIME
7442static int igb_runtime_idle(struct device *dev)
7443{
7444 struct pci_dev *pdev = to_pci_dev(dev);
7445 struct net_device *netdev = pci_get_drvdata(pdev);
7446 struct igb_adapter *adapter = netdev_priv(netdev);
7447
7448 if (!igb_has_link(adapter))
7449 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7450
7451 return -EBUSY;
7452}
7453
7454static int igb_runtime_suspend(struct device *dev)
7455{
7456 struct pci_dev *pdev = to_pci_dev(dev);
7457 int retval;
7458 bool wake;
7459
7460 retval = __igb_shutdown(pdev, &wake, 1);
7461 if (retval)
7462 return retval;
7463
7464 if (wake) {
7465 pci_prepare_to_sleep(pdev);
7466 } else {
7467 pci_wake_from_d3(pdev, false);
7468 pci_set_power_state(pdev, PCI_D3hot);
7469 }
9d5c8243 7470
9d5c8243
AK		 7471 return 0;
7472}
749ab2cd
YZ		 7473
7474static int igb_runtime_resume(struct device *dev)
7475{
7476 return igb_resume(dev);
7477}
7478#endif /* CONFIG_PM_RUNTIME */
9d5c8243
AK		 7479#endif
7480
7481static void igb_shutdown(struct pci_dev *pdev)
7482{
3fe7c4c9
RW		 7483 bool wake;
7484
749ab2cd 7485 __igb_shutdown(pdev, &wake, 0);
3fe7c4c9
RW		 7486
7487 if (system_state == SYSTEM_POWER_OFF) {
7488 pci_wake_from_d3(pdev, wake);
7489 pci_set_power_state(pdev, PCI_D3hot);
7490 }
9d5c8243
AK		 7491}
7492
fa44f2f1
GR		 7493#ifdef CONFIG_PCI_IOV
7494static int igb_sriov_reinit(struct pci_dev *dev)
7495{
7496 struct net_device *netdev = pci_get_drvdata(dev);
7497 struct igb_adapter *adapter = netdev_priv(netdev);
7498 struct pci_dev *pdev = adapter->pdev;
7499
7500 rtnl_lock();
7501
7502 if (netif_running(netdev))
7503 igb_close(netdev);
76252723
SA		 7504 else
7505 igb_reset(adapter);
fa44f2f1
GR		 7506
7507 igb_clear_interrupt_scheme(adapter);
7508
7509 igb_init_queue_configuration(adapter);
7510
7511 if (igb_init_interrupt_scheme(adapter, true)) {
7512 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7513 return -ENOMEM;
7514 }
7515
7516 if (netif_running(netdev))
7517 igb_open(netdev);
7518
7519 rtnl_unlock();
7520
7521 return 0;
7522}
7523
7524static int igb_pci_disable_sriov(struct pci_dev *dev)
7525{
7526 int err = igb_disable_sriov(dev);
7527
7528 if (!err)
7529 err = igb_sriov_reinit(dev);
7530
7531 return err;
7532}
7533
7534static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7535{
7536 int err = igb_enable_sriov(dev, num_vfs);
7537
7538 if (err)
7539 goto out;
7540
7541 err = igb_sriov_reinit(dev);
7542 if (!err)
7543 return num_vfs;
7544
7545out:
7546 return err;
7547}
7548
7549#endif
7550static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7551{
7552#ifdef CONFIG_PCI_IOV
7553 if (num_vfs == 0)
7554 return igb_pci_disable_sriov(dev);
7555 else
7556 return igb_pci_enable_sriov(dev, num_vfs);
7557#endif
7558 return 0;
7559}
7560
9d5c8243 7561#ifdef CONFIG_NET_POLL_CONTROLLER
b980ac18 7562/* Polling 'interrupt' - used by things like netconsole to send skbs
9d5c8243
AK		 7563 * without having to re-enable interrupts. It's not called while
7564 * the interrupt routine is executing.
7565 */
7566static void igb_netpoll(struct net_device *netdev)
7567{
7568 struct igb_adapter *adapter = netdev_priv(netdev);
eebbbdba 7569 struct e1000_hw *hw = &adapter->hw;
0d1ae7f4 7570 struct igb_q_vector *q_vector;
9d5c8243 7571 int i;
9d5c8243 7572
047e0030 7573 for (i = 0; i < adapter->num_q_vectors; i++) {
0d1ae7f4 7574 q_vector = adapter->q_vector[i];
cd14ef54 7575 if (adapter->flags & IGB_FLAG_HAS_MSIX)
0d1ae7f4
AD		 7576 wr32(E1000_EIMC, q_vector->eims_value);
7577 else
7578 igb_irq_disable(adapter);
047e0030 7579 napi_schedule(&q_vector->napi);
eebbbdba 7580 }
9d5c8243
AK		 7581}
7582#endif /* CONFIG_NET_POLL_CONTROLLER */
7583
7584/**
b980ac18
JK		 7585 * igb_io_error_detected - called when PCI error is detected
7586 * @pdev: Pointer to PCI device
7587 * @state: The current pci connection state
9d5c8243 7588 *
b980ac18
JK		 7589 * This function is called after a PCI bus error affecting
7590 * this device has been detected.
7591 **/
9d5c8243
AK		 7592static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7593 pci_channel_state_t state)
7594{
7595 struct net_device *netdev = pci_get_drvdata(pdev);
7596 struct igb_adapter *adapter = netdev_priv(netdev);
7597
7598 netif_device_detach(netdev);
7599
59ed6eec
AD		 7600 if (state == pci_channel_io_perm_failure)
7601 return PCI_ERS_RESULT_DISCONNECT;
7602
9d5c8243
AK		 7603 if (netif_running(netdev))
7604 igb_down(adapter);
7605 pci_disable_device(pdev);
7606
7607 /* Request a slot slot reset. */
7608 return PCI_ERS_RESULT_NEED_RESET;
7609}
7610
7611/**
b980ac18
JK		 7612 * igb_io_slot_reset - called after the pci bus has been reset.
7613 * @pdev: Pointer to PCI device
9d5c8243 7614 *
b980ac18
JK		 7615 * Restart the card from scratch, as if from a cold-boot. Implementation
7616 * resembles the first-half of the igb_resume routine.
7617 **/
9d5c8243
AK		 7618static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7619{
7620 struct net_device *netdev = pci_get_drvdata(pdev);
7621 struct igb_adapter *adapter = netdev_priv(netdev);
7622 struct e1000_hw *hw = &adapter->hw;
40a914fa 7623 pci_ers_result_t result;
42bfd33a 7624 int err;
9d5c8243 7625
aed5dec3 7626 if (pci_enable_device_mem(pdev)) {
9d5c8243
AK		 7627 dev_err(&pdev->dev,
7628 "Cannot re-enable PCI device after reset.\n");
40a914fa
AD		 7629 result = PCI_ERS_RESULT_DISCONNECT;
7630 } else {
7631 pci_set_master(pdev);
7632 pci_restore_state(pdev);
b94f2d77 7633 pci_save_state(pdev);
9d5c8243 7634
40a914fa
AD		 7635 pci_enable_wake(pdev, PCI_D3hot, 0);
7636 pci_enable_wake(pdev, PCI_D3cold, 0);
9d5c8243 7637
40a914fa
AD		 7638 igb_reset(adapter);
7639 wr32(E1000_WUS, ~0);
7640 result = PCI_ERS_RESULT_RECOVERED;
7641 }
9d5c8243 7642
ea943d41
JK		 7643 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7644 if (err) {
b980ac18
JK		 7645 dev_err(&pdev->dev,
7646 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7647 err);
ea943d41
JK		 7648 /* non-fatal, continue */
7649 }
40a914fa
AD		 7650
7651 return result;
9d5c8243
AK		 7652}
7653
7654/**
b980ac18
JK		 7655 * igb_io_resume - called when traffic can start flowing again.
7656 * @pdev: Pointer to PCI device
9d5c8243 7657 *
b980ac18
JK		 7658 * This callback is called when the error recovery driver tells us that
7659 * its OK to resume normal operation. Implementation resembles the
7660 * second-half of the igb_resume routine.
9d5c8243
AK		 7661 */
7662static void igb_io_resume(struct pci_dev *pdev)
7663{
7664 struct net_device *netdev = pci_get_drvdata(pdev);
7665 struct igb_adapter *adapter = netdev_priv(netdev);
7666
9d5c8243
AK		 7667 if (netif_running(netdev)) {
7668 if (igb_up(adapter)) {
7669 dev_err(&pdev->dev, "igb_up failed after reset\n");
7670 return;
7671 }
7672 }
7673
7674 netif_device_attach(netdev);
7675
7676 /* let the f/w know that the h/w is now under the control of the
b980ac18
JK		 7677 * driver.
7678 */
9d5c8243 7679 igb_get_hw_control(adapter);
9d5c8243
AK		 7680}
7681
26ad9178 7682static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
b980ac18 7683 u8 qsel)
26ad9178
AD		 7684{
7685 u32 rar_low, rar_high;
7686 struct e1000_hw *hw = &adapter->hw;
7687
7688 /* HW expects these in little endian so we reverse the byte order
7689 * from network order (big endian) to little endian
7690 */
7691 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
b980ac18 7692 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
26ad9178
AD		 7693 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7694
7695 /* Indicate to hardware the Address is Valid. */
7696 rar_high |= E1000_RAH_AV;
7697
7698 if (hw->mac.type == e1000_82575)
7699 rar_high |= E1000_RAH_POOL_1 * qsel;
7700 else
7701 rar_high |= E1000_RAH_POOL_1 << qsel;
7702
7703 wr32(E1000_RAL(index), rar_low);
7704 wrfl();
7705 wr32(E1000_RAH(index), rar_high);
7706 wrfl();
7707}
7708
4ae196df 7709static int igb_set_vf_mac(struct igb_adapter *adapter,
b980ac18 7710 int vf, unsigned char *mac_addr)
4ae196df
AD		 7711{
7712 struct e1000_hw *hw = &adapter->hw;
ff41f8dc 7713 /* VF MAC addresses start at end of receive addresses and moves
b980ac18
JK		 7714 * towards the first, as a result a collision should not be possible
7715 */
ff41f8dc 7716 int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4ae196df 7717
37680117 7718 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
4ae196df 7719
26ad9178 7720 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
4ae196df
AD		 7721
7722 return 0;
7723}
7724
8151d294
WM		 7725static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7726{
7727 struct igb_adapter *adapter = netdev_priv(netdev);
7728 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7729 return -EINVAL;
7730 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7731 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
b980ac18
JK		 7732 dev_info(&adapter->pdev->dev,
7733 "Reload the VF driver to make this change effective.");
8151d294 7734 if (test_bit(__IGB_DOWN, &adapter->state)) {
b980ac18
JK		 7735 dev_warn(&adapter->pdev->dev,
7736 "The VF MAC address has been set, but the PF device is not up.\n");
7737 dev_warn(&adapter->pdev->dev,
7738 "Bring the PF device up before attempting to use the VF device.\n");
8151d294
WM		 7739 }
7740 return igb_set_vf_mac(adapter, vf, mac);
7741}
7742
17dc566c
LL		 7743static int igb_link_mbps(int internal_link_speed)
7744{
7745 switch (internal_link_speed) {
7746 case SPEED_100:
7747 return 100;
7748 case SPEED_1000:
7749 return 1000;
7750 default:
7751 return 0;
7752 }
7753}
7754
7755static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7756 int link_speed)
7757{
7758 int rf_dec, rf_int;
7759 u32 bcnrc_val;
7760
7761 if (tx_rate != 0) {
7762 /* Calculate the rate factor values to set */
7763 rf_int = link_speed / tx_rate;
7764 rf_dec = (link_speed - (rf_int * tx_rate));
b980ac18
JK		 7765 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) /
7766 tx_rate;
17dc566c
LL		 7767
7768 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
b980ac18
JK		 7769 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
7770 E1000_RTTBCNRC_RF_INT_MASK);
17dc566c
LL		 7771 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7772 } else {
7773 bcnrc_val = 0;
7774 }
7775
7776 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
b980ac18 7777 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
f00b0da7
LL		 7778 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7779 */
7780 wr32(E1000_RTTBCNRM, 0x14);
17dc566c
LL		 7781 wr32(E1000_RTTBCNRC, bcnrc_val);
7782}
7783
7784static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7785{
7786 int actual_link_speed, i;
7787 bool reset_rate = false;
7788
7789 /* VF TX rate limit was not set or not supported */
7790 if ((adapter->vf_rate_link_speed == 0) ||
7791 (adapter->hw.mac.type != e1000_82576))
7792 return;
7793
7794 actual_link_speed = igb_link_mbps(adapter->link_speed);
7795 if (actual_link_speed != adapter->vf_rate_link_speed) {
7796 reset_rate = true;
7797 adapter->vf_rate_link_speed = 0;
7798 dev_info(&adapter->pdev->dev,
b980ac18 7799 "Link speed has been changed. VF Transmit rate is disabled\n");
17dc566c
LL		 7800 }
7801
7802 for (i = 0; i < adapter->vfs_allocated_count; i++) {
7803 if (reset_rate)
7804 adapter->vf_data[i].tx_rate = 0;
7805
7806 igb_set_vf_rate_limit(&adapter->hw, i,
b980ac18
JK		 7807 adapter->vf_data[i].tx_rate,
7808 actual_link_speed);
17dc566c
LL		 7809 }
7810}
7811
ed616689
SC		 7812static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
7813 int min_tx_rate, int max_tx_rate)
8151d294 7814{
17dc566c
LL		 7815 struct igb_adapter *adapter = netdev_priv(netdev);
7816 struct e1000_hw *hw = &adapter->hw;
7817 int actual_link_speed;
7818
7819 if (hw->mac.type != e1000_82576)
7820 return -EOPNOTSUPP;
7821
ed616689
SC		 7822 if (min_tx_rate)
7823 return -EINVAL;
7824
17dc566c
LL		 7825 actual_link_speed = igb_link_mbps(adapter->link_speed);
7826 if ((vf >= adapter->vfs_allocated_count) ||
7827 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
ed616689
SC		 7828 (max_tx_rate < 0) ||
7829 (max_tx_rate > actual_link_speed))
17dc566c
LL		 7830 return -EINVAL;
7831
7832 adapter->vf_rate_link_speed = actual_link_speed;
ed616689
SC		 7833 adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
7834 igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
17dc566c
LL		 7835
7836 return 0;
8151d294
WM		 7837}
7838
70ea4783
LL		 7839static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
7840 bool setting)
7841{
7842 struct igb_adapter *adapter = netdev_priv(netdev);
7843 struct e1000_hw *hw = &adapter->hw;
7844 u32 reg_val, reg_offset;
7845
7846 if (!adapter->vfs_allocated_count)
7847 return -EOPNOTSUPP;
7848
7849 if (vf >= adapter->vfs_allocated_count)
7850 return -EINVAL;
7851
7852 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
7853 reg_val = rd32(reg_offset);
7854 if (setting)
7855 reg_val |= ((1 << vf) |
7856 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7857 else
7858 reg_val &= ~((1 << vf) |
7859 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT)));
7860 wr32(reg_offset, reg_val);
7861
7862 adapter->vf_data[vf].spoofchk_enabled = setting;
23d87824 7863 return 0;
70ea4783
LL		 7864}
7865
8151d294
WM		 7866static int igb_ndo_get_vf_config(struct net_device *netdev,
7867 int vf, struct ifla_vf_info *ivi)
7868{
7869 struct igb_adapter *adapter = netdev_priv(netdev);
7870 if (vf >= adapter->vfs_allocated_count)
7871 return -EINVAL;
7872 ivi->vf = vf;
7873 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
ed616689
SC		 7874 ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
7875 ivi->min_tx_rate = 0;
8151d294
WM		 7876 ivi->vlan = adapter->vf_data[vf].pf_vlan;
7877 ivi->qos = adapter->vf_data[vf].pf_qos;
70ea4783 7878 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
8151d294
WM		 7879 return 0;
7880}
7881
4ae196df
AD		 7882static void igb_vmm_control(struct igb_adapter *adapter)
7883{
7884 struct e1000_hw *hw = &adapter->hw;
10d8e907 7885 u32 reg;
4ae196df 7886
52a1dd4d
AD		 7887 switch (hw->mac.type) {
7888 case e1000_82575:
f96a8a0b
CW		 7889 case e1000_i210:
7890 case e1000_i211:
ceb5f13b 7891 case e1000_i354:
52a1dd4d
AD		 7892 default:
7893 /* replication is not supported for 82575 */
4ae196df 7894 return;
52a1dd4d
AD		 7895 case e1000_82576:
7896 /* notify HW that the MAC is adding vlan tags */
7897 reg = rd32(E1000_DTXCTL);
7898 reg |= E1000_DTXCTL_VLAN_ADDED;
7899 wr32(E1000_DTXCTL, reg);
b26141d4 7900 /* Fall through */
52a1dd4d
AD		 7901 case e1000_82580:
7902 /* enable replication vlan tag stripping */
7903 reg = rd32(E1000_RPLOLR);
7904 reg |= E1000_RPLOLR_STRVLAN;
7905 wr32(E1000_RPLOLR, reg);
b26141d4 7906 /* Fall through */
d2ba2ed8
AD		 7907 case e1000_i350:
7908 /* none of the above registers are supported by i350 */
52a1dd4d
AD		 7909 break;
7910 }
10d8e907 7911
d4960307
AD		 7912 if (adapter->vfs_allocated_count) {
7913 igb_vmdq_set_loopback_pf(hw, true);
7914 igb_vmdq_set_replication_pf(hw, true);
13800469 7915 igb_vmdq_set_anti_spoofing_pf(hw, true,
b980ac18 7916 adapter->vfs_allocated_count);
d4960307
AD		 7917 } else {
7918 igb_vmdq_set_loopback_pf(hw, false);
7919 igb_vmdq_set_replication_pf(hw, false);
7920 }
4ae196df
AD		 7921}
7922
b6e0c419
CW		 7923static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7924{
7925 struct e1000_hw *hw = &adapter->hw;
7926 u32 dmac_thr;
7927 u16 hwm;
7928
7929 if (hw->mac.type > e1000_82580) {
7930 if (adapter->flags & IGB_FLAG_DMAC) {
7931 u32 reg;
7932
7933 /* force threshold to 0. */
7934 wr32(E1000_DMCTXTH, 0);
7935
b980ac18 7936 /* DMA Coalescing high water mark needs to be greater
e8c626e9
MV		 7937 * than the Rx threshold. Set hwm to PBA - max frame
7938 * size in 16B units, capping it at PBA - 6KB.
b6e0c419 7939 */
e8c626e9
MV		 7940 hwm = 64 * pba - adapter->max_frame_size / 16;
7941 if (hwm < 64 * (pba - 6))
7942 hwm = 64 * (pba - 6);
7943 reg = rd32(E1000_FCRTC);
7944 reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7945 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7946 & E1000_FCRTC_RTH_COAL_MASK);
7947 wr32(E1000_FCRTC, reg);
7948
b980ac18 7949 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
e8c626e9
MV		 7950 * frame size, capping it at PBA - 10KB.
7951 */
7952 dmac_thr = pba - adapter->max_frame_size / 512;
7953 if (dmac_thr < pba - 10)
7954 dmac_thr = pba - 10;
b6e0c419
CW		 7955 reg = rd32(E1000_DMACR);
7956 reg &= ~E1000_DMACR_DMACTHR_MASK;
b6e0c419
CW		 7957 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7958 & E1000_DMACR_DMACTHR_MASK);
7959
7960 /* transition to L0x or L1 if available..*/
7961 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7962
7963 /* watchdog timer= +-1000 usec in 32usec intervals */
7964 reg |= (1000 >> 5);
0c02dd98
MV		 7965
7966 /* Disable BMC-to-OS Watchdog Enable */
ceb5f13b
CW		 7967 if (hw->mac.type != e1000_i354)
7968 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7969
b6e0c419
CW		 7970 wr32(E1000_DMACR, reg);
7971
b980ac18 7972 /* no lower threshold to disable
b6e0c419
CW		 7973 * coalescing(smart fifb)-UTRESH=0
7974 */
7975 wr32(E1000_DMCRTRH, 0);
b6e0c419
CW		 7976
7977 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7978
7979 wr32(E1000_DMCTLX, reg);
7980
b980ac18 7981 /* free space in tx packet buffer to wake from
b6e0c419
CW		 7982 * DMA coal
7983 */
7984 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7985 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7986
b980ac18 7987 /* make low power state decision controlled
b6e0c419
CW		 7988 * by DMA coal
7989 */
7990 reg = rd32(E1000_PCIEMISC);
7991 reg &= ~E1000_PCIEMISC_LX_DECISION;
7992 wr32(E1000_PCIEMISC, reg);
7993 } /* endif adapter->dmac is not disabled */
7994 } else if (hw->mac.type == e1000_82580) {
7995 u32 reg = rd32(E1000_PCIEMISC);
9005df38 7996
b6e0c419
CW		 7997 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7998 wr32(E1000_DMACR, 0);
7999 }
8000}
8001
b980ac18
JK		 8002/**
8003 * igb_read_i2c_byte - Reads 8 bit word over I2C
441fc6fd
CW		 8004 * @hw: pointer to hardware structure
8005 * @byte_offset: byte offset to read
8006 * @dev_addr: device address
8007 * @data: value read
8008 *
8009 * Performs byte read operation over I2C interface at
8010 * a specified device address.
b980ac18 8011 **/
441fc6fd 8012s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8013 u8 dev_addr, u8 *data)
441fc6fd
CW		 8014{
8015 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8016 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8017 s32 status;
8018 u16 swfw_mask = 0;
8019
8020 if (!this_client)
8021 return E1000_ERR_I2C;
8022
8023 swfw_mask = E1000_SWFW_PHY0_SM;
8024
23d87824 8025 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8026 return E1000_ERR_SWFW_SYNC;
8027
8028 status = i2c_smbus_read_byte_data(this_client, byte_offset);
8029 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8030
8031 if (status < 0)
8032 return E1000_ERR_I2C;
8033 else {
8034 *data = status;
23d87824 8035 return 0;
441fc6fd
CW		 8036 }
8037}
8038
b980ac18
JK		 8039/**
8040 * igb_write_i2c_byte - Writes 8 bit word over I2C
441fc6fd
CW		 8041 * @hw: pointer to hardware structure
8042 * @byte_offset: byte offset to write
8043 * @dev_addr: device address
8044 * @data: value to write
8045 *
8046 * Performs byte write operation over I2C interface at
8047 * a specified device address.
b980ac18 8048 **/
441fc6fd 8049s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
b980ac18 8050 u8 dev_addr, u8 data)
441fc6fd
CW		 8051{
8052 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
603e86fa 8053 struct i2c_client *this_client = adapter->i2c_client;
441fc6fd
CW		 8054 s32 status;
8055 u16 swfw_mask = E1000_SWFW_PHY0_SM;
8056
8057 if (!this_client)
8058 return E1000_ERR_I2C;
8059
23d87824 8060 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
441fc6fd
CW		 8061 return E1000_ERR_SWFW_SYNC;
8062 status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
8063 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
8064
8065 if (status)
8066 return E1000_ERR_I2C;
8067 else
23d87824 8068 return 0;
441fc6fd
CW		 8069
8070}
907b7835
LMV		 8071
8072int igb_reinit_queues(struct igb_adapter *adapter)
8073{
8074 struct net_device *netdev = adapter->netdev;
8075 struct pci_dev *pdev = adapter->pdev;
8076 int err = 0;
8077
8078 if (netif_running(netdev))
8079 igb_close(netdev);
8080
02ef6e1d 8081 igb_reset_interrupt_capability(adapter);
907b7835
LMV		 8082
8083 if (igb_init_interrupt_scheme(adapter, true)) {
8084 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8085 return -ENOMEM;
8086 }
8087
8088 if (netif_running(netdev))
8089 err = igb_open(netdev);
8090
8091 return err;
8092}
9d5c8243 8093/* igb_main.c */
Linux kernel - Deliverables
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