[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_ptp.c

/*
 * PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
 *
 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */
#include <linux/module.h>
#include <linux/device.h>
#include <linux/pci.h>

#include "igb.h"

#define INCVALUE_MASK		0x7fffffff
#define ISGN			0x80000000

/*
 * Neither the 82576 nor the 82580 offer registers wide enough to hold
 * nanoseconds time values for very long. For the 82580, SYSTIM always
 * counts nanoseconds, but the upper 24 bits are not availible. The
 * frequency is adjusted by changing the 32 bit fractional nanoseconds
 * register, TIMINCA.
 *
 * For the 82576, the SYSTIM register time unit is affect by the
 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
 * field are needed to provide the nominal 16 nanosecond period,
 * leaving 19 bits for fractional nanoseconds.
 *
 *
 *             SYSTIMH            SYSTIML
 *        +--------------+   +---+---+------+
 *  82576 |      32      |   | 8 | 5 |  19  |
 *        +--------------+   +---+---+------+
 *         \________ 45 bits _______/  fract
 *
 *        +----------+---+   +--------------+
 *  82580 |    24    | 8 |   |      32      |
 *        +----------+---+   +--------------+
 *          reserved  \______ 40 bits _____/
 *
 *
 * The 45 bit 82576 SYSTIM overflows every
 *   2^45 * 10^-9 / 3600 = 9.77 hours.
 *
 * The 40 bit 82580 SYSTIM overflows every
 *   2^40 * 10^-9 /  60  = 18.3 minutes.
 */

#define IGB_OVERFLOW_PERIOD	(HZ * 60 * 9)
#define INCPERIOD_82576		(1 << E1000_TIMINCA_16NS_SHIFT)
#define INCVALUE_82576_MASK	((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
#define INCVALUE_82576		(16 << IGB_82576_TSYNC_SHIFT)
#define IGB_NBITS_82580		40

/*
 * SYSTIM read access for the 82576
 */

static cycle_t igb_82576_systim_read(const struct cyclecounter *cc)
{
	u64 val;
	u32 lo, hi;
	struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
	struct e1000_hw *hw = &igb->hw;

	lo = rd32(E1000_SYSTIML);
	hi = rd32(E1000_SYSTIMH);

	val = ((u64) hi) << 32;
	val |= lo;

	return val;
}

/*
 * SYSTIM read access for the 82580
 */

static cycle_t igb_82580_systim_read(const struct cyclecounter *cc)
{
	u64 val;
	u32 lo, hi, jk;
	struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
	struct e1000_hw *hw = &igb->hw;

	jk = rd32(E1000_SYSTIMR);
	lo = rd32(E1000_SYSTIML);
	hi = rd32(E1000_SYSTIMH);

	val = ((u64) hi) << 32;
	val |= lo;

	return val;
}

/*
 * PTP clock operations
 */

static int ptp_82576_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
	u64 rate;
	u32 incvalue;
	int neg_adj = 0;
	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
	struct e1000_hw *hw = &igb->hw;

	if (ppb < 0) {
		neg_adj = 1;
		ppb = -ppb;
	}
	rate = ppb;
	rate <<= 14;
	rate = div_u64(rate, 1953125);

	incvalue = 16 << IGB_82576_TSYNC_SHIFT;

	if (neg_adj)
		incvalue -= rate;
	else
		incvalue += rate;

	wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));

	return 0;
}

static int ptp_82580_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
{
	u64 rate;
	u32 inca;
	int neg_adj = 0;
	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
	struct e1000_hw *hw = &igb->hw;

	if (ppb < 0) {
		neg_adj = 1;
		ppb = -ppb;
	}
	rate = ppb;
	rate <<= 26;
	rate = div_u64(rate, 1953125);

	inca = rate & INCVALUE_MASK;
	if (neg_adj)
		inca |= ISGN;

	wr32(E1000_TIMINCA, inca);

	return 0;
}

static int igb_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
	s64 now;
	unsigned long flags;
	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);

	spin_lock_irqsave(&igb->tmreg_lock, flags);

	now = timecounter_read(&igb->tc);
	now += delta;
	timecounter_init(&igb->tc, &igb->cc, now);

	spin_unlock_irqrestore(&igb->tmreg_lock, flags);

	return 0;
}

static int igb_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
{
	u64 ns;
	u32 remainder;
	unsigned long flags;
	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);

	spin_lock_irqsave(&igb->tmreg_lock, flags);

	ns = timecounter_read(&igb->tc);

	spin_unlock_irqrestore(&igb->tmreg_lock, flags);

	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
	ts->tv_nsec = remainder;

	return 0;
}

static int igb_settime(struct ptp_clock_info *ptp, const struct timespec *ts)
{
	u64 ns;
	unsigned long flags;
	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);

	ns = ts->tv_sec * 1000000000ULL;
	ns += ts->tv_nsec;

	spin_lock_irqsave(&igb->tmreg_lock, flags);

	timecounter_init(&igb->tc, &igb->cc, ns);

	spin_unlock_irqrestore(&igb->tmreg_lock, flags);

	return 0;
}

static int ptp_82576_enable(struct ptp_clock_info *ptp,
			    struct ptp_clock_request *rq, int on)
{
	return -EOPNOTSUPP;
}

static int ptp_82580_enable(struct ptp_clock_info *ptp,
			    struct ptp_clock_request *rq, int on)
{
	return -EOPNOTSUPP;
}

static void igb_overflow_check(struct work_struct *work)
{
	struct timespec ts;
	struct igb_adapter *igb =
		container_of(work, struct igb_adapter, overflow_work.work);

	igb_gettime(&igb->caps, &ts);

	pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);

	schedule_delayed_work(&igb->overflow_work, IGB_OVERFLOW_PERIOD);
}

void igb_ptp_init(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;

	switch (hw->mac.type) {
	case e1000_i350:
	case e1000_82580:
		adapter->caps.owner	= THIS_MODULE;
		strcpy(adapter->caps.name, "igb-82580");
		adapter->caps.max_adj	= 62499999;
		adapter->caps.n_ext_ts	= 0;
		adapter->caps.pps	= 0;
		adapter->caps.adjfreq	= ptp_82580_adjfreq;
		adapter->caps.adjtime	= igb_adjtime;
		adapter->caps.gettime	= igb_gettime;
		adapter->caps.settime	= igb_settime;
		adapter->caps.enable	= ptp_82580_enable;
		adapter->cc.read	= igb_82580_systim_read;
		adapter->cc.mask	= CLOCKSOURCE_MASK(IGB_NBITS_82580);
		adapter->cc.mult	= 1;
		adapter->cc.shift	= 0;
		/* Enable the timer functions by clearing bit 31. */
		wr32(E1000_TSAUXC, 0x0);
		break;

	case e1000_82576:
		adapter->caps.owner	= THIS_MODULE;
		strcpy(adapter->caps.name, "igb-82576");
		adapter->caps.max_adj	= 1000000000;
		adapter->caps.n_ext_ts	= 0;
		adapter->caps.pps	= 0;
		adapter->caps.adjfreq	= ptp_82576_adjfreq;
		adapter->caps.adjtime	= igb_adjtime;
		adapter->caps.gettime	= igb_gettime;
		adapter->caps.settime	= igb_settime;
		adapter->caps.enable	= ptp_82576_enable;
		adapter->cc.read	= igb_82576_systim_read;
		adapter->cc.mask	= CLOCKSOURCE_MASK(64);
		adapter->cc.mult	= 1;
		adapter->cc.shift	= IGB_82576_TSYNC_SHIFT;
		/* Dial the nominal frequency. */
		wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
		break;

	default:
		adapter->ptp_clock = NULL;
		return;
	}

	wrfl();

	timecounter_init(&adapter->tc, &adapter->cc,
			 ktime_to_ns(ktime_get_real()));

	INIT_DELAYED_WORK(&adapter->overflow_work, igb_overflow_check);

	spin_lock_init(&adapter->tmreg_lock);

	schedule_delayed_work(&adapter->overflow_work, IGB_OVERFLOW_PERIOD);

	adapter->ptp_clock = ptp_clock_register(&adapter->caps);
	if (IS_ERR(adapter->ptp_clock)) {
		adapter->ptp_clock = NULL;
		dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
	} else
		dev_info(&adapter->pdev->dev, "added PHC on %s\n",
			 adapter->netdev->name);
}

void igb_ptp_remove(struct igb_adapter *adapter)
{
	cancel_delayed_work_sync(&adapter->overflow_work);

	if (adapter->ptp_clock) {
		ptp_clock_unregister(adapter->ptp_clock);
		dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
			 adapter->netdev->name);
	}
}
Commit	Line	Data
d339b133 RC	1	/*
	2	* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
	3	*
	4	* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20	#include <linux/module.h>
	21	#include <linux/device.h>
	22	#include <linux/pci.h>
	23
	24	#include "igb.h"
	25
	26	#define INCVALUE_MASK 0x7fffffff
	27	#define ISGN 0x80000000
	28
	29	/*
	30	* Neither the 82576 nor the 82580 offer registers wide enough to hold
	31	* nanoseconds time values for very long. For the 82580, SYSTIM always
	32	* counts nanoseconds, but the upper 24 bits are not availible. The
	33	* frequency is adjusted by changing the 32 bit fractional nanoseconds
	34	* register, TIMINCA.
	35	*
	36	* For the 82576, the SYSTIM register time unit is affect by the
	37	* choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
	38	* field are needed to provide the nominal 16 nanosecond period,
	39	* leaving 19 bits for fractional nanoseconds.
	40	*
	41	*
	42	* SYSTIMH SYSTIML
	43	* +--------------+ +---+---+------+
	44	* 82576 \| 32 \| \| 8 \| 5 \| 19 \|
	45	* +--------------+ +---+---+------+
	46	* \________ 45 bits _______/ fract
	47	*
	48	* +----------+---+ +--------------+
	49	* 82580 \| 24 \| 8 \| \| 32 \|
	50	* +----------+---+ +--------------+
	51	* reserved \______ 40 bits _____/
	52	*
	53	*
	54	* The 45 bit 82576 SYSTIM overflows every
	55	* 2^45 * 10^-9 / 3600 = 9.77 hours.
	56	*
	57	* The 40 bit 82580 SYSTIM overflows every
	58	* 2^40 * 10^-9 / 60 = 18.3 minutes.
	59	*/
	60
	61	#define IGB_OVERFLOW_PERIOD (HZ * 60 * 9)
	62	#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
	63	#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
	64	#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
65	#define IGB_NBITS_82580 40
66
67	/*
68	* SYSTIM read access for the 82576
69	*/
70
71	static cycle_t igb_82576_systim_read(const struct cyclecounter *cc)
72	{
73	u64 val;
74	u32 lo, hi;
75	struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
76	struct e1000_hw *hw = &igb->hw;
77
78	lo = rd32(E1000_SYSTIML);
79	hi = rd32(E1000_SYSTIMH);
80
81	val = ((u64) hi) << 32;
82	val \|= lo;
83
84	return val;
85	}
86
87	/*
88	* SYSTIM read access for the 82580
89	*/
90
91	static cycle_t igb_82580_systim_read(const struct cyclecounter *cc)
92	{
93	u64 val;
94	u32 lo, hi, jk;
95	struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
96	struct e1000_hw *hw = &igb->hw;
97
98	jk = rd32(E1000_SYSTIMR);
99	lo = rd32(E1000_SYSTIML);
100	hi = rd32(E1000_SYSTIMH);
101
102	val = ((u64) hi) << 32;
103	val \|= lo;
104
105	return val;
106	}
107
108	/*
109	* PTP clock operations
110	*/
111
112	static int ptp_82576_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
113	{
114	u64 rate;
115	u32 incvalue;
116	int neg_adj = 0;
117	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
118	struct e1000_hw *hw = &igb->hw;
119
120	if (ppb < 0) {
121	neg_adj = 1;
122	ppb = -ppb;
123	}
124	rate = ppb;
125	rate <<= 14;
126	rate = div_u64(rate, 1953125);
127
128	incvalue = 16 << IGB_82576_TSYNC_SHIFT;
129
130	if (neg_adj)
131	incvalue -= rate;
132	else
133	incvalue += rate;
134
135	wr32(E1000_TIMINCA, INCPERIOD_82576 \| (incvalue & INCVALUE_82576_MASK));
136
137	return 0;
138	}
139
140	static int ptp_82580_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
141	{
142	u64 rate;
143	u32 inca;
144	int neg_adj = 0;
145	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
146	struct e1000_hw *hw = &igb->hw;
147
148	if (ppb < 0) {
149	neg_adj = 1;
150	ppb = -ppb;
151	}
152	rate = ppb;
153	rate <<= 26;
154	rate = div_u64(rate, 1953125);
155
156	inca = rate & INCVALUE_MASK;
157	if (neg_adj)
158	inca \|= ISGN;
159
160	wr32(E1000_TIMINCA, inca);
161
162	return 0;
163	}
164
165	static int igb_adjtime(struct ptp_clock_info *ptp, s64 delta)
166	{
167	s64 now;
168	unsigned long flags;
169	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
170
171	spin_lock_irqsave(&igb->tmreg_lock, flags);
172
173	now = timecounter_read(&igb->tc);
174	now += delta;
175	timecounter_init(&igb->tc, &igb->cc, now);
176
177	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
178
179	return 0;
180	}
181
182	static int igb_gettime(struct ptp_clock_info ptp, struct timespec ts)
183	{
184	u64 ns;
185	u32 remainder;
186	unsigned long flags;
187	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
188
189	spin_lock_irqsave(&igb->tmreg_lock, flags);
190
191	ns = timecounter_read(&igb->tc);
192
193	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
194
195	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
196	ts->tv_nsec = remainder;
197
198	return 0;
199	}
200
201	static int igb_settime(struct ptp_clock_info ptp, const struct timespec ts)
202	{
203	u64 ns;
204	unsigned long flags;
205	struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
206
207	ns = ts->tv_sec * 1000000000ULL;
208	ns += ts->tv_nsec;
209
210	spin_lock_irqsave(&igb->tmreg_lock, flags);
211
212	timecounter_init(&igb->tc, &igb->cc, ns);
213
214	spin_unlock_irqrestore(&igb->tmreg_lock, flags);
215
216	return 0;
217	}
218
219	static int ptp_82576_enable(struct ptp_clock_info *ptp,
220	struct ptp_clock_request *rq, int on)
221	{
222	return -EOPNOTSUPP;
223	}
224
225	static int ptp_82580_enable(struct ptp_clock_info *ptp,
226	struct ptp_clock_request *rq, int on)
227	{
228	return -EOPNOTSUPP;
229	}
230
231	static void igb_overflow_check(struct work_struct *work)
232	{
233	struct timespec ts;
234	struct igb_adapter *igb =
235	container_of(work, struct igb_adapter, overflow_work.work);
236
237	igb_gettime(&igb->caps, &ts);
238
239	pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
240
241	schedule_delayed_work(&igb->overflow_work, IGB_OVERFLOW_PERIOD);
242	}
243
244	void igb_ptp_init(struct igb_adapter *adapter)
245	{
246	struct e1000_hw *hw = &adapter->hw;
247
248	switch (hw->mac.type) {
249	case e1000_i350:
250	case e1000_82580:
251	adapter->caps.owner = THIS_MODULE;
252	strcpy(adapter->caps.name, "igb-82580");
253	adapter->caps.max_adj = 62499999;
254	adapter->caps.n_ext_ts = 0;
255	adapter->caps.pps = 0;
256	adapter->caps.adjfreq = ptp_82580_adjfreq;
257	adapter->caps.adjtime = igb_adjtime;
258	adapter->caps.gettime = igb_gettime;
259	adapter->caps.settime = igb_settime;
260	adapter->caps.enable = ptp_82580_enable;
261	adapter->cc.read = igb_82580_systim_read;
262	adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);
263	adapter->cc.mult = 1;
264	adapter->cc.shift = 0;
265	/* Enable the timer functions by clearing bit 31. */
266	wr32(E1000_TSAUXC, 0x0);
267	break;
268
269	case e1000_82576:
270	adapter->caps.owner = THIS_MODULE;
271	strcpy(adapter->caps.name, "igb-82576");
272	adapter->caps.max_adj = 1000000000;
273	adapter->caps.n_ext_ts = 0;
274	adapter->caps.pps = 0;
275	adapter->caps.adjfreq = ptp_82576_adjfreq;
276	adapter->caps.adjtime = igb_adjtime;
277	adapter->caps.gettime = igb_gettime;
278	adapter->caps.settime = igb_settime;
279	adapter->caps.enable = ptp_82576_enable;
280	adapter->cc.read = igb_82576_systim_read;
281	adapter->cc.mask = CLOCKSOURCE_MASK(64);
282	adapter->cc.mult = 1;
283	adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
284	/* Dial the nominal frequency. */
285	wr32(E1000_TIMINCA, INCPERIOD_82576 \| INCVALUE_82576);
286	break;
287
288	default:
289	adapter->ptp_clock = NULL;
290	return;
291	}
292
293	wrfl();
294
295	timecounter_init(&adapter->tc, &adapter->cc,
296	ktime_to_ns(ktime_get_real()));
297
298	INIT_DELAYED_WORK(&adapter->overflow_work, igb_overflow_check);
299
300	spin_lock_init(&adapter->tmreg_lock);
301
302	schedule_delayed_work(&adapter->overflow_work, IGB_OVERFLOW_PERIOD);
303
304	adapter->ptp_clock = ptp_clock_register(&adapter->caps);
305	if (IS_ERR(adapter->ptp_clock)) {
306	adapter->ptp_clock = NULL;
307	dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
308	} else
309	dev_info(&adapter->pdev->dev, "added PHC on %s\n",
310	adapter->netdev->name);
311	}
312
313	void igb_ptp_remove(struct igb_adapter *adapter)
314	{
315	cancel_delayed_work_sync(&adapter->overflow_work);
316
317	if (adapter->ptp_clock) {
318	ptp_clock_unregister(adapter->ptp_clock);
319	dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
320	adapter->netdev->name);
321	}
322	}