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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #ifndef _IXGBE_H_ | |
29 | #define _IXGBE_H_ | |
30 | ||
f62bbb5e | 31 | #include <linux/bitops.h> |
9a799d71 AK |
32 | #include <linux/types.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/netdevice.h> | |
b25ebfd2 | 35 | #include <linux/cpumask.h> |
6fabd715 | 36 | #include <linux/aer.h> |
f62bbb5e | 37 | #include <linux/if_vlan.h> |
9a799d71 AK |
38 | |
39 | #include "ixgbe_type.h" | |
40 | #include "ixgbe_common.h" | |
2f90b865 | 41 | #include "ixgbe_dcb.h" |
eacd73f7 YZ |
42 | #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) |
43 | #define IXGBE_FCOE | |
44 | #include "ixgbe_fcoe.h" | |
45 | #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */ | |
5dd2d332 | 46 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
47 | #include <linux/dca.h> |
48 | #endif | |
9a799d71 | 49 | |
849c4542 ET |
50 | /* common prefix used by pr_<> macros */ |
51 | #undef pr_fmt | |
52 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
9a799d71 AK |
53 | |
54 | /* TX/RX descriptor defines */ | |
6bacb300 | 55 | #define IXGBE_DEFAULT_TXD 512 |
59224555 | 56 | #define IXGBE_DEFAULT_TX_WORK 256 |
9a799d71 AK |
57 | #define IXGBE_MAX_TXD 4096 |
58 | #define IXGBE_MIN_TXD 64 | |
59 | ||
6bacb300 | 60 | #define IXGBE_DEFAULT_RXD 512 |
9a799d71 AK |
61 | #define IXGBE_MAX_RXD 4096 |
62 | #define IXGBE_MIN_RXD 64 | |
63 | ||
9a799d71 | 64 | /* flow control */ |
2b9ade93 | 65 | #define IXGBE_MIN_FCRTL 0x40 |
9a799d71 | 66 | #define IXGBE_MAX_FCRTL 0x7FF80 |
2b9ade93 | 67 | #define IXGBE_MIN_FCRTH 0x600 |
9a799d71 | 68 | #define IXGBE_MAX_FCRTH 0x7FFF0 |
2b9ade93 | 69 | #define IXGBE_DEFAULT_FCPAUSE 0xFFFF |
9a799d71 AK |
70 | #define IXGBE_MIN_FCPAUSE 0 |
71 | #define IXGBE_MAX_FCPAUSE 0xFFFF | |
72 | ||
73 | /* Supported Rx Buffer Sizes */ | |
13958070 | 74 | #define IXGBE_RXBUFFER_512 512 /* Used for packet split */ |
919e78a6 | 75 | #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */ |
9a799d71 | 76 | |
13958070 AD |
77 | /* |
78 | * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we | |
79 | * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, | |
80 | * this adds up to 512 bytes of extra data meaning the smallest allocation | |
81 | * we could have is 1K. | |
82 | * i.e. RXBUFFER_512 --> size-1024 slab | |
83 | */ | |
84 | #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512 | |
9a799d71 AK |
85 | |
86 | #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) | |
87 | ||
9a799d71 AK |
88 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ |
89 | #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */ | |
90 | ||
91 | #define IXGBE_TX_FLAGS_CSUM (u32)(1) | |
66f32a8b AD |
92 | #define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1) |
93 | #define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2) | |
94 | #define IXGBE_TX_FLAGS_TSO (u32)(1 << 3) | |
95 | #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4) | |
96 | #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5) | |
97 | #define IXGBE_TX_FLAGS_FSO (u32)(1 << 6) | |
7f9643fd | 98 | #define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7) |
9a799d71 | 99 | #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 |
66f32a8b AD |
100 | #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 |
101 | #define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
9a799d71 AK |
102 | #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 |
103 | ||
0a924578 PWJ |
104 | #define IXGBE_MAX_RSC_INT_RATE 162760 |
105 | ||
7f870475 GR |
106 | #define IXGBE_MAX_VF_MC_ENTRIES 30 |
107 | #define IXGBE_MAX_VF_FUNCTIONS 64 | |
108 | #define IXGBE_MAX_VFTA_ENTRIES 128 | |
109 | #define MAX_EMULATION_MAC_ADDRS 16 | |
a1cbb15c | 110 | #define IXGBE_MAX_PF_MACVLANS 15 |
7f870475 | 111 | #define VMDQ_P(p) ((p) + adapter->num_vfs) |
83c61fa9 GR |
112 | #define IXGBE_82599_VF_DEVICE_ID 0x10ED |
113 | #define IXGBE_X540_VF_DEVICE_ID 0x1515 | |
7f870475 GR |
114 | |
115 | struct vf_data_storage { | |
116 | unsigned char vf_mac_addresses[ETH_ALEN]; | |
117 | u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES]; | |
118 | u16 num_vf_mc_hashes; | |
119 | u16 default_vf_vlan_id; | |
120 | u16 vlans_enabled; | |
7f870475 | 121 | bool clear_to_send; |
7f01648a | 122 | bool pf_set_mac; |
7f01648a GR |
123 | u16 pf_vlan; /* When set, guest VLAN config not allowed. */ |
124 | u16 pf_qos; | |
ff4ab206 | 125 | u16 tx_rate; |
de4c7f65 GR |
126 | u16 vlan_count; |
127 | u8 spoofchk_enabled; | |
c6bda30a | 128 | struct pci_dev *vfdev; |
7f870475 GR |
129 | }; |
130 | ||
a1cbb15c GR |
131 | struct vf_macvlans { |
132 | struct list_head l; | |
133 | int vf; | |
134 | int rar_entry; | |
135 | bool free; | |
136 | bool is_macvlan; | |
137 | u8 vf_macvlan[ETH_ALEN]; | |
138 | }; | |
139 | ||
a535c30e AD |
140 | #define IXGBE_MAX_TXD_PWR 14 |
141 | #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR) | |
142 | ||
143 | /* Tx Descriptors needed, worst case */ | |
144 | #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) | |
145 | #define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4) | |
146 | ||
9a799d71 AK |
147 | /* wrapper around a pointer to a socket buffer, |
148 | * so a DMA handle can be stored along with the buffer */ | |
149 | struct ixgbe_tx_buffer { | |
d3d00239 | 150 | union ixgbe_adv_tx_desc *next_to_watch; |
9a799d71 | 151 | unsigned long time_stamp; |
fd0db0ed AD |
152 | struct sk_buff *skb; |
153 | unsigned int bytecount; | |
154 | unsigned short gso_segs; | |
244e27ad | 155 | __be16 protocol; |
729739b7 AD |
156 | DEFINE_DMA_UNMAP_ADDR(dma); |
157 | DEFINE_DMA_UNMAP_LEN(len); | |
d3d00239 | 158 | u32 tx_flags; |
9a799d71 AK |
159 | }; |
160 | ||
161 | struct ixgbe_rx_buffer { | |
162 | struct sk_buff *skb; | |
163 | dma_addr_t dma; | |
164 | struct page *page; | |
762f4c57 | 165 | unsigned int page_offset; |
9a799d71 AK |
166 | }; |
167 | ||
168 | struct ixgbe_queue_stats { | |
169 | u64 packets; | |
170 | u64 bytes; | |
171 | }; | |
172 | ||
5b7da515 AD |
173 | struct ixgbe_tx_queue_stats { |
174 | u64 restart_queue; | |
175 | u64 tx_busy; | |
c84d324c | 176 | u64 tx_done_old; |
5b7da515 AD |
177 | }; |
178 | ||
179 | struct ixgbe_rx_queue_stats { | |
180 | u64 rsc_count; | |
181 | u64 rsc_flush; | |
182 | u64 non_eop_descs; | |
183 | u64 alloc_rx_page_failed; | |
184 | u64 alloc_rx_buff_failed; | |
8a0da21b | 185 | u64 csum_err; |
5b7da515 AD |
186 | }; |
187 | ||
f800326d | 188 | enum ixgbe_ring_state_t { |
7d637bcc AD |
189 | __IXGBE_TX_FDIR_INIT_DONE, |
190 | __IXGBE_TX_DETECT_HANG, | |
c84d324c | 191 | __IXGBE_HANG_CHECK_ARMED, |
7d637bcc | 192 | __IXGBE_RX_RSC_ENABLED, |
8a0da21b | 193 | __IXGBE_RX_CSUM_UDP_ZERO_ERR, |
f800326d | 194 | __IXGBE_RX_FCOE_BUFSZ, |
7d637bcc AD |
195 | }; |
196 | ||
7d637bcc AD |
197 | #define check_for_tx_hang(ring) \ |
198 | test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
199 | #define set_check_for_tx_hang(ring) \ | |
200 | set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
201 | #define clear_check_for_tx_hang(ring) \ | |
202 | clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state) | |
203 | #define ring_is_rsc_enabled(ring) \ | |
204 | test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
205 | #define set_ring_rsc_enabled(ring) \ | |
206 | set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
207 | #define clear_ring_rsc_enabled(ring) \ | |
208 | clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state) | |
9a799d71 | 209 | struct ixgbe_ring { |
efe3d3c8 | 210 | struct ixgbe_ring *next; /* pointer to next ring in q_vector */ |
9a799d71 | 211 | void *desc; /* descriptor ring memory */ |
b6ec895e | 212 | struct device *dev; /* device for DMA mapping */ |
fc77dc3c | 213 | struct net_device *netdev; /* netdev ring belongs to */ |
9a799d71 AK |
214 | union { |
215 | struct ixgbe_tx_buffer *tx_buffer_info; | |
216 | struct ixgbe_rx_buffer *rx_buffer_info; | |
217 | }; | |
7d637bcc | 218 | unsigned long state; |
bd198058 AD |
219 | u8 __iomem *tail; |
220 | ||
ae540af1 | 221 | u16 count; /* amount of descriptors */ |
ae540af1 JB |
222 | |
223 | u8 queue_index; /* needed for multiqueue queue management */ | |
7d637bcc AD |
224 | u8 reg_idx; /* holds the special value that gets |
225 | * the hardware register offset | |
226 | * associated with this ring, which is | |
227 | * different for DCB and RSS modes | |
228 | */ | |
f800326d AD |
229 | union { |
230 | struct { | |
231 | u8 atr_sample_rate; | |
232 | u8 atr_count; | |
233 | }; | |
234 | u16 next_to_alloc; | |
235 | }; | |
9a799d71 | 236 | |
bd198058 AD |
237 | u16 next_to_use; |
238 | u16 next_to_clean; | |
9a799d71 | 239 | |
bd198058 | 240 | u8 dcb_tc; |
9a799d71 | 241 | struct ixgbe_queue_stats stats; |
de1036b1 | 242 | struct u64_stats_sync syncp; |
5b7da515 AD |
243 | union { |
244 | struct ixgbe_tx_queue_stats tx_stats; | |
245 | struct ixgbe_rx_queue_stats rx_stats; | |
246 | }; | |
ae540af1 JB |
247 | unsigned int size; /* length in bytes */ |
248 | dma_addr_t dma; /* phys. address of descriptor ring */ | |
33cf09c9 | 249 | struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */ |
7ca3bc58 | 250 | } ____cacheline_internodealigned_in_smp; |
9a799d71 | 251 | |
c7e4358a SN |
252 | enum ixgbe_ring_f_enum { |
253 | RING_F_NONE = 0, | |
7f870475 | 254 | RING_F_VMDQ, /* SR-IOV uses the same ring feature */ |
c7e4358a | 255 | RING_F_RSS, |
c4cf55e5 | 256 | RING_F_FDIR, |
0331a832 YZ |
257 | #ifdef IXGBE_FCOE |
258 | RING_F_FCOE, | |
259 | #endif /* IXGBE_FCOE */ | |
c7e4358a SN |
260 | |
261 | RING_F_ARRAY_SIZE /* must be last in enum set */ | |
262 | }; | |
263 | ||
021230d4 | 264 | #define IXGBE_MAX_RSS_INDICES 16 |
7f870475 | 265 | #define IXGBE_MAX_VMDQ_INDICES 64 |
c4cf55e5 | 266 | #define IXGBE_MAX_FDIR_INDICES 64 |
0331a832 YZ |
267 | #ifdef IXGBE_FCOE |
268 | #define IXGBE_MAX_FCOE_INDICES 8 | |
e0fce695 JF |
269 | #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) |
270 | #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES) | |
271 | #else | |
272 | #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES | |
273 | #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES | |
0331a832 | 274 | #endif /* IXGBE_FCOE */ |
021230d4 AV |
275 | struct ixgbe_ring_feature { |
276 | int indices; | |
277 | int mask; | |
7ca3bc58 | 278 | } ____cacheline_internodealigned_in_smp; |
021230d4 | 279 | |
f800326d AD |
280 | /* |
281 | * FCoE requires that all Rx buffers be over 2200 bytes in length. Since | |
282 | * this is twice the size of a half page we need to double the page order | |
283 | * for FCoE enabled Rx queues. | |
284 | */ | |
285 | #if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192) | |
286 | static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring) | |
287 | { | |
288 | return test_bit(__IXGBE_RX_FCOE_BUFSZ, &ring->state) ? 1 : 0; | |
289 | } | |
290 | #else | |
291 | #define ixgbe_rx_pg_order(_ring) 0 | |
292 | #endif | |
293 | #define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring)) | |
294 | #define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring)) | |
295 | ||
08c8833b | 296 | struct ixgbe_ring_container { |
efe3d3c8 | 297 | struct ixgbe_ring *ring; /* pointer to linked list of rings */ |
bd198058 AD |
298 | unsigned int total_bytes; /* total bytes processed this int */ |
299 | unsigned int total_packets; /* total packets processed this int */ | |
300 | u16 work_limit; /* total work allowed per interrupt */ | |
08c8833b AD |
301 | u8 count; /* total number of rings in vector */ |
302 | u8 itr; /* current ITR setting for ring */ | |
303 | }; | |
021230d4 | 304 | |
a557928e AD |
305 | /* iterator for handling rings in ring container */ |
306 | #define ixgbe_for_each_ring(pos, head) \ | |
307 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
308 | ||
2f90b865 AD |
309 | #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ |
310 | ? 8 : 1) | |
311 | #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS | |
312 | ||
021230d4 AV |
313 | /* MAX_MSIX_Q_VECTORS of these are allocated, |
314 | * but we only use one per queue-specific vector. | |
315 | */ | |
316 | struct ixgbe_q_vector { | |
317 | struct ixgbe_adapter *adapter; | |
33cf09c9 AD |
318 | #ifdef CONFIG_IXGBE_DCA |
319 | int cpu; /* CPU for DCA */ | |
320 | #endif | |
d5bf4f67 ET |
321 | u16 v_idx; /* index of q_vector within array, also used for |
322 | * finding the bit in EICR and friends that | |
323 | * represents the vector for this ring */ | |
324 | u16 itr; /* Interrupt throttle rate written to EITR */ | |
08c8833b | 325 | struct ixgbe_ring_container rx, tx; |
d5bf4f67 ET |
326 | |
327 | struct napi_struct napi; | |
de88eeeb AD |
328 | cpumask_t affinity_mask; |
329 | int numa_node; | |
330 | struct rcu_head rcu; /* to avoid race with update stats on free */ | |
d0759ebb | 331 | char name[IFNAMSIZ + 9]; |
de88eeeb AD |
332 | |
333 | /* for dynamic allocation of rings associated with this q_vector */ | |
334 | struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp; | |
021230d4 AV |
335 | }; |
336 | ||
d5bf4f67 ET |
337 | /* |
338 | * microsecond values for various ITR rates shifted by 2 to fit itr register | |
339 | * with the first 3 bits reserved 0 | |
9a799d71 | 340 | */ |
d5bf4f67 ET |
341 | #define IXGBE_MIN_RSC_ITR 24 |
342 | #define IXGBE_100K_ITR 40 | |
343 | #define IXGBE_20K_ITR 200 | |
344 | #define IXGBE_10K_ITR 400 | |
345 | #define IXGBE_8K_ITR 500 | |
9a799d71 | 346 | |
f56e0cb1 AD |
347 | /* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */ |
348 | static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc, | |
349 | const u32 stat_err_bits) | |
350 | { | |
351 | return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); | |
352 | } | |
353 | ||
7d4987de AD |
354 | static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring) |
355 | { | |
356 | u16 ntc = ring->next_to_clean; | |
357 | u16 ntu = ring->next_to_use; | |
358 | ||
359 | return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; | |
360 | } | |
9a799d71 | 361 | |
e4f74028 | 362 | #define IXGBE_RX_DESC(R, i) \ |
31f05a2d | 363 | (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) |
e4f74028 | 364 | #define IXGBE_TX_DESC(R, i) \ |
31f05a2d | 365 | (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) |
e4f74028 | 366 | #define IXGBE_TX_CTXTDESC(R, i) \ |
31f05a2d | 367 | (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) |
9a799d71 AK |
368 | |
369 | #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128 | |
63f39bd1 YZ |
370 | #ifdef IXGBE_FCOE |
371 | /* Use 3K as the baby jumbo frame size for FCoE */ | |
372 | #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072 | |
373 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 374 | |
021230d4 AV |
375 | #define OTHER_VECTOR 1 |
376 | #define NON_Q_VECTORS (OTHER_VECTOR) | |
377 | ||
e8e26350 PW |
378 | #define MAX_MSIX_VECTORS_82599 64 |
379 | #define MAX_MSIX_Q_VECTORS_82599 64 | |
eb7f139c PWJ |
380 | #define MAX_MSIX_VECTORS_82598 18 |
381 | #define MAX_MSIX_Q_VECTORS_82598 16 | |
382 | ||
e8e26350 PW |
383 | #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599 |
384 | #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599 | |
eb7f139c | 385 | |
8f15486d | 386 | #define MIN_MSIX_Q_VECTORS 1 |
021230d4 AV |
387 | #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) |
388 | ||
46646e61 AD |
389 | /* default to trying for four seconds */ |
390 | #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ) | |
391 | ||
9a799d71 AK |
392 | /* board specific private data structure */ |
393 | struct ixgbe_adapter { | |
46646e61 AD |
394 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
395 | /* OS defined structs */ | |
396 | struct net_device *netdev; | |
397 | struct pci_dev *pdev; | |
398 | ||
e606bfe7 AD |
399 | unsigned long state; |
400 | ||
401 | /* Some features need tri-state capability, | |
402 | * thus the additional *_CAPABLE flags. | |
403 | */ | |
404 | u32 flags; | |
e606bfe7 AD |
405 | #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1) |
406 | #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2) | |
407 | #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3) | |
408 | #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4) | |
409 | #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6) | |
410 | #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7) | |
411 | #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8) | |
412 | #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9) | |
413 | #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10) | |
414 | #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11) | |
415 | #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12) | |
416 | #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13) | |
417 | #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14) | |
418 | #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16) | |
419 | #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17) | |
420 | #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18) | |
421 | #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19) | |
422 | #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20) | |
423 | #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22) | |
7086400d AD |
424 | #define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23) |
425 | #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24) | |
426 | #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25) | |
427 | #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26) | |
428 | #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27) | |
429 | #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28) | |
430 | #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29) | |
e606bfe7 AD |
431 | |
432 | u32 flags2; | |
433 | #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1) | |
434 | #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1) | |
435 | #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2) | |
f0f9778d | 436 | #define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3) |
7086400d AD |
437 | #define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4) |
438 | #define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5) | |
c83c6cbd | 439 | #define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6) |
d034acf1 | 440 | #define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7) |
e606bfe7 | 441 | |
d033d526 | 442 | |
46646e61 AD |
443 | /* Tx fast path data */ |
444 | int num_tx_queues; | |
445 | u16 tx_itr_setting; | |
bd198058 AD |
446 | u16 tx_work_limit; |
447 | ||
46646e61 AD |
448 | /* Rx fast path data */ |
449 | int num_rx_queues; | |
450 | u16 rx_itr_setting; | |
451 | ||
9a799d71 | 452 | /* TX */ |
4a0b9ca0 | 453 | struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp; |
9a799d71 | 454 | |
7ca3bc58 JB |
455 | u64 restart_queue; |
456 | u64 lsc_int; | |
46646e61 | 457 | u32 tx_timeout_count; |
7ca3bc58 | 458 | |
9a799d71 | 459 | /* RX */ |
46646e61 | 460 | struct ixgbe_ring *rx_ring[MAX_RX_QUEUES]; |
7f870475 GR |
461 | int num_rx_pools; /* == num_rx_queues in 82598 */ |
462 | int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */ | |
9a799d71 | 463 | u64 hw_csum_rx_error; |
e8e26350 | 464 | u64 hw_rx_no_dma_resources; |
46646e61 AD |
465 | u64 rsc_total_count; |
466 | u64 rsc_total_flush; | |
9a799d71 | 467 | u64 non_eop_descs; |
9a799d71 AK |
468 | u32 alloc_rx_page_failed; |
469 | u32 alloc_rx_buff_failed; | |
470 | ||
46646e61 | 471 | struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; |
9a799d71 | 472 | |
46646e61 AD |
473 | /* DCB parameters */ |
474 | struct ieee_pfc *ixgbe_ieee_pfc; | |
475 | struct ieee_ets *ixgbe_ieee_ets; | |
476 | struct ixgbe_dcb_config dcb_cfg; | |
477 | struct ixgbe_dcb_config temp_dcb_cfg; | |
478 | u8 dcb_set_bitmap; | |
479 | u8 dcbx_cap; | |
480 | enum ixgbe_fc_mode last_lfc_mode; | |
481 | ||
482 | int num_msix_vectors; | |
483 | int max_msix_q_vectors; /* true count of q_vectors for device */ | |
484 | struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE]; | |
485 | struct msix_entry *msix_entries; | |
9a799d71 | 486 | |
da4dd0f7 PWJ |
487 | u32 test_icr; |
488 | struct ixgbe_ring test_tx_ring; | |
489 | struct ixgbe_ring test_rx_ring; | |
490 | ||
9a799d71 AK |
491 | /* structs defined in ixgbe_hw.h */ |
492 | struct ixgbe_hw hw; | |
493 | u16 msg_enable; | |
494 | struct ixgbe_hw_stats stats; | |
021230d4 | 495 | |
9a799d71 | 496 | u64 tx_busy; |
30efa5a3 JB |
497 | unsigned int tx_ring_count; |
498 | unsigned int rx_ring_count; | |
cf8280ee JB |
499 | |
500 | u32 link_speed; | |
501 | bool link_up; | |
502 | unsigned long link_check_timeout; | |
503 | ||
7086400d | 504 | struct timer_list service_timer; |
46646e61 AD |
505 | struct work_struct service_task; |
506 | ||
507 | struct hlist_head fdir_filter_list; | |
508 | unsigned long fdir_overflow; /* number of times ATR was backed off */ | |
509 | union ixgbe_atr_input fdir_mask; | |
510 | int fdir_filter_count; | |
c4cf55e5 PWJ |
511 | u32 fdir_pballoc; |
512 | u32 atr_sample_rate; | |
513 | spinlock_t fdir_perfect_lock; | |
46646e61 | 514 | |
d0ed8937 YZ |
515 | #ifdef IXGBE_FCOE |
516 | struct ixgbe_fcoe fcoe; | |
517 | #endif /* IXGBE_FCOE */ | |
e8e26350 | 518 | u32 wol; |
46646e61 | 519 | |
46646e61 AD |
520 | u16 bd_number; |
521 | ||
15e5209f ET |
522 | u16 eeprom_verh; |
523 | u16 eeprom_verl; | |
c23f5b6b | 524 | u16 eeprom_cap; |
7f870475 | 525 | |
119fc60a | 526 | u32 interrupt_event; |
46646e61 | 527 | u32 led_reg; |
1a6c14a2 | 528 | |
7f870475 GR |
529 | /* SR-IOV */ |
530 | DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS); | |
531 | unsigned int num_vfs; | |
532 | struct vf_data_storage *vfinfo; | |
ff4ab206 | 533 | int vf_rate_link_speed; |
a1cbb15c GR |
534 | struct vf_macvlans vf_mvs; |
535 | struct vf_macvlans *mv_list; | |
3e05334f | 536 | |
83c61fa9 GR |
537 | u32 timer_event_accumulator; |
538 | u32 vferr_refcount; | |
3e05334f AD |
539 | }; |
540 | ||
541 | struct ixgbe_fdir_filter { | |
542 | struct hlist_node fdir_node; | |
543 | union ixgbe_atr_input filter; | |
544 | u16 sw_idx; | |
545 | u16 action; | |
9a799d71 AK |
546 | }; |
547 | ||
548 | enum ixbge_state_t { | |
549 | __IXGBE_TESTING, | |
550 | __IXGBE_RESETTING, | |
c4900be0 | 551 | __IXGBE_DOWN, |
7086400d AD |
552 | __IXGBE_SERVICE_SCHED, |
553 | __IXGBE_IN_SFP_INIT, | |
9a799d71 AK |
554 | }; |
555 | ||
4c1975d7 AD |
556 | struct ixgbe_cb { |
557 | union { /* Union defining head/tail partner */ | |
558 | struct sk_buff *head; | |
559 | struct sk_buff *tail; | |
560 | }; | |
aa80175a | 561 | dma_addr_t dma; |
4c1975d7 | 562 | u16 append_cnt; |
f800326d | 563 | bool page_released; |
aa80175a | 564 | }; |
4c1975d7 | 565 | #define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb) |
aa80175a | 566 | |
9a799d71 | 567 | enum ixgbe_boards { |
3957d63d | 568 | board_82598, |
e8e26350 | 569 | board_82599, |
fe15e8e1 | 570 | board_X540, |
9a799d71 AK |
571 | }; |
572 | ||
3957d63d | 573 | extern struct ixgbe_info ixgbe_82598_info; |
e8e26350 | 574 | extern struct ixgbe_info ixgbe_82599_info; |
fe15e8e1 | 575 | extern struct ixgbe_info ixgbe_X540_info; |
7a6b6f51 | 576 | #ifdef CONFIG_IXGBE_DCB |
32953543 | 577 | extern const struct dcbnl_rtnl_ops dcbnl_ops; |
2f90b865 AD |
578 | extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg, |
579 | struct ixgbe_dcb_config *dst_dcb_cfg, | |
580 | int tc_max); | |
581 | #endif | |
9a799d71 AK |
582 | |
583 | extern char ixgbe_driver_name[]; | |
9c8eb720 | 584 | extern const char ixgbe_driver_version[]; |
ea81875a | 585 | extern char ixgbe_default_device_descr[]; |
9a799d71 | 586 | |
c7ccde0f | 587 | extern void ixgbe_up(struct ixgbe_adapter *adapter); |
9a799d71 | 588 | extern void ixgbe_down(struct ixgbe_adapter *adapter); |
d4f80882 | 589 | extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter); |
9a799d71 | 590 | extern void ixgbe_reset(struct ixgbe_adapter *adapter); |
9a799d71 | 591 | extern void ixgbe_set_ethtool_ops(struct net_device *netdev); |
b6ec895e AD |
592 | extern int ixgbe_setup_rx_resources(struct ixgbe_ring *); |
593 | extern int ixgbe_setup_tx_resources(struct ixgbe_ring *); | |
594 | extern void ixgbe_free_rx_resources(struct ixgbe_ring *); | |
595 | extern void ixgbe_free_tx_resources(struct ixgbe_ring *); | |
84418e3b AD |
596 | extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); |
597 | extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *); | |
2d39d576 YZ |
598 | extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
599 | struct ixgbe_ring *); | |
b4617240 | 600 | extern void ixgbe_update_stats(struct ixgbe_adapter *adapter); |
2f90b865 | 601 | extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter); |
7a921c93 | 602 | extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter); |
84418e3b | 603 | extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *, |
84418e3b AD |
604 | struct ixgbe_adapter *, |
605 | struct ixgbe_ring *); | |
b6ec895e | 606 | extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *, |
84418e3b | 607 | struct ixgbe_tx_buffer *); |
fc77dc3c | 608 | extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16); |
fe49f04a AD |
609 | extern void ixgbe_write_eitr(struct ixgbe_q_vector *); |
610 | extern int ethtool_ioctl(struct ifreq *ifr); | |
ffff4772 | 611 | extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw); |
c04f6ca8 AD |
612 | extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl); |
613 | extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl); | |
ffff4772 | 614 | extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, |
69830529 AD |
615 | union ixgbe_atr_hash_dword input, |
616 | union ixgbe_atr_hash_dword common, | |
ffff4772 | 617 | u8 queue); |
c04f6ca8 AD |
618 | extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, |
619 | union ixgbe_atr_input *input_mask); | |
620 | extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, | |
621 | union ixgbe_atr_input *input, | |
622 | u16 soft_id, u8 queue); | |
623 | extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, | |
624 | union ixgbe_atr_input *input, | |
625 | u16 soft_id); | |
626 | extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input, | |
627 | union ixgbe_atr_input *mask); | |
7f870475 | 628 | extern void ixgbe_set_rx_mode(struct net_device *netdev); |
e5b64635 | 629 | extern int ixgbe_setup_tc(struct net_device *dev, u8 tc); |
897ab156 | 630 | extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32); |
082757af | 631 | extern void ixgbe_do_reset(struct net_device *netdev); |
eacd73f7 YZ |
632 | #ifdef IXGBE_FCOE |
633 | extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter); | |
fd0db0ed AD |
634 | extern int ixgbe_fso(struct ixgbe_ring *tx_ring, |
635 | struct ixgbe_tx_buffer *first, | |
244e27ad | 636 | u8 *hdr_len); |
332d4a7d YZ |
637 | extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter); |
638 | extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter, | |
ff886dfc | 639 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 640 | struct sk_buff *skb); |
332d4a7d YZ |
641 | extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid, |
642 | struct scatterlist *sgl, unsigned int sgc); | |
68a683cf YZ |
643 | extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid, |
644 | struct scatterlist *sgl, unsigned int sgc); | |
332d4a7d | 645 | extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid); |
8450ff8c YZ |
646 | extern int ixgbe_fcoe_enable(struct net_device *netdev); |
647 | extern int ixgbe_fcoe_disable(struct net_device *netdev); | |
6ee16520 YZ |
648 | #ifdef CONFIG_IXGBE_DCB |
649 | extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter); | |
650 | extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up); | |
651 | #endif /* CONFIG_IXGBE_DCB */ | |
61a1fa10 | 652 | extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); |
ea81875a NP |
653 | extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev, |
654 | struct netdev_fcoe_hbainfo *info); | |
eacd73f7 | 655 | #endif /* IXGBE_FCOE */ |
9a799d71 | 656 | |
b2d96e0a AD |
657 | static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring) |
658 | { | |
659 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
660 | } | |
661 | ||
9a799d71 | 662 | #endif /* _IXGBE_H_ */ |