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ixgbe: drop adapter from ixgbe_fso call documentation
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71
AK		 38
39#include "ixgbe_type.h"
40#include "ixgbe_common.h"
2f90b865 41#include "ixgbe_dcb.h"
eacd73f7
YZ		 42#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43#define IXGBE_FCOE
44#include "ixgbe_fcoe.h"
45#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 46#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 47#include <linux/dca.h>
48#endif
9a799d71 49
849c4542
ET		 50/* common prefix used by pr_<> macros */
51#undef pr_fmt
52#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 53
54/* TX/RX descriptor defines */
6bacb300 55#define IXGBE_DEFAULT_TXD 512
59224555 56#define IXGBE_DEFAULT_TX_WORK 256
9a799d71
AK		 57#define IXGBE_MAX_TXD 4096
58#define IXGBE_MIN_TXD 64
59
6bacb300 60#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 61#define IXGBE_MAX_RXD 4096
62#define IXGBE_MIN_RXD 64
63
9a799d71 64/* flow control */
2b9ade93 65#define IXGBE_MIN_FCRTL 0x40
9a799d71 66#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 67#define IXGBE_MIN_FCRTH 0x600
9a799d71 68#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 69#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 70#define IXGBE_MIN_FCPAUSE 0
71#define IXGBE_MAX_FCPAUSE 0xFFFF
72
73/* Supported Rx Buffer Sizes */
13958070 74#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71 75#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 76#define IXGBE_RXBUFFER_4096 4096
77#define IXGBE_RXBUFFER_8192 8192
32344a39 78#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 79
13958070
AD		 80/*
81 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
82 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
83 * this adds up to 512 bytes of extra data meaning the smallest allocation
84 * we could have is 1K.
85 * i.e. RXBUFFER_512 --> size-1024 slab
86 */
87#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 88
89#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
90
9a799d71
AK		 91/* How many Rx Buffers do we bundle into one write to the hardware ? */
92#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
93
94#define IXGBE_TX_FLAGS_CSUM (u32)(1)
66f32a8b
AD		 95#define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
96#define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
97#define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
98#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
99#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
100#define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
7f9643fd
AD		 101#define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
102#define IXGBE_TX_FLAGS_MAPPED_AS_PAGE (u32)(1 << 8)
9a799d71 103#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
66f32a8b
AD		 104#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
105#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
9a799d71
AK		 106#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
107
0a924578
PWJ		 108#define IXGBE_MAX_RSC_INT_RATE 162760
109
7f870475
GR		 110#define IXGBE_MAX_VF_MC_ENTRIES 30
111#define IXGBE_MAX_VF_FUNCTIONS 64
112#define IXGBE_MAX_VFTA_ENTRIES 128
113#define MAX_EMULATION_MAC_ADDRS 16
a1cbb15c 114#define IXGBE_MAX_PF_MACVLANS 15
7f870475
GR		 115#define VMDQ_P(p) ((p) + adapter->num_vfs)
116
117struct vf_data_storage {
118 unsigned char vf_mac_addresses[ETH_ALEN];
119 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
120 u16 num_vf_mc_hashes;
121 u16 default_vf_vlan_id;
122 u16 vlans_enabled;
7f870475 123 bool clear_to_send;
7f01648a 124 bool pf_set_mac;
7f01648a
GR		 125 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
126 u16 pf_qos;
ff4ab206 127 u16 tx_rate;
7f870475
GR		 128};
129
a1cbb15c
GR		 130struct vf_macvlans {
131 struct list_head l;
132 int vf;
133 int rar_entry;
134 bool free;
135 bool is_macvlan;
136 u8 vf_macvlan[ETH_ALEN];
137};
138
a535c30e
AD		 139#define IXGBE_MAX_TXD_PWR 14
140#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
141
142/* Tx Descriptors needed, worst case */
143#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
144#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
145
9a799d71
AK		 146/* wrapper around a pointer to a socket buffer,
147 * so a DMA handle can be stored along with the buffer */
148struct ixgbe_tx_buffer {
d3d00239 149 union ixgbe_adv_tx_desc *next_to_watch;
9a799d71 150 unsigned long time_stamp;
d3d00239
AD		 151 dma_addr_t dma;
152 u32 length;
153 u32 tx_flags;
154 struct sk_buff *skb;
155 u32 bytecount;
8ad494b0 156 u16 gso_segs;
9a799d71
AK		 157};
158
159struct ixgbe_rx_buffer {
160 struct sk_buff *skb;
161 dma_addr_t dma;
162 struct page *page;
163 dma_addr_t page_dma;
762f4c57 164 unsigned int page_offset;
9a799d71
AK		 165};
166
167struct ixgbe_queue_stats {
168 u64 packets;
169 u64 bytes;
170};
171
5b7da515
AD		 172struct ixgbe_tx_queue_stats {
173 u64 restart_queue;
174 u64 tx_busy;
c84d324c
JF		 175 u64 completed;
176 u64 tx_done_old;
5b7da515
AD		 177};
178
179struct ixgbe_rx_queue_stats {
180 u64 rsc_count;
181 u64 rsc_flush;
182 u64 non_eop_descs;
183 u64 alloc_rx_page_failed;
184 u64 alloc_rx_buff_failed;
185};
186
7d637bcc
AD		 187enum ixbge_ring_state_t {
188 __IXGBE_TX_FDIR_INIT_DONE,
189 __IXGBE_TX_DETECT_HANG,
c84d324c 190 __IXGBE_HANG_CHECK_ARMED,
7d637bcc
AD		 191 __IXGBE_RX_PS_ENABLED,
192 __IXGBE_RX_RSC_ENABLED,
193};
194
195#define ring_is_ps_enabled(ring) \
196 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
197#define set_ring_ps_enabled(ring) \
198 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
199#define clear_ring_ps_enabled(ring) \
200 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
201#define check_for_tx_hang(ring) \
202 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
203#define set_check_for_tx_hang(ring) \
204 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
205#define clear_check_for_tx_hang(ring) \
206 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
207#define ring_is_rsc_enabled(ring) \
208 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
209#define set_ring_rsc_enabled(ring) \
210 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
211#define clear_ring_rsc_enabled(ring) \
212 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
9a799d71 213struct ixgbe_ring {
efe3d3c8 214 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
9a799d71 215 void *desc; /* descriptor ring memory */
b6ec895e 216 struct device *dev; /* device for DMA mapping */
fc77dc3c 217 struct net_device *netdev; /* netdev ring belongs to */
9a799d71
AK		 218 union {
219 struct ixgbe_tx_buffer *tx_buffer_info;
220 struct ixgbe_rx_buffer *rx_buffer_info;
221 };
7d637bcc 222 unsigned long state;
bd198058
AD		 223 u8 __iomem *tail;
224
ae540af1
JB		 225 u16 count; /* amount of descriptors */
226 u16 rx_buf_len;
ae540af1
JB		 227
228 u8 queue_index; /* needed for multiqueue queue management */
7d637bcc
AD		 229 u8 reg_idx; /* holds the special value that gets
230 * the hardware register offset
231 * associated with this ring, which is
232 * different for DCB and RSS modes
233 */
bd198058
AD		 234 u8 atr_sample_rate;
235 u8 atr_count;
9a799d71 236
bd198058
AD		 237 u16 next_to_use;
238 u16 next_to_clean;
9a799d71 239
bd198058 240 u8 dcb_tc;
9a799d71 241 struct ixgbe_queue_stats stats;
de1036b1 242 struct u64_stats_sync syncp;
5b7da515
AD		 243 union {
244 struct ixgbe_tx_queue_stats tx_stats;
245 struct ixgbe_rx_queue_stats rx_stats;
246 };
5b7da515 247 int numa_node;
ae540af1
JB		 248 unsigned int size; /* length in bytes */
249 dma_addr_t dma; /* phys. address of descriptor ring */
1a51502b 250 struct rcu_head rcu;
33cf09c9 251 struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
7ca3bc58 252} ____cacheline_internodealigned_in_smp;
9a799d71 253
c7e4358a
SN		 254enum ixgbe_ring_f_enum {
255 RING_F_NONE = 0,
7f870475 256 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 257 RING_F_RSS,
c4cf55e5 258 RING_F_FDIR,
0331a832
YZ		 259#ifdef IXGBE_FCOE
260 RING_F_FCOE,
261#endif /* IXGBE_FCOE */
c7e4358a
SN		 262
263 RING_F_ARRAY_SIZE /* must be last in enum set */
264};
265
021230d4 266#define IXGBE_MAX_RSS_INDICES 16
7f870475 267#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 268#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 269#ifdef IXGBE_FCOE
270#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 271#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
272#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
273#else
274#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
275#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 276#endif /* IXGBE_FCOE */
021230d4
AV		 277struct ixgbe_ring_feature {
278 int indices;
279 int mask;
7ca3bc58 280} ____cacheline_internodealigned_in_smp;
021230d4 281
08c8833b 282struct ixgbe_ring_container {
efe3d3c8 283 struct ixgbe_ring *ring; /* pointer to linked list of rings */
bd198058
AD		 284 unsigned int total_bytes; /* total bytes processed this int */
285 unsigned int total_packets; /* total packets processed this int */
286 u16 work_limit; /* total work allowed per interrupt */
08c8833b
AD		 287 u8 count; /* total number of rings in vector */
288 u8 itr; /* current ITR setting for ring */
289};
021230d4 290
2f90b865
AD		 291#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
292 ? 8 : 1)
293#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
294
021230d4
AV		 295/* MAX_MSIX_Q_VECTORS of these are allocated,
296 * but we only use one per queue-specific vector.
297 */
298struct ixgbe_q_vector {
299 struct ixgbe_adapter *adapter;
fe49f04a
AD		 300 unsigned int v_idx; /* index of q_vector within array, also used for
301 * finding the bit in EICR and friends that
302 * represents the vector for this ring */
33cf09c9
AD		 303#ifdef CONFIG_IXGBE_DCA
304 int cpu; /* CPU for DCA */
305#endif
021230d4 306 struct napi_struct napi;
08c8833b 307 struct ixgbe_ring_container rx, tx;
021230d4 308 u32 eitr;
b25ebfd2 309 cpumask_var_t affinity_mask;
d0759ebb 310 char name[IFNAMSIZ + 9];
021230d4
AV		 311};
312
9a799d71 313/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 314 * And yes, it's the same math going both ways. The lowest value
315 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 316 */
317#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 318 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 319#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
320
7d4987de
AD		 321static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
322{
323 u16 ntc = ring->next_to_clean;
324 u16 ntu = ring->next_to_use;
325
326 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
327}
9a799d71
AK		 328
329#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 330 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 331#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 332 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 333#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 334 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 335
336#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 337#ifdef IXGBE_FCOE
338/* Use 3K as the baby jumbo frame size for FCoE */
339#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
340#endif /* IXGBE_FCOE */
9a799d71 341
021230d4
AV		 342#define OTHER_VECTOR 1
343#define NON_Q_VECTORS (OTHER_VECTOR)
344
e8e26350
PW		 345#define MAX_MSIX_VECTORS_82599 64
346#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 347#define MAX_MSIX_VECTORS_82598 18
348#define MAX_MSIX_Q_VECTORS_82598 16
349
e8e26350
PW		 350#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
351#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 352
021230d4 353#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 354#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
355
9a799d71
AK		 356/* board specific private data structure */
357struct ixgbe_adapter {
e606bfe7
AD		 358 unsigned long state;
359
360 /* Some features need tri-state capability,
361 * thus the additional *_CAPABLE flags.
362 */
363 u32 flags;
364#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
365#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
366#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
367#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
368#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
369#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
370#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
371#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
372#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
373#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
374#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
375#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
376#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
377#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
378#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
379#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
380#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
381#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
382#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
383#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
7086400d
AD		 384#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
385#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
386#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
387#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
388#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
389#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
390#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
e606bfe7
AD		 391
392 u32 flags2;
393#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
394#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
395#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
f0f9778d 396#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
7086400d
AD		 397#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
398#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
c83c6cbd 399#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
d034acf1 400#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
e606bfe7 401
f62bbb5e 402 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9a799d71 403 u16 bd_number;
7a921c93 404 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
d033d526
JF		 405
406 /* DCB parameters */
407 struct ieee_pfc *ixgbe_ieee_pfc;
408 struct ieee_ets *ixgbe_ieee_ets;
2f90b865
AD		 409 struct ixgbe_dcb_config dcb_cfg;
410 struct ixgbe_dcb_config temp_dcb_cfg;
411 u8 dcb_set_bitmap;
3032309b 412 u8 dcbx_cap;
264857b8 413 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 414
f494e8fa 415 /* Interrupt Throttle Rate */
f7554a2b
NS		 416 u32 rx_itr_setting;
417 u32 tx_itr_setting;
f494e8fa
AV		 418 u16 eitr_low;
419 u16 eitr_high;
420
bd198058
AD		 421 /* Work limits */
422 u16 tx_work_limit;
423
9a799d71 424 /* TX */
4a0b9ca0 425 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 426 int num_tx_queues;
9a799d71
AK		 427 u32 tx_timeout_count;
428 bool detect_tx_hung;
429
7ca3bc58
JB		 430 u64 restart_queue;
431 u64 lsc_int;
432
9a799d71 433 /* RX */
4a0b9ca0 434 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 435 int num_rx_queues;
7f870475
GR		 436 int num_rx_pools; /* == num_rx_queues in 82598 */
437 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 438 u64 hw_csum_rx_error;
e8e26350 439 u64 hw_rx_no_dma_resources;
9a799d71 440 u64 non_eop_descs;
021230d4 441 int num_msix_vectors;
eb7f139c 442 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 443 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 444 struct msix_entry *msix_entries;
445
9a799d71
AK		 446 u32 alloc_rx_page_failed;
447 u32 alloc_rx_buff_failed;
448
96b0e0f6
JB		 449/* default to trying for four seconds */
450#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 451
452 /* OS defined structs */
453 struct net_device *netdev;
454 struct pci_dev *pdev;
9a799d71 455
da4dd0f7
PWJ		 456 u32 test_icr;
457 struct ixgbe_ring test_tx_ring;
458 struct ixgbe_ring test_rx_ring;
459
9a799d71
AK		 460 /* structs defined in ixgbe_hw.h */
461 struct ixgbe_hw hw;
462 u16 msg_enable;
463 struct ixgbe_hw_stats stats;
021230d4
AV		 464
465 /* Interrupt Throttle Rate */
f7554a2b
NS		 466 u32 rx_eitr_param;
467 u32 tx_eitr_param;
9a799d71 468
9a799d71 469 u64 tx_busy;
30efa5a3
JB		 470 unsigned int tx_ring_count;
471 unsigned int rx_ring_count;
cf8280ee
JB		 472
473 u32 link_speed;
474 bool link_up;
475 unsigned long link_check_timeout;
476
7086400d 477 struct work_struct service_task;
7086400d 478 struct timer_list service_timer;
c4cf55e5
PWJ		 479 u32 fdir_pballoc;
480 u32 atr_sample_rate;
d034acf1 481 unsigned long fdir_overflow; /* number of times ATR was backed off */
c4cf55e5 482 spinlock_t fdir_perfect_lock;
d0ed8937
YZ		 483#ifdef IXGBE_FCOE
484 struct ixgbe_fcoe fcoe;
485#endif /* IXGBE_FCOE */
94b982b2
MC		 486 u64 rsc_total_count;
487 u64 rsc_total_flush;
e8e26350 488 u32 wol;
34b0368c 489 u16 eeprom_version;
7f870475 490
1a6c14a2 491 int node;
66e6961c 492 u32 led_reg;
119fc60a 493 u32 interrupt_event;
1a6c14a2 494
7f870475
GR		 495 /* SR-IOV */
496 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
497 unsigned int num_vfs;
498 struct vf_data_storage *vfinfo;
ff4ab206 499 int vf_rate_link_speed;
a1cbb15c
GR		 500 struct vf_macvlans vf_mvs;
501 struct vf_macvlans *mv_list;
502 bool antispoofing_enabled;
3e05334f
AD		 503
504 struct hlist_head fdir_filter_list;
505 union ixgbe_atr_input fdir_mask;
506 int fdir_filter_count;
507};
508
509struct ixgbe_fdir_filter {
510 struct hlist_node fdir_node;
511 union ixgbe_atr_input filter;
512 u16 sw_idx;
513 u16 action;
9a799d71
AK		 514};
515
516enum ixbge_state_t {
517 __IXGBE_TESTING,
518 __IXGBE_RESETTING,
c4900be0 519 __IXGBE_DOWN,
7086400d
AD		 520 __IXGBE_SERVICE_SCHED,
521 __IXGBE_IN_SFP_INIT,
9a799d71
AK		 522};
523
aa80175a
AD		 524struct ixgbe_rsc_cb {
525 dma_addr_t dma;
526 u16 skb_cnt;
527 bool delay_unmap;
528};
529#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
530
9a799d71 531enum ixgbe_boards {
3957d63d 532 board_82598,
e8e26350 533 board_82599,
fe15e8e1 534 board_X540,
9a799d71
AK		 535};
536
3957d63d 537extern struct ixgbe_info ixgbe_82598_info;
e8e26350 538extern struct ixgbe_info ixgbe_82599_info;
fe15e8e1 539extern struct ixgbe_info ixgbe_X540_info;
7a6b6f51 540#ifdef CONFIG_IXGBE_DCB
32953543 541extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 542extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
543 struct ixgbe_dcb_config *dst_dcb_cfg,
544 int tc_max);
545#endif
9a799d71
AK		 546
547extern char ixgbe_driver_name[];
9c8eb720 548extern const char ixgbe_driver_version[];
9a799d71 549
c7ccde0f 550extern void ixgbe_up(struct ixgbe_adapter *adapter);
9a799d71 551extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 552extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 553extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 554extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 555extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
556extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
557extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
558extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 559extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
560extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
2d39d576
YZ		 561extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
562 struct ixgbe_ring *);
b4617240 563extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 564extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 565extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 566extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 567 struct ixgbe_adapter *,
568 struct ixgbe_ring *);
b6ec895e 569extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 570 struct ixgbe_tx_buffer *);
fc77dc3c 571extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a
AD		 572extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
573extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772 574extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
c04f6ca8
AD		 575extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
576extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
ffff4772 577extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 578 union ixgbe_atr_hash_dword input,
579 union ixgbe_atr_hash_dword common,
ffff4772 580 u8 queue);
c04f6ca8
AD		 581extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
582 union ixgbe_atr_input *input_mask);
583extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
584 union ixgbe_atr_input *input,
585 u16 soft_id, u8 queue);
586extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
587 union ixgbe_atr_input *input,
588 u16 soft_id);
589extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
590 union ixgbe_atr_input *mask);
7f870475 591extern void ixgbe_set_rx_mode(struct net_device *netdev);
e5b64635 592extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
897ab156 593extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
082757af 594extern void ixgbe_do_reset(struct net_device *netdev);
eacd73f7
YZ		 595#ifdef IXGBE_FCOE
596extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
897ab156 597extern int ixgbe_fso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
eacd73f7 598 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 599extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
600extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
ff886dfc
AD		 601 union ixgbe_adv_rx_desc *rx_desc,
602 struct sk_buff *skb,
603 u32 staterr);
332d4a7d
YZ		 604extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
605 struct scatterlist *sgl, unsigned int sgc);
68a683cf
YZ		 606extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
607 struct scatterlist *sgl, unsigned int sgc);
332d4a7d 608extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 609extern int ixgbe_fcoe_enable(struct net_device *netdev);
610extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 611#ifdef CONFIG_IXGBE_DCB
612extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
613extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
614#endif /* CONFIG_IXGBE_DCB */
61a1fa10 615extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 616#endif /* IXGBE_FCOE */
9a799d71
AK		 617
618#endif /* _IXGBE_H_ */
Linux kernel - Deliverables
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