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ixgbe: Add upper limit to ring features
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71 38
3a6a4eda
JK		 39#ifdef CONFIG_IXGBE_PTP
40#include <linux/clocksource.h>
41#include <linux/net_tstamp.h>
42#include <linux/ptp_clock_kernel.h>
43#endif /* CONFIG_IXGBE_PTP */
44
9a799d71
AK		 45#include "ixgbe_type.h"
46#include "ixgbe_common.h"
2f90b865 47#include "ixgbe_dcb.h"
eacd73f7
YZ		 48#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
49#define IXGBE_FCOE
50#include "ixgbe_fcoe.h"
51#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 52#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 53#include <linux/dca.h>
54#endif
9a799d71 55
849c4542
ET		 56/* common prefix used by pr_<> macros */
57#undef pr_fmt
58#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 59
60/* TX/RX descriptor defines */
6bacb300 61#define IXGBE_DEFAULT_TXD 512
59224555 62#define IXGBE_DEFAULT_TX_WORK 256
9a799d71
AK		 63#define IXGBE_MAX_TXD 4096
64#define IXGBE_MIN_TXD 64
65
6bacb300 66#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 67#define IXGBE_MAX_RXD 4096
68#define IXGBE_MIN_RXD 64
69
9a799d71 70/* flow control */
2b9ade93 71#define IXGBE_MIN_FCRTL 0x40
9a799d71 72#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 73#define IXGBE_MIN_FCRTH 0x600
9a799d71 74#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 75#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 76#define IXGBE_MIN_FCPAUSE 0
77#define IXGBE_MAX_FCPAUSE 0xFFFF
78
79/* Supported Rx Buffer Sizes */
13958070 80#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
919e78a6 81#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 82
13958070
AD		 83/*
84 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
85 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
86 * this adds up to 512 bytes of extra data meaning the smallest allocation
87 * we could have is 1K.
88 * i.e. RXBUFFER_512 --> size-1024 slab
89 */
90#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 91
92#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
93
9a799d71
AK		 94/* How many Rx Buffers do we bundle into one write to the hardware ? */
95#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
96
97#define IXGBE_TX_FLAGS_CSUM (u32)(1)
66f32a8b
AD		 98#define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
99#define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
100#define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
101#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
102#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
103#define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
7f9643fd 104#define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
3a6a4eda 105#define IXGBE_TX_FLAGS_TSTAMP (u32)(1 << 8)
9a799d71 106#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
66f32a8b
AD		 107#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
108#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
9a799d71
AK		 109#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
110
7f870475
GR		 111#define IXGBE_MAX_VF_MC_ENTRIES 30
112#define IXGBE_MAX_VF_FUNCTIONS 64
113#define IXGBE_MAX_VFTA_ENTRIES 128
114#define MAX_EMULATION_MAC_ADDRS 16
a1cbb15c 115#define IXGBE_MAX_PF_MACVLANS 15
7f870475 116#define VMDQ_P(p) ((p) + adapter->num_vfs)
83c61fa9
GR		 117#define IXGBE_82599_VF_DEVICE_ID 0x10ED
118#define IXGBE_X540_VF_DEVICE_ID 0x1515
7f870475
GR		 119
120struct vf_data_storage {
121 unsigned char vf_mac_addresses[ETH_ALEN];
122 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
123 u16 num_vf_mc_hashes;
124 u16 default_vf_vlan_id;
125 u16 vlans_enabled;
7f870475 126 bool clear_to_send;
7f01648a 127 bool pf_set_mac;
7f01648a
GR		 128 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
129 u16 pf_qos;
ff4ab206 130 u16 tx_rate;
de4c7f65
GR		 131 u16 vlan_count;
132 u8 spoofchk_enabled;
c6bda30a 133 struct pci_dev *vfdev;
7f870475
GR		 134};
135
a1cbb15c
GR		 136struct vf_macvlans {
137 struct list_head l;
138 int vf;
139 int rar_entry;
140 bool free;
141 bool is_macvlan;
142 u8 vf_macvlan[ETH_ALEN];
143};
144
a535c30e
AD		 145#define IXGBE_MAX_TXD_PWR 14
146#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
147
148/* Tx Descriptors needed, worst case */
149#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
150#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
151
9a799d71
AK		 152/* wrapper around a pointer to a socket buffer,
153 * so a DMA handle can be stored along with the buffer */
154struct ixgbe_tx_buffer {
d3d00239 155 union ixgbe_adv_tx_desc *next_to_watch;
9a799d71 156 unsigned long time_stamp;
fd0db0ed
AD		 157 struct sk_buff *skb;
158 unsigned int bytecount;
159 unsigned short gso_segs;
244e27ad 160 __be16 protocol;
729739b7
AD		 161 DEFINE_DMA_UNMAP_ADDR(dma);
162 DEFINE_DMA_UNMAP_LEN(len);
d3d00239 163 u32 tx_flags;
9a799d71
AK		 164};
165
166struct ixgbe_rx_buffer {
167 struct sk_buff *skb;
168 dma_addr_t dma;
169 struct page *page;
762f4c57 170 unsigned int page_offset;
9a799d71
AK		 171};
172
173struct ixgbe_queue_stats {
174 u64 packets;
175 u64 bytes;
176};
177
5b7da515
AD		 178struct ixgbe_tx_queue_stats {
179 u64 restart_queue;
180 u64 tx_busy;
c84d324c 181 u64 tx_done_old;
5b7da515
AD		 182};
183
184struct ixgbe_rx_queue_stats {
185 u64 rsc_count;
186 u64 rsc_flush;
187 u64 non_eop_descs;
188 u64 alloc_rx_page_failed;
189 u64 alloc_rx_buff_failed;
8a0da21b 190 u64 csum_err;
5b7da515
AD		 191};
192
f800326d 193enum ixgbe_ring_state_t {
7d637bcc
AD		 194 __IXGBE_TX_FDIR_INIT_DONE,
195 __IXGBE_TX_DETECT_HANG,
c84d324c 196 __IXGBE_HANG_CHECK_ARMED,
7d637bcc 197 __IXGBE_RX_RSC_ENABLED,
8a0da21b 198 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
57efd44c 199 __IXGBE_RX_FCOE,
7d637bcc
AD		 200};
201
7d637bcc
AD		 202#define check_for_tx_hang(ring) \
203 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
204#define set_check_for_tx_hang(ring) \
205 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
206#define clear_check_for_tx_hang(ring) \
207 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
208#define ring_is_rsc_enabled(ring) \
209 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
210#define set_ring_rsc_enabled(ring) \
211 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
212#define clear_ring_rsc_enabled(ring) \
213 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
9a799d71 214struct ixgbe_ring {
efe3d3c8 215 struct ixgbe_ring *next; /* pointer to next ring in q_vector */
d3ee4294
AD		 216 struct ixgbe_q_vector *q_vector; /* backpointer to host q_vector */
217 struct net_device *netdev; /* netdev ring belongs to */
218 struct device *dev; /* device for DMA mapping */
9a799d71 219 void *desc; /* descriptor ring memory */
9a799d71
AK		 220 union {
221 struct ixgbe_tx_buffer *tx_buffer_info;
222 struct ixgbe_rx_buffer *rx_buffer_info;
223 };
7d637bcc 224 unsigned long state;
bd198058 225 u8 __iomem *tail;
d3ee4294
AD		 226 dma_addr_t dma; /* phys. address of descriptor ring */
227 unsigned int size; /* length in bytes */
bd198058 228
ae540af1 229 u16 count; /* amount of descriptors */
ae540af1
JB		 230
231 u8 queue_index; /* needed for multiqueue queue management */
7d637bcc
AD		 232 u8 reg_idx; /* holds the special value that gets
233 * the hardware register offset
234 * associated with this ring, which is
235 * different for DCB and RSS modes
236 */
d3ee4294
AD		 237 u16 next_to_use;
238 u16 next_to_clean;
239
f800326d 240 union {
d3ee4294 241 u16 next_to_alloc;
f800326d
AD		 242 struct {
243 u8 atr_sample_rate;
244 u8 atr_count;
245 };
f800326d 246 };
9a799d71 247
bd198058 248 u8 dcb_tc;
9a799d71 249 struct ixgbe_queue_stats stats;
de1036b1 250 struct u64_stats_sync syncp;
5b7da515
AD		 251 union {
252 struct ixgbe_tx_queue_stats tx_stats;
253 struct ixgbe_rx_queue_stats rx_stats;
254 };
7ca3bc58 255} ____cacheline_internodealigned_in_smp;
9a799d71 256
c7e4358a
SN		 257enum ixgbe_ring_f_enum {
258 RING_F_NONE = 0,
7f870475 259 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 260 RING_F_RSS,
c4cf55e5 261 RING_F_FDIR,
0331a832
YZ		 262#ifdef IXGBE_FCOE
263 RING_F_FCOE,
264#endif /* IXGBE_FCOE */
c7e4358a
SN		 265
266 RING_F_ARRAY_SIZE /* must be last in enum set */
267};
268
021230d4 269#define IXGBE_MAX_RSS_INDICES 16
7f870475 270#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 271#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 272#ifdef IXGBE_FCOE
273#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 274#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
275#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
276#else
277#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
278#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 279#endif /* IXGBE_FCOE */
021230d4 280struct ixgbe_ring_feature {
c087663e
AD		 281 u16 limit; /* upper limit on feature indices */
282 u16 indices; /* current value of indices */
021230d4 283 int mask;
7ca3bc58 284} ____cacheline_internodealigned_in_smp;
021230d4 285
f800326d
AD		 286/*
287 * FCoE requires that all Rx buffers be over 2200 bytes in length. Since
288 * this is twice the size of a half page we need to double the page order
289 * for FCoE enabled Rx queues.
290 */
291#if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
292static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
293{
57efd44c 294 return test_bit(__IXGBE_RX_FCOE, &ring->state) ? 1 : 0;
f800326d
AD		 295}
296#else
297#define ixgbe_rx_pg_order(_ring) 0
298#endif
299#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
300#define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
301
08c8833b 302struct ixgbe_ring_container {
efe3d3c8 303 struct ixgbe_ring *ring; /* pointer to linked list of rings */
bd198058
AD		 304 unsigned int total_bytes; /* total bytes processed this int */
305 unsigned int total_packets; /* total packets processed this int */
306 u16 work_limit; /* total work allowed per interrupt */
08c8833b
AD		 307 u8 count; /* total number of rings in vector */
308 u8 itr; /* current ITR setting for ring */
309};
021230d4 310
a557928e
AD		 311/* iterator for handling rings in ring container */
312#define ixgbe_for_each_ring(pos, head) \
313 for (pos = (head).ring; pos != NULL; pos = pos->next)
314
2f90b865
AD		 315#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
316 ? 8 : 1)
317#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
318
49c7ffbe 319/* MAX_Q_VECTORS of these are allocated,
021230d4
AV		 320 * but we only use one per queue-specific vector.
321 */
322struct ixgbe_q_vector {
323 struct ixgbe_adapter *adapter;
33cf09c9
AD		 324#ifdef CONFIG_IXGBE_DCA
325 int cpu; /* CPU for DCA */
326#endif
d5bf4f67
ET		 327 u16 v_idx; /* index of q_vector within array, also used for
328 * finding the bit in EICR and friends that
329 * represents the vector for this ring */
330 u16 itr; /* Interrupt throttle rate written to EITR */
08c8833b 331 struct ixgbe_ring_container rx, tx;
d5bf4f67
ET		 332
333 struct napi_struct napi;
de88eeeb
AD		 334 cpumask_t affinity_mask;
335 int numa_node;
336 struct rcu_head rcu; /* to avoid race with update stats on free */
d0759ebb 337 char name[IFNAMSIZ + 9];
de88eeeb
AD		 338
339 /* for dynamic allocation of rings associated with this q_vector */
340 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
021230d4 341};
3ca8bc6d
DS		 342#ifdef CONFIG_IXGBE_HWMON
343
344#define IXGBE_HWMON_TYPE_LOC 0
345#define IXGBE_HWMON_TYPE_TEMP 1
346#define IXGBE_HWMON_TYPE_CAUTION 2
347#define IXGBE_HWMON_TYPE_MAX 3
348
349struct hwmon_attr {
350 struct device_attribute dev_attr;
351 struct ixgbe_hw *hw;
352 struct ixgbe_thermal_diode_data *sensor;
353 char name[12];
354};
355
356struct hwmon_buff {
357 struct device *device;
358 struct hwmon_attr *hwmon_list;
359 unsigned int n_hwmon;
360};
361#endif /* CONFIG_IXGBE_HWMON */
021230d4 362
d5bf4f67
ET		 363/*
364 * microsecond values for various ITR rates shifted by 2 to fit itr register
365 * with the first 3 bits reserved 0
9a799d71 366 */
d5bf4f67
ET		 367#define IXGBE_MIN_RSC_ITR 24
368#define IXGBE_100K_ITR 40
369#define IXGBE_20K_ITR 200
370#define IXGBE_10K_ITR 400
371#define IXGBE_8K_ITR 500
9a799d71 372
f56e0cb1
AD		 373/* ixgbe_test_staterr - tests bits in Rx descriptor status and error fields */
374static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
375 const u32 stat_err_bits)
376{
377 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
378}
379
7d4987de
AD		 380static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
381{
382 u16 ntc = ring->next_to_clean;
383 u16 ntu = ring->next_to_use;
384
385 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
386}
9a799d71 387
e4f74028 388#define IXGBE_RX_DESC(R, i) \
31f05a2d 389 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
e4f74028 390#define IXGBE_TX_DESC(R, i) \
31f05a2d 391 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
e4f74028 392#define IXGBE_TX_CTXTDESC(R, i) \
31f05a2d 393 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 394
395#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 396#ifdef IXGBE_FCOE
397/* Use 3K as the baby jumbo frame size for FCoE */
398#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
399#endif /* IXGBE_FCOE */
9a799d71 400
021230d4
AV		 401#define OTHER_VECTOR 1
402#define NON_Q_VECTORS (OTHER_VECTOR)
403
e8e26350 404#define MAX_MSIX_VECTORS_82599 64
49c7ffbe 405#define MAX_Q_VECTORS_82599 64
eb7f139c 406#define MAX_MSIX_VECTORS_82598 18
49c7ffbe 407#define MAX_Q_VECTORS_82598 16
eb7f139c 408
49c7ffbe 409#define MAX_Q_VECTORS MAX_Q_VECTORS_82599
e8e26350 410#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 411
8f15486d 412#define MIN_MSIX_Q_VECTORS 1
021230d4
AV		 413#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
414
46646e61
AD		 415/* default to trying for four seconds */
416#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
417
9a799d71
AK		 418/* board specific private data structure */
419struct ixgbe_adapter {
46646e61
AD		 420 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
421 /* OS defined structs */
422 struct net_device *netdev;
423 struct pci_dev *pdev;
424
e606bfe7
AD		 425 unsigned long state;
426
427 /* Some features need tri-state capability,
428 * thus the additional *_CAPABLE flags.
429 */
430 u32 flags;
e606bfe7
AD		 431#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
432#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
433#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
434#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
435#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
436#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
437#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
438#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
439#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
440#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
441#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
442#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
443#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
444#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
445#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
446#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
447#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
448#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
449#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
7086400d
AD		 450#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
451#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
452#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
453#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
454#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
455#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
456#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
e606bfe7
AD		 457
458 u32 flags2;
459#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
460#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
461#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
f0f9778d 462#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
7086400d
AD		 463#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
464#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
c83c6cbd 465#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
d034acf1 466#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
ef6afc0c
AD		 467#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
468#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
3a6a4eda 469#define IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED (u32)(1 << 10)
681ae1ad 470#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 11)
d033d526 471
46646e61
AD		 472 /* Tx fast path data */
473 int num_tx_queues;
474 u16 tx_itr_setting;
bd198058
AD		 475 u16 tx_work_limit;
476
46646e61
AD		 477 /* Rx fast path data */
478 int num_rx_queues;
479 u16 rx_itr_setting;
480
9a799d71 481 /* TX */
4a0b9ca0 482 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
9a799d71 483
7ca3bc58
JB		 484 u64 restart_queue;
485 u64 lsc_int;
46646e61 486 u32 tx_timeout_count;
7ca3bc58 487
9a799d71 488 /* RX */
46646e61 489 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
7f870475
GR		 490 int num_rx_pools; /* == num_rx_queues in 82598 */
491 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 492 u64 hw_csum_rx_error;
e8e26350 493 u64 hw_rx_no_dma_resources;
46646e61
AD		 494 u64 rsc_total_count;
495 u64 rsc_total_flush;
9a799d71 496 u64 non_eop_descs;
9a799d71
AK		 497 u32 alloc_rx_page_failed;
498 u32 alloc_rx_buff_failed;
499
49c7ffbe 500 struct ixgbe_q_vector *q_vector[MAX_Q_VECTORS];
9a799d71 501
46646e61
AD		 502 /* DCB parameters */
503 struct ieee_pfc *ixgbe_ieee_pfc;
504 struct ieee_ets *ixgbe_ieee_ets;
505 struct ixgbe_dcb_config dcb_cfg;
506 struct ixgbe_dcb_config temp_dcb_cfg;
507 u8 dcb_set_bitmap;
508 u8 dcbx_cap;
509 enum ixgbe_fc_mode last_lfc_mode;
510
49c7ffbe
AD		 511 int num_q_vectors; /* current number of q_vectors for device */
512 int max_q_vectors; /* true count of q_vectors for device */
46646e61
AD		 513 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
514 struct msix_entry *msix_entries;
9a799d71 515
da4dd0f7
PWJ		 516 u32 test_icr;
517 struct ixgbe_ring test_tx_ring;
518 struct ixgbe_ring test_rx_ring;
519
9a799d71
AK		 520 /* structs defined in ixgbe_hw.h */
521 struct ixgbe_hw hw;
522 u16 msg_enable;
523 struct ixgbe_hw_stats stats;
021230d4 524
9a799d71 525 u64 tx_busy;
30efa5a3
JB		 526 unsigned int tx_ring_count;
527 unsigned int rx_ring_count;
cf8280ee
JB		 528
529 u32 link_speed;
530 bool link_up;
531 unsigned long link_check_timeout;
532
7086400d 533 struct timer_list service_timer;
46646e61
AD		 534 struct work_struct service_task;
535
536 struct hlist_head fdir_filter_list;
537 unsigned long fdir_overflow; /* number of times ATR was backed off */
538 union ixgbe_atr_input fdir_mask;
539 int fdir_filter_count;
c4cf55e5
PWJ		 540 u32 fdir_pballoc;
541 u32 atr_sample_rate;
542 spinlock_t fdir_perfect_lock;
46646e61 543
d0ed8937
YZ		 544#ifdef IXGBE_FCOE
545 struct ixgbe_fcoe fcoe;
546#endif /* IXGBE_FCOE */
e8e26350 547 u32 wol;
46646e61 548
46646e61
AD		 549 u16 bd_number;
550
15e5209f
ET		 551 u16 eeprom_verh;
552 u16 eeprom_verl;
c23f5b6b 553 u16 eeprom_cap;
7f870475 554
119fc60a 555 u32 interrupt_event;
46646e61 556 u32 led_reg;
1a6c14a2 557
3a6a4eda
JK		 558#ifdef CONFIG_IXGBE_PTP
559 struct ptp_clock *ptp_clock;
560 struct ptp_clock_info ptp_caps;
561 unsigned long last_overflow_check;
562 spinlock_t tmreg_lock;
563 struct cyclecounter cc;
564 struct timecounter tc;
1d1a79b5 565 int rx_hwtstamp_filter;
3a6a4eda
JK		 566 u32 base_incval;
567 u32 cycle_speed;
568#endif /* CONFIG_IXGBE_PTP */
569
7f870475
GR		 570 /* SR-IOV */
571 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
572 unsigned int num_vfs;
573 struct vf_data_storage *vfinfo;
ff4ab206 574 int vf_rate_link_speed;
a1cbb15c
GR		 575 struct vf_macvlans vf_mvs;
576 struct vf_macvlans *mv_list;
3e05334f 577
83c61fa9
GR		 578 u32 timer_event_accumulator;
579 u32 vferr_refcount;
3ca8bc6d
DS		 580 struct kobject *info_kobj;
581#ifdef CONFIG_IXGBE_HWMON
582 struct hwmon_buff ixgbe_hwmon_buff;
583#endif /* CONFIG_IXGBE_HWMON */
3e05334f
AD		 584};
585
586struct ixgbe_fdir_filter {
587 struct hlist_node fdir_node;
588 union ixgbe_atr_input filter;
589 u16 sw_idx;
590 u16 action;
9a799d71
AK		 591};
592
70e5576c 593enum ixgbe_state_t {
9a799d71
AK		 594 __IXGBE_TESTING,
595 __IXGBE_RESETTING,
c4900be0 596 __IXGBE_DOWN,
7086400d
AD		 597 __IXGBE_SERVICE_SCHED,
598 __IXGBE_IN_SFP_INIT,
9a799d71
AK		 599};
600
4c1975d7
AD		 601struct ixgbe_cb {
602 union { /* Union defining head/tail partner */
603 struct sk_buff *head;
604 struct sk_buff *tail;
605 };
aa80175a 606 dma_addr_t dma;
4c1975d7 607 u16 append_cnt;
f800326d 608 bool page_released;
aa80175a 609};
4c1975d7 610#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
aa80175a 611
9a799d71 612enum ixgbe_boards {
3957d63d 613 board_82598,
e8e26350 614 board_82599,
fe15e8e1 615 board_X540,
9a799d71
AK		 616};
617
3957d63d 618extern struct ixgbe_info ixgbe_82598_info;
e8e26350 619extern struct ixgbe_info ixgbe_82599_info;
fe15e8e1 620extern struct ixgbe_info ixgbe_X540_info;
7a6b6f51 621#ifdef CONFIG_IXGBE_DCB
32953543 622extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865 623#endif
9a799d71
AK		 624
625extern char ixgbe_driver_name[];
9c8eb720 626extern const char ixgbe_driver_version[];
8af3c33f 627#ifdef IXGBE_FCOE
ea81875a 628extern char ixgbe_default_device_descr[];
8af3c33f 629#endif /* IXGBE_FCOE */
9a799d71 630
c7ccde0f 631extern void ixgbe_up(struct ixgbe_adapter *adapter);
9a799d71 632extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 633extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 634extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 635extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 636extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
637extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
638extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
639extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 640extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
641extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
2d39d576
YZ		 642extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
643 struct ixgbe_ring *);
b4617240 644extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 645extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
8e2813f5
JK		 646extern int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
647 u16 subdevice_id);
7a921c93 648extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 649extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 650 struct ixgbe_adapter *,
651 struct ixgbe_ring *);
b6ec895e 652extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 653 struct ixgbe_tx_buffer *);
fc77dc3c 654extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a 655extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
8af3c33f 656extern int ixgbe_poll(struct napi_struct *napi, int budget);
fe49f04a 657extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772 658extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
c04f6ca8
AD		 659extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
660extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
ffff4772 661extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
69830529
AD		 662 union ixgbe_atr_hash_dword input,
663 union ixgbe_atr_hash_dword common,
ffff4772 664 u8 queue);
c04f6ca8
AD		 665extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
666 union ixgbe_atr_input *input_mask);
667extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
668 union ixgbe_atr_input *input,
669 u16 soft_id, u8 queue);
670extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
671 union ixgbe_atr_input *input,
672 u16 soft_id);
673extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
674 union ixgbe_atr_input *mask);
7f870475 675extern void ixgbe_set_rx_mode(struct net_device *netdev);
8af3c33f 676#ifdef CONFIG_IXGBE_DCB
3ebe8fde 677extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
e5b64635 678extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
8af3c33f 679#endif
897ab156 680extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
082757af 681extern void ixgbe_do_reset(struct net_device *netdev);
1210982b 682#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 683extern void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
684extern int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
1210982b 685#endif /* CONFIG_IXGBE_HWMON */
eacd73f7
YZ		 686#ifdef IXGBE_FCOE
687extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
fd0db0ed
AD		 688extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
689 struct ixgbe_tx_buffer *first,
244e27ad 690 u8 *hdr_len);
332d4a7d
YZ		 691extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
692extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
ff886dfc 693 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 694 struct sk_buff *skb);
332d4a7d
YZ		 695extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
696 struct scatterlist *sgl, unsigned int sgc);
68a683cf
YZ		 697extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
698 struct scatterlist *sgl, unsigned int sgc);
332d4a7d 699extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 700extern int ixgbe_fcoe_enable(struct net_device *netdev);
701extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 702#ifdef CONFIG_IXGBE_DCB
703extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
704extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
705#endif /* CONFIG_IXGBE_DCB */
61a1fa10 706extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
ea81875a
NP		 707extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
708 struct netdev_fcoe_hbainfo *info);
eacd73f7 709#endif /* IXGBE_FCOE */
9a799d71 710
b2d96e0a
AD		 711static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
712{
713 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
714}
715
3a6a4eda
JK		 716#ifdef CONFIG_IXGBE_PTP
717extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
718extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
719extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
720extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
721 struct sk_buff *skb);
722extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
1d1a79b5 723 union ixgbe_adv_rx_desc *rx_desc,
3a6a4eda
JK		 724 struct sk_buff *skb);
725extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
726 struct ifreq *ifr, int cmd);
727extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
681ae1ad 728extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
3a6a4eda
JK		 729#endif /* CONFIG_IXGBE_PTP */
730
9a799d71 731#endif /* _IXGBE_H_ */
Linux kernel - Deliverables
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