Commit | Line | Data |
---|---|---|
9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
afdc71e4 | 4 | Copyright(c) 1999 - 2016 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/pci.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/sched.h> | |
ccffad25 | 32 | #include <linux/netdevice.h> |
9a799d71 | 33 | |
11afc1b1 | 34 | #include "ixgbe.h" |
9a799d71 AK |
35 | #include "ixgbe_common.h" |
36 | #include "ixgbe_phy.h" | |
37 | ||
c44ade9e | 38 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); |
9a799d71 AK |
39 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); |
40 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); | |
c44ade9e JB |
41 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); |
42 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); | |
43 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | |
e7cf745b | 44 | u16 count); |
c44ade9e JB |
45 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); |
46 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); | |
47 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); | |
48 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw); | |
9a799d71 | 49 | |
9a799d71 | 50 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); |
eb9c3e3e | 51 | static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg); |
68c7005d ET |
52 | static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, |
53 | u16 words, u16 *data); | |
54 | static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, | |
55 | u16 words, u16 *data); | |
56 | static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, | |
57 | u16 offset); | |
ff9d1a5a | 58 | static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw); |
9a799d71 | 59 | |
9a900eca DS |
60 | /* Base table for registers values that change by MAC */ |
61 | const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = { | |
62 | IXGBE_MVALS_INIT(8259X) | |
63 | }; | |
64 | ||
67a79df2 AD |
65 | /** |
66 | * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow | |
67 | * control | |
68 | * @hw: pointer to hardware structure | |
69 | * | |
70 | * There are several phys that do not support autoneg flow control. This | |
71 | * function check the device id to see if the associated phy supports | |
72 | * autoneg flow control. | |
73 | **/ | |
73d80953 | 74 | bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) |
67a79df2 | 75 | { |
73d80953 DS |
76 | bool supported = false; |
77 | ixgbe_link_speed speed; | |
78 | bool link_up; | |
67a79df2 | 79 | |
73d80953 DS |
80 | switch (hw->phy.media_type) { |
81 | case ixgbe_media_type_fiber: | |
82 | hw->mac.ops.check_link(hw, &speed, &link_up, false); | |
83 | /* if link is down, assume supported */ | |
84 | if (link_up) | |
85 | supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
86 | true : false; | |
87 | else | |
88 | supported = true; | |
89 | break; | |
90 | case ixgbe_media_type_backplane: | |
91 | supported = true; | |
92 | break; | |
93 | case ixgbe_media_type_copper: | |
94 | /* only some copper devices support flow control autoneg */ | |
95 | switch (hw->device_id) { | |
96 | case IXGBE_DEV_ID_82599_T3_LOM: | |
97 | case IXGBE_DEV_ID_X540T: | |
98 | case IXGBE_DEV_ID_X540T1: | |
df8c26fd | 99 | case IXGBE_DEV_ID_X550T: |
a711ad89 | 100 | case IXGBE_DEV_ID_X550T1: |
df8c26fd | 101 | case IXGBE_DEV_ID_X550EM_X_10G_T: |
73d80953 DS |
102 | supported = true; |
103 | break; | |
104 | default: | |
105 | break; | |
106 | } | |
67a79df2 | 107 | default: |
73d80953 | 108 | break; |
67a79df2 | 109 | } |
73d80953 DS |
110 | |
111 | return supported; | |
67a79df2 AD |
112 | } |
113 | ||
114 | /** | |
afdc71e4 | 115 | * ixgbe_setup_fc_generic - Set up flow control |
67a79df2 AD |
116 | * @hw: pointer to hardware structure |
117 | * | |
118 | * Called at init time to set up flow control. | |
119 | **/ | |
afdc71e4 | 120 | s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) |
67a79df2 AD |
121 | { |
122 | s32 ret_val = 0; | |
123 | u32 reg = 0, reg_bp = 0; | |
124 | u16 reg_cu = 0; | |
429d6a3b | 125 | bool locked = false; |
67a79df2 | 126 | |
67a79df2 AD |
127 | /* |
128 | * Validate the requested mode. Strict IEEE mode does not allow | |
129 | * ixgbe_fc_rx_pause because it will cause us to fail at UNH. | |
130 | */ | |
131 | if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { | |
132 | hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); | |
e90dd264 | 133 | return IXGBE_ERR_INVALID_LINK_SETTINGS; |
67a79df2 AD |
134 | } |
135 | ||
136 | /* | |
137 | * 10gig parts do not have a word in the EEPROM to determine the | |
138 | * default flow control setting, so we explicitly set it to full. | |
139 | */ | |
140 | if (hw->fc.requested_mode == ixgbe_fc_default) | |
141 | hw->fc.requested_mode = ixgbe_fc_full; | |
142 | ||
143 | /* | |
144 | * Set up the 1G and 10G flow control advertisement registers so the | |
145 | * HW will be able to do fc autoneg once the cable is plugged in. If | |
146 | * we link at 10G, the 1G advertisement is harmless and vice versa. | |
147 | */ | |
67a79df2 | 148 | switch (hw->phy.media_type) { |
429d6a3b DS |
149 | case ixgbe_media_type_backplane: |
150 | /* some MAC's need RMW protection on AUTOC */ | |
151 | ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); | |
f8cf7a00 | 152 | if (ret_val) |
e90dd264 | 153 | return ret_val; |
429d6a3b DS |
154 | |
155 | /* only backplane uses autoc so fall though */ | |
67a79df2 | 156 | case ixgbe_media_type_fiber: |
67a79df2 | 157 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); |
429d6a3b | 158 | |
67a79df2 | 159 | break; |
67a79df2 AD |
160 | case ixgbe_media_type_copper: |
161 | hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, | |
162 | MDIO_MMD_AN, ®_cu); | |
163 | break; | |
67a79df2 | 164 | default: |
041441d0 | 165 | break; |
67a79df2 AD |
166 | } |
167 | ||
168 | /* | |
169 | * The possible values of fc.requested_mode are: | |
170 | * 0: Flow control is completely disabled | |
171 | * 1: Rx flow control is enabled (we can receive pause frames, | |
172 | * but not send pause frames). | |
173 | * 2: Tx flow control is enabled (we can send pause frames but | |
174 | * we do not support receiving pause frames). | |
175 | * 3: Both Rx and Tx flow control (symmetric) are enabled. | |
67a79df2 AD |
176 | * other: Invalid. |
177 | */ | |
178 | switch (hw->fc.requested_mode) { | |
179 | case ixgbe_fc_none: | |
180 | /* Flow control completely disabled by software override. */ | |
181 | reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); | |
182 | if (hw->phy.media_type == ixgbe_media_type_backplane) | |
183 | reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | | |
184 | IXGBE_AUTOC_ASM_PAUSE); | |
185 | else if (hw->phy.media_type == ixgbe_media_type_copper) | |
186 | reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); | |
187 | break; | |
67a79df2 AD |
188 | case ixgbe_fc_tx_pause: |
189 | /* | |
190 | * Tx Flow control is enabled, and Rx Flow control is | |
191 | * disabled by software override. | |
192 | */ | |
041441d0 AD |
193 | reg |= IXGBE_PCS1GANA_ASM_PAUSE; |
194 | reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; | |
67a79df2 | 195 | if (hw->phy.media_type == ixgbe_media_type_backplane) { |
041441d0 AD |
196 | reg_bp |= IXGBE_AUTOC_ASM_PAUSE; |
197 | reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; | |
67a79df2 | 198 | } else if (hw->phy.media_type == ixgbe_media_type_copper) { |
041441d0 AD |
199 | reg_cu |= IXGBE_TAF_ASM_PAUSE; |
200 | reg_cu &= ~IXGBE_TAF_SYM_PAUSE; | |
67a79df2 AD |
201 | } |
202 | break; | |
041441d0 AD |
203 | case ixgbe_fc_rx_pause: |
204 | /* | |
205 | * Rx Flow control is enabled and Tx Flow control is | |
206 | * disabled by software override. Since there really | |
207 | * isn't a way to advertise that we are capable of RX | |
208 | * Pause ONLY, we will advertise that we support both | |
209 | * symmetric and asymmetric Rx PAUSE, as such we fall | |
210 | * through to the fc_full statement. Later, we will | |
211 | * disable the adapter's ability to send PAUSE frames. | |
212 | */ | |
67a79df2 AD |
213 | case ixgbe_fc_full: |
214 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | |
041441d0 | 215 | reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; |
67a79df2 | 216 | if (hw->phy.media_type == ixgbe_media_type_backplane) |
041441d0 AD |
217 | reg_bp |= IXGBE_AUTOC_SYM_PAUSE | |
218 | IXGBE_AUTOC_ASM_PAUSE; | |
67a79df2 | 219 | else if (hw->phy.media_type == ixgbe_media_type_copper) |
041441d0 | 220 | reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; |
67a79df2 | 221 | break; |
67a79df2 AD |
222 | default: |
223 | hw_dbg(hw, "Flow control param set incorrectly\n"); | |
e90dd264 | 224 | return IXGBE_ERR_CONFIG; |
67a79df2 AD |
225 | } |
226 | ||
227 | if (hw->mac.type != ixgbe_mac_X540) { | |
228 | /* | |
229 | * Enable auto-negotiation between the MAC & PHY; | |
230 | * the MAC will advertise clause 37 flow control. | |
231 | */ | |
232 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); | |
233 | reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); | |
234 | ||
235 | /* Disable AN timeout */ | |
236 | if (hw->fc.strict_ieee) | |
237 | reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; | |
238 | ||
239 | IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); | |
240 | hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg); | |
241 | } | |
242 | ||
243 | /* | |
244 | * AUTOC restart handles negotiation of 1G and 10G on backplane | |
245 | * and copper. There is no need to set the PCS1GCTL register. | |
246 | * | |
247 | */ | |
248 | if (hw->phy.media_type == ixgbe_media_type_backplane) { | |
d7bbcd32 DS |
249 | /* Need the SW/FW semaphore around AUTOC writes if 82599 and |
250 | * LESM is on, likewise reset_pipeline requries the lock as | |
251 | * it also writes AUTOC. | |
252 | */ | |
429d6a3b DS |
253 | ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); |
254 | if (ret_val) | |
e90dd264 | 255 | return ret_val; |
d7bbcd32 | 256 | |
67a79df2 | 257 | } else if ((hw->phy.media_type == ixgbe_media_type_copper) && |
429d6a3b | 258 | ixgbe_device_supports_autoneg_fc(hw)) { |
67a79df2 AD |
259 | hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, |
260 | MDIO_MMD_AN, reg_cu); | |
261 | } | |
262 | ||
263 | hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); | |
67a79df2 AD |
264 | return ret_val; |
265 | } | |
266 | ||
9a799d71 | 267 | /** |
c44ade9e | 268 | * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx |
9a799d71 AK |
269 | * @hw: pointer to hardware structure |
270 | * | |
271 | * Starts the hardware by filling the bus info structure and media type, clears | |
272 | * all on chip counters, initializes receive address registers, multicast | |
273 | * table, VLAN filter table, calls routine to set up link and flow control | |
274 | * settings, and leaves transmit and receive units disabled and uninitialized | |
275 | **/ | |
c44ade9e | 276 | s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) |
9a799d71 | 277 | { |
e5776620 | 278 | s32 ret_val; |
9a799d71 AK |
279 | u32 ctrl_ext; |
280 | ||
281 | /* Set the media type */ | |
282 | hw->phy.media_type = hw->mac.ops.get_media_type(hw); | |
283 | ||
284 | /* Identify the PHY */ | |
c44ade9e | 285 | hw->phy.ops.identify(hw); |
9a799d71 | 286 | |
9a799d71 | 287 | /* Clear the VLAN filter table */ |
c44ade9e | 288 | hw->mac.ops.clear_vfta(hw); |
9a799d71 | 289 | |
9a799d71 | 290 | /* Clear statistics registers */ |
c44ade9e | 291 | hw->mac.ops.clear_hw_cntrs(hw); |
9a799d71 AK |
292 | |
293 | /* Set No Snoop Disable */ | |
294 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
295 | ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; | |
296 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
3957d63d | 297 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 | 298 | |
620fa036 | 299 | /* Setup flow control */ |
afdc71e4 | 300 | ret_val = hw->mac.ops.setup_fc(hw); |
3507a9b8 MR |
301 | if (ret_val) |
302 | return ret_val; | |
620fa036 | 303 | |
9a799d71 AK |
304 | /* Clear adapter stopped flag */ |
305 | hw->adapter_stopped = false; | |
306 | ||
3507a9b8 | 307 | return 0; |
9a799d71 AK |
308 | } |
309 | ||
7184b7cf ET |
310 | /** |
311 | * ixgbe_start_hw_gen2 - Init sequence for common device family | |
312 | * @hw: pointer to hw structure | |
313 | * | |
314 | * Performs the init sequence common to the second generation | |
315 | * of 10 GbE devices. | |
316 | * Devices in the second generation: | |
317 | * 82599 | |
318 | * X540 | |
319 | **/ | |
320 | s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) | |
321 | { | |
322 | u32 i; | |
323 | ||
324 | /* Clear the rate limiters */ | |
325 | for (i = 0; i < hw->mac.max_tx_queues; i++) { | |
326 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); | |
327 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); | |
328 | } | |
329 | IXGBE_WRITE_FLUSH(hw); | |
330 | ||
887012e8 | 331 | #ifndef CONFIG_SPARC |
3d5c5207 ET |
332 | /* Disable relaxed ordering */ |
333 | for (i = 0; i < hw->mac.max_tx_queues; i++) { | |
887012e8 JK |
334 | u32 regval; |
335 | ||
3d5c5207 | 336 | regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); |
bdda1a61 | 337 | regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; |
3d5c5207 ET |
338 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); |
339 | } | |
340 | ||
341 | for (i = 0; i < hw->mac.max_rx_queues; i++) { | |
887012e8 JK |
342 | u32 regval; |
343 | ||
3d5c5207 | 344 | regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); |
bdda1a61 AD |
345 | regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | |
346 | IXGBE_DCA_RXCTRL_HEAD_WRO_EN); | |
3d5c5207 ET |
347 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); |
348 | } | |
887012e8 | 349 | #endif |
7184b7cf ET |
350 | return 0; |
351 | } | |
352 | ||
9a799d71 | 353 | /** |
c44ade9e | 354 | * ixgbe_init_hw_generic - Generic hardware initialization |
9a799d71 AK |
355 | * @hw: pointer to hardware structure |
356 | * | |
c44ade9e | 357 | * Initialize the hardware by resetting the hardware, filling the bus info |
9a799d71 AK |
358 | * structure and media type, clears all on chip counters, initializes receive |
359 | * address registers, multicast table, VLAN filter table, calls routine to set | |
360 | * up link and flow control settings, and leaves transmit and receive units | |
361 | * disabled and uninitialized | |
362 | **/ | |
c44ade9e | 363 | s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) |
9a799d71 | 364 | { |
794caeb2 PWJ |
365 | s32 status; |
366 | ||
9a799d71 | 367 | /* Reset the hardware */ |
794caeb2 | 368 | status = hw->mac.ops.reset_hw(hw); |
9a799d71 | 369 | |
794caeb2 PWJ |
370 | if (status == 0) { |
371 | /* Start the HW */ | |
372 | status = hw->mac.ops.start_hw(hw); | |
373 | } | |
9a799d71 | 374 | |
794caeb2 | 375 | return status; |
9a799d71 AK |
376 | } |
377 | ||
378 | /** | |
c44ade9e | 379 | * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters |
9a799d71 AK |
380 | * @hw: pointer to hardware structure |
381 | * | |
382 | * Clears all hardware statistics counters by reading them from the hardware | |
383 | * Statistics counters are clear on read. | |
384 | **/ | |
c44ade9e | 385 | s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
386 | { |
387 | u16 i = 0; | |
388 | ||
389 | IXGBE_READ_REG(hw, IXGBE_CRCERRS); | |
390 | IXGBE_READ_REG(hw, IXGBE_ILLERRC); | |
391 | IXGBE_READ_REG(hw, IXGBE_ERRBC); | |
392 | IXGBE_READ_REG(hw, IXGBE_MSPDC); | |
393 | for (i = 0; i < 8; i++) | |
394 | IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
395 | ||
396 | IXGBE_READ_REG(hw, IXGBE_MLFC); | |
397 | IXGBE_READ_REG(hw, IXGBE_MRFC); | |
398 | IXGBE_READ_REG(hw, IXGBE_RLEC); | |
399 | IXGBE_READ_REG(hw, IXGBE_LXONTXC); | |
9a799d71 | 400 | IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
667c7565 ET |
401 | if (hw->mac.type >= ixgbe_mac_82599EB) { |
402 | IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); | |
403 | IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
404 | } else { | |
405 | IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
406 | IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
407 | } | |
9a799d71 AK |
408 | |
409 | for (i = 0; i < 8; i++) { | |
410 | IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); | |
9a799d71 | 411 | IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); |
667c7565 ET |
412 | if (hw->mac.type >= ixgbe_mac_82599EB) { |
413 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
414 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
415 | } else { | |
416 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
417 | IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
418 | } | |
9a799d71 | 419 | } |
667c7565 ET |
420 | if (hw->mac.type >= ixgbe_mac_82599EB) |
421 | for (i = 0; i < 8; i++) | |
422 | IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); | |
9a799d71 AK |
423 | IXGBE_READ_REG(hw, IXGBE_PRC64); |
424 | IXGBE_READ_REG(hw, IXGBE_PRC127); | |
425 | IXGBE_READ_REG(hw, IXGBE_PRC255); | |
426 | IXGBE_READ_REG(hw, IXGBE_PRC511); | |
427 | IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
428 | IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
429 | IXGBE_READ_REG(hw, IXGBE_GPRC); | |
430 | IXGBE_READ_REG(hw, IXGBE_BPRC); | |
431 | IXGBE_READ_REG(hw, IXGBE_MPRC); | |
432 | IXGBE_READ_REG(hw, IXGBE_GPTC); | |
433 | IXGBE_READ_REG(hw, IXGBE_GORCL); | |
434 | IXGBE_READ_REG(hw, IXGBE_GORCH); | |
435 | IXGBE_READ_REG(hw, IXGBE_GOTCL); | |
436 | IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
f3116f62 ET |
437 | if (hw->mac.type == ixgbe_mac_82598EB) |
438 | for (i = 0; i < 8; i++) | |
439 | IXGBE_READ_REG(hw, IXGBE_RNBC(i)); | |
9a799d71 AK |
440 | IXGBE_READ_REG(hw, IXGBE_RUC); |
441 | IXGBE_READ_REG(hw, IXGBE_RFC); | |
442 | IXGBE_READ_REG(hw, IXGBE_ROC); | |
443 | IXGBE_READ_REG(hw, IXGBE_RJC); | |
444 | IXGBE_READ_REG(hw, IXGBE_MNGPRC); | |
445 | IXGBE_READ_REG(hw, IXGBE_MNGPDC); | |
446 | IXGBE_READ_REG(hw, IXGBE_MNGPTC); | |
447 | IXGBE_READ_REG(hw, IXGBE_TORL); | |
448 | IXGBE_READ_REG(hw, IXGBE_TORH); | |
449 | IXGBE_READ_REG(hw, IXGBE_TPR); | |
450 | IXGBE_READ_REG(hw, IXGBE_TPT); | |
451 | IXGBE_READ_REG(hw, IXGBE_PTC64); | |
452 | IXGBE_READ_REG(hw, IXGBE_PTC127); | |
453 | IXGBE_READ_REG(hw, IXGBE_PTC255); | |
454 | IXGBE_READ_REG(hw, IXGBE_PTC511); | |
455 | IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
456 | IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
457 | IXGBE_READ_REG(hw, IXGBE_MPTC); | |
458 | IXGBE_READ_REG(hw, IXGBE_BPTC); | |
459 | for (i = 0; i < 16; i++) { | |
460 | IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
9a799d71 | 461 | IXGBE_READ_REG(hw, IXGBE_QPTC(i)); |
667c7565 ET |
462 | if (hw->mac.type >= ixgbe_mac_82599EB) { |
463 | IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
464 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); | |
465 | IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
466 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); | |
467 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
468 | } else { | |
469 | IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
470 | IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
471 | } | |
9a799d71 AK |
472 | } |
473 | ||
e87ce1cd | 474 | if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { |
a3aeea0e ET |
475 | if (hw->phy.id == 0) |
476 | hw->phy.ops.identify(hw); | |
c1085b10 ET |
477 | hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i); |
478 | hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i); | |
479 | hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i); | |
480 | hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i); | |
a3aeea0e ET |
481 | } |
482 | ||
9a799d71 AK |
483 | return 0; |
484 | } | |
485 | ||
486 | /** | |
289700db | 487 | * ixgbe_read_pba_string_generic - Reads part number string from EEPROM |
c44ade9e | 488 | * @hw: pointer to hardware structure |
289700db DS |
489 | * @pba_num: stores the part number string from the EEPROM |
490 | * @pba_num_size: part number string buffer length | |
c44ade9e | 491 | * |
289700db | 492 | * Reads the part number string from the EEPROM. |
c44ade9e | 493 | **/ |
289700db | 494 | s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, |
e7cf745b | 495 | u32 pba_num_size) |
c44ade9e JB |
496 | { |
497 | s32 ret_val; | |
498 | u16 data; | |
289700db DS |
499 | u16 pba_ptr; |
500 | u16 offset; | |
501 | u16 length; | |
502 | ||
503 | if (pba_num == NULL) { | |
504 | hw_dbg(hw, "PBA string buffer was null\n"); | |
505 | return IXGBE_ERR_INVALID_ARGUMENT; | |
506 | } | |
c44ade9e JB |
507 | |
508 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); | |
509 | if (ret_val) { | |
510 | hw_dbg(hw, "NVM Read Error\n"); | |
511 | return ret_val; | |
512 | } | |
c44ade9e | 513 | |
289700db | 514 | ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); |
c44ade9e JB |
515 | if (ret_val) { |
516 | hw_dbg(hw, "NVM Read Error\n"); | |
517 | return ret_val; | |
518 | } | |
289700db DS |
519 | |
520 | /* | |
521 | * if data is not ptr guard the PBA must be in legacy format which | |
522 | * means pba_ptr is actually our second data word for the PBA number | |
523 | * and we can decode it into an ascii string | |
524 | */ | |
525 | if (data != IXGBE_PBANUM_PTR_GUARD) { | |
526 | hw_dbg(hw, "NVM PBA number is not stored as string\n"); | |
527 | ||
528 | /* we will need 11 characters to store the PBA */ | |
529 | if (pba_num_size < 11) { | |
530 | hw_dbg(hw, "PBA string buffer too small\n"); | |
531 | return IXGBE_ERR_NO_SPACE; | |
532 | } | |
533 | ||
534 | /* extract hex string from data and pba_ptr */ | |
535 | pba_num[0] = (data >> 12) & 0xF; | |
536 | pba_num[1] = (data >> 8) & 0xF; | |
537 | pba_num[2] = (data >> 4) & 0xF; | |
538 | pba_num[3] = data & 0xF; | |
539 | pba_num[4] = (pba_ptr >> 12) & 0xF; | |
540 | pba_num[5] = (pba_ptr >> 8) & 0xF; | |
541 | pba_num[6] = '-'; | |
542 | pba_num[7] = 0; | |
543 | pba_num[8] = (pba_ptr >> 4) & 0xF; | |
544 | pba_num[9] = pba_ptr & 0xF; | |
545 | ||
546 | /* put a null character on the end of our string */ | |
547 | pba_num[10] = '\0'; | |
548 | ||
549 | /* switch all the data but the '-' to hex char */ | |
550 | for (offset = 0; offset < 10; offset++) { | |
551 | if (pba_num[offset] < 0xA) | |
552 | pba_num[offset] += '0'; | |
553 | else if (pba_num[offset] < 0x10) | |
554 | pba_num[offset] += 'A' - 0xA; | |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); | |
561 | if (ret_val) { | |
562 | hw_dbg(hw, "NVM Read Error\n"); | |
563 | return ret_val; | |
564 | } | |
565 | ||
566 | if (length == 0xFFFF || length == 0) { | |
567 | hw_dbg(hw, "NVM PBA number section invalid length\n"); | |
568 | return IXGBE_ERR_PBA_SECTION; | |
569 | } | |
570 | ||
571 | /* check if pba_num buffer is big enough */ | |
572 | if (pba_num_size < (((u32)length * 2) - 1)) { | |
573 | hw_dbg(hw, "PBA string buffer too small\n"); | |
574 | return IXGBE_ERR_NO_SPACE; | |
575 | } | |
576 | ||
577 | /* trim pba length from start of string */ | |
578 | pba_ptr++; | |
579 | length--; | |
580 | ||
581 | for (offset = 0; offset < length; offset++) { | |
582 | ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); | |
583 | if (ret_val) { | |
584 | hw_dbg(hw, "NVM Read Error\n"); | |
585 | return ret_val; | |
586 | } | |
587 | pba_num[offset * 2] = (u8)(data >> 8); | |
588 | pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); | |
589 | } | |
590 | pba_num[offset * 2] = '\0'; | |
c44ade9e JB |
591 | |
592 | return 0; | |
593 | } | |
594 | ||
595 | /** | |
596 | * ixgbe_get_mac_addr_generic - Generic get MAC address | |
9a799d71 AK |
597 | * @hw: pointer to hardware structure |
598 | * @mac_addr: Adapter MAC address | |
599 | * | |
600 | * Reads the adapter's MAC address from first Receive Address Register (RAR0) | |
601 | * A reset of the adapter must be performed prior to calling this function | |
602 | * in order for the MAC address to have been loaded from the EEPROM into RAR0 | |
603 | **/ | |
c44ade9e | 604 | s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) |
9a799d71 AK |
605 | { |
606 | u32 rar_high; | |
607 | u32 rar_low; | |
608 | u16 i; | |
609 | ||
610 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); | |
611 | rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); | |
612 | ||
613 | for (i = 0; i < 4; i++) | |
614 | mac_addr[i] = (u8)(rar_low >> (i*8)); | |
615 | ||
616 | for (i = 0; i < 2; i++) | |
617 | mac_addr[i+4] = (u8)(rar_high >> (i*8)); | |
618 | ||
619 | return 0; | |
620 | } | |
621 | ||
ef1889d5 JK |
622 | enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status) |
623 | { | |
624 | switch (link_status & IXGBE_PCI_LINK_WIDTH) { | |
625 | case IXGBE_PCI_LINK_WIDTH_1: | |
626 | return ixgbe_bus_width_pcie_x1; | |
627 | case IXGBE_PCI_LINK_WIDTH_2: | |
628 | return ixgbe_bus_width_pcie_x2; | |
629 | case IXGBE_PCI_LINK_WIDTH_4: | |
630 | return ixgbe_bus_width_pcie_x4; | |
631 | case IXGBE_PCI_LINK_WIDTH_8: | |
632 | return ixgbe_bus_width_pcie_x8; | |
633 | default: | |
634 | return ixgbe_bus_width_unknown; | |
635 | } | |
636 | } | |
637 | ||
638 | enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status) | |
639 | { | |
640 | switch (link_status & IXGBE_PCI_LINK_SPEED) { | |
641 | case IXGBE_PCI_LINK_SPEED_2500: | |
642 | return ixgbe_bus_speed_2500; | |
643 | case IXGBE_PCI_LINK_SPEED_5000: | |
644 | return ixgbe_bus_speed_5000; | |
645 | case IXGBE_PCI_LINK_SPEED_8000: | |
646 | return ixgbe_bus_speed_8000; | |
647 | default: | |
648 | return ixgbe_bus_speed_unknown; | |
649 | } | |
650 | } | |
651 | ||
11afc1b1 PW |
652 | /** |
653 | * ixgbe_get_bus_info_generic - Generic set PCI bus info | |
654 | * @hw: pointer to hardware structure | |
655 | * | |
656 | * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure | |
657 | **/ | |
658 | s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) | |
659 | { | |
11afc1b1 PW |
660 | u16 link_status; |
661 | ||
662 | hw->bus.type = ixgbe_bus_type_pci_express; | |
663 | ||
664 | /* Get the negotiated link width and speed from PCI config space */ | |
0d7c6e00 | 665 | link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS); |
11afc1b1 | 666 | |
ef1889d5 JK |
667 | hw->bus.width = ixgbe_convert_bus_width(link_status); |
668 | hw->bus.speed = ixgbe_convert_bus_speed(link_status); | |
11afc1b1 | 669 | |
0d7c6e00 | 670 | hw->mac.ops.set_lan_id(hw); |
11afc1b1 PW |
671 | |
672 | return 0; | |
673 | } | |
674 | ||
675 | /** | |
676 | * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices | |
677 | * @hw: pointer to the HW structure | |
678 | * | |
679 | * Determines the LAN function id by reading memory-mapped registers | |
680 | * and swaps the port value if requested. | |
681 | **/ | |
682 | void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) | |
683 | { | |
684 | struct ixgbe_bus_info *bus = &hw->bus; | |
c898fe28 | 685 | u16 ee_ctrl_4; |
11afc1b1 PW |
686 | u32 reg; |
687 | ||
688 | reg = IXGBE_READ_REG(hw, IXGBE_STATUS); | |
689 | bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; | |
690 | bus->lan_id = bus->func; | |
691 | ||
692 | /* check for a port swap */ | |
9a900eca | 693 | reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw)); |
11afc1b1 PW |
694 | if (reg & IXGBE_FACTPS_LFS) |
695 | bus->func ^= 0x1; | |
c898fe28 MR |
696 | |
697 | /* Get MAC instance from EEPROM for configuring CS4227 */ | |
698 | if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { | |
699 | hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); | |
700 | bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> | |
701 | IXGBE_EE_CTRL_4_INST_ID_SHIFT; | |
702 | } | |
11afc1b1 PW |
703 | } |
704 | ||
9a799d71 | 705 | /** |
c44ade9e | 706 | * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units |
9a799d71 AK |
707 | * @hw: pointer to hardware structure |
708 | * | |
709 | * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, | |
710 | * disables transmit and receive units. The adapter_stopped flag is used by | |
711 | * the shared code and drivers to determine if the adapter is in a stopped | |
712 | * state and should not touch the hardware. | |
713 | **/ | |
c44ade9e | 714 | s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) |
9a799d71 | 715 | { |
9a799d71 AK |
716 | u32 reg_val; |
717 | u16 i; | |
718 | ||
719 | /* | |
720 | * Set the adapter_stopped flag so other driver functions stop touching | |
721 | * the hardware | |
722 | */ | |
723 | hw->adapter_stopped = true; | |
724 | ||
725 | /* Disable the receive unit */ | |
1f9ac57c | 726 | hw->mac.ops.disable_rx(hw); |
9a799d71 | 727 | |
ff9d1a5a | 728 | /* Clear interrupt mask to stop interrupts from being generated */ |
9a799d71 AK |
729 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); |
730 | ||
ff9d1a5a | 731 | /* Clear any pending interrupts, flush previous writes */ |
9a799d71 AK |
732 | IXGBE_READ_REG(hw, IXGBE_EICR); |
733 | ||
734 | /* Disable the transmit unit. Each queue must be disabled. */ | |
ff9d1a5a ET |
735 | for (i = 0; i < hw->mac.max_tx_queues; i++) |
736 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); | |
737 | ||
738 | /* Disable the receive unit by stopping each queue */ | |
739 | for (i = 0; i < hw->mac.max_rx_queues; i++) { | |
740 | reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
741 | reg_val &= ~IXGBE_RXDCTL_ENABLE; | |
742 | reg_val |= IXGBE_RXDCTL_SWFLSH; | |
743 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); | |
9a799d71 AK |
744 | } |
745 | ||
ff9d1a5a ET |
746 | /* flush all queues disables */ |
747 | IXGBE_WRITE_FLUSH(hw); | |
748 | usleep_range(1000, 2000); | |
749 | ||
c44ade9e JB |
750 | /* |
751 | * Prevent the PCI-E bus from from hanging by disabling PCI-E master | |
752 | * access and verify no pending requests | |
753 | */ | |
ff9d1a5a | 754 | return ixgbe_disable_pcie_master(hw); |
9a799d71 AK |
755 | } |
756 | ||
757 | /** | |
c44ade9e | 758 | * ixgbe_led_on_generic - Turns on the software controllable LEDs. |
9a799d71 AK |
759 | * @hw: pointer to hardware structure |
760 | * @index: led number to turn on | |
761 | **/ | |
c44ade9e | 762 | s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) |
9a799d71 AK |
763 | { |
764 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
765 | ||
003287e0 DS |
766 | if (index > 3) |
767 | return IXGBE_ERR_PARAM; | |
768 | ||
9a799d71 AK |
769 | /* To turn on the LED, set mode to ON. */ |
770 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
771 | led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); | |
772 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
3957d63d | 773 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
774 | |
775 | return 0; | |
776 | } | |
777 | ||
778 | /** | |
c44ade9e | 779 | * ixgbe_led_off_generic - Turns off the software controllable LEDs. |
9a799d71 AK |
780 | * @hw: pointer to hardware structure |
781 | * @index: led number to turn off | |
782 | **/ | |
c44ade9e | 783 | s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) |
9a799d71 AK |
784 | { |
785 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
786 | ||
003287e0 DS |
787 | if (index > 3) |
788 | return IXGBE_ERR_PARAM; | |
789 | ||
9a799d71 AK |
790 | /* To turn off the LED, set mode to OFF. */ |
791 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
792 | led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); | |
793 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
3957d63d | 794 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
795 | |
796 | return 0; | |
797 | } | |
798 | ||
9a799d71 | 799 | /** |
c44ade9e | 800 | * ixgbe_init_eeprom_params_generic - Initialize EEPROM params |
9a799d71 AK |
801 | * @hw: pointer to hardware structure |
802 | * | |
803 | * Initializes the EEPROM parameters ixgbe_eeprom_info within the | |
804 | * ixgbe_hw struct in order to set up EEPROM access. | |
805 | **/ | |
c44ade9e | 806 | s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
807 | { |
808 | struct ixgbe_eeprom_info *eeprom = &hw->eeprom; | |
809 | u32 eec; | |
810 | u16 eeprom_size; | |
811 | ||
812 | if (eeprom->type == ixgbe_eeprom_uninitialized) { | |
813 | eeprom->type = ixgbe_eeprom_none; | |
c44ade9e JB |
814 | /* Set default semaphore delay to 10ms which is a well |
815 | * tested value */ | |
816 | eeprom->semaphore_delay = 10; | |
68c7005d ET |
817 | /* Clear EEPROM page size, it will be initialized as needed */ |
818 | eeprom->word_page_size = 0; | |
9a799d71 AK |
819 | |
820 | /* | |
821 | * Check for EEPROM present first. | |
822 | * If not present leave as none | |
823 | */ | |
9a900eca | 824 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
9a799d71 AK |
825 | if (eec & IXGBE_EEC_PRES) { |
826 | eeprom->type = ixgbe_eeprom_spi; | |
827 | ||
828 | /* | |
829 | * SPI EEPROM is assumed here. This code would need to | |
830 | * change if a future EEPROM is not SPI. | |
831 | */ | |
832 | eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> | |
833 | IXGBE_EEC_SIZE_SHIFT); | |
b4f47a48 JK |
834 | eeprom->word_size = BIT(eeprom_size + |
835 | IXGBE_EEPROM_WORD_SIZE_SHIFT); | |
9a799d71 AK |
836 | } |
837 | ||
838 | if (eec & IXGBE_EEC_ADDR_SIZE) | |
839 | eeprom->address_bits = 16; | |
840 | else | |
841 | eeprom->address_bits = 8; | |
6ec1b71f JK |
842 | hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n", |
843 | eeprom->type, eeprom->word_size, eeprom->address_bits); | |
9a799d71 AK |
844 | } |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
11afc1b1 | 849 | /** |
68c7005d | 850 | * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang |
11afc1b1 | 851 | * @hw: pointer to hardware structure |
68c7005d ET |
852 | * @offset: offset within the EEPROM to write |
853 | * @words: number of words | |
854 | * @data: 16 bit word(s) to write to EEPROM | |
11afc1b1 | 855 | * |
68c7005d | 856 | * Reads 16 bit word(s) from EEPROM through bit-bang method |
11afc1b1 | 857 | **/ |
68c7005d ET |
858 | s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
859 | u16 words, u16 *data) | |
11afc1b1 | 860 | { |
e90dd264 | 861 | s32 status; |
68c7005d | 862 | u16 i, count; |
11afc1b1 PW |
863 | |
864 | hw->eeprom.ops.init_params(hw); | |
865 | ||
e90dd264 MR |
866 | if (words == 0) |
867 | return IXGBE_ERR_INVALID_ARGUMENT; | |
68c7005d | 868 | |
e90dd264 MR |
869 | if (offset + words > hw->eeprom.word_size) |
870 | return IXGBE_ERR_EEPROM; | |
11afc1b1 | 871 | |
68c7005d ET |
872 | /* |
873 | * The EEPROM page size cannot be queried from the chip. We do lazy | |
874 | * initialization. It is worth to do that when we write large buffer. | |
875 | */ | |
876 | if ((hw->eeprom.word_page_size == 0) && | |
877 | (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) | |
878 | ixgbe_detect_eeprom_page_size_generic(hw, offset); | |
879 | ||
880 | /* | |
881 | * We cannot hold synchronization semaphores for too long | |
882 | * to avoid other entity starvation. However it is more efficient | |
883 | * to read in bursts than synchronizing access for each word. | |
884 | */ | |
885 | for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { | |
886 | count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? | |
887 | IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); | |
888 | status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, | |
889 | count, &data[i]); | |
890 | ||
891 | if (status != 0) | |
892 | break; | |
893 | } | |
894 | ||
68c7005d ET |
895 | return status; |
896 | } | |
897 | ||
898 | /** | |
899 | * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM | |
900 | * @hw: pointer to hardware structure | |
901 | * @offset: offset within the EEPROM to be written to | |
902 | * @words: number of word(s) | |
903 | * @data: 16 bit word(s) to be written to the EEPROM | |
904 | * | |
905 | * If ixgbe_eeprom_update_checksum is not called after this function, the | |
906 | * EEPROM will most likely contain an invalid checksum. | |
907 | **/ | |
908 | static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, | |
909 | u16 words, u16 *data) | |
910 | { | |
911 | s32 status; | |
912 | u16 word; | |
913 | u16 page_size; | |
914 | u16 i; | |
915 | u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; | |
916 | ||
11afc1b1 PW |
917 | /* Prepare the EEPROM for writing */ |
918 | status = ixgbe_acquire_eeprom(hw); | |
e90dd264 MR |
919 | if (status) |
920 | return status; | |
11afc1b1 | 921 | |
e90dd264 MR |
922 | if (ixgbe_ready_eeprom(hw) != 0) { |
923 | ixgbe_release_eeprom(hw); | |
924 | return IXGBE_ERR_EEPROM; | |
11afc1b1 PW |
925 | } |
926 | ||
e90dd264 MR |
927 | for (i = 0; i < words; i++) { |
928 | ixgbe_standby_eeprom(hw); | |
929 | ||
930 | /* Send the WRITE ENABLE command (8 bit opcode) */ | |
931 | ixgbe_shift_out_eeprom_bits(hw, | |
932 | IXGBE_EEPROM_WREN_OPCODE_SPI, | |
933 | IXGBE_EEPROM_OPCODE_BITS); | |
11afc1b1 | 934 | |
e90dd264 | 935 | ixgbe_standby_eeprom(hw); |
11afc1b1 | 936 | |
e90dd264 MR |
937 | /* Some SPI eeproms use the 8th address bit embedded |
938 | * in the opcode | |
939 | */ | |
940 | if ((hw->eeprom.address_bits == 8) && | |
941 | ((offset + i) >= 128)) | |
942 | write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; | |
11afc1b1 | 943 | |
e90dd264 MR |
944 | /* Send the Write command (8-bit opcode + addr) */ |
945 | ixgbe_shift_out_eeprom_bits(hw, write_opcode, | |
946 | IXGBE_EEPROM_OPCODE_BITS); | |
947 | ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), | |
948 | hw->eeprom.address_bits); | |
949 | ||
950 | page_size = hw->eeprom.word_page_size; | |
951 | ||
952 | /* Send the data in burst via SPI */ | |
953 | do { | |
954 | word = data[i]; | |
955 | word = (word >> 8) | (word << 8); | |
956 | ixgbe_shift_out_eeprom_bits(hw, word, 16); | |
957 | ||
958 | if (page_size == 0) | |
959 | break; | |
960 | ||
961 | /* do not wrap around page */ | |
962 | if (((offset + i) & (page_size - 1)) == | |
963 | (page_size - 1)) | |
964 | break; | |
965 | } while (++i < words); | |
966 | ||
967 | ixgbe_standby_eeprom(hw); | |
968 | usleep_range(10000, 20000); | |
68c7005d | 969 | } |
e90dd264 MR |
970 | /* Done with writing - release the EEPROM */ |
971 | ixgbe_release_eeprom(hw); | |
11afc1b1 | 972 | |
e90dd264 | 973 | return 0; |
68c7005d ET |
974 | } |
975 | ||
976 | /** | |
977 | * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM | |
978 | * @hw: pointer to hardware structure | |
979 | * @offset: offset within the EEPROM to be written to | |
980 | * @data: 16 bit word to be written to the EEPROM | |
981 | * | |
982 | * If ixgbe_eeprom_update_checksum is not called after this function, the | |
983 | * EEPROM will most likely contain an invalid checksum. | |
984 | **/ | |
985 | s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) | |
986 | { | |
68c7005d | 987 | hw->eeprom.ops.init_params(hw); |
11afc1b1 | 988 | |
e90dd264 MR |
989 | if (offset >= hw->eeprom.word_size) |
990 | return IXGBE_ERR_EEPROM; | |
11afc1b1 | 991 | |
e90dd264 | 992 | return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); |
11afc1b1 PW |
993 | } |
994 | ||
9a799d71 | 995 | /** |
68c7005d | 996 | * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang |
c44ade9e JB |
997 | * @hw: pointer to hardware structure |
998 | * @offset: offset within the EEPROM to be read | |
68c7005d ET |
999 | * @words: number of word(s) |
1000 | * @data: read 16 bit words(s) from EEPROM | |
c44ade9e | 1001 | * |
68c7005d | 1002 | * Reads 16 bit word(s) from EEPROM through bit-bang method |
c44ade9e | 1003 | **/ |
68c7005d ET |
1004 | s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, |
1005 | u16 words, u16 *data) | |
c44ade9e | 1006 | { |
e90dd264 | 1007 | s32 status; |
68c7005d | 1008 | u16 i, count; |
c44ade9e JB |
1009 | |
1010 | hw->eeprom.ops.init_params(hw); | |
1011 | ||
e90dd264 MR |
1012 | if (words == 0) |
1013 | return IXGBE_ERR_INVALID_ARGUMENT; | |
68c7005d | 1014 | |
e90dd264 MR |
1015 | if (offset + words > hw->eeprom.word_size) |
1016 | return IXGBE_ERR_EEPROM; | |
c44ade9e | 1017 | |
68c7005d ET |
1018 | /* |
1019 | * We cannot hold synchronization semaphores for too long | |
1020 | * to avoid other entity starvation. However it is more efficient | |
1021 | * to read in bursts than synchronizing access for each word. | |
1022 | */ | |
1023 | for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { | |
1024 | count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? | |
1025 | IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); | |
1026 | ||
1027 | status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, | |
1028 | count, &data[i]); | |
1029 | ||
e90dd264 MR |
1030 | if (status) |
1031 | return status; | |
68c7005d ET |
1032 | } |
1033 | ||
e90dd264 | 1034 | return 0; |
68c7005d ET |
1035 | } |
1036 | ||
1037 | /** | |
1038 | * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang | |
1039 | * @hw: pointer to hardware structure | |
1040 | * @offset: offset within the EEPROM to be read | |
1041 | * @words: number of word(s) | |
1042 | * @data: read 16 bit word(s) from EEPROM | |
1043 | * | |
1044 | * Reads 16 bit word(s) from EEPROM through bit-bang method | |
1045 | **/ | |
1046 | static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, | |
1047 | u16 words, u16 *data) | |
1048 | { | |
1049 | s32 status; | |
1050 | u16 word_in; | |
1051 | u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; | |
1052 | u16 i; | |
1053 | ||
c44ade9e JB |
1054 | /* Prepare the EEPROM for reading */ |
1055 | status = ixgbe_acquire_eeprom(hw); | |
e90dd264 MR |
1056 | if (status) |
1057 | return status; | |
c44ade9e | 1058 | |
e90dd264 MR |
1059 | if (ixgbe_ready_eeprom(hw) != 0) { |
1060 | ixgbe_release_eeprom(hw); | |
1061 | return IXGBE_ERR_EEPROM; | |
c44ade9e JB |
1062 | } |
1063 | ||
e90dd264 MR |
1064 | for (i = 0; i < words; i++) { |
1065 | ixgbe_standby_eeprom(hw); | |
1066 | /* Some SPI eeproms use the 8th address bit embedded | |
1067 | * in the opcode | |
1068 | */ | |
1069 | if ((hw->eeprom.address_bits == 8) && | |
1070 | ((offset + i) >= 128)) | |
1071 | read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; | |
c44ade9e | 1072 | |
e90dd264 MR |
1073 | /* Send the READ command (opcode + addr) */ |
1074 | ixgbe_shift_out_eeprom_bits(hw, read_opcode, | |
1075 | IXGBE_EEPROM_OPCODE_BITS); | |
1076 | ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), | |
1077 | hw->eeprom.address_bits); | |
1078 | ||
1079 | /* Read the data. */ | |
1080 | word_in = ixgbe_shift_in_eeprom_bits(hw, 16); | |
1081 | data[i] = (word_in >> 8) | (word_in << 8); | |
68c7005d | 1082 | } |
c44ade9e | 1083 | |
e90dd264 MR |
1084 | /* End this read operation */ |
1085 | ixgbe_release_eeprom(hw); | |
1086 | ||
1087 | return 0; | |
68c7005d | 1088 | } |
c44ade9e | 1089 | |
68c7005d ET |
1090 | /** |
1091 | * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang | |
1092 | * @hw: pointer to hardware structure | |
1093 | * @offset: offset within the EEPROM to be read | |
1094 | * @data: read 16 bit value from EEPROM | |
1095 | * | |
1096 | * Reads 16 bit value from EEPROM through bit-bang method | |
1097 | **/ | |
1098 | s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, | |
1099 | u16 *data) | |
1100 | { | |
68c7005d ET |
1101 | hw->eeprom.ops.init_params(hw); |
1102 | ||
e90dd264 MR |
1103 | if (offset >= hw->eeprom.word_size) |
1104 | return IXGBE_ERR_EEPROM; | |
68c7005d | 1105 | |
e90dd264 | 1106 | return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); |
c44ade9e JB |
1107 | } |
1108 | ||
1109 | /** | |
68c7005d | 1110 | * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD |
9a799d71 | 1111 | * @hw: pointer to hardware structure |
68c7005d ET |
1112 | * @offset: offset of word in the EEPROM to read |
1113 | * @words: number of word(s) | |
1114 | * @data: 16 bit word(s) from the EEPROM | |
9a799d71 | 1115 | * |
68c7005d | 1116 | * Reads a 16 bit word(s) from the EEPROM using the EERD register. |
9a799d71 | 1117 | **/ |
68c7005d ET |
1118 | s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, |
1119 | u16 words, u16 *data) | |
9a799d71 AK |
1120 | { |
1121 | u32 eerd; | |
e90dd264 | 1122 | s32 status; |
68c7005d | 1123 | u32 i; |
9a799d71 | 1124 | |
c44ade9e JB |
1125 | hw->eeprom.ops.init_params(hw); |
1126 | ||
e90dd264 MR |
1127 | if (words == 0) |
1128 | return IXGBE_ERR_INVALID_ARGUMENT; | |
68c7005d | 1129 | |
e90dd264 MR |
1130 | if (offset >= hw->eeprom.word_size) |
1131 | return IXGBE_ERR_EEPROM; | |
c44ade9e | 1132 | |
68c7005d | 1133 | for (i = 0; i < words; i++) { |
d0111575 | 1134 | eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | |
68c7005d | 1135 | IXGBE_EEPROM_RW_REG_START; |
9a799d71 | 1136 | |
68c7005d ET |
1137 | IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); |
1138 | status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); | |
9a799d71 | 1139 | |
68c7005d ET |
1140 | if (status == 0) { |
1141 | data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> | |
1142 | IXGBE_EEPROM_RW_REG_DATA); | |
1143 | } else { | |
1144 | hw_dbg(hw, "Eeprom read timed out\n"); | |
e90dd264 | 1145 | return status; |
68c7005d ET |
1146 | } |
1147 | } | |
e90dd264 MR |
1148 | |
1149 | return 0; | |
68c7005d | 1150 | } |
9a799d71 | 1151 | |
68c7005d ET |
1152 | /** |
1153 | * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size | |
1154 | * @hw: pointer to hardware structure | |
1155 | * @offset: offset within the EEPROM to be used as a scratch pad | |
1156 | * | |
1157 | * Discover EEPROM page size by writing marching data at given offset. | |
1158 | * This function is called only when we are writing a new large buffer | |
1159 | * at given offset so the data would be overwritten anyway. | |
1160 | **/ | |
1161 | static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, | |
1162 | u16 offset) | |
1163 | { | |
1164 | u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; | |
e90dd264 | 1165 | s32 status; |
68c7005d ET |
1166 | u16 i; |
1167 | ||
1168 | for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) | |
1169 | data[i] = i; | |
1170 | ||
1171 | hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; | |
1172 | status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, | |
1173 | IXGBE_EEPROM_PAGE_SIZE_MAX, data); | |
1174 | hw->eeprom.word_page_size = 0; | |
e90dd264 MR |
1175 | if (status) |
1176 | return status; | |
68c7005d ET |
1177 | |
1178 | status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); | |
e90dd264 MR |
1179 | if (status) |
1180 | return status; | |
68c7005d ET |
1181 | |
1182 | /* | |
1183 | * When writing in burst more than the actual page size | |
1184 | * EEPROM address wraps around current page. | |
1185 | */ | |
1186 | hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; | |
1187 | ||
c5ffe7e1 | 1188 | hw_dbg(hw, "Detected EEPROM page size = %d words.\n", |
68c7005d | 1189 | hw->eeprom.word_page_size); |
e90dd264 | 1190 | return 0; |
9a799d71 AK |
1191 | } |
1192 | ||
eb9c3e3e | 1193 | /** |
68c7005d ET |
1194 | * ixgbe_read_eerd_generic - Read EEPROM word using EERD |
1195 | * @hw: pointer to hardware structure | |
1196 | * @offset: offset of word in the EEPROM to read | |
1197 | * @data: word read from the EEPROM | |
1198 | * | |
1199 | * Reads a 16 bit word from the EEPROM using the EERD register. | |
1200 | **/ | |
1201 | s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) | |
1202 | { | |
1203 | return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); | |
1204 | } | |
1205 | ||
1206 | /** | |
1207 | * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR | |
eb9c3e3e ET |
1208 | * @hw: pointer to hardware structure |
1209 | * @offset: offset of word in the EEPROM to write | |
68c7005d ET |
1210 | * @words: number of words |
1211 | * @data: word(s) write to the EEPROM | |
eb9c3e3e | 1212 | * |
68c7005d | 1213 | * Write a 16 bit word(s) to the EEPROM using the EEWR register. |
eb9c3e3e | 1214 | **/ |
68c7005d ET |
1215 | s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, |
1216 | u16 words, u16 *data) | |
eb9c3e3e ET |
1217 | { |
1218 | u32 eewr; | |
e90dd264 | 1219 | s32 status; |
68c7005d | 1220 | u16 i; |
eb9c3e3e ET |
1221 | |
1222 | hw->eeprom.ops.init_params(hw); | |
1223 | ||
e90dd264 MR |
1224 | if (words == 0) |
1225 | return IXGBE_ERR_INVALID_ARGUMENT; | |
68c7005d | 1226 | |
e90dd264 MR |
1227 | if (offset >= hw->eeprom.word_size) |
1228 | return IXGBE_ERR_EEPROM; | |
eb9c3e3e | 1229 | |
68c7005d ET |
1230 | for (i = 0; i < words; i++) { |
1231 | eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | | |
1232 | (data[i] << IXGBE_EEPROM_RW_REG_DATA) | | |
1233 | IXGBE_EEPROM_RW_REG_START; | |
eb9c3e3e | 1234 | |
68c7005d | 1235 | status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); |
e90dd264 | 1236 | if (status) { |
68c7005d | 1237 | hw_dbg(hw, "Eeprom write EEWR timed out\n"); |
e90dd264 | 1238 | return status; |
68c7005d | 1239 | } |
eb9c3e3e | 1240 | |
68c7005d | 1241 | IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); |
eb9c3e3e | 1242 | |
68c7005d | 1243 | status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); |
e90dd264 | 1244 | if (status) { |
68c7005d | 1245 | hw_dbg(hw, "Eeprom write EEWR timed out\n"); |
e90dd264 | 1246 | return status; |
68c7005d | 1247 | } |
eb9c3e3e ET |
1248 | } |
1249 | ||
e90dd264 | 1250 | return 0; |
eb9c3e3e ET |
1251 | } |
1252 | ||
68c7005d ET |
1253 | /** |
1254 | * ixgbe_write_eewr_generic - Write EEPROM word using EEWR | |
1255 | * @hw: pointer to hardware structure | |
1256 | * @offset: offset of word in the EEPROM to write | |
1257 | * @data: word write to the EEPROM | |
1258 | * | |
1259 | * Write a 16 bit word to the EEPROM using the EEWR register. | |
1260 | **/ | |
1261 | s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) | |
1262 | { | |
1263 | return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); | |
1264 | } | |
1265 | ||
9a799d71 | 1266 | /** |
21ce849b | 1267 | * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status |
9a799d71 | 1268 | * @hw: pointer to hardware structure |
21ce849b | 1269 | * @ee_reg: EEPROM flag for polling |
9a799d71 | 1270 | * |
21ce849b MC |
1271 | * Polls the status bit (bit 1) of the EERD or EEWR to determine when the |
1272 | * read or write is done respectively. | |
9a799d71 | 1273 | **/ |
eb9c3e3e | 1274 | static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) |
9a799d71 AK |
1275 | { |
1276 | u32 i; | |
1277 | u32 reg; | |
9a799d71 | 1278 | |
21ce849b MC |
1279 | for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { |
1280 | if (ee_reg == IXGBE_NVM_POLL_READ) | |
1281 | reg = IXGBE_READ_REG(hw, IXGBE_EERD); | |
1282 | else | |
1283 | reg = IXGBE_READ_REG(hw, IXGBE_EEWR); | |
1284 | ||
1285 | if (reg & IXGBE_EEPROM_RW_REG_DONE) { | |
e90dd264 | 1286 | return 0; |
9a799d71 AK |
1287 | } |
1288 | udelay(5); | |
1289 | } | |
e90dd264 | 1290 | return IXGBE_ERR_EEPROM; |
9a799d71 AK |
1291 | } |
1292 | ||
c44ade9e JB |
1293 | /** |
1294 | * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang | |
1295 | * @hw: pointer to hardware structure | |
1296 | * | |
1297 | * Prepares EEPROM for access using bit-bang method. This function should | |
1298 | * be called before issuing a command to the EEPROM. | |
1299 | **/ | |
1300 | static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) | |
1301 | { | |
dbf893ee | 1302 | u32 eec; |
c44ade9e JB |
1303 | u32 i; |
1304 | ||
5e655105 | 1305 | if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0) |
e90dd264 | 1306 | return IXGBE_ERR_SWFW_SYNC; |
c44ade9e | 1307 | |
9a900eca | 1308 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
c44ade9e | 1309 | |
e90dd264 MR |
1310 | /* Request EEPROM Access */ |
1311 | eec |= IXGBE_EEC_REQ; | |
9a900eca | 1312 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
c44ade9e | 1313 | |
e90dd264 | 1314 | for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { |
9a900eca | 1315 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
e90dd264 MR |
1316 | if (eec & IXGBE_EEC_GNT) |
1317 | break; | |
1318 | udelay(5); | |
1319 | } | |
c44ade9e | 1320 | |
e90dd264 MR |
1321 | /* Release if grant not acquired */ |
1322 | if (!(eec & IXGBE_EEC_GNT)) { | |
1323 | eec &= ~IXGBE_EEC_REQ; | |
9a900eca | 1324 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
e90dd264 | 1325 | hw_dbg(hw, "Could not acquire EEPROM grant\n"); |
c44ade9e | 1326 | |
e90dd264 MR |
1327 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
1328 | return IXGBE_ERR_EEPROM; | |
c44ade9e | 1329 | } |
e90dd264 MR |
1330 | |
1331 | /* Setup EEPROM for Read/Write */ | |
1332 | /* Clear CS and SK */ | |
1333 | eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); | |
9a900eca | 1334 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
e90dd264 MR |
1335 | IXGBE_WRITE_FLUSH(hw); |
1336 | udelay(1); | |
1337 | return 0; | |
c44ade9e JB |
1338 | } |
1339 | ||
9a799d71 AK |
1340 | /** |
1341 | * ixgbe_get_eeprom_semaphore - Get hardware semaphore | |
1342 | * @hw: pointer to hardware structure | |
1343 | * | |
1344 | * Sets the hardware semaphores so EEPROM access can occur for bit-bang method | |
1345 | **/ | |
1346 | static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) | |
1347 | { | |
dbf893ee | 1348 | u32 timeout = 2000; |
9a799d71 AK |
1349 | u32 i; |
1350 | u32 swsm; | |
1351 | ||
9a799d71 AK |
1352 | /* Get SMBI software semaphore between device drivers first */ |
1353 | for (i = 0; i < timeout; i++) { | |
1354 | /* | |
1355 | * If the SMBI bit is 0 when we read it, then the bit will be | |
1356 | * set and we have the semaphore | |
1357 | */ | |
9a900eca | 1358 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); |
e90dd264 | 1359 | if (!(swsm & IXGBE_SWSM_SMBI)) |
9a799d71 | 1360 | break; |
d819fc52 | 1361 | usleep_range(50, 100); |
9a799d71 AK |
1362 | } |
1363 | ||
51275d37 | 1364 | if (i == timeout) { |
6ec1b71f | 1365 | hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n"); |
e90dd264 | 1366 | /* this release is particularly important because our attempts |
51275d37 ET |
1367 | * above to get the semaphore may have succeeded, and if there |
1368 | * was a timeout, we should unconditionally clear the semaphore | |
1369 | * bits to free the driver to make progress | |
1370 | */ | |
1371 | ixgbe_release_eeprom_semaphore(hw); | |
1372 | ||
d819fc52 | 1373 | usleep_range(50, 100); |
e90dd264 | 1374 | /* one last try |
51275d37 ET |
1375 | * If the SMBI bit is 0 when we read it, then the bit will be |
1376 | * set and we have the semaphore | |
1377 | */ | |
9a900eca | 1378 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); |
e90dd264 MR |
1379 | if (swsm & IXGBE_SWSM_SMBI) { |
1380 | hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n"); | |
1381 | return IXGBE_ERR_EEPROM; | |
1382 | } | |
51275d37 ET |
1383 | } |
1384 | ||
9a799d71 | 1385 | /* Now get the semaphore between SW/FW through the SWESMBI bit */ |
e90dd264 | 1386 | for (i = 0; i < timeout; i++) { |
9a900eca | 1387 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); |
9a799d71 | 1388 | |
e90dd264 MR |
1389 | /* Set the SW EEPROM semaphore bit to request access */ |
1390 | swsm |= IXGBE_SWSM_SWESMBI; | |
9a900eca | 1391 | IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); |
9a799d71 | 1392 | |
e90dd264 MR |
1393 | /* If we set the bit successfully then we got the |
1394 | * semaphore. | |
1395 | */ | |
9a900eca | 1396 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); |
e90dd264 MR |
1397 | if (swsm & IXGBE_SWSM_SWESMBI) |
1398 | break; | |
9a799d71 | 1399 | |
e90dd264 MR |
1400 | usleep_range(50, 100); |
1401 | } | |
9a799d71 | 1402 | |
e90dd264 MR |
1403 | /* Release semaphores and return error if SW EEPROM semaphore |
1404 | * was not granted because we don't have access to the EEPROM | |
1405 | */ | |
1406 | if (i >= timeout) { | |
1407 | hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n"); | |
1408 | ixgbe_release_eeprom_semaphore(hw); | |
1409 | return IXGBE_ERR_EEPROM; | |
9a799d71 AK |
1410 | } |
1411 | ||
e90dd264 | 1412 | return 0; |
9a799d71 AK |
1413 | } |
1414 | ||
1415 | /** | |
1416 | * ixgbe_release_eeprom_semaphore - Release hardware semaphore | |
1417 | * @hw: pointer to hardware structure | |
1418 | * | |
1419 | * This function clears hardware semaphore bits. | |
1420 | **/ | |
1421 | static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) | |
1422 | { | |
1423 | u32 swsm; | |
1424 | ||
9a900eca | 1425 | swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw)); |
9a799d71 AK |
1426 | |
1427 | /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ | |
1428 | swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); | |
9a900eca | 1429 | IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm); |
3957d63d | 1430 | IXGBE_WRITE_FLUSH(hw); |
9a799d71 AK |
1431 | } |
1432 | ||
c44ade9e JB |
1433 | /** |
1434 | * ixgbe_ready_eeprom - Polls for EEPROM ready | |
1435 | * @hw: pointer to hardware structure | |
1436 | **/ | |
1437 | static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) | |
1438 | { | |
c44ade9e JB |
1439 | u16 i; |
1440 | u8 spi_stat_reg; | |
1441 | ||
1442 | /* | |
1443 | * Read "Status Register" repeatedly until the LSB is cleared. The | |
1444 | * EEPROM will signal that the command has been completed by clearing | |
1445 | * bit 0 of the internal status register. If it's not cleared within | |
1446 | * 5 milliseconds, then error out. | |
1447 | */ | |
1448 | for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { | |
1449 | ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, | |
e7cf745b | 1450 | IXGBE_EEPROM_OPCODE_BITS); |
c44ade9e JB |
1451 | spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); |
1452 | if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) | |
1453 | break; | |
1454 | ||
1455 | udelay(5); | |
1456 | ixgbe_standby_eeprom(hw); | |
6403eab1 | 1457 | } |
c44ade9e JB |
1458 | |
1459 | /* | |
1460 | * On some parts, SPI write time could vary from 0-20mSec on 3.3V | |
1461 | * devices (and only 0-5mSec on 5V devices) | |
1462 | */ | |
1463 | if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { | |
1464 | hw_dbg(hw, "SPI EEPROM Status error\n"); | |
e90dd264 | 1465 | return IXGBE_ERR_EEPROM; |
c44ade9e JB |
1466 | } |
1467 | ||
e90dd264 | 1468 | return 0; |
c44ade9e JB |
1469 | } |
1470 | ||
1471 | /** | |
1472 | * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state | |
1473 | * @hw: pointer to hardware structure | |
1474 | **/ | |
1475 | static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) | |
1476 | { | |
1477 | u32 eec; | |
1478 | ||
9a900eca | 1479 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
c44ade9e JB |
1480 | |
1481 | /* Toggle CS to flush commands */ | |
1482 | eec |= IXGBE_EEC_CS; | |
9a900eca | 1483 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
c44ade9e JB |
1484 | IXGBE_WRITE_FLUSH(hw); |
1485 | udelay(1); | |
1486 | eec &= ~IXGBE_EEC_CS; | |
9a900eca | 1487 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
c44ade9e JB |
1488 | IXGBE_WRITE_FLUSH(hw); |
1489 | udelay(1); | |
1490 | } | |
1491 | ||
1492 | /** | |
1493 | * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. | |
1494 | * @hw: pointer to hardware structure | |
1495 | * @data: data to send to the EEPROM | |
1496 | * @count: number of bits to shift out | |
1497 | **/ | |
1498 | static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, | |
e7cf745b | 1499 | u16 count) |
c44ade9e JB |
1500 | { |
1501 | u32 eec; | |
1502 | u32 mask; | |
1503 | u32 i; | |
1504 | ||
9a900eca | 1505 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
c44ade9e JB |
1506 | |
1507 | /* | |
1508 | * Mask is used to shift "count" bits of "data" out to the EEPROM | |
1509 | * one bit at a time. Determine the starting bit based on count | |
1510 | */ | |
b4f47a48 | 1511 | mask = BIT(count - 1); |
c44ade9e JB |
1512 | |
1513 | for (i = 0; i < count; i++) { | |
1514 | /* | |
1515 | * A "1" is shifted out to the EEPROM by setting bit "DI" to a | |
1516 | * "1", and then raising and then lowering the clock (the SK | |
1517 | * bit controls the clock input to the EEPROM). A "0" is | |
1518 | * shifted out to the EEPROM by setting "DI" to "0" and then | |
1519 | * raising and then lowering the clock. | |
1520 | */ | |
1521 | if (data & mask) | |
1522 | eec |= IXGBE_EEC_DI; | |
1523 | else | |
1524 | eec &= ~IXGBE_EEC_DI; | |
1525 | ||
9a900eca | 1526 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
c44ade9e JB |
1527 | IXGBE_WRITE_FLUSH(hw); |
1528 | ||
1529 | udelay(1); | |
1530 | ||
1531 | ixgbe_raise_eeprom_clk(hw, &eec); | |
1532 | ixgbe_lower_eeprom_clk(hw, &eec); | |
1533 | ||
1534 | /* | |
1535 | * Shift mask to signify next bit of data to shift in to the | |
1536 | * EEPROM | |
1537 | */ | |
1538 | mask = mask >> 1; | |
6403eab1 | 1539 | } |
c44ade9e JB |
1540 | |
1541 | /* We leave the "DI" bit set to "0" when we leave this routine. */ | |
1542 | eec &= ~IXGBE_EEC_DI; | |
9a900eca | 1543 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
c44ade9e JB |
1544 | IXGBE_WRITE_FLUSH(hw); |
1545 | } | |
1546 | ||
1547 | /** | |
1548 | * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM | |
1549 | * @hw: pointer to hardware structure | |
1550 | **/ | |
1551 | static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) | |
1552 | { | |
1553 | u32 eec; | |
1554 | u32 i; | |
1555 | u16 data = 0; | |
1556 | ||
1557 | /* | |
1558 | * In order to read a register from the EEPROM, we need to shift | |
1559 | * 'count' bits in from the EEPROM. Bits are "shifted in" by raising | |
1560 | * the clock input to the EEPROM (setting the SK bit), and then reading | |
1561 | * the value of the "DO" bit. During this "shifting in" process the | |
1562 | * "DI" bit should always be clear. | |
1563 | */ | |
9a900eca | 1564 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
c44ade9e JB |
1565 | |
1566 | eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); | |
1567 | ||
1568 | for (i = 0; i < count; i++) { | |
1569 | data = data << 1; | |
1570 | ixgbe_raise_eeprom_clk(hw, &eec); | |
1571 | ||
9a900eca | 1572 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
c44ade9e JB |
1573 | |
1574 | eec &= ~(IXGBE_EEC_DI); | |
1575 | if (eec & IXGBE_EEC_DO) | |
1576 | data |= 1; | |
1577 | ||
1578 | ixgbe_lower_eeprom_clk(hw, &eec); | |
1579 | } | |
1580 | ||
1581 | return data; | |
1582 | } | |
1583 | ||
1584 | /** | |
1585 | * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. | |
1586 | * @hw: pointer to hardware structure | |
1587 | * @eec: EEC register's current value | |
1588 | **/ | |
1589 | static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | |
1590 | { | |
1591 | /* | |
1592 | * Raise the clock input to the EEPROM | |
1593 | * (setting the SK bit), then delay | |
1594 | */ | |
1595 | *eec = *eec | IXGBE_EEC_SK; | |
9a900eca | 1596 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); |
c44ade9e JB |
1597 | IXGBE_WRITE_FLUSH(hw); |
1598 | udelay(1); | |
1599 | } | |
1600 | ||
1601 | /** | |
1602 | * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. | |
1603 | * @hw: pointer to hardware structure | |
1604 | * @eecd: EECD's current value | |
1605 | **/ | |
1606 | static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) | |
1607 | { | |
1608 | /* | |
1609 | * Lower the clock input to the EEPROM (clearing the SK bit), then | |
1610 | * delay | |
1611 | */ | |
1612 | *eec = *eec & ~IXGBE_EEC_SK; | |
9a900eca | 1613 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec); |
c44ade9e JB |
1614 | IXGBE_WRITE_FLUSH(hw); |
1615 | udelay(1); | |
1616 | } | |
1617 | ||
1618 | /** | |
1619 | * ixgbe_release_eeprom - Release EEPROM, release semaphores | |
1620 | * @hw: pointer to hardware structure | |
1621 | **/ | |
1622 | static void ixgbe_release_eeprom(struct ixgbe_hw *hw) | |
1623 | { | |
1624 | u32 eec; | |
1625 | ||
9a900eca | 1626 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
c44ade9e JB |
1627 | |
1628 | eec |= IXGBE_EEC_CS; /* Pull CS high */ | |
1629 | eec &= ~IXGBE_EEC_SK; /* Lower SCK */ | |
1630 | ||
9a900eca | 1631 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
c44ade9e JB |
1632 | IXGBE_WRITE_FLUSH(hw); |
1633 | ||
1634 | udelay(1); | |
1635 | ||
1636 | /* Stop requesting EEPROM access */ | |
1637 | eec &= ~IXGBE_EEC_REQ; | |
9a900eca | 1638 | IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec); |
c44ade9e | 1639 | |
90827996 | 1640 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); |
dbf893ee | 1641 | |
032b4325 DS |
1642 | /* |
1643 | * Delay before attempt to obtain semaphore again to allow FW | |
1644 | * access. semaphore_delay is in ms we need us for usleep_range | |
1645 | */ | |
1646 | usleep_range(hw->eeprom.semaphore_delay * 1000, | |
1647 | hw->eeprom.semaphore_delay * 2000); | |
c44ade9e JB |
1648 | } |
1649 | ||
9a799d71 | 1650 | /** |
dbf893ee | 1651 | * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum |
9a799d71 AK |
1652 | * @hw: pointer to hardware structure |
1653 | **/ | |
735c35af | 1654 | s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
1655 | { |
1656 | u16 i; | |
1657 | u16 j; | |
1658 | u16 checksum = 0; | |
1659 | u16 length = 0; | |
1660 | u16 pointer = 0; | |
1661 | u16 word = 0; | |
1662 | ||
1663 | /* Include 0x0-0x3F in the checksum */ | |
1664 | for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { | |
735c35af | 1665 | if (hw->eeprom.ops.read(hw, i, &word)) { |
9a799d71 AK |
1666 | hw_dbg(hw, "EEPROM read failed\n"); |
1667 | break; | |
1668 | } | |
1669 | checksum += word; | |
1670 | } | |
1671 | ||
1672 | /* Include all data from pointers except for the fw pointer */ | |
1673 | for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { | |
735c35af DS |
1674 | if (hw->eeprom.ops.read(hw, i, &pointer)) { |
1675 | hw_dbg(hw, "EEPROM read failed\n"); | |
1676 | return IXGBE_ERR_EEPROM; | |
1677 | } | |
1678 | ||
1679 | /* If the pointer seems invalid */ | |
1680 | if (pointer == 0xFFFF || pointer == 0) | |
1681 | continue; | |
1682 | ||
1683 | if (hw->eeprom.ops.read(hw, pointer, &length)) { | |
1684 | hw_dbg(hw, "EEPROM read failed\n"); | |
1685 | return IXGBE_ERR_EEPROM; | |
1686 | } | |
9a799d71 | 1687 | |
735c35af DS |
1688 | if (length == 0xFFFF || length == 0) |
1689 | continue; | |
9a799d71 | 1690 | |
735c35af DS |
1691 | for (j = pointer + 1; j <= pointer + length; j++) { |
1692 | if (hw->eeprom.ops.read(hw, j, &word)) { | |
1693 | hw_dbg(hw, "EEPROM read failed\n"); | |
1694 | return IXGBE_ERR_EEPROM; | |
9a799d71 | 1695 | } |
735c35af | 1696 | checksum += word; |
9a799d71 AK |
1697 | } |
1698 | } | |
1699 | ||
1700 | checksum = (u16)IXGBE_EEPROM_SUM - checksum; | |
1701 | ||
735c35af | 1702 | return (s32)checksum; |
9a799d71 AK |
1703 | } |
1704 | ||
1705 | /** | |
c44ade9e | 1706 | * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum |
9a799d71 AK |
1707 | * @hw: pointer to hardware structure |
1708 | * @checksum_val: calculated checksum | |
1709 | * | |
1710 | * Performs checksum calculation and validates the EEPROM checksum. If the | |
1711 | * caller does not need checksum_val, the value can be NULL. | |
1712 | **/ | |
c44ade9e | 1713 | s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, |
e7cf745b | 1714 | u16 *checksum_val) |
9a799d71 AK |
1715 | { |
1716 | s32 status; | |
1717 | u16 checksum; | |
1718 | u16 read_checksum = 0; | |
1719 | ||
1720 | /* | |
1721 | * Read the first word from the EEPROM. If this times out or fails, do | |
1722 | * not continue or we could be in for a very long wait while every | |
1723 | * EEPROM read fails | |
1724 | */ | |
c44ade9e | 1725 | status = hw->eeprom.ops.read(hw, 0, &checksum); |
735c35af DS |
1726 | if (status) { |
1727 | hw_dbg(hw, "EEPROM read failed\n"); | |
1728 | return status; | |
1729 | } | |
9a799d71 | 1730 | |
735c35af DS |
1731 | status = hw->eeprom.ops.calc_checksum(hw); |
1732 | if (status < 0) | |
1733 | return status; | |
9a799d71 | 1734 | |
735c35af | 1735 | checksum = (u16)(status & 0xffff); |
9a799d71 | 1736 | |
735c35af DS |
1737 | status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); |
1738 | if (status) { | |
9a799d71 | 1739 | hw_dbg(hw, "EEPROM read failed\n"); |
735c35af | 1740 | return status; |
9a799d71 AK |
1741 | } |
1742 | ||
735c35af DS |
1743 | /* Verify read checksum from EEPROM is the same as |
1744 | * calculated checksum | |
1745 | */ | |
1746 | if (read_checksum != checksum) | |
1747 | status = IXGBE_ERR_EEPROM_CHECKSUM; | |
1748 | ||
1749 | /* If the user cares, return the calculated checksum */ | |
1750 | if (checksum_val) | |
1751 | *checksum_val = checksum; | |
1752 | ||
9a799d71 AK |
1753 | return status; |
1754 | } | |
1755 | ||
c44ade9e JB |
1756 | /** |
1757 | * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum | |
1758 | * @hw: pointer to hardware structure | |
1759 | **/ | |
1760 | s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) | |
1761 | { | |
1762 | s32 status; | |
1763 | u16 checksum; | |
1764 | ||
1765 | /* | |
1766 | * Read the first word from the EEPROM. If this times out or fails, do | |
1767 | * not continue or we could be in for a very long wait while every | |
1768 | * EEPROM read fails | |
1769 | */ | |
1770 | status = hw->eeprom.ops.read(hw, 0, &checksum); | |
735c35af | 1771 | if (status) { |
c44ade9e | 1772 | hw_dbg(hw, "EEPROM read failed\n"); |
735c35af | 1773 | return status; |
c44ade9e JB |
1774 | } |
1775 | ||
735c35af DS |
1776 | status = hw->eeprom.ops.calc_checksum(hw); |
1777 | if (status < 0) | |
1778 | return status; | |
1779 | ||
1780 | checksum = (u16)(status & 0xffff); | |
1781 | ||
1782 | status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); | |
1783 | ||
c44ade9e JB |
1784 | return status; |
1785 | } | |
1786 | ||
9a799d71 | 1787 | /** |
c44ade9e | 1788 | * ixgbe_set_rar_generic - Set Rx address register |
9a799d71 | 1789 | * @hw: pointer to hardware structure |
9a799d71 | 1790 | * @index: Receive address register to write |
c44ade9e JB |
1791 | * @addr: Address to put into receive address register |
1792 | * @vmdq: VMDq "set" or "pool" index | |
9a799d71 AK |
1793 | * @enable_addr: set flag that address is active |
1794 | * | |
1795 | * Puts an ethernet address into a receive address register. | |
1796 | **/ | |
c44ade9e | 1797 | s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, |
e7cf745b | 1798 | u32 enable_addr) |
9a799d71 AK |
1799 | { |
1800 | u32 rar_low, rar_high; | |
c44ade9e JB |
1801 | u32 rar_entries = hw->mac.num_rar_entries; |
1802 | ||
c700f4e6 ET |
1803 | /* Make sure we are using a valid rar index range */ |
1804 | if (index >= rar_entries) { | |
1805 | hw_dbg(hw, "RAR index %d is out of range.\n", index); | |
1806 | return IXGBE_ERR_INVALID_ARGUMENT; | |
1807 | } | |
1808 | ||
c44ade9e JB |
1809 | /* setup VMDq pool selection before this RAR gets enabled */ |
1810 | hw->mac.ops.set_vmdq(hw, index, vmdq); | |
9a799d71 | 1811 | |
c700f4e6 ET |
1812 | /* |
1813 | * HW expects these in little endian so we reverse the byte | |
1814 | * order from network order (big endian) to little endian | |
1815 | */ | |
1816 | rar_low = ((u32)addr[0] | | |
1817 | ((u32)addr[1] << 8) | | |
1818 | ((u32)addr[2] << 16) | | |
1819 | ((u32)addr[3] << 24)); | |
1820 | /* | |
1821 | * Some parts put the VMDq setting in the extra RAH bits, | |
1822 | * so save everything except the lower 16 bits that hold part | |
1823 | * of the address and the address valid bit. | |
1824 | */ | |
1825 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1826 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); | |
1827 | rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); | |
9a799d71 | 1828 | |
c700f4e6 ET |
1829 | if (enable_addr != 0) |
1830 | rar_high |= IXGBE_RAH_AV; | |
9a799d71 | 1831 | |
c700f4e6 ET |
1832 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); |
1833 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
c44ade9e JB |
1834 | |
1835 | return 0; | |
1836 | } | |
1837 | ||
1838 | /** | |
1839 | * ixgbe_clear_rar_generic - Remove Rx address register | |
1840 | * @hw: pointer to hardware structure | |
1841 | * @index: Receive address register to write | |
1842 | * | |
1843 | * Clears an ethernet address from a receive address register. | |
1844 | **/ | |
1845 | s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) | |
1846 | { | |
1847 | u32 rar_high; | |
1848 | u32 rar_entries = hw->mac.num_rar_entries; | |
1849 | ||
1850 | /* Make sure we are using a valid rar index range */ | |
c700f4e6 | 1851 | if (index >= rar_entries) { |
c44ade9e | 1852 | hw_dbg(hw, "RAR index %d is out of range.\n", index); |
c700f4e6 | 1853 | return IXGBE_ERR_INVALID_ARGUMENT; |
c44ade9e JB |
1854 | } |
1855 | ||
c700f4e6 ET |
1856 | /* |
1857 | * Some parts put the VMDq setting in the extra RAH bits, | |
1858 | * so save everything except the lower 16 bits that hold part | |
1859 | * of the address and the address valid bit. | |
1860 | */ | |
1861 | rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); | |
1862 | rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); | |
1863 | ||
1864 | IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); | |
1865 | IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); | |
1866 | ||
c44ade9e JB |
1867 | /* clear VMDq pool/queue selection for this RAR */ |
1868 | hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); | |
9a799d71 AK |
1869 | |
1870 | return 0; | |
1871 | } | |
1872 | ||
c44ade9e JB |
1873 | /** |
1874 | * ixgbe_init_rx_addrs_generic - Initializes receive address filters. | |
9a799d71 AK |
1875 | * @hw: pointer to hardware structure |
1876 | * | |
1877 | * Places the MAC address in receive address register 0 and clears the rest | |
c44ade9e | 1878 | * of the receive address registers. Clears the multicast table. Assumes |
9a799d71 AK |
1879 | * the receiver is in reset when the routine is called. |
1880 | **/ | |
c44ade9e | 1881 | s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) |
9a799d71 AK |
1882 | { |
1883 | u32 i; | |
2c5645cf | 1884 | u32 rar_entries = hw->mac.num_rar_entries; |
9a799d71 AK |
1885 | |
1886 | /* | |
1887 | * If the current mac address is valid, assume it is a software override | |
1888 | * to the permanent address. | |
1889 | * Otherwise, use the permanent address from the eeprom. | |
1890 | */ | |
f8ebc683 | 1891 | if (!is_valid_ether_addr(hw->mac.addr)) { |
9a799d71 | 1892 | /* Get the MAC address from the RAR0 for later reference */ |
c44ade9e | 1893 | hw->mac.ops.get_mac_addr(hw, hw->mac.addr); |
9a799d71 | 1894 | |
ce7194d8 | 1895 | hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr); |
9a799d71 AK |
1896 | } else { |
1897 | /* Setup the receive address. */ | |
1898 | hw_dbg(hw, "Overriding MAC Address in RAR[0]\n"); | |
ce7194d8 | 1899 | hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr); |
9a799d71 | 1900 | |
c44ade9e | 1901 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); |
9a799d71 | 1902 | } |
6e982aea AD |
1903 | |
1904 | /* clear VMDq pool/queue selection for RAR 0 */ | |
1905 | hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); | |
1906 | ||
c44ade9e | 1907 | hw->addr_ctrl.overflow_promisc = 0; |
9a799d71 AK |
1908 | |
1909 | hw->addr_ctrl.rar_used_count = 1; | |
1910 | ||
1911 | /* Zero out the other receive addresses. */ | |
c44ade9e | 1912 | hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1); |
9a799d71 AK |
1913 | for (i = 1; i < rar_entries; i++) { |
1914 | IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); | |
1915 | IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); | |
1916 | } | |
1917 | ||
1918 | /* Clear the MTA */ | |
9a799d71 AK |
1919 | hw->addr_ctrl.mta_in_use = 0; |
1920 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); | |
1921 | ||
1922 | hw_dbg(hw, " Clearing MTA\n"); | |
2c5645cf | 1923 | for (i = 0; i < hw->mac.mcft_size; i++) |
9a799d71 AK |
1924 | IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); |
1925 | ||
c44ade9e JB |
1926 | if (hw->mac.ops.init_uta_tables) |
1927 | hw->mac.ops.init_uta_tables(hw); | |
1928 | ||
9a799d71 AK |
1929 | return 0; |
1930 | } | |
1931 | ||
1932 | /** | |
1933 | * ixgbe_mta_vector - Determines bit-vector in multicast table to set | |
1934 | * @hw: pointer to hardware structure | |
1935 | * @mc_addr: the multicast address | |
1936 | * | |
1937 | * Extracts the 12 bits, from a multicast address, to determine which | |
1938 | * bit-vector to set in the multicast table. The hardware uses 12 bits, from | |
1939 | * incoming rx multicast addresses, to determine the bit-vector to check in | |
1940 | * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set | |
c44ade9e | 1941 | * by the MO field of the MCSTCTRL. The MO field is set during initialization |
9a799d71 AK |
1942 | * to mc_filter_type. |
1943 | **/ | |
1944 | static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) | |
1945 | { | |
1946 | u32 vector = 0; | |
1947 | ||
1948 | switch (hw->mac.mc_filter_type) { | |
b4617240 | 1949 | case 0: /* use bits [47:36] of the address */ |
9a799d71 AK |
1950 | vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); |
1951 | break; | |
b4617240 | 1952 | case 1: /* use bits [46:35] of the address */ |
9a799d71 AK |
1953 | vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); |
1954 | break; | |
b4617240 | 1955 | case 2: /* use bits [45:34] of the address */ |
9a799d71 AK |
1956 | vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); |
1957 | break; | |
b4617240 | 1958 | case 3: /* use bits [43:32] of the address */ |
9a799d71 AK |
1959 | vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); |
1960 | break; | |
b4617240 | 1961 | default: /* Invalid mc_filter_type */ |
9a799d71 AK |
1962 | hw_dbg(hw, "MC filter type param set incorrectly\n"); |
1963 | break; | |
1964 | } | |
1965 | ||
1966 | /* vector can only be 12-bits or boundary will be exceeded */ | |
1967 | vector &= 0xFFF; | |
1968 | return vector; | |
1969 | } | |
1970 | ||
1971 | /** | |
1972 | * ixgbe_set_mta - Set bit-vector in multicast table | |
1973 | * @hw: pointer to hardware structure | |
1974 | * @hash_value: Multicast address hash value | |
1975 | * | |
1976 | * Sets the bit-vector in the multicast table. | |
1977 | **/ | |
1978 | static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) | |
1979 | { | |
1980 | u32 vector; | |
1981 | u32 vector_bit; | |
1982 | u32 vector_reg; | |
9a799d71 AK |
1983 | |
1984 | hw->addr_ctrl.mta_in_use++; | |
1985 | ||
1986 | vector = ixgbe_mta_vector(hw, mc_addr); | |
1987 | hw_dbg(hw, " bit-vector = 0x%03X\n", vector); | |
1988 | ||
1989 | /* | |
1990 | * The MTA is a register array of 128 32-bit registers. It is treated | |
1991 | * like an array of 4096 bits. We want to set bit | |
1992 | * BitArray[vector_value]. So we figure out what register the bit is | |
1993 | * in, read it, OR in the new bit, then write back the new value. The | |
1994 | * register is determined by the upper 7 bits of the vector value and | |
1995 | * the bit within that register are determined by the lower 5 bits of | |
1996 | * the value. | |
1997 | */ | |
1998 | vector_reg = (vector >> 5) & 0x7F; | |
1999 | vector_bit = vector & 0x1F; | |
b4f47a48 | 2000 | hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit); |
9a799d71 AK |
2001 | } |
2002 | ||
9a799d71 | 2003 | /** |
c44ade9e | 2004 | * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses |
9a799d71 | 2005 | * @hw: pointer to hardware structure |
2853eb89 | 2006 | * @netdev: pointer to net device structure |
9a799d71 AK |
2007 | * |
2008 | * The given list replaces any existing list. Clears the MC addrs from receive | |
c44ade9e | 2009 | * address registers and the multicast table. Uses unused receive address |
9a799d71 AK |
2010 | * registers for the first multicast addresses, and hashes the rest into the |
2011 | * multicast table. | |
2012 | **/ | |
2853eb89 JP |
2013 | s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, |
2014 | struct net_device *netdev) | |
9a799d71 | 2015 | { |
22bedad3 | 2016 | struct netdev_hw_addr *ha; |
9a799d71 | 2017 | u32 i; |
9a799d71 AK |
2018 | |
2019 | /* | |
2020 | * Set the new number of MC addresses that we are being requested to | |
2021 | * use. | |
2022 | */ | |
2853eb89 | 2023 | hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); |
9a799d71 AK |
2024 | hw->addr_ctrl.mta_in_use = 0; |
2025 | ||
80960ab0 | 2026 | /* Clear mta_shadow */ |
9a799d71 | 2027 | hw_dbg(hw, " Clearing MTA\n"); |
80960ab0 | 2028 | memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); |
9a799d71 | 2029 | |
80960ab0 | 2030 | /* Update mta shadow */ |
22bedad3 | 2031 | netdev_for_each_mc_addr(ha, netdev) { |
9a799d71 | 2032 | hw_dbg(hw, " Adding the multicast addresses:\n"); |
22bedad3 | 2033 | ixgbe_set_mta(hw, ha->addr); |
9a799d71 AK |
2034 | } |
2035 | ||
2036 | /* Enable mta */ | |
80960ab0 ET |
2037 | for (i = 0; i < hw->mac.mcft_size; i++) |
2038 | IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, | |
2039 | hw->mac.mta_shadow[i]); | |
2040 | ||
9a799d71 AK |
2041 | if (hw->addr_ctrl.mta_in_use > 0) |
2042 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, | |
e7cf745b | 2043 | IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); |
9a799d71 | 2044 | |
c44ade9e | 2045 | hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n"); |
9a799d71 AK |
2046 | return 0; |
2047 | } | |
2048 | ||
2049 | /** | |
c44ade9e | 2050 | * ixgbe_enable_mc_generic - Enable multicast address in RAR |
9a799d71 AK |
2051 | * @hw: pointer to hardware structure |
2052 | * | |
c44ade9e | 2053 | * Enables multicast address in RAR and the use of the multicast hash table. |
9a799d71 | 2054 | **/ |
c44ade9e | 2055 | s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) |
9a799d71 | 2056 | { |
c44ade9e | 2057 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; |
9a799d71 | 2058 | |
c44ade9e JB |
2059 | if (a->mta_in_use > 0) |
2060 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | | |
e7cf745b | 2061 | hw->mac.mc_filter_type); |
9a799d71 AK |
2062 | |
2063 | return 0; | |
2064 | } | |
2065 | ||
2066 | /** | |
c44ade9e | 2067 | * ixgbe_disable_mc_generic - Disable multicast address in RAR |
9a799d71 | 2068 | * @hw: pointer to hardware structure |
9a799d71 | 2069 | * |
c44ade9e | 2070 | * Disables multicast address in RAR and the use of the multicast hash table. |
9a799d71 | 2071 | **/ |
c44ade9e | 2072 | s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) |
9a799d71 | 2073 | { |
c44ade9e | 2074 | struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; |
2b9ade93 | 2075 | |
c44ade9e JB |
2076 | if (a->mta_in_use > 0) |
2077 | IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); | |
9a799d71 AK |
2078 | |
2079 | return 0; | |
2080 | } | |
2081 | ||
11afc1b1 | 2082 | /** |
620fa036 | 2083 | * ixgbe_fc_enable_generic - Enable flow control |
11afc1b1 | 2084 | * @hw: pointer to hardware structure |
11afc1b1 PW |
2085 | * |
2086 | * Enable flow control according to the current settings. | |
2087 | **/ | |
041441d0 | 2088 | s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) |
11afc1b1 | 2089 | { |
620fa036 | 2090 | u32 mflcn_reg, fccfg_reg; |
11afc1b1 | 2091 | u32 reg; |
16b61beb | 2092 | u32 fcrtl, fcrth; |
041441d0 | 2093 | int i; |
70b77628 | 2094 | |
e5776620 | 2095 | /* Validate the water mark configuration. */ |
e90dd264 MR |
2096 | if (!hw->fc.pause_time) |
2097 | return IXGBE_ERR_INVALID_LINK_SETTINGS; | |
70b77628 | 2098 | |
e5776620 JK |
2099 | /* Low water mark of zero causes XOFF floods */ |
2100 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
2101 | if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && | |
2102 | hw->fc.high_water[i]) { | |
2103 | if (!hw->fc.low_water[i] || | |
2104 | hw->fc.low_water[i] >= hw->fc.high_water[i]) { | |
2105 | hw_dbg(hw, "Invalid water mark configuration\n"); | |
e90dd264 | 2106 | return IXGBE_ERR_INVALID_LINK_SETTINGS; |
e5776620 JK |
2107 | } |
2108 | } | |
2109 | } | |
2110 | ||
620fa036 | 2111 | /* Negotiate the fc mode to use */ |
786e9a5f | 2112 | ixgbe_fc_autoneg(hw); |
11afc1b1 | 2113 | |
620fa036 | 2114 | /* Disable any previous flow control settings */ |
11afc1b1 | 2115 | mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); |
041441d0 | 2116 | mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); |
11afc1b1 PW |
2117 | |
2118 | fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
2119 | fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); | |
2120 | ||
2121 | /* | |
2122 | * The possible values of fc.current_mode are: | |
2123 | * 0: Flow control is completely disabled | |
2124 | * 1: Rx flow control is enabled (we can receive pause frames, | |
2125 | * but not send pause frames). | |
bb3daa4a PW |
2126 | * 2: Tx flow control is enabled (we can send pause frames but |
2127 | * we do not support receiving pause frames). | |
11afc1b1 PW |
2128 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
2129 | * other: Invalid. | |
2130 | */ | |
2131 | switch (hw->fc.current_mode) { | |
2132 | case ixgbe_fc_none: | |
620fa036 MC |
2133 | /* |
2134 | * Flow control is disabled by software override or autoneg. | |
2135 | * The code below will actually disable it in the HW. | |
2136 | */ | |
11afc1b1 PW |
2137 | break; |
2138 | case ixgbe_fc_rx_pause: | |
2139 | /* | |
2140 | * Rx Flow control is enabled and Tx Flow control is | |
2141 | * disabled by software override. Since there really | |
2142 | * isn't a way to advertise that we are capable of RX | |
2143 | * Pause ONLY, we will advertise that we support both | |
2144 | * symmetric and asymmetric Rx PAUSE. Later, we will | |
2145 | * disable the adapter's ability to send PAUSE frames. | |
2146 | */ | |
2147 | mflcn_reg |= IXGBE_MFLCN_RFCE; | |
2148 | break; | |
2149 | case ixgbe_fc_tx_pause: | |
2150 | /* | |
2151 | * Tx Flow control is enabled, and Rx Flow control is | |
2152 | * disabled by software override. | |
2153 | */ | |
2154 | fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; | |
2155 | break; | |
2156 | case ixgbe_fc_full: | |
2157 | /* Flow control (both Rx and Tx) is enabled by SW override. */ | |
2158 | mflcn_reg |= IXGBE_MFLCN_RFCE; | |
2159 | fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; | |
2160 | break; | |
2161 | default: | |
2162 | hw_dbg(hw, "Flow control param set incorrectly\n"); | |
e90dd264 | 2163 | return IXGBE_ERR_CONFIG; |
11afc1b1 PW |
2164 | } |
2165 | ||
620fa036 | 2166 | /* Set 802.3x based flow control settings. */ |
2132d381 | 2167 | mflcn_reg |= IXGBE_MFLCN_DPF; |
11afc1b1 PW |
2168 | IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); |
2169 | IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); | |
2170 | ||
041441d0 AD |
2171 | /* Set up and enable Rx high/low water mark thresholds, enable XON. */ |
2172 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
2173 | if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && | |
2174 | hw->fc.high_water[i]) { | |
e5776620 | 2175 | fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; |
041441d0 AD |
2176 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); |
2177 | fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; | |
2178 | } else { | |
2179 | IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); | |
2180 | /* | |
2181 | * In order to prevent Tx hangs when the internal Tx | |
2182 | * switch is enabled we must set the high water mark | |
bc1fc64f MR |
2183 | * to the Rx packet buffer size - 24KB. This allows |
2184 | * the Tx switch to function even under heavy Rx | |
2185 | * workloads. | |
041441d0 | 2186 | */ |
bc1fc64f | 2187 | fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; |
041441d0 | 2188 | } |
11afc1b1 | 2189 | |
041441d0 AD |
2190 | IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); |
2191 | } | |
16b61beb | 2192 | |
11afc1b1 | 2193 | /* Configure pause time (2 TCs per register) */ |
041441d0 AD |
2194 | reg = hw->fc.pause_time * 0x00010001; |
2195 | for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++) | |
2196 | IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); | |
2197 | ||
2198 | IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); | |
11afc1b1 | 2199 | |
e90dd264 | 2200 | return 0; |
11afc1b1 PW |
2201 | } |
2202 | ||
0ecc061d | 2203 | /** |
67a79df2 | 2204 | * ixgbe_negotiate_fc - Negotiate flow control |
0ecc061d | 2205 | * @hw: pointer to hardware structure |
67a79df2 AD |
2206 | * @adv_reg: flow control advertised settings |
2207 | * @lp_reg: link partner's flow control settings | |
2208 | * @adv_sym: symmetric pause bit in advertisement | |
2209 | * @adv_asm: asymmetric pause bit in advertisement | |
2210 | * @lp_sym: symmetric pause bit in link partner advertisement | |
2211 | * @lp_asm: asymmetric pause bit in link partner advertisement | |
0ecc061d | 2212 | * |
67a79df2 AD |
2213 | * Find the intersection between advertised settings and link partner's |
2214 | * advertised settings | |
0ecc061d | 2215 | **/ |
67a79df2 AD |
2216 | static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, |
2217 | u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) | |
0ecc061d | 2218 | { |
67a79df2 AD |
2219 | if ((!(adv_reg)) || (!(lp_reg))) |
2220 | return IXGBE_ERR_FC_NOT_NEGOTIATED; | |
0b0c2b31 | 2221 | |
67a79df2 AD |
2222 | if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { |
2223 | /* | |
2224 | * Now we need to check if the user selected Rx ONLY | |
2225 | * of pause frames. In this case, we had to advertise | |
2226 | * FULL flow control because we could not advertise RX | |
2227 | * ONLY. Hence, we must now check to see if we need to | |
2228 | * turn OFF the TRANSMISSION of PAUSE frames. | |
2229 | */ | |
2230 | if (hw->fc.requested_mode == ixgbe_fc_full) { | |
2231 | hw->fc.current_mode = ixgbe_fc_full; | |
2232 | hw_dbg(hw, "Flow Control = FULL.\n"); | |
2233 | } else { | |
2234 | hw->fc.current_mode = ixgbe_fc_rx_pause; | |
2235 | hw_dbg(hw, "Flow Control=RX PAUSE frames only\n"); | |
2236 | } | |
2237 | } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && | |
2238 | (lp_reg & lp_sym) && (lp_reg & lp_asm)) { | |
2239 | hw->fc.current_mode = ixgbe_fc_tx_pause; | |
2240 | hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n"); | |
2241 | } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && | |
2242 | !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { | |
2243 | hw->fc.current_mode = ixgbe_fc_rx_pause; | |
2244 | hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n"); | |
0b0c2b31 | 2245 | } else { |
67a79df2 AD |
2246 | hw->fc.current_mode = ixgbe_fc_none; |
2247 | hw_dbg(hw, "Flow Control = NONE.\n"); | |
539e5f02 | 2248 | } |
67a79df2 | 2249 | return 0; |
0b0c2b31 ET |
2250 | } |
2251 | ||
2252 | /** | |
2253 | * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber | |
2254 | * @hw: pointer to hardware structure | |
2255 | * | |
2256 | * Enable flow control according on 1 gig fiber. | |
2257 | **/ | |
2258 | static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) | |
2259 | { | |
2260 | u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; | |
e90dd264 | 2261 | s32 ret_val; |
539e5f02 PWJ |
2262 | |
2263 | /* | |
2264 | * On multispeed fiber at 1g, bail out if | |
2265 | * - link is up but AN did not complete, or if | |
2266 | * - link is up and AN completed but timed out | |
2267 | */ | |
0b0c2b31 ET |
2268 | |
2269 | linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); | |
53f096de | 2270 | if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || |
786e9a5f | 2271 | (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) |
e90dd264 | 2272 | return IXGBE_ERR_FC_NOT_NEGOTIATED; |
539e5f02 | 2273 | |
0b0c2b31 ET |
2274 | pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); |
2275 | pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); | |
2276 | ||
2277 | ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, | |
2278 | pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, | |
2279 | IXGBE_PCS1GANA_ASM_PAUSE, | |
2280 | IXGBE_PCS1GANA_SYM_PAUSE, | |
2281 | IXGBE_PCS1GANA_ASM_PAUSE); | |
2282 | ||
0b0c2b31 ET |
2283 | return ret_val; |
2284 | } | |
2285 | ||
2286 | /** | |
2287 | * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 | |
2288 | * @hw: pointer to hardware structure | |
2289 | * | |
2290 | * Enable flow control according to IEEE clause 37. | |
2291 | **/ | |
2292 | static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) | |
2293 | { | |
2294 | u32 links2, anlp1_reg, autoc_reg, links; | |
e90dd264 | 2295 | s32 ret_val; |
0b0c2b31 | 2296 | |
9bbe3a57 | 2297 | /* |
0b0c2b31 ET |
2298 | * On backplane, bail out if |
2299 | * - backplane autoneg was not completed, or if | |
2300 | * - we are 82599 and link partner is not AN enabled | |
9bbe3a57 | 2301 | */ |
0b0c2b31 | 2302 | links = IXGBE_READ_REG(hw, IXGBE_LINKS); |
786e9a5f | 2303 | if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) |
e90dd264 | 2304 | return IXGBE_ERR_FC_NOT_NEGOTIATED; |
9bbe3a57 | 2305 | |
0b0c2b31 ET |
2306 | if (hw->mac.type == ixgbe_mac_82599EB) { |
2307 | links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); | |
786e9a5f | 2308 | if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) |
e90dd264 | 2309 | return IXGBE_ERR_FC_NOT_NEGOTIATED; |
0b0c2b31 | 2310 | } |
0ecc061d | 2311 | /* |
0b0c2b31 | 2312 | * Read the 10g AN autoc and LP ability registers and resolve |
0ecc061d PWJ |
2313 | * local flow control settings accordingly |
2314 | */ | |
0b0c2b31 ET |
2315 | autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
2316 | anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); | |
539e5f02 | 2317 | |
0b0c2b31 ET |
2318 | ret_val = ixgbe_negotiate_fc(hw, autoc_reg, |
2319 | anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, | |
2320 | IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); | |
2321 | ||
0b0c2b31 ET |
2322 | return ret_val; |
2323 | } | |
2324 | ||
2325 | /** | |
2326 | * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 | |
2327 | * @hw: pointer to hardware structure | |
2328 | * | |
2329 | * Enable flow control according to IEEE clause 37. | |
2330 | **/ | |
2331 | static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) | |
2332 | { | |
2333 | u16 technology_ability_reg = 0; | |
2334 | u16 lp_technology_ability_reg = 0; | |
2335 | ||
2336 | hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, | |
2337 | MDIO_MMD_AN, | |
2338 | &technology_ability_reg); | |
2339 | hw->phy.ops.read_reg(hw, MDIO_AN_LPA, | |
2340 | MDIO_MMD_AN, | |
2341 | &lp_technology_ability_reg); | |
2342 | ||
2343 | return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, | |
2344 | (u32)lp_technology_ability_reg, | |
2345 | IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, | |
2346 | IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); | |
2347 | } | |
2348 | ||
2349 | /** | |
67a79df2 | 2350 | * ixgbe_fc_autoneg - Configure flow control |
11afc1b1 PW |
2351 | * @hw: pointer to hardware structure |
2352 | * | |
67a79df2 AD |
2353 | * Compares our advertised flow control capabilities to those advertised by |
2354 | * our link partner, and determines the proper flow control mode to use. | |
11afc1b1 | 2355 | **/ |
67a79df2 | 2356 | void ixgbe_fc_autoneg(struct ixgbe_hw *hw) |
11afc1b1 | 2357 | { |
67a79df2 AD |
2358 | s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; |
2359 | ixgbe_link_speed speed; | |
2360 | bool link_up; | |
11afc1b1 PW |
2361 | |
2362 | /* | |
67a79df2 AD |
2363 | * AN should have completed when the cable was plugged in. |
2364 | * Look for reasons to bail out. Bail out if: | |
2365 | * - FC autoneg is disabled, or if | |
2366 | * - link is not up. | |
2367 | * | |
2368 | * Since we're being called from an LSC, link is already known to be up. | |
2369 | * So use link_up_wait_to_complete=false. | |
11afc1b1 | 2370 | */ |
67a79df2 | 2371 | if (hw->fc.disable_fc_autoneg) |
620fa036 | 2372 | goto out; |
11afc1b1 | 2373 | |
67a79df2 AD |
2374 | hw->mac.ops.check_link(hw, &speed, &link_up, false); |
2375 | if (!link_up) | |
11afc1b1 | 2376 | goto out; |
0b0c2b31 ET |
2377 | |
2378 | switch (hw->phy.media_type) { | |
67a79df2 | 2379 | /* Autoneg flow control on fiber adapters */ |
0b0c2b31 | 2380 | case ixgbe_media_type_fiber: |
67a79df2 AD |
2381 | if (speed == IXGBE_LINK_SPEED_1GB_FULL) |
2382 | ret_val = ixgbe_fc_autoneg_fiber(hw); | |
2383 | break; | |
2384 | ||
2385 | /* Autoneg flow control on backplane adapters */ | |
0b0c2b31 | 2386 | case ixgbe_media_type_backplane: |
67a79df2 | 2387 | ret_val = ixgbe_fc_autoneg_backplane(hw); |
0b0c2b31 ET |
2388 | break; |
2389 | ||
67a79df2 | 2390 | /* Autoneg flow control on copper adapters */ |
0b0c2b31 | 2391 | case ixgbe_media_type_copper: |
73d80953 | 2392 | if (ixgbe_device_supports_autoneg_fc(hw)) |
67a79df2 | 2393 | ret_val = ixgbe_fc_autoneg_copper(hw); |
0b0c2b31 ET |
2394 | break; |
2395 | ||
2396 | default: | |
620fa036 | 2397 | break; |
0b0c2b31 | 2398 | } |
539e5f02 | 2399 | |
11afc1b1 | 2400 | out: |
67a79df2 AD |
2401 | if (ret_val == 0) { |
2402 | hw->fc.fc_was_autonegged = true; | |
2403 | } else { | |
2404 | hw->fc.fc_was_autonegged = false; | |
2405 | hw->fc.current_mode = hw->fc.requested_mode; | |
2406 | } | |
11afc1b1 PW |
2407 | } |
2408 | ||
1f86c983 DS |
2409 | /** |
2410 | * ixgbe_pcie_timeout_poll - Return number of times to poll for completion | |
2411 | * @hw: pointer to hardware structure | |
2412 | * | |
2413 | * System-wide timeout range is encoded in PCIe Device Control2 register. | |
2414 | * | |
2415 | * Add 10% to specified maximum and return the number of times to poll for | |
2416 | * completion timeout, in units of 100 microsec. Never return less than | |
2417 | * 800 = 80 millisec. | |
2418 | **/ | |
2419 | static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) | |
2420 | { | |
1f86c983 DS |
2421 | s16 devctl2; |
2422 | u32 pollcnt; | |
2423 | ||
0d7c6e00 | 2424 | devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2); |
1f86c983 DS |
2425 | devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; |
2426 | ||
2427 | switch (devctl2) { | |
2428 | case IXGBE_PCIDEVCTRL2_65_130ms: | |
2429 | pollcnt = 1300; /* 130 millisec */ | |
2430 | break; | |
2431 | case IXGBE_PCIDEVCTRL2_260_520ms: | |
2432 | pollcnt = 5200; /* 520 millisec */ | |
2433 | break; | |
2434 | case IXGBE_PCIDEVCTRL2_1_2s: | |
2435 | pollcnt = 20000; /* 2 sec */ | |
2436 | break; | |
2437 | case IXGBE_PCIDEVCTRL2_4_8s: | |
2438 | pollcnt = 80000; /* 8 sec */ | |
2439 | break; | |
2440 | case IXGBE_PCIDEVCTRL2_17_34s: | |
2441 | pollcnt = 34000; /* 34 sec */ | |
2442 | break; | |
2443 | case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ | |
2444 | case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ | |
2445 | case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ | |
2446 | case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ | |
2447 | default: | |
2448 | pollcnt = 800; /* 80 millisec minimum */ | |
2449 | break; | |
2450 | } | |
2451 | ||
2452 | /* add 10% to spec maximum */ | |
2453 | return (pollcnt * 11) / 10; | |
2454 | } | |
2455 | ||
9a799d71 AK |
2456 | /** |
2457 | * ixgbe_disable_pcie_master - Disable PCI-express master access | |
2458 | * @hw: pointer to hardware structure | |
2459 | * | |
2460 | * Disables PCI-Express master access and verifies there are no pending | |
2461 | * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable | |
2462 | * bit hasn't caused the master requests to be disabled, else 0 | |
2463 | * is returned signifying master requests disabled. | |
2464 | **/ | |
ff9d1a5a | 2465 | static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) |
9a799d71 | 2466 | { |
1f86c983 | 2467 | u32 i, poll; |
ff9d1a5a ET |
2468 | u16 value; |
2469 | ||
2470 | /* Always set this bit to ensure any future transactions are blocked */ | |
2471 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); | |
a4297dc2 | 2472 | |
48b44612 MR |
2473 | /* Poll for bit to read as set */ |
2474 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { | |
2475 | if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS) | |
2476 | break; | |
2477 | usleep_range(100, 120); | |
2478 | } | |
2479 | if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) { | |
2480 | hw_dbg(hw, "GIO disable did not set - requesting resets\n"); | |
2481 | goto gio_disable_fail; | |
2482 | } | |
2483 | ||
ff9d1a5a | 2484 | /* Exit if master requests are blocked */ |
14438464 MR |
2485 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || |
2486 | ixgbe_removed(hw->hw_addr)) | |
e90dd264 | 2487 | return 0; |
9a799d71 | 2488 | |
ff9d1a5a | 2489 | /* Poll for master request bit to clear */ |
9a799d71 | 2490 | for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { |
a4297dc2 | 2491 | udelay(100); |
ff9d1a5a | 2492 | if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) |
e90dd264 | 2493 | return 0; |
a4297dc2 ET |
2494 | } |
2495 | ||
ff9d1a5a ET |
2496 | /* |
2497 | * Two consecutive resets are required via CTRL.RST per datasheet | |
2498 | * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine | |
2499 | * of this need. The first reset prevents new master requests from | |
2500 | * being issued by our device. We then must wait 1usec or more for any | |
2501 | * remaining completions from the PCIe bus to trickle in, and then reset | |
2502 | * again to clear out any effects they may have had on our device. | |
2503 | */ | |
a4297dc2 | 2504 | hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n"); |
48b44612 | 2505 | gio_disable_fail: |
ff9d1a5a | 2506 | hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; |
a4297dc2 | 2507 | |
7fc15103 MR |
2508 | if (hw->mac.type >= ixgbe_mac_X550) |
2509 | return 0; | |
2510 | ||
a4297dc2 ET |
2511 | /* |
2512 | * Before proceeding, make sure that the PCIe block does not have | |
2513 | * transactions pending. | |
2514 | */ | |
1f86c983 DS |
2515 | poll = ixgbe_pcie_timeout_poll(hw); |
2516 | for (i = 0; i < poll; i++) { | |
9a799d71 | 2517 | udelay(100); |
14438464 MR |
2518 | value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); |
2519 | if (ixgbe_removed(hw->hw_addr)) | |
e90dd264 | 2520 | return 0; |
ff9d1a5a | 2521 | if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) |
e90dd264 | 2522 | return 0; |
9a799d71 AK |
2523 | } |
2524 | ||
ff9d1a5a | 2525 | hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n"); |
e90dd264 | 2526 | return IXGBE_ERR_MASTER_REQUESTS_PENDING; |
9a799d71 AK |
2527 | } |
2528 | ||
9a799d71 | 2529 | /** |
c44ade9e | 2530 | * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore |
9a799d71 | 2531 | * @hw: pointer to hardware structure |
c44ade9e | 2532 | * @mask: Mask to specify which semaphore to acquire |
9a799d71 | 2533 | * |
da74cd4a | 2534 | * Acquires the SWFW semaphore through the GSSR register for the specified |
9a799d71 AK |
2535 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
2536 | **/ | |
030eaece | 2537 | s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) |
9a799d71 | 2538 | { |
674c18b2 | 2539 | u32 gssr = 0; |
9a799d71 AK |
2540 | u32 swmask = mask; |
2541 | u32 fwmask = mask << 5; | |
674c18b2 ET |
2542 | u32 timeout = 200; |
2543 | u32 i; | |
9a799d71 | 2544 | |
674c18b2 | 2545 | for (i = 0; i < timeout; i++) { |
dbf893ee | 2546 | /* |
674c18b2 ET |
2547 | * SW NVM semaphore bit is used for access to all |
2548 | * SW_FW_SYNC bits (not just NVM) | |
dbf893ee | 2549 | */ |
9a799d71 | 2550 | if (ixgbe_get_eeprom_semaphore(hw)) |
539e5f02 | 2551 | return IXGBE_ERR_SWFW_SYNC; |
9a799d71 AK |
2552 | |
2553 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | |
674c18b2 ET |
2554 | if (!(gssr & (fwmask | swmask))) { |
2555 | gssr |= swmask; | |
2556 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); | |
2557 | ixgbe_release_eeprom_semaphore(hw); | |
2558 | return 0; | |
2559 | } else { | |
2560 | /* Resource is currently in use by FW or SW */ | |
2561 | ixgbe_release_eeprom_semaphore(hw); | |
2562 | usleep_range(5000, 10000); | |
2563 | } | |
9a799d71 AK |
2564 | } |
2565 | ||
674c18b2 ET |
2566 | /* If time expired clear the bits holding the lock and retry */ |
2567 | if (gssr & (fwmask | swmask)) | |
2568 | ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); | |
9a799d71 | 2569 | |
674c18b2 ET |
2570 | usleep_range(5000, 10000); |
2571 | return IXGBE_ERR_SWFW_SYNC; | |
9a799d71 AK |
2572 | } |
2573 | ||
2574 | /** | |
2575 | * ixgbe_release_swfw_sync - Release SWFW semaphore | |
2576 | * @hw: pointer to hardware structure | |
c44ade9e | 2577 | * @mask: Mask to specify which semaphore to release |
9a799d71 | 2578 | * |
da74cd4a | 2579 | * Releases the SWFW semaphore through the GSSR register for the specified |
9a799d71 AK |
2580 | * function (CSR, PHY0, PHY1, EEPROM, Flash) |
2581 | **/ | |
030eaece | 2582 | void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) |
9a799d71 AK |
2583 | { |
2584 | u32 gssr; | |
2585 | u32 swmask = mask; | |
2586 | ||
2587 | ixgbe_get_eeprom_semaphore(hw); | |
2588 | ||
2589 | gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); | |
2590 | gssr &= ~swmask; | |
2591 | IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); | |
2592 | ||
2593 | ixgbe_release_eeprom_semaphore(hw); | |
2594 | } | |
2595 | ||
429d6a3b DS |
2596 | /** |
2597 | * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read | |
2598 | * @hw: pointer to hardware structure | |
2599 | * @reg_val: Value we read from AUTOC | |
2600 | * @locked: bool to indicate whether the SW/FW lock should be taken. Never | |
2601 | * true in this the generic case. | |
2602 | * | |
2603 | * The default case requires no protection so just to the register read. | |
2604 | **/ | |
2605 | s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) | |
2606 | { | |
2607 | *locked = false; | |
2608 | *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); | |
2609 | return 0; | |
2610 | } | |
2611 | ||
2612 | /** | |
2613 | * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write | |
2614 | * @hw: pointer to hardware structure | |
2615 | * @reg_val: value to write to AUTOC | |
2616 | * @locked: bool to indicate whether the SW/FW lock was already taken by | |
2617 | * previous read. | |
2618 | **/ | |
2619 | s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) | |
2620 | { | |
2621 | IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); | |
2622 | return 0; | |
2623 | } | |
2624 | ||
d2f5e7f3 AS |
2625 | /** |
2626 | * ixgbe_disable_rx_buff_generic - Stops the receive data path | |
2627 | * @hw: pointer to hardware structure | |
2628 | * | |
2629 | * Stops the receive data path and waits for the HW to internally | |
2630 | * empty the Rx security block. | |
2631 | **/ | |
2632 | s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw) | |
2633 | { | |
2634 | #define IXGBE_MAX_SECRX_POLL 40 | |
2635 | int i; | |
2636 | int secrxreg; | |
2637 | ||
2638 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); | |
2639 | secrxreg |= IXGBE_SECRXCTRL_RX_DIS; | |
2640 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); | |
2641 | for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { | |
2642 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); | |
2643 | if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) | |
2644 | break; | |
2645 | else | |
2646 | /* Use interrupt-safe sleep just in case */ | |
db76ad47 | 2647 | udelay(1000); |
d2f5e7f3 AS |
2648 | } |
2649 | ||
2650 | /* For informational purposes only */ | |
2651 | if (i >= IXGBE_MAX_SECRX_POLL) | |
6ec1b71f | 2652 | hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n"); |
d2f5e7f3 AS |
2653 | |
2654 | return 0; | |
2655 | ||
2656 | } | |
2657 | ||
2658 | /** | |
2659 | * ixgbe_enable_rx_buff - Enables the receive data path | |
2660 | * @hw: pointer to hardware structure | |
2661 | * | |
2662 | * Enables the receive data path | |
2663 | **/ | |
2664 | s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw) | |
2665 | { | |
2666 | int secrxreg; | |
2667 | ||
2668 | secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); | |
2669 | secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; | |
2670 | IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); | |
2671 | IXGBE_WRITE_FLUSH(hw); | |
2672 | ||
2673 | return 0; | |
2674 | } | |
2675 | ||
11afc1b1 PW |
2676 | /** |
2677 | * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit | |
2678 | * @hw: pointer to hardware structure | |
2679 | * @regval: register value to write to RXCTRL | |
2680 | * | |
2681 | * Enables the Rx DMA unit | |
2682 | **/ | |
2683 | s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) | |
2684 | { | |
1f9ac57c DS |
2685 | if (regval & IXGBE_RXCTRL_RXEN) |
2686 | hw->mac.ops.enable_rx(hw); | |
2687 | else | |
2688 | hw->mac.ops.disable_rx(hw); | |
11afc1b1 PW |
2689 | |
2690 | return 0; | |
2691 | } | |
87c12017 PW |
2692 | |
2693 | /** | |
2694 | * ixgbe_blink_led_start_generic - Blink LED based on index. | |
2695 | * @hw: pointer to hardware structure | |
2696 | * @index: led number to blink | |
2697 | **/ | |
2698 | s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) | |
2699 | { | |
2700 | ixgbe_link_speed speed = 0; | |
3db1cd5c | 2701 | bool link_up = false; |
87c12017 PW |
2702 | u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); |
2703 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); | |
429d6a3b | 2704 | bool locked = false; |
e90dd264 | 2705 | s32 ret_val; |
87c12017 | 2706 | |
003287e0 DS |
2707 | if (index > 3) |
2708 | return IXGBE_ERR_PARAM; | |
2709 | ||
87c12017 PW |
2710 | /* |
2711 | * Link must be up to auto-blink the LEDs; | |
2712 | * Force it if link is down. | |
2713 | */ | |
2714 | hw->mac.ops.check_link(hw, &speed, &link_up, false); | |
2715 | ||
2716 | if (!link_up) { | |
429d6a3b | 2717 | ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); |
f8cf7a00 | 2718 | if (ret_val) |
e90dd264 | 2719 | return ret_val; |
d7bbcd32 | 2720 | |
50ac58ba | 2721 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; |
87c12017 | 2722 | autoc_reg |= IXGBE_AUTOC_FLU; |
429d6a3b DS |
2723 | |
2724 | ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); | |
f8cf7a00 | 2725 | if (ret_val) |
e90dd264 | 2726 | return ret_val; |
429d6a3b | 2727 | |
945a5151 | 2728 | IXGBE_WRITE_FLUSH(hw); |
d7bbcd32 | 2729 | |
032b4325 | 2730 | usleep_range(10000, 20000); |
87c12017 PW |
2731 | } |
2732 | ||
2733 | led_reg &= ~IXGBE_LED_MODE_MASK(index); | |
2734 | led_reg |= IXGBE_LED_BLINK(index); | |
2735 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
2736 | IXGBE_WRITE_FLUSH(hw); | |
2737 | ||
e90dd264 | 2738 | return 0; |
87c12017 PW |
2739 | } |
2740 | ||
2741 | /** | |
2742 | * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. | |
2743 | * @hw: pointer to hardware structure | |
2744 | * @index: led number to stop blinking | |
2745 | **/ | |
2746 | s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) | |
2747 | { | |
429d6a3b | 2748 | u32 autoc_reg = 0; |
87c12017 | 2749 | u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); |
429d6a3b | 2750 | bool locked = false; |
e90dd264 | 2751 | s32 ret_val; |
d7bbcd32 | 2752 | |
003287e0 DS |
2753 | if (index > 3) |
2754 | return IXGBE_ERR_PARAM; | |
2755 | ||
429d6a3b | 2756 | ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); |
f8cf7a00 | 2757 | if (ret_val) |
e90dd264 | 2758 | return ret_val; |
87c12017 PW |
2759 | |
2760 | autoc_reg &= ~IXGBE_AUTOC_FLU; | |
2761 | autoc_reg |= IXGBE_AUTOC_AN_RESTART; | |
87c12017 | 2762 | |
429d6a3b | 2763 | ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); |
f8cf7a00 | 2764 | if (ret_val) |
e90dd264 | 2765 | return ret_val; |
d7bbcd32 | 2766 | |
87c12017 PW |
2767 | led_reg &= ~IXGBE_LED_MODE_MASK(index); |
2768 | led_reg &= ~IXGBE_LED_BLINK(index); | |
2769 | led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); | |
2770 | IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); | |
2771 | IXGBE_WRITE_FLUSH(hw); | |
2772 | ||
e90dd264 | 2773 | return 0; |
87c12017 | 2774 | } |
21ce849b MC |
2775 | |
2776 | /** | |
2777 | * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM | |
2778 | * @hw: pointer to hardware structure | |
2779 | * @san_mac_offset: SAN MAC address offset | |
2780 | * | |
2781 | * This function will read the EEPROM location for the SAN MAC address | |
2782 | * pointer, and returns the value at that location. This is used in both | |
2783 | * get and set mac_addr routines. | |
2784 | **/ | |
2785 | static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, | |
e7cf745b | 2786 | u16 *san_mac_offset) |
21ce849b | 2787 | { |
be0c27b4 MR |
2788 | s32 ret_val; |
2789 | ||
21ce849b MC |
2790 | /* |
2791 | * First read the EEPROM pointer to see if the MAC addresses are | |
2792 | * available. | |
2793 | */ | |
be0c27b4 MR |
2794 | ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, |
2795 | san_mac_offset); | |
2796 | if (ret_val) | |
2797 | hw_err(hw, "eeprom read at offset %d failed\n", | |
2798 | IXGBE_SAN_MAC_ADDR_PTR); | |
21ce849b | 2799 | |
be0c27b4 | 2800 | return ret_val; |
21ce849b MC |
2801 | } |
2802 | ||
2803 | /** | |
2804 | * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM | |
2805 | * @hw: pointer to hardware structure | |
2806 | * @san_mac_addr: SAN MAC address | |
2807 | * | |
2808 | * Reads the SAN MAC address from the EEPROM, if it's available. This is | |
2809 | * per-port, so set_lan_id() must be called before reading the addresses. | |
2810 | * set_lan_id() is called by identify_sfp(), but this cannot be relied | |
2811 | * upon for non-SFP connections, so we must call it here. | |
2812 | **/ | |
2813 | s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) | |
2814 | { | |
2815 | u16 san_mac_data, san_mac_offset; | |
2816 | u8 i; | |
be0c27b4 | 2817 | s32 ret_val; |
21ce849b MC |
2818 | |
2819 | /* | |
2820 | * First read the EEPROM pointer to see if the MAC addresses are | |
2821 | * available. If they're not, no point in calling set_lan_id() here. | |
2822 | */ | |
be0c27b4 MR |
2823 | ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); |
2824 | if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) | |
21ce849b | 2825 | |
be0c27b4 | 2826 | goto san_mac_addr_clr; |
21ce849b MC |
2827 | |
2828 | /* make sure we know which port we need to program */ | |
2829 | hw->mac.ops.set_lan_id(hw); | |
2830 | /* apply the port offset to the address offset */ | |
2831 | (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : | |
e7cf745b | 2832 | (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); |
21ce849b | 2833 | for (i = 0; i < 3; i++) { |
be0c27b4 MR |
2834 | ret_val = hw->eeprom.ops.read(hw, san_mac_offset, |
2835 | &san_mac_data); | |
2836 | if (ret_val) { | |
2837 | hw_err(hw, "eeprom read at offset %d failed\n", | |
2838 | san_mac_offset); | |
2839 | goto san_mac_addr_clr; | |
2840 | } | |
21ce849b MC |
2841 | san_mac_addr[i * 2] = (u8)(san_mac_data); |
2842 | san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); | |
2843 | san_mac_offset++; | |
2844 | } | |
21ce849b | 2845 | return 0; |
be0c27b4 MR |
2846 | |
2847 | san_mac_addr_clr: | |
2848 | /* No addresses available in this EEPROM. It's not necessarily an | |
2849 | * error though, so just wipe the local address and return. | |
2850 | */ | |
2851 | for (i = 0; i < 6; i++) | |
2852 | san_mac_addr[i] = 0xFF; | |
2853 | return ret_val; | |
21ce849b MC |
2854 | } |
2855 | ||
2856 | /** | |
2857 | * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count | |
2858 | * @hw: pointer to hardware structure | |
2859 | * | |
2860 | * Read PCIe configuration space, and get the MSI-X vector count from | |
2861 | * the capabilities table. | |
2862 | **/ | |
71161302 | 2863 | u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) |
21ce849b | 2864 | { |
e90dd264 | 2865 | u16 msix_count; |
71161302 ET |
2866 | u16 max_msix_count; |
2867 | u16 pcie_offset; | |
2868 | ||
2869 | switch (hw->mac.type) { | |
2870 | case ixgbe_mac_82598EB: | |
2871 | pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; | |
2872 | max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; | |
2873 | break; | |
2874 | case ixgbe_mac_82599EB: | |
2875 | case ixgbe_mac_X540: | |
9a75a1ac DS |
2876 | case ixgbe_mac_X550: |
2877 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2878 | case ixgbe_mac_x550em_a: |
71161302 ET |
2879 | pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; |
2880 | max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; | |
2881 | break; | |
2882 | default: | |
e90dd264 | 2883 | return 1; |
71161302 ET |
2884 | } |
2885 | ||
14438464 MR |
2886 | msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset); |
2887 | if (ixgbe_removed(hw->hw_addr)) | |
2888 | msix_count = 0; | |
21ce849b MC |
2889 | msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; |
2890 | ||
71161302 | 2891 | /* MSI-X count is zero-based in HW */ |
21ce849b MC |
2892 | msix_count++; |
2893 | ||
71161302 ET |
2894 | if (msix_count > max_msix_count) |
2895 | msix_count = max_msix_count; | |
2896 | ||
21ce849b MC |
2897 | return msix_count; |
2898 | } | |
2899 | ||
2900 | /** | |
2901 | * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address | |
2902 | * @hw: pointer to hardware struct | |
2903 | * @rar: receive address register index to disassociate | |
2904 | * @vmdq: VMDq pool index to remove from the rar | |
2905 | **/ | |
2906 | s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
2907 | { | |
2908 | u32 mpsar_lo, mpsar_hi; | |
2909 | u32 rar_entries = hw->mac.num_rar_entries; | |
2910 | ||
c700f4e6 ET |
2911 | /* Make sure we are using a valid rar index range */ |
2912 | if (rar >= rar_entries) { | |
2913 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); | |
2914 | return IXGBE_ERR_INVALID_ARGUMENT; | |
2915 | } | |
21ce849b | 2916 | |
c700f4e6 ET |
2917 | mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); |
2918 | mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); | |
21ce849b | 2919 | |
19458bd4 | 2920 | if (ixgbe_removed(hw->hw_addr)) |
e90dd264 | 2921 | return 0; |
19458bd4 | 2922 | |
c700f4e6 | 2923 | if (!mpsar_lo && !mpsar_hi) |
e90dd264 | 2924 | return 0; |
21ce849b | 2925 | |
c700f4e6 ET |
2926 | if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { |
2927 | if (mpsar_lo) { | |
2928 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); | |
2929 | mpsar_lo = 0; | |
2930 | } | |
2931 | if (mpsar_hi) { | |
2932 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); | |
2933 | mpsar_hi = 0; | |
2934 | } | |
2935 | } else if (vmdq < 32) { | |
b4f47a48 | 2936 | mpsar_lo &= ~BIT(vmdq); |
c700f4e6 | 2937 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); |
21ce849b | 2938 | } else { |
b4f47a48 | 2939 | mpsar_hi &= ~BIT(vmdq - 32); |
c700f4e6 | 2940 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); |
21ce849b MC |
2941 | } |
2942 | ||
c700f4e6 ET |
2943 | /* was that the last pool using this rar? */ |
2944 | if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) | |
2945 | hw->mac.ops.clear_rar(hw, rar); | |
21ce849b MC |
2946 | return 0; |
2947 | } | |
2948 | ||
2949 | /** | |
2950 | * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address | |
2951 | * @hw: pointer to hardware struct | |
2952 | * @rar: receive address register index to associate with a VMDq index | |
2953 | * @vmdq: VMDq pool index | |
2954 | **/ | |
2955 | s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) | |
2956 | { | |
2957 | u32 mpsar; | |
2958 | u32 rar_entries = hw->mac.num_rar_entries; | |
2959 | ||
c700f4e6 ET |
2960 | /* Make sure we are using a valid rar index range */ |
2961 | if (rar >= rar_entries) { | |
21ce849b | 2962 | hw_dbg(hw, "RAR index %d is out of range.\n", rar); |
c700f4e6 ET |
2963 | return IXGBE_ERR_INVALID_ARGUMENT; |
2964 | } | |
2965 | ||
2966 | if (vmdq < 32) { | |
2967 | mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); | |
b4f47a48 | 2968 | mpsar |= BIT(vmdq); |
c700f4e6 ET |
2969 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); |
2970 | } else { | |
2971 | mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); | |
b4f47a48 | 2972 | mpsar |= BIT(vmdq - 32); |
c700f4e6 | 2973 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); |
21ce849b MC |
2974 | } |
2975 | return 0; | |
2976 | } | |
2977 | ||
7fa7c9dc AD |
2978 | /** |
2979 | * This function should only be involved in the IOV mode. | |
2980 | * In IOV mode, Default pool is next pool after the number of | |
2981 | * VFs advertized and not 0. | |
2982 | * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] | |
2983 | * | |
2984 | * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address | |
2985 | * @hw: pointer to hardware struct | |
2986 | * @vmdq: VMDq pool index | |
2987 | **/ | |
2988 | s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) | |
2989 | { | |
2990 | u32 rar = hw->mac.san_mac_rar_index; | |
2991 | ||
2992 | if (vmdq < 32) { | |
b4f47a48 | 2993 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq)); |
7fa7c9dc AD |
2994 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); |
2995 | } else { | |
2996 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); | |
b4f47a48 | 2997 | IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32)); |
7fa7c9dc AD |
2998 | } |
2999 | ||
3000 | return 0; | |
3001 | } | |
3002 | ||
21ce849b MC |
3003 | /** |
3004 | * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array | |
3005 | * @hw: pointer to hardware structure | |
3006 | **/ | |
3007 | s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) | |
3008 | { | |
3009 | int i; | |
3010 | ||
21ce849b MC |
3011 | for (i = 0; i < 128; i++) |
3012 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); | |
3013 | ||
3014 | return 0; | |
3015 | } | |
3016 | ||
3017 | /** | |
3018 | * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot | |
3019 | * @hw: pointer to hardware structure | |
3020 | * @vlan: VLAN id to write to VLAN filter | |
3021 | * | |
3022 | * return the VLVF index where this VLAN id should be placed | |
3023 | * | |
3024 | **/ | |
b6488b66 | 3025 | static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) |
21ce849b | 3026 | { |
b6488b66 | 3027 | s32 regindex, first_empty_slot; |
c2bc9ce9 | 3028 | u32 bits; |
21ce849b MC |
3029 | |
3030 | /* short cut the special case */ | |
3031 | if (vlan == 0) | |
3032 | return 0; | |
3033 | ||
b6488b66 AD |
3034 | /* if vlvf_bypass is set we don't want to use an empty slot, we |
3035 | * will simply bypass the VLVF if there are no entries present in the | |
3036 | * VLVF that contain our VLAN | |
3037 | */ | |
3038 | first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0; | |
3039 | ||
c2bc9ce9 AD |
3040 | /* add VLAN enable bit for comparison */ |
3041 | vlan |= IXGBE_VLVF_VIEN; | |
3042 | ||
3043 | /* Search for the vlan id in the VLVF entries. Save off the first empty | |
3044 | * slot found along the way. | |
3045 | * | |
3046 | * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 | |
3047 | */ | |
3048 | for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { | |
21ce849b | 3049 | bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); |
c2bc9ce9 AD |
3050 | if (bits == vlan) |
3051 | return regindex; | |
3052 | if (!first_empty_slot && !bits) | |
21ce849b | 3053 | first_empty_slot = regindex; |
21ce849b MC |
3054 | } |
3055 | ||
c2bc9ce9 AD |
3056 | /* If we are here then we didn't find the VLAN. Return first empty |
3057 | * slot we found during our search, else error. | |
3058 | */ | |
3059 | if (!first_empty_slot) | |
3060 | hw_dbg(hw, "No space in VLVF.\n"); | |
21ce849b | 3061 | |
c2bc9ce9 | 3062 | return first_empty_slot ? : IXGBE_ERR_NO_SPACE; |
21ce849b MC |
3063 | } |
3064 | ||
3065 | /** | |
3066 | * ixgbe_set_vfta_generic - Set VLAN filter table | |
3067 | * @hw: pointer to hardware structure | |
3068 | * @vlan: VLAN id to write to VLAN filter | |
3069 | * @vind: VMDq output index that maps queue to VLAN id in VFVFB | |
3070 | * @vlan_on: boolean flag to turn on/off VLAN in VFVF | |
b6488b66 | 3071 | * @vlvf_bypass: boolean flag indicating updating default pool is okay |
21ce849b MC |
3072 | * |
3073 | * Turn on/off specified VLAN in the VLAN filter table. | |
3074 | **/ | |
3075 | s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, | |
b6488b66 | 3076 | bool vlan_on, bool vlvf_bypass) |
21ce849b | 3077 | { |
5ac736a6 | 3078 | u32 regidx, vfta_delta, vfta, bits; |
63d9379a | 3079 | s32 vlvf_index; |
21ce849b | 3080 | |
5ac736a6 | 3081 | if ((vlan > 4095) || (vind > 63)) |
21ce849b MC |
3082 | return IXGBE_ERR_PARAM; |
3083 | ||
3084 | /* | |
3085 | * this is a 2 part operation - first the VFTA, then the | |
3086 | * VLVF and VLVFB if VT Mode is set | |
3087 | * We don't write the VFTA until we know the VLVF part succeeded. | |
3088 | */ | |
3089 | ||
3090 | /* Part 1 | |
3091 | * The VFTA is a bitstring made up of 128 32-bit registers | |
3092 | * that enable the particular VLAN id, much like the MTA: | |
3093 | * bits[11-5]: which register | |
3094 | * bits[4-0]: which bit in the register | |
3095 | */ | |
c18fbd5f | 3096 | regidx = vlan / 32; |
b4f47a48 | 3097 | vfta_delta = BIT(vlan % 32); |
c18fbd5f AD |
3098 | vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); |
3099 | ||
3100 | /* vfta_delta represents the difference between the current value | |
3101 | * of vfta and the value we want in the register. Since the diff | |
3102 | * is an XOR mask we can just update vfta using an XOR. | |
3103 | */ | |
3104 | vfta_delta &= vlan_on ? ~vfta : vfta; | |
3105 | vfta ^= vfta_delta; | |
21ce849b MC |
3106 | |
3107 | /* Part 2 | |
3108 | * If VT Mode is set | |
3109 | * Either vlan_on | |
3110 | * make sure the vlan is in VLVF | |
3111 | * set the vind bit in the matching VLVFB | |
3112 | * Or !vlan_on | |
3113 | * clear the pool bit and possibly the vind | |
3114 | */ | |
63d9379a AD |
3115 | if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) |
3116 | goto vfta_update; | |
3117 | ||
b6488b66 AD |
3118 | vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); |
3119 | if (vlvf_index < 0) { | |
3120 | if (vlvf_bypass) | |
3121 | goto vfta_update; | |
63d9379a | 3122 | return vlvf_index; |
b6488b66 | 3123 | } |
63d9379a | 3124 | |
5ac736a6 AD |
3125 | bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); |
3126 | ||
3127 | /* set the pool bit */ | |
b4f47a48 | 3128 | bits |= BIT(vind % 32); |
5ac736a6 AD |
3129 | if (vlan_on) |
3130 | goto vlvf_update; | |
3131 | ||
3132 | /* clear the pool bit */ | |
b4f47a48 | 3133 | bits ^= BIT(vind % 32); |
5ac736a6 AD |
3134 | |
3135 | if (!bits && | |
3136 | !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { | |
3137 | /* Clear VFTA first, then disable VLVF. Otherwise | |
3138 | * we run the risk of stray packets leaking into | |
3139 | * the PF via the default pool | |
3140 | */ | |
3141 | if (vfta_delta) | |
3142 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); | |
3143 | ||
3144 | /* disable VLVF and clear remaining bit from pool */ | |
3145 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); | |
3146 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); | |
3147 | ||
3148 | return 0; | |
21ce849b MC |
3149 | } |
3150 | ||
63d9379a AD |
3151 | /* If there are still bits set in the VLVFB registers |
3152 | * for the VLAN ID indicated we need to see if the | |
3153 | * caller is requesting that we clear the VFTA entry bit. | |
3154 | * If the caller has requested that we clear the VFTA | |
3155 | * entry bit but there are still pools/VFs using this VLAN | |
3156 | * ID entry then ignore the request. We're not worried | |
3157 | * about the case where we're turning the VFTA VLAN ID | |
3158 | * entry bit on, only when requested to turn it off as | |
3159 | * there may be multiple pools and/or VFs using the | |
3160 | * VLAN ID entry. In that case we cannot clear the | |
3161 | * VFTA bit until all pools/VFs using that VLAN ID have also | |
3162 | * been cleared. This will be indicated by "bits" being | |
3163 | * zero. | |
3164 | */ | |
5ac736a6 | 3165 | vfta_delta = 0; |
63d9379a | 3166 | |
5ac736a6 AD |
3167 | vlvf_update: |
3168 | /* record pool change and enable VLAN ID if not already enabled */ | |
3169 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); | |
3170 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); | |
63d9379a AD |
3171 | |
3172 | vfta_update: | |
5ac736a6 | 3173 | /* Update VFTA now that we are ready for traffic */ |
c18fbd5f AD |
3174 | if (vfta_delta) |
3175 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); | |
21ce849b MC |
3176 | |
3177 | return 0; | |
3178 | } | |
3179 | ||
3180 | /** | |
3181 | * ixgbe_clear_vfta_generic - Clear VLAN filter table | |
3182 | * @hw: pointer to hardware structure | |
3183 | * | |
3184 | * Clears the VLAN filer table, and the VMDq index associated with the filter | |
3185 | **/ | |
3186 | s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) | |
3187 | { | |
3188 | u32 offset; | |
3189 | ||
3190 | for (offset = 0; offset < hw->mac.vft_size; offset++) | |
3191 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); | |
3192 | ||
3193 | for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { | |
3194 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); | |
5ac736a6 AD |
3195 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); |
3196 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); | |
21ce849b MC |
3197 | } |
3198 | ||
3199 | return 0; | |
3200 | } | |
3201 | ||
3202 | /** | |
3203 | * ixgbe_check_mac_link_generic - Determine link and speed status | |
3204 | * @hw: pointer to hardware structure | |
3205 | * @speed: pointer to link speed | |
3206 | * @link_up: true when link is up | |
3207 | * @link_up_wait_to_complete: bool used to wait for link up or not | |
3208 | * | |
3209 | * Reads the links register to determine if link is up and the current speed | |
3210 | **/ | |
3211 | s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, | |
8c7bea32 | 3212 | bool *link_up, bool link_up_wait_to_complete) |
21ce849b | 3213 | { |
48de36c5 | 3214 | u32 links_reg, links_orig; |
21ce849b MC |
3215 | u32 i; |
3216 | ||
48de36c5 ET |
3217 | /* clear the old state */ |
3218 | links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
3219 | ||
21ce849b | 3220 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); |
48de36c5 ET |
3221 | |
3222 | if (links_orig != links_reg) { | |
3223 | hw_dbg(hw, "LINKS changed from %08X to %08X\n", | |
3224 | links_orig, links_reg); | |
3225 | } | |
3226 | ||
21ce849b MC |
3227 | if (link_up_wait_to_complete) { |
3228 | for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { | |
3229 | if (links_reg & IXGBE_LINKS_UP) { | |
3230 | *link_up = true; | |
3231 | break; | |
3232 | } else { | |
3233 | *link_up = false; | |
3234 | } | |
3235 | msleep(100); | |
3236 | links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); | |
3237 | } | |
3238 | } else { | |
3239 | if (links_reg & IXGBE_LINKS_UP) | |
3240 | *link_up = true; | |
3241 | else | |
3242 | *link_up = false; | |
3243 | } | |
3244 | ||
9a75a1ac DS |
3245 | switch (links_reg & IXGBE_LINKS_SPEED_82599) { |
3246 | case IXGBE_LINKS_SPEED_10G_82599: | |
3247 | if ((hw->mac.type >= ixgbe_mac_X550) && | |
3248 | (links_reg & IXGBE_LINKS_SPEED_NON_STD)) | |
3249 | *speed = IXGBE_LINK_SPEED_2_5GB_FULL; | |
3250 | else | |
3251 | *speed = IXGBE_LINK_SPEED_10GB_FULL; | |
3252 | break; | |
3253 | case IXGBE_LINKS_SPEED_1G_82599: | |
21ce849b | 3254 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
9a75a1ac DS |
3255 | break; |
3256 | case IXGBE_LINKS_SPEED_100_82599: | |
3257 | if ((hw->mac.type >= ixgbe_mac_X550) && | |
3258 | (links_reg & IXGBE_LINKS_SPEED_NON_STD)) | |
3259 | *speed = IXGBE_LINK_SPEED_5GB_FULL; | |
3260 | else | |
3261 | *speed = IXGBE_LINK_SPEED_100_FULL; | |
3262 | break; | |
3263 | default: | |
63d778df | 3264 | *speed = IXGBE_LINK_SPEED_UNKNOWN; |
9a75a1ac | 3265 | } |
21ce849b | 3266 | |
21ce849b MC |
3267 | return 0; |
3268 | } | |
a391f1d5 DS |
3269 | |
3270 | /** | |
49ce9c2c | 3271 | * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from |
a391f1d5 DS |
3272 | * the EEPROM |
3273 | * @hw: pointer to hardware structure | |
3274 | * @wwnn_prefix: the alternative WWNN prefix | |
3275 | * @wwpn_prefix: the alternative WWPN prefix | |
3276 | * | |
3277 | * This function will read the EEPROM from the alternative SAN MAC address | |
3278 | * block to check the support for the alternative WWNN/WWPN prefix support. | |
3279 | **/ | |
3280 | s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, | |
e7cf745b | 3281 | u16 *wwpn_prefix) |
a391f1d5 DS |
3282 | { |
3283 | u16 offset, caps; | |
3284 | u16 alt_san_mac_blk_offset; | |
3285 | ||
3286 | /* clear output first */ | |
3287 | *wwnn_prefix = 0xFFFF; | |
3288 | *wwpn_prefix = 0xFFFF; | |
3289 | ||
3290 | /* check if alternative SAN MAC is supported */ | |
be0c27b4 MR |
3291 | offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; |
3292 | if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) | |
3293 | goto wwn_prefix_err; | |
a391f1d5 DS |
3294 | |
3295 | if ((alt_san_mac_blk_offset == 0) || | |
3296 | (alt_san_mac_blk_offset == 0xFFFF)) | |
e90dd264 | 3297 | return 0; |
a391f1d5 DS |
3298 | |
3299 | /* check capability in alternative san mac address block */ | |
3300 | offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; | |
be0c27b4 MR |
3301 | if (hw->eeprom.ops.read(hw, offset, &caps)) |
3302 | goto wwn_prefix_err; | |
a391f1d5 | 3303 | if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) |
e90dd264 | 3304 | return 0; |
a391f1d5 DS |
3305 | |
3306 | /* get the corresponding prefix for WWNN/WWPN */ | |
3307 | offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; | |
be0c27b4 MR |
3308 | if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) |
3309 | hw_err(hw, "eeprom read at offset %d failed\n", offset); | |
a391f1d5 DS |
3310 | |
3311 | offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; | |
be0c27b4 MR |
3312 | if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) |
3313 | goto wwn_prefix_err; | |
a391f1d5 | 3314 | |
a391f1d5 | 3315 | return 0; |
be0c27b4 MR |
3316 | |
3317 | wwn_prefix_err: | |
3318 | hw_err(hw, "eeprom read at offset %d failed\n", offset); | |
3319 | return 0; | |
a391f1d5 | 3320 | } |
a985b6c3 GR |
3321 | |
3322 | /** | |
3323 | * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing | |
3324 | * @hw: pointer to hardware structure | |
77f192af ET |
3325 | * @enable: enable or disable switch for MAC anti-spoofing |
3326 | * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing | |
a985b6c3 GR |
3327 | * |
3328 | **/ | |
77f192af | 3329 | void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) |
a985b6c3 | 3330 | { |
77f192af ET |
3331 | int vf_target_reg = vf >> 3; |
3332 | int vf_target_shift = vf % 8; | |
3333 | u32 pfvfspoof; | |
a985b6c3 GR |
3334 | |
3335 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3336 | return; | |
3337 | ||
77f192af | 3338 | pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); |
a985b6c3 | 3339 | if (enable) |
77f192af ET |
3340 | pfvfspoof |= BIT(vf_target_shift); |
3341 | else | |
3342 | pfvfspoof &= ~BIT(vf_target_shift); | |
3343 | IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); | |
a985b6c3 GR |
3344 | } |
3345 | ||
3346 | /** | |
3347 | * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing | |
3348 | * @hw: pointer to hardware structure | |
3349 | * @enable: enable or disable switch for VLAN anti-spoofing | |
3350 | * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing | |
3351 | * | |
3352 | **/ | |
3353 | void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) | |
3354 | { | |
3355 | int vf_target_reg = vf >> 3; | |
3356 | int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; | |
3357 | u32 pfvfspoof; | |
3358 | ||
3359 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3360 | return; | |
3361 | ||
3362 | pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); | |
3363 | if (enable) | |
b4f47a48 | 3364 | pfvfspoof |= BIT(vf_target_shift); |
a985b6c3 | 3365 | else |
b4f47a48 | 3366 | pfvfspoof &= ~BIT(vf_target_shift); |
a985b6c3 GR |
3367 | IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); |
3368 | } | |
b776d104 ET |
3369 | |
3370 | /** | |
3371 | * ixgbe_get_device_caps_generic - Get additional device capabilities | |
3372 | * @hw: pointer to hardware structure | |
3373 | * @device_caps: the EEPROM word with the extra device capabilities | |
3374 | * | |
3375 | * This function will read the EEPROM location for the device capabilities, | |
3376 | * and return the word through device_caps. | |
3377 | **/ | |
3378 | s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) | |
3379 | { | |
3380 | hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); | |
3381 | ||
3382 | return 0; | |
3383 | } | |
80605c65 JF |
3384 | |
3385 | /** | |
3386 | * ixgbe_set_rxpba_generic - Initialize RX packet buffer | |
3387 | * @hw: pointer to hardware structure | |
3388 | * @num_pb: number of packet buffers to allocate | |
3389 | * @headroom: reserve n KB of headroom | |
3390 | * @strategy: packet buffer allocation strategy | |
3391 | **/ | |
3392 | void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, | |
3393 | int num_pb, | |
3394 | u32 headroom, | |
3395 | int strategy) | |
3396 | { | |
3397 | u32 pbsize = hw->mac.rx_pb_size; | |
3398 | int i = 0; | |
3399 | u32 rxpktsize, txpktsize, txpbthresh; | |
3400 | ||
3401 | /* Reserve headroom */ | |
3402 | pbsize -= headroom; | |
3403 | ||
3404 | if (!num_pb) | |
3405 | num_pb = 1; | |
3406 | ||
3407 | /* Divide remaining packet buffer space amongst the number | |
3408 | * of packet buffers requested using supplied strategy. | |
3409 | */ | |
3410 | switch (strategy) { | |
3411 | case (PBA_STRATEGY_WEIGHTED): | |
3412 | /* pba_80_48 strategy weight first half of packet buffer with | |
3413 | * 5/8 of the packet buffer space. | |
3414 | */ | |
3415 | rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8)); | |
3416 | pbsize -= rxpktsize * (num_pb / 2); | |
3417 | rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; | |
3418 | for (; i < (num_pb / 2); i++) | |
3419 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); | |
3420 | /* Fall through to configure remaining packet buffers */ | |
3421 | case (PBA_STRATEGY_EQUAL): | |
3422 | /* Divide the remaining Rx packet buffer evenly among the TCs */ | |
3423 | rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; | |
3424 | for (; i < num_pb; i++) | |
3425 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); | |
3426 | break; | |
3427 | default: | |
3428 | break; | |
3429 | } | |
3430 | ||
3431 | /* | |
3432 | * Setup Tx packet buffer and threshold equally for all TCs | |
3433 | * TXPBTHRESH register is set in K so divide by 1024 and subtract | |
3434 | * 10 since the largest packet we support is just over 9K. | |
3435 | */ | |
3436 | txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; | |
3437 | txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; | |
3438 | for (i = 0; i < num_pb; i++) { | |
3439 | IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); | |
3440 | IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); | |
3441 | } | |
3442 | ||
3443 | /* Clear unused TCs, if any, to zero buffer size*/ | |
3444 | for (; i < IXGBE_MAX_PB; i++) { | |
3445 | IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); | |
3446 | IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); | |
3447 | IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); | |
3448 | } | |
3449 | } | |
9612de92 ET |
3450 | |
3451 | /** | |
3452 | * ixgbe_calculate_checksum - Calculate checksum for buffer | |
3453 | * @buffer: pointer to EEPROM | |
3454 | * @length: size of EEPROM to calculate a checksum for | |
49ce9c2c | 3455 | * |
9612de92 ET |
3456 | * Calculates the checksum for some buffer on a specified length. The |
3457 | * checksum calculated is returned. | |
3458 | **/ | |
3459 | static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length) | |
3460 | { | |
3461 | u32 i; | |
3462 | u8 sum = 0; | |
3463 | ||
3464 | if (!buffer) | |
3465 | return 0; | |
3466 | ||
3467 | for (i = 0; i < length; i++) | |
3468 | sum += buffer[i]; | |
3469 | ||
3470 | return (u8) (0 - sum); | |
3471 | } | |
3472 | ||
3473 | /** | |
3474 | * ixgbe_host_interface_command - Issue command to manageability block | |
3475 | * @hw: pointer to the HW structure | |
3476 | * @buffer: contains the command to write and where the return status will | |
3477 | * be placed | |
c466d7a7 | 3478 | * @length: length of buffer, must be multiple of 4 bytes |
b48e4aa3 DS |
3479 | * @timeout: time in ms to wait for command completion |
3480 | * @return_data: read and return data from the buffer (true) or not (false) | |
3481 | * Needed because FW structures are big endian and decoding of | |
3482 | * these fields can be 8 bit or 16 bit based on command. Decoding | |
3483 | * is not easily understood without making a table of commands. | |
3484 | * So we will leave this up to the caller to read back the data | |
3485 | * in these cases. | |
9612de92 ET |
3486 | * |
3487 | * Communicates with the manageability block. On success return 0 | |
3488 | * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. | |
3489 | **/ | |
5cffde30 | 3490 | s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer, |
6a14ee0c DS |
3491 | u32 length, u32 timeout, |
3492 | bool return_data) | |
9612de92 | 3493 | { |
9612de92 | 3494 | u32 hdr_size = sizeof(struct ixgbe_hic_hdr); |
5cffde30 | 3495 | u32 hicr, i, bi, fwsts; |
b48e4aa3 | 3496 | u16 buf_len, dword_len; |
5cffde30 MR |
3497 | union { |
3498 | struct ixgbe_hic_hdr hdr; | |
3499 | u32 u32arr[1]; | |
3500 | } *bp = buffer; | |
af741901 | 3501 | s32 status; |
9612de92 | 3502 | |
5cffde30 | 3503 | if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { |
b48e4aa3 | 3504 | hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length); |
e90dd264 | 3505 | return IXGBE_ERR_HOST_INTERFACE_COMMAND; |
9612de92 | 3506 | } |
af741901 MR |
3507 | /* Take management host interface semaphore */ |
3508 | status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); | |
3509 | if (status) | |
3510 | return status; | |
9612de92 | 3511 | |
b48e4aa3 DS |
3512 | /* Set bit 9 of FWSTS clearing FW reset indication */ |
3513 | fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); | |
3514 | IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); | |
3515 | ||
9612de92 ET |
3516 | /* Check that the host interface is enabled. */ |
3517 | hicr = IXGBE_READ_REG(hw, IXGBE_HICR); | |
5cffde30 | 3518 | if (!(hicr & IXGBE_HICR_EN)) { |
9612de92 | 3519 | hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n"); |
af741901 MR |
3520 | status = IXGBE_ERR_HOST_INTERFACE_COMMAND; |
3521 | goto rel_out; | |
9612de92 ET |
3522 | } |
3523 | ||
b48e4aa3 | 3524 | /* Calculate length in DWORDs. We must be DWORD aligned */ |
5cffde30 | 3525 | if (length % sizeof(u32)) { |
b48e4aa3 | 3526 | hw_dbg(hw, "Buffer length failure, not aligned to dword"); |
af741901 MR |
3527 | status = IXGBE_ERR_INVALID_ARGUMENT; |
3528 | goto rel_out; | |
b48e4aa3 DS |
3529 | } |
3530 | ||
9612de92 ET |
3531 | dword_len = length >> 2; |
3532 | ||
5cffde30 | 3533 | /* The device driver writes the relevant command block |
9612de92 ET |
3534 | * into the ram area. |
3535 | */ | |
3536 | for (i = 0; i < dword_len; i++) | |
3537 | IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, | |
5cffde30 | 3538 | i, cpu_to_le32(bp->u32arr[i])); |
9612de92 ET |
3539 | |
3540 | /* Setting this bit tells the ARC that a new command is pending. */ | |
3541 | IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); | |
3542 | ||
b48e4aa3 | 3543 | for (i = 0; i < timeout; i++) { |
9612de92 ET |
3544 | hicr = IXGBE_READ_REG(hw, IXGBE_HICR); |
3545 | if (!(hicr & IXGBE_HICR_C)) | |
3546 | break; | |
3547 | usleep_range(1000, 2000); | |
3548 | } | |
3549 | ||
3550 | /* Check command successful completion. */ | |
5cffde30 MR |
3551 | if ((timeout && i == timeout) || |
3552 | !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { | |
9612de92 | 3553 | hw_dbg(hw, "Command has failed with no status valid.\n"); |
af741901 MR |
3554 | status = IXGBE_ERR_HOST_INTERFACE_COMMAND; |
3555 | goto rel_out; | |
9612de92 ET |
3556 | } |
3557 | ||
b48e4aa3 | 3558 | if (!return_data) |
af741901 | 3559 | goto rel_out; |
b48e4aa3 | 3560 | |
9612de92 ET |
3561 | /* Calculate length in DWORDs */ |
3562 | dword_len = hdr_size >> 2; | |
3563 | ||
3564 | /* first pull in the header so we know the buffer length */ | |
331bcf45 | 3565 | for (bi = 0; bi < dword_len; bi++) { |
5cffde30 MR |
3566 | bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); |
3567 | le32_to_cpus(&bp->u32arr[bi]); | |
79488c58 | 3568 | } |
9612de92 ET |
3569 | |
3570 | /* If there is any thing in data position pull it in */ | |
5cffde30 MR |
3571 | buf_len = bp->hdr.buf_len; |
3572 | if (!buf_len) | |
af741901 | 3573 | goto rel_out; |
9612de92 | 3574 | |
73457165 | 3575 | if (length < round_up(buf_len, 4) + hdr_size) { |
9612de92 | 3576 | hw_dbg(hw, "Buffer not large enough for reply message.\n"); |
af741901 MR |
3577 | status = IXGBE_ERR_HOST_INTERFACE_COMMAND; |
3578 | goto rel_out; | |
9612de92 ET |
3579 | } |
3580 | ||
331bcf45 ET |
3581 | /* Calculate length in DWORDs, add 3 for odd lengths */ |
3582 | dword_len = (buf_len + 3) >> 2; | |
9612de92 | 3583 | |
5cffde30 | 3584 | /* Pull in the rest of the buffer (bi is where we left off) */ |
331bcf45 | 3585 | for (; bi <= dword_len; bi++) { |
5cffde30 MR |
3586 | bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); |
3587 | le32_to_cpus(&bp->u32arr[bi]); | |
331bcf45 | 3588 | } |
9612de92 | 3589 | |
af741901 MR |
3590 | rel_out: |
3591 | hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); | |
3592 | ||
3593 | return status; | |
9612de92 ET |
3594 | } |
3595 | ||
3596 | /** | |
3597 | * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware | |
3598 | * @hw: pointer to the HW structure | |
3599 | * @maj: driver version major number | |
3600 | * @min: driver version minor number | |
3601 | * @build: driver version build number | |
3602 | * @sub: driver version sub build number | |
3603 | * | |
3604 | * Sends driver version number to firmware through the manageability | |
3605 | * block. On success return 0 | |
3606 | * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring | |
3607 | * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. | |
3608 | **/ | |
3609 | s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, | |
3610 | u8 build, u8 sub) | |
3611 | { | |
3612 | struct ixgbe_hic_drv_info fw_cmd; | |
3613 | int i; | |
e90dd264 | 3614 | s32 ret_val; |
9612de92 | 3615 | |
9612de92 ET |
3616 | fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; |
3617 | fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; | |
3618 | fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; | |
3775b814 | 3619 | fw_cmd.port_num = hw->bus.func; |
9612de92 ET |
3620 | fw_cmd.ver_maj = maj; |
3621 | fw_cmd.ver_min = min; | |
3622 | fw_cmd.ver_build = build; | |
3623 | fw_cmd.ver_sub = sub; | |
3624 | fw_cmd.hdr.checksum = 0; | |
3625 | fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, | |
3626 | (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); | |
3627 | fw_cmd.pad = 0; | |
3628 | fw_cmd.pad2 = 0; | |
3629 | ||
3630 | for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { | |
5cffde30 | 3631 | ret_val = ixgbe_host_interface_command(hw, &fw_cmd, |
b48e4aa3 DS |
3632 | sizeof(fw_cmd), |
3633 | IXGBE_HI_COMMAND_TIMEOUT, | |
3634 | true); | |
9612de92 ET |
3635 | if (ret_val != 0) |
3636 | continue; | |
3637 | ||
3638 | if (fw_cmd.hdr.cmd_or_resp.ret_status == | |
3639 | FW_CEM_RESP_STATUS_SUCCESS) | |
3640 | ret_val = 0; | |
3641 | else | |
3642 | ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; | |
3643 | ||
3644 | break; | |
3645 | } | |
3646 | ||
9612de92 ET |
3647 | return ret_val; |
3648 | } | |
ff9d1a5a ET |
3649 | |
3650 | /** | |
3651 | * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo | |
3652 | * @hw: pointer to the hardware structure | |
3653 | * | |
3654 | * The 82599 and x540 MACs can experience issues if TX work is still pending | |
3655 | * when a reset occurs. This function prevents this by flushing the PCIe | |
3656 | * buffers on the system. | |
3657 | **/ | |
3658 | void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) | |
3659 | { | |
71bde601 DS |
3660 | u32 gcr_ext, hlreg0, i, poll; |
3661 | u16 value; | |
ff9d1a5a ET |
3662 | |
3663 | /* | |
3664 | * If double reset is not requested then all transactions should | |
3665 | * already be clear and as such there is no work to do | |
3666 | */ | |
3667 | if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) | |
3668 | return; | |
3669 | ||
3670 | /* | |
3671 | * Set loopback enable to prevent any transmits from being sent | |
3672 | * should the link come up. This assumes that the RXCTRL.RXEN bit | |
3673 | * has already been cleared. | |
3674 | */ | |
3675 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
3676 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); | |
3677 | ||
71bde601 DS |
3678 | /* wait for a last completion before clearing buffers */ |
3679 | IXGBE_WRITE_FLUSH(hw); | |
3680 | usleep_range(3000, 6000); | |
3681 | ||
3682 | /* Before proceeding, make sure that the PCIe block does not have | |
3683 | * transactions pending. | |
3684 | */ | |
3685 | poll = ixgbe_pcie_timeout_poll(hw); | |
3686 | for (i = 0; i < poll; i++) { | |
3687 | usleep_range(100, 200); | |
3688 | value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS); | |
3689 | if (ixgbe_removed(hw->hw_addr)) | |
3690 | break; | |
3691 | if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) | |
3692 | break; | |
3693 | } | |
3694 | ||
ff9d1a5a ET |
3695 | /* initiate cleaning flow for buffers in the PCIe transaction layer */ |
3696 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3697 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, | |
3698 | gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); | |
3699 | ||
3700 | /* Flush all writes and allow 20usec for all transactions to clear */ | |
3701 | IXGBE_WRITE_FLUSH(hw); | |
3702 | udelay(20); | |
3703 | ||
3704 | /* restore previous register values */ | |
3705 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3706 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
3707 | } | |
e1ea9158 DS |
3708 | |
3709 | static const u8 ixgbe_emc_temp_data[4] = { | |
3710 | IXGBE_EMC_INTERNAL_DATA, | |
3711 | IXGBE_EMC_DIODE1_DATA, | |
3712 | IXGBE_EMC_DIODE2_DATA, | |
3713 | IXGBE_EMC_DIODE3_DATA | |
3714 | }; | |
3715 | static const u8 ixgbe_emc_therm_limit[4] = { | |
3716 | IXGBE_EMC_INTERNAL_THERM_LIMIT, | |
3717 | IXGBE_EMC_DIODE1_THERM_LIMIT, | |
3718 | IXGBE_EMC_DIODE2_THERM_LIMIT, | |
3719 | IXGBE_EMC_DIODE3_THERM_LIMIT | |
3720 | }; | |
3721 | ||
3722 | /** | |
3723 | * ixgbe_get_ets_data - Extracts the ETS bit data | |
3724 | * @hw: pointer to hardware structure | |
3725 | * @ets_cfg: extected ETS data | |
3726 | * @ets_offset: offset of ETS data | |
3727 | * | |
3728 | * Returns error code. | |
3729 | **/ | |
3730 | static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg, | |
3731 | u16 *ets_offset) | |
3732 | { | |
e90dd264 | 3733 | s32 status; |
e1ea9158 DS |
3734 | |
3735 | status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset); | |
3736 | if (status) | |
e90dd264 | 3737 | return status; |
e1ea9158 | 3738 | |
e90dd264 MR |
3739 | if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) |
3740 | return IXGBE_NOT_IMPLEMENTED; | |
e1ea9158 DS |
3741 | |
3742 | status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg); | |
3743 | if (status) | |
e90dd264 | 3744 | return status; |
e1ea9158 | 3745 | |
e90dd264 MR |
3746 | if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) |
3747 | return IXGBE_NOT_IMPLEMENTED; | |
e1ea9158 | 3748 | |
e90dd264 | 3749 | return 0; |
e1ea9158 DS |
3750 | } |
3751 | ||
3752 | /** | |
3753 | * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data | |
3754 | * @hw: pointer to hardware structure | |
3755 | * | |
3756 | * Returns the thermal sensor data structure | |
3757 | **/ | |
3758 | s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) | |
3759 | { | |
e90dd264 | 3760 | s32 status; |
e1ea9158 DS |
3761 | u16 ets_offset; |
3762 | u16 ets_cfg; | |
3763 | u16 ets_sensor; | |
3764 | u8 num_sensors; | |
3765 | u8 i; | |
3766 | struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; | |
3767 | ||
3ca8bc6d | 3768 | /* Only support thermal sensors attached to physical port 0 */ |
e90dd264 MR |
3769 | if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) |
3770 | return IXGBE_NOT_IMPLEMENTED; | |
e1ea9158 DS |
3771 | |
3772 | status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); | |
3773 | if (status) | |
e90dd264 | 3774 | return status; |
e1ea9158 DS |
3775 | |
3776 | num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); | |
3777 | if (num_sensors > IXGBE_MAX_SENSORS) | |
3778 | num_sensors = IXGBE_MAX_SENSORS; | |
3779 | ||
3780 | for (i = 0; i < num_sensors; i++) { | |
3781 | u8 sensor_index; | |
3782 | u8 sensor_location; | |
3783 | ||
3784 | status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), | |
3785 | &ets_sensor); | |
3786 | if (status) | |
e90dd264 | 3787 | return status; |
e1ea9158 DS |
3788 | |
3789 | sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> | |
3790 | IXGBE_ETS_DATA_INDEX_SHIFT); | |
3791 | sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> | |
3792 | IXGBE_ETS_DATA_LOC_SHIFT); | |
3793 | ||
3794 | if (sensor_location != 0) { | |
3795 | status = hw->phy.ops.read_i2c_byte(hw, | |
3796 | ixgbe_emc_temp_data[sensor_index], | |
3797 | IXGBE_I2C_THERMAL_SENSOR_ADDR, | |
3798 | &data->sensor[i].temp); | |
3799 | if (status) | |
e90dd264 | 3800 | return status; |
e1ea9158 DS |
3801 | } |
3802 | } | |
e90dd264 MR |
3803 | |
3804 | return 0; | |
e1ea9158 DS |
3805 | } |
3806 | ||
3807 | /** | |
3808 | * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds | |
3809 | * @hw: pointer to hardware structure | |
3810 | * | |
3811 | * Inits the thermal sensor thresholds according to the NVM map | |
3812 | * and save off the threshold and location values into mac.thermal_sensor_data | |
3813 | **/ | |
3814 | s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) | |
3815 | { | |
e90dd264 | 3816 | s32 status; |
e1ea9158 DS |
3817 | u16 ets_offset; |
3818 | u16 ets_cfg; | |
3819 | u16 ets_sensor; | |
3820 | u8 low_thresh_delta; | |
3821 | u8 num_sensors; | |
3822 | u8 therm_limit; | |
3823 | u8 i; | |
3824 | struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; | |
3825 | ||
3826 | memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data)); | |
3827 | ||
3ca8bc6d | 3828 | /* Only support thermal sensors attached to physical port 0 */ |
e90dd264 MR |
3829 | if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) |
3830 | return IXGBE_NOT_IMPLEMENTED; | |
e1ea9158 DS |
3831 | |
3832 | status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset); | |
3833 | if (status) | |
e90dd264 | 3834 | return status; |
e1ea9158 DS |
3835 | |
3836 | low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >> | |
3837 | IXGBE_ETS_LTHRES_DELTA_SHIFT); | |
3838 | num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK); | |
3839 | if (num_sensors > IXGBE_MAX_SENSORS) | |
3840 | num_sensors = IXGBE_MAX_SENSORS; | |
3841 | ||
3842 | for (i = 0; i < num_sensors; i++) { | |
3843 | u8 sensor_index; | |
3844 | u8 sensor_location; | |
3845 | ||
be0c27b4 MR |
3846 | if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) { |
3847 | hw_err(hw, "eeprom read at offset %d failed\n", | |
3848 | ets_offset + 1 + i); | |
3849 | continue; | |
3850 | } | |
e1ea9158 DS |
3851 | sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >> |
3852 | IXGBE_ETS_DATA_INDEX_SHIFT); | |
3853 | sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >> | |
3854 | IXGBE_ETS_DATA_LOC_SHIFT); | |
3855 | therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK; | |
3856 | ||
3857 | hw->phy.ops.write_i2c_byte(hw, | |
3858 | ixgbe_emc_therm_limit[sensor_index], | |
3859 | IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit); | |
3860 | ||
3861 | if (sensor_location == 0) | |
3862 | continue; | |
3863 | ||
3864 | data->sensor[i].location = sensor_location; | |
3865 | data->sensor[i].caution_thresh = therm_limit; | |
3866 | data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta; | |
3867 | } | |
e90dd264 MR |
3868 | |
3869 | return 0; | |
e1ea9158 DS |
3870 | } |
3871 | ||
1f9ac57c DS |
3872 | void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) |
3873 | { | |
3874 | u32 rxctrl; | |
3875 | ||
3876 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3877 | if (rxctrl & IXGBE_RXCTRL_RXEN) { | |
3878 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3879 | u32 pfdtxgswc; | |
3880 | ||
3881 | pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); | |
3882 | if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { | |
3883 | pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; | |
3884 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); | |
3885 | hw->mac.set_lben = true; | |
3886 | } else { | |
3887 | hw->mac.set_lben = false; | |
3888 | } | |
3889 | } | |
3890 | rxctrl &= ~IXGBE_RXCTRL_RXEN; | |
3891 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); | |
3892 | } | |
3893 | } | |
3894 | ||
3895 | void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) | |
3896 | { | |
3897 | u32 rxctrl; | |
3898 | ||
3899 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3900 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); | |
3901 | ||
3902 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3903 | if (hw->mac.set_lben) { | |
3904 | u32 pfdtxgswc; | |
3905 | ||
3906 | pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); | |
3907 | pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN; | |
3908 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); | |
3909 | hw->mac.set_lben = false; | |
3910 | } | |
3911 | } | |
3912 | } | |
bd8069ac DS |
3913 | |
3914 | /** ixgbe_mng_present - returns true when management capability is present | |
3915 | * @hw: pointer to hardware structure | |
3916 | **/ | |
3917 | bool ixgbe_mng_present(struct ixgbe_hw *hw) | |
3918 | { | |
3919 | u32 fwsm; | |
3920 | ||
3921 | if (hw->mac.type < ixgbe_mac_82599EB) | |
3922 | return false; | |
3923 | ||
3924 | fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); | |
3925 | fwsm &= IXGBE_FWSM_MODE_MASK; | |
3926 | return fwsm == IXGBE_FWSM_FW_MODE_PT; | |
3927 | } | |
6d373a1b MR |
3928 | |
3929 | /** | |
3930 | * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed | |
3931 | * @hw: pointer to hardware structure | |
3932 | * @speed: new link speed | |
3933 | * @autoneg_wait_to_complete: true when waiting for completion is needed | |
3934 | * | |
3935 | * Set the link speed in the MAC and/or PHY register and restarts link. | |
3936 | */ | |
3937 | s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, | |
3938 | ixgbe_link_speed speed, | |
3939 | bool autoneg_wait_to_complete) | |
3940 | { | |
3941 | ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; | |
3942 | ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN; | |
3943 | s32 status = 0; | |
3944 | u32 speedcnt = 0; | |
3945 | u32 i = 0; | |
3946 | bool autoneg, link_up = false; | |
3947 | ||
3948 | /* Mask off requested but non-supported speeds */ | |
3949 | status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg); | |
3950 | if (status) | |
3951 | return status; | |
3952 | ||
3953 | speed &= link_speed; | |
3954 | ||
3955 | /* Try each speed one by one, highest priority first. We do this in | |
3956 | * software because 10Gb fiber doesn't support speed autonegotiation. | |
3957 | */ | |
3958 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { | |
3959 | speedcnt++; | |
3960 | highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
3961 | ||
3962 | /* If we already have link at this speed, just jump out */ | |
3963 | status = hw->mac.ops.check_link(hw, &link_speed, &link_up, | |
3964 | false); | |
3965 | if (status) | |
3966 | return status; | |
3967 | ||
3968 | if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up) | |
3969 | goto out; | |
3970 | ||
3971 | /* Set the module link speed */ | |
3972 | switch (hw->phy.media_type) { | |
3973 | case ixgbe_media_type_fiber: | |
3974 | hw->mac.ops.set_rate_select_speed(hw, | |
3975 | IXGBE_LINK_SPEED_10GB_FULL); | |
3976 | break; | |
3977 | case ixgbe_media_type_fiber_qsfp: | |
3978 | /* QSFP module automatically detects MAC link speed */ | |
3979 | break; | |
3980 | default: | |
3981 | hw_dbg(hw, "Unexpected media type\n"); | |
3982 | break; | |
3983 | } | |
3984 | ||
3985 | /* Allow module to change analog characteristics (1G->10G) */ | |
3986 | msleep(40); | |
3987 | ||
3988 | status = hw->mac.ops.setup_mac_link(hw, | |
3989 | IXGBE_LINK_SPEED_10GB_FULL, | |
3990 | autoneg_wait_to_complete); | |
3991 | if (status) | |
3992 | return status; | |
3993 | ||
3994 | /* Flap the Tx laser if it has not already been done */ | |
3995 | if (hw->mac.ops.flap_tx_laser) | |
3996 | hw->mac.ops.flap_tx_laser(hw); | |
3997 | ||
3998 | /* Wait for the controller to acquire link. Per IEEE 802.3ap, | |
3999 | * Section 73.10.2, we may have to wait up to 500ms if KR is | |
4000 | * attempted. 82599 uses the same timing for 10g SFI. | |
4001 | */ | |
4002 | for (i = 0; i < 5; i++) { | |
4003 | /* Wait for the link partner to also set speed */ | |
4004 | msleep(100); | |
4005 | ||
4006 | /* If we have link, just jump out */ | |
4007 | status = hw->mac.ops.check_link(hw, &link_speed, | |
4008 | &link_up, false); | |
4009 | if (status) | |
4010 | return status; | |
4011 | ||
4012 | if (link_up) | |
4013 | goto out; | |
4014 | } | |
4015 | } | |
4016 | ||
4017 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { | |
4018 | speedcnt++; | |
4019 | if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN) | |
4020 | highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL; | |
4021 | ||
4022 | /* If we already have link at this speed, just jump out */ | |
4023 | status = hw->mac.ops.check_link(hw, &link_speed, &link_up, | |
4024 | false); | |
4025 | if (status) | |
4026 | return status; | |
4027 | ||
4028 | if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up) | |
4029 | goto out; | |
4030 | ||
4031 | /* Set the module link speed */ | |
4032 | switch (hw->phy.media_type) { | |
4033 | case ixgbe_media_type_fiber: | |
4034 | hw->mac.ops.set_rate_select_speed(hw, | |
4035 | IXGBE_LINK_SPEED_1GB_FULL); | |
4036 | break; | |
4037 | case ixgbe_media_type_fiber_qsfp: | |
4038 | /* QSFP module automatically detects link speed */ | |
4039 | break; | |
4040 | default: | |
4041 | hw_dbg(hw, "Unexpected media type\n"); | |
4042 | break; | |
4043 | } | |
4044 | ||
4045 | /* Allow module to change analog characteristics (10G->1G) */ | |
4046 | msleep(40); | |
4047 | ||
4048 | status = hw->mac.ops.setup_mac_link(hw, | |
4049 | IXGBE_LINK_SPEED_1GB_FULL, | |
4050 | autoneg_wait_to_complete); | |
4051 | if (status) | |
4052 | return status; | |
4053 | ||
4054 | /* Flap the Tx laser if it has not already been done */ | |
4055 | if (hw->mac.ops.flap_tx_laser) | |
4056 | hw->mac.ops.flap_tx_laser(hw); | |
4057 | ||
4058 | /* Wait for the link partner to also set speed */ | |
4059 | msleep(100); | |
4060 | ||
4061 | /* If we have link, just jump out */ | |
4062 | status = hw->mac.ops.check_link(hw, &link_speed, &link_up, | |
4063 | false); | |
4064 | if (status) | |
4065 | return status; | |
4066 | ||
4067 | if (link_up) | |
4068 | goto out; | |
4069 | } | |
4070 | ||
4071 | /* We didn't get link. Configure back to the highest speed we tried, | |
4072 | * (if there was more than one). We call ourselves back with just the | |
4073 | * single highest speed that the user requested. | |
4074 | */ | |
4075 | if (speedcnt > 1) | |
4076 | status = ixgbe_setup_mac_link_multispeed_fiber(hw, | |
4077 | highest_link_speed, | |
4078 | autoneg_wait_to_complete); | |
4079 | ||
4080 | out: | |
4081 | /* Set autoneg_advertised value based on input link speed */ | |
4082 | hw->phy.autoneg_advertised = 0; | |
4083 | ||
4084 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
4085 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; | |
4086 | ||
4087 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) | |
4088 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; | |
4089 | ||
4090 | return status; | |
4091 | } | |
4092 | ||
4093 | /** | |
4094 | * ixgbe_set_soft_rate_select_speed - Set module link speed | |
4095 | * @hw: pointer to hardware structure | |
4096 | * @speed: link speed to set | |
4097 | * | |
4098 | * Set module link speed via the soft rate select. | |
4099 | */ | |
4100 | void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, | |
4101 | ixgbe_link_speed speed) | |
4102 | { | |
4103 | s32 status; | |
4104 | u8 rs, eeprom_data; | |
4105 | ||
4106 | switch (speed) { | |
4107 | case IXGBE_LINK_SPEED_10GB_FULL: | |
4108 | /* one bit mask same as setting on */ | |
4109 | rs = IXGBE_SFF_SOFT_RS_SELECT_10G; | |
4110 | break; | |
4111 | case IXGBE_LINK_SPEED_1GB_FULL: | |
4112 | rs = IXGBE_SFF_SOFT_RS_SELECT_1G; | |
4113 | break; | |
4114 | default: | |
4115 | hw_dbg(hw, "Invalid fixed module speed\n"); | |
4116 | return; | |
4117 | } | |
4118 | ||
4119 | /* Set RS0 */ | |
4120 | status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, | |
4121 | IXGBE_I2C_EEPROM_DEV_ADDR2, | |
4122 | &eeprom_data); | |
4123 | if (status) { | |
4124 | hw_dbg(hw, "Failed to read Rx Rate Select RS0\n"); | |
4125 | return; | |
4126 | } | |
4127 | ||
4128 | eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs; | |
4129 | ||
4130 | status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, | |
4131 | IXGBE_I2C_EEPROM_DEV_ADDR2, | |
4132 | eeprom_data); | |
4133 | if (status) { | |
4134 | hw_dbg(hw, "Failed to write Rx Rate Select RS0\n"); | |
4135 | return; | |
4136 | } | |
4137 | } |