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Merge branch 'for-davem' into for-next
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
14438464 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
ccffad25 32#include <linux/netdevice.h>
9a799d71 33
11afc1b1 34#include "ixgbe.h"
9a799d71
AK		 35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
c44ade9e 38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
9a799d71
AK		 39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
c44ade9e
JB		 41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 44 u16 count);
c44ade9e
JB		 45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
9a799d71 49
9a799d71 50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
eb9c3e3e 51static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
68c7005d
ET		 52static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
ff9d1a5a 58static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
9a799d71 59
67a79df2
AD		 60/**
61 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
62 * control
63 * @hw: pointer to hardware structure
64 *
65 * There are several phys that do not support autoneg flow control. This
66 * function check the device id to see if the associated phy supports
67 * autoneg flow control.
68 **/
73d80953 69bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
67a79df2 70{
73d80953
DS		 71 bool supported = false;
72 ixgbe_link_speed speed;
73 bool link_up;
67a79df2 74
73d80953
DS		 75 switch (hw->phy.media_type) {
76 case ixgbe_media_type_fiber:
77 hw->mac.ops.check_link(hw, &speed, &link_up, false);
78 /* if link is down, assume supported */
79 if (link_up)
80 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
81 true : false;
82 else
83 supported = true;
84 break;
85 case ixgbe_media_type_backplane:
86 supported = true;
87 break;
88 case ixgbe_media_type_copper:
89 /* only some copper devices support flow control autoneg */
90 switch (hw->device_id) {
91 case IXGBE_DEV_ID_82599_T3_LOM:
92 case IXGBE_DEV_ID_X540T:
93 case IXGBE_DEV_ID_X540T1:
94 supported = true;
95 break;
96 default:
97 break;
98 }
67a79df2 99 default:
73d80953 100 break;
67a79df2 101 }
73d80953
DS		 102
103 return supported;
67a79df2
AD		 104}
105
106/**
107 * ixgbe_setup_fc - Set up flow control
108 * @hw: pointer to hardware structure
109 *
110 * Called at init time to set up flow control.
111 **/
041441d0 112static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
67a79df2
AD		 113{
114 s32 ret_val = 0;
115 u32 reg = 0, reg_bp = 0;
116 u16 reg_cu = 0;
429d6a3b 117 bool locked = false;
67a79df2 118
67a79df2
AD		 119 /*
120 * Validate the requested mode. Strict IEEE mode does not allow
121 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
122 */
123 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
124 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
e90dd264 125 return IXGBE_ERR_INVALID_LINK_SETTINGS;
67a79df2
AD		 126 }
127
128 /*
129 * 10gig parts do not have a word in the EEPROM to determine the
130 * default flow control setting, so we explicitly set it to full.
131 */
132 if (hw->fc.requested_mode == ixgbe_fc_default)
133 hw->fc.requested_mode = ixgbe_fc_full;
134
135 /*
136 * Set up the 1G and 10G flow control advertisement registers so the
137 * HW will be able to do fc autoneg once the cable is plugged in. If
138 * we link at 10G, the 1G advertisement is harmless and vice versa.
139 */
67a79df2 140 switch (hw->phy.media_type) {
429d6a3b
DS		 141 case ixgbe_media_type_backplane:
142 /* some MAC's need RMW protection on AUTOC */
143 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
f8cf7a00 144 if (ret_val)
e90dd264 145 return ret_val;
429d6a3b
DS		 146
147 /* only backplane uses autoc so fall though */
67a79df2 148 case ixgbe_media_type_fiber:
67a79df2 149 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
429d6a3b 150
67a79df2 151 break;
67a79df2
AD		 152 case ixgbe_media_type_copper:
153 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
154 MDIO_MMD_AN, &reg_cu);
155 break;
67a79df2 156 default:
041441d0 157 break;
67a79df2
AD		 158 }
159
160 /*
161 * The possible values of fc.requested_mode are:
162 * 0: Flow control is completely disabled
163 * 1: Rx flow control is enabled (we can receive pause frames,
164 * but not send pause frames).
165 * 2: Tx flow control is enabled (we can send pause frames but
166 * we do not support receiving pause frames).
167 * 3: Both Rx and Tx flow control (symmetric) are enabled.
67a79df2
AD		 168 * other: Invalid.
169 */
170 switch (hw->fc.requested_mode) {
171 case ixgbe_fc_none:
172 /* Flow control completely disabled by software override. */
173 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
174 if (hw->phy.media_type == ixgbe_media_type_backplane)
175 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
176 IXGBE_AUTOC_ASM_PAUSE);
177 else if (hw->phy.media_type == ixgbe_media_type_copper)
178 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
179 break;
67a79df2
AD		 180 case ixgbe_fc_tx_pause:
181 /*
182 * Tx Flow control is enabled, and Rx Flow control is
183 * disabled by software override.
184 */
041441d0
AD		 185 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
186 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
67a79df2 187 if (hw->phy.media_type == ixgbe_media_type_backplane) {
041441d0
AD		 188 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
189 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
67a79df2 190 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
041441d0
AD		 191 reg_cu |= IXGBE_TAF_ASM_PAUSE;
192 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
67a79df2
AD		 193 }
194 break;
041441d0
AD		 195 case ixgbe_fc_rx_pause:
196 /*
197 * Rx Flow control is enabled and Tx Flow control is
198 * disabled by software override. Since there really
199 * isn't a way to advertise that we are capable of RX
200 * Pause ONLY, we will advertise that we support both
201 * symmetric and asymmetric Rx PAUSE, as such we fall
202 * through to the fc_full statement. Later, we will
203 * disable the adapter's ability to send PAUSE frames.
204 */
67a79df2
AD		 205 case ixgbe_fc_full:
206 /* Flow control (both Rx and Tx) is enabled by SW override. */
041441d0 207 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
67a79df2 208 if (hw->phy.media_type == ixgbe_media_type_backplane)
041441d0
AD		 209 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
210 IXGBE_AUTOC_ASM_PAUSE;
67a79df2 211 else if (hw->phy.media_type == ixgbe_media_type_copper)
041441d0 212 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
67a79df2 213 break;
67a79df2
AD		 214 default:
215 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 216 return IXGBE_ERR_CONFIG;
67a79df2
AD		 217 }
218
219 if (hw->mac.type != ixgbe_mac_X540) {
220 /*
221 * Enable auto-negotiation between the MAC & PHY;
222 * the MAC will advertise clause 37 flow control.
223 */
224 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
225 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
226
227 /* Disable AN timeout */
228 if (hw->fc.strict_ieee)
229 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
230
231 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
232 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
233 }
234
235 /*
236 * AUTOC restart handles negotiation of 1G and 10G on backplane
237 * and copper. There is no need to set the PCS1GCTL register.
238 *
239 */
240 if (hw->phy.media_type == ixgbe_media_type_backplane) {
d7bbcd32
DS		 241 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
242 * LESM is on, likewise reset_pipeline requries the lock as
243 * it also writes AUTOC.
244 */
429d6a3b
DS		 245 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
246 if (ret_val)
e90dd264 247 return ret_val;
d7bbcd32 248
67a79df2 249 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
429d6a3b 250 ixgbe_device_supports_autoneg_fc(hw)) {
67a79df2
AD		 251 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
252 MDIO_MMD_AN, reg_cu);
253 }
254
255 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
67a79df2
AD		 256 return ret_val;
257}
258
9a799d71 259/**
c44ade9e 260 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
9a799d71
AK		 261 * @hw: pointer to hardware structure
262 *
263 * Starts the hardware by filling the bus info structure and media type, clears
264 * all on chip counters, initializes receive address registers, multicast
265 * table, VLAN filter table, calls routine to set up link and flow control
266 * settings, and leaves transmit and receive units disabled and uninitialized
267 **/
c44ade9e 268s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
9a799d71 269{
e5776620 270 s32 ret_val;
9a799d71
AK		 271 u32 ctrl_ext;
272
273 /* Set the media type */
274 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
275
276 /* Identify the PHY */
c44ade9e 277 hw->phy.ops.identify(hw);
9a799d71 278
9a799d71 279 /* Clear the VLAN filter table */
c44ade9e 280 hw->mac.ops.clear_vfta(hw);
9a799d71 281
9a799d71 282 /* Clear statistics registers */
c44ade9e 283 hw->mac.ops.clear_hw_cntrs(hw);
9a799d71
AK		 284
285 /* Set No Snoop Disable */
286 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
287 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
288 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3957d63d 289 IXGBE_WRITE_FLUSH(hw);
9a799d71 290
620fa036 291 /* Setup flow control */
e5776620
JK		 292 ret_val = ixgbe_setup_fc(hw);
293 if (!ret_val)
e90dd264 294 return 0;
620fa036 295
9a799d71
AK		 296 /* Clear adapter stopped flag */
297 hw->adapter_stopped = false;
298
e5776620 299 return ret_val;
9a799d71
AK		 300}
301
7184b7cf
ET		 302/**
303 * ixgbe_start_hw_gen2 - Init sequence for common device family
304 * @hw: pointer to hw structure
305 *
306 * Performs the init sequence common to the second generation
307 * of 10 GbE devices.
308 * Devices in the second generation:
309 * 82599
310 * X540
311 **/
312s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
313{
314 u32 i;
315
316 /* Clear the rate limiters */
317 for (i = 0; i < hw->mac.max_tx_queues; i++) {
318 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
319 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
320 }
321 IXGBE_WRITE_FLUSH(hw);
322
887012e8 323#ifndef CONFIG_SPARC
3d5c5207
ET		 324 /* Disable relaxed ordering */
325 for (i = 0; i < hw->mac.max_tx_queues; i++) {
887012e8
JK		 326 u32 regval;
327
3d5c5207 328 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
bdda1a61 329 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3d5c5207
ET		 330 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
331 }
332
333 for (i = 0; i < hw->mac.max_rx_queues; i++) {
887012e8
JK		 334 u32 regval;
335
3d5c5207 336 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
bdda1a61
AD		 337 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
338 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
3d5c5207
ET		 339 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
340 }
887012e8 341#endif
7184b7cf
ET		 342 return 0;
343}
344
9a799d71 345/**
c44ade9e 346 * ixgbe_init_hw_generic - Generic hardware initialization
9a799d71
AK		 347 * @hw: pointer to hardware structure
348 *
c44ade9e 349 * Initialize the hardware by resetting the hardware, filling the bus info
9a799d71
AK		 350 * structure and media type, clears all on chip counters, initializes receive
351 * address registers, multicast table, VLAN filter table, calls routine to set
352 * up link and flow control settings, and leaves transmit and receive units
353 * disabled and uninitialized
354 **/
c44ade9e 355s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
9a799d71 356{
794caeb2
PWJ		 357 s32 status;
358
9a799d71 359 /* Reset the hardware */
794caeb2 360 status = hw->mac.ops.reset_hw(hw);
9a799d71 361
794caeb2
PWJ		 362 if (status == 0) {
363 /* Start the HW */
364 status = hw->mac.ops.start_hw(hw);
365 }
9a799d71 366
794caeb2 367 return status;
9a799d71
AK		 368}
369
370/**
c44ade9e 371 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
9a799d71
AK		 372 * @hw: pointer to hardware structure
373 *
374 * Clears all hardware statistics counters by reading them from the hardware
375 * Statistics counters are clear on read.
376 **/
c44ade9e 377s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 378{
379 u16 i = 0;
380
381 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
382 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
383 IXGBE_READ_REG(hw, IXGBE_ERRBC);
384 IXGBE_READ_REG(hw, IXGBE_MSPDC);
385 for (i = 0; i < 8; i++)
386 IXGBE_READ_REG(hw, IXGBE_MPC(i));
387
388 IXGBE_READ_REG(hw, IXGBE_MLFC);
389 IXGBE_READ_REG(hw, IXGBE_MRFC);
390 IXGBE_READ_REG(hw, IXGBE_RLEC);
391 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
9a799d71 392 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
667c7565
ET		 393 if (hw->mac.type >= ixgbe_mac_82599EB) {
394 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
395 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
396 } else {
397 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
398 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
399 }
9a799d71
AK		 400
401 for (i = 0; i < 8; i++) {
402 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
9a799d71 403 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
667c7565
ET		 404 if (hw->mac.type >= ixgbe_mac_82599EB) {
405 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
406 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
407 } else {
408 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
409 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
410 }
9a799d71 411 }
667c7565
ET		 412 if (hw->mac.type >= ixgbe_mac_82599EB)
413 for (i = 0; i < 8; i++)
414 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
9a799d71
AK		 415 IXGBE_READ_REG(hw, IXGBE_PRC64);
416 IXGBE_READ_REG(hw, IXGBE_PRC127);
417 IXGBE_READ_REG(hw, IXGBE_PRC255);
418 IXGBE_READ_REG(hw, IXGBE_PRC511);
419 IXGBE_READ_REG(hw, IXGBE_PRC1023);
420 IXGBE_READ_REG(hw, IXGBE_PRC1522);
421 IXGBE_READ_REG(hw, IXGBE_GPRC);
422 IXGBE_READ_REG(hw, IXGBE_BPRC);
423 IXGBE_READ_REG(hw, IXGBE_MPRC);
424 IXGBE_READ_REG(hw, IXGBE_GPTC);
425 IXGBE_READ_REG(hw, IXGBE_GORCL);
426 IXGBE_READ_REG(hw, IXGBE_GORCH);
427 IXGBE_READ_REG(hw, IXGBE_GOTCL);
428 IXGBE_READ_REG(hw, IXGBE_GOTCH);
f3116f62
ET		 429 if (hw->mac.type == ixgbe_mac_82598EB)
430 for (i = 0; i < 8; i++)
431 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
9a799d71
AK		 432 IXGBE_READ_REG(hw, IXGBE_RUC);
433 IXGBE_READ_REG(hw, IXGBE_RFC);
434 IXGBE_READ_REG(hw, IXGBE_ROC);
435 IXGBE_READ_REG(hw, IXGBE_RJC);
436 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
437 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
438 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
439 IXGBE_READ_REG(hw, IXGBE_TORL);
440 IXGBE_READ_REG(hw, IXGBE_TORH);
441 IXGBE_READ_REG(hw, IXGBE_TPR);
442 IXGBE_READ_REG(hw, IXGBE_TPT);
443 IXGBE_READ_REG(hw, IXGBE_PTC64);
444 IXGBE_READ_REG(hw, IXGBE_PTC127);
445 IXGBE_READ_REG(hw, IXGBE_PTC255);
446 IXGBE_READ_REG(hw, IXGBE_PTC511);
447 IXGBE_READ_REG(hw, IXGBE_PTC1023);
448 IXGBE_READ_REG(hw, IXGBE_PTC1522);
449 IXGBE_READ_REG(hw, IXGBE_MPTC);
450 IXGBE_READ_REG(hw, IXGBE_BPTC);
451 for (i = 0; i < 16; i++) {
452 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
9a799d71 453 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
667c7565
ET		 454 if (hw->mac.type >= ixgbe_mac_82599EB) {
455 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
456 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
457 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
458 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
459 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
460 } else {
461 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
462 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
463 }
9a799d71
AK		 464 }
465
a3aeea0e
ET		 466 if (hw->mac.type == ixgbe_mac_X540) {
467 if (hw->phy.id == 0)
468 hw->phy.ops.identify(hw);
c1085b10
ET		 469 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
470 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
471 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
472 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
a3aeea0e
ET		 473 }
474
9a799d71
AK		 475 return 0;
476}
477
478/**
289700db 479 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
c44ade9e 480 * @hw: pointer to hardware structure
289700db
DS		 481 * @pba_num: stores the part number string from the EEPROM
482 * @pba_num_size: part number string buffer length
c44ade9e 483 *
289700db 484 * Reads the part number string from the EEPROM.
c44ade9e 485 **/
289700db 486s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
e7cf745b 487 u32 pba_num_size)
c44ade9e
JB		 488{
489 s32 ret_val;
490 u16 data;
289700db
DS		 491 u16 pba_ptr;
492 u16 offset;
493 u16 length;
494
495 if (pba_num == NULL) {
496 hw_dbg(hw, "PBA string buffer was null\n");
497 return IXGBE_ERR_INVALID_ARGUMENT;
498 }
c44ade9e
JB		 499
500 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
501 if (ret_val) {
502 hw_dbg(hw, "NVM Read Error\n");
503 return ret_val;
504 }
c44ade9e 505
289700db 506 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
c44ade9e
JB		 507 if (ret_val) {
508 hw_dbg(hw, "NVM Read Error\n");
509 return ret_val;
510 }
289700db
DS		 511
512 /*
513 * if data is not ptr guard the PBA must be in legacy format which
514 * means pba_ptr is actually our second data word for the PBA number
515 * and we can decode it into an ascii string
516 */
517 if (data != IXGBE_PBANUM_PTR_GUARD) {
518 hw_dbg(hw, "NVM PBA number is not stored as string\n");
519
520 /* we will need 11 characters to store the PBA */
521 if (pba_num_size < 11) {
522 hw_dbg(hw, "PBA string buffer too small\n");
523 return IXGBE_ERR_NO_SPACE;
524 }
525
526 /* extract hex string from data and pba_ptr */
527 pba_num[0] = (data >> 12) & 0xF;
528 pba_num[1] = (data >> 8) & 0xF;
529 pba_num[2] = (data >> 4) & 0xF;
530 pba_num[3] = data & 0xF;
531 pba_num[4] = (pba_ptr >> 12) & 0xF;
532 pba_num[5] = (pba_ptr >> 8) & 0xF;
533 pba_num[6] = '-';
534 pba_num[7] = 0;
535 pba_num[8] = (pba_ptr >> 4) & 0xF;
536 pba_num[9] = pba_ptr & 0xF;
537
538 /* put a null character on the end of our string */
539 pba_num[10] = '\0';
540
541 /* switch all the data but the '-' to hex char */
542 for (offset = 0; offset < 10; offset++) {
543 if (pba_num[offset] < 0xA)
544 pba_num[offset] += '0';
545 else if (pba_num[offset] < 0x10)
546 pba_num[offset] += 'A' - 0xA;
547 }
548
549 return 0;
550 }
551
552 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
553 if (ret_val) {
554 hw_dbg(hw, "NVM Read Error\n");
555 return ret_val;
556 }
557
558 if (length == 0xFFFF || length == 0) {
559 hw_dbg(hw, "NVM PBA number section invalid length\n");
560 return IXGBE_ERR_PBA_SECTION;
561 }
562
563 /* check if pba_num buffer is big enough */
564 if (pba_num_size < (((u32)length * 2) - 1)) {
565 hw_dbg(hw, "PBA string buffer too small\n");
566 return IXGBE_ERR_NO_SPACE;
567 }
568
569 /* trim pba length from start of string */
570 pba_ptr++;
571 length--;
572
573 for (offset = 0; offset < length; offset++) {
574 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
575 if (ret_val) {
576 hw_dbg(hw, "NVM Read Error\n");
577 return ret_val;
578 }
579 pba_num[offset * 2] = (u8)(data >> 8);
580 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
581 }
582 pba_num[offset * 2] = '\0';
c44ade9e
JB		 583
584 return 0;
585}
586
587/**
588 * ixgbe_get_mac_addr_generic - Generic get MAC address
9a799d71
AK		 589 * @hw: pointer to hardware structure
590 * @mac_addr: Adapter MAC address
591 *
592 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
593 * A reset of the adapter must be performed prior to calling this function
594 * in order for the MAC address to have been loaded from the EEPROM into RAR0
595 **/
c44ade9e 596s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
9a799d71
AK		 597{
598 u32 rar_high;
599 u32 rar_low;
600 u16 i;
601
602 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
603 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
604
605 for (i = 0; i < 4; i++)
606 mac_addr[i] = (u8)(rar_low >> (i*8));
607
608 for (i = 0; i < 2; i++)
609 mac_addr[i+4] = (u8)(rar_high >> (i*8));
610
611 return 0;
612}
613
ef1889d5
JK		 614enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
615{
616 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
617 case IXGBE_PCI_LINK_WIDTH_1:
618 return ixgbe_bus_width_pcie_x1;
619 case IXGBE_PCI_LINK_WIDTH_2:
620 return ixgbe_bus_width_pcie_x2;
621 case IXGBE_PCI_LINK_WIDTH_4:
622 return ixgbe_bus_width_pcie_x4;
623 case IXGBE_PCI_LINK_WIDTH_8:
624 return ixgbe_bus_width_pcie_x8;
625 default:
626 return ixgbe_bus_width_unknown;
627 }
628}
629
630enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
631{
632 switch (link_status & IXGBE_PCI_LINK_SPEED) {
633 case IXGBE_PCI_LINK_SPEED_2500:
634 return ixgbe_bus_speed_2500;
635 case IXGBE_PCI_LINK_SPEED_5000:
636 return ixgbe_bus_speed_5000;
637 case IXGBE_PCI_LINK_SPEED_8000:
638 return ixgbe_bus_speed_8000;
639 default:
640 return ixgbe_bus_speed_unknown;
641 }
642}
643
11afc1b1
PW		 644/**
645 * ixgbe_get_bus_info_generic - Generic set PCI bus info
646 * @hw: pointer to hardware structure
647 *
648 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
649 **/
650s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
651{
11afc1b1
PW		 652 u16 link_status;
653
654 hw->bus.type = ixgbe_bus_type_pci_express;
655
656 /* Get the negotiated link width and speed from PCI config space */
0d7c6e00 657 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
11afc1b1 658
ef1889d5
JK		 659 hw->bus.width = ixgbe_convert_bus_width(link_status);
660 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
11afc1b1 661
0d7c6e00 662 hw->mac.ops.set_lan_id(hw);
11afc1b1
PW		 663
664 return 0;
665}
666
667/**
668 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
669 * @hw: pointer to the HW structure
670 *
671 * Determines the LAN function id by reading memory-mapped registers
672 * and swaps the port value if requested.
673 **/
674void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
675{
676 struct ixgbe_bus_info *bus = &hw->bus;
677 u32 reg;
678
679 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
680 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
681 bus->lan_id = bus->func;
682
683 /* check for a port swap */
684 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
685 if (reg & IXGBE_FACTPS_LFS)
686 bus->func ^= 0x1;
687}
688
9a799d71 689/**
c44ade9e 690 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
9a799d71
AK		 691 * @hw: pointer to hardware structure
692 *
693 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
694 * disables transmit and receive units. The adapter_stopped flag is used by
695 * the shared code and drivers to determine if the adapter is in a stopped
696 * state and should not touch the hardware.
697 **/
c44ade9e 698s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
9a799d71 699{
9a799d71
AK		 700 u32 reg_val;
701 u16 i;
702
703 /*
704 * Set the adapter_stopped flag so other driver functions stop touching
705 * the hardware
706 */
707 hw->adapter_stopped = true;
708
709 /* Disable the receive unit */
1f9ac57c 710 hw->mac.ops.disable_rx(hw);
9a799d71 711
ff9d1a5a 712 /* Clear interrupt mask to stop interrupts from being generated */
9a799d71
AK		 713 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
714
ff9d1a5a 715 /* Clear any pending interrupts, flush previous writes */
9a799d71
AK		 716 IXGBE_READ_REG(hw, IXGBE_EICR);
717
718 /* Disable the transmit unit. Each queue must be disabled. */
ff9d1a5a
ET		 719 for (i = 0; i < hw->mac.max_tx_queues; i++)
720 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
721
722 /* Disable the receive unit by stopping each queue */
723 for (i = 0; i < hw->mac.max_rx_queues; i++) {
724 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
725 reg_val &= ~IXGBE_RXDCTL_ENABLE;
726 reg_val |= IXGBE_RXDCTL_SWFLSH;
727 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
9a799d71
AK		 728 }
729
ff9d1a5a
ET		 730 /* flush all queues disables */
731 IXGBE_WRITE_FLUSH(hw);
732 usleep_range(1000, 2000);
733
c44ade9e
JB		 734 /*
735 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
736 * access and verify no pending requests
737 */
ff9d1a5a 738 return ixgbe_disable_pcie_master(hw);
9a799d71
AK		 739}
740
741/**
c44ade9e 742 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
9a799d71
AK		 743 * @hw: pointer to hardware structure
744 * @index: led number to turn on
745 **/
c44ade9e 746s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 747{
748 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
749
750 /* To turn on the LED, set mode to ON. */
751 led_reg &= ~IXGBE_LED_MODE_MASK(index);
752 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
753 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 754 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 755
756 return 0;
757}
758
759/**
c44ade9e 760 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
9a799d71
AK		 761 * @hw: pointer to hardware structure
762 * @index: led number to turn off
763 **/
c44ade9e 764s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
9a799d71
AK		 765{
766 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
767
768 /* To turn off the LED, set mode to OFF. */
769 led_reg &= ~IXGBE_LED_MODE_MASK(index);
770 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
771 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3957d63d 772 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 773
774 return 0;
775}
776
9a799d71 777/**
c44ade9e 778 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
9a799d71
AK		 779 * @hw: pointer to hardware structure
780 *
781 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
782 * ixgbe_hw struct in order to set up EEPROM access.
783 **/
c44ade9e 784s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
9a799d71
AK		 785{
786 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
787 u32 eec;
788 u16 eeprom_size;
789
790 if (eeprom->type == ixgbe_eeprom_uninitialized) {
791 eeprom->type = ixgbe_eeprom_none;
c44ade9e
JB		 792 /* Set default semaphore delay to 10ms which is a well
793 * tested value */
794 eeprom->semaphore_delay = 10;
68c7005d
ET		 795 /* Clear EEPROM page size, it will be initialized as needed */
796 eeprom->word_page_size = 0;
9a799d71
AK		 797
798 /*
799 * Check for EEPROM present first.
800 * If not present leave as none
801 */
802 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
803 if (eec & IXGBE_EEC_PRES) {
804 eeprom->type = ixgbe_eeprom_spi;
805
806 /*
807 * SPI EEPROM is assumed here. This code would need to
808 * change if a future EEPROM is not SPI.
809 */
810 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
811 IXGBE_EEC_SIZE_SHIFT);
812 eeprom->word_size = 1 << (eeprom_size +
813 IXGBE_EEPROM_WORD_SIZE_SHIFT);
814 }
815
816 if (eec & IXGBE_EEC_ADDR_SIZE)
817 eeprom->address_bits = 16;
818 else
819 eeprom->address_bits = 8;
6ec1b71f
JK		 820 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
821 eeprom->type, eeprom->word_size, eeprom->address_bits);
9a799d71
AK		 822 }
823
824 return 0;
825}
826
11afc1b1 827/**
68c7005d 828 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
11afc1b1 829 * @hw: pointer to hardware structure
68c7005d
ET		 830 * @offset: offset within the EEPROM to write
831 * @words: number of words
832 * @data: 16 bit word(s) to write to EEPROM
11afc1b1 833 *
68c7005d 834 * Reads 16 bit word(s) from EEPROM through bit-bang method
11afc1b1 835 **/
68c7005d
ET		 836s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
837 u16 words, u16 *data)
11afc1b1 838{
e90dd264 839 s32 status;
68c7005d 840 u16 i, count;
11afc1b1
PW		 841
842 hw->eeprom.ops.init_params(hw);
843
e90dd264
MR		 844 if (words == 0)
845 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 846
e90dd264
MR		 847 if (offset + words > hw->eeprom.word_size)
848 return IXGBE_ERR_EEPROM;
11afc1b1 849
68c7005d
ET		 850 /*
851 * The EEPROM page size cannot be queried from the chip. We do lazy
852 * initialization. It is worth to do that when we write large buffer.
853 */
854 if ((hw->eeprom.word_page_size == 0) &&
855 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
856 ixgbe_detect_eeprom_page_size_generic(hw, offset);
857
858 /*
859 * We cannot hold synchronization semaphores for too long
860 * to avoid other entity starvation. However it is more efficient
861 * to read in bursts than synchronizing access for each word.
862 */
863 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
864 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
865 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
866 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
867 count, &data[i]);
868
869 if (status != 0)
870 break;
871 }
872
68c7005d
ET		 873 return status;
874}
875
876/**
877 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
878 * @hw: pointer to hardware structure
879 * @offset: offset within the EEPROM to be written to
880 * @words: number of word(s)
881 * @data: 16 bit word(s) to be written to the EEPROM
882 *
883 * If ixgbe_eeprom_update_checksum is not called after this function, the
884 * EEPROM will most likely contain an invalid checksum.
885 **/
886static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
887 u16 words, u16 *data)
888{
889 s32 status;
890 u16 word;
891 u16 page_size;
892 u16 i;
893 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
894
11afc1b1
PW		 895 /* Prepare the EEPROM for writing */
896 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 897 if (status)
898 return status;
11afc1b1 899
e90dd264
MR		 900 if (ixgbe_ready_eeprom(hw) != 0) {
901 ixgbe_release_eeprom(hw);
902 return IXGBE_ERR_EEPROM;
11afc1b1
PW		 903 }
904
e90dd264
MR		 905 for (i = 0; i < words; i++) {
906 ixgbe_standby_eeprom(hw);
907
908 /* Send the WRITE ENABLE command (8 bit opcode) */
909 ixgbe_shift_out_eeprom_bits(hw,
910 IXGBE_EEPROM_WREN_OPCODE_SPI,
911 IXGBE_EEPROM_OPCODE_BITS);
11afc1b1 912
e90dd264 913 ixgbe_standby_eeprom(hw);
11afc1b1 914
e90dd264
MR		 915 /* Some SPI eeproms use the 8th address bit embedded
916 * in the opcode
917 */
918 if ((hw->eeprom.address_bits == 8) &&
919 ((offset + i) >= 128))
920 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
11afc1b1 921
e90dd264
MR		 922 /* Send the Write command (8-bit opcode + addr) */
923 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
924 IXGBE_EEPROM_OPCODE_BITS);
925 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
926 hw->eeprom.address_bits);
927
928 page_size = hw->eeprom.word_page_size;
929
930 /* Send the data in burst via SPI */
931 do {
932 word = data[i];
933 word = (word >> 8) | (word << 8);
934 ixgbe_shift_out_eeprom_bits(hw, word, 16);
935
936 if (page_size == 0)
937 break;
938
939 /* do not wrap around page */
940 if (((offset + i) & (page_size - 1)) ==
941 (page_size - 1))
942 break;
943 } while (++i < words);
944
945 ixgbe_standby_eeprom(hw);
946 usleep_range(10000, 20000);
68c7005d 947 }
e90dd264
MR		 948 /* Done with writing - release the EEPROM */
949 ixgbe_release_eeprom(hw);
11afc1b1 950
e90dd264 951 return 0;
68c7005d
ET		 952}
953
954/**
955 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
956 * @hw: pointer to hardware structure
957 * @offset: offset within the EEPROM to be written to
958 * @data: 16 bit word to be written to the EEPROM
959 *
960 * If ixgbe_eeprom_update_checksum is not called after this function, the
961 * EEPROM will most likely contain an invalid checksum.
962 **/
963s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
964{
68c7005d 965 hw->eeprom.ops.init_params(hw);
11afc1b1 966
e90dd264
MR		 967 if (offset >= hw->eeprom.word_size)
968 return IXGBE_ERR_EEPROM;
11afc1b1 969
e90dd264 970 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
11afc1b1
PW		 971}
972
9a799d71 973/**
68c7005d 974 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
c44ade9e
JB		 975 * @hw: pointer to hardware structure
976 * @offset: offset within the EEPROM to be read
68c7005d
ET		 977 * @words: number of word(s)
978 * @data: read 16 bit words(s) from EEPROM
c44ade9e 979 *
68c7005d 980 * Reads 16 bit word(s) from EEPROM through bit-bang method
c44ade9e 981 **/
68c7005d
ET		 982s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
983 u16 words, u16 *data)
c44ade9e 984{
e90dd264 985 s32 status;
68c7005d 986 u16 i, count;
c44ade9e
JB		 987
988 hw->eeprom.ops.init_params(hw);
989
e90dd264
MR		 990 if (words == 0)
991 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 992
e90dd264
MR		 993 if (offset + words > hw->eeprom.word_size)
994 return IXGBE_ERR_EEPROM;
c44ade9e 995
68c7005d
ET		 996 /*
997 * We cannot hold synchronization semaphores for too long
998 * to avoid other entity starvation. However it is more efficient
999 * to read in bursts than synchronizing access for each word.
1000 */
1001 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1002 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1003 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1004
1005 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1006 count, &data[i]);
1007
e90dd264
MR		 1008 if (status)
1009 return status;
68c7005d
ET		 1010 }
1011
e90dd264 1012 return 0;
68c7005d
ET		 1013}
1014
1015/**
1016 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1017 * @hw: pointer to hardware structure
1018 * @offset: offset within the EEPROM to be read
1019 * @words: number of word(s)
1020 * @data: read 16 bit word(s) from EEPROM
1021 *
1022 * Reads 16 bit word(s) from EEPROM through bit-bang method
1023 **/
1024static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1025 u16 words, u16 *data)
1026{
1027 s32 status;
1028 u16 word_in;
1029 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1030 u16 i;
1031
c44ade9e
JB		 1032 /* Prepare the EEPROM for reading */
1033 status = ixgbe_acquire_eeprom(hw);
e90dd264
MR		 1034 if (status)
1035 return status;
c44ade9e 1036
e90dd264
MR		 1037 if (ixgbe_ready_eeprom(hw) != 0) {
1038 ixgbe_release_eeprom(hw);
1039 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1040 }
1041
e90dd264
MR		 1042 for (i = 0; i < words; i++) {
1043 ixgbe_standby_eeprom(hw);
1044 /* Some SPI eeproms use the 8th address bit embedded
1045 * in the opcode
1046 */
1047 if ((hw->eeprom.address_bits == 8) &&
1048 ((offset + i) >= 128))
1049 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
c44ade9e 1050
e90dd264
MR		 1051 /* Send the READ command (opcode + addr) */
1052 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1053 IXGBE_EEPROM_OPCODE_BITS);
1054 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1055 hw->eeprom.address_bits);
1056
1057 /* Read the data. */
1058 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1059 data[i] = (word_in >> 8) | (word_in << 8);
68c7005d 1060 }
c44ade9e 1061
e90dd264
MR		 1062 /* End this read operation */
1063 ixgbe_release_eeprom(hw);
1064
1065 return 0;
68c7005d 1066}
c44ade9e 1067
68c7005d
ET		 1068/**
1069 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1070 * @hw: pointer to hardware structure
1071 * @offset: offset within the EEPROM to be read
1072 * @data: read 16 bit value from EEPROM
1073 *
1074 * Reads 16 bit value from EEPROM through bit-bang method
1075 **/
1076s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1077 u16 *data)
1078{
68c7005d
ET		 1079 hw->eeprom.ops.init_params(hw);
1080
e90dd264
MR		 1081 if (offset >= hw->eeprom.word_size)
1082 return IXGBE_ERR_EEPROM;
68c7005d 1083
e90dd264 1084 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
c44ade9e
JB		 1085}
1086
1087/**
68c7005d 1088 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
9a799d71 1089 * @hw: pointer to hardware structure
68c7005d
ET		 1090 * @offset: offset of word in the EEPROM to read
1091 * @words: number of word(s)
1092 * @data: 16 bit word(s) from the EEPROM
9a799d71 1093 *
68c7005d 1094 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
9a799d71 1095 **/
68c7005d
ET		 1096s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1097 u16 words, u16 *data)
9a799d71
AK		 1098{
1099 u32 eerd;
e90dd264 1100 s32 status;
68c7005d 1101 u32 i;
9a799d71 1102
c44ade9e
JB		 1103 hw->eeprom.ops.init_params(hw);
1104
e90dd264
MR		 1105 if (words == 0)
1106 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1107
e90dd264
MR		 1108 if (offset >= hw->eeprom.word_size)
1109 return IXGBE_ERR_EEPROM;
c44ade9e 1110
68c7005d 1111 for (i = 0; i < words; i++) {
d0111575 1112 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
68c7005d 1113 IXGBE_EEPROM_RW_REG_START;
9a799d71 1114
68c7005d
ET		 1115 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1116 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
9a799d71 1117
68c7005d
ET		 1118 if (status == 0) {
1119 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1120 IXGBE_EEPROM_RW_REG_DATA);
1121 } else {
1122 hw_dbg(hw, "Eeprom read timed out\n");
e90dd264 1123 return status;
68c7005d
ET		 1124 }
1125 }
e90dd264
MR		 1126
1127 return 0;
68c7005d 1128}
9a799d71 1129
68c7005d
ET		 1130/**
1131 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1132 * @hw: pointer to hardware structure
1133 * @offset: offset within the EEPROM to be used as a scratch pad
1134 *
1135 * Discover EEPROM page size by writing marching data at given offset.
1136 * This function is called only when we are writing a new large buffer
1137 * at given offset so the data would be overwritten anyway.
1138 **/
1139static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1140 u16 offset)
1141{
1142 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
e90dd264 1143 s32 status;
68c7005d
ET		 1144 u16 i;
1145
1146 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1147 data[i] = i;
1148
1149 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1150 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1151 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1152 hw->eeprom.word_page_size = 0;
e90dd264
MR		 1153 if (status)
1154 return status;
68c7005d
ET		 1155
1156 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
e90dd264
MR		 1157 if (status)
1158 return status;
68c7005d
ET		 1159
1160 /*
1161 * When writing in burst more than the actual page size
1162 * EEPROM address wraps around current page.
1163 */
1164 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1165
c5ffe7e1 1166 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
68c7005d 1167 hw->eeprom.word_page_size);
e90dd264 1168 return 0;
9a799d71
AK		 1169}
1170
eb9c3e3e 1171/**
68c7005d
ET		 1172 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1173 * @hw: pointer to hardware structure
1174 * @offset: offset of word in the EEPROM to read
1175 * @data: word read from the EEPROM
1176 *
1177 * Reads a 16 bit word from the EEPROM using the EERD register.
1178 **/
1179s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1180{
1181 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1182}
1183
1184/**
1185 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
eb9c3e3e
ET		 1186 * @hw: pointer to hardware structure
1187 * @offset: offset of word in the EEPROM to write
68c7005d
ET		 1188 * @words: number of words
1189 * @data: word(s) write to the EEPROM
eb9c3e3e 1190 *
68c7005d 1191 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
eb9c3e3e 1192 **/
68c7005d
ET		 1193s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1194 u16 words, u16 *data)
eb9c3e3e
ET		 1195{
1196 u32 eewr;
e90dd264 1197 s32 status;
68c7005d 1198 u16 i;
eb9c3e3e
ET		 1199
1200 hw->eeprom.ops.init_params(hw);
1201
e90dd264
MR		 1202 if (words == 0)
1203 return IXGBE_ERR_INVALID_ARGUMENT;
68c7005d 1204
e90dd264
MR		 1205 if (offset >= hw->eeprom.word_size)
1206 return IXGBE_ERR_EEPROM;
eb9c3e3e 1207
68c7005d
ET		 1208 for (i = 0; i < words; i++) {
1209 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1210 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1211 IXGBE_EEPROM_RW_REG_START;
eb9c3e3e 1212
68c7005d 1213 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1214 if (status) {
68c7005d 1215 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1216 return status;
68c7005d 1217 }
eb9c3e3e 1218
68c7005d 1219 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
eb9c3e3e 1220
68c7005d 1221 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
e90dd264 1222 if (status) {
68c7005d 1223 hw_dbg(hw, "Eeprom write EEWR timed out\n");
e90dd264 1224 return status;
68c7005d 1225 }
eb9c3e3e
ET		 1226 }
1227
e90dd264 1228 return 0;
eb9c3e3e
ET		 1229}
1230
68c7005d
ET		 1231/**
1232 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1233 * @hw: pointer to hardware structure
1234 * @offset: offset of word in the EEPROM to write
1235 * @data: word write to the EEPROM
1236 *
1237 * Write a 16 bit word to the EEPROM using the EEWR register.
1238 **/
1239s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1240{
1241 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1242}
1243
9a799d71 1244/**
21ce849b 1245 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
9a799d71 1246 * @hw: pointer to hardware structure
21ce849b 1247 * @ee_reg: EEPROM flag for polling
9a799d71 1248 *
21ce849b
MC		 1249 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1250 * read or write is done respectively.
9a799d71 1251 **/
eb9c3e3e 1252static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
9a799d71
AK		 1253{
1254 u32 i;
1255 u32 reg;
9a799d71 1256
21ce849b
MC		 1257 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1258 if (ee_reg == IXGBE_NVM_POLL_READ)
1259 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1260 else
1261 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1262
1263 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
e90dd264 1264 return 0;
9a799d71
AK		 1265 }
1266 udelay(5);
1267 }
e90dd264 1268 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1269}
1270
c44ade9e
JB		 1271/**
1272 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1273 * @hw: pointer to hardware structure
1274 *
1275 * Prepares EEPROM for access using bit-bang method. This function should
1276 * be called before issuing a command to the EEPROM.
1277 **/
1278static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1279{
dbf893ee 1280 u32 eec;
c44ade9e
JB		 1281 u32 i;
1282
5e655105 1283 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
e90dd264 1284 return IXGBE_ERR_SWFW_SYNC;
c44ade9e 1285
e90dd264 1286 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
c44ade9e 1287
e90dd264
MR		 1288 /* Request EEPROM Access */
1289 eec |= IXGBE_EEC_REQ;
1290 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
c44ade9e 1291
e90dd264
MR		 1292 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1293 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1294 if (eec & IXGBE_EEC_GNT)
1295 break;
1296 udelay(5);
1297 }
c44ade9e 1298
e90dd264
MR		 1299 /* Release if grant not acquired */
1300 if (!(eec & IXGBE_EEC_GNT)) {
1301 eec &= ~IXGBE_EEC_REQ;
1302 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1303 hw_dbg(hw, "Could not acquire EEPROM grant\n");
c44ade9e 1304
e90dd264
MR		 1305 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1306 return IXGBE_ERR_EEPROM;
c44ade9e 1307 }
e90dd264
MR		 1308
1309 /* Setup EEPROM for Read/Write */
1310 /* Clear CS and SK */
1311 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1312 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1313 IXGBE_WRITE_FLUSH(hw);
1314 udelay(1);
1315 return 0;
c44ade9e
JB		 1316}
1317
9a799d71
AK		 1318/**
1319 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1320 * @hw: pointer to hardware structure
1321 *
1322 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1323 **/
1324static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1325{
dbf893ee 1326 u32 timeout = 2000;
9a799d71
AK		 1327 u32 i;
1328 u32 swsm;
1329
9a799d71
AK		 1330 /* Get SMBI software semaphore between device drivers first */
1331 for (i = 0; i < timeout; i++) {
1332 /*
1333 * If the SMBI bit is 0 when we read it, then the bit will be
1334 * set and we have the semaphore
1335 */
1336 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
e90dd264 1337 if (!(swsm & IXGBE_SWSM_SMBI))
9a799d71 1338 break;
d819fc52 1339 usleep_range(50, 100);
9a799d71
AK		 1340 }
1341
51275d37 1342 if (i == timeout) {
6ec1b71f 1343 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
e90dd264 1344 /* this release is particularly important because our attempts
51275d37
ET		 1345 * above to get the semaphore may have succeeded, and if there
1346 * was a timeout, we should unconditionally clear the semaphore
1347 * bits to free the driver to make progress
1348 */
1349 ixgbe_release_eeprom_semaphore(hw);
1350
d819fc52 1351 usleep_range(50, 100);
e90dd264 1352 /* one last try
51275d37
ET		 1353 * If the SMBI bit is 0 when we read it, then the bit will be
1354 * set and we have the semaphore
1355 */
1356 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
e90dd264
MR		 1357 if (swsm & IXGBE_SWSM_SMBI) {
1358 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1359 return IXGBE_ERR_EEPROM;
1360 }
51275d37
ET		 1361 }
1362
9a799d71 1363 /* Now get the semaphore between SW/FW through the SWESMBI bit */
e90dd264
MR		 1364 for (i = 0; i < timeout; i++) {
1365 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
9a799d71 1366
e90dd264
MR		 1367 /* Set the SW EEPROM semaphore bit to request access */
1368 swsm |= IXGBE_SWSM_SWESMBI;
1369 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
9a799d71 1370
e90dd264
MR		 1371 /* If we set the bit successfully then we got the
1372 * semaphore.
1373 */
1374 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1375 if (swsm & IXGBE_SWSM_SWESMBI)
1376 break;
9a799d71 1377
e90dd264
MR		 1378 usleep_range(50, 100);
1379 }
9a799d71 1380
e90dd264
MR		 1381 /* Release semaphores and return error if SW EEPROM semaphore
1382 * was not granted because we don't have access to the EEPROM
1383 */
1384 if (i >= timeout) {
1385 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1386 ixgbe_release_eeprom_semaphore(hw);
1387 return IXGBE_ERR_EEPROM;
9a799d71
AK		 1388 }
1389
e90dd264 1390 return 0;
9a799d71
AK		 1391}
1392
1393/**
1394 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1395 * @hw: pointer to hardware structure
1396 *
1397 * This function clears hardware semaphore bits.
1398 **/
1399static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1400{
1401 u32 swsm;
1402
1403 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1404
1405 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1406 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1407 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
3957d63d 1408 IXGBE_WRITE_FLUSH(hw);
9a799d71
AK		 1409}
1410
c44ade9e
JB		 1411/**
1412 * ixgbe_ready_eeprom - Polls for EEPROM ready
1413 * @hw: pointer to hardware structure
1414 **/
1415static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1416{
c44ade9e
JB		 1417 u16 i;
1418 u8 spi_stat_reg;
1419
1420 /*
1421 * Read "Status Register" repeatedly until the LSB is cleared. The
1422 * EEPROM will signal that the command has been completed by clearing
1423 * bit 0 of the internal status register. If it's not cleared within
1424 * 5 milliseconds, then error out.
1425 */
1426 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1427 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
e7cf745b 1428 IXGBE_EEPROM_OPCODE_BITS);
c44ade9e
JB		 1429 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1430 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1431 break;
1432
1433 udelay(5);
1434 ixgbe_standby_eeprom(hw);
6403eab1 1435 }
c44ade9e
JB		 1436
1437 /*
1438 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1439 * devices (and only 0-5mSec on 5V devices)
1440 */
1441 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1442 hw_dbg(hw, "SPI EEPROM Status error\n");
e90dd264 1443 return IXGBE_ERR_EEPROM;
c44ade9e
JB		 1444 }
1445
e90dd264 1446 return 0;
c44ade9e
JB		 1447}
1448
1449/**
1450 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1451 * @hw: pointer to hardware structure
1452 **/
1453static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1454{
1455 u32 eec;
1456
1457 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1458
1459 /* Toggle CS to flush commands */
1460 eec |= IXGBE_EEC_CS;
1461 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1462 IXGBE_WRITE_FLUSH(hw);
1463 udelay(1);
1464 eec &= ~IXGBE_EEC_CS;
1465 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1466 IXGBE_WRITE_FLUSH(hw);
1467 udelay(1);
1468}
1469
1470/**
1471 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1472 * @hw: pointer to hardware structure
1473 * @data: data to send to the EEPROM
1474 * @count: number of bits to shift out
1475 **/
1476static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
e7cf745b 1477 u16 count)
c44ade9e
JB		 1478{
1479 u32 eec;
1480 u32 mask;
1481 u32 i;
1482
1483 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1484
1485 /*
1486 * Mask is used to shift "count" bits of "data" out to the EEPROM
1487 * one bit at a time. Determine the starting bit based on count
1488 */
1489 mask = 0x01 << (count - 1);
1490
1491 for (i = 0; i < count; i++) {
1492 /*
1493 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1494 * "1", and then raising and then lowering the clock (the SK
1495 * bit controls the clock input to the EEPROM). A "0" is
1496 * shifted out to the EEPROM by setting "DI" to "0" and then
1497 * raising and then lowering the clock.
1498 */
1499 if (data & mask)
1500 eec |= IXGBE_EEC_DI;
1501 else
1502 eec &= ~IXGBE_EEC_DI;
1503
1504 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1505 IXGBE_WRITE_FLUSH(hw);
1506
1507 udelay(1);
1508
1509 ixgbe_raise_eeprom_clk(hw, &eec);
1510 ixgbe_lower_eeprom_clk(hw, &eec);
1511
1512 /*
1513 * Shift mask to signify next bit of data to shift in to the
1514 * EEPROM
1515 */
1516 mask = mask >> 1;
6403eab1 1517 }
c44ade9e
JB		 1518
1519 /* We leave the "DI" bit set to "0" when we leave this routine. */
1520 eec &= ~IXGBE_EEC_DI;
1521 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1522 IXGBE_WRITE_FLUSH(hw);
1523}
1524
1525/**
1526 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1527 * @hw: pointer to hardware structure
1528 **/
1529static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1530{
1531 u32 eec;
1532 u32 i;
1533 u16 data = 0;
1534
1535 /*
1536 * In order to read a register from the EEPROM, we need to shift
1537 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1538 * the clock input to the EEPROM (setting the SK bit), and then reading
1539 * the value of the "DO" bit. During this "shifting in" process the
1540 * "DI" bit should always be clear.
1541 */
1542 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1543
1544 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1545
1546 for (i = 0; i < count; i++) {
1547 data = data << 1;
1548 ixgbe_raise_eeprom_clk(hw, &eec);
1549
1550 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1551
1552 eec &= ~(IXGBE_EEC_DI);
1553 if (eec & IXGBE_EEC_DO)
1554 data |= 1;
1555
1556 ixgbe_lower_eeprom_clk(hw, &eec);
1557 }
1558
1559 return data;
1560}
1561
1562/**
1563 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1564 * @hw: pointer to hardware structure
1565 * @eec: EEC register's current value
1566 **/
1567static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1568{
1569 /*
1570 * Raise the clock input to the EEPROM
1571 * (setting the SK bit), then delay
1572 */
1573 *eec = *eec | IXGBE_EEC_SK;
1574 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1575 IXGBE_WRITE_FLUSH(hw);
1576 udelay(1);
1577}
1578
1579/**
1580 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1581 * @hw: pointer to hardware structure
1582 * @eecd: EECD's current value
1583 **/
1584static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1585{
1586 /*
1587 * Lower the clock input to the EEPROM (clearing the SK bit), then
1588 * delay
1589 */
1590 *eec = *eec & ~IXGBE_EEC_SK;
1591 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1592 IXGBE_WRITE_FLUSH(hw);
1593 udelay(1);
1594}
1595
1596/**
1597 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1598 * @hw: pointer to hardware structure
1599 **/
1600static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1601{
1602 u32 eec;
1603
1604 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1605
1606 eec |= IXGBE_EEC_CS; /* Pull CS high */
1607 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1608
1609 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1610 IXGBE_WRITE_FLUSH(hw);
1611
1612 udelay(1);
1613
1614 /* Stop requesting EEPROM access */
1615 eec &= ~IXGBE_EEC_REQ;
1616 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1617
90827996 1618 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
dbf893ee 1619
032b4325
DS		 1620 /*
1621 * Delay before attempt to obtain semaphore again to allow FW
1622 * access. semaphore_delay is in ms we need us for usleep_range
1623 */
1624 usleep_range(hw->eeprom.semaphore_delay * 1000,
1625 hw->eeprom.semaphore_delay * 2000);
c44ade9e
JB		 1626}
1627
9a799d71 1628/**
dbf893ee 1629 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
9a799d71
AK		 1630 * @hw: pointer to hardware structure
1631 **/
735c35af 1632s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1633{
1634 u16 i;
1635 u16 j;
1636 u16 checksum = 0;
1637 u16 length = 0;
1638 u16 pointer = 0;
1639 u16 word = 0;
1640
1641 /* Include 0x0-0x3F in the checksum */
1642 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
735c35af 1643 if (hw->eeprom.ops.read(hw, i, &word)) {
9a799d71
AK		 1644 hw_dbg(hw, "EEPROM read failed\n");
1645 break;
1646 }
1647 checksum += word;
1648 }
1649
1650 /* Include all data from pointers except for the fw pointer */
1651 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
735c35af
DS		 1652 if (hw->eeprom.ops.read(hw, i, &pointer)) {
1653 hw_dbg(hw, "EEPROM read failed\n");
1654 return IXGBE_ERR_EEPROM;
1655 }
1656
1657 /* If the pointer seems invalid */
1658 if (pointer == 0xFFFF || pointer == 0)
1659 continue;
1660
1661 if (hw->eeprom.ops.read(hw, pointer, &length)) {
1662 hw_dbg(hw, "EEPROM read failed\n");
1663 return IXGBE_ERR_EEPROM;
1664 }
9a799d71 1665
735c35af
DS		 1666 if (length == 0xFFFF || length == 0)
1667 continue;
9a799d71 1668
735c35af
DS		 1669 for (j = pointer + 1; j <= pointer + length; j++) {
1670 if (hw->eeprom.ops.read(hw, j, &word)) {
1671 hw_dbg(hw, "EEPROM read failed\n");
1672 return IXGBE_ERR_EEPROM;
9a799d71 1673 }
735c35af 1674 checksum += word;
9a799d71
AK		 1675 }
1676 }
1677
1678 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1679
735c35af 1680 return (s32)checksum;
9a799d71
AK		 1681}
1682
1683/**
c44ade9e 1684 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
9a799d71
AK		 1685 * @hw: pointer to hardware structure
1686 * @checksum_val: calculated checksum
1687 *
1688 * Performs checksum calculation and validates the EEPROM checksum. If the
1689 * caller does not need checksum_val, the value can be NULL.
1690 **/
c44ade9e 1691s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
e7cf745b 1692 u16 *checksum_val)
9a799d71
AK		 1693{
1694 s32 status;
1695 u16 checksum;
1696 u16 read_checksum = 0;
1697
1698 /*
1699 * Read the first word from the EEPROM. If this times out or fails, do
1700 * not continue or we could be in for a very long wait while every
1701 * EEPROM read fails
1702 */
c44ade9e 1703 status = hw->eeprom.ops.read(hw, 0, &checksum);
735c35af
DS		 1704 if (status) {
1705 hw_dbg(hw, "EEPROM read failed\n");
1706 return status;
1707 }
9a799d71 1708
735c35af
DS		 1709 status = hw->eeprom.ops.calc_checksum(hw);
1710 if (status < 0)
1711 return status;
9a799d71 1712
735c35af 1713 checksum = (u16)(status & 0xffff);
9a799d71 1714
735c35af
DS		 1715 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1716 if (status) {
9a799d71 1717 hw_dbg(hw, "EEPROM read failed\n");
735c35af 1718 return status;
9a799d71
AK		 1719 }
1720
735c35af
DS		 1721 /* Verify read checksum from EEPROM is the same as
1722 * calculated checksum
1723 */
1724 if (read_checksum != checksum)
1725 status = IXGBE_ERR_EEPROM_CHECKSUM;
1726
1727 /* If the user cares, return the calculated checksum */
1728 if (checksum_val)
1729 *checksum_val = checksum;
1730
9a799d71
AK		 1731 return status;
1732}
1733
c44ade9e
JB		 1734/**
1735 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1736 * @hw: pointer to hardware structure
1737 **/
1738s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1739{
1740 s32 status;
1741 u16 checksum;
1742
1743 /*
1744 * Read the first word from the EEPROM. If this times out or fails, do
1745 * not continue or we could be in for a very long wait while every
1746 * EEPROM read fails
1747 */
1748 status = hw->eeprom.ops.read(hw, 0, &checksum);
735c35af 1749 if (status) {
c44ade9e 1750 hw_dbg(hw, "EEPROM read failed\n");
735c35af 1751 return status;
c44ade9e
JB		 1752 }
1753
735c35af
DS		 1754 status = hw->eeprom.ops.calc_checksum(hw);
1755 if (status < 0)
1756 return status;
1757
1758 checksum = (u16)(status & 0xffff);
1759
1760 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
1761
c44ade9e
JB		 1762 return status;
1763}
1764
9a799d71 1765/**
c44ade9e 1766 * ixgbe_set_rar_generic - Set Rx address register
9a799d71 1767 * @hw: pointer to hardware structure
9a799d71 1768 * @index: Receive address register to write
c44ade9e
JB		 1769 * @addr: Address to put into receive address register
1770 * @vmdq: VMDq "set" or "pool" index
9a799d71
AK		 1771 * @enable_addr: set flag that address is active
1772 *
1773 * Puts an ethernet address into a receive address register.
1774 **/
c44ade9e 1775s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
e7cf745b 1776 u32 enable_addr)
9a799d71
AK		 1777{
1778 u32 rar_low, rar_high;
c44ade9e
JB		 1779 u32 rar_entries = hw->mac.num_rar_entries;
1780
c700f4e6
ET		 1781 /* Make sure we are using a valid rar index range */
1782 if (index >= rar_entries) {
1783 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1784 return IXGBE_ERR_INVALID_ARGUMENT;
1785 }
1786
c44ade9e
JB		 1787 /* setup VMDq pool selection before this RAR gets enabled */
1788 hw->mac.ops.set_vmdq(hw, index, vmdq);
9a799d71 1789
c700f4e6
ET		 1790 /*
1791 * HW expects these in little endian so we reverse the byte
1792 * order from network order (big endian) to little endian
1793 */
1794 rar_low = ((u32)addr[0] |
1795 ((u32)addr[1] << 8) |
1796 ((u32)addr[2] << 16) |
1797 ((u32)addr[3] << 24));
1798 /*
1799 * Some parts put the VMDq setting in the extra RAH bits,
1800 * so save everything except the lower 16 bits that hold part
1801 * of the address and the address valid bit.
1802 */
1803 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1804 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1805 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
9a799d71 1806
c700f4e6
ET		 1807 if (enable_addr != 0)
1808 rar_high |= IXGBE_RAH_AV;
9a799d71 1809
c700f4e6
ET		 1810 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1811 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
c44ade9e
JB		 1812
1813 return 0;
1814}
1815
1816/**
1817 * ixgbe_clear_rar_generic - Remove Rx address register
1818 * @hw: pointer to hardware structure
1819 * @index: Receive address register to write
1820 *
1821 * Clears an ethernet address from a receive address register.
1822 **/
1823s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1824{
1825 u32 rar_high;
1826 u32 rar_entries = hw->mac.num_rar_entries;
1827
1828 /* Make sure we are using a valid rar index range */
c700f4e6 1829 if (index >= rar_entries) {
c44ade9e 1830 hw_dbg(hw, "RAR index %d is out of range.\n", index);
c700f4e6 1831 return IXGBE_ERR_INVALID_ARGUMENT;
c44ade9e
JB		 1832 }
1833
c700f4e6
ET		 1834 /*
1835 * Some parts put the VMDq setting in the extra RAH bits,
1836 * so save everything except the lower 16 bits that hold part
1837 * of the address and the address valid bit.
1838 */
1839 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1840 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1841
1842 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1843 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1844
c44ade9e
JB		 1845 /* clear VMDq pool/queue selection for this RAR */
1846 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
9a799d71
AK		 1847
1848 return 0;
1849}
1850
c44ade9e
JB		 1851/**
1852 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
9a799d71
AK		 1853 * @hw: pointer to hardware structure
1854 *
1855 * Places the MAC address in receive address register 0 and clears the rest
c44ade9e 1856 * of the receive address registers. Clears the multicast table. Assumes
9a799d71
AK		 1857 * the receiver is in reset when the routine is called.
1858 **/
c44ade9e 1859s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
9a799d71
AK		 1860{
1861 u32 i;
2c5645cf 1862 u32 rar_entries = hw->mac.num_rar_entries;
9a799d71
AK		 1863
1864 /*
1865 * If the current mac address is valid, assume it is a software override
1866 * to the permanent address.
1867 * Otherwise, use the permanent address from the eeprom.
1868 */
f8ebc683 1869 if (!is_valid_ether_addr(hw->mac.addr)) {
9a799d71 1870 /* Get the MAC address from the RAR0 for later reference */
c44ade9e 1871 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
9a799d71 1872
ce7194d8 1873 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
9a799d71
AK		 1874 } else {
1875 /* Setup the receive address. */
1876 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
ce7194d8 1877 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
9a799d71 1878
c44ade9e 1879 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
96cc6372
AD		 1880
1881 /* clear VMDq pool/queue selection for RAR 0 */
1882 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
9a799d71 1883 }
c44ade9e 1884 hw->addr_ctrl.overflow_promisc = 0;
9a799d71
AK		 1885
1886 hw->addr_ctrl.rar_used_count = 1;
1887
1888 /* Zero out the other receive addresses. */
c44ade9e 1889 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
9a799d71
AK		 1890 for (i = 1; i < rar_entries; i++) {
1891 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1892 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1893 }
1894
1895 /* Clear the MTA */
9a799d71
AK		 1896 hw->addr_ctrl.mta_in_use = 0;
1897 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1898
1899 hw_dbg(hw, " Clearing MTA\n");
2c5645cf 1900 for (i = 0; i < hw->mac.mcft_size; i++)
9a799d71
AK		 1901 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1902
c44ade9e
JB		 1903 if (hw->mac.ops.init_uta_tables)
1904 hw->mac.ops.init_uta_tables(hw);
1905
9a799d71
AK		 1906 return 0;
1907}
1908
1909/**
1910 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1911 * @hw: pointer to hardware structure
1912 * @mc_addr: the multicast address
1913 *
1914 * Extracts the 12 bits, from a multicast address, to determine which
1915 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1916 * incoming rx multicast addresses, to determine the bit-vector to check in
1917 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
c44ade9e 1918 * by the MO field of the MCSTCTRL. The MO field is set during initialization
9a799d71
AK		 1919 * to mc_filter_type.
1920 **/
1921static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1922{
1923 u32 vector = 0;
1924
1925 switch (hw->mac.mc_filter_type) {
b4617240 1926 case 0: /* use bits [47:36] of the address */
9a799d71
AK		 1927 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1928 break;
b4617240 1929 case 1: /* use bits [46:35] of the address */
9a799d71
AK		 1930 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1931 break;
b4617240 1932 case 2: /* use bits [45:34] of the address */
9a799d71
AK		 1933 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1934 break;
b4617240 1935 case 3: /* use bits [43:32] of the address */
9a799d71
AK		 1936 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1937 break;
b4617240 1938 default: /* Invalid mc_filter_type */
9a799d71
AK		 1939 hw_dbg(hw, "MC filter type param set incorrectly\n");
1940 break;
1941 }
1942
1943 /* vector can only be 12-bits or boundary will be exceeded */
1944 vector &= 0xFFF;
1945 return vector;
1946}
1947
1948/**
1949 * ixgbe_set_mta - Set bit-vector in multicast table
1950 * @hw: pointer to hardware structure
1951 * @hash_value: Multicast address hash value
1952 *
1953 * Sets the bit-vector in the multicast table.
1954 **/
1955static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1956{
1957 u32 vector;
1958 u32 vector_bit;
1959 u32 vector_reg;
9a799d71
AK		 1960
1961 hw->addr_ctrl.mta_in_use++;
1962
1963 vector = ixgbe_mta_vector(hw, mc_addr);
1964 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1965
1966 /*
1967 * The MTA is a register array of 128 32-bit registers. It is treated
1968 * like an array of 4096 bits. We want to set bit
1969 * BitArray[vector_value]. So we figure out what register the bit is
1970 * in, read it, OR in the new bit, then write back the new value. The
1971 * register is determined by the upper 7 bits of the vector value and
1972 * the bit within that register are determined by the lower 5 bits of
1973 * the value.
1974 */
1975 vector_reg = (vector >> 5) & 0x7F;
1976 vector_bit = vector & 0x1F;
80960ab0 1977 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
9a799d71
AK		 1978}
1979
9a799d71 1980/**
c44ade9e 1981 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
9a799d71 1982 * @hw: pointer to hardware structure
2853eb89 1983 * @netdev: pointer to net device structure
9a799d71
AK		 1984 *
1985 * The given list replaces any existing list. Clears the MC addrs from receive
c44ade9e 1986 * address registers and the multicast table. Uses unused receive address
9a799d71
AK		 1987 * registers for the first multicast addresses, and hashes the rest into the
1988 * multicast table.
1989 **/
2853eb89
JP		 1990s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1991 struct net_device *netdev)
9a799d71 1992{
22bedad3 1993 struct netdev_hw_addr *ha;
9a799d71 1994 u32 i;
9a799d71
AK		 1995
1996 /*
1997 * Set the new number of MC addresses that we are being requested to
1998 * use.
1999 */
2853eb89 2000 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
9a799d71
AK		 2001 hw->addr_ctrl.mta_in_use = 0;
2002
80960ab0 2003 /* Clear mta_shadow */
9a799d71 2004 hw_dbg(hw, " Clearing MTA\n");
80960ab0 2005 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
9a799d71 2006
80960ab0 2007 /* Update mta shadow */
22bedad3 2008 netdev_for_each_mc_addr(ha, netdev) {
9a799d71 2009 hw_dbg(hw, " Adding the multicast addresses:\n");
22bedad3 2010 ixgbe_set_mta(hw, ha->addr);
9a799d71
AK		 2011 }
2012
2013 /* Enable mta */
80960ab0
ET		 2014 for (i = 0; i < hw->mac.mcft_size; i++)
2015 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2016 hw->mac.mta_shadow[i]);
2017
9a799d71
AK		 2018 if (hw->addr_ctrl.mta_in_use > 0)
2019 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
e7cf745b 2020 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
9a799d71 2021
c44ade9e 2022 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
9a799d71
AK		 2023 return 0;
2024}
2025
2026/**
c44ade9e 2027 * ixgbe_enable_mc_generic - Enable multicast address in RAR
9a799d71
AK		 2028 * @hw: pointer to hardware structure
2029 *
c44ade9e 2030 * Enables multicast address in RAR and the use of the multicast hash table.
9a799d71 2031 **/
c44ade9e 2032s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2033{
c44ade9e 2034 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
9a799d71 2035
c44ade9e
JB		 2036 if (a->mta_in_use > 0)
2037 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
e7cf745b 2038 hw->mac.mc_filter_type);
9a799d71
AK		 2039
2040 return 0;
2041}
2042
2043/**
c44ade9e 2044 * ixgbe_disable_mc_generic - Disable multicast address in RAR
9a799d71 2045 * @hw: pointer to hardware structure
9a799d71 2046 *
c44ade9e 2047 * Disables multicast address in RAR and the use of the multicast hash table.
9a799d71 2048 **/
c44ade9e 2049s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
9a799d71 2050{
c44ade9e 2051 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2b9ade93 2052
c44ade9e
JB		 2053 if (a->mta_in_use > 0)
2054 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
9a799d71
AK		 2055
2056 return 0;
2057}
2058
11afc1b1 2059/**
620fa036 2060 * ixgbe_fc_enable_generic - Enable flow control
11afc1b1 2061 * @hw: pointer to hardware structure
11afc1b1
PW		 2062 *
2063 * Enable flow control according to the current settings.
2064 **/
041441d0 2065s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
11afc1b1 2066{
620fa036 2067 u32 mflcn_reg, fccfg_reg;
11afc1b1 2068 u32 reg;
16b61beb 2069 u32 fcrtl, fcrth;
041441d0 2070 int i;
70b77628 2071
e5776620 2072 /* Validate the water mark configuration. */
e90dd264
MR		 2073 if (!hw->fc.pause_time)
2074 return IXGBE_ERR_INVALID_LINK_SETTINGS;
70b77628 2075
e5776620
JK		 2076 /* Low water mark of zero causes XOFF floods */
2077 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2078 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2079 hw->fc.high_water[i]) {
2080 if (!hw->fc.low_water[i] ||
2081 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2082 hw_dbg(hw, "Invalid water mark configuration\n");
e90dd264 2083 return IXGBE_ERR_INVALID_LINK_SETTINGS;
e5776620
JK		 2084 }
2085 }
2086 }
2087
620fa036 2088 /* Negotiate the fc mode to use */
786e9a5f 2089 ixgbe_fc_autoneg(hw);
11afc1b1 2090
620fa036 2091 /* Disable any previous flow control settings */
11afc1b1 2092 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
041441d0 2093 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
11afc1b1
PW		 2094
2095 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2096 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2097
2098 /*
2099 * The possible values of fc.current_mode are:
2100 * 0: Flow control is completely disabled
2101 * 1: Rx flow control is enabled (we can receive pause frames,
2102 * but not send pause frames).
bb3daa4a
PW		 2103 * 2: Tx flow control is enabled (we can send pause frames but
2104 * we do not support receiving pause frames).
11afc1b1
PW		 2105 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2106 * other: Invalid.
2107 */
2108 switch (hw->fc.current_mode) {
2109 case ixgbe_fc_none:
620fa036
MC		 2110 /*
2111 * Flow control is disabled by software override or autoneg.
2112 * The code below will actually disable it in the HW.
2113 */
11afc1b1
PW		 2114 break;
2115 case ixgbe_fc_rx_pause:
2116 /*
2117 * Rx Flow control is enabled and Tx Flow control is
2118 * disabled by software override. Since there really
2119 * isn't a way to advertise that we are capable of RX
2120 * Pause ONLY, we will advertise that we support both
2121 * symmetric and asymmetric Rx PAUSE. Later, we will
2122 * disable the adapter's ability to send PAUSE frames.
2123 */
2124 mflcn_reg |= IXGBE_MFLCN_RFCE;
2125 break;
2126 case ixgbe_fc_tx_pause:
2127 /*
2128 * Tx Flow control is enabled, and Rx Flow control is
2129 * disabled by software override.
2130 */
2131 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2132 break;
2133 case ixgbe_fc_full:
2134 /* Flow control (both Rx and Tx) is enabled by SW override. */
2135 mflcn_reg |= IXGBE_MFLCN_RFCE;
2136 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2137 break;
2138 default:
2139 hw_dbg(hw, "Flow control param set incorrectly\n");
e90dd264 2140 return IXGBE_ERR_CONFIG;
11afc1b1
PW		 2141 }
2142
620fa036 2143 /* Set 802.3x based flow control settings. */
2132d381 2144 mflcn_reg |= IXGBE_MFLCN_DPF;
11afc1b1
PW		 2145 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2146 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2147
041441d0
AD		 2148 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2149 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2150 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2151 hw->fc.high_water[i]) {
e5776620 2152 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
041441d0
AD		 2153 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2154 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2155 } else {
2156 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2157 /*
2158 * In order to prevent Tx hangs when the internal Tx
2159 * switch is enabled we must set the high water mark
2160 * to the maximum FCRTH value. This allows the Tx
2161 * switch to function even under heavy Rx workloads.
2162 */
2163 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2164 }
11afc1b1 2165
041441d0
AD		 2166 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2167 }
16b61beb 2168
11afc1b1 2169 /* Configure pause time (2 TCs per register) */
041441d0
AD		 2170 reg = hw->fc.pause_time * 0x00010001;
2171 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2172 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2173
2174 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
11afc1b1 2175
e90dd264 2176 return 0;
11afc1b1
PW		 2177}
2178
0ecc061d 2179/**
67a79df2 2180 * ixgbe_negotiate_fc - Negotiate flow control
0ecc061d 2181 * @hw: pointer to hardware structure
67a79df2
AD		 2182 * @adv_reg: flow control advertised settings
2183 * @lp_reg: link partner's flow control settings
2184 * @adv_sym: symmetric pause bit in advertisement
2185 * @adv_asm: asymmetric pause bit in advertisement
2186 * @lp_sym: symmetric pause bit in link partner advertisement
2187 * @lp_asm: asymmetric pause bit in link partner advertisement
0ecc061d 2188 *
67a79df2
AD		 2189 * Find the intersection between advertised settings and link partner's
2190 * advertised settings
0ecc061d 2191 **/
67a79df2
AD		 2192static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2193 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
0ecc061d 2194{
67a79df2
AD		 2195 if ((!(adv_reg)) || (!(lp_reg)))
2196 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2197
67a79df2
AD		 2198 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2199 /*
2200 * Now we need to check if the user selected Rx ONLY
2201 * of pause frames. In this case, we had to advertise
2202 * FULL flow control because we could not advertise RX
2203 * ONLY. Hence, we must now check to see if we need to
2204 * turn OFF the TRANSMISSION of PAUSE frames.
2205 */
2206 if (hw->fc.requested_mode == ixgbe_fc_full) {
2207 hw->fc.current_mode = ixgbe_fc_full;
2208 hw_dbg(hw, "Flow Control = FULL.\n");
2209 } else {
2210 hw->fc.current_mode = ixgbe_fc_rx_pause;
2211 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2212 }
2213 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2214 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2215 hw->fc.current_mode = ixgbe_fc_tx_pause;
2216 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2217 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2218 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2219 hw->fc.current_mode = ixgbe_fc_rx_pause;
2220 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
0b0c2b31 2221 } else {
67a79df2
AD		 2222 hw->fc.current_mode = ixgbe_fc_none;
2223 hw_dbg(hw, "Flow Control = NONE.\n");
539e5f02 2224 }
67a79df2 2225 return 0;
0b0c2b31
ET		 2226}
2227
2228/**
2229 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2230 * @hw: pointer to hardware structure
2231 *
2232 * Enable flow control according on 1 gig fiber.
2233 **/
2234static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2235{
2236 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
e90dd264 2237 s32 ret_val;
539e5f02
PWJ		 2238
2239 /*
2240 * On multispeed fiber at 1g, bail out if
2241 * - link is up but AN did not complete, or if
2242 * - link is up and AN completed but timed out
2243 */
0b0c2b31
ET		 2244
2245 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
53f096de 2246 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
786e9a5f 2247 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
e90dd264 2248 return IXGBE_ERR_FC_NOT_NEGOTIATED;
539e5f02 2249
0b0c2b31
ET		 2250 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2251 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2252
2253 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2254 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2255 IXGBE_PCS1GANA_ASM_PAUSE,
2256 IXGBE_PCS1GANA_SYM_PAUSE,
2257 IXGBE_PCS1GANA_ASM_PAUSE);
2258
0b0c2b31
ET		 2259 return ret_val;
2260}
2261
2262/**
2263 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2264 * @hw: pointer to hardware structure
2265 *
2266 * Enable flow control according to IEEE clause 37.
2267 **/
2268static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2269{
2270 u32 links2, anlp1_reg, autoc_reg, links;
e90dd264 2271 s32 ret_val;
0b0c2b31 2272
9bbe3a57 2273 /*
0b0c2b31
ET		 2274 * On backplane, bail out if
2275 * - backplane autoneg was not completed, or if
2276 * - we are 82599 and link partner is not AN enabled
9bbe3a57 2277 */
0b0c2b31 2278 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
786e9a5f 2279 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
e90dd264 2280 return IXGBE_ERR_FC_NOT_NEGOTIATED;
9bbe3a57 2281
0b0c2b31
ET		 2282 if (hw->mac.type == ixgbe_mac_82599EB) {
2283 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
786e9a5f 2284 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
e90dd264 2285 return IXGBE_ERR_FC_NOT_NEGOTIATED;
0b0c2b31 2286 }
0ecc061d 2287 /*
0b0c2b31 2288 * Read the 10g AN autoc and LP ability registers and resolve
0ecc061d
PWJ		 2289 * local flow control settings accordingly
2290 */
0b0c2b31
ET		 2291 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2292 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
539e5f02 2293
0b0c2b31
ET		 2294 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2295 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2296 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2297
0b0c2b31
ET		 2298 return ret_val;
2299}
2300
2301/**
2302 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2303 * @hw: pointer to hardware structure
2304 *
2305 * Enable flow control according to IEEE clause 37.
2306 **/
2307static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2308{
2309 u16 technology_ability_reg = 0;
2310 u16 lp_technology_ability_reg = 0;
2311
2312 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2313 MDIO_MMD_AN,
2314 &technology_ability_reg);
2315 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2316 MDIO_MMD_AN,
2317 &lp_technology_ability_reg);
2318
2319 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2320 (u32)lp_technology_ability_reg,
2321 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2322 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2323}
2324
2325/**
67a79df2 2326 * ixgbe_fc_autoneg - Configure flow control
11afc1b1
PW		 2327 * @hw: pointer to hardware structure
2328 *
67a79df2
AD		 2329 * Compares our advertised flow control capabilities to those advertised by
2330 * our link partner, and determines the proper flow control mode to use.
11afc1b1 2331 **/
67a79df2 2332void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
11afc1b1 2333{
67a79df2
AD		 2334 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2335 ixgbe_link_speed speed;
2336 bool link_up;
11afc1b1
PW		 2337
2338 /*
67a79df2
AD		 2339 * AN should have completed when the cable was plugged in.
2340 * Look for reasons to bail out. Bail out if:
2341 * - FC autoneg is disabled, or if
2342 * - link is not up.
2343 *
2344 * Since we're being called from an LSC, link is already known to be up.
2345 * So use link_up_wait_to_complete=false.
11afc1b1 2346 */
67a79df2 2347 if (hw->fc.disable_fc_autoneg)
620fa036 2348 goto out;
11afc1b1 2349
67a79df2
AD		 2350 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2351 if (!link_up)
11afc1b1 2352 goto out;
0b0c2b31
ET		 2353
2354 switch (hw->phy.media_type) {
67a79df2 2355 /* Autoneg flow control on fiber adapters */
0b0c2b31 2356 case ixgbe_media_type_fiber:
67a79df2
AD		 2357 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2358 ret_val = ixgbe_fc_autoneg_fiber(hw);
2359 break;
2360
2361 /* Autoneg flow control on backplane adapters */
0b0c2b31 2362 case ixgbe_media_type_backplane:
67a79df2 2363 ret_val = ixgbe_fc_autoneg_backplane(hw);
0b0c2b31
ET		 2364 break;
2365
67a79df2 2366 /* Autoneg flow control on copper adapters */
0b0c2b31 2367 case ixgbe_media_type_copper:
73d80953 2368 if (ixgbe_device_supports_autoneg_fc(hw))
67a79df2 2369 ret_val = ixgbe_fc_autoneg_copper(hw);
0b0c2b31
ET		 2370 break;
2371
2372 default:
620fa036 2373 break;
0b0c2b31 2374 }
539e5f02 2375
11afc1b1 2376out:
67a79df2
AD		 2377 if (ret_val == 0) {
2378 hw->fc.fc_was_autonegged = true;
2379 } else {
2380 hw->fc.fc_was_autonegged = false;
2381 hw->fc.current_mode = hw->fc.requested_mode;
2382 }
11afc1b1
PW		 2383}
2384
1f86c983
DS		 2385/**
2386 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2387 * @hw: pointer to hardware structure
2388 *
2389 * System-wide timeout range is encoded in PCIe Device Control2 register.
2390 *
2391 * Add 10% to specified maximum and return the number of times to poll for
2392 * completion timeout, in units of 100 microsec. Never return less than
2393 * 800 = 80 millisec.
2394 **/
2395static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2396{
1f86c983
DS		 2397 s16 devctl2;
2398 u32 pollcnt;
2399
0d7c6e00 2400 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
1f86c983
DS		 2401 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2402
2403 switch (devctl2) {
2404 case IXGBE_PCIDEVCTRL2_65_130ms:
2405 pollcnt = 1300; /* 130 millisec */
2406 break;
2407 case IXGBE_PCIDEVCTRL2_260_520ms:
2408 pollcnt = 5200; /* 520 millisec */
2409 break;
2410 case IXGBE_PCIDEVCTRL2_1_2s:
2411 pollcnt = 20000; /* 2 sec */
2412 break;
2413 case IXGBE_PCIDEVCTRL2_4_8s:
2414 pollcnt = 80000; /* 8 sec */
2415 break;
2416 case IXGBE_PCIDEVCTRL2_17_34s:
2417 pollcnt = 34000; /* 34 sec */
2418 break;
2419 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2420 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2421 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2422 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2423 default:
2424 pollcnt = 800; /* 80 millisec minimum */
2425 break;
2426 }
2427
2428 /* add 10% to spec maximum */
2429 return (pollcnt * 11) / 10;
2430}
2431
9a799d71
AK		 2432/**
2433 * ixgbe_disable_pcie_master - Disable PCI-express master access
2434 * @hw: pointer to hardware structure
2435 *
2436 * Disables PCI-Express master access and verifies there are no pending
2437 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2438 * bit hasn't caused the master requests to be disabled, else 0
2439 * is returned signifying master requests disabled.
2440 **/
ff9d1a5a 2441static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
9a799d71 2442{
1f86c983 2443 u32 i, poll;
ff9d1a5a
ET		 2444 u16 value;
2445
2446 /* Always set this bit to ensure any future transactions are blocked */
2447 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
a4297dc2 2448
ff9d1a5a 2449 /* Exit if master requests are blocked */
14438464
MR		 2450 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2451 ixgbe_removed(hw->hw_addr))
e90dd264 2452 return 0;
9a799d71 2453
ff9d1a5a 2454 /* Poll for master request bit to clear */
9a799d71 2455 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
a4297dc2 2456 udelay(100);
ff9d1a5a 2457 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
e90dd264 2458 return 0;
a4297dc2
ET		 2459 }
2460
ff9d1a5a
ET		 2461 /*
2462 * Two consecutive resets are required via CTRL.RST per datasheet
2463 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2464 * of this need. The first reset prevents new master requests from
2465 * being issued by our device. We then must wait 1usec or more for any
2466 * remaining completions from the PCIe bus to trickle in, and then reset
2467 * again to clear out any effects they may have had on our device.
2468 */
a4297dc2 2469 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
ff9d1a5a 2470 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 2471
2472 /*
2473 * Before proceeding, make sure that the PCIe block does not have
2474 * transactions pending.
2475 */
1f86c983
DS		 2476 poll = ixgbe_pcie_timeout_poll(hw);
2477 for (i = 0; i < poll; i++) {
9a799d71 2478 udelay(100);
14438464
MR		 2479 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2480 if (ixgbe_removed(hw->hw_addr))
e90dd264 2481 return 0;
ff9d1a5a 2482 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
e90dd264 2483 return 0;
9a799d71
AK		 2484 }
2485
ff9d1a5a 2486 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
e90dd264 2487 return IXGBE_ERR_MASTER_REQUESTS_PENDING;
9a799d71
AK		 2488}
2489
9a799d71 2490/**
c44ade9e 2491 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
9a799d71 2492 * @hw: pointer to hardware structure
c44ade9e 2493 * @mask: Mask to specify which semaphore to acquire
9a799d71 2494 *
da74cd4a 2495 * Acquires the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2496 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2497 **/
030eaece 2498s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
9a799d71 2499{
674c18b2 2500 u32 gssr = 0;
9a799d71
AK		 2501 u32 swmask = mask;
2502 u32 fwmask = mask << 5;
674c18b2
ET		 2503 u32 timeout = 200;
2504 u32 i;
9a799d71 2505
674c18b2 2506 for (i = 0; i < timeout; i++) {
dbf893ee 2507 /*
674c18b2
ET		 2508 * SW NVM semaphore bit is used for access to all
2509 * SW_FW_SYNC bits (not just NVM)
dbf893ee 2510 */
9a799d71 2511 if (ixgbe_get_eeprom_semaphore(hw))
539e5f02 2512 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2513
2514 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
674c18b2
ET		 2515 if (!(gssr & (fwmask | swmask))) {
2516 gssr |= swmask;
2517 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2518 ixgbe_release_eeprom_semaphore(hw);
2519 return 0;
2520 } else {
2521 /* Resource is currently in use by FW or SW */
2522 ixgbe_release_eeprom_semaphore(hw);
2523 usleep_range(5000, 10000);
2524 }
9a799d71
AK		 2525 }
2526
674c18b2
ET		 2527 /* If time expired clear the bits holding the lock and retry */
2528 if (gssr & (fwmask | swmask))
2529 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
9a799d71 2530
674c18b2
ET		 2531 usleep_range(5000, 10000);
2532 return IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 2533}
2534
2535/**
2536 * ixgbe_release_swfw_sync - Release SWFW semaphore
2537 * @hw: pointer to hardware structure
c44ade9e 2538 * @mask: Mask to specify which semaphore to release
9a799d71 2539 *
da74cd4a 2540 * Releases the SWFW semaphore through the GSSR register for the specified
9a799d71
AK		 2541 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2542 **/
030eaece 2543void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
9a799d71
AK		 2544{
2545 u32 gssr;
2546 u32 swmask = mask;
2547
2548 ixgbe_get_eeprom_semaphore(hw);
2549
2550 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2551 gssr &= ~swmask;
2552 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2553
2554 ixgbe_release_eeprom_semaphore(hw);
2555}
2556
429d6a3b
DS		 2557/**
2558 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2559 * @hw: pointer to hardware structure
2560 * @reg_val: Value we read from AUTOC
2561 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2562 * true in this the generic case.
2563 *
2564 * The default case requires no protection so just to the register read.
2565 **/
2566s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2567{
2568 *locked = false;
2569 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2570 return 0;
2571}
2572
2573/**
2574 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2575 * @hw: pointer to hardware structure
2576 * @reg_val: value to write to AUTOC
2577 * @locked: bool to indicate whether the SW/FW lock was already taken by
2578 * previous read.
2579 **/
2580s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2581{
2582 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2583 return 0;
2584}
2585
d2f5e7f3
AS		 2586/**
2587 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2588 * @hw: pointer to hardware structure
2589 *
2590 * Stops the receive data path and waits for the HW to internally
2591 * empty the Rx security block.
2592 **/
2593s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2594{
2595#define IXGBE_MAX_SECRX_POLL 40
2596 int i;
2597 int secrxreg;
2598
2599 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2600 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2601 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2602 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2603 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2604 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2605 break;
2606 else
2607 /* Use interrupt-safe sleep just in case */
db76ad47 2608 udelay(1000);
d2f5e7f3
AS		 2609 }
2610
2611 /* For informational purposes only */
2612 if (i >= IXGBE_MAX_SECRX_POLL)
6ec1b71f 2613 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
d2f5e7f3
AS		 2614
2615 return 0;
2616
2617}
2618
2619/**
2620 * ixgbe_enable_rx_buff - Enables the receive data path
2621 * @hw: pointer to hardware structure
2622 *
2623 * Enables the receive data path
2624 **/
2625s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2626{
2627 int secrxreg;
2628
2629 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2630 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2631 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2632 IXGBE_WRITE_FLUSH(hw);
2633
2634 return 0;
2635}
2636
11afc1b1
PW		 2637/**
2638 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2639 * @hw: pointer to hardware structure
2640 * @regval: register value to write to RXCTRL
2641 *
2642 * Enables the Rx DMA unit
2643 **/
2644s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2645{
1f9ac57c
DS		 2646 if (regval & IXGBE_RXCTRL_RXEN)
2647 hw->mac.ops.enable_rx(hw);
2648 else
2649 hw->mac.ops.disable_rx(hw);
11afc1b1
PW		 2650
2651 return 0;
2652}
87c12017
PW		 2653
2654/**
2655 * ixgbe_blink_led_start_generic - Blink LED based on index.
2656 * @hw: pointer to hardware structure
2657 * @index: led number to blink
2658 **/
2659s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2660{
2661 ixgbe_link_speed speed = 0;
3db1cd5c 2662 bool link_up = false;
87c12017
PW		 2663 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2664 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2665 bool locked = false;
e90dd264 2666 s32 ret_val;
87c12017
PW		 2667
2668 /*
2669 * Link must be up to auto-blink the LEDs;
2670 * Force it if link is down.
2671 */
2672 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2673
2674 if (!link_up) {
429d6a3b 2675 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2676 if (ret_val)
e90dd264 2677 return ret_val;
d7bbcd32 2678
50ac58ba 2679 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2680 autoc_reg |= IXGBE_AUTOC_FLU;
429d6a3b
DS		 2681
2682 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2683 if (ret_val)
e90dd264 2684 return ret_val;
429d6a3b 2685
945a5151 2686 IXGBE_WRITE_FLUSH(hw);
d7bbcd32 2687
032b4325 2688 usleep_range(10000, 20000);
87c12017
PW		 2689 }
2690
2691 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2692 led_reg |= IXGBE_LED_BLINK(index);
2693 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2694 IXGBE_WRITE_FLUSH(hw);
2695
e90dd264 2696 return 0;
87c12017
PW		 2697}
2698
2699/**
2700 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2701 * @hw: pointer to hardware structure
2702 * @index: led number to stop blinking
2703 **/
2704s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2705{
429d6a3b 2706 u32 autoc_reg = 0;
87c12017 2707 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
429d6a3b 2708 bool locked = false;
e90dd264 2709 s32 ret_val;
d7bbcd32 2710
429d6a3b 2711 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
f8cf7a00 2712 if (ret_val)
e90dd264 2713 return ret_val;
87c12017
PW		 2714
2715 autoc_reg &= ~IXGBE_AUTOC_FLU;
2716 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
87c12017 2717
429d6a3b 2718 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
f8cf7a00 2719 if (ret_val)
e90dd264 2720 return ret_val;
d7bbcd32 2721
87c12017
PW		 2722 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2723 led_reg &= ~IXGBE_LED_BLINK(index);
2724 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2725 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2726 IXGBE_WRITE_FLUSH(hw);
2727
e90dd264 2728 return 0;
87c12017 2729}
21ce849b
MC		 2730
2731/**
2732 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2733 * @hw: pointer to hardware structure
2734 * @san_mac_offset: SAN MAC address offset
2735 *
2736 * This function will read the EEPROM location for the SAN MAC address
2737 * pointer, and returns the value at that location. This is used in both
2738 * get and set mac_addr routines.
2739 **/
2740static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
e7cf745b 2741 u16 *san_mac_offset)
21ce849b 2742{
be0c27b4
MR		 2743 s32 ret_val;
2744
21ce849b
MC		 2745 /*
2746 * First read the EEPROM pointer to see if the MAC addresses are
2747 * available.
2748 */
be0c27b4
MR		 2749 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2750 san_mac_offset);
2751 if (ret_val)
2752 hw_err(hw, "eeprom read at offset %d failed\n",
2753 IXGBE_SAN_MAC_ADDR_PTR);
21ce849b 2754
be0c27b4 2755 return ret_val;
21ce849b
MC		 2756}
2757
2758/**
2759 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2760 * @hw: pointer to hardware structure
2761 * @san_mac_addr: SAN MAC address
2762 *
2763 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2764 * per-port, so set_lan_id() must be called before reading the addresses.
2765 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2766 * upon for non-SFP connections, so we must call it here.
2767 **/
2768s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2769{
2770 u16 san_mac_data, san_mac_offset;
2771 u8 i;
be0c27b4 2772 s32 ret_val;
21ce849b
MC		 2773
2774 /*
2775 * First read the EEPROM pointer to see if the MAC addresses are
2776 * available. If they're not, no point in calling set_lan_id() here.
2777 */
be0c27b4
MR		 2778 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2779 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
21ce849b 2780
be0c27b4 2781 goto san_mac_addr_clr;
21ce849b
MC		 2782
2783 /* make sure we know which port we need to program */
2784 hw->mac.ops.set_lan_id(hw);
2785 /* apply the port offset to the address offset */
2786 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
e7cf745b 2787 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
21ce849b 2788 for (i = 0; i < 3; i++) {
be0c27b4
MR		 2789 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2790 &san_mac_data);
2791 if (ret_val) {
2792 hw_err(hw, "eeprom read at offset %d failed\n",
2793 san_mac_offset);
2794 goto san_mac_addr_clr;
2795 }
21ce849b
MC		 2796 san_mac_addr[i * 2] = (u8)(san_mac_data);
2797 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2798 san_mac_offset++;
2799 }
21ce849b 2800 return 0;
be0c27b4
MR		 2801
2802san_mac_addr_clr:
2803 /* No addresses available in this EEPROM. It's not necessarily an
2804 * error though, so just wipe the local address and return.
2805 */
2806 for (i = 0; i < 6; i++)
2807 san_mac_addr[i] = 0xFF;
2808 return ret_val;
21ce849b
MC		 2809}
2810
2811/**
2812 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2813 * @hw: pointer to hardware structure
2814 *
2815 * Read PCIe configuration space, and get the MSI-X vector count from
2816 * the capabilities table.
2817 **/
71161302 2818u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
21ce849b 2819{
e90dd264 2820 u16 msix_count;
71161302
ET		 2821 u16 max_msix_count;
2822 u16 pcie_offset;
2823
2824 switch (hw->mac.type) {
2825 case ixgbe_mac_82598EB:
2826 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2827 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2828 break;
2829 case ixgbe_mac_82599EB:
2830 case ixgbe_mac_X540:
9a75a1ac
DS		 2831 case ixgbe_mac_X550:
2832 case ixgbe_mac_X550EM_x:
71161302
ET		 2833 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2834 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2835 break;
2836 default:
e90dd264 2837 return 1;
71161302
ET		 2838 }
2839
14438464
MR		 2840 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2841 if (ixgbe_removed(hw->hw_addr))
2842 msix_count = 0;
21ce849b
MC		 2843 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2844
71161302 2845 /* MSI-X count is zero-based in HW */
21ce849b
MC		 2846 msix_count++;
2847
71161302
ET		 2848 if (msix_count > max_msix_count)
2849 msix_count = max_msix_count;
2850
21ce849b
MC		 2851 return msix_count;
2852}
2853
2854/**
2855 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2856 * @hw: pointer to hardware struct
2857 * @rar: receive address register index to disassociate
2858 * @vmdq: VMDq pool index to remove from the rar
2859 **/
2860s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2861{
2862 u32 mpsar_lo, mpsar_hi;
2863 u32 rar_entries = hw->mac.num_rar_entries;
2864
c700f4e6
ET		 2865 /* Make sure we are using a valid rar index range */
2866 if (rar >= rar_entries) {
2867 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2868 return IXGBE_ERR_INVALID_ARGUMENT;
2869 }
21ce849b 2870
c700f4e6
ET		 2871 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2872 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
21ce849b 2873
19458bd4 2874 if (ixgbe_removed(hw->hw_addr))
e90dd264 2875 return 0;
19458bd4 2876
c700f4e6 2877 if (!mpsar_lo && !mpsar_hi)
e90dd264 2878 return 0;
21ce849b 2879
c700f4e6
ET		 2880 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2881 if (mpsar_lo) {
2882 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2883 mpsar_lo = 0;
2884 }
2885 if (mpsar_hi) {
2886 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2887 mpsar_hi = 0;
2888 }
2889 } else if (vmdq < 32) {
2890 mpsar_lo &= ~(1 << vmdq);
2891 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
21ce849b 2892 } else {
c700f4e6
ET		 2893 mpsar_hi &= ~(1 << (vmdq - 32));
2894 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
21ce849b
MC		 2895 }
2896
c700f4e6
ET		 2897 /* was that the last pool using this rar? */
2898 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2899 hw->mac.ops.clear_rar(hw, rar);
21ce849b
MC		 2900 return 0;
2901}
2902
2903/**
2904 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2905 * @hw: pointer to hardware struct
2906 * @rar: receive address register index to associate with a VMDq index
2907 * @vmdq: VMDq pool index
2908 **/
2909s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2910{
2911 u32 mpsar;
2912 u32 rar_entries = hw->mac.num_rar_entries;
2913
c700f4e6
ET		 2914 /* Make sure we are using a valid rar index range */
2915 if (rar >= rar_entries) {
21ce849b 2916 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
c700f4e6
ET		 2917 return IXGBE_ERR_INVALID_ARGUMENT;
2918 }
2919
2920 if (vmdq < 32) {
2921 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2922 mpsar |= 1 << vmdq;
2923 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2924 } else {
2925 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2926 mpsar |= 1 << (vmdq - 32);
2927 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
21ce849b
MC		 2928 }
2929 return 0;
2930}
2931
7fa7c9dc
AD		 2932/**
2933 * This function should only be involved in the IOV mode.
2934 * In IOV mode, Default pool is next pool after the number of
2935 * VFs advertized and not 0.
2936 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2937 *
2938 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2939 * @hw: pointer to hardware struct
2940 * @vmdq: VMDq pool index
2941 **/
2942s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2943{
2944 u32 rar = hw->mac.san_mac_rar_index;
2945
2946 if (vmdq < 32) {
2947 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2948 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2949 } else {
2950 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2951 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2952 }
2953
2954 return 0;
2955}
2956
21ce849b
MC		 2957/**
2958 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2959 * @hw: pointer to hardware structure
2960 **/
2961s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2962{
2963 int i;
2964
21ce849b
MC		 2965 for (i = 0; i < 128; i++)
2966 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2967
2968 return 0;
2969}
2970
2971/**
2972 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2973 * @hw: pointer to hardware structure
2974 * @vlan: VLAN id to write to VLAN filter
2975 *
2976 * return the VLVF index where this VLAN id should be placed
2977 *
2978 **/
5d5b7c39 2979static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
21ce849b
MC		 2980{
2981 u32 bits = 0;
2982 u32 first_empty_slot = 0;
2983 s32 regindex;
2984
2985 /* short cut the special case */
2986 if (vlan == 0)
2987 return 0;
2988
2989 /*
2990 * Search for the vlan id in the VLVF entries. Save off the first empty
2991 * slot found along the way
2992 */
2993 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2994 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2995 if (!bits && !(first_empty_slot))
2996 first_empty_slot = regindex;
2997 else if ((bits & 0x0FFF) == vlan)
2998 break;
2999 }
3000
3001 /*
3002 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3003 * in the VLVF. Else use the first empty VLVF register for this
3004 * vlan id.
3005 */
3006 if (regindex >= IXGBE_VLVF_ENTRIES) {
3007 if (first_empty_slot)
3008 regindex = first_empty_slot;
3009 else {
3010 hw_dbg(hw, "No space in VLVF.\n");
3011 regindex = IXGBE_ERR_NO_SPACE;
3012 }
3013 }
3014
3015 return regindex;
3016}
3017
3018/**
3019 * ixgbe_set_vfta_generic - Set VLAN filter table
3020 * @hw: pointer to hardware structure
3021 * @vlan: VLAN id to write to VLAN filter
3022 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3023 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3024 *
3025 * Turn on/off specified VLAN in the VLAN filter table.
3026 **/
3027s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
e7cf745b 3028 bool vlan_on)
21ce849b
MC		 3029{
3030 s32 regindex;
3031 u32 bitindex;
3032 u32 vfta;
3033 u32 bits;
3034 u32 vt;
3035 u32 targetbit;
3036 bool vfta_changed = false;
3037
3038 if (vlan > 4095)
3039 return IXGBE_ERR_PARAM;
3040
3041 /*
3042 * this is a 2 part operation - first the VFTA, then the
3043 * VLVF and VLVFB if VT Mode is set
3044 * We don't write the VFTA until we know the VLVF part succeeded.
3045 */
3046
3047 /* Part 1
3048 * The VFTA is a bitstring made up of 128 32-bit registers
3049 * that enable the particular VLAN id, much like the MTA:
3050 * bits[11-5]: which register
3051 * bits[4-0]: which bit in the register
3052 */
3053 regindex = (vlan >> 5) & 0x7F;
3054 bitindex = vlan & 0x1F;
3055 targetbit = (1 << bitindex);
3056 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3057
3058 if (vlan_on) {
3059 if (!(vfta & targetbit)) {
3060 vfta |= targetbit;
3061 vfta_changed = true;
3062 }
3063 } else {
3064 if ((vfta & targetbit)) {
3065 vfta &= ~targetbit;
3066 vfta_changed = true;
3067 }
3068 }
3069
3070 /* Part 2
3071 * If VT Mode is set
3072 * Either vlan_on
3073 * make sure the vlan is in VLVF
3074 * set the vind bit in the matching VLVFB
3075 * Or !vlan_on
3076 * clear the pool bit and possibly the vind
3077 */
3078 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3079 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3080 s32 vlvf_index;
3081
3082 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3083 if (vlvf_index < 0)
3084 return vlvf_index;
3085
3086 if (vlan_on) {
3087 /* set the pool bit */
3088 if (vind < 32) {
3089 bits = IXGBE_READ_REG(hw,
3090 IXGBE_VLVFB(vlvf_index*2));
3091 bits |= (1 << vind);
3092 IXGBE_WRITE_REG(hw,
3093 IXGBE_VLVFB(vlvf_index*2),
3094 bits);
3095 } else {
3096 bits = IXGBE_READ_REG(hw,
3097 IXGBE_VLVFB((vlvf_index*2)+1));
3098 bits |= (1 << (vind-32));
3099 IXGBE_WRITE_REG(hw,
3100 IXGBE_VLVFB((vlvf_index*2)+1),
3101 bits);
3102 }
3103 } else {
3104 /* clear the pool bit */
3105 if (vind < 32) {
3106 bits = IXGBE_READ_REG(hw,
3107 IXGBE_VLVFB(vlvf_index*2));
3108 bits &= ~(1 << vind);
3109 IXGBE_WRITE_REG(hw,
3110 IXGBE_VLVFB(vlvf_index*2),
3111 bits);
3112 bits |= IXGBE_READ_REG(hw,
3113 IXGBE_VLVFB((vlvf_index*2)+1));
3114 } else {
3115 bits = IXGBE_READ_REG(hw,
3116 IXGBE_VLVFB((vlvf_index*2)+1));
3117 bits &= ~(1 << (vind-32));
3118 IXGBE_WRITE_REG(hw,
3119 IXGBE_VLVFB((vlvf_index*2)+1),
3120 bits);
3121 bits |= IXGBE_READ_REG(hw,
3122 IXGBE_VLVFB(vlvf_index*2));
3123 }
3124 }
3125
3126 /*
3127 * If there are still bits set in the VLVFB registers
3128 * for the VLAN ID indicated we need to see if the
3129 * caller is requesting that we clear the VFTA entry bit.
3130 * If the caller has requested that we clear the VFTA
3131 * entry bit but there are still pools/VFs using this VLAN
3132 * ID entry then ignore the request. We're not worried
3133 * about the case where we're turning the VFTA VLAN ID
3134 * entry bit on, only when requested to turn it off as
3135 * there may be multiple pools and/or VFs using the
3136 * VLAN ID entry. In that case we cannot clear the
3137 * VFTA bit until all pools/VFs using that VLAN ID have also
3138 * been cleared. This will be indicated by "bits" being
3139 * zero.
3140 */
3141 if (bits) {
3142 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3143 (IXGBE_VLVF_VIEN | vlan));
3144 if (!vlan_on) {
3145 /* someone wants to clear the vfta entry
3146 * but some pools/VFs are still using it.
3147 * Ignore it. */
3148 vfta_changed = false;
3149 }
63b64de3 3150 } else {
21ce849b 3151 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
63b64de3 3152 }
21ce849b
MC		 3153 }
3154
3155 if (vfta_changed)
3156 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3157
3158 return 0;
3159}
3160
3161/**
3162 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3163 * @hw: pointer to hardware structure
3164 *
3165 * Clears the VLAN filer table, and the VMDq index associated with the filter
3166 **/
3167s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3168{
3169 u32 offset;
3170
3171 for (offset = 0; offset < hw->mac.vft_size; offset++)
3172 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3173
3174 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3175 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3176 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3177 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3178 }
3179
3180 return 0;
3181}
3182
3183/**
3184 * ixgbe_check_mac_link_generic - Determine link and speed status
3185 * @hw: pointer to hardware structure
3186 * @speed: pointer to link speed
3187 * @link_up: true when link is up
3188 * @link_up_wait_to_complete: bool used to wait for link up or not
3189 *
3190 * Reads the links register to determine if link is up and the current speed
3191 **/
3192s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
8c7bea32 3193 bool *link_up, bool link_up_wait_to_complete)
21ce849b 3194{
48de36c5 3195 u32 links_reg, links_orig;
21ce849b
MC		 3196 u32 i;
3197
48de36c5
ET		 3198 /* clear the old state */
3199 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3200
21ce849b 3201 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
48de36c5
ET		 3202
3203 if (links_orig != links_reg) {
3204 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3205 links_orig, links_reg);
3206 }
3207
21ce849b
MC		 3208 if (link_up_wait_to_complete) {
3209 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3210 if (links_reg & IXGBE_LINKS_UP) {
3211 *link_up = true;
3212 break;
3213 } else {
3214 *link_up = false;
3215 }
3216 msleep(100);
3217 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3218 }
3219 } else {
3220 if (links_reg & IXGBE_LINKS_UP)
3221 *link_up = true;
3222 else
3223 *link_up = false;
3224 }
3225
9a75a1ac
DS		 3226 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3227 case IXGBE_LINKS_SPEED_10G_82599:
3228 if ((hw->mac.type >= ixgbe_mac_X550) &&
3229 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3230 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3231 else
3232 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3233 break;
3234 case IXGBE_LINKS_SPEED_1G_82599:
21ce849b 3235 *speed = IXGBE_LINK_SPEED_1GB_FULL;
9a75a1ac
DS		 3236 break;
3237 case IXGBE_LINKS_SPEED_100_82599:
3238 if ((hw->mac.type >= ixgbe_mac_X550) &&
3239 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3240 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3241 else
3242 *speed = IXGBE_LINK_SPEED_100_FULL;
3243 break;
3244 default:
63d778df 3245 *speed = IXGBE_LINK_SPEED_UNKNOWN;
9a75a1ac 3246 }
21ce849b 3247
21ce849b
MC		 3248 return 0;
3249}
a391f1d5
DS		 3250
3251/**
49ce9c2c 3252 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
a391f1d5
DS		 3253 * the EEPROM
3254 * @hw: pointer to hardware structure
3255 * @wwnn_prefix: the alternative WWNN prefix
3256 * @wwpn_prefix: the alternative WWPN prefix
3257 *
3258 * This function will read the EEPROM from the alternative SAN MAC address
3259 * block to check the support for the alternative WWNN/WWPN prefix support.
3260 **/
3261s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
e7cf745b 3262 u16 *wwpn_prefix)
a391f1d5
DS		 3263{
3264 u16 offset, caps;
3265 u16 alt_san_mac_blk_offset;
3266
3267 /* clear output first */
3268 *wwnn_prefix = 0xFFFF;
3269 *wwpn_prefix = 0xFFFF;
3270
3271 /* check if alternative SAN MAC is supported */
be0c27b4
MR		 3272 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3273 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3274 goto wwn_prefix_err;
a391f1d5
DS		 3275
3276 if ((alt_san_mac_blk_offset == 0) ||
3277 (alt_san_mac_blk_offset == 0xFFFF))
e90dd264 3278 return 0;
a391f1d5
DS		 3279
3280 /* check capability in alternative san mac address block */
3281 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
be0c27b4
MR		 3282 if (hw->eeprom.ops.read(hw, offset, &caps))
3283 goto wwn_prefix_err;
a391f1d5 3284 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
e90dd264 3285 return 0;
a391f1d5
DS		 3286
3287 /* get the corresponding prefix for WWNN/WWPN */
3288 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
be0c27b4
MR		 3289 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3290 hw_err(hw, "eeprom read at offset %d failed\n", offset);
a391f1d5
DS		 3291
3292 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
be0c27b4
MR		 3293 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3294 goto wwn_prefix_err;
a391f1d5 3295
a391f1d5 3296 return 0;
be0c27b4
MR		 3297
3298wwn_prefix_err:
3299 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3300 return 0;
a391f1d5 3301}
a985b6c3
GR		 3302
3303/**
3304 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3305 * @hw: pointer to hardware structure
3306 * @enable: enable or disable switch for anti-spoofing
3307 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3308 *
3309 **/
3310void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3311{
3312 int j;
3313 int pf_target_reg = pf >> 3;
3314 int pf_target_shift = pf % 8;
3315 u32 pfvfspoof = 0;
3316
3317 if (hw->mac.type == ixgbe_mac_82598EB)
3318 return;
3319
3320 if (enable)
3321 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3322
3323 /*
3324 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3325 * MAC anti-spoof enables in each register array element.
3326 */
ef89e0a2 3327 for (j = 0; j < pf_target_reg; j++)
a985b6c3
GR		 3328 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3329
a985b6c3
GR		 3330 /*
3331 * The PF should be allowed to spoof so that it can support
ef89e0a2
AD		 3332 * emulation mode NICs. Do not set the bits assigned to the PF
3333 */
3334 pfvfspoof &= (1 << pf_target_shift) - 1;
3335 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3336
3337 /*
3338 * Remaining pools belong to the PF so they do not need to have
3339 * anti-spoofing enabled.
a985b6c3 3340 */
ef89e0a2
AD		 3341 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3342 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
a985b6c3
GR		 3343}
3344
3345/**
3346 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3347 * @hw: pointer to hardware structure
3348 * @enable: enable or disable switch for VLAN anti-spoofing
3349 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3350 *
3351 **/
3352void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3353{
3354 int vf_target_reg = vf >> 3;
3355 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3356 u32 pfvfspoof;
3357
3358 if (hw->mac.type == ixgbe_mac_82598EB)
3359 return;
3360
3361 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3362 if (enable)
3363 pfvfspoof |= (1 << vf_target_shift);
3364 else
3365 pfvfspoof &= ~(1 << vf_target_shift);
3366 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3367}
b776d104
ET		 3368
3369/**
3370 * ixgbe_get_device_caps_generic - Get additional device capabilities
3371 * @hw: pointer to hardware structure
3372 * @device_caps: the EEPROM word with the extra device capabilities
3373 *
3374 * This function will read the EEPROM location for the device capabilities,
3375 * and return the word through device_caps.
3376 **/
3377s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3378{
3379 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3380
3381 return 0;
3382}
80605c65
JF		 3383
3384/**
3385 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3386 * @hw: pointer to hardware structure
3387 * @num_pb: number of packet buffers to allocate
3388 * @headroom: reserve n KB of headroom
3389 * @strategy: packet buffer allocation strategy
3390 **/
3391void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3392 int num_pb,
3393 u32 headroom,
3394 int strategy)
3395{
3396 u32 pbsize = hw->mac.rx_pb_size;
3397 int i = 0;
3398 u32 rxpktsize, txpktsize, txpbthresh;
3399
3400 /* Reserve headroom */
3401 pbsize -= headroom;
3402
3403 if (!num_pb)
3404 num_pb = 1;
3405
3406 /* Divide remaining packet buffer space amongst the number
3407 * of packet buffers requested using supplied strategy.
3408 */
3409 switch (strategy) {
3410 case (PBA_STRATEGY_WEIGHTED):
3411 /* pba_80_48 strategy weight first half of packet buffer with
3412 * 5/8 of the packet buffer space.
3413 */
3414 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3415 pbsize -= rxpktsize * (num_pb / 2);
3416 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3417 for (; i < (num_pb / 2); i++)
3418 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3419 /* Fall through to configure remaining packet buffers */
3420 case (PBA_STRATEGY_EQUAL):
3421 /* Divide the remaining Rx packet buffer evenly among the TCs */
3422 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3423 for (; i < num_pb; i++)
3424 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3425 break;
3426 default:
3427 break;
3428 }
3429
3430 /*
3431 * Setup Tx packet buffer and threshold equally for all TCs
3432 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3433 * 10 since the largest packet we support is just over 9K.
3434 */
3435 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3436 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3437 for (i = 0; i < num_pb; i++) {
3438 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3439 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3440 }
3441
3442 /* Clear unused TCs, if any, to zero buffer size*/
3443 for (; i < IXGBE_MAX_PB; i++) {
3444 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3445 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3446 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3447 }
3448}
9612de92
ET		 3449
3450/**
3451 * ixgbe_calculate_checksum - Calculate checksum for buffer
3452 * @buffer: pointer to EEPROM
3453 * @length: size of EEPROM to calculate a checksum for
49ce9c2c 3454 *
9612de92
ET		 3455 * Calculates the checksum for some buffer on a specified length. The
3456 * checksum calculated is returned.
3457 **/
3458static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3459{
3460 u32 i;
3461 u8 sum = 0;
3462
3463 if (!buffer)
3464 return 0;
3465
3466 for (i = 0; i < length; i++)
3467 sum += buffer[i];
3468
3469 return (u8) (0 - sum);
3470}
3471
3472/**
3473 * ixgbe_host_interface_command - Issue command to manageability block
3474 * @hw: pointer to the HW structure
3475 * @buffer: contains the command to write and where the return status will
3476 * be placed
c466d7a7 3477 * @length: length of buffer, must be multiple of 4 bytes
b48e4aa3
DS		 3478 * @timeout: time in ms to wait for command completion
3479 * @return_data: read and return data from the buffer (true) or not (false)
3480 * Needed because FW structures are big endian and decoding of
3481 * these fields can be 8 bit or 16 bit based on command. Decoding
3482 * is not easily understood without making a table of commands.
3483 * So we will leave this up to the caller to read back the data
3484 * in these cases.
9612de92
ET		 3485 *
3486 * Communicates with the manageability block. On success return 0
3487 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3488 **/
6a14ee0c
DS		 3489s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3490 u32 length, u32 timeout,
3491 bool return_data)
9612de92 3492{
b48e4aa3 3493 u32 hicr, i, bi, fwsts;
9612de92 3494 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
b48e4aa3 3495 u16 buf_len, dword_len;
9612de92 3496
b48e4aa3
DS		 3497 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3498 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
e90dd264 3499 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3500 }
3501
b48e4aa3
DS		 3502 /* Set bit 9 of FWSTS clearing FW reset indication */
3503 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3504 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3505
9612de92
ET		 3506 /* Check that the host interface is enabled. */
3507 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3508 if ((hicr & IXGBE_HICR_EN) == 0) {
3509 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
e90dd264 3510 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3511 }
3512
b48e4aa3
DS		 3513 /* Calculate length in DWORDs. We must be DWORD aligned */
3514 if ((length % (sizeof(u32))) != 0) {
3515 hw_dbg(hw, "Buffer length failure, not aligned to dword");
3516 return IXGBE_ERR_INVALID_ARGUMENT;
3517 }
3518
9612de92
ET		 3519 dword_len = length >> 2;
3520
3521 /*
3522 * The device driver writes the relevant command block
3523 * into the ram area.
3524 */
3525 for (i = 0; i < dword_len; i++)
3526 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
79488c58 3527 i, cpu_to_le32(buffer[i]));
9612de92
ET		 3528
3529 /* Setting this bit tells the ARC that a new command is pending. */
3530 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3531
b48e4aa3 3532 for (i = 0; i < timeout; i++) {
9612de92
ET		 3533 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3534 if (!(hicr & IXGBE_HICR_C))
3535 break;
3536 usleep_range(1000, 2000);
3537 }
3538
3539 /* Check command successful completion. */
b48e4aa3 3540 if ((timeout != 0 && i == timeout) ||
9612de92
ET		 3541 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3542 hw_dbg(hw, "Command has failed with no status valid.\n");
e90dd264 3543 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3544 }
3545
b48e4aa3
DS		 3546 if (!return_data)
3547 return 0;
3548
9612de92
ET		 3549 /* Calculate length in DWORDs */
3550 dword_len = hdr_size >> 2;
3551
3552 /* first pull in the header so we know the buffer length */
331bcf45
ET		 3553 for (bi = 0; bi < dword_len; bi++) {
3554 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3555 le32_to_cpus(&buffer[bi]);
79488c58 3556 }
9612de92
ET		 3557
3558 /* If there is any thing in data position pull it in */
3559 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3560 if (buf_len == 0)
e90dd264 3561 return 0;
9612de92
ET		 3562
3563 if (length < (buf_len + hdr_size)) {
3564 hw_dbg(hw, "Buffer not large enough for reply message.\n");
e90dd264 3565 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
9612de92
ET		 3566 }
3567
331bcf45
ET		 3568 /* Calculate length in DWORDs, add 3 for odd lengths */
3569 dword_len = (buf_len + 3) >> 2;
9612de92 3570
331bcf45
ET		 3571 /* Pull in the rest of the buffer (bi is where we left off)*/
3572 for (; bi <= dword_len; bi++) {
3573 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3574 le32_to_cpus(&buffer[bi]);
3575 }
9612de92 3576
e90dd264 3577 return 0;
9612de92
ET		 3578}
3579
3580/**
3581 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3582 * @hw: pointer to the HW structure
3583 * @maj: driver version major number
3584 * @min: driver version minor number
3585 * @build: driver version build number
3586 * @sub: driver version sub build number
3587 *
3588 * Sends driver version number to firmware through the manageability
3589 * block. On success return 0
3590 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3591 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3592 **/
3593s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3594 u8 build, u8 sub)
3595{
3596 struct ixgbe_hic_drv_info fw_cmd;
3597 int i;
e90dd264 3598 s32 ret_val;
9612de92 3599
e90dd264
MR		 3600 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM))
3601 return IXGBE_ERR_SWFW_SYNC;
9612de92
ET		 3602
3603 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3604 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3605 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3606 fw_cmd.port_num = (u8)hw->bus.func;
3607 fw_cmd.ver_maj = maj;
3608 fw_cmd.ver_min = min;
3609 fw_cmd.ver_build = build;
3610 fw_cmd.ver_sub = sub;
3611 fw_cmd.hdr.checksum = 0;
3612 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3613 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3614 fw_cmd.pad = 0;
3615 fw_cmd.pad2 = 0;
3616
3617 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
79488c58 3618 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
b48e4aa3
DS		 3619 sizeof(fw_cmd),
3620 IXGBE_HI_COMMAND_TIMEOUT,
3621 true);
9612de92
ET		 3622 if (ret_val != 0)
3623 continue;
3624
3625 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3626 FW_CEM_RESP_STATUS_SUCCESS)
3627 ret_val = 0;
3628 else
3629 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3630
3631 break;
3632 }
3633
3634 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
9612de92
ET		 3635 return ret_val;
3636}
ff9d1a5a
ET		 3637
3638/**
3639 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3640 * @hw: pointer to the hardware structure
3641 *
3642 * The 82599 and x540 MACs can experience issues if TX work is still pending
3643 * when a reset occurs. This function prevents this by flushing the PCIe
3644 * buffers on the system.
3645 **/
3646void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3647{
71bde601
DS		 3648 u32 gcr_ext, hlreg0, i, poll;
3649 u16 value;
ff9d1a5a
ET		 3650
3651 /*
3652 * If double reset is not requested then all transactions should
3653 * already be clear and as such there is no work to do
3654 */
3655 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3656 return;
3657
3658 /*
3659 * Set loopback enable to prevent any transmits from being sent
3660 * should the link come up. This assumes that the RXCTRL.RXEN bit
3661 * has already been cleared.
3662 */
3663 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3664 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3665
71bde601
DS		 3666 /* wait for a last completion before clearing buffers */
3667 IXGBE_WRITE_FLUSH(hw);
3668 usleep_range(3000, 6000);
3669
3670 /* Before proceeding, make sure that the PCIe block does not have
3671 * transactions pending.
3672 */
3673 poll = ixgbe_pcie_timeout_poll(hw);
3674 for (i = 0; i < poll; i++) {
3675 usleep_range(100, 200);
3676 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3677 if (ixgbe_removed(hw->hw_addr))
3678 break;
3679 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3680 break;
3681 }
3682
ff9d1a5a
ET		 3683 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3684 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3685 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3686 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3687
3688 /* Flush all writes and allow 20usec for all transactions to clear */
3689 IXGBE_WRITE_FLUSH(hw);
3690 udelay(20);
3691
3692 /* restore previous register values */
3693 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3694 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3695}
e1ea9158
DS		 3696
3697static const u8 ixgbe_emc_temp_data[4] = {
3698 IXGBE_EMC_INTERNAL_DATA,
3699 IXGBE_EMC_DIODE1_DATA,
3700 IXGBE_EMC_DIODE2_DATA,
3701 IXGBE_EMC_DIODE3_DATA
3702};
3703static const u8 ixgbe_emc_therm_limit[4] = {
3704 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3705 IXGBE_EMC_DIODE1_THERM_LIMIT,
3706 IXGBE_EMC_DIODE2_THERM_LIMIT,
3707 IXGBE_EMC_DIODE3_THERM_LIMIT
3708};
3709
3710/**
3711 * ixgbe_get_ets_data - Extracts the ETS bit data
3712 * @hw: pointer to hardware structure
3713 * @ets_cfg: extected ETS data
3714 * @ets_offset: offset of ETS data
3715 *
3716 * Returns error code.
3717 **/
3718static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3719 u16 *ets_offset)
3720{
e90dd264 3721 s32 status;
e1ea9158
DS		 3722
3723 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3724 if (status)
e90dd264 3725 return status;
e1ea9158 3726
e90dd264
MR		 3727 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3728 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3729
3730 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3731 if (status)
e90dd264 3732 return status;
e1ea9158 3733
e90dd264
MR		 3734 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3735 return IXGBE_NOT_IMPLEMENTED;
e1ea9158 3736
e90dd264 3737 return 0;
e1ea9158
DS		 3738}
3739
3740/**
3741 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3742 * @hw: pointer to hardware structure
3743 *
3744 * Returns the thermal sensor data structure
3745 **/
3746s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3747{
e90dd264 3748 s32 status;
e1ea9158
DS		 3749 u16 ets_offset;
3750 u16 ets_cfg;
3751 u16 ets_sensor;
3752 u8 num_sensors;
3753 u8 i;
3754 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3755
3ca8bc6d 3756 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3757 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3758 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3759
3760 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3761 if (status)
e90dd264 3762 return status;
e1ea9158
DS		 3763
3764 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3765 if (num_sensors > IXGBE_MAX_SENSORS)
3766 num_sensors = IXGBE_MAX_SENSORS;
3767
3768 for (i = 0; i < num_sensors; i++) {
3769 u8 sensor_index;
3770 u8 sensor_location;
3771
3772 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3773 &ets_sensor);
3774 if (status)
e90dd264 3775 return status;
e1ea9158
DS		 3776
3777 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3778 IXGBE_ETS_DATA_INDEX_SHIFT);
3779 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3780 IXGBE_ETS_DATA_LOC_SHIFT);
3781
3782 if (sensor_location != 0) {
3783 status = hw->phy.ops.read_i2c_byte(hw,
3784 ixgbe_emc_temp_data[sensor_index],
3785 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3786 &data->sensor[i].temp);
3787 if (status)
e90dd264 3788 return status;
e1ea9158
DS		 3789 }
3790 }
e90dd264
MR		 3791
3792 return 0;
e1ea9158
DS		 3793}
3794
3795/**
3796 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3797 * @hw: pointer to hardware structure
3798 *
3799 * Inits the thermal sensor thresholds according to the NVM map
3800 * and save off the threshold and location values into mac.thermal_sensor_data
3801 **/
3802s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3803{
e90dd264 3804 s32 status;
e1ea9158
DS		 3805 u16 ets_offset;
3806 u16 ets_cfg;
3807 u16 ets_sensor;
3808 u8 low_thresh_delta;
3809 u8 num_sensors;
3810 u8 therm_limit;
3811 u8 i;
3812 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3813
3814 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3815
3ca8bc6d 3816 /* Only support thermal sensors attached to physical port 0 */
e90dd264
MR		 3817 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3818 return IXGBE_NOT_IMPLEMENTED;
e1ea9158
DS		 3819
3820 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3821 if (status)
e90dd264 3822 return status;
e1ea9158
DS		 3823
3824 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3825 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3826 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3827 if (num_sensors > IXGBE_MAX_SENSORS)
3828 num_sensors = IXGBE_MAX_SENSORS;
3829
3830 for (i = 0; i < num_sensors; i++) {
3831 u8 sensor_index;
3832 u8 sensor_location;
3833
be0c27b4
MR		 3834 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3835 hw_err(hw, "eeprom read at offset %d failed\n",
3836 ets_offset + 1 + i);
3837 continue;
3838 }
e1ea9158
DS		 3839 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3840 IXGBE_ETS_DATA_INDEX_SHIFT);
3841 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3842 IXGBE_ETS_DATA_LOC_SHIFT);
3843 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3844
3845 hw->phy.ops.write_i2c_byte(hw,
3846 ixgbe_emc_therm_limit[sensor_index],
3847 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3848
3849 if (sensor_location == 0)
3850 continue;
3851
3852 data->sensor[i].location = sensor_location;
3853 data->sensor[i].caution_thresh = therm_limit;
3854 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3855 }
e90dd264
MR		 3856
3857 return 0;
e1ea9158
DS		 3858}
3859
1f9ac57c
DS		 3860void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
3861{
3862 u32 rxctrl;
3863
3864 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3865 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3866 if (hw->mac.type != ixgbe_mac_82598EB) {
3867 u32 pfdtxgswc;
3868
3869 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3870 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3871 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3872 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3873 hw->mac.set_lben = true;
3874 } else {
3875 hw->mac.set_lben = false;
3876 }
3877 }
3878 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3879 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3880 }
3881}
3882
3883void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
3884{
3885 u32 rxctrl;
3886
3887 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3888 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
3889
3890 if (hw->mac.type != ixgbe_mac_82598EB) {
3891 if (hw->mac.set_lben) {
3892 u32 pfdtxgswc;
3893
3894 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3895 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
3896 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3897 hw->mac.set_lben = false;
3898 }
3899 }
3900}
Linux kernel - Deliverables
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