[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_dcb.c

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2012 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/


#include "ixgbe.h"
#include "ixgbe_type.h"
#include "ixgbe_dcb.h"
#include "ixgbe_dcb_82598.h"
#include "ixgbe_dcb_82599.h"

/**
 * ixgbe_ieee_credits - This calculates the ieee traffic class
 * credits from the configured bandwidth percentages. Credits
 * are the smallest unit programmable into the underlying
 * hardware. The IEEE 802.1Qaz specification do not use bandwidth
 * groups so this is much simplified from the CEE case.
 */
static s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill,
			      __u16 *max, int max_frame)
{
	int min_percent = 100;
	int min_credit, multiplier;
	int i;

	min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
			DCB_CREDIT_QUANTUM;

	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		if (bw[i] < min_percent && bw[i])
			min_percent = bw[i];
	}

	multiplier = (min_credit / min_percent) + 1;

	/* Find out the hw credits for each TC */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL);

		if (val < min_credit)
			val = min_credit;
		refill[i] = val;

		max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit;
	}
	return 0;
}

/**
 * ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits
 * @ixgbe_dcb_config: Struct containing DCB settings.
 * @direction: Configuring either Tx or Rx.
 *
 * This function calculates the credits allocated to each traffic class.
 * It should be called only after the rules are checked by
 * ixgbe_dcb_check_config().
 */
s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *hw,
				   struct ixgbe_dcb_config *dcb_config,
				   int max_frame, u8 direction)
{
	struct tc_bw_alloc *p;
	int min_credit;
	int min_multiplier;
	int min_percent = 100;
	s32 ret_val = 0;
	/* Initialization values default for Tx settings */
	u32 credit_refill       = 0;
	u32 credit_max          = 0;
	u16 link_percentage     = 0;
	u8  bw_percent          = 0;
	u8  i;

	if (dcb_config == NULL) {
		ret_val = DCB_ERR_CONFIG;
		goto out;
	}

	min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
			DCB_CREDIT_QUANTUM;

	/* Find smallest link percentage */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		p = &dcb_config->tc_config[i].path[direction];
		bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
		link_percentage = p->bwg_percent;

		link_percentage = (link_percentage * bw_percent) / 100;

		if (link_percentage && link_percentage < min_percent)
			min_percent = link_percentage;
	}

	/*
	 * The ratio between traffic classes will control the bandwidth
	 * percentages seen on the wire. To calculate this ratio we use
	 * a multiplier. It is required that the refill credits must be
	 * larger than the max frame size so here we find the smallest
	 * multiplier that will allow all bandwidth percentages to be
	 * greater than the max frame size.
	 */
	min_multiplier = (min_credit / min_percent) + 1;

	/* Find out the link percentage for each TC first */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		p = &dcb_config->tc_config[i].path[direction];
		bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];

		link_percentage = p->bwg_percent;
		/* Must be careful of integer division for very small nums */
		link_percentage = (link_percentage * bw_percent) / 100;
		if (p->bwg_percent > 0 && link_percentage == 0)
			link_percentage = 1;

		/* Save link_percentage for reference */
		p->link_percent = (u8)link_percentage;

		/* Calculate credit refill ratio using multiplier */
		credit_refill = min(link_percentage * min_multiplier,
				    MAX_CREDIT_REFILL);
		p->data_credits_refill = (u16)credit_refill;

		/* Calculate maximum credit for the TC */
		credit_max = (link_percentage * MAX_CREDIT) / 100;

		/*
		 * Adjustment based on rule checking, if the percentage
		 * of a TC is too small, the maximum credit may not be
		 * enough to send out a jumbo frame in data plane arbitration.
		 */
		if (credit_max && (credit_max < min_credit))
			credit_max = min_credit;

		if (direction == DCB_TX_CONFIG) {
			/*
			 * Adjustment based on rule checking, if the
			 * percentage of a TC is too small, the maximum
			 * credit may not be enough to send out a TSO
			 * packet in descriptor plane arbitration.
			 */
			if ((hw->mac.type == ixgbe_mac_82598EB) &&
			    credit_max &&
			    (credit_max < MINIMUM_CREDIT_FOR_TSO))
				credit_max = MINIMUM_CREDIT_FOR_TSO;

			dcb_config->tc_config[i].desc_credits_max =
				(u16)credit_max;
		}

		p->data_credits_max = (u16)credit_max;
	}

out:
	return ret_val;
}

void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en)
{
	struct tc_configuration *tc_config = &cfg->tc_config[0];
	int tc;

	for (*pfc_en = 0, tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) {
		if (tc_config[tc].dcb_pfc != pfc_disabled)
			*pfc_en |= 1 << tc;
	}
}

void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *cfg, int direction,
			     u16 *refill)
{
	struct tc_configuration *tc_config = &cfg->tc_config[0];
	int tc;

	for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
		refill[tc] = tc_config[tc].path[direction].data_credits_refill;
}

void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *cfg, u16 *max)
{
	struct tc_configuration *tc_config = &cfg->tc_config[0];
	int tc;

	for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
		max[tc] = tc_config[tc].desc_credits_max;
}

void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *cfg, int direction,
			    u8 *bwgid)
{
	struct tc_configuration *tc_config = &cfg->tc_config[0];
	int tc;

	for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
		bwgid[tc] = tc_config[tc].path[direction].bwg_id;
}

void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction,
			    u8 *ptype)
{
	struct tc_configuration *tc_config = &cfg->tc_config[0];
	int tc;

	for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
		ptype[tc] = tc_config[tc].path[direction].prio_type;
}

u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
{
	struct tc_configuration *tc_config = &cfg->tc_config[0];
	u8 prio_mask = 1 << up;
	u8 tc;

	/*
	 * Test for TCs 7 through 1 and report the first match we find.  If
	 * we find no match we can assume that the TC is 0 since the TC must
	 * be set for all user priorities
	 */
	for (tc = MAX_TRAFFIC_CLASS - 1; tc; tc--) {
		if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
			break;
	}

	return tc;
}

void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *cfg, int direction, u8 *map)
{
	u8 up;

	for (up = 0; up < MAX_USER_PRIORITY; up++)
		map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
}

/**
 * ixgbe_dcb_hw_config - Config and enable DCB
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure dcb settings and enable dcb mode.
 */
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
                        struct ixgbe_dcb_config *dcb_config)
{
	s32 ret = 0;
	u8 pfc_en;
	u8 ptype[MAX_TRAFFIC_CLASS];
	u8 bwgid[MAX_TRAFFIC_CLASS];
	u8 prio_tc[MAX_TRAFFIC_CLASS];
	u16 refill[MAX_TRAFFIC_CLASS];
	u16 max[MAX_TRAFFIC_CLASS];

	/* Unpack CEE standard containers */
	ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en);
	ixgbe_dcb_unpack_refill(dcb_config, DCB_TX_CONFIG, refill);
	ixgbe_dcb_unpack_max(dcb_config, max);
	ixgbe_dcb_unpack_bwgid(dcb_config, DCB_TX_CONFIG, bwgid);
	ixgbe_dcb_unpack_prio(dcb_config, DCB_TX_CONFIG, ptype);
	ixgbe_dcb_unpack_map(dcb_config, DCB_TX_CONFIG, prio_tc);

	switch (hw->mac.type) {
	case ixgbe_mac_82598EB:
		ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,
						bwgid, ptype);
		break;
	case ixgbe_mac_82599EB:
	case ixgbe_mac_X540:
		ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
						bwgid, ptype, prio_tc);
		break;
	default:
		break;
	}
	return ret;
}

/* Helper routines to abstract HW specifics from DCB netlink ops */
s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
{
	int ret = -EINVAL;

	switch (hw->mac.type) {
	case ixgbe_mac_82598EB:
		ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
		break;
	case ixgbe_mac_82599EB:
	case ixgbe_mac_X540:
		ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
		break;
	default:
		break;
	}
	return ret;
}

s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame)
{
	__u16 refill[IEEE_8021QAZ_MAX_TCS], max[IEEE_8021QAZ_MAX_TCS];
	__u8 prio_type[IEEE_8021QAZ_MAX_TCS];
	int i;

	/* naively give each TC a bwg to map onto CEE hardware */
	__u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7};

	/* Map TSA onto CEE prio type */
	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
		switch (ets->tc_tsa[i]) {
		case IEEE_8021QAZ_TSA_STRICT:
			prio_type[i] = 2;
			break;
		case IEEE_8021QAZ_TSA_ETS:
			prio_type[i] = 0;
			break;
		default:
			/* Hardware only supports priority strict or
			 * ETS transmission selection algorithms if
			 * we receive some other value from dcbnl
			 * throw an error
			 */
			return -EINVAL;
		}
	}

	ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame);
	return ixgbe_dcb_hw_ets_config(hw, refill, max,
				       bwg_id, prio_type, ets->prio_tc);
}

s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
			    u16 *refill, u16 *max, u8 *bwg_id,
			    u8 *prio_type, u8 *prio_tc)
{
	switch (hw->mac.type) {
	case ixgbe_mac_82598EB:
		ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max,
							prio_type);
		ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
							     bwg_id, prio_type);
		ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
							     bwg_id, prio_type);
		break;
	case ixgbe_mac_82599EB:
	case ixgbe_mac_X540:
		ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
						  bwg_id, prio_type, prio_tc);
		ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
						       bwg_id, prio_type);
		ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
						       prio_type, prio_tc);
		break;
	default:
		break;
	}
	return 0;
}
Commit	Line	Data
2f90b865 AD	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
94971820	4	Copyright(c) 1999 - 2012 Intel Corporation.
2f90b865 AD	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	Linux NICS <linux.nics@intel.com>
	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26
	27	*******************************************************************************/
	28
	29
	30	#include "ixgbe.h"
	31	#include "ixgbe_type.h"
	32	#include "ixgbe_dcb.h"
	33	#include "ixgbe_dcb_82598.h"
235ea828	34	#include "ixgbe_dcb_82599.h"
2f90b865	35
d033d526 JF	36	/**
	37	* ixgbe_ieee_credits - This calculates the ieee traffic class
	38	* credits from the configured bandwidth percentages. Credits
25985edc	39	* are the smallest unit programmable into the underlying
d033d526 JF	40	* hardware. The IEEE 802.1Qaz specification do not use bandwidth
	41	* groups so this is much simplified from the CEE case.
	42	*/
4c09f3a0 JF	43	static s32 ixgbe_ieee_credits(__u8 bw, __u16 refill,
4c09f3a0 JF	44	__u16 *max, int max_frame)
d033d526 JF	45	{
	46	int min_percent = 100;
	47	int min_credit, multiplier;
	48	int i;
	49
	50	min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
	51	DCB_CREDIT_QUANTUM;
	52
	53	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
	54	if (bw[i] < min_percent && bw[i])
	55	min_percent = bw[i];
	56	}
	57
	58	multiplier = (min_credit / min_percent) + 1;
	59
	60	/* Find out the hw credits for each TC */
	61	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
	62	int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL);
	63
	64	if (val < min_credit)
	65	val = min_credit;
	66	refill[i] = val;
	67
1390a594	68	max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit;
d033d526 JF	69	}
	70	return 0;
	71	}
	72
2f90b865 AD	73	/**
	74	* ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits
	75	* @ixgbe_dcb_config: Struct containing DCB settings.
	76	* @direction: Configuring either Tx or Rx.
	77	*
	78	* This function calculates the credits allocated to each traffic class.
	79	* It should be called only after the rules are checked by
	80	* ixgbe_dcb_check_config().
	81	*/
80ab193d JF	82	s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *hw,
80ab193d JF	83	struct ixgbe_dcb_config *dcb_config,
9806307a	84	int max_frame, u8 direction)
2f90b865 AD	85	{
2f90b865 AD	86	struct tc_bw_alloc *p;
9806307a JF	87	int min_credit;
	88	int min_multiplier;
	89	int min_percent = 100;
2f90b865 AD	90	s32 ret_val = 0;
	91	/* Initialization values default for Tx settings */
	92	u32 credit_refill = 0;
	93	u32 credit_max = 0;
	94	u16 link_percentage = 0;
	95	u8 bw_percent = 0;
	96	u8 i;
	97
	98	if (dcb_config == NULL) {
	99	ret_val = DCB_ERR_CONFIG;
	100	goto out;
	101	}
	102
9806307a JF	103	min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
	104	DCB_CREDIT_QUANTUM;
	105
	106	/* Find smallest link percentage */
	107	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
	108	p = &dcb_config->tc_config[i].path[direction];
	109	bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
	110	link_percentage = p->bwg_percent;
	111
	112	link_percentage = (link_percentage * bw_percent) / 100;
	113
	114	if (link_percentage && link_percentage < min_percent)
	115	min_percent = link_percentage;
	116	}
	117
	118	/*
	119	* The ratio between traffic classes will control the bandwidth
	120	* percentages seen on the wire. To calculate this ratio we use
	121	* a multiplier. It is required that the refill credits must be
	122	* larger than the max frame size so here we find the smallest
	123	* multiplier that will allow all bandwidth percentages to be
	124	* greater than the max frame size.
	125	*/
	126	min_multiplier = (min_credit / min_percent) + 1;
	127
2f90b865 AD	128	/* Find out the link percentage for each TC first */
	129	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
	130	p = &dcb_config->tc_config[i].path[direction];
	131	bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
	132
	133	link_percentage = p->bwg_percent;
	134	/* Must be careful of integer division for very small nums */
	135	link_percentage = (link_percentage * bw_percent) / 100;
	136	if (p->bwg_percent > 0 && link_percentage == 0)
	137	link_percentage = 1;
	138
	139	/* Save link_percentage for reference */
	140	p->link_percent = (u8)link_percentage;
	141
9806307a JF	142	/* Calculate credit refill ratio using multiplier */
	143	credit_refill = min(link_percentage * min_multiplier,
	144	MAX_CREDIT_REFILL);
2f90b865 AD	145	p->data_credits_refill = (u16)credit_refill;
	146
	147	/* Calculate maximum credit for the TC */
	148	credit_max = (link_percentage * MAX_CREDIT) / 100;
	149
	150	/*
	151	* Adjustment based on rule checking, if the percentage
	152	* of a TC is too small, the maximum credit may not be
	153	* enough to send out a jumbo frame in data plane arbitration.
	154	*/
9806307a JF	155	if (credit_max && (credit_max < min_credit))
9806307a JF	156	credit_max = min_credit;
2f90b865 AD	157
	158	if (direction == DCB_TX_CONFIG) {
	159	/*
	160	* Adjustment based on rule checking, if the
	161	* percentage of a TC is too small, the maximum
	162	* credit may not be enough to send out a TSO
	163	* packet in descriptor plane arbitration.
	164	*/
80ab193d JF	165	if ((hw->mac.type == ixgbe_mac_82598EB) &&
80ab193d JF	166	credit_max &&
2f90b865 AD	167	(credit_max < MINIMUM_CREDIT_FOR_TSO))
	168	credit_max = MINIMUM_CREDIT_FOR_TSO;
	169
	170	dcb_config->tc_config[i].desc_credits_max =
	171	(u16)credit_max;
	172	}
	173
	174	p->data_credits_max = (u16)credit_max;
	175	}
	176
	177	out:
	178	return ret_val;
	179	}
	180
55320cb5 JF	181	void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config cfg, u8 pfc_en)
55320cb5 JF	182	{
df0676d1 AD	183	struct tc_configuration *tc_config = &cfg->tc_config[0];
df0676d1 AD	184	int tc;
55320cb5	185
df0676d1 AD	186	for (*pfc_en = 0, tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) {
	187	if (tc_config[tc].dcb_pfc != pfc_disabled)
	188	*pfc_en \|= 1 << tc;
	189	}
55320cb5 JF	190	}
	191
	192	void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *cfg, int direction,
	193	u16 *refill)
	194	{
df0676d1 AD	195	struct tc_configuration *tc_config = &cfg->tc_config[0];
df0676d1 AD	196	int tc;
55320cb5	197
df0676d1 AD	198	for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
df0676d1 AD	199	refill[tc] = tc_config[tc].path[direction].data_credits_refill;
55320cb5 JF	200	}
	201
	202	void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config cfg, u16 max)
	203	{
df0676d1 AD	204	struct tc_configuration *tc_config = &cfg->tc_config[0];
df0676d1 AD	205	int tc;
55320cb5	206
df0676d1 AD	207	for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
df0676d1 AD	208	max[tc] = tc_config[tc].desc_credits_max;
55320cb5 JF	209	}
	210
	211	void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *cfg, int direction,
	212	u8 *bwgid)
	213	{
df0676d1 AD	214	struct tc_configuration *tc_config = &cfg->tc_config[0];
df0676d1 AD	215	int tc;
55320cb5	216
df0676d1 AD	217	for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
df0676d1 AD	218	bwgid[tc] = tc_config[tc].path[direction].bwg_id;
55320cb5 JF	219	}
	220
	221	void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction,
	222	u8 *ptype)
	223	{
df0676d1 AD	224	struct tc_configuration *tc_config = &cfg->tc_config[0];
df0676d1 AD	225	int tc;
55320cb5	226
df0676d1 AD	227	for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
df0676d1 AD	228	ptype[tc] = tc_config[tc].path[direction].prio_type;
55320cb5 JF	229	}
55320cb5 JF	230
02debdc9	231	u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
32701dc2	232	{
15cbc70e AD	233	struct tc_configuration *tc_config = &cfg->tc_config[0];
	234	u8 prio_mask = 1 << up;
	235	u8 tc;
32701dc2	236
15cbc70e AD	237	/*
	238	* Test for TCs 7 through 1 and report the first match we find. If
	239	* we find no match we can assume that the TC is 0 since the TC must
	240	* be set for all user priorities
	241	*/
	242	for (tc = MAX_TRAFFIC_CLASS - 1; tc; tc--) {
	243	if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
	244	break;
32701dc2	245	}
15cbc70e AD	246
	247	return tc;
	248	}
	249
	250	void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config cfg, int direction, u8 map)
	251	{
	252	u8 up;
	253
	254	for (up = 0; up < MAX_USER_PRIORITY; up++)
	255	map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
32701dc2 JF	256	}
32701dc2 JF	257
2f90b865 AD	258	/**
	259	* ixgbe_dcb_hw_config - Config and enable DCB
	260	* @hw: pointer to hardware structure
	261	* @dcb_config: pointer to ixgbe_dcb_config structure
	262	*
	263	* Configure dcb settings and enable dcb mode.
	264	*/
	265	s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
	266	struct ixgbe_dcb_config *dcb_config)
	267	{
	268	s32 ret = 0;
55320cb5 JF	269	u8 pfc_en;
	270	u8 ptype[MAX_TRAFFIC_CLASS];
	271	u8 bwgid[MAX_TRAFFIC_CLASS];
32701dc2	272	u8 prio_tc[MAX_TRAFFIC_CLASS];
55320cb5 JF	273	u16 refill[MAX_TRAFFIC_CLASS];
	274	u16 max[MAX_TRAFFIC_CLASS];
	275
	276	/* Unpack CEE standard containers */
	277	ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en);
	278	ixgbe_dcb_unpack_refill(dcb_config, DCB_TX_CONFIG, refill);
	279	ixgbe_dcb_unpack_max(dcb_config, max);
	280	ixgbe_dcb_unpack_bwgid(dcb_config, DCB_TX_CONFIG, bwgid);
	281	ixgbe_dcb_unpack_prio(dcb_config, DCB_TX_CONFIG, ptype);
32701dc2	282	ixgbe_dcb_unpack_map(dcb_config, DCB_TX_CONFIG, prio_tc);
55320cb5	283
b93a2226 DS	284	switch (hw->mac.type) {
b93a2226 DS	285	case ixgbe_mac_82598EB:
80605c65 JF	286	ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,
80605c65 JF	287	bwgid, ptype);
b93a2226 DS	288	break;
	289	case ixgbe_mac_82599EB:
	290	case ixgbe_mac_X540:
80605c65 JF	291	ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
80605c65 JF	292	bwgid, ptype, prio_tc);
b93a2226 DS	293	break;
	294	default:
	295	break;
	296	}
2f90b865 AD	297	return ret;
	298	}
	299
d033d526	300	/* Helper routines to abstract HW specifics from DCB netlink ops */
32701dc2	301	s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw hw, u8 pfc_en, u8 prio_tc)
d033d526 JF	302	{
	303	int ret = -EINVAL;
	304
	305	switch (hw->mac.type) {
	306	case ixgbe_mac_82598EB:
	307	ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
	308	break;
	309	case ixgbe_mac_82599EB:
	310	case ixgbe_mac_X540:
32701dc2	311	ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
d033d526 JF	312	break;
	313	default:
	314	break;
	315	}
	316	return ret;
	317	}
	318
4c09f3a0 JF	319	s32 ixgbe_dcb_hw_ets(struct ixgbe_hw hw, struct ieee_ets ets, int max_frame)
	320	{
	321	__u16 refill[IEEE_8021QAZ_MAX_TCS], max[IEEE_8021QAZ_MAX_TCS];
	322	__u8 prio_type[IEEE_8021QAZ_MAX_TCS];
	323	int i;
	324
	325	/* naively give each TC a bwg to map onto CEE hardware */
	326	__u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7};
	327
	328	/* Map TSA onto CEE prio type */
	329	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
	330	switch (ets->tc_tsa[i]) {
	331	case IEEE_8021QAZ_TSA_STRICT:
	332	prio_type[i] = 2;
	333	break;
	334	case IEEE_8021QAZ_TSA_ETS:
	335	prio_type[i] = 0;
	336	break;
	337	default:
	338	/* Hardware only supports priority strict or
	339	* ETS transmission selection algorithms if
	340	* we receive some other value from dcbnl
	341	* throw an error
	342	*/
	343	return -EINVAL;
	344	}
	345	}
	346
	347	ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame);
	348	return ixgbe_dcb_hw_ets_config(hw, refill, max,
	349	bwg_id, prio_type, ets->prio_tc);
	350	}
	351
d033d526	352	s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
17049d30 JF	353	u16 refill, u16 max, u8 *bwg_id,
17049d30 JF	354	u8 prio_type, u8 prio_tc)
d033d526	355	{
d033d526 JF	356	switch (hw->mac.type) {
	357	case ixgbe_mac_82598EB:
	358	ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max,
	359	prio_type);
	360	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
	361	bwg_id, prio_type);
	362	ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
	363	bwg_id, prio_type);
	364	break;
	365	case ixgbe_mac_82599EB:
	366	case ixgbe_mac_X540:
	367	ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
17049d30	368	bwg_id, prio_type, prio_tc);
d033d526 JF	369	ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
d033d526 JF	370	bwg_id, prio_type);
17049d30 JF	371	ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
17049d30 JF	372	prio_type, prio_tc);
d033d526 JF	373	break;
	374	default:
	375	break;
	376	}
	377	return 0;
	378	}