[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_dcb_82598.c

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2012 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include "ixgbe.h"
#include "ixgbe_type.h"
#include "ixgbe_dcb.h"
#include "ixgbe_dcb_82598.h"

/**
 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure Rx Data Arbiter and credits for each traffic class.
 */
s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
					u16 *refill,
					u16 *max,
					u8 *prio_type)
{
	u32    reg           = 0;
	u32    credit_refill = 0;
	u32    credit_max    = 0;
	u8     i             = 0;

	reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
	IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);

	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
	/* Enable Arbiter */
	reg &= ~IXGBE_RMCS_ARBDIS;
	/* Enable Receive Recycle within the BWG */
	reg |= IXGBE_RMCS_RRM;
	/* Enable Deficit Fixed Priority arbitration*/
	reg |= IXGBE_RMCS_DFP;

	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		credit_refill = refill[i];
		credit_max    = max[i];

		reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);

		if (prio_type[i] == prio_link)
			reg |= IXGBE_RT2CR_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
	}

	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
	reg |= IXGBE_RDRXCTL_RDMTS_1_2;
	reg |= IXGBE_RDRXCTL_MPBEN;
	reg |= IXGBE_RDRXCTL_MCEN;
	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);

	reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
	/* Make sure there is enough descriptors before arbitration */
	reg &= ~IXGBE_RXCTRL_DMBYPS;
	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);

	return 0;
}

/**
 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure Tx Descriptor Arbiter and credits for each traffic class.
 */
s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
						u16 *refill,
						u16 *max,
						u8 *bwg_id,
						u8 *prio_type)
{
	u32    reg, max_credits;
	u8     i;

	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);

	/* Enable arbiter */
	reg &= ~IXGBE_DPMCS_ARBDIS;
	/* Enable DFP and Recycle mode */
	reg |= (IXGBE_DPMCS_TDPAC | IXGBE_DPMCS_TRM);
	reg |= IXGBE_DPMCS_TSOEF;
	/* Configure Max TSO packet size 34KB including payload and headers */
	reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);

	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		max_credits = max[i];
		reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
		reg |= refill[i];
		reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;

		if (prio_type[i] == prio_group)
			reg |= IXGBE_TDTQ2TCCR_GSP;

		if (prio_type[i] == prio_link)
			reg |= IXGBE_TDTQ2TCCR_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
	}

	return 0;
}

/**
 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure Tx Data Arbiter and credits for each traffic class.
 */
s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
						u16 *refill,
						u16 *max,
						u8 *bwg_id,
						u8 *prio_type)
{
	u32 reg;
	u8 i;

	reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
	/* Enable Data Plane Arbiter */
	reg &= ~IXGBE_PDPMCS_ARBDIS;
	/* Enable DFP and Transmit Recycle Mode */
	reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);

	IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		reg = refill[i];
		reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
		reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;

		if (prio_type[i] == prio_group)
			reg |= IXGBE_TDPT2TCCR_GSP;

		if (prio_type[i] == prio_link)
			reg |= IXGBE_TDPT2TCCR_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
	}

	/* Enable Tx packet buffer division */
	reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
	reg |= IXGBE_DTXCTL_ENDBUBD;
	IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);

	return 0;
}

/**
 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure Priority Flow Control for each traffic class.
 */
s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
{
	u32 fcrtl, reg;
	u8  i;

	/* Enable Transmit Priority Flow Control */
	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
	reg &= ~IXGBE_RMCS_TFCE_802_3X;
	reg |= IXGBE_RMCS_TFCE_PRIORITY;
	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);

	/* Enable Receive Priority Flow Control */
	reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
	reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);

	if (pfc_en)
		reg |= IXGBE_FCTRL_RPFCE;

	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);

	fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;
	/* Configure PFC Tx thresholds per TC */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		if (!(pfc_en & (1 << i))) {
			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
			continue;
		}

		reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
		IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
	}

	/* Configure pause time */
	reg = hw->fc.pause_time * 0x00010001;
	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

	/* Configure flow control refresh threshold value */
	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);


	return 0;
}

/**
 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
 * @hw: pointer to hardware structure
 *
 * Configure queue statistics registers, all queues belonging to same traffic
 * class uses a single set of queue statistics counters.
 */
static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
{
	u32 reg = 0;
	u8  i   = 0;
	u8  j   = 0;

	/* Receive Queues stats setting -  8 queues per statistics reg */
	for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
		reg |= ((0x1010101) * j);
		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
		reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
		reg |= ((0x1010101) * j);
		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
	}
	/* Transmit Queues stats setting -  4 queues per statistics reg */
	for (i = 0; i < 8; i++) {
		reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
		reg |= ((0x1010101) * i);
		IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
	}

	return 0;
}

/**
 * ixgbe_dcb_hw_config_82598 - Config and enable DCB
 * @hw: pointer to hardware structure
 * @dcb_config: pointer to ixgbe_dcb_config structure
 *
 * Configure dcb settings and enable dcb mode.
 */
s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
			      u16 *max, u8 *bwg_id, u8 *prio_type)
{
	ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
					       bwg_id, prio_type);
	ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
					       bwg_id, prio_type);
	ixgbe_dcb_config_pfc_82598(hw, pfc_en);
	ixgbe_dcb_config_tc_stats_82598(hw);

	return 0;
}
Commit	Line	Data
2f90b865 AD	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
94971820	4	Copyright(c) 1999 - 2012 Intel Corporation.
2f90b865 AD	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	Linux NICS <linux.nics@intel.com>
	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26
	27	*******************************************************************************/
	28
	29	#include "ixgbe.h"
	30	#include "ixgbe_type.h"
	31	#include "ixgbe_dcb.h"
	32	#include "ixgbe_dcb_82598.h"
	33
2f90b865 AD	34	/**
	35	* ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
	36	* @hw: pointer to hardware structure
	37	* @dcb_config: pointer to ixgbe_dcb_config structure
	38	*
	39	* Configure Rx Data Arbiter and credits for each traffic class.
	40	*/
55320cb5 JF	41	s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
	42	u16 *refill,
	43	u16 *max,
	44	u8 *prio_type)
2f90b865	45	{
2f90b865 AD	46	u32 reg = 0;
	47	u32 credit_refill = 0;
	48	u32 credit_max = 0;
	49	u8 i = 0;
	50
	51	reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) \| IXGBE_RUPPBMR_MQA;
	52	IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
	53
	54	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
	55	/* Enable Arbiter */
	56	reg &= ~IXGBE_RMCS_ARBDIS;
	57	/* Enable Receive Recycle within the BWG */
	58	reg \|= IXGBE_RMCS_RRM;
	59	/* Enable Deficit Fixed Priority arbitration*/
	60	reg \|= IXGBE_RMCS_DFP;
	61
	62	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
	63
	64	/* Configure traffic class credits and priority */
	65	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
55320cb5 JF	66	credit_refill = refill[i];
55320cb5 JF	67	credit_max = max[i];
2f90b865 AD	68
	69	reg = credit_refill \| (credit_max << IXGBE_RT2CR_MCL_SHIFT);
	70
55320cb5	71	if (prio_type[i] == prio_link)
2f90b865 AD	72	reg \|= IXGBE_RT2CR_LSP;
	73
	74	IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
	75	}
	76
	77	reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
	78	reg \|= IXGBE_RDRXCTL_RDMTS_1_2;
	79	reg \|= IXGBE_RDRXCTL_MPBEN;
	80	reg \|= IXGBE_RDRXCTL_MCEN;
	81	IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
	82
	83	reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
	84	/* Make sure there is enough descriptors before arbitration */
	85	reg &= ~IXGBE_RXCTRL_DMBYPS;
	86	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
	87
	88	return 0;
	89	}
	90
	91	/**
	92	* ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
	93	* @hw: pointer to hardware structure
	94	* @dcb_config: pointer to ixgbe_dcb_config structure
	95	*
	96	* Configure Tx Descriptor Arbiter and credits for each traffic class.
	97	*/
55320cb5 JF	98	s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
	99	u16 *refill,
	100	u16 *max,
	101	u8 *bwg_id,
	102	u8 *prio_type)
2f90b865	103	{
2f90b865 AD	104	u32 reg, max_credits;
	105	u8 i;
	106
	107	reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
	108
	109	/* Enable arbiter */
	110	reg &= ~IXGBE_DPMCS_ARBDIS;
39a7e587 JF	111	/* Enable DFP and Recycle mode */
39a7e587 JF	112	reg \|= (IXGBE_DPMCS_TDPAC \| IXGBE_DPMCS_TRM);
2f90b865 AD	113	reg \|= IXGBE_DPMCS_TSOEF;
	114	/* Configure Max TSO packet size 34KB including payload and headers */
	115	reg \|= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
	116
	117	IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
	118
	119	/* Configure traffic class credits and priority */
	120	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
55320cb5	121	max_credits = max[i];
2f90b865	122	reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
55320cb5 JF	123	reg \|= refill[i];
55320cb5 JF	124	reg \|= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
2f90b865	125
55320cb5	126	if (prio_type[i] == prio_group)
2f90b865 AD	127	reg \|= IXGBE_TDTQ2TCCR_GSP;
2f90b865 AD	128
55320cb5	129	if (prio_type[i] == prio_link)
2f90b865 AD	130	reg \|= IXGBE_TDTQ2TCCR_LSP;
	131
	132	IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
	133	}
	134
	135	return 0;
	136	}
	137
	138	/**
	139	* ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
	140	* @hw: pointer to hardware structure
	141	* @dcb_config: pointer to ixgbe_dcb_config structure
	142	*
	143	* Configure Tx Data Arbiter and credits for each traffic class.
	144	*/
55320cb5 JF	145	s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
	146	u16 *refill,
	147	u16 *max,
	148	u8 *bwg_id,
	149	u8 *prio_type)
2f90b865	150	{
2f90b865 AD	151	u32 reg;
	152	u8 i;
	153
	154	reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
	155	/* Enable Data Plane Arbiter */
	156	reg &= ~IXGBE_PDPMCS_ARBDIS;
	157	/* Enable DFP and Transmit Recycle Mode */
	158	reg \|= (IXGBE_PDPMCS_TPPAC \| IXGBE_PDPMCS_TRM);
	159
	160	IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
	161
	162	/* Configure traffic class credits and priority */
	163	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
55320cb5 JF	164	reg = refill[i];
	165	reg \|= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
	166	reg \|= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
2f90b865	167
55320cb5	168	if (prio_type[i] == prio_group)
2f90b865 AD	169	reg \|= IXGBE_TDPT2TCCR_GSP;
2f90b865 AD	170
55320cb5	171	if (prio_type[i] == prio_link)
2f90b865 AD	172	reg \|= IXGBE_TDPT2TCCR_LSP;
	173
	174	IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
	175	}
	176
	177	/* Enable Tx packet buffer division */
	178	reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
	179	reg \|= IXGBE_DTXCTL_ENDBUBD;
	180	IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
	181
	182	return 0;
	183	}
	184
	185	/**
	186	* ixgbe_dcb_config_pfc_82598 - Config priority flow control
	187	* @hw: pointer to hardware structure
	188	* @dcb_config: pointer to ixgbe_dcb_config structure
	189	*
	190	* Configure Priority Flow Control for each traffic class.
	191	*/
55320cb5	192	s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
2f90b865	193	{
943561d3	194	u32 fcrtl, reg;
2f90b865 AD	195	u8 i;
2f90b865 AD	196
943561d3 AD	197	/* Enable Transmit Priority Flow Control */
	198	reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
	199	reg &= ~IXGBE_RMCS_TFCE_802_3X;
	200	reg \|= IXGBE_RMCS_TFCE_PRIORITY;
	201	IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
1f4a0244	202
943561d3 AD	203	/* Enable Receive Priority Flow Control */
	204	reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
	205	reg &= ~(IXGBE_FCTRL_RPFCE \| IXGBE_FCTRL_RFCE);
2f90b865	206
943561d3 AD	207	if (pfc_en)
943561d3 AD	208	reg \|= IXGBE_FCTRL_RPFCE;
9da712d2	209
943561d3	210	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
2f90b865	211
943561d3 AD	212	fcrtl = (hw->fc.low_water << 10) \| IXGBE_FCRTL_XONE;
	213	/* Configure PFC Tx thresholds per TC */
	214	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
	215	if (!(pfc_en & (1 << i))) {
	216	IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
	217	IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
	218	continue;
	219	}
	220
	221	reg = (hw->fc.high_water[i] << 10) \| IXGBE_FCRTH_FCEN;
	222	IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
	223	IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
	224	}
2f90b865	225
943561d3 AD	226	/* Configure pause time */
	227	reg = hw->fc.pause_time * 0x00010001;
	228	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
	229	IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2f90b865	230
943561d3 AD	231	/* Configure flow control refresh threshold value */
943561d3 AD	232	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2f90b865	233
2f90b865	234
2f90b865 AD	235	return 0;
	236	}
	237
	238	/**
	239	* ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
	240	* @hw: pointer to hardware structure
	241	*
	242	* Configure queue statistics registers, all queues belonging to same traffic
	243	* class uses a single set of queue statistics counters.
	244	*/
b32c8dcc	245	static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
2f90b865 AD	246	{
	247	u32 reg = 0;
	248	u8 i = 0;
	249	u8 j = 0;
	250
	251	/* Receive Queues stats setting - 8 queues per statistics reg */
	252	for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
	253	reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
	254	reg \|= ((0x1010101) * j);
	255	IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
	256	reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
	257	reg \|= ((0x1010101) * j);
	258	IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
	259	}
	260	/* Transmit Queues stats setting - 4 queues per statistics reg */
	261	for (i = 0; i < 8; i++) {
	262	reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
	263	reg \|= ((0x1010101) * i);
	264	IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
	265	}
	266
	267	return 0;
	268	}
	269
	270	/**
	271	* ixgbe_dcb_hw_config_82598 - Config and enable DCB
	272	* @hw: pointer to hardware structure
	273	* @dcb_config: pointer to ixgbe_dcb_config structure
	274	*
	275	* Configure dcb settings and enable dcb mode.
	276	*/
80605c65	277	s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw hw, u8 pfc_en, u16 refill,
55320cb5	278	u16 max, u8 bwg_id, u8 *prio_type)
2f90b865	279	{
55320cb5 JF	280	ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
	281	ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
	282	bwg_id, prio_type);
	283	ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
	284	bwg_id, prio_type);
	285	ixgbe_dcb_config_pfc_82598(hw, pfc_en);
2f90b865 AD	286	ixgbe_dcb_config_tc_stats_82598(hw);
	287
	288	return 0;
	289	}