[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_dcb_82599.c

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2011 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include "ixgbe.h"
#include "ixgbe_type.h"
#include "ixgbe_dcb.h"
#include "ixgbe_dcb_82599.h"

/**
 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
 * @hw: pointer to hardware structure
 * @refill: refill credits index by traffic class
 * @max: max credits index by traffic class
 * @bwg_id: bandwidth grouping indexed by traffic class
 * @prio_type: priority type indexed by traffic class
 *
 * Configure Rx Packet Arbiter and credits for each traffic class.
 */
s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
				      u16 *refill,
				      u16 *max,
				      u8 *bwg_id,
				      u8 *prio_type,
				      u8 *prio_tc)
{
	u32    reg           = 0;
	u32    credit_refill = 0;
	u32    credit_max    = 0;
	u8     i             = 0;

	/*
	 * Disable the arbiter before changing parameters
	 * (always enable recycle mode; WSP)
	 */
	reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);

	/* Map all traffic classes to their UP */
	reg = 0;
	for (i = 0; i < MAX_USER_PRIORITY; i++)
		reg |= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
	IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		credit_refill = refill[i];
		credit_max    = max[i];
		reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);

		reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;

		if (prio_type[i] == prio_link)
			reg |= IXGBE_RTRPT4C_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
	}

	/*
	 * Configure Rx packet plane (recycle mode; WSP) and
	 * enable arbiter
	 */
	reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);

	return 0;
}

/**
 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
 * @hw: pointer to hardware structure
 * @refill: refill credits index by traffic class
 * @max: max credits index by traffic class
 * @bwg_id: bandwidth grouping indexed by traffic class
 * @prio_type: priority type indexed by traffic class
 *
 * Configure Tx Descriptor Arbiter and credits for each traffic class.
 */
s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
					   u16 *refill,
					   u16 *max,
					   u8 *bwg_id,
					   u8 *prio_type)
{
	u32    reg, max_credits;
	u8     i;

	/* Clear the per-Tx queue credits; we use per-TC instead */
	for (i = 0; i < 128; i++) {
		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
		IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
	}

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		max_credits = max[i];
		reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
		reg |= refill[i];
		reg |= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;

		if (prio_type[i] == prio_group)
			reg |= IXGBE_RTTDT2C_GSP;

		if (prio_type[i] == prio_link)
			reg |= IXGBE_RTTDT2C_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
	}

	/*
	 * Configure Tx descriptor plane (recycle mode; WSP) and
	 * enable arbiter
	 */
	reg = IXGBE_RTTDCS_TDPAC | IXGBE_RTTDCS_TDRM;
	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);

	return 0;
}

/**
 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
 * @hw: pointer to hardware structure
 * @refill: refill credits index by traffic class
 * @max: max credits index by traffic class
 * @bwg_id: bandwidth grouping indexed by traffic class
 * @prio_type: priority type indexed by traffic class
 *
 * Configure Tx Packet Arbiter and credits for each traffic class.
 */
s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
					   u16 *refill,
					   u16 *max,
					   u8 *bwg_id,
					   u8 *prio_type,
					   u8 *prio_tc)
{
	u32 reg;
	u8 i;

	/*
	 * Disable the arbiter before changing parameters
	 * (always enable recycle mode; SP; arb delay)
	 */
	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
	      (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) |
	      IXGBE_RTTPCS_ARBDIS;
	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

	/* Map all traffic classes to their UP */
	reg = 0;
	for (i = 0; i < MAX_USER_PRIORITY; i++)
		reg |= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
	IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);

	/* Configure traffic class credits and priority */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		reg = refill[i];
		reg |= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
		reg |= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;

		if (prio_type[i] == prio_group)
			reg |= IXGBE_RTTPT2C_GSP;

		if (prio_type[i] == prio_link)
			reg |= IXGBE_RTTPT2C_LSP;

		IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
	}

	/*
	 * Configure Tx packet plane (recycle mode; SP; arb delay) and
	 * enable arbiter
	 */
	reg = IXGBE_RTTPCS_TPPAC | IXGBE_RTTPCS_TPRM |
	      (IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);

	return 0;
}

/**
 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
 * @hw: pointer to hardware structure
 * @pfc_en: enabled pfc bitmask
 * @prio_tc: priority to tc assignments indexed by priority
 *
 * Configure Priority Flow Control (PFC) for each traffic class.
 */
s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
{
	u32 i, j, reg;
	u8 max_tc = 0;

	for (i = 0; i < MAX_USER_PRIORITY; i++)
		if (prio_tc[i] > max_tc)
			max_tc = prio_tc[i];

	/* Configure PFC Tx thresholds per TC */
	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
		int enabled = 0;

		if (i > max_tc) {
			reg = 0;
			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
			IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
			continue;
		}

		for (j = 0; j < MAX_USER_PRIORITY; j++) {
			if ((prio_tc[j] == i) && (pfc_en & (1 << j))) {
				enabled = 1;
				break;
			}
		}

		reg = hw->fc.low_water << 10;

		if (enabled)
			reg |= IXGBE_FCRTL_XONE;
		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);

		reg = hw->fc.high_water[i] << 10;
		if (enabled)
			reg |= IXGBE_FCRTH_FCEN;
		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
	}

	if (pfc_en) {
		/* Configure pause time (2 TCs per register) */
		reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
		for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
			IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);

		/* Configure flow control refresh threshold value */
		IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);


		reg = IXGBE_FCCFG_TFCE_PRIORITY;
		IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
		/*
		 * Enable Receive PFC
		 * 82599 will always honor XOFF frames we receive when
		 * we are in PFC mode however X540 only honors enabled
		 * traffic classes.
		 */
		reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
		reg &= ~IXGBE_MFLCN_RFCE;
		reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;

		if (hw->mac.type == ixgbe_mac_X540) {
			reg &= ~(IXGBE_MFLCN_RPFCE_MASK | 0x10);
			reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
		}

		IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);

	} else {
		for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
			hw->mac.ops.fc_enable(hw, i);
	}

	return 0;
}

/**
 * ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
 * @hw: pointer to hardware structure
 *
 * Configure queue statistics registers, all queues belonging to same traffic
 * class uses a single set of queue statistics counters.
 */
static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
{
	u32 reg = 0;
	u8  i   = 0;

	/*
	 * Receive Queues stats setting
	 * 32 RQSMR registers, each configuring 4 queues.
	 * Set all 16 queues of each TC to the same stat
	 * with TC 'n' going to stat 'n'.
	 */
	for (i = 0; i < 32; i++) {
		reg = 0x01010101 * (i / 4);
		IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
	}
	/*
	 * Transmit Queues stats setting
	 * 32 TQSM registers, each controlling 4 queues.
	 * Set all queues of each TC to the same stat
	 * with TC 'n' going to stat 'n'.
	 * Tx queues are allocated non-uniformly to TCs:
	 * 32, 32, 16, 16, 8, 8, 8, 8.
	 */
	for (i = 0; i < 32; i++) {
		if (i < 8)
			reg = 0x00000000;
		else if (i < 16)
			reg = 0x01010101;
		else if (i < 20)
			reg = 0x02020202;
		else if (i < 24)
			reg = 0x03030303;
		else if (i < 26)
			reg = 0x04040404;
		else if (i < 28)
			reg = 0x05050505;
		else if (i < 30)
			reg = 0x06060606;
		else
			reg = 0x07070707;
		IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
	}

	return 0;
}

/**
 * ixgbe_dcb_hw_config_82599 - Configure and enable DCB
 * @hw: pointer to hardware structure
 * @refill: refill credits index by traffic class
 * @max: max credits index by traffic class
 * @bwg_id: bandwidth grouping indexed by traffic class
 * @prio_type: priority type indexed by traffic class
 * @pfc_en: enabled pfc bitmask
 *
 * Configure dcb settings and enable dcb mode.
 */
s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
			      u16 *max, u8 *bwg_id, u8 *prio_type, u8 *prio_tc)
{
	ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
					  prio_type, prio_tc);
	ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
					       bwg_id, prio_type);
	ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
					       bwg_id, prio_type, prio_tc);
	ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
	ixgbe_dcb_config_tc_stats_82599(hw);

	return 0;
}
Commit	Line	Data
235ea828 PW	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
a52055e0	4	Copyright(c) 1999 - 2011 Intel Corporation.
235ea828 PW	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#include "ixgbe.h"
	29	#include "ixgbe_type.h"
	30	#include "ixgbe_dcb.h"
	31	#include "ixgbe_dcb_82599.h"
	32
235ea828 PW	33	/**
	34	* ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
	35	* @hw: pointer to hardware structure
55320cb5 JF	36	* @refill: refill credits index by traffic class
	37	* @max: max credits index by traffic class
	38	* @bwg_id: bandwidth grouping indexed by traffic class
	39	* @prio_type: priority type indexed by traffic class
235ea828 PW	40	*
	41	* Configure Rx Packet Arbiter and credits for each traffic class.
	42	*/
55320cb5 JF	43	s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
	44	u16 *refill,
	45	u16 *max,
	46	u8 *bwg_id,
17049d30 JF	47	u8 *prio_type,
17049d30 JF	48	u8 *prio_tc)
235ea828	49	{
235ea828 PW	50	u32 reg = 0;
	51	u32 credit_refill = 0;
	52	u32 credit_max = 0;
	53	u8 i = 0;
	54
b7fdb714 PWJ	55	/*
	56	* Disable the arbiter before changing parameters
	57	* (always enable recycle mode; WSP)
	58	*/
	59	reg = IXGBE_RTRPCS_RRM \| IXGBE_RTRPCS_RAC \| IXGBE_RTRPCS_ARBDIS;
	60	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
235ea828	61
32701dc2	62	/* Map all traffic classes to their UP */
235ea828	63	reg = 0;
32701dc2	64	for (i = 0; i < MAX_USER_PRIORITY; i++)
17049d30	65	reg \|= (prio_tc[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT));
235ea828 PW	66	IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
	67
	68	/* Configure traffic class credits and priority */
	69	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
55320cb5 JF	70	credit_refill = refill[i];
55320cb5 JF	71	credit_max = max[i];
235ea828 PW	72	reg = credit_refill \| (credit_max << IXGBE_RTRPT4C_MCL_SHIFT);
235ea828 PW	73
55320cb5	74	reg \|= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT;
235ea828	75
55320cb5	76	if (prio_type[i] == prio_link)
235ea828 PW	77	reg \|= IXGBE_RTRPT4C_LSP;
	78
	79	IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg);
	80	}
	81
	82	/*
	83	* Configure Rx packet plane (recycle mode; WSP) and
	84	* enable arbiter
	85	*/
	86	reg = IXGBE_RTRPCS_RRM \| IXGBE_RTRPCS_RAC;
	87	IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
	88
	89	return 0;
	90	}
	91
	92	/**
	93	* ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
	94	* @hw: pointer to hardware structure
55320cb5 JF	95	* @refill: refill credits index by traffic class
	96	* @max: max credits index by traffic class
	97	* @bwg_id: bandwidth grouping indexed by traffic class
	98	* @prio_type: priority type indexed by traffic class
235ea828 PW	99	*
	100	* Configure Tx Descriptor Arbiter and credits for each traffic class.
	101	*/
55320cb5 JF	102	s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
	103	u16 *refill,
	104	u16 *max,
	105	u8 *bwg_id,
	106	u8 *prio_type)
235ea828	107	{
235ea828 PW	108	u32 reg, max_credits;
	109	u8 i;
	110
235ea828 PW	111	/* Clear the per-Tx queue credits; we use per-TC instead */
	112	for (i = 0; i < 128; i++) {
	113	IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
	114	IXGBE_WRITE_REG(hw, IXGBE_RTTDT1C, 0);
	115	}
	116
	117	/* Configure traffic class credits and priority */
	118	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
55320cb5	119	max_credits = max[i];
235ea828	120	reg = max_credits << IXGBE_RTTDT2C_MCL_SHIFT;
55320cb5 JF	121	reg \|= refill[i];
55320cb5 JF	122	reg \|= (u32)(bwg_id[i]) << IXGBE_RTTDT2C_BWG_SHIFT;
235ea828	123
55320cb5	124	if (prio_type[i] == prio_group)
235ea828 PW	125	reg \|= IXGBE_RTTDT2C_GSP;
235ea828 PW	126
55320cb5	127	if (prio_type[i] == prio_link)
235ea828 PW	128	reg \|= IXGBE_RTTDT2C_LSP;
	129
	130	IXGBE_WRITE_REG(hw, IXGBE_RTTDT2C(i), reg);
	131	}
	132
	133	/*
	134	* Configure Tx descriptor plane (recycle mode; WSP) and
	135	* enable arbiter
	136	*/
	137	reg = IXGBE_RTTDCS_TDPAC \| IXGBE_RTTDCS_TDRM;
	138	IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
	139
	140	return 0;
	141	}
	142
	143	/**
	144	* ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
	145	* @hw: pointer to hardware structure
55320cb5 JF	146	* @refill: refill credits index by traffic class
	147	* @max: max credits index by traffic class
	148	* @bwg_id: bandwidth grouping indexed by traffic class
	149	* @prio_type: priority type indexed by traffic class
235ea828 PW	150	*
	151	* Configure Tx Packet Arbiter and credits for each traffic class.
	152	*/
55320cb5 JF	153	s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
	154	u16 *refill,
	155	u16 *max,
	156	u8 *bwg_id,
17049d30 JF	157	u8 *prio_type,
17049d30 JF	158	u8 *prio_tc)
235ea828	159	{
235ea828 PW	160	u32 reg;
	161	u8 i;
	162
b7fdb714 PWJ	163	/*
	164	* Disable the arbiter before changing parameters
	165	* (always enable recycle mode; SP; arb delay)
	166	*/
	167	reg = IXGBE_RTTPCS_TPPAC \| IXGBE_RTTPCS_TPRM \|
	168	(IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT) \|
	169	IXGBE_RTTPCS_ARBDIS;
	170	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
235ea828	171
32701dc2	172	/* Map all traffic classes to their UP */
235ea828	173	reg = 0;
32701dc2	174	for (i = 0; i < MAX_USER_PRIORITY; i++)
17049d30	175	reg \|= (prio_tc[i] << (i * IXGBE_RTTUP2TC_UP_SHIFT));
235ea828 PW	176	IXGBE_WRITE_REG(hw, IXGBE_RTTUP2TC, reg);
	177
	178	/* Configure traffic class credits and priority */
	179	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
55320cb5 JF	180	reg = refill[i];
	181	reg \|= (u32)(max[i]) << IXGBE_RTTPT2C_MCL_SHIFT;
	182	reg \|= (u32)(bwg_id[i]) << IXGBE_RTTPT2C_BWG_SHIFT;
235ea828	183
55320cb5	184	if (prio_type[i] == prio_group)
235ea828 PW	185	reg \|= IXGBE_RTTPT2C_GSP;
235ea828 PW	186
55320cb5	187	if (prio_type[i] == prio_link)
235ea828 PW	188	reg \|= IXGBE_RTTPT2C_LSP;
	189
	190	IXGBE_WRITE_REG(hw, IXGBE_RTTPT2C(i), reg);
	191	}
	192
	193	/*
	194	* Configure Tx packet plane (recycle mode; SP; arb delay) and
	195	* enable arbiter
	196	*/
	197	reg = IXGBE_RTTPCS_TPPAC \| IXGBE_RTTPCS_TPRM \|
	198	(IXGBE_RTTPCS_ARBD_DCB << IXGBE_RTTPCS_ARBD_SHIFT);
	199	IXGBE_WRITE_REG(hw, IXGBE_RTTPCS, reg);
	200
	201	return 0;
	202	}
	203
	204	/**
	205	* ixgbe_dcb_config_pfc_82599 - Configure priority flow control
	206	* @hw: pointer to hardware structure
55320cb5	207	* @pfc_en: enabled pfc bitmask
32701dc2	208	* @prio_tc: priority to tc assignments indexed by priority
235ea828 PW	209	*
	210	* Configure Priority Flow Control (PFC) for each traffic class.
	211	*/
32701dc2	212	s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw hw, u8 pfc_en, u8 prio_tc)
235ea828	213	{
32701dc2 JF	214	u32 i, j, reg;
	215	u8 max_tc = 0;
	216
	217	for (i = 0; i < MAX_USER_PRIORITY; i++)
	218	if (prio_tc[i] > max_tc)
	219	max_tc = prio_tc[i];
235ea828	220
235ea828 PW	221	/* Configure PFC Tx thresholds per TC */
235ea828 PW	222	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
32701dc2 JF	223	int enabled = 0;
	224
	225	if (i > max_tc) {
	226	reg = 0;
	227	IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
	228	IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
	229	continue;
	230	}
	231
	232	for (j = 0; j < MAX_USER_PRIORITY; j++) {
	233	if ((prio_tc[j] == i) && (pfc_en & (1 << j))) {
	234	enabled = 1;
	235	break;
	236	}
	237	}
16b61beb	238
9da712d2	239	reg = hw->fc.low_water << 10;
2f3889f4	240
55320cb5	241	if (enabled)
2f3889f4 PW	242	reg \|= IXGBE_FCRTL_XONE;
	243	IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
	244
9da712d2	245	reg = hw->fc.high_water[i] << 10;
55320cb5	246	if (enabled)
2f3889f4 PW	247	reg \|= IXGBE_FCRTH_FCEN;
2f3889f4 PW	248	IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), reg);
235ea828 PW	249	}
235ea828 PW	250
1f4a0244 JF	251	if (pfc_en) {
	252	/* Configure pause time (2 TCs per register) */
	253	reg = hw->fc.pause_time \| (hw->fc.pause_time << 16);
	254	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
	255	IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
	256
	257	/* Configure flow control refresh threshold value */
	258	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
	259
	260
	261	reg = IXGBE_FCCFG_TFCE_PRIORITY;
	262	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);
	263	/*
	264	* Enable Receive PFC
45a5f720 JF	265	* 82599 will always honor XOFF frames we receive when
	266	* we are in PFC mode however X540 only honors enabled
	267	* traffic classes.
1f4a0244 JF	268	*/
	269	reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
	270	reg &= ~IXGBE_MFLCN_RFCE;
	271	reg \|= IXGBE_MFLCN_RPFCE \| IXGBE_MFLCN_DPF;
45a5f720	272
634cdca5	273	if (hw->mac.type == ixgbe_mac_X540) {
32701dc2	274	reg &= ~(IXGBE_MFLCN_RPFCE_MASK \| 0x10);
45a5f720	275	reg \|= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;
634cdca5	276	}
45a5f720	277
1f4a0244 JF	278	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);
	279
	280	} else {
	281	for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
	282	hw->mac.ops.fc_enable(hw, i);
	283	}
235ea828	284
235ea828 PW	285	return 0;
	286	}
	287
	288	/**
	289	* ixgbe_dcb_config_tc_stats_82599 - Config traffic class statistics
	290	* @hw: pointer to hardware structure
	291	*
	292	* Configure queue statistics registers, all queues belonging to same traffic
	293	* class uses a single set of queue statistics counters.
	294	*/
5d5b7c39	295	static s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *hw)
235ea828 PW	296	{
	297	u32 reg = 0;
	298	u8 i = 0;
	299
	300	/*
	301	* Receive Queues stats setting
	302	* 32 RQSMR registers, each configuring 4 queues.
	303	* Set all 16 queues of each TC to the same stat
	304	* with TC 'n' going to stat 'n'.
	305	*/
	306	for (i = 0; i < 32; i++) {
	307	reg = 0x01010101 * (i / 4);
	308	IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
	309	}
	310	/*
	311	* Transmit Queues stats setting
	312	* 32 TQSM registers, each controlling 4 queues.
	313	* Set all queues of each TC to the same stat
	314	* with TC 'n' going to stat 'n'.
	315	* Tx queues are allocated non-uniformly to TCs:
	316	* 32, 32, 16, 16, 8, 8, 8, 8.
	317	*/
	318	for (i = 0; i < 32; i++) {
	319	if (i < 8)
	320	reg = 0x00000000;
	321	else if (i < 16)
	322	reg = 0x01010101;
	323	else if (i < 20)
	324	reg = 0x02020202;
	325	else if (i < 24)
	326	reg = 0x03030303;
	327	else if (i < 26)
	328	reg = 0x04040404;
	329	else if (i < 28)
	330	reg = 0x05050505;
	331	else if (i < 30)
	332	reg = 0x06060606;
	333	else
	334	reg = 0x07070707;
	335	IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), reg);
	336	}
	337
	338	return 0;
	339	}
	340
235ea828 PW	341	/**
	342	* ixgbe_dcb_hw_config_82599 - Configure and enable DCB
	343	* @hw: pointer to hardware structure
55320cb5 JF	344	* @refill: refill credits index by traffic class
	345	* @max: max credits index by traffic class
	346	* @bwg_id: bandwidth grouping indexed by traffic class
	347	* @prio_type: priority type indexed by traffic class
	348	* @pfc_en: enabled pfc bitmask
235ea828 PW	349	*
	350	* Configure dcb settings and enable dcb mode.
	351	*/
80605c65	352	s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw hw, u8 pfc_en, u16 refill,
17049d30	353	u16 max, u8 bwg_id, u8 prio_type, u8 prio_tc)
235ea828	354	{
17049d30 JF	355	ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
17049d30 JF	356	prio_type, prio_tc);
55320cb5 JF	357	ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
	358	bwg_id, prio_type);
	359	ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
17049d30	360	bwg_id, prio_type, prio_tc);
32701dc2	361	ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
235ea828 PW	362	ixgbe_dcb_config_tc_stats_82599(hw);
	363
	364	return 0;
	365	}
	366