projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbevf: Correct parameter sent to LED function
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
49425dfc 4 Copyright(c) 1999 - 2016 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ethtool support for ixgbe */
30
a6b7a407 31#include <linux/interrupt.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/module.h>
5a0e3ad6 34#include <linux/slab.h>
9a799d71
AK		 35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/ethtool.h>
38#include <linux/vmalloc.h>
f800326d 39#include <linux/highmem.h>
9a799d71
AK		 40#include <linux/uaccess.h>
41
42#include "ixgbe.h"
71858acb 43#include "ixgbe_phy.h"
9a799d71
AK		 44
45
46#define IXGBE_ALL_RAR_ENTRIES 16
47
29c3a050
AK		 48enum {NETDEV_STATS, IXGBE_STATS};
49
9a799d71
AK		 50struct ixgbe_stats {
51 char stat_string[ETH_GSTRING_LEN];
29c3a050 52 int type;
9a799d71
AK		 53 int sizeof_stat;
54 int stat_offset;
55};
56
29c3a050
AK		 57#define IXGBE_STAT(m) IXGBE_STATS, \
58 sizeof(((struct ixgbe_adapter *)0)->m), \
59 offsetof(struct ixgbe_adapter, m)
60#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 61 sizeof(((struct rtnl_link_stats64 *)0)->m), \
62 offsetof(struct rtnl_link_stats64, m)
29c3a050 63
1bba2e81 64static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 65 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
66 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
67 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
68 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 69 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
70 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
71 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
72 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 73 {"lsc_int", IXGBE_STAT(lsc_int)},
74 {"tx_busy", IXGBE_STAT(tx_busy)},
75 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 76 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
77 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
78 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
79 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
80 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 81 {"broadcast", IXGBE_STAT(stats.bprc)},
82 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 83 {"collisions", IXGBE_NETDEV_STAT(collisions)},
84 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
85 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
86 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 87 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
88 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 89 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
90 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 91 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 92 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
93 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
94 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
95 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
96 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
97 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 98 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
99 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
100 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
101 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 102 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
103 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
104 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
105 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 106 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 107 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
108 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 109 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 110 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
111 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
112 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
113 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 114#ifdef IXGBE_FCOE
115 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
116 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
117 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
118 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
7b859ebc
AH		 119 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
120 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
6d45522c
YZ		 121 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
122 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
123#endif /* IXGBE_FCOE */
9a799d71
AK		 124};
125
9cc00b51
JF		 126/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
127 * we set the num_rx_queues to evaluate to num_tx_queues. This is
128 * used because we do not have a good way to get the max number of
129 * rx queues with CONFIG_RPS disabled.
130 */
131#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
132
133#define IXGBE_QUEUE_STATS_LEN ( \
134 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
454d7c9b 135 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 136#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 137#define IXGBE_PB_STATS_LEN ( \
9cc00b51
JF		 138 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
141 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
142 / sizeof(u64))
2f90b865 143#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
e7cf745b
JK		 144 IXGBE_PB_STATS_LEN + \
145 IXGBE_QUEUE_STATS_LEN)
9a799d71 146
da4dd0f7
PWJ		 147static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
148 "Register test (offline)", "Eeprom test (offline)",
149 "Interrupt test (offline)", "Loopback test (offline)",
150 "Link test (on/offline)"
151};
152#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
153
695b816d
VN		 154/* currently supported speeds for 10G */
155#define ADVRTSD_MSK_10G (SUPPORTED_10000baseT_Full | \
156 SUPPORTED_10000baseKX4_Full | \
157 SUPPORTED_10000baseKR_Full)
158
159#define ixgbe_isbackplane(type) ((type) == ixgbe_media_type_backplane)
160
161static u32 ixgbe_get_supported_10gtypes(struct ixgbe_hw *hw)
162{
163 if (!ixgbe_isbackplane(hw->phy.media_type))
164 return SUPPORTED_10000baseT_Full;
165
166 switch (hw->device_id) {
167 case IXGBE_DEV_ID_82598:
168 case IXGBE_DEV_ID_82599_KX4:
169 case IXGBE_DEV_ID_82599_KX4_MEZZ:
170 case IXGBE_DEV_ID_X550EM_X_KX4:
171 return SUPPORTED_10000baseKX4_Full;
172 case IXGBE_DEV_ID_82598_BX:
173 case IXGBE_DEV_ID_82599_KR:
174 case IXGBE_DEV_ID_X550EM_X_KR:
175 return SUPPORTED_10000baseKR_Full;
176 default:
177 return SUPPORTED_10000baseKX4_Full |
178 SUPPORTED_10000baseKR_Full;
179 }
180}
181
9a799d71 182static int ixgbe_get_settings(struct net_device *netdev,
e7cf745b 183 struct ethtool_cmd *ecmd)
9a799d71
AK		 184{
185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 186 struct ixgbe_hw *hw = &adapter->hw;
db018963 187 ixgbe_link_speed supported_link;
fd0326f2 188 bool autoneg = false;
9a799d71 189
db018963 190 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
1b1c0a48 191
db018963
JK		 192 /* set the supported link speeds */
193 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
695b816d 194 ecmd->supported |= ixgbe_get_supported_10gtypes(hw);
db018963
JK		 195 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
196 ecmd->supported |= SUPPORTED_1000baseT_Full;
197 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
695b816d
VN		 198 ecmd->supported |= ixgbe_isbackplane(hw->phy.media_type) ?
199 SUPPORTED_1000baseKX_Full :
200 SUPPORTED_1000baseT_Full;
1b1c0a48 201
695b816d
VN		 202 /* default advertised speed if phy.autoneg_advertised isn't set */
203 ecmd->advertising = ecmd->supported;
db018963
JK		 204 /* set the advertised speeds */
205 if (hw->phy.autoneg_advertised) {
695b816d 206 ecmd->advertising = 0;
db018963
JK		 207 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
208 ecmd->advertising |= ADVERTISED_100baseT_Full;
209 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
695b816d
VN		 210 ecmd->advertising |= ecmd->supported & ADVRTSD_MSK_10G;
211 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {
212 if (ecmd->supported & SUPPORTED_1000baseKX_Full)
213 ecmd->advertising |= ADVERTISED_1000baseKX_Full;
214 else
215 ecmd->advertising |= ADVERTISED_1000baseT_Full;
216 }
735441fb 217 } else {
ed33ff66
ET		 218 if (hw->phy.multispeed_fiber && !autoneg) {
219 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
220 ecmd->advertising = ADVERTISED_10000baseT_Full;
221 }
735441fb 222 }
9a799d71 223
db018963
JK		 224 if (autoneg) {
225 ecmd->supported |= SUPPORTED_Autoneg;
226 ecmd->advertising |= ADVERTISED_Autoneg;
227 ecmd->autoneg = AUTONEG_ENABLE;
228 } else
229 ecmd->autoneg = AUTONEG_DISABLE;
230
231 ecmd->transceiver = XCVR_EXTERNAL;
232
233 /* Determine the remaining settings based on the PHY type. */
3b8626ba
PW		 234 switch (adapter->hw.phy.type) {
235 case ixgbe_phy_tn:
fe15e8e1 236 case ixgbe_phy_aq:
c2c78d5c 237 case ixgbe_phy_x550em_ext_t:
3b8626ba 238 case ixgbe_phy_cu_unknown:
db018963
JK		 239 ecmd->supported |= SUPPORTED_TP;
240 ecmd->advertising |= ADVERTISED_TP;
3b8626ba
PW		 241 ecmd->port = PORT_TP;
242 break;
243 case ixgbe_phy_qt:
db018963
JK		 244 ecmd->supported |= SUPPORTED_FIBRE;
245 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 246 ecmd->port = PORT_FIBRE;
247 break;
248 case ixgbe_phy_nl:
ea0a04df
DS		 249 case ixgbe_phy_sfp_passive_tyco:
250 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 251 case ixgbe_phy_sfp_ftl:
252 case ixgbe_phy_sfp_avago:
253 case ixgbe_phy_sfp_intel:
254 case ixgbe_phy_sfp_unknown:
af56b4d8
ET		 255 case ixgbe_phy_qsfp_passive_unknown:
256 case ixgbe_phy_qsfp_active_unknown:
257 case ixgbe_phy_qsfp_intel:
258 case ixgbe_phy_qsfp_unknown:
3b8626ba 259 /* SFP+ devices, further checking needed */
db018963 260 switch (adapter->hw.phy.sfp_type) {
3b8626ba
PW		 261 case ixgbe_sfp_type_da_cu:
262 case ixgbe_sfp_type_da_cu_core0:
263 case ixgbe_sfp_type_da_cu_core1:
db018963
JK		 264 ecmd->supported |= SUPPORTED_FIBRE;
265 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 266 ecmd->port = PORT_DA;
267 break;
268 case ixgbe_sfp_type_sr:
269 case ixgbe_sfp_type_lr:
270 case ixgbe_sfp_type_srlr_core0:
271 case ixgbe_sfp_type_srlr_core1:
345be204
DS		 272 case ixgbe_sfp_type_1g_sx_core0:
273 case ixgbe_sfp_type_1g_sx_core1:
274 case ixgbe_sfp_type_1g_lx_core0:
275 case ixgbe_sfp_type_1g_lx_core1:
db018963
JK		 276 ecmd->supported |= SUPPORTED_FIBRE;
277 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 278 ecmd->port = PORT_FIBRE;
279 break;
280 case ixgbe_sfp_type_not_present:
db018963
JK		 281 ecmd->supported |= SUPPORTED_FIBRE;
282 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 283 ecmd->port = PORT_NONE;
284 break;
cb836a97
DS		 285 case ixgbe_sfp_type_1g_cu_core0:
286 case ixgbe_sfp_type_1g_cu_core1:
db018963
JK		 287 ecmd->supported |= SUPPORTED_TP;
288 ecmd->advertising |= ADVERTISED_TP;
cb836a97 289 ecmd->port = PORT_TP;
db018963 290 break;
3b8626ba
PW		 291 case ixgbe_sfp_type_unknown:
292 default:
db018963
JK		 293 ecmd->supported |= SUPPORTED_FIBRE;
294 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 295 ecmd->port = PORT_OTHER;
296 break;
297 }
298 break;
299 case ixgbe_phy_xaui:
db018963
JK		 300 ecmd->supported |= SUPPORTED_FIBRE;
301 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 302 ecmd->port = PORT_NONE;
303 break;
304 case ixgbe_phy_unknown:
305 case ixgbe_phy_generic:
306 case ixgbe_phy_sfp_unsupported:
307 default:
db018963
JK		 308 ecmd->supported |= SUPPORTED_FIBRE;
309 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 310 ecmd->port = PORT_OTHER;
311 break;
312 }
313
0e4d422f
ET		 314 if (netif_carrier_ok(netdev)) {
315 switch (adapter->link_speed) {
1b1c0a48 316 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 317 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48 318 break;
454adb00
MR		 319 case IXGBE_LINK_SPEED_2_5GB_FULL:
320 ethtool_cmd_speed_set(ecmd, SPEED_2500);
321 break;
1b1c0a48 322 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 323 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 324 break;
325 case IXGBE_LINK_SPEED_100_FULL:
70739497 326 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 327 break;
328 default:
329 break;
330 }
9a799d71
AK		 331 ecmd->duplex = DUPLEX_FULL;
332 } else {
537fae01
JP		 333 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
334 ecmd->duplex = DUPLEX_UNKNOWN;
9a799d71
AK		 335 }
336
9a799d71
AK		 337 return 0;
338}
339
340static int ixgbe_set_settings(struct net_device *netdev,
e7cf745b 341 struct ethtool_cmd *ecmd)
9a799d71
AK		 342{
343 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 344 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 345 u32 advertised, old;
74766013 346 s32 err = 0;
9a799d71 347
74766013 348 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 349 (hw->phy.multispeed_fiber)) {
abcc80d2
ET		 350 /*
351 * this function does not support duplex forcing, but can
352 * limit the advertising of the adapter to the specified speed
353 */
abcc80d2
ET		 354 if (ecmd->advertising & ~ecmd->supported)
355 return -EINVAL;
356
ed33ff66
ET		 357 /* only allow one speed at a time if no autoneg */
358 if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
359 if (ecmd->advertising ==
360 (ADVERTISED_10000baseT_Full |
361 ADVERTISED_1000baseT_Full))
362 return -EINVAL;
363 }
364
0befdb3e
JB		 365 old = hw->phy.autoneg_advertised;
366 advertised = 0;
367 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
368 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
369
370 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
371 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
372
2b642ca5
ET		 373 if (ecmd->advertising & ADVERTISED_100baseT_Full)
374 advertised |= IXGBE_LINK_SPEED_100_FULL;
375
0befdb3e 376 if (old == advertised)
74766013 377 return err;
0befdb3e 378 /* this sets the link speed and restarts auto-neg */
e3215f0a
ET		 379 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
380 usleep_range(1000, 2000);
381
74766013 382 hw->mac.autotry_restart = true;
fd0326f2 383 err = hw->mac.ops.setup_link(hw, advertised, true);
0befdb3e 384 if (err) {
396e799c 385 e_info(probe, "setup link failed with code %d\n", err);
fd0326f2 386 hw->mac.ops.setup_link(hw, old, true);
0befdb3e 387 }
e3215f0a 388 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
74766013
MC		 389 } else {
390 /* in this case we currently only support 10Gb/FULL */
25db0338 391 u32 speed = ethtool_cmd_speed(ecmd);
74766013 392 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 393 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 394 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 395 return -EINVAL;
9a799d71
AK		 396 }
397
74766013 398 return err;
9a799d71
AK		 399}
400
401static void ixgbe_get_pauseparam(struct net_device *netdev,
e7cf745b 402 struct ethtool_pauseparam *pause)
9a799d71
AK		 403{
404 struct ixgbe_adapter *adapter = netdev_priv(netdev);
405 struct ixgbe_hw *hw = &adapter->hw;
406
73d80953
DS		 407 if (ixgbe_device_supports_autoneg_fc(hw) &&
408 !hw->fc.disable_fc_autoneg)
71fd570b 409 pause->autoneg = 1;
73d80953
DS		 410 else
411 pause->autoneg = 0;
9a799d71 412
0ecc061d 413 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 414 pause->rx_pause = 1;
0ecc061d 415 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 416 pause->tx_pause = 1;
0ecc061d 417 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 418 pause->rx_pause = 1;
419 pause->tx_pause = 1;
420 }
421}
422
423static int ixgbe_set_pauseparam(struct net_device *netdev,
e7cf745b 424 struct ethtool_pauseparam *pause)
9a799d71
AK		 425{
426 struct ixgbe_adapter *adapter = netdev_priv(netdev);
427 struct ixgbe_hw *hw = &adapter->hw;
943561d3 428 struct ixgbe_fc_info fc = hw->fc;
9a799d71 429
943561d3
AD		 430 /* 82598 does no support link flow control with DCB enabled */
431 if ((hw->mac.type == ixgbe_mac_82598EB) &&
432 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
264857b8
PWJ		 433 return -EINVAL;
434
db2adc2d
JK		 435 /* some devices do not support autoneg of link flow control */
436 if ((pause->autoneg == AUTONEG_ENABLE) &&
73d80953 437 !ixgbe_device_supports_autoneg_fc(hw))
db2adc2d
JK		 438 return -EINVAL;
439
943561d3 440 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
71fd570b 441
1c4f0ef8 442 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 443 fc.requested_mode = ixgbe_fc_full;
9a799d71 444 else if (pause->rx_pause && !pause->tx_pause)
620fa036 445 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 446 else if (!pause->rx_pause && pause->tx_pause)
620fa036 447 fc.requested_mode = ixgbe_fc_tx_pause;
9c83b070 448 else
943561d3 449 fc.requested_mode = ixgbe_fc_none;
620fa036
MC		 450
451 /* if the thing changed then we'll update and use new autoneg */
452 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
453 hw->fc = fc;
454 if (netif_running(netdev))
455 ixgbe_reinit_locked(adapter);
456 else
457 ixgbe_reset(adapter);
458 }
9a799d71
AK		 459
460 return 0;
461}
462
9a799d71
AK		 463static u32 ixgbe_get_msglevel(struct net_device *netdev)
464{
465 struct ixgbe_adapter *adapter = netdev_priv(netdev);
466 return adapter->msg_enable;
467}
468
469static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
470{
471 struct ixgbe_adapter *adapter = netdev_priv(netdev);
472 adapter->msg_enable = data;
473}
474
475static int ixgbe_get_regs_len(struct net_device *netdev)
476{
51e409f1 477#define IXGBE_REGS_LEN 1139
9a799d71
AK		 478 return IXGBE_REGS_LEN * sizeof(u32);
479}
480
481#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
482
483static void ixgbe_get_regs(struct net_device *netdev,
e7cf745b 484 struct ethtool_regs *regs, void *p)
9a799d71
AK		 485{
486 struct ixgbe_adapter *adapter = netdev_priv(netdev);
487 struct ixgbe_hw *hw = &adapter->hw;
488 u32 *regs_buff = p;
489 u8 i;
490
491 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
492
c4a56de8
ET		 493 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
494 hw->device_id;
9a799d71
AK		 495
496 /* General Registers */
497 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
498 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
499 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
500 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
501 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
502 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
503 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
504 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
505
506 /* NVM Register */
9a900eca 507 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
9a799d71 508 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
9a900eca 509 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA(hw));
9a799d71
AK		 510 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
511 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
512 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
513 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
514 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
515 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
9a900eca 516 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC(hw));
9a799d71
AK		 517
518 /* Interrupt */
98c00a1c
JB		 519 /* don't read EICR because it can clear interrupt causes, instead
520 * read EICS which is a shadow but doesn't clear EICR */
521 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 522 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
523 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
524 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
525 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
526 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
527 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
528 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
529 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
530 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 531 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 532 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
533
534 /* Flow Control */
535 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
45a88dfc
PB		 536 for (i = 0; i < 4; i++)
537 regs_buff[31 + i] = IXGBE_READ_REG(hw, IXGBE_FCTTV(i));
bd508178
AD		 538 for (i = 0; i < 8; i++) {
539 switch (hw->mac.type) {
540 case ixgbe_mac_82598EB:
541 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
542 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
543 break;
544 case ixgbe_mac_82599EB:
80bb25e3 545 case ixgbe_mac_X540:
9a75a1ac
DS		 546 case ixgbe_mac_X550:
547 case ixgbe_mac_X550EM_x:
49425dfc 548 case ixgbe_mac_x550em_a:
bd508178
AD		 549 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
550 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
551 break;
552 default:
553 break;
554 }
555 }
9a799d71
AK		 556 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
557 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
558
559 /* Receive DMA */
560 for (i = 0; i < 64; i++)
561 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
562 for (i = 0; i < 64; i++)
563 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
564 for (i = 0; i < 64; i++)
565 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
566 for (i = 0; i < 64; i++)
567 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
568 for (i = 0; i < 64; i++)
569 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
570 for (i = 0; i < 64; i++)
571 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
572 for (i = 0; i < 16; i++)
573 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
574 for (i = 0; i < 16; i++)
575 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
576 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
577 for (i = 0; i < 8; i++)
578 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
579 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
580 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
581
582 /* Receive */
583 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
584 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
585 for (i = 0; i < 16; i++)
586 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
587 for (i = 0; i < 16; i++)
588 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 589 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 590 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
591 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
592 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
593 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
594 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
595 for (i = 0; i < 8; i++)
596 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
597 for (i = 0; i < 8; i++)
598 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
599 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
600
601 /* Transmit */
602 for (i = 0; i < 32; i++)
603 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
604 for (i = 0; i < 32; i++)
605 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
606 for (i = 0; i < 32; i++)
607 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
608 for (i = 0; i < 32; i++)
609 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
610 for (i = 0; i < 32; i++)
611 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
612 for (i = 0; i < 32; i++)
613 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
614 for (i = 0; i < 32; i++)
615 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
616 for (i = 0; i < 32; i++)
617 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
618 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
619 for (i = 0; i < 16; i++)
620 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
621 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
622 for (i = 0; i < 8; i++)
623 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
624 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
625
626 /* Wake Up */
627 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
628 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
629 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
630 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
631 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
632 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
633 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
634 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 635 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 636
673ac604 637 /* DCB */
51e409f1
LP		 638 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS); /* same as FCCFG */
639 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
640
641 switch (hw->mac.type) {
642 case ixgbe_mac_82598EB:
643 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
644 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
645 for (i = 0; i < 8; i++)
646 regs_buff[833 + i] =
647 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
648 for (i = 0; i < 8; i++)
649 regs_buff[841 + i] =
650 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
651 for (i = 0; i < 8; i++)
652 regs_buff[849 + i] =
653 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
654 for (i = 0; i < 8; i++)
655 regs_buff[857 + i] =
656 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
657 break;
658 case ixgbe_mac_82599EB:
659 case ixgbe_mac_X540:
9a75a1ac
DS		 660 case ixgbe_mac_X550:
661 case ixgbe_mac_X550EM_x:
49425dfc 662 case ixgbe_mac_x550em_a:
51e409f1
LP		 663 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
664 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
665 for (i = 0; i < 8; i++)
666 regs_buff[833 + i] =
667 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
668 for (i = 0; i < 8; i++)
669 regs_buff[841 + i] =
670 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
671 for (i = 0; i < 8; i++)
672 regs_buff[849 + i] =
673 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
674 for (i = 0; i < 8; i++)
675 regs_buff[857 + i] =
676 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
677 break;
678 default:
679 break;
680 }
681
9a799d71 682 for (i = 0; i < 8; i++)
51e409f1
LP		 683 regs_buff[865 + i] =
684 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
9a799d71 685 for (i = 0; i < 8; i++)
51e409f1
LP		 686 regs_buff[873 + i] =
687 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
9a799d71
AK		 688
689 /* Statistics */
690 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
691 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
692 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
693 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
694 for (i = 0; i < 8; i++)
695 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
696 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
697 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
698 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
699 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
700 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
701 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
702 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
703 for (i = 0; i < 8; i++)
704 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
705 for (i = 0; i < 8; i++)
706 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
707 for (i = 0; i < 8; i++)
708 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
709 for (i = 0; i < 8; i++)
710 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
711 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
712 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
713 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
714 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
715 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
716 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
717 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
718 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
719 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
720 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
4c4f8023
PB		 721 regs_buff[942] = (u32)IXGBE_GET_STAT(adapter, gorc);
722 regs_buff[943] = (u32)(IXGBE_GET_STAT(adapter, gorc) >> 32);
723 regs_buff[944] = (u32)IXGBE_GET_STAT(adapter, gotc);
724 regs_buff[945] = (u32)(IXGBE_GET_STAT(adapter, gotc) >> 32);
9a799d71
AK		 725 for (i = 0; i < 8; i++)
726 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
727 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
728 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
729 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
730 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
731 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
732 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
733 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
4c4f8023
PB		 734 regs_buff[961] = (u32)IXGBE_GET_STAT(adapter, tor);
735 regs_buff[962] = (u32)(IXGBE_GET_STAT(adapter, tor) >> 32);
9a799d71
AK		 736 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
737 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
738 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
739 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
740 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
741 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
742 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
743 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
744 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
745 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
746 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
747 for (i = 0; i < 16; i++)
748 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
749 for (i = 0; i < 16; i++)
750 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
751 for (i = 0; i < 16; i++)
752 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
753 for (i = 0; i < 16; i++)
754 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
755
756 /* MAC */
757 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
758 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
759 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
760 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
761 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
762 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
763 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
764 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
765 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
766 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
767 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
768 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
769 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
770 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
771 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
772 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
773 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
774 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
775 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
776 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
777 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
778 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
779 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
780 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
781 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
782 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
783 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
784 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
785 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
786 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
787 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
788 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
789 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
790
791 /* Diagnostic */
792 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
793 for (i = 0; i < 8; i++)
98c00a1c 794 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 795 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 796 for (i = 0; i < 4; i++)
797 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 798 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
799 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
800 for (i = 0; i < 8; i++)
98c00a1c 801 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 802 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 803 for (i = 0; i < 4; i++)
804 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 805 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
806 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
45a88dfc
PB		 807 for (i = 0; i < 4; i++)
808 regs_buff[1102 + i] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA(i));
9a799d71 809 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
45a88dfc
PB		 810 for (i = 0; i < 4; i++)
811 regs_buff[1107 + i] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA(i));
9a799d71 812 for (i = 0; i < 8; i++)
98c00a1c 813 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 814 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
815 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
816 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
817 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
818 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
819 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
820 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
821 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
822 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
217995ec
ET		 823
824 /* 82599 X540 specific registers */
825 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
51e409f1
LP		 826
827 /* 82599 X540 specific DCB registers */
828 regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
829 regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
830 for (i = 0; i < 4; i++)
831 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
832 regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
833 /* same as RTTQCNRM */
834 regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
835 /* same as RTTQCNRR */
836
837 /* X540 specific DCB registers */
838 regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
839 regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
9a799d71
AK		 840}
841
842static int ixgbe_get_eeprom_len(struct net_device *netdev)
843{
844 struct ixgbe_adapter *adapter = netdev_priv(netdev);
845 return adapter->hw.eeprom.word_size * 2;
846}
847
848static int ixgbe_get_eeprom(struct net_device *netdev,
e7cf745b 849 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 850{
851 struct ixgbe_adapter *adapter = netdev_priv(netdev);
852 struct ixgbe_hw *hw = &adapter->hw;
853 u16 *eeprom_buff;
854 int first_word, last_word, eeprom_len;
855 int ret_val = 0;
856 u16 i;
857
858 if (eeprom->len == 0)
859 return -EINVAL;
860
861 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
862
863 first_word = eeprom->offset >> 1;
864 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
865 eeprom_len = last_word - first_word + 1;
866
867 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
868 if (!eeprom_buff)
869 return -ENOMEM;
870
68c7005d
ET		 871 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
872 eeprom_buff);
9a799d71
AK		 873
874 /* Device's eeprom is always little-endian, word addressable */
875 for (i = 0; i < eeprom_len; i++)
876 le16_to_cpus(&eeprom_buff[i]);
877
878 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
879 kfree(eeprom_buff);
880
881 return ret_val;
882}
883
2fa5eef4
ET		 884static int ixgbe_set_eeprom(struct net_device *netdev,
885 struct ethtool_eeprom *eeprom, u8 *bytes)
886{
887 struct ixgbe_adapter *adapter = netdev_priv(netdev);
888 struct ixgbe_hw *hw = &adapter->hw;
889 u16 *eeprom_buff;
890 void *ptr;
891 int max_len, first_word, last_word, ret_val = 0;
892 u16 i;
893
894 if (eeprom->len == 0)
895 return -EINVAL;
896
897 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
898 return -EINVAL;
899
900 max_len = hw->eeprom.word_size * 2;
901
902 first_word = eeprom->offset >> 1;
903 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
904 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
905 if (!eeprom_buff)
906 return -ENOMEM;
907
908 ptr = eeprom_buff;
909
910 if (eeprom->offset & 1) {
911 /*
912 * need read/modify/write of first changed EEPROM word
913 * only the second byte of the word is being modified
914 */
915 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
916 if (ret_val)
917 goto err;
918
919 ptr++;
920 }
921 if ((eeprom->offset + eeprom->len) & 1) {
922 /*
923 * need read/modify/write of last changed EEPROM word
924 * only the first byte of the word is being modified
925 */
926 ret_val = hw->eeprom.ops.read(hw, last_word,
927 &eeprom_buff[last_word - first_word]);
928 if (ret_val)
929 goto err;
930 }
931
932 /* Device's eeprom is always little-endian, word addressable */
933 for (i = 0; i < last_word - first_word + 1; i++)
934 le16_to_cpus(&eeprom_buff[i]);
935
936 memcpy(ptr, bytes, eeprom->len);
937
938 for (i = 0; i < last_word - first_word + 1; i++)
939 cpu_to_le16s(&eeprom_buff[i]);
940
941 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
942 last_word - first_word + 1,
943 eeprom_buff);
944
945 /* Update the checksum */
946 if (ret_val == 0)
947 hw->eeprom.ops.update_checksum(hw);
948
949err:
950 kfree(eeprom_buff);
951 return ret_val;
952}
953
9a799d71 954static void ixgbe_get_drvinfo(struct net_device *netdev,
e7cf745b 955 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 956{
957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
15e5209f 958 u32 nvm_track_id;
9a799d71 959
612a94d6
RJ		 960 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
961 strlcpy(drvinfo->version, ixgbe_driver_version,
962 sizeof(drvinfo->version));
083fc582 963
15e5209f
ET		 964 nvm_track_id = (adapter->eeprom_verh << 16) |
965 adapter->eeprom_verl;
612a94d6 966 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
15e5209f 967 nvm_track_id);
083fc582 968
612a94d6
RJ		 969 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
970 sizeof(drvinfo->bus_info));
9a799d71
AK		 971}
972
973static void ixgbe_get_ringparam(struct net_device *netdev,
e7cf745b 974 struct ethtool_ringparam *ring)
9a799d71
AK		 975{
976 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 977 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
978 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 979
980 ring->rx_max_pending = IXGBE_MAX_RXD;
981 ring->tx_max_pending = IXGBE_MAX_TXD;
9a799d71
AK		 982 ring->rx_pending = rx_ring->count;
983 ring->tx_pending = tx_ring->count;
9a799d71
AK		 984}
985
986static int ixgbe_set_ringparam(struct net_device *netdev,
e7cf745b 987 struct ethtool_ringparam *ring)
9a799d71
AK		 988{
989 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1f4702aa 990 struct ixgbe_ring *temp_ring;
759884b4 991 int i, err = 0;
c431f97e 992 u32 new_rx_count, new_tx_count;
9a799d71
AK		 993
994 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
995 return -EINVAL;
996
1f4702aa
AD		 997 new_tx_count = clamp_t(u32, ring->tx_pending,
998 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
9a799d71
AK		 999 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
1000
1f4702aa
AD		 1001 new_rx_count = clamp_t(u32, ring->rx_pending,
1002 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
1003 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
1004
1005 if ((new_tx_count == adapter->tx_ring_count) &&
1006 (new_rx_count == adapter->rx_ring_count)) {
9a799d71
AK		 1007 /* nothing to do */
1008 return 0;
1009 }
1010
d4f80882 1011 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 1012 usleep_range(1000, 2000);
d4f80882 1013
759884b4
AD		 1014 if (!netif_running(adapter->netdev)) {
1015 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 1016 adapter->tx_ring[i]->count = new_tx_count;
759884b4 1017 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 1018 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 1019 adapter->tx_ring_count = new_tx_count;
1020 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 1021 goto clear_reset;
759884b4
AD		 1022 }
1023
1f4702aa
AD		 1024 /* allocate temporary buffer to store rings in */
1025 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
1026 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
1027
1028 if (!temp_ring) {
f9ed8854 1029 err = -ENOMEM;
4a0b9ca0 1030 goto clear_reset;
f9ed8854
MC		 1031 }
1032
1f4702aa
AD		 1033 ixgbe_down(adapter);
1034
1035 /*
1036 * Setup new Tx resources and free the old Tx resources in that order.
1037 * We can then assign the new resources to the rings via a memcpy.
1038 * The advantage to this approach is that we are guaranteed to still
1039 * have resources even in the case of an allocation failure.
1040 */
f9ed8854 1041 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 1042 for (i = 0; i < adapter->num_tx_queues; i++) {
1f4702aa 1043 memcpy(&temp_ring[i], adapter->tx_ring[i],
4a0b9ca0 1044 sizeof(struct ixgbe_ring));
1f4702aa
AD		 1045
1046 temp_ring[i].count = new_tx_count;
1047 err = ixgbe_setup_tx_resources(&temp_ring[i]);
9a799d71 1048 if (err) {
c431f97e
JB		 1049 while (i) {
1050 i--;
1f4702aa 1051 ixgbe_free_tx_resources(&temp_ring[i]);
c431f97e 1052 }
1f4702aa 1053 goto err_setup;
9a799d71 1054 }
9a799d71 1055 }
9a799d71 1056
1f4702aa
AD		 1057 for (i = 0; i < adapter->num_tx_queues; i++) {
1058 ixgbe_free_tx_resources(adapter->tx_ring[i]);
1059
1060 memcpy(adapter->tx_ring[i], &temp_ring[i],
1061 sizeof(struct ixgbe_ring));
1062 }
1063
1064 adapter->tx_ring_count = new_tx_count;
d3fa4721 1065 }
9a799d71 1066
1f4702aa 1067 /* Repeat the process for the Rx rings if needed */
f9ed8854 1068 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 1069 for (i = 0; i < adapter->num_rx_queues; i++) {
1f4702aa 1070 memcpy(&temp_ring[i], adapter->rx_ring[i],
4a0b9ca0 1071 sizeof(struct ixgbe_ring));
1f4702aa
AD		 1072
1073 temp_ring[i].count = new_rx_count;
1074 err = ixgbe_setup_rx_resources(&temp_ring[i]);
9a799d71 1075 if (err) {
c431f97e
JB		 1076 while (i) {
1077 i--;
1f4702aa 1078 ixgbe_free_rx_resources(&temp_ring[i]);
c431f97e 1079 }
9a799d71
AK		 1080 goto err_setup;
1081 }
1f4702aa 1082
9a799d71 1083 }
f9ed8854 1084
1f4702aa
AD		 1085 for (i = 0; i < adapter->num_rx_queues; i++) {
1086 ixgbe_free_rx_resources(adapter->rx_ring[i]);
f9ed8854 1087
1f4702aa
AD		 1088 memcpy(adapter->rx_ring[i], &temp_ring[i],
1089 sizeof(struct ixgbe_ring));
f9ed8854
MC		 1090 }
1091
1f4702aa 1092 adapter->rx_ring_count = new_rx_count;
759884b4 1093 }
4a0b9ca0 1094
f9ed8854 1095err_setup:
1f4702aa
AD		 1096 ixgbe_up(adapter);
1097 vfree(temp_ring);
4a0b9ca0 1098clear_reset:
d4f80882 1099 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1100 return err;
1101}
1102
b9f2c044 1103static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1104{
b9f2c044 1105 switch (sset) {
da4dd0f7
PWJ		 1106 case ETH_SS_TEST:
1107 return IXGBE_TEST_LEN;
b9f2c044
JG		 1108 case ETH_SS_STATS:
1109 return IXGBE_STATS_LEN;
1110 default:
1111 return -EOPNOTSUPP;
1112 }
9a799d71
AK		 1113}
1114
1115static void ixgbe_get_ethtool_stats(struct net_device *netdev,
e7cf745b 1116 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1117{
1118 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1119 struct rtnl_link_stats64 temp;
1120 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1121 unsigned int start;
1122 struct ixgbe_ring *ring;
1123 int i, j;
29c3a050 1124 char *p = NULL;
9a799d71
AK		 1125
1126 ixgbe_update_stats(adapter);
28172739 1127 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1128 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1129 switch (ixgbe_gstrings_stats[i].type) {
1130 case NETDEV_STATS:
28172739 1131 p = (char *) net_stats +
29c3a050
AK		 1132 ixgbe_gstrings_stats[i].stat_offset;
1133 break;
1134 case IXGBE_STATS:
1135 p = (char *) adapter +
1136 ixgbe_gstrings_stats[i].stat_offset;
1137 break;
f752be9c
JH		 1138 default:
1139 data[i] = 0;
1140 continue;
29c3a050
AK		 1141 }
1142
9a799d71 1143 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
e7cf745b 1144 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71 1145 }
bd8a1b12 1146 for (j = 0; j < netdev->num_tx_queues; j++) {
de1036b1 1147 ring = adapter->tx_ring[j];
9cc00b51
JF		 1148 if (!ring) {
1149 data[i] = 0;
1150 data[i+1] = 0;
1151 i += 2;
b4640030 1152#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1153 data[i] = 0;
1154 data[i+1] = 0;
1155 data[i+2] = 0;
1156 i += 3;
1157#endif
9cc00b51
JF		 1158 continue;
1159 }
1160
de1036b1 1161 do {
57a7744e 1162 start = u64_stats_fetch_begin_irq(&ring->syncp);
de1036b1
ED		 1163 data[i] = ring->stats.packets;
1164 data[i+1] = ring->stats.bytes;
57a7744e 1165 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
de1036b1 1166 i += 2;
b4640030 1167#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1168 data[i] = ring->stats.yields;
1169 data[i+1] = ring->stats.misses;
1170 data[i+2] = ring->stats.cleaned;
1171 i += 3;
1172#endif
9a799d71 1173 }
9cc00b51 1174 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
de1036b1 1175 ring = adapter->rx_ring[j];
9cc00b51
JF		 1176 if (!ring) {
1177 data[i] = 0;
1178 data[i+1] = 0;
1179 i += 2;
b4640030 1180#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1181 data[i] = 0;
1182 data[i+1] = 0;
1183 data[i+2] = 0;
1184 i += 3;
1185#endif
9cc00b51
JF		 1186 continue;
1187 }
1188
de1036b1 1189 do {
57a7744e 1190 start = u64_stats_fetch_begin_irq(&ring->syncp);
de1036b1
ED		 1191 data[i] = ring->stats.packets;
1192 data[i+1] = ring->stats.bytes;
57a7744e 1193 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
de1036b1 1194 i += 2;
b4640030 1195#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 1196 data[i] = ring->stats.yields;
1197 data[i+1] = ring->stats.misses;
1198 data[i+2] = ring->stats.cleaned;
1199 i += 3;
1200#endif
9a799d71 1201 }
9cc00b51
JF		 1202
1203 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1204 data[i++] = adapter->stats.pxontxc[j];
1205 data[i++] = adapter->stats.pxofftxc[j];
1206 }
1207 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1208 data[i++] = adapter->stats.pxonrxc[j];
1209 data[i++] = adapter->stats.pxoffrxc[j];
2f90b865 1210 }
9a799d71
AK		 1211}
1212
1213static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
e7cf745b 1214 u8 *data)
9a799d71 1215{
c44ade9e 1216 char *p = (char *)data;
9a799d71
AK		 1217 int i;
1218
1219 switch (stringset) {
da4dd0f7 1220 case ETH_SS_TEST:
d2c47b62
JH		 1221 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1222 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1223 data += ETH_GSTRING_LEN;
1224 }
da4dd0f7 1225 break;
9a799d71
AK		 1226 case ETH_SS_STATS:
1227 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1228 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1229 ETH_GSTRING_LEN);
1230 p += ETH_GSTRING_LEN;
1231 }
9cc00b51 1232 for (i = 0; i < netdev->num_tx_queues; i++) {
9a799d71
AK		 1233 sprintf(p, "tx_queue_%u_packets", i);
1234 p += ETH_GSTRING_LEN;
1235 sprintf(p, "tx_queue_%u_bytes", i);
1236 p += ETH_GSTRING_LEN;
b4640030
JK		 1237#ifdef BP_EXTENDED_STATS
1238 sprintf(p, "tx_queue_%u_bp_napi_yield", i);
7e15b90f 1239 p += ETH_GSTRING_LEN;
b4640030 1240 sprintf(p, "tx_queue_%u_bp_misses", i);
7e15b90f 1241 p += ETH_GSTRING_LEN;
b4640030 1242 sprintf(p, "tx_queue_%u_bp_cleaned", i);
7e15b90f 1243 p += ETH_GSTRING_LEN;
b4640030 1244#endif /* BP_EXTENDED_STATS */
9a799d71 1245 }
9cc00b51 1246 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
9a799d71
AK		 1247 sprintf(p, "rx_queue_%u_packets", i);
1248 p += ETH_GSTRING_LEN;
1249 sprintf(p, "rx_queue_%u_bytes", i);
1250 p += ETH_GSTRING_LEN;
b4640030
JK		 1251#ifdef BP_EXTENDED_STATS
1252 sprintf(p, "rx_queue_%u_bp_poll_yield", i);
7e15b90f 1253 p += ETH_GSTRING_LEN;
b4640030 1254 sprintf(p, "rx_queue_%u_bp_misses", i);
7e15b90f 1255 p += ETH_GSTRING_LEN;
b4640030 1256 sprintf(p, "rx_queue_%u_bp_cleaned", i);
7e15b90f 1257 p += ETH_GSTRING_LEN;
b4640030 1258#endif /* BP_EXTENDED_STATS */
9a799d71 1259 }
9cc00b51
JF		 1260 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1261 sprintf(p, "tx_pb_%u_pxon", i);
1262 p += ETH_GSTRING_LEN;
1263 sprintf(p, "tx_pb_%u_pxoff", i);
1264 p += ETH_GSTRING_LEN;
1265 }
1266 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1267 sprintf(p, "rx_pb_%u_pxon", i);
1268 p += ETH_GSTRING_LEN;
1269 sprintf(p, "rx_pb_%u_pxoff", i);
1270 p += ETH_GSTRING_LEN;
2f90b865 1271 }
b4617240 1272 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1273 break;
1274 }
1275}
1276
da4dd0f7
PWJ		 1277static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1278{
1279 struct ixgbe_hw *hw = &adapter->hw;
1280 bool link_up;
1281 u32 link_speed = 0;
0edd2bdf
MR		 1282
1283 if (ixgbe_removed(hw->hw_addr)) {
1284 *data = 1;
1285 return 1;
1286 }
da4dd0f7
PWJ		 1287 *data = 0;
1288
1289 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1290 if (link_up)
1291 return *data;
1292 else
1293 *data = 1;
1294 return *data;
1295}
1296
1297/* ethtool register test data */
1298struct ixgbe_reg_test {
1299 u16 reg;
1300 u8 array_len;
1301 u8 test_type;
1302 u32 mask;
1303 u32 write;
1304};
1305
1306/* In the hardware, registers are laid out either singly, in arrays
1307 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1308 * most tests take place on arrays or single registers (handled
1309 * as a single-element array) and special-case the tables.
1310 * Table tests are always pattern tests.
1311 *
1312 * We also make provision for some required setup steps by specifying
1313 * registers to be written without any read-back testing.
1314 */
1315
1316#define PATTERN_TEST 1
1317#define SET_READ_TEST 2
1318#define WRITE_NO_TEST 3
1319#define TABLE32_TEST 4
1320#define TABLE64_TEST_LO 5
1321#define TABLE64_TEST_HI 6
1322
1323/* default 82599 register test */
66744500 1324static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1325 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1326 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1327 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1328 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1329 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1330 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1331 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1332 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1333 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1334 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1335 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1336 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1337 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1338 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1339 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1340 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1341 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1342 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1343 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
ca8dfe25 1344 { .reg = 0 }
da4dd0f7
PWJ		 1345};
1346
1347/* default 82598 register test */
66744500 1348static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1349 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1350 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1351 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1352 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1353 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1354 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1355 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1356 /* Enable all four RX queues before testing. */
1357 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1358 /* RDH is read-only for 82598, only test RDT. */
1359 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1360 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1361 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1362 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1363 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1364 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1365 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1366 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1367 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1368 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1369 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1370 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1371 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
ca8dfe25 1372 { .reg = 0 }
da4dd0f7
PWJ		 1373};
1374
95a46011
ET		 1375static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1376 u32 mask, u32 write)
1377{
1378 u32 pat, val, before;
1379 static const u32 test_pattern[] = {
1380 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1381
b0483c8f
MR		 1382 if (ixgbe_removed(adapter->hw.hw_addr)) {
1383 *data = 1;
4e833c59 1384 return true;
b0483c8f 1385 }
95a46011 1386 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
49bde319
MR		 1387 before = ixgbe_read_reg(&adapter->hw, reg);
1388 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1389 val = ixgbe_read_reg(&adapter->hw, reg);
95a46011 1390 if (val != (test_pattern[pat] & write & mask)) {
6ec1b71f 1391 e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
95a46011
ET		 1392 reg, val, (test_pattern[pat] & write & mask));
1393 *data = reg;
49bde319
MR		 1394 ixgbe_write_reg(&adapter->hw, reg, before);
1395 return true;
95a46011 1396 }
49bde319 1397 ixgbe_write_reg(&adapter->hw, reg, before);
95a46011 1398 }
49bde319 1399 return false;
da4dd0f7
PWJ		 1400}
1401
95a46011
ET		 1402static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1403 u32 mask, u32 write)
1404{
1405 u32 val, before;
49bde319 1406
b0483c8f
MR		 1407 if (ixgbe_removed(adapter->hw.hw_addr)) {
1408 *data = 1;
4e833c59 1409 return true;
b0483c8f 1410 }
49bde319
MR		 1411 before = ixgbe_read_reg(&adapter->hw, reg);
1412 ixgbe_write_reg(&adapter->hw, reg, write & mask);
1413 val = ixgbe_read_reg(&adapter->hw, reg);
95a46011 1414 if ((write & mask) != (val & mask)) {
6ec1b71f
JK		 1415 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1416 reg, (val & mask), (write & mask));
95a46011 1417 *data = reg;
49bde319
MR		 1418 ixgbe_write_reg(&adapter->hw, reg, before);
1419 return true;
95a46011 1420 }
49bde319
MR		 1421 ixgbe_write_reg(&adapter->hw, reg, before);
1422 return false;
da4dd0f7
PWJ		 1423}
1424
1425static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1426{
66744500 1427 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1428 u32 value, before, after;
1429 u32 i, toggle;
1430
b0483c8f
MR		 1431 if (ixgbe_removed(adapter->hw.hw_addr)) {
1432 e_err(drv, "Adapter removed - register test blocked\n");
1433 *data = 1;
1434 return 1;
1435 }
bd508178
AD		 1436 switch (adapter->hw.mac.type) {
1437 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1438 toggle = 0x7FFFF3FF;
1439 test = reg_test_82598;
bd508178
AD		 1440 break;
1441 case ixgbe_mac_82599EB:
b93a2226 1442 case ixgbe_mac_X540:
9a75a1ac
DS		 1443 case ixgbe_mac_X550:
1444 case ixgbe_mac_X550EM_x:
49425dfc 1445 case ixgbe_mac_x550em_a:
bd508178
AD		 1446 toggle = 0x7FFFF30F;
1447 test = reg_test_82599;
1448 break;
1449 default:
1450 *data = 1;
1451 return 1;
da4dd0f7
PWJ		 1452 }
1453
1454 /*
1455 * Because the status register is such a special case,
1456 * we handle it separately from the rest of the register
1457 * tests. Some bits are read-only, some toggle, and some
1458 * are writeable on newer MACs.
1459 */
49bde319
MR		 1460 before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1461 value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1462 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1463 after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
da4dd0f7 1464 if (value != after) {
6ec1b71f
JK		 1465 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1466 after, value);
da4dd0f7
PWJ		 1467 *data = 1;
1468 return 1;
1469 }
1470 /* restore previous status */
49bde319 1471 ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
da4dd0f7
PWJ		 1472
1473 /*
1474 * Perform the remainder of the register test, looping through
1475 * the test table until we either fail or reach the null entry.
1476 */
1477 while (test->reg) {
1478 for (i = 0; i < test->array_len; i++) {
49bde319
MR		 1479 bool b = false;
1480
da4dd0f7
PWJ		 1481 switch (test->test_type) {
1482 case PATTERN_TEST:
49bde319
MR		 1483 b = reg_pattern_test(adapter, data,
1484 test->reg + (i * 0x40),
1485 test->mask,
1486 test->write);
da4dd0f7
PWJ		 1487 break;
1488 case SET_READ_TEST:
49bde319
MR		 1489 b = reg_set_and_check(adapter, data,
1490 test->reg + (i * 0x40),
1491 test->mask,
1492 test->write);
da4dd0f7
PWJ		 1493 break;
1494 case WRITE_NO_TEST:
49bde319
MR		 1495 ixgbe_write_reg(&adapter->hw,
1496 test->reg + (i * 0x40),
1497 test->write);
da4dd0f7
PWJ		 1498 break;
1499 case TABLE32_TEST:
49bde319
MR		 1500 b = reg_pattern_test(adapter, data,
1501 test->reg + (i * 4),
1502 test->mask,
1503 test->write);
da4dd0f7
PWJ		 1504 break;
1505 case TABLE64_TEST_LO:
49bde319
MR		 1506 b = reg_pattern_test(adapter, data,
1507 test->reg + (i * 8),
1508 test->mask,
1509 test->write);
da4dd0f7
PWJ		 1510 break;
1511 case TABLE64_TEST_HI:
49bde319
MR		 1512 b = reg_pattern_test(adapter, data,
1513 (test->reg + 4) + (i * 8),
1514 test->mask,
1515 test->write);
da4dd0f7
PWJ		 1516 break;
1517 }
49bde319
MR		 1518 if (b)
1519 return 1;
da4dd0f7
PWJ		 1520 }
1521 test++;
1522 }
1523
1524 *data = 0;
1525 return 0;
1526}
1527
1528static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1529{
1530 struct ixgbe_hw *hw = &adapter->hw;
1531 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1532 *data = 1;
1533 else
1534 *data = 0;
1535 return *data;
1536}
1537
1538static irqreturn_t ixgbe_test_intr(int irq, void *data)
1539{
1540 struct net_device *netdev = (struct net_device *) data;
1541 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1542
1543 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1544
1545 return IRQ_HANDLED;
1546}
1547
1548static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1549{
1550 struct net_device *netdev = adapter->netdev;
1551 u32 mask, i = 0, shared_int = true;
1552 u32 irq = adapter->pdev->irq;
1553
1554 *data = 0;
1555
1556 /* Hook up test interrupt handler just for this test */
1557 if (adapter->msix_entries) {
1558 /* NOTE: we don't test MSI-X interrupts here, yet */
1559 return 0;
1560 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1561 shared_int = false;
a0607fd3 1562 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1563 netdev)) {
1564 *data = 1;
1565 return -1;
1566 }
a0607fd3 1567 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
e7cf745b 1568 netdev->name, netdev)) {
da4dd0f7 1569 shared_int = false;
a0607fd3 1570 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
e7cf745b 1571 netdev->name, netdev)) {
da4dd0f7
PWJ		 1572 *data = 1;
1573 return -1;
1574 }
396e799c
ET		 1575 e_info(hw, "testing %s interrupt\n", shared_int ?
1576 "shared" : "unshared");
da4dd0f7
PWJ		 1577
1578 /* Disable all the interrupts */
1579 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1580 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1581 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1582
1583 /* Test each interrupt */
1584 for (; i < 10; i++) {
1585 /* Interrupt to test */
b4f47a48 1586 mask = BIT(i);
da4dd0f7
PWJ		 1587
1588 if (!shared_int) {
1589 /*
1590 * Disable the interrupts to be reported in
1591 * the cause register and then force the same
1592 * interrupt and see if one gets posted. If
1593 * an interrupt was posted to the bus, the
1594 * test failed.
1595 */
1596 adapter->test_icr = 0;
1597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
e7cf745b 1598 ~mask & 0x00007FFF);
da4dd0f7 1599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
e7cf745b 1600 ~mask & 0x00007FFF);
945a5151 1601 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1602 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1603
1604 if (adapter->test_icr & mask) {
1605 *data = 3;
1606 break;
1607 }
1608 }
1609
1610 /*
1611 * Enable the interrupt to be reported in the cause
1612 * register and then force the same interrupt and see
1613 * if one gets posted. If an interrupt was not posted
1614 * to the bus, the test failed.
1615 */
1616 adapter->test_icr = 0;
1617 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1618 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
945a5151 1619 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1620 usleep_range(10000, 20000);
da4dd0f7 1621
8105ecdf 1622 if (!(adapter->test_icr & mask)) {
da4dd0f7
PWJ		 1623 *data = 4;
1624 break;
1625 }
1626
1627 if (!shared_int) {
1628 /*
1629 * Disable the other interrupts to be reported in
1630 * the cause register and then force the other
1631 * interrupts and see if any get posted. If
1632 * an interrupt was posted to the bus, the
1633 * test failed.
1634 */
1635 adapter->test_icr = 0;
1636 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
e7cf745b 1637 ~mask & 0x00007FFF);
da4dd0f7 1638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
e7cf745b 1639 ~mask & 0x00007FFF);
945a5151 1640 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1641 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1642
1643 if (adapter->test_icr) {
1644 *data = 5;
1645 break;
1646 }
1647 }
1648 }
1649
1650 /* Disable all the interrupts */
1651 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1652 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1653 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1654
1655 /* Unhook test interrupt handler */
1656 free_irq(irq, netdev);
1657
1658 return *data;
1659}
1660
1661static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1662{
1663 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1664 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1665 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1666 u32 reg_ctl;
da4dd0f7
PWJ		 1667
1668 /* shut down the DMA engines now so they can be reinitialized later */
1669
1670 /* first Rx */
1f9ac57c 1671 hw->mac.ops.disable_rx(hw);
2d39d576 1672 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1673
1674 /* now Tx */
84418e3b 1675 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1676 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1677 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1678
bd508178
AD		 1679 switch (hw->mac.type) {
1680 case ixgbe_mac_82599EB:
b93a2226 1681 case ixgbe_mac_X540:
9a75a1ac
DS		 1682 case ixgbe_mac_X550:
1683 case ixgbe_mac_X550EM_x:
49425dfc 1684 case ixgbe_mac_x550em_a:
da4dd0f7
PWJ		 1685 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1686 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1687 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1688 break;
1689 default:
1690 break;
da4dd0f7
PWJ		 1691 }
1692
1693 ixgbe_reset(adapter);
1694
b6ec895e
AD		 1695 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1696 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1697}
1698
1699static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1700{
1701 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1702 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1f9ac57c 1703 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1704 u32 rctl, reg_data;
84418e3b
AD		 1705 int ret_val;
1706 int err;
da4dd0f7
PWJ		 1707
1708 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1709 tx_ring->count = IXGBE_DEFAULT_TXD;
1710 tx_ring->queue_index = 0;
b6ec895e 1711 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1712 tx_ring->netdev = adapter->netdev;
84418e3b 1713 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
da4dd0f7 1714
b6ec895e 1715 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1716 if (err)
1717 return 1;
da4dd0f7 1718
bd508178
AD		 1719 switch (adapter->hw.mac.type) {
1720 case ixgbe_mac_82599EB:
b93a2226 1721 case ixgbe_mac_X540:
9a75a1ac
DS		 1722 case ixgbe_mac_X550:
1723 case ixgbe_mac_X550EM_x:
49425dfc 1724 case ixgbe_mac_x550em_a:
da4dd0f7
PWJ		 1725 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1726 reg_data |= IXGBE_DMATXCTL_TE;
1727 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1728 break;
1729 default:
1730 break;
da4dd0f7 1731 }
f4ec443b 1732
84418e3b 1733 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1734
1735 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1736 rx_ring->count = IXGBE_DEFAULT_RXD;
1737 rx_ring->queue_index = 0;
b6ec895e 1738 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1739 rx_ring->netdev = adapter->netdev;
84418e3b 1740 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
84418e3b 1741
b6ec895e 1742 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1743 if (err) {
da4dd0f7
PWJ		 1744 ret_val = 4;
1745 goto err_nomem;
1746 }
1747
1f9ac57c 1748 hw->mac.ops.disable_rx(hw);
da4dd0f7 1749
84418e3b 1750 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7 1751
1f9ac57c
DS		 1752 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1753 rctl |= IXGBE_RXCTRL_DMBYPS;
da4dd0f7
PWJ		 1754 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1755
1f9ac57c
DS		 1756 hw->mac.ops.enable_rx(hw);
1757
da4dd0f7
PWJ		 1758 return 0;
1759
1760err_nomem:
1761 ixgbe_free_desc_rings(adapter);
1762 return ret_val;
1763}
1764
1765static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1766{
1767 struct ixgbe_hw *hw = &adapter->hw;
1768 u32 reg_data;
1769
e7fd9253 1770
84418e3b 1771 /* Setup MAC loopback */
26b4742b 1772 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
da4dd0f7 1773 reg_data |= IXGBE_HLREG0_LPBK;
35c7f8a1 1774 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
da4dd0f7 1775
35c7f8a1 1776 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
84418e3b 1777 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
35c7f8a1 1778 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
84418e3b 1779
9a75a1ac
DS		 1780 /* X540 and X550 needs to set the MACC.FLU bit to force link up */
1781 switch (adapter->hw.mac.type) {
1782 case ixgbe_mac_X540:
1783 case ixgbe_mac_X550:
1784 case ixgbe_mac_X550EM_x:
49425dfc 1785 case ixgbe_mac_x550em_a:
26b4742b
ET		 1786 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1787 reg_data |= IXGBE_MACC_FLU;
1788 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
9a75a1ac
DS		 1789 break;
1790 default:
26b4742b
ET		 1791 if (hw->mac.orig_autoc) {
1792 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1793 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1794 } else {
1795 return 10;
1796 }
1797 }
35c7f8a1 1798 IXGBE_WRITE_FLUSH(hw);
032b4325 1799 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1800
1801 /* Disable Atlas Tx lanes; re-enabled in reset path */
1802 if (hw->mac.type == ixgbe_mac_82598EB) {
1803 u8 atlas;
1804
1805 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1806 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1807 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1808
1809 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1810 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1811 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1812
1813 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1814 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1815 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1816
1817 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1818 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1819 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1820 }
1821
1822 return 0;
1823}
1824
1825static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1826{
1827 u32 reg_data;
1828
1829 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1830 reg_data &= ~IXGBE_HLREG0_LPBK;
1831 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1832}
1833
1834static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
3832b26e 1835 unsigned int frame_size)
da4dd0f7
PWJ		 1836{
1837 memset(skb->data, 0xFF, frame_size);
3832b26e
AD		 1838 frame_size >>= 1;
1839 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1840 memset(&skb->data[frame_size + 10], 0xBE, 1);
1841 memset(&skb->data[frame_size + 12], 0xAF, 1);
da4dd0f7
PWJ		 1842}
1843
3832b26e
AD		 1844static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1845 unsigned int frame_size)
da4dd0f7 1846{
3832b26e
AD		 1847 unsigned char *data;
1848 bool match = true;
1849
1850 frame_size >>= 1;
1851
f800326d 1852 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
3832b26e
AD		 1853
1854 if (data[3] != 0xFF ||
1855 data[frame_size + 10] != 0xBE ||
1856 data[frame_size + 12] != 0xAF)
1857 match = false;
1858
f800326d
AD		 1859 kunmap(rx_buffer->page);
1860
3832b26e 1861 return match;
da4dd0f7
PWJ		 1862}
1863
fc77dc3c 1864static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
3832b26e
AD		 1865 struct ixgbe_ring *tx_ring,
1866 unsigned int size)
84418e3b
AD		 1867{
1868 union ixgbe_adv_rx_desc *rx_desc;
3832b26e
AD		 1869 struct ixgbe_rx_buffer *rx_buffer;
1870 struct ixgbe_tx_buffer *tx_buffer;
84418e3b
AD		 1871 u16 rx_ntc, tx_ntc, count = 0;
1872
1873 /* initialize next to clean and descriptor values */
1874 rx_ntc = rx_ring->next_to_clean;
1875 tx_ntc = tx_ring->next_to_clean;
e4f74028 1876 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b 1877
3832b26e 1878 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
84418e3b 1879 /* check Rx buffer */
3832b26e 1880 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
84418e3b 1881
f800326d
AD		 1882 /* sync Rx buffer for CPU read */
1883 dma_sync_single_for_cpu(rx_ring->dev,
1884 rx_buffer->dma,
1885 ixgbe_rx_bufsz(rx_ring),
1886 DMA_FROM_DEVICE);
84418e3b
AD		 1887
1888 /* verify contents of skb */
3832b26e 1889 if (ixgbe_check_lbtest_frame(rx_buffer, size))
84418e3b
AD		 1890 count++;
1891
f800326d
AD		 1892 /* sync Rx buffer for device write */
1893 dma_sync_single_for_device(rx_ring->dev,
1894 rx_buffer->dma,
1895 ixgbe_rx_bufsz(rx_ring),
1896 DMA_FROM_DEVICE);
1897
84418e3b 1898 /* unmap buffer on Tx side */
3832b26e
AD		 1899 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1900 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
84418e3b
AD		 1901
1902 /* increment Rx/Tx next to clean counters */
1903 rx_ntc++;
1904 if (rx_ntc == rx_ring->count)
1905 rx_ntc = 0;
1906 tx_ntc++;
1907 if (tx_ntc == tx_ring->count)
1908 tx_ntc = 0;
1909
1910 /* fetch next descriptor */
e4f74028 1911 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b
AD		 1912 }
1913
dad8a3b3
JF		 1914 netdev_tx_reset_queue(txring_txq(tx_ring));
1915
84418e3b 1916 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1917 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1918 rx_ring->next_to_clean = rx_ntc;
1919 tx_ring->next_to_clean = tx_ntc;
1920
1921 return count;
1922}
1923
da4dd0f7
PWJ		 1924static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1925{
1926 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1927 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1928 int i, j, lc, good_cnt, ret_val = 0;
1929 unsigned int size = 1024;
1930 netdev_tx_t tx_ret_val;
1931 struct sk_buff *skb;
91ffdc84
ET		 1932 u32 flags_orig = adapter->flags;
1933
1934 /* DCB can modify the frames on Tx */
1935 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
84418e3b
AD		 1936
1937 /* allocate test skb */
1938 skb = alloc_skb(size, GFP_KERNEL);
1939 if (!skb)
1940 return 11;
da4dd0f7 1941
84418e3b
AD		 1942 /* place data into test skb */
1943 ixgbe_create_lbtest_frame(skb, size);
1944 skb_put(skb, size);
da4dd0f7
PWJ		 1945
1946 /*
1947 * Calculate the loop count based on the largest descriptor ring
1948 * The idea is to wrap the largest ring a number of times using 64
1949 * send/receive pairs during each loop
1950 */
1951
1952 if (rx_ring->count <= tx_ring->count)
1953 lc = ((tx_ring->count / 64) * 2) + 1;
1954 else
1955 lc = ((rx_ring->count / 64) * 2) + 1;
1956
da4dd0f7 1957 for (j = 0; j <= lc; j++) {
84418e3b 1958 /* reset count of good packets */
da4dd0f7 1959 good_cnt = 0;
84418e3b
AD		 1960
1961 /* place 64 packets on the transmit queue*/
1962 for (i = 0; i < 64; i++) {
1963 skb_get(skb);
1964 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1965 adapter,
1966 tx_ring);
1967 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1968 good_cnt++;
84418e3b
AD		 1969 }
1970
da4dd0f7 1971 if (good_cnt != 64) {
84418e3b 1972 ret_val = 12;
da4dd0f7
PWJ		 1973 break;
1974 }
84418e3b
AD		 1975
1976 /* allow 200 milliseconds for packets to go from Tx to Rx */
1977 msleep(200);
1978
fc77dc3c 1979 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1980 if (good_cnt != 64) {
1981 ret_val = 13;
da4dd0f7
PWJ		 1982 break;
1983 }
1984 }
1985
84418e3b
AD		 1986 /* free the original skb */
1987 kfree_skb(skb);
91ffdc84 1988 adapter->flags = flags_orig;
84418e3b 1989
da4dd0f7
PWJ		 1990 return ret_val;
1991}
1992
1993static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1994{
1995 *data = ixgbe_setup_desc_rings(adapter);
1996 if (*data)
1997 goto out;
1998 *data = ixgbe_setup_loopback_test(adapter);
1999 if (*data)
2000 goto err_loopback;
2001 *data = ixgbe_run_loopback_test(adapter);
2002 ixgbe_loopback_cleanup(adapter);
2003
2004err_loopback:
2005 ixgbe_free_desc_rings(adapter);
2006out:
2007 return *data;
2008}
2009
2010static void ixgbe_diag_test(struct net_device *netdev,
e7cf745b 2011 struct ethtool_test *eth_test, u64 *data)
da4dd0f7
PWJ		 2012{
2013 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2014 bool if_running = netif_running(netdev);
2015
b0483c8f
MR		 2016 if (ixgbe_removed(adapter->hw.hw_addr)) {
2017 e_err(hw, "Adapter removed - test blocked\n");
2018 data[0] = 1;
2019 data[1] = 1;
2020 data[2] = 1;
2021 data[3] = 1;
0edd2bdf 2022 data[4] = 1;
b0483c8f
MR		 2023 eth_test->flags |= ETH_TEST_FL_FAILED;
2024 return;
2025 }
da4dd0f7
PWJ		 2026 set_bit(__IXGBE_TESTING, &adapter->state);
2027 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
4ec375b1
ET		 2028 struct ixgbe_hw *hw = &adapter->hw;
2029
e7d481a6
GR		 2030 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2031 int i;
2032 for (i = 0; i < adapter->num_vfs; i++) {
2033 if (adapter->vfinfo[i].clear_to_send) {
6ec1b71f 2034 netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
e7d481a6
GR		 2035 data[0] = 1;
2036 data[1] = 1;
2037 data[2] = 1;
2038 data[3] = 1;
0edd2bdf 2039 data[4] = 1;
e7d481a6
GR		 2040 eth_test->flags |= ETH_TEST_FL_FAILED;
2041 clear_bit(__IXGBE_TESTING,
2042 &adapter->state);
2043 goto skip_ol_tests;
2044 }
2045 }
2046 }
2047
dfcc4615
JK		 2048 /* Offline tests */
2049 e_info(hw, "offline testing starting\n");
2050
dfcc4615
JK		 2051 /* Link test performed before hardware reset so autoneg doesn't
2052 * interfere with test result
2053 */
2054 if (ixgbe_link_test(adapter, &data[4]))
2055 eth_test->flags |= ETH_TEST_FL_FAILED;
2056
4ec375b1
ET		 2057 if (if_running)
2058 /* indicate we're in test mode */
6c211fe1 2059 ixgbe_close(netdev);
4ec375b1
ET		 2060 else
2061 ixgbe_reset(adapter);
2062
396e799c 2063 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 2064 if (ixgbe_reg_test(adapter, &data[0]))
2065 eth_test->flags |= ETH_TEST_FL_FAILED;
2066
2067 ixgbe_reset(adapter);
396e799c 2068 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 2069 if (ixgbe_eeprom_test(adapter, &data[1]))
2070 eth_test->flags |= ETH_TEST_FL_FAILED;
2071
2072 ixgbe_reset(adapter);
396e799c 2073 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 2074 if (ixgbe_intr_test(adapter, &data[2]))
2075 eth_test->flags |= ETH_TEST_FL_FAILED;
2076
bdbec4b8
GR		 2077 /* If SRIOV or VMDq is enabled then skip MAC
2078 * loopback diagnostic. */
2079 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2080 IXGBE_FLAG_VMDQ_ENABLED)) {
6ec1b71f 2081 e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
bdbec4b8
GR		 2082 data[3] = 0;
2083 goto skip_loopback;
2084 }
2085
da4dd0f7 2086 ixgbe_reset(adapter);
396e799c 2087 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 2088 if (ixgbe_loopback_test(adapter, &data[3]))
2089 eth_test->flags |= ETH_TEST_FL_FAILED;
2090
bdbec4b8 2091skip_loopback:
da4dd0f7
PWJ		 2092 ixgbe_reset(adapter);
2093
dfcc4615 2094 /* clear testing bit and return adapter to previous state */
da4dd0f7
PWJ		 2095 clear_bit(__IXGBE_TESTING, &adapter->state);
2096 if (if_running)
6c211fe1 2097 ixgbe_open(netdev);
4ec375b1
ET		 2098 else if (hw->mac.ops.disable_tx_laser)
2099 hw->mac.ops.disable_tx_laser(hw);
da4dd0f7 2100 } else {
396e799c 2101 e_info(hw, "online testing starting\n");
dfcc4615 2102
da4dd0f7
PWJ		 2103 /* Online tests */
2104 if (ixgbe_link_test(adapter, &data[4]))
2105 eth_test->flags |= ETH_TEST_FL_FAILED;
2106
dfcc4615 2107 /* Offline tests aren't run; pass by default */
da4dd0f7
PWJ		 2108 data[0] = 0;
2109 data[1] = 0;
2110 data[2] = 0;
2111 data[3] = 0;
2112
2113 clear_bit(__IXGBE_TESTING, &adapter->state);
2114 }
dfcc4615 2115
e7d481a6 2116skip_ol_tests:
da4dd0f7
PWJ		 2117 msleep_interruptible(4 * 1000);
2118}
9a799d71 2119
d6c519e1 2120static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
e7cf745b 2121 struct ethtool_wolinfo *wol)
d6c519e1
AD		 2122{
2123 struct ixgbe_hw *hw = &adapter->hw;
8e2813f5 2124 int retval = 0;
c23f5b6b 2125
8e2813f5
JK		 2126 /* WOL not supported for all devices */
2127 if (!ixgbe_wol_supported(adapter, hw->device_id,
2128 hw->subsystem_device_id)) {
2129 retval = 1;
d6c519e1 2130 wol->supported = 0;
d6c519e1
AD		 2131 }
2132
2133 return retval;
2134}
2135
9a799d71 2136static void ixgbe_get_wol(struct net_device *netdev,
e7cf745b 2137 struct ethtool_wolinfo *wol)
9a799d71 2138{
e63d9762
PW		 2139 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2140
2141 wol->supported = WAKE_UCAST | WAKE_MCAST |
e7cf745b 2142 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 2143 wol->wolopts = 0;
2144
d6c519e1
AD		 2145 if (ixgbe_wol_exclusion(adapter, wol) ||
2146 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 2147 return;
2148
2149 if (adapter->wol & IXGBE_WUFC_EX)
2150 wol->wolopts |= WAKE_UCAST;
2151 if (adapter->wol & IXGBE_WUFC_MC)
2152 wol->wolopts |= WAKE_MCAST;
2153 if (adapter->wol & IXGBE_WUFC_BC)
2154 wol->wolopts |= WAKE_BCAST;
2155 if (adapter->wol & IXGBE_WUFC_MAG)
2156 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 2157}
2158
e63d9762
PW		 2159static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2160{
2161 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2162
2163 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2164 return -EOPNOTSUPP;
2165
d6c519e1
AD		 2166 if (ixgbe_wol_exclusion(adapter, wol))
2167 return wol->wolopts ? -EOPNOTSUPP : 0;
2168
e63d9762
PW		 2169 adapter->wol = 0;
2170
2171 if (wol->wolopts & WAKE_UCAST)
2172 adapter->wol |= IXGBE_WUFC_EX;
2173 if (wol->wolopts & WAKE_MCAST)
2174 adapter->wol |= IXGBE_WUFC_MC;
2175 if (wol->wolopts & WAKE_BCAST)
2176 adapter->wol |= IXGBE_WUFC_BC;
2177 if (wol->wolopts & WAKE_MAGIC)
2178 adapter->wol |= IXGBE_WUFC_MAG;
2179
2180 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2181
2182 return 0;
2183}
2184
9a799d71
AK		 2185static int ixgbe_nway_reset(struct net_device *netdev)
2186{
2187 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2188
d4f80882
AV		 2189 if (netif_running(netdev))
2190 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2191
2192 return 0;
2193}
2194
66e6961c
ET		 2195static int ixgbe_set_phys_id(struct net_device *netdev,
2196 enum ethtool_phys_id_state state)
9a799d71
AK		 2197{
2198 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2199 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2200
66e6961c
ET		 2201 switch (state) {
2202 case ETHTOOL_ID_ACTIVE:
2203 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2204 return 2;
9a799d71 2205
66e6961c 2206 case ETHTOOL_ID_ON:
003287e0 2207 hw->mac.ops.led_on(hw, hw->bus.func);
66e6961c
ET		 2208 break;
2209
2210 case ETHTOOL_ID_OFF:
003287e0 2211 hw->mac.ops.led_off(hw, hw->bus.func);
66e6961c 2212 break;
9a799d71 2213
66e6961c
ET		 2214 case ETHTOOL_ID_INACTIVE:
2215 /* Restore LED settings */
2216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2217 break;
2218 }
9a799d71
AK		 2219
2220 return 0;
2221}
2222
2223static int ixgbe_get_coalesce(struct net_device *netdev,
e7cf745b 2224 struct ethtool_coalesce *ec)
9a799d71
AK		 2225{
2226 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2227
30efa5a3 2228 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2229 if (adapter->rx_itr_setting <= 1)
2230 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2231 else
2232 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
f7554a2b 2233
cfb3f91a 2234 /* if in mixed tx/rx queues per vector mode, report only rx settings */
08c8833b 2235 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
cfb3f91a
SN		 2236 return 0;
2237
f7554a2b 2238 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2239 if (adapter->tx_itr_setting <= 1)
2240 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2241 else
2242 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
f7554a2b 2243
9a799d71
AK		 2244 return 0;
2245}
2246
80fba3f4
AD		 2247/*
2248 * this function must be called before setting the new value of
2249 * rx_itr_setting
2250 */
567d2de2 2251static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
80fba3f4
AD		 2252{
2253 struct net_device *netdev = adapter->netdev;
2254
567d2de2
AD		 2255 /* nothing to do if LRO or RSC are not enabled */
2256 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2257 !(netdev->features & NETIF_F_LRO))
80fba3f4
AD		 2258 return false;
2259
567d2de2
AD		 2260 /* check the feature flag value and enable RSC if necessary */
2261 if (adapter->rx_itr_setting == 1 ||
2262 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2263 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
80fba3f4 2264 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6ec1b71f 2265 e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
80fba3f4
AD		 2266 return true;
2267 }
567d2de2
AD		 2268 /* if interrupt rate is too high then disable RSC */
2269 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2270 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2271 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2272 return true;
80fba3f4
AD		 2273 }
2274 return false;
2275}
2276
9a799d71 2277static int ixgbe_set_coalesce(struct net_device *netdev,
e7cf745b 2278 struct ethtool_coalesce *ec)
9a799d71
AK		 2279{
2280 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2281 struct ixgbe_q_vector *q_vector;
30efa5a3 2282 int i;
67da097e 2283 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
ef021194 2284 bool need_reset = false;
9a799d71 2285
67da097e
ET		 2286 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2287 /* reject Tx specific changes in case of mixed RxTx vectors */
2288 if (ec->tx_coalesce_usecs)
2289 return -EINVAL;
2290 tx_itr_prev = adapter->rx_itr_setting;
2291 } else {
2292 tx_itr_prev = adapter->tx_itr_setting;
2293 }
f7554a2b 2294
d5bf4f67
ET		 2295 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2296 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2297 return -EINVAL;
30efa5a3 2298
d5bf4f67
ET		 2299 if (ec->rx_coalesce_usecs > 1)
2300 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2301 else
2302 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
f7554a2b 2303
d5bf4f67
ET		 2304 if (adapter->rx_itr_setting == 1)
2305 rx_itr_param = IXGBE_20K_ITR;
2306 else
2307 rx_itr_param = adapter->rx_itr_setting;
f7554a2b 2308
d5bf4f67
ET		 2309 if (ec->tx_coalesce_usecs > 1)
2310 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2311 else
2312 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
f7554a2b 2313
d5bf4f67 2314 if (adapter->tx_itr_setting == 1)
8ac34f10 2315 tx_itr_param = IXGBE_12K_ITR;
d5bf4f67
ET		 2316 else
2317 tx_itr_param = adapter->tx_itr_setting;
f7554a2b 2318
67da097e
ET		 2319 /* mixed Rx/Tx */
2320 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2321 adapter->tx_itr_setting = adapter->rx_itr_setting;
2322
67da097e 2323 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2e010381 2324 if ((adapter->tx_itr_setting != 1) &&
67da097e
ET		 2325 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2326 if ((tx_itr_prev == 1) ||
2e010381 2327 (tx_itr_prev >= IXGBE_100K_ITR))
67da097e
ET		 2328 need_reset = true;
2329 } else {
2e010381 2330 if ((tx_itr_prev != 1) &&
67da097e
ET		 2331 (tx_itr_prev < IXGBE_100K_ITR))
2332 need_reset = true;
2333 }
ffefa9f6 2334
567d2de2 2335 /* check the old value and enable RSC if necessary */
67da097e 2336 need_reset |= ixgbe_update_rsc(adapter);
567d2de2 2337
49c7ffbe 2338 for (i = 0; i < adapter->num_q_vectors; i++) {
d5bf4f67 2339 q_vector = adapter->q_vector[i];
d5bf4f67
ET		 2340 if (q_vector->tx.count && !q_vector->rx.count)
2341 /* tx only */
2342 q_vector->itr = tx_itr_param;
2343 else
2344 /* rx only or mixed */
2345 q_vector->itr = rx_itr_param;
fe49f04a 2346 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2347 }
2348
ef021194
JB		 2349 /*
2350 * do reset here at the end to make sure EITR==0 case is handled
2351 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2352 * also locks in RSC enable/disable which requires reset
2353 */
c988ee82
ET		 2354 if (need_reset)
2355 ixgbe_do_reset(netdev);
ef021194 2356
9a799d71
AK		 2357 return 0;
2358}
2359
3e05334f
AD		 2360static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2361 struct ethtool_rxnfc *cmd)
2362{
2363 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2364 struct ethtool_rx_flow_spec *fsp =
2365 (struct ethtool_rx_flow_spec *)&cmd->fs;
b67bfe0d 2366 struct hlist_node *node2;
3e05334f
AD		 2367 struct ixgbe_fdir_filter *rule = NULL;
2368
2369 /* report total rule count */
2370 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2371
b67bfe0d 2372 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2373 &adapter->fdir_filter_list, fdir_node) {
2374 if (fsp->location <= rule->sw_idx)
2375 break;
2376 }
2377
2378 if (!rule || fsp->location != rule->sw_idx)
2379 return -EINVAL;
2380
2381 /* fill out the flow spec entry */
2382
2383 /* set flow type field */
2384 switch (rule->filter.formatted.flow_type) {
2385 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2386 fsp->flow_type = TCP_V4_FLOW;
2387 break;
2388 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2389 fsp->flow_type = UDP_V4_FLOW;
2390 break;
2391 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2392 fsp->flow_type = SCTP_V4_FLOW;
2393 break;
2394 case IXGBE_ATR_FLOW_TYPE_IPV4:
2395 fsp->flow_type = IP_USER_FLOW;
2396 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2397 fsp->h_u.usr_ip4_spec.proto = 0;
2398 fsp->m_u.usr_ip4_spec.proto = 0;
2399 break;
2400 default:
2401 return -EINVAL;
2402 }
2403
2404 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2405 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2406 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2407 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2408 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2409 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2410 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2411 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2412 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2413 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2414 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2415 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2416 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2417 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2418 fsp->flow_type |= FLOW_EXT;
2419
2420 /* record action */
2421 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2422 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2423 else
2424 fsp->ring_cookie = rule->action;
2425
2426 return 0;
2427}
2428
2429static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2430 struct ethtool_rxnfc *cmd,
2431 u32 *rule_locs)
2432{
b67bfe0d 2433 struct hlist_node *node2;
3e05334f
AD		 2434 struct ixgbe_fdir_filter *rule;
2435 int cnt = 0;
2436
2437 /* report total rule count */
2438 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2439
b67bfe0d 2440 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2441 &adapter->fdir_filter_list, fdir_node) {
2442 if (cnt == cmd->rule_cnt)
2443 return -EMSGSIZE;
2444 rule_locs[cnt] = rule->sw_idx;
2445 cnt++;
2446 }
2447
473e64ee
BH		 2448 cmd->rule_cnt = cnt;
2449
3e05334f
AD		 2450 return 0;
2451}
2452
ef6afc0c
AD		 2453static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2454 struct ethtool_rxnfc *cmd)
2455{
2456 cmd->data = 0;
2457
ef6afc0c
AD		 2458 /* Report default options for RSS on ixgbe */
2459 switch (cmd->flow_type) {
2460 case TCP_V4_FLOW:
2461 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
3bf2379a 2462 /* fallthrough */
ef6afc0c
AD		 2463 case UDP_V4_FLOW:
2464 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2465 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
3bf2379a 2466 /* fallthrough */
ef6afc0c
AD		 2467 case SCTP_V4_FLOW:
2468 case AH_ESP_V4_FLOW:
2469 case AH_V4_FLOW:
2470 case ESP_V4_FLOW:
2471 case IPV4_FLOW:
2472 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2473 break;
2474 case TCP_V6_FLOW:
2475 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
3bf2379a 2476 /* fallthrough */
ef6afc0c
AD		 2477 case UDP_V6_FLOW:
2478 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2479 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
3bf2379a 2480 /* fallthrough */
ef6afc0c
AD		 2481 case SCTP_V6_FLOW:
2482 case AH_ESP_V6_FLOW:
2483 case AH_V6_FLOW:
2484 case ESP_V6_FLOW:
2485 case IPV6_FLOW:
2486 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2487 break;
2488 default:
2489 return -EINVAL;
2490 }
2491
2492 return 0;
2493}
2494
91cd94bf 2495static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
815c7db5 2496 u32 *rule_locs)
91cd94bf
AD		 2497{
2498 struct ixgbe_adapter *adapter = netdev_priv(dev);
2499 int ret = -EOPNOTSUPP;
2500
2501 switch (cmd->cmd) {
2502 case ETHTOOL_GRXRINGS:
2503 cmd->data = adapter->num_rx_queues;
2504 ret = 0;
2505 break;
3e05334f
AD		 2506 case ETHTOOL_GRXCLSRLCNT:
2507 cmd->rule_cnt = adapter->fdir_filter_count;
2508 ret = 0;
2509 break;
2510 case ETHTOOL_GRXCLSRULE:
2511 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2512 break;
2513 case ETHTOOL_GRXCLSRLALL:
815c7db5 2514 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
3e05334f 2515 break;
ef6afc0c
AD		 2516 case ETHTOOL_GRXFH:
2517 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2518 break;
91cd94bf
AD		 2519 default:
2520 break;
2521 }
2522
2523 return ret;
2524}
2525
b82b17d9
JF		 2526int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2527 struct ixgbe_fdir_filter *input,
2528 u16 sw_idx)
e4911d57
AD		 2529{
2530 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d
SL		 2531 struct hlist_node *node2;
2532 struct ixgbe_fdir_filter *rule, *parent;
e4911d57
AD		 2533 int err = -EINVAL;
2534
2535 parent = NULL;
2536 rule = NULL;
2537
b67bfe0d 2538 hlist_for_each_entry_safe(rule, node2,
e4911d57
AD		 2539 &adapter->fdir_filter_list, fdir_node) {
2540 /* hash found, or no matching entry */
2541 if (rule->sw_idx >= sw_idx)
2542 break;
b67bfe0d 2543 parent = rule;
e4911d57
AD		 2544 }
2545
2546 /* if there is an old rule occupying our place remove it */
2547 if (rule && (rule->sw_idx == sw_idx)) {
2548 if (!input || (rule->filter.formatted.bkt_hash !=
2549 input->filter.formatted.bkt_hash)) {
2550 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2551 &rule->filter,
2552 sw_idx);
2553 }
2554
2555 hlist_del(&rule->fdir_node);
2556 kfree(rule);
2557 adapter->fdir_filter_count--;
2558 }
2559
2560 /*
2561 * If no input this was a delete, err should be 0 if a rule was
2562 * successfully found and removed from the list else -EINVAL
2563 */
2564 if (!input)
2565 return err;
2566
2567 /* initialize node and set software index */
2568 INIT_HLIST_NODE(&input->fdir_node);
2569
2570 /* add filter to the list */
2571 if (parent)
1d023284 2572 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
e4911d57
AD		 2573 else
2574 hlist_add_head(&input->fdir_node,
2575 &adapter->fdir_filter_list);
2576
2577 /* update counts */
2578 adapter->fdir_filter_count++;
2579
2580 return 0;
2581}
2582
2583static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2584 u8 *flow_type)
2585{
2586 switch (fsp->flow_type & ~FLOW_EXT) {
2587 case TCP_V4_FLOW:
2588 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2589 break;
2590 case UDP_V4_FLOW:
2591 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2592 break;
2593 case SCTP_V4_FLOW:
2594 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2595 break;
2596 case IP_USER_FLOW:
2597 switch (fsp->h_u.usr_ip4_spec.proto) {
2598 case IPPROTO_TCP:
2599 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2600 break;
2601 case IPPROTO_UDP:
2602 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2603 break;
2604 case IPPROTO_SCTP:
2605 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2606 break;
2607 case 0:
2608 if (!fsp->m_u.usr_ip4_spec.proto) {
2609 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2610 break;
2611 }
2612 default:
2613 return 0;
2614 }
2615 break;
2616 default:
2617 return 0;
2618 }
2619
2620 return 1;
2621}
2622
2623static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2624 struct ethtool_rxnfc *cmd)
2625{
2626 struct ethtool_rx_flow_spec *fsp =
2627 (struct ethtool_rx_flow_spec *)&cmd->fs;
2628 struct ixgbe_hw *hw = &adapter->hw;
2629 struct ixgbe_fdir_filter *input;
2630 union ixgbe_atr_input mask;
7aac8425 2631 u8 queue;
e4911d57
AD		 2632 int err;
2633
2634 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2635 return -EOPNOTSUPP;
2636
7aac8425
JF		 2637 /* ring_cookie is a masked into a set of queues and ixgbe pools or
2638 * we use the drop index.
e4911d57 2639 */
7aac8425
JF		 2640 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
2641 queue = IXGBE_FDIR_DROP_QUEUE;
2642 } else {
2643 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
2644 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
2645
2646 if (!vf && (ring >= adapter->num_rx_queues))
2647 return -EINVAL;
2648 else if (vf &&
2649 ((vf > adapter->num_vfs) ||
2650 ring >= adapter->num_rx_queues_per_pool))
2651 return -EINVAL;
2652
2653 /* Map the ring onto the absolute queue index */
2654 if (!vf)
2655 queue = adapter->rx_ring[ring]->reg_idx;
2656 else
2657 queue = ((vf - 1) *
2658 adapter->num_rx_queues_per_pool) + ring;
2659 }
e4911d57
AD		 2660
2661 /* Don't allow indexes to exist outside of available space */
2662 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2663 e_err(drv, "Location out of range\n");
2664 return -EINVAL;
2665 }
2666
2667 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2668 if (!input)
2669 return -ENOMEM;
2670
2671 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2672
2673 /* set SW index */
2674 input->sw_idx = fsp->location;
2675
2676 /* record flow type */
2677 if (!ixgbe_flowspec_to_flow_type(fsp,
2678 &input->filter.formatted.flow_type)) {
2679 e_err(drv, "Unrecognized flow type\n");
2680 goto err_out;
2681 }
2682
2683 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2684 IXGBE_ATR_L4TYPE_MASK;
2685
2686 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2687 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2688
2689 /* Copy input into formatted structures */
2690 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2691 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2692 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2693 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2694 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2695 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2696 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2697 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2698
2699 if (fsp->flow_type & FLOW_EXT) {
2700 input->filter.formatted.vm_pool =
2701 (unsigned char)ntohl(fsp->h_ext.data[1]);
2702 mask.formatted.vm_pool =
2703 (unsigned char)ntohl(fsp->m_ext.data[1]);
2704 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2705 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2706 input->filter.formatted.flex_bytes =
2707 fsp->h_ext.vlan_etype;
2708 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2709 }
2710
2711 /* determine if we need to drop or route the packet */
2712 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2713 input->action = IXGBE_FDIR_DROP_QUEUE;
2714 else
2715 input->action = fsp->ring_cookie;
2716
2717 spin_lock(&adapter->fdir_perfect_lock);
2718
2719 if (hlist_empty(&adapter->fdir_filter_list)) {
2720 /* save mask and program input mask into HW */
2721 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2722 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2723 if (err) {
2724 e_err(drv, "Error writing mask\n");
2725 goto err_out_w_lock;
2726 }
2727 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2728 e_err(drv, "Only one mask supported per port\n");
2729 goto err_out_w_lock;
2730 }
2731
2732 /* apply mask and compute/store hash */
2733 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2734
2735 /* program filters to filter memory */
2736 err = ixgbe_fdir_write_perfect_filter_82599(hw,
7aac8425 2737 &input->filter, input->sw_idx, queue);
e4911d57
AD		 2738 if (err)
2739 goto err_out_w_lock;
2740
2741 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2742
2743 spin_unlock(&adapter->fdir_perfect_lock);
2744
2745 return err;
2746err_out_w_lock:
2747 spin_unlock(&adapter->fdir_perfect_lock);
2748err_out:
2749 kfree(input);
2750 return -EINVAL;
2751}
2752
2753static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2754 struct ethtool_rxnfc *cmd)
2755{
2756 struct ethtool_rx_flow_spec *fsp =
2757 (struct ethtool_rx_flow_spec *)&cmd->fs;
2758 int err;
2759
2760 spin_lock(&adapter->fdir_perfect_lock);
2761 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2762 spin_unlock(&adapter->fdir_perfect_lock);
2763
2764 return err;
2765}
2766
ef6afc0c
AD		 2767#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2768 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2769static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2770 struct ethtool_rxnfc *nfc)
2771{
2772 u32 flags2 = adapter->flags2;
2773
2774 /*
2775 * RSS does not support anything other than hashing
2776 * to queues on src and dst IPs and ports
2777 */
2778 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2779 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2780 return -EINVAL;
2781
2782 switch (nfc->flow_type) {
2783 case TCP_V4_FLOW:
2784 case TCP_V6_FLOW:
2785 if (!(nfc->data & RXH_IP_SRC) ||
2786 !(nfc->data & RXH_IP_DST) ||
2787 !(nfc->data & RXH_L4_B_0_1) ||
2788 !(nfc->data & RXH_L4_B_2_3))
2789 return -EINVAL;
2790 break;
2791 case UDP_V4_FLOW:
2792 if (!(nfc->data & RXH_IP_SRC) ||
2793 !(nfc->data & RXH_IP_DST))
2794 return -EINVAL;
2795 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2796 case 0:
2797 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2798 break;
2799 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2800 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2801 break;
2802 default:
2803 return -EINVAL;
2804 }
2805 break;
2806 case UDP_V6_FLOW:
2807 if (!(nfc->data & RXH_IP_SRC) ||
2808 !(nfc->data & RXH_IP_DST))
2809 return -EINVAL;
2810 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2811 case 0:
2812 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2813 break;
2814 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2815 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2816 break;
2817 default:
2818 return -EINVAL;
2819 }
2820 break;
2821 case AH_ESP_V4_FLOW:
2822 case AH_V4_FLOW:
2823 case ESP_V4_FLOW:
2824 case SCTP_V4_FLOW:
2825 case AH_ESP_V6_FLOW:
2826 case AH_V6_FLOW:
2827 case ESP_V6_FLOW:
2828 case SCTP_V6_FLOW:
2829 if (!(nfc->data & RXH_IP_SRC) ||
2830 !(nfc->data & RXH_IP_DST) ||
2831 (nfc->data & RXH_L4_B_0_1) ||
2832 (nfc->data & RXH_L4_B_2_3))
2833 return -EINVAL;
2834 break;
2835 default:
2836 return -EINVAL;
2837 }
2838
2839 /* if we changed something we need to update flags */
2840 if (flags2 != adapter->flags2) {
2841 struct ixgbe_hw *hw = &adapter->hw;
9a75a1ac
DS		 2842 u32 mrqc;
2843 unsigned int pf_pool = adapter->num_vfs;
2844
2845 if ((hw->mac.type >= ixgbe_mac_X550) &&
2846 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2847 mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
2848 else
2849 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
ef6afc0c
AD		 2850
2851 if ((flags2 & UDP_RSS_FLAGS) &&
2852 !(adapter->flags2 & UDP_RSS_FLAGS))
6ec1b71f 2853 e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
ef6afc0c
AD		 2854
2855 adapter->flags2 = flags2;
2856
2857 /* Perform hash on these packet types */
2858 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2859 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2860 | IXGBE_MRQC_RSS_FIELD_IPV6
2861 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2862
2863 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2864 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2865
2866 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2867 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2868
2869 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2870 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2871
9a75a1ac
DS		 2872 if ((hw->mac.type >= ixgbe_mac_X550) &&
2873 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2874 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
2875 else
2876 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
ef6afc0c
AD		 2877 }
2878
2879 return 0;
2880}
2881
e4911d57
AD		 2882static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2883{
2884 struct ixgbe_adapter *adapter = netdev_priv(dev);
2885 int ret = -EOPNOTSUPP;
2886
2887 switch (cmd->cmd) {
2888 case ETHTOOL_SRXCLSRLINS:
2889 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2890 break;
2891 case ETHTOOL_SRXCLSRLDEL:
2892 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2893 break;
ef6afc0c
AD		 2894 case ETHTOOL_SRXFH:
2895 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2896 break;
e4911d57
AD		 2897 default:
2898 break;
2899 }
2900
2901 return ret;
2902}
2903
1c7cf078
TB		 2904static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter)
2905{
2906 if (adapter->hw.mac.type < ixgbe_mac_X550)
2907 return 16;
2908 else
2909 return 64;
2910}
2911
7f276efb
VZ		 2912static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev)
2913{
2914 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2915
2916 return sizeof(adapter->rss_key);
2917}
2918
2919static u32 ixgbe_rss_indir_size(struct net_device *netdev)
2920{
2921 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2922
2923 return ixgbe_rss_indir_tbl_entries(adapter);
2924}
2925
2926static void ixgbe_get_reta(struct ixgbe_adapter *adapter, u32 *indir)
2927{
2928 int i, reta_size = ixgbe_rss_indir_tbl_entries(adapter);
2929
2930 for (i = 0; i < reta_size; i++)
2931 indir[i] = adapter->rss_indir_tbl[i];
2932}
2933
2934static int ixgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
2935 u8 *hfunc)
2936{
2937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2938
2939 if (hfunc)
2940 *hfunc = ETH_RSS_HASH_TOP;
2941
2942 if (indir)
2943 ixgbe_get_reta(adapter, indir);
2944
2945 if (key)
2946 memcpy(key, adapter->rss_key, ixgbe_get_rxfh_key_size(netdev));
2947
2948 return 0;
2949}
2950
1c7cf078
TB		 2951static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir,
2952 const u8 *key, const u8 hfunc)
2953{
2954 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2955 int i;
2956 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
2957
2958 if (hfunc)
2959 return -EINVAL;
2960
2961 /* Fill out the redirection table */
2962 if (indir) {
2963 int max_queues = min_t(int, adapter->num_rx_queues,
2964 ixgbe_rss_indir_tbl_max(adapter));
2965
2966 /*Allow at least 2 queues w/ SR-IOV.*/
2967 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2968 (max_queues < 2))
2969 max_queues = 2;
2970
2971 /* Verify user input. */
2972 for (i = 0; i < reta_entries; i++)
2973 if (indir[i] >= max_queues)
2974 return -EINVAL;
2975
2976 for (i = 0; i < reta_entries; i++)
2977 adapter->rss_indir_tbl[i] = indir[i];
2978 }
2979
2980 /* Fill out the rss hash key */
2981 if (key)
2982 memcpy(adapter->rss_key, key, ixgbe_get_rxfh_key_size(netdev));
2983
2984 ixgbe_store_reta(adapter);
2985
2986 return 0;
2987}
2988
e3aac889
JK		 2989static int ixgbe_get_ts_info(struct net_device *dev,
2990 struct ethtool_ts_info *info)
2991{
2992 struct ixgbe_adapter *adapter = netdev_priv(dev);
2993
918b89e7
TN		 2994 /* we always support timestamping disabled */
2995 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
2996
e3aac889 2997 switch (adapter->hw.mac.type) {
9a75a1ac
DS		 2998 case ixgbe_mac_X550:
2999 case ixgbe_mac_X550EM_x:
49425dfc 3000 case ixgbe_mac_x550em_a:
918b89e7
TN		 3001 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
3002 /* fallthrough */
e3aac889
JK		 3003 case ixgbe_mac_X540:
3004 case ixgbe_mac_82599EB:
3005 info->so_timestamping =
50f8d35d
JK		 3006 SOF_TIMESTAMPING_TX_SOFTWARE |
3007 SOF_TIMESTAMPING_RX_SOFTWARE |
3008 SOF_TIMESTAMPING_SOFTWARE |
e3aac889
JK		 3009 SOF_TIMESTAMPING_TX_HARDWARE |
3010 SOF_TIMESTAMPING_RX_HARDWARE |
3011 SOF_TIMESTAMPING_RAW_HARDWARE;
3012
3013 if (adapter->ptp_clock)
3014 info->phc_index = ptp_clock_index(adapter->ptp_clock);
3015 else
3016 info->phc_index = -1;
3017
3018 info->tx_types =
b4f47a48
JK		 3019 BIT(HWTSTAMP_TX_OFF) |
3020 BIT(HWTSTAMP_TX_ON);
e3aac889 3021
918b89e7 3022 info->rx_filters |=
b4f47a48
JK		 3023 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
3024 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
3025 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
e3aac889 3026 break;
e3aac889
JK		 3027 default:
3028 return ethtool_op_get_ts_info(dev, info);
e3aac889
JK		 3029 }
3030 return 0;
3031}
3032
5348c9db
AD		 3033static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
3034{
3035 unsigned int max_combined;
3036 u8 tcs = netdev_get_num_tc(adapter->netdev);
3037
3038 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3039 /* We only support one q_vector without MSI-X */
3040 max_combined = 1;
3041 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3042 /* SR-IOV currently only allows one queue on the PF */
3043 max_combined = 1;
3044 } else if (tcs > 1) {
3045 /* For DCB report channels per traffic class */
3046 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3047 /* 8 TC w/ 4 queues per TC */
3048 max_combined = 4;
3049 } else if (tcs > 4) {
3050 /* 8 TC w/ 8 queues per TC */
3051 max_combined = 8;
3052 } else {
3053 /* 4 TC w/ 16 queues per TC */
3054 max_combined = 16;
3055 }
3056 } else if (adapter->atr_sample_rate) {
3057 /* support up to 64 queues with ATR */
3058 max_combined = IXGBE_MAX_FDIR_INDICES;
3059 } else {
3060 /* support up to 16 queues with RSS */
0f9b232b 3061 max_combined = ixgbe_max_rss_indices(adapter);
5348c9db
AD		 3062 }
3063
3064 return max_combined;
3065}
3066
3067static void ixgbe_get_channels(struct net_device *dev,
3068 struct ethtool_channels *ch)
3069{
3070 struct ixgbe_adapter *adapter = netdev_priv(dev);
3071
3072 /* report maximum channels */
3073 ch->max_combined = ixgbe_max_channels(adapter);
3074
3075 /* report info for other vector */
3076 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3077 ch->max_other = NON_Q_VECTORS;
3078 ch->other_count = NON_Q_VECTORS;
3079 }
3080
3081 /* record RSS queues */
3082 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
3083
3084 /* nothing else to report if RSS is disabled */
3085 if (ch->combined_count == 1)
3086 return;
3087
3088 /* we do not support ATR queueing if SR-IOV is enabled */
3089 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3090 return;
3091
3092 /* same thing goes for being DCB enabled */
3093 if (netdev_get_num_tc(dev) > 1)
3094 return;
3095
3096 /* if ATR is disabled we can exit */
3097 if (!adapter->atr_sample_rate)
3098 return;
3099
3100 /* report flow director queues as maximum channels */
3101 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
3102}
3103
4c696ca9
AD		 3104static int ixgbe_set_channels(struct net_device *dev,
3105 struct ethtool_channels *ch)
3106{
3107 struct ixgbe_adapter *adapter = netdev_priv(dev);
3108 unsigned int count = ch->combined_count;
0f9b232b 3109 u8 max_rss_indices = ixgbe_max_rss_indices(adapter);
4c696ca9
AD		 3110
3111 /* verify they are not requesting separate vectors */
3112 if (!count || ch->rx_count || ch->tx_count)
3113 return -EINVAL;
3114
3115 /* verify other_count has not changed */
3116 if (ch->other_count != NON_Q_VECTORS)
3117 return -EINVAL;
3118
3119 /* verify the number of channels does not exceed hardware limits */
3120 if (count > ixgbe_max_channels(adapter))
3121 return -EINVAL;
3122
3123 /* update feature limits from largest to smallest supported values */
3124 adapter->ring_feature[RING_F_FDIR].limit = count;
3125
0f9b232b
DS		 3126 /* cap RSS limit */
3127 if (count > max_rss_indices)
3128 count = max_rss_indices;
4c696ca9
AD		 3129 adapter->ring_feature[RING_F_RSS].limit = count;
3130
3131#ifdef IXGBE_FCOE
3132 /* cap FCoE limit at 8 */
3133 if (count > IXGBE_FCRETA_SIZE)
3134 count = IXGBE_FCRETA_SIZE;
3135 adapter->ring_feature[RING_F_FCOE].limit = count;
3136
3137#endif
3138 /* use setup TC to update any traffic class queue mapping */
3139 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
3140}
3141
71858acb
AG		 3142static int ixgbe_get_module_info(struct net_device *dev,
3143 struct ethtool_modinfo *modinfo)
3144{
3145 struct ixgbe_adapter *adapter = netdev_priv(dev);
3146 struct ixgbe_hw *hw = &adapter->hw;
a1e869de 3147 s32 status;
71858acb 3148 u8 sff8472_rev, addr_mode;
71858acb
AG		 3149 bool page_swap = false;
3150
71858acb
AG		 3151 /* Check whether we support SFF-8472 or not */
3152 status = hw->phy.ops.read_i2c_eeprom(hw,
3153 IXGBE_SFF_SFF_8472_COMP,
3154 &sff8472_rev);
a1e869de 3155 if (status)
a4b6fc6b 3156 return -EIO;
71858acb
AG		 3157
3158 /* addressing mode is not supported */
3159 status = hw->phy.ops.read_i2c_eeprom(hw,
3160 IXGBE_SFF_SFF_8472_SWAP,
3161 &addr_mode);
a1e869de 3162 if (status)
a4b6fc6b 3163 return -EIO;
71858acb
AG		 3164
3165 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3166 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3167 page_swap = true;
3168 }
3169
3170 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3171 /* We have a SFP, but it does not support SFF-8472 */
3172 modinfo->type = ETH_MODULE_SFF_8079;
3173 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3174 } else {
3175 /* We have a SFP which supports a revision of SFF-8472. */
3176 modinfo->type = ETH_MODULE_SFF_8472;
3177 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3178 }
3179
a4b6fc6b 3180 return 0;
71858acb
AG		 3181}
3182
3183static int ixgbe_get_module_eeprom(struct net_device *dev,
3184 struct ethtool_eeprom *ee,
3185 u8 *data)
3186{
3187 struct ixgbe_adapter *adapter = netdev_priv(dev);
3188 struct ixgbe_hw *hw = &adapter->hw;
a1e869de 3189 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
71858acb
AG		 3190 u8 databyte = 0xFF;
3191 int i = 0;
71858acb 3192
a4b6fc6b
ET		 3193 if (ee->len == 0)
3194 return -EINVAL;
71858acb 3195
31c7d2b0 3196 for (i = ee->offset; i < ee->offset + ee->len; i++) {
a4b6fc6b
ET		 3197 /* I2C reads can take long time */
3198 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3199 return -EBUSY;
71858acb 3200
a4b6fc6b 3201 if (i < ETH_MODULE_SFF_8079_LEN)
31c7d2b0 3202 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
a4b6fc6b
ET		 3203 else
3204 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3205
a1e869de 3206 if (status)
31c7d2b0 3207 return -EIO;
71858acb 3208
a4b6fc6b 3209 data[i - ee->offset] = databyte;
71858acb
AG		 3210 }
3211
31c7d2b0 3212 return 0;
71858acb
AG		 3213}
3214
b9804972 3215static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 3216 .get_settings = ixgbe_get_settings,
3217 .set_settings = ixgbe_set_settings,
3218 .get_drvinfo = ixgbe_get_drvinfo,
3219 .get_regs_len = ixgbe_get_regs_len,
3220 .get_regs = ixgbe_get_regs,
3221 .get_wol = ixgbe_get_wol,
e63d9762 3222 .set_wol = ixgbe_set_wol,
9a799d71
AK		 3223 .nway_reset = ixgbe_nway_reset,
3224 .get_link = ethtool_op_get_link,
3225 .get_eeprom_len = ixgbe_get_eeprom_len,
3226 .get_eeprom = ixgbe_get_eeprom,
2fa5eef4 3227 .set_eeprom = ixgbe_set_eeprom,
9a799d71
AK		 3228 .get_ringparam = ixgbe_get_ringparam,
3229 .set_ringparam = ixgbe_set_ringparam,
3230 .get_pauseparam = ixgbe_get_pauseparam,
3231 .set_pauseparam = ixgbe_set_pauseparam,
9a799d71
AK		 3232 .get_msglevel = ixgbe_get_msglevel,
3233 .set_msglevel = ixgbe_set_msglevel,
da4dd0f7 3234 .self_test = ixgbe_diag_test,
9a799d71 3235 .get_strings = ixgbe_get_strings,
66e6961c 3236 .set_phys_id = ixgbe_set_phys_id,
b4617240 3237 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 3238 .get_ethtool_stats = ixgbe_get_ethtool_stats,
3239 .get_coalesce = ixgbe_get_coalesce,
3240 .set_coalesce = ixgbe_set_coalesce,
91cd94bf 3241 .get_rxnfc = ixgbe_get_rxnfc,
e4911d57 3242 .set_rxnfc = ixgbe_set_rxnfc,
7f276efb
VZ		 3243 .get_rxfh_indir_size = ixgbe_rss_indir_size,
3244 .get_rxfh_key_size = ixgbe_get_rxfh_key_size,
3245 .get_rxfh = ixgbe_get_rxfh,
1c7cf078 3246 .set_rxfh = ixgbe_set_rxfh,
5348c9db 3247 .get_channels = ixgbe_get_channels,
4c696ca9 3248 .set_channels = ixgbe_set_channels,
e3aac889 3249 .get_ts_info = ixgbe_get_ts_info,
71858acb
AG		 3250 .get_module_info = ixgbe_get_module_info,
3251 .get_module_eeprom = ixgbe_get_module_eeprom,
9a799d71
AK		 3252};
3253
3254void ixgbe_set_ethtool_ops(struct net_device *netdev)
3255{
7ad24ea4 3256 netdev->ethtool_ops = &ixgbe_ethtool_ops;
9a799d71 3257}
Linux kernel - Deliverables
This page took 1.263745 seconds and 5 git commands to generate.