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ixgbe: add SFP+ LX module support
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
a6b7a407 30#include <linux/interrupt.h>
9a799d71
AK		 31#include <linux/types.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
9a799d71
AK		 34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/ethtool.h>
37#include <linux/vmalloc.h>
f800326d 38#include <linux/highmem.h>
9a799d71
AK		 39#include <linux/uaccess.h>
40
41#include "ixgbe.h"
71858acb 42#include "ixgbe_phy.h"
9a799d71
AK		 43
44
45#define IXGBE_ALL_RAR_ENTRIES 16
46
29c3a050
AK		 47enum {NETDEV_STATS, IXGBE_STATS};
48
9a799d71
AK		 49struct ixgbe_stats {
50 char stat_string[ETH_GSTRING_LEN];
29c3a050 51 int type;
9a799d71
AK		 52 int sizeof_stat;
53 int stat_offset;
54};
55
29c3a050
AK		 56#define IXGBE_STAT(m) IXGBE_STATS, \
57 sizeof(((struct ixgbe_adapter *)0)->m), \
58 offsetof(struct ixgbe_adapter, m)
59#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 60 sizeof(((struct rtnl_link_stats64 *)0)->m), \
61 offsetof(struct rtnl_link_stats64, m)
29c3a050 62
1bba2e81 63static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 64 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
65 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
66 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
67 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 68 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
69 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
70 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
71 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 72 {"lsc_int", IXGBE_STAT(lsc_int)},
73 {"tx_busy", IXGBE_STAT(tx_busy)},
74 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 75 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
76 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
77 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
78 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
79 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 80 {"broadcast", IXGBE_STAT(stats.bprc)},
81 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 82 {"collisions", IXGBE_NETDEV_STAT(collisions)},
83 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
84 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
85 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 86 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
87 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 88 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
89 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 90 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 91 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
92 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
93 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
94 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
95 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
96 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 97 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
98 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
99 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
100 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 101 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
102 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
103 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
104 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 105 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 106 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
107 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 108 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 109 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
110 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
111 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
112 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 113#ifdef IXGBE_FCOE
114 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
115 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
116 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
117 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
7b859ebc
AH		 118 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
119 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
6d45522c
YZ		 120 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
121 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
122#endif /* IXGBE_FCOE */
9a799d71
AK		 123};
124
9cc00b51
JF		 125/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
126 * we set the num_rx_queues to evaluate to num_tx_queues. This is
127 * used because we do not have a good way to get the max number of
128 * rx queues with CONFIG_RPS disabled.
129 */
130#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
131
132#define IXGBE_QUEUE_STATS_LEN ( \
133 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
454d7c9b 134 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 135#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 136#define IXGBE_PB_STATS_LEN ( \
9cc00b51
JF		 137 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
138 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
141 / sizeof(u64))
2f90b865
AD		 142#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
143 IXGBE_PB_STATS_LEN + \
144 IXGBE_QUEUE_STATS_LEN)
9a799d71 145
da4dd0f7
PWJ		 146static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
147 "Register test (offline)", "Eeprom test (offline)",
148 "Interrupt test (offline)", "Loopback test (offline)",
149 "Link test (on/offline)"
150};
151#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
152
9a799d71 153static int ixgbe_get_settings(struct net_device *netdev,
b4617240 154 struct ethtool_cmd *ecmd)
9a799d71
AK		 155{
156 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 157 struct ixgbe_hw *hw = &adapter->hw;
db018963 158 ixgbe_link_speed supported_link;
735441fb 159 u32 link_speed = 0;
fd0326f2 160 bool autoneg = false;
735441fb 161 bool link_up;
9a799d71 162
db018963 163 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
1b1c0a48 164
db018963
JK		 165 /* set the supported link speeds */
166 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
167 ecmd->supported |= SUPPORTED_10000baseT_Full;
168 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
169 ecmd->supported |= SUPPORTED_1000baseT_Full;
170 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
171 ecmd->supported |= SUPPORTED_100baseT_Full;
1b1c0a48 172
db018963
JK		 173 /* set the advertised speeds */
174 if (hw->phy.autoneg_advertised) {
175 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
176 ecmd->advertising |= ADVERTISED_100baseT_Full;
177 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
178 ecmd->advertising |= ADVERTISED_10000baseT_Full;
179 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
180 ecmd->advertising |= ADVERTISED_1000baseT_Full;
735441fb 181 } else {
db018963
JK		 182 /* default modes in case phy.autoneg_advertised isn't set */
183 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
184 ecmd->advertising |= ADVERTISED_10000baseT_Full;
185 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
186 ecmd->advertising |= ADVERTISED_1000baseT_Full;
187 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
188 ecmd->advertising |= ADVERTISED_100baseT_Full;
735441fb 189 }
9a799d71 190
db018963
JK		 191 if (autoneg) {
192 ecmd->supported |= SUPPORTED_Autoneg;
193 ecmd->advertising |= ADVERTISED_Autoneg;
194 ecmd->autoneg = AUTONEG_ENABLE;
195 } else
196 ecmd->autoneg = AUTONEG_DISABLE;
197
198 ecmd->transceiver = XCVR_EXTERNAL;
199
200 /* Determine the remaining settings based on the PHY type. */
3b8626ba
PW		 201 switch (adapter->hw.phy.type) {
202 case ixgbe_phy_tn:
fe15e8e1 203 case ixgbe_phy_aq:
3b8626ba 204 case ixgbe_phy_cu_unknown:
db018963
JK		 205 ecmd->supported |= SUPPORTED_TP;
206 ecmd->advertising |= ADVERTISED_TP;
3b8626ba
PW		 207 ecmd->port = PORT_TP;
208 break;
209 case ixgbe_phy_qt:
db018963
JK		 210 ecmd->supported |= SUPPORTED_FIBRE;
211 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
ea0a04df
DS		 215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
3b8626ba 221 /* SFP+ devices, further checking needed */
db018963 222 switch (adapter->hw.phy.sfp_type) {
3b8626ba
PW		 223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
db018963
JK		 226 ecmd->supported |= SUPPORTED_FIBRE;
227 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 228 ecmd->port = PORT_DA;
229 break;
230 case ixgbe_sfp_type_sr:
231 case ixgbe_sfp_type_lr:
232 case ixgbe_sfp_type_srlr_core0:
233 case ixgbe_sfp_type_srlr_core1:
345be204
DS		 234 case ixgbe_sfp_type_1g_sx_core0:
235 case ixgbe_sfp_type_1g_sx_core1:
236 case ixgbe_sfp_type_1g_lx_core0:
237 case ixgbe_sfp_type_1g_lx_core1:
db018963
JK		 238 ecmd->supported |= SUPPORTED_FIBRE;
239 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 240 ecmd->port = PORT_FIBRE;
241 break;
242 case ixgbe_sfp_type_not_present:
db018963
JK		 243 ecmd->supported |= SUPPORTED_FIBRE;
244 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 245 ecmd->port = PORT_NONE;
246 break;
cb836a97
DS		 247 case ixgbe_sfp_type_1g_cu_core0:
248 case ixgbe_sfp_type_1g_cu_core1:
db018963
JK		 249 ecmd->supported |= SUPPORTED_TP;
250 ecmd->advertising |= ADVERTISED_TP;
cb836a97 251 ecmd->port = PORT_TP;
db018963 252 break;
3b8626ba
PW		 253 case ixgbe_sfp_type_unknown:
254 default:
db018963
JK		 255 ecmd->supported |= SUPPORTED_FIBRE;
256 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 257 ecmd->port = PORT_OTHER;
258 break;
259 }
260 break;
261 case ixgbe_phy_xaui:
db018963
JK		 262 ecmd->supported |= SUPPORTED_FIBRE;
263 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 264 ecmd->port = PORT_NONE;
265 break;
266 case ixgbe_phy_unknown:
267 case ixgbe_phy_generic:
268 case ixgbe_phy_sfp_unsupported:
269 default:
db018963
JK		 270 ecmd->supported |= SUPPORTED_FIBRE;
271 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 272 ecmd->port = PORT_OTHER;
273 break;
274 }
275
c44ade9e 276 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 277 if (link_up) {
1b1c0a48
AS		 278 switch (link_speed) {
279 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 280 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48
AS		 281 break;
282 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 283 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 284 break;
285 case IXGBE_LINK_SPEED_100_FULL:
70739497 286 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 287 break;
288 default:
289 break;
290 }
9a799d71
AK		 291 ecmd->duplex = DUPLEX_FULL;
292 } else {
70739497 293 ethtool_cmd_speed_set(ecmd, -1);
9a799d71
AK		 294 ecmd->duplex = -1;
295 }
296
9a799d71
AK		 297 return 0;
298}
299
300static int ixgbe_set_settings(struct net_device *netdev,
b4617240 301 struct ethtool_cmd *ecmd)
9a799d71
AK		 302{
303 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 304 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 305 u32 advertised, old;
74766013 306 s32 err = 0;
9a799d71 307
74766013 308 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 309 (hw->phy.multispeed_fiber)) {
abcc80d2
ET		 310 /*
311 * this function does not support duplex forcing, but can
312 * limit the advertising of the adapter to the specified speed
313 */
0befdb3e
JB		 314 if (ecmd->autoneg == AUTONEG_DISABLE)
315 return -EINVAL;
316
abcc80d2
ET		 317 if (ecmd->advertising & ~ecmd->supported)
318 return -EINVAL;
319
0befdb3e
JB		 320 old = hw->phy.autoneg_advertised;
321 advertised = 0;
322 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
323 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
324
325 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
326 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
327
2b642ca5
ET		 328 if (ecmd->advertising & ADVERTISED_100baseT_Full)
329 advertised |= IXGBE_LINK_SPEED_100_FULL;
330
0befdb3e 331 if (old == advertised)
74766013 332 return err;
0befdb3e 333 /* this sets the link speed and restarts auto-neg */
74766013 334 hw->mac.autotry_restart = true;
fd0326f2 335 err = hw->mac.ops.setup_link(hw, advertised, true);
0befdb3e 336 if (err) {
396e799c 337 e_info(probe, "setup link failed with code %d\n", err);
fd0326f2 338 hw->mac.ops.setup_link(hw, old, true);
0befdb3e 339 }
74766013
MC		 340 } else {
341 /* in this case we currently only support 10Gb/FULL */
25db0338 342 u32 speed = ethtool_cmd_speed(ecmd);
74766013 343 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 344 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 345 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 346 return -EINVAL;
9a799d71
AK		 347 }
348
74766013 349 return err;
9a799d71
AK		 350}
351
352static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 353 struct ethtool_pauseparam *pause)
9a799d71
AK		 354{
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
357
860502bf 358 if (hw->fc.disable_fc_autoneg)
71fd570b
DS		 359 pause->autoneg = 0;
360 else
361 pause->autoneg = 1;
9a799d71 362
0ecc061d 363 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 364 pause->rx_pause = 1;
0ecc061d 365 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 366 pause->tx_pause = 1;
0ecc061d 367 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 368 pause->rx_pause = 1;
369 pause->tx_pause = 1;
370 }
371}
372
373static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 374 struct ethtool_pauseparam *pause)
9a799d71
AK		 375{
376 struct ixgbe_adapter *adapter = netdev_priv(netdev);
377 struct ixgbe_hw *hw = &adapter->hw;
943561d3 378 struct ixgbe_fc_info fc = hw->fc;
9a799d71 379
943561d3
AD		 380 /* 82598 does no support link flow control with DCB enabled */
381 if ((hw->mac.type == ixgbe_mac_82598EB) &&
382 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
264857b8
PWJ		 383 return -EINVAL;
384
db2adc2d
JK		 385 /* some devices do not support autoneg of link flow control */
386 if ((pause->autoneg == AUTONEG_ENABLE) &&
387 (ixgbe_device_supports_autoneg_fc(hw) != 0))
388 return -EINVAL;
389
943561d3 390 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
71fd570b 391
1c4f0ef8 392 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 393 fc.requested_mode = ixgbe_fc_full;
9a799d71 394 else if (pause->rx_pause && !pause->tx_pause)
620fa036 395 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 396 else if (!pause->rx_pause && pause->tx_pause)
620fa036 397 fc.requested_mode = ixgbe_fc_tx_pause;
9c83b070 398 else
943561d3 399 fc.requested_mode = ixgbe_fc_none;
620fa036
MC		 400
401 /* if the thing changed then we'll update and use new autoneg */
402 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
403 hw->fc = fc;
404 if (netif_running(netdev))
405 ixgbe_reinit_locked(adapter);
406 else
407 ixgbe_reset(adapter);
408 }
9a799d71
AK		 409
410 return 0;
411}
412
9a799d71
AK		 413static u32 ixgbe_get_msglevel(struct net_device *netdev)
414{
415 struct ixgbe_adapter *adapter = netdev_priv(netdev);
416 return adapter->msg_enable;
417}
418
419static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
420{
421 struct ixgbe_adapter *adapter = netdev_priv(netdev);
422 adapter->msg_enable = data;
423}
424
425static int ixgbe_get_regs_len(struct net_device *netdev)
426{
217995ec 427#define IXGBE_REGS_LEN 1129
9a799d71
AK		 428 return IXGBE_REGS_LEN * sizeof(u32);
429}
430
431#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
432
433static void ixgbe_get_regs(struct net_device *netdev,
b4617240 434 struct ethtool_regs *regs, void *p)
9a799d71
AK		 435{
436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
437 struct ixgbe_hw *hw = &adapter->hw;
438 u32 *regs_buff = p;
439 u8 i;
440
441 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
442
443 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
444
445 /* General Registers */
446 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
447 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
448 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
449 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
450 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
451 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
452 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
453 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
454
455 /* NVM Register */
456 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
457 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
458 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
459 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
460 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
461 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
462 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
463 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
464 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
465 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
466
467 /* Interrupt */
98c00a1c
JB		 468 /* don't read EICR because it can clear interrupt causes, instead
469 * read EICS which is a shadow but doesn't clear EICR */
470 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 471 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
472 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
473 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
474 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
475 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
476 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
477 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
478 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
479 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 480 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 481 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
482
483 /* Flow Control */
484 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
485 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
486 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
487 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
488 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 489 for (i = 0; i < 8; i++) {
490 switch (hw->mac.type) {
491 case ixgbe_mac_82598EB:
492 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
493 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
494 break;
495 case ixgbe_mac_82599EB:
80bb25e3 496 case ixgbe_mac_X540:
bd508178
AD		 497 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
498 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
499 break;
500 default:
501 break;
502 }
503 }
9a799d71
AK		 504 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
505 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
506
507 /* Receive DMA */
508 for (i = 0; i < 64; i++)
509 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
510 for (i = 0; i < 64; i++)
511 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
512 for (i = 0; i < 64; i++)
513 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
514 for (i = 0; i < 64; i++)
515 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
516 for (i = 0; i < 64; i++)
517 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
518 for (i = 0; i < 64; i++)
519 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
520 for (i = 0; i < 16; i++)
521 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
522 for (i = 0; i < 16; i++)
523 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
524 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
525 for (i = 0; i < 8; i++)
526 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
527 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
528 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
529
530 /* Receive */
531 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
532 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
533 for (i = 0; i < 16; i++)
534 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
535 for (i = 0; i < 16; i++)
536 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 537 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 538 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
539 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
540 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
541 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
542 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
543 for (i = 0; i < 8; i++)
544 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
545 for (i = 0; i < 8; i++)
546 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
547 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
548
549 /* Transmit */
550 for (i = 0; i < 32; i++)
551 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
552 for (i = 0; i < 32; i++)
553 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
554 for (i = 0; i < 32; i++)
555 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
556 for (i = 0; i < 32; i++)
557 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
558 for (i = 0; i < 32; i++)
559 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
560 for (i = 0; i < 32; i++)
561 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
562 for (i = 0; i < 32; i++)
563 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
564 for (i = 0; i < 32; i++)
565 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
566 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
567 for (i = 0; i < 16; i++)
568 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
569 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
570 for (i = 0; i < 8; i++)
571 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
572 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
573
574 /* Wake Up */
575 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
576 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
577 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
578 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
579 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
580 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
581 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
582 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 583 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 584
673ac604 585 /* DCB */
9a799d71
AK		 586 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
587 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
588 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
589 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
590 for (i = 0; i < 8; i++)
591 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
592 for (i = 0; i < 8; i++)
593 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
594 for (i = 0; i < 8; i++)
595 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
596 for (i = 0; i < 8; i++)
597 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
598 for (i = 0; i < 8; i++)
599 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
600 for (i = 0; i < 8; i++)
601 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
602
603 /* Statistics */
604 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
605 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
606 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
607 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
608 for (i = 0; i < 8; i++)
609 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
610 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
611 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
612 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
613 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
614 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
615 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
616 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
617 for (i = 0; i < 8; i++)
618 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
619 for (i = 0; i < 8; i++)
620 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
621 for (i = 0; i < 8; i++)
622 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
623 for (i = 0; i < 8; i++)
624 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
625 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
626 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
627 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
628 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
629 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
630 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
631 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
632 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
633 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
634 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
635 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
636 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
637 for (i = 0; i < 8; i++)
638 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
639 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
640 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
641 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
642 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
643 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
644 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
645 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
646 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
647 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
648 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
649 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
650 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
651 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
652 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
653 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
654 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
655 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
656 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
657 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
658 for (i = 0; i < 16; i++)
659 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
660 for (i = 0; i < 16; i++)
661 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
662 for (i = 0; i < 16; i++)
663 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
664 for (i = 0; i < 16; i++)
665 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
666
667 /* MAC */
668 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
669 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
670 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
671 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
672 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
673 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
674 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
675 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
676 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
677 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
678 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
679 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
680 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
681 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
682 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
683 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
684 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
685 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
686 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
687 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
688 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
689 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
690 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
691 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
692 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
693 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
694 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
695 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
696 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
697 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
698 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
699 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
700 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
701
702 /* Diagnostic */
703 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
704 for (i = 0; i < 8; i++)
98c00a1c 705 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 706 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 707 for (i = 0; i < 4; i++)
708 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 709 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
710 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
711 for (i = 0; i < 8; i++)
98c00a1c 712 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 713 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 714 for (i = 0; i < 4; i++)
715 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 716 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
717 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
718 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
719 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
720 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
721 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
722 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
723 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
724 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
725 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
726 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
727 for (i = 0; i < 8; i++)
98c00a1c 728 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 729 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
730 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
731 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
732 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
733 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
734 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
735 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
736 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
737 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
217995ec
ET		 738
739 /* 82599 X540 specific registers */
740 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
9a799d71
AK		 741}
742
743static int ixgbe_get_eeprom_len(struct net_device *netdev)
744{
745 struct ixgbe_adapter *adapter = netdev_priv(netdev);
746 return adapter->hw.eeprom.word_size * 2;
747}
748
749static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 750 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 751{
752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
753 struct ixgbe_hw *hw = &adapter->hw;
754 u16 *eeprom_buff;
755 int first_word, last_word, eeprom_len;
756 int ret_val = 0;
757 u16 i;
758
759 if (eeprom->len == 0)
760 return -EINVAL;
761
762 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
763
764 first_word = eeprom->offset >> 1;
765 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
766 eeprom_len = last_word - first_word + 1;
767
768 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
769 if (!eeprom_buff)
770 return -ENOMEM;
771
68c7005d
ET		 772 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
773 eeprom_buff);
9a799d71
AK		 774
775 /* Device's eeprom is always little-endian, word addressable */
776 for (i = 0; i < eeprom_len; i++)
777 le16_to_cpus(&eeprom_buff[i]);
778
779 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
780 kfree(eeprom_buff);
781
782 return ret_val;
783}
784
2fa5eef4
ET		 785static int ixgbe_set_eeprom(struct net_device *netdev,
786 struct ethtool_eeprom *eeprom, u8 *bytes)
787{
788 struct ixgbe_adapter *adapter = netdev_priv(netdev);
789 struct ixgbe_hw *hw = &adapter->hw;
790 u16 *eeprom_buff;
791 void *ptr;
792 int max_len, first_word, last_word, ret_val = 0;
793 u16 i;
794
795 if (eeprom->len == 0)
796 return -EINVAL;
797
798 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
799 return -EINVAL;
800
801 max_len = hw->eeprom.word_size * 2;
802
803 first_word = eeprom->offset >> 1;
804 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
805 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
806 if (!eeprom_buff)
807 return -ENOMEM;
808
809 ptr = eeprom_buff;
810
811 if (eeprom->offset & 1) {
812 /*
813 * need read/modify/write of first changed EEPROM word
814 * only the second byte of the word is being modified
815 */
816 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
817 if (ret_val)
818 goto err;
819
820 ptr++;
821 }
822 if ((eeprom->offset + eeprom->len) & 1) {
823 /*
824 * need read/modify/write of last changed EEPROM word
825 * only the first byte of the word is being modified
826 */
827 ret_val = hw->eeprom.ops.read(hw, last_word,
828 &eeprom_buff[last_word - first_word]);
829 if (ret_val)
830 goto err;
831 }
832
833 /* Device's eeprom is always little-endian, word addressable */
834 for (i = 0; i < last_word - first_word + 1; i++)
835 le16_to_cpus(&eeprom_buff[i]);
836
837 memcpy(ptr, bytes, eeprom->len);
838
839 for (i = 0; i < last_word - first_word + 1; i++)
840 cpu_to_le16s(&eeprom_buff[i]);
841
842 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
843 last_word - first_word + 1,
844 eeprom_buff);
845
846 /* Update the checksum */
847 if (ret_val == 0)
848 hw->eeprom.ops.update_checksum(hw);
849
850err:
851 kfree(eeprom_buff);
852 return ret_val;
853}
854
9a799d71 855static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 856 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 857{
858 struct ixgbe_adapter *adapter = netdev_priv(netdev);
15e5209f 859 u32 nvm_track_id;
9a799d71 860
612a94d6
RJ		 861 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
862 strlcpy(drvinfo->version, ixgbe_driver_version,
863 sizeof(drvinfo->version));
083fc582 864
15e5209f
ET		 865 nvm_track_id = (adapter->eeprom_verh << 16) |
866 adapter->eeprom_verl;
612a94d6 867 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
15e5209f 868 nvm_track_id);
083fc582 869
612a94d6
RJ		 870 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
871 sizeof(drvinfo->bus_info));
9a799d71 872 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 873 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 874 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
875}
876
877static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 878 struct ethtool_ringparam *ring)
9a799d71
AK		 879{
880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 881 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
882 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 883
884 ring->rx_max_pending = IXGBE_MAX_RXD;
885 ring->tx_max_pending = IXGBE_MAX_TXD;
9a799d71
AK		 886 ring->rx_pending = rx_ring->count;
887 ring->tx_pending = tx_ring->count;
9a799d71
AK		 888}
889
890static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 891 struct ethtool_ringparam *ring)
9a799d71
AK		 892{
893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1f4702aa 894 struct ixgbe_ring *temp_ring;
759884b4 895 int i, err = 0;
c431f97e 896 u32 new_rx_count, new_tx_count;
9a799d71
AK		 897
898 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
899 return -EINVAL;
900
1f4702aa
AD		 901 new_tx_count = clamp_t(u32, ring->tx_pending,
902 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
9a799d71
AK		 903 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
904
1f4702aa
AD		 905 new_rx_count = clamp_t(u32, ring->rx_pending,
906 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
907 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
908
909 if ((new_tx_count == adapter->tx_ring_count) &&
910 (new_rx_count == adapter->rx_ring_count)) {
9a799d71
AK		 911 /* nothing to do */
912 return 0;
913 }
914
d4f80882 915 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 916 usleep_range(1000, 2000);
d4f80882 917
759884b4
AD		 918 if (!netif_running(adapter->netdev)) {
919 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 920 adapter->tx_ring[i]->count = new_tx_count;
759884b4 921 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 922 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 923 adapter->tx_ring_count = new_tx_count;
924 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 925 goto clear_reset;
759884b4
AD		 926 }
927
1f4702aa
AD		 928 /* allocate temporary buffer to store rings in */
929 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
930 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
931
932 if (!temp_ring) {
f9ed8854 933 err = -ENOMEM;
4a0b9ca0 934 goto clear_reset;
f9ed8854
MC		 935 }
936
1f4702aa
AD		 937 ixgbe_down(adapter);
938
939 /*
940 * Setup new Tx resources and free the old Tx resources in that order.
941 * We can then assign the new resources to the rings via a memcpy.
942 * The advantage to this approach is that we are guaranteed to still
943 * have resources even in the case of an allocation failure.
944 */
f9ed8854 945 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 946 for (i = 0; i < adapter->num_tx_queues; i++) {
1f4702aa 947 memcpy(&temp_ring[i], adapter->tx_ring[i],
4a0b9ca0 948 sizeof(struct ixgbe_ring));
1f4702aa
AD		 949
950 temp_ring[i].count = new_tx_count;
951 err = ixgbe_setup_tx_resources(&temp_ring[i]);
9a799d71 952 if (err) {
c431f97e
JB		 953 while (i) {
954 i--;
1f4702aa 955 ixgbe_free_tx_resources(&temp_ring[i]);
c431f97e 956 }
1f4702aa 957 goto err_setup;
9a799d71 958 }
9a799d71 959 }
9a799d71 960
1f4702aa
AD		 961 for (i = 0; i < adapter->num_tx_queues; i++) {
962 ixgbe_free_tx_resources(adapter->tx_ring[i]);
963
964 memcpy(adapter->tx_ring[i], &temp_ring[i],
965 sizeof(struct ixgbe_ring));
966 }
967
968 adapter->tx_ring_count = new_tx_count;
d3fa4721 969 }
9a799d71 970
1f4702aa 971 /* Repeat the process for the Rx rings if needed */
f9ed8854 972 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 973 for (i = 0; i < adapter->num_rx_queues; i++) {
1f4702aa 974 memcpy(&temp_ring[i], adapter->rx_ring[i],
4a0b9ca0 975 sizeof(struct ixgbe_ring));
1f4702aa
AD		 976
977 temp_ring[i].count = new_rx_count;
978 err = ixgbe_setup_rx_resources(&temp_ring[i]);
9a799d71 979 if (err) {
c431f97e
JB		 980 while (i) {
981 i--;
1f4702aa 982 ixgbe_free_rx_resources(&temp_ring[i]);
c431f97e 983 }
9a799d71
AK		 984 goto err_setup;
985 }
1f4702aa 986
9a799d71 987 }
f9ed8854 988
1f4702aa
AD		 989 for (i = 0; i < adapter->num_rx_queues; i++) {
990 ixgbe_free_rx_resources(adapter->rx_ring[i]);
f9ed8854 991
1f4702aa
AD		 992 memcpy(adapter->rx_ring[i], &temp_ring[i],
993 sizeof(struct ixgbe_ring));
f9ed8854
MC		 994 }
995
1f4702aa 996 adapter->rx_ring_count = new_rx_count;
759884b4 997 }
4a0b9ca0 998
f9ed8854 999err_setup:
1f4702aa
AD		 1000 ixgbe_up(adapter);
1001 vfree(temp_ring);
4a0b9ca0 1002clear_reset:
d4f80882 1003 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1004 return err;
1005}
1006
b9f2c044 1007static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1008{
b9f2c044 1009 switch (sset) {
da4dd0f7
PWJ		 1010 case ETH_SS_TEST:
1011 return IXGBE_TEST_LEN;
b9f2c044
JG		 1012 case ETH_SS_STATS:
1013 return IXGBE_STATS_LEN;
1014 default:
1015 return -EOPNOTSUPP;
1016 }
9a799d71
AK		 1017}
1018
1019static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 1020 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1021{
1022 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1023 struct rtnl_link_stats64 temp;
1024 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1025 unsigned int start;
1026 struct ixgbe_ring *ring;
1027 int i, j;
29c3a050 1028 char *p = NULL;
9a799d71
AK		 1029
1030 ixgbe_update_stats(adapter);
28172739 1031 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1032 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1033 switch (ixgbe_gstrings_stats[i].type) {
1034 case NETDEV_STATS:
28172739 1035 p = (char *) net_stats +
29c3a050
AK		 1036 ixgbe_gstrings_stats[i].stat_offset;
1037 break;
1038 case IXGBE_STATS:
1039 p = (char *) adapter +
1040 ixgbe_gstrings_stats[i].stat_offset;
1041 break;
f752be9c
JH		 1042 default:
1043 data[i] = 0;
1044 continue;
29c3a050
AK		 1045 }
1046
9a799d71 1047 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1048 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71 1049 }
9cc00b51 1050 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
de1036b1 1051 ring = adapter->tx_ring[j];
9cc00b51
JF		 1052 if (!ring) {
1053 data[i] = 0;
1054 data[i+1] = 0;
1055 i += 2;
1056 continue;
1057 }
1058
de1036b1
ED		 1059 do {
1060 start = u64_stats_fetch_begin_bh(&ring->syncp);
1061 data[i] = ring->stats.packets;
1062 data[i+1] = ring->stats.bytes;
1063 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1064 i += 2;
9a799d71 1065 }
9cc00b51 1066 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
de1036b1 1067 ring = adapter->rx_ring[j];
9cc00b51
JF		 1068 if (!ring) {
1069 data[i] = 0;
1070 data[i+1] = 0;
1071 i += 2;
1072 continue;
1073 }
1074
de1036b1
ED		 1075 do {
1076 start = u64_stats_fetch_begin_bh(&ring->syncp);
1077 data[i] = ring->stats.packets;
1078 data[i+1] = ring->stats.bytes;
1079 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1080 i += 2;
9a799d71 1081 }
9cc00b51
JF		 1082
1083 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1084 data[i++] = adapter->stats.pxontxc[j];
1085 data[i++] = adapter->stats.pxofftxc[j];
1086 }
1087 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1088 data[i++] = adapter->stats.pxonrxc[j];
1089 data[i++] = adapter->stats.pxoffrxc[j];
2f90b865 1090 }
9a799d71
AK		 1091}
1092
1093static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1094 u8 *data)
9a799d71 1095{
c44ade9e 1096 char *p = (char *)data;
9a799d71
AK		 1097 int i;
1098
1099 switch (stringset) {
da4dd0f7 1100 case ETH_SS_TEST:
d2c47b62
JH		 1101 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1102 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1103 data += ETH_GSTRING_LEN;
1104 }
da4dd0f7 1105 break;
9a799d71
AK		 1106 case ETH_SS_STATS:
1107 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1108 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1109 ETH_GSTRING_LEN);
1110 p += ETH_GSTRING_LEN;
1111 }
9cc00b51 1112 for (i = 0; i < netdev->num_tx_queues; i++) {
9a799d71
AK		 1113 sprintf(p, "tx_queue_%u_packets", i);
1114 p += ETH_GSTRING_LEN;
1115 sprintf(p, "tx_queue_%u_bytes", i);
1116 p += ETH_GSTRING_LEN;
1117 }
9cc00b51 1118 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
9a799d71
AK		 1119 sprintf(p, "rx_queue_%u_packets", i);
1120 p += ETH_GSTRING_LEN;
1121 sprintf(p, "rx_queue_%u_bytes", i);
1122 p += ETH_GSTRING_LEN;
1123 }
9cc00b51
JF		 1124 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1125 sprintf(p, "tx_pb_%u_pxon", i);
1126 p += ETH_GSTRING_LEN;
1127 sprintf(p, "tx_pb_%u_pxoff", i);
1128 p += ETH_GSTRING_LEN;
1129 }
1130 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1131 sprintf(p, "rx_pb_%u_pxon", i);
1132 p += ETH_GSTRING_LEN;
1133 sprintf(p, "rx_pb_%u_pxoff", i);
1134 p += ETH_GSTRING_LEN;
2f90b865 1135 }
b4617240 1136 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1137 break;
1138 }
1139}
1140
da4dd0f7
PWJ		 1141static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1142{
1143 struct ixgbe_hw *hw = &adapter->hw;
1144 bool link_up;
1145 u32 link_speed = 0;
1146 *data = 0;
1147
1148 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1149 if (link_up)
1150 return *data;
1151 else
1152 *data = 1;
1153 return *data;
1154}
1155
1156/* ethtool register test data */
1157struct ixgbe_reg_test {
1158 u16 reg;
1159 u8 array_len;
1160 u8 test_type;
1161 u32 mask;
1162 u32 write;
1163};
1164
1165/* In the hardware, registers are laid out either singly, in arrays
1166 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1167 * most tests take place on arrays or single registers (handled
1168 * as a single-element array) and special-case the tables.
1169 * Table tests are always pattern tests.
1170 *
1171 * We also make provision for some required setup steps by specifying
1172 * registers to be written without any read-back testing.
1173 */
1174
1175#define PATTERN_TEST 1
1176#define SET_READ_TEST 2
1177#define WRITE_NO_TEST 3
1178#define TABLE32_TEST 4
1179#define TABLE64_TEST_LO 5
1180#define TABLE64_TEST_HI 6
1181
1182/* default 82599 register test */
66744500 1183static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1184 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1185 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1186 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1187 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1188 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1189 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1190 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1191 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1192 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1193 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1194 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1195 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1196 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1197 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1198 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1199 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1200 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1201 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1202 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1203 { 0, 0, 0, 0 }
1204};
1205
1206/* default 82598 register test */
66744500 1207static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1208 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1209 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1210 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1211 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1212 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1213 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1214 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1215 /* Enable all four RX queues before testing. */
1216 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1217 /* RDH is read-only for 82598, only test RDT. */
1218 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1219 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1220 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1221 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1222 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1223 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1224 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1225 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1226 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1227 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1228 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1229 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1230 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1231 { 0, 0, 0, 0 }
1232};
1233
95a46011
ET		 1234static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1235 u32 mask, u32 write)
1236{
1237 u32 pat, val, before;
1238 static const u32 test_pattern[] = {
1239 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1240
1241 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1242 before = readl(adapter->hw.hw_addr + reg);
1243 writel((test_pattern[pat] & write),
1244 (adapter->hw.hw_addr + reg));
1245 val = readl(adapter->hw.hw_addr + reg);
1246 if (val != (test_pattern[pat] & write & mask)) {
1247 e_err(drv, "pattern test reg %04X failed: got "
1248 "0x%08X expected 0x%08X\n",
1249 reg, val, (test_pattern[pat] & write & mask));
1250 *data = reg;
1251 writel(before, adapter->hw.hw_addr + reg);
1252 return 1;
1253 }
1254 writel(before, adapter->hw.hw_addr + reg);
1255 }
1256 return 0;
da4dd0f7
PWJ		 1257}
1258
95a46011
ET		 1259static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1260 u32 mask, u32 write)
1261{
1262 u32 val, before;
1263 before = readl(adapter->hw.hw_addr + reg);
1264 writel((write & mask), (adapter->hw.hw_addr + reg));
1265 val = readl(adapter->hw.hw_addr + reg);
1266 if ((write & mask) != (val & mask)) {
1267 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1268 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1269 *data = reg;
1270 writel(before, (adapter->hw.hw_addr + reg));
1271 return 1;
1272 }
1273 writel(before, (adapter->hw.hw_addr + reg));
1274 return 0;
da4dd0f7
PWJ		 1275}
1276
95a46011
ET		 1277#define REG_PATTERN_TEST(reg, mask, write) \
1278 do { \
1279 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1280 return 1; \
1281 } while (0) \
1282
1283
1284#define REG_SET_AND_CHECK(reg, mask, write) \
1285 do { \
1286 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1287 return 1; \
1288 } while (0) \
1289
da4dd0f7
PWJ		 1290static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1291{
66744500 1292 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1293 u32 value, before, after;
1294 u32 i, toggle;
1295
bd508178
AD		 1296 switch (adapter->hw.mac.type) {
1297 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1298 toggle = 0x7FFFF3FF;
1299 test = reg_test_82598;
bd508178
AD		 1300 break;
1301 case ixgbe_mac_82599EB:
b93a2226 1302 case ixgbe_mac_X540:
bd508178
AD		 1303 toggle = 0x7FFFF30F;
1304 test = reg_test_82599;
1305 break;
1306 default:
1307 *data = 1;
1308 return 1;
1309 break;
da4dd0f7
PWJ		 1310 }
1311
1312 /*
1313 * Because the status register is such a special case,
1314 * we handle it separately from the rest of the register
1315 * tests. Some bits are read-only, some toggle, and some
1316 * are writeable on newer MACs.
1317 */
1318 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1319 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1321 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1322 if (value != after) {
396e799c
ET		 1323 e_err(drv, "failed STATUS register test got: 0x%08X "
1324 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1325 *data = 1;
1326 return 1;
1327 }
1328 /* restore previous status */
1329 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1330
1331 /*
1332 * Perform the remainder of the register test, looping through
1333 * the test table until we either fail or reach the null entry.
1334 */
1335 while (test->reg) {
1336 for (i = 0; i < test->array_len; i++) {
1337 switch (test->test_type) {
1338 case PATTERN_TEST:
1339 REG_PATTERN_TEST(test->reg + (i * 0x40),
95a46011
ET		 1340 test->mask,
1341 test->write);
da4dd0f7
PWJ		 1342 break;
1343 case SET_READ_TEST:
1344 REG_SET_AND_CHECK(test->reg + (i * 0x40),
95a46011
ET		 1345 test->mask,
1346 test->write);
da4dd0f7
PWJ		 1347 break;
1348 case WRITE_NO_TEST:
1349 writel(test->write,
1350 (adapter->hw.hw_addr + test->reg)
1351 + (i * 0x40));
1352 break;
1353 case TABLE32_TEST:
1354 REG_PATTERN_TEST(test->reg + (i * 4),
95a46011
ET		 1355 test->mask,
1356 test->write);
da4dd0f7
PWJ		 1357 break;
1358 case TABLE64_TEST_LO:
1359 REG_PATTERN_TEST(test->reg + (i * 8),
95a46011
ET		 1360 test->mask,
1361 test->write);
da4dd0f7
PWJ		 1362 break;
1363 case TABLE64_TEST_HI:
1364 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
95a46011
ET		 1365 test->mask,
1366 test->write);
da4dd0f7
PWJ		 1367 break;
1368 }
1369 }
1370 test++;
1371 }
1372
1373 *data = 0;
1374 return 0;
1375}
1376
1377static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1378{
1379 struct ixgbe_hw *hw = &adapter->hw;
1380 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1381 *data = 1;
1382 else
1383 *data = 0;
1384 return *data;
1385}
1386
1387static irqreturn_t ixgbe_test_intr(int irq, void *data)
1388{
1389 struct net_device *netdev = (struct net_device *) data;
1390 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1391
1392 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1393
1394 return IRQ_HANDLED;
1395}
1396
1397static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1398{
1399 struct net_device *netdev = adapter->netdev;
1400 u32 mask, i = 0, shared_int = true;
1401 u32 irq = adapter->pdev->irq;
1402
1403 *data = 0;
1404
1405 /* Hook up test interrupt handler just for this test */
1406 if (adapter->msix_entries) {
1407 /* NOTE: we don't test MSI-X interrupts here, yet */
1408 return 0;
1409 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1410 shared_int = false;
a0607fd3 1411 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1412 netdev)) {
1413 *data = 1;
1414 return -1;
1415 }
a0607fd3 1416 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1417 netdev->name, netdev)) {
1418 shared_int = false;
a0607fd3 1419 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1420 netdev->name, netdev)) {
1421 *data = 1;
1422 return -1;
1423 }
396e799c
ET		 1424 e_info(hw, "testing %s interrupt\n", shared_int ?
1425 "shared" : "unshared");
da4dd0f7
PWJ		 1426
1427 /* Disable all the interrupts */
1428 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1429 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1430 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1431
1432 /* Test each interrupt */
1433 for (; i < 10; i++) {
1434 /* Interrupt to test */
1435 mask = 1 << i;
1436
1437 if (!shared_int) {
1438 /*
1439 * Disable the interrupts to be reported in
1440 * the cause register and then force the same
1441 * interrupt and see if one gets posted. If
1442 * an interrupt was posted to the bus, the
1443 * test failed.
1444 */
1445 adapter->test_icr = 0;
1446 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1447 ~mask & 0x00007FFF);
1448 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1449 ~mask & 0x00007FFF);
945a5151 1450 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1451 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1452
1453 if (adapter->test_icr & mask) {
1454 *data = 3;
1455 break;
1456 }
1457 }
1458
1459 /*
1460 * Enable the interrupt to be reported in the cause
1461 * register and then force the same interrupt and see
1462 * if one gets posted. If an interrupt was not posted
1463 * to the bus, the test failed.
1464 */
1465 adapter->test_icr = 0;
1466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1467 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
945a5151 1468 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1469 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1470
1471 if (!(adapter->test_icr &mask)) {
1472 *data = 4;
1473 break;
1474 }
1475
1476 if (!shared_int) {
1477 /*
1478 * Disable the other interrupts to be reported in
1479 * the cause register and then force the other
1480 * interrupts and see if any get posted. If
1481 * an interrupt was posted to the bus, the
1482 * test failed.
1483 */
1484 adapter->test_icr = 0;
1485 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1486 ~mask & 0x00007FFF);
1487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1488 ~mask & 0x00007FFF);
945a5151 1489 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1490 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1491
1492 if (adapter->test_icr) {
1493 *data = 5;
1494 break;
1495 }
1496 }
1497 }
1498
1499 /* Disable all the interrupts */
1500 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1501 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1502 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1503
1504 /* Unhook test interrupt handler */
1505 free_irq(irq, netdev);
1506
1507 return *data;
1508}
1509
1510static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1511{
1512 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1513 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1514 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1515 u32 reg_ctl;
da4dd0f7
PWJ		 1516
1517 /* shut down the DMA engines now so they can be reinitialized later */
1518
1519 /* first Rx */
1520 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1521 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1522 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
2d39d576 1523 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1524
1525 /* now Tx */
84418e3b 1526 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1527 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1528 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1529
bd508178
AD		 1530 switch (hw->mac.type) {
1531 case ixgbe_mac_82599EB:
b93a2226 1532 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1533 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1534 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1535 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1536 break;
1537 default:
1538 break;
da4dd0f7
PWJ		 1539 }
1540
1541 ixgbe_reset(adapter);
1542
b6ec895e
AD		 1543 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1544 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1545}
1546
1547static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1548{
1549 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1550 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1551 u32 rctl, reg_data;
84418e3b
AD		 1552 int ret_val;
1553 int err;
da4dd0f7
PWJ		 1554
1555 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1556 tx_ring->count = IXGBE_DEFAULT_TXD;
1557 tx_ring->queue_index = 0;
b6ec895e 1558 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1559 tx_ring->netdev = adapter->netdev;
84418e3b 1560 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
da4dd0f7 1561
b6ec895e 1562 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1563 if (err)
1564 return 1;
da4dd0f7 1565
bd508178
AD		 1566 switch (adapter->hw.mac.type) {
1567 case ixgbe_mac_82599EB:
b93a2226 1568 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1569 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1570 reg_data |= IXGBE_DMATXCTL_TE;
1571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1572 break;
1573 default:
1574 break;
da4dd0f7 1575 }
f4ec443b 1576
84418e3b 1577 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1578
1579 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1580 rx_ring->count = IXGBE_DEFAULT_RXD;
1581 rx_ring->queue_index = 0;
b6ec895e 1582 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1583 rx_ring->netdev = adapter->netdev;
84418e3b 1584 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
84418e3b 1585
b6ec895e 1586 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1587 if (err) {
da4dd0f7
PWJ		 1588 ret_val = 4;
1589 goto err_nomem;
1590 }
1591
da4dd0f7
PWJ		 1592 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1593 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1594
84418e3b 1595 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1596
1597 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1599
da4dd0f7
PWJ		 1600 return 0;
1601
1602err_nomem:
1603 ixgbe_free_desc_rings(adapter);
1604 return ret_val;
1605}
1606
1607static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1608{
1609 struct ixgbe_hw *hw = &adapter->hw;
1610 u32 reg_data;
1611
e7fd9253
DS		 1612 /* X540 needs to set the MACC.FLU bit to force link up */
1613 if (adapter->hw.mac.type == ixgbe_mac_X540) {
35c7f8a1 1614 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
e7fd9253 1615 reg_data |= IXGBE_MACC_FLU;
35c7f8a1 1616 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
e7fd9253
DS		 1617 }
1618
da4dd0f7 1619 /* right now we only support MAC loopback in the driver */
35c7f8a1 1620 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
84418e3b 1621 /* Setup MAC loopback */
da4dd0f7 1622 reg_data |= IXGBE_HLREG0_LPBK;
35c7f8a1 1623 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
da4dd0f7 1624
35c7f8a1 1625 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
84418e3b 1626 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
35c7f8a1 1627 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
84418e3b 1628
35c7f8a1 1629 reg_data = IXGBE_READ_REG(hw, IXGBE_AUTOC);
da4dd0f7
PWJ		 1630 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1631 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
35c7f8a1
AD		 1632 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1633 IXGBE_WRITE_FLUSH(hw);
032b4325 1634 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1635
1636 /* Disable Atlas Tx lanes; re-enabled in reset path */
1637 if (hw->mac.type == ixgbe_mac_82598EB) {
1638 u8 atlas;
1639
1640 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1641 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1642 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1643
1644 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1645 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1646 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1647
1648 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1649 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1650 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1651
1652 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1653 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1654 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1655 }
1656
1657 return 0;
1658}
1659
1660static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1661{
1662 u32 reg_data;
1663
1664 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1665 reg_data &= ~IXGBE_HLREG0_LPBK;
1666 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1667}
1668
1669static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
3832b26e 1670 unsigned int frame_size)
da4dd0f7
PWJ		 1671{
1672 memset(skb->data, 0xFF, frame_size);
3832b26e
AD		 1673 frame_size >>= 1;
1674 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1675 memset(&skb->data[frame_size + 10], 0xBE, 1);
1676 memset(&skb->data[frame_size + 12], 0xAF, 1);
da4dd0f7
PWJ		 1677}
1678
3832b26e
AD		 1679static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1680 unsigned int frame_size)
da4dd0f7 1681{
3832b26e
AD		 1682 unsigned char *data;
1683 bool match = true;
1684
1685 frame_size >>= 1;
1686
f800326d 1687 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
3832b26e
AD		 1688
1689 if (data[3] != 0xFF ||
1690 data[frame_size + 10] != 0xBE ||
1691 data[frame_size + 12] != 0xAF)
1692 match = false;
1693
f800326d
AD		 1694 kunmap(rx_buffer->page);
1695
3832b26e 1696 return match;
da4dd0f7
PWJ		 1697}
1698
fc77dc3c 1699static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
3832b26e
AD		 1700 struct ixgbe_ring *tx_ring,
1701 unsigned int size)
84418e3b
AD		 1702{
1703 union ixgbe_adv_rx_desc *rx_desc;
3832b26e
AD		 1704 struct ixgbe_rx_buffer *rx_buffer;
1705 struct ixgbe_tx_buffer *tx_buffer;
84418e3b
AD		 1706 u16 rx_ntc, tx_ntc, count = 0;
1707
1708 /* initialize next to clean and descriptor values */
1709 rx_ntc = rx_ring->next_to_clean;
1710 tx_ntc = tx_ring->next_to_clean;
e4f74028 1711 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b 1712
3832b26e 1713 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
84418e3b 1714 /* check Rx buffer */
3832b26e 1715 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
84418e3b 1716
f800326d
AD		 1717 /* sync Rx buffer for CPU read */
1718 dma_sync_single_for_cpu(rx_ring->dev,
1719 rx_buffer->dma,
1720 ixgbe_rx_bufsz(rx_ring),
1721 DMA_FROM_DEVICE);
84418e3b
AD		 1722
1723 /* verify contents of skb */
3832b26e 1724 if (ixgbe_check_lbtest_frame(rx_buffer, size))
84418e3b
AD		 1725 count++;
1726
f800326d
AD		 1727 /* sync Rx buffer for device write */
1728 dma_sync_single_for_device(rx_ring->dev,
1729 rx_buffer->dma,
1730 ixgbe_rx_bufsz(rx_ring),
1731 DMA_FROM_DEVICE);
1732
84418e3b 1733 /* unmap buffer on Tx side */
3832b26e
AD		 1734 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1735 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
84418e3b
AD		 1736
1737 /* increment Rx/Tx next to clean counters */
1738 rx_ntc++;
1739 if (rx_ntc == rx_ring->count)
1740 rx_ntc = 0;
1741 tx_ntc++;
1742 if (tx_ntc == tx_ring->count)
1743 tx_ntc = 0;
1744
1745 /* fetch next descriptor */
e4f74028 1746 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b
AD		 1747 }
1748
dad8a3b3
JF		 1749 netdev_tx_reset_queue(txring_txq(tx_ring));
1750
84418e3b 1751 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1752 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1753 rx_ring->next_to_clean = rx_ntc;
1754 tx_ring->next_to_clean = tx_ntc;
1755
1756 return count;
1757}
1758
da4dd0f7
PWJ		 1759static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1760{
1761 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1762 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1763 int i, j, lc, good_cnt, ret_val = 0;
1764 unsigned int size = 1024;
1765 netdev_tx_t tx_ret_val;
1766 struct sk_buff *skb;
1767
1768 /* allocate test skb */
1769 skb = alloc_skb(size, GFP_KERNEL);
1770 if (!skb)
1771 return 11;
da4dd0f7 1772
84418e3b
AD		 1773 /* place data into test skb */
1774 ixgbe_create_lbtest_frame(skb, size);
1775 skb_put(skb, size);
da4dd0f7
PWJ		 1776
1777 /*
1778 * Calculate the loop count based on the largest descriptor ring
1779 * The idea is to wrap the largest ring a number of times using 64
1780 * send/receive pairs during each loop
1781 */
1782
1783 if (rx_ring->count <= tx_ring->count)
1784 lc = ((tx_ring->count / 64) * 2) + 1;
1785 else
1786 lc = ((rx_ring->count / 64) * 2) + 1;
1787
da4dd0f7 1788 for (j = 0; j <= lc; j++) {
84418e3b 1789 /* reset count of good packets */
da4dd0f7 1790 good_cnt = 0;
84418e3b
AD		 1791
1792 /* place 64 packets on the transmit queue*/
1793 for (i = 0; i < 64; i++) {
1794 skb_get(skb);
1795 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1796 adapter,
1797 tx_ring);
1798 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1799 good_cnt++;
84418e3b
AD		 1800 }
1801
da4dd0f7 1802 if (good_cnt != 64) {
84418e3b 1803 ret_val = 12;
da4dd0f7
PWJ		 1804 break;
1805 }
84418e3b
AD		 1806
1807 /* allow 200 milliseconds for packets to go from Tx to Rx */
1808 msleep(200);
1809
fc77dc3c 1810 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1811 if (good_cnt != 64) {
1812 ret_val = 13;
da4dd0f7
PWJ		 1813 break;
1814 }
1815 }
1816
84418e3b
AD		 1817 /* free the original skb */
1818 kfree_skb(skb);
1819
da4dd0f7
PWJ		 1820 return ret_val;
1821}
1822
1823static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1824{
1825 *data = ixgbe_setup_desc_rings(adapter);
1826 if (*data)
1827 goto out;
1828 *data = ixgbe_setup_loopback_test(adapter);
1829 if (*data)
1830 goto err_loopback;
1831 *data = ixgbe_run_loopback_test(adapter);
1832 ixgbe_loopback_cleanup(adapter);
1833
1834err_loopback:
1835 ixgbe_free_desc_rings(adapter);
1836out:
1837 return *data;
1838}
1839
1840static void ixgbe_diag_test(struct net_device *netdev,
1841 struct ethtool_test *eth_test, u64 *data)
1842{
1843 struct ixgbe_adapter *adapter = netdev_priv(netdev);
dfcc4615 1844 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7
PWJ		 1845 bool if_running = netif_running(netdev);
1846
1847 set_bit(__IXGBE_TESTING, &adapter->state);
1848 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
e7d481a6
GR		 1849 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1850 int i;
1851 for (i = 0; i < adapter->num_vfs; i++) {
1852 if (adapter->vfinfo[i].clear_to_send) {
1853 netdev_warn(netdev, "%s",
1854 "offline diagnostic is not "
1855 "supported when VFs are "
1856 "present\n");
1857 data[0] = 1;
1858 data[1] = 1;
1859 data[2] = 1;
1860 data[3] = 1;
1861 eth_test->flags |= ETH_TEST_FL_FAILED;
1862 clear_bit(__IXGBE_TESTING,
1863 &adapter->state);
1864 goto skip_ol_tests;
1865 }
1866 }
1867 }
1868
dfcc4615
JK		 1869 /* Offline tests */
1870 e_info(hw, "offline testing starting\n");
1871
da4dd0f7
PWJ		 1872 if (if_running)
1873 /* indicate we're in test mode */
1874 dev_close(netdev);
da4dd0f7 1875
dfcc4615
JK		 1876 /* bringing adapter down disables SFP+ optics */
1877 if (hw->mac.ops.enable_tx_laser)
1878 hw->mac.ops.enable_tx_laser(hw);
1879
1880 /* Link test performed before hardware reset so autoneg doesn't
1881 * interfere with test result
1882 */
1883 if (ixgbe_link_test(adapter, &data[4]))
1884 eth_test->flags |= ETH_TEST_FL_FAILED;
1885
1886 ixgbe_reset(adapter);
396e799c 1887 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1888 if (ixgbe_reg_test(adapter, &data[0]))
1889 eth_test->flags |= ETH_TEST_FL_FAILED;
1890
1891 ixgbe_reset(adapter);
396e799c 1892 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1893 if (ixgbe_eeprom_test(adapter, &data[1]))
1894 eth_test->flags |= ETH_TEST_FL_FAILED;
1895
1896 ixgbe_reset(adapter);
396e799c 1897 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1898 if (ixgbe_intr_test(adapter, &data[2]))
1899 eth_test->flags |= ETH_TEST_FL_FAILED;
1900
bdbec4b8
GR		 1901 /* If SRIOV or VMDq is enabled then skip MAC
1902 * loopback diagnostic. */
1903 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1904 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1905 e_info(hw, "Skip MAC loopback diagnostic in VT "
1906 "mode\n");
bdbec4b8
GR		 1907 data[3] = 0;
1908 goto skip_loopback;
1909 }
1910
da4dd0f7 1911 ixgbe_reset(adapter);
396e799c 1912 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1913 if (ixgbe_loopback_test(adapter, &data[3]))
1914 eth_test->flags |= ETH_TEST_FL_FAILED;
1915
bdbec4b8 1916skip_loopback:
da4dd0f7
PWJ		 1917 ixgbe_reset(adapter);
1918
dfcc4615 1919 /* clear testing bit and return adapter to previous state */
da4dd0f7
PWJ		 1920 clear_bit(__IXGBE_TESTING, &adapter->state);
1921 if (if_running)
1922 dev_open(netdev);
1923 } else {
396e799c 1924 e_info(hw, "online testing starting\n");
dfcc4615
JK		 1925
1926 /* if adapter is down, SFP+ optics will be disabled */
1927 if (!if_running && hw->mac.ops.enable_tx_laser)
1928 hw->mac.ops.enable_tx_laser(hw);
1929
da4dd0f7
PWJ		 1930 /* Online tests */
1931 if (ixgbe_link_test(adapter, &data[4]))
1932 eth_test->flags |= ETH_TEST_FL_FAILED;
1933
dfcc4615 1934 /* Offline tests aren't run; pass by default */
da4dd0f7
PWJ		 1935 data[0] = 0;
1936 data[1] = 0;
1937 data[2] = 0;
1938 data[3] = 0;
1939
1940 clear_bit(__IXGBE_TESTING, &adapter->state);
1941 }
dfcc4615
JK		 1942
1943 /* if adapter was down, ensure SFP+ optics are disabled again */
1944 if (!if_running && hw->mac.ops.disable_tx_laser)
1945 hw->mac.ops.disable_tx_laser(hw);
e7d481a6 1946skip_ol_tests:
da4dd0f7
PWJ		 1947 msleep_interruptible(4 * 1000);
1948}
9a799d71 1949
d6c519e1
AD		 1950static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1951 struct ethtool_wolinfo *wol)
1952{
1953 struct ixgbe_hw *hw = &adapter->hw;
8e2813f5 1954 int retval = 0;
c23f5b6b 1955
8e2813f5
JK		 1956 /* WOL not supported for all devices */
1957 if (!ixgbe_wol_supported(adapter, hw->device_id,
1958 hw->subsystem_device_id)) {
1959 retval = 1;
d6c519e1 1960 wol->supported = 0;
d6c519e1
AD		 1961 }
1962
1963 return retval;
1964}
1965
9a799d71 1966static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1967 struct ethtool_wolinfo *wol)
9a799d71 1968{
e63d9762
PW		 1969 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1970
1971 wol->supported = WAKE_UCAST | WAKE_MCAST |
1972 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1973 wol->wolopts = 0;
1974
d6c519e1
AD		 1975 if (ixgbe_wol_exclusion(adapter, wol) ||
1976 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1977 return;
1978
1979 if (adapter->wol & IXGBE_WUFC_EX)
1980 wol->wolopts |= WAKE_UCAST;
1981 if (adapter->wol & IXGBE_WUFC_MC)
1982 wol->wolopts |= WAKE_MCAST;
1983 if (adapter->wol & IXGBE_WUFC_BC)
1984 wol->wolopts |= WAKE_BCAST;
1985 if (adapter->wol & IXGBE_WUFC_MAG)
1986 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 1987}
1988
e63d9762
PW		 1989static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1990{
1991 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1992
1993 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1994 return -EOPNOTSUPP;
1995
d6c519e1
AD		 1996 if (ixgbe_wol_exclusion(adapter, wol))
1997 return wol->wolopts ? -EOPNOTSUPP : 0;
1998
e63d9762
PW		 1999 adapter->wol = 0;
2000
2001 if (wol->wolopts & WAKE_UCAST)
2002 adapter->wol |= IXGBE_WUFC_EX;
2003 if (wol->wolopts & WAKE_MCAST)
2004 adapter->wol |= IXGBE_WUFC_MC;
2005 if (wol->wolopts & WAKE_BCAST)
2006 adapter->wol |= IXGBE_WUFC_BC;
2007 if (wol->wolopts & WAKE_MAGIC)
2008 adapter->wol |= IXGBE_WUFC_MAG;
2009
2010 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2011
2012 return 0;
2013}
2014
9a799d71
AK		 2015static int ixgbe_nway_reset(struct net_device *netdev)
2016{
2017 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2018
d4f80882
AV		 2019 if (netif_running(netdev))
2020 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2021
2022 return 0;
2023}
2024
66e6961c
ET		 2025static int ixgbe_set_phys_id(struct net_device *netdev,
2026 enum ethtool_phys_id_state state)
9a799d71
AK		 2027{
2028 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2029 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2030
66e6961c
ET		 2031 switch (state) {
2032 case ETHTOOL_ID_ACTIVE:
2033 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2034 return 2;
9a799d71 2035
66e6961c 2036 case ETHTOOL_ID_ON:
c44ade9e 2037 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 2038 break;
2039
2040 case ETHTOOL_ID_OFF:
c44ade9e 2041 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 2042 break;
9a799d71 2043
66e6961c
ET		 2044 case ETHTOOL_ID_INACTIVE:
2045 /* Restore LED settings */
2046 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2047 break;
2048 }
9a799d71
AK		 2049
2050 return 0;
2051}
2052
2053static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 2054 struct ethtool_coalesce *ec)
9a799d71
AK		 2055{
2056 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2057
30efa5a3 2058 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2059 if (adapter->rx_itr_setting <= 1)
2060 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2061 else
2062 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
f7554a2b 2063
cfb3f91a 2064 /* if in mixed tx/rx queues per vector mode, report only rx settings */
08c8833b 2065 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
cfb3f91a
SN		 2066 return 0;
2067
f7554a2b 2068 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2069 if (adapter->tx_itr_setting <= 1)
2070 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2071 else
2072 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
f7554a2b 2073
9a799d71
AK		 2074 return 0;
2075}
2076
80fba3f4
AD		 2077/*
2078 * this function must be called before setting the new value of
2079 * rx_itr_setting
2080 */
567d2de2 2081static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
80fba3f4
AD		 2082{
2083 struct net_device *netdev = adapter->netdev;
2084
567d2de2
AD		 2085 /* nothing to do if LRO or RSC are not enabled */
2086 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2087 !(netdev->features & NETIF_F_LRO))
80fba3f4
AD		 2088 return false;
2089
567d2de2
AD		 2090 /* check the feature flag value and enable RSC if necessary */
2091 if (adapter->rx_itr_setting == 1 ||
2092 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2093 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
80fba3f4 2094 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
567d2de2
AD		 2095 e_info(probe, "rx-usecs value high enough "
2096 "to re-enable RSC\n");
80fba3f4
AD		 2097 return true;
2098 }
567d2de2
AD		 2099 /* if interrupt rate is too high then disable RSC */
2100 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2101 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2102 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2103 return true;
80fba3f4
AD		 2104 }
2105 return false;
2106}
2107
9a799d71 2108static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2109 struct ethtool_coalesce *ec)
9a799d71
AK		 2110{
2111 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2112 struct ixgbe_q_vector *q_vector;
30efa5a3 2113 int i;
67da097e 2114 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
ef021194 2115 bool need_reset = false;
9a799d71 2116
67da097e
ET		 2117 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2118 /* reject Tx specific changes in case of mixed RxTx vectors */
2119 if (ec->tx_coalesce_usecs)
2120 return -EINVAL;
2121 tx_itr_prev = adapter->rx_itr_setting;
2122 } else {
2123 tx_itr_prev = adapter->tx_itr_setting;
2124 }
f7554a2b 2125
d5bf4f67
ET		 2126 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2127 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2128 return -EINVAL;
30efa5a3 2129
d5bf4f67
ET		 2130 if (ec->rx_coalesce_usecs > 1)
2131 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2132 else
2133 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
f7554a2b 2134
d5bf4f67
ET		 2135 if (adapter->rx_itr_setting == 1)
2136 rx_itr_param = IXGBE_20K_ITR;
2137 else
2138 rx_itr_param = adapter->rx_itr_setting;
f7554a2b 2139
d5bf4f67
ET		 2140 if (ec->tx_coalesce_usecs > 1)
2141 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2142 else
2143 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
f7554a2b 2144
d5bf4f67
ET		 2145 if (adapter->tx_itr_setting == 1)
2146 tx_itr_param = IXGBE_10K_ITR;
2147 else
2148 tx_itr_param = adapter->tx_itr_setting;
f7554a2b 2149
67da097e
ET		 2150 /* mixed Rx/Tx */
2151 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2152 adapter->tx_itr_setting = adapter->rx_itr_setting;
2153
2154#if IS_ENABLED(CONFIG_BQL)
2155 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2156 if ((adapter->tx_itr_setting > 1) &&
2157 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2158 if ((tx_itr_prev == 1) ||
2159 (tx_itr_prev > IXGBE_100K_ITR))
2160 need_reset = true;
2161 } else {
2162 if ((tx_itr_prev > 1) &&
2163 (tx_itr_prev < IXGBE_100K_ITR))
2164 need_reset = true;
2165 }
2166#endif
567d2de2 2167 /* check the old value and enable RSC if necessary */
67da097e 2168 need_reset |= ixgbe_update_rsc(adapter);
567d2de2 2169
49c7ffbe 2170 for (i = 0; i < adapter->num_q_vectors; i++) {
d5bf4f67 2171 q_vector = adapter->q_vector[i];
d5bf4f67
ET		 2172 if (q_vector->tx.count && !q_vector->rx.count)
2173 /* tx only */
2174 q_vector->itr = tx_itr_param;
2175 else
2176 /* rx only or mixed */
2177 q_vector->itr = rx_itr_param;
fe49f04a 2178 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2179 }
2180
ef021194
JB		 2181 /*
2182 * do reset here at the end to make sure EITR==0 case is handled
2183 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2184 * also locks in RSC enable/disable which requires reset
2185 */
c988ee82
ET		 2186 if (need_reset)
2187 ixgbe_do_reset(netdev);
ef021194 2188
9a799d71
AK		 2189 return 0;
2190}
2191
3e05334f
AD		 2192static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2193 struct ethtool_rxnfc *cmd)
2194{
2195 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2196 struct ethtool_rx_flow_spec *fsp =
2197 (struct ethtool_rx_flow_spec *)&cmd->fs;
b67bfe0d 2198 struct hlist_node *node2;
3e05334f
AD		 2199 struct ixgbe_fdir_filter *rule = NULL;
2200
2201 /* report total rule count */
2202 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2203
b67bfe0d 2204 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2205 &adapter->fdir_filter_list, fdir_node) {
2206 if (fsp->location <= rule->sw_idx)
2207 break;
2208 }
2209
2210 if (!rule || fsp->location != rule->sw_idx)
2211 return -EINVAL;
2212
2213 /* fill out the flow spec entry */
2214
2215 /* set flow type field */
2216 switch (rule->filter.formatted.flow_type) {
2217 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2218 fsp->flow_type = TCP_V4_FLOW;
2219 break;
2220 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2221 fsp->flow_type = UDP_V4_FLOW;
2222 break;
2223 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2224 fsp->flow_type = SCTP_V4_FLOW;
2225 break;
2226 case IXGBE_ATR_FLOW_TYPE_IPV4:
2227 fsp->flow_type = IP_USER_FLOW;
2228 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2229 fsp->h_u.usr_ip4_spec.proto = 0;
2230 fsp->m_u.usr_ip4_spec.proto = 0;
2231 break;
2232 default:
2233 return -EINVAL;
2234 }
2235
2236 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2237 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2238 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2239 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2240 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2241 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2242 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2243 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2244 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2245 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2246 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2247 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2248 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2249 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2250 fsp->flow_type |= FLOW_EXT;
2251
2252 /* record action */
2253 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2254 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2255 else
2256 fsp->ring_cookie = rule->action;
2257
2258 return 0;
2259}
2260
2261static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2262 struct ethtool_rxnfc *cmd,
2263 u32 *rule_locs)
2264{
b67bfe0d 2265 struct hlist_node *node2;
3e05334f
AD		 2266 struct ixgbe_fdir_filter *rule;
2267 int cnt = 0;
2268
2269 /* report total rule count */
2270 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2271
b67bfe0d 2272 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2273 &adapter->fdir_filter_list, fdir_node) {
2274 if (cnt == cmd->rule_cnt)
2275 return -EMSGSIZE;
2276 rule_locs[cnt] = rule->sw_idx;
2277 cnt++;
2278 }
2279
473e64ee
BH		 2280 cmd->rule_cnt = cnt;
2281
3e05334f
AD		 2282 return 0;
2283}
2284
ef6afc0c
AD		 2285static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2286 struct ethtool_rxnfc *cmd)
2287{
2288 cmd->data = 0;
2289
ef6afc0c
AD		 2290 /* Report default options for RSS on ixgbe */
2291 switch (cmd->flow_type) {
2292 case TCP_V4_FLOW:
2293 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2294 case UDP_V4_FLOW:
2295 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2296 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2297 case SCTP_V4_FLOW:
2298 case AH_ESP_V4_FLOW:
2299 case AH_V4_FLOW:
2300 case ESP_V4_FLOW:
2301 case IPV4_FLOW:
2302 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2303 break;
2304 case TCP_V6_FLOW:
2305 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2306 case UDP_V6_FLOW:
2307 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2308 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2309 case SCTP_V6_FLOW:
2310 case AH_ESP_V6_FLOW:
2311 case AH_V6_FLOW:
2312 case ESP_V6_FLOW:
2313 case IPV6_FLOW:
2314 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2315 break;
2316 default:
2317 return -EINVAL;
2318 }
2319
2320 return 0;
2321}
2322
91cd94bf 2323static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
815c7db5 2324 u32 *rule_locs)
91cd94bf
AD		 2325{
2326 struct ixgbe_adapter *adapter = netdev_priv(dev);
2327 int ret = -EOPNOTSUPP;
2328
2329 switch (cmd->cmd) {
2330 case ETHTOOL_GRXRINGS:
2331 cmd->data = adapter->num_rx_queues;
2332 ret = 0;
2333 break;
3e05334f
AD		 2334 case ETHTOOL_GRXCLSRLCNT:
2335 cmd->rule_cnt = adapter->fdir_filter_count;
2336 ret = 0;
2337 break;
2338 case ETHTOOL_GRXCLSRULE:
2339 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2340 break;
2341 case ETHTOOL_GRXCLSRLALL:
815c7db5 2342 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
3e05334f 2343 break;
ef6afc0c
AD		 2344 case ETHTOOL_GRXFH:
2345 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2346 break;
91cd94bf
AD		 2347 default:
2348 break;
2349 }
2350
2351 return ret;
2352}
2353
e4911d57
AD		 2354static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2355 struct ixgbe_fdir_filter *input,
2356 u16 sw_idx)
2357{
2358 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d
SL		 2359 struct hlist_node *node2;
2360 struct ixgbe_fdir_filter *rule, *parent;
e4911d57
AD		 2361 int err = -EINVAL;
2362
2363 parent = NULL;
2364 rule = NULL;
2365
b67bfe0d 2366 hlist_for_each_entry_safe(rule, node2,
e4911d57
AD		 2367 &adapter->fdir_filter_list, fdir_node) {
2368 /* hash found, or no matching entry */
2369 if (rule->sw_idx >= sw_idx)
2370 break;
b67bfe0d 2371 parent = rule;
e4911d57
AD		 2372 }
2373
2374 /* if there is an old rule occupying our place remove it */
2375 if (rule && (rule->sw_idx == sw_idx)) {
2376 if (!input || (rule->filter.formatted.bkt_hash !=
2377 input->filter.formatted.bkt_hash)) {
2378 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2379 &rule->filter,
2380 sw_idx);
2381 }
2382
2383 hlist_del(&rule->fdir_node);
2384 kfree(rule);
2385 adapter->fdir_filter_count--;
2386 }
2387
2388 /*
2389 * If no input this was a delete, err should be 0 if a rule was
2390 * successfully found and removed from the list else -EINVAL
2391 */
2392 if (!input)
2393 return err;
2394
2395 /* initialize node and set software index */
2396 INIT_HLIST_NODE(&input->fdir_node);
2397
2398 /* add filter to the list */
2399 if (parent)
b67bfe0d 2400 hlist_add_after(&parent->fdir_node, &input->fdir_node);
e4911d57
AD		 2401 else
2402 hlist_add_head(&input->fdir_node,
2403 &adapter->fdir_filter_list);
2404
2405 /* update counts */
2406 adapter->fdir_filter_count++;
2407
2408 return 0;
2409}
2410
2411static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2412 u8 *flow_type)
2413{
2414 switch (fsp->flow_type & ~FLOW_EXT) {
2415 case TCP_V4_FLOW:
2416 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2417 break;
2418 case UDP_V4_FLOW:
2419 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2420 break;
2421 case SCTP_V4_FLOW:
2422 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2423 break;
2424 case IP_USER_FLOW:
2425 switch (fsp->h_u.usr_ip4_spec.proto) {
2426 case IPPROTO_TCP:
2427 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2428 break;
2429 case IPPROTO_UDP:
2430 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2431 break;
2432 case IPPROTO_SCTP:
2433 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2434 break;
2435 case 0:
2436 if (!fsp->m_u.usr_ip4_spec.proto) {
2437 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2438 break;
2439 }
2440 default:
2441 return 0;
2442 }
2443 break;
2444 default:
2445 return 0;
2446 }
2447
2448 return 1;
2449}
2450
2451static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2452 struct ethtool_rxnfc *cmd)
2453{
2454 struct ethtool_rx_flow_spec *fsp =
2455 (struct ethtool_rx_flow_spec *)&cmd->fs;
2456 struct ixgbe_hw *hw = &adapter->hw;
2457 struct ixgbe_fdir_filter *input;
2458 union ixgbe_atr_input mask;
2459 int err;
2460
2461 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2462 return -EOPNOTSUPP;
2463
2464 /*
2465 * Don't allow programming if the action is a queue greater than
2466 * the number of online Rx queues.
2467 */
2468 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2469 (fsp->ring_cookie >= adapter->num_rx_queues))
2470 return -EINVAL;
2471
2472 /* Don't allow indexes to exist outside of available space */
2473 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2474 e_err(drv, "Location out of range\n");
2475 return -EINVAL;
2476 }
2477
2478 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2479 if (!input)
2480 return -ENOMEM;
2481
2482 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2483
2484 /* set SW index */
2485 input->sw_idx = fsp->location;
2486
2487 /* record flow type */
2488 if (!ixgbe_flowspec_to_flow_type(fsp,
2489 &input->filter.formatted.flow_type)) {
2490 e_err(drv, "Unrecognized flow type\n");
2491 goto err_out;
2492 }
2493
2494 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2495 IXGBE_ATR_L4TYPE_MASK;
2496
2497 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2498 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2499
2500 /* Copy input into formatted structures */
2501 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2502 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2503 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2504 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2505 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2506 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2507 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2508 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2509
2510 if (fsp->flow_type & FLOW_EXT) {
2511 input->filter.formatted.vm_pool =
2512 (unsigned char)ntohl(fsp->h_ext.data[1]);
2513 mask.formatted.vm_pool =
2514 (unsigned char)ntohl(fsp->m_ext.data[1]);
2515 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2516 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2517 input->filter.formatted.flex_bytes =
2518 fsp->h_ext.vlan_etype;
2519 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2520 }
2521
2522 /* determine if we need to drop or route the packet */
2523 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2524 input->action = IXGBE_FDIR_DROP_QUEUE;
2525 else
2526 input->action = fsp->ring_cookie;
2527
2528 spin_lock(&adapter->fdir_perfect_lock);
2529
2530 if (hlist_empty(&adapter->fdir_filter_list)) {
2531 /* save mask and program input mask into HW */
2532 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2533 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2534 if (err) {
2535 e_err(drv, "Error writing mask\n");
2536 goto err_out_w_lock;
2537 }
2538 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2539 e_err(drv, "Only one mask supported per port\n");
2540 goto err_out_w_lock;
2541 }
2542
2543 /* apply mask and compute/store hash */
2544 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2545
2546 /* program filters to filter memory */
2547 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2548 &input->filter, input->sw_idx,
1f4d5183
AD		 2549 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2550 IXGBE_FDIR_DROP_QUEUE :
e4911d57
AD		 2551 adapter->rx_ring[input->action]->reg_idx);
2552 if (err)
2553 goto err_out_w_lock;
2554
2555 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2556
2557 spin_unlock(&adapter->fdir_perfect_lock);
2558
2559 return err;
2560err_out_w_lock:
2561 spin_unlock(&adapter->fdir_perfect_lock);
2562err_out:
2563 kfree(input);
2564 return -EINVAL;
2565}
2566
2567static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2568 struct ethtool_rxnfc *cmd)
2569{
2570 struct ethtool_rx_flow_spec *fsp =
2571 (struct ethtool_rx_flow_spec *)&cmd->fs;
2572 int err;
2573
2574 spin_lock(&adapter->fdir_perfect_lock);
2575 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2576 spin_unlock(&adapter->fdir_perfect_lock);
2577
2578 return err;
2579}
2580
ef6afc0c
AD		 2581#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2582 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2583static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2584 struct ethtool_rxnfc *nfc)
2585{
2586 u32 flags2 = adapter->flags2;
2587
2588 /*
2589 * RSS does not support anything other than hashing
2590 * to queues on src and dst IPs and ports
2591 */
2592 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2593 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2594 return -EINVAL;
2595
2596 switch (nfc->flow_type) {
2597 case TCP_V4_FLOW:
2598 case TCP_V6_FLOW:
2599 if (!(nfc->data & RXH_IP_SRC) ||
2600 !(nfc->data & RXH_IP_DST) ||
2601 !(nfc->data & RXH_L4_B_0_1) ||
2602 !(nfc->data & RXH_L4_B_2_3))
2603 return -EINVAL;
2604 break;
2605 case UDP_V4_FLOW:
2606 if (!(nfc->data & RXH_IP_SRC) ||
2607 !(nfc->data & RXH_IP_DST))
2608 return -EINVAL;
2609 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2610 case 0:
2611 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2612 break;
2613 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2614 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2615 break;
2616 default:
2617 return -EINVAL;
2618 }
2619 break;
2620 case UDP_V6_FLOW:
2621 if (!(nfc->data & RXH_IP_SRC) ||
2622 !(nfc->data & RXH_IP_DST))
2623 return -EINVAL;
2624 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2625 case 0:
2626 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2627 break;
2628 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2629 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2630 break;
2631 default:
2632 return -EINVAL;
2633 }
2634 break;
2635 case AH_ESP_V4_FLOW:
2636 case AH_V4_FLOW:
2637 case ESP_V4_FLOW:
2638 case SCTP_V4_FLOW:
2639 case AH_ESP_V6_FLOW:
2640 case AH_V6_FLOW:
2641 case ESP_V6_FLOW:
2642 case SCTP_V6_FLOW:
2643 if (!(nfc->data & RXH_IP_SRC) ||
2644 !(nfc->data & RXH_IP_DST) ||
2645 (nfc->data & RXH_L4_B_0_1) ||
2646 (nfc->data & RXH_L4_B_2_3))
2647 return -EINVAL;
2648 break;
2649 default:
2650 return -EINVAL;
2651 }
2652
2653 /* if we changed something we need to update flags */
2654 if (flags2 != adapter->flags2) {
2655 struct ixgbe_hw *hw = &adapter->hw;
2656 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2657
2658 if ((flags2 & UDP_RSS_FLAGS) &&
2659 !(adapter->flags2 & UDP_RSS_FLAGS))
2660 e_warn(drv, "enabling UDP RSS: fragmented packets"
2661 " may arrive out of order to the stack above\n");
2662
2663 adapter->flags2 = flags2;
2664
2665 /* Perform hash on these packet types */
2666 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2667 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2668 | IXGBE_MRQC_RSS_FIELD_IPV6
2669 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2670
2671 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2672 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2673
2674 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2675 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2676
2677 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2678 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2679
2680 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2681 }
2682
2683 return 0;
2684}
2685
e4911d57
AD		 2686static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2687{
2688 struct ixgbe_adapter *adapter = netdev_priv(dev);
2689 int ret = -EOPNOTSUPP;
2690
2691 switch (cmd->cmd) {
2692 case ETHTOOL_SRXCLSRLINS:
2693 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2694 break;
2695 case ETHTOOL_SRXCLSRLDEL:
2696 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2697 break;
ef6afc0c
AD		 2698 case ETHTOOL_SRXFH:
2699 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2700 break;
e4911d57
AD		 2701 default:
2702 break;
2703 }
2704
2705 return ret;
2706}
2707
e3aac889
JK		 2708static int ixgbe_get_ts_info(struct net_device *dev,
2709 struct ethtool_ts_info *info)
2710{
2711 struct ixgbe_adapter *adapter = netdev_priv(dev);
2712
2713 switch (adapter->hw.mac.type) {
e3aac889
JK		 2714 case ixgbe_mac_X540:
2715 case ixgbe_mac_82599EB:
2716 info->so_timestamping =
50f8d35d
JK		 2717 SOF_TIMESTAMPING_TX_SOFTWARE |
2718 SOF_TIMESTAMPING_RX_SOFTWARE |
2719 SOF_TIMESTAMPING_SOFTWARE |
e3aac889
JK		 2720 SOF_TIMESTAMPING_TX_HARDWARE |
2721 SOF_TIMESTAMPING_RX_HARDWARE |
2722 SOF_TIMESTAMPING_RAW_HARDWARE;
2723
2724 if (adapter->ptp_clock)
2725 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2726 else
2727 info->phc_index = -1;
2728
2729 info->tx_types =
2730 (1 << HWTSTAMP_TX_OFF) |
2731 (1 << HWTSTAMP_TX_ON);
2732
2733 info->rx_filters =
2734 (1 << HWTSTAMP_FILTER_NONE) |
2735 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2736 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
aeb82648
JK		 2737 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2738 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2739 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2740 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2741 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2742 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2743 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2744 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1cc92eb8 2745 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
e3aac889 2746 break;
e3aac889
JK		 2747 default:
2748 return ethtool_op_get_ts_info(dev, info);
2749 break;
2750 }
2751 return 0;
2752}
2753
5348c9db
AD		 2754static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2755{
2756 unsigned int max_combined;
2757 u8 tcs = netdev_get_num_tc(adapter->netdev);
2758
2759 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2760 /* We only support one q_vector without MSI-X */
2761 max_combined = 1;
2762 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2763 /* SR-IOV currently only allows one queue on the PF */
2764 max_combined = 1;
2765 } else if (tcs > 1) {
2766 /* For DCB report channels per traffic class */
2767 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2768 /* 8 TC w/ 4 queues per TC */
2769 max_combined = 4;
2770 } else if (tcs > 4) {
2771 /* 8 TC w/ 8 queues per TC */
2772 max_combined = 8;
2773 } else {
2774 /* 4 TC w/ 16 queues per TC */
2775 max_combined = 16;
2776 }
2777 } else if (adapter->atr_sample_rate) {
2778 /* support up to 64 queues with ATR */
2779 max_combined = IXGBE_MAX_FDIR_INDICES;
2780 } else {
2781 /* support up to 16 queues with RSS */
2782 max_combined = IXGBE_MAX_RSS_INDICES;
2783 }
2784
2785 return max_combined;
2786}
2787
2788static void ixgbe_get_channels(struct net_device *dev,
2789 struct ethtool_channels *ch)
2790{
2791 struct ixgbe_adapter *adapter = netdev_priv(dev);
2792
2793 /* report maximum channels */
2794 ch->max_combined = ixgbe_max_channels(adapter);
2795
2796 /* report info for other vector */
2797 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2798 ch->max_other = NON_Q_VECTORS;
2799 ch->other_count = NON_Q_VECTORS;
2800 }
2801
2802 /* record RSS queues */
2803 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2804
2805 /* nothing else to report if RSS is disabled */
2806 if (ch->combined_count == 1)
2807 return;
2808
2809 /* we do not support ATR queueing if SR-IOV is enabled */
2810 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2811 return;
2812
2813 /* same thing goes for being DCB enabled */
2814 if (netdev_get_num_tc(dev) > 1)
2815 return;
2816
2817 /* if ATR is disabled we can exit */
2818 if (!adapter->atr_sample_rate)
2819 return;
2820
2821 /* report flow director queues as maximum channels */
2822 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
2823}
2824
4c696ca9
AD		 2825static int ixgbe_set_channels(struct net_device *dev,
2826 struct ethtool_channels *ch)
2827{
2828 struct ixgbe_adapter *adapter = netdev_priv(dev);
2829 unsigned int count = ch->combined_count;
2830
2831 /* verify they are not requesting separate vectors */
2832 if (!count || ch->rx_count || ch->tx_count)
2833 return -EINVAL;
2834
2835 /* verify other_count has not changed */
2836 if (ch->other_count != NON_Q_VECTORS)
2837 return -EINVAL;
2838
2839 /* verify the number of channels does not exceed hardware limits */
2840 if (count > ixgbe_max_channels(adapter))
2841 return -EINVAL;
2842
2843 /* update feature limits from largest to smallest supported values */
2844 adapter->ring_feature[RING_F_FDIR].limit = count;
2845
2846 /* cap RSS limit at 16 */
2847 if (count > IXGBE_MAX_RSS_INDICES)
2848 count = IXGBE_MAX_RSS_INDICES;
2849 adapter->ring_feature[RING_F_RSS].limit = count;
2850
2851#ifdef IXGBE_FCOE
2852 /* cap FCoE limit at 8 */
2853 if (count > IXGBE_FCRETA_SIZE)
2854 count = IXGBE_FCRETA_SIZE;
2855 adapter->ring_feature[RING_F_FCOE].limit = count;
2856
2857#endif
2858 /* use setup TC to update any traffic class queue mapping */
2859 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
2860}
2861
71858acb
AG		 2862static int ixgbe_get_module_info(struct net_device *dev,
2863 struct ethtool_modinfo *modinfo)
2864{
2865 struct ixgbe_adapter *adapter = netdev_priv(dev);
2866 struct ixgbe_hw *hw = &adapter->hw;
2867 u32 status;
2868 u8 sff8472_rev, addr_mode;
2869 int ret_val = 0;
2870 bool page_swap = false;
2871
2872 /* avoid concurent i2c reads */
2873 while (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
2874 msleep(100);
2875
2876 /* used by the service task */
2877 set_bit(__IXGBE_READ_I2C, &adapter->state);
2878
2879 /* Check whether we support SFF-8472 or not */
2880 status = hw->phy.ops.read_i2c_eeprom(hw,
2881 IXGBE_SFF_SFF_8472_COMP,
2882 &sff8472_rev);
2883 if (status != 0) {
2884 ret_val = -EIO;
2885 goto err_out;
2886 }
2887
2888 /* addressing mode is not supported */
2889 status = hw->phy.ops.read_i2c_eeprom(hw,
2890 IXGBE_SFF_SFF_8472_SWAP,
2891 &addr_mode);
2892 if (status != 0) {
2893 ret_val = -EIO;
2894 goto err_out;
2895 }
2896
2897 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
2898 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2899 page_swap = true;
2900 }
2901
2902 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
2903 /* We have a SFP, but it does not support SFF-8472 */
2904 modinfo->type = ETH_MODULE_SFF_8079;
2905 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2906 } else {
2907 /* We have a SFP which supports a revision of SFF-8472. */
2908 modinfo->type = ETH_MODULE_SFF_8472;
2909 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2910 }
2911
2912err_out:
2913 clear_bit(__IXGBE_READ_I2C, &adapter->state);
2914 return ret_val;
2915}
2916
2917static int ixgbe_get_module_eeprom(struct net_device *dev,
2918 struct ethtool_eeprom *ee,
2919 u8 *data)
2920{
2921 struct ixgbe_adapter *adapter = netdev_priv(dev);
2922 struct ixgbe_hw *hw = &adapter->hw;
2923 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2924 u8 databyte = 0xFF;
2925 int i = 0;
2926 int ret_val = 0;
2927
2928 /* ixgbe_get_module_info is called before this function in all
2929 * cases, so we do not need any checks we already do above,
2930 * and can trust ee->len to be a known value.
2931 */
2932
2933 while (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
2934 msleep(100);
2935 set_bit(__IXGBE_READ_I2C, &adapter->state);
2936
2937 /* Read the first block, SFF-8079 */
2938 for (i = 0; i < ETH_MODULE_SFF_8079_LEN; i++) {
2939 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
2940 if (status != 0) {
2941 /* Error occured while reading module */
2942 ret_val = -EIO;
2943 goto err_out;
2944 }
2945 data[i] = databyte;
2946 }
2947
2948 /* If the second block is requested, check if SFF-8472 is supported. */
2949 if (ee->len == ETH_MODULE_SFF_8472_LEN) {
2950 if (data[IXGBE_SFF_SFF_8472_COMP] == IXGBE_SFF_SFF_8472_UNSUP)
2951 return -EOPNOTSUPP;
2952
2953 /* Read the second block, SFF-8472 */
2954 for (i = ETH_MODULE_SFF_8079_LEN;
2955 i < ETH_MODULE_SFF_8472_LEN; i++) {
2956 status = hw->phy.ops.read_i2c_sff8472(hw,
2957 i - ETH_MODULE_SFF_8079_LEN, &databyte);
2958 if (status != 0) {
2959 /* Error occured while reading module */
2960 ret_val = -EIO;
2961 goto err_out;
2962 }
2963 data[i] = databyte;
2964 }
2965 }
2966
2967err_out:
2968 clear_bit(__IXGBE_READ_I2C, &adapter->state);
2969
2970 return ret_val;
2971}
2972
b9804972 2973static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2974 .get_settings = ixgbe_get_settings,
2975 .set_settings = ixgbe_set_settings,
2976 .get_drvinfo = ixgbe_get_drvinfo,
2977 .get_regs_len = ixgbe_get_regs_len,
2978 .get_regs = ixgbe_get_regs,
2979 .get_wol = ixgbe_get_wol,
e63d9762 2980 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2981 .nway_reset = ixgbe_nway_reset,
2982 .get_link = ethtool_op_get_link,
2983 .get_eeprom_len = ixgbe_get_eeprom_len,
2984 .get_eeprom = ixgbe_get_eeprom,
2fa5eef4 2985 .set_eeprom = ixgbe_set_eeprom,
9a799d71
AK		 2986 .get_ringparam = ixgbe_get_ringparam,
2987 .set_ringparam = ixgbe_set_ringparam,
2988 .get_pauseparam = ixgbe_get_pauseparam,
2989 .set_pauseparam = ixgbe_set_pauseparam,
9a799d71
AK		 2990 .get_msglevel = ixgbe_get_msglevel,
2991 .set_msglevel = ixgbe_set_msglevel,
da4dd0f7 2992 .self_test = ixgbe_diag_test,
9a799d71 2993 .get_strings = ixgbe_get_strings,
66e6961c 2994 .set_phys_id = ixgbe_set_phys_id,
b4617240 2995 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2996 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2997 .get_coalesce = ixgbe_get_coalesce,
2998 .set_coalesce = ixgbe_set_coalesce,
91cd94bf 2999 .get_rxnfc = ixgbe_get_rxnfc,
e4911d57 3000 .set_rxnfc = ixgbe_set_rxnfc,
5348c9db 3001 .get_channels = ixgbe_get_channels,
4c696ca9 3002 .set_channels = ixgbe_set_channels,
e3aac889 3003 .get_ts_info = ixgbe_get_ts_info,
71858acb
AG		 3004 .get_module_info = ixgbe_get_module_info,
3005 .get_module_eeprom = ixgbe_get_module_eeprom,
9a799d71
AK		 3006};
3007
3008void ixgbe_set_ethtool_ops(struct net_device *netdev)
3009{
3010 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
3011}
Linux kernel - Deliverables
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