projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: fix ethtool loopback diagnostic with DCB enabled
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
a6b7a407 30#include <linux/interrupt.h>
9a799d71
AK		 31#include <linux/types.h>
32#include <linux/module.h>
5a0e3ad6 33#include <linux/slab.h>
9a799d71
AK		 34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/ethtool.h>
37#include <linux/vmalloc.h>
f800326d 38#include <linux/highmem.h>
9a799d71
AK		 39#include <linux/uaccess.h>
40
41#include "ixgbe.h"
71858acb 42#include "ixgbe_phy.h"
9a799d71
AK		 43
44
45#define IXGBE_ALL_RAR_ENTRIES 16
46
29c3a050
AK		 47enum {NETDEV_STATS, IXGBE_STATS};
48
9a799d71
AK		 49struct ixgbe_stats {
50 char stat_string[ETH_GSTRING_LEN];
29c3a050 51 int type;
9a799d71
AK		 52 int sizeof_stat;
53 int stat_offset;
54};
55
29c3a050
AK		 56#define IXGBE_STAT(m) IXGBE_STATS, \
57 sizeof(((struct ixgbe_adapter *)0)->m), \
58 offsetof(struct ixgbe_adapter, m)
59#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 60 sizeof(((struct rtnl_link_stats64 *)0)->m), \
61 offsetof(struct rtnl_link_stats64, m)
29c3a050 62
1bba2e81 63static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 64 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
65 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
66 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
67 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 68 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
69 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
70 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
71 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 72 {"lsc_int", IXGBE_STAT(lsc_int)},
73 {"tx_busy", IXGBE_STAT(tx_busy)},
74 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 75 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
76 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
77 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
78 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
79 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 80 {"broadcast", IXGBE_STAT(stats.bprc)},
81 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 82 {"collisions", IXGBE_NETDEV_STAT(collisions)},
83 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
84 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
85 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 86 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
87 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 88 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
89 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
d034acf1 90 {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
55bad823
ED		 91 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
92 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
93 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
94 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
95 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
96 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 97 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
98 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
99 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
100 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 101 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
102 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
103 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
104 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 105 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 106 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
107 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 108 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
58f6bcf9
ET		 109 {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
110 {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
111 {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
112 {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
6d45522c
YZ		 113#ifdef IXGBE_FCOE
114 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
115 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
116 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
117 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
7b859ebc
AH		 118 {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
119 {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
6d45522c
YZ		 120 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
121 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
122#endif /* IXGBE_FCOE */
9a799d71
AK		 123};
124
9cc00b51
JF		 125/* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
126 * we set the num_rx_queues to evaluate to num_tx_queues. This is
127 * used because we do not have a good way to get the max number of
128 * rx queues with CONFIG_RPS disabled.
129 */
130#define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
131
132#define IXGBE_QUEUE_STATS_LEN ( \
133 (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
454d7c9b 134 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 135#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 136#define IXGBE_PB_STATS_LEN ( \
9cc00b51
JF		 137 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
138 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
139 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
140 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
141 / sizeof(u64))
2f90b865
AD		 142#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
143 IXGBE_PB_STATS_LEN + \
144 IXGBE_QUEUE_STATS_LEN)
9a799d71 145
da4dd0f7
PWJ		 146static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
147 "Register test (offline)", "Eeprom test (offline)",
148 "Interrupt test (offline)", "Loopback test (offline)",
149 "Link test (on/offline)"
150};
151#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
152
9a799d71 153static int ixgbe_get_settings(struct net_device *netdev,
b4617240 154 struct ethtool_cmd *ecmd)
9a799d71
AK		 155{
156 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 157 struct ixgbe_hw *hw = &adapter->hw;
db018963 158 ixgbe_link_speed supported_link;
735441fb 159 u32 link_speed = 0;
fd0326f2 160 bool autoneg = false;
735441fb 161 bool link_up;
9a799d71 162
db018963 163 hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
1b1c0a48 164
db018963
JK		 165 /* set the supported link speeds */
166 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
167 ecmd->supported |= SUPPORTED_10000baseT_Full;
168 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
169 ecmd->supported |= SUPPORTED_1000baseT_Full;
170 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
171 ecmd->supported |= SUPPORTED_100baseT_Full;
1b1c0a48 172
db018963
JK		 173 /* set the advertised speeds */
174 if (hw->phy.autoneg_advertised) {
175 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
176 ecmd->advertising |= ADVERTISED_100baseT_Full;
177 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
178 ecmd->advertising |= ADVERTISED_10000baseT_Full;
179 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
180 ecmd->advertising |= ADVERTISED_1000baseT_Full;
735441fb 181 } else {
db018963
JK		 182 /* default modes in case phy.autoneg_advertised isn't set */
183 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
184 ecmd->advertising |= ADVERTISED_10000baseT_Full;
185 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
186 ecmd->advertising |= ADVERTISED_1000baseT_Full;
187 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
188 ecmd->advertising |= ADVERTISED_100baseT_Full;
735441fb 189 }
9a799d71 190
db018963
JK		 191 if (autoneg) {
192 ecmd->supported |= SUPPORTED_Autoneg;
193 ecmd->advertising |= ADVERTISED_Autoneg;
194 ecmd->autoneg = AUTONEG_ENABLE;
195 } else
196 ecmd->autoneg = AUTONEG_DISABLE;
197
198 ecmd->transceiver = XCVR_EXTERNAL;
199
200 /* Determine the remaining settings based on the PHY type. */
3b8626ba
PW		 201 switch (adapter->hw.phy.type) {
202 case ixgbe_phy_tn:
fe15e8e1 203 case ixgbe_phy_aq:
3b8626ba 204 case ixgbe_phy_cu_unknown:
db018963
JK		 205 ecmd->supported |= SUPPORTED_TP;
206 ecmd->advertising |= ADVERTISED_TP;
3b8626ba
PW		 207 ecmd->port = PORT_TP;
208 break;
209 case ixgbe_phy_qt:
db018963
JK		 210 ecmd->supported |= SUPPORTED_FIBRE;
211 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
ea0a04df
DS		 215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
3b8626ba 221 /* SFP+ devices, further checking needed */
db018963 222 switch (adapter->hw.phy.sfp_type) {
3b8626ba
PW		 223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
db018963
JK		 226 ecmd->supported |= SUPPORTED_FIBRE;
227 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 228 ecmd->port = PORT_DA;
229 break;
230 case ixgbe_sfp_type_sr:
231 case ixgbe_sfp_type_lr:
232 case ixgbe_sfp_type_srlr_core0:
233 case ixgbe_sfp_type_srlr_core1:
345be204
DS		 234 case ixgbe_sfp_type_1g_sx_core0:
235 case ixgbe_sfp_type_1g_sx_core1:
236 case ixgbe_sfp_type_1g_lx_core0:
237 case ixgbe_sfp_type_1g_lx_core1:
db018963
JK		 238 ecmd->supported |= SUPPORTED_FIBRE;
239 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 240 ecmd->port = PORT_FIBRE;
241 break;
242 case ixgbe_sfp_type_not_present:
db018963
JK		 243 ecmd->supported |= SUPPORTED_FIBRE;
244 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 245 ecmd->port = PORT_NONE;
246 break;
cb836a97
DS		 247 case ixgbe_sfp_type_1g_cu_core0:
248 case ixgbe_sfp_type_1g_cu_core1:
db018963
JK		 249 ecmd->supported |= SUPPORTED_TP;
250 ecmd->advertising |= ADVERTISED_TP;
cb836a97 251 ecmd->port = PORT_TP;
db018963 252 break;
3b8626ba
PW		 253 case ixgbe_sfp_type_unknown:
254 default:
db018963
JK		 255 ecmd->supported |= SUPPORTED_FIBRE;
256 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 257 ecmd->port = PORT_OTHER;
258 break;
259 }
260 break;
261 case ixgbe_phy_xaui:
db018963
JK		 262 ecmd->supported |= SUPPORTED_FIBRE;
263 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 264 ecmd->port = PORT_NONE;
265 break;
266 case ixgbe_phy_unknown:
267 case ixgbe_phy_generic:
268 case ixgbe_phy_sfp_unsupported:
269 default:
db018963
JK		 270 ecmd->supported |= SUPPORTED_FIBRE;
271 ecmd->advertising |= ADVERTISED_FIBRE;
3b8626ba
PW		 272 ecmd->port = PORT_OTHER;
273 break;
274 }
275
c44ade9e 276 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb 277 if (link_up) {
1b1c0a48
AS		 278 switch (link_speed) {
279 case IXGBE_LINK_SPEED_10GB_FULL:
70739497 280 ethtool_cmd_speed_set(ecmd, SPEED_10000);
1b1c0a48
AS		 281 break;
282 case IXGBE_LINK_SPEED_1GB_FULL:
70739497 283 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1b1c0a48
AS		 284 break;
285 case IXGBE_LINK_SPEED_100_FULL:
70739497 286 ethtool_cmd_speed_set(ecmd, SPEED_100);
1b1c0a48
AS		 287 break;
288 default:
289 break;
290 }
9a799d71
AK		 291 ecmd->duplex = DUPLEX_FULL;
292 } else {
70739497 293 ethtool_cmd_speed_set(ecmd, -1);
9a799d71
AK		 294 ecmd->duplex = -1;
295 }
296
9a799d71
AK		 297 return 0;
298}
299
300static int ixgbe_set_settings(struct net_device *netdev,
b4617240 301 struct ethtool_cmd *ecmd)
9a799d71
AK		 302{
303 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 304 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 305 u32 advertised, old;
74766013 306 s32 err = 0;
9a799d71 307
74766013 308 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 309 (hw->phy.multispeed_fiber)) {
abcc80d2
ET		 310 /*
311 * this function does not support duplex forcing, but can
312 * limit the advertising of the adapter to the specified speed
313 */
abcc80d2
ET		 314 if (ecmd->advertising & ~ecmd->supported)
315 return -EINVAL;
316
0befdb3e
JB		 317 old = hw->phy.autoneg_advertised;
318 advertised = 0;
319 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
320 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
321
322 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
323 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
324
2b642ca5
ET		 325 if (ecmd->advertising & ADVERTISED_100baseT_Full)
326 advertised |= IXGBE_LINK_SPEED_100_FULL;
327
0befdb3e 328 if (old == advertised)
74766013 329 return err;
0befdb3e 330 /* this sets the link speed and restarts auto-neg */
74766013 331 hw->mac.autotry_restart = true;
fd0326f2 332 err = hw->mac.ops.setup_link(hw, advertised, true);
0befdb3e 333 if (err) {
396e799c 334 e_info(probe, "setup link failed with code %d\n", err);
fd0326f2 335 hw->mac.ops.setup_link(hw, old, true);
0befdb3e 336 }
74766013
MC		 337 } else {
338 /* in this case we currently only support 10Gb/FULL */
25db0338 339 u32 speed = ethtool_cmd_speed(ecmd);
74766013 340 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 341 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
25db0338 342 (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
74766013 343 return -EINVAL;
9a799d71
AK		 344 }
345
74766013 346 return err;
9a799d71
AK		 347}
348
349static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 350 struct ethtool_pauseparam *pause)
9a799d71
AK		 351{
352 struct ixgbe_adapter *adapter = netdev_priv(netdev);
353 struct ixgbe_hw *hw = &adapter->hw;
354
73d80953
DS		 355 if (ixgbe_device_supports_autoneg_fc(hw) &&
356 !hw->fc.disable_fc_autoneg)
71fd570b 357 pause->autoneg = 1;
73d80953
DS		 358 else
359 pause->autoneg = 0;
9a799d71 360
0ecc061d 361 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 362 pause->rx_pause = 1;
0ecc061d 363 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 364 pause->tx_pause = 1;
0ecc061d 365 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 366 pause->rx_pause = 1;
367 pause->tx_pause = 1;
368 }
369}
370
371static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 372 struct ethtool_pauseparam *pause)
9a799d71
AK		 373{
374 struct ixgbe_adapter *adapter = netdev_priv(netdev);
375 struct ixgbe_hw *hw = &adapter->hw;
943561d3 376 struct ixgbe_fc_info fc = hw->fc;
9a799d71 377
943561d3
AD		 378 /* 82598 does no support link flow control with DCB enabled */
379 if ((hw->mac.type == ixgbe_mac_82598EB) &&
380 (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
264857b8
PWJ		 381 return -EINVAL;
382
db2adc2d
JK		 383 /* some devices do not support autoneg of link flow control */
384 if ((pause->autoneg == AUTONEG_ENABLE) &&
73d80953 385 !ixgbe_device_supports_autoneg_fc(hw))
db2adc2d
JK		 386 return -EINVAL;
387
943561d3 388 fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
71fd570b 389
1c4f0ef8 390 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 391 fc.requested_mode = ixgbe_fc_full;
9a799d71 392 else if (pause->rx_pause && !pause->tx_pause)
620fa036 393 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 394 else if (!pause->rx_pause && pause->tx_pause)
620fa036 395 fc.requested_mode = ixgbe_fc_tx_pause;
9c83b070 396 else
943561d3 397 fc.requested_mode = ixgbe_fc_none;
620fa036
MC		 398
399 /* if the thing changed then we'll update and use new autoneg */
400 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
401 hw->fc = fc;
402 if (netif_running(netdev))
403 ixgbe_reinit_locked(adapter);
404 else
405 ixgbe_reset(adapter);
406 }
9a799d71
AK		 407
408 return 0;
409}
410
9a799d71
AK		 411static u32 ixgbe_get_msglevel(struct net_device *netdev)
412{
413 struct ixgbe_adapter *adapter = netdev_priv(netdev);
414 return adapter->msg_enable;
415}
416
417static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
418{
419 struct ixgbe_adapter *adapter = netdev_priv(netdev);
420 adapter->msg_enable = data;
421}
422
423static int ixgbe_get_regs_len(struct net_device *netdev)
424{
217995ec 425#define IXGBE_REGS_LEN 1129
9a799d71
AK		 426 return IXGBE_REGS_LEN * sizeof(u32);
427}
428
429#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
430
431static void ixgbe_get_regs(struct net_device *netdev,
b4617240 432 struct ethtool_regs *regs, void *p)
9a799d71
AK		 433{
434 struct ixgbe_adapter *adapter = netdev_priv(netdev);
435 struct ixgbe_hw *hw = &adapter->hw;
436 u32 *regs_buff = p;
437 u8 i;
438
439 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
440
c4a56de8
ET		 441 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
442 hw->device_id;
9a799d71
AK		 443
444 /* General Registers */
445 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
446 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
447 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
448 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
449 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
450 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
451 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
452 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
453
454 /* NVM Register */
455 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
456 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
457 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
458 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
459 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
460 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
461 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
462 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
463 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
464 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
465
466 /* Interrupt */
98c00a1c
JB		 467 /* don't read EICR because it can clear interrupt causes, instead
468 * read EICS which is a shadow but doesn't clear EICR */
469 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 470 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
471 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
472 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
473 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
474 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
475 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
476 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
477 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
478 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 479 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 480 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
481
482 /* Flow Control */
483 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
484 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
485 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
486 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
487 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 488 for (i = 0; i < 8; i++) {
489 switch (hw->mac.type) {
490 case ixgbe_mac_82598EB:
491 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
492 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
493 break;
494 case ixgbe_mac_82599EB:
80bb25e3 495 case ixgbe_mac_X540:
bd508178
AD		 496 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
497 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
498 break;
499 default:
500 break;
501 }
502 }
9a799d71
AK		 503 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
504 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
505
506 /* Receive DMA */
507 for (i = 0; i < 64; i++)
508 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
509 for (i = 0; i < 64; i++)
510 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
511 for (i = 0; i < 64; i++)
512 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
513 for (i = 0; i < 64; i++)
514 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
515 for (i = 0; i < 64; i++)
516 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
517 for (i = 0; i < 64; i++)
518 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
519 for (i = 0; i < 16; i++)
520 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
521 for (i = 0; i < 16; i++)
522 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
523 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
524 for (i = 0; i < 8; i++)
525 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
526 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
527 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
528
529 /* Receive */
530 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
531 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
532 for (i = 0; i < 16; i++)
533 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
534 for (i = 0; i < 16; i++)
535 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 536 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 537 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
538 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
539 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
540 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
541 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
542 for (i = 0; i < 8; i++)
543 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
544 for (i = 0; i < 8; i++)
545 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
546 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
547
548 /* Transmit */
549 for (i = 0; i < 32; i++)
550 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
551 for (i = 0; i < 32; i++)
552 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
553 for (i = 0; i < 32; i++)
554 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
555 for (i = 0; i < 32; i++)
556 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
557 for (i = 0; i < 32; i++)
558 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
559 for (i = 0; i < 32; i++)
560 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
561 for (i = 0; i < 32; i++)
562 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
563 for (i = 0; i < 32; i++)
564 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
565 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
566 for (i = 0; i < 16; i++)
567 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
568 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
569 for (i = 0; i < 8; i++)
570 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
571 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
572
573 /* Wake Up */
574 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
575 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
576 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
577 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
578 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
579 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
580 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
581 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 582 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 583
673ac604 584 /* DCB */
9a799d71
AK		 585 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
586 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
587 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
588 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
589 for (i = 0; i < 8; i++)
590 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
591 for (i = 0; i < 8; i++)
592 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
593 for (i = 0; i < 8; i++)
594 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
595 for (i = 0; i < 8; i++)
596 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
597 for (i = 0; i < 8; i++)
598 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
599 for (i = 0; i < 8; i++)
600 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
601
602 /* Statistics */
603 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
604 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
605 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
606 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
607 for (i = 0; i < 8; i++)
608 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
609 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
610 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
611 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
612 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
613 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
614 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
615 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
616 for (i = 0; i < 8; i++)
617 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
618 for (i = 0; i < 8; i++)
619 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
620 for (i = 0; i < 8; i++)
621 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
622 for (i = 0; i < 8; i++)
623 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
624 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
625 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
626 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
627 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
628 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
629 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
630 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
631 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
632 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
633 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
634 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
635 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
636 for (i = 0; i < 8; i++)
637 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
638 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
639 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
640 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
641 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
642 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
643 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
644 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
645 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
646 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
647 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
648 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
649 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
650 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
651 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
652 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
653 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
654 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
655 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
656 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
657 for (i = 0; i < 16; i++)
658 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
659 for (i = 0; i < 16; i++)
660 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
661 for (i = 0; i < 16; i++)
662 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
663 for (i = 0; i < 16; i++)
664 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
665
666 /* MAC */
667 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
668 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
669 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
670 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
671 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
672 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
673 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
674 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
675 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
676 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
677 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
678 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
679 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
680 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
681 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
682 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
683 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
684 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
685 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
686 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
687 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
688 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
689 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
690 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
691 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
692 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
693 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
694 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
695 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
696 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
697 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
698 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
699 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
700
701 /* Diagnostic */
702 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
703 for (i = 0; i < 8; i++)
98c00a1c 704 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 705 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 706 for (i = 0; i < 4; i++)
707 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 708 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
709 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
710 for (i = 0; i < 8; i++)
98c00a1c 711 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 712 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 713 for (i = 0; i < 4; i++)
714 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 715 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
716 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
717 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
718 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
719 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
720 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
721 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
722 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
723 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
724 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
725 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
726 for (i = 0; i < 8; i++)
98c00a1c 727 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 728 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
729 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
730 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
731 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
732 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
733 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
734 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
735 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
736 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
217995ec
ET		 737
738 /* 82599 X540 specific registers */
739 regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
9a799d71
AK		 740}
741
742static int ixgbe_get_eeprom_len(struct net_device *netdev)
743{
744 struct ixgbe_adapter *adapter = netdev_priv(netdev);
745 return adapter->hw.eeprom.word_size * 2;
746}
747
748static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 749 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 750{
751 struct ixgbe_adapter *adapter = netdev_priv(netdev);
752 struct ixgbe_hw *hw = &adapter->hw;
753 u16 *eeprom_buff;
754 int first_word, last_word, eeprom_len;
755 int ret_val = 0;
756 u16 i;
757
758 if (eeprom->len == 0)
759 return -EINVAL;
760
761 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
762
763 first_word = eeprom->offset >> 1;
764 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
765 eeprom_len = last_word - first_word + 1;
766
767 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
768 if (!eeprom_buff)
769 return -ENOMEM;
770
68c7005d
ET		 771 ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
772 eeprom_buff);
9a799d71
AK		 773
774 /* Device's eeprom is always little-endian, word addressable */
775 for (i = 0; i < eeprom_len; i++)
776 le16_to_cpus(&eeprom_buff[i]);
777
778 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
779 kfree(eeprom_buff);
780
781 return ret_val;
782}
783
2fa5eef4
ET		 784static int ixgbe_set_eeprom(struct net_device *netdev,
785 struct ethtool_eeprom *eeprom, u8 *bytes)
786{
787 struct ixgbe_adapter *adapter = netdev_priv(netdev);
788 struct ixgbe_hw *hw = &adapter->hw;
789 u16 *eeprom_buff;
790 void *ptr;
791 int max_len, first_word, last_word, ret_val = 0;
792 u16 i;
793
794 if (eeprom->len == 0)
795 return -EINVAL;
796
797 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
798 return -EINVAL;
799
800 max_len = hw->eeprom.word_size * 2;
801
802 first_word = eeprom->offset >> 1;
803 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
804 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
805 if (!eeprom_buff)
806 return -ENOMEM;
807
808 ptr = eeprom_buff;
809
810 if (eeprom->offset & 1) {
811 /*
812 * need read/modify/write of first changed EEPROM word
813 * only the second byte of the word is being modified
814 */
815 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
816 if (ret_val)
817 goto err;
818
819 ptr++;
820 }
821 if ((eeprom->offset + eeprom->len) & 1) {
822 /*
823 * need read/modify/write of last changed EEPROM word
824 * only the first byte of the word is being modified
825 */
826 ret_val = hw->eeprom.ops.read(hw, last_word,
827 &eeprom_buff[last_word - first_word]);
828 if (ret_val)
829 goto err;
830 }
831
832 /* Device's eeprom is always little-endian, word addressable */
833 for (i = 0; i < last_word - first_word + 1; i++)
834 le16_to_cpus(&eeprom_buff[i]);
835
836 memcpy(ptr, bytes, eeprom->len);
837
838 for (i = 0; i < last_word - first_word + 1; i++)
839 cpu_to_le16s(&eeprom_buff[i]);
840
841 ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
842 last_word - first_word + 1,
843 eeprom_buff);
844
845 /* Update the checksum */
846 if (ret_val == 0)
847 hw->eeprom.ops.update_checksum(hw);
848
849err:
850 kfree(eeprom_buff);
851 return ret_val;
852}
853
9a799d71 854static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 855 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 856{
857 struct ixgbe_adapter *adapter = netdev_priv(netdev);
15e5209f 858 u32 nvm_track_id;
9a799d71 859
612a94d6
RJ		 860 strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
861 strlcpy(drvinfo->version, ixgbe_driver_version,
862 sizeof(drvinfo->version));
083fc582 863
15e5209f
ET		 864 nvm_track_id = (adapter->eeprom_verh << 16) |
865 adapter->eeprom_verl;
612a94d6 866 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
15e5209f 867 nvm_track_id);
083fc582 868
612a94d6
RJ		 869 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
870 sizeof(drvinfo->bus_info));
9a799d71 871 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 872 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 873 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
874}
875
876static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 877 struct ethtool_ringparam *ring)
9a799d71
AK		 878{
879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 880 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
881 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 882
883 ring->rx_max_pending = IXGBE_MAX_RXD;
884 ring->tx_max_pending = IXGBE_MAX_TXD;
9a799d71
AK		 885 ring->rx_pending = rx_ring->count;
886 ring->tx_pending = tx_ring->count;
9a799d71
AK		 887}
888
889static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 890 struct ethtool_ringparam *ring)
9a799d71
AK		 891{
892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1f4702aa 893 struct ixgbe_ring *temp_ring;
759884b4 894 int i, err = 0;
c431f97e 895 u32 new_rx_count, new_tx_count;
9a799d71
AK		 896
897 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
898 return -EINVAL;
899
1f4702aa
AD		 900 new_tx_count = clamp_t(u32, ring->tx_pending,
901 IXGBE_MIN_TXD, IXGBE_MAX_TXD);
9a799d71
AK		 902 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
903
1f4702aa
AD		 904 new_rx_count = clamp_t(u32, ring->rx_pending,
905 IXGBE_MIN_RXD, IXGBE_MAX_RXD);
906 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
907
908 if ((new_tx_count == adapter->tx_ring_count) &&
909 (new_rx_count == adapter->rx_ring_count)) {
9a799d71
AK		 910 /* nothing to do */
911 return 0;
912 }
913
d4f80882 914 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 915 usleep_range(1000, 2000);
d4f80882 916
759884b4
AD		 917 if (!netif_running(adapter->netdev)) {
918 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 919 adapter->tx_ring[i]->count = new_tx_count;
759884b4 920 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 921 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 922 adapter->tx_ring_count = new_tx_count;
923 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 924 goto clear_reset;
759884b4
AD		 925 }
926
1f4702aa
AD		 927 /* allocate temporary buffer to store rings in */
928 i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
929 temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
930
931 if (!temp_ring) {
f9ed8854 932 err = -ENOMEM;
4a0b9ca0 933 goto clear_reset;
f9ed8854
MC		 934 }
935
1f4702aa
AD		 936 ixgbe_down(adapter);
937
938 /*
939 * Setup new Tx resources and free the old Tx resources in that order.
940 * We can then assign the new resources to the rings via a memcpy.
941 * The advantage to this approach is that we are guaranteed to still
942 * have resources even in the case of an allocation failure.
943 */
f9ed8854 944 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 945 for (i = 0; i < adapter->num_tx_queues; i++) {
1f4702aa 946 memcpy(&temp_ring[i], adapter->tx_ring[i],
4a0b9ca0 947 sizeof(struct ixgbe_ring));
1f4702aa
AD		 948
949 temp_ring[i].count = new_tx_count;
950 err = ixgbe_setup_tx_resources(&temp_ring[i]);
9a799d71 951 if (err) {
c431f97e
JB		 952 while (i) {
953 i--;
1f4702aa 954 ixgbe_free_tx_resources(&temp_ring[i]);
c431f97e 955 }
1f4702aa 956 goto err_setup;
9a799d71 957 }
9a799d71 958 }
9a799d71 959
1f4702aa
AD		 960 for (i = 0; i < adapter->num_tx_queues; i++) {
961 ixgbe_free_tx_resources(adapter->tx_ring[i]);
962
963 memcpy(adapter->tx_ring[i], &temp_ring[i],
964 sizeof(struct ixgbe_ring));
965 }
966
967 adapter->tx_ring_count = new_tx_count;
d3fa4721 968 }
9a799d71 969
1f4702aa 970 /* Repeat the process for the Rx rings if needed */
f9ed8854 971 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 972 for (i = 0; i < adapter->num_rx_queues; i++) {
1f4702aa 973 memcpy(&temp_ring[i], adapter->rx_ring[i],
4a0b9ca0 974 sizeof(struct ixgbe_ring));
1f4702aa
AD		 975
976 temp_ring[i].count = new_rx_count;
977 err = ixgbe_setup_rx_resources(&temp_ring[i]);
9a799d71 978 if (err) {
c431f97e
JB		 979 while (i) {
980 i--;
1f4702aa 981 ixgbe_free_rx_resources(&temp_ring[i]);
c431f97e 982 }
9a799d71
AK		 983 goto err_setup;
984 }
1f4702aa 985
9a799d71 986 }
f9ed8854 987
1f4702aa
AD		 988 for (i = 0; i < adapter->num_rx_queues; i++) {
989 ixgbe_free_rx_resources(adapter->rx_ring[i]);
f9ed8854 990
1f4702aa
AD		 991 memcpy(adapter->rx_ring[i], &temp_ring[i],
992 sizeof(struct ixgbe_ring));
f9ed8854
MC		 993 }
994
1f4702aa 995 adapter->rx_ring_count = new_rx_count;
759884b4 996 }
4a0b9ca0 997
f9ed8854 998err_setup:
1f4702aa
AD		 999 ixgbe_up(adapter);
1000 vfree(temp_ring);
4a0b9ca0 1001clear_reset:
d4f80882 1002 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 1003 return err;
1004}
1005
b9f2c044 1006static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 1007{
b9f2c044 1008 switch (sset) {
da4dd0f7
PWJ		 1009 case ETH_SS_TEST:
1010 return IXGBE_TEST_LEN;
b9f2c044
JG		 1011 case ETH_SS_STATS:
1012 return IXGBE_STATS_LEN;
1013 default:
1014 return -EOPNOTSUPP;
1015 }
9a799d71
AK		 1016}
1017
1018static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 1019 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 1020{
1021 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1022 struct rtnl_link_stats64 temp;
1023 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1024 unsigned int start;
1025 struct ixgbe_ring *ring;
1026 int i, j;
29c3a050 1027 char *p = NULL;
9a799d71
AK		 1028
1029 ixgbe_update_stats(adapter);
28172739 1030 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1031 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1032 switch (ixgbe_gstrings_stats[i].type) {
1033 case NETDEV_STATS:
28172739 1034 p = (char *) net_stats +
29c3a050
AK		 1035 ixgbe_gstrings_stats[i].stat_offset;
1036 break;
1037 case IXGBE_STATS:
1038 p = (char *) adapter +
1039 ixgbe_gstrings_stats[i].stat_offset;
1040 break;
f752be9c
JH		 1041 default:
1042 data[i] = 0;
1043 continue;
29c3a050
AK		 1044 }
1045
9a799d71 1046 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1047 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71 1048 }
bd8a1b12 1049 for (j = 0; j < netdev->num_tx_queues; j++) {
de1036b1 1050 ring = adapter->tx_ring[j];
9cc00b51
JF		 1051 if (!ring) {
1052 data[i] = 0;
1053 data[i+1] = 0;
1054 i += 2;
7e15b90f
ET		 1055#ifdef LL_EXTENDED_STATS
1056 data[i] = 0;
1057 data[i+1] = 0;
1058 data[i+2] = 0;
1059 i += 3;
1060#endif
9cc00b51
JF		 1061 continue;
1062 }
1063
de1036b1
ED		 1064 do {
1065 start = u64_stats_fetch_begin_bh(&ring->syncp);
1066 data[i] = ring->stats.packets;
1067 data[i+1] = ring->stats.bytes;
1068 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1069 i += 2;
7e15b90f
ET		 1070#ifdef LL_EXTENDED_STATS
1071 data[i] = ring->stats.yields;
1072 data[i+1] = ring->stats.misses;
1073 data[i+2] = ring->stats.cleaned;
1074 i += 3;
1075#endif
9a799d71 1076 }
9cc00b51 1077 for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
de1036b1 1078 ring = adapter->rx_ring[j];
9cc00b51
JF		 1079 if (!ring) {
1080 data[i] = 0;
1081 data[i+1] = 0;
1082 i += 2;
7e15b90f
ET		 1083#ifdef LL_EXTENDED_STATS
1084 data[i] = 0;
1085 data[i+1] = 0;
1086 data[i+2] = 0;
1087 i += 3;
1088#endif
9cc00b51
JF		 1089 continue;
1090 }
1091
de1036b1
ED		 1092 do {
1093 start = u64_stats_fetch_begin_bh(&ring->syncp);
1094 data[i] = ring->stats.packets;
1095 data[i+1] = ring->stats.bytes;
1096 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1097 i += 2;
7e15b90f
ET		 1098#ifdef LL_EXTENDED_STATS
1099 data[i] = ring->stats.yields;
1100 data[i+1] = ring->stats.misses;
1101 data[i+2] = ring->stats.cleaned;
1102 i += 3;
1103#endif
9a799d71 1104 }
9cc00b51
JF		 1105
1106 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1107 data[i++] = adapter->stats.pxontxc[j];
1108 data[i++] = adapter->stats.pxofftxc[j];
1109 }
1110 for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1111 data[i++] = adapter->stats.pxonrxc[j];
1112 data[i++] = adapter->stats.pxoffrxc[j];
2f90b865 1113 }
9a799d71
AK		 1114}
1115
1116static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1117 u8 *data)
9a799d71 1118{
c44ade9e 1119 char *p = (char *)data;
9a799d71
AK		 1120 int i;
1121
1122 switch (stringset) {
da4dd0f7 1123 case ETH_SS_TEST:
d2c47b62
JH		 1124 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1125 memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1126 data += ETH_GSTRING_LEN;
1127 }
da4dd0f7 1128 break;
9a799d71
AK		 1129 case ETH_SS_STATS:
1130 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1131 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1132 ETH_GSTRING_LEN);
1133 p += ETH_GSTRING_LEN;
1134 }
9cc00b51 1135 for (i = 0; i < netdev->num_tx_queues; i++) {
9a799d71
AK		 1136 sprintf(p, "tx_queue_%u_packets", i);
1137 p += ETH_GSTRING_LEN;
1138 sprintf(p, "tx_queue_%u_bytes", i);
1139 p += ETH_GSTRING_LEN;
7e15b90f 1140#ifdef LL_EXTENDED_STATS
9c432ada 1141 sprintf(p, "tx_queue_%u_ll_napi_yield", i);
7e15b90f 1142 p += ETH_GSTRING_LEN;
9c432ada 1143 sprintf(p, "tx_queue_%u_ll_misses", i);
7e15b90f 1144 p += ETH_GSTRING_LEN;
9c432ada 1145 sprintf(p, "tx_queue_%u_ll_cleaned", i);
7e15b90f
ET		 1146 p += ETH_GSTRING_LEN;
1147#endif /* LL_EXTENDED_STATS */
9a799d71 1148 }
9cc00b51 1149 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
9a799d71
AK		 1150 sprintf(p, "rx_queue_%u_packets", i);
1151 p += ETH_GSTRING_LEN;
1152 sprintf(p, "rx_queue_%u_bytes", i);
1153 p += ETH_GSTRING_LEN;
7e15b90f 1154#ifdef LL_EXTENDED_STATS
9c432ada 1155 sprintf(p, "rx_queue_%u_ll_poll_yield", i);
7e15b90f 1156 p += ETH_GSTRING_LEN;
9c432ada 1157 sprintf(p, "rx_queue_%u_ll_misses", i);
7e15b90f 1158 p += ETH_GSTRING_LEN;
9c432ada 1159 sprintf(p, "rx_queue_%u_ll_cleaned", i);
7e15b90f
ET		 1160 p += ETH_GSTRING_LEN;
1161#endif /* LL_EXTENDED_STATS */
9a799d71 1162 }
9cc00b51
JF		 1163 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1164 sprintf(p, "tx_pb_%u_pxon", i);
1165 p += ETH_GSTRING_LEN;
1166 sprintf(p, "tx_pb_%u_pxoff", i);
1167 p += ETH_GSTRING_LEN;
1168 }
1169 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1170 sprintf(p, "rx_pb_%u_pxon", i);
1171 p += ETH_GSTRING_LEN;
1172 sprintf(p, "rx_pb_%u_pxoff", i);
1173 p += ETH_GSTRING_LEN;
2f90b865 1174 }
b4617240 1175 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1176 break;
1177 }
1178}
1179
da4dd0f7
PWJ		 1180static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1181{
1182 struct ixgbe_hw *hw = &adapter->hw;
1183 bool link_up;
1184 u32 link_speed = 0;
1185 *data = 0;
1186
1187 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1188 if (link_up)
1189 return *data;
1190 else
1191 *data = 1;
1192 return *data;
1193}
1194
1195/* ethtool register test data */
1196struct ixgbe_reg_test {
1197 u16 reg;
1198 u8 array_len;
1199 u8 test_type;
1200 u32 mask;
1201 u32 write;
1202};
1203
1204/* In the hardware, registers are laid out either singly, in arrays
1205 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1206 * most tests take place on arrays or single registers (handled
1207 * as a single-element array) and special-case the tables.
1208 * Table tests are always pattern tests.
1209 *
1210 * We also make provision for some required setup steps by specifying
1211 * registers to be written without any read-back testing.
1212 */
1213
1214#define PATTERN_TEST 1
1215#define SET_READ_TEST 2
1216#define WRITE_NO_TEST 3
1217#define TABLE32_TEST 4
1218#define TABLE64_TEST_LO 5
1219#define TABLE64_TEST_HI 6
1220
1221/* default 82599 register test */
66744500 1222static const struct ixgbe_reg_test reg_test_82599[] = {
da4dd0f7
PWJ		 1223 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1224 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1225 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1226 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1227 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1228 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1229 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1230 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1231 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1232 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1233 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1234 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1235 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1236 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1237 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1238 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1239 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1240 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1241 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1242 { 0, 0, 0, 0 }
1243};
1244
1245/* default 82598 register test */
66744500 1246static const struct ixgbe_reg_test reg_test_82598[] = {
da4dd0f7
PWJ		 1247 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1248 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1249 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1250 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1251 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1252 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1253 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1254 /* Enable all four RX queues before testing. */
1255 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1256 /* RDH is read-only for 82598, only test RDT. */
1257 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1258 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1259 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1260 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1261 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1262 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1263 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1264 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1265 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1266 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1267 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1268 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1269 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1270 { 0, 0, 0, 0 }
1271};
1272
95a46011
ET		 1273static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1274 u32 mask, u32 write)
1275{
1276 u32 pat, val, before;
1277 static const u32 test_pattern[] = {
1278 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1279
1280 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1281 before = readl(adapter->hw.hw_addr + reg);
1282 writel((test_pattern[pat] & write),
1283 (adapter->hw.hw_addr + reg));
1284 val = readl(adapter->hw.hw_addr + reg);
1285 if (val != (test_pattern[pat] & write & mask)) {
1286 e_err(drv, "pattern test reg %04X failed: got "
1287 "0x%08X expected 0x%08X\n",
1288 reg, val, (test_pattern[pat] & write & mask));
1289 *data = reg;
1290 writel(before, adapter->hw.hw_addr + reg);
1291 return 1;
1292 }
1293 writel(before, adapter->hw.hw_addr + reg);
1294 }
1295 return 0;
da4dd0f7
PWJ		 1296}
1297
95a46011
ET		 1298static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1299 u32 mask, u32 write)
1300{
1301 u32 val, before;
1302 before = readl(adapter->hw.hw_addr + reg);
1303 writel((write & mask), (adapter->hw.hw_addr + reg));
1304 val = readl(adapter->hw.hw_addr + reg);
1305 if ((write & mask) != (val & mask)) {
1306 e_err(drv, "set/check reg %04X test failed: got 0x%08X "
1307 "expected 0x%08X\n", reg, (val & mask), (write & mask));
1308 *data = reg;
1309 writel(before, (adapter->hw.hw_addr + reg));
1310 return 1;
1311 }
1312 writel(before, (adapter->hw.hw_addr + reg));
1313 return 0;
da4dd0f7
PWJ		 1314}
1315
95a46011
ET		 1316#define REG_PATTERN_TEST(reg, mask, write) \
1317 do { \
1318 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1319 return 1; \
1320 } while (0) \
1321
1322
1323#define REG_SET_AND_CHECK(reg, mask, write) \
1324 do { \
1325 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1326 return 1; \
1327 } while (0) \
1328
da4dd0f7
PWJ		 1329static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1330{
66744500 1331 const struct ixgbe_reg_test *test;
da4dd0f7
PWJ		 1332 u32 value, before, after;
1333 u32 i, toggle;
1334
bd508178
AD		 1335 switch (adapter->hw.mac.type) {
1336 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1337 toggle = 0x7FFFF3FF;
1338 test = reg_test_82598;
bd508178
AD		 1339 break;
1340 case ixgbe_mac_82599EB:
b93a2226 1341 case ixgbe_mac_X540:
bd508178
AD		 1342 toggle = 0x7FFFF30F;
1343 test = reg_test_82599;
1344 break;
1345 default:
1346 *data = 1;
1347 return 1;
1348 break;
da4dd0f7
PWJ		 1349 }
1350
1351 /*
1352 * Because the status register is such a special case,
1353 * we handle it separately from the rest of the register
1354 * tests. Some bits are read-only, some toggle, and some
1355 * are writeable on newer MACs.
1356 */
1357 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1358 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1360 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1361 if (value != after) {
396e799c
ET		 1362 e_err(drv, "failed STATUS register test got: 0x%08X "
1363 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1364 *data = 1;
1365 return 1;
1366 }
1367 /* restore previous status */
1368 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1369
1370 /*
1371 * Perform the remainder of the register test, looping through
1372 * the test table until we either fail or reach the null entry.
1373 */
1374 while (test->reg) {
1375 for (i = 0; i < test->array_len; i++) {
1376 switch (test->test_type) {
1377 case PATTERN_TEST:
1378 REG_PATTERN_TEST(test->reg + (i * 0x40),
95a46011
ET		 1379 test->mask,
1380 test->write);
da4dd0f7
PWJ		 1381 break;
1382 case SET_READ_TEST:
1383 REG_SET_AND_CHECK(test->reg + (i * 0x40),
95a46011
ET		 1384 test->mask,
1385 test->write);
da4dd0f7
PWJ		 1386 break;
1387 case WRITE_NO_TEST:
1388 writel(test->write,
1389 (adapter->hw.hw_addr + test->reg)
1390 + (i * 0x40));
1391 break;
1392 case TABLE32_TEST:
1393 REG_PATTERN_TEST(test->reg + (i * 4),
95a46011
ET		 1394 test->mask,
1395 test->write);
da4dd0f7
PWJ		 1396 break;
1397 case TABLE64_TEST_LO:
1398 REG_PATTERN_TEST(test->reg + (i * 8),
95a46011
ET		 1399 test->mask,
1400 test->write);
da4dd0f7
PWJ		 1401 break;
1402 case TABLE64_TEST_HI:
1403 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
95a46011
ET		 1404 test->mask,
1405 test->write);
da4dd0f7
PWJ		 1406 break;
1407 }
1408 }
1409 test++;
1410 }
1411
1412 *data = 0;
1413 return 0;
1414}
1415
1416static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1417{
1418 struct ixgbe_hw *hw = &adapter->hw;
1419 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1420 *data = 1;
1421 else
1422 *data = 0;
1423 return *data;
1424}
1425
1426static irqreturn_t ixgbe_test_intr(int irq, void *data)
1427{
1428 struct net_device *netdev = (struct net_device *) data;
1429 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1430
1431 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1432
1433 return IRQ_HANDLED;
1434}
1435
1436static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1437{
1438 struct net_device *netdev = adapter->netdev;
1439 u32 mask, i = 0, shared_int = true;
1440 u32 irq = adapter->pdev->irq;
1441
1442 *data = 0;
1443
1444 /* Hook up test interrupt handler just for this test */
1445 if (adapter->msix_entries) {
1446 /* NOTE: we don't test MSI-X interrupts here, yet */
1447 return 0;
1448 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1449 shared_int = false;
a0607fd3 1450 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1451 netdev)) {
1452 *data = 1;
1453 return -1;
1454 }
a0607fd3 1455 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1456 netdev->name, netdev)) {
1457 shared_int = false;
a0607fd3 1458 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1459 netdev->name, netdev)) {
1460 *data = 1;
1461 return -1;
1462 }
396e799c
ET		 1463 e_info(hw, "testing %s interrupt\n", shared_int ?
1464 "shared" : "unshared");
da4dd0f7
PWJ		 1465
1466 /* Disable all the interrupts */
1467 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1468 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1469 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1470
1471 /* Test each interrupt */
1472 for (; i < 10; i++) {
1473 /* Interrupt to test */
1474 mask = 1 << i;
1475
1476 if (!shared_int) {
1477 /*
1478 * Disable the interrupts to be reported in
1479 * the cause register and then force the same
1480 * interrupt and see if one gets posted. If
1481 * an interrupt was posted to the bus, the
1482 * test failed.
1483 */
1484 adapter->test_icr = 0;
1485 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1486 ~mask & 0x00007FFF);
1487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1488 ~mask & 0x00007FFF);
945a5151 1489 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1490 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1491
1492 if (adapter->test_icr & mask) {
1493 *data = 3;
1494 break;
1495 }
1496 }
1497
1498 /*
1499 * Enable the interrupt to be reported in the cause
1500 * register and then force the same interrupt and see
1501 * if one gets posted. If an interrupt was not posted
1502 * to the bus, the test failed.
1503 */
1504 adapter->test_icr = 0;
1505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
945a5151 1507 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1508 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1509
1510 if (!(adapter->test_icr &mask)) {
1511 *data = 4;
1512 break;
1513 }
1514
1515 if (!shared_int) {
1516 /*
1517 * Disable the other interrupts to be reported in
1518 * the cause register and then force the other
1519 * interrupts and see if any get posted. If
1520 * an interrupt was posted to the bus, the
1521 * test failed.
1522 */
1523 adapter->test_icr = 0;
1524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1525 ~mask & 0x00007FFF);
1526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1527 ~mask & 0x00007FFF);
945a5151 1528 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1529 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1530
1531 if (adapter->test_icr) {
1532 *data = 5;
1533 break;
1534 }
1535 }
1536 }
1537
1538 /* Disable all the interrupts */
1539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
945a5151 1540 IXGBE_WRITE_FLUSH(&adapter->hw);
032b4325 1541 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1542
1543 /* Unhook test interrupt handler */
1544 free_irq(irq, netdev);
1545
1546 return *data;
1547}
1548
1549static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1550{
1551 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1552 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1553 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1554 u32 reg_ctl;
da4dd0f7
PWJ		 1555
1556 /* shut down the DMA engines now so they can be reinitialized later */
1557
1558 /* first Rx */
1559 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1560 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1561 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
2d39d576 1562 ixgbe_disable_rx_queue(adapter, rx_ring);
da4dd0f7
PWJ		 1563
1564 /* now Tx */
84418e3b 1565 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1566 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1567 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1568
bd508178
AD		 1569 switch (hw->mac.type) {
1570 case ixgbe_mac_82599EB:
b93a2226 1571 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1572 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1573 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1574 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1575 break;
1576 default:
1577 break;
da4dd0f7
PWJ		 1578 }
1579
1580 ixgbe_reset(adapter);
1581
b6ec895e
AD		 1582 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1583 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1584}
1585
1586static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1587{
1588 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1589 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1590 u32 rctl, reg_data;
84418e3b
AD		 1591 int ret_val;
1592 int err;
da4dd0f7
PWJ		 1593
1594 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1595 tx_ring->count = IXGBE_DEFAULT_TXD;
1596 tx_ring->queue_index = 0;
b6ec895e 1597 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1598 tx_ring->netdev = adapter->netdev;
84418e3b 1599 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
da4dd0f7 1600
b6ec895e 1601 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1602 if (err)
1603 return 1;
da4dd0f7 1604
bd508178
AD		 1605 switch (adapter->hw.mac.type) {
1606 case ixgbe_mac_82599EB:
b93a2226 1607 case ixgbe_mac_X540:
da4dd0f7
PWJ		 1608 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1609 reg_data |= IXGBE_DMATXCTL_TE;
1610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1611 break;
1612 default:
1613 break;
da4dd0f7 1614 }
f4ec443b 1615
84418e3b 1616 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1617
1618 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1619 rx_ring->count = IXGBE_DEFAULT_RXD;
1620 rx_ring->queue_index = 0;
b6ec895e 1621 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1622 rx_ring->netdev = adapter->netdev;
84418e3b 1623 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
84418e3b 1624
b6ec895e 1625 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1626 if (err) {
da4dd0f7
PWJ		 1627 ret_val = 4;
1628 goto err_nomem;
1629 }
1630
da4dd0f7
PWJ		 1631 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1633
84418e3b 1634 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1635
1636 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1638
da4dd0f7
PWJ		 1639 return 0;
1640
1641err_nomem:
1642 ixgbe_free_desc_rings(adapter);
1643 return ret_val;
1644}
1645
1646static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1647{
1648 struct ixgbe_hw *hw = &adapter->hw;
1649 u32 reg_data;
1650
e7fd9253 1651
84418e3b 1652 /* Setup MAC loopback */
26b4742b 1653 reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
da4dd0f7 1654 reg_data |= IXGBE_HLREG0_LPBK;
35c7f8a1 1655 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
da4dd0f7 1656
35c7f8a1 1657 reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
84418e3b 1658 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
35c7f8a1 1659 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
84418e3b 1660
26b4742b
ET		 1661 /* X540 needs to set the MACC.FLU bit to force link up */
1662 if (adapter->hw.mac.type == ixgbe_mac_X540) {
1663 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1664 reg_data |= IXGBE_MACC_FLU;
1665 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1666 } else {
1667 if (hw->mac.orig_autoc) {
1668 reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1669 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1670 } else {
1671 return 10;
1672 }
1673 }
35c7f8a1 1674 IXGBE_WRITE_FLUSH(hw);
032b4325 1675 usleep_range(10000, 20000);
da4dd0f7
PWJ		 1676
1677 /* Disable Atlas Tx lanes; re-enabled in reset path */
1678 if (hw->mac.type == ixgbe_mac_82598EB) {
1679 u8 atlas;
1680
1681 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1682 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1683 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1684
1685 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1686 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1687 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1688
1689 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1690 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1691 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1692
1693 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1694 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1695 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1696 }
1697
1698 return 0;
1699}
1700
1701static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1702{
1703 u32 reg_data;
1704
1705 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1706 reg_data &= ~IXGBE_HLREG0_LPBK;
1707 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1708}
1709
1710static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
3832b26e 1711 unsigned int frame_size)
da4dd0f7
PWJ		 1712{
1713 memset(skb->data, 0xFF, frame_size);
3832b26e
AD		 1714 frame_size >>= 1;
1715 memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1716 memset(&skb->data[frame_size + 10], 0xBE, 1);
1717 memset(&skb->data[frame_size + 12], 0xAF, 1);
da4dd0f7
PWJ		 1718}
1719
3832b26e
AD		 1720static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1721 unsigned int frame_size)
da4dd0f7 1722{
3832b26e
AD		 1723 unsigned char *data;
1724 bool match = true;
1725
1726 frame_size >>= 1;
1727
f800326d 1728 data = kmap(rx_buffer->page) + rx_buffer->page_offset;
3832b26e
AD		 1729
1730 if (data[3] != 0xFF ||
1731 data[frame_size + 10] != 0xBE ||
1732 data[frame_size + 12] != 0xAF)
1733 match = false;
1734
f800326d
AD		 1735 kunmap(rx_buffer->page);
1736
3832b26e 1737 return match;
da4dd0f7
PWJ		 1738}
1739
fc77dc3c 1740static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
3832b26e
AD		 1741 struct ixgbe_ring *tx_ring,
1742 unsigned int size)
84418e3b
AD		 1743{
1744 union ixgbe_adv_rx_desc *rx_desc;
3832b26e
AD		 1745 struct ixgbe_rx_buffer *rx_buffer;
1746 struct ixgbe_tx_buffer *tx_buffer;
84418e3b
AD		 1747 u16 rx_ntc, tx_ntc, count = 0;
1748
1749 /* initialize next to clean and descriptor values */
1750 rx_ntc = rx_ring->next_to_clean;
1751 tx_ntc = tx_ring->next_to_clean;
e4f74028 1752 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b 1753
3832b26e 1754 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
84418e3b 1755 /* check Rx buffer */
3832b26e 1756 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
84418e3b 1757
f800326d
AD		 1758 /* sync Rx buffer for CPU read */
1759 dma_sync_single_for_cpu(rx_ring->dev,
1760 rx_buffer->dma,
1761 ixgbe_rx_bufsz(rx_ring),
1762 DMA_FROM_DEVICE);
84418e3b
AD		 1763
1764 /* verify contents of skb */
3832b26e 1765 if (ixgbe_check_lbtest_frame(rx_buffer, size))
84418e3b
AD		 1766 count++;
1767
f800326d
AD		 1768 /* sync Rx buffer for device write */
1769 dma_sync_single_for_device(rx_ring->dev,
1770 rx_buffer->dma,
1771 ixgbe_rx_bufsz(rx_ring),
1772 DMA_FROM_DEVICE);
1773
84418e3b 1774 /* unmap buffer on Tx side */
3832b26e
AD		 1775 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1776 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
84418e3b
AD		 1777
1778 /* increment Rx/Tx next to clean counters */
1779 rx_ntc++;
1780 if (rx_ntc == rx_ring->count)
1781 rx_ntc = 0;
1782 tx_ntc++;
1783 if (tx_ntc == tx_ring->count)
1784 tx_ntc = 0;
1785
1786 /* fetch next descriptor */
e4f74028 1787 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
84418e3b
AD		 1788 }
1789
dad8a3b3
JF		 1790 netdev_tx_reset_queue(txring_txq(tx_ring));
1791
84418e3b 1792 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1793 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1794 rx_ring->next_to_clean = rx_ntc;
1795 tx_ring->next_to_clean = tx_ntc;
1796
1797 return count;
1798}
1799
da4dd0f7
PWJ		 1800static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1801{
1802 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1803 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1804 int i, j, lc, good_cnt, ret_val = 0;
1805 unsigned int size = 1024;
1806 netdev_tx_t tx_ret_val;
1807 struct sk_buff *skb;
91ffdc84
ET		 1808 u32 flags_orig = adapter->flags;
1809
1810 /* DCB can modify the frames on Tx */
1811 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
84418e3b
AD		 1812
1813 /* allocate test skb */
1814 skb = alloc_skb(size, GFP_KERNEL);
1815 if (!skb)
1816 return 11;
da4dd0f7 1817
84418e3b
AD		 1818 /* place data into test skb */
1819 ixgbe_create_lbtest_frame(skb, size);
1820 skb_put(skb, size);
da4dd0f7
PWJ		 1821
1822 /*
1823 * Calculate the loop count based on the largest descriptor ring
1824 * The idea is to wrap the largest ring a number of times using 64
1825 * send/receive pairs during each loop
1826 */
1827
1828 if (rx_ring->count <= tx_ring->count)
1829 lc = ((tx_ring->count / 64) * 2) + 1;
1830 else
1831 lc = ((rx_ring->count / 64) * 2) + 1;
1832
da4dd0f7 1833 for (j = 0; j <= lc; j++) {
84418e3b 1834 /* reset count of good packets */
da4dd0f7 1835 good_cnt = 0;
84418e3b
AD		 1836
1837 /* place 64 packets on the transmit queue*/
1838 for (i = 0; i < 64; i++) {
1839 skb_get(skb);
1840 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1841 adapter,
1842 tx_ring);
1843 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1844 good_cnt++;
84418e3b
AD		 1845 }
1846
da4dd0f7 1847 if (good_cnt != 64) {
84418e3b 1848 ret_val = 12;
da4dd0f7
PWJ		 1849 break;
1850 }
84418e3b
AD		 1851
1852 /* allow 200 milliseconds for packets to go from Tx to Rx */
1853 msleep(200);
1854
fc77dc3c 1855 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1856 if (good_cnt != 64) {
1857 ret_val = 13;
da4dd0f7
PWJ		 1858 break;
1859 }
1860 }
1861
84418e3b
AD		 1862 /* free the original skb */
1863 kfree_skb(skb);
91ffdc84 1864 adapter->flags = flags_orig;
84418e3b 1865
da4dd0f7
PWJ		 1866 return ret_val;
1867}
1868
1869static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1870{
1871 *data = ixgbe_setup_desc_rings(adapter);
1872 if (*data)
1873 goto out;
1874 *data = ixgbe_setup_loopback_test(adapter);
1875 if (*data)
1876 goto err_loopback;
1877 *data = ixgbe_run_loopback_test(adapter);
1878 ixgbe_loopback_cleanup(adapter);
1879
1880err_loopback:
1881 ixgbe_free_desc_rings(adapter);
1882out:
1883 return *data;
1884}
1885
1886static void ixgbe_diag_test(struct net_device *netdev,
1887 struct ethtool_test *eth_test, u64 *data)
1888{
1889 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1890 bool if_running = netif_running(netdev);
1891
1892 set_bit(__IXGBE_TESTING, &adapter->state);
1893 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
4ec375b1
ET		 1894 struct ixgbe_hw *hw = &adapter->hw;
1895
e7d481a6
GR		 1896 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1897 int i;
1898 for (i = 0; i < adapter->num_vfs; i++) {
1899 if (adapter->vfinfo[i].clear_to_send) {
1900 netdev_warn(netdev, "%s",
1901 "offline diagnostic is not "
1902 "supported when VFs are "
1903 "present\n");
1904 data[0] = 1;
1905 data[1] = 1;
1906 data[2] = 1;
1907 data[3] = 1;
1908 eth_test->flags |= ETH_TEST_FL_FAILED;
1909 clear_bit(__IXGBE_TESTING,
1910 &adapter->state);
1911 goto skip_ol_tests;
1912 }
1913 }
1914 }
1915
dfcc4615
JK		 1916 /* Offline tests */
1917 e_info(hw, "offline testing starting\n");
1918
dfcc4615
JK		 1919 /* Link test performed before hardware reset so autoneg doesn't
1920 * interfere with test result
1921 */
1922 if (ixgbe_link_test(adapter, &data[4]))
1923 eth_test->flags |= ETH_TEST_FL_FAILED;
1924
4ec375b1
ET		 1925 if (if_running)
1926 /* indicate we're in test mode */
1927 dev_close(netdev);
1928 else
1929 ixgbe_reset(adapter);
1930
396e799c 1931 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1932 if (ixgbe_reg_test(adapter, &data[0]))
1933 eth_test->flags |= ETH_TEST_FL_FAILED;
1934
1935 ixgbe_reset(adapter);
396e799c 1936 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1937 if (ixgbe_eeprom_test(adapter, &data[1]))
1938 eth_test->flags |= ETH_TEST_FL_FAILED;
1939
1940 ixgbe_reset(adapter);
396e799c 1941 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1942 if (ixgbe_intr_test(adapter, &data[2]))
1943 eth_test->flags |= ETH_TEST_FL_FAILED;
1944
bdbec4b8
GR		 1945 /* If SRIOV or VMDq is enabled then skip MAC
1946 * loopback diagnostic. */
1947 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1948 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1949 e_info(hw, "Skip MAC loopback diagnostic in VT "
1950 "mode\n");
bdbec4b8
GR		 1951 data[3] = 0;
1952 goto skip_loopback;
1953 }
1954
da4dd0f7 1955 ixgbe_reset(adapter);
396e799c 1956 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1957 if (ixgbe_loopback_test(adapter, &data[3]))
1958 eth_test->flags |= ETH_TEST_FL_FAILED;
1959
bdbec4b8 1960skip_loopback:
da4dd0f7
PWJ		 1961 ixgbe_reset(adapter);
1962
dfcc4615 1963 /* clear testing bit and return adapter to previous state */
da4dd0f7
PWJ		 1964 clear_bit(__IXGBE_TESTING, &adapter->state);
1965 if (if_running)
1966 dev_open(netdev);
4ec375b1
ET		 1967 else if (hw->mac.ops.disable_tx_laser)
1968 hw->mac.ops.disable_tx_laser(hw);
da4dd0f7 1969 } else {
396e799c 1970 e_info(hw, "online testing starting\n");
dfcc4615 1971
da4dd0f7
PWJ		 1972 /* Online tests */
1973 if (ixgbe_link_test(adapter, &data[4]))
1974 eth_test->flags |= ETH_TEST_FL_FAILED;
1975
dfcc4615 1976 /* Offline tests aren't run; pass by default */
da4dd0f7
PWJ		 1977 data[0] = 0;
1978 data[1] = 0;
1979 data[2] = 0;
1980 data[3] = 0;
1981
1982 clear_bit(__IXGBE_TESTING, &adapter->state);
1983 }
dfcc4615 1984
e7d481a6 1985skip_ol_tests:
da4dd0f7
PWJ		 1986 msleep_interruptible(4 * 1000);
1987}
9a799d71 1988
d6c519e1
AD		 1989static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1990 struct ethtool_wolinfo *wol)
1991{
1992 struct ixgbe_hw *hw = &adapter->hw;
8e2813f5 1993 int retval = 0;
c23f5b6b 1994
8e2813f5
JK		 1995 /* WOL not supported for all devices */
1996 if (!ixgbe_wol_supported(adapter, hw->device_id,
1997 hw->subsystem_device_id)) {
1998 retval = 1;
d6c519e1 1999 wol->supported = 0;
d6c519e1
AD		 2000 }
2001
2002 return retval;
2003}
2004
9a799d71 2005static void ixgbe_get_wol(struct net_device *netdev,
b4617240 2006 struct ethtool_wolinfo *wol)
9a799d71 2007{
e63d9762
PW		 2008 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2009
2010 wol->supported = WAKE_UCAST | WAKE_MCAST |
2011 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 2012 wol->wolopts = 0;
2013
d6c519e1
AD		 2014 if (ixgbe_wol_exclusion(adapter, wol) ||
2015 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 2016 return;
2017
2018 if (adapter->wol & IXGBE_WUFC_EX)
2019 wol->wolopts |= WAKE_UCAST;
2020 if (adapter->wol & IXGBE_WUFC_MC)
2021 wol->wolopts |= WAKE_MCAST;
2022 if (adapter->wol & IXGBE_WUFC_BC)
2023 wol->wolopts |= WAKE_BCAST;
2024 if (adapter->wol & IXGBE_WUFC_MAG)
2025 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 2026}
2027
e63d9762
PW		 2028static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2029{
2030 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2031
2032 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2033 return -EOPNOTSUPP;
2034
d6c519e1
AD		 2035 if (ixgbe_wol_exclusion(adapter, wol))
2036 return wol->wolopts ? -EOPNOTSUPP : 0;
2037
e63d9762
PW		 2038 adapter->wol = 0;
2039
2040 if (wol->wolopts & WAKE_UCAST)
2041 adapter->wol |= IXGBE_WUFC_EX;
2042 if (wol->wolopts & WAKE_MCAST)
2043 adapter->wol |= IXGBE_WUFC_MC;
2044 if (wol->wolopts & WAKE_BCAST)
2045 adapter->wol |= IXGBE_WUFC_BC;
2046 if (wol->wolopts & WAKE_MAGIC)
2047 adapter->wol |= IXGBE_WUFC_MAG;
2048
2049 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2050
2051 return 0;
2052}
2053
9a799d71
AK		 2054static int ixgbe_nway_reset(struct net_device *netdev)
2055{
2056 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2057
d4f80882
AV		 2058 if (netif_running(netdev))
2059 ixgbe_reinit_locked(adapter);
9a799d71
AK		 2060
2061 return 0;
2062}
2063
66e6961c
ET		 2064static int ixgbe_set_phys_id(struct net_device *netdev,
2065 enum ethtool_phys_id_state state)
9a799d71
AK		 2066{
2067 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 2068 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 2069
66e6961c
ET		 2070 switch (state) {
2071 case ETHTOOL_ID_ACTIVE:
2072 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2073 return 2;
9a799d71 2074
66e6961c 2075 case ETHTOOL_ID_ON:
c44ade9e 2076 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
66e6961c
ET		 2077 break;
2078
2079 case ETHTOOL_ID_OFF:
c44ade9e 2080 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
66e6961c 2081 break;
9a799d71 2082
66e6961c
ET		 2083 case ETHTOOL_ID_INACTIVE:
2084 /* Restore LED settings */
2085 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2086 break;
2087 }
9a799d71
AK		 2088
2089 return 0;
2090}
2091
2092static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 2093 struct ethtool_coalesce *ec)
9a799d71
AK		 2094{
2095 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2096
30efa5a3 2097 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2098 if (adapter->rx_itr_setting <= 1)
2099 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2100 else
2101 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
f7554a2b 2102
cfb3f91a 2103 /* if in mixed tx/rx queues per vector mode, report only rx settings */
08c8833b 2104 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
cfb3f91a
SN		 2105 return 0;
2106
f7554a2b 2107 /* only valid if in constant ITR mode */
d5bf4f67
ET		 2108 if (adapter->tx_itr_setting <= 1)
2109 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2110 else
2111 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
f7554a2b 2112
9a799d71
AK		 2113 return 0;
2114}
2115
80fba3f4
AD		 2116/*
2117 * this function must be called before setting the new value of
2118 * rx_itr_setting
2119 */
567d2de2 2120static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
80fba3f4
AD		 2121{
2122 struct net_device *netdev = adapter->netdev;
2123
567d2de2
AD		 2124 /* nothing to do if LRO or RSC are not enabled */
2125 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2126 !(netdev->features & NETIF_F_LRO))
80fba3f4
AD		 2127 return false;
2128
567d2de2
AD		 2129 /* check the feature flag value and enable RSC if necessary */
2130 if (adapter->rx_itr_setting == 1 ||
2131 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2132 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
80fba3f4 2133 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
567d2de2
AD		 2134 e_info(probe, "rx-usecs value high enough "
2135 "to re-enable RSC\n");
80fba3f4
AD		 2136 return true;
2137 }
567d2de2
AD		 2138 /* if interrupt rate is too high then disable RSC */
2139 } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2140 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2141 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2142 return true;
80fba3f4
AD		 2143 }
2144 return false;
2145}
2146
9a799d71 2147static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2148 struct ethtool_coalesce *ec)
9a799d71
AK		 2149{
2150 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2151 struct ixgbe_q_vector *q_vector;
30efa5a3 2152 int i;
67da097e 2153 u16 tx_itr_param, rx_itr_param, tx_itr_prev;
ef021194 2154 bool need_reset = false;
9a799d71 2155
67da097e
ET		 2156 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2157 /* reject Tx specific changes in case of mixed RxTx vectors */
2158 if (ec->tx_coalesce_usecs)
2159 return -EINVAL;
2160 tx_itr_prev = adapter->rx_itr_setting;
2161 } else {
2162 tx_itr_prev = adapter->tx_itr_setting;
2163 }
f7554a2b 2164
d5bf4f67
ET		 2165 if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2166 (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2167 return -EINVAL;
30efa5a3 2168
d5bf4f67
ET		 2169 if (ec->rx_coalesce_usecs > 1)
2170 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2171 else
2172 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
f7554a2b 2173
d5bf4f67
ET		 2174 if (adapter->rx_itr_setting == 1)
2175 rx_itr_param = IXGBE_20K_ITR;
2176 else
2177 rx_itr_param = adapter->rx_itr_setting;
f7554a2b 2178
d5bf4f67
ET		 2179 if (ec->tx_coalesce_usecs > 1)
2180 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2181 else
2182 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
f7554a2b 2183
d5bf4f67
ET		 2184 if (adapter->tx_itr_setting == 1)
2185 tx_itr_param = IXGBE_10K_ITR;
2186 else
2187 tx_itr_param = adapter->tx_itr_setting;
f7554a2b 2188
67da097e
ET		 2189 /* mixed Rx/Tx */
2190 if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2191 adapter->tx_itr_setting = adapter->rx_itr_setting;
2192
2193#if IS_ENABLED(CONFIG_BQL)
2194 /* detect ITR changes that require update of TXDCTL.WTHRESH */
2195 if ((adapter->tx_itr_setting > 1) &&
2196 (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2197 if ((tx_itr_prev == 1) ||
2198 (tx_itr_prev > IXGBE_100K_ITR))
2199 need_reset = true;
2200 } else {
2201 if ((tx_itr_prev > 1) &&
2202 (tx_itr_prev < IXGBE_100K_ITR))
2203 need_reset = true;
2204 }
2205#endif
567d2de2 2206 /* check the old value and enable RSC if necessary */
67da097e 2207 need_reset |= ixgbe_update_rsc(adapter);
567d2de2 2208
49c7ffbe 2209 for (i = 0; i < adapter->num_q_vectors; i++) {
d5bf4f67 2210 q_vector = adapter->q_vector[i];
d5bf4f67
ET		 2211 if (q_vector->tx.count && !q_vector->rx.count)
2212 /* tx only */
2213 q_vector->itr = tx_itr_param;
2214 else
2215 /* rx only or mixed */
2216 q_vector->itr = rx_itr_param;
fe49f04a 2217 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2218 }
2219
ef021194
JB		 2220 /*
2221 * do reset here at the end to make sure EITR==0 case is handled
2222 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2223 * also locks in RSC enable/disable which requires reset
2224 */
c988ee82
ET		 2225 if (need_reset)
2226 ixgbe_do_reset(netdev);
ef021194 2227
9a799d71
AK		 2228 return 0;
2229}
2230
3e05334f
AD		 2231static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2232 struct ethtool_rxnfc *cmd)
2233{
2234 union ixgbe_atr_input *mask = &adapter->fdir_mask;
2235 struct ethtool_rx_flow_spec *fsp =
2236 (struct ethtool_rx_flow_spec *)&cmd->fs;
b67bfe0d 2237 struct hlist_node *node2;
3e05334f
AD		 2238 struct ixgbe_fdir_filter *rule = NULL;
2239
2240 /* report total rule count */
2241 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2242
b67bfe0d 2243 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2244 &adapter->fdir_filter_list, fdir_node) {
2245 if (fsp->location <= rule->sw_idx)
2246 break;
2247 }
2248
2249 if (!rule || fsp->location != rule->sw_idx)
2250 return -EINVAL;
2251
2252 /* fill out the flow spec entry */
2253
2254 /* set flow type field */
2255 switch (rule->filter.formatted.flow_type) {
2256 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2257 fsp->flow_type = TCP_V4_FLOW;
2258 break;
2259 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2260 fsp->flow_type = UDP_V4_FLOW;
2261 break;
2262 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2263 fsp->flow_type = SCTP_V4_FLOW;
2264 break;
2265 case IXGBE_ATR_FLOW_TYPE_IPV4:
2266 fsp->flow_type = IP_USER_FLOW;
2267 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2268 fsp->h_u.usr_ip4_spec.proto = 0;
2269 fsp->m_u.usr_ip4_spec.proto = 0;
2270 break;
2271 default:
2272 return -EINVAL;
2273 }
2274
2275 fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2276 fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2277 fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2278 fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2279 fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2280 fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2281 fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2282 fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2283 fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2284 fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2285 fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2286 fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2287 fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2288 fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2289 fsp->flow_type |= FLOW_EXT;
2290
2291 /* record action */
2292 if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2293 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2294 else
2295 fsp->ring_cookie = rule->action;
2296
2297 return 0;
2298}
2299
2300static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2301 struct ethtool_rxnfc *cmd,
2302 u32 *rule_locs)
2303{
b67bfe0d 2304 struct hlist_node *node2;
3e05334f
AD		 2305 struct ixgbe_fdir_filter *rule;
2306 int cnt = 0;
2307
2308 /* report total rule count */
2309 cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2310
b67bfe0d 2311 hlist_for_each_entry_safe(rule, node2,
3e05334f
AD		 2312 &adapter->fdir_filter_list, fdir_node) {
2313 if (cnt == cmd->rule_cnt)
2314 return -EMSGSIZE;
2315 rule_locs[cnt] = rule->sw_idx;
2316 cnt++;
2317 }
2318
473e64ee
BH		 2319 cmd->rule_cnt = cnt;
2320
3e05334f
AD		 2321 return 0;
2322}
2323
ef6afc0c
AD		 2324static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2325 struct ethtool_rxnfc *cmd)
2326{
2327 cmd->data = 0;
2328
ef6afc0c
AD		 2329 /* Report default options for RSS on ixgbe */
2330 switch (cmd->flow_type) {
2331 case TCP_V4_FLOW:
2332 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2333 case UDP_V4_FLOW:
2334 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2335 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2336 case SCTP_V4_FLOW:
2337 case AH_ESP_V4_FLOW:
2338 case AH_V4_FLOW:
2339 case ESP_V4_FLOW:
2340 case IPV4_FLOW:
2341 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2342 break;
2343 case TCP_V6_FLOW:
2344 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2345 case UDP_V6_FLOW:
2346 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2347 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2348 case SCTP_V6_FLOW:
2349 case AH_ESP_V6_FLOW:
2350 case AH_V6_FLOW:
2351 case ESP_V6_FLOW:
2352 case IPV6_FLOW:
2353 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2354 break;
2355 default:
2356 return -EINVAL;
2357 }
2358
2359 return 0;
2360}
2361
91cd94bf 2362static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
815c7db5 2363 u32 *rule_locs)
91cd94bf
AD		 2364{
2365 struct ixgbe_adapter *adapter = netdev_priv(dev);
2366 int ret = -EOPNOTSUPP;
2367
2368 switch (cmd->cmd) {
2369 case ETHTOOL_GRXRINGS:
2370 cmd->data = adapter->num_rx_queues;
2371 ret = 0;
2372 break;
3e05334f
AD		 2373 case ETHTOOL_GRXCLSRLCNT:
2374 cmd->rule_cnt = adapter->fdir_filter_count;
2375 ret = 0;
2376 break;
2377 case ETHTOOL_GRXCLSRULE:
2378 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2379 break;
2380 case ETHTOOL_GRXCLSRLALL:
815c7db5 2381 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
3e05334f 2382 break;
ef6afc0c
AD		 2383 case ETHTOOL_GRXFH:
2384 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2385 break;
91cd94bf
AD		 2386 default:
2387 break;
2388 }
2389
2390 return ret;
2391}
2392
e4911d57
AD		 2393static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2394 struct ixgbe_fdir_filter *input,
2395 u16 sw_idx)
2396{
2397 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d
SL		 2398 struct hlist_node *node2;
2399 struct ixgbe_fdir_filter *rule, *parent;
e4911d57
AD		 2400 int err = -EINVAL;
2401
2402 parent = NULL;
2403 rule = NULL;
2404
b67bfe0d 2405 hlist_for_each_entry_safe(rule, node2,
e4911d57
AD		 2406 &adapter->fdir_filter_list, fdir_node) {
2407 /* hash found, or no matching entry */
2408 if (rule->sw_idx >= sw_idx)
2409 break;
b67bfe0d 2410 parent = rule;
e4911d57
AD		 2411 }
2412
2413 /* if there is an old rule occupying our place remove it */
2414 if (rule && (rule->sw_idx == sw_idx)) {
2415 if (!input || (rule->filter.formatted.bkt_hash !=
2416 input->filter.formatted.bkt_hash)) {
2417 err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2418 &rule->filter,
2419 sw_idx);
2420 }
2421
2422 hlist_del(&rule->fdir_node);
2423 kfree(rule);
2424 adapter->fdir_filter_count--;
2425 }
2426
2427 /*
2428 * If no input this was a delete, err should be 0 if a rule was
2429 * successfully found and removed from the list else -EINVAL
2430 */
2431 if (!input)
2432 return err;
2433
2434 /* initialize node and set software index */
2435 INIT_HLIST_NODE(&input->fdir_node);
2436
2437 /* add filter to the list */
2438 if (parent)
b67bfe0d 2439 hlist_add_after(&parent->fdir_node, &input->fdir_node);
e4911d57
AD		 2440 else
2441 hlist_add_head(&input->fdir_node,
2442 &adapter->fdir_filter_list);
2443
2444 /* update counts */
2445 adapter->fdir_filter_count++;
2446
2447 return 0;
2448}
2449
2450static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2451 u8 *flow_type)
2452{
2453 switch (fsp->flow_type & ~FLOW_EXT) {
2454 case TCP_V4_FLOW:
2455 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2456 break;
2457 case UDP_V4_FLOW:
2458 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2459 break;
2460 case SCTP_V4_FLOW:
2461 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2462 break;
2463 case IP_USER_FLOW:
2464 switch (fsp->h_u.usr_ip4_spec.proto) {
2465 case IPPROTO_TCP:
2466 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2467 break;
2468 case IPPROTO_UDP:
2469 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2470 break;
2471 case IPPROTO_SCTP:
2472 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2473 break;
2474 case 0:
2475 if (!fsp->m_u.usr_ip4_spec.proto) {
2476 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2477 break;
2478 }
2479 default:
2480 return 0;
2481 }
2482 break;
2483 default:
2484 return 0;
2485 }
2486
2487 return 1;
2488}
2489
2490static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2491 struct ethtool_rxnfc *cmd)
2492{
2493 struct ethtool_rx_flow_spec *fsp =
2494 (struct ethtool_rx_flow_spec *)&cmd->fs;
2495 struct ixgbe_hw *hw = &adapter->hw;
2496 struct ixgbe_fdir_filter *input;
2497 union ixgbe_atr_input mask;
2498 int err;
2499
2500 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2501 return -EOPNOTSUPP;
2502
2503 /*
2504 * Don't allow programming if the action is a queue greater than
2505 * the number of online Rx queues.
2506 */
2507 if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2508 (fsp->ring_cookie >= adapter->num_rx_queues))
2509 return -EINVAL;
2510
2511 /* Don't allow indexes to exist outside of available space */
2512 if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2513 e_err(drv, "Location out of range\n");
2514 return -EINVAL;
2515 }
2516
2517 input = kzalloc(sizeof(*input), GFP_ATOMIC);
2518 if (!input)
2519 return -ENOMEM;
2520
2521 memset(&mask, 0, sizeof(union ixgbe_atr_input));
2522
2523 /* set SW index */
2524 input->sw_idx = fsp->location;
2525
2526 /* record flow type */
2527 if (!ixgbe_flowspec_to_flow_type(fsp,
2528 &input->filter.formatted.flow_type)) {
2529 e_err(drv, "Unrecognized flow type\n");
2530 goto err_out;
2531 }
2532
2533 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2534 IXGBE_ATR_L4TYPE_MASK;
2535
2536 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2537 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2538
2539 /* Copy input into formatted structures */
2540 input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2541 mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2542 input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2543 mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2544 input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2545 mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2546 input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2547 mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2548
2549 if (fsp->flow_type & FLOW_EXT) {
2550 input->filter.formatted.vm_pool =
2551 (unsigned char)ntohl(fsp->h_ext.data[1]);
2552 mask.formatted.vm_pool =
2553 (unsigned char)ntohl(fsp->m_ext.data[1]);
2554 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2555 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2556 input->filter.formatted.flex_bytes =
2557 fsp->h_ext.vlan_etype;
2558 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2559 }
2560
2561 /* determine if we need to drop or route the packet */
2562 if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2563 input->action = IXGBE_FDIR_DROP_QUEUE;
2564 else
2565 input->action = fsp->ring_cookie;
2566
2567 spin_lock(&adapter->fdir_perfect_lock);
2568
2569 if (hlist_empty(&adapter->fdir_filter_list)) {
2570 /* save mask and program input mask into HW */
2571 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2572 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2573 if (err) {
2574 e_err(drv, "Error writing mask\n");
2575 goto err_out_w_lock;
2576 }
2577 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2578 e_err(drv, "Only one mask supported per port\n");
2579 goto err_out_w_lock;
2580 }
2581
2582 /* apply mask and compute/store hash */
2583 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2584
2585 /* program filters to filter memory */
2586 err = ixgbe_fdir_write_perfect_filter_82599(hw,
2587 &input->filter, input->sw_idx,
1f4d5183
AD		 2588 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2589 IXGBE_FDIR_DROP_QUEUE :
e4911d57
AD		 2590 adapter->rx_ring[input->action]->reg_idx);
2591 if (err)
2592 goto err_out_w_lock;
2593
2594 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2595
2596 spin_unlock(&adapter->fdir_perfect_lock);
2597
2598 return err;
2599err_out_w_lock:
2600 spin_unlock(&adapter->fdir_perfect_lock);
2601err_out:
2602 kfree(input);
2603 return -EINVAL;
2604}
2605
2606static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2607 struct ethtool_rxnfc *cmd)
2608{
2609 struct ethtool_rx_flow_spec *fsp =
2610 (struct ethtool_rx_flow_spec *)&cmd->fs;
2611 int err;
2612
2613 spin_lock(&adapter->fdir_perfect_lock);
2614 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2615 spin_unlock(&adapter->fdir_perfect_lock);
2616
2617 return err;
2618}
2619
ef6afc0c
AD		 2620#define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2621 IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2622static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2623 struct ethtool_rxnfc *nfc)
2624{
2625 u32 flags2 = adapter->flags2;
2626
2627 /*
2628 * RSS does not support anything other than hashing
2629 * to queues on src and dst IPs and ports
2630 */
2631 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2632 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2633 return -EINVAL;
2634
2635 switch (nfc->flow_type) {
2636 case TCP_V4_FLOW:
2637 case TCP_V6_FLOW:
2638 if (!(nfc->data & RXH_IP_SRC) ||
2639 !(nfc->data & RXH_IP_DST) ||
2640 !(nfc->data & RXH_L4_B_0_1) ||
2641 !(nfc->data & RXH_L4_B_2_3))
2642 return -EINVAL;
2643 break;
2644 case UDP_V4_FLOW:
2645 if (!(nfc->data & RXH_IP_SRC) ||
2646 !(nfc->data & RXH_IP_DST))
2647 return -EINVAL;
2648 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2649 case 0:
2650 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2651 break;
2652 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2653 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2654 break;
2655 default:
2656 return -EINVAL;
2657 }
2658 break;
2659 case UDP_V6_FLOW:
2660 if (!(nfc->data & RXH_IP_SRC) ||
2661 !(nfc->data & RXH_IP_DST))
2662 return -EINVAL;
2663 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2664 case 0:
2665 flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2666 break;
2667 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2668 flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2669 break;
2670 default:
2671 return -EINVAL;
2672 }
2673 break;
2674 case AH_ESP_V4_FLOW:
2675 case AH_V4_FLOW:
2676 case ESP_V4_FLOW:
2677 case SCTP_V4_FLOW:
2678 case AH_ESP_V6_FLOW:
2679 case AH_V6_FLOW:
2680 case ESP_V6_FLOW:
2681 case SCTP_V6_FLOW:
2682 if (!(nfc->data & RXH_IP_SRC) ||
2683 !(nfc->data & RXH_IP_DST) ||
2684 (nfc->data & RXH_L4_B_0_1) ||
2685 (nfc->data & RXH_L4_B_2_3))
2686 return -EINVAL;
2687 break;
2688 default:
2689 return -EINVAL;
2690 }
2691
2692 /* if we changed something we need to update flags */
2693 if (flags2 != adapter->flags2) {
2694 struct ixgbe_hw *hw = &adapter->hw;
2695 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2696
2697 if ((flags2 & UDP_RSS_FLAGS) &&
2698 !(adapter->flags2 & UDP_RSS_FLAGS))
2699 e_warn(drv, "enabling UDP RSS: fragmented packets"
2700 " may arrive out of order to the stack above\n");
2701
2702 adapter->flags2 = flags2;
2703
2704 /* Perform hash on these packet types */
2705 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2706 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2707 | IXGBE_MRQC_RSS_FIELD_IPV6
2708 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2709
2710 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2711 IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2712
2713 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2714 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2715
2716 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2717 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2718
2719 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2720 }
2721
2722 return 0;
2723}
2724
e4911d57
AD		 2725static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2726{
2727 struct ixgbe_adapter *adapter = netdev_priv(dev);
2728 int ret = -EOPNOTSUPP;
2729
2730 switch (cmd->cmd) {
2731 case ETHTOOL_SRXCLSRLINS:
2732 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2733 break;
2734 case ETHTOOL_SRXCLSRLDEL:
2735 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2736 break;
ef6afc0c
AD		 2737 case ETHTOOL_SRXFH:
2738 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2739 break;
e4911d57
AD		 2740 default:
2741 break;
2742 }
2743
2744 return ret;
2745}
2746
e3aac889
JK		 2747static int ixgbe_get_ts_info(struct net_device *dev,
2748 struct ethtool_ts_info *info)
2749{
2750 struct ixgbe_adapter *adapter = netdev_priv(dev);
2751
2752 switch (adapter->hw.mac.type) {
e3aac889
JK		 2753 case ixgbe_mac_X540:
2754 case ixgbe_mac_82599EB:
2755 info->so_timestamping =
50f8d35d
JK		 2756 SOF_TIMESTAMPING_TX_SOFTWARE |
2757 SOF_TIMESTAMPING_RX_SOFTWARE |
2758 SOF_TIMESTAMPING_SOFTWARE |
e3aac889
JK		 2759 SOF_TIMESTAMPING_TX_HARDWARE |
2760 SOF_TIMESTAMPING_RX_HARDWARE |
2761 SOF_TIMESTAMPING_RAW_HARDWARE;
2762
2763 if (adapter->ptp_clock)
2764 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2765 else
2766 info->phc_index = -1;
2767
2768 info->tx_types =
2769 (1 << HWTSTAMP_TX_OFF) |
2770 (1 << HWTSTAMP_TX_ON);
2771
2772 info->rx_filters =
2773 (1 << HWTSTAMP_FILTER_NONE) |
2774 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2775 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
aeb82648
JK		 2776 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2777 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2778 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2779 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2780 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2781 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2782 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2783 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1cc92eb8 2784 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
e3aac889 2785 break;
e3aac889
JK		 2786 default:
2787 return ethtool_op_get_ts_info(dev, info);
2788 break;
2789 }
2790 return 0;
2791}
2792
5348c9db
AD		 2793static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2794{
2795 unsigned int max_combined;
2796 u8 tcs = netdev_get_num_tc(adapter->netdev);
2797
2798 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2799 /* We only support one q_vector without MSI-X */
2800 max_combined = 1;
2801 } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2802 /* SR-IOV currently only allows one queue on the PF */
2803 max_combined = 1;
2804 } else if (tcs > 1) {
2805 /* For DCB report channels per traffic class */
2806 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2807 /* 8 TC w/ 4 queues per TC */
2808 max_combined = 4;
2809 } else if (tcs > 4) {
2810 /* 8 TC w/ 8 queues per TC */
2811 max_combined = 8;
2812 } else {
2813 /* 4 TC w/ 16 queues per TC */
2814 max_combined = 16;
2815 }
2816 } else if (adapter->atr_sample_rate) {
2817 /* support up to 64 queues with ATR */
2818 max_combined = IXGBE_MAX_FDIR_INDICES;
2819 } else {
2820 /* support up to 16 queues with RSS */
2821 max_combined = IXGBE_MAX_RSS_INDICES;
2822 }
2823
2824 return max_combined;
2825}
2826
2827static void ixgbe_get_channels(struct net_device *dev,
2828 struct ethtool_channels *ch)
2829{
2830 struct ixgbe_adapter *adapter = netdev_priv(dev);
2831
2832 /* report maximum channels */
2833 ch->max_combined = ixgbe_max_channels(adapter);
2834
2835 /* report info for other vector */
2836 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2837 ch->max_other = NON_Q_VECTORS;
2838 ch->other_count = NON_Q_VECTORS;
2839 }
2840
2841 /* record RSS queues */
2842 ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2843
2844 /* nothing else to report if RSS is disabled */
2845 if (ch->combined_count == 1)
2846 return;
2847
2848 /* we do not support ATR queueing if SR-IOV is enabled */
2849 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2850 return;
2851
2852 /* same thing goes for being DCB enabled */
2853 if (netdev_get_num_tc(dev) > 1)
2854 return;
2855
2856 /* if ATR is disabled we can exit */
2857 if (!adapter->atr_sample_rate)
2858 return;
2859
2860 /* report flow director queues as maximum channels */
2861 ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
2862}
2863
4c696ca9
AD		 2864static int ixgbe_set_channels(struct net_device *dev,
2865 struct ethtool_channels *ch)
2866{
2867 struct ixgbe_adapter *adapter = netdev_priv(dev);
2868 unsigned int count = ch->combined_count;
2869
2870 /* verify they are not requesting separate vectors */
2871 if (!count || ch->rx_count || ch->tx_count)
2872 return -EINVAL;
2873
2874 /* verify other_count has not changed */
2875 if (ch->other_count != NON_Q_VECTORS)
2876 return -EINVAL;
2877
2878 /* verify the number of channels does not exceed hardware limits */
2879 if (count > ixgbe_max_channels(adapter))
2880 return -EINVAL;
2881
2882 /* update feature limits from largest to smallest supported values */
2883 adapter->ring_feature[RING_F_FDIR].limit = count;
2884
2885 /* cap RSS limit at 16 */
2886 if (count > IXGBE_MAX_RSS_INDICES)
2887 count = IXGBE_MAX_RSS_INDICES;
2888 adapter->ring_feature[RING_F_RSS].limit = count;
2889
2890#ifdef IXGBE_FCOE
2891 /* cap FCoE limit at 8 */
2892 if (count > IXGBE_FCRETA_SIZE)
2893 count = IXGBE_FCRETA_SIZE;
2894 adapter->ring_feature[RING_F_FCOE].limit = count;
2895
2896#endif
2897 /* use setup TC to update any traffic class queue mapping */
2898 return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
2899}
2900
71858acb
AG		 2901static int ixgbe_get_module_info(struct net_device *dev,
2902 struct ethtool_modinfo *modinfo)
2903{
2904 struct ixgbe_adapter *adapter = netdev_priv(dev);
2905 struct ixgbe_hw *hw = &adapter->hw;
2906 u32 status;
2907 u8 sff8472_rev, addr_mode;
71858acb
AG		 2908 bool page_swap = false;
2909
71858acb
AG		 2910 /* Check whether we support SFF-8472 or not */
2911 status = hw->phy.ops.read_i2c_eeprom(hw,
2912 IXGBE_SFF_SFF_8472_COMP,
2913 &sff8472_rev);
a4b6fc6b
ET		 2914 if (status != 0)
2915 return -EIO;
71858acb
AG		 2916
2917 /* addressing mode is not supported */
2918 status = hw->phy.ops.read_i2c_eeprom(hw,
2919 IXGBE_SFF_SFF_8472_SWAP,
2920 &addr_mode);
a4b6fc6b
ET		 2921 if (status != 0)
2922 return -EIO;
71858acb
AG		 2923
2924 if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
2925 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2926 page_swap = true;
2927 }
2928
2929 if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
2930 /* We have a SFP, but it does not support SFF-8472 */
2931 modinfo->type = ETH_MODULE_SFF_8079;
2932 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2933 } else {
2934 /* We have a SFP which supports a revision of SFF-8472. */
2935 modinfo->type = ETH_MODULE_SFF_8472;
2936 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2937 }
2938
a4b6fc6b 2939 return 0;
71858acb
AG		 2940}
2941
2942static int ixgbe_get_module_eeprom(struct net_device *dev,
2943 struct ethtool_eeprom *ee,
2944 u8 *data)
2945{
2946 struct ixgbe_adapter *adapter = netdev_priv(dev);
2947 struct ixgbe_hw *hw = &adapter->hw;
2948 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2949 u8 databyte = 0xFF;
2950 int i = 0;
71858acb 2951
a4b6fc6b
ET		 2952 if (ee->len == 0)
2953 return -EINVAL;
71858acb 2954
31c7d2b0 2955 for (i = ee->offset; i < ee->offset + ee->len; i++) {
a4b6fc6b
ET		 2956 /* I2C reads can take long time */
2957 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
2958 return -EBUSY;
71858acb 2959
a4b6fc6b 2960 if (i < ETH_MODULE_SFF_8079_LEN)
31c7d2b0 2961 status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
a4b6fc6b
ET		 2962 else
2963 status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
2964
2965 if (status != 0)
31c7d2b0 2966 return -EIO;
71858acb 2967
a4b6fc6b 2968 data[i - ee->offset] = databyte;
71858acb
AG		 2969 }
2970
31c7d2b0 2971 return 0;
71858acb
AG		 2972}
2973
b9804972 2974static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2975 .get_settings = ixgbe_get_settings,
2976 .set_settings = ixgbe_set_settings,
2977 .get_drvinfo = ixgbe_get_drvinfo,
2978 .get_regs_len = ixgbe_get_regs_len,
2979 .get_regs = ixgbe_get_regs,
2980 .get_wol = ixgbe_get_wol,
e63d9762 2981 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2982 .nway_reset = ixgbe_nway_reset,
2983 .get_link = ethtool_op_get_link,
2984 .get_eeprom_len = ixgbe_get_eeprom_len,
2985 .get_eeprom = ixgbe_get_eeprom,
2fa5eef4 2986 .set_eeprom = ixgbe_set_eeprom,
9a799d71
AK		 2987 .get_ringparam = ixgbe_get_ringparam,
2988 .set_ringparam = ixgbe_set_ringparam,
2989 .get_pauseparam = ixgbe_get_pauseparam,
2990 .set_pauseparam = ixgbe_set_pauseparam,
9a799d71
AK		 2991 .get_msglevel = ixgbe_get_msglevel,
2992 .set_msglevel = ixgbe_set_msglevel,
da4dd0f7 2993 .self_test = ixgbe_diag_test,
9a799d71 2994 .get_strings = ixgbe_get_strings,
66e6961c 2995 .set_phys_id = ixgbe_set_phys_id,
b4617240 2996 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2997 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2998 .get_coalesce = ixgbe_get_coalesce,
2999 .set_coalesce = ixgbe_set_coalesce,
91cd94bf 3000 .get_rxnfc = ixgbe_get_rxnfc,
e4911d57 3001 .set_rxnfc = ixgbe_set_rxnfc,
5348c9db 3002 .get_channels = ixgbe_get_channels,
4c696ca9 3003 .set_channels = ixgbe_set_channels,
e3aac889 3004 .get_ts_info = ixgbe_get_ts_info,
71858acb
AG		 3005 .get_module_info = ixgbe_get_module_info,
3006 .get_module_eeprom = ixgbe_get_module_eeprom,
9a799d71
AK		 3007};
3008
3009void ixgbe_set_ethtool_ops(struct net_device *netdev)
3010{
3011 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
3012}
Linux kernel - Deliverables
This page took 0.920446 seconds and 5 git commands to generate.