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[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
9a799d71
AK		 68
69char ixgbe_driver_name[] = "ixgbe";
9c8eb720 70static const char ixgbe_driver_string[] =
e8e9f696 71 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 72#ifdef IXGBE_FCOE
ea81875a
NP		 73char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 75#else
76static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78#endif
9be4a9bb 79#define DRV_VERSION "4.0.1-k"
9c8eb720 80const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 81static const char ixgbe_copyright[] =
0391bbe3 82 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 83
84static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 85 [board_82598] = &ixgbe_82598_info,
86 [board_82599] = &ixgbe_82599_info,
87 [board_X540] = &ixgbe_X540_info,
88 [board_X550] = &ixgbe_X550_info,
89 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 90};
91
92/* ixgbe_pci_tbl - PCI Device ID Table
93 *
94 * Wildcard entries (PCI_ANY_ID) should come last
95 * Last entry must be all 0s
96 *
97 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
98 * Class, Class Mask, private data (not used) }
99 */
9baa3c34 100static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
9a799d71
AK		 134 /* required last entry */
135 {0, }
136};
137MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
5dd2d332 139#ifdef CONFIG_IXGBE_DCA
bd0362dd 140static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 141 void *p);
bd0362dd
JC		 142static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146};
147#endif
148
1cdd1ec8
GR		 149#ifdef CONFIG_PCI_IOV
150static unsigned int max_vfs;
151module_param(max_vfs, uint, 0);
e8e9f696 152MODULE_PARM_DESC(max_vfs,
170e8543 153 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 154#endif /* CONFIG_PCI_IOV */
155
8ef78adc
PWJ		 156static unsigned int allow_unsupported_sfp;
157module_param(allow_unsupported_sfp, uint, 0);
158MODULE_PARM_DESC(allow_unsupported_sfp,
159 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
160
b3f4d599 161#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
162static int debug = -1;
163module_param(debug, int, 0);
164MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
165
9a799d71
AK		 166MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
167MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
168MODULE_LICENSE("GPL");
169MODULE_VERSION(DRV_VERSION);
170
14438464
MR		 171static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
172
b8e82001
JK		 173static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
174 u32 reg, u16 *value)
175{
b8e82001
JK		 176 struct pci_dev *parent_dev;
177 struct pci_bus *parent_bus;
178
179 parent_bus = adapter->pdev->bus->parent;
180 if (!parent_bus)
181 return -1;
182
183 parent_dev = parent_bus->self;
184 if (!parent_dev)
185 return -1;
186
c0798edf 187 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 188 return -1;
189
c0798edf 190 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 191 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
192 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
193 return -1;
b8e82001
JK		 194 return 0;
195}
196
197static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
198{
199 struct ixgbe_hw *hw = &adapter->hw;
200 u16 link_status = 0;
201 int err;
202
203 hw->bus.type = ixgbe_bus_type_pci_express;
204
205 /* Get the negotiated link width and speed from PCI config space of the
206 * parent, as this device is behind a switch
207 */
208 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
209
210 /* assume caller will handle error case */
211 if (err)
212 return err;
213
214 hw->bus.width = ixgbe_convert_bus_width(link_status);
215 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
216
217 return 0;
218}
219
e027d1ae
JK		 220/**
221 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
222 * @hw: hw specific details
223 *
224 * This function is used by probe to determine whether a device's PCI-Express
225 * bandwidth details should be gathered from the parent bus instead of from the
226 * device. Used to ensure that various locations all have the correct device ID
227 * checks.
228 */
229static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
230{
231 switch (hw->device_id) {
232 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 233 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 234 return true;
235 default:
236 return false;
237 }
238}
239
240static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
241 int expected_gts)
242{
243 int max_gts = 0;
244 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
245 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
246 struct pci_dev *pdev;
247
248 /* determine whether to use the the parent device
249 */
250 if (ixgbe_pcie_from_parent(&adapter->hw))
251 pdev = adapter->pdev->bus->parent->self;
252 else
253 pdev = adapter->pdev;
254
255 if (pcie_get_minimum_link(pdev, &speed, &width) ||
256 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
257 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
258 return;
259 }
260
261 switch (speed) {
262 case PCIE_SPEED_2_5GT:
263 /* 8b/10b encoding reduces max throughput by 20% */
264 max_gts = 2 * width;
265 break;
266 case PCIE_SPEED_5_0GT:
267 /* 8b/10b encoding reduces max throughput by 20% */
268 max_gts = 4 * width;
269 break;
270 case PCIE_SPEED_8_0GT:
9f0a433c 271 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 272 max_gts = 8 * width;
273 break;
274 default:
275 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
276 return;
277 }
278
279 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
280 max_gts);
281 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
282 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
283 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
284 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
285 "Unknown"),
286 width,
287 (speed == PCIE_SPEED_2_5GT ? "20%" :
288 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 289 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 290 "Unknown"));
291
292 if (max_gts < expected_gts) {
293 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
294 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
295 expected_gts);
296 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
297 }
298}
299
7086400d
AD		 300static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
301{
302 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 303 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 304 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
305 schedule_work(&adapter->service_task);
306}
307
2a1a091c
MR		 308static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
309{
310 struct ixgbe_adapter *adapter = hw->back;
311
312 if (!hw->hw_addr)
313 return;
314 hw->hw_addr = NULL;
315 e_dev_err("Adapter removed\n");
58cf663f
MR		 316 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
317 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 318}
319
f8e2472f 320static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 321{
322 u32 value;
323
324 /* The following check not only optimizes a bit by not
325 * performing a read on the status register when the
326 * register just read was a status register read that
327 * returned IXGBE_FAILED_READ_REG. It also blocks any
328 * potential recursion.
329 */
330 if (reg == IXGBE_STATUS) {
331 ixgbe_remove_adapter(hw);
332 return;
333 }
334 value = ixgbe_read_reg(hw, IXGBE_STATUS);
335 if (value == IXGBE_FAILED_READ_REG)
336 ixgbe_remove_adapter(hw);
337}
338
f8e2472f
MR		 339/**
340 * ixgbe_read_reg - Read from device register
341 * @hw: hw specific details
342 * @reg: offset of register to read
343 *
344 * Returns : value read or IXGBE_FAILED_READ_REG if removed
345 *
346 * This function is used to read device registers. It checks for device
347 * removal by confirming any read that returns all ones by checking the
348 * status register value for all ones. This function avoids reading from
349 * the hardware if a removal was previously detected in which case it
350 * returns IXGBE_FAILED_READ_REG (all ones).
351 */
352u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
353{
354 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
355 u32 value;
356
357 if (ixgbe_removed(reg_addr))
358 return IXGBE_FAILED_READ_REG;
359 value = readl(reg_addr + reg);
360 if (unlikely(value == IXGBE_FAILED_READ_REG))
361 ixgbe_check_remove(hw, reg);
362 return value;
363}
364
14438464
MR		 365static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
366{
367 u16 value;
368
369 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
370 if (value == IXGBE_FAILED_READ_CFG_WORD) {
371 ixgbe_remove_adapter(hw);
372 return true;
373 }
374 return false;
375}
376
377u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
378{
379 struct ixgbe_adapter *adapter = hw->back;
380 u16 value;
381
382 if (ixgbe_removed(hw->hw_addr))
383 return IXGBE_FAILED_READ_CFG_WORD;
384 pci_read_config_word(adapter->pdev, reg, &value);
385 if (value == IXGBE_FAILED_READ_CFG_WORD &&
386 ixgbe_check_cfg_remove(hw, adapter->pdev))
387 return IXGBE_FAILED_READ_CFG_WORD;
388 return value;
389}
390
391#ifdef CONFIG_PCI_IOV
392static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
393{
394 struct ixgbe_adapter *adapter = hw->back;
395 u32 value;
396
397 if (ixgbe_removed(hw->hw_addr))
398 return IXGBE_FAILED_READ_CFG_DWORD;
399 pci_read_config_dword(adapter->pdev, reg, &value);
400 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
401 ixgbe_check_cfg_remove(hw, adapter->pdev))
402 return IXGBE_FAILED_READ_CFG_DWORD;
403 return value;
404}
405#endif /* CONFIG_PCI_IOV */
406
ed19231c
JK		 407void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
408{
409 struct ixgbe_adapter *adapter = hw->back;
410
411 if (ixgbe_removed(hw->hw_addr))
412 return;
413 pci_write_config_word(adapter->pdev, reg, value);
414}
415
7086400d
AD		 416static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
417{
418 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
419
52f33af8 420 /* flush memory to make sure state is correct before next watchdog */
4e857c58 421 smp_mb__before_atomic();
7086400d
AD		 422 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
423}
424
dcd79aeb
TI		 425struct ixgbe_reg_info {
426 u32 ofs;
427 char *name;
428};
429
430static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
431
432 /* General Registers */
433 {IXGBE_CTRL, "CTRL"},
434 {IXGBE_STATUS, "STATUS"},
435 {IXGBE_CTRL_EXT, "CTRL_EXT"},
436
437 /* Interrupt Registers */
438 {IXGBE_EICR, "EICR"},
439
440 /* RX Registers */
441 {IXGBE_SRRCTL(0), "SRRCTL"},
442 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
443 {IXGBE_RDLEN(0), "RDLEN"},
444 {IXGBE_RDH(0), "RDH"},
445 {IXGBE_RDT(0), "RDT"},
446 {IXGBE_RXDCTL(0), "RXDCTL"},
447 {IXGBE_RDBAL(0), "RDBAL"},
448 {IXGBE_RDBAH(0), "RDBAH"},
449
450 /* TX Registers */
451 {IXGBE_TDBAL(0), "TDBAL"},
452 {IXGBE_TDBAH(0), "TDBAH"},
453 {IXGBE_TDLEN(0), "TDLEN"},
454 {IXGBE_TDH(0), "TDH"},
455 {IXGBE_TDT(0), "TDT"},
456 {IXGBE_TXDCTL(0), "TXDCTL"},
457
458 /* List Terminator */
ca8dfe25 459 { .name = NULL }
dcd79aeb
TI		 460};
461
462
463/*
464 * ixgbe_regdump - register printout routine
465 */
466static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
467{
468 int i = 0, j = 0;
469 char rname[16];
470 u32 regs[64];
471
472 switch (reginfo->ofs) {
473 case IXGBE_SRRCTL(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
476 break;
477 case IXGBE_DCA_RXCTRL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
480 break;
481 case IXGBE_RDLEN(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
484 break;
485 case IXGBE_RDH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
488 break;
489 case IXGBE_RDT(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
492 break;
493 case IXGBE_RXDCTL(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
496 break;
497 case IXGBE_RDBAL(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
500 break;
501 case IXGBE_RDBAH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
504 break;
505 case IXGBE_TDBAL(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
508 break;
509 case IXGBE_TDBAH(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
512 break;
513 case IXGBE_TDLEN(0):
514 for (i = 0; i < 64; i++)
515 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
516 break;
517 case IXGBE_TDH(0):
518 for (i = 0; i < 64; i++)
519 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
520 break;
521 case IXGBE_TDT(0):
522 for (i = 0; i < 64; i++)
523 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
524 break;
525 case IXGBE_TXDCTL(0):
526 for (i = 0; i < 64; i++)
527 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
528 break;
529 default:
c7689578 530 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 531 IXGBE_READ_REG(hw, reginfo->ofs));
532 return;
533 }
534
535 for (i = 0; i < 8; i++) {
536 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 537 pr_err("%-15s", rname);
dcd79aeb 538 for (j = 0; j < 8; j++)
c7689578
JP		 539 pr_cont(" %08x", regs[i*8+j]);
540 pr_cont("\n");
dcd79aeb
TI		 541 }
542
543}
544
545/*
546 * ixgbe_dump - Print registers, tx-rings and rx-rings
547 */
548static void ixgbe_dump(struct ixgbe_adapter *adapter)
549{
550 struct net_device *netdev = adapter->netdev;
551 struct ixgbe_hw *hw = &adapter->hw;
552 struct ixgbe_reg_info *reginfo;
553 int n = 0;
554 struct ixgbe_ring *tx_ring;
729739b7 555 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 556 union ixgbe_adv_tx_desc *tx_desc;
557 struct my_u0 { u64 a; u64 b; } *u0;
558 struct ixgbe_ring *rx_ring;
559 union ixgbe_adv_rx_desc *rx_desc;
560 struct ixgbe_rx_buffer *rx_buffer_info;
561 u32 staterr;
562 int i = 0;
563
564 if (!netif_msg_hw(adapter))
565 return;
566
567 /* Print netdevice Info */
568 if (netdev) {
569 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 570 pr_info("Device Name state "
dcd79aeb 571 "trans_start last_rx\n");
c7689578
JP		 572 pr_info("%-15s %016lX %016lX %016lX\n",
573 netdev->name,
574 netdev->state,
575 netdev->trans_start,
576 netdev->last_rx);
dcd79aeb
TI		 577 }
578
579 /* Print Registers */
580 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 581 pr_info(" Register Name Value\n");
dcd79aeb
TI		 582 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
583 reginfo->name; reginfo++) {
584 ixgbe_regdump(hw, reginfo);
585 }
586
587 /* Print TX Ring Summary */
588 if (!netdev || !netif_running(netdev))
e90dd264 589 return;
dcd79aeb
TI		 590
591 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 592 pr_info(" %s %s %s %s\n",
593 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
594 "leng", "ntw", "timestamp");
dcd79aeb
TI		 595 for (n = 0; n < adapter->num_tx_queues; n++) {
596 tx_ring = adapter->tx_ring[n];
729739b7 597 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 598 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 599 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 600 (u64)dma_unmap_addr(tx_buffer, dma),
601 dma_unmap_len(tx_buffer, len),
602 tx_buffer->next_to_watch,
603 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 604 }
605
606 /* Print TX Rings */
607 if (!netif_msg_tx_done(adapter))
608 goto rx_ring_summary;
609
610 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
611
612 /* Transmit Descriptor Formats
613 *
39ac868a 614 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
39ac868a 618 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 621 *
622 * 82598 Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | NXTSEQ |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
629 *
630 * 82599+ Advanced Transmit Descriptor
631 * +--------------------------------------------------------------+
632 * 0 | Buffer Address [63:0] |
633 * +--------------------------------------------------------------+
634 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
635 * +--------------------------------------------------------------+
636 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
637 *
638 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
639 * +--------------------------------------------------------------+
640 * 0 | RSV [63:0] |
641 * +--------------------------------------------------------------+
642 * 8 | RSV | STA | RSV |
643 * +--------------------------------------------------------------+
644 * 63 36 35 32 31 0
dcd79aeb
TI		 645 */
646
647 for (n = 0; n < adapter->num_tx_queues; n++) {
648 tx_ring = adapter->tx_ring[n];
c7689578
JP		 649 pr_info("------------------------------------\n");
650 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
651 pr_info("------------------------------------\n");
8ad88e37
JH		 652 pr_info("%s%s %s %s %s %s\n",
653 "T [desc] [address 63:0 ] ",
654 "[PlPOIdStDDt Ln] [bi->dma ] ",
655 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 656
657 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 658 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 659 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 660 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 661 if (dma_unmap_len(tx_buffer, len) > 0) {
662 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
663 i,
664 le64_to_cpu(u0->a),
665 le64_to_cpu(u0->b),
666 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 667 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 668 tx_buffer->next_to_watch,
669 (u64)tx_buffer->time_stamp,
670 tx_buffer->skb);
671 if (i == tx_ring->next_to_use &&
672 i == tx_ring->next_to_clean)
673 pr_cont(" NTC/U\n");
674 else if (i == tx_ring->next_to_use)
675 pr_cont(" NTU\n");
676 else if (i == tx_ring->next_to_clean)
677 pr_cont(" NTC\n");
678 else
679 pr_cont("\n");
680
681 if (netif_msg_pktdata(adapter) &&
682 tx_buffer->skb)
683 print_hex_dump(KERN_INFO, "",
684 DUMP_PREFIX_ADDRESS, 16, 1,
685 tx_buffer->skb->data,
686 dma_unmap_len(tx_buffer, len),
687 true);
688 }
dcd79aeb
TI		 689 }
690 }
691
692 /* Print RX Rings Summary */
693rx_ring_summary:
694 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 695 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 696 for (n = 0; n < adapter->num_rx_queues; n++) {
697 rx_ring = adapter->rx_ring[n];
c7689578
JP		 698 pr_info("%5d %5X %5X\n",
699 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 700 }
701
702 /* Print RX Rings */
703 if (!netif_msg_rx_status(adapter))
e90dd264 704 return;
dcd79aeb
TI		 705
706 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
707
39ac868a
JH		 708 /* Receive Descriptor Formats
709 *
710 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 711 * 63 1 0
712 * +-----------------------------------------------------+
713 * 0 | Packet Buffer Address [63:1] |A0/NSE|
714 * +----------------------------------------------+------+
715 * 8 | Header Buffer Address [63:1] | DD |
716 * +-----------------------------------------------------+
717 *
718 *
39ac868a 719 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 720 *
721 * 63 48 47 32 31 30 21 20 16 15 4 3 0
722 * +------------------------------------------------------+
39ac868a
JH		 723 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
724 * | Packet | IP | | | | Type | Type |
725 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 726 * +------------------------------------------------------+
727 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
728 * +------------------------------------------------------+
729 * 63 48 47 32 31 20 19 0
39ac868a
JH		 730 *
731 * 82599+ Advanced Receive Descriptor (Read) Format
732 * 63 1 0
733 * +-----------------------------------------------------+
734 * 0 | Packet Buffer Address [63:1] |A0/NSE|
735 * +----------------------------------------------+------+
736 * 8 | Header Buffer Address [63:1] | DD |
737 * +-----------------------------------------------------+
738 *
739 *
740 * 82599+ Advanced Receive Descriptor (Write-Back) Format
741 *
742 * 63 48 47 32 31 30 21 20 17 16 4 3 0
743 * +------------------------------------------------------+
744 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
745 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
746 * |/ Flow Dir Flt ID | | | | | |
747 * +------------------------------------------------------+
748 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
749 * +------------------------------------------------------+
750 * 63 48 47 32 31 20 19 0
dcd79aeb 751 */
39ac868a 752
dcd79aeb
TI		 753 for (n = 0; n < adapter->num_rx_queues; n++) {
754 rx_ring = adapter->rx_ring[n];
c7689578
JP		 755 pr_info("------------------------------------\n");
756 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
757 pr_info("------------------------------------\n");
8ad88e37
JH		 758 pr_info("%s%s%s",
759 "R [desc] [ PktBuf A0] ",
760 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 761 "<-- Adv Rx Read format\n");
8ad88e37
JH		 762 pr_info("%s%s%s",
763 "RWB[desc] [PcsmIpSHl PtRs] ",
764 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 765 "<-- Adv Rx Write-Back format\n");
766
767 for (i = 0; i < rx_ring->count; i++) {
768 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 769 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 770 u0 = (struct my_u0 *)rx_desc;
771 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
772 if (staterr & IXGBE_RXD_STAT_DD) {
773 /* Descriptor Done */
c7689578 774 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 775 "%016llX ---------------- %p", i,
776 le64_to_cpu(u0->a),
777 le64_to_cpu(u0->b),
778 rx_buffer_info->skb);
779 } else {
c7689578 780 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 781 "%016llX %016llX %p", i,
782 le64_to_cpu(u0->a),
783 le64_to_cpu(u0->b),
784 (u64)rx_buffer_info->dma,
785 rx_buffer_info->skb);
786
9c50c035
ET		 787 if (netif_msg_pktdata(adapter) &&
788 rx_buffer_info->dma) {
dcd79aeb
TI		 789 print_hex_dump(KERN_INFO, "",
790 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 791 page_address(rx_buffer_info->page) +
792 rx_buffer_info->page_offset,
f800326d 793 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 794 }
795 }
796
797 if (i == rx_ring->next_to_use)
c7689578 798 pr_cont(" NTU\n");
dcd79aeb 799 else if (i == rx_ring->next_to_clean)
c7689578 800 pr_cont(" NTC\n");
dcd79aeb 801 else
c7689578 802 pr_cont("\n");
dcd79aeb
TI		 803
804 }
805 }
dcd79aeb
TI		 806}
807
5eba3699
AV		 808static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
809{
810 u32 ctrl_ext;
811
812 /* Let firmware take over control of h/w */
813 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
814 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 815 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 816}
817
818static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
819{
820 u32 ctrl_ext;
821
822 /* Let firmware know the driver has taken over */
823 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 825 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 826}
9a799d71 827
49ce9c2c 828/**
e8e26350
PW		 829 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
830 * @adapter: pointer to adapter struct
831 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
832 * @queue: queue to map the corresponding interrupt to
833 * @msix_vector: the vector to map to the corresponding queue
834 *
835 */
836static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 837 u8 queue, u8 msix_vector)
9a799d71
AK		 838{
839 u32 ivar, index;
e8e26350
PW		 840 struct ixgbe_hw *hw = &adapter->hw;
841 switch (hw->mac.type) {
842 case ixgbe_mac_82598EB:
843 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
844 if (direction == -1)
845 direction = 0;
846 index = (((direction * 64) + queue) >> 2) & 0x1F;
847 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
848 ivar &= ~(0xFF << (8 * (queue & 0x3)));
849 ivar |= (msix_vector << (8 * (queue & 0x3)));
850 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
851 break;
852 case ixgbe_mac_82599EB:
b93a2226 853 case ixgbe_mac_X540:
9a75a1ac
DS		 854 case ixgbe_mac_X550:
855 case ixgbe_mac_X550EM_x:
e8e26350
PW		 856 if (direction == -1) {
857 /* other causes */
858 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
859 index = ((queue & 1) * 8);
860 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
861 ivar &= ~(0xFF << index);
862 ivar |= (msix_vector << index);
863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
864 break;
865 } else {
866 /* tx or rx causes */
867 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
868 index = ((16 * (queue & 1)) + (8 * direction));
869 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
870 ivar &= ~(0xFF << index);
871 ivar |= (msix_vector << index);
872 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
873 break;
874 }
875 default:
876 break;
877 }
9a799d71
AK		 878}
879
fe49f04a 880static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 881 u64 qmask)
fe49f04a
AD		 882{
883 u32 mask;
884
bd508178
AD		 885 switch (adapter->hw.mac.type) {
886 case ixgbe_mac_82598EB:
fe49f04a
AD		 887 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 889 break;
890 case ixgbe_mac_82599EB:
b93a2226 891 case ixgbe_mac_X540:
9a75a1ac
DS		 892 case ixgbe_mac_X550:
893 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 894 mask = (qmask & 0xFFFFFFFF);
895 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
896 mask = (qmask >> 32);
897 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 898 break;
899 default:
900 break;
fe49f04a
AD		 901 }
902}
903
729739b7
AD		 904void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
905 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 906{
729739b7
AD		 907 if (tx_buffer->skb) {
908 dev_kfree_skb_any(tx_buffer->skb);
909 if (dma_unmap_len(tx_buffer, len))
d3d00239 910 dma_unmap_single(ring->dev,
729739b7
AD		 911 dma_unmap_addr(tx_buffer, dma),
912 dma_unmap_len(tx_buffer, len),
913 DMA_TO_DEVICE);
914 } else if (dma_unmap_len(tx_buffer, len)) {
915 dma_unmap_page(ring->dev,
916 dma_unmap_addr(tx_buffer, dma),
917 dma_unmap_len(tx_buffer, len),
918 DMA_TO_DEVICE);
e5a43549 919 }
729739b7
AD		 920 tx_buffer->next_to_watch = NULL;
921 tx_buffer->skb = NULL;
922 dma_unmap_len_set(tx_buffer, len, 0);
923 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 924}
925
943561d3 926static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 927{
928 struct ixgbe_hw *hw = &adapter->hw;
929 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 930 int i;
943561d3 931 u32 data;
c84d324c 932
943561d3
AD		 933 if ((hw->fc.current_mode != ixgbe_fc_full) &&
934 (hw->fc.current_mode != ixgbe_fc_rx_pause))
935 return;
c84d324c 936
943561d3
AD		 937 switch (hw->mac.type) {
938 case ixgbe_mac_82598EB:
939 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
940 break;
941 default:
942 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
943 }
944 hwstats->lxoffrxc += data;
c84d324c 945
943561d3
AD		 946 /* refill credits (no tx hang) if we received xoff */
947 if (!data)
c84d324c 948 return;
943561d3
AD		 949
950 for (i = 0; i < adapter->num_tx_queues; i++)
951 clear_bit(__IXGBE_HANG_CHECK_ARMED,
952 &adapter->tx_ring[i]->state);
953}
954
955static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
956{
957 struct ixgbe_hw *hw = &adapter->hw;
958 struct ixgbe_hw_stats *hwstats = &adapter->stats;
959 u32 xoff[8] = {0};
2afaa00d 960 u8 tc;
943561d3
AD		 961 int i;
962 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
963
964 if (adapter->ixgbe_ieee_pfc)
965 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
966
967 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
968 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 969 return;
943561d3 970 }
c84d324c
JF		 971
972 /* update stats for each tc, only valid with PFC enabled */
973 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 974 u32 pxoffrxc;
975
c84d324c
JF		 976 switch (hw->mac.type) {
977 case ixgbe_mac_82598EB:
2afaa00d 978 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 979 break;
c84d324c 980 default:
2afaa00d 981 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 982 }
2afaa00d
PN		 983 hwstats->pxoffrxc[i] += pxoffrxc;
984 /* Get the TC for given UP */
985 tc = netdev_get_prio_tc_map(adapter->netdev, i);
986 xoff[tc] += pxoffrxc;
c84d324c
JF		 987 }
988
989 /* disarm tx queues that have received xoff frames */
990 for (i = 0; i < adapter->num_tx_queues; i++) {
991 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 992
2afaa00d 993 tc = tx_ring->dcb_tc;
c84d324c
JF		 994 if (xoff[tc])
995 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 996 }
26f23d82
YZ		 997}
998
c84d324c 999static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1000{
7d7ce682 1001 return ring->stats.packets;
c84d324c
JF		 1002}
1003
1004static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1005{
2a47fa45
JF		 1006 struct ixgbe_adapter *adapter;
1007 struct ixgbe_hw *hw;
1008 u32 head, tail;
1009
1010 if (ring->l2_accel_priv)
1011 adapter = ring->l2_accel_priv->real_adapter;
1012 else
1013 adapter = netdev_priv(ring->netdev);
e01c31a5 1014
2a47fa45
JF		 1015 hw = &adapter->hw;
1016 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1017 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1018
1019 if (head != tail)
1020 return (head < tail) ?
1021 tail - head : (tail + ring->count - head);
1022
1023 return 0;
1024}
1025
1026static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1027{
1028 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1029 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1030 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1031
7d637bcc 1032 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1033
1034 /*
1035 * Check for a hung queue, but be thorough. This verifies
1036 * that a transmit has been completed since the previous
1037 * check AND there is at least one packet pending. The
1038 * ARMED bit is set to indicate a potential hang. The
1039 * bit is cleared if a pause frame is received to remove
1040 * false hang detection due to PFC or 802.3x frames. By
1041 * requiring this to fail twice we avoid races with
1042 * pfc clearing the ARMED bit and conditions where we
1043 * run the check_tx_hang logic with a transmit completion
1044 * pending but without time to complete it yet.
1045 */
e90dd264 1046 if (tx_done_old == tx_done && tx_pending)
c84d324c 1047 /* make sure it is true for two checks in a row */
e90dd264
MR		 1048 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1049 &tx_ring->state);
1050 /* update completed stats and continue */
1051 tx_ring->tx_stats.tx_done_old = tx_done;
1052 /* reset the countdown */
1053 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1054
e90dd264 1055 return false;
9a799d71
AK		 1056}
1057
c83c6cbd
AD		 1058/**
1059 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1060 * @adapter: driver private struct
1061 **/
1062static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1063{
1064
1065 /* Do the reset outside of interrupt context */
1066 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1067 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1068 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1069 ixgbe_service_event_schedule(adapter);
1070 }
1071}
e01c31a5 1072
9a799d71
AK		 1073/**
1074 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1075 * @q_vector: structure containing interrupt and ring information
e01c31a5 1076 * @tx_ring: tx ring to clean
9a799d71 1077 **/
fe49f04a 1078static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1079 struct ixgbe_ring *tx_ring)
9a799d71 1080{
fe49f04a 1081 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1082 struct ixgbe_tx_buffer *tx_buffer;
1083 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1084 unsigned int total_bytes = 0, total_packets = 0;
59224555 1085 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1086 unsigned int i = tx_ring->next_to_clean;
1087
1088 if (test_bit(__IXGBE_DOWN, &adapter->state))
1089 return true;
9a799d71 1090
d3d00239 1091 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1092 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1093 i -= tx_ring->count;
12207e49 1094
729739b7 1095 do {
d3d00239
AD		 1096 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1097
1098 /* if next_to_watch is not set then there is no work pending */
1099 if (!eop_desc)
1100 break;
1101
7f83a9e6 1102 /* prevent any other reads prior to eop_desc */
7e63bf49 1103 read_barrier_depends();
7f83a9e6 1104
d3d00239
AD		 1105 /* if DD is not set pending work has not been completed */
1106 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1107 break;
8ad494b0 1108
d3d00239
AD		 1109 /* clear next_to_watch to prevent false hangs */
1110 tx_buffer->next_to_watch = NULL;
8ad494b0 1111
091a6246
AD		 1112 /* update the statistics for this packet */
1113 total_bytes += tx_buffer->bytecount;
1114 total_packets += tx_buffer->gso_segs;
1115
fd0db0ed 1116 /* free the skb */
fe1f2a97 1117 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1118
729739b7
AD		 1119 /* unmap skb header data */
1120 dma_unmap_single(tx_ring->dev,
1121 dma_unmap_addr(tx_buffer, dma),
1122 dma_unmap_len(tx_buffer, len),
1123 DMA_TO_DEVICE);
1124
fd0db0ed
AD		 1125 /* clear tx_buffer data */
1126 tx_buffer->skb = NULL;
729739b7 1127 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1128
729739b7
AD		 1129 /* unmap remaining buffers */
1130 while (tx_desc != eop_desc) {
d3d00239
AD		 1131 tx_buffer++;
1132 tx_desc++;
8ad494b0 1133 i++;
729739b7
AD		 1134 if (unlikely(!i)) {
1135 i -= tx_ring->count;
d3d00239 1136 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1138 }
e01c31a5 1139
729739b7
AD		 1140 /* unmap any remaining paged data */
1141 if (dma_unmap_len(tx_buffer, len)) {
1142 dma_unmap_page(tx_ring->dev,
1143 dma_unmap_addr(tx_buffer, dma),
1144 dma_unmap_len(tx_buffer, len),
1145 DMA_TO_DEVICE);
1146 dma_unmap_len_set(tx_buffer, len, 0);
1147 }
1148 }
1149
1150 /* move us one more past the eop_desc for start of next pkt */
1151 tx_buffer++;
1152 tx_desc++;
1153 i++;
1154 if (unlikely(!i)) {
1155 i -= tx_ring->count;
1156 tx_buffer = tx_ring->tx_buffer_info;
1157 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1158 }
1159
1160 /* issue prefetch for next Tx descriptor */
1161 prefetch(tx_desc);
12207e49 1162
729739b7
AD		 1163 /* update budget accounting */
1164 budget--;
1165 } while (likely(budget));
1166
1167 i += tx_ring->count;
9a799d71 1168 tx_ring->next_to_clean = i;
d3d00239 1169 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1170 tx_ring->stats.bytes += total_bytes;
bd198058 1171 tx_ring->stats.packets += total_packets;
d3d00239 1172 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1173 q_vector->tx.total_bytes += total_bytes;
1174 q_vector->tx.total_packets += total_packets;
b953799e 1175
c84d324c
JF		 1176 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1177 /* schedule immediate reset if we believe we hung */
1178 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1179 e_err(drv, "Detected Tx Unit Hang\n"
1180 " Tx Queue <%d>\n"
1181 " TDH, TDT <%x>, <%x>\n"
1182 " next_to_use <%x>\n"
1183 " next_to_clean <%x>\n"
1184 "tx_buffer_info[next_to_clean]\n"
1185 " time_stamp <%lx>\n"
1186 " jiffies <%lx>\n",
1187 tx_ring->queue_index,
1188 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1189 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1190 tx_ring->next_to_use, i,
1191 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1192
1193 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1194
1195 e_info(probe,
1196 "tx hang %d detected on queue %d, resetting adapter\n",
1197 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1198
b953799e 1199 /* schedule immediate reset if we believe we hung */
c83c6cbd 1200 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1201
1202 /* the adapter is about to reset, no point in enabling stuff */
59224555 1203 return true;
b953799e 1204 }
9a799d71 1205
b2d96e0a
AD		 1206 netdev_tx_completed_queue(txring_txq(tx_ring),
1207 total_packets, total_bytes);
1208
e092be60 1209#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1210 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1211 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1212 /* Make sure that anybody stopping the queue after this
1213 * sees the new next_to_clean.
1214 */
1215 smp_mb();
729739b7
AD		 1216 if (__netif_subqueue_stopped(tx_ring->netdev,
1217 tx_ring->queue_index)
1218 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1219 netif_wake_subqueue(tx_ring->netdev,
1220 tx_ring->queue_index);
5b7da515 1221 ++tx_ring->tx_stats.restart_queue;
30eba97a 1222 }
e092be60 1223 }
9a799d71 1224
59224555 1225 return !!budget;
9a799d71
AK		 1226}
1227
5dd2d332 1228#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1229static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1230 struct ixgbe_ring *tx_ring,
33cf09c9 1231 int cpu)
bd0362dd 1232{
33cf09c9 1233 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1234 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1235 u16 reg_offset;
33cf09c9 1236
33cf09c9
AD		 1237 switch (hw->mac.type) {
1238 case ixgbe_mac_82598EB:
bdda1a61 1239 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1240 break;
1241 case ixgbe_mac_82599EB:
b93a2226 1242 case ixgbe_mac_X540:
bdda1a61
AD		 1243 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1244 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1245 break;
1246 default:
bdda1a61
AD		 1247 /* for unknown hardware do not write register */
1248 return;
bd0362dd 1249 }
bdda1a61
AD		 1250
1251 /*
1252 * We can enable relaxed ordering for reads, but not writes when
1253 * DCA is enabled. This is due to a known issue in some chipsets
1254 * which will cause the DCA tag to be cleared.
1255 */
1256 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1257 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1258 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1259
1260 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1261}
1262
bdda1a61
AD		 1263static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1264 struct ixgbe_ring *rx_ring,
33cf09c9 1265 int cpu)
bd0362dd 1266{
33cf09c9 1267 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1268 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1269 u8 reg_idx = rx_ring->reg_idx;
1270
33cf09c9
AD		 1271
1272 switch (hw->mac.type) {
33cf09c9 1273 case ixgbe_mac_82599EB:
b93a2226 1274 case ixgbe_mac_X540:
bdda1a61 1275 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1276 break;
1277 default:
1278 break;
1279 }
bdda1a61
AD		 1280
1281 /*
1282 * We can enable relaxed ordering for reads, but not writes when
1283 * DCA is enabled. This is due to a known issue in some chipsets
1284 * which will cause the DCA tag to be cleared.
1285 */
1286 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1287 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1288
1289 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1290}
1291
1292static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1293{
1294 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1295 struct ixgbe_ring *ring;
bd0362dd 1296 int cpu = get_cpu();
bd0362dd 1297
33cf09c9
AD		 1298 if (q_vector->cpu == cpu)
1299 goto out_no_update;
1300
a557928e 1301 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1302 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1303
a557928e 1304 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1305 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1306
1307 q_vector->cpu = cpu;
1308out_no_update:
bd0362dd
JC		 1309 put_cpu();
1310}
1311
1312static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1313{
1314 int i;
1315
1316 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1317 return;
1318
e35ec126
AD		 1319 /* always use CB2 mode, difference is masked in the CB driver */
1320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1321
49c7ffbe 1322 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1323 adapter->q_vector[i]->cpu = -1;
1324 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1325 }
1326}
1327
1328static int __ixgbe_notify_dca(struct device *dev, void *data)
1329{
c60fbb00 1330 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1331 unsigned long event = *(unsigned long *)data;
1332
2a72c31e 1333 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1334 return 0;
1335
bd0362dd
JC		 1336 switch (event) {
1337 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1338 /* if we're already enabled, don't do it again */
1339 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1340 break;
652f093f 1341 if (dca_add_requester(dev) == 0) {
96b0e0f6 1342 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1343 ixgbe_setup_dca(adapter);
1344 break;
1345 }
1346 /* Fall Through since DCA is disabled. */
1347 case DCA_PROVIDER_REMOVE:
1348 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1349 dca_remove_requester(dev);
1350 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1352 }
1353 break;
1354 }
1355
652f093f 1356 return 0;
bd0362dd 1357}
67a74ee2 1358
bdda1a61 1359#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1360static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1361 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1362 struct sk_buff *skb)
1363{
8a0da21b 1364 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1365 skb_set_hash(skb,
1366 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1367 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1368}
1369
f800326d 1370#ifdef IXGBE_FCOE
ff886dfc
AD		 1371/**
1372 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1373 * @ring: structure containing ring specific data
ff886dfc
AD		 1374 * @rx_desc: advanced rx descriptor
1375 *
1376 * Returns : true if it is FCoE pkt
1377 */
57efd44c 1378static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1379 union ixgbe_adv_rx_desc *rx_desc)
1380{
1381 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1382
57efd44c 1383 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1384 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1385 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1386 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1387}
1388
f800326d 1389#endif /* IXGBE_FCOE */
e59bd25d
AV		 1390/**
1391 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1392 * @ring: structure containing ring specific data
1393 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1394 * @skb: skb currently being received and modified
1395 **/
8a0da21b 1396static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1397 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1398 struct sk_buff *skb)
9a799d71 1399{
3f207800
DS		 1400 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1401 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1402 bool encap_pkt = false;
1403
8a0da21b 1404 skb_checksum_none_assert(skb);
9a799d71 1405
712744be 1406 /* Rx csum disabled */
8a0da21b 1407 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1408 return;
e59bd25d 1409
3f207800
DS		 1410 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1411 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1412 encap_pkt = true;
1413 skb->encapsulation = 1;
1414 skb->ip_summed = CHECKSUM_NONE;
1415 }
1416
e59bd25d 1417 /* if IP and error */
f56e0cb1
AD		 1418 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1419 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1420 ring->rx_stats.csum_err++;
9a799d71
AK		 1421 return;
1422 }
e59bd25d 1423
f56e0cb1 1424 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1425 return;
1426
f56e0cb1 1427 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1428 /*
1429 * 82599 errata, UDP frames with a 0 checksum can be marked as
1430 * checksum errors.
1431 */
8a0da21b
AD		 1432 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1433 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1434 return;
1435
8a0da21b 1436 ring->rx_stats.csum_err++;
e59bd25d
AV		 1437 return;
1438 }
1439
9a799d71 1440 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1441 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1442 if (encap_pkt) {
1443 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1444 return;
1445
1446 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1447 ring->rx_stats.csum_err++;
1448 return;
1449 }
1450 /* If we checked the outer header let the stack know */
1451 skb->csum_level = 1;
1452 }
9a799d71
AK		 1453}
1454
f990b79b
AD		 1455static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1456 struct ixgbe_rx_buffer *bi)
1457{
1458 struct page *page = bi->page;
18cb652a 1459 dma_addr_t dma;
f990b79b 1460
f800326d 1461 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1462 if (likely(page))
f990b79b
AD		 1463 return true;
1464
f800326d 1465 /* alloc new page for storage */
18cb652a
AD		 1466 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1467 if (unlikely(!page)) {
1468 rx_ring->rx_stats.alloc_rx_page_failed++;
1469 return false;
f990b79b
AD		 1470 }
1471
f800326d
AD		 1472 /* map page for use */
1473 dma = dma_map_page(rx_ring->dev, page, 0,
1474 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1475
1476 /*
1477 * if mapping failed free memory back to system since
1478 * there isn't much point in holding memory we can't use
1479 */
1480 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1481 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1482
f990b79b
AD		 1483 rx_ring->rx_stats.alloc_rx_page_failed++;
1484 return false;
1485 }
1486
f800326d 1487 bi->dma = dma;
18cb652a 1488 bi->page = page;
afaa9459 1489 bi->page_offset = 0;
f800326d 1490
f990b79b
AD		 1491 return true;
1492}
1493
9a799d71 1494/**
f990b79b 1495 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1496 * @rx_ring: ring to place buffers on
1497 * @cleaned_count: number of buffers to replace
9a799d71 1498 **/
fc77dc3c 1499void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1500{
9a799d71 1501 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1502 struct ixgbe_rx_buffer *bi;
d5f398ed 1503 u16 i = rx_ring->next_to_use;
9a799d71 1504
f800326d
AD		 1505 /* nothing to do */
1506 if (!cleaned_count)
fc77dc3c
AD		 1507 return;
1508
e4f74028 1509 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1510 bi = &rx_ring->rx_buffer_info[i];
1511 i -= rx_ring->count;
9a799d71 1512
f800326d
AD		 1513 do {
1514 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1515 break;
d5f398ed 1516
f800326d
AD		 1517 /*
1518 * Refresh the desc even if buffer_addrs didn't change
1519 * because each write-back erases this info.
1520 */
1521 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1522
f990b79b
AD		 1523 rx_desc++;
1524 bi++;
9a799d71 1525 i++;
f990b79b 1526 if (unlikely(!i)) {
e4f74028 1527 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1528 bi = rx_ring->rx_buffer_info;
1529 i -= rx_ring->count;
1530 }
1531
18cb652a
AD		 1532 /* clear the status bits for the next_to_use descriptor */
1533 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1534
1535 cleaned_count--;
1536 } while (cleaned_count);
7c6e0a43 1537
f990b79b
AD		 1538 i += rx_ring->count;
1539
ad435ec6
AD		 1540 if (rx_ring->next_to_use != i) {
1541 rx_ring->next_to_use = i;
1542
1543 /* update next to alloc since we have filled the ring */
1544 rx_ring->next_to_alloc = i;
1545
1546 /* Force memory writes to complete before letting h/w
1547 * know there are new descriptors to fetch. (Only
1548 * applicable for weak-ordered memory model archs,
1549 * such as IA-64).
1550 */
1551 wmb();
1552 writel(i, rx_ring->tail);
1553 }
9a799d71
AK		 1554}
1555
1d2024f6
AD		 1556static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1557 struct sk_buff *skb)
1558{
f800326d 1559 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1560
1561 /* set gso_size to avoid messing up TCP MSS */
1562 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1563 IXGBE_CB(skb)->append_cnt);
96be80ab 1564 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1565}
1566
1567static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1568 struct sk_buff *skb)
1569{
1570 /* if append_cnt is 0 then frame is not RSC */
1571 if (!IXGBE_CB(skb)->append_cnt)
1572 return;
1573
1574 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1575 rx_ring->rx_stats.rsc_flush++;
1576
1577 ixgbe_set_rsc_gso_size(rx_ring, skb);
1578
1579 /* gso_size is computed using append_cnt so always clear it last */
1580 IXGBE_CB(skb)->append_cnt = 0;
1581}
1582
8a0da21b
AD		 1583/**
1584 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1585 * @rx_ring: rx descriptor ring packet is being transacted on
1586 * @rx_desc: pointer to the EOP Rx descriptor
1587 * @skb: pointer to current skb being populated
f8212f97 1588 *
8a0da21b
AD		 1589 * This function checks the ring, descriptor, and packet information in
1590 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1591 * other fields within the skb.
f8212f97 1592 **/
8a0da21b
AD		 1593static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1594 union ixgbe_adv_rx_desc *rx_desc,
1595 struct sk_buff *skb)
f8212f97 1596{
43e95f11
JF		 1597 struct net_device *dev = rx_ring->netdev;
1598
8a0da21b
AD		 1599 ixgbe_update_rsc_stats(rx_ring, skb);
1600
1601 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1602
8a0da21b
AD		 1603 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1604
eda183c2
JK		 1605 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1606 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1607
f646968f 1608 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1609 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1610 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1611 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1612 }
1613
8a0da21b 1614 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1615
43e95f11 1616 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1617}
1618
8a0da21b
AD		 1619static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1620 struct sk_buff *skb)
aa80175a 1621{
b4640030 1622 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1623 netif_receive_skb(skb);
8a0da21b 1624 else
856f606e 1625 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1626}
43634e82 1627
f800326d
AD		 1628/**
1629 * ixgbe_is_non_eop - process handling of non-EOP buffers
1630 * @rx_ring: Rx ring being processed
1631 * @rx_desc: Rx descriptor for current buffer
1632 * @skb: Current socket buffer containing buffer in progress
1633 *
1634 * This function updates next to clean. If the buffer is an EOP buffer
1635 * this function exits returning false, otherwise it will place the
1636 * sk_buff in the next buffer to be chained and return true indicating
1637 * that this is in fact a non-EOP buffer.
1638 **/
1639static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1640 union ixgbe_adv_rx_desc *rx_desc,
1641 struct sk_buff *skb)
1642{
1643 u32 ntc = rx_ring->next_to_clean + 1;
1644
1645 /* fetch, update, and store next to clean */
1646 ntc = (ntc < rx_ring->count) ? ntc : 0;
1647 rx_ring->next_to_clean = ntc;
1648
1649 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1650
5a02cbd1
AD		 1651 /* update RSC append count if present */
1652 if (ring_is_rsc_enabled(rx_ring)) {
1653 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1654 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1655
1656 if (unlikely(rsc_enabled)) {
1657 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1658
1659 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1660 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1661
5a02cbd1
AD		 1662 /* update ntc based on RSC value */
1663 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1664 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1665 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1666 }
f800326d
AD		 1667 }
1668
5a02cbd1
AD		 1669 /* if we are the last buffer then there is nothing else to do */
1670 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1671 return false;
1672
f800326d
AD		 1673 /* place skb in next buffer to be received */
1674 rx_ring->rx_buffer_info[ntc].skb = skb;
1675 rx_ring->rx_stats.non_eop_descs++;
1676
1677 return true;
1678}
1679
19861ce2
AD		 1680/**
1681 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1682 * @rx_ring: rx descriptor ring packet is being transacted on
1683 * @skb: pointer to current skb being adjusted
1684 *
1685 * This function is an ixgbe specific version of __pskb_pull_tail. The
1686 * main difference between this version and the original function is that
1687 * this function can make several assumptions about the state of things
1688 * that allow for significant optimizations versus the standard function.
1689 * As a result we can do things like drop a frag and maintain an accurate
1690 * truesize for the skb.
1691 */
1692static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1693 struct sk_buff *skb)
1694{
1695 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1696 unsigned char *va;
1697 unsigned int pull_len;
1698
1699 /*
1700 * it is valid to use page_address instead of kmap since we are
1701 * working with pages allocated out of the lomem pool per
1702 * alloc_page(GFP_ATOMIC)
1703 */
1704 va = skb_frag_address(frag);
1705
1706 /*
1707 * we need the header to contain the greater of either ETH_HLEN or
1708 * 60 bytes if the skb->len is less than 60 for skb_pad.
1709 */
8496e338 1710 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1711
1712 /* align pull length to size of long to optimize memcpy performance */
1713 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1714
1715 /* update all of the pointers */
1716 skb_frag_size_sub(frag, pull_len);
1717 frag->page_offset += pull_len;
1718 skb->data_len -= pull_len;
1719 skb->tail += pull_len;
19861ce2
AD		 1720}
1721
42073d91
AD		 1722/**
1723 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1724 * @rx_ring: rx descriptor ring packet is being transacted on
1725 * @skb: pointer to current skb being updated
1726 *
1727 * This function provides a basic DMA sync up for the first fragment of an
1728 * skb. The reason for doing this is that the first fragment cannot be
1729 * unmapped until we have reached the end of packet descriptor for a buffer
1730 * chain.
1731 */
1732static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1733 struct sk_buff *skb)
1734{
1735 /* if the page was released unmap it, else just sync our portion */
1736 if (unlikely(IXGBE_CB(skb)->page_released)) {
1737 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1738 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1739 IXGBE_CB(skb)->page_released = false;
1740 } else {
1741 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1742
1743 dma_sync_single_range_for_cpu(rx_ring->dev,
1744 IXGBE_CB(skb)->dma,
1745 frag->page_offset,
1746 ixgbe_rx_bufsz(rx_ring),
1747 DMA_FROM_DEVICE);
1748 }
1749 IXGBE_CB(skb)->dma = 0;
1750}
1751
f800326d
AD		 1752/**
1753 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1754 * @rx_ring: rx descriptor ring packet is being transacted on
1755 * @rx_desc: pointer to the EOP Rx descriptor
1756 * @skb: pointer to current skb being fixed
1757 *
1758 * Check for corrupted packet headers caused by senders on the local L2
1759 * embedded NIC switch not setting up their Tx Descriptors right. These
1760 * should be very rare.
1761 *
1762 * Also address the case where we are pulling data in on pages only
1763 * and as such no data is present in the skb header.
1764 *
1765 * In addition if skb is not at least 60 bytes we need to pad it so that
1766 * it is large enough to qualify as a valid Ethernet frame.
1767 *
1768 * Returns true if an error was encountered and skb was freed.
1769 **/
1770static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1771 union ixgbe_adv_rx_desc *rx_desc,
1772 struct sk_buff *skb)
1773{
f800326d 1774 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1775
1776 /* verify that the packet does not have any known errors */
1777 if (unlikely(ixgbe_test_staterr(rx_desc,
1778 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1779 !(netdev->features & NETIF_F_RXALL))) {
1780 dev_kfree_skb_any(skb);
1781 return true;
1782 }
1783
19861ce2 1784 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1785 if (skb_is_nonlinear(skb))
1786 ixgbe_pull_tail(rx_ring, skb);
f800326d 1787
57efd44c
AD		 1788#ifdef IXGBE_FCOE
1789 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1790 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1791 return false;
1792
1793#endif
a94d9e22
AD		 1794 /* if eth_skb_pad returns an error the skb was freed */
1795 if (eth_skb_pad(skb))
1796 return true;
f800326d
AD		 1797
1798 return false;
1799}
1800
f800326d
AD		 1801/**
1802 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1803 * @rx_ring: rx descriptor ring to store buffers on
1804 * @old_buff: donor buffer to have page reused
1805 *
0549ae20 1806 * Synchronizes page for reuse by the adapter
f800326d
AD		 1807 **/
1808static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1809 struct ixgbe_rx_buffer *old_buff)
1810{
1811 struct ixgbe_rx_buffer *new_buff;
1812 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1813
1814 new_buff = &rx_ring->rx_buffer_info[nta];
1815
1816 /* update, and store next to alloc */
1817 nta++;
1818 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1819
1820 /* transfer page from old buffer to new buffer */
18cb652a 1821 *new_buff = *old_buff;
f800326d
AD		 1822
1823 /* sync the buffer for use by the device */
1824 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1825 new_buff->page_offset,
1826 ixgbe_rx_bufsz(rx_ring),
f800326d 1827 DMA_FROM_DEVICE);
f800326d
AD		 1828}
1829
18cb652a
AD		 1830static inline bool ixgbe_page_is_reserved(struct page *page)
1831{
1832 return (page_to_nid(page) != numa_mem_id()) || page->pfmemalloc;
1833}
1834
f800326d
AD		 1835/**
1836 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1837 * @rx_ring: rx descriptor ring to transact packets on
1838 * @rx_buffer: buffer containing page to add
1839 * @rx_desc: descriptor containing length of buffer written by hardware
1840 * @skb: sk_buff to place the data into
1841 *
0549ae20
AD		 1842 * This function will add the data contained in rx_buffer->page to the skb.
1843 * This is done either through a direct copy if the data in the buffer is
1844 * less than the skb header size, otherwise it will just attach the page as
1845 * a frag to the skb.
1846 *
1847 * The function will then update the page offset if necessary and return
1848 * true if the buffer can be reused by the adapter.
f800326d 1849 **/
0549ae20 1850static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1851 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1852 union ixgbe_adv_rx_desc *rx_desc,
1853 struct sk_buff *skb)
f800326d 1854{
0549ae20
AD		 1855 struct page *page = rx_buffer->page;
1856 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1857#if (PAGE_SIZE < 8192)
0549ae20 1858 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1859#else
1860 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1861 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1862 ixgbe_rx_bufsz(rx_ring);
1863#endif
0549ae20 1864
cf3fe7ac
AD		 1865 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1866 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1867
1868 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1869
18cb652a
AD		 1870 /* page is not reserved, we can reuse buffer as-is */
1871 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1872 return true;
1873
1874 /* this page cannot be reused so discard it */
18cb652a 1875 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1876 return false;
1877 }
1878
0549ae20
AD		 1879 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1880 rx_buffer->page_offset, size, truesize);
1881
09816fbe 1882 /* avoid re-using remote pages */
18cb652a 1883 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1884 return false;
1885
1886#if (PAGE_SIZE < 8192)
1887 /* if we are only owner of page we can reuse it */
1888 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1889 return false;
1890
1891 /* flip page offset to other buffer */
1892 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1893#else
1894 /* move offset up to the next cache line */
1895 rx_buffer->page_offset += truesize;
1896
1897 if (rx_buffer->page_offset > last_offset)
1898 return false;
09816fbe 1899#endif
0549ae20 1900
18cb652a
AD		 1901 /* Even if we own the page, we are not allowed to use atomic_set()
1902 * This would break get_page_unless_zero() users.
1903 */
1904 atomic_inc(&page->_count);
1905
0549ae20 1906 return true;
f800326d
AD		 1907}
1908
18806c9e
AD		 1909static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1910 union ixgbe_adv_rx_desc *rx_desc)
1911{
1912 struct ixgbe_rx_buffer *rx_buffer;
1913 struct sk_buff *skb;
1914 struct page *page;
1915
1916 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1917 page = rx_buffer->page;
1918 prefetchw(page);
1919
1920 skb = rx_buffer->skb;
1921
1922 if (likely(!skb)) {
1923 void *page_addr = page_address(page) +
1924 rx_buffer->page_offset;
1925
1926 /* prefetch first cache line of first page */
1927 prefetch(page_addr);
1928#if L1_CACHE_BYTES < 128
1929 prefetch(page_addr + L1_CACHE_BYTES);
1930#endif
1931
1932 /* allocate a skb to store the frags */
67fd893e
AD		 1933 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1934 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1935 if (unlikely(!skb)) {
1936 rx_ring->rx_stats.alloc_rx_buff_failed++;
1937 return NULL;
1938 }
1939
1940 /*
1941 * we will be copying header into skb->data in
1942 * pskb_may_pull so it is in our interest to prefetch
1943 * it now to avoid a possible cache miss
1944 */
1945 prefetchw(skb->data);
1946
1947 /*
1948 * Delay unmapping of the first packet. It carries the
1949 * header information, HW may still access the header
1950 * after the writeback. Only unmap it when EOP is
1951 * reached
1952 */
1953 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1954 goto dma_sync;
1955
1956 IXGBE_CB(skb)->dma = rx_buffer->dma;
1957 } else {
1958 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1959 ixgbe_dma_sync_frag(rx_ring, skb);
1960
1961dma_sync:
1962 /* we are reusing so sync this buffer for CPU use */
1963 dma_sync_single_range_for_cpu(rx_ring->dev,
1964 rx_buffer->dma,
1965 rx_buffer->page_offset,
1966 ixgbe_rx_bufsz(rx_ring),
1967 DMA_FROM_DEVICE);
18cb652a
AD		 1968
1969 rx_buffer->skb = NULL;
18806c9e
AD		 1970 }
1971
1972 /* pull page into skb */
1973 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1974 /* hand second half of page back to the ring */
1975 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1976 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1977 /* the page has been released from the ring */
1978 IXGBE_CB(skb)->page_released = true;
1979 } else {
1980 /* we are not reusing the buffer so unmap it */
1981 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1982 ixgbe_rx_pg_size(rx_ring),
1983 DMA_FROM_DEVICE);
1984 }
1985
1986 /* clear contents of buffer_info */
18806c9e
AD		 1987 rx_buffer->page = NULL;
1988
1989 return skb;
f800326d
AD		 1990}
1991
1992/**
1993 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1994 * @q_vector: structure containing interrupt and ring information
1995 * @rx_ring: rx descriptor ring to transact packets on
1996 * @budget: Total limit on number of packets to process
1997 *
1998 * This function provides a "bounce buffer" approach to Rx interrupt
1999 * processing. The advantage to this is that on systems that have
2000 * expensive overhead for IOMMU access this provides a means of avoiding
2001 * it by maintaining the mapping of the page to the syste.
2002 *
5a85e737 2003 * Returns amount of work completed
f800326d 2004 **/
5a85e737 2005static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2006 struct ixgbe_ring *rx_ring,
f4de00ed 2007 const int budget)
9a799d71 2008{
d2f4fbe2 2009 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2010#ifdef IXGBE_FCOE
f800326d 2011 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2012 int ddp_bytes;
2013 unsigned int mss = 0;
3d8fd385 2014#endif /* IXGBE_FCOE */
f800326d 2015 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2016
fdabfc8a 2017 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2018 union ixgbe_adv_rx_desc *rx_desc;
2019 struct sk_buff *skb;
f800326d
AD		 2020
2021 /* return some buffers to hardware, one at a time is too slow */
2022 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2023 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2024 cleaned_count = 0;
2025 }
2026
18806c9e 2027 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2028
124b74c1 2029 if (!rx_desc->wb.upper.status_error)
f800326d 2030 break;
9a799d71 2031
124b74c1 2032 /* This memory barrier is needed to keep us from reading
f800326d 2033 * any other fields out of the rx_desc until we know the
124b74c1 2034 * descriptor has been written back
f800326d 2035 */
124b74c1 2036 dma_rmb();
9a799d71 2037
18806c9e
AD		 2038 /* retrieve a buffer from the ring */
2039 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2040
18806c9e
AD		 2041 /* exit if we failed to retrieve a buffer */
2042 if (!skb)
2043 break;
9a799d71 2044
9a799d71 2045 cleaned_count++;
f8212f97 2046
f800326d
AD		 2047 /* place incomplete frames back on ring for completion */
2048 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2049 continue;
c267fc16 2050
f800326d
AD		 2051 /* verify the packet layout is correct */
2052 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2053 continue;
9a799d71 2054
d2f4fbe2
AV		 2055 /* probably a little skewed due to removing CRC */
2056 total_rx_bytes += skb->len;
d2f4fbe2 2057
8a0da21b
AD		 2058 /* populate checksum, timestamp, VLAN, and protocol */
2059 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2060
332d4a7d
YZ		 2061#ifdef IXGBE_FCOE
2062 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2063 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2064 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2065 /* include DDPed FCoE data */
2066 if (ddp_bytes > 0) {
2067 if (!mss) {
2068 mss = rx_ring->netdev->mtu -
2069 sizeof(struct fcoe_hdr) -
2070 sizeof(struct fc_frame_header) -
2071 sizeof(struct fcoe_crc_eof);
2072 if (mss > 512)
2073 mss &= ~511;
2074 }
2075 total_rx_bytes += ddp_bytes;
2076 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2077 mss);
2078 }
63d635b2
AD		 2079 if (!ddp_bytes) {
2080 dev_kfree_skb_any(skb);
f800326d 2081 continue;
63d635b2 2082 }
3d8fd385 2083 }
f800326d 2084
332d4a7d 2085#endif /* IXGBE_FCOE */
8b80cda5 2086 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2087 ixgbe_rx_skb(q_vector, skb);
9a799d71 2088
f800326d 2089 /* update budget accounting */
f4de00ed 2090 total_rx_packets++;
fdabfc8a 2091 }
9a799d71 2092
c267fc16
AD		 2093 u64_stats_update_begin(&rx_ring->syncp);
2094 rx_ring->stats.packets += total_rx_packets;
2095 rx_ring->stats.bytes += total_rx_bytes;
2096 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2097 q_vector->rx.total_packets += total_rx_packets;
2098 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2099
5a85e737 2100 return total_rx_packets;
9a799d71
AK		 2101}
2102
e0d1095a 2103#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2104/* must be called with local_bh_disable()d */
2105static int ixgbe_low_latency_recv(struct napi_struct *napi)
2106{
2107 struct ixgbe_q_vector *q_vector =
2108 container_of(napi, struct ixgbe_q_vector, napi);
2109 struct ixgbe_adapter *adapter = q_vector->adapter;
2110 struct ixgbe_ring *ring;
2111 int found = 0;
2112
2113 if (test_bit(__IXGBE_DOWN, &adapter->state))
2114 return LL_FLUSH_FAILED;
2115
2116 if (!ixgbe_qv_lock_poll(q_vector))
2117 return LL_FLUSH_BUSY;
2118
2119 ixgbe_for_each_ring(ring, q_vector->rx) {
2120 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2121#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2122 if (found)
2123 ring->stats.cleaned += found;
2124 else
2125 ring->stats.misses++;
2126#endif
5a85e737
ET		 2127 if (found)
2128 break;
2129 }
2130
2131 ixgbe_qv_unlock_poll(q_vector);
2132
2133 return found;
2134}
e0d1095a 2135#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2136
9a799d71
AK		 2137/**
2138 * ixgbe_configure_msix - Configure MSI-X hardware
2139 * @adapter: board private structure
2140 *
2141 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2142 * interrupts.
2143 **/
2144static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2145{
021230d4 2146 struct ixgbe_q_vector *q_vector;
49c7ffbe 2147 int v_idx;
021230d4 2148 u32 mask;
9a799d71 2149
8e34d1aa
AD		 2150 /* Populate MSIX to EITR Select */
2151 if (adapter->num_vfs > 32) {
2152 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2153 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2154 }
2155
4df10466
JB		 2156 /*
2157 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2158 * corresponding register.
2159 */
49c7ffbe 2160 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2161 struct ixgbe_ring *ring;
7a921c93 2162 q_vector = adapter->q_vector[v_idx];
021230d4 2163
a557928e 2164 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2165 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2166
a557928e 2167 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2168 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2169
fe49f04a 2170 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2171 }
2172
bd508178
AD		 2173 switch (adapter->hw.mac.type) {
2174 case ixgbe_mac_82598EB:
e8e26350 2175 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2176 v_idx);
bd508178
AD		 2177 break;
2178 case ixgbe_mac_82599EB:
b93a2226 2179 case ixgbe_mac_X540:
9a75a1ac
DS		 2180 case ixgbe_mac_X550:
2181 case ixgbe_mac_X550EM_x:
e8e26350 2182 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2183 break;
bd508178
AD		 2184 default:
2185 break;
2186 }
021230d4
AV		 2187 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2188
41fb9248 2189 /* set up to autoclear timer, and the vectors */
021230d4 2190 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2191 mask &= ~(IXGBE_EIMS_OTHER |
2192 IXGBE_EIMS_MAILBOX |
2193 IXGBE_EIMS_LSC);
2194
021230d4 2195 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2196}
2197
f494e8fa
AV		 2198enum latency_range {
2199 lowest_latency = 0,
2200 low_latency = 1,
2201 bulk_latency = 2,
2202 latency_invalid = 255
2203};
2204
2205/**
2206 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2207 * @q_vector: structure containing interrupt and ring information
2208 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2209 *
2210 * Stores a new ITR value based on packets and byte
2211 * counts during the last interrupt. The advantage of per interrupt
2212 * computation is faster updates and more accurate ITR for the current
2213 * traffic pattern. Constants in this function were computed
2214 * based on theoretical maximum wire speed and thresholds were set based
2215 * on testing data as well as attempting to minimize response time
2216 * while increasing bulk throughput.
2217 * this functionality is controlled by the InterruptThrottleRate module
2218 * parameter (see ixgbe_param.c)
2219 **/
bd198058
AD		 2220static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2221 struct ixgbe_ring_container *ring_container)
f494e8fa 2222{
bd198058
AD		 2223 int bytes = ring_container->total_bytes;
2224 int packets = ring_container->total_packets;
2225 u32 timepassed_us;
621bd70e 2226 u64 bytes_perint;
bd198058 2227 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2228
2229 if (packets == 0)
bd198058 2230 return;
f494e8fa
AV		 2231
2232 /* simple throttlerate management
621bd70e
AD		 2233 * 0-10MB/s lowest (100000 ints/s)
2234 * 10-20MB/s low (20000 ints/s)
2235 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2236 */
2237 /* what was last interrupt timeslice? */
d5bf4f67 2238 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2239 if (timepassed_us == 0)
2240 return;
2241
f494e8fa
AV		 2242 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2243
2244 switch (itr_setting) {
2245 case lowest_latency:
621bd70e 2246 if (bytes_perint > 10)
bd198058 2247 itr_setting = low_latency;
f494e8fa
AV		 2248 break;
2249 case low_latency:
621bd70e 2250 if (bytes_perint > 20)
bd198058 2251 itr_setting = bulk_latency;
621bd70e 2252 else if (bytes_perint <= 10)
bd198058 2253 itr_setting = lowest_latency;
f494e8fa
AV		 2254 break;
2255 case bulk_latency:
621bd70e 2256 if (bytes_perint <= 20)
bd198058 2257 itr_setting = low_latency;
f494e8fa
AV		 2258 break;
2259 }
2260
bd198058
AD		 2261 /* clear work counters since we have the values we need */
2262 ring_container->total_bytes = 0;
2263 ring_container->total_packets = 0;
2264
2265 /* write updated itr to ring container */
2266 ring_container->itr = itr_setting;
f494e8fa
AV		 2267}
2268
509ee935
JB		 2269/**
2270 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2271 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2272 *
2273 * This function is made to be called by ethtool and by the driver
2274 * when it needs to update EITR registers at runtime. Hardware
2275 * specific quirks/differences are taken care of here.
2276 */
fe49f04a 2277void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2278{
fe49f04a 2279 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2280 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2281 int v_idx = q_vector->v_idx;
5d967eb7 2282 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2283
bd508178
AD		 2284 switch (adapter->hw.mac.type) {
2285 case ixgbe_mac_82598EB:
509ee935
JB		 2286 /* must write high and low 16 bits to reset counter */
2287 itr_reg |= (itr_reg << 16);
bd508178
AD		 2288 break;
2289 case ixgbe_mac_82599EB:
b93a2226 2290 case ixgbe_mac_X540:
9a75a1ac
DS		 2291 case ixgbe_mac_X550:
2292 case ixgbe_mac_X550EM_x:
509ee935
JB		 2293 /*
2294 * set the WDIS bit to not clear the timer bits and cause an
2295 * immediate assertion of the interrupt
2296 */
2297 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2298 break;
2299 default:
2300 break;
509ee935
JB		 2301 }
2302 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2303}
2304
bd198058 2305static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2306{
d5bf4f67 2307 u32 new_itr = q_vector->itr;
bd198058 2308 u8 current_itr;
f494e8fa 2309
bd198058
AD		 2310 ixgbe_update_itr(q_vector, &q_vector->tx);
2311 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2312
08c8833b 2313 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2314
2315 switch (current_itr) {
2316 /* counts and packets in update_itr are dependent on these numbers */
2317 case lowest_latency:
d5bf4f67 2318 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2319 break;
2320 case low_latency:
d5bf4f67 2321 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2322 break;
2323 case bulk_latency:
d5bf4f67 2324 new_itr = IXGBE_8K_ITR;
f494e8fa 2325 break;
bd198058
AD		 2326 default:
2327 break;
f494e8fa
AV		 2328 }
2329
d5bf4f67 2330 if (new_itr != q_vector->itr) {
fe49f04a 2331 /* do an exponential smoothing */
d5bf4f67
ET		 2332 new_itr = (10 * new_itr * q_vector->itr) /
2333 ((9 * new_itr) + q_vector->itr);
509ee935 2334
bd198058 2335 /* save the algorithm value here */
5d967eb7 2336 q_vector->itr = new_itr;
fe49f04a
AD		 2337
2338 ixgbe_write_eitr(q_vector);
f494e8fa 2339 }
f494e8fa
AV		 2340}
2341
119fc60a 2342/**
de88eeeb 2343 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2344 * @adapter: pointer to adapter
119fc60a 2345 **/
f0f9778d 2346static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2347{
119fc60a
MC		 2348 struct ixgbe_hw *hw = &adapter->hw;
2349 u32 eicr = adapter->interrupt_event;
2350
f0f9778d 2351 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2352 return;
2353
f0f9778d
AD		 2354 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2355 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2356 return;
2357
2358 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2359
7ca647bd 2360 switch (hw->device_id) {
f0f9778d
AD		 2361 case IXGBE_DEV_ID_82599_T3_LOM:
2362 /*
2363 * Since the warning interrupt is for both ports
2364 * we don't have to check if:
2365 * - This interrupt wasn't for our port.
2366 * - We may have missed the interrupt so always have to
2367 * check if we got a LSC
2368 */
2369 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2370 !(eicr & IXGBE_EICR_LSC))
2371 return;
2372
2373 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2374 u32 speed;
f0f9778d 2375 bool link_up = false;
7ca647bd 2376
3d292265 2377 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2378
f0f9778d
AD		 2379 if (link_up)
2380 return;
2381 }
2382
2383 /* Check if this is not due to overtemp */
2384 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2385 return;
2386
2387 break;
7ca647bd
JP		 2388 default:
2389 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2390 return;
7ca647bd 2391 break;
119fc60a 2392 }
7ca647bd
JP		 2393 e_crit(drv,
2394 "Network adapter has been stopped because it has over heated. "
2395 "Restart the computer. If the problem persists, "
2396 "power off the system and replace the adapter\n");
f0f9778d
AD		 2397
2398 adapter->interrupt_event = 0;
119fc60a
MC		 2399}
2400
0befdb3e
JB		 2401static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2402{
2403 struct ixgbe_hw *hw = &adapter->hw;
2404
2405 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2406 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2407 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2408 /* write to clear the interrupt */
2409 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2410 }
2411}
cf8280ee 2412
4f51bf70
JK		 2413static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2414{
2415 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2416 return;
2417
2418 switch (adapter->hw.mac.type) {
2419 case ixgbe_mac_82599EB:
2420 /*
2421 * Need to check link state so complete overtemp check
2422 * on service task
2423 */
2424 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2425 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2426 adapter->interrupt_event = eicr;
2427 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2428 ixgbe_service_event_schedule(adapter);
2429 return;
2430 }
2431 return;
2432 case ixgbe_mac_X540:
2433 if (!(eicr & IXGBE_EICR_TS))
2434 return;
2435 break;
2436 default:
2437 return;
2438 }
2439
2440 e_crit(drv,
2441 "Network adapter has been stopped because it has over heated. "
2442 "Restart the computer. If the problem persists, "
2443 "power off the system and replace the adapter\n");
2444}
2445
e8e26350
PW		 2446static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2447{
2448 struct ixgbe_hw *hw = &adapter->hw;
2449
73c4b7cd
AD		 2450 if (eicr & IXGBE_EICR_GPI_SDP2) {
2451 /* Clear the interrupt */
2452 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2453 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2454 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2455 ixgbe_service_event_schedule(adapter);
2456 }
73c4b7cd
AD		 2457 }
2458
e8e26350
PW		 2459 if (eicr & IXGBE_EICR_GPI_SDP1) {
2460 /* Clear the interrupt */
2461 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2462 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2463 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2464 ixgbe_service_event_schedule(adapter);
2465 }
e8e26350
PW		 2466 }
2467}
2468
cf8280ee
JB		 2469static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2470{
2471 struct ixgbe_hw *hw = &adapter->hw;
2472
2473 adapter->lsc_int++;
2474 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2475 adapter->link_check_timeout = jiffies;
2476 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2477 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2478 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2479 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2480 }
2481}
2482
fe49f04a
AD		 2483static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2484 u64 qmask)
2485{
2486 u32 mask;
bd508178 2487 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2488
bd508178
AD		 2489 switch (hw->mac.type) {
2490 case ixgbe_mac_82598EB:
fe49f04a 2491 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2492 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2493 break;
2494 case ixgbe_mac_82599EB:
b93a2226 2495 case ixgbe_mac_X540:
9a75a1ac
DS		 2496 case ixgbe_mac_X550:
2497 case ixgbe_mac_X550EM_x:
fe49f04a 2498 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2499 if (mask)
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2501 mask = (qmask >> 32);
bd508178
AD		 2502 if (mask)
2503 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2504 break;
2505 default:
2506 break;
fe49f04a
AD		 2507 }
2508 /* skip the flush */
2509}
2510
2511static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2512 u64 qmask)
fe49f04a
AD		 2513{
2514 u32 mask;
bd508178 2515 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2516
bd508178
AD		 2517 switch (hw->mac.type) {
2518 case ixgbe_mac_82598EB:
fe49f04a 2519 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2520 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2521 break;
2522 case ixgbe_mac_82599EB:
b93a2226 2523 case ixgbe_mac_X540:
9a75a1ac
DS		 2524 case ixgbe_mac_X550:
2525 case ixgbe_mac_X550EM_x:
fe49f04a 2526 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2527 if (mask)
2528 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2529 mask = (qmask >> 32);
bd508178
AD		 2530 if (mask)
2531 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2532 break;
2533 default:
2534 break;
fe49f04a
AD		 2535 }
2536 /* skip the flush */
2537}
2538
021230d4 2539/**
2c4af694
AD		 2540 * ixgbe_irq_enable - Enable default interrupt generation settings
2541 * @adapter: board private structure
021230d4 2542 **/
2c4af694
AD		 2543static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2544 bool flush)
9a799d71 2545{
2c4af694 2546 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2547
2c4af694
AD		 2548 /* don't reenable LSC while waiting for link */
2549 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2550 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2551
2c4af694 2552 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2553 switch (adapter->hw.mac.type) {
2554 case ixgbe_mac_82599EB:
2555 mask |= IXGBE_EIMS_GPI_SDP0;
2556 break;
2557 case ixgbe_mac_X540:
9a75a1ac
DS		 2558 case ixgbe_mac_X550:
2559 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2560 mask |= IXGBE_EIMS_TS;
2561 break;
2562 default:
2563 break;
2564 }
2c4af694
AD		 2565 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2566 mask |= IXGBE_EIMS_GPI_SDP1;
2567 switch (adapter->hw.mac.type) {
2568 case ixgbe_mac_82599EB:
2c4af694
AD		 2569 mask |= IXGBE_EIMS_GPI_SDP1;
2570 mask |= IXGBE_EIMS_GPI_SDP2;
9a75a1ac 2571 /* fall through */
858bc081 2572 case ixgbe_mac_X540:
9a75a1ac
DS		 2573 case ixgbe_mac_X550:
2574 case ixgbe_mac_X550EM_x:
858bc081 2575 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2576 mask |= IXGBE_EIMS_MAILBOX;
2577 break;
2578 default:
2579 break;
9a799d71 2580 }
db0677fa 2581
2c4af694
AD		 2582 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2583 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2584 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2585
2c4af694
AD		 2586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2587 if (queues)
2588 ixgbe_irq_enable_queues(adapter, ~0);
2589 if (flush)
2590 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2591}
2592
2c4af694 2593static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2594{
a65151ba 2595 struct ixgbe_adapter *adapter = data;
9a799d71 2596 struct ixgbe_hw *hw = &adapter->hw;
54037505 2597 u32 eicr;
91281fd3 2598
54037505
DS		 2599 /*
2600 * Workaround for Silicon errata. Use clear-by-write instead
2601 * of clear-by-read. Reading with EICS will return the
2602 * interrupt causes without clearing, which later be done
2603 * with the write to EICR.
2604 */
2605 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2606
2607 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2608 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2609 * the bits are high when ixgbe_msix_other is called. There is a race
2610 * condition otherwise which results in possible performance loss
2611 * especially if the ixgbe_msix_other interrupt is triggering
2612 * consistently (as it would when PPS is turned on for the X540 device)
2613 */
2614 eicr &= 0xFFFF0000;
2615
54037505 2616 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2617
cf8280ee
JB		 2618 if (eicr & IXGBE_EICR_LSC)
2619 ixgbe_check_lsc(adapter);
f0848276 2620
1cdd1ec8
GR		 2621 if (eicr & IXGBE_EICR_MAILBOX)
2622 ixgbe_msg_task(adapter);
efe3d3c8 2623
bd508178
AD		 2624 switch (hw->mac.type) {
2625 case ixgbe_mac_82599EB:
b93a2226 2626 case ixgbe_mac_X540:
9a75a1ac
DS		 2627 case ixgbe_mac_X550:
2628 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2629 if (eicr & IXGBE_EICR_ECC) {
2630 e_info(link, "Received ECC Err, initiating reset\n");
2631 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2632 ixgbe_service_event_schedule(adapter);
2633 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2634 }
c4cf55e5
PWJ		 2635 /* Handle Flow Director Full threshold interrupt */
2636 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2637 int reinit_count = 0;
c4cf55e5 2638 int i;
c4cf55e5 2639 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2640 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2641 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2642 &ring->state))
2643 reinit_count++;
2644 }
2645 if (reinit_count) {
2646 /* no more flow director interrupts until after init */
2647 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2648 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2649 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2650 }
2651 }
f0f9778d 2652 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2653 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2654 break;
2655 default:
2656 break;
c4cf55e5 2657 }
f0848276 2658
bd508178 2659 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2660
db0677fa
JK		 2661 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2662 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2663
7086400d 2664 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2665 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2666 ixgbe_irq_enable(adapter, false, false);
f0848276 2667
9a799d71 2668 return IRQ_HANDLED;
f0848276 2669}
91281fd3 2670
4ff7fb12 2671static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2672{
021230d4 2673 struct ixgbe_q_vector *q_vector = data;
91281fd3 2674
9b471446 2675 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2676
4ff7fb12
AD		 2677 if (q_vector->rx.ring || q_vector->tx.ring)
2678 napi_schedule(&q_vector->napi);
91281fd3 2679
9a799d71 2680 return IRQ_HANDLED;
91281fd3
AD		 2681}
2682
eb01b975
AD		 2683/**
2684 * ixgbe_poll - NAPI Rx polling callback
2685 * @napi: structure for representing this polling device
2686 * @budget: how many packets driver is allowed to clean
2687 *
2688 * This function is used for legacy and MSI, NAPI mode
2689 **/
8af3c33f 2690int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2691{
2692 struct ixgbe_q_vector *q_vector =
2693 container_of(napi, struct ixgbe_q_vector, napi);
2694 struct ixgbe_adapter *adapter = q_vector->adapter;
2695 struct ixgbe_ring *ring;
2696 int per_ring_budget;
2697 bool clean_complete = true;
2698
2699#ifdef CONFIG_IXGBE_DCA
2700 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2701 ixgbe_update_dca(q_vector);
2702#endif
2703
2704 ixgbe_for_each_ring(ring, q_vector->tx)
2705 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2706
5a85e737
ET		 2707 if (!ixgbe_qv_lock_napi(q_vector))
2708 return budget;
2709
eb01b975
AD		 2710 /* attempt to distribute budget to each queue fairly, but don't allow
2711 * the budget to go below 1 because we'll exit polling */
2712 if (q_vector->rx.count > 1)
2713 per_ring_budget = max(budget/q_vector->rx.count, 1);
2714 else
2715 per_ring_budget = budget;
2716
2717 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2718 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2719 per_ring_budget) < per_ring_budget);
eb01b975 2720
5a85e737 2721 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2722 /* If all work not completed, return budget and keep polling */
2723 if (!clean_complete)
2724 return budget;
2725
2726 /* all work done, exit the polling mode */
2727 napi_complete(napi);
2728 if (adapter->rx_itr_setting & 1)
2729 ixgbe_set_itr(q_vector);
2730 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2731 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2732
2733 return 0;
2734}
2735
021230d4
AV		 2736/**
2737 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2738 * @adapter: board private structure
2739 *
2740 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2741 * interrupts from the kernel.
2742 **/
2743static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2744{
2745 struct net_device *netdev = adapter->netdev;
207867f5 2746 int vector, err;
e8e9f696 2747 int ri = 0, ti = 0;
021230d4 2748
49c7ffbe 2749 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2750 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2751 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2752
4ff7fb12 2753 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2754 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2755 "%s-%s-%d", netdev->name, "TxRx", ri++);
2756 ti++;
2757 } else if (q_vector->rx.ring) {
9fe93afd 2758 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2759 "%s-%s-%d", netdev->name, "rx", ri++);
2760 } else if (q_vector->tx.ring) {
9fe93afd 2761 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2762 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2763 } else {
2764 /* skip this unused q_vector */
2765 continue;
32aa77a4 2766 }
207867f5
AD		 2767 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2768 q_vector->name, q_vector);
9a799d71 2769 if (err) {
396e799c 2770 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2771 "Error: %d\n", err);
021230d4 2772 goto free_queue_irqs;
9a799d71 2773 }
207867f5
AD		 2774 /* If Flow Director is enabled, set interrupt affinity */
2775 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2776 /* assign the mask for this irq */
2777 irq_set_affinity_hint(entry->vector,
de88eeeb 2778 &q_vector->affinity_mask);
207867f5 2779 }
9a799d71
AK		 2780 }
2781
021230d4 2782 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2783 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2784 if (err) {
de88eeeb 2785 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2786 goto free_queue_irqs;
9a799d71
AK		 2787 }
2788
9a799d71
AK		 2789 return 0;
2790
021230d4 2791free_queue_irqs:
207867f5
AD		 2792 while (vector) {
2793 vector--;
2794 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2795 NULL);
2796 free_irq(adapter->msix_entries[vector].vector,
2797 adapter->q_vector[vector]);
2798 }
021230d4
AV		 2799 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2800 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2801 kfree(adapter->msix_entries);
2802 adapter->msix_entries = NULL;
9a799d71
AK		 2803 return err;
2804}
2805
2806/**
021230d4 2807 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2808 * @irq: interrupt number
2809 * @data: pointer to a network interface device structure
9a799d71
AK		 2810 **/
2811static irqreturn_t ixgbe_intr(int irq, void *data)
2812{
a65151ba 2813 struct ixgbe_adapter *adapter = data;
9a799d71 2814 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2815 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2816 u32 eicr;
2817
54037505 2818 /*
24ddd967 2819 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2820 * before the read of EICR.
2821 */
2822 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2823
021230d4 2824 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2825 * therefore no explicit interrupt disable is necessary */
021230d4 2826 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2827 if (!eicr) {
6af3b9eb
ET		 2828 /*
2829 * shared interrupt alert!
f47cf66e 2830 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2831 * have disabled interrupts due to EIAM
2832 * finish the workaround of silicon errata on 82598. Unmask
2833 * the interrupt that we masked before the EICR read.
2834 */
2835 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2836 ixgbe_irq_enable(adapter, true, true);
9a799d71 2837 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2838 }
9a799d71 2839
cf8280ee
JB		 2840 if (eicr & IXGBE_EICR_LSC)
2841 ixgbe_check_lsc(adapter);
021230d4 2842
bd508178
AD		 2843 switch (hw->mac.type) {
2844 case ixgbe_mac_82599EB:
e8e26350 2845 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2846 /* Fall through */
2847 case ixgbe_mac_X540:
9a75a1ac
DS		 2848 case ixgbe_mac_X550:
2849 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2850 if (eicr & IXGBE_EICR_ECC) {
2851 e_info(link, "Received ECC Err, initiating reset\n");
2852 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2853 ixgbe_service_event_schedule(adapter);
2854 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2855 }
4f51bf70 2856 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2857 break;
2858 default:
2859 break;
2860 }
e8e26350 2861
0befdb3e 2862 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2863 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2864 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2865
b9f6ed2b
AD		 2866 /* would disable interrupts here but EIAM disabled it */
2867 napi_schedule(&q_vector->napi);
9a799d71 2868
6af3b9eb
ET		 2869 /*
2870 * re-enable link(maybe) and non-queue interrupts, no flush.
2871 * ixgbe_poll will re-enable the queue interrupts
2872 */
6af3b9eb
ET		 2873 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2874 ixgbe_irq_enable(adapter, false, false);
2875
9a799d71
AK		 2876 return IRQ_HANDLED;
2877}
2878
2879/**
2880 * ixgbe_request_irq - initialize interrupts
2881 * @adapter: board private structure
2882 *
2883 * Attempts to configure interrupts using the best available
2884 * capabilities of the hardware and kernel.
2885 **/
021230d4 2886static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2887{
2888 struct net_device *netdev = adapter->netdev;
021230d4 2889 int err;
9a799d71 2890
4cc6df29 2891 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2892 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2893 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2894 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2895 netdev->name, adapter);
4cc6df29 2896 else
a0607fd3 2897 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2898 netdev->name, adapter);
9a799d71 2899
de88eeeb 2900 if (err)
396e799c 2901 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2902
9a799d71
AK		 2903 return err;
2904}
2905
2906static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2907{
49c7ffbe 2908 int vector;
9a799d71 2909
49c7ffbe
AD		 2910 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2911 free_irq(adapter->pdev->irq, adapter);
2912 return;
2913 }
4cc6df29 2914
49c7ffbe
AD		 2915 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2916 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2917 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2918
49c7ffbe
AD		 2919 /* free only the irqs that were actually requested */
2920 if (!q_vector->rx.ring && !q_vector->tx.ring)
2921 continue;
207867f5 2922
49c7ffbe
AD		 2923 /* clear the affinity_mask in the IRQ descriptor */
2924 irq_set_affinity_hint(entry->vector, NULL);
2925
2926 free_irq(entry->vector, q_vector);
9a799d71 2927 }
49c7ffbe
AD		 2928
2929 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2930}
2931
22d5a71b
JB		 2932/**
2933 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2934 * @adapter: board private structure
2935 **/
2936static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2937{
bd508178
AD		 2938 switch (adapter->hw.mac.type) {
2939 case ixgbe_mac_82598EB:
835462fc 2940 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2941 break;
2942 case ixgbe_mac_82599EB:
b93a2226 2943 case ixgbe_mac_X540:
9a75a1ac
DS		 2944 case ixgbe_mac_X550:
2945 case ixgbe_mac_X550EM_x:
835462fc
NS		 2946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2947 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2948 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2949 break;
2950 default:
2951 break;
22d5a71b
JB		 2952 }
2953 IXGBE_WRITE_FLUSH(&adapter->hw);
2954 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2955 int vector;
2956
2957 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2958 synchronize_irq(adapter->msix_entries[vector].vector);
2959
2960 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2961 } else {
2962 synchronize_irq(adapter->pdev->irq);
2963 }
2964}
2965
9a799d71
AK		 2966/**
2967 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2968 *
2969 **/
2970static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2971{
d5bf4f67 2972 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2973
d5bf4f67 2974 ixgbe_write_eitr(q_vector);
9a799d71 2975
e8e26350
PW		 2976 ixgbe_set_ivar(adapter, 0, 0, 0);
2977 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2978
396e799c 2979 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2980}
2981
43e69bf0
AD		 2982/**
2983 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2984 * @adapter: board private structure
2985 * @ring: structure containing ring specific data
2986 *
2987 * Configure the Tx descriptor ring after a reset.
2988 **/
84418e3b
AD		 2989void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2990 struct ixgbe_ring *ring)
43e69bf0
AD		 2991{
2992 struct ixgbe_hw *hw = &adapter->hw;
2993 u64 tdba = ring->dma;
2f1860b8 2994 int wait_loop = 10;
b88c6de2 2995 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2996 u8 reg_idx = ring->reg_idx;
43e69bf0 2997
2f1860b8 2998 /* disable queue to avoid issues while updating state */
b88c6de2 2999 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3000 IXGBE_WRITE_FLUSH(hw);
3001
43e69bf0 3002 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3003 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3004 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3005 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3006 ring->count * sizeof(union ixgbe_adv_tx_desc));
3007 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3008 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3009 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3010
b88c6de2
AD		 3011 /*
3012 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3013 * higher than 1 when:
3014 * - ITR is 0 as it could cause false TX hangs
3015 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3016 *
3017 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3018 * to or less than the number of on chip descriptors, which is
3019 * currently 40.
3020 */
67da097e 3021 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3022 txdctl |= (1 << 16); /* WTHRESH = 1 */
3023 else
3024 txdctl |= (8 << 16); /* WTHRESH = 8 */
3025
e954b374
AD		 3026 /*
3027 * Setting PTHRESH to 32 both improves performance
3028 * and avoids a TX hang with DFP enabled
3029 */
b88c6de2
AD		 3030 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3031 32; /* PTHRESH = 32 */
2f1860b8
AD		 3032
3033 /* reinitialize flowdirector state */
39cb681b 3034 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3035 ring->atr_sample_rate = adapter->atr_sample_rate;
3036 ring->atr_count = 0;
3037 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3038 } else {
3039 ring->atr_sample_rate = 0;
3040 }
2f1860b8 3041
fd786b7b
AD		 3042 /* initialize XPS */
3043 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3044 struct ixgbe_q_vector *q_vector = ring->q_vector;
3045
3046 if (q_vector)
2a47fa45 3047 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3048 &q_vector->affinity_mask,
3049 ring->queue_index);
3050 }
3051
c84d324c
JF		 3052 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3053
2f1860b8 3054 /* enable queue */
2f1860b8
AD		 3055 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3056
3057 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3058 if (hw->mac.type == ixgbe_mac_82598EB &&
3059 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3060 return;
3061
3062 /* poll to verify queue is enabled */
3063 do {
032b4325 3064 usleep_range(1000, 2000);
2f1860b8
AD		 3065 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3066 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3067 if (!wait_loop)
3068 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3069}
3070
120ff942
AD		 3071static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3072{
3073 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3074 u32 rttdcs, mtqc;
8b1c0b24 3075 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3076
3077 if (hw->mac.type == ixgbe_mac_82598EB)
3078 return;
3079
3080 /* disable the arbiter while setting MTQC */
3081 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3082 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3083 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3084
3085 /* set transmit pool layout */
671c0adb
AD		 3086 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3087 mtqc = IXGBE_MTQC_VT_ENA;
3088 if (tcs > 4)
3089 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3090 else if (tcs > 1)
3091 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3092 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3093 mtqc |= IXGBE_MTQC_32VF;
3094 else
3095 mtqc |= IXGBE_MTQC_64VF;
3096 } else {
3097 if (tcs > 4)
3098 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3099 else if (tcs > 1)
3100 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3101 else
671c0adb
AD		 3102 mtqc = IXGBE_MTQC_64Q_1PB;
3103 }
120ff942 3104
671c0adb 3105 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3106
671c0adb
AD		 3107 /* Enable Security TX Buffer IFG for multiple pb */
3108 if (tcs) {
3109 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3110 sectx |= IXGBE_SECTX_DCB;
3111 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3112 }
3113
3114 /* re-enable the arbiter */
3115 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3116 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3117}
3118
9a799d71 3119/**
3a581073 3120 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3121 * @adapter: board private structure
3122 *
3123 * Configure the Tx unit of the MAC after a reset.
3124 **/
3125static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3126{
2f1860b8
AD		 3127 struct ixgbe_hw *hw = &adapter->hw;
3128 u32 dmatxctl;
43e69bf0 3129 u32 i;
9a799d71 3130
2f1860b8
AD		 3131 ixgbe_setup_mtqc(adapter);
3132
3133 if (hw->mac.type != ixgbe_mac_82598EB) {
3134 /* DMATXCTL.EN must be before Tx queues are enabled */
3135 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3136 dmatxctl |= IXGBE_DMATXCTL_TE;
3137 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3138 }
3139
9a799d71 3140 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3141 for (i = 0; i < adapter->num_tx_queues; i++)
3142 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3143}
3144
3ebe8fde
AD		 3145static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3146 struct ixgbe_ring *ring)
3147{
3148 struct ixgbe_hw *hw = &adapter->hw;
3149 u8 reg_idx = ring->reg_idx;
3150 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3151
3152 srrctl |= IXGBE_SRRCTL_DROP_EN;
3153
3154 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3155}
3156
3157static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3158 struct ixgbe_ring *ring)
3159{
3160 struct ixgbe_hw *hw = &adapter->hw;
3161 u8 reg_idx = ring->reg_idx;
3162 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3163
3164 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3165
3166 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3167}
3168
3169#ifdef CONFIG_IXGBE_DCB
3170void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3171#else
3172static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3173#endif
3174{
3175 int i;
3176 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3177
3178 if (adapter->ixgbe_ieee_pfc)
3179 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3180
3181 /*
3182 * We should set the drop enable bit if:
3183 * SR-IOV is enabled
3184 * or
3185 * Number of Rx queues > 1 and flow control is disabled
3186 *
3187 * This allows us to avoid head of line blocking for security
3188 * and performance reasons.
3189 */
3190 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3191 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3192 for (i = 0; i < adapter->num_rx_queues; i++)
3193 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3194 } else {
3195 for (i = 0; i < adapter->num_rx_queues; i++)
3196 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3197 }
3198}
3199
e8e26350 3200#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3201
a6616b42 3202static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3203 struct ixgbe_ring *rx_ring)
cc41ac7c 3204{
45e9baa5 3205 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3206 u32 srrctl;
bf29ee6c 3207 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3208
45e9baa5
AD		 3209 if (hw->mac.type == ixgbe_mac_82598EB) {
3210 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3211
45e9baa5
AD		 3212 /*
3213 * if VMDq is not active we must program one srrctl register
3214 * per RSS queue since we have enabled RDRXCTL.MVMEN
3215 */
3216 reg_idx &= mask;
3217 }
cc41ac7c 3218
45e9baa5
AD		 3219 /* configure header buffer length, needed for RSC */
3220 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3221
45e9baa5 3222 /* configure the packet buffer length */
f800326d 3223 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3224
3225 /* configure descriptor type */
f800326d 3226 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3227
45e9baa5 3228 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3229}
9a799d71 3230
dfaf891d
VZ		 3231/**
3232 * Return a number of entries in the RSS indirection table
3233 *
3234 * @adapter: device handle
3235 *
3236 * - 82598/82599/X540: 128
3237 * - X550(non-SRIOV mode): 512
3238 * - X550(SRIOV mode): 64
3239 */
7f276efb 3240u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3241{
3242 if (adapter->hw.mac.type < ixgbe_mac_X550)
3243 return 128;
3244 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3245 return 64;
3246 else
3247 return 512;
3248}
3249
3250/**
3251 * Write the RETA table to HW
3252 *
3253 * @adapter: device handle
3254 *
3255 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3256 */
3257static void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3258{
dfaf891d 3259 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3260 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3261 u32 reta = 0;
dfaf891d
VZ		 3262 u32 indices_multi;
3263 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3264
0f9b232b 3265 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3266 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3267 * indices.
3268 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3269 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3270 */
3271 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3272 indices_multi = 0x11;
3273 else
3274 indices_multi = 0x1;
3275
dfaf891d
VZ		 3276 /* Write redirection table to HW */
3277 for (i = 0; i < reta_entries; i++) {
3278 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3279 if ((i & 3) == 3) {
3280 if (i < 128)
3281 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3282 else
3283 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3284 reta);
dfaf891d 3285 reta = 0;
0f9b232b
DS		 3286 }
3287 }
3288}
3289
dfaf891d
VZ		 3290/**
3291 * Write the RETA table to HW (for x550 devices in SRIOV mode)
3292 *
3293 * @adapter: device handle
3294 *
3295 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3296 */
3297static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3298{
dfaf891d 3299 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3300 struct ixgbe_hw *hw = &adapter->hw;
3301 u32 vfreta = 0;
dfaf891d
VZ		 3302 unsigned int pf_pool = adapter->num_vfs;
3303
3304 /* Write redirection table to HW */
3305 for (i = 0; i < reta_entries; i++) {
3306 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3307 if ((i & 3) == 3) {
3308 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3309 vfreta);
3310 vfreta = 0;
3311 }
3312 }
3313}
3314
3315static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3316{
3317 struct ixgbe_hw *hw = &adapter->hw;
3318 u32 i, j;
3319 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3320 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3321
3322 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3323 * make full use of any rings they may have. We will use the
3324 * PSRTYPE register to control how many rings we use within the PF.
3325 */
3326 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3327 rss_i = 2;
3328
3329 /* Fill out hash function seeds */
3330 for (i = 0; i < 10; i++)
3331 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3332
3333 /* Fill out redirection table */
3334 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3335
3336 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3337 if (j == rss_i)
3338 j = 0;
3339
3340 adapter->rss_indir_tbl[i] = j;
3341 }
3342
3343 ixgbe_store_reta(adapter);
3344}
3345
3346static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3347{
3348 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3349 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3350 unsigned int pf_pool = adapter->num_vfs;
3351 int i, j;
3352
3353 /* Fill out hash function seeds */
3354 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3355 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3356 adapter->rss_key[i]);
0f9b232b
DS		 3357
3358 /* Fill out the redirection table */
3359 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3360 if (j == rss_i)
05abb126 3361 j = 0;
dfaf891d
VZ		 3362
3363 adapter->rss_indir_tbl[i] = j;
05abb126 3364 }
dfaf891d
VZ		 3365
3366 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3367}
3368
3369static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3370{
3371 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3372 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3373 u32 rxcsum;
0cefafad 3374
05abb126
AD		 3375 /* Disable indicating checksum in descriptor, enables RSS hash */
3376 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3377 rxcsum |= IXGBE_RXCSUM_PCSD;
3378 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3379
671c0adb 3380 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3381 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3382 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3383 } else {
671c0adb
AD		 3384 u8 tcs = netdev_get_num_tc(adapter->netdev);
3385
3386 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3387 if (tcs > 4)
3388 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3389 else if (tcs > 1)
3390 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3391 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3392 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3393 else
671c0adb
AD		 3394 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3395 } else {
3396 if (tcs > 4)
8b1c0b24 3397 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3398 else if (tcs > 1)
3399 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3400 else
3401 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3402 }
0cefafad
JB		 3403 }
3404
05abb126 3405 /* Perform hash on these packet types */
d1b849b9
DS		 3406 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3407 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3408 IXGBE_MRQC_RSS_FIELD_IPV6 |
3409 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3410
ef6afc0c 3411 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3412 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3413 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3414 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3415
dfaf891d 3416 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3417 if ((hw->mac.type >= ixgbe_mac_X550) &&
3418 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3419 unsigned int pf_pool = adapter->num_vfs;
3420
3421 /* Enable VF RSS mode */
3422 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3423 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3424
3425 /* Setup RSS through the VF registers */
dfaf891d 3426 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3427 vfmrqc = IXGBE_MRQC_RSSEN;
3428 vfmrqc |= rss_field;
3429 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3430 } else {
dfaf891d 3431 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3432 mrqc |= rss_field;
3433 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3434 }
0cefafad
JB		 3435}
3436
bb5a9ad2
NS		 3437/**
3438 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3439 * @adapter: address of board private structure
3440 * @index: index of ring to set
bb5a9ad2 3441 **/
082757af 3442static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3443 struct ixgbe_ring *ring)
bb5a9ad2 3444{
bb5a9ad2 3445 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3446 u32 rscctrl;
bf29ee6c 3447 u8 reg_idx = ring->reg_idx;
7367096a 3448
7d637bcc 3449 if (!ring_is_rsc_enabled(ring))
7367096a 3450 return;
bb5a9ad2 3451
7367096a 3452 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3453 rscctrl |= IXGBE_RSCCTL_RSCEN;
3454 /*
3455 * we must limit the number of descriptors so that the
3456 * total size of max desc * buf_len is not greater
642c680e 3457 * than 65536
bb5a9ad2 3458 */
f800326d 3459 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3460 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3461}
3462
9e10e045
AD		 3463#define IXGBE_MAX_RX_DESC_POLL 10
3464static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3465 struct ixgbe_ring *ring)
3466{
3467 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3468 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3469 u32 rxdctl;
bf29ee6c 3470 u8 reg_idx = ring->reg_idx;
9e10e045 3471
b0483c8f
MR		 3472 if (ixgbe_removed(hw->hw_addr))
3473 return;
9e10e045
AD		 3474 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3475 if (hw->mac.type == ixgbe_mac_82598EB &&
3476 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3477 return;
3478
3479 do {
032b4325 3480 usleep_range(1000, 2000);
9e10e045
AD		 3481 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3482 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3483
3484 if (!wait_loop) {
3485 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3486 "the polling period\n", reg_idx);
3487 }
3488}
3489
2d39d576
YZ		 3490void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3491 struct ixgbe_ring *ring)
3492{
3493 struct ixgbe_hw *hw = &adapter->hw;
3494 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3495 u32 rxdctl;
3496 u8 reg_idx = ring->reg_idx;
3497
b0483c8f
MR		 3498 if (ixgbe_removed(hw->hw_addr))
3499 return;
2d39d576
YZ		 3500 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3501 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3502
3503 /* write value back with RXDCTL.ENABLE bit cleared */
3504 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3505
3506 if (hw->mac.type == ixgbe_mac_82598EB &&
3507 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3508 return;
3509
3510 /* the hardware may take up to 100us to really disable the rx queue */
3511 do {
3512 udelay(10);
3513 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3514 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3515
3516 if (!wait_loop) {
3517 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3518 "the polling period\n", reg_idx);
3519 }
3520}
3521
84418e3b
AD		 3522void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3523 struct ixgbe_ring *ring)
acd37177
AD		 3524{
3525 struct ixgbe_hw *hw = &adapter->hw;
3526 u64 rdba = ring->dma;
9e10e045 3527 u32 rxdctl;
bf29ee6c 3528 u8 reg_idx = ring->reg_idx;
acd37177 3529
9e10e045
AD		 3530 /* disable queue to avoid issues while updating state */
3531 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3532 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3533
acd37177
AD		 3534 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3535 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3536 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3537 ring->count * sizeof(union ixgbe_adv_rx_desc));
3538 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3539 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3540 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3541
3542 ixgbe_configure_srrctl(adapter, ring);
3543 ixgbe_configure_rscctl(adapter, ring);
3544
3545 if (hw->mac.type == ixgbe_mac_82598EB) {
3546 /*
3547 * enable cache line friendly hardware writes:
3548 * PTHRESH=32 descriptors (half the internal cache),
3549 * this also removes ugly rx_no_buffer_count increment
3550 * HTHRESH=4 descriptors (to minimize latency on fetch)
3551 * WTHRESH=8 burst writeback up to two cache lines
3552 */
3553 rxdctl &= ~0x3FFFFF;
3554 rxdctl |= 0x080420;
3555 }
3556
3557 /* enable receive descriptor ring */
3558 rxdctl |= IXGBE_RXDCTL_ENABLE;
3559 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3560
3561 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3562 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3563}
3564
48654521
AD		 3565static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3566{
3567 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3568 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3569 u16 pool;
48654521
AD		 3570
3571 /* PSRTYPE must be initialized in non 82598 adapters */
3572 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3573 IXGBE_PSRTYPE_UDPHDR |
3574 IXGBE_PSRTYPE_IPV4HDR |
48654521 3575 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3576 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3577
3578 if (hw->mac.type == ixgbe_mac_82598EB)
3579 return;
3580
fbe7ca7f
AD		 3581 if (rss_i > 3)
3582 psrtype |= 2 << 29;
3583 else if (rss_i > 1)
3584 psrtype |= 1 << 29;
48654521 3585
2a47fa45
JF		 3586 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3587 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3588}
3589
f5b4a52e
AD		 3590static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3591{
3592 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3593 u32 reg_offset, vf_shift;
435b19f6 3594 u32 gcr_ext, vmdctl;
de4c7f65 3595 int i;
f5b4a52e
AD		 3596
3597 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3598 return;
3599
3600 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3601 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3602 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3603 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3604 vmdctl |= IXGBE_VT_CTL_REPLEN;
3605 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3606
1d9c0bfd
AD		 3607 vf_shift = VMDQ_P(0) % 32;
3608 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3609
3610 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3611 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3612 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3613 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3614 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3615 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3616 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3617
3618 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3619 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3620
3621 /*
3622 * Set up VF register offsets for selected VT Mode,
3623 * i.e. 32 or 64 VFs for SR-IOV
3624 */
73079ea0
AD		 3625 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3626 case IXGBE_82599_VMDQ_8Q_MASK:
3627 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3628 break;
3629 case IXGBE_82599_VMDQ_4Q_MASK:
3630 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3631 break;
3632 default:
3633 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3634 break;
3635 }
3636
f5b4a52e
AD		 3637 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3638
435b19f6 3639
a985b6c3 3640 /* Enable MAC Anti-Spoofing */
435b19f6 3641 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3642 adapter->num_vfs);
5b7f000f
DS		 3643
3644 /* Ensure LLDP is set for Ethertype Antispoofing if we will be
3645 * calling set_ethertype_anti_spoofing for each VF in loop below
3646 */
3647 if (hw->mac.ops.set_ethertype_anti_spoofing)
3648 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3649 (IXGBE_ETQF_FILTER_EN | /* enable filter */
3650 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */
3651 IXGBE_ETH_P_LLDP)); /* LLDP eth type */
3652
de4c7f65
GR		 3653 /* For VFs that have spoof checking turned off */
3654 for (i = 0; i < adapter->num_vfs; i++) {
3655 if (!adapter->vfinfo[i].spoofchk_enabled)
3656 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3657
3658 /* enable ethertype anti spoofing if hw supports it */
3659 if (hw->mac.ops.set_ethertype_anti_spoofing)
3660 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
de4c7f65 3661 }
f5b4a52e
AD		 3662}
3663
477de6ed 3664static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3665{
9a799d71
AK		 3666 struct ixgbe_hw *hw = &adapter->hw;
3667 struct net_device *netdev = adapter->netdev;
3668 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3669 struct ixgbe_ring *rx_ring;
3670 int i;
3671 u32 mhadd, hlreg0;
48654521 3672
63f39bd1 3673#ifdef IXGBE_FCOE
477de6ed
AD		 3674 /* adjust max frame to be able to do baby jumbo for FCoE */
3675 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3676 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3677 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3678
477de6ed 3679#endif /* IXGBE_FCOE */
872844dd
AD		 3680
3681 /* adjust max frame to be at least the size of a standard frame */
3682 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3683 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3684
477de6ed
AD		 3685 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3686 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3687 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3688 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3689
3690 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3691 }
3692
3693 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3694 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3695 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3696 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3697
0cefafad
JB		 3698 /*
3699 * Setup the HW Rx Head and Tail Descriptor Pointers and
3700 * the Base and Length of the Rx Descriptor Ring
3701 */
9a799d71 3702 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3703 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3704 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3705 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3706 else
7d637bcc 3707 clear_ring_rsc_enabled(rx_ring);
477de6ed 3708 }
477de6ed
AD		 3709}
3710
7367096a
AD		 3711static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3712{
3713 struct ixgbe_hw *hw = &adapter->hw;
3714 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3715
3716 switch (hw->mac.type) {
9a75a1ac
DS		 3717 case ixgbe_mac_X550:
3718 case ixgbe_mac_X550EM_x:
7367096a
AD		 3719 case ixgbe_mac_82598EB:
3720 /*
3721 * For VMDq support of different descriptor types or
3722 * buffer sizes through the use of multiple SRRCTL
3723 * registers, RDRXCTL.MVMEN must be set to 1
3724 *
3725 * also, the manual doesn't mention it clearly but DCA hints
3726 * will only use queue 0's tags unless this bit is set. Side
3727 * effects of setting this bit are only that SRRCTL must be
3728 * fully programmed [0..15]
3729 */
3730 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3731 break;
3732 case ixgbe_mac_82599EB:
b93a2226 3733 case ixgbe_mac_X540:
7367096a
AD		 3734 /* Disable RSC for ACK packets */
3735 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3736 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3737 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3738 /* hardware requires some bits to be set by default */
3739 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3740 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3741 break;
3742 default:
3743 /* We should do nothing since we don't know this hardware */
3744 return;
3745 }
3746
3747 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3748}
3749
477de6ed
AD		 3750/**
3751 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3752 * @adapter: board private structure
3753 *
3754 * Configure the Rx unit of the MAC after a reset.
3755 **/
3756static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3757{
3758 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3759 int i;
6dcc28b9 3760 u32 rxctrl, rfctl;
477de6ed
AD		 3761
3762 /* disable receives while setting up the descriptors */
1f9ac57c 3763 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3764
3765 ixgbe_setup_psrtype(adapter);
7367096a 3766 ixgbe_setup_rdrxctl(adapter);
477de6ed 3767
6dcc28b9
JK		 3768 /* RSC Setup */
3769 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3770 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3771 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3772 rfctl |= IXGBE_RFCTL_RSC_DIS;
3773 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3774
9e10e045 3775 /* Program registers for the distribution of queues */
f5b4a52e 3776 ixgbe_setup_mrqc(adapter);
f5b4a52e 3777
477de6ed
AD		 3778 /* set_rx_buffer_len must be called before ring initialization */
3779 ixgbe_set_rx_buffer_len(adapter);
3780
3781 /*
3782 * Setup the HW Rx Head and Tail Descriptor Pointers and
3783 * the Base and Length of the Rx Descriptor Ring
3784 */
9e10e045
AD		 3785 for (i = 0; i < adapter->num_rx_queues; i++)
3786 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3787
1f9ac57c 3788 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3789 /* disable drop enable for 82598 parts */
3790 if (hw->mac.type == ixgbe_mac_82598EB)
3791 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3792
3793 /* enable all receives */
3794 rxctrl |= IXGBE_RXCTRL_RXEN;
3795 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3796}
3797
80d5c368
PM		 3798static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3799 __be16 proto, u16 vid)
068c89b0
DS		 3800{
3801 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3802 struct ixgbe_hw *hw = &adapter->hw;
3803
3804 /* add VID to filter table */
1d9c0bfd 3805 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3806 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3807
3808 return 0;
068c89b0
DS		 3809}
3810
80d5c368
PM		 3811static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3812 __be16 proto, u16 vid)
068c89b0
DS		 3813{
3814 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3815 struct ixgbe_hw *hw = &adapter->hw;
3816
068c89b0 3817 /* remove VID from filter table */
1d9c0bfd 3818 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3819 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3820
3821 return 0;
068c89b0
DS		 3822}
3823
f62bbb5e
JG		 3824/**
3825 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3826 * @adapter: driver data
3827 */
3828static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3829{
3830 struct ixgbe_hw *hw = &adapter->hw;
3831 u32 vlnctrl;
5f6c0181
JB		 3832 int i, j;
3833
3834 switch (hw->mac.type) {
3835 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3836 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3837 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3838 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3839 break;
3840 case ixgbe_mac_82599EB:
b93a2226 3841 case ixgbe_mac_X540:
9a75a1ac
DS		 3842 case ixgbe_mac_X550:
3843 case ixgbe_mac_X550EM_x:
5f6c0181 3844 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3845 struct ixgbe_ring *ring = adapter->rx_ring[i];
3846
3847 if (ring->l2_accel_priv)
3848 continue;
3849 j = ring->reg_idx;
5f6c0181
JB		 3850 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3851 vlnctrl &= ~IXGBE_RXDCTL_VME;
3852 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3853 }
3854 break;
3855 default:
3856 break;
3857 }
3858}
3859
3860/**
f62bbb5e 3861 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3862 * @adapter: driver data
3863 */
f62bbb5e 3864static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3865{
3866 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3867 u32 vlnctrl;
5f6c0181
JB		 3868 int i, j;
3869
3870 switch (hw->mac.type) {
3871 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3872 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3873 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3874 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3875 break;
3876 case ixgbe_mac_82599EB:
b93a2226 3877 case ixgbe_mac_X540:
9a75a1ac
DS		 3878 case ixgbe_mac_X550:
3879 case ixgbe_mac_X550EM_x:
5f6c0181 3880 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3881 struct ixgbe_ring *ring = adapter->rx_ring[i];
3882
3883 if (ring->l2_accel_priv)
3884 continue;
3885 j = ring->reg_idx;
5f6c0181
JB		 3886 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3887 vlnctrl |= IXGBE_RXDCTL_VME;
3888 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3889 }
3890 break;
3891 default:
3892 break;
3893 }
3894}
3895
9a799d71
AK		 3896static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3897{
f62bbb5e 3898 u16 vid;
9a799d71 3899
80d5c368 3900 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3901
3902 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3903 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3904}
3905
b335e75b
JK		 3906/**
3907 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3908 * @netdev: network interface device structure
3909 *
3910 * Writes multicast address list to the MTA hash table.
3911 * Returns: -ENOMEM on failure
3912 * 0 on no addresses written
3913 * X on writing X addresses to MTA
3914 **/
3915static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3916{
3917 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3918 struct ixgbe_hw *hw = &adapter->hw;
3919
3920 if (!netif_running(netdev))
3921 return 0;
3922
3923 if (hw->mac.ops.update_mc_addr_list)
3924 hw->mac.ops.update_mc_addr_list(hw, netdev);
3925 else
3926 return -ENOMEM;
3927
3928#ifdef CONFIG_PCI_IOV
5d7daa35 3929 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 3930#endif
3931
3932 return netdev_mc_count(netdev);
3933}
3934
5d7daa35
JK		 3935#ifdef CONFIG_PCI_IOV
3936void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3937{
3938 struct ixgbe_hw *hw = &adapter->hw;
3939 int i;
3940 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3941 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3942 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3943 adapter->mac_table[i].queue,
3944 IXGBE_RAH_AV);
3945 else
3946 hw->mac.ops.clear_rar(hw, i);
3947
3948 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3949 }
3950}
3951#endif
3952
3953static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3954{
3955 struct ixgbe_hw *hw = &adapter->hw;
3956 int i;
3957 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3958 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3959 if (adapter->mac_table[i].state &
3960 IXGBE_MAC_STATE_IN_USE)
3961 hw->mac.ops.set_rar(hw, i,
3962 adapter->mac_table[i].addr,
3963 adapter->mac_table[i].queue,
3964 IXGBE_RAH_AV);
3965 else
3966 hw->mac.ops.clear_rar(hw, i);
3967
3968 adapter->mac_table[i].state &=
3969 ~(IXGBE_MAC_STATE_MODIFIED);
3970 }
3971 }
3972}
3973
3974static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3975{
3976 int i;
3977 struct ixgbe_hw *hw = &adapter->hw;
3978
3979 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3980 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3981 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 3982 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 3983 adapter->mac_table[i].queue = 0;
3984 }
3985 ixgbe_sync_mac_table(adapter);
3986}
3987
3988static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3989{
3990 struct ixgbe_hw *hw = &adapter->hw;
3991 int i, count = 0;
3992
3993 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3994 if (adapter->mac_table[i].state == 0)
3995 count++;
3996 }
3997 return count;
3998}
3999
4000/* this function destroys the first RAR entry */
4001static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4002 u8 *addr)
4003{
4004 struct ixgbe_hw *hw = &adapter->hw;
4005
4006 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4007 adapter->mac_table[0].queue = VMDQ_P(0);
4008 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4009 IXGBE_MAC_STATE_IN_USE);
4010 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4011 adapter->mac_table[0].queue,
4012 IXGBE_RAH_AV);
4013}
4014
4015int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4016{
4017 struct ixgbe_hw *hw = &adapter->hw;
4018 int i;
4019
4020 if (is_zero_ether_addr(addr))
4021 return -EINVAL;
4022
4023 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4024 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4025 continue;
4026 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4027 IXGBE_MAC_STATE_IN_USE);
4028 ether_addr_copy(adapter->mac_table[i].addr, addr);
4029 adapter->mac_table[i].queue = queue;
4030 ixgbe_sync_mac_table(adapter);
4031 return i;
4032 }
4033 return -ENOMEM;
4034}
4035
4036int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4037{
4038 /* search table for addr, if found, set to 0 and sync */
4039 int i;
4040 struct ixgbe_hw *hw = &adapter->hw;
4041
4042 if (is_zero_ether_addr(addr))
4043 return -EINVAL;
4044
4045 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4046 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4047 adapter->mac_table[i].queue == queue) {
4048 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4049 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4050 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4051 adapter->mac_table[i].queue = 0;
4052 ixgbe_sync_mac_table(adapter);
4053 return 0;
4054 }
4055 }
4056 return -ENOMEM;
4057}
2850062a
AD		 4058/**
4059 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4060 * @netdev: network interface device structure
4061 *
4062 * Writes unicast address list to the RAR table.
4063 * Returns: -ENOMEM on failure/insufficient address space
4064 * 0 on no addresses written
4065 * X on writing X addresses to the RAR table
4066 **/
5d7daa35 4067static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4068{
4069 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4070 int count = 0;
4071
4072 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4073 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4074 return -ENOMEM;
4075
95447461 4076 if (!netdev_uc_empty(netdev)) {
2850062a 4077 struct netdev_hw_addr *ha;
2850062a 4078 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4079 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4080 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4081 count++;
4082 }
4083 }
2850062a
AD		 4084 return count;
4085}
4086
9a799d71 4087/**
2c5645cf 4088 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4089 * @netdev: network interface device structure
4090 *
2c5645cf
CL		 4091 * The set_rx_method entry point is called whenever the unicast/multicast
4092 * address list or the network interface flags are updated. This routine is
4093 * responsible for configuring the hardware for proper unicast, multicast and
4094 * promiscuous mode.
9a799d71 4095 **/
7f870475 4096void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4097{
4098 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4099 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4100 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4101 u32 vlnctrl;
2850062a 4102 int count;
9a799d71
AK		 4103
4104 /* Check for Promiscuous and All Multicast modes */
9a799d71 4105 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4106 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4107
f5dc442b 4108 /* set all bits that we expect to always be set */
3f2d1c0f 4109 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4110 fctrl |= IXGBE_FCTRL_BAM;
4111 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4112 fctrl |= IXGBE_FCTRL_PMCF;
4113
2850062a
AD		 4114 /* clear the bits we are changing the status of */
4115 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4116 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4117 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4118 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4119 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4120 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4121 /* Only disable hardware filter vlans in promiscuous mode
4122 * if SR-IOV and VMDQ are disabled - otherwise ensure
4123 * that hardware VLAN filters remain enabled.
4124 */
4556dc59
VY		 4125 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4126 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 4127 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4128 } else {
746b9f02
PM		 4129 if (netdev->flags & IFF_ALLMULTI) {
4130 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4131 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4132 }
a9b8943e 4133 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4134 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4135 }
4136
4137 /*
4138 * Write addresses to available RAR registers, if there is not
4139 * sufficient space to store all the addresses then enable
4140 * unicast promiscuous mode
4141 */
5d7daa35 4142 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4143 if (count < 0) {
4144 fctrl |= IXGBE_FCTRL_UPE;
4145 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4146 }
4147
cf78959c
ET		 4148 /* Write addresses to the MTA, if the attempt fails
4149 * then we should just turn on promiscuous mode so
4150 * that we can at least receive multicast traffic
4151 */
b335e75b
JK		 4152 count = ixgbe_write_mc_addr_list(netdev);
4153 if (count < 0) {
4154 fctrl |= IXGBE_FCTRL_MPE;
4155 vmolr |= IXGBE_VMOLR_MPE;
4156 } else if (count) {
4157 vmolr |= IXGBE_VMOLR_ROMPE;
4158 }
1d9c0bfd
AD		 4159
4160 if (hw->mac.type != ixgbe_mac_82598EB) {
4161 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4162 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4163 IXGBE_VMOLR_ROPE);
1d9c0bfd 4164 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4165 }
4166
3f2d1c0f
BG		 4167 /* This is useful for sniffing bad packets. */
4168 if (adapter->netdev->features & NETIF_F_RXALL) {
4169 /* UPE and MPE will be handled by normal PROMISC logic
4170 * in e1000e_set_rx_mode */
4171 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4172 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4173 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4174
4175 fctrl &= ~(IXGBE_FCTRL_DPF);
4176 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4177 }
4178
a9b8943e 4179 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4180 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4181
f646968f 4182 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4183 ixgbe_vlan_strip_enable(adapter);
4184 else
4185 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4186}
4187
021230d4
AV		 4188static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4189{
4190 int q_idx;
021230d4 4191
5a85e737
ET		 4192 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4193 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4194 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4195 }
021230d4
AV		 4196}
4197
4198static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4199{
4200 int q_idx;
021230d4 4201
5a85e737 4202 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4203 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4204 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4205 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4206 usleep_range(1000, 20000);
5a85e737
ET		 4207 }
4208 }
021230d4
AV		 4209}
4210
7a6b6f51 4211#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4212/**
2f90b865
AD		 4213 * ixgbe_configure_dcb - Configure DCB hardware
4214 * @adapter: ixgbe adapter struct
4215 *
4216 * This is called by the driver on open to configure the DCB hardware.
4217 * This is also called by the gennetlink interface when reconfiguring
4218 * the DCB state.
4219 */
4220static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4221{
4222 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4223 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4224
67ebd791
AD		 4225 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4226 if (hw->mac.type == ixgbe_mac_82598EB)
4227 netif_set_gso_max_size(adapter->netdev, 65536);
4228 return;
4229 }
4230
4231 if (hw->mac.type == ixgbe_mac_82598EB)
4232 netif_set_gso_max_size(adapter->netdev, 32768);
4233
971060b1 4234#ifdef IXGBE_FCOE
b120818e
JF		 4235 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4236 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4237#endif
b120818e
JF		 4238
4239 /* reconfigure the hardware */
4240 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4241 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4242 DCB_TX_CONFIG);
4243 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4244 DCB_RX_CONFIG);
4245 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4246 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4247 ixgbe_dcb_hw_ets(&adapter->hw,
4248 adapter->ixgbe_ieee_ets,
4249 max_frame);
4250 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4251 adapter->ixgbe_ieee_pfc->pfc_en,
4252 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4253 }
8187cd48
JF		 4254
4255 /* Enable RSS Hash per TC */
4256 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4257 u32 msb = 0;
4258 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4259
d411a936
AD		 4260 while (rss_i) {
4261 msb++;
4262 rss_i >>= 1;
4263 }
8187cd48 4264
4ae63730
AD		 4265 /* write msb to all 8 TCs in one write */
4266 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4267 }
2f90b865 4268}
9da712d2
JF		 4269#endif
4270
4271/* Additional bittime to account for IXGBE framing */
4272#define IXGBE_ETH_FRAMING 20
4273
49ce9c2c 4274/**
9da712d2
JF		 4275 * ixgbe_hpbthresh - calculate high water mark for flow control
4276 *
4277 * @adapter: board private structure to calculate for
49ce9c2c 4278 * @pb: packet buffer to calculate
9da712d2
JF		 4279 */
4280static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4281{
4282 struct ixgbe_hw *hw = &adapter->hw;
4283 struct net_device *dev = adapter->netdev;
4284 int link, tc, kb, marker;
4285 u32 dv_id, rx_pba;
4286
4287 /* Calculate max LAN frame size */
4288 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4289
4290#ifdef IXGBE_FCOE
4291 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4292 if ((dev->features & NETIF_F_FCOE_MTU) &&
4293 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4294 (pb == ixgbe_fcoe_get_tc(adapter)))
4295 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4296#endif
e5776620 4297
9da712d2
JF		 4298 /* Calculate delay value for device */
4299 switch (hw->mac.type) {
4300 case ixgbe_mac_X540:
9a75a1ac
DS		 4301 case ixgbe_mac_X550:
4302 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4303 dv_id = IXGBE_DV_X540(link, tc);
4304 break;
4305 default:
4306 dv_id = IXGBE_DV(link, tc);
4307 break;
4308 }
4309
4310 /* Loopback switch introduces additional latency */
4311 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4312 dv_id += IXGBE_B2BT(tc);
4313
4314 /* Delay value is calculated in bit times convert to KB */
4315 kb = IXGBE_BT2KB(dv_id);
4316 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4317
4318 marker = rx_pba - kb;
4319
4320 /* It is possible that the packet buffer is not large enough
4321 * to provide required headroom. In this case throw an error
4322 * to user and a do the best we can.
4323 */
4324 if (marker < 0) {
4325 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4326 "headroom to support flow control."
4327 "Decrease MTU or number of traffic classes\n", pb);
4328 marker = tc + 1;
4329 }
4330
4331 return marker;
4332}
4333
49ce9c2c 4334/**
9da712d2
JF		 4335 * ixgbe_lpbthresh - calculate low water mark for for flow control
4336 *
4337 * @adapter: board private structure to calculate for
49ce9c2c 4338 * @pb: packet buffer to calculate
9da712d2 4339 */
e5776620 4340static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4341{
4342 struct ixgbe_hw *hw = &adapter->hw;
4343 struct net_device *dev = adapter->netdev;
4344 int tc;
4345 u32 dv_id;
4346
4347 /* Calculate max LAN frame size */
4348 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4349
e5776620
JK		 4350#ifdef IXGBE_FCOE
4351 /* FCoE traffic class uses FCOE jumbo frames */
4352 if ((dev->features & NETIF_F_FCOE_MTU) &&
4353 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4354 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4355 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4356#endif
4357
9da712d2
JF		 4358 /* Calculate delay value for device */
4359 switch (hw->mac.type) {
4360 case ixgbe_mac_X540:
9a75a1ac
DS		 4361 case ixgbe_mac_X550:
4362 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4363 dv_id = IXGBE_LOW_DV_X540(tc);
4364 break;
4365 default:
4366 dv_id = IXGBE_LOW_DV(tc);
4367 break;
4368 }
4369
4370 /* Delay value is calculated in bit times convert to KB */
4371 return IXGBE_BT2KB(dv_id);
4372}
4373
4374/*
4375 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4376 */
4377static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4378{
4379 struct ixgbe_hw *hw = &adapter->hw;
4380 int num_tc = netdev_get_num_tc(adapter->netdev);
4381 int i;
4382
4383 if (!num_tc)
4384 num_tc = 1;
4385
9da712d2
JF		 4386 for (i = 0; i < num_tc; i++) {
4387 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4388 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4389
4390 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4391 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4392 hw->fc.low_water[i] = 0;
9da712d2 4393 }
e5776620
JK		 4394
4395 for (; i < MAX_TRAFFIC_CLASS; i++)
4396 hw->fc.high_water[i] = 0;
9da712d2
JF		 4397}
4398
80605c65
JF		 4399static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4400{
80605c65 4401 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4402 int hdrm;
4403 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4404
4405 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4406 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4407 hdrm = 32 << adapter->fdir_pballoc;
4408 else
4409 hdrm = 0;
80605c65 4410
f7e1027f 4411 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4412 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4413}
4414
e4911d57
AD		 4415static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4416{
4417 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4418 struct hlist_node *node2;
e4911d57
AD		 4419 struct ixgbe_fdir_filter *filter;
4420
4421 spin_lock(&adapter->fdir_perfect_lock);
4422
4423 if (!hlist_empty(&adapter->fdir_filter_list))
4424 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4425
b67bfe0d 4426 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4427 &adapter->fdir_filter_list, fdir_node) {
4428 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4429 &filter->filter,
4430 filter->sw_idx,
4431 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4432 IXGBE_FDIR_DROP_QUEUE :
4433 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4434 }
4435
4436 spin_unlock(&adapter->fdir_perfect_lock);
4437}
4438
2a47fa45
JF		 4439static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4440 struct ixgbe_adapter *adapter)
4441{
4442 struct ixgbe_hw *hw = &adapter->hw;
4443 u32 vmolr;
4444
4445 /* No unicast promiscuous support for VMDQ devices. */
4446 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4447 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4448
4449 /* clear the affected bit */
4450 vmolr &= ~IXGBE_VMOLR_MPE;
4451
4452 if (dev->flags & IFF_ALLMULTI) {
4453 vmolr |= IXGBE_VMOLR_MPE;
4454 } else {
4455 vmolr |= IXGBE_VMOLR_ROMPE;
4456 hw->mac.ops.update_mc_addr_list(hw, dev);
4457 }
5d7daa35 4458 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4459 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4460}
4461
2a47fa45
JF		 4462static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4463{
4464 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4465 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4466 struct ixgbe_hw *hw = &adapter->hw;
4467 u16 pool = vadapter->pool;
4468 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4469 IXGBE_PSRTYPE_UDPHDR |
4470 IXGBE_PSRTYPE_IPV4HDR |
4471 IXGBE_PSRTYPE_L2HDR |
4472 IXGBE_PSRTYPE_IPV6HDR;
4473
4474 if (hw->mac.type == ixgbe_mac_82598EB)
4475 return;
4476
4477 if (rss_i > 3)
4478 psrtype |= 2 << 29;
4479 else if (rss_i > 1)
4480 psrtype |= 1 << 29;
4481
4482 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4483}
4484
4485/**
4486 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4487 * @rx_ring: ring to free buffers from
4488 **/
4489static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4490{
4491 struct device *dev = rx_ring->dev;
4492 unsigned long size;
4493 u16 i;
4494
4495 /* ring already cleared, nothing to do */
4496 if (!rx_ring->rx_buffer_info)
4497 return;
4498
4499 /* Free all the Rx ring sk_buffs */
4500 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4501 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4502
2a47fa45
JF		 4503 if (rx_buffer->skb) {
4504 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4505 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4506 dma_unmap_page(dev,
4507 IXGBE_CB(skb)->dma,
4508 ixgbe_rx_bufsz(rx_ring),
4509 DMA_FROM_DEVICE);
2a47fa45 4510 dev_kfree_skb(skb);
4d2fcfbc 4511 rx_buffer->skb = NULL;
2a47fa45 4512 }
18cb652a
AD		 4513
4514 if (!rx_buffer->page)
4515 continue;
4516
4517 dma_unmap_page(dev, rx_buffer->dma,
4518 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4519 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4520
2a47fa45
JF		 4521 rx_buffer->page = NULL;
4522 }
4523
4524 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4525 memset(rx_ring->rx_buffer_info, 0, size);
4526
4527 /* Zero out the descriptor ring */
4528 memset(rx_ring->desc, 0, rx_ring->size);
4529
4530 rx_ring->next_to_alloc = 0;
4531 rx_ring->next_to_clean = 0;
4532 rx_ring->next_to_use = 0;
4533}
4534
4535static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4536 struct ixgbe_ring *rx_ring)
4537{
4538 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4539 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4540
4541 /* shutdown specific queue receive and wait for dma to settle */
4542 ixgbe_disable_rx_queue(adapter, rx_ring);
4543 usleep_range(10000, 20000);
4544 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4545 ixgbe_clean_rx_ring(rx_ring);
4546 rx_ring->l2_accel_priv = NULL;
4547}
4548
ae72c8d0
JF		 4549static int ixgbe_fwd_ring_down(struct net_device *vdev,
4550 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4551{
4552 struct ixgbe_adapter *adapter = accel->real_adapter;
4553 unsigned int rxbase = accel->rx_base_queue;
4554 unsigned int txbase = accel->tx_base_queue;
4555 int i;
4556
4557 netif_tx_stop_all_queues(vdev);
4558
4559 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4560 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4561 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4562 }
4563
4564 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4565 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4566 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4567 }
4568
4569
4570 return 0;
4571}
4572
4573static int ixgbe_fwd_ring_up(struct net_device *vdev,
4574 struct ixgbe_fwd_adapter *accel)
4575{
4576 struct ixgbe_adapter *adapter = accel->real_adapter;
4577 unsigned int rxbase, txbase, queues;
4578 int i, baseq, err = 0;
4579
4580 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4581 return 0;
4582
4583 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4584 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4585 accel->pool, adapter->num_rx_pools,
4586 baseq, baseq + adapter->num_rx_queues_per_pool,
4587 adapter->fwd_bitmask);
4588
4589 accel->netdev = vdev;
4590 accel->rx_base_queue = rxbase = baseq;
4591 accel->tx_base_queue = txbase = baseq;
4592
4593 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4594 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4595
4596 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4597 adapter->rx_ring[rxbase + i]->netdev = vdev;
4598 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4599 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4600 }
4601
4602 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4603 adapter->tx_ring[txbase + i]->netdev = vdev;
4604 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4605 }
4606
4607 queues = min_t(unsigned int,
4608 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4609 err = netif_set_real_num_tx_queues(vdev, queues);
4610 if (err)
4611 goto fwd_queue_err;
4612
2a47fa45
JF		 4613 err = netif_set_real_num_rx_queues(vdev, queues);
4614 if (err)
4615 goto fwd_queue_err;
4616
4617 if (is_valid_ether_addr(vdev->dev_addr))
4618 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4619
4620 ixgbe_fwd_psrtype(accel);
4621 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4622 return err;
4623fwd_queue_err:
4624 ixgbe_fwd_ring_down(vdev, accel);
4625 return err;
4626}
4627
4628static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4629{
4630 struct net_device *upper;
4631 struct list_head *iter;
4632 int err;
4633
4634 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4635 if (netif_is_macvlan(upper)) {
4636 struct macvlan_dev *dfwd = netdev_priv(upper);
4637 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4638
4639 if (dfwd->fwd_priv) {
4640 err = ixgbe_fwd_ring_up(upper, vadapter);
4641 if (err)
4642 continue;
4643 }
4644 }
4645 }
4646}
4647
9a799d71
AK		 4648static void ixgbe_configure(struct ixgbe_adapter *adapter)
4649{
d2f5e7f3
AS		 4650 struct ixgbe_hw *hw = &adapter->hw;
4651
80605c65 4652 ixgbe_configure_pb(adapter);
7a6b6f51 4653#ifdef CONFIG_IXGBE_DCB
67ebd791 4654 ixgbe_configure_dcb(adapter);
2f90b865 4655#endif
b35d4d42
AD		 4656 /*
4657 * We must restore virtualization before VLANs or else
4658 * the VLVF registers will not be populated
4659 */
4660 ixgbe_configure_virtualization(adapter);
9a799d71 4661
4c1d7b4b 4662 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4663 ixgbe_restore_vlan(adapter);
4664
d2f5e7f3
AS		 4665 switch (hw->mac.type) {
4666 case ixgbe_mac_82599EB:
4667 case ixgbe_mac_X540:
4668 hw->mac.ops.disable_rx_buff(hw);
4669 break;
4670 default:
4671 break;
4672 }
4673
c4cf55e5 4674 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4675 ixgbe_init_fdir_signature_82599(&adapter->hw,
4676 adapter->fdir_pballoc);
e4911d57
AD		 4677 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4678 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4679 adapter->fdir_pballoc);
4680 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4681 }
4c1d7b4b 4682
d2f5e7f3
AS		 4683 switch (hw->mac.type) {
4684 case ixgbe_mac_82599EB:
4685 case ixgbe_mac_X540:
4686 hw->mac.ops.enable_rx_buff(hw);
4687 break;
4688 default:
4689 break;
4690 }
4691
7c8ae65a
AD		 4692#ifdef IXGBE_FCOE
4693 /* configure FCoE L2 filters, redirection table, and Rx control */
4694 ixgbe_configure_fcoe(adapter);
4695
4696#endif /* IXGBE_FCOE */
9a799d71
AK		 4697 ixgbe_configure_tx(adapter);
4698 ixgbe_configure_rx(adapter);
2a47fa45 4699 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4700}
4701
e8e26350
PW		 4702static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4703{
4704 switch (hw->phy.type) {
4705 case ixgbe_phy_sfp_avago:
4706 case ixgbe_phy_sfp_ftl:
4707 case ixgbe_phy_sfp_intel:
4708 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4709 case ixgbe_phy_sfp_passive_tyco:
4710 case ixgbe_phy_sfp_passive_unknown:
4711 case ixgbe_phy_sfp_active_unknown:
4712 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4713 case ixgbe_phy_qsfp_passive_unknown:
4714 case ixgbe_phy_qsfp_active_unknown:
4715 case ixgbe_phy_qsfp_intel:
4716 case ixgbe_phy_qsfp_unknown:
d9cd46cd
ET		 4717 /* ixgbe_phy_none is set when no SFP module is present */
4718 case ixgbe_phy_none:
e8e26350 4719 return true;
8917b447
AD		 4720 case ixgbe_phy_nl:
4721 if (hw->mac.type == ixgbe_mac_82598EB)
4722 return true;
e8e26350
PW		 4723 default:
4724 return false;
4725 }
4726}
4727
0ecc061d 4728/**
e8e26350
PW		 4729 * ixgbe_sfp_link_config - set up SFP+ link
4730 * @adapter: pointer to private adapter struct
4731 **/
4732static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4733{
7086400d 4734 /*
52f33af8 4735 * We are assuming the worst case scenario here, and that
7086400d
AD		 4736 * is that an SFP was inserted/removed after the reset
4737 * but before SFP detection was enabled. As such the best
4738 * solution is to just start searching as soon as we start
4739 */
4740 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4741 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4742
7086400d 4743 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4744}
4745
4746/**
4747 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4748 * @hw: pointer to private hardware struct
4749 *
4750 * Returns 0 on success, negative on failure
4751 **/
e8e26350 4752static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4753{
3d292265
JH		 4754 u32 speed;
4755 bool autoneg, link_up = false;
0ecc061d
PWJ		 4756 u32 ret = IXGBE_ERR_LINK_SETUP;
4757
4758 if (hw->mac.ops.check_link)
3d292265 4759 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4760
4761 if (ret)
e90dd264 4762 return ret;
0ecc061d 4763
3d292265
JH		 4764 speed = hw->phy.autoneg_advertised;
4765 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4766 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4767 &autoneg);
0ecc061d 4768 if (ret)
e90dd264 4769 return ret;
0ecc061d 4770
8620a103 4771 if (hw->mac.ops.setup_link)
fd0326f2 4772 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4773
0ecc061d
PWJ		 4774 return ret;
4775}
4776
a34bcfff 4777static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4778{
9a799d71 4779 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4780 u32 gpie = 0;
9a799d71 4781
9b471446 4782 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4783 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4784 IXGBE_GPIE_OCD;
4785 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4786 /*
4787 * use EIAM to auto-mask when MSI-X interrupt is asserted
4788 * this saves a register write for every interrupt
4789 */
4790 switch (hw->mac.type) {
4791 case ixgbe_mac_82598EB:
4792 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4793 break;
9b471446 4794 case ixgbe_mac_82599EB:
b93a2226 4795 case ixgbe_mac_X540:
9a75a1ac
DS		 4796 case ixgbe_mac_X550:
4797 case ixgbe_mac_X550EM_x:
b93a2226 4798 default:
9b471446
JB		 4799 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4800 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4801 break;
4802 }
4803 } else {
021230d4
AV		 4804 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4805 * specifically only auto mask tx and rx interrupts */
4806 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4807 }
9a799d71 4808
a34bcfff
AD		 4809 /* XXX: to interrupt immediately for EICS writes, enable this */
4810 /* gpie |= IXGBE_GPIE_EIMEN; */
4811
4812 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4813 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4814
4815 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4816 case IXGBE_82599_VMDQ_8Q_MASK:
4817 gpie |= IXGBE_GPIE_VTMODE_16;
4818 break;
4819 case IXGBE_82599_VMDQ_4Q_MASK:
4820 gpie |= IXGBE_GPIE_VTMODE_32;
4821 break;
4822 default:
4823 gpie |= IXGBE_GPIE_VTMODE_64;
4824 break;
4825 }
119fc60a
MC		 4826 }
4827
5fdd31f9 4828 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4829 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4830 switch (adapter->hw.mac.type) {
4831 case ixgbe_mac_82599EB:
4832 gpie |= IXGBE_SDP0_GPIEN;
4833 break;
4834 case ixgbe_mac_X540:
4835 gpie |= IXGBE_EIMS_TS;
4836 break;
4837 default:
4838 break;
4839 }
4840 }
5fdd31f9 4841
a34bcfff
AD		 4842 /* Enable fan failure interrupt */
4843 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4844 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4845
2698b208 4846 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4847 gpie |= IXGBE_SDP1_GPIEN;
4848 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4849 }
a34bcfff
AD		 4850
4851 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4852}
4853
c7ccde0f 4854static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4855{
4856 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4857 int err;
a34bcfff
AD		 4858 u32 ctrl_ext;
4859
4860 ixgbe_get_hw_control(adapter);
4861 ixgbe_setup_gpie(adapter);
e8e26350 4862
9a799d71
AK		 4863 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4864 ixgbe_configure_msix(adapter);
4865 else
4866 ixgbe_configure_msi_and_legacy(adapter);
4867
ec74a471
ET		 4868 /* enable the optics for 82599 SFP+ fiber */
4869 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4870 hw->mac.ops.enable_tx_laser(hw);
4871
4e857c58 4872 smp_mb__before_atomic();
9a799d71 4873 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4874 ixgbe_napi_enable_all(adapter);
4875
73c4b7cd
AD		 4876 if (ixgbe_is_sfp(hw)) {
4877 ixgbe_sfp_link_config(adapter);
4878 } else {
4879 err = ixgbe_non_sfp_link_config(hw);
4880 if (err)
4881 e_err(probe, "link_config FAILED %d\n", err);
4882 }
4883
021230d4
AV		 4884 /* clear any pending interrupts, may auto mask */
4885 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4886 ixgbe_irq_enable(adapter, true, true);
9a799d71 4887
bf069c97
DS		 4888 /*
4889 * If this adapter has a fan, check to see if we had a failure
4890 * before we enabled the interrupt.
4891 */
4892 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4893 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4894 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4895 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4896 }
4897
9a799d71
AK		 4898 /* bring the link up in the watchdog, this could race with our first
4899 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4900 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4901 adapter->link_check_timeout = jiffies;
7086400d 4902 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4903
4904 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4905 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4906 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4907 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4908}
4909
d4f80882
AV		 4910void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4911{
4912 WARN_ON(in_interrupt());
7086400d
AD		 4913 /* put off any impending NetWatchDogTimeout */
4914 adapter->netdev->trans_start = jiffies;
4915
d4f80882 4916 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4917 usleep_range(1000, 2000);
d4f80882 4918 ixgbe_down(adapter);
5809a1ae
GR		 4919 /*
4920 * If SR-IOV enabled then wait a bit before bringing the adapter
4921 * back up to give the VFs time to respond to the reset. The
4922 * two second wait is based upon the watchdog timer cycle in
4923 * the VF driver.
4924 */
4925 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4926 msleep(2000);
d4f80882
AV		 4927 ixgbe_up(adapter);
4928 clear_bit(__IXGBE_RESETTING, &adapter->state);
4929}
4930
c7ccde0f 4931void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4932{
4933 /* hardware has been reset, we need to reload some things */
4934 ixgbe_configure(adapter);
4935
c7ccde0f 4936 ixgbe_up_complete(adapter);
9a799d71
AK		 4937}
4938
4939void ixgbe_reset(struct ixgbe_adapter *adapter)
4940{
c44ade9e 4941 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 4942 struct net_device *netdev = adapter->netdev;
8ca783ab 4943 int err;
5d7daa35 4944 u8 old_addr[ETH_ALEN];
8ca783ab 4945
b0483c8f
MR		 4946 if (ixgbe_removed(hw->hw_addr))
4947 return;
7086400d
AD		 4948 /* lock SFP init bit to prevent race conditions with the watchdog */
4949 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4950 usleep_range(1000, 2000);
4951
4952 /* clear all SFP and link config related flags while holding SFP_INIT */
4953 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4954 IXGBE_FLAG2_SFP_NEEDS_RESET);
4955 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4956
8ca783ab 4957 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4958 switch (err) {
4959 case 0:
4960 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4961 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4962 break;
4963 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4964 e_dev_err("master disable timed out\n");
da4dd0f7 4965 break;
794caeb2
PWJ		 4966 case IXGBE_ERR_EEPROM_VERSION:
4967 /* We are running on a pre-production device, log a warning */
849c4542 4968 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4969 "Please be aware there may be issues associated with "
849c4542
ET		 4970 "your hardware. If you are experiencing problems "
4971 "please contact your Intel or hardware "
4972 "representative who provided you with this "
4973 "hardware.\n");
794caeb2 4974 break;
da4dd0f7 4975 default:
849c4542 4976 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4977 }
9a799d71 4978
7086400d 4979 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 4980 /* do not flush user set addresses */
4981 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4982 ixgbe_flush_sw_mac_table(adapter);
4983 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 4984
4985 /* update SAN MAC vmdq pool selection */
4986 if (hw->mac.san_mac_rar_index)
4987 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4988
8fecf67c 4989 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4990 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4991}
4992
9a799d71
AK		 4993/**
4994 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4995 * @tx_ring: ring to be cleaned
4996 **/
b6ec895e 4997static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4998{
4999 struct ixgbe_tx_buffer *tx_buffer_info;
5000 unsigned long size;
b6ec895e 5001 u16 i;
9a799d71 5002
84418e3b
AD		 5003 /* ring already cleared, nothing to do */
5004 if (!tx_ring->tx_buffer_info)
5005 return;
9a799d71 5006
84418e3b 5007 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5008 for (i = 0; i < tx_ring->count; i++) {
5009 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5010 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5011 }
5012
dad8a3b3
JF		 5013 netdev_tx_reset_queue(txring_txq(tx_ring));
5014
9a799d71
AK		 5015 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5016 memset(tx_ring->tx_buffer_info, 0, size);
5017
5018 /* Zero out the descriptor ring */
5019 memset(tx_ring->desc, 0, tx_ring->size);
5020
5021 tx_ring->next_to_use = 0;
5022 tx_ring->next_to_clean = 0;
9a799d71
AK		 5023}
5024
5025/**
021230d4 5026 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5027 * @adapter: board private structure
5028 **/
021230d4 5029static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5030{
5031 int i;
5032
021230d4 5033 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5034 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5035}
5036
5037/**
021230d4 5038 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5039 * @adapter: board private structure
5040 **/
021230d4 5041static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5042{
5043 int i;
5044
021230d4 5045 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5046 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5047}
5048
e4911d57
AD		 5049static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5050{
b67bfe0d 5051 struct hlist_node *node2;
e4911d57
AD		 5052 struct ixgbe_fdir_filter *filter;
5053
5054 spin_lock(&adapter->fdir_perfect_lock);
5055
b67bfe0d 5056 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5057 &adapter->fdir_filter_list, fdir_node) {
5058 hlist_del(&filter->fdir_node);
5059 kfree(filter);
5060 }
5061 adapter->fdir_filter_count = 0;
5062
5063 spin_unlock(&adapter->fdir_perfect_lock);
5064}
5065
9a799d71
AK		 5066void ixgbe_down(struct ixgbe_adapter *adapter)
5067{
5068 struct net_device *netdev = adapter->netdev;
7f821875 5069 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5070 struct net_device *upper;
5071 struct list_head *iter;
bf29ee6c 5072 int i;
9a799d71
AK		 5073
5074 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5075 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5076 return; /* do nothing if already down */
9a799d71
AK		 5077
5078 /* disable receives */
1f9ac57c 5079 hw->mac.ops.disable_rx(hw);
9a799d71 5080
2d39d576
YZ		 5081 /* disable all enabled rx queues */
5082 for (i = 0; i < adapter->num_rx_queues; i++)
5083 /* this call also flushes the previous write */
5084 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5085
032b4325 5086 usleep_range(10000, 20000);
9a799d71 5087
7f821875
JB		 5088 netif_tx_stop_all_queues(netdev);
5089
7086400d 5090 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5091 netif_carrier_off(netdev);
5092 netif_tx_disable(netdev);
5093
2a47fa45
JF		 5094 /* disable any upper devices */
5095 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5096 if (netif_is_macvlan(upper)) {
5097 struct macvlan_dev *vlan = netdev_priv(upper);
5098
5099 if (vlan->fwd_priv) {
5100 netif_tx_stop_all_queues(upper);
5101 netif_carrier_off(upper);
5102 netif_tx_disable(upper);
5103 }
5104 }
5105 }
5106
c0dfb90e
JF		 5107 ixgbe_irq_disable(adapter);
5108
5109 ixgbe_napi_disable_all(adapter);
5110
d034acf1
AD		 5111 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5112 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5113 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5114
5115 del_timer_sync(&adapter->service_timer);
5116
34cecbbf 5117 if (adapter->num_vfs) {
8e34d1aa
AD		 5118 /* Clear EITR Select mapping */
5119 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5120
5121 /* Mark all the VFs as inactive */
5122 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5123 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5124
34cecbbf
AD		 5125 /* ping all the active vfs to let them know we are going down */
5126 ixgbe_ping_all_vfs(adapter);
5127
5128 /* Disable all VFTE/VFRE TX/RX */
5129 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5130 }
5131
7f821875
JB		 5132 /* disable transmits in the hardware now that interrupts are off */
5133 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5134 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5135 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5136 }
34cecbbf 5137
9a75a1ac 5138 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5139 switch (hw->mac.type) {
5140 case ixgbe_mac_82599EB:
b93a2226 5141 case ixgbe_mac_X540:
9a75a1ac
DS		 5142 case ixgbe_mac_X550:
5143 case ixgbe_mac_X550EM_x:
88512539 5144 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5145 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5146 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5147 break;
5148 default:
5149 break;
5150 }
7f821875 5151
6f4a0e45
PL		 5152 if (!pci_channel_offline(adapter->pdev))
5153 ixgbe_reset(adapter);
c6ecf39a 5154
ec74a471
ET		 5155 /* power down the optics for 82599 SFP+ fiber */
5156 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5157 hw->mac.ops.disable_tx_laser(hw);
5158
9a799d71
AK		 5159 ixgbe_clean_all_tx_rings(adapter);
5160 ixgbe_clean_all_rx_rings(adapter);
5161
5dd2d332 5162#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5163 /* since we reset the hardware DCA settings were cleared */
e35ec126 5164 ixgbe_setup_dca(adapter);
96b0e0f6 5165#endif
9a799d71
AK		 5166}
5167
9a799d71
AK		 5168/**
5169 * ixgbe_tx_timeout - Respond to a Tx Hang
5170 * @netdev: network interface device structure
5171 **/
5172static void ixgbe_tx_timeout(struct net_device *netdev)
5173{
5174 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5175
5176 /* Do the reset outside of interrupt context */
c83c6cbd 5177 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5178}
5179
9a799d71
AK		 5180/**
5181 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5182 * @adapter: board private structure to initialize
5183 *
5184 * ixgbe_sw_init initializes the Adapter private data structure.
5185 * Fields are initialized based on PCI device information and
5186 * OS network device settings (MTU size).
5187 **/
9f9a12f8 5188static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5189{
5190 struct ixgbe_hw *hw = &adapter->hw;
5191 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5192 unsigned int rss, fdir;
cb6d0f5e 5193 u32 fwsm;
7a6b6f51 5194#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5195 int j;
5196 struct tc_configuration *tc;
5197#endif
021230d4 5198
c44ade9e
JB		 5199 /* PCI config space info */
5200
5201 hw->vendor_id = pdev->vendor;
5202 hw->device_id = pdev->device;
5203 hw->revision_id = pdev->revision;
5204 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5205 hw->subsystem_device_id = pdev->subsystem_device;
5206
8fc3bb6d 5207 /* Set common capability flags and settings */
0f9b232b 5208 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5209 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5210 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5211 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5212 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5213 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5214 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5215 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5216 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5217#ifdef CONFIG_IXGBE_DCA
5218 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5219#endif
5220#ifdef IXGBE_FCOE
5221 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5222 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5223#ifdef CONFIG_IXGBE_DCB
5224 /* Default traffic class to use for FCoE */
5225 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5226#endif /* CONFIG_IXGBE_DCB */
5227#endif /* IXGBE_FCOE */
5228
5d7daa35
JK		 5229 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5230 hw->mac.num_rar_entries,
5231 GFP_ATOMIC);
5232
8fc3bb6d 5233 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5234 switch (hw->mac.type) {
5235 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5236 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5237 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5238
bf069c97
DS		 5239 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5240 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5241
49c7ffbe 5242 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5243 adapter->ring_feature[RING_F_FDIR].limit = 0;
5244 adapter->atr_sample_rate = 0;
5245 adapter->fdir_pballoc = 0;
5246#ifdef IXGBE_FCOE
5247 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5248 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5249#ifdef CONFIG_IXGBE_DCB
5250 adapter->fcoe.up = 0;
5251#endif /* IXGBE_DCB */
5252#endif /* IXGBE_FCOE */
5253 break;
5254 case ixgbe_mac_82599EB:
5255 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5256 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5257 break;
b93a2226 5258 case ixgbe_mac_X540:
cb6d0f5e
JK		 5259 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5260 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5261 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5262 break;
9a75a1ac
DS		 5263 case ixgbe_mac_X550EM_x:
5264 case ixgbe_mac_X550:
5265#ifdef CONFIG_IXGBE_DCA
5266 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5267#endif
5268 break;
bd508178
AD		 5269 default:
5270 break;
f8212f97 5271 }
2f90b865 5272
7c8ae65a
AD		 5273#ifdef IXGBE_FCOE
5274 /* FCoE support exists, always init the FCoE lock */
5275 spin_lock_init(&adapter->fcoe.lock);
5276
5277#endif
1fc5f038
AD		 5278 /* n-tuple support exists, always init our spinlock */
5279 spin_lock_init(&adapter->fdir_perfect_lock);
5280
7a6b6f51 5281#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5282 switch (hw->mac.type) {
5283 case ixgbe_mac_X540:
9a75a1ac
DS		 5284 case ixgbe_mac_X550:
5285 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5286 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5287 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5288 break;
5289 default:
5290 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5291 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5292 break;
5293 }
5294
2f90b865
AD		 5295 /* Configure DCB traffic classes */
5296 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5297 tc = &adapter->dcb_cfg.tc_config[j];
5298 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5299 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5300 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5301 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5302 tc->dcb_pfc = pfc_disabled;
5303 }
4de2a022
JF		 5304
5305 /* Initialize default user to priority mapping, UPx->TC0 */
5306 tc = &adapter->dcb_cfg.tc_config[0];
5307 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5308 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5309
2f90b865
AD		 5310 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5311 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5312 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5313 adapter->dcb_set_bitmap = 0x00;
3032309b 5314 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5315 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5316 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5317
5318#endif
9a799d71
AK		 5319
5320 /* default flow control settings */
cd7664f6 5321 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5322 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5323 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5324 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5325 hw->fc.send_xon = true;
73d80953 5326 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5327
99d74487 5328#ifdef CONFIG_PCI_IOV
170e8543
JK		 5329 if (max_vfs > 0)
5330 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5331
99d74487 5332 /* assign number of SR-IOV VFs */
170e8543 5333 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5334 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5335 adapter->num_vfs = 0;
5336 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5337 } else {
5338 adapter->num_vfs = max_vfs;
5339 }
5340 }
5341#endif /* CONFIG_PCI_IOV */
99d74487 5342
30efa5a3 5343 /* enable itr by default in dynamic mode */
f7554a2b 5344 adapter->rx_itr_setting = 1;
f7554a2b 5345 adapter->tx_itr_setting = 1;
30efa5a3 5346
30efa5a3
JB		 5347 /* set default ring sizes */
5348 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5349 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5350
bd198058 5351 /* set default work limits */
59224555 5352 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5353
9a799d71 5354 /* initialize eeprom parameters */
c44ade9e 5355 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5356 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5357 return -EIO;
5358 }
5359
2a47fa45
JF		 5360 /* PF holds first pool slot */
5361 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5362 set_bit(__IXGBE_DOWN, &adapter->state);
5363
5364 return 0;
5365}
5366
5367/**
5368 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5369 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5370 *
5371 * Return 0 on success, negative on failure
5372 **/
b6ec895e 5373int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5374{
b6ec895e 5375 struct device *dev = tx_ring->dev;
de88eeeb 5376 int orig_node = dev_to_node(dev);
ca8dfe25 5377 int ring_node = -1;
9a799d71
AK		 5378 int size;
5379
3a581073 5380 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5381
5382 if (tx_ring->q_vector)
ca8dfe25 5383 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5384
ca8dfe25 5385 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5386 if (!tx_ring->tx_buffer_info)
89bf67f1 5387 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5388 if (!tx_ring->tx_buffer_info)
5389 goto err;
9a799d71 5390
827da44c
JS		 5391 u64_stats_init(&tx_ring->syncp);
5392
9a799d71 5393 /* round up to nearest 4K */
12207e49 5394 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5395 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5396
ca8dfe25 5397 set_dev_node(dev, ring_node);
de88eeeb
AD		 5398 tx_ring->desc = dma_alloc_coherent(dev,
5399 tx_ring->size,
5400 &tx_ring->dma,
5401 GFP_KERNEL);
5402 set_dev_node(dev, orig_node);
5403 if (!tx_ring->desc)
5404 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5405 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5406 if (!tx_ring->desc)
5407 goto err;
9a799d71 5408
3a581073
JB		 5409 tx_ring->next_to_use = 0;
5410 tx_ring->next_to_clean = 0;
9a799d71 5411 return 0;
e01c31a5
JB		 5412
5413err:
5414 vfree(tx_ring->tx_buffer_info);
5415 tx_ring->tx_buffer_info = NULL;
b6ec895e 5416 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5417 return -ENOMEM;
9a799d71
AK		 5418}
5419
69888674
AD		 5420/**
5421 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5422 * @adapter: board private structure
5423 *
5424 * If this function returns with an error, then it's possible one or
5425 * more of the rings is populated (while the rest are not). It is the
5426 * callers duty to clean those orphaned rings.
5427 *
5428 * Return 0 on success, negative on failure
5429 **/
5430static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5431{
5432 int i, err = 0;
5433
5434 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5435 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5436 if (!err)
5437 continue;
de3d5b94 5438
396e799c 5439 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5440 goto err_setup_tx;
69888674
AD		 5441 }
5442
de3d5b94
AD		 5443 return 0;
5444err_setup_tx:
5445 /* rewind the index freeing the rings as we go */
5446 while (i--)
5447 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5448 return err;
5449}
5450
9a799d71
AK		 5451/**
5452 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5453 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5454 *
5455 * Returns 0 on success, negative on failure
5456 **/
b6ec895e 5457int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5458{
b6ec895e 5459 struct device *dev = rx_ring->dev;
de88eeeb 5460 int orig_node = dev_to_node(dev);
ca8dfe25 5461 int ring_node = -1;
021230d4 5462 int size;
9a799d71 5463
3a581073 5464 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5465
5466 if (rx_ring->q_vector)
ca8dfe25 5467 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5468
ca8dfe25 5469 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5470 if (!rx_ring->rx_buffer_info)
89bf67f1 5471 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5472 if (!rx_ring->rx_buffer_info)
5473 goto err;
9a799d71 5474
827da44c
JS		 5475 u64_stats_init(&rx_ring->syncp);
5476
9a799d71 5477 /* Round up to nearest 4K */
3a581073
JB		 5478 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5479 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5480
ca8dfe25 5481 set_dev_node(dev, ring_node);
de88eeeb
AD		 5482 rx_ring->desc = dma_alloc_coherent(dev,
5483 rx_ring->size,
5484 &rx_ring->dma,
5485 GFP_KERNEL);
5486 set_dev_node(dev, orig_node);
5487 if (!rx_ring->desc)
5488 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5489 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5490 if (!rx_ring->desc)
5491 goto err;
9a799d71 5492
3a581073
JB		 5493 rx_ring->next_to_clean = 0;
5494 rx_ring->next_to_use = 0;
9a799d71
AK		 5495
5496 return 0;
b6ec895e
AD		 5497err:
5498 vfree(rx_ring->rx_buffer_info);
5499 rx_ring->rx_buffer_info = NULL;
5500 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5501 return -ENOMEM;
9a799d71
AK		 5502}
5503
69888674
AD		 5504/**
5505 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5506 * @adapter: board private structure
5507 *
5508 * If this function returns with an error, then it's possible one or
5509 * more of the rings is populated (while the rest are not). It is the
5510 * callers duty to clean those orphaned rings.
5511 *
5512 * Return 0 on success, negative on failure
5513 **/
69888674
AD		 5514static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5515{
5516 int i, err = 0;
5517
5518 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5519 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5520 if (!err)
5521 continue;
de3d5b94 5522
396e799c 5523 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5524 goto err_setup_rx;
69888674
AD		 5525 }
5526
7c8ae65a
AD		 5527#ifdef IXGBE_FCOE
5528 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5529 if (!err)
5530#endif
5531 return 0;
de3d5b94
AD		 5532err_setup_rx:
5533 /* rewind the index freeing the rings as we go */
5534 while (i--)
5535 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5536 return err;
5537}
5538
9a799d71
AK		 5539/**
5540 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5541 * @tx_ring: Tx descriptor ring for a specific queue
5542 *
5543 * Free all transmit software resources
5544 **/
b6ec895e 5545void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5546{
b6ec895e 5547 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5548
5549 vfree(tx_ring->tx_buffer_info);
5550 tx_ring->tx_buffer_info = NULL;
5551
b6ec895e
AD		 5552 /* if not set, then don't free */
5553 if (!tx_ring->desc)
5554 return;
5555
5556 dma_free_coherent(tx_ring->dev, tx_ring->size,
5557 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5558
5559 tx_ring->desc = NULL;
5560}
5561
5562/**
5563 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5564 * @adapter: board private structure
5565 *
5566 * Free all transmit software resources
5567 **/
5568static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5569{
5570 int i;
5571
5572 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5573 if (adapter->tx_ring[i]->desc)
b6ec895e 5574 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5575}
5576
5577/**
b4617240 5578 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5579 * @rx_ring: ring to clean the resources from
5580 *
5581 * Free all receive software resources
5582 **/
b6ec895e 5583void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5584{
b6ec895e 5585 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5586
5587 vfree(rx_ring->rx_buffer_info);
5588 rx_ring->rx_buffer_info = NULL;
5589
b6ec895e
AD		 5590 /* if not set, then don't free */
5591 if (!rx_ring->desc)
5592 return;
5593
5594 dma_free_coherent(rx_ring->dev, rx_ring->size,
5595 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5596
5597 rx_ring->desc = NULL;
5598}
5599
5600/**
5601 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5602 * @adapter: board private structure
5603 *
5604 * Free all receive software resources
5605 **/
5606static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5607{
5608 int i;
5609
7c8ae65a
AD		 5610#ifdef IXGBE_FCOE
5611 ixgbe_free_fcoe_ddp_resources(adapter);
5612
5613#endif
9a799d71 5614 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5615 if (adapter->rx_ring[i]->desc)
b6ec895e 5616 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5617}
5618
9a799d71
AK		 5619/**
5620 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5621 * @netdev: network interface device structure
5622 * @new_mtu: new value for maximum frame size
5623 *
5624 * Returns 0 on success, negative on failure
5625 **/
5626static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5627{
5628 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5629 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5630
42c783c5 5631 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5632 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5633 return -EINVAL;
5634
5635 /*
872844dd
AD		 5636 * For 82599EB we cannot allow legacy VFs to enable their receive
5637 * paths when MTU greater than 1500 is configured. So display a
5638 * warning that legacy VFs will be disabled.
655309e9
AD		 5639 */
5640 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5641 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5642 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5643 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5644
396e799c 5645 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5646
021230d4 5647 /* must set new MTU before calling down or up */
9a799d71
AK		 5648 netdev->mtu = new_mtu;
5649
d4f80882
AV		 5650 if (netif_running(netdev))
5651 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5652
5653 return 0;
5654}
5655
5656/**
5657 * ixgbe_open - Called when a network interface is made active
5658 * @netdev: network interface device structure
5659 *
5660 * Returns 0 on success, negative value on failure
5661 *
5662 * The open entry point is called when a network interface is made
5663 * active by the system (IFF_UP). At this point all resources needed
5664 * for transmit and receive operations are allocated, the interrupt
5665 * handler is registered with the OS, the watchdog timer is started,
5666 * and the stack is notified that the interface is ready.
5667 **/
5668static int ixgbe_open(struct net_device *netdev)
5669{
5670 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5671 int err, queues;
4bebfaa5
AK		 5672
5673 /* disallow open during test */
5674 if (test_bit(__IXGBE_TESTING, &adapter->state))
5675 return -EBUSY;
9a799d71 5676
54386467
JB		 5677 netif_carrier_off(netdev);
5678
9a799d71
AK		 5679 /* allocate transmit descriptors */
5680 err = ixgbe_setup_all_tx_resources(adapter);
5681 if (err)
5682 goto err_setup_tx;
5683
9a799d71
AK		 5684 /* allocate receive descriptors */
5685 err = ixgbe_setup_all_rx_resources(adapter);
5686 if (err)
5687 goto err_setup_rx;
5688
5689 ixgbe_configure(adapter);
5690
021230d4 5691 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5692 if (err)
5693 goto err_req_irq;
5694
ac802f5d 5695 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5696 if (adapter->num_rx_pools > 1)
5697 queues = adapter->num_rx_queues_per_pool;
5698 else
5699 queues = adapter->num_tx_queues;
5700
5701 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5702 if (err)
5703 goto err_set_queues;
5704
2a47fa45
JF		 5705 if (adapter->num_rx_pools > 1 &&
5706 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5707 queues = IXGBE_MAX_L2A_QUEUES;
5708 else
5709 queues = adapter->num_rx_queues;
5710 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5711 if (err)
5712 goto err_set_queues;
5713
1a71ab24 5714 ixgbe_ptp_init(adapter);
1a71ab24 5715
c7ccde0f 5716 ixgbe_up_complete(adapter);
9a799d71 5717
3f207800
DS		 5718#if IS_ENABLED(CONFIG_IXGBE_VXLAN)
5719 vxlan_get_rx_port(netdev);
5720
5721#endif
9a799d71
AK		 5722 return 0;
5723
ac802f5d
AD		 5724err_set_queues:
5725 ixgbe_free_irq(adapter);
9a799d71 5726err_req_irq:
a20a1199 5727 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5728err_setup_rx:
a20a1199 5729 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5730err_setup_tx:
9a799d71
AK		 5731 ixgbe_reset(adapter);
5732
5733 return err;
5734}
5735
a0cccce2
JK		 5736static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5737{
5738 ixgbe_ptp_suspend(adapter);
5739
5740 ixgbe_down(adapter);
5741 ixgbe_free_irq(adapter);
5742
5743 ixgbe_free_all_tx_resources(adapter);
5744 ixgbe_free_all_rx_resources(adapter);
5745}
5746
9a799d71
AK		 5747/**
5748 * ixgbe_close - Disables a network interface
5749 * @netdev: network interface device structure
5750 *
5751 * Returns 0, this is not allowed to fail
5752 *
5753 * The close entry point is called when an interface is de-activated
5754 * by the OS. The hardware is still under the drivers control, but
5755 * needs to be disabled. A global MAC reset is issued to stop the
5756 * hardware, and all transmit and receive resources are freed.
5757 **/
5758static int ixgbe_close(struct net_device *netdev)
5759{
5760 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5761
1a71ab24 5762 ixgbe_ptp_stop(adapter);
1a71ab24 5763
a0cccce2 5764 ixgbe_close_suspend(adapter);
9a799d71 5765
e4911d57
AD		 5766 ixgbe_fdir_filter_exit(adapter);
5767
5eba3699 5768 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5769
5770 return 0;
5771}
5772
b3c8b4ba
AD		 5773#ifdef CONFIG_PM
5774static int ixgbe_resume(struct pci_dev *pdev)
5775{
c60fbb00
AD		 5776 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5777 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5778 u32 err;
5779
0391bbe3 5780 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5781 pci_set_power_state(pdev, PCI_D0);
5782 pci_restore_state(pdev);
656ab817
DS		 5783 /*
5784 * pci_restore_state clears dev->state_saved so call
5785 * pci_save_state to restore it.
5786 */
5787 pci_save_state(pdev);
9ce77666 5788
5789 err = pci_enable_device_mem(pdev);
b3c8b4ba 5790 if (err) {
849c4542 5791 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5792 return err;
5793 }
4e857c58 5794 smp_mb__before_atomic();
41c62843 5795 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5796 pci_set_master(pdev);
5797
dd4d8ca6 5798 pci_wake_from_d3(pdev, false);
b3c8b4ba 5799
b3c8b4ba
AD		 5800 ixgbe_reset(adapter);
5801
495dce12
WJP		 5802 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5803
ac802f5d
AD		 5804 rtnl_lock();
5805 err = ixgbe_init_interrupt_scheme(adapter);
5806 if (!err && netif_running(netdev))
c60fbb00 5807 err = ixgbe_open(netdev);
ac802f5d
AD		 5808
5809 rtnl_unlock();
5810
5811 if (err)
5812 return err;
b3c8b4ba
AD		 5813
5814 netif_device_attach(netdev);
5815
5816 return 0;
5817}
b3c8b4ba 5818#endif /* CONFIG_PM */
9d8d05ae
RW		 5819
5820static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5821{
c60fbb00
AD		 5822 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5823 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5824 struct ixgbe_hw *hw = &adapter->hw;
5825 u32 ctrl, fctrl;
5826 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5827#ifdef CONFIG_PM
5828 int retval = 0;
5829#endif
5830
5831 netif_device_detach(netdev);
5832
499ab5cc 5833 rtnl_lock();
a0cccce2
JK		 5834 if (netif_running(netdev))
5835 ixgbe_close_suspend(adapter);
499ab5cc 5836 rtnl_unlock();
b3c8b4ba 5837
5f5ae6fc
AD		 5838 ixgbe_clear_interrupt_scheme(adapter);
5839
b3c8b4ba
AD		 5840#ifdef CONFIG_PM
5841 retval = pci_save_state(pdev);
5842 if (retval)
5843 return retval;
4df10466 5844
b3c8b4ba 5845#endif
f4f1040a
JK		 5846 if (hw->mac.ops.stop_link_on_d3)
5847 hw->mac.ops.stop_link_on_d3(hw);
5848
e8e26350
PW		 5849 if (wufc) {
5850 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5851
ec74a471
ET		 5852 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5853 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5854 hw->mac.ops.enable_tx_laser(hw);
5855
e8e26350
PW		 5856 /* turn on all-multi mode if wake on multicast is enabled */
5857 if (wufc & IXGBE_WUFC_MC) {
5858 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5859 fctrl |= IXGBE_FCTRL_MPE;
5860 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5861 }
5862
5863 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5864 ctrl |= IXGBE_CTRL_GIO_DIS;
5865 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5866
5867 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5868 } else {
5869 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5870 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5871 }
5872
bd508178
AD		 5873 switch (hw->mac.type) {
5874 case ixgbe_mac_82598EB:
dd4d8ca6 5875 pci_wake_from_d3(pdev, false);
bd508178
AD		 5876 break;
5877 case ixgbe_mac_82599EB:
b93a2226 5878 case ixgbe_mac_X540:
9a75a1ac
DS		 5879 case ixgbe_mac_X550:
5880 case ixgbe_mac_X550EM_x:
bd508178
AD		 5881 pci_wake_from_d3(pdev, !!wufc);
5882 break;
5883 default:
5884 break;
5885 }
b3c8b4ba 5886
9d8d05ae
RW		 5887 *enable_wake = !!wufc;
5888
b3c8b4ba
AD		 5889 ixgbe_release_hw_control(adapter);
5890
41c62843
MR		 5891 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5892 pci_disable_device(pdev);
b3c8b4ba 5893
9d8d05ae
RW		 5894 return 0;
5895}
5896
5897#ifdef CONFIG_PM
5898static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5899{
5900 int retval;
5901 bool wake;
5902
5903 retval = __ixgbe_shutdown(pdev, &wake);
5904 if (retval)
5905 return retval;
5906
5907 if (wake) {
5908 pci_prepare_to_sleep(pdev);
5909 } else {
5910 pci_wake_from_d3(pdev, false);
5911 pci_set_power_state(pdev, PCI_D3hot);
5912 }
b3c8b4ba
AD		 5913
5914 return 0;
5915}
9d8d05ae 5916#endif /* CONFIG_PM */
b3c8b4ba
AD		 5917
5918static void ixgbe_shutdown(struct pci_dev *pdev)
5919{
9d8d05ae
RW		 5920 bool wake;
5921
5922 __ixgbe_shutdown(pdev, &wake);
5923
5924 if (system_state == SYSTEM_POWER_OFF) {
5925 pci_wake_from_d3(pdev, wake);
5926 pci_set_power_state(pdev, PCI_D3hot);
5927 }
b3c8b4ba
AD		 5928}
5929
9a799d71
AK		 5930/**
5931 * ixgbe_update_stats - Update the board statistics counters.
5932 * @adapter: board private structure
5933 **/
5934void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5935{
2d86f139 5936 struct net_device *netdev = adapter->netdev;
9a799d71 5937 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5938 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5939 u64 total_mpc = 0;
5940 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5941 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5942 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5943 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5944
d08935c2
DS		 5945 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5946 test_bit(__IXGBE_RESETTING, &adapter->state))
5947 return;
5948
94b982b2 5949 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5950 u64 rsc_count = 0;
94b982b2 5951 u64 rsc_flush = 0;
94b982b2 5952 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5953 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5954 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5955 }
5956 adapter->rsc_total_count = rsc_count;
5957 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5958 }
5959
5b7da515
AD		 5960 for (i = 0; i < adapter->num_rx_queues; i++) {
5961 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5962 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5963 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5964 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5965 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5966 bytes += rx_ring->stats.bytes;
5967 packets += rx_ring->stats.packets;
5968 }
5969 adapter->non_eop_descs = non_eop_descs;
5970 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5971 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5972 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5973 netdev->stats.rx_bytes = bytes;
5974 netdev->stats.rx_packets = packets;
5975
5976 bytes = 0;
5977 packets = 0;
7ca3bc58 5978 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5979 for (i = 0; i < adapter->num_tx_queues; i++) {
5980 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5981 restart_queue += tx_ring->tx_stats.restart_queue;
5982 tx_busy += tx_ring->tx_stats.tx_busy;
5983 bytes += tx_ring->stats.bytes;
5984 packets += tx_ring->stats.packets;
5985 }
eb985f09 5986 adapter->restart_queue = restart_queue;
5b7da515
AD		 5987 adapter->tx_busy = tx_busy;
5988 netdev->stats.tx_bytes = bytes;
5989 netdev->stats.tx_packets = packets;
7ca3bc58 5990
7ca647bd 5991 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5992
5993 /* 8 register reads */
6f11eef7
AV		 5994 for (i = 0; i < 8; i++) {
5995 /* for packet buffers not used, the register should read 0 */
5996 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5997 missed_rx += mpc;
7ca647bd
JP		 5998 hwstats->mpc[i] += mpc;
5999 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6000 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6001 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6002 switch (hw->mac.type) {
6003 case ixgbe_mac_82598EB:
1a70db4b
ET		 6004 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6005 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6006 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6007 hwstats->pxonrxc[i] +=
6008 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6009 break;
6010 case ixgbe_mac_82599EB:
b93a2226 6011 case ixgbe_mac_X540:
9a75a1ac
DS		 6012 case ixgbe_mac_X550:
6013 case ixgbe_mac_X550EM_x:
bd508178
AD		 6014 hwstats->pxonrxc[i] +=
6015 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6016 break;
6017 default:
6018 break;
e8e26350 6019 }
6f11eef7 6020 }
1a70db4b
ET		 6021
6022 /*16 register reads */
6023 for (i = 0; i < 16; i++) {
6024 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6025 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6026 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6027 (hw->mac.type == ixgbe_mac_X540) ||
6028 (hw->mac.type == ixgbe_mac_X550) ||
6029 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6030 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6031 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6032 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6033 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6034 }
6035 }
6036
7ca647bd 6037 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6038 /* work around hardware counting issue */
7ca647bd 6039 hwstats->gprc -= missed_rx;
6f11eef7 6040
c84d324c
JF		 6041 ixgbe_update_xoff_received(adapter);
6042
6f11eef7 6043 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6044 switch (hw->mac.type) {
6045 case ixgbe_mac_82598EB:
6046 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6047 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6048 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6049 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6050 break;
b93a2226 6051 case ixgbe_mac_X540:
9a75a1ac
DS		 6052 case ixgbe_mac_X550:
6053 case ixgbe_mac_X550EM_x:
6054 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6055 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6056 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6057 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6058 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6059 case ixgbe_mac_82599EB:
a4d4f629
AD		 6060 for (i = 0; i < 16; i++)
6061 adapter->hw_rx_no_dma_resources +=
6062 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6063 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6064 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6065 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6066 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6067 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6068 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6069 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6070 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6071 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6072#ifdef IXGBE_FCOE
7ca647bd
JP		 6073 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6074 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6075 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6076 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6077 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6078 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6079 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6080 if (adapter->fcoe.ddp_pool) {
6081 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6082 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6083 unsigned int cpu;
6084 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6085 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6086 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6087 noddp += ddp_pool->noddp;
6088 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6089 }
5a1ee270
AD		 6090 hwstats->fcoe_noddp = noddp;
6091 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6092 }
6d45522c 6093#endif /* IXGBE_FCOE */
bd508178
AD		 6094 break;
6095 default:
6096 break;
e8e26350 6097 }
9a799d71 6098 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6099 hwstats->bprc += bprc;
6100 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6101 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6102 hwstats->mprc -= bprc;
6103 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6104 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6105 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6106 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6107 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6108 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6109 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6110 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6111 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6112 hwstats->lxontxc += lxon;
6f11eef7 6113 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6114 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6115 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6116 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6117 /*
6118 * 82598 errata - tx of flow control packets is included in tx counters
6119 */
6120 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6121 hwstats->gptc -= xon_off_tot;
6122 hwstats->mptc -= xon_off_tot;
6123 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6124 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6125 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6126 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6127 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6128 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6129 hwstats->ptc64 -= xon_off_tot;
6130 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6131 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6132 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6133 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6134 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6135 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6136
6137 /* Fill out the OS statistics structure */
7ca647bd 6138 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6139
6140 /* Rx Errors */
7ca647bd 6141 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6142 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6143 netdev->stats.rx_length_errors = hwstats->rlec;
6144 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6145 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6146}
6147
6148/**
d034acf1 6149 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6150 * @adapter: pointer to the device adapter structure
9a799d71 6151 **/
d034acf1 6152static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6153{
cf8280ee 6154 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6155 int i;
cf8280ee 6156
d034acf1
AD		 6157 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6158 return;
6159
6160 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6161
d034acf1 6162 /* if interface is down do nothing */
fe49f04a 6163 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6164 return;
6165
6166 /* do nothing if we are not using signature filters */
6167 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6168 return;
6169
6170 adapter->fdir_overflow++;
6171
93c52dd0
AD		 6172 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6173 for (i = 0; i < adapter->num_tx_queues; i++)
6174 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6175 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6176 /* re-enable flow director interrupts */
6177 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6178 } else {
6179 e_err(probe, "failed to finish FDIR re-initialization, "
6180 "ignored adding FDIR ATR filters\n");
6181 }
93c52dd0
AD		 6182}
6183
6184/**
6185 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6186 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6187 *
6188 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6189 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6190 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6191 * determine if a hang has occurred.
93c52dd0
AD		 6192 */
6193static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6194{
cf8280ee 6195 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6196 u64 eics = 0;
6197 int i;
cf8280ee 6198
09f40aed 6199 /* If we're down, removing or resetting, just bail */
93c52dd0 6200 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6201 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6202 test_bit(__IXGBE_RESETTING, &adapter->state))
6203 return;
22d5a71b 6204
93c52dd0
AD		 6205 /* Force detection of hung controller */
6206 if (netif_carrier_ok(adapter->netdev)) {
6207 for (i = 0; i < adapter->num_tx_queues; i++)
6208 set_check_for_tx_hang(adapter->tx_ring[i]);
6209 }
22d5a71b 6210
fe49f04a
AD		 6211 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6212 /*
6213 * for legacy and MSI interrupts don't set any bits
6214 * that are enabled for EIAM, because this operation
6215 * would set *both* EIMS and EICS for any bit in EIAM
6216 */
6217 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6218 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6219 } else {
6220 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6221 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6222 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6223 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6224 eics |= ((u64)1 << i);
6225 }
cf8280ee 6226 }
9a799d71 6227
93c52dd0 6228 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6229 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6230}
6231
e8e26350 6232/**
93c52dd0 6233 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6234 * @adapter: pointer to the device adapter structure
6235 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6236 **/
93c52dd0 6237static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6238{
e8e26350 6239 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6240 u32 link_speed = adapter->link_speed;
6241 bool link_up = adapter->link_up;
041441d0 6242 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6243
93c52dd0
AD		 6244 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6245 return;
6246
6247 if (hw->mac.ops.check_link) {
6248 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6249 } else {
93c52dd0
AD		 6250 /* always assume link is up, if no check link function */
6251 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6252 link_up = true;
c4cf55e5 6253 }
041441d0
AD		 6254
6255 if (adapter->ixgbe_ieee_pfc)
6256 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6257
3ebe8fde 6258 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6259 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6260 ixgbe_set_rx_drop_en(adapter);
6261 }
93c52dd0
AD		 6262
6263 if (link_up ||
6264 time_after(jiffies, (adapter->link_check_timeout +
6265 IXGBE_TRY_LINK_TIMEOUT))) {
6266 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6267 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6268 IXGBE_WRITE_FLUSH(hw);
6269 }
6270
6271 adapter->link_up = link_up;
6272 adapter->link_speed = link_speed;
e8e26350
PW		 6273}
6274
107d3018
AD		 6275static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6276{
6277#ifdef CONFIG_IXGBE_DCB
6278 struct net_device *netdev = adapter->netdev;
6279 struct dcb_app app = {
6280 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6281 .protocol = 0,
6282 };
6283 u8 up = 0;
6284
6285 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6286 up = dcb_ieee_getapp_mask(netdev, &app);
6287
6288 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6289#endif
6290}
6291
e8e26350 6292/**
93c52dd0
AD		 6293 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6294 * print link up message
49ce9c2c 6295 * @adapter: pointer to the device adapter structure
e8e26350 6296 **/
93c52dd0 6297static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6298{
93c52dd0 6299 struct net_device *netdev = adapter->netdev;
e8e26350 6300 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6301 struct net_device *upper;
6302 struct list_head *iter;
93c52dd0
AD		 6303 u32 link_speed = adapter->link_speed;
6304 bool flow_rx, flow_tx;
e8e26350 6305
93c52dd0
AD		 6306 /* only continue if link was previously down */
6307 if (netif_carrier_ok(netdev))
a985b6c3 6308 return;
63d6e1d8 6309
93c52dd0 6310 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6311
93c52dd0
AD		 6312 switch (hw->mac.type) {
6313 case ixgbe_mac_82598EB: {
6314 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6315 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6316 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6317 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6318 }
6319 break;
6320 case ixgbe_mac_X540:
9a75a1ac
DS		 6321 case ixgbe_mac_X550:
6322 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6323 case ixgbe_mac_82599EB: {
6324 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6325 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6326 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6327 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6328 }
6329 break;
6330 default:
6331 flow_tx = false;
6332 flow_rx = false;
6333 break;
e8e26350 6334 }
3a6a4eda 6335
6cb562d6
JK		 6336 adapter->last_rx_ptp_check = jiffies;
6337
8fecf67c 6338 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6339 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6340
93c52dd0
AD		 6341 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6342 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6343 "10 Gbps" :
6344 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6345 "1 Gbps" :
6346 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6347 "100 Mbps" :
6348 "unknown speed"))),
6349 ((flow_rx && flow_tx) ? "RX/TX" :
6350 (flow_rx ? "RX" :
6351 (flow_tx ? "TX" : "None"))));
e8e26350 6352
93c52dd0 6353 netif_carrier_on(netdev);
93c52dd0 6354 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6355
cdc04dcc
ET		 6356 /* enable transmits */
6357 netif_tx_wake_all_queues(adapter->netdev);
6358
6359 /* enable any upper devices */
6360 rtnl_lock();
6361 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6362 if (netif_is_macvlan(upper)) {
6363 struct macvlan_dev *vlan = netdev_priv(upper);
6364
6365 if (vlan->fwd_priv)
6366 netif_tx_wake_all_queues(upper);
6367 }
6368 }
6369 rtnl_unlock();
6370
107d3018
AD		 6371 /* update the default user priority for VFs */
6372 ixgbe_update_default_up(adapter);
6373
befa2af7
AD		 6374 /* ping all the active vfs to let them know link has changed */
6375 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6376}
6377
c4cf55e5 6378/**
93c52dd0
AD		 6379 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6380 * print link down message
49ce9c2c 6381 * @adapter: pointer to the adapter structure
c4cf55e5 6382 **/
581330ba 6383static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6384{
cf8280ee 6385 struct net_device *netdev = adapter->netdev;
c4cf55e5 6386 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6387
93c52dd0
AD		 6388 adapter->link_up = false;
6389 adapter->link_speed = 0;
cf8280ee 6390
93c52dd0
AD		 6391 /* only continue if link was up previously */
6392 if (!netif_carrier_ok(netdev))
6393 return;
264857b8 6394
93c52dd0
AD		 6395 /* poll for SFP+ cable when link is down */
6396 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6397 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6398
8fecf67c 6399 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6400 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6401
93c52dd0
AD		 6402 e_info(drv, "NIC Link is Down\n");
6403 netif_carrier_off(netdev);
befa2af7
AD		 6404
6405 /* ping all the active vfs to let them know link has changed */
6406 ixgbe_ping_all_vfs(adapter);
93c52dd0 6407}
e8e26350 6408
07923c17
ET		 6409static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6410{
6411 int i;
6412
6413 for (i = 0; i < adapter->num_tx_queues; i++) {
6414 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6415
6416 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6417 return true;
6418 }
6419
6420 return false;
6421}
6422
6423static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6424{
6425 struct ixgbe_hw *hw = &adapter->hw;
6426 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6427 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6428
6429 int i, j;
6430
6431 if (!adapter->num_vfs)
6432 return false;
6433
9a75a1ac
DS		 6434 /* resetting the PF is only needed for MAC before X550 */
6435 if (hw->mac.type >= ixgbe_mac_X550)
6436 return false;
6437
07923c17
ET		 6438 for (i = 0; i < adapter->num_vfs; i++) {
6439 for (j = 0; j < q_per_pool; j++) {
6440 u32 h, t;
6441
6442 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6443 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6444
6445 if (h != t)
6446 return true;
6447 }
6448 }
6449
6450 return false;
6451}
6452
93c52dd0
AD		 6453/**
6454 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6455 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6456 **/
6457static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6458{
93c52dd0 6459 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6460 if (ixgbe_ring_tx_pending(adapter) ||
6461 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6462 /* We've lost link, so the controller stops DMA,
6463 * but we've got queued Tx work that's never going
6464 * to get done, so reset controller to flush Tx.
6465 * (Do the reset outside of interrupt context).
6466 */
12ff3f3b 6467 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6468 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6469 }
c4cf55e5 6470 }
c4cf55e5
PWJ		 6471}
6472
9079e416
ET		 6473#ifdef CONFIG_PCI_IOV
6474static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6475 struct pci_dev *vfdev)
6476{
6477 if (!pci_wait_for_pending_transaction(vfdev))
6478 e_dev_warn("Issuing VFLR with pending transactions\n");
6479
6480 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6481 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6482
6483 msleep(100);
6484}
6485
6486static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6487{
6488 struct ixgbe_hw *hw = &adapter->hw;
6489 struct pci_dev *pdev = adapter->pdev;
6490 struct pci_dev *vfdev;
6491 u32 gpc;
6492 int pos;
6493 unsigned short vf_id;
6494
6495 if (!(netif_carrier_ok(adapter->netdev)))
6496 return;
6497
6498 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6499 if (gpc) /* If incrementing then no need for the check below */
6500 return;
6501 /* Check to see if a bad DMA write target from an errant or
6502 * malicious VF has caused a PCIe error. If so then we can
6503 * issue a VFLR to the offending VF(s) and then resume without
6504 * requesting a full slot reset.
6505 */
6506
6507 if (!pdev)
6508 return;
6509
6510 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6511 if (!pos)
6512 return;
6513
6514 /* get the device ID for the VF */
6515 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6516
6517 /* check status reg for all VFs owned by this PF */
6518 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6519 while (vfdev) {
6520 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6521 u16 status_reg;
6522
6523 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6524 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6525 /* issue VFLR */
6526 ixgbe_issue_vf_flr(adapter, vfdev);
6527 }
6528
6529 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6530 }
6531}
6532
a985b6c3
GR		 6533static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6534{
6535 u32 ssvpc;
6536
0584d999
GR		 6537 /* Do not perform spoof check for 82598 or if not in IOV mode */
6538 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6539 adapter->num_vfs == 0)
a985b6c3
GR		 6540 return;
6541
6542 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6543
6544 /*
6545 * ssvpc register is cleared on read, if zero then no
6546 * spoofed packets in the last interval.
6547 */
6548 if (!ssvpc)
6549 return;
6550
d6ea0754 6551 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6552}
9079e416
ET		 6553#else
6554static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6555{
6556}
6557
6558static void
6559ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6560{
6561}
6562#endif /* CONFIG_PCI_IOV */
6563
a985b6c3 6564
93c52dd0
AD		 6565/**
6566 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6567 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6568 **/
6569static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6570{
09f40aed 6571 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6572 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6573 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6574 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6575 return;
6576
6577 ixgbe_watchdog_update_link(adapter);
6578
6579 if (adapter->link_up)
6580 ixgbe_watchdog_link_is_up(adapter);
6581 else
6582 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6583
9079e416 6584 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6585 ixgbe_spoof_check(adapter);
9a799d71 6586 ixgbe_update_stats(adapter);
93c52dd0
AD		 6587
6588 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6589}
10eec955 6590
cf8280ee 6591/**
7086400d 6592 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6593 * @adapter: the ixgbe adapter structure
cf8280ee 6594 **/
7086400d 6595static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6596{
cf8280ee 6597 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6598 s32 err;
cf8280ee 6599
7086400d
AD		 6600 /* not searching for SFP so there is nothing to do here */
6601 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6602 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6603 return;
10eec955 6604
7086400d
AD		 6605 /* someone else is in init, wait until next service event */
6606 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6607 return;
cf8280ee 6608
7086400d
AD		 6609 err = hw->phy.ops.identify_sfp(hw);
6610 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6611 goto sfp_out;
264857b8 6612
7086400d
AD		 6613 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6614 /* If no cable is present, then we need to reset
6615 * the next time we find a good cable. */
6616 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6617 }
9a799d71 6618
7086400d
AD		 6619 /* exit on error */
6620 if (err)
6621 goto sfp_out;
e8e26350 6622
7086400d
AD		 6623 /* exit if reset not needed */
6624 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6625 goto sfp_out;
9a799d71 6626
7086400d 6627 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6628
7086400d
AD		 6629 /*
6630 * A module may be identified correctly, but the EEPROM may not have
6631 * support for that module. setup_sfp() will fail in that case, so
6632 * we should not allow that module to load.
6633 */
6634 if (hw->mac.type == ixgbe_mac_82598EB)
6635 err = hw->phy.ops.reset(hw);
6636 else
6637 err = hw->mac.ops.setup_sfp(hw);
6638
6639 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6640 goto sfp_out;
6641
6642 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6643 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6644
6645sfp_out:
6646 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6647
6648 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6649 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6650 e_dev_err("failed to initialize because an unsupported "
6651 "SFP+ module type was detected.\n");
6652 e_dev_err("Reload the driver after installing a "
6653 "supported module.\n");
6654 unregister_netdev(adapter->netdev);
bc59fcda 6655 }
7086400d 6656}
bc59fcda 6657
7086400d
AD		 6658/**
6659 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6660 * @adapter: the ixgbe adapter structure
7086400d
AD		 6661 **/
6662static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6663{
6664 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6665 u32 speed;
6666 bool autoneg = false;
7086400d
AD		 6667
6668 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6669 return;
6670
6671 /* someone else is in init, wait until next service event */
6672 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6673 return;
6674
6675 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6676
3d292265 6677 speed = hw->phy.autoneg_advertised;
ed33ff66 6678 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6679 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6680
6681 /* setup the highest link when no autoneg */
6682 if (!autoneg) {
6683 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6684 speed = IXGBE_LINK_SPEED_10GB_FULL;
6685 }
6686 }
6687
7086400d 6688 if (hw->mac.ops.setup_link)
fd0326f2 6689 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6690
6691 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6692 adapter->link_check_timeout = jiffies;
6693 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6694}
6695
6696/**
6697 * ixgbe_service_timer - Timer Call-back
6698 * @data: pointer to adapter cast into an unsigned long
6699 **/
6700static void ixgbe_service_timer(unsigned long data)
6701{
6702 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6703 unsigned long next_event_offset;
6704
6bb78cfb
AD		 6705 /* poll faster when waiting for link */
6706 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6707 next_event_offset = HZ / 10;
6708 else
6709 next_event_offset = HZ * 2;
83c61fa9 6710
7086400d
AD		 6711 /* Reset the timer */
6712 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6713
9079e416 6714 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6715}
6716
c83c6cbd
AD		 6717static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6718{
6719 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6720 return;
6721
6722 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6723
09f40aed 6724 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6725 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6726 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6727 test_bit(__IXGBE_RESETTING, &adapter->state))
6728 return;
6729
6730 ixgbe_dump(adapter);
6731 netdev_err(adapter->netdev, "Reset adapter\n");
6732 adapter->tx_timeout_count++;
6733
8f4c5c9f 6734 rtnl_lock();
c83c6cbd 6735 ixgbe_reinit_locked(adapter);
8f4c5c9f 6736 rtnl_unlock();
c83c6cbd
AD		 6737}
6738
7086400d
AD		 6739/**
6740 * ixgbe_service_task - manages and runs subtasks
6741 * @work: pointer to work_struct containing our data
6742 **/
6743static void ixgbe_service_task(struct work_struct *work)
6744{
6745 struct ixgbe_adapter *adapter = container_of(work,
6746 struct ixgbe_adapter,
6747 service_task);
b0483c8f
MR		 6748 if (ixgbe_removed(adapter->hw.hw_addr)) {
6749 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6750 rtnl_lock();
6751 ixgbe_down(adapter);
6752 rtnl_unlock();
6753 }
6754 ixgbe_service_event_complete(adapter);
6755 return;
6756 }
c83c6cbd 6757 ixgbe_reset_subtask(adapter);
7086400d
AD		 6758 ixgbe_sfp_detection_subtask(adapter);
6759 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6760 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6761 ixgbe_watchdog_subtask(adapter);
d034acf1 6762 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6763 ixgbe_check_hang_subtask(adapter);
891dc082 6764
8fecf67c 6765 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6766 ixgbe_ptp_overflow_check(adapter);
6767 ixgbe_ptp_rx_hang(adapter);
6768 }
7086400d
AD		 6769
6770 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6771}
6772
fd0db0ed
AD		 6773static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6774 struct ixgbe_tx_buffer *first,
244e27ad 6775 u8 *hdr_len)
897ab156 6776{
fd0db0ed 6777 struct sk_buff *skb = first->skb;
897ab156
AD		 6778 u32 vlan_macip_lens, type_tucmd;
6779 u32 mss_l4len_idx, l4len;
2049e1f6 6780 int err;
9a799d71 6781
8f4fbb9b
AD		 6782 if (skb->ip_summed != CHECKSUM_PARTIAL)
6783 return 0;
6784
897ab156
AD		 6785 if (!skb_is_gso(skb))
6786 return 0;
9a799d71 6787
2049e1f6
FR		 6788 err = skb_cow_head(skb, 0);
6789 if (err < 0)
6790 return err;
9a799d71 6791
897ab156
AD		 6792 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6793 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6794
a1108ffd 6795 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6796 struct iphdr *iph = ip_hdr(skb);
6797 iph->tot_len = 0;
6798 iph->check = 0;
6799 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6800 iph->daddr, 0,
6801 IPPROTO_TCP,
6802 0);
6803 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6804 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6805 IXGBE_TX_FLAGS_CSUM |
6806 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6807 } else if (skb_is_gso_v6(skb)) {
6808 ipv6_hdr(skb)->payload_len = 0;
6809 tcp_hdr(skb)->check =
6810 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6811 &ipv6_hdr(skb)->daddr,
6812 0, IPPROTO_TCP, 0);
244e27ad
AD		 6813 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6814 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6815 }
6816
091a6246 6817 /* compute header lengths */
897ab156
AD		 6818 l4len = tcp_hdrlen(skb);
6819 *hdr_len = skb_transport_offset(skb) + l4len;
6820
091a6246
AD		 6821 /* update gso size and bytecount with header size */
6822 first->gso_segs = skb_shinfo(skb)->gso_segs;
6823 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6824
c44f5f51 6825 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6826 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6827 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6828
6829 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6830 vlan_macip_lens = skb_network_header_len(skb);
6831 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6832 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6833
6834 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6835 mss_l4len_idx);
897ab156
AD		 6836
6837 return 1;
6838}
6839
244e27ad
AD		 6840static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6841 struct ixgbe_tx_buffer *first)
7ca647bd 6842{
fd0db0ed 6843 struct sk_buff *skb = first->skb;
897ab156
AD		 6844 u32 vlan_macip_lens = 0;
6845 u32 mss_l4len_idx = 0;
6846 u32 type_tucmd = 0;
7ca647bd 6847
897ab156 6848 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6849 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6850 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6851 return;
897ab156
AD		 6852 } else {
6853 u8 l4_hdr = 0;
244e27ad 6854 switch (first->protocol) {
a1108ffd 6855 case htons(ETH_P_IP):
897ab156
AD		 6856 vlan_macip_lens |= skb_network_header_len(skb);
6857 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6858 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6859 break;
a1108ffd 6860 case htons(ETH_P_IPV6):
897ab156
AD		 6861 vlan_macip_lens |= skb_network_header_len(skb);
6862 l4_hdr = ipv6_hdr(skb)->nexthdr;
6863 break;
6864 default:
6865 if (unlikely(net_ratelimit())) {
6866 dev_warn(tx_ring->dev,
6867 "partial checksum but proto=%x!\n",
244e27ad 6868 first->protocol);
897ab156 6869 }
7ca647bd
JP		 6870 break;
6871 }
897ab156
AD		 6872
6873 switch (l4_hdr) {
7ca647bd 6874 case IPPROTO_TCP:
897ab156
AD		 6875 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6876 mss_l4len_idx = tcp_hdrlen(skb) <<
6877 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6878 break;
6879 case IPPROTO_SCTP:
897ab156
AD		 6880 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6881 mss_l4len_idx = sizeof(struct sctphdr) <<
6882 IXGBE_ADVTXD_L4LEN_SHIFT;
6883 break;
6884 case IPPROTO_UDP:
6885 mss_l4len_idx = sizeof(struct udphdr) <<
6886 IXGBE_ADVTXD_L4LEN_SHIFT;
6887 break;
6888 default:
6889 if (unlikely(net_ratelimit())) {
6890 dev_warn(tx_ring->dev,
6891 "partial checksum but l4 proto=%x!\n",
244e27ad 6892 l4_hdr);
897ab156 6893 }
7ca647bd
JP		 6894 break;
6895 }
244e27ad
AD		 6896
6897 /* update TX checksum flag */
6898 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6899 }
6900
244e27ad 6901 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6902 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6903 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6904
897ab156
AD		 6905 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6906 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6907}
6908
472148c3
AD		 6909#define IXGBE_SET_FLAG(_input, _flag, _result) \
6910 ((_flag <= _result) ? \
6911 ((u32)(_input & _flag) * (_result / _flag)) : \
6912 ((u32)(_input & _flag) / (_flag / _result)))
6913
6914static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6915{
d3d00239 6916 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6917 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6918 IXGBE_ADVTXD_DCMD_DEXT |
6919 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6920
d3d00239 6921 /* set HW vlan bit if vlan is present */
472148c3
AD		 6922 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6923 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6924
d3d00239 6925 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6926 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6927 IXGBE_ADVTXD_DCMD_TSE);
6928
6929 /* set timestamp bit if present */
6930 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6931 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6932
62748b7b 6933 /* insert frame checksum */
472148c3 6934 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6935
d3d00239
AD		 6936 return cmd_type;
6937}
9a799d71 6938
729739b7
AD		 6939static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6940 u32 tx_flags, unsigned int paylen)
d3d00239 6941{
472148c3 6942 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6943
d3d00239 6944 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6945 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6946 IXGBE_TX_FLAGS_CSUM,
6947 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6948
93f5b3c1 6949 /* enble IPv4 checksum for TSO */
472148c3
AD		 6950 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6951 IXGBE_TX_FLAGS_IPV4,
6952 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6953
7f9643fd
AD		 6954 /*
6955 * Check Context must be set if Tx switch is enabled, which it
6956 * always is for case where virtual functions are running
6957 */
472148c3
AD		 6958 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6959 IXGBE_TX_FLAGS_CC,
6960 IXGBE_ADVTXD_CC);
7f9643fd 6961
472148c3 6962 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6963}
44df32c5 6964
2367a173
DB		 6965static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6966{
6967 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6968
6969 /* Herbert's original patch had:
6970 * smp_mb__after_netif_stop_queue();
6971 * but since that doesn't exist yet, just open code it.
6972 */
6973 smp_mb();
6974
6975 /* We need to check again in a case another CPU has just
6976 * made room available.
6977 */
6978 if (likely(ixgbe_desc_unused(tx_ring) < size))
6979 return -EBUSY;
6980
6981 /* A reprieve! - use start_queue because it doesn't call schedule */
6982 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6983 ++tx_ring->tx_stats.restart_queue;
6984 return 0;
6985}
6986
6987static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6988{
6989 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6990 return 0;
6991
6992 return __ixgbe_maybe_stop_tx(tx_ring, size);
6993}
6994
d3d00239
AD		 6995#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6996 IXGBE_TXD_CMD_RS)
6997
6998static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6999 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7000 const u8 hdr_len)
7001{
fd0db0ed 7002 struct sk_buff *skb = first->skb;
729739b7 7003 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7004 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7005 struct skb_frag_struct *frag;
7006 dma_addr_t dma;
7007 unsigned int data_len, size;
244e27ad 7008 u32 tx_flags = first->tx_flags;
472148c3 7009 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7010 u16 i = tx_ring->next_to_use;
d3d00239 7011
729739b7
AD		 7012 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7013
ec718254
AD		 7014 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7015
7016 size = skb_headlen(skb);
7017 data_len = skb->data_len;
729739b7 7018
d3d00239
AD		 7019#ifdef IXGBE_FCOE
7020 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7021 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7022 size -= sizeof(struct fcoe_crc_eof) - data_len;
7023 data_len = 0;
729739b7
AD		 7024 } else {
7025 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7026 }
7027 }
44df32c5 7028
d3d00239 7029#endif
729739b7 7030 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7031
ec718254 7032 tx_buffer = first;
9a799d71 7033
ec718254
AD		 7034 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7035 if (dma_mapping_error(tx_ring->dev, dma))
7036 goto dma_error;
7037
7038 /* record length, and DMA address */
7039 dma_unmap_len_set(tx_buffer, len, size);
7040 dma_unmap_addr_set(tx_buffer, dma, dma);
7041
7042 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7043
729739b7 7044 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7045 tx_desc->read.cmd_type_len =
472148c3 7046 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7047
d3d00239 7048 i++;
729739b7 7049 tx_desc++;
d3d00239 7050 if (i == tx_ring->count) {
e4f74028 7051 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7052 i = 0;
7053 }
ec718254 7054 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7055
7056 dma += IXGBE_MAX_DATA_PER_TXD;
7057 size -= IXGBE_MAX_DATA_PER_TXD;
7058
7059 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7060 }
e5a43549 7061
729739b7
AD		 7062 if (likely(!data_len))
7063 break;
9a799d71 7064
472148c3 7065 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7066
729739b7
AD		 7067 i++;
7068 tx_desc++;
7069 if (i == tx_ring->count) {
7070 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7071 i = 0;
7072 }
ec718254 7073 tx_desc->read.olinfo_status = 0;
9a799d71 7074
d3d00239 7075#ifdef IXGBE_FCOE
9e903e08 7076 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7077#else
9e903e08 7078 size = skb_frag_size(frag);
d3d00239
AD		 7079#endif
7080 data_len -= size;
9a799d71 7081
729739b7
AD		 7082 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7083 DMA_TO_DEVICE);
9a799d71 7084
729739b7 7085 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7086 }
9a799d71 7087
729739b7 7088 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7089 cmd_type |= size | IXGBE_TXD_CMD;
7090 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7091
091a6246 7092 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7093
d3d00239
AD		 7094 /* set the timestamp */
7095 first->time_stamp = jiffies;
9a799d71
AK		 7096
7097 /*
729739b7
AD		 7098 * Force memory writes to complete before letting h/w know there
7099 * are new descriptors to fetch. (Only applicable for weak-ordered
7100 * memory model archs, such as IA-64).
7101 *
7102 * We also need this memory barrier to make certain all of the
7103 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7104 */
7105 wmb();
7106
d3d00239
AD		 7107 /* set next_to_watch value indicating a packet is present */
7108 first->next_to_watch = tx_desc;
7109
729739b7
AD		 7110 i++;
7111 if (i == tx_ring->count)
7112 i = 0;
7113
7114 tx_ring->next_to_use = i;
7115
2367a173
DB		 7116 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7117
7118 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7119 writel(i, tx_ring->tail);
7120
7121 /* we need this if more than one processor can write to our tail
7122 * at a time, it synchronizes IO on IA64/Altix systems
7123 */
7124 mmiowb();
9c938cdd 7125 }
2367a173 7126
d3d00239
AD		 7127 return;
7128dma_error:
729739b7 7129 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7130
7131 /* clear dma mappings for failed tx_buffer_info map */
7132 for (;;) {
729739b7
AD		 7133 tx_buffer = &tx_ring->tx_buffer_info[i];
7134 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7135 if (tx_buffer == first)
d3d00239
AD		 7136 break;
7137 if (i == 0)
7138 i = tx_ring->count;
7139 i--;
7140 }
7141
d3d00239 7142 tx_ring->next_to_use = i;
9a799d71
AK		 7143}
7144
fd0db0ed 7145static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7146 struct ixgbe_tx_buffer *first)
69830529
AD		 7147{
7148 struct ixgbe_q_vector *q_vector = ring->q_vector;
7149 union ixgbe_atr_hash_dword input = { .dword = 0 };
7150 union ixgbe_atr_hash_dword common = { .dword = 0 };
7151 union {
7152 unsigned char *network;
7153 struct iphdr *ipv4;
7154 struct ipv6hdr *ipv6;
7155 } hdr;
ee9e0f0b 7156 struct tcphdr *th;
905e4a41 7157 __be16 vlan_id;
c4cf55e5 7158
69830529
AD		 7159 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7160 if (!q_vector)
7161 return;
7162
7163 /* do nothing if sampling is disabled */
7164 if (!ring->atr_sample_rate)
d3ead241 7165 return;
c4cf55e5 7166
69830529 7167 ring->atr_count++;
c4cf55e5 7168
69830529 7169 /* snag network header to get L4 type and address */
fd0db0ed 7170 hdr.network = skb_network_header(first->skb);
69830529
AD		 7171
7172 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 7173 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 7174 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 7175 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 7176 hdr.ipv4->protocol != IPPROTO_TCP))
7177 return;
ee9e0f0b 7178
fd0db0ed 7179 th = tcp_hdr(first->skb);
c4cf55e5 7180
66f32a8b
AD		 7181 /* skip this packet since it is invalid or the socket is closing */
7182 if (!th || th->fin)
69830529
AD		 7183 return;
7184
7185 /* sample on all syn packets or once every atr sample count */
7186 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7187 return;
7188
7189 /* reset sample count */
7190 ring->atr_count = 0;
7191
244e27ad 7192 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7193
7194 /*
7195 * src and dst are inverted, think how the receiver sees them
7196 *
7197 * The input is broken into two sections, a non-compressed section
7198 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7199 * is XORed together and stored in the compressed dword.
7200 */
7201 input.formatted.vlan_id = vlan_id;
7202
7203 /*
7204 * since src port and flex bytes occupy the same word XOR them together
7205 * and write the value to source port portion of compressed dword
7206 */
244e27ad 7207 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7208 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7209 else
244e27ad 7210 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7211 common.port.dst ^= th->source;
7212
a1108ffd 7213 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7214 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7215 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7216 } else {
7217 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7218 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7219 hdr.ipv6->saddr.s6_addr32[1] ^
7220 hdr.ipv6->saddr.s6_addr32[2] ^
7221 hdr.ipv6->saddr.s6_addr32[3] ^
7222 hdr.ipv6->daddr.s6_addr32[0] ^
7223 hdr.ipv6->daddr.s6_addr32[1] ^
7224 hdr.ipv6->daddr.s6_addr32[2] ^
7225 hdr.ipv6->daddr.s6_addr32[3];
7226 }
c4cf55e5
PWJ		 7227
7228 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7229 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7230 input, common, ring->queue_index);
c4cf55e5
PWJ		 7231}
7232
f663dd9a 7233static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7234 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7235{
f663dd9a
JW		 7236 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7237#ifdef IXGBE_FCOE
97488bd1
AD		 7238 struct ixgbe_adapter *adapter;
7239 struct ixgbe_ring_feature *f;
7240 int txq;
f663dd9a
JW		 7241#endif
7242
7243 if (fwd_adapter)
7244 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7245
7246#ifdef IXGBE_FCOE
5e09a105 7247
97488bd1
AD		 7248 /*
7249 * only execute the code below if protocol is FCoE
7250 * or FIP and we have FCoE enabled on the adapter
7251 */
7252 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7253 case htons(ETH_P_FCOE):
7254 case htons(ETH_P_FIP):
97488bd1 7255 adapter = netdev_priv(dev);
c087663e 7256
97488bd1
AD		 7257 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7258 break;
7259 default:
99932d4f 7260 return fallback(dev, skb);
97488bd1 7261 }
c087663e 7262
97488bd1 7263 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7264
97488bd1
AD		 7265 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7266 smp_processor_id();
56075a98 7267
97488bd1
AD		 7268 while (txq >= f->indices)
7269 txq -= f->indices;
c4cf55e5 7270
97488bd1 7271 return txq + f->offset;
f663dd9a 7272#else
99932d4f 7273 return fallback(dev, skb);
f663dd9a 7274#endif
09a3b1f8
SH		 7275}
7276
fc77dc3c 7277netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7278 struct ixgbe_adapter *adapter,
7279 struct ixgbe_ring *tx_ring)
9a799d71 7280{
d3d00239 7281 struct ixgbe_tx_buffer *first;
5f715823 7282 int tso;
d3d00239 7283 u32 tx_flags = 0;
a535c30e 7284 unsigned short f;
a535c30e 7285 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7286 __be16 protocol = skb->protocol;
63544e9c 7287 u8 hdr_len = 0;
5e09a105 7288
a535c30e
AD		 7289 /*
7290 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7291 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7292 * + 2 desc gap to keep tail from touching head,
7293 * + 1 desc for context descriptor,
7294 * otherwise try next time
7295 */
a535c30e
AD		 7296 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7297 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7298
a535c30e
AD		 7299 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7300 tx_ring->tx_stats.tx_busy++;
7301 return NETDEV_TX_BUSY;
7302 }
7303
fd0db0ed
AD		 7304 /* record the location of the first descriptor for this packet */
7305 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7306 first->skb = skb;
091a6246
AD		 7307 first->bytecount = skb->len;
7308 first->gso_segs = 1;
fd0db0ed 7309
66f32a8b 7310 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7311 if (skb_vlan_tag_present(skb)) {
7312 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7313 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7314 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7315 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7316 struct vlan_hdr *vhdr, _vhdr;
7317 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7318 if (!vhdr)
7319 goto out_drop;
7320
9e0c5648
AD		 7321 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7322 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7323 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7324 }
0213668f 7325 protocol = vlan_get_protocol(skb);
66f32a8b 7326
d5234933
MR		 7327 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7328 adapter->ptp_clock &&
7329 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7330 &adapter->state)) {
3a6a4eda
JK		 7331 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7332 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7333
7334 /* schedule check for Tx timestamp */
7335 adapter->ptp_tx_skb = skb_get(skb);
7336 adapter->ptp_tx_start = jiffies;
7337 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7338 }
3a6a4eda 7339
ff29a86e
JK		 7340 skb_tx_timestamp(skb);
7341
9e0c5648
AD		 7342#ifdef CONFIG_PCI_IOV
7343 /*
7344 * Use the l2switch_enable flag - would be false if the DMA
7345 * Tx switch had been disabled.
7346 */
7347 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7348 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7349
7350#endif
32701dc2 7351 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7352 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7353 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7354 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7355 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7356 tx_flags |= (skb->priority & 0x7) <<
7357 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7358 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7359 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7360
7361 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7362 goto out_drop;
7363 vhdr = (struct vlan_ethhdr *)skb->data;
7364 vhdr->h_vlan_TCI = htons(tx_flags >>
7365 IXGBE_TX_FLAGS_VLAN_SHIFT);
7366 } else {
7367 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7368 }
9a799d71 7369 }
eacd73f7 7370
244e27ad
AD		 7371 /* record initial flags and protocol */
7372 first->tx_flags = tx_flags;
7373 first->protocol = protocol;
7374
eacd73f7 7375#ifdef IXGBE_FCOE
66f32a8b 7376 /* setup tx offload for FCoE */
a1108ffd 7377 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7378 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7379 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7380 if (tso < 0)
7381 goto out_drop;
9a799d71 7382
66f32a8b 7383 goto xmit_fcoe;
eacd73f7 7384 }
9a799d71 7385
66f32a8b 7386#endif /* IXGBE_FCOE */
244e27ad 7387 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7388 if (tso < 0)
897ab156 7389 goto out_drop;
244e27ad
AD		 7390 else if (!tso)
7391 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7392
7393 /* add the ATR filter if ATR is on */
7394 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7395 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7396
7397#ifdef IXGBE_FCOE
7398xmit_fcoe:
7399#endif /* IXGBE_FCOE */
244e27ad 7400 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7401
9a799d71 7402 return NETDEV_TX_OK;
897ab156
AD		 7403
7404out_drop:
fd0db0ed
AD		 7405 dev_kfree_skb_any(first->skb);
7406 first->skb = NULL;
7407
897ab156 7408 return NETDEV_TX_OK;
9a799d71
AK		 7409}
7410
2a47fa45
JF		 7411static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7412 struct net_device *netdev,
7413 struct ixgbe_ring *ring)
84418e3b
AD		 7414{
7415 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7416 struct ixgbe_ring *tx_ring;
7417
a50c29dd
AD		 7418 /*
7419 * The minimum packet size for olinfo paylen is 17 so pad the skb
7420 * in order to meet this minimum size requirement.
7421 */
a94d9e22
AD		 7422 if (skb_put_padto(skb, 17))
7423 return NETDEV_TX_OK;
a50c29dd 7424
2a47fa45
JF		 7425 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7426
fc77dc3c 7427 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7428}
7429
2a47fa45
JF		 7430static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7431 struct net_device *netdev)
7432{
7433 return __ixgbe_xmit_frame(skb, netdev, NULL);
7434}
7435
9a799d71
AK		 7436/**
7437 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7438 * @netdev: network interface device structure
7439 * @p: pointer to an address structure
7440 *
7441 * Returns 0 on success, negative on failure
7442 **/
7443static int ixgbe_set_mac(struct net_device *netdev, void *p)
7444{
7445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7446 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7447 struct sockaddr *addr = p;
5d7daa35 7448 int ret;
9a799d71
AK		 7449
7450 if (!is_valid_ether_addr(addr->sa_data))
7451 return -EADDRNOTAVAIL;
7452
5d7daa35 7453 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7454 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7455 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7456
5d7daa35
JK		 7457 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7458 return ret > 0 ? 0 : ret;
9a799d71
AK		 7459}
7460
6b73e10d
BH		 7461static int
7462ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7463{
7464 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7465 struct ixgbe_hw *hw = &adapter->hw;
7466 u16 value;
7467 int rc;
7468
7469 if (prtad != hw->phy.mdio.prtad)
7470 return -EINVAL;
7471 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7472 if (!rc)
7473 rc = value;
7474 return rc;
7475}
7476
7477static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7478 u16 addr, u16 value)
7479{
7480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7481 struct ixgbe_hw *hw = &adapter->hw;
7482
7483 if (prtad != hw->phy.mdio.prtad)
7484 return -EINVAL;
7485 return hw->phy.ops.write_reg(hw, addr, devad, value);
7486}
7487
7488static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7489{
7490 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7491
3a6a4eda 7492 switch (cmd) {
3a6a4eda 7493 case SIOCSHWTSTAMP:
93501d48
JK		 7494 return ixgbe_ptp_set_ts_config(adapter, req);
7495 case SIOCGHWTSTAMP:
7496 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7497 default:
7498 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7499 }
6b73e10d
BH		 7500}
7501
0365e6e4
PW		 7502/**
7503 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7504 * netdev->dev_addrs
0365e6e4
PW		 7505 * @netdev: network interface device structure
7506 *
7507 * Returns non-zero on failure
7508 **/
7509static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7510{
7511 int err = 0;
7512 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7513 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7514
7fa7c9dc 7515 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7516 rtnl_lock();
7fa7c9dc 7517 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7518 rtnl_unlock();
7fa7c9dc
AD		 7519
7520 /* update SAN MAC vmdq pool selection */
7521 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7522 }
7523 return err;
7524}
7525
7526/**
7527 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7528 * netdev->dev_addrs
0365e6e4
PW		 7529 * @netdev: network interface device structure
7530 *
7531 * Returns non-zero on failure
7532 **/
7533static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7534{
7535 int err = 0;
7536 struct ixgbe_adapter *adapter = netdev_priv(dev);
7537 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7538
7539 if (is_valid_ether_addr(mac->san_addr)) {
7540 rtnl_lock();
7541 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7542 rtnl_unlock();
7543 }
7544 return err;
7545}
7546
9a799d71
AK		 7547#ifdef CONFIG_NET_POLL_CONTROLLER
7548/*
7549 * Polling 'interrupt' - used by things like netconsole to send skbs
7550 * without having to re-enable interrupts. It's not called while
7551 * the interrupt routine is executing.
7552 */
7553static void ixgbe_netpoll(struct net_device *netdev)
7554{
7555 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7556 int i;
9a799d71 7557
1a647bd2
AD		 7558 /* if interface is down do nothing */
7559 if (test_bit(__IXGBE_DOWN, &adapter->state))
7560 return;
7561
856f606e
AD		 7562 /* loop through and schedule all active queues */
7563 for (i = 0; i < adapter->num_q_vectors; i++)
7564 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 7565}
9a799d71 7566
581330ba 7567#endif
de1036b1
ED		 7568static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7569 struct rtnl_link_stats64 *stats)
7570{
7571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7572 int i;
7573
1a51502b 7574 rcu_read_lock();
de1036b1 7575 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7576 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7577 u64 bytes, packets;
7578 unsigned int start;
7579
1a51502b
ED		 7580 if (ring) {
7581 do {
57a7744e 7582 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7583 packets = ring->stats.packets;
7584 bytes = ring->stats.bytes;
57a7744e 7585 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7586 stats->rx_packets += packets;
7587 stats->rx_bytes += bytes;
7588 }
de1036b1 7589 }
1ac9ad13
ED		 7590
7591 for (i = 0; i < adapter->num_tx_queues; i++) {
7592 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7593 u64 bytes, packets;
7594 unsigned int start;
7595
7596 if (ring) {
7597 do {
57a7744e 7598 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7599 packets = ring->stats.packets;
7600 bytes = ring->stats.bytes;
57a7744e 7601 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7602 stats->tx_packets += packets;
7603 stats->tx_bytes += bytes;
7604 }
7605 }
1a51502b 7606 rcu_read_unlock();
de1036b1
ED		 7607 /* following stats updated by ixgbe_watchdog_task() */
7608 stats->multicast = netdev->stats.multicast;
7609 stats->rx_errors = netdev->stats.rx_errors;
7610 stats->rx_length_errors = netdev->stats.rx_length_errors;
7611 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7612 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7613 return stats;
7614}
7615
8af3c33f 7616#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7617/**
7618 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7619 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7620 * @tc: number of traffic classes currently enabled
7621 *
7622 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7623 * 802.1Q priority maps to a packet buffer that exists.
7624 */
7625static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7626{
7627 struct ixgbe_hw *hw = &adapter->hw;
7628 u32 reg, rsave;
7629 int i;
7630
7631 /* 82598 have a static priority to TC mapping that can not
7632 * be changed so no validation is needed.
7633 */
7634 if (hw->mac.type == ixgbe_mac_82598EB)
7635 return;
7636
7637 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7638 rsave = reg;
7639
7640 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7641 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7642
7643 /* If up2tc is out of bounds default to zero */
7644 if (up2tc > tc)
7645 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7646 }
7647
7648 if (reg != rsave)
7649 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7650
7651 return;
7652}
7653
02debdc9
AD		 7654/**
7655 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7656 * @adapter: Pointer to adapter struct
7657 *
7658 * Populate the netdev user priority to tc map
7659 */
7660static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7661{
7662 struct net_device *dev = adapter->netdev;
7663 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7664 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7665 u8 prio;
7666
7667 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7668 u8 tc = 0;
7669
7670 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7671 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7672 else if (ets)
7673 tc = ets->prio_tc[prio];
7674
7675 netdev_set_prio_tc_map(dev, prio, tc);
7676 }
7677}
7678
cca73c59 7679#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7680/**
7681 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7682 *
7683 * @netdev: net device to configure
7684 * @tc: number of traffic classes to enable
7685 */
7686int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7687{
8b1c0b24
JF		 7688 struct ixgbe_adapter *adapter = netdev_priv(dev);
7689 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7690 bool pools;
8b1c0b24 7691
8b1c0b24 7692 /* Hardware supports up to 8 traffic classes */
4de2a022 7693 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7694 (hw->mac.type == ixgbe_mac_82598EB &&
7695 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7696 return -EINVAL;
7697
2a47fa45
JF		 7698 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7699 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7700 return -EBUSY;
7701
8b1c0b24 7702 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7703 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7704 * hardware is not flexible enough to do this dynamically.
7705 */
7706 if (netif_running(dev))
7707 ixgbe_close(dev);
7708 ixgbe_clear_interrupt_scheme(adapter);
7709
cca73c59 7710#ifdef CONFIG_IXGBE_DCB
e7589eab 7711 if (tc) {
8b1c0b24 7712 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7713 ixgbe_set_prio_tc_map(adapter);
7714
e7589eab 7715 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7716
943561d3
AD		 7717 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7718 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7719 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7720 }
e7589eab 7721 } else {
8b1c0b24 7722 netdev_reset_tc(dev);
02debdc9 7723
943561d3
AD		 7724 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7725 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7726
7727 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7728
7729 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7730 adapter->dcb_cfg.pfc_mode_enable = false;
7731 }
7732
8b1c0b24 7733 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7734
7735#endif /* CONFIG_IXGBE_DCB */
7736 ixgbe_init_interrupt_scheme(adapter);
7737
8b1c0b24 7738 if (netif_running(dev))
cca73c59 7739 return ixgbe_open(dev);
8b1c0b24
JF		 7740
7741 return 0;
7742}
de1036b1 7743
da36b647
GR		 7744#ifdef CONFIG_PCI_IOV
7745void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7746{
7747 struct net_device *netdev = adapter->netdev;
7748
7749 rtnl_lock();
da36b647 7750 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7751 rtnl_unlock();
7752}
7753
7754#endif
082757af
DS		 7755void ixgbe_do_reset(struct net_device *netdev)
7756{
7757 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7758
7759 if (netif_running(netdev))
7760 ixgbe_reinit_locked(adapter);
7761 else
7762 ixgbe_reset(adapter);
7763}
7764
c8f44aff 7765static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7766 netdev_features_t features)
082757af
DS		 7767{
7768 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7769
082757af 7770 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7771 if (!(features & NETIF_F_RXCSUM))
7772 features &= ~NETIF_F_LRO;
082757af 7773
567d2de2
AD		 7774 /* Turn off LRO if not RSC capable */
7775 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7776 features &= ~NETIF_F_LRO;
8e2813f5 7777
567d2de2 7778 return features;
082757af
DS		 7779}
7780
c8f44aff 7781static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7782 netdev_features_t features)
082757af
DS		 7783{
7784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7785 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7786 bool need_reset = false;
7787
082757af 7788 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7789 if (!(features & NETIF_F_LRO)) {
7790 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7791 need_reset = true;
567d2de2
AD		 7792 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7793 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7794 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7795 if (adapter->rx_itr_setting == 1 ||
7796 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7797 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7798 need_reset = true;
7799 } else if ((changed ^ features) & NETIF_F_LRO) {
7800 e_info(probe, "rx-usecs set too low, "
7801 "disabling RSC\n");
082757af
DS		 7802 }
7803 }
7804
7805 /*
7806 * Check if Flow Director n-tuple support was enabled or disabled. If
7807 * the state changed, we need to reset.
7808 */
39cb681b
AD		 7809 switch (features & NETIF_F_NTUPLE) {
7810 case NETIF_F_NTUPLE:
567d2de2 7811 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7812 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7813 need_reset = true;
7814
567d2de2
AD		 7815 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7816 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7817 break;
7818 default:
7819 /* turn off perfect filters, enable ATR and reset */
7820 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7821 need_reset = true;
7822
7823 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7824
7825 /* We cannot enable ATR if SR-IOV is enabled */
7826 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7827 break;
7828
7829 /* We cannot enable ATR if we have 2 or more traffic classes */
7830 if (netdev_get_num_tc(netdev) > 1)
7831 break;
7832
7833 /* We cannot enable ATR if RSS is disabled */
7834 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7835 break;
7836
7837 /* A sample rate of 0 indicates ATR disabled */
7838 if (!adapter->atr_sample_rate)
7839 break;
7840
7841 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7842 break;
082757af
DS		 7843 }
7844
f646968f 7845 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7846 ixgbe_vlan_strip_enable(adapter);
7847 else
7848 ixgbe_vlan_strip_disable(adapter);
7849
3f2d1c0f
BG		 7850 if (changed & NETIF_F_RXALL)
7851 need_reset = true;
7852
567d2de2 7853 netdev->features = features;
082757af
DS		 7854 if (need_reset)
7855 ixgbe_do_reset(netdev);
7856
7857 return 0;
082757af
DS		 7858}
7859
3f207800
DS		 7860/**
7861 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
7862 * @dev: The port's netdev
7863 * @sa_family: Socket Family that VXLAN is notifiying us about
7864 * @port: New UDP port number that VXLAN started listening to
7865 **/
7866static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
7867 __be16 port)
7868{
7869 struct ixgbe_adapter *adapter = netdev_priv(dev);
7870 struct ixgbe_hw *hw = &adapter->hw;
7871 u16 new_port = ntohs(port);
7872
7873 if (sa_family == AF_INET6)
7874 return;
7875
7876 if (adapter->vxlan_port == new_port) {
7877 netdev_info(dev, "Port %d already offloaded\n", new_port);
7878 return;
7879 }
7880
7881 if (adapter->vxlan_port) {
7882 netdev_info(dev,
7883 "Hit Max num of UDP ports, not adding port %d\n",
7884 new_port);
7885 return;
7886 }
7887
7888 adapter->vxlan_port = new_port;
7889 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
7890}
7891
7892/**
7893 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
7894 * @dev: The port's netdev
7895 * @sa_family: Socket Family that VXLAN is notifying us about
7896 * @port: UDP port number that VXLAN stopped listening to
7897 **/
7898static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
7899 __be16 port)
7900{
7901 struct ixgbe_adapter *adapter = netdev_priv(dev);
7902 struct ixgbe_hw *hw = &adapter->hw;
7903 u16 new_port = ntohs(port);
7904
7905 if (sa_family == AF_INET6)
7906 return;
7907
7908 if (adapter->vxlan_port != new_port) {
7909 netdev_info(dev, "Port %d was not found, not deleting\n",
7910 new_port);
7911 return;
7912 }
7913
7914 adapter->vxlan_port = 0;
7915 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, 0);
7916}
7917
edc7d573 7918static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7919 struct net_device *dev,
f6f6424b 7920 const unsigned char *addr, u16 vid,
0f4b0add
JF		 7921 u16 flags)
7922{
bcfd3432 7923 /* guarantee we can provide a unique filter for the unicast address */
46acc460 7924 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 7925 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7926 return -ENOMEM;
0f4b0add
JF		 7927 }
7928
f6f6424b 7929 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 7930}
7931
219efe97
DS		 7932/**
7933 * ixgbe_configure_bridge_mode - set various bridge modes
7934 * @adapter - the private structure
7935 * @mode - requested bridge mode
7936 *
7937 * Configure some settings require for various bridge modes.
7938 **/
7939static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
7940 __u16 mode)
7941{
6d4c96ad
DS		 7942 struct ixgbe_hw *hw = &adapter->hw;
7943 unsigned int p, num_pools;
7944 u32 vmdctl;
7945
219efe97
DS		 7946 switch (mode) {
7947 case BRIDGE_MODE_VEPA:
6d4c96ad 7948 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 7949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 7950
7951 /* must enable Rx switching replication to allow multicast
7952 * packet reception on all VFs, and to enable source address
7953 * pruning.
7954 */
7955 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
7956 vmdctl |= IXGBE_VT_CTL_REPLEN;
7957 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
7958
7959 /* enable Rx source address pruning. Note, this requires
7960 * replication to be enabled or else it does nothing.
7961 */
7962 num_pools = adapter->num_vfs + adapter->num_rx_pools;
7963 for (p = 0; p < num_pools; p++) {
7964 if (hw->mac.ops.set_source_address_pruning)
7965 hw->mac.ops.set_source_address_pruning(hw,
7966 true,
7967 p);
7968 }
219efe97
DS		 7969 break;
7970 case BRIDGE_MODE_VEB:
6d4c96ad 7971 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 7972 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
7973 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 7974
7975 /* disable Rx switching replication unless we have SR-IOV
7976 * virtual functions
7977 */
7978 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
7979 if (!adapter->num_vfs)
7980 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
7981 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
7982
7983 /* disable Rx source address pruning, since we don't expect to
7984 * be receiving external loopback of our transmitted frames.
7985 */
7986 num_pools = adapter->num_vfs + adapter->num_rx_pools;
7987 for (p = 0; p < num_pools; p++) {
7988 if (hw->mac.ops.set_source_address_pruning)
7989 hw->mac.ops.set_source_address_pruning(hw,
7990 false,
7991 p);
7992 }
219efe97
DS		 7993 break;
7994 default:
7995 return -EINVAL;
7996 }
7997
7998 adapter->bridge_mode = mode;
7999
8000 e_info(drv, "enabling bridge mode: %s\n",
8001 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8002
8003 return 0;
8004}
8005
815cccbf 8006static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8007 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8008{
8009 struct ixgbe_adapter *adapter = netdev_priv(dev);
8010 struct nlattr *attr, *br_spec;
8011 int rem;
8012
8013 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8014 return -EOPNOTSUPP;
8015
8016 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8017 if (!br_spec)
8018 return -EINVAL;
815cccbf
JF		 8019
8020 nla_for_each_nested(attr, br_spec, rem) {
219efe97 8021 u32 status;
815cccbf 8022 __u16 mode;
815cccbf
JF		 8023
8024 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8025 continue;
8026
b7c1a314
TG		 8027 if (nla_len(attr) < sizeof(mode))
8028 return -EINVAL;
8029
815cccbf 8030 mode = nla_get_u16(attr);
219efe97
DS		 8031 status = ixgbe_configure_bridge_mode(adapter, mode);
8032 if (status)
8033 return status;
aa2bacb6
DS		 8034
8035 break;
815cccbf
JF		 8036 }
8037
8038 return 0;
8039}
8040
8041static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 8042 struct net_device *dev,
8043 u32 filter_mask)
815cccbf
JF		 8044{
8045 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8046
8047 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8048 return 0;
8049
aa2bacb6
DS		 8050 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
8051 adapter->bridge_mode, 0, 0);
815cccbf
JF		 8052}
8053
2a47fa45
JF		 8054static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8055{
8056 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8057 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8058 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8059 unsigned int limit;
2a47fa45
JF		 8060 int pool, err;
8061
aac2f1bf
JK		 8062 /* Hardware has a limited number of available pools. Each VF, and the
8063 * PF require a pool. Check to ensure we don't attempt to use more
8064 * then the available number of pools.
8065 */
8066 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8067 return ERR_PTR(-EINVAL);
8068
219354d4
JF		 8069#ifdef CONFIG_RPS
8070 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8071 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8072 vdev->name);
8073 return ERR_PTR(-EINVAL);
8074 }
8075#endif
2a47fa45 8076 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8077 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8078 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8079 netdev_info(pdev,
8080 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8081 pdev->name);
8082 return ERR_PTR(-EINVAL);
8083 }
8084
8085 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8086 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8087 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8088 return ERR_PTR(-EBUSY);
8089
8090 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
8091 if (!fwd_adapter)
8092 return ERR_PTR(-ENOMEM);
8093
8094 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8095 adapter->num_rx_pools++;
8096 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8097 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8098
8099 /* Enable VMDq flag so device will be set in VM mode */
8100 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8101 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8102 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8103
8104 /* Force reinit of ring allocation with VMDQ enabled */
8105 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8106 if (err)
8107 goto fwd_add_err;
8108 fwd_adapter->pool = pool;
8109 fwd_adapter->real_adapter = adapter;
8110 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8111 if (err)
8112 goto fwd_add_err;
8113 netif_tx_start_all_queues(vdev);
8114 return fwd_adapter;
8115fwd_add_err:
8116 /* unwind counter and free adapter struct */
8117 netdev_info(pdev,
8118 "%s: dfwd hardware acceleration failed\n", vdev->name);
8119 clear_bit(pool, &adapter->fwd_bitmask);
8120 adapter->num_rx_pools--;
8121 kfree(fwd_adapter);
8122 return ERR_PTR(err);
8123}
8124
8125static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8126{
8127 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8128 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8129 unsigned int limit;
2a47fa45
JF		 8130
8131 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8132 adapter->num_rx_pools--;
8133
51f3773b
JF		 8134 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8135 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8136 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8137 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8138 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8139 fwd_adapter->pool, adapter->num_rx_pools,
8140 fwd_adapter->rx_base_queue,
8141 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8142 adapter->fwd_bitmask);
8143 kfree(fwd_adapter);
8144}
8145
0edc3527 8146static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8147 .ndo_open = ixgbe_open,
0edc3527 8148 .ndo_stop = ixgbe_close,
00829823 8149 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8150 .ndo_select_queue = ixgbe_select_queue,
581330ba 8151 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8152 .ndo_validate_addr = eth_validate_addr,
8153 .ndo_set_mac_address = ixgbe_set_mac,
8154 .ndo_change_mtu = ixgbe_change_mtu,
8155 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8156 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8157 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8158 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8159 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8160 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8161 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8162 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 8163 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8164 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8165#ifdef CONFIG_IXGBE_DCB
24095aa3 8166 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8167#endif
0edc3527
SH		 8168#ifdef CONFIG_NET_POLL_CONTROLLER
8169 .ndo_poll_controller = ixgbe_netpoll,
8170#endif
e0d1095a 8171#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8172 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8173#endif
332d4a7d
YZ		 8174#ifdef IXGBE_FCOE
8175 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8176 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8177 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8178 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8179 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8180 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8181 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8182#endif /* IXGBE_FCOE */
082757af
DS		 8183 .ndo_set_features = ixgbe_set_features,
8184 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8185 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8186 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8187 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8188 .ndo_dfwd_add_station = ixgbe_fwd_add,
8189 .ndo_dfwd_del_station = ixgbe_fwd_del,
3f207800
DS		 8190 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8191 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
0edc3527
SH		 8192};
8193
e027d1ae
JK		 8194/**
8195 * ixgbe_enumerate_functions - Get the number of ports this device has
8196 * @adapter: adapter structure
8197 *
8198 * This function enumerates the phsyical functions co-located on a single slot,
8199 * in order to determine how many ports a device has. This is most useful in
8200 * determining the required GT/s of PCIe bandwidth necessary for optimal
8201 * performance.
8202 **/
8203static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8204{
caafb95d 8205 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8206 int physfns = 0;
8207
f1f96579
JK		 8208 /* Some cards can not use the generic count PCIe functions method,
8209 * because they are behind a parent switch, so we hardcode these with
8210 * the correct number of functions.
e027d1ae 8211 */
8818970d 8212 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8213 physfns = 4;
8818970d
JK		 8214
8215 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8216 /* don't count virtual functions */
caafb95d
JK		 8217 if (entry->is_virtfn)
8218 continue;
8219
8220 /* When the devices on the bus don't all match our device ID,
8221 * we can't reliably determine the correct number of
8222 * functions. This can occur if a function has been direct
8223 * attached to a virtual machine using VT-d, for example. In
8224 * this case, simply return -1 to indicate this.
8225 */
8226 if ((entry->vendor != pdev->vendor) ||
8227 (entry->device != pdev->device))
8228 return -1;
8229
8230 physfns++;
e027d1ae
JK		 8231 }
8232
8233 return physfns;
8234}
8235
8e2813f5
JK		 8236/**
8237 * ixgbe_wol_supported - Check whether device supports WoL
8238 * @hw: hw specific details
8239 * @device_id: the device ID
8240 * @subdev_id: the subsystem device ID
8241 *
8242 * This function is used by probe and ethtool to determine
8243 * which devices have WoL support
8244 *
8245 **/
8246int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8247 u16 subdevice_id)
8248{
8249 struct ixgbe_hw *hw = &adapter->hw;
8250 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8251 int is_wol_supported = 0;
8252
8253 switch (device_id) {
8254 case IXGBE_DEV_ID_82599_SFP:
8255 /* Only these subdevices could supports WOL */
8256 switch (subdevice_id) {
87557440 8257 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8258 case IXGBE_SUBDEV_ID_82599_560FLR:
8259 /* only support first port */
8260 if (hw->bus.func != 0)
8261 break;
5700ff26 8262 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8263 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8264 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8265 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8266 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8267 is_wol_supported = 1;
8268 break;
8269 }
8270 break;
5daebbb0
DS		 8271 case IXGBE_DEV_ID_82599EN_SFP:
8272 /* Only this subdevice supports WOL */
8273 switch (subdevice_id) {
8274 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8275 is_wol_supported = 1;
8276 break;
8277 }
8278 break;
8e2813f5
JK		 8279 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8280 /* All except this subdevice support WOL */
8281 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8282 is_wol_supported = 1;
8283 break;
8284 case IXGBE_DEV_ID_82599_KX4:
8285 is_wol_supported = 1;
8286 break;
8287 case IXGBE_DEV_ID_X540T:
df376f0d 8288 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 8289 /* check eeprom to see if enabled wol */
8290 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8291 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8292 (hw->bus.func == 0))) {
8293 is_wol_supported = 1;
8294 }
8295 break;
8296 }
8297
8298 return is_wol_supported;
8299}
8300
c762dff2
MP		 8301/**
8302 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8303 * @adapter: Pointer to adapter struct
8304 */
8305static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8306{
8307#ifdef CONFIG_OF
8308 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8309 struct ixgbe_hw *hw = &adapter->hw;
8310 const unsigned char *addr;
8311
8312 addr = of_get_mac_address(dp);
8313 if (addr) {
8314 ether_addr_copy(hw->mac.perm_addr, addr);
8315 return;
8316 }
8317#endif /* CONFIG_OF */
8318
8319#ifdef CONFIG_SPARC
8320 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8321#endif /* CONFIG_SPARC */
8322}
8323
9a799d71
AK		 8324/**
8325 * ixgbe_probe - Device Initialization Routine
8326 * @pdev: PCI device information struct
8327 * @ent: entry in ixgbe_pci_tbl
8328 *
8329 * Returns 0 on success, negative on failure
8330 *
8331 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8332 * The OS initialization, configuring of the adapter private structure,
8333 * and a hardware reset occur.
8334 **/
1dd06ae8 8335static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8336{
8337 struct net_device *netdev;
8338 struct ixgbe_adapter *adapter = NULL;
8339 struct ixgbe_hw *hw;
8340 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8341 int i, err, pci_using_dac, expected_gts;
d3cb9869 8342 unsigned int indices = MAX_TX_QUEUES;
289700db 8343 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8344 bool disable_dev = false;
eacd73f7
YZ		 8345#ifdef IXGBE_FCOE
8346 u16 device_caps;
8347#endif
289700db 8348 u32 eec;
9a799d71 8349
bded64a7
AG		 8350 /* Catch broken hardware that put the wrong VF device ID in
8351 * the PCIe SR-IOV capability.
8352 */
8353 if (pdev->is_virtfn) {
8354 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8355 pci_name(pdev), pdev->vendor, pdev->device);
8356 return -EINVAL;
8357 }
8358
9ce77666 8359 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8360 if (err)
8361 return err;
8362
f5f2eda8 8363 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8364 pci_using_dac = 1;
8365 } else {
f5f2eda8 8366 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8367 if (err) {
f5f2eda8
RK		 8368 dev_err(&pdev->dev,
8369 "No usable DMA configuration, aborting\n");
8370 goto err_dma;
9a799d71
AK		 8371 }
8372 pci_using_dac = 0;
8373 }
8374
9ce77666 8375 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8376 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8377 if (err) {
b8bc0421
DC		 8378 dev_err(&pdev->dev,
8379 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8380 goto err_pci_reg;
8381 }
8382
19d5afd4 8383 pci_enable_pcie_error_reporting(pdev);
6fabd715 8384
9a799d71 8385 pci_set_master(pdev);
fb3b27bc 8386 pci_save_state(pdev);
9a799d71 8387
d3cb9869 8388 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8389#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8390 /* 8 TC w/ 4 queues per TC */
8391 indices = 4 * MAX_TRAFFIC_CLASS;
8392#else
8393 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8394#endif
d3cb9869 8395 }
e901acd6 8396
c85a2618 8397 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8398 if (!netdev) {
8399 err = -ENOMEM;
8400 goto err_alloc_etherdev;
8401 }
8402
9a799d71
AK		 8403 SET_NETDEV_DEV(netdev, &pdev->dev);
8404
9a799d71
AK		 8405 adapter = netdev_priv(netdev);
8406
8407 adapter->netdev = netdev;
8408 adapter->pdev = pdev;
8409 hw = &adapter->hw;
8410 hw->back = adapter;
b3f4d599 8411 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8412
05857980 8413 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8414 pci_resource_len(pdev, 0));
2a1a091c 8415 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8416 if (!hw->hw_addr) {
8417 err = -EIO;
8418 goto err_ioremap;
8419 }
8420
0edc3527 8421 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8422 ixgbe_set_ethtool_ops(netdev);
9a799d71 8423 netdev->watchdog_timeo = 5 * HZ;
339de30f 8424 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8425
9a799d71
AK		 8426 /* Setup hw api */
8427 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8428 hw->mac.type = ii->mac;
9a799d71 8429
c44ade9e
JB		 8430 /* EEPROM */
8431 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8432 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
58cf663f
MR		 8433 if (ixgbe_removed(hw->hw_addr)) {
8434 err = -EIO;
8435 goto err_ioremap;
8436 }
c44ade9e
JB		 8437 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8438 if (!(eec & (1 << 8)))
8439 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8440
8441 /* PHY */
8442 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8443 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8444 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8445 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8446 hw->phy.mdio.mmds = 0;
8447 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8448 hw->phy.mdio.dev = netdev;
8449 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8450 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8451
8ca783ab 8452 ii->get_invariants(hw);
9a799d71
AK		 8453
8454 /* setup the private structure */
8455 err = ixgbe_sw_init(adapter);
8456 if (err)
8457 goto err_sw_init;
8458
e86bff0e 8459 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8460 switch (adapter->hw.mac.type) {
8461 case ixgbe_mac_82599EB:
8462 case ixgbe_mac_X540:
9a75a1ac
DS		 8463 case ixgbe_mac_X550:
8464 case ixgbe_mac_X550EM_x:
e86bff0e 8465 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8466 break;
8467 default:
8468 break;
8469 }
e86bff0e 8470
bf069c97
DS		 8471 /*
8472 * If there is a fan on this device and it has failed log the
8473 * failure.
8474 */
8475 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8476 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8477 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8478 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8479 }
8480
8ef78adc
PWJ		 8481 if (allow_unsupported_sfp)
8482 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8483
c44ade9e 8484 /* reset_hw fills in the perm_addr as well */
119fc60a 8485 hw->phy.reset_if_overtemp = true;
c44ade9e 8486 err = hw->mac.ops.reset_hw(hw);
119fc60a 8487 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8488 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8489 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8490 err = 0;
8491 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8492 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8493 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8494 goto err_sw_init;
8495 } else if (err) {
849c4542 8496 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8497 goto err_sw_init;
8498 }
8499
99d74487 8500#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8501 /* SR-IOV not supported on the 82598 */
8502 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8503 goto skip_sriov;
8504 /* Mailbox */
8505 ixgbe_init_mbx_params_pf(hw);
8506 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8507 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8508 ixgbe_enable_sriov(adapter);
60a1a680 8509skip_sriov:
1cdd1ec8 8510
99d74487 8511#endif
396e799c 8512 netdev->features = NETIF_F_SG |
e8e9f696 8513 NETIF_F_IP_CSUM |
082757af 8514 NETIF_F_IPV6_CSUM |
f646968f
PM		 8515 NETIF_F_HW_VLAN_CTAG_TX |
8516 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 8517 NETIF_F_TSO |
8518 NETIF_F_TSO6 |
082757af 8519 NETIF_F_RXHASH |
8bf1264d 8520 NETIF_F_RXCSUM;
9a799d71 8521
8bf1264d 8522 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8523
58be7666
DS		 8524 switch (adapter->hw.mac.type) {
8525 case ixgbe_mac_82599EB:
8526 case ixgbe_mac_X540:
9a75a1ac
DS		 8527 case ixgbe_mac_X550:
8528 case ixgbe_mac_X550EM_x:
45a5ead0 8529 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8530 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8531 NETIF_F_NTUPLE;
58be7666
DS		 8532 break;
8533 default:
8534 break;
8535 }
45a5ead0 8536
3f2d1c0f 8537 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 8538 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 8539
ad31c402
JK		 8540 netdev->vlan_features |= NETIF_F_TSO;
8541 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8542 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8543 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8544 netdev->vlan_features |= NETIF_F_SG;
8545
01789349 8546 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8547 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8548
3f207800
DS		 8549 switch (adapter->hw.mac.type) {
8550 case ixgbe_mac_X550:
8551 case ixgbe_mac_X550EM_x:
8552 netdev->hw_enc_features |= NETIF_F_RXCSUM;
8553 break;
8554 default:
8555 break;
8556 }
8557
7a6b6f51 8558#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8559 netdev->dcbnl_ops = &dcbnl_ops;
8560#endif
8561
eacd73f7 8562#ifdef IXGBE_FCOE
0d551589 8563 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8564 unsigned int fcoe_l;
8565
eacd73f7
YZ		 8566 if (hw->mac.ops.get_device_caps) {
8567 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8568 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8569 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8570 }
7c8ae65a 8571
d3cb9869
AD		 8572
8573 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8574 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8575
a58915c7
AD		 8576 netdev->features |= NETIF_F_FSO |
8577 NETIF_F_FCOE_CRC;
8578
7c8ae65a
AD		 8579 netdev->vlan_features |= NETIF_F_FSO |
8580 NETIF_F_FCOE_CRC |
8581 NETIF_F_FCOE_MTU;
5e09d7f6 8582 }
eacd73f7 8583#endif /* IXGBE_FCOE */
7b872a55 8584 if (pci_using_dac) {
9a799d71 8585 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8586 netdev->vlan_features |= NETIF_F_HIGHDMA;
8587 }
9a799d71 8588
082757af
DS		 8589 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8590 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8591 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8592 netdev->features |= NETIF_F_LRO;
8593
9a799d71 8594 /* make sure the EEPROM is good */
c44ade9e 8595 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8596 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8597 err = -EIO;
35937c05 8598 goto err_sw_init;
9a799d71
AK		 8599 }
8600
c762dff2
MP		 8601 ixgbe_get_platform_mac_addr(adapter);
8602
9a799d71 8603 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8604
aaeb6cdf 8605 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8606 e_dev_err("invalid MAC address\n");
9a799d71 8607 err = -EIO;
35937c05 8608 goto err_sw_init;
9a799d71
AK		 8609 }
8610
5d7daa35
JK		 8611 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8612
7086400d 8613 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8614 (unsigned long) adapter);
9a799d71 8615
58cf663f
MR		 8616 if (ixgbe_removed(hw->hw_addr)) {
8617 err = -EIO;
8618 goto err_sw_init;
8619 }
7086400d 8620 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8621 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8622 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8623
021230d4
AV		 8624 err = ixgbe_init_interrupt_scheme(adapter);
8625 if (err)
8626 goto err_sw_init;
9a799d71 8627
8e2813f5 8628 /* WOL not supported for all devices */
c23f5b6b 8629 adapter->wol = 0;
8e2813f5 8630 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8631 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8632 pdev->subsystem_device);
6b92b0ba 8633 if (hw->wol_enabled)
9417c464 8634 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8635
e8e26350
PW		 8636 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8637
15e5209f
ET		 8638 /* save off EEPROM version number */
8639 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8640 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8641
04f165ef
PW		 8642 /* pick up the PCI bus settings for reporting later */
8643 hw->mac.ops.get_bus_info(hw);
e027d1ae 8644 if (ixgbe_pcie_from_parent(hw))
b8e82001 8645 ixgbe_get_parent_bus_info(adapter);
04f165ef 8646
e027d1ae
JK		 8647 /* calculate the expected PCIe bandwidth required for optimal
8648 * performance. Note that some older parts will never have enough
8649 * bandwidth due to being older generation PCIe parts. We clamp these
8650 * parts to ensure no warning is displayed if it can't be fixed.
8651 */
8652 switch (hw->mac.type) {
8653 case ixgbe_mac_82598EB:
8654 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8655 break;
8656 default:
8657 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8658 break;
0c254d86 8659 }
caafb95d
JK		 8660
8661 /* don't check link if we failed to enumerate functions */
8662 if (expected_gts > 0)
8663 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8664
339de30f 8665 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8666 if (err)
339de30f 8667 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8668 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8669 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8670 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8671 part_str);
6a2aae5a
JK		 8672 else
8673 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8674 hw->mac.type, hw->phy.type, part_str);
8675
8676 e_dev_info("%pM\n", netdev->dev_addr);
8677
9a799d71 8678 /* reset the hardware with the new settings */
794caeb2 8679 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8680 if (err == IXGBE_ERR_EEPROM_VERSION) {
8681 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8682 e_dev_warn("This device is a pre-production adapter/LOM. "
8683 "Please be aware there may be issues associated "
8684 "with your hardware. If you are experiencing "
8685 "problems please contact your Intel or hardware "
8686 "representative who provided you with this "
8687 "hardware.\n");
794caeb2 8688 }
9a799d71
AK		 8689 strcpy(netdev->name, "eth%d");
8690 err = register_netdev(netdev);
8691 if (err)
8692 goto err_register;
8693
0fb6a55c
ET		 8694 pci_set_drvdata(pdev, adapter);
8695
ec74a471
ET		 8696 /* power down the optics for 82599 SFP+ fiber */
8697 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8698 hw->mac.ops.disable_tx_laser(hw);
8699
54386467
JB		 8700 /* carrier off reporting is important to ethtool even BEFORE open */
8701 netif_carrier_off(netdev);
8702
5dd2d332 8703#ifdef CONFIG_IXGBE_DCA
652f093f 8704 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8705 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8706 ixgbe_setup_dca(adapter);
8707 }
8708#endif
1cdd1ec8 8709 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8710 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8711 for (i = 0; i < adapter->num_vfs; i++)
8712 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8713 }
8714
2466dd9c
JK		 8715 /* firmware requires driver version to be 0xFFFFFFFF
8716 * since os does not support feature
8717 */
9612de92 8718 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8719 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8720 0xFF);
9612de92 8721
0365e6e4
PW		 8722 /* add san mac addr to netdev */
8723 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8724
ea81875a 8725 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8726
1210982b 8727#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8728 if (ixgbe_sysfs_init(adapter))
8729 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8730#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8731
00949167 8732 ixgbe_dbg_adapter_init(adapter);
00949167 8733
d1a35ee2
ET		 8734 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8735 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8736 hw->mac.ops.setup_link(hw,
8737 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8738 true);
8739
9a799d71
AK		 8740 return 0;
8741
8742err_register:
5eba3699 8743 ixgbe_release_hw_control(adapter);
7a921c93 8744 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8745err_sw_init:
99d74487 8746 ixgbe_disable_sriov(adapter);
7086400d 8747 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8748 iounmap(adapter->io_addr);
5d7daa35 8749 kfree(adapter->mac_table);
9a799d71 8750err_ioremap:
b5b2ffc0 8751 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8752 free_netdev(netdev);
8753err_alloc_etherdev:
e8e9f696
JP		 8754 pci_release_selected_regions(pdev,
8755 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8756err_pci_reg:
8757err_dma:
b5b2ffc0 8758 if (!adapter || disable_dev)
41c62843 8759 pci_disable_device(pdev);
9a799d71
AK		 8760 return err;
8761}
8762
8763/**
8764 * ixgbe_remove - Device Removal Routine
8765 * @pdev: PCI device information struct
8766 *
8767 * ixgbe_remove is called by the PCI subsystem to alert the driver
8768 * that it should release a PCI device. The could be caused by a
8769 * Hot-Plug event, or because the driver is going to be removed from
8770 * memory.
8771 **/
9f9a12f8 8772static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8773{
c60fbb00 8774 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 8775 struct net_device *netdev;
b5b2ffc0 8776 bool disable_dev;
9a799d71 8777
0fb6a55c
ET		 8778 /* if !adapter then we already cleaned up in probe */
8779 if (!adapter)
8780 return;
8781
8782 netdev = adapter->netdev;
00949167 8783 ixgbe_dbg_adapter_exit(adapter);
00949167 8784
09f40aed 8785 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8786 cancel_work_sync(&adapter->service_task);
9a799d71 8787
3a6a4eda 8788
5dd2d332 8789#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8790 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8791 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8792 dca_remove_requester(&pdev->dev);
8793 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8794 }
8795
8796#endif
1210982b 8797#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8798 ixgbe_sysfs_exit(adapter);
1210982b 8799#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8800
0365e6e4
PW		 8801 /* remove the added san mac */
8802 ixgbe_del_sanmac_netdev(netdev);
8803
c4900be0
DS		 8804 if (netdev->reg_state == NETREG_REGISTERED)
8805 unregister_netdev(netdev);
9a799d71 8806
da36b647
GR		 8807#ifdef CONFIG_PCI_IOV
8808 /*
8809 * Only disable SR-IOV on unload if the user specified the now
8810 * deprecated max_vfs module parameter.
8811 */
8812 if (max_vfs)
8813 ixgbe_disable_sriov(adapter);
8814#endif
7a921c93 8815 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8816
021230d4 8817 ixgbe_release_hw_control(adapter);
9a799d71 8818
2b1588c3
AD		 8819#ifdef CONFIG_DCB
8820 kfree(adapter->ixgbe_ieee_pfc);
8821 kfree(adapter->ixgbe_ieee_ets);
8822
8823#endif
2a1a091c 8824 iounmap(adapter->io_addr);
9ce77666 8825 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8826 IORESOURCE_MEM));
9a799d71 8827
849c4542 8828 e_dev_info("complete\n");
021230d4 8829
5d7daa35 8830 kfree(adapter->mac_table);
b5b2ffc0 8831 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8832 free_netdev(netdev);
8833
19d5afd4 8834 pci_disable_pcie_error_reporting(pdev);
6fabd715 8835
b5b2ffc0 8836 if (disable_dev)
41c62843 8837 pci_disable_device(pdev);
9a799d71
AK		 8838}
8839
8840/**
8841 * ixgbe_io_error_detected - called when PCI error is detected
8842 * @pdev: Pointer to PCI device
8843 * @state: The current pci connection state
8844 *
8845 * This function is called after a PCI bus error affecting
8846 * this device has been detected.
8847 */
8848static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8849 pci_channel_state_t state)
9a799d71 8850{
c60fbb00
AD		 8851 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8852 struct net_device *netdev = adapter->netdev;
9a799d71 8853
83c61fa9 8854#ifdef CONFIG_PCI_IOV
14438464 8855 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8856 struct pci_dev *bdev, *vfdev;
8857 u32 dw0, dw1, dw2, dw3;
8858 int vf, pos;
8859 u16 req_id, pf_func;
8860
8861 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8862 adapter->num_vfs == 0)
8863 goto skip_bad_vf_detection;
8864
8865 bdev = pdev->bus->self;
62f87c0e 8866 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8867 bdev = bdev->bus->self;
8868
8869 if (!bdev)
8870 goto skip_bad_vf_detection;
8871
8872 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8873 if (!pos)
8874 goto skip_bad_vf_detection;
8875
14438464
MR		 8876 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8877 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8878 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8879 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8880 if (ixgbe_removed(hw->hw_addr))
8881 goto skip_bad_vf_detection;
83c61fa9
GR		 8882
8883 req_id = dw1 >> 16;
8884 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8885 if (!(req_id & 0x0080))
8886 goto skip_bad_vf_detection;
8887
8888 pf_func = req_id & 0x01;
8889 if ((pf_func & 1) == (pdev->devfn & 1)) {
8890 unsigned int device_id;
8891
8892 vf = (req_id & 0x7F) >> 1;
8893 e_dev_err("VF %d has caused a PCIe error\n", vf);
8894 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8895 "%8.8x\tdw3: %8.8x\n",
8896 dw0, dw1, dw2, dw3);
8897 switch (adapter->hw.mac.type) {
8898 case ixgbe_mac_82599EB:
8899 device_id = IXGBE_82599_VF_DEVICE_ID;
8900 break;
8901 case ixgbe_mac_X540:
8902 device_id = IXGBE_X540_VF_DEVICE_ID;
8903 break;
9a75a1ac
DS		 8904 case ixgbe_mac_X550:
8905 device_id = IXGBE_DEV_ID_X550_VF;
8906 break;
8907 case ixgbe_mac_X550EM_x:
8908 device_id = IXGBE_DEV_ID_X550EM_X_VF;
8909 break;
83c61fa9
GR		 8910 default:
8911 device_id = 0;
8912 break;
8913 }
8914
8915 /* Find the pci device of the offending VF */
36e90319 8916 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8917 while (vfdev) {
8918 if (vfdev->devfn == (req_id & 0xFF))
8919 break;
36e90319 8920 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8921 device_id, vfdev);
8922 }
8923 /*
8924 * There's a slim chance the VF could have been hot plugged,
8925 * so if it is no longer present we don't need to issue the
8926 * VFLR. Just clean up the AER in that case.
8927 */
8928 if (vfdev) {
9079e416 8929 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 8930 /* Free device reference count */
8931 pci_dev_put(vfdev);
83c61fa9
GR		 8932 }
8933
8934 pci_cleanup_aer_uncorrect_error_status(pdev);
8935 }
8936
8937 /*
8938 * Even though the error may have occurred on the other port
8939 * we still need to increment the vf error reference count for
8940 * both ports because the I/O resume function will be called
8941 * for both of them.
8942 */
8943 adapter->vferr_refcount++;
8944
8945 return PCI_ERS_RESULT_RECOVERED;
8946
8947skip_bad_vf_detection:
8948#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 8949 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8950 return PCI_ERS_RESULT_DISCONNECT;
8951
41c62843 8952 rtnl_lock();
9a799d71
AK		 8953 netif_device_detach(netdev);
8954
41c62843
MR		 8955 if (state == pci_channel_io_perm_failure) {
8956 rtnl_unlock();
3044b8d1 8957 return PCI_ERS_RESULT_DISCONNECT;
41c62843 8958 }
3044b8d1 8959
9a799d71
AK		 8960 if (netif_running(netdev))
8961 ixgbe_down(adapter);
41c62843
MR		 8962
8963 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8964 pci_disable_device(pdev);
8965 rtnl_unlock();
9a799d71 8966
b4617240 8967 /* Request a slot reset. */
9a799d71
AK		 8968 return PCI_ERS_RESULT_NEED_RESET;
8969}
8970
8971/**
8972 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8973 * @pdev: Pointer to PCI device
8974 *
8975 * Restart the card from scratch, as if from a cold-boot.
8976 */
8977static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8978{
c60fbb00 8979 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8980 pci_ers_result_t result;
8981 int err;
9a799d71 8982
9ce77666 8983 if (pci_enable_device_mem(pdev)) {
396e799c 8984 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8985 result = PCI_ERS_RESULT_DISCONNECT;
8986 } else {
4e857c58 8987 smp_mb__before_atomic();
41c62843 8988 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 8989 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8990 pci_set_master(pdev);
8991 pci_restore_state(pdev);
c0e1f68b 8992 pci_save_state(pdev);
9a799d71 8993
dd4d8ca6 8994 pci_wake_from_d3(pdev, false);
9a799d71 8995
6fabd715 8996 ixgbe_reset(adapter);
88512539 8997 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8998 result = PCI_ERS_RESULT_RECOVERED;
8999 }
9000
9001 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9002 if (err) {
849c4542
ET		 9003 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9004 "failed 0x%0x\n", err);
6fabd715
PWJ		 9005 /* non-fatal, continue */
9006 }
9a799d71 9007
6fabd715 9008 return result;
9a799d71
AK		 9009}
9010
9011/**
9012 * ixgbe_io_resume - called when traffic can start flowing again.
9013 * @pdev: Pointer to PCI device
9014 *
9015 * This callback is called when the error recovery driver tells us that
9016 * its OK to resume normal operation.
9017 */
9018static void ixgbe_io_resume(struct pci_dev *pdev)
9019{
c60fbb00
AD		 9020 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9021 struct net_device *netdev = adapter->netdev;
9a799d71 9022
83c61fa9
GR		 9023#ifdef CONFIG_PCI_IOV
9024 if (adapter->vferr_refcount) {
9025 e_info(drv, "Resuming after VF err\n");
9026 adapter->vferr_refcount--;
9027 return;
9028 }
9029
9030#endif
c7ccde0f
AD		 9031 if (netif_running(netdev))
9032 ixgbe_up(adapter);
9a799d71
AK		 9033
9034 netif_device_attach(netdev);
9a799d71
AK		 9035}
9036
3646f0e5 9037static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9038 .error_detected = ixgbe_io_error_detected,
9039 .slot_reset = ixgbe_io_slot_reset,
9040 .resume = ixgbe_io_resume,
9041};
9042
9043static struct pci_driver ixgbe_driver = {
9044 .name = ixgbe_driver_name,
9045 .id_table = ixgbe_pci_tbl,
9046 .probe = ixgbe_probe,
9f9a12f8 9047 .remove = ixgbe_remove,
9a799d71
AK		 9048#ifdef CONFIG_PM
9049 .suspend = ixgbe_suspend,
9050 .resume = ixgbe_resume,
9051#endif
9052 .shutdown = ixgbe_shutdown,
da36b647 9053 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9054 .err_handler = &ixgbe_err_handler
9055};
9056
9057/**
9058 * ixgbe_init_module - Driver Registration Routine
9059 *
9060 * ixgbe_init_module is the first routine called when the driver is
9061 * loaded. All it does is register with the PCI subsystem.
9062 **/
9063static int __init ixgbe_init_module(void)
9064{
9065 int ret;
c7689578 9066 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9067 pr_info("%s\n", ixgbe_copyright);
9a799d71 9068
00949167 9069 ixgbe_dbg_init();
00949167 9070
f01fc1a8
JK		 9071 ret = pci_register_driver(&ixgbe_driver);
9072 if (ret) {
f01fc1a8 9073 ixgbe_dbg_exit();
f01fc1a8
JK		 9074 return ret;
9075 }
9076
5dd2d332 9077#ifdef CONFIG_IXGBE_DCA
bd0362dd 9078 dca_register_notify(&dca_notifier);
bd0362dd 9079#endif
5dd2d332 9080
f01fc1a8 9081 return 0;
9a799d71 9082}
b4617240 9083
9a799d71
AK		 9084module_init(ixgbe_init_module);
9085
9086/**
9087 * ixgbe_exit_module - Driver Exit Cleanup Routine
9088 *
9089 * ixgbe_exit_module is called just before the driver is removed
9090 * from memory.
9091 **/
9092static void __exit ixgbe_exit_module(void)
9093{
5dd2d332 9094#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9095 dca_unregister_notify(&dca_notifier);
9096#endif
9a799d71 9097 pci_unregister_driver(&ixgbe_driver);
00949167 9098
00949167 9099 ixgbe_dbg_exit();
9a799d71 9100}
bd0362dd 9101
5dd2d332 9102#ifdef CONFIG_IXGBE_DCA
bd0362dd 9103static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9104 void *p)
bd0362dd
JC		 9105{
9106 int ret_val;
9107
9108 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9109 __ixgbe_notify_dca);
bd0362dd
JC		 9110
9111 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9112}
b453368d 9113
5dd2d332 9114#endif /* CONFIG_IXGBE_DCA */
849c4542 9115
9a799d71
AK		 9116module_exit(ixgbe_exit_module);
9117
9118/* ixgbe_main.c */
Linux kernel - Deliverables
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