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ixgbe: Correct setting of RDRXCTL register for X550* devices
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
67359c3c 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
67359c3c
MR		 68#ifdef CONFIG_IXGBE_VXLAN
69#include <net/vxlan.h>
70#endif
9a799d71
AK		 71
72char ixgbe_driver_name[] = "ixgbe";
9c8eb720 73static const char ixgbe_driver_string[] =
e8e9f696 74 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 75#ifdef IXGBE_FCOE
ea81875a
NP		 76char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 78#else
79static char ixgbe_default_device_descr[] =
80 "Intel(R) 10 Gigabit Network Connection";
81#endif
9be4a9bb 82#define DRV_VERSION "4.0.1-k"
9c8eb720 83const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 84static const char ixgbe_copyright[] =
67359c3c 85 "Copyright (c) 1999-2015 Intel Corporation.";
9a799d71 86
f44e751b
DS		 87static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
88
9a799d71 89static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 90 [board_82598] = &ixgbe_82598_info,
91 [board_82599] = &ixgbe_82599_info,
92 [board_X540] = &ixgbe_X540_info,
93 [board_X550] = &ixgbe_X550_info,
94 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 95};
96
97/* ixgbe_pci_tbl - PCI Device ID Table
98 *
99 * Wildcard entries (PCI_ANY_ID) should come last
100 * Last entry must be all 0s
101 *
102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
103 * Class, Class Mask, private data (not used) }
104 */
9baa3c34 105static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
9a799d71
AK		 140 /* required last entry */
141 {0, }
142};
143MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
144
5dd2d332 145#ifdef CONFIG_IXGBE_DCA
bd0362dd 146static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 147 void *p);
bd0362dd
JC		 148static struct notifier_block dca_notifier = {
149 .notifier_call = ixgbe_notify_dca,
150 .next = NULL,
151 .priority = 0
152};
153#endif
154
1cdd1ec8
GR		 155#ifdef CONFIG_PCI_IOV
156static unsigned int max_vfs;
157module_param(max_vfs, uint, 0);
e8e9f696 158MODULE_PARM_DESC(max_vfs,
170e8543 159 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 160#endif /* CONFIG_PCI_IOV */
161
8ef78adc
PWJ		 162static unsigned int allow_unsupported_sfp;
163module_param(allow_unsupported_sfp, uint, 0);
164MODULE_PARM_DESC(allow_unsupported_sfp,
165 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
166
b3f4d599 167#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
168static int debug = -1;
169module_param(debug, int, 0);
170MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
171
9a799d71
AK		 172MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
173MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
174MODULE_LICENSE("GPL");
175MODULE_VERSION(DRV_VERSION);
176
14438464
MR		 177static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
178
b8e82001
JK		 179static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
180 u32 reg, u16 *value)
181{
b8e82001
JK		 182 struct pci_dev *parent_dev;
183 struct pci_bus *parent_bus;
184
185 parent_bus = adapter->pdev->bus->parent;
186 if (!parent_bus)
187 return -1;
188
189 parent_dev = parent_bus->self;
190 if (!parent_dev)
191 return -1;
192
c0798edf 193 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 194 return -1;
195
c0798edf 196 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 197 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
199 return -1;
b8e82001
JK		 200 return 0;
201}
202
203static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
204{
205 struct ixgbe_hw *hw = &adapter->hw;
206 u16 link_status = 0;
207 int err;
208
209 hw->bus.type = ixgbe_bus_type_pci_express;
210
211 /* Get the negotiated link width and speed from PCI config space of the
212 * parent, as this device is behind a switch
213 */
214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
215
216 /* assume caller will handle error case */
217 if (err)
218 return err;
219
220 hw->bus.width = ixgbe_convert_bus_width(link_status);
221 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
222
223 return 0;
224}
225
e027d1ae
JK		 226/**
227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
228 * @hw: hw specific details
229 *
230 * This function is used by probe to determine whether a device's PCI-Express
231 * bandwidth details should be gathered from the parent bus instead of from the
232 * device. Used to ensure that various locations all have the correct device ID
233 * checks.
234 */
235static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
236{
237 switch (hw->device_id) {
238 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 239 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 240 return true;
241 default:
242 return false;
243 }
244}
245
246static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
247 int expected_gts)
248{
f9328bc6 249 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 250 int max_gts = 0;
251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
253 struct pci_dev *pdev;
254
f9328bc6
DS		 255 /* Some devices are not connected over PCIe and thus do not negotiate
256 * speed. These devices do not have valid bus info, and thus any report
257 * we generate may not be correct.
258 */
259 if (hw->bus.type == ixgbe_bus_type_internal)
260 return;
261
56d1392f 262 /* determine whether to use the parent device */
e027d1ae
JK		 263 if (ixgbe_pcie_from_parent(&adapter->hw))
264 pdev = adapter->pdev->bus->parent->self;
265 else
266 pdev = adapter->pdev;
267
268 if (pcie_get_minimum_link(pdev, &speed, &width) ||
269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
270 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
271 return;
272 }
273
274 switch (speed) {
275 case PCIE_SPEED_2_5GT:
276 /* 8b/10b encoding reduces max throughput by 20% */
277 max_gts = 2 * width;
278 break;
279 case PCIE_SPEED_5_0GT:
280 /* 8b/10b encoding reduces max throughput by 20% */
281 max_gts = 4 * width;
282 break;
283 case PCIE_SPEED_8_0GT:
9f0a433c 284 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 285 max_gts = 8 * width;
286 break;
287 default:
288 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
289 return;
290 }
291
292 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
293 max_gts);
294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
298 "Unknown"),
299 width,
300 (speed == PCIE_SPEED_2_5GT ? "20%" :
301 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 302 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 303 "Unknown"));
304
305 if (max_gts < expected_gts) {
306 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
308 expected_gts);
309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
310 }
311}
312
7086400d
AD		 313static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
314{
315 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 316 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
318 schedule_work(&adapter->service_task);
319}
320
2a1a091c
MR		 321static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
322{
323 struct ixgbe_adapter *adapter = hw->back;
324
325 if (!hw->hw_addr)
326 return;
327 hw->hw_addr = NULL;
328 e_dev_err("Adapter removed\n");
58cf663f
MR		 329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
330 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 331}
332
f8e2472f 333static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 334{
335 u32 value;
336
337 /* The following check not only optimizes a bit by not
338 * performing a read on the status register when the
339 * register just read was a status register read that
340 * returned IXGBE_FAILED_READ_REG. It also blocks any
341 * potential recursion.
342 */
343 if (reg == IXGBE_STATUS) {
344 ixgbe_remove_adapter(hw);
345 return;
346 }
347 value = ixgbe_read_reg(hw, IXGBE_STATUS);
348 if (value == IXGBE_FAILED_READ_REG)
349 ixgbe_remove_adapter(hw);
350}
351
f8e2472f
MR		 352/**
353 * ixgbe_read_reg - Read from device register
354 * @hw: hw specific details
355 * @reg: offset of register to read
356 *
357 * Returns : value read or IXGBE_FAILED_READ_REG if removed
358 *
359 * This function is used to read device registers. It checks for device
360 * removal by confirming any read that returns all ones by checking the
361 * status register value for all ones. This function avoids reading from
362 * the hardware if a removal was previously detected in which case it
363 * returns IXGBE_FAILED_READ_REG (all ones).
364 */
365u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
366{
367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
368 u32 value;
369
370 if (ixgbe_removed(reg_addr))
371 return IXGBE_FAILED_READ_REG;
372 value = readl(reg_addr + reg);
373 if (unlikely(value == IXGBE_FAILED_READ_REG))
374 ixgbe_check_remove(hw, reg);
375 return value;
376}
377
14438464
MR		 378static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
379{
380 u16 value;
381
382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
383 if (value == IXGBE_FAILED_READ_CFG_WORD) {
384 ixgbe_remove_adapter(hw);
385 return true;
386 }
387 return false;
388}
389
390u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
391{
392 struct ixgbe_adapter *adapter = hw->back;
393 u16 value;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return IXGBE_FAILED_READ_CFG_WORD;
397 pci_read_config_word(adapter->pdev, reg, &value);
398 if (value == IXGBE_FAILED_READ_CFG_WORD &&
399 ixgbe_check_cfg_remove(hw, adapter->pdev))
400 return IXGBE_FAILED_READ_CFG_WORD;
401 return value;
402}
403
404#ifdef CONFIG_PCI_IOV
405static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
406{
407 struct ixgbe_adapter *adapter = hw->back;
408 u32 value;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return IXGBE_FAILED_READ_CFG_DWORD;
412 pci_read_config_dword(adapter->pdev, reg, &value);
413 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
414 ixgbe_check_cfg_remove(hw, adapter->pdev))
415 return IXGBE_FAILED_READ_CFG_DWORD;
416 return value;
417}
418#endif /* CONFIG_PCI_IOV */
419
ed19231c
JK		 420void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
421{
422 struct ixgbe_adapter *adapter = hw->back;
423
424 if (ixgbe_removed(hw->hw_addr))
425 return;
426 pci_write_config_word(adapter->pdev, reg, value);
427}
428
7086400d
AD		 429static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
430{
431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
432
52f33af8 433 /* flush memory to make sure state is correct before next watchdog */
4e857c58 434 smp_mb__before_atomic();
7086400d
AD		 435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
436}
437
dcd79aeb
TI		 438struct ixgbe_reg_info {
439 u32 ofs;
440 char *name;
441};
442
443static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
444
445 /* General Registers */
446 {IXGBE_CTRL, "CTRL"},
447 {IXGBE_STATUS, "STATUS"},
448 {IXGBE_CTRL_EXT, "CTRL_EXT"},
449
450 /* Interrupt Registers */
451 {IXGBE_EICR, "EICR"},
452
453 /* RX Registers */
454 {IXGBE_SRRCTL(0), "SRRCTL"},
455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
456 {IXGBE_RDLEN(0), "RDLEN"},
457 {IXGBE_RDH(0), "RDH"},
458 {IXGBE_RDT(0), "RDT"},
459 {IXGBE_RXDCTL(0), "RXDCTL"},
460 {IXGBE_RDBAL(0), "RDBAL"},
461 {IXGBE_RDBAH(0), "RDBAH"},
462
463 /* TX Registers */
464 {IXGBE_TDBAL(0), "TDBAL"},
465 {IXGBE_TDBAH(0), "TDBAH"},
466 {IXGBE_TDLEN(0), "TDLEN"},
467 {IXGBE_TDH(0), "TDH"},
468 {IXGBE_TDT(0), "TDT"},
469 {IXGBE_TXDCTL(0), "TXDCTL"},
470
471 /* List Terminator */
ca8dfe25 472 { .name = NULL }
dcd79aeb
TI		 473};
474
475
476/*
477 * ixgbe_regdump - register printout routine
478 */
479static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
480{
481 int i = 0, j = 0;
482 char rname[16];
483 u32 regs[64];
484
485 switch (reginfo->ofs) {
486 case IXGBE_SRRCTL(0):
487 for (i = 0; i < 64; i++)
488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
489 break;
490 case IXGBE_DCA_RXCTRL(0):
491 for (i = 0; i < 64; i++)
492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
493 break;
494 case IXGBE_RDLEN(0):
495 for (i = 0; i < 64; i++)
496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
497 break;
498 case IXGBE_RDH(0):
499 for (i = 0; i < 64; i++)
500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
501 break;
502 case IXGBE_RDT(0):
503 for (i = 0; i < 64; i++)
504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
505 break;
506 case IXGBE_RXDCTL(0):
507 for (i = 0; i < 64; i++)
508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
509 break;
510 case IXGBE_RDBAL(0):
511 for (i = 0; i < 64; i++)
512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
513 break;
514 case IXGBE_RDBAH(0):
515 for (i = 0; i < 64; i++)
516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
517 break;
518 case IXGBE_TDBAL(0):
519 for (i = 0; i < 64; i++)
520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
521 break;
522 case IXGBE_TDBAH(0):
523 for (i = 0; i < 64; i++)
524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
525 break;
526 case IXGBE_TDLEN(0):
527 for (i = 0; i < 64; i++)
528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
529 break;
530 case IXGBE_TDH(0):
531 for (i = 0; i < 64; i++)
532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
533 break;
534 case IXGBE_TDT(0):
535 for (i = 0; i < 64; i++)
536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
537 break;
538 case IXGBE_TXDCTL(0):
539 for (i = 0; i < 64; i++)
540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
541 break;
542 default:
c7689578 543 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 544 IXGBE_READ_REG(hw, reginfo->ofs));
545 return;
546 }
547
548 for (i = 0; i < 8; i++) {
549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 550 pr_err("%-15s", rname);
dcd79aeb 551 for (j = 0; j < 8; j++)
c7689578
JP		 552 pr_cont(" %08x", regs[i*8+j]);
553 pr_cont("\n");
dcd79aeb
TI		 554 }
555
556}
557
558/*
559 * ixgbe_dump - Print registers, tx-rings and rx-rings
560 */
561static void ixgbe_dump(struct ixgbe_adapter *adapter)
562{
563 struct net_device *netdev = adapter->netdev;
564 struct ixgbe_hw *hw = &adapter->hw;
565 struct ixgbe_reg_info *reginfo;
566 int n = 0;
567 struct ixgbe_ring *tx_ring;
729739b7 568 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 569 union ixgbe_adv_tx_desc *tx_desc;
570 struct my_u0 { u64 a; u64 b; } *u0;
571 struct ixgbe_ring *rx_ring;
572 union ixgbe_adv_rx_desc *rx_desc;
573 struct ixgbe_rx_buffer *rx_buffer_info;
574 u32 staterr;
575 int i = 0;
576
577 if (!netif_msg_hw(adapter))
578 return;
579
580 /* Print netdevice Info */
581 if (netdev) {
582 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 583 pr_info("Device Name state "
dcd79aeb 584 "trans_start last_rx\n");
c7689578
JP		 585 pr_info("%-15s %016lX %016lX %016lX\n",
586 netdev->name,
587 netdev->state,
588 netdev->trans_start,
589 netdev->last_rx);
dcd79aeb
TI		 590 }
591
592 /* Print Registers */
593 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 594 pr_info(" Register Name Value\n");
dcd79aeb
TI		 595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
596 reginfo->name; reginfo++) {
597 ixgbe_regdump(hw, reginfo);
598 }
599
600 /* Print TX Ring Summary */
601 if (!netdev || !netif_running(netdev))
e90dd264 602 return;
dcd79aeb
TI		 603
604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 605 pr_info(" %s %s %s %s\n",
606 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
607 "leng", "ntw", "timestamp");
dcd79aeb
TI		 608 for (n = 0; n < adapter->num_tx_queues; n++) {
609 tx_ring = adapter->tx_ring[n];
729739b7 610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 612 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 613 (u64)dma_unmap_addr(tx_buffer, dma),
614 dma_unmap_len(tx_buffer, len),
615 tx_buffer->next_to_watch,
616 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
39ac868a 627 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
39ac868a 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
dcd79aeb
TI		 658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 tx_ring = adapter->tx_ring[n];
c7689578
JP		 662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
664 pr_info("------------------------------------\n");
8ad88e37
JH		 665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 669
670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 671 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 672 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 673 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
676 i,
677 le64_to_cpu(u0->a),
678 le64_to_cpu(u0->b),
679 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 680 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 681 tx_buffer->next_to_watch,
682 (u64)tx_buffer->time_stamp,
683 tx_buffer->skb);
684 if (i == tx_ring->next_to_use &&
685 i == tx_ring->next_to_clean)
686 pr_cont(" NTC/U\n");
687 else if (i == tx_ring->next_to_use)
688 pr_cont(" NTU\n");
689 else if (i == tx_ring->next_to_clean)
690 pr_cont(" NTC\n");
691 else
692 pr_cont("\n");
693
694 if (netif_msg_pktdata(adapter) &&
695 tx_buffer->skb)
696 print_hex_dump(KERN_INFO, "",
697 DUMP_PREFIX_ADDRESS, 16, 1,
698 tx_buffer->skb->data,
699 dma_unmap_len(tx_buffer, len),
700 true);
701 }
dcd79aeb
TI		 702 }
703 }
704
705 /* Print RX Rings Summary */
706rx_ring_summary:
707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 708 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 709 for (n = 0; n < adapter->num_rx_queues; n++) {
710 rx_ring = adapter->rx_ring[n];
c7689578
JP		 711 pr_info("%5d %5X %5X\n",
712 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 713 }
714
715 /* Print RX Rings */
716 if (!netif_msg_rx_status(adapter))
e90dd264 717 return;
dcd79aeb
TI		 718
719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
720
39ac868a
JH		 721 /* Receive Descriptor Formats
722 *
723 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 724 * 63 1 0
725 * +-----------------------------------------------------+
726 * 0 | Packet Buffer Address [63:1] |A0/NSE|
727 * +----------------------------------------------+------+
728 * 8 | Header Buffer Address [63:1] | DD |
729 * +-----------------------------------------------------+
730 *
731 *
39ac868a 732 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 733 *
734 * 63 48 47 32 31 30 21 20 16 15 4 3 0
735 * +------------------------------------------------------+
39ac868a
JH		 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
737 * | Packet | IP | | | | Type | Type |
738 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 739 * +------------------------------------------------------+
740 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
741 * +------------------------------------------------------+
742 * 63 48 47 32 31 20 19 0
39ac868a
JH		 743 *
744 * 82599+ Advanced Receive Descriptor (Read) Format
745 * 63 1 0
746 * +-----------------------------------------------------+
747 * 0 | Packet Buffer Address [63:1] |A0/NSE|
748 * +----------------------------------------------+------+
749 * 8 | Header Buffer Address [63:1] | DD |
750 * +-----------------------------------------------------+
751 *
752 *
753 * 82599+ Advanced Receive Descriptor (Write-Back) Format
754 *
755 * 63 48 47 32 31 30 21 20 17 16 4 3 0
756 * +------------------------------------------------------+
757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
759 * |/ Flow Dir Flt ID | | | | | |
760 * +------------------------------------------------------+
761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
762 * +------------------------------------------------------+
763 * 63 48 47 32 31 20 19 0
dcd79aeb 764 */
39ac868a 765
dcd79aeb
TI		 766 for (n = 0; n < adapter->num_rx_queues; n++) {
767 rx_ring = adapter->rx_ring[n];
c7689578
JP		 768 pr_info("------------------------------------\n");
769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
770 pr_info("------------------------------------\n");
8ad88e37
JH		 771 pr_info("%s%s%s",
772 "R [desc] [ PktBuf A0] ",
773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 774 "<-- Adv Rx Read format\n");
8ad88e37
JH		 775 pr_info("%s%s%s",
776 "RWB[desc] [PcsmIpSHl PtRs] ",
777 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 778 "<-- Adv Rx Write-Back format\n");
779
780 for (i = 0; i < rx_ring->count; i++) {
781 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 782 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 783 u0 = (struct my_u0 *)rx_desc;
784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
785 if (staterr & IXGBE_RXD_STAT_DD) {
786 /* Descriptor Done */
c7689578 787 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 788 "%016llX ---------------- %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 rx_buffer_info->skb);
792 } else {
c7689578 793 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 794 "%016llX %016llX %p", i,
795 le64_to_cpu(u0->a),
796 le64_to_cpu(u0->b),
797 (u64)rx_buffer_info->dma,
798 rx_buffer_info->skb);
799
9c50c035
ET		 800 if (netif_msg_pktdata(adapter) &&
801 rx_buffer_info->dma) {
dcd79aeb
TI		 802 print_hex_dump(KERN_INFO, "",
803 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 804 page_address(rx_buffer_info->page) +
805 rx_buffer_info->page_offset,
f800326d 806 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 807 }
808 }
809
810 if (i == rx_ring->next_to_use)
c7689578 811 pr_cont(" NTU\n");
dcd79aeb 812 else if (i == rx_ring->next_to_clean)
c7689578 813 pr_cont(" NTC\n");
dcd79aeb 814 else
c7689578 815 pr_cont("\n");
dcd79aeb
TI		 816
817 }
818 }
dcd79aeb
TI		 819}
820
5eba3699
AV		 821static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
822{
823 u32 ctrl_ext;
824
825 /* Let firmware take over control of h/w */
826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 829}
830
831static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
832{
833 u32 ctrl_ext;
834
835 /* Let firmware know the driver has taken over */
836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 839}
9a799d71 840
49ce9c2c 841/**
e8e26350
PW		 842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
843 * @adapter: pointer to adapter struct
844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
845 * @queue: queue to map the corresponding interrupt to
846 * @msix_vector: the vector to map to the corresponding queue
847 *
848 */
849static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 850 u8 queue, u8 msix_vector)
9a799d71
AK		 851{
852 u32 ivar, index;
e8e26350
PW		 853 struct ixgbe_hw *hw = &adapter->hw;
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
857 if (direction == -1)
858 direction = 0;
859 index = (((direction * 64) + queue) >> 2) & 0x1F;
860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
861 ivar &= ~(0xFF << (8 * (queue & 0x3)));
862 ivar |= (msix_vector << (8 * (queue & 0x3)));
863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
864 break;
865 case ixgbe_mac_82599EB:
b93a2226 866 case ixgbe_mac_X540:
9a75a1ac
DS		 867 case ixgbe_mac_X550:
868 case ixgbe_mac_X550EM_x:
e8e26350
PW		 869 if (direction == -1) {
870 /* other causes */
871 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
872 index = ((queue & 1) * 8);
873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
874 ivar &= ~(0xFF << index);
875 ivar |= (msix_vector << index);
876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
877 break;
878 } else {
879 /* tx or rx causes */
880 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
881 index = ((16 * (queue & 1)) + (8 * direction));
882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
883 ivar &= ~(0xFF << index);
884 ivar |= (msix_vector << index);
885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
886 break;
887 }
888 default:
889 break;
890 }
9a799d71
AK		 891}
892
fe49f04a 893static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 894 u64 qmask)
fe49f04a
AD		 895{
896 u32 mask;
897
bd508178
AD		 898 switch (adapter->hw.mac.type) {
899 case ixgbe_mac_82598EB:
fe49f04a
AD		 900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 902 break;
903 case ixgbe_mac_82599EB:
b93a2226 904 case ixgbe_mac_X540:
9a75a1ac
DS		 905 case ixgbe_mac_X550:
906 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 907 mask = (qmask & 0xFFFFFFFF);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
909 mask = (qmask >> 32);
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 911 break;
912 default:
913 break;
fe49f04a
AD		 914 }
915}
916
729739b7
AD		 917void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
918 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 919{
729739b7
AD		 920 if (tx_buffer->skb) {
921 dev_kfree_skb_any(tx_buffer->skb);
922 if (dma_unmap_len(tx_buffer, len))
d3d00239 923 dma_unmap_single(ring->dev,
729739b7
AD		 924 dma_unmap_addr(tx_buffer, dma),
925 dma_unmap_len(tx_buffer, len),
926 DMA_TO_DEVICE);
927 } else if (dma_unmap_len(tx_buffer, len)) {
928 dma_unmap_page(ring->dev,
929 dma_unmap_addr(tx_buffer, dma),
930 dma_unmap_len(tx_buffer, len),
931 DMA_TO_DEVICE);
e5a43549 932 }
729739b7
AD		 933 tx_buffer->next_to_watch = NULL;
934 tx_buffer->skb = NULL;
935 dma_unmap_len_set(tx_buffer, len, 0);
936 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 937}
938
943561d3 939static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 940{
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 943 int i;
943561d3 944 u32 data;
c84d324c 945
943561d3
AD		 946 if ((hw->fc.current_mode != ixgbe_fc_full) &&
947 (hw->fc.current_mode != ixgbe_fc_rx_pause))
948 return;
c84d324c 949
943561d3
AD		 950 switch (hw->mac.type) {
951 case ixgbe_mac_82598EB:
952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
953 break;
954 default:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
956 }
957 hwstats->lxoffrxc += data;
c84d324c 958
943561d3
AD		 959 /* refill credits (no tx hang) if we received xoff */
960 if (!data)
c84d324c 961 return;
943561d3
AD		 962
963 for (i = 0; i < adapter->num_tx_queues; i++)
964 clear_bit(__IXGBE_HANG_CHECK_ARMED,
965 &adapter->tx_ring[i]->state);
966}
967
968static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
969{
970 struct ixgbe_hw *hw = &adapter->hw;
971 struct ixgbe_hw_stats *hwstats = &adapter->stats;
972 u32 xoff[8] = {0};
2afaa00d 973 u8 tc;
943561d3
AD		 974 int i;
975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
976
977 if (adapter->ixgbe_ieee_pfc)
978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
979
980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
981 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 982 return;
943561d3 983 }
c84d324c
JF		 984
985 /* update stats for each tc, only valid with PFC enabled */
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 987 u32 pxoffrxc;
988
c84d324c
JF		 989 switch (hw->mac.type) {
990 case ixgbe_mac_82598EB:
2afaa00d 991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 992 break;
c84d324c 993 default:
2afaa00d 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 995 }
2afaa00d
PN		 996 hwstats->pxoffrxc[i] += pxoffrxc;
997 /* Get the TC for given UP */
998 tc = netdev_get_prio_tc_map(adapter->netdev, i);
999 xoff[tc] += pxoffrxc;
c84d324c
JF		 1000 }
1001
1002 /* disarm tx queues that have received xoff frames */
1003 for (i = 0; i < adapter->num_tx_queues; i++) {
1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1005
2afaa00d 1006 tc = tx_ring->dcb_tc;
c84d324c
JF		 1007 if (xoff[tc])
1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1009 }
26f23d82
YZ		 1010}
1011
c84d324c 1012static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1013{
7d7ce682 1014 return ring->stats.packets;
c84d324c
JF		 1015}
1016
1017static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1018{
2a47fa45
JF		 1019 struct ixgbe_adapter *adapter;
1020 struct ixgbe_hw *hw;
1021 u32 head, tail;
1022
1023 if (ring->l2_accel_priv)
1024 adapter = ring->l2_accel_priv->real_adapter;
1025 else
1026 adapter = netdev_priv(ring->netdev);
e01c31a5 1027
2a47fa45
JF		 1028 hw = &adapter->hw;
1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1031
1032 if (head != tail)
1033 return (head < tail) ?
1034 tail - head : (tail + ring->count - head);
1035
1036 return 0;
1037}
1038
1039static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1040{
1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1044
7d637bcc 1045 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1046
1047 /*
1048 * Check for a hung queue, but be thorough. This verifies
1049 * that a transmit has been completed since the previous
1050 * check AND there is at least one packet pending. The
1051 * ARMED bit is set to indicate a potential hang. The
1052 * bit is cleared if a pause frame is received to remove
1053 * false hang detection due to PFC or 802.3x frames. By
1054 * requiring this to fail twice we avoid races with
1055 * pfc clearing the ARMED bit and conditions where we
1056 * run the check_tx_hang logic with a transmit completion
1057 * pending but without time to complete it yet.
1058 */
e90dd264 1059 if (tx_done_old == tx_done && tx_pending)
c84d324c 1060 /* make sure it is true for two checks in a row */
e90dd264
MR		 1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1062 &tx_ring->state);
1063 /* update completed stats and continue */
1064 tx_ring->tx_stats.tx_done_old = tx_done;
1065 /* reset the countdown */
1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1067
e90dd264 1068 return false;
9a799d71
AK		 1069}
1070
c83c6cbd
AD		 1071/**
1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1073 * @adapter: driver private struct
1074 **/
1075static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1076{
1077
1078 /* Do the reset outside of interrupt context */
1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1081 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1082 ixgbe_service_event_schedule(adapter);
1083 }
1084}
e01c31a5 1085
9a799d71
AK		 1086/**
1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1088 * @q_vector: structure containing interrupt and ring information
e01c31a5 1089 * @tx_ring: tx ring to clean
9a799d71 1090 **/
fe49f04a 1091static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1092 struct ixgbe_ring *tx_ring)
9a799d71 1093{
fe49f04a 1094 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1095 struct ixgbe_tx_buffer *tx_buffer;
1096 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1097 unsigned int total_bytes = 0, total_packets = 0;
59224555 1098 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1099 unsigned int i = tx_ring->next_to_clean;
1100
1101 if (test_bit(__IXGBE_DOWN, &adapter->state))
1102 return true;
9a799d71 1103
d3d00239 1104 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1105 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1106 i -= tx_ring->count;
12207e49 1107
729739b7 1108 do {
d3d00239
AD		 1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1110
1111 /* if next_to_watch is not set then there is no work pending */
1112 if (!eop_desc)
1113 break;
1114
7f83a9e6 1115 /* prevent any other reads prior to eop_desc */
7e63bf49 1116 read_barrier_depends();
7f83a9e6 1117
d3d00239
AD		 1118 /* if DD is not set pending work has not been completed */
1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1120 break;
8ad494b0 1121
d3d00239
AD		 1122 /* clear next_to_watch to prevent false hangs */
1123 tx_buffer->next_to_watch = NULL;
8ad494b0 1124
091a6246
AD		 1125 /* update the statistics for this packet */
1126 total_bytes += tx_buffer->bytecount;
1127 total_packets += tx_buffer->gso_segs;
1128
fd0db0ed 1129 /* free the skb */
fe1f2a97 1130 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1131
729739b7
AD		 1132 /* unmap skb header data */
1133 dma_unmap_single(tx_ring->dev,
1134 dma_unmap_addr(tx_buffer, dma),
1135 dma_unmap_len(tx_buffer, len),
1136 DMA_TO_DEVICE);
1137
fd0db0ed
AD		 1138 /* clear tx_buffer data */
1139 tx_buffer->skb = NULL;
729739b7 1140 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1141
729739b7
AD		 1142 /* unmap remaining buffers */
1143 while (tx_desc != eop_desc) {
d3d00239
AD		 1144 tx_buffer++;
1145 tx_desc++;
8ad494b0 1146 i++;
729739b7
AD		 1147 if (unlikely(!i)) {
1148 i -= tx_ring->count;
d3d00239 1149 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1151 }
e01c31a5 1152
729739b7
AD		 1153 /* unmap any remaining paged data */
1154 if (dma_unmap_len(tx_buffer, len)) {
1155 dma_unmap_page(tx_ring->dev,
1156 dma_unmap_addr(tx_buffer, dma),
1157 dma_unmap_len(tx_buffer, len),
1158 DMA_TO_DEVICE);
1159 dma_unmap_len_set(tx_buffer, len, 0);
1160 }
1161 }
1162
1163 /* move us one more past the eop_desc for start of next pkt */
1164 tx_buffer++;
1165 tx_desc++;
1166 i++;
1167 if (unlikely(!i)) {
1168 i -= tx_ring->count;
1169 tx_buffer = tx_ring->tx_buffer_info;
1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1171 }
1172
1173 /* issue prefetch for next Tx descriptor */
1174 prefetch(tx_desc);
12207e49 1175
729739b7
AD		 1176 /* update budget accounting */
1177 budget--;
1178 } while (likely(budget));
1179
1180 i += tx_ring->count;
9a799d71 1181 tx_ring->next_to_clean = i;
d3d00239 1182 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1183 tx_ring->stats.bytes += total_bytes;
bd198058 1184 tx_ring->stats.packets += total_packets;
d3d00239 1185 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1186 q_vector->tx.total_bytes += total_bytes;
1187 q_vector->tx.total_packets += total_packets;
b953799e 1188
c84d324c
JF		 1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1190 /* schedule immediate reset if we believe we hung */
1191 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1192 e_err(drv, "Detected Tx Unit Hang\n"
1193 " Tx Queue <%d>\n"
1194 " TDH, TDT <%x>, <%x>\n"
1195 " next_to_use <%x>\n"
1196 " next_to_clean <%x>\n"
1197 "tx_buffer_info[next_to_clean]\n"
1198 " time_stamp <%lx>\n"
1199 " jiffies <%lx>\n",
1200 tx_ring->queue_index,
1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1203 tx_ring->next_to_use, i,
1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1205
1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1207
1208 e_info(probe,
1209 "tx hang %d detected on queue %d, resetting adapter\n",
1210 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1211
b953799e 1212 /* schedule immediate reset if we believe we hung */
c83c6cbd 1213 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1214
1215 /* the adapter is about to reset, no point in enabling stuff */
59224555 1216 return true;
b953799e 1217 }
9a799d71 1218
b2d96e0a
AD		 1219 netdev_tx_completed_queue(txring_txq(tx_ring),
1220 total_packets, total_bytes);
1221
e092be60 1222#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1225 /* Make sure that anybody stopping the queue after this
1226 * sees the new next_to_clean.
1227 */
1228 smp_mb();
729739b7
AD		 1229 if (__netif_subqueue_stopped(tx_ring->netdev,
1230 tx_ring->queue_index)
1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1232 netif_wake_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
5b7da515 1234 ++tx_ring->tx_stats.restart_queue;
30eba97a 1235 }
e092be60 1236 }
9a799d71 1237
59224555 1238 return !!budget;
9a799d71
AK		 1239}
1240
5dd2d332 1241#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1242static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1243 struct ixgbe_ring *tx_ring,
33cf09c9 1244 int cpu)
bd0362dd 1245{
33cf09c9 1246 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1247 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1248 u16 reg_offset;
33cf09c9 1249
33cf09c9
AD		 1250 switch (hw->mac.type) {
1251 case ixgbe_mac_82598EB:
bdda1a61 1252 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1253 break;
1254 case ixgbe_mac_82599EB:
b93a2226 1255 case ixgbe_mac_X540:
bdda1a61
AD		 1256 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1257 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1258 break;
1259 default:
bdda1a61
AD		 1260 /* for unknown hardware do not write register */
1261 return;
bd0362dd 1262 }
bdda1a61
AD		 1263
1264 /*
1265 * We can enable relaxed ordering for reads, but not writes when
1266 * DCA is enabled. This is due to a known issue in some chipsets
1267 * which will cause the DCA tag to be cleared.
1268 */
1269 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1270 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1271 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1272
1273 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1274}
1275
bdda1a61
AD		 1276static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1277 struct ixgbe_ring *rx_ring,
33cf09c9 1278 int cpu)
bd0362dd 1279{
33cf09c9 1280 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1281 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1282 u8 reg_idx = rx_ring->reg_idx;
1283
33cf09c9
AD		 1284
1285 switch (hw->mac.type) {
33cf09c9 1286 case ixgbe_mac_82599EB:
b93a2226 1287 case ixgbe_mac_X540:
bdda1a61 1288 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1289 break;
1290 default:
1291 break;
1292 }
bdda1a61
AD		 1293
1294 /*
1295 * We can enable relaxed ordering for reads, but not writes when
1296 * DCA is enabled. This is due to a known issue in some chipsets
1297 * which will cause the DCA tag to be cleared.
1298 */
1299 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1300 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1301
1302 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1303}
1304
1305static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1306{
1307 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1308 struct ixgbe_ring *ring;
bd0362dd 1309 int cpu = get_cpu();
bd0362dd 1310
33cf09c9
AD		 1311 if (q_vector->cpu == cpu)
1312 goto out_no_update;
1313
a557928e 1314 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1315 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1316
a557928e 1317 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1318 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1319
1320 q_vector->cpu = cpu;
1321out_no_update:
bd0362dd
JC		 1322 put_cpu();
1323}
1324
1325static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1326{
1327 int i;
1328
1329 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1330 return;
1331
e35ec126
AD		 1332 /* always use CB2 mode, difference is masked in the CB driver */
1333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1334
49c7ffbe 1335 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1336 adapter->q_vector[i]->cpu = -1;
1337 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1338 }
1339}
1340
1341static int __ixgbe_notify_dca(struct device *dev, void *data)
1342{
c60fbb00 1343 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1344 unsigned long event = *(unsigned long *)data;
1345
2a72c31e 1346 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1347 return 0;
1348
bd0362dd
JC		 1349 switch (event) {
1350 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1351 /* if we're already enabled, don't do it again */
1352 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1353 break;
652f093f 1354 if (dca_add_requester(dev) == 0) {
96b0e0f6 1355 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1356 ixgbe_setup_dca(adapter);
1357 break;
1358 }
1359 /* Fall Through since DCA is disabled. */
1360 case DCA_PROVIDER_REMOVE:
1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1362 dca_remove_requester(dev);
1363 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1365 }
1366 break;
1367 }
1368
652f093f 1369 return 0;
bd0362dd 1370}
67a74ee2 1371
bdda1a61 1372#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1373
1374#define IXGBE_RSS_L4_TYPES_MASK \
1375 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1376 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1377 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1378 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1379
8a0da21b
AD		 1380static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1381 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1382 struct sk_buff *skb)
1383{
7edda4b8
FD		 1384 u16 rss_type;
1385
1386 if (!(ring->netdev->features & NETIF_F_RXHASH))
1387 return;
1388
1389 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1390 IXGBE_RXDADV_RSSTYPE_MASK;
1391
1392 if (!rss_type)
1393 return;
1394
1395 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1396 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1397 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1398}
1399
f800326d 1400#ifdef IXGBE_FCOE
ff886dfc
AD		 1401/**
1402 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1403 * @ring: structure containing ring specific data
ff886dfc
AD		 1404 * @rx_desc: advanced rx descriptor
1405 *
1406 * Returns : true if it is FCoE pkt
1407 */
57efd44c 1408static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1409 union ixgbe_adv_rx_desc *rx_desc)
1410{
1411 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1412
57efd44c 1413 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1414 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1415 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1416 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1417}
1418
f800326d 1419#endif /* IXGBE_FCOE */
e59bd25d
AV		 1420/**
1421 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1422 * @ring: structure containing ring specific data
1423 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1424 * @skb: skb currently being received and modified
1425 **/
8a0da21b 1426static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1427 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1428 struct sk_buff *skb)
9a799d71 1429{
3f207800
DS		 1430 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1431 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1432 bool encap_pkt = false;
1433
8a0da21b 1434 skb_checksum_none_assert(skb);
9a799d71 1435
712744be 1436 /* Rx csum disabled */
8a0da21b 1437 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1438 return;
e59bd25d 1439
3f207800
DS		 1440 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1441 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1442 encap_pkt = true;
1443 skb->encapsulation = 1;
3f207800
DS		 1444 }
1445
e59bd25d 1446 /* if IP and error */
f56e0cb1
AD		 1447 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1448 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1449 ring->rx_stats.csum_err++;
9a799d71
AK		 1450 return;
1451 }
e59bd25d 1452
f56e0cb1 1453 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1454 return;
1455
f56e0cb1 1456 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1457 /*
1458 * 82599 errata, UDP frames with a 0 checksum can be marked as
1459 * checksum errors.
1460 */
8a0da21b
AD		 1461 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1462 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1463 return;
1464
8a0da21b 1465 ring->rx_stats.csum_err++;
e59bd25d
AV		 1466 return;
1467 }
1468
9a799d71 1469 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1470 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1471 if (encap_pkt) {
1472 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1473 return;
1474
1475 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1476 ring->rx_stats.csum_err++;
1477 return;
1478 }
1479 /* If we checked the outer header let the stack know */
1480 skb->csum_level = 1;
1481 }
9a799d71
AK		 1482}
1483
f990b79b
AD		 1484static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1485 struct ixgbe_rx_buffer *bi)
1486{
1487 struct page *page = bi->page;
18cb652a 1488 dma_addr_t dma;
f990b79b 1489
f800326d 1490 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1491 if (likely(page))
f990b79b
AD		 1492 return true;
1493
f800326d 1494 /* alloc new page for storage */
18cb652a
AD		 1495 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1496 if (unlikely(!page)) {
1497 rx_ring->rx_stats.alloc_rx_page_failed++;
1498 return false;
f990b79b
AD		 1499 }
1500
f800326d
AD		 1501 /* map page for use */
1502 dma = dma_map_page(rx_ring->dev, page, 0,
1503 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1504
1505 /*
1506 * if mapping failed free memory back to system since
1507 * there isn't much point in holding memory we can't use
1508 */
1509 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1510 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1511
f990b79b
AD		 1512 rx_ring->rx_stats.alloc_rx_page_failed++;
1513 return false;
1514 }
1515
f800326d 1516 bi->dma = dma;
18cb652a 1517 bi->page = page;
afaa9459 1518 bi->page_offset = 0;
f800326d 1519
f990b79b
AD		 1520 return true;
1521}
1522
9a799d71 1523/**
f990b79b 1524 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1525 * @rx_ring: ring to place buffers on
1526 * @cleaned_count: number of buffers to replace
9a799d71 1527 **/
fc77dc3c 1528void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1529{
9a799d71 1530 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1531 struct ixgbe_rx_buffer *bi;
d5f398ed 1532 u16 i = rx_ring->next_to_use;
9a799d71 1533
f800326d
AD		 1534 /* nothing to do */
1535 if (!cleaned_count)
fc77dc3c
AD		 1536 return;
1537
e4f74028 1538 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1539 bi = &rx_ring->rx_buffer_info[i];
1540 i -= rx_ring->count;
9a799d71 1541
f800326d
AD		 1542 do {
1543 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1544 break;
d5f398ed 1545
f800326d
AD		 1546 /*
1547 * Refresh the desc even if buffer_addrs didn't change
1548 * because each write-back erases this info.
1549 */
1550 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1551
f990b79b
AD		 1552 rx_desc++;
1553 bi++;
9a799d71 1554 i++;
f990b79b 1555 if (unlikely(!i)) {
e4f74028 1556 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1557 bi = rx_ring->rx_buffer_info;
1558 i -= rx_ring->count;
1559 }
1560
18cb652a
AD		 1561 /* clear the status bits for the next_to_use descriptor */
1562 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1563
1564 cleaned_count--;
1565 } while (cleaned_count);
7c6e0a43 1566
f990b79b
AD		 1567 i += rx_ring->count;
1568
ad435ec6
AD		 1569 if (rx_ring->next_to_use != i) {
1570 rx_ring->next_to_use = i;
1571
1572 /* update next to alloc since we have filled the ring */
1573 rx_ring->next_to_alloc = i;
1574
1575 /* Force memory writes to complete before letting h/w
1576 * know there are new descriptors to fetch. (Only
1577 * applicable for weak-ordered memory model archs,
1578 * such as IA-64).
1579 */
1580 wmb();
1581 writel(i, rx_ring->tail);
1582 }
9a799d71
AK		 1583}
1584
1d2024f6
AD		 1585static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1586 struct sk_buff *skb)
1587{
f800326d 1588 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1589
1590 /* set gso_size to avoid messing up TCP MSS */
1591 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1592 IXGBE_CB(skb)->append_cnt);
96be80ab 1593 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1594}
1595
1596static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1597 struct sk_buff *skb)
1598{
1599 /* if append_cnt is 0 then frame is not RSC */
1600 if (!IXGBE_CB(skb)->append_cnt)
1601 return;
1602
1603 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1604 rx_ring->rx_stats.rsc_flush++;
1605
1606 ixgbe_set_rsc_gso_size(rx_ring, skb);
1607
1608 /* gso_size is computed using append_cnt so always clear it last */
1609 IXGBE_CB(skb)->append_cnt = 0;
1610}
1611
8a0da21b
AD		 1612/**
1613 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1614 * @rx_ring: rx descriptor ring packet is being transacted on
1615 * @rx_desc: pointer to the EOP Rx descriptor
1616 * @skb: pointer to current skb being populated
f8212f97 1617 *
8a0da21b
AD		 1618 * This function checks the ring, descriptor, and packet information in
1619 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1620 * other fields within the skb.
f8212f97 1621 **/
8a0da21b
AD		 1622static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1623 union ixgbe_adv_rx_desc *rx_desc,
1624 struct sk_buff *skb)
f8212f97 1625{
43e95f11
JF		 1626 struct net_device *dev = rx_ring->netdev;
1627
8a0da21b
AD		 1628 ixgbe_update_rsc_stats(rx_ring, skb);
1629
1630 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1631
8a0da21b
AD		 1632 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1633
eda183c2
JK		 1634 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1635 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1636
f646968f 1637 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1638 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1639 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1640 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1641 }
1642
8a0da21b 1643 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1644
43e95f11 1645 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1646}
1647
8a0da21b
AD		 1648static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1649 struct sk_buff *skb)
aa80175a 1650{
b4640030 1651 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1652 netif_receive_skb(skb);
8a0da21b 1653 else
856f606e 1654 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1655}
43634e82 1656
f800326d
AD		 1657/**
1658 * ixgbe_is_non_eop - process handling of non-EOP buffers
1659 * @rx_ring: Rx ring being processed
1660 * @rx_desc: Rx descriptor for current buffer
1661 * @skb: Current socket buffer containing buffer in progress
1662 *
1663 * This function updates next to clean. If the buffer is an EOP buffer
1664 * this function exits returning false, otherwise it will place the
1665 * sk_buff in the next buffer to be chained and return true indicating
1666 * that this is in fact a non-EOP buffer.
1667 **/
1668static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1669 union ixgbe_adv_rx_desc *rx_desc,
1670 struct sk_buff *skb)
1671{
1672 u32 ntc = rx_ring->next_to_clean + 1;
1673
1674 /* fetch, update, and store next to clean */
1675 ntc = (ntc < rx_ring->count) ? ntc : 0;
1676 rx_ring->next_to_clean = ntc;
1677
1678 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1679
5a02cbd1
AD		 1680 /* update RSC append count if present */
1681 if (ring_is_rsc_enabled(rx_ring)) {
1682 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1683 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1684
1685 if (unlikely(rsc_enabled)) {
1686 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1687
1688 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1689 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1690
5a02cbd1
AD		 1691 /* update ntc based on RSC value */
1692 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1693 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1694 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1695 }
f800326d
AD		 1696 }
1697
5a02cbd1
AD		 1698 /* if we are the last buffer then there is nothing else to do */
1699 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1700 return false;
1701
f800326d
AD		 1702 /* place skb in next buffer to be received */
1703 rx_ring->rx_buffer_info[ntc].skb = skb;
1704 rx_ring->rx_stats.non_eop_descs++;
1705
1706 return true;
1707}
1708
19861ce2
AD		 1709/**
1710 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1711 * @rx_ring: rx descriptor ring packet is being transacted on
1712 * @skb: pointer to current skb being adjusted
1713 *
1714 * This function is an ixgbe specific version of __pskb_pull_tail. The
1715 * main difference between this version and the original function is that
1716 * this function can make several assumptions about the state of things
1717 * that allow for significant optimizations versus the standard function.
1718 * As a result we can do things like drop a frag and maintain an accurate
1719 * truesize for the skb.
1720 */
1721static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1722 struct sk_buff *skb)
1723{
1724 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1725 unsigned char *va;
1726 unsigned int pull_len;
1727
1728 /*
1729 * it is valid to use page_address instead of kmap since we are
1730 * working with pages allocated out of the lomem pool per
1731 * alloc_page(GFP_ATOMIC)
1732 */
1733 va = skb_frag_address(frag);
1734
1735 /*
1736 * we need the header to contain the greater of either ETH_HLEN or
1737 * 60 bytes if the skb->len is less than 60 for skb_pad.
1738 */
8496e338 1739 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1740
1741 /* align pull length to size of long to optimize memcpy performance */
1742 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1743
1744 /* update all of the pointers */
1745 skb_frag_size_sub(frag, pull_len);
1746 frag->page_offset += pull_len;
1747 skb->data_len -= pull_len;
1748 skb->tail += pull_len;
19861ce2
AD		 1749}
1750
42073d91
AD		 1751/**
1752 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1753 * @rx_ring: rx descriptor ring packet is being transacted on
1754 * @skb: pointer to current skb being updated
1755 *
1756 * This function provides a basic DMA sync up for the first fragment of an
1757 * skb. The reason for doing this is that the first fragment cannot be
1758 * unmapped until we have reached the end of packet descriptor for a buffer
1759 * chain.
1760 */
1761static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1762 struct sk_buff *skb)
1763{
1764 /* if the page was released unmap it, else just sync our portion */
1765 if (unlikely(IXGBE_CB(skb)->page_released)) {
1766 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1767 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1768 IXGBE_CB(skb)->page_released = false;
1769 } else {
1770 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1771
1772 dma_sync_single_range_for_cpu(rx_ring->dev,
1773 IXGBE_CB(skb)->dma,
1774 frag->page_offset,
1775 ixgbe_rx_bufsz(rx_ring),
1776 DMA_FROM_DEVICE);
1777 }
1778 IXGBE_CB(skb)->dma = 0;
1779}
1780
f800326d
AD		 1781/**
1782 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1783 * @rx_ring: rx descriptor ring packet is being transacted on
1784 * @rx_desc: pointer to the EOP Rx descriptor
1785 * @skb: pointer to current skb being fixed
1786 *
1787 * Check for corrupted packet headers caused by senders on the local L2
1788 * embedded NIC switch not setting up their Tx Descriptors right. These
1789 * should be very rare.
1790 *
1791 * Also address the case where we are pulling data in on pages only
1792 * and as such no data is present in the skb header.
1793 *
1794 * In addition if skb is not at least 60 bytes we need to pad it so that
1795 * it is large enough to qualify as a valid Ethernet frame.
1796 *
1797 * Returns true if an error was encountered and skb was freed.
1798 **/
1799static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1800 union ixgbe_adv_rx_desc *rx_desc,
1801 struct sk_buff *skb)
1802{
f800326d 1803 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1804
1805 /* verify that the packet does not have any known errors */
1806 if (unlikely(ixgbe_test_staterr(rx_desc,
1807 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1808 !(netdev->features & NETIF_F_RXALL))) {
1809 dev_kfree_skb_any(skb);
1810 return true;
1811 }
1812
19861ce2 1813 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1814 if (skb_is_nonlinear(skb))
1815 ixgbe_pull_tail(rx_ring, skb);
f800326d 1816
57efd44c
AD		 1817#ifdef IXGBE_FCOE
1818 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1819 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1820 return false;
1821
1822#endif
a94d9e22
AD		 1823 /* if eth_skb_pad returns an error the skb was freed */
1824 if (eth_skb_pad(skb))
1825 return true;
f800326d
AD		 1826
1827 return false;
1828}
1829
f800326d
AD		 1830/**
1831 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1832 * @rx_ring: rx descriptor ring to store buffers on
1833 * @old_buff: donor buffer to have page reused
1834 *
0549ae20 1835 * Synchronizes page for reuse by the adapter
f800326d
AD		 1836 **/
1837static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1838 struct ixgbe_rx_buffer *old_buff)
1839{
1840 struct ixgbe_rx_buffer *new_buff;
1841 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1842
1843 new_buff = &rx_ring->rx_buffer_info[nta];
1844
1845 /* update, and store next to alloc */
1846 nta++;
1847 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1848
1849 /* transfer page from old buffer to new buffer */
18cb652a 1850 *new_buff = *old_buff;
f800326d
AD		 1851
1852 /* sync the buffer for use by the device */
1853 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1854 new_buff->page_offset,
1855 ixgbe_rx_bufsz(rx_ring),
f800326d 1856 DMA_FROM_DEVICE);
f800326d
AD		 1857}
1858
18cb652a
AD		 1859static inline bool ixgbe_page_is_reserved(struct page *page)
1860{
2f064f34 1861 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1862}
1863
f800326d
AD		 1864/**
1865 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1866 * @rx_ring: rx descriptor ring to transact packets on
1867 * @rx_buffer: buffer containing page to add
1868 * @rx_desc: descriptor containing length of buffer written by hardware
1869 * @skb: sk_buff to place the data into
1870 *
0549ae20
AD		 1871 * This function will add the data contained in rx_buffer->page to the skb.
1872 * This is done either through a direct copy if the data in the buffer is
1873 * less than the skb header size, otherwise it will just attach the page as
1874 * a frag to the skb.
1875 *
1876 * The function will then update the page offset if necessary and return
1877 * true if the buffer can be reused by the adapter.
f800326d 1878 **/
0549ae20 1879static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1880 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1881 union ixgbe_adv_rx_desc *rx_desc,
1882 struct sk_buff *skb)
f800326d 1883{
0549ae20
AD		 1884 struct page *page = rx_buffer->page;
1885 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1886#if (PAGE_SIZE < 8192)
0549ae20 1887 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1888#else
1889 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1890 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1891 ixgbe_rx_bufsz(rx_ring);
1892#endif
0549ae20 1893
cf3fe7ac
AD		 1894 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1895 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1896
1897 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1898
18cb652a
AD		 1899 /* page is not reserved, we can reuse buffer as-is */
1900 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1901 return true;
1902
1903 /* this page cannot be reused so discard it */
18cb652a 1904 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1905 return false;
1906 }
1907
0549ae20
AD		 1908 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1909 rx_buffer->page_offset, size, truesize);
1910
09816fbe 1911 /* avoid re-using remote pages */
18cb652a 1912 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1913 return false;
1914
1915#if (PAGE_SIZE < 8192)
1916 /* if we are only owner of page we can reuse it */
1917 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1918 return false;
1919
1920 /* flip page offset to other buffer */
1921 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1922#else
1923 /* move offset up to the next cache line */
1924 rx_buffer->page_offset += truesize;
1925
1926 if (rx_buffer->page_offset > last_offset)
1927 return false;
09816fbe 1928#endif
0549ae20 1929
18cb652a
AD		 1930 /* Even if we own the page, we are not allowed to use atomic_set()
1931 * This would break get_page_unless_zero() users.
1932 */
1933 atomic_inc(&page->_count);
1934
0549ae20 1935 return true;
f800326d
AD		 1936}
1937
18806c9e
AD		 1938static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1939 union ixgbe_adv_rx_desc *rx_desc)
1940{
1941 struct ixgbe_rx_buffer *rx_buffer;
1942 struct sk_buff *skb;
1943 struct page *page;
1944
1945 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1946 page = rx_buffer->page;
1947 prefetchw(page);
1948
1949 skb = rx_buffer->skb;
1950
1951 if (likely(!skb)) {
1952 void *page_addr = page_address(page) +
1953 rx_buffer->page_offset;
1954
1955 /* prefetch first cache line of first page */
1956 prefetch(page_addr);
1957#if L1_CACHE_BYTES < 128
1958 prefetch(page_addr + L1_CACHE_BYTES);
1959#endif
1960
1961 /* allocate a skb to store the frags */
67fd893e
AD		 1962 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1963 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1964 if (unlikely(!skb)) {
1965 rx_ring->rx_stats.alloc_rx_buff_failed++;
1966 return NULL;
1967 }
1968
1969 /*
1970 * we will be copying header into skb->data in
1971 * pskb_may_pull so it is in our interest to prefetch
1972 * it now to avoid a possible cache miss
1973 */
1974 prefetchw(skb->data);
1975
1976 /*
1977 * Delay unmapping of the first packet. It carries the
1978 * header information, HW may still access the header
1979 * after the writeback. Only unmap it when EOP is
1980 * reached
1981 */
1982 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1983 goto dma_sync;
1984
1985 IXGBE_CB(skb)->dma = rx_buffer->dma;
1986 } else {
1987 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1988 ixgbe_dma_sync_frag(rx_ring, skb);
1989
1990dma_sync:
1991 /* we are reusing so sync this buffer for CPU use */
1992 dma_sync_single_range_for_cpu(rx_ring->dev,
1993 rx_buffer->dma,
1994 rx_buffer->page_offset,
1995 ixgbe_rx_bufsz(rx_ring),
1996 DMA_FROM_DEVICE);
18cb652a
AD		 1997
1998 rx_buffer->skb = NULL;
18806c9e
AD		 1999 }
2000
2001 /* pull page into skb */
2002 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2003 /* hand second half of page back to the ring */
2004 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2005 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2006 /* the page has been released from the ring */
2007 IXGBE_CB(skb)->page_released = true;
2008 } else {
2009 /* we are not reusing the buffer so unmap it */
2010 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2011 ixgbe_rx_pg_size(rx_ring),
2012 DMA_FROM_DEVICE);
2013 }
2014
2015 /* clear contents of buffer_info */
18806c9e
AD		 2016 rx_buffer->page = NULL;
2017
2018 return skb;
f800326d
AD		 2019}
2020
2021/**
2022 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2023 * @q_vector: structure containing interrupt and ring information
2024 * @rx_ring: rx descriptor ring to transact packets on
2025 * @budget: Total limit on number of packets to process
2026 *
2027 * This function provides a "bounce buffer" approach to Rx interrupt
2028 * processing. The advantage to this is that on systems that have
2029 * expensive overhead for IOMMU access this provides a means of avoiding
2030 * it by maintaining the mapping of the page to the syste.
2031 *
5a85e737 2032 * Returns amount of work completed
f800326d 2033 **/
5a85e737 2034static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2035 struct ixgbe_ring *rx_ring,
f4de00ed 2036 const int budget)
9a799d71 2037{
d2f4fbe2 2038 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2039#ifdef IXGBE_FCOE
f800326d 2040 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2041 int ddp_bytes;
2042 unsigned int mss = 0;
3d8fd385 2043#endif /* IXGBE_FCOE */
f800326d 2044 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2045
fdabfc8a 2046 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2047 union ixgbe_adv_rx_desc *rx_desc;
2048 struct sk_buff *skb;
f800326d
AD		 2049
2050 /* return some buffers to hardware, one at a time is too slow */
2051 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2052 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2053 cleaned_count = 0;
2054 }
2055
18806c9e 2056 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2057
124b74c1 2058 if (!rx_desc->wb.upper.status_error)
f800326d 2059 break;
9a799d71 2060
124b74c1 2061 /* This memory barrier is needed to keep us from reading
f800326d 2062 * any other fields out of the rx_desc until we know the
124b74c1 2063 * descriptor has been written back
f800326d 2064 */
124b74c1 2065 dma_rmb();
9a799d71 2066
18806c9e
AD		 2067 /* retrieve a buffer from the ring */
2068 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2069
18806c9e
AD		 2070 /* exit if we failed to retrieve a buffer */
2071 if (!skb)
2072 break;
9a799d71 2073
9a799d71 2074 cleaned_count++;
f8212f97 2075
f800326d
AD		 2076 /* place incomplete frames back on ring for completion */
2077 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2078 continue;
c267fc16 2079
f800326d
AD		 2080 /* verify the packet layout is correct */
2081 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2082 continue;
9a799d71 2083
d2f4fbe2
AV		 2084 /* probably a little skewed due to removing CRC */
2085 total_rx_bytes += skb->len;
d2f4fbe2 2086
8a0da21b
AD		 2087 /* populate checksum, timestamp, VLAN, and protocol */
2088 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2089
332d4a7d
YZ		 2090#ifdef IXGBE_FCOE
2091 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2092 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2093 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2094 /* include DDPed FCoE data */
2095 if (ddp_bytes > 0) {
2096 if (!mss) {
2097 mss = rx_ring->netdev->mtu -
2098 sizeof(struct fcoe_hdr) -
2099 sizeof(struct fc_frame_header) -
2100 sizeof(struct fcoe_crc_eof);
2101 if (mss > 512)
2102 mss &= ~511;
2103 }
2104 total_rx_bytes += ddp_bytes;
2105 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2106 mss);
2107 }
63d635b2
AD		 2108 if (!ddp_bytes) {
2109 dev_kfree_skb_any(skb);
f800326d 2110 continue;
63d635b2 2111 }
3d8fd385 2112 }
f800326d 2113
332d4a7d 2114#endif /* IXGBE_FCOE */
8b80cda5 2115 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2116 ixgbe_rx_skb(q_vector, skb);
9a799d71 2117
f800326d 2118 /* update budget accounting */
f4de00ed 2119 total_rx_packets++;
fdabfc8a 2120 }
9a799d71 2121
c267fc16
AD		 2122 u64_stats_update_begin(&rx_ring->syncp);
2123 rx_ring->stats.packets += total_rx_packets;
2124 rx_ring->stats.bytes += total_rx_bytes;
2125 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2126 q_vector->rx.total_packets += total_rx_packets;
2127 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2128
5a85e737 2129 return total_rx_packets;
9a799d71
AK		 2130}
2131
e0d1095a 2132#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2133/* must be called with local_bh_disable()d */
2134static int ixgbe_low_latency_recv(struct napi_struct *napi)
2135{
2136 struct ixgbe_q_vector *q_vector =
2137 container_of(napi, struct ixgbe_q_vector, napi);
2138 struct ixgbe_adapter *adapter = q_vector->adapter;
2139 struct ixgbe_ring *ring;
2140 int found = 0;
2141
2142 if (test_bit(__IXGBE_DOWN, &adapter->state))
2143 return LL_FLUSH_FAILED;
2144
2145 if (!ixgbe_qv_lock_poll(q_vector))
2146 return LL_FLUSH_BUSY;
2147
2148 ixgbe_for_each_ring(ring, q_vector->rx) {
2149 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2150#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2151 if (found)
2152 ring->stats.cleaned += found;
2153 else
2154 ring->stats.misses++;
2155#endif
5a85e737
ET		 2156 if (found)
2157 break;
2158 }
2159
2160 ixgbe_qv_unlock_poll(q_vector);
2161
2162 return found;
2163}
e0d1095a 2164#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2165
9a799d71
AK		 2166/**
2167 * ixgbe_configure_msix - Configure MSI-X hardware
2168 * @adapter: board private structure
2169 *
2170 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2171 * interrupts.
2172 **/
2173static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2174{
021230d4 2175 struct ixgbe_q_vector *q_vector;
49c7ffbe 2176 int v_idx;
021230d4 2177 u32 mask;
9a799d71 2178
8e34d1aa
AD		 2179 /* Populate MSIX to EITR Select */
2180 if (adapter->num_vfs > 32) {
2181 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2183 }
2184
4df10466
JB		 2185 /*
2186 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2187 * corresponding register.
2188 */
49c7ffbe 2189 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2190 struct ixgbe_ring *ring;
7a921c93 2191 q_vector = adapter->q_vector[v_idx];
021230d4 2192
a557928e 2193 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2194 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2195
a557928e 2196 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2197 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2198
fe49f04a 2199 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2200 }
2201
bd508178
AD		 2202 switch (adapter->hw.mac.type) {
2203 case ixgbe_mac_82598EB:
e8e26350 2204 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2205 v_idx);
bd508178
AD		 2206 break;
2207 case ixgbe_mac_82599EB:
b93a2226 2208 case ixgbe_mac_X540:
9a75a1ac
DS		 2209 case ixgbe_mac_X550:
2210 case ixgbe_mac_X550EM_x:
e8e26350 2211 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2212 break;
bd508178
AD		 2213 default:
2214 break;
2215 }
021230d4
AV		 2216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2217
41fb9248 2218 /* set up to autoclear timer, and the vectors */
021230d4 2219 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2220 mask &= ~(IXGBE_EIMS_OTHER |
2221 IXGBE_EIMS_MAILBOX |
2222 IXGBE_EIMS_LSC);
2223
021230d4 2224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2225}
2226
f494e8fa
AV		 2227enum latency_range {
2228 lowest_latency = 0,
2229 low_latency = 1,
2230 bulk_latency = 2,
2231 latency_invalid = 255
2232};
2233
2234/**
2235 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2236 * @q_vector: structure containing interrupt and ring information
2237 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2238 *
2239 * Stores a new ITR value based on packets and byte
2240 * counts during the last interrupt. The advantage of per interrupt
2241 * computation is faster updates and more accurate ITR for the current
2242 * traffic pattern. Constants in this function were computed
2243 * based on theoretical maximum wire speed and thresholds were set based
2244 * on testing data as well as attempting to minimize response time
2245 * while increasing bulk throughput.
2246 * this functionality is controlled by the InterruptThrottleRate module
2247 * parameter (see ixgbe_param.c)
2248 **/
bd198058
AD		 2249static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2250 struct ixgbe_ring_container *ring_container)
f494e8fa 2251{
bd198058
AD		 2252 int bytes = ring_container->total_bytes;
2253 int packets = ring_container->total_packets;
2254 u32 timepassed_us;
621bd70e 2255 u64 bytes_perint;
bd198058 2256 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2257
2258 if (packets == 0)
bd198058 2259 return;
f494e8fa
AV		 2260
2261 /* simple throttlerate management
621bd70e
AD		 2262 * 0-10MB/s lowest (100000 ints/s)
2263 * 10-20MB/s low (20000 ints/s)
8ac34f10 2264 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2265 */
2266 /* what was last interrupt timeslice? */
d5bf4f67 2267 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2268 if (timepassed_us == 0)
2269 return;
2270
f494e8fa
AV		 2271 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2272
2273 switch (itr_setting) {
2274 case lowest_latency:
621bd70e 2275 if (bytes_perint > 10)
bd198058 2276 itr_setting = low_latency;
f494e8fa
AV		 2277 break;
2278 case low_latency:
621bd70e 2279 if (bytes_perint > 20)
bd198058 2280 itr_setting = bulk_latency;
621bd70e 2281 else if (bytes_perint <= 10)
bd198058 2282 itr_setting = lowest_latency;
f494e8fa
AV		 2283 break;
2284 case bulk_latency:
621bd70e 2285 if (bytes_perint <= 20)
bd198058 2286 itr_setting = low_latency;
f494e8fa
AV		 2287 break;
2288 }
2289
bd198058
AD		 2290 /* clear work counters since we have the values we need */
2291 ring_container->total_bytes = 0;
2292 ring_container->total_packets = 0;
2293
2294 /* write updated itr to ring container */
2295 ring_container->itr = itr_setting;
f494e8fa
AV		 2296}
2297
509ee935
JB		 2298/**
2299 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2300 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2301 *
2302 * This function is made to be called by ethtool and by the driver
2303 * when it needs to update EITR registers at runtime. Hardware
2304 * specific quirks/differences are taken care of here.
2305 */
fe49f04a 2306void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2307{
fe49f04a 2308 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2309 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2310 int v_idx = q_vector->v_idx;
5d967eb7 2311 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2312
bd508178
AD		 2313 switch (adapter->hw.mac.type) {
2314 case ixgbe_mac_82598EB:
509ee935
JB		 2315 /* must write high and low 16 bits to reset counter */
2316 itr_reg |= (itr_reg << 16);
bd508178
AD		 2317 break;
2318 case ixgbe_mac_82599EB:
b93a2226 2319 case ixgbe_mac_X540:
9a75a1ac
DS		 2320 case ixgbe_mac_X550:
2321 case ixgbe_mac_X550EM_x:
509ee935
JB		 2322 /*
2323 * set the WDIS bit to not clear the timer bits and cause an
2324 * immediate assertion of the interrupt
2325 */
2326 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2327 break;
2328 default:
2329 break;
509ee935
JB		 2330 }
2331 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2332}
2333
bd198058 2334static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2335{
d5bf4f67 2336 u32 new_itr = q_vector->itr;
bd198058 2337 u8 current_itr;
f494e8fa 2338
bd198058
AD		 2339 ixgbe_update_itr(q_vector, &q_vector->tx);
2340 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2341
08c8833b 2342 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2343
2344 switch (current_itr) {
2345 /* counts and packets in update_itr are dependent on these numbers */
2346 case lowest_latency:
d5bf4f67 2347 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2348 break;
2349 case low_latency:
d5bf4f67 2350 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2351 break;
2352 case bulk_latency:
8ac34f10 2353 new_itr = IXGBE_12K_ITR;
f494e8fa 2354 break;
bd198058
AD		 2355 default:
2356 break;
f494e8fa
AV		 2357 }
2358
d5bf4f67 2359 if (new_itr != q_vector->itr) {
fe49f04a 2360 /* do an exponential smoothing */
d5bf4f67
ET		 2361 new_itr = (10 * new_itr * q_vector->itr) /
2362 ((9 * new_itr) + q_vector->itr);
509ee935 2363
bd198058 2364 /* save the algorithm value here */
5d967eb7 2365 q_vector->itr = new_itr;
fe49f04a
AD		 2366
2367 ixgbe_write_eitr(q_vector);
f494e8fa 2368 }
f494e8fa
AV		 2369}
2370
119fc60a 2371/**
de88eeeb 2372 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2373 * @adapter: pointer to adapter
119fc60a 2374 **/
f0f9778d 2375static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2376{
119fc60a
MC		 2377 struct ixgbe_hw *hw = &adapter->hw;
2378 u32 eicr = adapter->interrupt_event;
2379
f0f9778d 2380 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2381 return;
2382
f0f9778d
AD		 2383 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2384 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2385 return;
2386
2387 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2388
7ca647bd 2389 switch (hw->device_id) {
f0f9778d
AD		 2390 case IXGBE_DEV_ID_82599_T3_LOM:
2391 /*
2392 * Since the warning interrupt is for both ports
2393 * we don't have to check if:
2394 * - This interrupt wasn't for our port.
2395 * - We may have missed the interrupt so always have to
2396 * check if we got a LSC
2397 */
9a900eca 2398 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2399 !(eicr & IXGBE_EICR_LSC))
2400 return;
2401
2402 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2403 u32 speed;
f0f9778d 2404 bool link_up = false;
7ca647bd 2405
3d292265 2406 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2407
f0f9778d
AD		 2408 if (link_up)
2409 return;
2410 }
2411
2412 /* Check if this is not due to overtemp */
2413 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2414 return;
2415
2416 break;
7ca647bd 2417 default:
597f22d6
DS		 2418 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2419 return;
9a900eca 2420 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2421 return;
7ca647bd 2422 break;
119fc60a 2423 }
f44e751b 2424 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2425
2426 adapter->interrupt_event = 0;
119fc60a
MC		 2427}
2428
0befdb3e
JB		 2429static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2430{
2431 struct ixgbe_hw *hw = &adapter->hw;
2432
2433 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2434 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2435 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2436 /* write to clear the interrupt */
9a900eca 2437 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2438 }
2439}
cf8280ee 2440
4f51bf70
JK		 2441static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2442{
9a900eca
DS		 2443 struct ixgbe_hw *hw = &adapter->hw;
2444
4f51bf70
JK		 2445 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2446 return;
2447
2448 switch (adapter->hw.mac.type) {
2449 case ixgbe_mac_82599EB:
2450 /*
2451 * Need to check link state so complete overtemp check
2452 * on service task
2453 */
9a900eca
DS		 2454 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2455 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2456 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2457 adapter->interrupt_event = eicr;
2458 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2459 ixgbe_service_event_schedule(adapter);
2460 return;
2461 }
2462 return;
2463 case ixgbe_mac_X540:
2464 if (!(eicr & IXGBE_EICR_TS))
2465 return;
2466 break;
2467 default:
2468 return;
2469 }
2470
f44e751b 2471 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2472}
2473
45788d2a
DS		 2474static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2475{
2476 switch (hw->mac.type) {
2477 case ixgbe_mac_82598EB:
2478 if (hw->phy.type == ixgbe_phy_nl)
2479 return true;
2480 return false;
2481 case ixgbe_mac_82599EB:
2482 case ixgbe_mac_X550EM_x:
2483 switch (hw->mac.ops.get_media_type(hw)) {
2484 case ixgbe_media_type_fiber:
2485 case ixgbe_media_type_fiber_qsfp:
2486 return true;
2487 default:
2488 return false;
2489 }
2490 default:
2491 return false;
2492 }
2493}
2494
e8e26350
PW		 2495static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2496{
2497 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2498 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2499
4ccc650c
DS		 2500 if (!ixgbe_is_sfp(hw))
2501 return;
2502
2503 /* Later MAC's use different SDP */
2504 if (hw->mac.type >= ixgbe_mac_X540)
2505 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2506
2507 if (eicr & eicr_mask) {
73c4b7cd 2508 /* Clear the interrupt */
4ccc650c 2509 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2510 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2511 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2512 adapter->sfp_poll_time = 0;
7086400d
AD		 2513 ixgbe_service_event_schedule(adapter);
2514 }
73c4b7cd
AD		 2515 }
2516
4ccc650c
DS		 2517 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2518 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2519 /* Clear the interrupt */
9a900eca 2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2522 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2523 ixgbe_service_event_schedule(adapter);
2524 }
e8e26350
PW		 2525 }
2526}
2527
cf8280ee
JB		 2528static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2529{
2530 struct ixgbe_hw *hw = &adapter->hw;
2531
2532 adapter->lsc_int++;
2533 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2534 adapter->link_check_timeout = jiffies;
2535 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2536 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2537 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2538 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2539 }
2540}
2541
fe49f04a
AD		 2542static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2543 u64 qmask)
2544{
2545 u32 mask;
bd508178 2546 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2547
bd508178
AD		 2548 switch (hw->mac.type) {
2549 case ixgbe_mac_82598EB:
fe49f04a 2550 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2551 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2552 break;
2553 case ixgbe_mac_82599EB:
b93a2226 2554 case ixgbe_mac_X540:
9a75a1ac
DS		 2555 case ixgbe_mac_X550:
2556 case ixgbe_mac_X550EM_x:
fe49f04a 2557 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2558 if (mask)
2559 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2560 mask = (qmask >> 32);
bd508178
AD		 2561 if (mask)
2562 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2563 break;
2564 default:
2565 break;
fe49f04a
AD		 2566 }
2567 /* skip the flush */
2568}
2569
2570static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2571 u64 qmask)
fe49f04a
AD		 2572{
2573 u32 mask;
bd508178 2574 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2575
bd508178
AD		 2576 switch (hw->mac.type) {
2577 case ixgbe_mac_82598EB:
fe49f04a 2578 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2579 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2580 break;
2581 case ixgbe_mac_82599EB:
b93a2226 2582 case ixgbe_mac_X540:
9a75a1ac
DS		 2583 case ixgbe_mac_X550:
2584 case ixgbe_mac_X550EM_x:
fe49f04a 2585 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2586 if (mask)
2587 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2588 mask = (qmask >> 32);
bd508178
AD		 2589 if (mask)
2590 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2591 break;
2592 default:
2593 break;
fe49f04a
AD		 2594 }
2595 /* skip the flush */
2596}
2597
021230d4 2598/**
2c4af694
AD		 2599 * ixgbe_irq_enable - Enable default interrupt generation settings
2600 * @adapter: board private structure
021230d4 2601 **/
2c4af694
AD		 2602static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2603 bool flush)
9a799d71 2604{
9a900eca 2605 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2606 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2607
2c4af694
AD		 2608 /* don't reenable LSC while waiting for link */
2609 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2610 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2611
2c4af694 2612 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2613 switch (adapter->hw.mac.type) {
2614 case ixgbe_mac_82599EB:
9a900eca 2615 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2616 break;
2617 case ixgbe_mac_X540:
9a75a1ac
DS		 2618 case ixgbe_mac_X550:
2619 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2620 mask |= IXGBE_EIMS_TS;
2621 break;
2622 default:
2623 break;
2624 }
2c4af694 2625 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2626 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2627 switch (adapter->hw.mac.type) {
2628 case ixgbe_mac_82599EB:
9a900eca
DS		 2629 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2630 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2631 /* fall through */
858bc081 2632 case ixgbe_mac_X540:
9a75a1ac
DS		 2633 case ixgbe_mac_X550:
2634 case ixgbe_mac_X550EM_x:
cbd45ec7
MR		 2635 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2636 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2637 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2638 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2639 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2640 mask |= IXGBE_EIMS_MAILBOX;
2641 break;
2642 default:
2643 break;
9a799d71 2644 }
db0677fa 2645
2c4af694
AD		 2646 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2647 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2648 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2649
2c4af694
AD		 2650 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2651 if (queues)
2652 ixgbe_irq_enable_queues(adapter, ~0);
2653 if (flush)
2654 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2655}
2656
2c4af694 2657static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2658{
a65151ba 2659 struct ixgbe_adapter *adapter = data;
9a799d71 2660 struct ixgbe_hw *hw = &adapter->hw;
54037505 2661 u32 eicr;
91281fd3 2662
54037505
DS		 2663 /*
2664 * Workaround for Silicon errata. Use clear-by-write instead
2665 * of clear-by-read. Reading with EICS will return the
2666 * interrupt causes without clearing, which later be done
2667 * with the write to EICR.
2668 */
2669 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2670
2671 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2672 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2673 * the bits are high when ixgbe_msix_other is called. There is a race
2674 * condition otherwise which results in possible performance loss
2675 * especially if the ixgbe_msix_other interrupt is triggering
2676 * consistently (as it would when PPS is turned on for the X540 device)
2677 */
2678 eicr &= 0xFFFF0000;
2679
54037505 2680 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2681
cf8280ee
JB		 2682 if (eicr & IXGBE_EICR_LSC)
2683 ixgbe_check_lsc(adapter);
f0848276 2684
1cdd1ec8
GR		 2685 if (eicr & IXGBE_EICR_MAILBOX)
2686 ixgbe_msg_task(adapter);
efe3d3c8 2687
bd508178
AD		 2688 switch (hw->mac.type) {
2689 case ixgbe_mac_82599EB:
b93a2226 2690 case ixgbe_mac_X540:
9a75a1ac
DS		 2691 case ixgbe_mac_X550:
2692 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2693 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2694 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2695 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2696 ixgbe_service_event_schedule(adapter);
2697 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2698 IXGBE_EICR_GPI_SDP0_X540);
2699 }
d773ce2d
DS		 2700 if (eicr & IXGBE_EICR_ECC) {
2701 e_info(link, "Received ECC Err, initiating reset\n");
2702 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2703 ixgbe_service_event_schedule(adapter);
2704 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2705 }
c4cf55e5
PWJ		 2706 /* Handle Flow Director Full threshold interrupt */
2707 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2708 int reinit_count = 0;
c4cf55e5 2709 int i;
c4cf55e5 2710 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2711 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2712 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2713 &ring->state))
2714 reinit_count++;
2715 }
2716 if (reinit_count) {
2717 /* no more flow director interrupts until after init */
2718 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2719 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2720 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2721 }
2722 }
f0f9778d 2723 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2724 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2725 break;
2726 default:
2727 break;
c4cf55e5 2728 }
f0848276 2729
bd508178 2730 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2731
db0677fa
JK		 2732 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2733 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2734
7086400d 2735 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2736 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2737 ixgbe_irq_enable(adapter, false, false);
f0848276 2738
9a799d71 2739 return IRQ_HANDLED;
f0848276 2740}
91281fd3 2741
4ff7fb12 2742static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2743{
021230d4 2744 struct ixgbe_q_vector *q_vector = data;
91281fd3 2745
9b471446 2746 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2747
4ff7fb12
AD		 2748 if (q_vector->rx.ring || q_vector->tx.ring)
2749 napi_schedule(&q_vector->napi);
91281fd3 2750
9a799d71 2751 return IRQ_HANDLED;
91281fd3
AD		 2752}
2753
eb01b975
AD		 2754/**
2755 * ixgbe_poll - NAPI Rx polling callback
2756 * @napi: structure for representing this polling device
2757 * @budget: how many packets driver is allowed to clean
2758 *
2759 * This function is used for legacy and MSI, NAPI mode
2760 **/
8af3c33f 2761int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2762{
2763 struct ixgbe_q_vector *q_vector =
2764 container_of(napi, struct ixgbe_q_vector, napi);
2765 struct ixgbe_adapter *adapter = q_vector->adapter;
2766 struct ixgbe_ring *ring;
2767 int per_ring_budget;
2768 bool clean_complete = true;
2769
2770#ifdef CONFIG_IXGBE_DCA
2771 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2772 ixgbe_update_dca(q_vector);
2773#endif
2774
2775 ixgbe_for_each_ring(ring, q_vector->tx)
2776 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2777
5a85e737
ET		 2778 if (!ixgbe_qv_lock_napi(q_vector))
2779 return budget;
2780
eb01b975
AD		 2781 /* attempt to distribute budget to each queue fairly, but don't allow
2782 * the budget to go below 1 because we'll exit polling */
2783 if (q_vector->rx.count > 1)
2784 per_ring_budget = max(budget/q_vector->rx.count, 1);
2785 else
2786 per_ring_budget = budget;
2787
2788 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2789 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2790 per_ring_budget) < per_ring_budget);
eb01b975 2791
5a85e737 2792 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2793 /* If all work not completed, return budget and keep polling */
2794 if (!clean_complete)
2795 return budget;
2796
2797 /* all work done, exit the polling mode */
2798 napi_complete(napi);
2799 if (adapter->rx_itr_setting & 1)
2800 ixgbe_set_itr(q_vector);
2801 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2802 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2803
2804 return 0;
2805}
2806
021230d4
AV		 2807/**
2808 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2809 * @adapter: board private structure
2810 *
2811 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2812 * interrupts from the kernel.
2813 **/
2814static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2815{
2816 struct net_device *netdev = adapter->netdev;
207867f5 2817 int vector, err;
e8e9f696 2818 int ri = 0, ti = 0;
021230d4 2819
49c7ffbe 2820 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2821 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2822 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2823
4ff7fb12 2824 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2825 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2826 "%s-%s-%d", netdev->name, "TxRx", ri++);
2827 ti++;
2828 } else if (q_vector->rx.ring) {
9fe93afd 2829 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2830 "%s-%s-%d", netdev->name, "rx", ri++);
2831 } else if (q_vector->tx.ring) {
9fe93afd 2832 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2833 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2834 } else {
2835 /* skip this unused q_vector */
2836 continue;
32aa77a4 2837 }
207867f5
AD		 2838 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2839 q_vector->name, q_vector);
9a799d71 2840 if (err) {
396e799c 2841 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2842 "Error: %d\n", err);
021230d4 2843 goto free_queue_irqs;
9a799d71 2844 }
207867f5
AD		 2845 /* If Flow Director is enabled, set interrupt affinity */
2846 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2847 /* assign the mask for this irq */
2848 irq_set_affinity_hint(entry->vector,
de88eeeb 2849 &q_vector->affinity_mask);
207867f5 2850 }
9a799d71
AK		 2851 }
2852
021230d4 2853 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2854 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2855 if (err) {
de88eeeb 2856 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2857 goto free_queue_irqs;
9a799d71
AK		 2858 }
2859
9a799d71
AK		 2860 return 0;
2861
021230d4 2862free_queue_irqs:
207867f5
AD		 2863 while (vector) {
2864 vector--;
2865 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2866 NULL);
2867 free_irq(adapter->msix_entries[vector].vector,
2868 adapter->q_vector[vector]);
2869 }
021230d4
AV		 2870 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2871 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2872 kfree(adapter->msix_entries);
2873 adapter->msix_entries = NULL;
9a799d71
AK		 2874 return err;
2875}
2876
2877/**
021230d4 2878 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2879 * @irq: interrupt number
2880 * @data: pointer to a network interface device structure
9a799d71
AK		 2881 **/
2882static irqreturn_t ixgbe_intr(int irq, void *data)
2883{
a65151ba 2884 struct ixgbe_adapter *adapter = data;
9a799d71 2885 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2886 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2887 u32 eicr;
2888
54037505 2889 /*
24ddd967 2890 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2891 * before the read of EICR.
2892 */
2893 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2894
021230d4 2895 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2896 * therefore no explicit interrupt disable is necessary */
021230d4 2897 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2898 if (!eicr) {
6af3b9eb
ET		 2899 /*
2900 * shared interrupt alert!
f47cf66e 2901 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2902 * have disabled interrupts due to EIAM
2903 * finish the workaround of silicon errata on 82598. Unmask
2904 * the interrupt that we masked before the EICR read.
2905 */
2906 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2907 ixgbe_irq_enable(adapter, true, true);
9a799d71 2908 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2909 }
9a799d71 2910
cf8280ee
JB		 2911 if (eicr & IXGBE_EICR_LSC)
2912 ixgbe_check_lsc(adapter);
021230d4 2913
bd508178
AD		 2914 switch (hw->mac.type) {
2915 case ixgbe_mac_82599EB:
e8e26350 2916 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2917 /* Fall through */
2918 case ixgbe_mac_X540:
9a75a1ac
DS		 2919 case ixgbe_mac_X550:
2920 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2921 if (eicr & IXGBE_EICR_ECC) {
2922 e_info(link, "Received ECC Err, initiating reset\n");
2923 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2924 ixgbe_service_event_schedule(adapter);
2925 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2926 }
4f51bf70 2927 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2928 break;
2929 default:
2930 break;
2931 }
e8e26350 2932
0befdb3e 2933 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2934 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2935 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2936
b9f6ed2b
AD		 2937 /* would disable interrupts here but EIAM disabled it */
2938 napi_schedule(&q_vector->napi);
9a799d71 2939
6af3b9eb
ET		 2940 /*
2941 * re-enable link(maybe) and non-queue interrupts, no flush.
2942 * ixgbe_poll will re-enable the queue interrupts
2943 */
6af3b9eb
ET		 2944 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2945 ixgbe_irq_enable(adapter, false, false);
2946
9a799d71
AK		 2947 return IRQ_HANDLED;
2948}
2949
2950/**
2951 * ixgbe_request_irq - initialize interrupts
2952 * @adapter: board private structure
2953 *
2954 * Attempts to configure interrupts using the best available
2955 * capabilities of the hardware and kernel.
2956 **/
021230d4 2957static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2958{
2959 struct net_device *netdev = adapter->netdev;
021230d4 2960 int err;
9a799d71 2961
4cc6df29 2962 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2963 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2964 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2965 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2966 netdev->name, adapter);
4cc6df29 2967 else
a0607fd3 2968 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2969 netdev->name, adapter);
9a799d71 2970
de88eeeb 2971 if (err)
396e799c 2972 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2973
9a799d71
AK		 2974 return err;
2975}
2976
2977static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2978{
49c7ffbe 2979 int vector;
9a799d71 2980
49c7ffbe
AD		 2981 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2982 free_irq(adapter->pdev->irq, adapter);
2983 return;
2984 }
4cc6df29 2985
49c7ffbe
AD		 2986 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2987 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2988 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2989
49c7ffbe
AD		 2990 /* free only the irqs that were actually requested */
2991 if (!q_vector->rx.ring && !q_vector->tx.ring)
2992 continue;
207867f5 2993
49c7ffbe
AD		 2994 /* clear the affinity_mask in the IRQ descriptor */
2995 irq_set_affinity_hint(entry->vector, NULL);
2996
2997 free_irq(entry->vector, q_vector);
9a799d71 2998 }
49c7ffbe
AD		 2999
3000 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3001}
3002
22d5a71b
JB		 3003/**
3004 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3005 * @adapter: board private structure
3006 **/
3007static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3008{
bd508178
AD		 3009 switch (adapter->hw.mac.type) {
3010 case ixgbe_mac_82598EB:
835462fc 3011 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3012 break;
3013 case ixgbe_mac_82599EB:
b93a2226 3014 case ixgbe_mac_X540:
9a75a1ac
DS		 3015 case ixgbe_mac_X550:
3016 case ixgbe_mac_X550EM_x:
835462fc
NS		 3017 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3018 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3020 break;
3021 default:
3022 break;
22d5a71b
JB		 3023 }
3024 IXGBE_WRITE_FLUSH(&adapter->hw);
3025 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3026 int vector;
3027
3028 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3029 synchronize_irq(adapter->msix_entries[vector].vector);
3030
3031 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3032 } else {
3033 synchronize_irq(adapter->pdev->irq);
3034 }
3035}
3036
9a799d71
AK		 3037/**
3038 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3039 *
3040 **/
3041static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3042{
d5bf4f67 3043 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3044
d5bf4f67 3045 ixgbe_write_eitr(q_vector);
9a799d71 3046
e8e26350
PW		 3047 ixgbe_set_ivar(adapter, 0, 0, 0);
3048 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3049
396e799c 3050 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3051}
3052
43e69bf0
AD		 3053/**
3054 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3055 * @adapter: board private structure
3056 * @ring: structure containing ring specific data
3057 *
3058 * Configure the Tx descriptor ring after a reset.
3059 **/
84418e3b
AD		 3060void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3061 struct ixgbe_ring *ring)
43e69bf0
AD		 3062{
3063 struct ixgbe_hw *hw = &adapter->hw;
3064 u64 tdba = ring->dma;
2f1860b8 3065 int wait_loop = 10;
b88c6de2 3066 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3067 u8 reg_idx = ring->reg_idx;
43e69bf0 3068
2f1860b8 3069 /* disable queue to avoid issues while updating state */
b88c6de2 3070 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3071 IXGBE_WRITE_FLUSH(hw);
3072
43e69bf0 3073 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3074 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3075 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3076 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3077 ring->count * sizeof(union ixgbe_adv_tx_desc));
3078 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3079 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3080 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3081
b88c6de2
AD		 3082 /*
3083 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3084 * higher than 1 when:
3085 * - ITR is 0 as it could cause false TX hangs
3086 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3087 *
3088 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3089 * to or less than the number of on chip descriptors, which is
3090 * currently 40.
3091 */
67da097e 3092 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3093 txdctl |= (1 << 16); /* WTHRESH = 1 */
3094 else
3095 txdctl |= (8 << 16); /* WTHRESH = 8 */
3096
e954b374
AD		 3097 /*
3098 * Setting PTHRESH to 32 both improves performance
3099 * and avoids a TX hang with DFP enabled
3100 */
b88c6de2
AD		 3101 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3102 32; /* PTHRESH = 32 */
2f1860b8
AD		 3103
3104 /* reinitialize flowdirector state */
39cb681b 3105 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3106 ring->atr_sample_rate = adapter->atr_sample_rate;
3107 ring->atr_count = 0;
3108 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3109 } else {
3110 ring->atr_sample_rate = 0;
3111 }
2f1860b8 3112
fd786b7b
AD		 3113 /* initialize XPS */
3114 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3115 struct ixgbe_q_vector *q_vector = ring->q_vector;
3116
3117 if (q_vector)
2a47fa45 3118 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3119 &q_vector->affinity_mask,
3120 ring->queue_index);
3121 }
3122
c84d324c
JF		 3123 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3124
2f1860b8 3125 /* enable queue */
2f1860b8
AD		 3126 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3127
3128 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3129 if (hw->mac.type == ixgbe_mac_82598EB &&
3130 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3131 return;
3132
3133 /* poll to verify queue is enabled */
3134 do {
032b4325 3135 usleep_range(1000, 2000);
2f1860b8
AD		 3136 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3137 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3138 if (!wait_loop)
3139 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3140}
3141
120ff942
AD		 3142static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3143{
3144 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3145 u32 rttdcs, mtqc;
8b1c0b24 3146 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3147
3148 if (hw->mac.type == ixgbe_mac_82598EB)
3149 return;
3150
3151 /* disable the arbiter while setting MTQC */
3152 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3153 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3154 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3155
3156 /* set transmit pool layout */
671c0adb
AD		 3157 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3158 mtqc = IXGBE_MTQC_VT_ENA;
3159 if (tcs > 4)
3160 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3161 else if (tcs > 1)
3162 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3163 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3164 mtqc |= IXGBE_MTQC_32VF;
3165 else
3166 mtqc |= IXGBE_MTQC_64VF;
3167 } else {
3168 if (tcs > 4)
3169 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3170 else if (tcs > 1)
3171 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3172 else
671c0adb
AD		 3173 mtqc = IXGBE_MTQC_64Q_1PB;
3174 }
120ff942 3175
671c0adb 3176 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3177
671c0adb
AD		 3178 /* Enable Security TX Buffer IFG for multiple pb */
3179 if (tcs) {
3180 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3181 sectx |= IXGBE_SECTX_DCB;
3182 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3183 }
3184
3185 /* re-enable the arbiter */
3186 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3187 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3188}
3189
9a799d71 3190/**
3a581073 3191 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3192 * @adapter: board private structure
3193 *
3194 * Configure the Tx unit of the MAC after a reset.
3195 **/
3196static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3197{
2f1860b8
AD		 3198 struct ixgbe_hw *hw = &adapter->hw;
3199 u32 dmatxctl;
43e69bf0 3200 u32 i;
9a799d71 3201
2f1860b8
AD		 3202 ixgbe_setup_mtqc(adapter);
3203
3204 if (hw->mac.type != ixgbe_mac_82598EB) {
3205 /* DMATXCTL.EN must be before Tx queues are enabled */
3206 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3207 dmatxctl |= IXGBE_DMATXCTL_TE;
3208 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3209 }
3210
9a799d71 3211 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3212 for (i = 0; i < adapter->num_tx_queues; i++)
3213 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3214}
3215
3ebe8fde
AD		 3216static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3217 struct ixgbe_ring *ring)
3218{
3219 struct ixgbe_hw *hw = &adapter->hw;
3220 u8 reg_idx = ring->reg_idx;
3221 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3222
3223 srrctl |= IXGBE_SRRCTL_DROP_EN;
3224
3225 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3226}
3227
3228static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3229 struct ixgbe_ring *ring)
3230{
3231 struct ixgbe_hw *hw = &adapter->hw;
3232 u8 reg_idx = ring->reg_idx;
3233 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3234
3235 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3236
3237 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3238}
3239
3240#ifdef CONFIG_IXGBE_DCB
3241void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3242#else
3243static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3244#endif
3245{
3246 int i;
3247 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3248
3249 if (adapter->ixgbe_ieee_pfc)
3250 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3251
3252 /*
3253 * We should set the drop enable bit if:
3254 * SR-IOV is enabled
3255 * or
3256 * Number of Rx queues > 1 and flow control is disabled
3257 *
3258 * This allows us to avoid head of line blocking for security
3259 * and performance reasons.
3260 */
3261 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3262 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3263 for (i = 0; i < adapter->num_rx_queues; i++)
3264 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3265 } else {
3266 for (i = 0; i < adapter->num_rx_queues; i++)
3267 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3268 }
3269}
3270
e8e26350 3271#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3272
a6616b42 3273static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3274 struct ixgbe_ring *rx_ring)
cc41ac7c 3275{
45e9baa5 3276 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3277 u32 srrctl;
bf29ee6c 3278 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3279
45e9baa5
AD		 3280 if (hw->mac.type == ixgbe_mac_82598EB) {
3281 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3282
45e9baa5
AD		 3283 /*
3284 * if VMDq is not active we must program one srrctl register
3285 * per RSS queue since we have enabled RDRXCTL.MVMEN
3286 */
3287 reg_idx &= mask;
3288 }
cc41ac7c 3289
45e9baa5
AD		 3290 /* configure header buffer length, needed for RSC */
3291 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3292
45e9baa5 3293 /* configure the packet buffer length */
f800326d 3294 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3295
3296 /* configure descriptor type */
f800326d 3297 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3298
45e9baa5 3299 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3300}
9a799d71 3301
dfaf891d
VZ		 3302/**
3303 * Return a number of entries in the RSS indirection table
3304 *
3305 * @adapter: device handle
3306 *
3307 * - 82598/82599/X540: 128
3308 * - X550(non-SRIOV mode): 512
3309 * - X550(SRIOV mode): 64
3310 */
7f276efb 3311u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3312{
3313 if (adapter->hw.mac.type < ixgbe_mac_X550)
3314 return 128;
3315 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3316 return 64;
3317 else
3318 return 512;
3319}
3320
3321/**
3322 * Write the RETA table to HW
3323 *
3324 * @adapter: device handle
3325 *
3326 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3327 */
1c7cf078 3328void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3329{
dfaf891d 3330 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3331 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3332 u32 reta = 0;
dfaf891d
VZ		 3333 u32 indices_multi;
3334 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3335
0f9b232b 3336 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3337 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3338 * indices.
3339 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3340 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3341 */
3342 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3343 indices_multi = 0x11;
3344 else
3345 indices_multi = 0x1;
3346
dfaf891d
VZ		 3347 /* Write redirection table to HW */
3348 for (i = 0; i < reta_entries; i++) {
3349 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3350 if ((i & 3) == 3) {
3351 if (i < 128)
3352 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3353 else
3354 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3355 reta);
dfaf891d 3356 reta = 0;
0f9b232b
DS		 3357 }
3358 }
3359}
3360
dfaf891d
VZ		 3361/**
3362 * Write the RETA table to HW (for x550 devices in SRIOV mode)
3363 *
3364 * @adapter: device handle
3365 *
3366 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3367 */
3368static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3369{
dfaf891d 3370 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3371 struct ixgbe_hw *hw = &adapter->hw;
3372 u32 vfreta = 0;
dfaf891d
VZ		 3373 unsigned int pf_pool = adapter->num_vfs;
3374
3375 /* Write redirection table to HW */
3376 for (i = 0; i < reta_entries; i++) {
3377 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3378 if ((i & 3) == 3) {
3379 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3380 vfreta);
3381 vfreta = 0;
3382 }
3383 }
3384}
3385
3386static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3387{
3388 struct ixgbe_hw *hw = &adapter->hw;
3389 u32 i, j;
3390 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3391 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3392
3393 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3394 * make full use of any rings they may have. We will use the
3395 * PSRTYPE register to control how many rings we use within the PF.
3396 */
3397 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3398 rss_i = 2;
3399
3400 /* Fill out hash function seeds */
3401 for (i = 0; i < 10; i++)
3402 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3403
3404 /* Fill out redirection table */
3405 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3406
3407 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3408 if (j == rss_i)
3409 j = 0;
3410
3411 adapter->rss_indir_tbl[i] = j;
3412 }
3413
3414 ixgbe_store_reta(adapter);
3415}
3416
3417static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3418{
3419 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3420 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3421 unsigned int pf_pool = adapter->num_vfs;
3422 int i, j;
3423
3424 /* Fill out hash function seeds */
3425 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3426 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3427 adapter->rss_key[i]);
0f9b232b
DS		 3428
3429 /* Fill out the redirection table */
3430 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3431 if (j == rss_i)
05abb126 3432 j = 0;
dfaf891d
VZ		 3433
3434 adapter->rss_indir_tbl[i] = j;
05abb126 3435 }
dfaf891d
VZ		 3436
3437 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3438}
3439
3440static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3441{
3442 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3443 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3444 u32 rxcsum;
0cefafad 3445
05abb126
AD		 3446 /* Disable indicating checksum in descriptor, enables RSS hash */
3447 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3448 rxcsum |= IXGBE_RXCSUM_PCSD;
3449 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3450
671c0adb 3451 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3452 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3453 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3454 } else {
671c0adb
AD		 3455 u8 tcs = netdev_get_num_tc(adapter->netdev);
3456
3457 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3458 if (tcs > 4)
3459 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3460 else if (tcs > 1)
3461 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3462 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3463 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3464 else
671c0adb
AD		 3465 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3466 } else {
3467 if (tcs > 4)
8b1c0b24 3468 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3469 else if (tcs > 1)
3470 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3471 else
3472 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3473 }
0cefafad
JB		 3474 }
3475
05abb126 3476 /* Perform hash on these packet types */
d1b849b9
DS		 3477 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3478 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3479 IXGBE_MRQC_RSS_FIELD_IPV6 |
3480 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3481
ef6afc0c 3482 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3483 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3484 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3485 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3486
dfaf891d 3487 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3488 if ((hw->mac.type >= ixgbe_mac_X550) &&
3489 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3490 unsigned int pf_pool = adapter->num_vfs;
3491
3492 /* Enable VF RSS mode */
3493 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3494 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3495
3496 /* Setup RSS through the VF registers */
dfaf891d 3497 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3498 vfmrqc = IXGBE_MRQC_RSSEN;
3499 vfmrqc |= rss_field;
3500 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3501 } else {
dfaf891d 3502 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3503 mrqc |= rss_field;
3504 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3505 }
0cefafad
JB		 3506}
3507
bb5a9ad2
NS		 3508/**
3509 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3510 * @adapter: address of board private structure
3511 * @index: index of ring to set
bb5a9ad2 3512 **/
082757af 3513static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3514 struct ixgbe_ring *ring)
bb5a9ad2 3515{
bb5a9ad2 3516 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3517 u32 rscctrl;
bf29ee6c 3518 u8 reg_idx = ring->reg_idx;
7367096a 3519
7d637bcc 3520 if (!ring_is_rsc_enabled(ring))
7367096a 3521 return;
bb5a9ad2 3522
7367096a 3523 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3524 rscctrl |= IXGBE_RSCCTL_RSCEN;
3525 /*
3526 * we must limit the number of descriptors so that the
3527 * total size of max desc * buf_len is not greater
642c680e 3528 * than 65536
bb5a9ad2 3529 */
f800326d 3530 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3531 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3532}
3533
9e10e045
AD		 3534#define IXGBE_MAX_RX_DESC_POLL 10
3535static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3536 struct ixgbe_ring *ring)
3537{
3538 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3539 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3540 u32 rxdctl;
bf29ee6c 3541 u8 reg_idx = ring->reg_idx;
9e10e045 3542
b0483c8f
MR		 3543 if (ixgbe_removed(hw->hw_addr))
3544 return;
9e10e045
AD		 3545 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3546 if (hw->mac.type == ixgbe_mac_82598EB &&
3547 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3548 return;
3549
3550 do {
032b4325 3551 usleep_range(1000, 2000);
9e10e045
AD		 3552 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3553 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3554
3555 if (!wait_loop) {
3556 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3557 "the polling period\n", reg_idx);
3558 }
3559}
3560
2d39d576
YZ		 3561void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3562 struct ixgbe_ring *ring)
3563{
3564 struct ixgbe_hw *hw = &adapter->hw;
3565 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3566 u32 rxdctl;
3567 u8 reg_idx = ring->reg_idx;
3568
b0483c8f
MR		 3569 if (ixgbe_removed(hw->hw_addr))
3570 return;
2d39d576
YZ		 3571 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3572 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3573
3574 /* write value back with RXDCTL.ENABLE bit cleared */
3575 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3576
3577 if (hw->mac.type == ixgbe_mac_82598EB &&
3578 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3579 return;
3580
3581 /* the hardware may take up to 100us to really disable the rx queue */
3582 do {
3583 udelay(10);
3584 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3585 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3586
3587 if (!wait_loop) {
3588 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3589 "the polling period\n", reg_idx);
3590 }
3591}
3592
84418e3b
AD		 3593void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3594 struct ixgbe_ring *ring)
acd37177
AD		 3595{
3596 struct ixgbe_hw *hw = &adapter->hw;
3597 u64 rdba = ring->dma;
9e10e045 3598 u32 rxdctl;
bf29ee6c 3599 u8 reg_idx = ring->reg_idx;
acd37177 3600
9e10e045
AD		 3601 /* disable queue to avoid issues while updating state */
3602 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3603 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3604
acd37177
AD		 3605 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3606 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3607 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3608 ring->count * sizeof(union ixgbe_adv_rx_desc));
3609 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3610 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3611 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3612
3613 ixgbe_configure_srrctl(adapter, ring);
3614 ixgbe_configure_rscctl(adapter, ring);
3615
3616 if (hw->mac.type == ixgbe_mac_82598EB) {
3617 /*
3618 * enable cache line friendly hardware writes:
3619 * PTHRESH=32 descriptors (half the internal cache),
3620 * this also removes ugly rx_no_buffer_count increment
3621 * HTHRESH=4 descriptors (to minimize latency on fetch)
3622 * WTHRESH=8 burst writeback up to two cache lines
3623 */
3624 rxdctl &= ~0x3FFFFF;
3625 rxdctl |= 0x080420;
3626 }
3627
3628 /* enable receive descriptor ring */
3629 rxdctl |= IXGBE_RXDCTL_ENABLE;
3630 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3631
3632 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3633 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3634}
3635
48654521
AD		 3636static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3637{
3638 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3639 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3640 u16 pool;
48654521
AD		 3641
3642 /* PSRTYPE must be initialized in non 82598 adapters */
3643 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3644 IXGBE_PSRTYPE_UDPHDR |
3645 IXGBE_PSRTYPE_IPV4HDR |
48654521 3646 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3647 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3648
3649 if (hw->mac.type == ixgbe_mac_82598EB)
3650 return;
3651
fbe7ca7f
AD		 3652 if (rss_i > 3)
3653 psrtype |= 2 << 29;
3654 else if (rss_i > 1)
3655 psrtype |= 1 << 29;
48654521 3656
2a47fa45
JF		 3657 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3658 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3659}
3660
f5b4a52e
AD		 3661static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3662{
3663 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3664 u32 reg_offset, vf_shift;
435b19f6 3665 u32 gcr_ext, vmdctl;
de4c7f65 3666 int i;
f5b4a52e
AD		 3667
3668 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3669 return;
3670
3671 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3672 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3673 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3674 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3675 vmdctl |= IXGBE_VT_CTL_REPLEN;
3676 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3677
1d9c0bfd
AD		 3678 vf_shift = VMDQ_P(0) % 32;
3679 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3680
3681 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3682 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3683 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3684 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3685 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3686 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3687 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3688
3689 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3690 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3691
3692 /*
3693 * Set up VF register offsets for selected VT Mode,
3694 * i.e. 32 or 64 VFs for SR-IOV
3695 */
73079ea0
AD		 3696 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3697 case IXGBE_82599_VMDQ_8Q_MASK:
3698 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3699 break;
3700 case IXGBE_82599_VMDQ_4Q_MASK:
3701 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3702 break;
3703 default:
3704 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3705 break;
3706 }
3707
f5b4a52e
AD		 3708 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3709
435b19f6 3710
a985b6c3 3711 /* Enable MAC Anti-Spoofing */
435b19f6 3712 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3713 adapter->num_vfs);
5b7f000f
DS		 3714
3715 /* Ensure LLDP is set for Ethertype Antispoofing if we will be
3716 * calling set_ethertype_anti_spoofing for each VF in loop below
3717 */
3718 if (hw->mac.ops.set_ethertype_anti_spoofing)
3719 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3720 (IXGBE_ETQF_FILTER_EN | /* enable filter */
3721 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */
3722 IXGBE_ETH_P_LLDP)); /* LLDP eth type */
3723
de4c7f65
GR		 3724 /* For VFs that have spoof checking turned off */
3725 for (i = 0; i < adapter->num_vfs; i++) {
3726 if (!adapter->vfinfo[i].spoofchk_enabled)
3727 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3728
3729 /* enable ethertype anti spoofing if hw supports it */
3730 if (hw->mac.ops.set_ethertype_anti_spoofing)
3731 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3732
3733 /* Enable/Disable RSS query feature */
3734 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3735 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3736 }
f5b4a52e
AD		 3737}
3738
477de6ed 3739static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3740{
9a799d71
AK		 3741 struct ixgbe_hw *hw = &adapter->hw;
3742 struct net_device *netdev = adapter->netdev;
3743 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3744 struct ixgbe_ring *rx_ring;
3745 int i;
3746 u32 mhadd, hlreg0;
48654521 3747
63f39bd1 3748#ifdef IXGBE_FCOE
477de6ed
AD		 3749 /* adjust max frame to be able to do baby jumbo for FCoE */
3750 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3751 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3752 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3753
477de6ed 3754#endif /* IXGBE_FCOE */
872844dd
AD		 3755
3756 /* adjust max frame to be at least the size of a standard frame */
3757 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3758 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3759
477de6ed
AD		 3760 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3761 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3762 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3763 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3764
3765 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3766 }
3767
3768 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3769 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3770 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3771 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3772
0cefafad
JB		 3773 /*
3774 * Setup the HW Rx Head and Tail Descriptor Pointers and
3775 * the Base and Length of the Rx Descriptor Ring
3776 */
9a799d71 3777 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3778 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3779 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3780 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3781 else
7d637bcc 3782 clear_ring_rsc_enabled(rx_ring);
477de6ed 3783 }
477de6ed
AD		 3784}
3785
7367096a
AD		 3786static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3787{
3788 struct ixgbe_hw *hw = &adapter->hw;
3789 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3790
3791 switch (hw->mac.type) {
3792 case ixgbe_mac_82598EB:
3793 /*
3794 * For VMDq support of different descriptor types or
3795 * buffer sizes through the use of multiple SRRCTL
3796 * registers, RDRXCTL.MVMEN must be set to 1
3797 *
3798 * also, the manual doesn't mention it clearly but DCA hints
3799 * will only use queue 0's tags unless this bit is set. Side
3800 * effects of setting this bit are only that SRRCTL must be
3801 * fully programmed [0..15]
3802 */
3803 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3804 break;
052a1a72
MR		 3805 case ixgbe_mac_X550:
3806 case ixgbe_mac_X550EM_x:
7367096a 3807 case ixgbe_mac_82599EB:
b93a2226 3808 case ixgbe_mac_X540:
7367096a
AD		 3809 /* Disable RSC for ACK packets */
3810 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3811 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3812 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3813 /* hardware requires some bits to be set by default */
3814 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3815 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3816 break;
3817 default:
3818 /* We should do nothing since we don't know this hardware */
3819 return;
3820 }
3821
3822 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3823}
3824
477de6ed
AD		 3825/**
3826 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3827 * @adapter: board private structure
3828 *
3829 * Configure the Rx unit of the MAC after a reset.
3830 **/
3831static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3832{
3833 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3834 int i;
6dcc28b9 3835 u32 rxctrl, rfctl;
477de6ed
AD		 3836
3837 /* disable receives while setting up the descriptors */
1f9ac57c 3838 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3839
3840 ixgbe_setup_psrtype(adapter);
7367096a 3841 ixgbe_setup_rdrxctl(adapter);
477de6ed 3842
6dcc28b9
JK		 3843 /* RSC Setup */
3844 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3845 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3846 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3847 rfctl |= IXGBE_RFCTL_RSC_DIS;
3848 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3849
9e10e045 3850 /* Program registers for the distribution of queues */
f5b4a52e 3851 ixgbe_setup_mrqc(adapter);
f5b4a52e 3852
477de6ed
AD		 3853 /* set_rx_buffer_len must be called before ring initialization */
3854 ixgbe_set_rx_buffer_len(adapter);
3855
3856 /*
3857 * Setup the HW Rx Head and Tail Descriptor Pointers and
3858 * the Base and Length of the Rx Descriptor Ring
3859 */
9e10e045
AD		 3860 for (i = 0; i < adapter->num_rx_queues; i++)
3861 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3862
1f9ac57c 3863 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3864 /* disable drop enable for 82598 parts */
3865 if (hw->mac.type == ixgbe_mac_82598EB)
3866 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3867
3868 /* enable all receives */
3869 rxctrl |= IXGBE_RXCTRL_RXEN;
3870 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3871}
3872
80d5c368
PM		 3873static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3874 __be16 proto, u16 vid)
068c89b0
DS		 3875{
3876 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3877 struct ixgbe_hw *hw = &adapter->hw;
3878
3879 /* add VID to filter table */
1d9c0bfd 3880 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3881 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3882
3883 return 0;
068c89b0
DS		 3884}
3885
80d5c368
PM		 3886static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3887 __be16 proto, u16 vid)
068c89b0
DS		 3888{
3889 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3890 struct ixgbe_hw *hw = &adapter->hw;
3891
068c89b0 3892 /* remove VID from filter table */
1d9c0bfd 3893 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3894 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3895
3896 return 0;
068c89b0
DS		 3897}
3898
f62bbb5e
JG		 3899/**
3900 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3901 * @adapter: driver data
3902 */
3903static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3904{
3905 struct ixgbe_hw *hw = &adapter->hw;
3906 u32 vlnctrl;
5f6c0181
JB		 3907 int i, j;
3908
3909 switch (hw->mac.type) {
3910 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3911 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3912 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3913 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3914 break;
3915 case ixgbe_mac_82599EB:
b93a2226 3916 case ixgbe_mac_X540:
9a75a1ac
DS		 3917 case ixgbe_mac_X550:
3918 case ixgbe_mac_X550EM_x:
5f6c0181 3919 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3920 struct ixgbe_ring *ring = adapter->rx_ring[i];
3921
3922 if (ring->l2_accel_priv)
3923 continue;
3924 j = ring->reg_idx;
5f6c0181
JB		 3925 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3926 vlnctrl &= ~IXGBE_RXDCTL_VME;
3927 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3928 }
3929 break;
3930 default:
3931 break;
3932 }
3933}
3934
3935/**
f62bbb5e 3936 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3937 * @adapter: driver data
3938 */
f62bbb5e 3939static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3940{
3941 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3942 u32 vlnctrl;
5f6c0181
JB		 3943 int i, j;
3944
3945 switch (hw->mac.type) {
3946 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3947 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3948 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3949 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3950 break;
3951 case ixgbe_mac_82599EB:
b93a2226 3952 case ixgbe_mac_X540:
9a75a1ac
DS		 3953 case ixgbe_mac_X550:
3954 case ixgbe_mac_X550EM_x:
5f6c0181 3955 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3956 struct ixgbe_ring *ring = adapter->rx_ring[i];
3957
3958 if (ring->l2_accel_priv)
3959 continue;
3960 j = ring->reg_idx;
5f6c0181
JB		 3961 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3962 vlnctrl |= IXGBE_RXDCTL_VME;
3963 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3964 }
3965 break;
3966 default:
3967 break;
3968 }
3969}
3970
9a799d71
AK		 3971static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3972{
f62bbb5e 3973 u16 vid;
9a799d71 3974
80d5c368 3975 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3976
3977 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3978 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3979}
3980
b335e75b
JK		 3981/**
3982 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3983 * @netdev: network interface device structure
3984 *
3985 * Writes multicast address list to the MTA hash table.
3986 * Returns: -ENOMEM on failure
3987 * 0 on no addresses written
3988 * X on writing X addresses to MTA
3989 **/
3990static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3991{
3992 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3993 struct ixgbe_hw *hw = &adapter->hw;
3994
3995 if (!netif_running(netdev))
3996 return 0;
3997
3998 if (hw->mac.ops.update_mc_addr_list)
3999 hw->mac.ops.update_mc_addr_list(hw, netdev);
4000 else
4001 return -ENOMEM;
4002
4003#ifdef CONFIG_PCI_IOV
5d7daa35 4004 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4005#endif
4006
4007 return netdev_mc_count(netdev);
4008}
4009
5d7daa35
JK		 4010#ifdef CONFIG_PCI_IOV
4011void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4012{
4013 struct ixgbe_hw *hw = &adapter->hw;
4014 int i;
4015 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4016 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4017 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
4018 adapter->mac_table[i].queue,
4019 IXGBE_RAH_AV);
4020 else
4021 hw->mac.ops.clear_rar(hw, i);
4022
4023 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
4024 }
4025}
4026#endif
4027
4028static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4029{
4030 struct ixgbe_hw *hw = &adapter->hw;
4031 int i;
4032 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4033 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
4034 if (adapter->mac_table[i].state &
4035 IXGBE_MAC_STATE_IN_USE)
4036 hw->mac.ops.set_rar(hw, i,
4037 adapter->mac_table[i].addr,
4038 adapter->mac_table[i].queue,
4039 IXGBE_RAH_AV);
4040 else
4041 hw->mac.ops.clear_rar(hw, i);
4042
4043 adapter->mac_table[i].state &=
4044 ~(IXGBE_MAC_STATE_MODIFIED);
4045 }
4046 }
4047}
4048
4049static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4050{
4051 int i;
4052 struct ixgbe_hw *hw = &adapter->hw;
4053
4054 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4055 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4056 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4057 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4058 adapter->mac_table[i].queue = 0;
4059 }
4060 ixgbe_sync_mac_table(adapter);
4061}
4062
4063static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
4064{
4065 struct ixgbe_hw *hw = &adapter->hw;
4066 int i, count = 0;
4067
4068 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4069 if (adapter->mac_table[i].state == 0)
4070 count++;
4071 }
4072 return count;
4073}
4074
4075/* this function destroys the first RAR entry */
4076static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4077 u8 *addr)
4078{
4079 struct ixgbe_hw *hw = &adapter->hw;
4080
4081 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4082 adapter->mac_table[0].queue = VMDQ_P(0);
4083 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4084 IXGBE_MAC_STATE_IN_USE);
4085 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4086 adapter->mac_table[0].queue,
4087 IXGBE_RAH_AV);
4088}
4089
4090int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4091{
4092 struct ixgbe_hw *hw = &adapter->hw;
4093 int i;
4094
4095 if (is_zero_ether_addr(addr))
4096 return -EINVAL;
4097
4098 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4099 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4100 continue;
4101 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4102 IXGBE_MAC_STATE_IN_USE);
4103 ether_addr_copy(adapter->mac_table[i].addr, addr);
4104 adapter->mac_table[i].queue = queue;
4105 ixgbe_sync_mac_table(adapter);
4106 return i;
4107 }
4108 return -ENOMEM;
4109}
4110
4111int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4112{
4113 /* search table for addr, if found, set to 0 and sync */
4114 int i;
4115 struct ixgbe_hw *hw = &adapter->hw;
4116
4117 if (is_zero_ether_addr(addr))
4118 return -EINVAL;
4119
4120 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4121 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4122 adapter->mac_table[i].queue == queue) {
4123 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4124 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4125 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4126 adapter->mac_table[i].queue = 0;
4127 ixgbe_sync_mac_table(adapter);
4128 return 0;
4129 }
4130 }
4131 return -ENOMEM;
4132}
2850062a
AD		 4133/**
4134 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4135 * @netdev: network interface device structure
4136 *
4137 * Writes unicast address list to the RAR table.
4138 * Returns: -ENOMEM on failure/insufficient address space
4139 * 0 on no addresses written
4140 * X on writing X addresses to the RAR table
4141 **/
5d7daa35 4142static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4143{
4144 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4145 int count = 0;
4146
4147 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4148 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4149 return -ENOMEM;
4150
95447461 4151 if (!netdev_uc_empty(netdev)) {
2850062a 4152 struct netdev_hw_addr *ha;
2850062a 4153 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4154 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4155 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4156 count++;
4157 }
4158 }
2850062a
AD		 4159 return count;
4160}
4161
9a799d71 4162/**
2c5645cf 4163 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4164 * @netdev: network interface device structure
4165 *
2c5645cf
CL		 4166 * The set_rx_method entry point is called whenever the unicast/multicast
4167 * address list or the network interface flags are updated. This routine is
4168 * responsible for configuring the hardware for proper unicast, multicast and
4169 * promiscuous mode.
9a799d71 4170 **/
7f870475 4171void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4172{
4173 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4174 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4175 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4176 u32 vlnctrl;
2850062a 4177 int count;
9a799d71
AK		 4178
4179 /* Check for Promiscuous and All Multicast modes */
9a799d71 4180 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4181 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4182
f5dc442b 4183 /* set all bits that we expect to always be set */
3f2d1c0f 4184 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4185 fctrl |= IXGBE_FCTRL_BAM;
4186 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4187 fctrl |= IXGBE_FCTRL_PMCF;
4188
2850062a
AD		 4189 /* clear the bits we are changing the status of */
4190 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4191 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4192 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4193 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4194 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4195 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4196 /* Only disable hardware filter vlans in promiscuous mode
4197 * if SR-IOV and VMDQ are disabled - otherwise ensure
4198 * that hardware VLAN filters remain enabled.
4199 */
4556dc59
VY		 4200 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4201 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 4202 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4203 } else {
746b9f02
PM		 4204 if (netdev->flags & IFF_ALLMULTI) {
4205 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4206 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4207 }
a9b8943e 4208 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4209 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4210 }
4211
4212 /*
4213 * Write addresses to available RAR registers, if there is not
4214 * sufficient space to store all the addresses then enable
4215 * unicast promiscuous mode
4216 */
5d7daa35 4217 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4218 if (count < 0) {
4219 fctrl |= IXGBE_FCTRL_UPE;
4220 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4221 }
4222
cf78959c
ET		 4223 /* Write addresses to the MTA, if the attempt fails
4224 * then we should just turn on promiscuous mode so
4225 * that we can at least receive multicast traffic
4226 */
b335e75b
JK		 4227 count = ixgbe_write_mc_addr_list(netdev);
4228 if (count < 0) {
4229 fctrl |= IXGBE_FCTRL_MPE;
4230 vmolr |= IXGBE_VMOLR_MPE;
4231 } else if (count) {
4232 vmolr |= IXGBE_VMOLR_ROMPE;
4233 }
1d9c0bfd
AD		 4234
4235 if (hw->mac.type != ixgbe_mac_82598EB) {
4236 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4237 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4238 IXGBE_VMOLR_ROPE);
1d9c0bfd 4239 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4240 }
4241
3f2d1c0f
BG		 4242 /* This is useful for sniffing bad packets. */
4243 if (adapter->netdev->features & NETIF_F_RXALL) {
4244 /* UPE and MPE will be handled by normal PROMISC logic
4245 * in e1000e_set_rx_mode */
4246 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4247 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4248 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4249
4250 fctrl &= ~(IXGBE_FCTRL_DPF);
4251 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4252 }
4253
a9b8943e 4254 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4255 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4256
f646968f 4257 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4258 ixgbe_vlan_strip_enable(adapter);
4259 else
4260 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4261}
4262
021230d4
AV		 4263static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4264{
4265 int q_idx;
021230d4 4266
5a85e737
ET		 4267 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4268 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4269 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4270 }
021230d4
AV		 4271}
4272
4273static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4274{
4275 int q_idx;
021230d4 4276
5a85e737 4277 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4278 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4279 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4280 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4281 usleep_range(1000, 20000);
5a85e737
ET		 4282 }
4283 }
021230d4
AV		 4284}
4285
67359c3c
MR		 4286static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4287{
4288 switch (adapter->hw.mac.type) {
4289 case ixgbe_mac_X550:
4290 case ixgbe_mac_X550EM_x:
4291 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4292#ifdef CONFIG_IXGBE_VXLAN
4293 adapter->vxlan_port = 0;
4294#endif
4295 break;
4296 default:
4297 break;
4298 }
4299}
4300
7a6b6f51 4301#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4302/**
2f90b865
AD		 4303 * ixgbe_configure_dcb - Configure DCB hardware
4304 * @adapter: ixgbe adapter struct
4305 *
4306 * This is called by the driver on open to configure the DCB hardware.
4307 * This is also called by the gennetlink interface when reconfiguring
4308 * the DCB state.
4309 */
4310static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4311{
4312 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4313 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4314
67ebd791
AD		 4315 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4316 if (hw->mac.type == ixgbe_mac_82598EB)
4317 netif_set_gso_max_size(adapter->netdev, 65536);
4318 return;
4319 }
4320
4321 if (hw->mac.type == ixgbe_mac_82598EB)
4322 netif_set_gso_max_size(adapter->netdev, 32768);
4323
971060b1 4324#ifdef IXGBE_FCOE
b120818e
JF		 4325 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4326 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4327#endif
b120818e
JF		 4328
4329 /* reconfigure the hardware */
4330 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4331 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4332 DCB_TX_CONFIG);
4333 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4334 DCB_RX_CONFIG);
4335 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4336 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4337 ixgbe_dcb_hw_ets(&adapter->hw,
4338 adapter->ixgbe_ieee_ets,
4339 max_frame);
4340 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4341 adapter->ixgbe_ieee_pfc->pfc_en,
4342 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4343 }
8187cd48
JF		 4344
4345 /* Enable RSS Hash per TC */
4346 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4347 u32 msb = 0;
4348 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4349
d411a936
AD		 4350 while (rss_i) {
4351 msb++;
4352 rss_i >>= 1;
4353 }
8187cd48 4354
4ae63730
AD		 4355 /* write msb to all 8 TCs in one write */
4356 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4357 }
2f90b865 4358}
9da712d2
JF		 4359#endif
4360
4361/* Additional bittime to account for IXGBE framing */
4362#define IXGBE_ETH_FRAMING 20
4363
49ce9c2c 4364/**
9da712d2
JF		 4365 * ixgbe_hpbthresh - calculate high water mark for flow control
4366 *
4367 * @adapter: board private structure to calculate for
49ce9c2c 4368 * @pb: packet buffer to calculate
9da712d2
JF		 4369 */
4370static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4371{
4372 struct ixgbe_hw *hw = &adapter->hw;
4373 struct net_device *dev = adapter->netdev;
4374 int link, tc, kb, marker;
4375 u32 dv_id, rx_pba;
4376
4377 /* Calculate max LAN frame size */
4378 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4379
4380#ifdef IXGBE_FCOE
4381 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4382 if ((dev->features & NETIF_F_FCOE_MTU) &&
4383 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4384 (pb == ixgbe_fcoe_get_tc(adapter)))
4385 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4386#endif
e5776620 4387
9da712d2
JF		 4388 /* Calculate delay value for device */
4389 switch (hw->mac.type) {
4390 case ixgbe_mac_X540:
9a75a1ac
DS		 4391 case ixgbe_mac_X550:
4392 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4393 dv_id = IXGBE_DV_X540(link, tc);
4394 break;
4395 default:
4396 dv_id = IXGBE_DV(link, tc);
4397 break;
4398 }
4399
4400 /* Loopback switch introduces additional latency */
4401 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4402 dv_id += IXGBE_B2BT(tc);
4403
4404 /* Delay value is calculated in bit times convert to KB */
4405 kb = IXGBE_BT2KB(dv_id);
4406 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4407
4408 marker = rx_pba - kb;
4409
4410 /* It is possible that the packet buffer is not large enough
4411 * to provide required headroom. In this case throw an error
4412 * to user and a do the best we can.
4413 */
4414 if (marker < 0) {
4415 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4416 "headroom to support flow control."
4417 "Decrease MTU or number of traffic classes\n", pb);
4418 marker = tc + 1;
4419 }
4420
4421 return marker;
4422}
4423
49ce9c2c 4424/**
9da712d2
JF		 4425 * ixgbe_lpbthresh - calculate low water mark for for flow control
4426 *
4427 * @adapter: board private structure to calculate for
49ce9c2c 4428 * @pb: packet buffer to calculate
9da712d2 4429 */
e5776620 4430static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4431{
4432 struct ixgbe_hw *hw = &adapter->hw;
4433 struct net_device *dev = adapter->netdev;
4434 int tc;
4435 u32 dv_id;
4436
4437 /* Calculate max LAN frame size */
4438 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4439
e5776620
JK		 4440#ifdef IXGBE_FCOE
4441 /* FCoE traffic class uses FCOE jumbo frames */
4442 if ((dev->features & NETIF_F_FCOE_MTU) &&
4443 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4444 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4445 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4446#endif
4447
9da712d2
JF		 4448 /* Calculate delay value for device */
4449 switch (hw->mac.type) {
4450 case ixgbe_mac_X540:
9a75a1ac
DS		 4451 case ixgbe_mac_X550:
4452 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4453 dv_id = IXGBE_LOW_DV_X540(tc);
4454 break;
4455 default:
4456 dv_id = IXGBE_LOW_DV(tc);
4457 break;
4458 }
4459
4460 /* Delay value is calculated in bit times convert to KB */
4461 return IXGBE_BT2KB(dv_id);
4462}
4463
4464/*
4465 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4466 */
4467static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4468{
4469 struct ixgbe_hw *hw = &adapter->hw;
4470 int num_tc = netdev_get_num_tc(adapter->netdev);
4471 int i;
4472
4473 if (!num_tc)
4474 num_tc = 1;
4475
9da712d2
JF		 4476 for (i = 0; i < num_tc; i++) {
4477 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4478 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4479
4480 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4481 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4482 hw->fc.low_water[i] = 0;
9da712d2 4483 }
e5776620
JK		 4484
4485 for (; i < MAX_TRAFFIC_CLASS; i++)
4486 hw->fc.high_water[i] = 0;
9da712d2
JF		 4487}
4488
80605c65
JF		 4489static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4490{
80605c65 4491 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4492 int hdrm;
4493 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4494
4495 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4496 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4497 hdrm = 32 << adapter->fdir_pballoc;
4498 else
4499 hdrm = 0;
80605c65 4500
f7e1027f 4501 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4502 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4503}
4504
e4911d57
AD		 4505static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4506{
4507 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4508 struct hlist_node *node2;
e4911d57
AD		 4509 struct ixgbe_fdir_filter *filter;
4510
4511 spin_lock(&adapter->fdir_perfect_lock);
4512
4513 if (!hlist_empty(&adapter->fdir_filter_list))
4514 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4515
b67bfe0d 4516 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4517 &adapter->fdir_filter_list, fdir_node) {
4518 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4519 &filter->filter,
4520 filter->sw_idx,
4521 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4522 IXGBE_FDIR_DROP_QUEUE :
4523 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4524 }
4525
4526 spin_unlock(&adapter->fdir_perfect_lock);
4527}
4528
2a47fa45
JF		 4529static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4530 struct ixgbe_adapter *adapter)
4531{
4532 struct ixgbe_hw *hw = &adapter->hw;
4533 u32 vmolr;
4534
4535 /* No unicast promiscuous support for VMDQ devices. */
4536 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4537 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4538
4539 /* clear the affected bit */
4540 vmolr &= ~IXGBE_VMOLR_MPE;
4541
4542 if (dev->flags & IFF_ALLMULTI) {
4543 vmolr |= IXGBE_VMOLR_MPE;
4544 } else {
4545 vmolr |= IXGBE_VMOLR_ROMPE;
4546 hw->mac.ops.update_mc_addr_list(hw, dev);
4547 }
5d7daa35 4548 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4549 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4550}
4551
2a47fa45
JF		 4552static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4553{
4554 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4555 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4556 struct ixgbe_hw *hw = &adapter->hw;
4557 u16 pool = vadapter->pool;
4558 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4559 IXGBE_PSRTYPE_UDPHDR |
4560 IXGBE_PSRTYPE_IPV4HDR |
4561 IXGBE_PSRTYPE_L2HDR |
4562 IXGBE_PSRTYPE_IPV6HDR;
4563
4564 if (hw->mac.type == ixgbe_mac_82598EB)
4565 return;
4566
4567 if (rss_i > 3)
4568 psrtype |= 2 << 29;
4569 else if (rss_i > 1)
4570 psrtype |= 1 << 29;
4571
4572 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4573}
4574
4575/**
4576 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4577 * @rx_ring: ring to free buffers from
4578 **/
4579static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4580{
4581 struct device *dev = rx_ring->dev;
4582 unsigned long size;
4583 u16 i;
4584
4585 /* ring already cleared, nothing to do */
4586 if (!rx_ring->rx_buffer_info)
4587 return;
4588
4589 /* Free all the Rx ring sk_buffs */
4590 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4591 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4592
2a47fa45
JF		 4593 if (rx_buffer->skb) {
4594 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4595 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4596 dma_unmap_page(dev,
4597 IXGBE_CB(skb)->dma,
4598 ixgbe_rx_bufsz(rx_ring),
4599 DMA_FROM_DEVICE);
2a47fa45 4600 dev_kfree_skb(skb);
4d2fcfbc 4601 rx_buffer->skb = NULL;
2a47fa45 4602 }
18cb652a
AD		 4603
4604 if (!rx_buffer->page)
4605 continue;
4606
4607 dma_unmap_page(dev, rx_buffer->dma,
4608 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4609 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4610
2a47fa45
JF		 4611 rx_buffer->page = NULL;
4612 }
4613
4614 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4615 memset(rx_ring->rx_buffer_info, 0, size);
4616
4617 /* Zero out the descriptor ring */
4618 memset(rx_ring->desc, 0, rx_ring->size);
4619
4620 rx_ring->next_to_alloc = 0;
4621 rx_ring->next_to_clean = 0;
4622 rx_ring->next_to_use = 0;
4623}
4624
4625static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4626 struct ixgbe_ring *rx_ring)
4627{
4628 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4629 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4630
4631 /* shutdown specific queue receive and wait for dma to settle */
4632 ixgbe_disable_rx_queue(adapter, rx_ring);
4633 usleep_range(10000, 20000);
4634 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4635 ixgbe_clean_rx_ring(rx_ring);
4636 rx_ring->l2_accel_priv = NULL;
4637}
4638
ae72c8d0
JF		 4639static int ixgbe_fwd_ring_down(struct net_device *vdev,
4640 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4641{
4642 struct ixgbe_adapter *adapter = accel->real_adapter;
4643 unsigned int rxbase = accel->rx_base_queue;
4644 unsigned int txbase = accel->tx_base_queue;
4645 int i;
4646
4647 netif_tx_stop_all_queues(vdev);
4648
4649 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4650 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4651 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4652 }
4653
4654 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4655 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4656 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4657 }
4658
4659
4660 return 0;
4661}
4662
4663static int ixgbe_fwd_ring_up(struct net_device *vdev,
4664 struct ixgbe_fwd_adapter *accel)
4665{
4666 struct ixgbe_adapter *adapter = accel->real_adapter;
4667 unsigned int rxbase, txbase, queues;
4668 int i, baseq, err = 0;
4669
4670 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4671 return 0;
4672
4673 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4674 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4675 accel->pool, adapter->num_rx_pools,
4676 baseq, baseq + adapter->num_rx_queues_per_pool,
4677 adapter->fwd_bitmask);
4678
4679 accel->netdev = vdev;
4680 accel->rx_base_queue = rxbase = baseq;
4681 accel->tx_base_queue = txbase = baseq;
4682
4683 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4684 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4685
4686 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4687 adapter->rx_ring[rxbase + i]->netdev = vdev;
4688 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4689 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4690 }
4691
4692 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4693 adapter->tx_ring[txbase + i]->netdev = vdev;
4694 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4695 }
4696
4697 queues = min_t(unsigned int,
4698 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4699 err = netif_set_real_num_tx_queues(vdev, queues);
4700 if (err)
4701 goto fwd_queue_err;
4702
2a47fa45
JF		 4703 err = netif_set_real_num_rx_queues(vdev, queues);
4704 if (err)
4705 goto fwd_queue_err;
4706
4707 if (is_valid_ether_addr(vdev->dev_addr))
4708 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4709
4710 ixgbe_fwd_psrtype(accel);
4711 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4712 return err;
4713fwd_queue_err:
4714 ixgbe_fwd_ring_down(vdev, accel);
4715 return err;
4716}
4717
4718static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4719{
4720 struct net_device *upper;
4721 struct list_head *iter;
4722 int err;
4723
4724 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4725 if (netif_is_macvlan(upper)) {
4726 struct macvlan_dev *dfwd = netdev_priv(upper);
4727 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4728
4729 if (dfwd->fwd_priv) {
4730 err = ixgbe_fwd_ring_up(upper, vadapter);
4731 if (err)
4732 continue;
4733 }
4734 }
4735 }
4736}
4737
9a799d71
AK		 4738static void ixgbe_configure(struct ixgbe_adapter *adapter)
4739{
d2f5e7f3
AS		 4740 struct ixgbe_hw *hw = &adapter->hw;
4741
80605c65 4742 ixgbe_configure_pb(adapter);
7a6b6f51 4743#ifdef CONFIG_IXGBE_DCB
67ebd791 4744 ixgbe_configure_dcb(adapter);
2f90b865 4745#endif
b35d4d42
AD		 4746 /*
4747 * We must restore virtualization before VLANs or else
4748 * the VLVF registers will not be populated
4749 */
4750 ixgbe_configure_virtualization(adapter);
9a799d71 4751
4c1d7b4b 4752 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4753 ixgbe_restore_vlan(adapter);
4754
d2f5e7f3
AS		 4755 switch (hw->mac.type) {
4756 case ixgbe_mac_82599EB:
4757 case ixgbe_mac_X540:
4758 hw->mac.ops.disable_rx_buff(hw);
4759 break;
4760 default:
4761 break;
4762 }
4763
c4cf55e5 4764 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4765 ixgbe_init_fdir_signature_82599(&adapter->hw,
4766 adapter->fdir_pballoc);
e4911d57
AD		 4767 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4768 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4769 adapter->fdir_pballoc);
4770 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4771 }
4c1d7b4b 4772
d2f5e7f3
AS		 4773 switch (hw->mac.type) {
4774 case ixgbe_mac_82599EB:
4775 case ixgbe_mac_X540:
4776 hw->mac.ops.enable_rx_buff(hw);
4777 break;
4778 default:
4779 break;
4780 }
4781
7c8ae65a
AD		 4782#ifdef IXGBE_FCOE
4783 /* configure FCoE L2 filters, redirection table, and Rx control */
4784 ixgbe_configure_fcoe(adapter);
4785
4786#endif /* IXGBE_FCOE */
9a799d71
AK		 4787 ixgbe_configure_tx(adapter);
4788 ixgbe_configure_rx(adapter);
2a47fa45 4789 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4790}
4791
0ecc061d 4792/**
e8e26350
PW		 4793 * ixgbe_sfp_link_config - set up SFP+ link
4794 * @adapter: pointer to private adapter struct
4795 **/
4796static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4797{
7086400d 4798 /*
52f33af8 4799 * We are assuming the worst case scenario here, and that
7086400d
AD		 4800 * is that an SFP was inserted/removed after the reset
4801 * but before SFP detection was enabled. As such the best
4802 * solution is to just start searching as soon as we start
4803 */
4804 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4805 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4806
7086400d 4807 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 4808 adapter->sfp_poll_time = 0;
e8e26350
PW		 4809}
4810
4811/**
4812 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4813 * @hw: pointer to private hardware struct
4814 *
4815 * Returns 0 on success, negative on failure
4816 **/
e8e26350 4817static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4818{
3d292265
JH		 4819 u32 speed;
4820 bool autoneg, link_up = false;
a1e869de 4821 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 4822
4823 if (hw->mac.ops.check_link)
3d292265 4824 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4825
4826 if (ret)
e90dd264 4827 return ret;
0ecc061d 4828
3d292265
JH		 4829 speed = hw->phy.autoneg_advertised;
4830 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4831 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4832 &autoneg);
0ecc061d 4833 if (ret)
e90dd264 4834 return ret;
0ecc061d 4835
8620a103 4836 if (hw->mac.ops.setup_link)
fd0326f2 4837 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4838
0ecc061d
PWJ		 4839 return ret;
4840}
4841
a34bcfff 4842static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4843{
9a799d71 4844 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4845 u32 gpie = 0;
9a799d71 4846
9b471446 4847 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4848 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4849 IXGBE_GPIE_OCD;
4850 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4851 /*
4852 * use EIAM to auto-mask when MSI-X interrupt is asserted
4853 * this saves a register write for every interrupt
4854 */
4855 switch (hw->mac.type) {
4856 case ixgbe_mac_82598EB:
4857 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4858 break;
9b471446 4859 case ixgbe_mac_82599EB:
b93a2226 4860 case ixgbe_mac_X540:
9a75a1ac
DS		 4861 case ixgbe_mac_X550:
4862 case ixgbe_mac_X550EM_x:
b93a2226 4863 default:
9b471446
JB		 4864 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4865 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4866 break;
4867 }
4868 } else {
021230d4
AV		 4869 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4870 * specifically only auto mask tx and rx interrupts */
4871 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4872 }
9a799d71 4873
a34bcfff
AD		 4874 /* XXX: to interrupt immediately for EICS writes, enable this */
4875 /* gpie |= IXGBE_GPIE_EIMEN; */
4876
4877 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4878 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4879
4880 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4881 case IXGBE_82599_VMDQ_8Q_MASK:
4882 gpie |= IXGBE_GPIE_VTMODE_16;
4883 break;
4884 case IXGBE_82599_VMDQ_4Q_MASK:
4885 gpie |= IXGBE_GPIE_VTMODE_32;
4886 break;
4887 default:
4888 gpie |= IXGBE_GPIE_VTMODE_64;
4889 break;
4890 }
119fc60a
MC		 4891 }
4892
5fdd31f9 4893 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4894 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4895 switch (adapter->hw.mac.type) {
4896 case ixgbe_mac_82599EB:
9a900eca 4897 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec
DS		 4898 break;
4899 case ixgbe_mac_X540:
4900 gpie |= IXGBE_EIMS_TS;
4901 break;
4902 default:
4903 break;
4904 }
4905 }
5fdd31f9 4906
a34bcfff
AD		 4907 /* Enable fan failure interrupt */
4908 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 4909 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 4910
a023bbd0
DS		 4911 switch (hw->mac.type) {
4912 case ixgbe_mac_82599EB:
4913 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
4914 break;
4915 case ixgbe_mac_X550EM_x:
4916 gpie |= IXGBE_SDP0_GPIEN_X540;
4917 break;
4918 default:
4919 break;
2698b208 4920 }
a34bcfff
AD		 4921
4922 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4923}
4924
c7ccde0f 4925static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4926{
4927 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4928 int err;
a34bcfff
AD		 4929 u32 ctrl_ext;
4930
4931 ixgbe_get_hw_control(adapter);
4932 ixgbe_setup_gpie(adapter);
e8e26350 4933
9a799d71
AK		 4934 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4935 ixgbe_configure_msix(adapter);
4936 else
4937 ixgbe_configure_msi_and_legacy(adapter);
4938
ec74a471
ET		 4939 /* enable the optics for 82599 SFP+ fiber */
4940 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4941 hw->mac.ops.enable_tx_laser(hw);
4942
961fac88
DS		 4943 if (hw->phy.ops.set_phy_power)
4944 hw->phy.ops.set_phy_power(hw, true);
4945
4e857c58 4946 smp_mb__before_atomic();
9a799d71 4947 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4948 ixgbe_napi_enable_all(adapter);
4949
73c4b7cd
AD		 4950 if (ixgbe_is_sfp(hw)) {
4951 ixgbe_sfp_link_config(adapter);
4952 } else {
4953 err = ixgbe_non_sfp_link_config(hw);
4954 if (err)
4955 e_err(probe, "link_config FAILED %d\n", err);
4956 }
4957
021230d4
AV		 4958 /* clear any pending interrupts, may auto mask */
4959 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4960 ixgbe_irq_enable(adapter, true, true);
9a799d71 4961
bf069c97
DS		 4962 /*
4963 * If this adapter has a fan, check to see if we had a failure
4964 * before we enabled the interrupt.
4965 */
4966 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4967 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4968 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4969 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4970 }
4971
9a799d71
AK		 4972 /* bring the link up in the watchdog, this could race with our first
4973 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4974 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4975 adapter->link_check_timeout = jiffies;
7086400d 4976 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4977
4978 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4979 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4980 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4981 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4982}
4983
d4f80882
AV		 4984void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4985{
4986 WARN_ON(in_interrupt());
7086400d
AD		 4987 /* put off any impending NetWatchDogTimeout */
4988 adapter->netdev->trans_start = jiffies;
4989
d4f80882 4990 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4991 usleep_range(1000, 2000);
d4f80882 4992 ixgbe_down(adapter);
5809a1ae
GR		 4993 /*
4994 * If SR-IOV enabled then wait a bit before bringing the adapter
4995 * back up to give the VFs time to respond to the reset. The
4996 * two second wait is based upon the watchdog timer cycle in
4997 * the VF driver.
4998 */
4999 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5000 msleep(2000);
d4f80882
AV		 5001 ixgbe_up(adapter);
5002 clear_bit(__IXGBE_RESETTING, &adapter->state);
5003}
5004
c7ccde0f 5005void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5006{
5007 /* hardware has been reset, we need to reload some things */
5008 ixgbe_configure(adapter);
5009
c7ccde0f 5010 ixgbe_up_complete(adapter);
9a799d71
AK		 5011}
5012
5013void ixgbe_reset(struct ixgbe_adapter *adapter)
5014{
c44ade9e 5015 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5016 struct net_device *netdev = adapter->netdev;
8ca783ab 5017 int err;
5d7daa35 5018 u8 old_addr[ETH_ALEN];
8ca783ab 5019
b0483c8f
MR		 5020 if (ixgbe_removed(hw->hw_addr))
5021 return;
7086400d
AD		 5022 /* lock SFP init bit to prevent race conditions with the watchdog */
5023 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5024 usleep_range(1000, 2000);
5025
5026 /* clear all SFP and link config related flags while holding SFP_INIT */
5027 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5028 IXGBE_FLAG2_SFP_NEEDS_RESET);
5029 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5030
8ca783ab 5031 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5032 switch (err) {
5033 case 0:
5034 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5035 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5036 break;
5037 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5038 e_dev_err("master disable timed out\n");
da4dd0f7 5039 break;
794caeb2
PWJ		 5040 case IXGBE_ERR_EEPROM_VERSION:
5041 /* We are running on a pre-production device, log a warning */
849c4542 5042 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5043 "Please be aware there may be issues associated with "
849c4542
ET		 5044 "your hardware. If you are experiencing problems "
5045 "please contact your Intel or hardware "
5046 "representative who provided you with this "
5047 "hardware.\n");
794caeb2 5048 break;
da4dd0f7 5049 default:
849c4542 5050 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5051 }
9a799d71 5052
7086400d 5053 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 5054 /* do not flush user set addresses */
5055 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
5056 ixgbe_flush_sw_mac_table(adapter);
5057 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 5058
5059 /* update SAN MAC vmdq pool selection */
5060 if (hw->mac.san_mac_rar_index)
5061 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5062
8fecf67c 5063 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5064 ixgbe_ptp_reset(adapter);
961fac88
DS		 5065
5066 if (hw->phy.ops.set_phy_power) {
5067 if (!netif_running(adapter->netdev) && !adapter->wol)
5068 hw->phy.ops.set_phy_power(hw, false);
5069 else
5070 hw->phy.ops.set_phy_power(hw, true);
5071 }
9a799d71
AK		 5072}
5073
9a799d71
AK		 5074/**
5075 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5076 * @tx_ring: ring to be cleaned
5077 **/
b6ec895e 5078static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5079{
5080 struct ixgbe_tx_buffer *tx_buffer_info;
5081 unsigned long size;
b6ec895e 5082 u16 i;
9a799d71 5083
84418e3b
AD		 5084 /* ring already cleared, nothing to do */
5085 if (!tx_ring->tx_buffer_info)
5086 return;
9a799d71 5087
84418e3b 5088 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5089 for (i = 0; i < tx_ring->count; i++) {
5090 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5091 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5092 }
5093
dad8a3b3
JF		 5094 netdev_tx_reset_queue(txring_txq(tx_ring));
5095
9a799d71
AK		 5096 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5097 memset(tx_ring->tx_buffer_info, 0, size);
5098
5099 /* Zero out the descriptor ring */
5100 memset(tx_ring->desc, 0, tx_ring->size);
5101
5102 tx_ring->next_to_use = 0;
5103 tx_ring->next_to_clean = 0;
9a799d71
AK		 5104}
5105
5106/**
021230d4 5107 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5108 * @adapter: board private structure
5109 **/
021230d4 5110static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5111{
5112 int i;
5113
021230d4 5114 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5115 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5116}
5117
5118/**
021230d4 5119 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5120 * @adapter: board private structure
5121 **/
021230d4 5122static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5123{
5124 int i;
5125
021230d4 5126 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5127 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5128}
5129
e4911d57
AD		 5130static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5131{
b67bfe0d 5132 struct hlist_node *node2;
e4911d57
AD		 5133 struct ixgbe_fdir_filter *filter;
5134
5135 spin_lock(&adapter->fdir_perfect_lock);
5136
b67bfe0d 5137 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5138 &adapter->fdir_filter_list, fdir_node) {
5139 hlist_del(&filter->fdir_node);
5140 kfree(filter);
5141 }
5142 adapter->fdir_filter_count = 0;
5143
5144 spin_unlock(&adapter->fdir_perfect_lock);
5145}
5146
9a799d71
AK		 5147void ixgbe_down(struct ixgbe_adapter *adapter)
5148{
5149 struct net_device *netdev = adapter->netdev;
7f821875 5150 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5151 struct net_device *upper;
5152 struct list_head *iter;
bf29ee6c 5153 int i;
9a799d71
AK		 5154
5155 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5156 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5157 return; /* do nothing if already down */
9a799d71
AK		 5158
5159 /* disable receives */
1f9ac57c 5160 hw->mac.ops.disable_rx(hw);
9a799d71 5161
2d39d576
YZ		 5162 /* disable all enabled rx queues */
5163 for (i = 0; i < adapter->num_rx_queues; i++)
5164 /* this call also flushes the previous write */
5165 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5166
032b4325 5167 usleep_range(10000, 20000);
9a799d71 5168
7f821875
JB		 5169 netif_tx_stop_all_queues(netdev);
5170
7086400d 5171 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5172 netif_carrier_off(netdev);
5173 netif_tx_disable(netdev);
5174
2a47fa45
JF		 5175 /* disable any upper devices */
5176 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5177 if (netif_is_macvlan(upper)) {
5178 struct macvlan_dev *vlan = netdev_priv(upper);
5179
5180 if (vlan->fwd_priv) {
5181 netif_tx_stop_all_queues(upper);
5182 netif_carrier_off(upper);
5183 netif_tx_disable(upper);
5184 }
5185 }
5186 }
5187
c0dfb90e
JF		 5188 ixgbe_irq_disable(adapter);
5189
5190 ixgbe_napi_disable_all(adapter);
5191
d034acf1
AD		 5192 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5193 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5194 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5195
5196 del_timer_sync(&adapter->service_timer);
5197
34cecbbf 5198 if (adapter->num_vfs) {
8e34d1aa
AD		 5199 /* Clear EITR Select mapping */
5200 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5201
5202 /* Mark all the VFs as inactive */
5203 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5204 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5205
34cecbbf
AD		 5206 /* ping all the active vfs to let them know we are going down */
5207 ixgbe_ping_all_vfs(adapter);
5208
5209 /* Disable all VFTE/VFRE TX/RX */
5210 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5211 }
5212
7f821875
JB		 5213 /* disable transmits in the hardware now that interrupts are off */
5214 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5215 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5216 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5217 }
34cecbbf 5218
9a75a1ac 5219 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5220 switch (hw->mac.type) {
5221 case ixgbe_mac_82599EB:
b93a2226 5222 case ixgbe_mac_X540:
9a75a1ac
DS		 5223 case ixgbe_mac_X550:
5224 case ixgbe_mac_X550EM_x:
88512539 5225 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5226 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5227 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5228 break;
5229 default:
5230 break;
5231 }
7f821875 5232
6f4a0e45
PL		 5233 if (!pci_channel_offline(adapter->pdev))
5234 ixgbe_reset(adapter);
c6ecf39a 5235
ec74a471
ET		 5236 /* power down the optics for 82599 SFP+ fiber */
5237 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5238 hw->mac.ops.disable_tx_laser(hw);
5239
9a799d71
AK		 5240 ixgbe_clean_all_tx_rings(adapter);
5241 ixgbe_clean_all_rx_rings(adapter);
5242
5dd2d332 5243#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5244 /* since we reset the hardware DCA settings were cleared */
e35ec126 5245 ixgbe_setup_dca(adapter);
96b0e0f6 5246#endif
9a799d71
AK		 5247}
5248
9a799d71
AK		 5249/**
5250 * ixgbe_tx_timeout - Respond to a Tx Hang
5251 * @netdev: network interface device structure
5252 **/
5253static void ixgbe_tx_timeout(struct net_device *netdev)
5254{
5255 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5256
5257 /* Do the reset outside of interrupt context */
c83c6cbd 5258 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5259}
5260
9a799d71
AK		 5261/**
5262 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5263 * @adapter: board private structure to initialize
5264 *
5265 * ixgbe_sw_init initializes the Adapter private data structure.
5266 * Fields are initialized based on PCI device information and
5267 * OS network device settings (MTU size).
5268 **/
9f9a12f8 5269static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5270{
5271 struct ixgbe_hw *hw = &adapter->hw;
5272 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5273 unsigned int rss, fdir;
cb6d0f5e 5274 u32 fwsm;
7a6b6f51 5275#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5276 int j;
5277 struct tc_configuration *tc;
5278#endif
021230d4 5279
c44ade9e
JB		 5280 /* PCI config space info */
5281
5282 hw->vendor_id = pdev->vendor;
5283 hw->device_id = pdev->device;
5284 hw->revision_id = pdev->revision;
5285 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5286 hw->subsystem_device_id = pdev->subsystem_device;
5287
8fc3bb6d 5288 /* Set common capability flags and settings */
0f9b232b 5289 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5290 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5291 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5292 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5293 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5294 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5295 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5296 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5297 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5298#ifdef CONFIG_IXGBE_DCA
5299 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5300#endif
5301#ifdef IXGBE_FCOE
5302 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5303 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5304#ifdef CONFIG_IXGBE_DCB
5305 /* Default traffic class to use for FCoE */
5306 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5307#endif /* CONFIG_IXGBE_DCB */
5308#endif /* IXGBE_FCOE */
5309
5d7daa35
JK		 5310 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5311 hw->mac.num_rar_entries,
5312 GFP_ATOMIC);
5313
8fc3bb6d 5314 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5315 switch (hw->mac.type) {
5316 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5317 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5318 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5319
bf069c97
DS		 5320 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5321 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5322
49c7ffbe 5323 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5324 adapter->ring_feature[RING_F_FDIR].limit = 0;
5325 adapter->atr_sample_rate = 0;
5326 adapter->fdir_pballoc = 0;
5327#ifdef IXGBE_FCOE
5328 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5329 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5330#ifdef CONFIG_IXGBE_DCB
5331 adapter->fcoe.up = 0;
5332#endif /* IXGBE_DCB */
5333#endif /* IXGBE_FCOE */
5334 break;
5335 case ixgbe_mac_82599EB:
5336 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5337 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5338 break;
b93a2226 5339 case ixgbe_mac_X540:
9a900eca 5340 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5341 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5342 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5343 break;
9a75a1ac
DS		 5344 case ixgbe_mac_X550EM_x:
5345 case ixgbe_mac_X550:
5346#ifdef CONFIG_IXGBE_DCA
5347 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5348#endif
5349#ifdef CONFIG_IXGBE_VXLAN
5350 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5351#endif
5352 break;
bd508178
AD		 5353 default:
5354 break;
f8212f97 5355 }
2f90b865 5356
7c8ae65a
AD		 5357#ifdef IXGBE_FCOE
5358 /* FCoE support exists, always init the FCoE lock */
5359 spin_lock_init(&adapter->fcoe.lock);
5360
5361#endif
1fc5f038
AD		 5362 /* n-tuple support exists, always init our spinlock */
5363 spin_lock_init(&adapter->fdir_perfect_lock);
5364
7a6b6f51 5365#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5366 switch (hw->mac.type) {
5367 case ixgbe_mac_X540:
9a75a1ac
DS		 5368 case ixgbe_mac_X550:
5369 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5370 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5371 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5372 break;
5373 default:
5374 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5375 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5376 break;
5377 }
5378
2f90b865
AD		 5379 /* Configure DCB traffic classes */
5380 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5381 tc = &adapter->dcb_cfg.tc_config[j];
5382 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5383 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5384 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5385 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5386 tc->dcb_pfc = pfc_disabled;
5387 }
4de2a022
JF		 5388
5389 /* Initialize default user to priority mapping, UPx->TC0 */
5390 tc = &adapter->dcb_cfg.tc_config[0];
5391 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5392 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5393
2f90b865
AD		 5394 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5395 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5396 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5397 adapter->dcb_set_bitmap = 0x00;
3032309b 5398 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5399 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5400 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5401
5402#endif
9a799d71
AK		 5403
5404 /* default flow control settings */
cd7664f6 5405 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5406 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5407 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5408 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5409 hw->fc.send_xon = true;
73d80953 5410 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5411
99d74487 5412#ifdef CONFIG_PCI_IOV
170e8543
JK		 5413 if (max_vfs > 0)
5414 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5415
99d74487 5416 /* assign number of SR-IOV VFs */
170e8543 5417 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5418 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5419 adapter->num_vfs = 0;
5420 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5421 } else {
5422 adapter->num_vfs = max_vfs;
5423 }
5424 }
5425#endif /* CONFIG_PCI_IOV */
99d74487 5426
30efa5a3 5427 /* enable itr by default in dynamic mode */
f7554a2b 5428 adapter->rx_itr_setting = 1;
f7554a2b 5429 adapter->tx_itr_setting = 1;
30efa5a3 5430
30efa5a3
JB		 5431 /* set default ring sizes */
5432 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5433 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5434
bd198058 5435 /* set default work limits */
59224555 5436 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5437
9a799d71 5438 /* initialize eeprom parameters */
c44ade9e 5439 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5440 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5441 return -EIO;
5442 }
5443
2a47fa45
JF		 5444 /* PF holds first pool slot */
5445 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5446 set_bit(__IXGBE_DOWN, &adapter->state);
5447
5448 return 0;
5449}
5450
5451/**
5452 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5453 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5454 *
5455 * Return 0 on success, negative on failure
5456 **/
b6ec895e 5457int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5458{
b6ec895e 5459 struct device *dev = tx_ring->dev;
de88eeeb 5460 int orig_node = dev_to_node(dev);
ca8dfe25 5461 int ring_node = -1;
9a799d71
AK		 5462 int size;
5463
3a581073 5464 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5465
5466 if (tx_ring->q_vector)
ca8dfe25 5467 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5468
ca8dfe25 5469 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5470 if (!tx_ring->tx_buffer_info)
89bf67f1 5471 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5472 if (!tx_ring->tx_buffer_info)
5473 goto err;
9a799d71 5474
827da44c
JS		 5475 u64_stats_init(&tx_ring->syncp);
5476
9a799d71 5477 /* round up to nearest 4K */
12207e49 5478 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5479 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5480
ca8dfe25 5481 set_dev_node(dev, ring_node);
de88eeeb
AD		 5482 tx_ring->desc = dma_alloc_coherent(dev,
5483 tx_ring->size,
5484 &tx_ring->dma,
5485 GFP_KERNEL);
5486 set_dev_node(dev, orig_node);
5487 if (!tx_ring->desc)
5488 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5489 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5490 if (!tx_ring->desc)
5491 goto err;
9a799d71 5492
3a581073
JB		 5493 tx_ring->next_to_use = 0;
5494 tx_ring->next_to_clean = 0;
9a799d71 5495 return 0;
e01c31a5
JB		 5496
5497err:
5498 vfree(tx_ring->tx_buffer_info);
5499 tx_ring->tx_buffer_info = NULL;
b6ec895e 5500 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5501 return -ENOMEM;
9a799d71
AK		 5502}
5503
69888674
AD		 5504/**
5505 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5506 * @adapter: board private structure
5507 *
5508 * If this function returns with an error, then it's possible one or
5509 * more of the rings is populated (while the rest are not). It is the
5510 * callers duty to clean those orphaned rings.
5511 *
5512 * Return 0 on success, negative on failure
5513 **/
5514static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5515{
5516 int i, err = 0;
5517
5518 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5519 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5520 if (!err)
5521 continue;
de3d5b94 5522
396e799c 5523 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5524 goto err_setup_tx;
69888674
AD		 5525 }
5526
de3d5b94
AD		 5527 return 0;
5528err_setup_tx:
5529 /* rewind the index freeing the rings as we go */
5530 while (i--)
5531 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5532 return err;
5533}
5534
9a799d71
AK		 5535/**
5536 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5537 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5538 *
5539 * Returns 0 on success, negative on failure
5540 **/
b6ec895e 5541int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5542{
b6ec895e 5543 struct device *dev = rx_ring->dev;
de88eeeb 5544 int orig_node = dev_to_node(dev);
ca8dfe25 5545 int ring_node = -1;
021230d4 5546 int size;
9a799d71 5547
3a581073 5548 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5549
5550 if (rx_ring->q_vector)
ca8dfe25 5551 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5552
ca8dfe25 5553 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5554 if (!rx_ring->rx_buffer_info)
89bf67f1 5555 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5556 if (!rx_ring->rx_buffer_info)
5557 goto err;
9a799d71 5558
827da44c
JS		 5559 u64_stats_init(&rx_ring->syncp);
5560
9a799d71 5561 /* Round up to nearest 4K */
3a581073
JB		 5562 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5563 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5564
ca8dfe25 5565 set_dev_node(dev, ring_node);
de88eeeb
AD		 5566 rx_ring->desc = dma_alloc_coherent(dev,
5567 rx_ring->size,
5568 &rx_ring->dma,
5569 GFP_KERNEL);
5570 set_dev_node(dev, orig_node);
5571 if (!rx_ring->desc)
5572 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5573 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5574 if (!rx_ring->desc)
5575 goto err;
9a799d71 5576
3a581073
JB		 5577 rx_ring->next_to_clean = 0;
5578 rx_ring->next_to_use = 0;
9a799d71
AK		 5579
5580 return 0;
b6ec895e
AD		 5581err:
5582 vfree(rx_ring->rx_buffer_info);
5583 rx_ring->rx_buffer_info = NULL;
5584 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5585 return -ENOMEM;
9a799d71
AK		 5586}
5587
69888674
AD		 5588/**
5589 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5590 * @adapter: board private structure
5591 *
5592 * If this function returns with an error, then it's possible one or
5593 * more of the rings is populated (while the rest are not). It is the
5594 * callers duty to clean those orphaned rings.
5595 *
5596 * Return 0 on success, negative on failure
5597 **/
69888674
AD		 5598static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5599{
5600 int i, err = 0;
5601
5602 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5603 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5604 if (!err)
5605 continue;
de3d5b94 5606
396e799c 5607 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5608 goto err_setup_rx;
69888674
AD		 5609 }
5610
7c8ae65a
AD		 5611#ifdef IXGBE_FCOE
5612 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5613 if (!err)
5614#endif
5615 return 0;
de3d5b94
AD		 5616err_setup_rx:
5617 /* rewind the index freeing the rings as we go */
5618 while (i--)
5619 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5620 return err;
5621}
5622
9a799d71
AK		 5623/**
5624 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5625 * @tx_ring: Tx descriptor ring for a specific queue
5626 *
5627 * Free all transmit software resources
5628 **/
b6ec895e 5629void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5630{
b6ec895e 5631 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5632
5633 vfree(tx_ring->tx_buffer_info);
5634 tx_ring->tx_buffer_info = NULL;
5635
b6ec895e
AD		 5636 /* if not set, then don't free */
5637 if (!tx_ring->desc)
5638 return;
5639
5640 dma_free_coherent(tx_ring->dev, tx_ring->size,
5641 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5642
5643 tx_ring->desc = NULL;
5644}
5645
5646/**
5647 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5648 * @adapter: board private structure
5649 *
5650 * Free all transmit software resources
5651 **/
5652static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5653{
5654 int i;
5655
5656 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5657 if (adapter->tx_ring[i]->desc)
b6ec895e 5658 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5659}
5660
5661/**
b4617240 5662 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5663 * @rx_ring: ring to clean the resources from
5664 *
5665 * Free all receive software resources
5666 **/
b6ec895e 5667void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5668{
b6ec895e 5669 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5670
5671 vfree(rx_ring->rx_buffer_info);
5672 rx_ring->rx_buffer_info = NULL;
5673
b6ec895e
AD		 5674 /* if not set, then don't free */
5675 if (!rx_ring->desc)
5676 return;
5677
5678 dma_free_coherent(rx_ring->dev, rx_ring->size,
5679 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5680
5681 rx_ring->desc = NULL;
5682}
5683
5684/**
5685 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5686 * @adapter: board private structure
5687 *
5688 * Free all receive software resources
5689 **/
5690static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5691{
5692 int i;
5693
7c8ae65a
AD		 5694#ifdef IXGBE_FCOE
5695 ixgbe_free_fcoe_ddp_resources(adapter);
5696
5697#endif
9a799d71 5698 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5699 if (adapter->rx_ring[i]->desc)
b6ec895e 5700 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5701}
5702
9a799d71
AK		 5703/**
5704 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5705 * @netdev: network interface device structure
5706 * @new_mtu: new value for maximum frame size
5707 *
5708 * Returns 0 on success, negative on failure
5709 **/
5710static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5711{
5712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5713 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5714
42c783c5 5715 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5716 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5717 return -EINVAL;
5718
5719 /*
872844dd
AD		 5720 * For 82599EB we cannot allow legacy VFs to enable their receive
5721 * paths when MTU greater than 1500 is configured. So display a
5722 * warning that legacy VFs will be disabled.
655309e9
AD		 5723 */
5724 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5725 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5726 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5727 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5728
396e799c 5729 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5730
021230d4 5731 /* must set new MTU before calling down or up */
9a799d71
AK		 5732 netdev->mtu = new_mtu;
5733
d4f80882
AV		 5734 if (netif_running(netdev))
5735 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5736
5737 return 0;
5738}
5739
5740/**
5741 * ixgbe_open - Called when a network interface is made active
5742 * @netdev: network interface device structure
5743 *
5744 * Returns 0 on success, negative value on failure
5745 *
5746 * The open entry point is called when a network interface is made
5747 * active by the system (IFF_UP). At this point all resources needed
5748 * for transmit and receive operations are allocated, the interrupt
5749 * handler is registered with the OS, the watchdog timer is started,
5750 * and the stack is notified that the interface is ready.
5751 **/
5752static int ixgbe_open(struct net_device *netdev)
5753{
5754 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5755 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5756 int err, queues;
4bebfaa5
AK		 5757
5758 /* disallow open during test */
5759 if (test_bit(__IXGBE_TESTING, &adapter->state))
5760 return -EBUSY;
9a799d71 5761
54386467
JB		 5762 netif_carrier_off(netdev);
5763
9a799d71
AK		 5764 /* allocate transmit descriptors */
5765 err = ixgbe_setup_all_tx_resources(adapter);
5766 if (err)
5767 goto err_setup_tx;
5768
9a799d71
AK		 5769 /* allocate receive descriptors */
5770 err = ixgbe_setup_all_rx_resources(adapter);
5771 if (err)
5772 goto err_setup_rx;
5773
5774 ixgbe_configure(adapter);
5775
021230d4 5776 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5777 if (err)
5778 goto err_req_irq;
5779
ac802f5d 5780 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5781 if (adapter->num_rx_pools > 1)
5782 queues = adapter->num_rx_queues_per_pool;
5783 else
5784 queues = adapter->num_tx_queues;
5785
5786 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5787 if (err)
5788 goto err_set_queues;
5789
2a47fa45
JF		 5790 if (adapter->num_rx_pools > 1 &&
5791 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5792 queues = IXGBE_MAX_L2A_QUEUES;
5793 else
5794 queues = adapter->num_rx_queues;
5795 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5796 if (err)
5797 goto err_set_queues;
5798
1a71ab24 5799 ixgbe_ptp_init(adapter);
1a71ab24 5800
c7ccde0f 5801 ixgbe_up_complete(adapter);
9a799d71 5802
67359c3c
MR		 5803 ixgbe_clear_vxlan_port(adapter);
5804#ifdef CONFIG_IXGBE_VXLAN
3f207800 5805 vxlan_get_rx_port(netdev);
3f207800 5806#endif
67359c3c 5807
9a799d71
AK		 5808 return 0;
5809
ac802f5d
AD		 5810err_set_queues:
5811 ixgbe_free_irq(adapter);
9a799d71 5812err_req_irq:
a20a1199 5813 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 5814 if (hw->phy.ops.set_phy_power && !adapter->wol)
5815 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 5816err_setup_rx:
a20a1199 5817 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5818err_setup_tx:
9a799d71
AK		 5819 ixgbe_reset(adapter);
5820
5821 return err;
5822}
5823
a0cccce2
JK		 5824static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5825{
5826 ixgbe_ptp_suspend(adapter);
5827
6ac74394
DS		 5828 if (adapter->hw.phy.ops.enter_lplu) {
5829 adapter->hw.phy.reset_disable = true;
5830 ixgbe_down(adapter);
5831 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5832 adapter->hw.phy.reset_disable = false;
5833 } else {
5834 ixgbe_down(adapter);
5835 }
5836
a0cccce2
JK		 5837 ixgbe_free_irq(adapter);
5838
5839 ixgbe_free_all_tx_resources(adapter);
5840 ixgbe_free_all_rx_resources(adapter);
5841}
5842
9a799d71
AK		 5843/**
5844 * ixgbe_close - Disables a network interface
5845 * @netdev: network interface device structure
5846 *
5847 * Returns 0, this is not allowed to fail
5848 *
5849 * The close entry point is called when an interface is de-activated
5850 * by the OS. The hardware is still under the drivers control, but
5851 * needs to be disabled. A global MAC reset is issued to stop the
5852 * hardware, and all transmit and receive resources are freed.
5853 **/
5854static int ixgbe_close(struct net_device *netdev)
5855{
5856 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5857
1a71ab24 5858 ixgbe_ptp_stop(adapter);
1a71ab24 5859
a0cccce2 5860 ixgbe_close_suspend(adapter);
9a799d71 5861
e4911d57
AD		 5862 ixgbe_fdir_filter_exit(adapter);
5863
5eba3699 5864 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5865
5866 return 0;
5867}
5868
b3c8b4ba
AD		 5869#ifdef CONFIG_PM
5870static int ixgbe_resume(struct pci_dev *pdev)
5871{
c60fbb00
AD		 5872 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5873 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5874 u32 err;
5875
0391bbe3 5876 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5877 pci_set_power_state(pdev, PCI_D0);
5878 pci_restore_state(pdev);
656ab817
DS		 5879 /*
5880 * pci_restore_state clears dev->state_saved so call
5881 * pci_save_state to restore it.
5882 */
5883 pci_save_state(pdev);
9ce77666 5884
5885 err = pci_enable_device_mem(pdev);
b3c8b4ba 5886 if (err) {
849c4542 5887 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5888 return err;
5889 }
4e857c58 5890 smp_mb__before_atomic();
41c62843 5891 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5892 pci_set_master(pdev);
5893
dd4d8ca6 5894 pci_wake_from_d3(pdev, false);
b3c8b4ba 5895
b3c8b4ba
AD		 5896 ixgbe_reset(adapter);
5897
495dce12
WJP		 5898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5899
ac802f5d
AD		 5900 rtnl_lock();
5901 err = ixgbe_init_interrupt_scheme(adapter);
5902 if (!err && netif_running(netdev))
c60fbb00 5903 err = ixgbe_open(netdev);
ac802f5d
AD		 5904
5905 rtnl_unlock();
5906
5907 if (err)
5908 return err;
b3c8b4ba
AD		 5909
5910 netif_device_attach(netdev);
5911
5912 return 0;
5913}
b3c8b4ba 5914#endif /* CONFIG_PM */
9d8d05ae
RW		 5915
5916static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5917{
c60fbb00
AD		 5918 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5919 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5920 struct ixgbe_hw *hw = &adapter->hw;
5921 u32 ctrl, fctrl;
5922 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5923#ifdef CONFIG_PM
5924 int retval = 0;
5925#endif
5926
5927 netif_device_detach(netdev);
5928
499ab5cc 5929 rtnl_lock();
a0cccce2
JK		 5930 if (netif_running(netdev))
5931 ixgbe_close_suspend(adapter);
499ab5cc 5932 rtnl_unlock();
b3c8b4ba 5933
5f5ae6fc
AD		 5934 ixgbe_clear_interrupt_scheme(adapter);
5935
b3c8b4ba
AD		 5936#ifdef CONFIG_PM
5937 retval = pci_save_state(pdev);
5938 if (retval)
5939 return retval;
4df10466 5940
b3c8b4ba 5941#endif
f4f1040a
JK		 5942 if (hw->mac.ops.stop_link_on_d3)
5943 hw->mac.ops.stop_link_on_d3(hw);
5944
e8e26350
PW		 5945 if (wufc) {
5946 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5947
ec74a471
ET		 5948 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5949 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5950 hw->mac.ops.enable_tx_laser(hw);
5951
e8e26350
PW		 5952 /* turn on all-multi mode if wake on multicast is enabled */
5953 if (wufc & IXGBE_WUFC_MC) {
5954 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5955 fctrl |= IXGBE_FCTRL_MPE;
5956 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5957 }
5958
5959 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5960 ctrl |= IXGBE_CTRL_GIO_DIS;
5961 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5962
5963 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5964 } else {
5965 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5966 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5967 }
5968
bd508178
AD		 5969 switch (hw->mac.type) {
5970 case ixgbe_mac_82598EB:
dd4d8ca6 5971 pci_wake_from_d3(pdev, false);
bd508178
AD		 5972 break;
5973 case ixgbe_mac_82599EB:
b93a2226 5974 case ixgbe_mac_X540:
9a75a1ac
DS		 5975 case ixgbe_mac_X550:
5976 case ixgbe_mac_X550EM_x:
bd508178
AD		 5977 pci_wake_from_d3(pdev, !!wufc);
5978 break;
5979 default:
5980 break;
5981 }
b3c8b4ba 5982
9d8d05ae 5983 *enable_wake = !!wufc;
961fac88
DS		 5984 if (hw->phy.ops.set_phy_power && !*enable_wake)
5985 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 5986
b3c8b4ba
AD		 5987 ixgbe_release_hw_control(adapter);
5988
41c62843
MR		 5989 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5990 pci_disable_device(pdev);
b3c8b4ba 5991
9d8d05ae
RW		 5992 return 0;
5993}
5994
5995#ifdef CONFIG_PM
5996static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5997{
5998 int retval;
5999 bool wake;
6000
6001 retval = __ixgbe_shutdown(pdev, &wake);
6002 if (retval)
6003 return retval;
6004
6005 if (wake) {
6006 pci_prepare_to_sleep(pdev);
6007 } else {
6008 pci_wake_from_d3(pdev, false);
6009 pci_set_power_state(pdev, PCI_D3hot);
6010 }
b3c8b4ba
AD		 6011
6012 return 0;
6013}
9d8d05ae 6014#endif /* CONFIG_PM */
b3c8b4ba
AD		 6015
6016static void ixgbe_shutdown(struct pci_dev *pdev)
6017{
9d8d05ae
RW		 6018 bool wake;
6019
6020 __ixgbe_shutdown(pdev, &wake);
6021
6022 if (system_state == SYSTEM_POWER_OFF) {
6023 pci_wake_from_d3(pdev, wake);
6024 pci_set_power_state(pdev, PCI_D3hot);
6025 }
b3c8b4ba
AD		 6026}
6027
9a799d71
AK		 6028/**
6029 * ixgbe_update_stats - Update the board statistics counters.
6030 * @adapter: board private structure
6031 **/
6032void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6033{
2d86f139 6034 struct net_device *netdev = adapter->netdev;
9a799d71 6035 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6036 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6037 u64 total_mpc = 0;
6038 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6039 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6040 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6041 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6042
d08935c2
DS		 6043 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6044 test_bit(__IXGBE_RESETTING, &adapter->state))
6045 return;
6046
94b982b2 6047 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6048 u64 rsc_count = 0;
94b982b2 6049 u64 rsc_flush = 0;
94b982b2 6050 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6051 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6052 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6053 }
6054 adapter->rsc_total_count = rsc_count;
6055 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6056 }
6057
5b7da515
AD		 6058 for (i = 0; i < adapter->num_rx_queues; i++) {
6059 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6060 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6061 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6062 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6063 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6064 bytes += rx_ring->stats.bytes;
6065 packets += rx_ring->stats.packets;
6066 }
6067 adapter->non_eop_descs = non_eop_descs;
6068 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6069 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6070 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6071 netdev->stats.rx_bytes = bytes;
6072 netdev->stats.rx_packets = packets;
6073
6074 bytes = 0;
6075 packets = 0;
7ca3bc58 6076 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6077 for (i = 0; i < adapter->num_tx_queues; i++) {
6078 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6079 restart_queue += tx_ring->tx_stats.restart_queue;
6080 tx_busy += tx_ring->tx_stats.tx_busy;
6081 bytes += tx_ring->stats.bytes;
6082 packets += tx_ring->stats.packets;
6083 }
eb985f09 6084 adapter->restart_queue = restart_queue;
5b7da515
AD		 6085 adapter->tx_busy = tx_busy;
6086 netdev->stats.tx_bytes = bytes;
6087 netdev->stats.tx_packets = packets;
7ca3bc58 6088
7ca647bd 6089 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6090
6091 /* 8 register reads */
6f11eef7
AV		 6092 for (i = 0; i < 8; i++) {
6093 /* for packet buffers not used, the register should read 0 */
6094 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6095 missed_rx += mpc;
7ca647bd
JP		 6096 hwstats->mpc[i] += mpc;
6097 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6098 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6099 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6100 switch (hw->mac.type) {
6101 case ixgbe_mac_82598EB:
1a70db4b
ET		 6102 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6103 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6104 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6105 hwstats->pxonrxc[i] +=
6106 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6107 break;
6108 case ixgbe_mac_82599EB:
b93a2226 6109 case ixgbe_mac_X540:
9a75a1ac
DS		 6110 case ixgbe_mac_X550:
6111 case ixgbe_mac_X550EM_x:
bd508178
AD		 6112 hwstats->pxonrxc[i] +=
6113 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6114 break;
6115 default:
6116 break;
e8e26350 6117 }
6f11eef7 6118 }
1a70db4b
ET		 6119
6120 /*16 register reads */
6121 for (i = 0; i < 16; i++) {
6122 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6123 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6124 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6125 (hw->mac.type == ixgbe_mac_X540) ||
6126 (hw->mac.type == ixgbe_mac_X550) ||
6127 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6128 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6129 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6130 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6131 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6132 }
6133 }
6134
7ca647bd 6135 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6136 /* work around hardware counting issue */
7ca647bd 6137 hwstats->gprc -= missed_rx;
6f11eef7 6138
c84d324c
JF		 6139 ixgbe_update_xoff_received(adapter);
6140
6f11eef7 6141 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6142 switch (hw->mac.type) {
6143 case ixgbe_mac_82598EB:
6144 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6145 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6146 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6147 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6148 break;
b93a2226 6149 case ixgbe_mac_X540:
9a75a1ac
DS		 6150 case ixgbe_mac_X550:
6151 case ixgbe_mac_X550EM_x:
6152 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6153 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6154 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6155 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6156 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6157 case ixgbe_mac_82599EB:
a4d4f629
AD		 6158 for (i = 0; i < 16; i++)
6159 adapter->hw_rx_no_dma_resources +=
6160 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6161 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6162 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6163 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6164 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6165 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6166 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6167 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6168 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6169 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6170#ifdef IXGBE_FCOE
7ca647bd
JP		 6171 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6172 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6173 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6174 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6175 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6176 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6177 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6178 if (adapter->fcoe.ddp_pool) {
6179 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6180 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6181 unsigned int cpu;
6182 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6183 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6184 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6185 noddp += ddp_pool->noddp;
6186 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6187 }
5a1ee270
AD		 6188 hwstats->fcoe_noddp = noddp;
6189 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6190 }
6d45522c 6191#endif /* IXGBE_FCOE */
bd508178
AD		 6192 break;
6193 default:
6194 break;
e8e26350 6195 }
9a799d71 6196 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6197 hwstats->bprc += bprc;
6198 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6199 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6200 hwstats->mprc -= bprc;
6201 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6202 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6203 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6204 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6205 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6206 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6207 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6208 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6209 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6210 hwstats->lxontxc += lxon;
6f11eef7 6211 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6212 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6213 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6214 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6215 /*
6216 * 82598 errata - tx of flow control packets is included in tx counters
6217 */
6218 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6219 hwstats->gptc -= xon_off_tot;
6220 hwstats->mptc -= xon_off_tot;
6221 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6222 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6223 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6224 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6225 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6226 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6227 hwstats->ptc64 -= xon_off_tot;
6228 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6229 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6230 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6231 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6232 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6233 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6234
6235 /* Fill out the OS statistics structure */
7ca647bd 6236 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6237
6238 /* Rx Errors */
7ca647bd 6239 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6240 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6241 netdev->stats.rx_length_errors = hwstats->rlec;
6242 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6243 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6244}
6245
6246/**
d034acf1 6247 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6248 * @adapter: pointer to the device adapter structure
9a799d71 6249 **/
d034acf1 6250static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6251{
cf8280ee 6252 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6253 int i;
cf8280ee 6254
d034acf1
AD		 6255 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6256 return;
6257
6258 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6259
d034acf1 6260 /* if interface is down do nothing */
fe49f04a 6261 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6262 return;
6263
6264 /* do nothing if we are not using signature filters */
6265 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6266 return;
6267
6268 adapter->fdir_overflow++;
6269
93c52dd0
AD		 6270 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6271 for (i = 0; i < adapter->num_tx_queues; i++)
6272 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6273 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6274 /* re-enable flow director interrupts */
6275 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6276 } else {
6277 e_err(probe, "failed to finish FDIR re-initialization, "
6278 "ignored adding FDIR ATR filters\n");
6279 }
93c52dd0
AD		 6280}
6281
6282/**
6283 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6284 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6285 *
6286 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6287 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6288 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6289 * determine if a hang has occurred.
93c52dd0
AD		 6290 */
6291static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6292{
cf8280ee 6293 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6294 u64 eics = 0;
6295 int i;
cf8280ee 6296
09f40aed 6297 /* If we're down, removing or resetting, just bail */
93c52dd0 6298 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6299 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6300 test_bit(__IXGBE_RESETTING, &adapter->state))
6301 return;
22d5a71b 6302
93c52dd0
AD		 6303 /* Force detection of hung controller */
6304 if (netif_carrier_ok(adapter->netdev)) {
6305 for (i = 0; i < adapter->num_tx_queues; i++)
6306 set_check_for_tx_hang(adapter->tx_ring[i]);
6307 }
22d5a71b 6308
fe49f04a
AD		 6309 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6310 /*
6311 * for legacy and MSI interrupts don't set any bits
6312 * that are enabled for EIAM, because this operation
6313 * would set *both* EIMS and EICS for any bit in EIAM
6314 */
6315 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6316 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6317 } else {
6318 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6319 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6320 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6321 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6322 eics |= ((u64)1 << i);
6323 }
cf8280ee 6324 }
9a799d71 6325
93c52dd0 6326 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6327 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6328}
6329
e8e26350 6330/**
93c52dd0 6331 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6332 * @adapter: pointer to the device adapter structure
6333 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6334 **/
93c52dd0 6335static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6336{
e8e26350 6337 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6338 u32 link_speed = adapter->link_speed;
6339 bool link_up = adapter->link_up;
041441d0 6340 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6341
93c52dd0
AD		 6342 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6343 return;
6344
6345 if (hw->mac.ops.check_link) {
6346 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6347 } else {
93c52dd0
AD		 6348 /* always assume link is up, if no check link function */
6349 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6350 link_up = true;
c4cf55e5 6351 }
041441d0
AD		 6352
6353 if (adapter->ixgbe_ieee_pfc)
6354 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6355
3ebe8fde 6356 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6357 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6358 ixgbe_set_rx_drop_en(adapter);
6359 }
93c52dd0
AD		 6360
6361 if (link_up ||
6362 time_after(jiffies, (adapter->link_check_timeout +
6363 IXGBE_TRY_LINK_TIMEOUT))) {
6364 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6365 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6366 IXGBE_WRITE_FLUSH(hw);
6367 }
6368
6369 adapter->link_up = link_up;
6370 adapter->link_speed = link_speed;
e8e26350
PW		 6371}
6372
107d3018
AD		 6373static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6374{
6375#ifdef CONFIG_IXGBE_DCB
6376 struct net_device *netdev = adapter->netdev;
6377 struct dcb_app app = {
6378 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6379 .protocol = 0,
6380 };
6381 u8 up = 0;
6382
6383 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6384 up = dcb_ieee_getapp_mask(netdev, &app);
6385
6386 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6387#endif
6388}
6389
e8e26350 6390/**
93c52dd0
AD		 6391 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6392 * print link up message
49ce9c2c 6393 * @adapter: pointer to the device adapter structure
e8e26350 6394 **/
93c52dd0 6395static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6396{
93c52dd0 6397 struct net_device *netdev = adapter->netdev;
e8e26350 6398 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6399 struct net_device *upper;
6400 struct list_head *iter;
93c52dd0 6401 u32 link_speed = adapter->link_speed;
454adb00 6402 const char *speed_str;
93c52dd0 6403 bool flow_rx, flow_tx;
e8e26350 6404
93c52dd0
AD		 6405 /* only continue if link was previously down */
6406 if (netif_carrier_ok(netdev))
a985b6c3 6407 return;
63d6e1d8 6408
93c52dd0 6409 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6410
93c52dd0
AD		 6411 switch (hw->mac.type) {
6412 case ixgbe_mac_82598EB: {
6413 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6414 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6415 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6416 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6417 }
6418 break;
6419 case ixgbe_mac_X540:
9a75a1ac
DS		 6420 case ixgbe_mac_X550:
6421 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6422 case ixgbe_mac_82599EB: {
6423 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6424 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6425 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6426 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6427 }
6428 break;
6429 default:
6430 flow_tx = false;
6431 flow_rx = false;
6432 break;
e8e26350 6433 }
3a6a4eda 6434
6cb562d6
JK		 6435 adapter->last_rx_ptp_check = jiffies;
6436
8fecf67c 6437 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6438 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6439
454adb00
MR		 6440 switch (link_speed) {
6441 case IXGBE_LINK_SPEED_10GB_FULL:
6442 speed_str = "10 Gbps";
6443 break;
6444 case IXGBE_LINK_SPEED_2_5GB_FULL:
6445 speed_str = "2.5 Gbps";
6446 break;
6447 case IXGBE_LINK_SPEED_1GB_FULL:
6448 speed_str = "1 Gbps";
6449 break;
6450 case IXGBE_LINK_SPEED_100_FULL:
6451 speed_str = "100 Mbps";
6452 break;
6453 default:
6454 speed_str = "unknown speed";
6455 break;
6456 }
6457 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6458 ((flow_rx && flow_tx) ? "RX/TX" :
6459 (flow_rx ? "RX" :
6460 (flow_tx ? "TX" : "None"))));
e8e26350 6461
93c52dd0 6462 netif_carrier_on(netdev);
93c52dd0 6463 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6464
cdc04dcc
ET		 6465 /* enable transmits */
6466 netif_tx_wake_all_queues(adapter->netdev);
6467
6468 /* enable any upper devices */
6469 rtnl_lock();
6470 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6471 if (netif_is_macvlan(upper)) {
6472 struct macvlan_dev *vlan = netdev_priv(upper);
6473
6474 if (vlan->fwd_priv)
6475 netif_tx_wake_all_queues(upper);
6476 }
6477 }
6478 rtnl_unlock();
6479
107d3018
AD		 6480 /* update the default user priority for VFs */
6481 ixgbe_update_default_up(adapter);
6482
befa2af7
AD		 6483 /* ping all the active vfs to let them know link has changed */
6484 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6485}
6486
c4cf55e5 6487/**
93c52dd0
AD		 6488 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6489 * print link down message
49ce9c2c 6490 * @adapter: pointer to the adapter structure
c4cf55e5 6491 **/
581330ba 6492static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6493{
cf8280ee 6494 struct net_device *netdev = adapter->netdev;
c4cf55e5 6495 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6496
93c52dd0
AD		 6497 adapter->link_up = false;
6498 adapter->link_speed = 0;
cf8280ee 6499
93c52dd0
AD		 6500 /* only continue if link was up previously */
6501 if (!netif_carrier_ok(netdev))
6502 return;
264857b8 6503
93c52dd0
AD		 6504 /* poll for SFP+ cable when link is down */
6505 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6506 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6507
8fecf67c 6508 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6509 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6510
93c52dd0
AD		 6511 e_info(drv, "NIC Link is Down\n");
6512 netif_carrier_off(netdev);
befa2af7
AD		 6513
6514 /* ping all the active vfs to let them know link has changed */
6515 ixgbe_ping_all_vfs(adapter);
93c52dd0 6516}
e8e26350 6517
07923c17
ET		 6518static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6519{
6520 int i;
6521
6522 for (i = 0; i < adapter->num_tx_queues; i++) {
6523 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6524
6525 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6526 return true;
6527 }
6528
6529 return false;
6530}
6531
6532static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6533{
6534 struct ixgbe_hw *hw = &adapter->hw;
6535 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6536 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6537
6538 int i, j;
6539
6540 if (!adapter->num_vfs)
6541 return false;
6542
9a75a1ac
DS		 6543 /* resetting the PF is only needed for MAC before X550 */
6544 if (hw->mac.type >= ixgbe_mac_X550)
6545 return false;
6546
07923c17
ET		 6547 for (i = 0; i < adapter->num_vfs; i++) {
6548 for (j = 0; j < q_per_pool; j++) {
6549 u32 h, t;
6550
6551 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6552 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6553
6554 if (h != t)
6555 return true;
6556 }
6557 }
6558
6559 return false;
6560}
6561
93c52dd0
AD		 6562/**
6563 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6564 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6565 **/
6566static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6567{
93c52dd0 6568 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6569 if (ixgbe_ring_tx_pending(adapter) ||
6570 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6571 /* We've lost link, so the controller stops DMA,
6572 * but we've got queued Tx work that's never going
6573 * to get done, so reset controller to flush Tx.
6574 * (Do the reset outside of interrupt context).
6575 */
12ff3f3b 6576 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6577 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6578 }
c4cf55e5 6579 }
c4cf55e5
PWJ		 6580}
6581
9079e416
ET		 6582#ifdef CONFIG_PCI_IOV
6583static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6584 struct pci_dev *vfdev)
6585{
6586 if (!pci_wait_for_pending_transaction(vfdev))
6587 e_dev_warn("Issuing VFLR with pending transactions\n");
6588
6589 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6590 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6591
6592 msleep(100);
6593}
6594
6595static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6596{
6597 struct ixgbe_hw *hw = &adapter->hw;
6598 struct pci_dev *pdev = adapter->pdev;
6599 struct pci_dev *vfdev;
6600 u32 gpc;
6601 int pos;
6602 unsigned short vf_id;
6603
6604 if (!(netif_carrier_ok(adapter->netdev)))
6605 return;
6606
6607 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6608 if (gpc) /* If incrementing then no need for the check below */
6609 return;
6610 /* Check to see if a bad DMA write target from an errant or
6611 * malicious VF has caused a PCIe error. If so then we can
6612 * issue a VFLR to the offending VF(s) and then resume without
6613 * requesting a full slot reset.
6614 */
6615
6616 if (!pdev)
6617 return;
6618
6619 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6620 if (!pos)
6621 return;
6622
6623 /* get the device ID for the VF */
6624 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6625
6626 /* check status reg for all VFs owned by this PF */
6627 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6628 while (vfdev) {
6629 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6630 u16 status_reg;
6631
6632 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6633 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6634 /* issue VFLR */
6635 ixgbe_issue_vf_flr(adapter, vfdev);
6636 }
6637
6638 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6639 }
6640}
6641
a985b6c3
GR		 6642static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6643{
6644 u32 ssvpc;
6645
0584d999
GR		 6646 /* Do not perform spoof check for 82598 or if not in IOV mode */
6647 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6648 adapter->num_vfs == 0)
a985b6c3
GR		 6649 return;
6650
6651 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6652
6653 /*
6654 * ssvpc register is cleared on read, if zero then no
6655 * spoofed packets in the last interval.
6656 */
6657 if (!ssvpc)
6658 return;
6659
d6ea0754 6660 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6661}
9079e416
ET		 6662#else
6663static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6664{
6665}
6666
6667static void
6668ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6669{
6670}
6671#endif /* CONFIG_PCI_IOV */
6672
a985b6c3 6673
93c52dd0
AD		 6674/**
6675 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6676 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6677 **/
6678static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6679{
09f40aed 6680 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6681 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6682 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6683 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6684 return;
6685
6686 ixgbe_watchdog_update_link(adapter);
6687
6688 if (adapter->link_up)
6689 ixgbe_watchdog_link_is_up(adapter);
6690 else
6691 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6692
9079e416 6693 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6694 ixgbe_spoof_check(adapter);
9a799d71 6695 ixgbe_update_stats(adapter);
93c52dd0
AD		 6696
6697 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6698}
10eec955 6699
cf8280ee 6700/**
7086400d 6701 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6702 * @adapter: the ixgbe adapter structure
cf8280ee 6703 **/
7086400d 6704static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6705{
cf8280ee 6706 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6707 s32 err;
cf8280ee 6708
7086400d
AD		 6709 /* not searching for SFP so there is nothing to do here */
6710 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6711 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6712 return;
10eec955 6713
58e7cd24
MR		 6714 if (adapter->sfp_poll_time &&
6715 time_after(adapter->sfp_poll_time, jiffies))
6716 return; /* If not yet time to poll for SFP */
6717
7086400d
AD		 6718 /* someone else is in init, wait until next service event */
6719 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6720 return;
cf8280ee 6721
58e7cd24
MR		 6722 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6723
7086400d
AD		 6724 err = hw->phy.ops.identify_sfp(hw);
6725 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6726 goto sfp_out;
264857b8 6727
7086400d
AD		 6728 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6729 /* If no cable is present, then we need to reset
6730 * the next time we find a good cable. */
6731 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6732 }
9a799d71 6733
7086400d
AD		 6734 /* exit on error */
6735 if (err)
6736 goto sfp_out;
e8e26350 6737
7086400d
AD		 6738 /* exit if reset not needed */
6739 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6740 goto sfp_out;
9a799d71 6741
7086400d 6742 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6743
7086400d
AD		 6744 /*
6745 * A module may be identified correctly, but the EEPROM may not have
6746 * support for that module. setup_sfp() will fail in that case, so
6747 * we should not allow that module to load.
6748 */
6749 if (hw->mac.type == ixgbe_mac_82598EB)
6750 err = hw->phy.ops.reset(hw);
6751 else
6752 err = hw->mac.ops.setup_sfp(hw);
6753
6754 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6755 goto sfp_out;
6756
6757 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6758 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6759
6760sfp_out:
6761 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6762
6763 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6764 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6765 e_dev_err("failed to initialize because an unsupported "
6766 "SFP+ module type was detected.\n");
6767 e_dev_err("Reload the driver after installing a "
6768 "supported module.\n");
6769 unregister_netdev(adapter->netdev);
bc59fcda 6770 }
7086400d 6771}
bc59fcda 6772
7086400d
AD		 6773/**
6774 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6775 * @adapter: the ixgbe adapter structure
7086400d
AD		 6776 **/
6777static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6778{
6779 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6780 u32 speed;
6781 bool autoneg = false;
7086400d
AD		 6782
6783 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6784 return;
6785
6786 /* someone else is in init, wait until next service event */
6787 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6788 return;
6789
6790 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6791
3d292265 6792 speed = hw->phy.autoneg_advertised;
ed33ff66 6793 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6794 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6795
6796 /* setup the highest link when no autoneg */
6797 if (!autoneg) {
6798 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6799 speed = IXGBE_LINK_SPEED_10GB_FULL;
6800 }
6801 }
6802
7086400d 6803 if (hw->mac.ops.setup_link)
fd0326f2 6804 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6805
6806 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6807 adapter->link_check_timeout = jiffies;
6808 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6809}
6810
6811/**
6812 * ixgbe_service_timer - Timer Call-back
6813 * @data: pointer to adapter cast into an unsigned long
6814 **/
6815static void ixgbe_service_timer(unsigned long data)
6816{
6817 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6818 unsigned long next_event_offset;
6819
6bb78cfb
AD		 6820 /* poll faster when waiting for link */
6821 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6822 next_event_offset = HZ / 10;
6823 else
6824 next_event_offset = HZ * 2;
83c61fa9 6825
7086400d
AD		 6826 /* Reset the timer */
6827 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6828
9079e416 6829 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6830}
6831
597f22d6
DS		 6832static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6833{
6834 struct ixgbe_hw *hw = &adapter->hw;
6835 u32 status;
6836
6837 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6838 return;
6839
6840 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6841
6842 if (!hw->phy.ops.handle_lasi)
6843 return;
6844
6845 status = hw->phy.ops.handle_lasi(&adapter->hw);
6846 if (status != IXGBE_ERR_OVERTEMP)
6847 return;
6848
6849 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6850}
6851
c83c6cbd
AD		 6852static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6853{
6854 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6855 return;
6856
6857 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6858
09f40aed 6859 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6860 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6861 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6862 test_bit(__IXGBE_RESETTING, &adapter->state))
6863 return;
6864
6865 ixgbe_dump(adapter);
6866 netdev_err(adapter->netdev, "Reset adapter\n");
6867 adapter->tx_timeout_count++;
6868
8f4c5c9f 6869 rtnl_lock();
c83c6cbd 6870 ixgbe_reinit_locked(adapter);
8f4c5c9f 6871 rtnl_unlock();
c83c6cbd
AD		 6872}
6873
7086400d
AD		 6874/**
6875 * ixgbe_service_task - manages and runs subtasks
6876 * @work: pointer to work_struct containing our data
6877 **/
6878static void ixgbe_service_task(struct work_struct *work)
6879{
6880 struct ixgbe_adapter *adapter = container_of(work,
6881 struct ixgbe_adapter,
6882 service_task);
b0483c8f
MR		 6883 if (ixgbe_removed(adapter->hw.hw_addr)) {
6884 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6885 rtnl_lock();
6886 ixgbe_down(adapter);
6887 rtnl_unlock();
6888 }
6889 ixgbe_service_event_complete(adapter);
6890 return;
6891 }
67359c3c
MR		 6892#ifdef CONFIG_IXGBE_VXLAN
6893 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6894 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6895 vxlan_get_rx_port(adapter->netdev);
6896 }
6897#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 6898 ixgbe_reset_subtask(adapter);
597f22d6 6899 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 6900 ixgbe_sfp_detection_subtask(adapter);
6901 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6902 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6903 ixgbe_watchdog_subtask(adapter);
d034acf1 6904 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6905 ixgbe_check_hang_subtask(adapter);
891dc082 6906
8fecf67c 6907 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6908 ixgbe_ptp_overflow_check(adapter);
6909 ixgbe_ptp_rx_hang(adapter);
6910 }
7086400d
AD		 6911
6912 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6913}
6914
fd0db0ed
AD		 6915static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6916 struct ixgbe_tx_buffer *first,
244e27ad 6917 u8 *hdr_len)
897ab156 6918{
fd0db0ed 6919 struct sk_buff *skb = first->skb;
897ab156
AD		 6920 u32 vlan_macip_lens, type_tucmd;
6921 u32 mss_l4len_idx, l4len;
2049e1f6 6922 int err;
9a799d71 6923
8f4fbb9b
AD		 6924 if (skb->ip_summed != CHECKSUM_PARTIAL)
6925 return 0;
6926
897ab156
AD		 6927 if (!skb_is_gso(skb))
6928 return 0;
9a799d71 6929
2049e1f6
FR		 6930 err = skb_cow_head(skb, 0);
6931 if (err < 0)
6932 return err;
9a799d71 6933
897ab156
AD		 6934 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6935 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6936
a1108ffd 6937 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6938 struct iphdr *iph = ip_hdr(skb);
6939 iph->tot_len = 0;
6940 iph->check = 0;
6941 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6942 iph->daddr, 0,
6943 IPPROTO_TCP,
6944 0);
6945 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6946 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6947 IXGBE_TX_FLAGS_CSUM |
6948 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6949 } else if (skb_is_gso_v6(skb)) {
6950 ipv6_hdr(skb)->payload_len = 0;
6951 tcp_hdr(skb)->check =
6952 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6953 &ipv6_hdr(skb)->daddr,
6954 0, IPPROTO_TCP, 0);
244e27ad
AD		 6955 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6956 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6957 }
6958
091a6246 6959 /* compute header lengths */
897ab156
AD		 6960 l4len = tcp_hdrlen(skb);
6961 *hdr_len = skb_transport_offset(skb) + l4len;
6962
091a6246
AD		 6963 /* update gso size and bytecount with header size */
6964 first->gso_segs = skb_shinfo(skb)->gso_segs;
6965 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6966
c44f5f51 6967 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6968 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6969 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6970
6971 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6972 vlan_macip_lens = skb_network_header_len(skb);
6973 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6974 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6975
6976 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6977 mss_l4len_idx);
897ab156
AD		 6978
6979 return 1;
6980}
6981
244e27ad
AD		 6982static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6983 struct ixgbe_tx_buffer *first)
7ca647bd 6984{
fd0db0ed 6985 struct sk_buff *skb = first->skb;
897ab156
AD		 6986 u32 vlan_macip_lens = 0;
6987 u32 mss_l4len_idx = 0;
6988 u32 type_tucmd = 0;
7ca647bd 6989
897ab156 6990 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6991 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6992 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6993 return;
f467bc06
MR		 6994 vlan_macip_lens = skb_network_offset(skb) <<
6995 IXGBE_ADVTXD_MACLEN_SHIFT;
897ab156
AD		 6996 } else {
6997 u8 l4_hdr = 0;
f467bc06
MR		 6998 union {
6999 struct iphdr *ipv4;
7000 struct ipv6hdr *ipv6;
7001 u8 *raw;
7002 } network_hdr;
7003 union {
7004 struct tcphdr *tcphdr;
7005 u8 *raw;
7006 } transport_hdr;
7007
7008 if (skb->encapsulation) {
7009 network_hdr.raw = skb_inner_network_header(skb);
7010 transport_hdr.raw = skb_inner_transport_header(skb);
7011 vlan_macip_lens = skb_inner_network_offset(skb) <<
7012 IXGBE_ADVTXD_MACLEN_SHIFT;
7013 } else {
7014 network_hdr.raw = skb_network_header(skb);
7015 transport_hdr.raw = skb_transport_header(skb);
7016 vlan_macip_lens = skb_network_offset(skb) <<
7017 IXGBE_ADVTXD_MACLEN_SHIFT;
7018 }
7019
7020 /* use first 4 bits to determine IP version */
7021 switch (network_hdr.ipv4->version) {
7022 case IPVERSION:
7023 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
897ab156 7024 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
f467bc06 7025 l4_hdr = network_hdr.ipv4->protocol;
7ca647bd 7026 break;
f467bc06
MR		 7027 case 6:
7028 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7029 l4_hdr = network_hdr.ipv6->nexthdr;
897ab156
AD		 7030 break;
7031 default:
7032 if (unlikely(net_ratelimit())) {
7033 dev_warn(tx_ring->dev,
f467bc06
MR		 7034 "partial checksum but version=%d\n",
7035 network_hdr.ipv4->version);
897ab156 7036 }
7ca647bd 7037 }
897ab156
AD		 7038
7039 switch (l4_hdr) {
7ca647bd 7040 case IPPROTO_TCP:
897ab156 7041 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
f467bc06 7042 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
897ab156 7043 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 7044 break;
7045 case IPPROTO_SCTP:
897ab156
AD		 7046 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7047 mss_l4len_idx = sizeof(struct sctphdr) <<
7048 IXGBE_ADVTXD_L4LEN_SHIFT;
7049 break;
7050 case IPPROTO_UDP:
7051 mss_l4len_idx = sizeof(struct udphdr) <<
7052 IXGBE_ADVTXD_L4LEN_SHIFT;
7053 break;
7054 default:
7055 if (unlikely(net_ratelimit())) {
7056 dev_warn(tx_ring->dev,
7057 "partial checksum but l4 proto=%x!\n",
244e27ad 7058 l4_hdr);
897ab156 7059 }
7ca647bd
JP		 7060 break;
7061 }
244e27ad
AD		 7062
7063 /* update TX checksum flag */
7064 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 7065 }
7066
244e27ad 7067 /* vlan_macip_lens: MACLEN, VLAN tag */
244e27ad 7068 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7069
897ab156
AD		 7070 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7071 type_tucmd, mss_l4len_idx);
9a799d71
AK		 7072}
7073
472148c3
AD		 7074#define IXGBE_SET_FLAG(_input, _flag, _result) \
7075 ((_flag <= _result) ? \
7076 ((u32)(_input & _flag) * (_result / _flag)) : \
7077 ((u32)(_input & _flag) / (_flag / _result)))
7078
7079static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7080{
d3d00239 7081 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7082 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7083 IXGBE_ADVTXD_DCMD_DEXT |
7084 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7085
d3d00239 7086 /* set HW vlan bit if vlan is present */
472148c3
AD		 7087 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7088 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7089
d3d00239 7090 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7091 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7092 IXGBE_ADVTXD_DCMD_TSE);
7093
7094 /* set timestamp bit if present */
7095 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7096 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7097
62748b7b 7098 /* insert frame checksum */
472148c3 7099 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7100
d3d00239
AD		 7101 return cmd_type;
7102}
9a799d71 7103
729739b7
AD		 7104static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7105 u32 tx_flags, unsigned int paylen)
d3d00239 7106{
472148c3 7107 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7108
d3d00239 7109 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7110 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7111 IXGBE_TX_FLAGS_CSUM,
7112 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7113
93f5b3c1 7114 /* enble IPv4 checksum for TSO */
472148c3
AD		 7115 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7116 IXGBE_TX_FLAGS_IPV4,
7117 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7118
7f9643fd
AD		 7119 /*
7120 * Check Context must be set if Tx switch is enabled, which it
7121 * always is for case where virtual functions are running
7122 */
472148c3
AD		 7123 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7124 IXGBE_TX_FLAGS_CC,
7125 IXGBE_ADVTXD_CC);
7f9643fd 7126
472148c3 7127 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7128}
44df32c5 7129
2367a173
DB		 7130static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7131{
7132 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7133
7134 /* Herbert's original patch had:
7135 * smp_mb__after_netif_stop_queue();
7136 * but since that doesn't exist yet, just open code it.
7137 */
7138 smp_mb();
7139
7140 /* We need to check again in a case another CPU has just
7141 * made room available.
7142 */
7143 if (likely(ixgbe_desc_unused(tx_ring) < size))
7144 return -EBUSY;
7145
7146 /* A reprieve! - use start_queue because it doesn't call schedule */
7147 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7148 ++tx_ring->tx_stats.restart_queue;
7149 return 0;
7150}
7151
7152static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7153{
7154 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7155 return 0;
7156
7157 return __ixgbe_maybe_stop_tx(tx_ring, size);
7158}
7159
d3d00239
AD		 7160#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7161 IXGBE_TXD_CMD_RS)
7162
7163static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7164 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7165 const u8 hdr_len)
7166{
fd0db0ed 7167 struct sk_buff *skb = first->skb;
729739b7 7168 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7169 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7170 struct skb_frag_struct *frag;
7171 dma_addr_t dma;
7172 unsigned int data_len, size;
244e27ad 7173 u32 tx_flags = first->tx_flags;
472148c3 7174 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7175 u16 i = tx_ring->next_to_use;
d3d00239 7176
729739b7
AD		 7177 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7178
ec718254
AD		 7179 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7180
7181 size = skb_headlen(skb);
7182 data_len = skb->data_len;
729739b7 7183
d3d00239
AD		 7184#ifdef IXGBE_FCOE
7185 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7186 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7187 size -= sizeof(struct fcoe_crc_eof) - data_len;
7188 data_len = 0;
729739b7
AD		 7189 } else {
7190 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7191 }
7192 }
44df32c5 7193
d3d00239 7194#endif
729739b7 7195 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7196
ec718254 7197 tx_buffer = first;
9a799d71 7198
ec718254
AD		 7199 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7200 if (dma_mapping_error(tx_ring->dev, dma))
7201 goto dma_error;
7202
7203 /* record length, and DMA address */
7204 dma_unmap_len_set(tx_buffer, len, size);
7205 dma_unmap_addr_set(tx_buffer, dma, dma);
7206
7207 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7208
729739b7 7209 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7210 tx_desc->read.cmd_type_len =
472148c3 7211 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7212
d3d00239 7213 i++;
729739b7 7214 tx_desc++;
d3d00239 7215 if (i == tx_ring->count) {
e4f74028 7216 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7217 i = 0;
7218 }
ec718254 7219 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7220
7221 dma += IXGBE_MAX_DATA_PER_TXD;
7222 size -= IXGBE_MAX_DATA_PER_TXD;
7223
7224 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7225 }
e5a43549 7226
729739b7
AD		 7227 if (likely(!data_len))
7228 break;
9a799d71 7229
472148c3 7230 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7231
729739b7
AD		 7232 i++;
7233 tx_desc++;
7234 if (i == tx_ring->count) {
7235 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7236 i = 0;
7237 }
ec718254 7238 tx_desc->read.olinfo_status = 0;
9a799d71 7239
d3d00239 7240#ifdef IXGBE_FCOE
9e903e08 7241 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7242#else
9e903e08 7243 size = skb_frag_size(frag);
d3d00239
AD		 7244#endif
7245 data_len -= size;
9a799d71 7246
729739b7
AD		 7247 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7248 DMA_TO_DEVICE);
9a799d71 7249
729739b7 7250 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7251 }
9a799d71 7252
729739b7 7253 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7254 cmd_type |= size | IXGBE_TXD_CMD;
7255 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7256
091a6246 7257 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7258
d3d00239
AD		 7259 /* set the timestamp */
7260 first->time_stamp = jiffies;
9a799d71
AK		 7261
7262 /*
729739b7
AD		 7263 * Force memory writes to complete before letting h/w know there
7264 * are new descriptors to fetch. (Only applicable for weak-ordered
7265 * memory model archs, such as IA-64).
7266 *
7267 * We also need this memory barrier to make certain all of the
7268 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7269 */
7270 wmb();
7271
d3d00239
AD		 7272 /* set next_to_watch value indicating a packet is present */
7273 first->next_to_watch = tx_desc;
7274
729739b7
AD		 7275 i++;
7276 if (i == tx_ring->count)
7277 i = 0;
7278
7279 tx_ring->next_to_use = i;
7280
2367a173
DB		 7281 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7282
7283 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7284 writel(i, tx_ring->tail);
7285
7286 /* we need this if more than one processor can write to our tail
7287 * at a time, it synchronizes IO on IA64/Altix systems
7288 */
7289 mmiowb();
9c938cdd 7290 }
2367a173 7291
d3d00239
AD		 7292 return;
7293dma_error:
729739b7 7294 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7295
7296 /* clear dma mappings for failed tx_buffer_info map */
7297 for (;;) {
729739b7
AD		 7298 tx_buffer = &tx_ring->tx_buffer_info[i];
7299 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7300 if (tx_buffer == first)
d3d00239
AD		 7301 break;
7302 if (i == 0)
7303 i = tx_ring->count;
7304 i--;
7305 }
7306
d3d00239 7307 tx_ring->next_to_use = i;
9a799d71
AK		 7308}
7309
fd0db0ed 7310static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7311 struct ixgbe_tx_buffer *first)
69830529
AD		 7312{
7313 struct ixgbe_q_vector *q_vector = ring->q_vector;
7314 union ixgbe_atr_hash_dword input = { .dword = 0 };
7315 union ixgbe_atr_hash_dword common = { .dword = 0 };
7316 union {
7317 unsigned char *network;
7318 struct iphdr *ipv4;
7319 struct ipv6hdr *ipv6;
7320 } hdr;
ee9e0f0b 7321 struct tcphdr *th;
67359c3c
MR		 7322 struct sk_buff *skb;
7323#ifdef CONFIG_IXGBE_VXLAN
7324 u8 encap = false;
7325#endif /* CONFIG_IXGBE_VXLAN */
905e4a41 7326 __be16 vlan_id;
c4cf55e5 7327
69830529
AD		 7328 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7329 if (!q_vector)
7330 return;
7331
7332 /* do nothing if sampling is disabled */
7333 if (!ring->atr_sample_rate)
d3ead241 7334 return;
c4cf55e5 7335
69830529 7336 ring->atr_count++;
c4cf55e5 7337
69830529 7338 /* snag network header to get L4 type and address */
67359c3c
MR		 7339 skb = first->skb;
7340 hdr.network = skb_network_header(skb);
7341 if (skb->encapsulation) {
7342#ifdef CONFIG_IXGBE_VXLAN
7343 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7344
67359c3c
MR		 7345 if (!adapter->vxlan_port)
7346 return;
7347 if (first->protocol != htons(ETH_P_IP) ||
7348 hdr.ipv4->version != IPVERSION ||
7349 hdr.ipv4->protocol != IPPROTO_UDP) {
7350 return;
7351 }
7352 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7353 return;
7354 encap = true;
7355 hdr.network = skb_inner_network_header(skb);
7356 th = inner_tcp_hdr(skb);
7357#else
69830529 7358 return;
67359c3c
MR		 7359#endif /* CONFIG_IXGBE_VXLAN */
7360 } else {
7361 /* Currently only IPv4/IPv6 with TCP is supported */
7362 if ((first->protocol != htons(ETH_P_IPV6) ||
7363 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7364 (first->protocol != htons(ETH_P_IP) ||
7365 hdr.ipv4->protocol != IPPROTO_TCP))
7366 return;
7367 th = tcp_hdr(skb);
7368 }
c4cf55e5 7369
66f32a8b
AD		 7370 /* skip this packet since it is invalid or the socket is closing */
7371 if (!th || th->fin)
69830529
AD		 7372 return;
7373
7374 /* sample on all syn packets or once every atr sample count */
7375 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7376 return;
7377
7378 /* reset sample count */
7379 ring->atr_count = 0;
7380
244e27ad 7381 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7382
7383 /*
7384 * src and dst are inverted, think how the receiver sees them
7385 *
7386 * The input is broken into two sections, a non-compressed section
7387 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7388 * is XORed together and stored in the compressed dword.
7389 */
7390 input.formatted.vlan_id = vlan_id;
7391
7392 /*
7393 * since src port and flex bytes occupy the same word XOR them together
7394 * and write the value to source port portion of compressed dword
7395 */
244e27ad 7396 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7397 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7398 else
244e27ad 7399 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7400 common.port.dst ^= th->source;
7401
a1108ffd 7402 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7403 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7404 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7405 } else {
7406 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7407 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7408 hdr.ipv6->saddr.s6_addr32[1] ^
7409 hdr.ipv6->saddr.s6_addr32[2] ^
7410 hdr.ipv6->saddr.s6_addr32[3] ^
7411 hdr.ipv6->daddr.s6_addr32[0] ^
7412 hdr.ipv6->daddr.s6_addr32[1] ^
7413 hdr.ipv6->daddr.s6_addr32[2] ^
7414 hdr.ipv6->daddr.s6_addr32[3];
7415 }
c4cf55e5 7416
67359c3c
MR		 7417#ifdef CONFIG_IXGBE_VXLAN
7418 if (encap)
7419 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7420#endif /* CONFIG_IXGBE_VXLAN */
7421
c4cf55e5 7422 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7423 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7424 input, common, ring->queue_index);
c4cf55e5
PWJ		 7425}
7426
f663dd9a 7427static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7428 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7429{
f663dd9a
JW		 7430 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7431#ifdef IXGBE_FCOE
97488bd1
AD		 7432 struct ixgbe_adapter *adapter;
7433 struct ixgbe_ring_feature *f;
7434 int txq;
f663dd9a
JW		 7435#endif
7436
7437 if (fwd_adapter)
7438 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7439
7440#ifdef IXGBE_FCOE
5e09a105 7441
97488bd1
AD		 7442 /*
7443 * only execute the code below if protocol is FCoE
7444 * or FIP and we have FCoE enabled on the adapter
7445 */
7446 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7447 case htons(ETH_P_FCOE):
7448 case htons(ETH_P_FIP):
97488bd1 7449 adapter = netdev_priv(dev);
c087663e 7450
97488bd1
AD		 7451 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7452 break;
7453 default:
99932d4f 7454 return fallback(dev, skb);
97488bd1 7455 }
c087663e 7456
97488bd1 7457 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7458
97488bd1
AD		 7459 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7460 smp_processor_id();
56075a98 7461
97488bd1
AD		 7462 while (txq >= f->indices)
7463 txq -= f->indices;
c4cf55e5 7464
97488bd1 7465 return txq + f->offset;
f663dd9a 7466#else
99932d4f 7467 return fallback(dev, skb);
f663dd9a 7468#endif
09a3b1f8
SH		 7469}
7470
fc77dc3c 7471netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7472 struct ixgbe_adapter *adapter,
7473 struct ixgbe_ring *tx_ring)
9a799d71 7474{
d3d00239 7475 struct ixgbe_tx_buffer *first;
5f715823 7476 int tso;
d3d00239 7477 u32 tx_flags = 0;
a535c30e 7478 unsigned short f;
a535c30e 7479 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7480 __be16 protocol = skb->protocol;
63544e9c 7481 u8 hdr_len = 0;
5e09a105 7482
a535c30e
AD		 7483 /*
7484 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7485 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7486 * + 2 desc gap to keep tail from touching head,
7487 * + 1 desc for context descriptor,
7488 * otherwise try next time
7489 */
a535c30e
AD		 7490 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7491 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7492
a535c30e
AD		 7493 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7494 tx_ring->tx_stats.tx_busy++;
7495 return NETDEV_TX_BUSY;
7496 }
7497
fd0db0ed
AD		 7498 /* record the location of the first descriptor for this packet */
7499 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7500 first->skb = skb;
091a6246
AD		 7501 first->bytecount = skb->len;
7502 first->gso_segs = 1;
fd0db0ed 7503
66f32a8b 7504 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7505 if (skb_vlan_tag_present(skb)) {
7506 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7507 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7508 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7509 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7510 struct vlan_hdr *vhdr, _vhdr;
7511 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7512 if (!vhdr)
7513 goto out_drop;
7514
9e0c5648
AD		 7515 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7516 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7517 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7518 }
0213668f 7519 protocol = vlan_get_protocol(skb);
66f32a8b 7520
d5234933
MR		 7521 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7522 adapter->ptp_clock &&
7523 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7524 &adapter->state)) {
3a6a4eda
JK		 7525 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7526 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7527
7528 /* schedule check for Tx timestamp */
7529 adapter->ptp_tx_skb = skb_get(skb);
7530 adapter->ptp_tx_start = jiffies;
7531 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7532 }
3a6a4eda 7533
ff29a86e
JK		 7534 skb_tx_timestamp(skb);
7535
9e0c5648
AD		 7536#ifdef CONFIG_PCI_IOV
7537 /*
7538 * Use the l2switch_enable flag - would be false if the DMA
7539 * Tx switch had been disabled.
7540 */
7541 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7542 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7543
7544#endif
32701dc2 7545 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7546 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7547 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7548 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7549 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7550 tx_flags |= (skb->priority & 0x7) <<
7551 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7552 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7553 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7554
7555 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7556 goto out_drop;
7557 vhdr = (struct vlan_ethhdr *)skb->data;
7558 vhdr->h_vlan_TCI = htons(tx_flags >>
7559 IXGBE_TX_FLAGS_VLAN_SHIFT);
7560 } else {
7561 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7562 }
9a799d71 7563 }
eacd73f7 7564
244e27ad
AD		 7565 /* record initial flags and protocol */
7566 first->tx_flags = tx_flags;
7567 first->protocol = protocol;
7568
eacd73f7 7569#ifdef IXGBE_FCOE
66f32a8b 7570 /* setup tx offload for FCoE */
a1108ffd 7571 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7572 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7573 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7574 if (tso < 0)
7575 goto out_drop;
9a799d71 7576
66f32a8b 7577 goto xmit_fcoe;
eacd73f7 7578 }
9a799d71 7579
66f32a8b 7580#endif /* IXGBE_FCOE */
244e27ad 7581 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7582 if (tso < 0)
897ab156 7583 goto out_drop;
244e27ad
AD		 7584 else if (!tso)
7585 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7586
7587 /* add the ATR filter if ATR is on */
7588 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7589 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7590
7591#ifdef IXGBE_FCOE
7592xmit_fcoe:
7593#endif /* IXGBE_FCOE */
244e27ad 7594 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7595
9a799d71 7596 return NETDEV_TX_OK;
897ab156
AD		 7597
7598out_drop:
fd0db0ed
AD		 7599 dev_kfree_skb_any(first->skb);
7600 first->skb = NULL;
7601
897ab156 7602 return NETDEV_TX_OK;
9a799d71
AK		 7603}
7604
2a47fa45
JF		 7605static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7606 struct net_device *netdev,
7607 struct ixgbe_ring *ring)
84418e3b
AD		 7608{
7609 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7610 struct ixgbe_ring *tx_ring;
7611
a50c29dd
AD		 7612 /*
7613 * The minimum packet size for olinfo paylen is 17 so pad the skb
7614 * in order to meet this minimum size requirement.
7615 */
a94d9e22
AD		 7616 if (skb_put_padto(skb, 17))
7617 return NETDEV_TX_OK;
a50c29dd 7618
2a47fa45
JF		 7619 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7620
fc77dc3c 7621 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7622}
7623
2a47fa45
JF		 7624static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7625 struct net_device *netdev)
7626{
7627 return __ixgbe_xmit_frame(skb, netdev, NULL);
7628}
7629
9a799d71
AK		 7630/**
7631 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7632 * @netdev: network interface device structure
7633 * @p: pointer to an address structure
7634 *
7635 * Returns 0 on success, negative on failure
7636 **/
7637static int ixgbe_set_mac(struct net_device *netdev, void *p)
7638{
7639 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7640 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7641 struct sockaddr *addr = p;
5d7daa35 7642 int ret;
9a799d71
AK		 7643
7644 if (!is_valid_ether_addr(addr->sa_data))
7645 return -EADDRNOTAVAIL;
7646
5d7daa35 7647 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7648 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7649 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7650
5d7daa35
JK		 7651 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7652 return ret > 0 ? 0 : ret;
9a799d71
AK		 7653}
7654
6b73e10d
BH		 7655static int
7656ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7657{
7658 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7659 struct ixgbe_hw *hw = &adapter->hw;
7660 u16 value;
7661 int rc;
7662
7663 if (prtad != hw->phy.mdio.prtad)
7664 return -EINVAL;
7665 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7666 if (!rc)
7667 rc = value;
7668 return rc;
7669}
7670
7671static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7672 u16 addr, u16 value)
7673{
7674 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7675 struct ixgbe_hw *hw = &adapter->hw;
7676
7677 if (prtad != hw->phy.mdio.prtad)
7678 return -EINVAL;
7679 return hw->phy.ops.write_reg(hw, addr, devad, value);
7680}
7681
7682static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7683{
7684 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7685
3a6a4eda 7686 switch (cmd) {
3a6a4eda 7687 case SIOCSHWTSTAMP:
93501d48
JK		 7688 return ixgbe_ptp_set_ts_config(adapter, req);
7689 case SIOCGHWTSTAMP:
7690 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7691 default:
7692 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7693 }
6b73e10d
BH		 7694}
7695
0365e6e4
PW		 7696/**
7697 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7698 * netdev->dev_addrs
0365e6e4
PW		 7699 * @netdev: network interface device structure
7700 *
7701 * Returns non-zero on failure
7702 **/
7703static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7704{
7705 int err = 0;
7706 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7707 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7708
7fa7c9dc 7709 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7710 rtnl_lock();
7fa7c9dc 7711 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7712 rtnl_unlock();
7fa7c9dc
AD		 7713
7714 /* update SAN MAC vmdq pool selection */
7715 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7716 }
7717 return err;
7718}
7719
7720/**
7721 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7722 * netdev->dev_addrs
0365e6e4
PW		 7723 * @netdev: network interface device structure
7724 *
7725 * Returns non-zero on failure
7726 **/
7727static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7728{
7729 int err = 0;
7730 struct ixgbe_adapter *adapter = netdev_priv(dev);
7731 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7732
7733 if (is_valid_ether_addr(mac->san_addr)) {
7734 rtnl_lock();
7735 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7736 rtnl_unlock();
7737 }
7738 return err;
7739}
7740
9a799d71
AK		 7741#ifdef CONFIG_NET_POLL_CONTROLLER
7742/*
7743 * Polling 'interrupt' - used by things like netconsole to send skbs
7744 * without having to re-enable interrupts. It's not called while
7745 * the interrupt routine is executing.
7746 */
7747static void ixgbe_netpoll(struct net_device *netdev)
7748{
7749 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7750 int i;
9a799d71 7751
1a647bd2
AD		 7752 /* if interface is down do nothing */
7753 if (test_bit(__IXGBE_DOWN, &adapter->state))
7754 return;
7755
856f606e
AD		 7756 /* loop through and schedule all active queues */
7757 for (i = 0; i < adapter->num_q_vectors; i++)
7758 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 7759}
9a799d71 7760
581330ba 7761#endif
de1036b1
ED		 7762static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7763 struct rtnl_link_stats64 *stats)
7764{
7765 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7766 int i;
7767
1a51502b 7768 rcu_read_lock();
de1036b1 7769 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7770 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7771 u64 bytes, packets;
7772 unsigned int start;
7773
1a51502b
ED		 7774 if (ring) {
7775 do {
57a7744e 7776 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7777 packets = ring->stats.packets;
7778 bytes = ring->stats.bytes;
57a7744e 7779 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7780 stats->rx_packets += packets;
7781 stats->rx_bytes += bytes;
7782 }
de1036b1 7783 }
1ac9ad13
ED		 7784
7785 for (i = 0; i < adapter->num_tx_queues; i++) {
7786 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7787 u64 bytes, packets;
7788 unsigned int start;
7789
7790 if (ring) {
7791 do {
57a7744e 7792 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7793 packets = ring->stats.packets;
7794 bytes = ring->stats.bytes;
57a7744e 7795 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7796 stats->tx_packets += packets;
7797 stats->tx_bytes += bytes;
7798 }
7799 }
1a51502b 7800 rcu_read_unlock();
de1036b1
ED		 7801 /* following stats updated by ixgbe_watchdog_task() */
7802 stats->multicast = netdev->stats.multicast;
7803 stats->rx_errors = netdev->stats.rx_errors;
7804 stats->rx_length_errors = netdev->stats.rx_length_errors;
7805 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7806 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7807 return stats;
7808}
7809
8af3c33f 7810#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7811/**
7812 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7813 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7814 * @tc: number of traffic classes currently enabled
7815 *
7816 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7817 * 802.1Q priority maps to a packet buffer that exists.
7818 */
7819static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7820{
7821 struct ixgbe_hw *hw = &adapter->hw;
7822 u32 reg, rsave;
7823 int i;
7824
7825 /* 82598 have a static priority to TC mapping that can not
7826 * be changed so no validation is needed.
7827 */
7828 if (hw->mac.type == ixgbe_mac_82598EB)
7829 return;
7830
7831 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7832 rsave = reg;
7833
7834 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7835 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7836
7837 /* If up2tc is out of bounds default to zero */
7838 if (up2tc > tc)
7839 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7840 }
7841
7842 if (reg != rsave)
7843 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7844
7845 return;
7846}
7847
02debdc9
AD		 7848/**
7849 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7850 * @adapter: Pointer to adapter struct
7851 *
7852 * Populate the netdev user priority to tc map
7853 */
7854static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7855{
7856 struct net_device *dev = adapter->netdev;
7857 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7858 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7859 u8 prio;
7860
7861 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7862 u8 tc = 0;
7863
7864 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7865 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7866 else if (ets)
7867 tc = ets->prio_tc[prio];
7868
7869 netdev_set_prio_tc_map(dev, prio, tc);
7870 }
7871}
7872
cca73c59 7873#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7874/**
7875 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7876 *
7877 * @netdev: net device to configure
7878 * @tc: number of traffic classes to enable
7879 */
7880int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7881{
8b1c0b24
JF		 7882 struct ixgbe_adapter *adapter = netdev_priv(dev);
7883 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7884 bool pools;
8b1c0b24 7885
8b1c0b24 7886 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 7887 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
7888 return -EINVAL;
7889
7890 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 7891 return -EINVAL;
7892
2a47fa45
JF		 7893 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7894 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7895 return -EBUSY;
7896
8b1c0b24 7897 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7898 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7899 * hardware is not flexible enough to do this dynamically.
7900 */
7901 if (netif_running(dev))
7902 ixgbe_close(dev);
7903 ixgbe_clear_interrupt_scheme(adapter);
7904
cca73c59 7905#ifdef CONFIG_IXGBE_DCB
e7589eab 7906 if (tc) {
8b1c0b24 7907 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7908 ixgbe_set_prio_tc_map(adapter);
7909
e7589eab 7910 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7911
943561d3
AD		 7912 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7913 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7914 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7915 }
e7589eab 7916 } else {
8b1c0b24 7917 netdev_reset_tc(dev);
02debdc9 7918
943561d3
AD		 7919 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7920 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7921
7922 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7923
7924 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7925 adapter->dcb_cfg.pfc_mode_enable = false;
7926 }
7927
8b1c0b24 7928 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7929
7930#endif /* CONFIG_IXGBE_DCB */
7931 ixgbe_init_interrupt_scheme(adapter);
7932
8b1c0b24 7933 if (netif_running(dev))
cca73c59 7934 return ixgbe_open(dev);
8b1c0b24
JF		 7935
7936 return 0;
7937}
de1036b1 7938
da36b647
GR		 7939#ifdef CONFIG_PCI_IOV
7940void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7941{
7942 struct net_device *netdev = adapter->netdev;
7943
7944 rtnl_lock();
da36b647 7945 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7946 rtnl_unlock();
7947}
7948
7949#endif
082757af
DS		 7950void ixgbe_do_reset(struct net_device *netdev)
7951{
7952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7953
7954 if (netif_running(netdev))
7955 ixgbe_reinit_locked(adapter);
7956 else
7957 ixgbe_reset(adapter);
7958}
7959
c8f44aff 7960static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7961 netdev_features_t features)
082757af
DS		 7962{
7963 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7964
082757af 7965 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7966 if (!(features & NETIF_F_RXCSUM))
7967 features &= ~NETIF_F_LRO;
082757af 7968
567d2de2
AD		 7969 /* Turn off LRO if not RSC capable */
7970 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7971 features &= ~NETIF_F_LRO;
8e2813f5 7972
567d2de2 7973 return features;
082757af
DS		 7974}
7975
c8f44aff 7976static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7977 netdev_features_t features)
082757af
DS		 7978{
7979 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7980 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7981 bool need_reset = false;
7982
082757af 7983 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7984 if (!(features & NETIF_F_LRO)) {
7985 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7986 need_reset = true;
567d2de2
AD		 7987 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7988 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7989 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7990 if (adapter->rx_itr_setting == 1 ||
7991 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7992 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7993 need_reset = true;
7994 } else if ((changed ^ features) & NETIF_F_LRO) {
7995 e_info(probe, "rx-usecs set too low, "
7996 "disabling RSC\n");
082757af
DS		 7997 }
7998 }
7999
8000 /*
8001 * Check if Flow Director n-tuple support was enabled or disabled. If
8002 * the state changed, we need to reset.
8003 */
39cb681b
AD		 8004 switch (features & NETIF_F_NTUPLE) {
8005 case NETIF_F_NTUPLE:
567d2de2 8006 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8007 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8008 need_reset = true;
8009
567d2de2
AD		 8010 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8011 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 8012 break;
8013 default:
8014 /* turn off perfect filters, enable ATR and reset */
8015 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8016 need_reset = true;
8017
8018 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8019
8020 /* We cannot enable ATR if SR-IOV is enabled */
8021 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8022 break;
8023
8024 /* We cannot enable ATR if we have 2 or more traffic classes */
8025 if (netdev_get_num_tc(netdev) > 1)
8026 break;
8027
8028 /* We cannot enable ATR if RSS is disabled */
8029 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8030 break;
8031
8032 /* A sample rate of 0 indicates ATR disabled */
8033 if (!adapter->atr_sample_rate)
8034 break;
8035
8036 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8037 break;
082757af
DS		 8038 }
8039
f646968f 8040 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 8041 ixgbe_vlan_strip_enable(adapter);
8042 else
8043 ixgbe_vlan_strip_disable(adapter);
8044
3f2d1c0f
BG		 8045 if (changed & NETIF_F_RXALL)
8046 need_reset = true;
8047
567d2de2 8048 netdev->features = features;
67359c3c
MR		 8049
8050#ifdef CONFIG_IXGBE_VXLAN
8051 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8052 if (features & NETIF_F_RXCSUM)
8053 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8054 else
8055 ixgbe_clear_vxlan_port(adapter);
8056 }
8057#endif /* CONFIG_IXGBE_VXLAN */
8058
082757af
DS		 8059 if (need_reset)
8060 ixgbe_do_reset(netdev);
8061
8062 return 0;
082757af
DS		 8063}
8064
67359c3c 8065#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8066/**
8067 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8068 * @dev: The port's netdev
8069 * @sa_family: Socket Family that VXLAN is notifiying us about
8070 * @port: New UDP port number that VXLAN started listening to
8071 **/
8072static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8073 __be16 port)
8074{
8075 struct ixgbe_adapter *adapter = netdev_priv(dev);
8076 struct ixgbe_hw *hw = &adapter->hw;
8077 u16 new_port = ntohs(port);
8078
67359c3c
MR		 8079 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8080 return;
8081
3f207800
DS		 8082 if (sa_family == AF_INET6)
8083 return;
8084
67359c3c 8085 if (adapter->vxlan_port == new_port)
3f207800 8086 return;
3f207800
DS		 8087
8088 if (adapter->vxlan_port) {
8089 netdev_info(dev,
67359c3c 8090 "Hit Max num of VXLAN ports, not adding port %d\n",
3f207800
DS		 8091 new_port);
8092 return;
8093 }
8094
8095 adapter->vxlan_port = new_port;
8096 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8097}
8098
8099/**
8100 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8101 * @dev: The port's netdev
8102 * @sa_family: Socket Family that VXLAN is notifying us about
8103 * @port: UDP port number that VXLAN stopped listening to
8104 **/
8105static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8106 __be16 port)
8107{
8108 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800
DS		 8109 u16 new_port = ntohs(port);
8110
67359c3c
MR		 8111 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8112 return;
8113
3f207800
DS		 8114 if (sa_family == AF_INET6)
8115 return;
8116
8117 if (adapter->vxlan_port != new_port) {
8118 netdev_info(dev, "Port %d was not found, not deleting\n",
8119 new_port);
8120 return;
8121 }
8122
67359c3c
MR		 8123 ixgbe_clear_vxlan_port(adapter);
8124 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8125}
67359c3c 8126#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8127
edc7d573 8128static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8129 struct net_device *dev,
f6f6424b 8130 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8131 u16 flags)
8132{
bcfd3432 8133 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8134 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 8135 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
8136 return -ENOMEM;
0f4b0add
JF		 8137 }
8138
f6f6424b 8139 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8140}
8141
219efe97
DS		 8142/**
8143 * ixgbe_configure_bridge_mode - set various bridge modes
8144 * @adapter - the private structure
8145 * @mode - requested bridge mode
8146 *
8147 * Configure some settings require for various bridge modes.
8148 **/
8149static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8150 __u16 mode)
8151{
6d4c96ad
DS		 8152 struct ixgbe_hw *hw = &adapter->hw;
8153 unsigned int p, num_pools;
8154 u32 vmdctl;
8155
219efe97
DS		 8156 switch (mode) {
8157 case BRIDGE_MODE_VEPA:
6d4c96ad 8158 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8159 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8160
8161 /* must enable Rx switching replication to allow multicast
8162 * packet reception on all VFs, and to enable source address
8163 * pruning.
8164 */
8165 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8166 vmdctl |= IXGBE_VT_CTL_REPLEN;
8167 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8168
8169 /* enable Rx source address pruning. Note, this requires
8170 * replication to be enabled or else it does nothing.
8171 */
8172 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8173 for (p = 0; p < num_pools; p++) {
8174 if (hw->mac.ops.set_source_address_pruning)
8175 hw->mac.ops.set_source_address_pruning(hw,
8176 true,
8177 p);
8178 }
219efe97
DS		 8179 break;
8180 case BRIDGE_MODE_VEB:
6d4c96ad 8181 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8183 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8184
8185 /* disable Rx switching replication unless we have SR-IOV
8186 * virtual functions
8187 */
8188 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8189 if (!adapter->num_vfs)
8190 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8191 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8192
8193 /* disable Rx source address pruning, since we don't expect to
8194 * be receiving external loopback of our transmitted frames.
8195 */
8196 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8197 for (p = 0; p < num_pools; p++) {
8198 if (hw->mac.ops.set_source_address_pruning)
8199 hw->mac.ops.set_source_address_pruning(hw,
8200 false,
8201 p);
8202 }
219efe97
DS		 8203 break;
8204 default:
8205 return -EINVAL;
8206 }
8207
8208 adapter->bridge_mode = mode;
8209
8210 e_info(drv, "enabling bridge mode: %s\n",
8211 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8212
8213 return 0;
8214}
8215
815cccbf 8216static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8217 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8218{
8219 struct ixgbe_adapter *adapter = netdev_priv(dev);
8220 struct nlattr *attr, *br_spec;
8221 int rem;
8222
8223 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8224 return -EOPNOTSUPP;
8225
8226 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8227 if (!br_spec)
8228 return -EINVAL;
815cccbf
JF		 8229
8230 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8231 int status;
815cccbf 8232 __u16 mode;
815cccbf
JF		 8233
8234 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8235 continue;
8236
b7c1a314
TG		 8237 if (nla_len(attr) < sizeof(mode))
8238 return -EINVAL;
8239
815cccbf 8240 mode = nla_get_u16(attr);
219efe97
DS		 8241 status = ixgbe_configure_bridge_mode(adapter, mode);
8242 if (status)
8243 return status;
aa2bacb6
DS		 8244
8245 break;
815cccbf
JF		 8246 }
8247
8248 return 0;
8249}
8250
8251static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8252 struct net_device *dev,
46c264da 8253 u32 filter_mask, int nlflags)
815cccbf
JF		 8254{
8255 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8256
8257 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8258 return 0;
8259
aa2bacb6 8260 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8261 adapter->bridge_mode, 0, 0, nlflags,
8262 filter_mask, NULL);
815cccbf
JF		 8263}
8264
2a47fa45
JF		 8265static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8266{
8267 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8268 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8269 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8270 unsigned int limit;
2a47fa45
JF		 8271 int pool, err;
8272
aac2f1bf
JK		 8273 /* Hardware has a limited number of available pools. Each VF, and the
8274 * PF require a pool. Check to ensure we don't attempt to use more
8275 * then the available number of pools.
8276 */
8277 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8278 return ERR_PTR(-EINVAL);
8279
219354d4
JF		 8280#ifdef CONFIG_RPS
8281 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8282 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8283 vdev->name);
8284 return ERR_PTR(-EINVAL);
8285 }
8286#endif
2a47fa45 8287 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8288 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8289 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8290 netdev_info(pdev,
8291 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8292 pdev->name);
8293 return ERR_PTR(-EINVAL);
8294 }
8295
8296 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8297 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8298 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8299 return ERR_PTR(-EBUSY);
8300
bc52f951 8301 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8302 if (!fwd_adapter)
8303 return ERR_PTR(-ENOMEM);
8304
8305 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8306 adapter->num_rx_pools++;
8307 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8308 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8309
8310 /* Enable VMDq flag so device will be set in VM mode */
8311 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8312 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8313 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8314
8315 /* Force reinit of ring allocation with VMDQ enabled */
8316 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8317 if (err)
8318 goto fwd_add_err;
8319 fwd_adapter->pool = pool;
8320 fwd_adapter->real_adapter = adapter;
8321 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8322 if (err)
8323 goto fwd_add_err;
8324 netif_tx_start_all_queues(vdev);
8325 return fwd_adapter;
8326fwd_add_err:
8327 /* unwind counter and free adapter struct */
8328 netdev_info(pdev,
8329 "%s: dfwd hardware acceleration failed\n", vdev->name);
8330 clear_bit(pool, &adapter->fwd_bitmask);
8331 adapter->num_rx_pools--;
8332 kfree(fwd_adapter);
8333 return ERR_PTR(err);
8334}
8335
8336static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8337{
8338 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8339 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8340 unsigned int limit;
2a47fa45
JF		 8341
8342 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8343 adapter->num_rx_pools--;
8344
51f3773b
JF		 8345 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8346 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8347 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8348 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8349 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8350 fwd_adapter->pool, adapter->num_rx_pools,
8351 fwd_adapter->rx_base_queue,
8352 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8353 adapter->fwd_bitmask);
8354 kfree(fwd_adapter);
8355}
8356
f467bc06
MR		 8357#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8358static netdev_features_t
8359ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8360 netdev_features_t features)
8361{
8362 if (!skb->encapsulation)
8363 return features;
8364
8365 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8366 IXGBE_MAX_TUNNEL_HDR_LEN))
8367 return features & ~NETIF_F_ALL_CSUM;
8368
8369 return features;
8370}
8371
0edc3527 8372static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8373 .ndo_open = ixgbe_open,
0edc3527 8374 .ndo_stop = ixgbe_close,
00829823 8375 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8376 .ndo_select_queue = ixgbe_select_queue,
581330ba 8377 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8378 .ndo_validate_addr = eth_validate_addr,
8379 .ndo_set_mac_address = ixgbe_set_mac,
8380 .ndo_change_mtu = ixgbe_change_mtu,
8381 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8382 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8383 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8384 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8385 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8386 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8387 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8388 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8389 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
7f01648a 8390 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8391 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8392#ifdef CONFIG_IXGBE_DCB
24095aa3 8393 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8394#endif
0edc3527
SH		 8395#ifdef CONFIG_NET_POLL_CONTROLLER
8396 .ndo_poll_controller = ixgbe_netpoll,
8397#endif
e0d1095a 8398#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8399 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8400#endif
332d4a7d
YZ		 8401#ifdef IXGBE_FCOE
8402 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8403 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8404 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8405 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8406 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8407 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8408 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8409#endif /* IXGBE_FCOE */
082757af
DS		 8410 .ndo_set_features = ixgbe_set_features,
8411 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8412 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8413 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8414 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8415 .ndo_dfwd_add_station = ixgbe_fwd_add,
8416 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8417#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8418 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8419 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8420#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8421 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8422};
8423
e027d1ae
JK		 8424/**
8425 * ixgbe_enumerate_functions - Get the number of ports this device has
8426 * @adapter: adapter structure
8427 *
8428 * This function enumerates the phsyical functions co-located on a single slot,
8429 * in order to determine how many ports a device has. This is most useful in
8430 * determining the required GT/s of PCIe bandwidth necessary for optimal
8431 * performance.
8432 **/
8433static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8434{
caafb95d 8435 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8436 int physfns = 0;
8437
f1f96579
JK		 8438 /* Some cards can not use the generic count PCIe functions method,
8439 * because they are behind a parent switch, so we hardcode these with
8440 * the correct number of functions.
e027d1ae 8441 */
8818970d 8442 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8443 physfns = 4;
8818970d
JK		 8444
8445 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8446 /* don't count virtual functions */
caafb95d
JK		 8447 if (entry->is_virtfn)
8448 continue;
8449
8450 /* When the devices on the bus don't all match our device ID,
8451 * we can't reliably determine the correct number of
8452 * functions. This can occur if a function has been direct
8453 * attached to a virtual machine using VT-d, for example. In
8454 * this case, simply return -1 to indicate this.
8455 */
8456 if ((entry->vendor != pdev->vendor) ||
8457 (entry->device != pdev->device))
8458 return -1;
8459
8460 physfns++;
e027d1ae
JK		 8461 }
8462
8463 return physfns;
8464}
8465
8e2813f5
JK		 8466/**
8467 * ixgbe_wol_supported - Check whether device supports WoL
8468 * @hw: hw specific details
8469 * @device_id: the device ID
8470 * @subdev_id: the subsystem device ID
8471 *
8472 * This function is used by probe and ethtool to determine
8473 * which devices have WoL support
8474 *
8475 **/
8476int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8477 u16 subdevice_id)
8478{
8479 struct ixgbe_hw *hw = &adapter->hw;
8480 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8481 int is_wol_supported = 0;
8482
8483 switch (device_id) {
8484 case IXGBE_DEV_ID_82599_SFP:
8485 /* Only these subdevices could supports WOL */
8486 switch (subdevice_id) {
87557440 8487 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8488 case IXGBE_SUBDEV_ID_82599_560FLR:
8489 /* only support first port */
8490 if (hw->bus.func != 0)
8491 break;
5700ff26 8492 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8493 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8494 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8495 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8496 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8497 is_wol_supported = 1;
8498 break;
8499 }
8500 break;
5daebbb0
DS		 8501 case IXGBE_DEV_ID_82599EN_SFP:
8502 /* Only this subdevice supports WOL */
8503 switch (subdevice_id) {
8504 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8505 is_wol_supported = 1;
8506 break;
8507 }
8508 break;
8e2813f5
JK		 8509 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8510 /* All except this subdevice support WOL */
8511 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8512 is_wol_supported = 1;
8513 break;
8514 case IXGBE_DEV_ID_82599_KX4:
8515 is_wol_supported = 1;
8516 break;
8517 case IXGBE_DEV_ID_X540T:
df376f0d 8518 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8519 case IXGBE_DEV_ID_X550T:
8520 case IXGBE_DEV_ID_X550EM_X_KX4:
8521 case IXGBE_DEV_ID_X550EM_X_KR:
8522 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8523 /* check eeprom to see if enabled wol */
8524 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8525 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8526 (hw->bus.func == 0))) {
8527 is_wol_supported = 1;
8528 }
8529 break;
8530 }
8531
8532 return is_wol_supported;
8533}
8534
c762dff2
MP		 8535/**
8536 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8537 * @adapter: Pointer to adapter struct
8538 */
8539static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8540{
8541#ifdef CONFIG_OF
8542 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8543 struct ixgbe_hw *hw = &adapter->hw;
8544 const unsigned char *addr;
8545
8546 addr = of_get_mac_address(dp);
8547 if (addr) {
8548 ether_addr_copy(hw->mac.perm_addr, addr);
8549 return;
8550 }
8551#endif /* CONFIG_OF */
8552
8553#ifdef CONFIG_SPARC
8554 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8555#endif /* CONFIG_SPARC */
8556}
8557
9a799d71
AK		 8558/**
8559 * ixgbe_probe - Device Initialization Routine
8560 * @pdev: PCI device information struct
8561 * @ent: entry in ixgbe_pci_tbl
8562 *
8563 * Returns 0 on success, negative on failure
8564 *
8565 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8566 * The OS initialization, configuring of the adapter private structure,
8567 * and a hardware reset occur.
8568 **/
1dd06ae8 8569static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8570{
8571 struct net_device *netdev;
8572 struct ixgbe_adapter *adapter = NULL;
8573 struct ixgbe_hw *hw;
8574 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8575 int i, err, pci_using_dac, expected_gts;
d3cb9869 8576 unsigned int indices = MAX_TX_QUEUES;
289700db 8577 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8578 bool disable_dev = false;
eacd73f7
YZ		 8579#ifdef IXGBE_FCOE
8580 u16 device_caps;
8581#endif
289700db 8582 u32 eec;
9a799d71 8583
bded64a7
AG		 8584 /* Catch broken hardware that put the wrong VF device ID in
8585 * the PCIe SR-IOV capability.
8586 */
8587 if (pdev->is_virtfn) {
8588 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8589 pci_name(pdev), pdev->vendor, pdev->device);
8590 return -EINVAL;
8591 }
8592
9ce77666 8593 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8594 if (err)
8595 return err;
8596
f5f2eda8 8597 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8598 pci_using_dac = 1;
8599 } else {
f5f2eda8 8600 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8601 if (err) {
f5f2eda8
RK		 8602 dev_err(&pdev->dev,
8603 "No usable DMA configuration, aborting\n");
8604 goto err_dma;
9a799d71
AK		 8605 }
8606 pci_using_dac = 0;
8607 }
8608
9ce77666 8609 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8610 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8611 if (err) {
b8bc0421
DC		 8612 dev_err(&pdev->dev,
8613 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8614 goto err_pci_reg;
8615 }
8616
19d5afd4 8617 pci_enable_pcie_error_reporting(pdev);
6fabd715 8618
9a799d71 8619 pci_set_master(pdev);
fb3b27bc 8620 pci_save_state(pdev);
9a799d71 8621
d3cb9869 8622 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8623#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8624 /* 8 TC w/ 4 queues per TC */
8625 indices = 4 * MAX_TRAFFIC_CLASS;
8626#else
8627 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8628#endif
d3cb9869 8629 }
e901acd6 8630
c85a2618 8631 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8632 if (!netdev) {
8633 err = -ENOMEM;
8634 goto err_alloc_etherdev;
8635 }
8636
9a799d71
AK		 8637 SET_NETDEV_DEV(netdev, &pdev->dev);
8638
9a799d71
AK		 8639 adapter = netdev_priv(netdev);
8640
8641 adapter->netdev = netdev;
8642 adapter->pdev = pdev;
8643 hw = &adapter->hw;
8644 hw->back = adapter;
b3f4d599 8645 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8646
05857980 8647 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8648 pci_resource_len(pdev, 0));
2a1a091c 8649 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8650 if (!hw->hw_addr) {
8651 err = -EIO;
8652 goto err_ioremap;
8653 }
8654
0edc3527 8655 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8656 ixgbe_set_ethtool_ops(netdev);
9a799d71 8657 netdev->watchdog_timeo = 5 * HZ;
339de30f 8658 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8659
9a799d71
AK		 8660 /* Setup hw api */
8661 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8662 hw->mac.type = ii->mac;
9a900eca 8663 hw->mvals = ii->mvals;
9a799d71 8664
c44ade9e
JB		 8665 /* EEPROM */
8666 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 8667 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 8668 if (ixgbe_removed(hw->hw_addr)) {
8669 err = -EIO;
8670 goto err_ioremap;
8671 }
c44ade9e
JB		 8672 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8673 if (!(eec & (1 << 8)))
8674 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8675
8676 /* PHY */
8677 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8678 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8679 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8680 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8681 hw->phy.mdio.mmds = 0;
8682 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8683 hw->phy.mdio.dev = netdev;
8684 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8685 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8686
8ca783ab 8687 ii->get_invariants(hw);
9a799d71
AK		 8688
8689 /* setup the private structure */
8690 err = ixgbe_sw_init(adapter);
8691 if (err)
8692 goto err_sw_init;
8693
e86bff0e 8694 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8695 switch (adapter->hw.mac.type) {
8696 case ixgbe_mac_82599EB:
8697 case ixgbe_mac_X540:
9a75a1ac
DS		 8698 case ixgbe_mac_X550:
8699 case ixgbe_mac_X550EM_x:
e86bff0e 8700 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8701 break;
8702 default:
8703 break;
8704 }
e86bff0e 8705
bf069c97
DS		 8706 /*
8707 * If there is a fan on this device and it has failed log the
8708 * failure.
8709 */
8710 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8711 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8712 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8713 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8714 }
8715
8ef78adc
PWJ		 8716 if (allow_unsupported_sfp)
8717 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8718
c44ade9e 8719 /* reset_hw fills in the perm_addr as well */
119fc60a 8720 hw->phy.reset_if_overtemp = true;
c44ade9e 8721 err = hw->mac.ops.reset_hw(hw);
119fc60a 8722 hw->phy.reset_if_overtemp = false;
29a8dca1 8723 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 8724 err = 0;
8725 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8726 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8727 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8728 goto err_sw_init;
8729 } else if (err) {
849c4542 8730 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8731 goto err_sw_init;
8732 }
8733
99d74487 8734#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8735 /* SR-IOV not supported on the 82598 */
8736 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8737 goto skip_sriov;
8738 /* Mailbox */
8739 ixgbe_init_mbx_params_pf(hw);
8740 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8741 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8742 ixgbe_enable_sriov(adapter);
60a1a680 8743skip_sriov:
1cdd1ec8 8744
99d74487 8745#endif
396e799c 8746 netdev->features = NETIF_F_SG |
e8e9f696 8747 NETIF_F_IP_CSUM |
082757af 8748 NETIF_F_IPV6_CSUM |
f646968f
PM		 8749 NETIF_F_HW_VLAN_CTAG_TX |
8750 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 8751 NETIF_F_TSO |
8752 NETIF_F_TSO6 |
082757af 8753 NETIF_F_RXHASH |
8bf1264d 8754 NETIF_F_RXCSUM;
9a799d71 8755
8bf1264d 8756 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8757
58be7666
DS		 8758 switch (adapter->hw.mac.type) {
8759 case ixgbe_mac_82599EB:
8760 case ixgbe_mac_X540:
9a75a1ac
DS		 8761 case ixgbe_mac_X550:
8762 case ixgbe_mac_X550EM_x:
45a5ead0 8763 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8764 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8765 NETIF_F_NTUPLE;
58be7666
DS		 8766 break;
8767 default:
8768 break;
8769 }
45a5ead0 8770
3f2d1c0f 8771 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 8772 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 8773
ad31c402
JK		 8774 netdev->vlan_features |= NETIF_F_TSO;
8775 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8776 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8777 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8778 netdev->vlan_features |= NETIF_F_SG;
8779
f467bc06
MR		 8780 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8781 NETIF_F_IPV6_CSUM;
8782
01789349 8783 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8784 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8785
67359c3c 8786#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8787 switch (adapter->hw.mac.type) {
8788 case ixgbe_mac_X550:
8789 case ixgbe_mac_X550EM_x:
67359c3c
MR		 8790 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8791 NETIF_F_IP_CSUM |
8792 NETIF_F_IPV6_CSUM;
3f207800
DS		 8793 break;
8794 default:
8795 break;
8796 }
67359c3c 8797#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8798
7a6b6f51 8799#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8800 netdev->dcbnl_ops = &dcbnl_ops;
8801#endif
8802
eacd73f7 8803#ifdef IXGBE_FCOE
0d551589 8804 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8805 unsigned int fcoe_l;
8806
eacd73f7
YZ		 8807 if (hw->mac.ops.get_device_caps) {
8808 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8809 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8810 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8811 }
7c8ae65a 8812
d3cb9869
AD		 8813
8814 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8815 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8816
a58915c7
AD		 8817 netdev->features |= NETIF_F_FSO |
8818 NETIF_F_FCOE_CRC;
8819
7c8ae65a
AD		 8820 netdev->vlan_features |= NETIF_F_FSO |
8821 NETIF_F_FCOE_CRC |
8822 NETIF_F_FCOE_MTU;
5e09d7f6 8823 }
eacd73f7 8824#endif /* IXGBE_FCOE */
7b872a55 8825 if (pci_using_dac) {
9a799d71 8826 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8827 netdev->vlan_features |= NETIF_F_HIGHDMA;
8828 }
9a799d71 8829
082757af
DS		 8830 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8831 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8832 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8833 netdev->features |= NETIF_F_LRO;
8834
9a799d71 8835 /* make sure the EEPROM is good */
c44ade9e 8836 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8837 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8838 err = -EIO;
35937c05 8839 goto err_sw_init;
9a799d71
AK		 8840 }
8841
c762dff2
MP		 8842 ixgbe_get_platform_mac_addr(adapter);
8843
9a799d71 8844 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8845
aaeb6cdf 8846 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8847 e_dev_err("invalid MAC address\n");
9a799d71 8848 err = -EIO;
35937c05 8849 goto err_sw_init;
9a799d71
AK		 8850 }
8851
5d7daa35
JK		 8852 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8853
7086400d 8854 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8855 (unsigned long) adapter);
9a799d71 8856
58cf663f
MR		 8857 if (ixgbe_removed(hw->hw_addr)) {
8858 err = -EIO;
8859 goto err_sw_init;
8860 }
7086400d 8861 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8862 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8863 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8864
021230d4
AV		 8865 err = ixgbe_init_interrupt_scheme(adapter);
8866 if (err)
8867 goto err_sw_init;
9a799d71 8868
8e2813f5 8869 /* WOL not supported for all devices */
c23f5b6b 8870 adapter->wol = 0;
8e2813f5 8871 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8872 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8873 pdev->subsystem_device);
6b92b0ba 8874 if (hw->wol_enabled)
9417c464 8875 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8876
e8e26350
PW		 8877 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8878
15e5209f
ET		 8879 /* save off EEPROM version number */
8880 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8881 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8882
04f165ef 8883 /* pick up the PCI bus settings for reporting later */
e027d1ae 8884 if (ixgbe_pcie_from_parent(hw))
b8e82001 8885 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 8886 else
8887 hw->mac.ops.get_bus_info(hw);
04f165ef 8888
e027d1ae
JK		 8889 /* calculate the expected PCIe bandwidth required for optimal
8890 * performance. Note that some older parts will never have enough
8891 * bandwidth due to being older generation PCIe parts. We clamp these
8892 * parts to ensure no warning is displayed if it can't be fixed.
8893 */
8894 switch (hw->mac.type) {
8895 case ixgbe_mac_82598EB:
8896 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8897 break;
8898 default:
8899 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8900 break;
0c254d86 8901 }
caafb95d
JK		 8902
8903 /* don't check link if we failed to enumerate functions */
8904 if (expected_gts > 0)
8905 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8906
339de30f 8907 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8908 if (err)
339de30f 8909 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8910 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8911 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8912 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8913 part_str);
6a2aae5a
JK		 8914 else
8915 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8916 hw->mac.type, hw->phy.type, part_str);
8917
8918 e_dev_info("%pM\n", netdev->dev_addr);
8919
9a799d71 8920 /* reset the hardware with the new settings */
794caeb2 8921 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8922 if (err == IXGBE_ERR_EEPROM_VERSION) {
8923 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8924 e_dev_warn("This device is a pre-production adapter/LOM. "
8925 "Please be aware there may be issues associated "
8926 "with your hardware. If you are experiencing "
8927 "problems please contact your Intel or hardware "
8928 "representative who provided you with this "
8929 "hardware.\n");
794caeb2 8930 }
9a799d71
AK		 8931 strcpy(netdev->name, "eth%d");
8932 err = register_netdev(netdev);
8933 if (err)
8934 goto err_register;
8935
0fb6a55c
ET		 8936 pci_set_drvdata(pdev, adapter);
8937
ec74a471
ET		 8938 /* power down the optics for 82599 SFP+ fiber */
8939 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8940 hw->mac.ops.disable_tx_laser(hw);
8941
54386467
JB		 8942 /* carrier off reporting is important to ethtool even BEFORE open */
8943 netif_carrier_off(netdev);
8944
5dd2d332 8945#ifdef CONFIG_IXGBE_DCA
652f093f 8946 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8947 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8948 ixgbe_setup_dca(adapter);
8949 }
8950#endif
1cdd1ec8 8951 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8952 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8953 for (i = 0; i < adapter->num_vfs; i++)
8954 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8955 }
8956
2466dd9c
JK		 8957 /* firmware requires driver version to be 0xFFFFFFFF
8958 * since os does not support feature
8959 */
9612de92 8960 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8961 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8962 0xFF);
9612de92 8963
0365e6e4
PW		 8964 /* add san mac addr to netdev */
8965 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8966
ea81875a 8967 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8968
1210982b 8969#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8970 if (ixgbe_sysfs_init(adapter))
8971 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8972#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8973
00949167 8974 ixgbe_dbg_adapter_init(adapter);
00949167 8975
d1a35ee2
ET		 8976 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8977 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8978 hw->mac.ops.setup_link(hw,
8979 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8980 true);
8981
9a799d71
AK		 8982 return 0;
8983
8984err_register:
5eba3699 8985 ixgbe_release_hw_control(adapter);
7a921c93 8986 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8987err_sw_init:
99d74487 8988 ixgbe_disable_sriov(adapter);
7086400d 8989 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8990 iounmap(adapter->io_addr);
5d7daa35 8991 kfree(adapter->mac_table);
9a799d71 8992err_ioremap:
b5b2ffc0 8993 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8994 free_netdev(netdev);
8995err_alloc_etherdev:
e8e9f696
JP		 8996 pci_release_selected_regions(pdev,
8997 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8998err_pci_reg:
8999err_dma:
b5b2ffc0 9000 if (!adapter || disable_dev)
41c62843 9001 pci_disable_device(pdev);
9a799d71
AK		 9002 return err;
9003}
9004
9005/**
9006 * ixgbe_remove - Device Removal Routine
9007 * @pdev: PCI device information struct
9008 *
9009 * ixgbe_remove is called by the PCI subsystem to alert the driver
9010 * that it should release a PCI device. The could be caused by a
9011 * Hot-Plug event, or because the driver is going to be removed from
9012 * memory.
9013 **/
9f9a12f8 9014static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9015{
c60fbb00 9016 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9017 struct net_device *netdev;
b5b2ffc0 9018 bool disable_dev;
9a799d71 9019
0fb6a55c
ET		 9020 /* if !adapter then we already cleaned up in probe */
9021 if (!adapter)
9022 return;
9023
9024 netdev = adapter->netdev;
00949167 9025 ixgbe_dbg_adapter_exit(adapter);
00949167 9026
09f40aed 9027 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9028 cancel_work_sync(&adapter->service_task);
9a799d71 9029
3a6a4eda 9030
5dd2d332 9031#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9032 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9033 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9034 dca_remove_requester(&pdev->dev);
9035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
9036 }
9037
9038#endif
1210982b 9039#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9040 ixgbe_sysfs_exit(adapter);
1210982b 9041#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9042
0365e6e4
PW		 9043 /* remove the added san mac */
9044 ixgbe_del_sanmac_netdev(netdev);
9045
da36b647 9046#ifdef CONFIG_PCI_IOV
7837e286 9047 ixgbe_disable_sriov(adapter);
da36b647 9048#endif
6b010e9b
AW		 9049 if (netdev->reg_state == NETREG_REGISTERED)
9050 unregister_netdev(netdev);
9051
7a921c93 9052 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9053
021230d4 9054 ixgbe_release_hw_control(adapter);
9a799d71 9055
2b1588c3
AD		 9056#ifdef CONFIG_DCB
9057 kfree(adapter->ixgbe_ieee_pfc);
9058 kfree(adapter->ixgbe_ieee_ets);
9059
9060#endif
2a1a091c 9061 iounmap(adapter->io_addr);
9ce77666 9062 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9063 IORESOURCE_MEM));
9a799d71 9064
849c4542 9065 e_dev_info("complete\n");
021230d4 9066
5d7daa35 9067 kfree(adapter->mac_table);
b5b2ffc0 9068 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9069 free_netdev(netdev);
9070
19d5afd4 9071 pci_disable_pcie_error_reporting(pdev);
6fabd715 9072
b5b2ffc0 9073 if (disable_dev)
41c62843 9074 pci_disable_device(pdev);
9a799d71
AK		 9075}
9076
9077/**
9078 * ixgbe_io_error_detected - called when PCI error is detected
9079 * @pdev: Pointer to PCI device
9080 * @state: The current pci connection state
9081 *
9082 * This function is called after a PCI bus error affecting
9083 * this device has been detected.
9084 */
9085static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9086 pci_channel_state_t state)
9a799d71 9087{
c60fbb00
AD		 9088 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9089 struct net_device *netdev = adapter->netdev;
9a799d71 9090
83c61fa9 9091#ifdef CONFIG_PCI_IOV
14438464 9092 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9093 struct pci_dev *bdev, *vfdev;
9094 u32 dw0, dw1, dw2, dw3;
9095 int vf, pos;
9096 u16 req_id, pf_func;
9097
9098 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9099 adapter->num_vfs == 0)
9100 goto skip_bad_vf_detection;
9101
9102 bdev = pdev->bus->self;
62f87c0e 9103 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9104 bdev = bdev->bus->self;
9105
9106 if (!bdev)
9107 goto skip_bad_vf_detection;
9108
9109 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9110 if (!pos)
9111 goto skip_bad_vf_detection;
9112
14438464
MR		 9113 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9114 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9115 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9116 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9117 if (ixgbe_removed(hw->hw_addr))
9118 goto skip_bad_vf_detection;
83c61fa9
GR		 9119
9120 req_id = dw1 >> 16;
9121 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9122 if (!(req_id & 0x0080))
9123 goto skip_bad_vf_detection;
9124
9125 pf_func = req_id & 0x01;
9126 if ((pf_func & 1) == (pdev->devfn & 1)) {
9127 unsigned int device_id;
9128
9129 vf = (req_id & 0x7F) >> 1;
9130 e_dev_err("VF %d has caused a PCIe error\n", vf);
9131 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9132 "%8.8x\tdw3: %8.8x\n",
9133 dw0, dw1, dw2, dw3);
9134 switch (adapter->hw.mac.type) {
9135 case ixgbe_mac_82599EB:
9136 device_id = IXGBE_82599_VF_DEVICE_ID;
9137 break;
9138 case ixgbe_mac_X540:
9139 device_id = IXGBE_X540_VF_DEVICE_ID;
9140 break;
9a75a1ac
DS		 9141 case ixgbe_mac_X550:
9142 device_id = IXGBE_DEV_ID_X550_VF;
9143 break;
9144 case ixgbe_mac_X550EM_x:
9145 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9146 break;
83c61fa9
GR		 9147 default:
9148 device_id = 0;
9149 break;
9150 }
9151
9152 /* Find the pci device of the offending VF */
36e90319 9153 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9154 while (vfdev) {
9155 if (vfdev->devfn == (req_id & 0xFF))
9156 break;
36e90319 9157 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9158 device_id, vfdev);
9159 }
9160 /*
9161 * There's a slim chance the VF could have been hot plugged,
9162 * so if it is no longer present we don't need to issue the
9163 * VFLR. Just clean up the AER in that case.
9164 */
9165 if (vfdev) {
9079e416 9166 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9167 /* Free device reference count */
9168 pci_dev_put(vfdev);
83c61fa9
GR		 9169 }
9170
9171 pci_cleanup_aer_uncorrect_error_status(pdev);
9172 }
9173
9174 /*
9175 * Even though the error may have occurred on the other port
9176 * we still need to increment the vf error reference count for
9177 * both ports because the I/O resume function will be called
9178 * for both of them.
9179 */
9180 adapter->vferr_refcount++;
9181
9182 return PCI_ERS_RESULT_RECOVERED;
9183
9184skip_bad_vf_detection:
9185#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9186 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9187 return PCI_ERS_RESULT_DISCONNECT;
9188
41c62843 9189 rtnl_lock();
9a799d71
AK		 9190 netif_device_detach(netdev);
9191
41c62843
MR		 9192 if (state == pci_channel_io_perm_failure) {
9193 rtnl_unlock();
3044b8d1 9194 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9195 }
3044b8d1 9196
9a799d71
AK		 9197 if (netif_running(netdev))
9198 ixgbe_down(adapter);
41c62843
MR		 9199
9200 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9201 pci_disable_device(pdev);
9202 rtnl_unlock();
9a799d71 9203
b4617240 9204 /* Request a slot reset. */
9a799d71
AK		 9205 return PCI_ERS_RESULT_NEED_RESET;
9206}
9207
9208/**
9209 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9210 * @pdev: Pointer to PCI device
9211 *
9212 * Restart the card from scratch, as if from a cold-boot.
9213 */
9214static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9215{
c60fbb00 9216 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9217 pci_ers_result_t result;
9218 int err;
9a799d71 9219
9ce77666 9220 if (pci_enable_device_mem(pdev)) {
396e799c 9221 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9222 result = PCI_ERS_RESULT_DISCONNECT;
9223 } else {
4e857c58 9224 smp_mb__before_atomic();
41c62843 9225 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9226 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9227 pci_set_master(pdev);
9228 pci_restore_state(pdev);
c0e1f68b 9229 pci_save_state(pdev);
9a799d71 9230
dd4d8ca6 9231 pci_wake_from_d3(pdev, false);
9a799d71 9232
6fabd715 9233 ixgbe_reset(adapter);
88512539 9234 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9235 result = PCI_ERS_RESULT_RECOVERED;
9236 }
9237
9238 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9239 if (err) {
849c4542
ET		 9240 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9241 "failed 0x%0x\n", err);
6fabd715
PWJ		 9242 /* non-fatal, continue */
9243 }
9a799d71 9244
6fabd715 9245 return result;
9a799d71
AK		 9246}
9247
9248/**
9249 * ixgbe_io_resume - called when traffic can start flowing again.
9250 * @pdev: Pointer to PCI device
9251 *
9252 * This callback is called when the error recovery driver tells us that
9253 * its OK to resume normal operation.
9254 */
9255static void ixgbe_io_resume(struct pci_dev *pdev)
9256{
c60fbb00
AD		 9257 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9258 struct net_device *netdev = adapter->netdev;
9a799d71 9259
83c61fa9
GR		 9260#ifdef CONFIG_PCI_IOV
9261 if (adapter->vferr_refcount) {
9262 e_info(drv, "Resuming after VF err\n");
9263 adapter->vferr_refcount--;
9264 return;
9265 }
9266
9267#endif
c7ccde0f
AD		 9268 if (netif_running(netdev))
9269 ixgbe_up(adapter);
9a799d71
AK		 9270
9271 netif_device_attach(netdev);
9a799d71
AK		 9272}
9273
3646f0e5 9274static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9275 .error_detected = ixgbe_io_error_detected,
9276 .slot_reset = ixgbe_io_slot_reset,
9277 .resume = ixgbe_io_resume,
9278};
9279
9280static struct pci_driver ixgbe_driver = {
9281 .name = ixgbe_driver_name,
9282 .id_table = ixgbe_pci_tbl,
9283 .probe = ixgbe_probe,
9f9a12f8 9284 .remove = ixgbe_remove,
9a799d71
AK		 9285#ifdef CONFIG_PM
9286 .suspend = ixgbe_suspend,
9287 .resume = ixgbe_resume,
9288#endif
9289 .shutdown = ixgbe_shutdown,
da36b647 9290 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9291 .err_handler = &ixgbe_err_handler
9292};
9293
9294/**
9295 * ixgbe_init_module - Driver Registration Routine
9296 *
9297 * ixgbe_init_module is the first routine called when the driver is
9298 * loaded. All it does is register with the PCI subsystem.
9299 **/
9300static int __init ixgbe_init_module(void)
9301{
9302 int ret;
c7689578 9303 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9304 pr_info("%s\n", ixgbe_copyright);
9a799d71 9305
00949167 9306 ixgbe_dbg_init();
00949167 9307
f01fc1a8
JK		 9308 ret = pci_register_driver(&ixgbe_driver);
9309 if (ret) {
f01fc1a8 9310 ixgbe_dbg_exit();
f01fc1a8
JK		 9311 return ret;
9312 }
9313
5dd2d332 9314#ifdef CONFIG_IXGBE_DCA
bd0362dd 9315 dca_register_notify(&dca_notifier);
bd0362dd 9316#endif
5dd2d332 9317
f01fc1a8 9318 return 0;
9a799d71 9319}
b4617240 9320
9a799d71
AK		 9321module_init(ixgbe_init_module);
9322
9323/**
9324 * ixgbe_exit_module - Driver Exit Cleanup Routine
9325 *
9326 * ixgbe_exit_module is called just before the driver is removed
9327 * from memory.
9328 **/
9329static void __exit ixgbe_exit_module(void)
9330{
5dd2d332 9331#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9332 dca_unregister_notify(&dca_notifier);
9333#endif
9a799d71 9334 pci_unregister_driver(&ixgbe_driver);
00949167 9335
00949167 9336 ixgbe_dbg_exit();
9a799d71 9337}
bd0362dd 9338
5dd2d332 9339#ifdef CONFIG_IXGBE_DCA
bd0362dd 9340static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9341 void *p)
bd0362dd
JC		 9342{
9343 int ret_val;
9344
9345 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9346 __ixgbe_notify_dca);
bd0362dd
JC		 9347
9348 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9349}
b453368d 9350
5dd2d332 9351#endif /* CONFIG_IXGBE_DCA */
849c4542 9352
9a799d71
AK		 9353module_exit(ixgbe_exit_module);
9354
9355/* ixgbe_main.c */
Linux kernel - Deliverables
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