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ixgbe: Use __dev_uc_sync and __dev_uc_unsync for unicast addresses
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
67359c3c 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
9a799d71
AK		 68
69char ixgbe_driver_name[] = "ixgbe";
9c8eb720 70static const char ixgbe_driver_string[] =
e8e9f696 71 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 72#ifdef IXGBE_FCOE
ea81875a
NP		 73char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 75#else
76static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78#endif
21dd5601 79#define DRV_VERSION "4.2.1-k"
9c8eb720 80const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 81static const char ixgbe_copyright[] =
67359c3c 82 "Copyright (c) 1999-2015 Intel Corporation.";
9a799d71 83
f44e751b
DS		 84static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
85
9a799d71 86static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 87 [board_82598] = &ixgbe_82598_info,
88 [board_82599] = &ixgbe_82599_info,
89 [board_X540] = &ixgbe_X540_info,
90 [board_X550] = &ixgbe_X550_info,
91 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 92};
93
94/* ixgbe_pci_tbl - PCI Device ID Table
95 *
96 * Wildcard entries (PCI_ANY_ID) should come last
97 * Last entry must be all 0s
98 *
99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
100 * Class, Class Mask, private data (not used) }
101 */
9baa3c34 102static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
9a799d71
AK		 138 /* required last entry */
139 {0, }
140};
141MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
142
5dd2d332 143#ifdef CONFIG_IXGBE_DCA
bd0362dd 144static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 145 void *p);
bd0362dd
JC		 146static struct notifier_block dca_notifier = {
147 .notifier_call = ixgbe_notify_dca,
148 .next = NULL,
149 .priority = 0
150};
151#endif
152
1cdd1ec8
GR		 153#ifdef CONFIG_PCI_IOV
154static unsigned int max_vfs;
155module_param(max_vfs, uint, 0);
e8e9f696 156MODULE_PARM_DESC(max_vfs,
170e8543 157 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 158#endif /* CONFIG_PCI_IOV */
159
8ef78adc
PWJ		 160static unsigned int allow_unsupported_sfp;
161module_param(allow_unsupported_sfp, uint, 0);
162MODULE_PARM_DESC(allow_unsupported_sfp,
163 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
164
b3f4d599 165#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
166static int debug = -1;
167module_param(debug, int, 0);
168MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
169
9a799d71
AK		 170MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
171MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
172MODULE_LICENSE("GPL");
173MODULE_VERSION(DRV_VERSION);
174
780484d8
MR		 175static struct workqueue_struct *ixgbe_wq;
176
14438464
MR		 177static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
178
b8e82001
JK		 179static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
180 u32 reg, u16 *value)
181{
b8e82001
JK		 182 struct pci_dev *parent_dev;
183 struct pci_bus *parent_bus;
184
185 parent_bus = adapter->pdev->bus->parent;
186 if (!parent_bus)
187 return -1;
188
189 parent_dev = parent_bus->self;
190 if (!parent_dev)
191 return -1;
192
c0798edf 193 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 194 return -1;
195
c0798edf 196 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 197 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
199 return -1;
b8e82001
JK		 200 return 0;
201}
202
203static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
204{
205 struct ixgbe_hw *hw = &adapter->hw;
206 u16 link_status = 0;
207 int err;
208
209 hw->bus.type = ixgbe_bus_type_pci_express;
210
211 /* Get the negotiated link width and speed from PCI config space of the
212 * parent, as this device is behind a switch
213 */
214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
215
216 /* assume caller will handle error case */
217 if (err)
218 return err;
219
220 hw->bus.width = ixgbe_convert_bus_width(link_status);
221 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
222
223 return 0;
224}
225
e027d1ae
JK		 226/**
227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
228 * @hw: hw specific details
229 *
230 * This function is used by probe to determine whether a device's PCI-Express
231 * bandwidth details should be gathered from the parent bus instead of from the
232 * device. Used to ensure that various locations all have the correct device ID
233 * checks.
234 */
235static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
236{
237 switch (hw->device_id) {
238 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 239 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 240 return true;
241 default:
242 return false;
243 }
244}
245
246static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
247 int expected_gts)
248{
f9328bc6 249 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 250 int max_gts = 0;
251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
253 struct pci_dev *pdev;
254
f9328bc6
DS		 255 /* Some devices are not connected over PCIe and thus do not negotiate
256 * speed. These devices do not have valid bus info, and thus any report
257 * we generate may not be correct.
258 */
259 if (hw->bus.type == ixgbe_bus_type_internal)
260 return;
261
56d1392f 262 /* determine whether to use the parent device */
e027d1ae
JK		 263 if (ixgbe_pcie_from_parent(&adapter->hw))
264 pdev = adapter->pdev->bus->parent->self;
265 else
266 pdev = adapter->pdev;
267
268 if (pcie_get_minimum_link(pdev, &speed, &width) ||
269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
270 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
271 return;
272 }
273
274 switch (speed) {
275 case PCIE_SPEED_2_5GT:
276 /* 8b/10b encoding reduces max throughput by 20% */
277 max_gts = 2 * width;
278 break;
279 case PCIE_SPEED_5_0GT:
280 /* 8b/10b encoding reduces max throughput by 20% */
281 max_gts = 4 * width;
282 break;
283 case PCIE_SPEED_8_0GT:
9f0a433c 284 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 285 max_gts = 8 * width;
286 break;
287 default:
288 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
289 return;
290 }
291
292 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
293 max_gts);
294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
298 "Unknown"),
299 width,
300 (speed == PCIE_SPEED_2_5GT ? "20%" :
301 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 302 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 303 "Unknown"));
304
305 if (max_gts < expected_gts) {
306 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
308 expected_gts);
309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
310 }
311}
312
7086400d
AD		 313static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
314{
315 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 316 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 318 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 319}
320
2a1a091c
MR		 321static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
322{
323 struct ixgbe_adapter *adapter = hw->back;
324
325 if (!hw->hw_addr)
326 return;
327 hw->hw_addr = NULL;
328 e_dev_err("Adapter removed\n");
58cf663f
MR		 329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
330 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 331}
332
f8e2472f 333static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 334{
335 u32 value;
336
337 /* The following check not only optimizes a bit by not
338 * performing a read on the status register when the
339 * register just read was a status register read that
340 * returned IXGBE_FAILED_READ_REG. It also blocks any
341 * potential recursion.
342 */
343 if (reg == IXGBE_STATUS) {
344 ixgbe_remove_adapter(hw);
345 return;
346 }
347 value = ixgbe_read_reg(hw, IXGBE_STATUS);
348 if (value == IXGBE_FAILED_READ_REG)
349 ixgbe_remove_adapter(hw);
350}
351
f8e2472f
MR		 352/**
353 * ixgbe_read_reg - Read from device register
354 * @hw: hw specific details
355 * @reg: offset of register to read
356 *
357 * Returns : value read or IXGBE_FAILED_READ_REG if removed
358 *
359 * This function is used to read device registers. It checks for device
360 * removal by confirming any read that returns all ones by checking the
361 * status register value for all ones. This function avoids reading from
362 * the hardware if a removal was previously detected in which case it
363 * returns IXGBE_FAILED_READ_REG (all ones).
364 */
365u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
366{
367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
368 u32 value;
369
370 if (ixgbe_removed(reg_addr))
371 return IXGBE_FAILED_READ_REG;
372 value = readl(reg_addr + reg);
373 if (unlikely(value == IXGBE_FAILED_READ_REG))
374 ixgbe_check_remove(hw, reg);
375 return value;
376}
377
14438464
MR		 378static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
379{
380 u16 value;
381
382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
383 if (value == IXGBE_FAILED_READ_CFG_WORD) {
384 ixgbe_remove_adapter(hw);
385 return true;
386 }
387 return false;
388}
389
390u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
391{
392 struct ixgbe_adapter *adapter = hw->back;
393 u16 value;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return IXGBE_FAILED_READ_CFG_WORD;
397 pci_read_config_word(adapter->pdev, reg, &value);
398 if (value == IXGBE_FAILED_READ_CFG_WORD &&
399 ixgbe_check_cfg_remove(hw, adapter->pdev))
400 return IXGBE_FAILED_READ_CFG_WORD;
401 return value;
402}
403
404#ifdef CONFIG_PCI_IOV
405static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
406{
407 struct ixgbe_adapter *adapter = hw->back;
408 u32 value;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return IXGBE_FAILED_READ_CFG_DWORD;
412 pci_read_config_dword(adapter->pdev, reg, &value);
413 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
414 ixgbe_check_cfg_remove(hw, adapter->pdev))
415 return IXGBE_FAILED_READ_CFG_DWORD;
416 return value;
417}
418#endif /* CONFIG_PCI_IOV */
419
ed19231c
JK		 420void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
421{
422 struct ixgbe_adapter *adapter = hw->back;
423
424 if (ixgbe_removed(hw->hw_addr))
425 return;
426 pci_write_config_word(adapter->pdev, reg, value);
427}
428
7086400d
AD		 429static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
430{
431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
432
52f33af8 433 /* flush memory to make sure state is correct before next watchdog */
4e857c58 434 smp_mb__before_atomic();
7086400d
AD		 435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
436}
437
dcd79aeb
TI		 438struct ixgbe_reg_info {
439 u32 ofs;
440 char *name;
441};
442
443static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
444
445 /* General Registers */
446 {IXGBE_CTRL, "CTRL"},
447 {IXGBE_STATUS, "STATUS"},
448 {IXGBE_CTRL_EXT, "CTRL_EXT"},
449
450 /* Interrupt Registers */
451 {IXGBE_EICR, "EICR"},
452
453 /* RX Registers */
454 {IXGBE_SRRCTL(0), "SRRCTL"},
455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
456 {IXGBE_RDLEN(0), "RDLEN"},
457 {IXGBE_RDH(0), "RDH"},
458 {IXGBE_RDT(0), "RDT"},
459 {IXGBE_RXDCTL(0), "RXDCTL"},
460 {IXGBE_RDBAL(0), "RDBAL"},
461 {IXGBE_RDBAH(0), "RDBAH"},
462
463 /* TX Registers */
464 {IXGBE_TDBAL(0), "TDBAL"},
465 {IXGBE_TDBAH(0), "TDBAH"},
466 {IXGBE_TDLEN(0), "TDLEN"},
467 {IXGBE_TDH(0), "TDH"},
468 {IXGBE_TDT(0), "TDT"},
469 {IXGBE_TXDCTL(0), "TXDCTL"},
470
471 /* List Terminator */
ca8dfe25 472 { .name = NULL }
dcd79aeb
TI		 473};
474
475
476/*
477 * ixgbe_regdump - register printout routine
478 */
479static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
480{
481 int i = 0, j = 0;
482 char rname[16];
483 u32 regs[64];
484
485 switch (reginfo->ofs) {
486 case IXGBE_SRRCTL(0):
487 for (i = 0; i < 64; i++)
488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
489 break;
490 case IXGBE_DCA_RXCTRL(0):
491 for (i = 0; i < 64; i++)
492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
493 break;
494 case IXGBE_RDLEN(0):
495 for (i = 0; i < 64; i++)
496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
497 break;
498 case IXGBE_RDH(0):
499 for (i = 0; i < 64; i++)
500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
501 break;
502 case IXGBE_RDT(0):
503 for (i = 0; i < 64; i++)
504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
505 break;
506 case IXGBE_RXDCTL(0):
507 for (i = 0; i < 64; i++)
508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
509 break;
510 case IXGBE_RDBAL(0):
511 for (i = 0; i < 64; i++)
512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
513 break;
514 case IXGBE_RDBAH(0):
515 for (i = 0; i < 64; i++)
516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
517 break;
518 case IXGBE_TDBAL(0):
519 for (i = 0; i < 64; i++)
520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
521 break;
522 case IXGBE_TDBAH(0):
523 for (i = 0; i < 64; i++)
524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
525 break;
526 case IXGBE_TDLEN(0):
527 for (i = 0; i < 64; i++)
528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
529 break;
530 case IXGBE_TDH(0):
531 for (i = 0; i < 64; i++)
532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
533 break;
534 case IXGBE_TDT(0):
535 for (i = 0; i < 64; i++)
536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
537 break;
538 case IXGBE_TXDCTL(0):
539 for (i = 0; i < 64; i++)
540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
541 break;
542 default:
c7689578 543 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 544 IXGBE_READ_REG(hw, reginfo->ofs));
545 return;
546 }
547
548 for (i = 0; i < 8; i++) {
549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 550 pr_err("%-15s", rname);
dcd79aeb 551 for (j = 0; j < 8; j++)
c7689578
JP		 552 pr_cont(" %08x", regs[i*8+j]);
553 pr_cont("\n");
dcd79aeb
TI		 554 }
555
556}
557
558/*
559 * ixgbe_dump - Print registers, tx-rings and rx-rings
560 */
561static void ixgbe_dump(struct ixgbe_adapter *adapter)
562{
563 struct net_device *netdev = adapter->netdev;
564 struct ixgbe_hw *hw = &adapter->hw;
565 struct ixgbe_reg_info *reginfo;
566 int n = 0;
567 struct ixgbe_ring *tx_ring;
729739b7 568 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 569 union ixgbe_adv_tx_desc *tx_desc;
570 struct my_u0 { u64 a; u64 b; } *u0;
571 struct ixgbe_ring *rx_ring;
572 union ixgbe_adv_rx_desc *rx_desc;
573 struct ixgbe_rx_buffer *rx_buffer_info;
574 u32 staterr;
575 int i = 0;
576
577 if (!netif_msg_hw(adapter))
578 return;
579
580 /* Print netdevice Info */
581 if (netdev) {
582 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 583 pr_info("Device Name state "
dcd79aeb 584 "trans_start last_rx\n");
c7689578
JP		 585 pr_info("%-15s %016lX %016lX %016lX\n",
586 netdev->name,
587 netdev->state,
588 netdev->trans_start,
589 netdev->last_rx);
dcd79aeb
TI		 590 }
591
592 /* Print Registers */
593 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 594 pr_info(" Register Name Value\n");
dcd79aeb
TI		 595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
596 reginfo->name; reginfo++) {
597 ixgbe_regdump(hw, reginfo);
598 }
599
600 /* Print TX Ring Summary */
601 if (!netdev || !netif_running(netdev))
e90dd264 602 return;
dcd79aeb
TI		 603
604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 605 pr_info(" %s %s %s %s\n",
606 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
607 "leng", "ntw", "timestamp");
dcd79aeb
TI		 608 for (n = 0; n < adapter->num_tx_queues; n++) {
609 tx_ring = adapter->tx_ring[n];
729739b7 610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 612 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 613 (u64)dma_unmap_addr(tx_buffer, dma),
614 dma_unmap_len(tx_buffer, len),
615 tx_buffer->next_to_watch,
616 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
39ac868a 627 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
39ac868a 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
dcd79aeb
TI		 658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 tx_ring = adapter->tx_ring[n];
c7689578
JP		 662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
664 pr_info("------------------------------------\n");
8ad88e37
JH		 665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 669
670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 671 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 672 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 673 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
676 i,
677 le64_to_cpu(u0->a),
678 le64_to_cpu(u0->b),
679 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 680 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 681 tx_buffer->next_to_watch,
682 (u64)tx_buffer->time_stamp,
683 tx_buffer->skb);
684 if (i == tx_ring->next_to_use &&
685 i == tx_ring->next_to_clean)
686 pr_cont(" NTC/U\n");
687 else if (i == tx_ring->next_to_use)
688 pr_cont(" NTU\n");
689 else if (i == tx_ring->next_to_clean)
690 pr_cont(" NTC\n");
691 else
692 pr_cont("\n");
693
694 if (netif_msg_pktdata(adapter) &&
695 tx_buffer->skb)
696 print_hex_dump(KERN_INFO, "",
697 DUMP_PREFIX_ADDRESS, 16, 1,
698 tx_buffer->skb->data,
699 dma_unmap_len(tx_buffer, len),
700 true);
701 }
dcd79aeb
TI		 702 }
703 }
704
705 /* Print RX Rings Summary */
706rx_ring_summary:
707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 708 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 709 for (n = 0; n < adapter->num_rx_queues; n++) {
710 rx_ring = adapter->rx_ring[n];
c7689578
JP		 711 pr_info("%5d %5X %5X\n",
712 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 713 }
714
715 /* Print RX Rings */
716 if (!netif_msg_rx_status(adapter))
e90dd264 717 return;
dcd79aeb
TI		 718
719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
720
39ac868a
JH		 721 /* Receive Descriptor Formats
722 *
723 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 724 * 63 1 0
725 * +-----------------------------------------------------+
726 * 0 | Packet Buffer Address [63:1] |A0/NSE|
727 * +----------------------------------------------+------+
728 * 8 | Header Buffer Address [63:1] | DD |
729 * +-----------------------------------------------------+
730 *
731 *
39ac868a 732 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 733 *
734 * 63 48 47 32 31 30 21 20 16 15 4 3 0
735 * +------------------------------------------------------+
39ac868a
JH		 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
737 * | Packet | IP | | | | Type | Type |
738 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 739 * +------------------------------------------------------+
740 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
741 * +------------------------------------------------------+
742 * 63 48 47 32 31 20 19 0
39ac868a
JH		 743 *
744 * 82599+ Advanced Receive Descriptor (Read) Format
745 * 63 1 0
746 * +-----------------------------------------------------+
747 * 0 | Packet Buffer Address [63:1] |A0/NSE|
748 * +----------------------------------------------+------+
749 * 8 | Header Buffer Address [63:1] | DD |
750 * +-----------------------------------------------------+
751 *
752 *
753 * 82599+ Advanced Receive Descriptor (Write-Back) Format
754 *
755 * 63 48 47 32 31 30 21 20 17 16 4 3 0
756 * +------------------------------------------------------+
757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
759 * |/ Flow Dir Flt ID | | | | | |
760 * +------------------------------------------------------+
761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
762 * +------------------------------------------------------+
763 * 63 48 47 32 31 20 19 0
dcd79aeb 764 */
39ac868a 765
dcd79aeb
TI		 766 for (n = 0; n < adapter->num_rx_queues; n++) {
767 rx_ring = adapter->rx_ring[n];
c7689578
JP		 768 pr_info("------------------------------------\n");
769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
770 pr_info("------------------------------------\n");
8ad88e37
JH		 771 pr_info("%s%s%s",
772 "R [desc] [ PktBuf A0] ",
773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 774 "<-- Adv Rx Read format\n");
8ad88e37
JH		 775 pr_info("%s%s%s",
776 "RWB[desc] [PcsmIpSHl PtRs] ",
777 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 778 "<-- Adv Rx Write-Back format\n");
779
780 for (i = 0; i < rx_ring->count; i++) {
781 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 782 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 783 u0 = (struct my_u0 *)rx_desc;
784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
785 if (staterr & IXGBE_RXD_STAT_DD) {
786 /* Descriptor Done */
c7689578 787 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 788 "%016llX ---------------- %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 rx_buffer_info->skb);
792 } else {
c7689578 793 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 794 "%016llX %016llX %p", i,
795 le64_to_cpu(u0->a),
796 le64_to_cpu(u0->b),
797 (u64)rx_buffer_info->dma,
798 rx_buffer_info->skb);
799
9c50c035
ET		 800 if (netif_msg_pktdata(adapter) &&
801 rx_buffer_info->dma) {
dcd79aeb
TI		 802 print_hex_dump(KERN_INFO, "",
803 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 804 page_address(rx_buffer_info->page) +
805 rx_buffer_info->page_offset,
f800326d 806 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 807 }
808 }
809
810 if (i == rx_ring->next_to_use)
c7689578 811 pr_cont(" NTU\n");
dcd79aeb 812 else if (i == rx_ring->next_to_clean)
c7689578 813 pr_cont(" NTC\n");
dcd79aeb 814 else
c7689578 815 pr_cont("\n");
dcd79aeb
TI		 816
817 }
818 }
dcd79aeb
TI		 819}
820
5eba3699
AV		 821static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
822{
823 u32 ctrl_ext;
824
825 /* Let firmware take over control of h/w */
826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 829}
830
831static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
832{
833 u32 ctrl_ext;
834
835 /* Let firmware know the driver has taken over */
836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 839}
9a799d71 840
49ce9c2c 841/**
e8e26350
PW		 842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
843 * @adapter: pointer to adapter struct
844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
845 * @queue: queue to map the corresponding interrupt to
846 * @msix_vector: the vector to map to the corresponding queue
847 *
848 */
849static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 850 u8 queue, u8 msix_vector)
9a799d71
AK		 851{
852 u32 ivar, index;
e8e26350
PW		 853 struct ixgbe_hw *hw = &adapter->hw;
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
857 if (direction == -1)
858 direction = 0;
859 index = (((direction * 64) + queue) >> 2) & 0x1F;
860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
861 ivar &= ~(0xFF << (8 * (queue & 0x3)));
862 ivar |= (msix_vector << (8 * (queue & 0x3)));
863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
864 break;
865 case ixgbe_mac_82599EB:
b93a2226 866 case ixgbe_mac_X540:
9a75a1ac
DS		 867 case ixgbe_mac_X550:
868 case ixgbe_mac_X550EM_x:
e8e26350
PW		 869 if (direction == -1) {
870 /* other causes */
871 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
872 index = ((queue & 1) * 8);
873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
874 ivar &= ~(0xFF << index);
875 ivar |= (msix_vector << index);
876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
877 break;
878 } else {
879 /* tx or rx causes */
880 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
881 index = ((16 * (queue & 1)) + (8 * direction));
882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
883 ivar &= ~(0xFF << index);
884 ivar |= (msix_vector << index);
885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
886 break;
887 }
888 default:
889 break;
890 }
9a799d71
AK		 891}
892
fe49f04a 893static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 894 u64 qmask)
fe49f04a
AD		 895{
896 u32 mask;
897
bd508178
AD		 898 switch (adapter->hw.mac.type) {
899 case ixgbe_mac_82598EB:
fe49f04a
AD		 900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 902 break;
903 case ixgbe_mac_82599EB:
b93a2226 904 case ixgbe_mac_X540:
9a75a1ac
DS		 905 case ixgbe_mac_X550:
906 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 907 mask = (qmask & 0xFFFFFFFF);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
909 mask = (qmask >> 32);
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 911 break;
912 default:
913 break;
fe49f04a
AD		 914 }
915}
916
729739b7
AD		 917void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
918 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 919{
729739b7
AD		 920 if (tx_buffer->skb) {
921 dev_kfree_skb_any(tx_buffer->skb);
922 if (dma_unmap_len(tx_buffer, len))
d3d00239 923 dma_unmap_single(ring->dev,
729739b7
AD		 924 dma_unmap_addr(tx_buffer, dma),
925 dma_unmap_len(tx_buffer, len),
926 DMA_TO_DEVICE);
927 } else if (dma_unmap_len(tx_buffer, len)) {
928 dma_unmap_page(ring->dev,
929 dma_unmap_addr(tx_buffer, dma),
930 dma_unmap_len(tx_buffer, len),
931 DMA_TO_DEVICE);
e5a43549 932 }
729739b7
AD		 933 tx_buffer->next_to_watch = NULL;
934 tx_buffer->skb = NULL;
935 dma_unmap_len_set(tx_buffer, len, 0);
936 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 937}
938
943561d3 939static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 940{
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 943 int i;
943561d3 944 u32 data;
c84d324c 945
943561d3
AD		 946 if ((hw->fc.current_mode != ixgbe_fc_full) &&
947 (hw->fc.current_mode != ixgbe_fc_rx_pause))
948 return;
c84d324c 949
943561d3
AD		 950 switch (hw->mac.type) {
951 case ixgbe_mac_82598EB:
952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
953 break;
954 default:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
956 }
957 hwstats->lxoffrxc += data;
c84d324c 958
943561d3
AD		 959 /* refill credits (no tx hang) if we received xoff */
960 if (!data)
c84d324c 961 return;
943561d3
AD		 962
963 for (i = 0; i < adapter->num_tx_queues; i++)
964 clear_bit(__IXGBE_HANG_CHECK_ARMED,
965 &adapter->tx_ring[i]->state);
966}
967
968static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
969{
970 struct ixgbe_hw *hw = &adapter->hw;
971 struct ixgbe_hw_stats *hwstats = &adapter->stats;
972 u32 xoff[8] = {0};
2afaa00d 973 u8 tc;
943561d3
AD		 974 int i;
975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
976
977 if (adapter->ixgbe_ieee_pfc)
978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
979
980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
981 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 982 return;
943561d3 983 }
c84d324c
JF		 984
985 /* update stats for each tc, only valid with PFC enabled */
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 987 u32 pxoffrxc;
988
c84d324c
JF		 989 switch (hw->mac.type) {
990 case ixgbe_mac_82598EB:
2afaa00d 991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 992 break;
c84d324c 993 default:
2afaa00d 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 995 }
2afaa00d
PN		 996 hwstats->pxoffrxc[i] += pxoffrxc;
997 /* Get the TC for given UP */
998 tc = netdev_get_prio_tc_map(adapter->netdev, i);
999 xoff[tc] += pxoffrxc;
c84d324c
JF		 1000 }
1001
1002 /* disarm tx queues that have received xoff frames */
1003 for (i = 0; i < adapter->num_tx_queues; i++) {
1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1005
2afaa00d 1006 tc = tx_ring->dcb_tc;
c84d324c
JF		 1007 if (xoff[tc])
1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1009 }
26f23d82
YZ		 1010}
1011
c84d324c 1012static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1013{
7d7ce682 1014 return ring->stats.packets;
c84d324c
JF		 1015}
1016
1017static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1018{
2a47fa45
JF		 1019 struct ixgbe_adapter *adapter;
1020 struct ixgbe_hw *hw;
1021 u32 head, tail;
1022
1023 if (ring->l2_accel_priv)
1024 adapter = ring->l2_accel_priv->real_adapter;
1025 else
1026 adapter = netdev_priv(ring->netdev);
e01c31a5 1027
2a47fa45
JF		 1028 hw = &adapter->hw;
1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1031
1032 if (head != tail)
1033 return (head < tail) ?
1034 tail - head : (tail + ring->count - head);
1035
1036 return 0;
1037}
1038
1039static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1040{
1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1044
7d637bcc 1045 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1046
1047 /*
1048 * Check for a hung queue, but be thorough. This verifies
1049 * that a transmit has been completed since the previous
1050 * check AND there is at least one packet pending. The
1051 * ARMED bit is set to indicate a potential hang. The
1052 * bit is cleared if a pause frame is received to remove
1053 * false hang detection due to PFC or 802.3x frames. By
1054 * requiring this to fail twice we avoid races with
1055 * pfc clearing the ARMED bit and conditions where we
1056 * run the check_tx_hang logic with a transmit completion
1057 * pending but without time to complete it yet.
1058 */
e90dd264 1059 if (tx_done_old == tx_done && tx_pending)
c84d324c 1060 /* make sure it is true for two checks in a row */
e90dd264
MR		 1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1062 &tx_ring->state);
1063 /* update completed stats and continue */
1064 tx_ring->tx_stats.tx_done_old = tx_done;
1065 /* reset the countdown */
1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1067
e90dd264 1068 return false;
9a799d71
AK		 1069}
1070
c83c6cbd
AD		 1071/**
1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1073 * @adapter: driver private struct
1074 **/
1075static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1076{
1077
1078 /* Do the reset outside of interrupt context */
1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1081 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1082 ixgbe_service_event_schedule(adapter);
1083 }
1084}
e01c31a5 1085
9a799d71
AK		 1086/**
1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1088 * @q_vector: structure containing interrupt and ring information
e01c31a5 1089 * @tx_ring: tx ring to clean
9a799d71 1090 **/
fe49f04a 1091static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1092 struct ixgbe_ring *tx_ring)
9a799d71 1093{
fe49f04a 1094 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1095 struct ixgbe_tx_buffer *tx_buffer;
1096 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1097 unsigned int total_bytes = 0, total_packets = 0;
59224555 1098 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1099 unsigned int i = tx_ring->next_to_clean;
1100
1101 if (test_bit(__IXGBE_DOWN, &adapter->state))
1102 return true;
9a799d71 1103
d3d00239 1104 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1105 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1106 i -= tx_ring->count;
12207e49 1107
729739b7 1108 do {
d3d00239
AD		 1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1110
1111 /* if next_to_watch is not set then there is no work pending */
1112 if (!eop_desc)
1113 break;
1114
7f83a9e6 1115 /* prevent any other reads prior to eop_desc */
7e63bf49 1116 read_barrier_depends();
7f83a9e6 1117
d3d00239
AD		 1118 /* if DD is not set pending work has not been completed */
1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1120 break;
8ad494b0 1121
d3d00239
AD		 1122 /* clear next_to_watch to prevent false hangs */
1123 tx_buffer->next_to_watch = NULL;
8ad494b0 1124
091a6246
AD		 1125 /* update the statistics for this packet */
1126 total_bytes += tx_buffer->bytecount;
1127 total_packets += tx_buffer->gso_segs;
1128
fd0db0ed 1129 /* free the skb */
fe1f2a97 1130 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1131
729739b7
AD		 1132 /* unmap skb header data */
1133 dma_unmap_single(tx_ring->dev,
1134 dma_unmap_addr(tx_buffer, dma),
1135 dma_unmap_len(tx_buffer, len),
1136 DMA_TO_DEVICE);
1137
fd0db0ed
AD		 1138 /* clear tx_buffer data */
1139 tx_buffer->skb = NULL;
729739b7 1140 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1141
729739b7
AD		 1142 /* unmap remaining buffers */
1143 while (tx_desc != eop_desc) {
d3d00239
AD		 1144 tx_buffer++;
1145 tx_desc++;
8ad494b0 1146 i++;
729739b7
AD		 1147 if (unlikely(!i)) {
1148 i -= tx_ring->count;
d3d00239 1149 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1151 }
e01c31a5 1152
729739b7
AD		 1153 /* unmap any remaining paged data */
1154 if (dma_unmap_len(tx_buffer, len)) {
1155 dma_unmap_page(tx_ring->dev,
1156 dma_unmap_addr(tx_buffer, dma),
1157 dma_unmap_len(tx_buffer, len),
1158 DMA_TO_DEVICE);
1159 dma_unmap_len_set(tx_buffer, len, 0);
1160 }
1161 }
1162
1163 /* move us one more past the eop_desc for start of next pkt */
1164 tx_buffer++;
1165 tx_desc++;
1166 i++;
1167 if (unlikely(!i)) {
1168 i -= tx_ring->count;
1169 tx_buffer = tx_ring->tx_buffer_info;
1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1171 }
1172
1173 /* issue prefetch for next Tx descriptor */
1174 prefetch(tx_desc);
12207e49 1175
729739b7
AD		 1176 /* update budget accounting */
1177 budget--;
1178 } while (likely(budget));
1179
1180 i += tx_ring->count;
9a799d71 1181 tx_ring->next_to_clean = i;
d3d00239 1182 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1183 tx_ring->stats.bytes += total_bytes;
bd198058 1184 tx_ring->stats.packets += total_packets;
d3d00239 1185 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1186 q_vector->tx.total_bytes += total_bytes;
1187 q_vector->tx.total_packets += total_packets;
b953799e 1188
c84d324c
JF		 1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1190 /* schedule immediate reset if we believe we hung */
1191 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1192 e_err(drv, "Detected Tx Unit Hang\n"
1193 " Tx Queue <%d>\n"
1194 " TDH, TDT <%x>, <%x>\n"
1195 " next_to_use <%x>\n"
1196 " next_to_clean <%x>\n"
1197 "tx_buffer_info[next_to_clean]\n"
1198 " time_stamp <%lx>\n"
1199 " jiffies <%lx>\n",
1200 tx_ring->queue_index,
1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1203 tx_ring->next_to_use, i,
1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1205
1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1207
1208 e_info(probe,
1209 "tx hang %d detected on queue %d, resetting adapter\n",
1210 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1211
b953799e 1212 /* schedule immediate reset if we believe we hung */
c83c6cbd 1213 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1214
1215 /* the adapter is about to reset, no point in enabling stuff */
59224555 1216 return true;
b953799e 1217 }
9a799d71 1218
b2d96e0a
AD		 1219 netdev_tx_completed_queue(txring_txq(tx_ring),
1220 total_packets, total_bytes);
1221
e092be60 1222#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1225 /* Make sure that anybody stopping the queue after this
1226 * sees the new next_to_clean.
1227 */
1228 smp_mb();
729739b7
AD		 1229 if (__netif_subqueue_stopped(tx_ring->netdev,
1230 tx_ring->queue_index)
1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1232 netif_wake_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
5b7da515 1234 ++tx_ring->tx_stats.restart_queue;
30eba97a 1235 }
e092be60 1236 }
9a799d71 1237
59224555 1238 return !!budget;
9a799d71
AK		 1239}
1240
5dd2d332 1241#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1242static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1243 struct ixgbe_ring *tx_ring,
33cf09c9 1244 int cpu)
bd0362dd 1245{
33cf09c9 1246 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1247 u32 txctrl = 0;
bdda1a61 1248 u16 reg_offset;
33cf09c9 1249
9de7605e
MR		 1250 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1251 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1252
33cf09c9
AD		 1253 switch (hw->mac.type) {
1254 case ixgbe_mac_82598EB:
bdda1a61 1255 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1256 break;
1257 case ixgbe_mac_82599EB:
b93a2226 1258 case ixgbe_mac_X540:
bdda1a61
AD		 1259 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1260 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1261 break;
1262 default:
bdda1a61
AD		 1263 /* for unknown hardware do not write register */
1264 return;
bd0362dd 1265 }
bdda1a61
AD		 1266
1267 /*
1268 * We can enable relaxed ordering for reads, but not writes when
1269 * DCA is enabled. This is due to a known issue in some chipsets
1270 * which will cause the DCA tag to be cleared.
1271 */
1272 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1273 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1274 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1275
1276 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1277}
1278
bdda1a61
AD		 1279static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1280 struct ixgbe_ring *rx_ring,
33cf09c9 1281 int cpu)
bd0362dd 1282{
33cf09c9 1283 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1284 u32 rxctrl = 0;
bdda1a61
AD		 1285 u8 reg_idx = rx_ring->reg_idx;
1286
9de7605e
MR		 1287 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1288 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1289
1290 switch (hw->mac.type) {
33cf09c9 1291 case ixgbe_mac_82599EB:
b93a2226 1292 case ixgbe_mac_X540:
bdda1a61 1293 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1294 break;
1295 default:
1296 break;
1297 }
bdda1a61
AD		 1298
1299 /*
1300 * We can enable relaxed ordering for reads, but not writes when
1301 * DCA is enabled. This is due to a known issue in some chipsets
1302 * which will cause the DCA tag to be cleared.
1303 */
1304 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1305 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1306 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1307
1308 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1309}
1310
1311static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1312{
1313 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1314 struct ixgbe_ring *ring;
bd0362dd 1315 int cpu = get_cpu();
bd0362dd 1316
33cf09c9
AD		 1317 if (q_vector->cpu == cpu)
1318 goto out_no_update;
1319
a557928e 1320 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1321 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1322
a557928e 1323 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1324 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1325
1326 q_vector->cpu = cpu;
1327out_no_update:
bd0362dd
JC		 1328 put_cpu();
1329}
1330
1331static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1332{
1333 int i;
1334
e35ec126 1335 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1336 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1338 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1339 else
1340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1341 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1342
49c7ffbe 1343 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1344 adapter->q_vector[i]->cpu = -1;
1345 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1346 }
1347}
1348
1349static int __ixgbe_notify_dca(struct device *dev, void *data)
1350{
c60fbb00 1351 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1352 unsigned long event = *(unsigned long *)data;
1353
2a72c31e 1354 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1355 return 0;
1356
bd0362dd
JC		 1357 switch (event) {
1358 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1359 /* if we're already enabled, don't do it again */
1360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1361 break;
652f093f 1362 if (dca_add_requester(dev) == 0) {
96b0e0f6 1363 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1365 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1366 break;
1367 }
1368 /* Fall Through since DCA is disabled. */
1369 case DCA_PROVIDER_REMOVE:
1370 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1371 dca_remove_requester(dev);
1372 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1373 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1374 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1375 }
1376 break;
1377 }
1378
652f093f 1379 return 0;
bd0362dd 1380}
67a74ee2 1381
bdda1a61 1382#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1383
1384#define IXGBE_RSS_L4_TYPES_MASK \
1385 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1386 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1387 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1388 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1389
8a0da21b
AD		 1390static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1391 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1392 struct sk_buff *skb)
1393{
7edda4b8
FD		 1394 u16 rss_type;
1395
1396 if (!(ring->netdev->features & NETIF_F_RXHASH))
1397 return;
1398
1399 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1400 IXGBE_RXDADV_RSSTYPE_MASK;
1401
1402 if (!rss_type)
1403 return;
1404
1405 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1406 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1407 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1408}
1409
f800326d 1410#ifdef IXGBE_FCOE
ff886dfc
AD		 1411/**
1412 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1413 * @ring: structure containing ring specific data
ff886dfc
AD		 1414 * @rx_desc: advanced rx descriptor
1415 *
1416 * Returns : true if it is FCoE pkt
1417 */
57efd44c 1418static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1419 union ixgbe_adv_rx_desc *rx_desc)
1420{
1421 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1422
57efd44c 1423 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1424 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1425 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1426 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1427}
1428
f800326d 1429#endif /* IXGBE_FCOE */
e59bd25d
AV		 1430/**
1431 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1432 * @ring: structure containing ring specific data
1433 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1434 * @skb: skb currently being received and modified
1435 **/
8a0da21b 1436static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1437 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1438 struct sk_buff *skb)
9a799d71 1439{
3f207800
DS		 1440 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1441 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1442 bool encap_pkt = false;
1443
8a0da21b 1444 skb_checksum_none_assert(skb);
9a799d71 1445
712744be 1446 /* Rx csum disabled */
8a0da21b 1447 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1448 return;
e59bd25d 1449
3f207800
DS		 1450 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1451 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1452 encap_pkt = true;
1453 skb->encapsulation = 1;
3f207800
DS		 1454 }
1455
e59bd25d 1456 /* if IP and error */
f56e0cb1
AD		 1457 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1458 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1459 ring->rx_stats.csum_err++;
9a799d71
AK		 1460 return;
1461 }
e59bd25d 1462
f56e0cb1 1463 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1464 return;
1465
f56e0cb1 1466 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1467 /*
1468 * 82599 errata, UDP frames with a 0 checksum can be marked as
1469 * checksum errors.
1470 */
8a0da21b
AD		 1471 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1472 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1473 return;
1474
8a0da21b 1475 ring->rx_stats.csum_err++;
e59bd25d
AV		 1476 return;
1477 }
1478
9a799d71 1479 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1480 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1481 if (encap_pkt) {
1482 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1483 return;
1484
1485 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1486 ring->rx_stats.csum_err++;
1487 return;
1488 }
1489 /* If we checked the outer header let the stack know */
1490 skb->csum_level = 1;
1491 }
9a799d71
AK		 1492}
1493
f990b79b
AD		 1494static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1495 struct ixgbe_rx_buffer *bi)
1496{
1497 struct page *page = bi->page;
18cb652a 1498 dma_addr_t dma;
f990b79b 1499
f800326d 1500 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1501 if (likely(page))
f990b79b
AD		 1502 return true;
1503
f800326d 1504 /* alloc new page for storage */
18cb652a
AD		 1505 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1506 if (unlikely(!page)) {
1507 rx_ring->rx_stats.alloc_rx_page_failed++;
1508 return false;
f990b79b
AD		 1509 }
1510
f800326d
AD		 1511 /* map page for use */
1512 dma = dma_map_page(rx_ring->dev, page, 0,
1513 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1514
1515 /*
1516 * if mapping failed free memory back to system since
1517 * there isn't much point in holding memory we can't use
1518 */
1519 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1520 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1521
f990b79b
AD		 1522 rx_ring->rx_stats.alloc_rx_page_failed++;
1523 return false;
1524 }
1525
f800326d 1526 bi->dma = dma;
18cb652a 1527 bi->page = page;
afaa9459 1528 bi->page_offset = 0;
f800326d 1529
f990b79b
AD		 1530 return true;
1531}
1532
9a799d71 1533/**
f990b79b 1534 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1535 * @rx_ring: ring to place buffers on
1536 * @cleaned_count: number of buffers to replace
9a799d71 1537 **/
fc77dc3c 1538void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1539{
9a799d71 1540 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1541 struct ixgbe_rx_buffer *bi;
d5f398ed 1542 u16 i = rx_ring->next_to_use;
9a799d71 1543
f800326d
AD		 1544 /* nothing to do */
1545 if (!cleaned_count)
fc77dc3c
AD		 1546 return;
1547
e4f74028 1548 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1549 bi = &rx_ring->rx_buffer_info[i];
1550 i -= rx_ring->count;
9a799d71 1551
f800326d
AD		 1552 do {
1553 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1554 break;
d5f398ed 1555
f800326d
AD		 1556 /*
1557 * Refresh the desc even if buffer_addrs didn't change
1558 * because each write-back erases this info.
1559 */
1560 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1561
f990b79b
AD		 1562 rx_desc++;
1563 bi++;
9a799d71 1564 i++;
f990b79b 1565 if (unlikely(!i)) {
e4f74028 1566 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1567 bi = rx_ring->rx_buffer_info;
1568 i -= rx_ring->count;
1569 }
1570
18cb652a
AD		 1571 /* clear the status bits for the next_to_use descriptor */
1572 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1573
1574 cleaned_count--;
1575 } while (cleaned_count);
7c6e0a43 1576
f990b79b
AD		 1577 i += rx_ring->count;
1578
ad435ec6
AD		 1579 if (rx_ring->next_to_use != i) {
1580 rx_ring->next_to_use = i;
1581
1582 /* update next to alloc since we have filled the ring */
1583 rx_ring->next_to_alloc = i;
1584
1585 /* Force memory writes to complete before letting h/w
1586 * know there are new descriptors to fetch. (Only
1587 * applicable for weak-ordered memory model archs,
1588 * such as IA-64).
1589 */
1590 wmb();
1591 writel(i, rx_ring->tail);
1592 }
9a799d71
AK		 1593}
1594
1d2024f6
AD		 1595static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1596 struct sk_buff *skb)
1597{
f800326d 1598 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1599
1600 /* set gso_size to avoid messing up TCP MSS */
1601 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1602 IXGBE_CB(skb)->append_cnt);
96be80ab 1603 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1604}
1605
1606static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1607 struct sk_buff *skb)
1608{
1609 /* if append_cnt is 0 then frame is not RSC */
1610 if (!IXGBE_CB(skb)->append_cnt)
1611 return;
1612
1613 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1614 rx_ring->rx_stats.rsc_flush++;
1615
1616 ixgbe_set_rsc_gso_size(rx_ring, skb);
1617
1618 /* gso_size is computed using append_cnt so always clear it last */
1619 IXGBE_CB(skb)->append_cnt = 0;
1620}
1621
8a0da21b
AD		 1622/**
1623 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1624 * @rx_ring: rx descriptor ring packet is being transacted on
1625 * @rx_desc: pointer to the EOP Rx descriptor
1626 * @skb: pointer to current skb being populated
f8212f97 1627 *
8a0da21b
AD		 1628 * This function checks the ring, descriptor, and packet information in
1629 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1630 * other fields within the skb.
f8212f97 1631 **/
8a0da21b
AD		 1632static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1633 union ixgbe_adv_rx_desc *rx_desc,
1634 struct sk_buff *skb)
f8212f97 1635{
43e95f11
JF		 1636 struct net_device *dev = rx_ring->netdev;
1637
8a0da21b
AD		 1638 ixgbe_update_rsc_stats(rx_ring, skb);
1639
1640 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1641
8a0da21b
AD		 1642 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1643
eda183c2
JK		 1644 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1645 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1646
f646968f 1647 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1648 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1649 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1650 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1651 }
1652
8a0da21b 1653 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1654
43e95f11 1655 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1656}
1657
8a0da21b
AD		 1658static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1659 struct sk_buff *skb)
aa80175a 1660{
93f93a44 1661 skb_mark_napi_id(skb, &q_vector->napi);
b4640030 1662 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1663 netif_receive_skb(skb);
8a0da21b 1664 else
856f606e 1665 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1666}
43634e82 1667
f800326d
AD		 1668/**
1669 * ixgbe_is_non_eop - process handling of non-EOP buffers
1670 * @rx_ring: Rx ring being processed
1671 * @rx_desc: Rx descriptor for current buffer
1672 * @skb: Current socket buffer containing buffer in progress
1673 *
1674 * This function updates next to clean. If the buffer is an EOP buffer
1675 * this function exits returning false, otherwise it will place the
1676 * sk_buff in the next buffer to be chained and return true indicating
1677 * that this is in fact a non-EOP buffer.
1678 **/
1679static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1680 union ixgbe_adv_rx_desc *rx_desc,
1681 struct sk_buff *skb)
1682{
1683 u32 ntc = rx_ring->next_to_clean + 1;
1684
1685 /* fetch, update, and store next to clean */
1686 ntc = (ntc < rx_ring->count) ? ntc : 0;
1687 rx_ring->next_to_clean = ntc;
1688
1689 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1690
5a02cbd1
AD		 1691 /* update RSC append count if present */
1692 if (ring_is_rsc_enabled(rx_ring)) {
1693 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1694 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1695
1696 if (unlikely(rsc_enabled)) {
1697 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1698
1699 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1700 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1701
5a02cbd1
AD		 1702 /* update ntc based on RSC value */
1703 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1704 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1705 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1706 }
f800326d
AD		 1707 }
1708
5a02cbd1
AD		 1709 /* if we are the last buffer then there is nothing else to do */
1710 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1711 return false;
1712
f800326d
AD		 1713 /* place skb in next buffer to be received */
1714 rx_ring->rx_buffer_info[ntc].skb = skb;
1715 rx_ring->rx_stats.non_eop_descs++;
1716
1717 return true;
1718}
1719
19861ce2
AD		 1720/**
1721 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1722 * @rx_ring: rx descriptor ring packet is being transacted on
1723 * @skb: pointer to current skb being adjusted
1724 *
1725 * This function is an ixgbe specific version of __pskb_pull_tail. The
1726 * main difference between this version and the original function is that
1727 * this function can make several assumptions about the state of things
1728 * that allow for significant optimizations versus the standard function.
1729 * As a result we can do things like drop a frag and maintain an accurate
1730 * truesize for the skb.
1731 */
1732static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1733 struct sk_buff *skb)
1734{
1735 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1736 unsigned char *va;
1737 unsigned int pull_len;
1738
1739 /*
1740 * it is valid to use page_address instead of kmap since we are
1741 * working with pages allocated out of the lomem pool per
1742 * alloc_page(GFP_ATOMIC)
1743 */
1744 va = skb_frag_address(frag);
1745
1746 /*
1747 * we need the header to contain the greater of either ETH_HLEN or
1748 * 60 bytes if the skb->len is less than 60 for skb_pad.
1749 */
8496e338 1750 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1751
1752 /* align pull length to size of long to optimize memcpy performance */
1753 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1754
1755 /* update all of the pointers */
1756 skb_frag_size_sub(frag, pull_len);
1757 frag->page_offset += pull_len;
1758 skb->data_len -= pull_len;
1759 skb->tail += pull_len;
19861ce2
AD		 1760}
1761
42073d91
AD		 1762/**
1763 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1764 * @rx_ring: rx descriptor ring packet is being transacted on
1765 * @skb: pointer to current skb being updated
1766 *
1767 * This function provides a basic DMA sync up for the first fragment of an
1768 * skb. The reason for doing this is that the first fragment cannot be
1769 * unmapped until we have reached the end of packet descriptor for a buffer
1770 * chain.
1771 */
1772static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1773 struct sk_buff *skb)
1774{
1775 /* if the page was released unmap it, else just sync our portion */
1776 if (unlikely(IXGBE_CB(skb)->page_released)) {
1777 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1778 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1779 IXGBE_CB(skb)->page_released = false;
1780 } else {
1781 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1782
1783 dma_sync_single_range_for_cpu(rx_ring->dev,
1784 IXGBE_CB(skb)->dma,
1785 frag->page_offset,
1786 ixgbe_rx_bufsz(rx_ring),
1787 DMA_FROM_DEVICE);
1788 }
1789 IXGBE_CB(skb)->dma = 0;
1790}
1791
f800326d
AD		 1792/**
1793 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1794 * @rx_ring: rx descriptor ring packet is being transacted on
1795 * @rx_desc: pointer to the EOP Rx descriptor
1796 * @skb: pointer to current skb being fixed
1797 *
1798 * Check for corrupted packet headers caused by senders on the local L2
1799 * embedded NIC switch not setting up their Tx Descriptors right. These
1800 * should be very rare.
1801 *
1802 * Also address the case where we are pulling data in on pages only
1803 * and as such no data is present in the skb header.
1804 *
1805 * In addition if skb is not at least 60 bytes we need to pad it so that
1806 * it is large enough to qualify as a valid Ethernet frame.
1807 *
1808 * Returns true if an error was encountered and skb was freed.
1809 **/
1810static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1811 union ixgbe_adv_rx_desc *rx_desc,
1812 struct sk_buff *skb)
1813{
f800326d 1814 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1815
1816 /* verify that the packet does not have any known errors */
1817 if (unlikely(ixgbe_test_staterr(rx_desc,
1818 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1819 !(netdev->features & NETIF_F_RXALL))) {
1820 dev_kfree_skb_any(skb);
1821 return true;
1822 }
1823
19861ce2 1824 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1825 if (skb_is_nonlinear(skb))
1826 ixgbe_pull_tail(rx_ring, skb);
f800326d 1827
57efd44c
AD		 1828#ifdef IXGBE_FCOE
1829 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1830 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1831 return false;
1832
1833#endif
a94d9e22
AD		 1834 /* if eth_skb_pad returns an error the skb was freed */
1835 if (eth_skb_pad(skb))
1836 return true;
f800326d
AD		 1837
1838 return false;
1839}
1840
f800326d
AD		 1841/**
1842 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1843 * @rx_ring: rx descriptor ring to store buffers on
1844 * @old_buff: donor buffer to have page reused
1845 *
0549ae20 1846 * Synchronizes page for reuse by the adapter
f800326d
AD		 1847 **/
1848static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1849 struct ixgbe_rx_buffer *old_buff)
1850{
1851 struct ixgbe_rx_buffer *new_buff;
1852 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1853
1854 new_buff = &rx_ring->rx_buffer_info[nta];
1855
1856 /* update, and store next to alloc */
1857 nta++;
1858 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1859
1860 /* transfer page from old buffer to new buffer */
18cb652a 1861 *new_buff = *old_buff;
f800326d
AD		 1862
1863 /* sync the buffer for use by the device */
1864 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1865 new_buff->page_offset,
1866 ixgbe_rx_bufsz(rx_ring),
f800326d 1867 DMA_FROM_DEVICE);
f800326d
AD		 1868}
1869
18cb652a
AD		 1870static inline bool ixgbe_page_is_reserved(struct page *page)
1871{
2f064f34 1872 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1873}
1874
f800326d
AD		 1875/**
1876 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1877 * @rx_ring: rx descriptor ring to transact packets on
1878 * @rx_buffer: buffer containing page to add
1879 * @rx_desc: descriptor containing length of buffer written by hardware
1880 * @skb: sk_buff to place the data into
1881 *
0549ae20
AD		 1882 * This function will add the data contained in rx_buffer->page to the skb.
1883 * This is done either through a direct copy if the data in the buffer is
1884 * less than the skb header size, otherwise it will just attach the page as
1885 * a frag to the skb.
1886 *
1887 * The function will then update the page offset if necessary and return
1888 * true if the buffer can be reused by the adapter.
f800326d 1889 **/
0549ae20 1890static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1891 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1892 union ixgbe_adv_rx_desc *rx_desc,
1893 struct sk_buff *skb)
f800326d 1894{
0549ae20
AD		 1895 struct page *page = rx_buffer->page;
1896 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1897#if (PAGE_SIZE < 8192)
0549ae20 1898 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1899#else
1900 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1901 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1902 ixgbe_rx_bufsz(rx_ring);
1903#endif
0549ae20 1904
cf3fe7ac
AD		 1905 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1906 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1907
1908 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1909
18cb652a
AD		 1910 /* page is not reserved, we can reuse buffer as-is */
1911 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1912 return true;
1913
1914 /* this page cannot be reused so discard it */
18cb652a 1915 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1916 return false;
1917 }
1918
0549ae20
AD		 1919 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1920 rx_buffer->page_offset, size, truesize);
1921
09816fbe 1922 /* avoid re-using remote pages */
18cb652a 1923 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1924 return false;
1925
1926#if (PAGE_SIZE < 8192)
1927 /* if we are only owner of page we can reuse it */
1928 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1929 return false;
1930
1931 /* flip page offset to other buffer */
1932 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1933#else
1934 /* move offset up to the next cache line */
1935 rx_buffer->page_offset += truesize;
1936
1937 if (rx_buffer->page_offset > last_offset)
1938 return false;
09816fbe 1939#endif
0549ae20 1940
18cb652a
AD		 1941 /* Even if we own the page, we are not allowed to use atomic_set()
1942 * This would break get_page_unless_zero() users.
1943 */
1944 atomic_inc(&page->_count);
1945
0549ae20 1946 return true;
f800326d
AD		 1947}
1948
18806c9e
AD		 1949static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1950 union ixgbe_adv_rx_desc *rx_desc)
1951{
1952 struct ixgbe_rx_buffer *rx_buffer;
1953 struct sk_buff *skb;
1954 struct page *page;
1955
1956 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1957 page = rx_buffer->page;
1958 prefetchw(page);
1959
1960 skb = rx_buffer->skb;
1961
1962 if (likely(!skb)) {
1963 void *page_addr = page_address(page) +
1964 rx_buffer->page_offset;
1965
1966 /* prefetch first cache line of first page */
1967 prefetch(page_addr);
1968#if L1_CACHE_BYTES < 128
1969 prefetch(page_addr + L1_CACHE_BYTES);
1970#endif
1971
1972 /* allocate a skb to store the frags */
67fd893e
AD		 1973 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1974 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1975 if (unlikely(!skb)) {
1976 rx_ring->rx_stats.alloc_rx_buff_failed++;
1977 return NULL;
1978 }
1979
1980 /*
1981 * we will be copying header into skb->data in
1982 * pskb_may_pull so it is in our interest to prefetch
1983 * it now to avoid a possible cache miss
1984 */
1985 prefetchw(skb->data);
1986
1987 /*
1988 * Delay unmapping of the first packet. It carries the
1989 * header information, HW may still access the header
1990 * after the writeback. Only unmap it when EOP is
1991 * reached
1992 */
1993 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1994 goto dma_sync;
1995
1996 IXGBE_CB(skb)->dma = rx_buffer->dma;
1997 } else {
1998 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1999 ixgbe_dma_sync_frag(rx_ring, skb);
2000
2001dma_sync:
2002 /* we are reusing so sync this buffer for CPU use */
2003 dma_sync_single_range_for_cpu(rx_ring->dev,
2004 rx_buffer->dma,
2005 rx_buffer->page_offset,
2006 ixgbe_rx_bufsz(rx_ring),
2007 DMA_FROM_DEVICE);
18cb652a
AD		 2008
2009 rx_buffer->skb = NULL;
18806c9e
AD		 2010 }
2011
2012 /* pull page into skb */
2013 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2014 /* hand second half of page back to the ring */
2015 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2016 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2017 /* the page has been released from the ring */
2018 IXGBE_CB(skb)->page_released = true;
2019 } else {
2020 /* we are not reusing the buffer so unmap it */
2021 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2022 ixgbe_rx_pg_size(rx_ring),
2023 DMA_FROM_DEVICE);
2024 }
2025
2026 /* clear contents of buffer_info */
18806c9e
AD		 2027 rx_buffer->page = NULL;
2028
2029 return skb;
f800326d
AD		 2030}
2031
2032/**
2033 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2034 * @q_vector: structure containing interrupt and ring information
2035 * @rx_ring: rx descriptor ring to transact packets on
2036 * @budget: Total limit on number of packets to process
2037 *
2038 * This function provides a "bounce buffer" approach to Rx interrupt
2039 * processing. The advantage to this is that on systems that have
2040 * expensive overhead for IOMMU access this provides a means of avoiding
2041 * it by maintaining the mapping of the page to the syste.
2042 *
5a85e737 2043 * Returns amount of work completed
f800326d 2044 **/
5a85e737 2045static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2046 struct ixgbe_ring *rx_ring,
f4de00ed 2047 const int budget)
9a799d71 2048{
d2f4fbe2 2049 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2050#ifdef IXGBE_FCOE
f800326d 2051 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2052 int ddp_bytes;
2053 unsigned int mss = 0;
3d8fd385 2054#endif /* IXGBE_FCOE */
f800326d 2055 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2056
fdabfc8a 2057 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2058 union ixgbe_adv_rx_desc *rx_desc;
2059 struct sk_buff *skb;
f800326d
AD		 2060
2061 /* return some buffers to hardware, one at a time is too slow */
2062 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2063 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2064 cleaned_count = 0;
2065 }
2066
18806c9e 2067 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2068
124b74c1 2069 if (!rx_desc->wb.upper.status_error)
f800326d 2070 break;
9a799d71 2071
124b74c1 2072 /* This memory barrier is needed to keep us from reading
f800326d 2073 * any other fields out of the rx_desc until we know the
124b74c1 2074 * descriptor has been written back
f800326d 2075 */
124b74c1 2076 dma_rmb();
9a799d71 2077
18806c9e
AD		 2078 /* retrieve a buffer from the ring */
2079 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2080
18806c9e
AD		 2081 /* exit if we failed to retrieve a buffer */
2082 if (!skb)
2083 break;
9a799d71 2084
9a799d71 2085 cleaned_count++;
f8212f97 2086
f800326d
AD		 2087 /* place incomplete frames back on ring for completion */
2088 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2089 continue;
c267fc16 2090
f800326d
AD		 2091 /* verify the packet layout is correct */
2092 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2093 continue;
9a799d71 2094
d2f4fbe2
AV		 2095 /* probably a little skewed due to removing CRC */
2096 total_rx_bytes += skb->len;
d2f4fbe2 2097
8a0da21b
AD		 2098 /* populate checksum, timestamp, VLAN, and protocol */
2099 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2100
332d4a7d
YZ		 2101#ifdef IXGBE_FCOE
2102 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2103 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2104 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2105 /* include DDPed FCoE data */
2106 if (ddp_bytes > 0) {
2107 if (!mss) {
2108 mss = rx_ring->netdev->mtu -
2109 sizeof(struct fcoe_hdr) -
2110 sizeof(struct fc_frame_header) -
2111 sizeof(struct fcoe_crc_eof);
2112 if (mss > 512)
2113 mss &= ~511;
2114 }
2115 total_rx_bytes += ddp_bytes;
2116 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2117 mss);
2118 }
63d635b2
AD		 2119 if (!ddp_bytes) {
2120 dev_kfree_skb_any(skb);
f800326d 2121 continue;
63d635b2 2122 }
3d8fd385 2123 }
f800326d 2124
332d4a7d 2125#endif /* IXGBE_FCOE */
8a0da21b 2126 ixgbe_rx_skb(q_vector, skb);
9a799d71 2127
f800326d 2128 /* update budget accounting */
f4de00ed 2129 total_rx_packets++;
fdabfc8a 2130 }
9a799d71 2131
c267fc16
AD		 2132 u64_stats_update_begin(&rx_ring->syncp);
2133 rx_ring->stats.packets += total_rx_packets;
2134 rx_ring->stats.bytes += total_rx_bytes;
2135 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2136 q_vector->rx.total_packets += total_rx_packets;
2137 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2138
5a85e737 2139 return total_rx_packets;
9a799d71
AK		 2140}
2141
e0d1095a 2142#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2143/* must be called with local_bh_disable()d */
2144static int ixgbe_low_latency_recv(struct napi_struct *napi)
2145{
2146 struct ixgbe_q_vector *q_vector =
2147 container_of(napi, struct ixgbe_q_vector, napi);
2148 struct ixgbe_adapter *adapter = q_vector->adapter;
2149 struct ixgbe_ring *ring;
2150 int found = 0;
2151
2152 if (test_bit(__IXGBE_DOWN, &adapter->state))
2153 return LL_FLUSH_FAILED;
2154
2155 if (!ixgbe_qv_lock_poll(q_vector))
2156 return LL_FLUSH_BUSY;
2157
2158 ixgbe_for_each_ring(ring, q_vector->rx) {
2159 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2160#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2161 if (found)
2162 ring->stats.cleaned += found;
2163 else
2164 ring->stats.misses++;
2165#endif
5a85e737
ET		 2166 if (found)
2167 break;
2168 }
2169
2170 ixgbe_qv_unlock_poll(q_vector);
2171
2172 return found;
2173}
e0d1095a 2174#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2175
9a799d71
AK		 2176/**
2177 * ixgbe_configure_msix - Configure MSI-X hardware
2178 * @adapter: board private structure
2179 *
2180 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2181 * interrupts.
2182 **/
2183static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2184{
021230d4 2185 struct ixgbe_q_vector *q_vector;
49c7ffbe 2186 int v_idx;
021230d4 2187 u32 mask;
9a799d71 2188
8e34d1aa
AD		 2189 /* Populate MSIX to EITR Select */
2190 if (adapter->num_vfs > 32) {
2191 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2192 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2193 }
2194
4df10466
JB		 2195 /*
2196 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2197 * corresponding register.
2198 */
49c7ffbe 2199 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2200 struct ixgbe_ring *ring;
7a921c93 2201 q_vector = adapter->q_vector[v_idx];
021230d4 2202
a557928e 2203 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2204 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2205
a557928e 2206 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2207 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2208
fe49f04a 2209 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2210 }
2211
bd508178
AD		 2212 switch (adapter->hw.mac.type) {
2213 case ixgbe_mac_82598EB:
e8e26350 2214 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2215 v_idx);
bd508178
AD		 2216 break;
2217 case ixgbe_mac_82599EB:
b93a2226 2218 case ixgbe_mac_X540:
9a75a1ac
DS		 2219 case ixgbe_mac_X550:
2220 case ixgbe_mac_X550EM_x:
e8e26350 2221 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2222 break;
bd508178
AD		 2223 default:
2224 break;
2225 }
021230d4
AV		 2226 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2227
41fb9248 2228 /* set up to autoclear timer, and the vectors */
021230d4 2229 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2230 mask &= ~(IXGBE_EIMS_OTHER |
2231 IXGBE_EIMS_MAILBOX |
2232 IXGBE_EIMS_LSC);
2233
021230d4 2234 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2235}
2236
f494e8fa
AV		 2237enum latency_range {
2238 lowest_latency = 0,
2239 low_latency = 1,
2240 bulk_latency = 2,
2241 latency_invalid = 255
2242};
2243
2244/**
2245 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2246 * @q_vector: structure containing interrupt and ring information
2247 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2248 *
2249 * Stores a new ITR value based on packets and byte
2250 * counts during the last interrupt. The advantage of per interrupt
2251 * computation is faster updates and more accurate ITR for the current
2252 * traffic pattern. Constants in this function were computed
2253 * based on theoretical maximum wire speed and thresholds were set based
2254 * on testing data as well as attempting to minimize response time
2255 * while increasing bulk throughput.
2256 * this functionality is controlled by the InterruptThrottleRate module
2257 * parameter (see ixgbe_param.c)
2258 **/
bd198058
AD		 2259static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2260 struct ixgbe_ring_container *ring_container)
f494e8fa 2261{
bd198058
AD		 2262 int bytes = ring_container->total_bytes;
2263 int packets = ring_container->total_packets;
2264 u32 timepassed_us;
621bd70e 2265 u64 bytes_perint;
bd198058 2266 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2267
2268 if (packets == 0)
bd198058 2269 return;
f494e8fa
AV		 2270
2271 /* simple throttlerate management
621bd70e
AD		 2272 * 0-10MB/s lowest (100000 ints/s)
2273 * 10-20MB/s low (20000 ints/s)
8ac34f10 2274 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2275 */
2276 /* what was last interrupt timeslice? */
d5bf4f67 2277 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2278 if (timepassed_us == 0)
2279 return;
2280
f494e8fa
AV		 2281 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2282
2283 switch (itr_setting) {
2284 case lowest_latency:
621bd70e 2285 if (bytes_perint > 10)
bd198058 2286 itr_setting = low_latency;
f494e8fa
AV		 2287 break;
2288 case low_latency:
621bd70e 2289 if (bytes_perint > 20)
bd198058 2290 itr_setting = bulk_latency;
621bd70e 2291 else if (bytes_perint <= 10)
bd198058 2292 itr_setting = lowest_latency;
f494e8fa
AV		 2293 break;
2294 case bulk_latency:
621bd70e 2295 if (bytes_perint <= 20)
bd198058 2296 itr_setting = low_latency;
f494e8fa
AV		 2297 break;
2298 }
2299
bd198058
AD		 2300 /* clear work counters since we have the values we need */
2301 ring_container->total_bytes = 0;
2302 ring_container->total_packets = 0;
2303
2304 /* write updated itr to ring container */
2305 ring_container->itr = itr_setting;
f494e8fa
AV		 2306}
2307
509ee935
JB		 2308/**
2309 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2310 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2311 *
2312 * This function is made to be called by ethtool and by the driver
2313 * when it needs to update EITR registers at runtime. Hardware
2314 * specific quirks/differences are taken care of here.
2315 */
fe49f04a 2316void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2317{
fe49f04a 2318 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2319 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2320 int v_idx = q_vector->v_idx;
5d967eb7 2321 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2322
bd508178
AD		 2323 switch (adapter->hw.mac.type) {
2324 case ixgbe_mac_82598EB:
509ee935
JB		 2325 /* must write high and low 16 bits to reset counter */
2326 itr_reg |= (itr_reg << 16);
bd508178
AD		 2327 break;
2328 case ixgbe_mac_82599EB:
b93a2226 2329 case ixgbe_mac_X540:
9a75a1ac
DS		 2330 case ixgbe_mac_X550:
2331 case ixgbe_mac_X550EM_x:
509ee935
JB		 2332 /*
2333 * set the WDIS bit to not clear the timer bits and cause an
2334 * immediate assertion of the interrupt
2335 */
2336 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2337 break;
2338 default:
2339 break;
509ee935
JB		 2340 }
2341 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2342}
2343
bd198058 2344static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2345{
d5bf4f67 2346 u32 new_itr = q_vector->itr;
bd198058 2347 u8 current_itr;
f494e8fa 2348
bd198058
AD		 2349 ixgbe_update_itr(q_vector, &q_vector->tx);
2350 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2351
08c8833b 2352 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2353
2354 switch (current_itr) {
2355 /* counts and packets in update_itr are dependent on these numbers */
2356 case lowest_latency:
d5bf4f67 2357 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2358 break;
2359 case low_latency:
d5bf4f67 2360 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2361 break;
2362 case bulk_latency:
8ac34f10 2363 new_itr = IXGBE_12K_ITR;
f494e8fa 2364 break;
bd198058
AD		 2365 default:
2366 break;
f494e8fa
AV		 2367 }
2368
d5bf4f67 2369 if (new_itr != q_vector->itr) {
fe49f04a 2370 /* do an exponential smoothing */
d5bf4f67
ET		 2371 new_itr = (10 * new_itr * q_vector->itr) /
2372 ((9 * new_itr) + q_vector->itr);
509ee935 2373
bd198058 2374 /* save the algorithm value here */
5d967eb7 2375 q_vector->itr = new_itr;
fe49f04a
AD		 2376
2377 ixgbe_write_eitr(q_vector);
f494e8fa 2378 }
f494e8fa
AV		 2379}
2380
119fc60a 2381/**
de88eeeb 2382 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2383 * @adapter: pointer to adapter
119fc60a 2384 **/
f0f9778d 2385static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2386{
119fc60a
MC		 2387 struct ixgbe_hw *hw = &adapter->hw;
2388 u32 eicr = adapter->interrupt_event;
2389
f0f9778d 2390 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2391 return;
2392
f0f9778d
AD		 2393 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2394 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2395 return;
2396
2397 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2398
7ca647bd 2399 switch (hw->device_id) {
f0f9778d
AD		 2400 case IXGBE_DEV_ID_82599_T3_LOM:
2401 /*
2402 * Since the warning interrupt is for both ports
2403 * we don't have to check if:
2404 * - This interrupt wasn't for our port.
2405 * - We may have missed the interrupt so always have to
2406 * check if we got a LSC
2407 */
9a900eca 2408 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2409 !(eicr & IXGBE_EICR_LSC))
2410 return;
2411
2412 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2413 u32 speed;
f0f9778d 2414 bool link_up = false;
7ca647bd 2415
3d292265 2416 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2417
f0f9778d
AD		 2418 if (link_up)
2419 return;
2420 }
2421
2422 /* Check if this is not due to overtemp */
2423 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2424 return;
2425
2426 break;
7ca647bd 2427 default:
597f22d6
DS		 2428 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2429 return;
9a900eca 2430 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2431 return;
7ca647bd 2432 break;
119fc60a 2433 }
f44e751b 2434 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2435
2436 adapter->interrupt_event = 0;
119fc60a
MC		 2437}
2438
0befdb3e
JB		 2439static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2440{
2441 struct ixgbe_hw *hw = &adapter->hw;
2442
2443 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2444 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2445 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2446 /* write to clear the interrupt */
9a900eca 2447 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2448 }
2449}
cf8280ee 2450
4f51bf70
JK		 2451static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2452{
9a900eca
DS		 2453 struct ixgbe_hw *hw = &adapter->hw;
2454
4f51bf70
JK		 2455 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2456 return;
2457
2458 switch (adapter->hw.mac.type) {
2459 case ixgbe_mac_82599EB:
2460 /*
2461 * Need to check link state so complete overtemp check
2462 * on service task
2463 */
9a900eca
DS		 2464 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2465 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2466 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2467 adapter->interrupt_event = eicr;
2468 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2469 ixgbe_service_event_schedule(adapter);
2470 return;
2471 }
2472 return;
2473 case ixgbe_mac_X540:
2474 if (!(eicr & IXGBE_EICR_TS))
2475 return;
2476 break;
2477 default:
2478 return;
2479 }
2480
f44e751b 2481 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2482}
2483
45788d2a
DS		 2484static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2485{
2486 switch (hw->mac.type) {
2487 case ixgbe_mac_82598EB:
2488 if (hw->phy.type == ixgbe_phy_nl)
2489 return true;
2490 return false;
2491 case ixgbe_mac_82599EB:
2492 case ixgbe_mac_X550EM_x:
2493 switch (hw->mac.ops.get_media_type(hw)) {
2494 case ixgbe_media_type_fiber:
2495 case ixgbe_media_type_fiber_qsfp:
2496 return true;
2497 default:
2498 return false;
2499 }
2500 default:
2501 return false;
2502 }
2503}
2504
e8e26350
PW		 2505static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2506{
2507 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2508 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2509
4ccc650c
DS		 2510 if (!ixgbe_is_sfp(hw))
2511 return;
2512
2513 /* Later MAC's use different SDP */
2514 if (hw->mac.type >= ixgbe_mac_X540)
2515 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2516
2517 if (eicr & eicr_mask) {
73c4b7cd 2518 /* Clear the interrupt */
4ccc650c 2519 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2520 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2521 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2522 adapter->sfp_poll_time = 0;
7086400d
AD		 2523 ixgbe_service_event_schedule(adapter);
2524 }
73c4b7cd
AD		 2525 }
2526
4ccc650c
DS		 2527 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2528 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2529 /* Clear the interrupt */
9a900eca 2530 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2531 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2532 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2533 ixgbe_service_event_schedule(adapter);
2534 }
e8e26350
PW		 2535 }
2536}
2537
cf8280ee
JB		 2538static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2539{
2540 struct ixgbe_hw *hw = &adapter->hw;
2541
2542 adapter->lsc_int++;
2543 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2544 adapter->link_check_timeout = jiffies;
2545 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2546 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2547 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2548 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2549 }
2550}
2551
fe49f04a
AD		 2552static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2553 u64 qmask)
2554{
2555 u32 mask;
bd508178 2556 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2557
bd508178
AD		 2558 switch (hw->mac.type) {
2559 case ixgbe_mac_82598EB:
fe49f04a 2560 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2561 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2562 break;
2563 case ixgbe_mac_82599EB:
b93a2226 2564 case ixgbe_mac_X540:
9a75a1ac
DS		 2565 case ixgbe_mac_X550:
2566 case ixgbe_mac_X550EM_x:
fe49f04a 2567 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2568 if (mask)
2569 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2570 mask = (qmask >> 32);
bd508178
AD		 2571 if (mask)
2572 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2573 break;
2574 default:
2575 break;
fe49f04a
AD		 2576 }
2577 /* skip the flush */
2578}
2579
2580static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2581 u64 qmask)
fe49f04a
AD		 2582{
2583 u32 mask;
bd508178 2584 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2585
bd508178
AD		 2586 switch (hw->mac.type) {
2587 case ixgbe_mac_82598EB:
fe49f04a 2588 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2589 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2590 break;
2591 case ixgbe_mac_82599EB:
b93a2226 2592 case ixgbe_mac_X540:
9a75a1ac
DS		 2593 case ixgbe_mac_X550:
2594 case ixgbe_mac_X550EM_x:
fe49f04a 2595 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2596 if (mask)
2597 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2598 mask = (qmask >> 32);
bd508178
AD		 2599 if (mask)
2600 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2601 break;
2602 default:
2603 break;
fe49f04a
AD		 2604 }
2605 /* skip the flush */
2606}
2607
021230d4 2608/**
2c4af694
AD		 2609 * ixgbe_irq_enable - Enable default interrupt generation settings
2610 * @adapter: board private structure
021230d4 2611 **/
2c4af694
AD		 2612static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2613 bool flush)
9a799d71 2614{
9a900eca 2615 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2616 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2617
2c4af694
AD		 2618 /* don't reenable LSC while waiting for link */
2619 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2620 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2621
2c4af694 2622 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2623 switch (adapter->hw.mac.type) {
2624 case ixgbe_mac_82599EB:
9a900eca 2625 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2626 break;
2627 case ixgbe_mac_X540:
9a75a1ac
DS		 2628 case ixgbe_mac_X550:
2629 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2630 mask |= IXGBE_EIMS_TS;
2631 break;
2632 default:
2633 break;
2634 }
2c4af694 2635 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2636 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2637 switch (adapter->hw.mac.type) {
2638 case ixgbe_mac_82599EB:
9a900eca
DS		 2639 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2640 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2641 /* fall through */
858bc081 2642 case ixgbe_mac_X540:
9a75a1ac
DS		 2643 case ixgbe_mac_X550:
2644 case ixgbe_mac_X550EM_x:
cbd45ec7
MR		 2645 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2646 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2647 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2648 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2649 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2650 mask |= IXGBE_EIMS_MAILBOX;
2651 break;
2652 default:
2653 break;
9a799d71 2654 }
db0677fa 2655
2c4af694
AD		 2656 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2657 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2658 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2659
2c4af694
AD		 2660 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2661 if (queues)
2662 ixgbe_irq_enable_queues(adapter, ~0);
2663 if (flush)
2664 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2665}
2666
2c4af694 2667static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2668{
a65151ba 2669 struct ixgbe_adapter *adapter = data;
9a799d71 2670 struct ixgbe_hw *hw = &adapter->hw;
54037505 2671 u32 eicr;
91281fd3 2672
54037505
DS		 2673 /*
2674 * Workaround for Silicon errata. Use clear-by-write instead
2675 * of clear-by-read. Reading with EICS will return the
2676 * interrupt causes without clearing, which later be done
2677 * with the write to EICR.
2678 */
2679 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2680
2681 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2682 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2683 * the bits are high when ixgbe_msix_other is called. There is a race
2684 * condition otherwise which results in possible performance loss
2685 * especially if the ixgbe_msix_other interrupt is triggering
2686 * consistently (as it would when PPS is turned on for the X540 device)
2687 */
2688 eicr &= 0xFFFF0000;
2689
54037505 2690 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2691
cf8280ee
JB		 2692 if (eicr & IXGBE_EICR_LSC)
2693 ixgbe_check_lsc(adapter);
f0848276 2694
1cdd1ec8
GR		 2695 if (eicr & IXGBE_EICR_MAILBOX)
2696 ixgbe_msg_task(adapter);
efe3d3c8 2697
bd508178
AD		 2698 switch (hw->mac.type) {
2699 case ixgbe_mac_82599EB:
b93a2226 2700 case ixgbe_mac_X540:
9a75a1ac
DS		 2701 case ixgbe_mac_X550:
2702 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2703 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2704 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2705 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2706 ixgbe_service_event_schedule(adapter);
2707 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2708 IXGBE_EICR_GPI_SDP0_X540);
2709 }
d773ce2d
DS		 2710 if (eicr & IXGBE_EICR_ECC) {
2711 e_info(link, "Received ECC Err, initiating reset\n");
2712 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2713 ixgbe_service_event_schedule(adapter);
2714 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2715 }
c4cf55e5
PWJ		 2716 /* Handle Flow Director Full threshold interrupt */
2717 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2718 int reinit_count = 0;
c4cf55e5 2719 int i;
c4cf55e5 2720 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2721 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2722 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2723 &ring->state))
2724 reinit_count++;
2725 }
2726 if (reinit_count) {
2727 /* no more flow director interrupts until after init */
2728 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2729 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2730 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2731 }
2732 }
f0f9778d 2733 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2734 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2735 break;
2736 default:
2737 break;
c4cf55e5 2738 }
f0848276 2739
bd508178 2740 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2741
db0677fa
JK		 2742 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2743 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2744
7086400d 2745 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2746 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2747 ixgbe_irq_enable(adapter, false, false);
f0848276 2748
9a799d71 2749 return IRQ_HANDLED;
f0848276 2750}
91281fd3 2751
4ff7fb12 2752static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2753{
021230d4 2754 struct ixgbe_q_vector *q_vector = data;
91281fd3 2755
9b471446 2756 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2757
4ff7fb12 2758 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 2759 napi_schedule_irqoff(&q_vector->napi);
91281fd3 2760
9a799d71 2761 return IRQ_HANDLED;
91281fd3
AD		 2762}
2763
eb01b975
AD		 2764/**
2765 * ixgbe_poll - NAPI Rx polling callback
2766 * @napi: structure for representing this polling device
2767 * @budget: how many packets driver is allowed to clean
2768 *
2769 * This function is used for legacy and MSI, NAPI mode
2770 **/
8af3c33f 2771int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2772{
2773 struct ixgbe_q_vector *q_vector =
2774 container_of(napi, struct ixgbe_q_vector, napi);
2775 struct ixgbe_adapter *adapter = q_vector->adapter;
2776 struct ixgbe_ring *ring;
32b3e08f 2777 int per_ring_budget, work_done = 0;
eb01b975
AD		 2778 bool clean_complete = true;
2779
2780#ifdef CONFIG_IXGBE_DCA
2781 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2782 ixgbe_update_dca(q_vector);
2783#endif
2784
2785 ixgbe_for_each_ring(ring, q_vector->tx)
2786 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2787
5d6002b7
AD		 2788 /* Exit if we are called by netpoll or busy polling is active */
2789 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
5a85e737
ET		 2790 return budget;
2791
eb01b975
AD		 2792 /* attempt to distribute budget to each queue fairly, but don't allow
2793 * the budget to go below 1 because we'll exit polling */
2794 if (q_vector->rx.count > 1)
2795 per_ring_budget = max(budget/q_vector->rx.count, 1);
2796 else
2797 per_ring_budget = budget;
2798
32b3e08f
JB		 2799 ixgbe_for_each_ring(ring, q_vector->rx) {
2800 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2801 per_ring_budget);
2802
2803 work_done += cleaned;
2804 clean_complete &= (cleaned < per_ring_budget);
2805 }
eb01b975 2806
5a85e737 2807 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2808 /* If all work not completed, return budget and keep polling */
2809 if (!clean_complete)
2810 return budget;
2811
2812 /* all work done, exit the polling mode */
32b3e08f 2813 napi_complete_done(napi, work_done);
eb01b975
AD		 2814 if (adapter->rx_itr_setting & 1)
2815 ixgbe_set_itr(q_vector);
2816 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2817 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2818
2819 return 0;
2820}
2821
021230d4
AV		 2822/**
2823 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2824 * @adapter: board private structure
2825 *
2826 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2827 * interrupts from the kernel.
2828 **/
2829static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2830{
2831 struct net_device *netdev = adapter->netdev;
207867f5 2832 int vector, err;
e8e9f696 2833 int ri = 0, ti = 0;
021230d4 2834
49c7ffbe 2835 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2836 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2837 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2838
4ff7fb12 2839 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2840 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2841 "%s-%s-%d", netdev->name, "TxRx", ri++);
2842 ti++;
2843 } else if (q_vector->rx.ring) {
9fe93afd 2844 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2845 "%s-%s-%d", netdev->name, "rx", ri++);
2846 } else if (q_vector->tx.ring) {
9fe93afd 2847 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2848 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2849 } else {
2850 /* skip this unused q_vector */
2851 continue;
32aa77a4 2852 }
207867f5
AD		 2853 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2854 q_vector->name, q_vector);
9a799d71 2855 if (err) {
396e799c 2856 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2857 "Error: %d\n", err);
021230d4 2858 goto free_queue_irqs;
9a799d71 2859 }
207867f5
AD		 2860 /* If Flow Director is enabled, set interrupt affinity */
2861 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2862 /* assign the mask for this irq */
2863 irq_set_affinity_hint(entry->vector,
de88eeeb 2864 &q_vector->affinity_mask);
207867f5 2865 }
9a799d71
AK		 2866 }
2867
021230d4 2868 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2869 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2870 if (err) {
de88eeeb 2871 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2872 goto free_queue_irqs;
9a799d71
AK		 2873 }
2874
9a799d71
AK		 2875 return 0;
2876
021230d4 2877free_queue_irqs:
207867f5
AD		 2878 while (vector) {
2879 vector--;
2880 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2881 NULL);
2882 free_irq(adapter->msix_entries[vector].vector,
2883 adapter->q_vector[vector]);
2884 }
021230d4
AV		 2885 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2886 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2887 kfree(adapter->msix_entries);
2888 adapter->msix_entries = NULL;
9a799d71
AK		 2889 return err;
2890}
2891
2892/**
021230d4 2893 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2894 * @irq: interrupt number
2895 * @data: pointer to a network interface device structure
9a799d71
AK		 2896 **/
2897static irqreturn_t ixgbe_intr(int irq, void *data)
2898{
a65151ba 2899 struct ixgbe_adapter *adapter = data;
9a799d71 2900 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2901 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2902 u32 eicr;
2903
54037505 2904 /*
24ddd967 2905 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2906 * before the read of EICR.
2907 */
2908 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2909
021230d4 2910 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2911 * therefore no explicit interrupt disable is necessary */
021230d4 2912 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2913 if (!eicr) {
6af3b9eb
ET		 2914 /*
2915 * shared interrupt alert!
f47cf66e 2916 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2917 * have disabled interrupts due to EIAM
2918 * finish the workaround of silicon errata on 82598. Unmask
2919 * the interrupt that we masked before the EICR read.
2920 */
2921 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2922 ixgbe_irq_enable(adapter, true, true);
9a799d71 2923 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2924 }
9a799d71 2925
cf8280ee
JB		 2926 if (eicr & IXGBE_EICR_LSC)
2927 ixgbe_check_lsc(adapter);
021230d4 2928
bd508178
AD		 2929 switch (hw->mac.type) {
2930 case ixgbe_mac_82599EB:
e8e26350 2931 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2932 /* Fall through */
2933 case ixgbe_mac_X540:
9a75a1ac
DS		 2934 case ixgbe_mac_X550:
2935 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2936 if (eicr & IXGBE_EICR_ECC) {
2937 e_info(link, "Received ECC Err, initiating reset\n");
2938 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2939 ixgbe_service_event_schedule(adapter);
2940 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2941 }
4f51bf70 2942 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2943 break;
2944 default:
2945 break;
2946 }
e8e26350 2947
0befdb3e 2948 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2949 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2950 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2951
b9f6ed2b 2952 /* would disable interrupts here but EIAM disabled it */
ef2662b2 2953 napi_schedule_irqoff(&q_vector->napi);
9a799d71 2954
6af3b9eb
ET		 2955 /*
2956 * re-enable link(maybe) and non-queue interrupts, no flush.
2957 * ixgbe_poll will re-enable the queue interrupts
2958 */
6af3b9eb
ET		 2959 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2960 ixgbe_irq_enable(adapter, false, false);
2961
9a799d71
AK		 2962 return IRQ_HANDLED;
2963}
2964
2965/**
2966 * ixgbe_request_irq - initialize interrupts
2967 * @adapter: board private structure
2968 *
2969 * Attempts to configure interrupts using the best available
2970 * capabilities of the hardware and kernel.
2971 **/
021230d4 2972static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2973{
2974 struct net_device *netdev = adapter->netdev;
021230d4 2975 int err;
9a799d71 2976
4cc6df29 2977 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2978 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2979 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2980 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2981 netdev->name, adapter);
4cc6df29 2982 else
a0607fd3 2983 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2984 netdev->name, adapter);
9a799d71 2985
de88eeeb 2986 if (err)
396e799c 2987 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2988
9a799d71
AK		 2989 return err;
2990}
2991
2992static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2993{
49c7ffbe 2994 int vector;
9a799d71 2995
49c7ffbe
AD		 2996 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2997 free_irq(adapter->pdev->irq, adapter);
2998 return;
2999 }
4cc6df29 3000
49c7ffbe
AD		 3001 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3002 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3003 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3004
49c7ffbe
AD		 3005 /* free only the irqs that were actually requested */
3006 if (!q_vector->rx.ring && !q_vector->tx.ring)
3007 continue;
207867f5 3008
49c7ffbe
AD		 3009 /* clear the affinity_mask in the IRQ descriptor */
3010 irq_set_affinity_hint(entry->vector, NULL);
3011
3012 free_irq(entry->vector, q_vector);
9a799d71 3013 }
49c7ffbe
AD		 3014
3015 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3016}
3017
22d5a71b
JB		 3018/**
3019 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3020 * @adapter: board private structure
3021 **/
3022static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3023{
bd508178
AD		 3024 switch (adapter->hw.mac.type) {
3025 case ixgbe_mac_82598EB:
835462fc 3026 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3027 break;
3028 case ixgbe_mac_82599EB:
b93a2226 3029 case ixgbe_mac_X540:
9a75a1ac
DS		 3030 case ixgbe_mac_X550:
3031 case ixgbe_mac_X550EM_x:
835462fc
NS		 3032 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3035 break;
3036 default:
3037 break;
22d5a71b
JB		 3038 }
3039 IXGBE_WRITE_FLUSH(&adapter->hw);
3040 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3041 int vector;
3042
3043 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3044 synchronize_irq(adapter->msix_entries[vector].vector);
3045
3046 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3047 } else {
3048 synchronize_irq(adapter->pdev->irq);
3049 }
3050}
3051
9a799d71
AK		 3052/**
3053 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3054 *
3055 **/
3056static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3057{
d5bf4f67 3058 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3059
d5bf4f67 3060 ixgbe_write_eitr(q_vector);
9a799d71 3061
e8e26350
PW		 3062 ixgbe_set_ivar(adapter, 0, 0, 0);
3063 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3064
396e799c 3065 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3066}
3067
43e69bf0
AD		 3068/**
3069 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3070 * @adapter: board private structure
3071 * @ring: structure containing ring specific data
3072 *
3073 * Configure the Tx descriptor ring after a reset.
3074 **/
84418e3b
AD		 3075void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3076 struct ixgbe_ring *ring)
43e69bf0
AD		 3077{
3078 struct ixgbe_hw *hw = &adapter->hw;
3079 u64 tdba = ring->dma;
2f1860b8 3080 int wait_loop = 10;
b88c6de2 3081 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3082 u8 reg_idx = ring->reg_idx;
43e69bf0 3083
2f1860b8 3084 /* disable queue to avoid issues while updating state */
b88c6de2 3085 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3086 IXGBE_WRITE_FLUSH(hw);
3087
43e69bf0 3088 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3089 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3090 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3091 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3092 ring->count * sizeof(union ixgbe_adv_tx_desc));
3093 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3094 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3095 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3096
b88c6de2
AD		 3097 /*
3098 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3099 * higher than 1 when:
3100 * - ITR is 0 as it could cause false TX hangs
3101 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3102 *
3103 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3104 * to or less than the number of on chip descriptors, which is
3105 * currently 40.
3106 */
67da097e 3107 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3108 txdctl |= (1 << 16); /* WTHRESH = 1 */
3109 else
3110 txdctl |= (8 << 16); /* WTHRESH = 8 */
3111
e954b374
AD		 3112 /*
3113 * Setting PTHRESH to 32 both improves performance
3114 * and avoids a TX hang with DFP enabled
3115 */
b88c6de2
AD		 3116 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3117 32; /* PTHRESH = 32 */
2f1860b8
AD		 3118
3119 /* reinitialize flowdirector state */
39cb681b 3120 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3121 ring->atr_sample_rate = adapter->atr_sample_rate;
3122 ring->atr_count = 0;
3123 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3124 } else {
3125 ring->atr_sample_rate = 0;
3126 }
2f1860b8 3127
fd786b7b
AD		 3128 /* initialize XPS */
3129 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3130 struct ixgbe_q_vector *q_vector = ring->q_vector;
3131
3132 if (q_vector)
2a47fa45 3133 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3134 &q_vector->affinity_mask,
3135 ring->queue_index);
3136 }
3137
c84d324c
JF		 3138 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3139
2f1860b8 3140 /* enable queue */
2f1860b8
AD		 3141 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3142
3143 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3144 if (hw->mac.type == ixgbe_mac_82598EB &&
3145 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3146 return;
3147
3148 /* poll to verify queue is enabled */
3149 do {
032b4325 3150 usleep_range(1000, 2000);
2f1860b8
AD		 3151 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3152 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3153 if (!wait_loop)
3154 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3155}
3156
120ff942
AD		 3157static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3158{
3159 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3160 u32 rttdcs, mtqc;
8b1c0b24 3161 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3162
3163 if (hw->mac.type == ixgbe_mac_82598EB)
3164 return;
3165
3166 /* disable the arbiter while setting MTQC */
3167 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3168 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3169 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3170
3171 /* set transmit pool layout */
671c0adb
AD		 3172 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3173 mtqc = IXGBE_MTQC_VT_ENA;
3174 if (tcs > 4)
3175 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3176 else if (tcs > 1)
3177 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3178 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3179 mtqc |= IXGBE_MTQC_32VF;
3180 else
3181 mtqc |= IXGBE_MTQC_64VF;
3182 } else {
3183 if (tcs > 4)
3184 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3185 else if (tcs > 1)
3186 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3187 else
671c0adb
AD		 3188 mtqc = IXGBE_MTQC_64Q_1PB;
3189 }
120ff942 3190
671c0adb 3191 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3192
671c0adb
AD		 3193 /* Enable Security TX Buffer IFG for multiple pb */
3194 if (tcs) {
3195 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3196 sectx |= IXGBE_SECTX_DCB;
3197 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3198 }
3199
3200 /* re-enable the arbiter */
3201 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3202 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3203}
3204
9a799d71 3205/**
3a581073 3206 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3207 * @adapter: board private structure
3208 *
3209 * Configure the Tx unit of the MAC after a reset.
3210 **/
3211static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3212{
2f1860b8
AD		 3213 struct ixgbe_hw *hw = &adapter->hw;
3214 u32 dmatxctl;
43e69bf0 3215 u32 i;
9a799d71 3216
2f1860b8
AD		 3217 ixgbe_setup_mtqc(adapter);
3218
3219 if (hw->mac.type != ixgbe_mac_82598EB) {
3220 /* DMATXCTL.EN must be before Tx queues are enabled */
3221 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3222 dmatxctl |= IXGBE_DMATXCTL_TE;
3223 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3224 }
3225
9a799d71 3226 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3227 for (i = 0; i < adapter->num_tx_queues; i++)
3228 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3229}
3230
3ebe8fde
AD		 3231static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3232 struct ixgbe_ring *ring)
3233{
3234 struct ixgbe_hw *hw = &adapter->hw;
3235 u8 reg_idx = ring->reg_idx;
3236 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3237
3238 srrctl |= IXGBE_SRRCTL_DROP_EN;
3239
3240 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3241}
3242
3243static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3244 struct ixgbe_ring *ring)
3245{
3246 struct ixgbe_hw *hw = &adapter->hw;
3247 u8 reg_idx = ring->reg_idx;
3248 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3249
3250 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3251
3252 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3253}
3254
3255#ifdef CONFIG_IXGBE_DCB
3256void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3257#else
3258static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3259#endif
3260{
3261 int i;
3262 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3263
3264 if (adapter->ixgbe_ieee_pfc)
3265 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3266
3267 /*
3268 * We should set the drop enable bit if:
3269 * SR-IOV is enabled
3270 * or
3271 * Number of Rx queues > 1 and flow control is disabled
3272 *
3273 * This allows us to avoid head of line blocking for security
3274 * and performance reasons.
3275 */
3276 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3277 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3278 for (i = 0; i < adapter->num_rx_queues; i++)
3279 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3280 } else {
3281 for (i = 0; i < adapter->num_rx_queues; i++)
3282 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3283 }
3284}
3285
e8e26350 3286#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3287
a6616b42 3288static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3289 struct ixgbe_ring *rx_ring)
cc41ac7c 3290{
45e9baa5 3291 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3292 u32 srrctl;
bf29ee6c 3293 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3294
45e9baa5
AD		 3295 if (hw->mac.type == ixgbe_mac_82598EB) {
3296 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3297
45e9baa5
AD		 3298 /*
3299 * if VMDq is not active we must program one srrctl register
3300 * per RSS queue since we have enabled RDRXCTL.MVMEN
3301 */
3302 reg_idx &= mask;
3303 }
cc41ac7c 3304
45e9baa5
AD		 3305 /* configure header buffer length, needed for RSC */
3306 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3307
45e9baa5 3308 /* configure the packet buffer length */
f800326d 3309 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3310
3311 /* configure descriptor type */
f800326d 3312 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3313
45e9baa5 3314 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3315}
9a799d71 3316
dfaf891d 3317/**
a897a2ad 3318 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3319 * @adapter: device handle
3320 *
3321 * - 82598/82599/X540: 128
3322 * - X550(non-SRIOV mode): 512
3323 * - X550(SRIOV mode): 64
3324 */
7f276efb 3325u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3326{
3327 if (adapter->hw.mac.type < ixgbe_mac_X550)
3328 return 128;
3329 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3330 return 64;
3331 else
3332 return 512;
3333}
3334
3335/**
a897a2ad 3336 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3337 * @adapter: device handle
3338 *
3339 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3340 */
1c7cf078 3341void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3342{
dfaf891d 3343 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3344 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3345 u32 reta = 0;
dfaf891d
VZ		 3346 u32 indices_multi;
3347 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3348
0f9b232b 3349 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3350 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3351 * indices.
3352 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3353 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3354 */
3355 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3356 indices_multi = 0x11;
3357 else
3358 indices_multi = 0x1;
3359
dfaf891d
VZ		 3360 /* Write redirection table to HW */
3361 for (i = 0; i < reta_entries; i++) {
3362 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3363 if ((i & 3) == 3) {
3364 if (i < 128)
3365 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3366 else
3367 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3368 reta);
dfaf891d 3369 reta = 0;
0f9b232b
DS		 3370 }
3371 }
3372}
3373
dfaf891d 3374/**
a897a2ad 3375 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3376 * @adapter: device handle
3377 *
3378 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3379 */
3380static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3381{
dfaf891d 3382 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3383 struct ixgbe_hw *hw = &adapter->hw;
3384 u32 vfreta = 0;
dfaf891d
VZ		 3385 unsigned int pf_pool = adapter->num_vfs;
3386
3387 /* Write redirection table to HW */
3388 for (i = 0; i < reta_entries; i++) {
3389 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3390 if ((i & 3) == 3) {
3391 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3392 vfreta);
3393 vfreta = 0;
3394 }
3395 }
3396}
3397
3398static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3399{
3400 struct ixgbe_hw *hw = &adapter->hw;
3401 u32 i, j;
3402 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3403 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3404
3405 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3406 * make full use of any rings they may have. We will use the
3407 * PSRTYPE register to control how many rings we use within the PF.
3408 */
3409 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3410 rss_i = 2;
3411
3412 /* Fill out hash function seeds */
3413 for (i = 0; i < 10; i++)
3414 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3415
3416 /* Fill out redirection table */
3417 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3418
3419 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3420 if (j == rss_i)
3421 j = 0;
3422
3423 adapter->rss_indir_tbl[i] = j;
3424 }
3425
3426 ixgbe_store_reta(adapter);
3427}
3428
3429static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3430{
3431 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3432 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3433 unsigned int pf_pool = adapter->num_vfs;
3434 int i, j;
3435
3436 /* Fill out hash function seeds */
3437 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3438 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3439 adapter->rss_key[i]);
0f9b232b
DS		 3440
3441 /* Fill out the redirection table */
3442 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3443 if (j == rss_i)
05abb126 3444 j = 0;
dfaf891d
VZ		 3445
3446 adapter->rss_indir_tbl[i] = j;
05abb126 3447 }
dfaf891d
VZ		 3448
3449 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3450}
3451
3452static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3453{
3454 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3455 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3456 u32 rxcsum;
0cefafad 3457
05abb126
AD		 3458 /* Disable indicating checksum in descriptor, enables RSS hash */
3459 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3460 rxcsum |= IXGBE_RXCSUM_PCSD;
3461 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3462
671c0adb 3463 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3464 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3465 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3466 } else {
671c0adb
AD		 3467 u8 tcs = netdev_get_num_tc(adapter->netdev);
3468
3469 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3470 if (tcs > 4)
3471 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3472 else if (tcs > 1)
3473 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3474 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3475 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3476 else
671c0adb
AD		 3477 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3478 } else {
3479 if (tcs > 4)
8b1c0b24 3480 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3481 else if (tcs > 1)
3482 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3483 else
3484 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3485 }
0cefafad
JB		 3486 }
3487
05abb126 3488 /* Perform hash on these packet types */
d1b849b9
DS		 3489 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3490 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3491 IXGBE_MRQC_RSS_FIELD_IPV6 |
3492 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3493
ef6afc0c 3494 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3495 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3496 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3497 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3498
dfaf891d 3499 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3500 if ((hw->mac.type >= ixgbe_mac_X550) &&
3501 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3502 unsigned int pf_pool = adapter->num_vfs;
3503
3504 /* Enable VF RSS mode */
3505 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3506 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3507
3508 /* Setup RSS through the VF registers */
dfaf891d 3509 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3510 vfmrqc = IXGBE_MRQC_RSSEN;
3511 vfmrqc |= rss_field;
3512 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3513 } else {
dfaf891d 3514 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3515 mrqc |= rss_field;
3516 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3517 }
0cefafad
JB		 3518}
3519
bb5a9ad2
NS		 3520/**
3521 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3522 * @adapter: address of board private structure
3523 * @index: index of ring to set
bb5a9ad2 3524 **/
082757af 3525static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3526 struct ixgbe_ring *ring)
bb5a9ad2 3527{
bb5a9ad2 3528 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3529 u32 rscctrl;
bf29ee6c 3530 u8 reg_idx = ring->reg_idx;
7367096a 3531
7d637bcc 3532 if (!ring_is_rsc_enabled(ring))
7367096a 3533 return;
bb5a9ad2 3534
7367096a 3535 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3536 rscctrl |= IXGBE_RSCCTL_RSCEN;
3537 /*
3538 * we must limit the number of descriptors so that the
3539 * total size of max desc * buf_len is not greater
642c680e 3540 * than 65536
bb5a9ad2 3541 */
f800326d 3542 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3543 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3544}
3545
9e10e045
AD		 3546#define IXGBE_MAX_RX_DESC_POLL 10
3547static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3548 struct ixgbe_ring *ring)
3549{
3550 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3551 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3552 u32 rxdctl;
bf29ee6c 3553 u8 reg_idx = ring->reg_idx;
9e10e045 3554
b0483c8f
MR		 3555 if (ixgbe_removed(hw->hw_addr))
3556 return;
9e10e045
AD		 3557 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3558 if (hw->mac.type == ixgbe_mac_82598EB &&
3559 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3560 return;
3561
3562 do {
032b4325 3563 usleep_range(1000, 2000);
9e10e045
AD		 3564 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3565 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3566
3567 if (!wait_loop) {
3568 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3569 "the polling period\n", reg_idx);
3570 }
3571}
3572
2d39d576
YZ		 3573void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3574 struct ixgbe_ring *ring)
3575{
3576 struct ixgbe_hw *hw = &adapter->hw;
3577 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3578 u32 rxdctl;
3579 u8 reg_idx = ring->reg_idx;
3580
b0483c8f
MR		 3581 if (ixgbe_removed(hw->hw_addr))
3582 return;
2d39d576
YZ		 3583 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3584 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3585
3586 /* write value back with RXDCTL.ENABLE bit cleared */
3587 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3588
3589 if (hw->mac.type == ixgbe_mac_82598EB &&
3590 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3591 return;
3592
3593 /* the hardware may take up to 100us to really disable the rx queue */
3594 do {
3595 udelay(10);
3596 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3597 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3598
3599 if (!wait_loop) {
3600 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3601 "the polling period\n", reg_idx);
3602 }
3603}
3604
84418e3b
AD		 3605void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3606 struct ixgbe_ring *ring)
acd37177
AD		 3607{
3608 struct ixgbe_hw *hw = &adapter->hw;
3609 u64 rdba = ring->dma;
9e10e045 3610 u32 rxdctl;
bf29ee6c 3611 u8 reg_idx = ring->reg_idx;
acd37177 3612
9e10e045
AD		 3613 /* disable queue to avoid issues while updating state */
3614 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3615 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3616
acd37177
AD		 3617 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3618 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3619 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3620 ring->count * sizeof(union ixgbe_adv_rx_desc));
3621 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3622 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3623 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3624
3625 ixgbe_configure_srrctl(adapter, ring);
3626 ixgbe_configure_rscctl(adapter, ring);
3627
3628 if (hw->mac.type == ixgbe_mac_82598EB) {
3629 /*
3630 * enable cache line friendly hardware writes:
3631 * PTHRESH=32 descriptors (half the internal cache),
3632 * this also removes ugly rx_no_buffer_count increment
3633 * HTHRESH=4 descriptors (to minimize latency on fetch)
3634 * WTHRESH=8 burst writeback up to two cache lines
3635 */
3636 rxdctl &= ~0x3FFFFF;
3637 rxdctl |= 0x080420;
3638 }
3639
3640 /* enable receive descriptor ring */
3641 rxdctl |= IXGBE_RXDCTL_ENABLE;
3642 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3643
3644 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3645 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3646}
3647
48654521
AD		 3648static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3649{
3650 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3651 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3652 u16 pool;
48654521
AD		 3653
3654 /* PSRTYPE must be initialized in non 82598 adapters */
3655 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3656 IXGBE_PSRTYPE_UDPHDR |
3657 IXGBE_PSRTYPE_IPV4HDR |
48654521 3658 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3659 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3660
3661 if (hw->mac.type == ixgbe_mac_82598EB)
3662 return;
3663
fbe7ca7f
AD		 3664 if (rss_i > 3)
3665 psrtype |= 2 << 29;
3666 else if (rss_i > 1)
3667 psrtype |= 1 << 29;
48654521 3668
2a47fa45
JF		 3669 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3670 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3671}
3672
f5b4a52e
AD		 3673static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3674{
3675 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3676 u32 reg_offset, vf_shift;
435b19f6 3677 u32 gcr_ext, vmdctl;
de4c7f65 3678 int i;
f5b4a52e
AD		 3679
3680 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3681 return;
3682
3683 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3684 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3685 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3686 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3687 vmdctl |= IXGBE_VT_CTL_REPLEN;
3688 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3689
1d9c0bfd
AD		 3690 vf_shift = VMDQ_P(0) % 32;
3691 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3692
3693 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3694 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3695 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3696 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3697 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3698 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3699 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3700
3701 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3702 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3703
3704 /*
3705 * Set up VF register offsets for selected VT Mode,
3706 * i.e. 32 or 64 VFs for SR-IOV
3707 */
73079ea0
AD		 3708 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3709 case IXGBE_82599_VMDQ_8Q_MASK:
3710 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3711 break;
3712 case IXGBE_82599_VMDQ_4Q_MASK:
3713 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3714 break;
3715 default:
3716 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3717 break;
3718 }
3719
f5b4a52e
AD		 3720 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3721
435b19f6 3722
a985b6c3 3723 /* Enable MAC Anti-Spoofing */
435b19f6 3724 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3725 adapter->num_vfs);
5b7f000f 3726
f079fa00 3727 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
5b7f000f
DS		 3728 * calling set_ethertype_anti_spoofing for each VF in loop below
3729 */
f079fa00 3730 if (hw->mac.ops.set_ethertype_anti_spoofing) {
5b7f000f 3731 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
f079fa00
ET		 3732 (IXGBE_ETQF_FILTER_EN |
3733 IXGBE_ETQF_TX_ANTISPOOF |
3734 IXGBE_ETH_P_LLDP));
3735
3736 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3737 (IXGBE_ETQF_FILTER_EN |
3738 IXGBE_ETQF_TX_ANTISPOOF |
3739 ETH_P_PAUSE));
3740 }
5b7f000f 3741
de4c7f65
GR		 3742 /* For VFs that have spoof checking turned off */
3743 for (i = 0; i < adapter->num_vfs; i++) {
3744 if (!adapter->vfinfo[i].spoofchk_enabled)
3745 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3746
3747 /* enable ethertype anti spoofing if hw supports it */
3748 if (hw->mac.ops.set_ethertype_anti_spoofing)
3749 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3750
3751 /* Enable/Disable RSS query feature */
3752 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3753 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3754 }
f5b4a52e
AD		 3755}
3756
477de6ed 3757static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3758{
9a799d71
AK		 3759 struct ixgbe_hw *hw = &adapter->hw;
3760 struct net_device *netdev = adapter->netdev;
3761 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3762 struct ixgbe_ring *rx_ring;
3763 int i;
3764 u32 mhadd, hlreg0;
48654521 3765
63f39bd1 3766#ifdef IXGBE_FCOE
477de6ed
AD		 3767 /* adjust max frame to be able to do baby jumbo for FCoE */
3768 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3769 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3770 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3771
477de6ed 3772#endif /* IXGBE_FCOE */
872844dd
AD		 3773
3774 /* adjust max frame to be at least the size of a standard frame */
3775 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3776 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3777
477de6ed
AD		 3778 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3779 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3780 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3781 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3782
3783 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3784 }
3785
3786 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3787 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3788 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3789 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3790
0cefafad
JB		 3791 /*
3792 * Setup the HW Rx Head and Tail Descriptor Pointers and
3793 * the Base and Length of the Rx Descriptor Ring
3794 */
9a799d71 3795 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3796 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3797 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3798 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3799 else
7d637bcc 3800 clear_ring_rsc_enabled(rx_ring);
477de6ed 3801 }
477de6ed
AD		 3802}
3803
7367096a
AD		 3804static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3805{
3806 struct ixgbe_hw *hw = &adapter->hw;
3807 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3808
3809 switch (hw->mac.type) {
3810 case ixgbe_mac_82598EB:
3811 /*
3812 * For VMDq support of different descriptor types or
3813 * buffer sizes through the use of multiple SRRCTL
3814 * registers, RDRXCTL.MVMEN must be set to 1
3815 *
3816 * also, the manual doesn't mention it clearly but DCA hints
3817 * will only use queue 0's tags unless this bit is set. Side
3818 * effects of setting this bit are only that SRRCTL must be
3819 * fully programmed [0..15]
3820 */
3821 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3822 break;
052a1a72
MR		 3823 case ixgbe_mac_X550:
3824 case ixgbe_mac_X550EM_x:
f961ddae
MR		 3825 if (adapter->num_vfs)
3826 rdrxctl |= IXGBE_RDRXCTL_PSP;
3827 /* fall through for older HW */
7367096a 3828 case ixgbe_mac_82599EB:
b93a2226 3829 case ixgbe_mac_X540:
7367096a
AD		 3830 /* Disable RSC for ACK packets */
3831 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3832 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3833 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3834 /* hardware requires some bits to be set by default */
3835 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3836 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3837 break;
3838 default:
3839 /* We should do nothing since we don't know this hardware */
3840 return;
3841 }
3842
3843 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3844}
3845
477de6ed
AD		 3846/**
3847 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3848 * @adapter: board private structure
3849 *
3850 * Configure the Rx unit of the MAC after a reset.
3851 **/
3852static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3853{
3854 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3855 int i;
6dcc28b9 3856 u32 rxctrl, rfctl;
477de6ed
AD		 3857
3858 /* disable receives while setting up the descriptors */
1f9ac57c 3859 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3860
3861 ixgbe_setup_psrtype(adapter);
7367096a 3862 ixgbe_setup_rdrxctl(adapter);
477de6ed 3863
6dcc28b9
JK		 3864 /* RSC Setup */
3865 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3866 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3867 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3868 rfctl |= IXGBE_RFCTL_RSC_DIS;
3869 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3870
9e10e045 3871 /* Program registers for the distribution of queues */
f5b4a52e 3872 ixgbe_setup_mrqc(adapter);
f5b4a52e 3873
477de6ed
AD		 3874 /* set_rx_buffer_len must be called before ring initialization */
3875 ixgbe_set_rx_buffer_len(adapter);
3876
3877 /*
3878 * Setup the HW Rx Head and Tail Descriptor Pointers and
3879 * the Base and Length of the Rx Descriptor Ring
3880 */
9e10e045
AD		 3881 for (i = 0; i < adapter->num_rx_queues; i++)
3882 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3883
1f9ac57c 3884 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3885 /* disable drop enable for 82598 parts */
3886 if (hw->mac.type == ixgbe_mac_82598EB)
3887 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3888
3889 /* enable all receives */
3890 rxctrl |= IXGBE_RXCTRL_RXEN;
3891 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3892}
3893
80d5c368
PM		 3894static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3895 __be16 proto, u16 vid)
068c89b0
DS		 3896{
3897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3898 struct ixgbe_hw *hw = &adapter->hw;
3899
3900 /* add VID to filter table */
1d9c0bfd 3901 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3902 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3903
3904 return 0;
068c89b0
DS		 3905}
3906
80d5c368
PM		 3907static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3908 __be16 proto, u16 vid)
068c89b0
DS		 3909{
3910 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3911 struct ixgbe_hw *hw = &adapter->hw;
3912
068c89b0 3913 /* remove VID from filter table */
1d9c0bfd 3914 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3915 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3916
3917 return 0;
068c89b0
DS		 3918}
3919
f62bbb5e
JG		 3920/**
3921 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3922 * @adapter: driver data
3923 */
3924static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3925{
3926 struct ixgbe_hw *hw = &adapter->hw;
3927 u32 vlnctrl;
5f6c0181
JB		 3928 int i, j;
3929
3930 switch (hw->mac.type) {
3931 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3932 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3933 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3934 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3935 break;
3936 case ixgbe_mac_82599EB:
b93a2226 3937 case ixgbe_mac_X540:
9a75a1ac
DS		 3938 case ixgbe_mac_X550:
3939 case ixgbe_mac_X550EM_x:
5f6c0181 3940 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3941 struct ixgbe_ring *ring = adapter->rx_ring[i];
3942
3943 if (ring->l2_accel_priv)
3944 continue;
3945 j = ring->reg_idx;
5f6c0181
JB		 3946 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3947 vlnctrl &= ~IXGBE_RXDCTL_VME;
3948 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3949 }
3950 break;
3951 default:
3952 break;
3953 }
3954}
3955
3956/**
f62bbb5e 3957 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3958 * @adapter: driver data
3959 */
f62bbb5e 3960static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3961{
3962 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3963 u32 vlnctrl;
5f6c0181
JB		 3964 int i, j;
3965
3966 switch (hw->mac.type) {
3967 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3968 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3969 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3970 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3971 break;
3972 case ixgbe_mac_82599EB:
b93a2226 3973 case ixgbe_mac_X540:
9a75a1ac
DS		 3974 case ixgbe_mac_X550:
3975 case ixgbe_mac_X550EM_x:
5f6c0181 3976 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3977 struct ixgbe_ring *ring = adapter->rx_ring[i];
3978
3979 if (ring->l2_accel_priv)
3980 continue;
3981 j = ring->reg_idx;
5f6c0181
JB		 3982 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3983 vlnctrl |= IXGBE_RXDCTL_VME;
3984 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3985 }
3986 break;
3987 default:
3988 break;
3989 }
3990}
3991
9a799d71
AK		 3992static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3993{
f62bbb5e 3994 u16 vid;
9a799d71 3995
80d5c368 3996 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3997
3998 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3999 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4000}
4001
b335e75b
JK		 4002/**
4003 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4004 * @netdev: network interface device structure
4005 *
4006 * Writes multicast address list to the MTA hash table.
4007 * Returns: -ENOMEM on failure
4008 * 0 on no addresses written
4009 * X on writing X addresses to MTA
4010 **/
4011static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4012{
4013 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4014 struct ixgbe_hw *hw = &adapter->hw;
4015
4016 if (!netif_running(netdev))
4017 return 0;
4018
4019 if (hw->mac.ops.update_mc_addr_list)
4020 hw->mac.ops.update_mc_addr_list(hw, netdev);
4021 else
4022 return -ENOMEM;
4023
4024#ifdef CONFIG_PCI_IOV
5d7daa35 4025 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4026#endif
4027
4028 return netdev_mc_count(netdev);
4029}
4030
5d7daa35
JK		 4031#ifdef CONFIG_PCI_IOV
4032void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4033{
c9f53e63 4034 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4035 struct ixgbe_hw *hw = &adapter->hw;
4036 int i;
c9f53e63
AD		 4037
4038 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4039 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4040
4041 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4042 hw->mac.ops.set_rar(hw, i,
4043 mac_table->addr,
4044 mac_table->pool,
5d7daa35
JK		 4045 IXGBE_RAH_AV);
4046 else
4047 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4048 }
4049}
5d7daa35 4050
c9f53e63 4051#endif
5d7daa35
JK		 4052static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4053{
c9f53e63 4054 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4055 struct ixgbe_hw *hw = &adapter->hw;
4056 int i;
5d7daa35 4057
c9f53e63
AD		 4058 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4059 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4060 continue;
4061
4062 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4063
4064 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4065 hw->mac.ops.set_rar(hw, i,
4066 mac_table->addr,
4067 mac_table->pool,
4068 IXGBE_RAH_AV);
4069 else
4070 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4071 }
4072}
4073
4074static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4075{
c9f53e63 4076 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4077 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4078 int i;
5d7daa35 4079
c9f53e63
AD		 4080 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4081 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4082 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4083 }
c9f53e63 4084
5d7daa35
JK		 4085 ixgbe_sync_mac_table(adapter);
4086}
4087
c9f53e63 4088static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4089{
c9f53e63 4090 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4091 struct ixgbe_hw *hw = &adapter->hw;
4092 int i, count = 0;
4093
c9f53e63
AD		 4094 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4095 /* do not count default RAR as available */
4096 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4097 continue;
4098
4099 /* only count unused and addresses that belong to us */
4100 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4101 if (mac_table->pool != pool)
4102 continue;
4103 }
4104
4105 count++;
5d7daa35 4106 }
c9f53e63 4107
5d7daa35
JK		 4108 return count;
4109}
4110
4111/* this function destroys the first RAR entry */
c9f53e63 4112static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4113{
c9f53e63 4114 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4115 struct ixgbe_hw *hw = &adapter->hw;
4116
c9f53e63
AD		 4117 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4118 mac_table->pool = VMDQ_P(0);
4119
4120 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4121
4122 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4123 IXGBE_RAH_AV);
4124}
4125
c9f53e63
AD		 4126int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4127 const u8 *addr, u16 pool)
5d7daa35 4128{
c9f53e63 4129 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4130 struct ixgbe_hw *hw = &adapter->hw;
4131 int i;
4132
4133 if (is_zero_ether_addr(addr))
4134 return -EINVAL;
4135
c9f53e63
AD		 4136 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4137 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4138 continue;
c9f53e63
AD		 4139
4140 ether_addr_copy(mac_table->addr, addr);
4141 mac_table->pool = pool;
4142
4143 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4144 IXGBE_MAC_STATE_IN_USE;
4145
5d7daa35 4146 ixgbe_sync_mac_table(adapter);
c9f53e63 4147
5d7daa35
JK		 4148 return i;
4149 }
c9f53e63 4150
5d7daa35
JK		 4151 return -ENOMEM;
4152}
4153
c9f53e63
AD		 4154int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4155 const u8 *addr, u16 pool)
5d7daa35 4156{
c9f53e63 4157 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4158 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4159 int i;
5d7daa35
JK		 4160
4161 if (is_zero_ether_addr(addr))
4162 return -EINVAL;
4163
c9f53e63
AD		 4164 /* search table for addr, if found clear IN_USE flag and sync */
4165 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4166 /* we can only delete an entry if it is in use */
4167 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4168 continue;
4169 /* we only care about entries that belong to the given pool */
4170 if (mac_table->pool != pool)
4171 continue;
4172 /* we only care about a specific MAC address */
4173 if (!ether_addr_equal(addr, mac_table->addr))
4174 continue;
4175
4176 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4177 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4178
4179 ixgbe_sync_mac_table(adapter);
4180
4181 return 0;
5d7daa35 4182 }
c9f53e63 4183
5d7daa35
JK		 4184 return -ENOMEM;
4185}
2850062a
AD		 4186/**
4187 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4188 * @netdev: network interface device structure
4189 *
4190 * Writes unicast address list to the RAR table.
4191 * Returns: -ENOMEM on failure/insufficient address space
4192 * 0 on no addresses written
4193 * X on writing X addresses to the RAR table
4194 **/
5d7daa35 4195static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4196{
4197 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4198 int count = 0;
4199
4200 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4201 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4202 return -ENOMEM;
4203
95447461 4204 if (!netdev_uc_empty(netdev)) {
2850062a 4205 struct netdev_hw_addr *ha;
2850062a 4206 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4207 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4208 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4209 count++;
4210 }
4211 }
2850062a
AD		 4212 return count;
4213}
4214
0f079d22
AD		 4215static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4216{
4217 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4218 int ret;
4219
4220 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4221
4222 return min_t(int, ret, 0);
4223}
4224
4225static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4226{
4227 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4228
4229 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4230
4231 return 0;
4232}
4233
9a799d71 4234/**
2c5645cf 4235 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4236 * @netdev: network interface device structure
4237 *
2c5645cf
CL		 4238 * The set_rx_method entry point is called whenever the unicast/multicast
4239 * address list or the network interface flags are updated. This routine is
4240 * responsible for configuring the hardware for proper unicast, multicast and
4241 * promiscuous mode.
9a799d71 4242 **/
7f870475 4243void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4244{
4245 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4246 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4247 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4248 u32 vlnctrl;
2850062a 4249 int count;
9a799d71
AK		 4250
4251 /* Check for Promiscuous and All Multicast modes */
9a799d71 4252 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4253 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4254
f5dc442b 4255 /* set all bits that we expect to always be set */
3f2d1c0f 4256 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4257 fctrl |= IXGBE_FCTRL_BAM;
4258 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4259 fctrl |= IXGBE_FCTRL_PMCF;
4260
2850062a
AD		 4261 /* clear the bits we are changing the status of */
4262 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4263 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4264 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4265 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4266 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4267 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4268 /* Only disable hardware filter vlans in promiscuous mode
4269 * if SR-IOV and VMDQ are disabled - otherwise ensure
4270 * that hardware VLAN filters remain enabled.
4271 */
4556dc59
VY		 4272 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4273 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 4274 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4275 } else {
746b9f02
PM		 4276 if (netdev->flags & IFF_ALLMULTI) {
4277 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4278 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4279 }
a9b8943e 4280 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4281 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4282 }
4283
4284 /*
4285 * Write addresses to available RAR registers, if there is not
4286 * sufficient space to store all the addresses then enable
4287 * unicast promiscuous mode
4288 */
0f079d22 4289 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4290 fctrl |= IXGBE_FCTRL_UPE;
4291 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4292 }
4293
cf78959c
ET		 4294 /* Write addresses to the MTA, if the attempt fails
4295 * then we should just turn on promiscuous mode so
4296 * that we can at least receive multicast traffic
4297 */
b335e75b
JK		 4298 count = ixgbe_write_mc_addr_list(netdev);
4299 if (count < 0) {
4300 fctrl |= IXGBE_FCTRL_MPE;
4301 vmolr |= IXGBE_VMOLR_MPE;
4302 } else if (count) {
4303 vmolr |= IXGBE_VMOLR_ROMPE;
4304 }
1d9c0bfd
AD		 4305
4306 if (hw->mac.type != ixgbe_mac_82598EB) {
4307 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4308 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4309 IXGBE_VMOLR_ROPE);
1d9c0bfd 4310 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4311 }
4312
3f2d1c0f
BG		 4313 /* This is useful for sniffing bad packets. */
4314 if (adapter->netdev->features & NETIF_F_RXALL) {
4315 /* UPE and MPE will be handled by normal PROMISC logic
4316 * in e1000e_set_rx_mode */
4317 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4318 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4319 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4320
4321 fctrl &= ~(IXGBE_FCTRL_DPF);
4322 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4323 }
4324
a9b8943e 4325 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4326 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4327
f646968f 4328 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4329 ixgbe_vlan_strip_enable(adapter);
4330 else
4331 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4332}
4333
021230d4
AV		 4334static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4335{
4336 int q_idx;
021230d4 4337
5a85e737
ET		 4338 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4339 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4340 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4341 }
021230d4
AV		 4342}
4343
4344static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4345{
4346 int q_idx;
021230d4 4347
5a85e737 4348 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4349 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4350 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4351 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4352 usleep_range(1000, 20000);
5a85e737
ET		 4353 }
4354 }
021230d4
AV		 4355}
4356
67359c3c
MR		 4357static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4358{
4359 switch (adapter->hw.mac.type) {
4360 case ixgbe_mac_X550:
4361 case ixgbe_mac_X550EM_x:
4362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4363#ifdef CONFIG_IXGBE_VXLAN
4364 adapter->vxlan_port = 0;
4365#endif
4366 break;
4367 default:
4368 break;
4369 }
4370}
4371
7a6b6f51 4372#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4373/**
2f90b865
AD		 4374 * ixgbe_configure_dcb - Configure DCB hardware
4375 * @adapter: ixgbe adapter struct
4376 *
4377 * This is called by the driver on open to configure the DCB hardware.
4378 * This is also called by the gennetlink interface when reconfiguring
4379 * the DCB state.
4380 */
4381static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4382{
4383 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4384 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4385
67ebd791
AD		 4386 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4387 if (hw->mac.type == ixgbe_mac_82598EB)
4388 netif_set_gso_max_size(adapter->netdev, 65536);
4389 return;
4390 }
4391
4392 if (hw->mac.type == ixgbe_mac_82598EB)
4393 netif_set_gso_max_size(adapter->netdev, 32768);
4394
971060b1 4395#ifdef IXGBE_FCOE
b120818e
JF		 4396 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4397 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4398#endif
b120818e
JF		 4399
4400 /* reconfigure the hardware */
4401 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4402 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4403 DCB_TX_CONFIG);
4404 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4405 DCB_RX_CONFIG);
4406 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4407 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4408 ixgbe_dcb_hw_ets(&adapter->hw,
4409 adapter->ixgbe_ieee_ets,
4410 max_frame);
4411 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4412 adapter->ixgbe_ieee_pfc->pfc_en,
4413 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4414 }
8187cd48
JF		 4415
4416 /* Enable RSS Hash per TC */
4417 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4418 u32 msb = 0;
4419 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4420
d411a936
AD		 4421 while (rss_i) {
4422 msb++;
4423 rss_i >>= 1;
4424 }
8187cd48 4425
4ae63730
AD		 4426 /* write msb to all 8 TCs in one write */
4427 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4428 }
2f90b865 4429}
9da712d2
JF		 4430#endif
4431
4432/* Additional bittime to account for IXGBE framing */
4433#define IXGBE_ETH_FRAMING 20
4434
49ce9c2c 4435/**
9da712d2
JF		 4436 * ixgbe_hpbthresh - calculate high water mark for flow control
4437 *
4438 * @adapter: board private structure to calculate for
49ce9c2c 4439 * @pb: packet buffer to calculate
9da712d2
JF		 4440 */
4441static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4442{
4443 struct ixgbe_hw *hw = &adapter->hw;
4444 struct net_device *dev = adapter->netdev;
4445 int link, tc, kb, marker;
4446 u32 dv_id, rx_pba;
4447
4448 /* Calculate max LAN frame size */
4449 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4450
4451#ifdef IXGBE_FCOE
4452 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4453 if ((dev->features & NETIF_F_FCOE_MTU) &&
4454 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4455 (pb == ixgbe_fcoe_get_tc(adapter)))
4456 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4457#endif
e5776620 4458
9da712d2
JF		 4459 /* Calculate delay value for device */
4460 switch (hw->mac.type) {
4461 case ixgbe_mac_X540:
9a75a1ac
DS		 4462 case ixgbe_mac_X550:
4463 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4464 dv_id = IXGBE_DV_X540(link, tc);
4465 break;
4466 default:
4467 dv_id = IXGBE_DV(link, tc);
4468 break;
4469 }
4470
4471 /* Loopback switch introduces additional latency */
4472 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4473 dv_id += IXGBE_B2BT(tc);
4474
4475 /* Delay value is calculated in bit times convert to KB */
4476 kb = IXGBE_BT2KB(dv_id);
4477 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4478
4479 marker = rx_pba - kb;
4480
4481 /* It is possible that the packet buffer is not large enough
4482 * to provide required headroom. In this case throw an error
4483 * to user and a do the best we can.
4484 */
4485 if (marker < 0) {
4486 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4487 "headroom to support flow control."
4488 "Decrease MTU or number of traffic classes\n", pb);
4489 marker = tc + 1;
4490 }
4491
4492 return marker;
4493}
4494
49ce9c2c 4495/**
9da712d2
JF		 4496 * ixgbe_lpbthresh - calculate low water mark for for flow control
4497 *
4498 * @adapter: board private structure to calculate for
49ce9c2c 4499 * @pb: packet buffer to calculate
9da712d2 4500 */
e5776620 4501static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4502{
4503 struct ixgbe_hw *hw = &adapter->hw;
4504 struct net_device *dev = adapter->netdev;
4505 int tc;
4506 u32 dv_id;
4507
4508 /* Calculate max LAN frame size */
4509 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4510
e5776620
JK		 4511#ifdef IXGBE_FCOE
4512 /* FCoE traffic class uses FCOE jumbo frames */
4513 if ((dev->features & NETIF_F_FCOE_MTU) &&
4514 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4515 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4516 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4517#endif
4518
9da712d2
JF		 4519 /* Calculate delay value for device */
4520 switch (hw->mac.type) {
4521 case ixgbe_mac_X540:
9a75a1ac
DS		 4522 case ixgbe_mac_X550:
4523 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4524 dv_id = IXGBE_LOW_DV_X540(tc);
4525 break;
4526 default:
4527 dv_id = IXGBE_LOW_DV(tc);
4528 break;
4529 }
4530
4531 /* Delay value is calculated in bit times convert to KB */
4532 return IXGBE_BT2KB(dv_id);
4533}
4534
4535/*
4536 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4537 */
4538static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4539{
4540 struct ixgbe_hw *hw = &adapter->hw;
4541 int num_tc = netdev_get_num_tc(adapter->netdev);
4542 int i;
4543
4544 if (!num_tc)
4545 num_tc = 1;
4546
9da712d2
JF		 4547 for (i = 0; i < num_tc; i++) {
4548 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4549 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4550
4551 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4552 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4553 hw->fc.low_water[i] = 0;
9da712d2 4554 }
e5776620
JK		 4555
4556 for (; i < MAX_TRAFFIC_CLASS; i++)
4557 hw->fc.high_water[i] = 0;
9da712d2
JF		 4558}
4559
80605c65
JF		 4560static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4561{
80605c65 4562 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4563 int hdrm;
4564 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4565
4566 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4567 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4568 hdrm = 32 << adapter->fdir_pballoc;
4569 else
4570 hdrm = 0;
80605c65 4571
f7e1027f 4572 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4573 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4574}
4575
e4911d57
AD		 4576static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4577{
4578 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4579 struct hlist_node *node2;
e4911d57
AD		 4580 struct ixgbe_fdir_filter *filter;
4581
4582 spin_lock(&adapter->fdir_perfect_lock);
4583
4584 if (!hlist_empty(&adapter->fdir_filter_list))
4585 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4586
b67bfe0d 4587 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4588 &adapter->fdir_filter_list, fdir_node) {
4589 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4590 &filter->filter,
4591 filter->sw_idx,
4592 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4593 IXGBE_FDIR_DROP_QUEUE :
4594 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4595 }
4596
4597 spin_unlock(&adapter->fdir_perfect_lock);
4598}
4599
2a47fa45
JF		 4600static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4601 struct ixgbe_adapter *adapter)
4602{
4603 struct ixgbe_hw *hw = &adapter->hw;
4604 u32 vmolr;
4605
4606 /* No unicast promiscuous support for VMDQ devices. */
4607 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4608 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4609
4610 /* clear the affected bit */
4611 vmolr &= ~IXGBE_VMOLR_MPE;
4612
4613 if (dev->flags & IFF_ALLMULTI) {
4614 vmolr |= IXGBE_VMOLR_MPE;
4615 } else {
4616 vmolr |= IXGBE_VMOLR_ROMPE;
4617 hw->mac.ops.update_mc_addr_list(hw, dev);
4618 }
5d7daa35 4619 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4620 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4621}
4622
2a47fa45
JF		 4623static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4624{
4625 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4626 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4627 struct ixgbe_hw *hw = &adapter->hw;
4628 u16 pool = vadapter->pool;
4629 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4630 IXGBE_PSRTYPE_UDPHDR |
4631 IXGBE_PSRTYPE_IPV4HDR |
4632 IXGBE_PSRTYPE_L2HDR |
4633 IXGBE_PSRTYPE_IPV6HDR;
4634
4635 if (hw->mac.type == ixgbe_mac_82598EB)
4636 return;
4637
4638 if (rss_i > 3)
4639 psrtype |= 2 << 29;
4640 else if (rss_i > 1)
4641 psrtype |= 1 << 29;
4642
4643 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4644}
4645
4646/**
4647 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4648 * @rx_ring: ring to free buffers from
4649 **/
4650static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4651{
4652 struct device *dev = rx_ring->dev;
4653 unsigned long size;
4654 u16 i;
4655
4656 /* ring already cleared, nothing to do */
4657 if (!rx_ring->rx_buffer_info)
4658 return;
4659
4660 /* Free all the Rx ring sk_buffs */
4661 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4662 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4663
2a47fa45
JF		 4664 if (rx_buffer->skb) {
4665 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4666 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4667 dma_unmap_page(dev,
4668 IXGBE_CB(skb)->dma,
4669 ixgbe_rx_bufsz(rx_ring),
4670 DMA_FROM_DEVICE);
2a47fa45 4671 dev_kfree_skb(skb);
4d2fcfbc 4672 rx_buffer->skb = NULL;
2a47fa45 4673 }
18cb652a
AD		 4674
4675 if (!rx_buffer->page)
4676 continue;
4677
4678 dma_unmap_page(dev, rx_buffer->dma,
4679 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4680 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4681
2a47fa45
JF		 4682 rx_buffer->page = NULL;
4683 }
4684
4685 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4686 memset(rx_ring->rx_buffer_info, 0, size);
4687
4688 /* Zero out the descriptor ring */
4689 memset(rx_ring->desc, 0, rx_ring->size);
4690
4691 rx_ring->next_to_alloc = 0;
4692 rx_ring->next_to_clean = 0;
4693 rx_ring->next_to_use = 0;
4694}
4695
4696static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4697 struct ixgbe_ring *rx_ring)
4698{
4699 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4700 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4701
4702 /* shutdown specific queue receive and wait for dma to settle */
4703 ixgbe_disable_rx_queue(adapter, rx_ring);
4704 usleep_range(10000, 20000);
4705 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4706 ixgbe_clean_rx_ring(rx_ring);
4707 rx_ring->l2_accel_priv = NULL;
4708}
4709
ae72c8d0
JF		 4710static int ixgbe_fwd_ring_down(struct net_device *vdev,
4711 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4712{
4713 struct ixgbe_adapter *adapter = accel->real_adapter;
4714 unsigned int rxbase = accel->rx_base_queue;
4715 unsigned int txbase = accel->tx_base_queue;
4716 int i;
4717
4718 netif_tx_stop_all_queues(vdev);
4719
4720 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4721 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4722 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4723 }
4724
4725 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4726 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4727 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4728 }
4729
4730
4731 return 0;
4732}
4733
4734static int ixgbe_fwd_ring_up(struct net_device *vdev,
4735 struct ixgbe_fwd_adapter *accel)
4736{
4737 struct ixgbe_adapter *adapter = accel->real_adapter;
4738 unsigned int rxbase, txbase, queues;
4739 int i, baseq, err = 0;
4740
4741 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4742 return 0;
4743
4744 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4745 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4746 accel->pool, adapter->num_rx_pools,
4747 baseq, baseq + adapter->num_rx_queues_per_pool,
4748 adapter->fwd_bitmask);
4749
4750 accel->netdev = vdev;
4751 accel->rx_base_queue = rxbase = baseq;
4752 accel->tx_base_queue = txbase = baseq;
4753
4754 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4755 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4756
4757 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4758 adapter->rx_ring[rxbase + i]->netdev = vdev;
4759 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4760 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4761 }
4762
4763 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4764 adapter->tx_ring[txbase + i]->netdev = vdev;
4765 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4766 }
4767
4768 queues = min_t(unsigned int,
4769 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4770 err = netif_set_real_num_tx_queues(vdev, queues);
4771 if (err)
4772 goto fwd_queue_err;
4773
2a47fa45
JF		 4774 err = netif_set_real_num_rx_queues(vdev, queues);
4775 if (err)
4776 goto fwd_queue_err;
4777
4778 if (is_valid_ether_addr(vdev->dev_addr))
4779 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4780
4781 ixgbe_fwd_psrtype(accel);
4782 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4783 return err;
4784fwd_queue_err:
4785 ixgbe_fwd_ring_down(vdev, accel);
4786 return err;
4787}
4788
4789static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4790{
4791 struct net_device *upper;
4792 struct list_head *iter;
4793 int err;
4794
4795 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4796 if (netif_is_macvlan(upper)) {
4797 struct macvlan_dev *dfwd = netdev_priv(upper);
4798 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4799
4800 if (dfwd->fwd_priv) {
4801 err = ixgbe_fwd_ring_up(upper, vadapter);
4802 if (err)
4803 continue;
4804 }
4805 }
4806 }
4807}
4808
9a799d71
AK		 4809static void ixgbe_configure(struct ixgbe_adapter *adapter)
4810{
d2f5e7f3
AS		 4811 struct ixgbe_hw *hw = &adapter->hw;
4812
80605c65 4813 ixgbe_configure_pb(adapter);
7a6b6f51 4814#ifdef CONFIG_IXGBE_DCB
67ebd791 4815 ixgbe_configure_dcb(adapter);
2f90b865 4816#endif
b35d4d42
AD		 4817 /*
4818 * We must restore virtualization before VLANs or else
4819 * the VLVF registers will not be populated
4820 */
4821 ixgbe_configure_virtualization(adapter);
9a799d71 4822
4c1d7b4b 4823 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4824 ixgbe_restore_vlan(adapter);
4825
d2f5e7f3
AS		 4826 switch (hw->mac.type) {
4827 case ixgbe_mac_82599EB:
4828 case ixgbe_mac_X540:
4829 hw->mac.ops.disable_rx_buff(hw);
4830 break;
4831 default:
4832 break;
4833 }
4834
c4cf55e5 4835 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4836 ixgbe_init_fdir_signature_82599(&adapter->hw,
4837 adapter->fdir_pballoc);
e4911d57
AD		 4838 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4839 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4840 adapter->fdir_pballoc);
4841 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4842 }
4c1d7b4b 4843
d2f5e7f3
AS		 4844 switch (hw->mac.type) {
4845 case ixgbe_mac_82599EB:
4846 case ixgbe_mac_X540:
4847 hw->mac.ops.enable_rx_buff(hw);
4848 break;
4849 default:
4850 break;
4851 }
4852
9de7605e
MR		 4853#ifdef CONFIG_IXGBE_DCA
4854 /* configure DCA */
4855 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
4856 ixgbe_setup_dca(adapter);
4857#endif /* CONFIG_IXGBE_DCA */
4858
7c8ae65a
AD		 4859#ifdef IXGBE_FCOE
4860 /* configure FCoE L2 filters, redirection table, and Rx control */
4861 ixgbe_configure_fcoe(adapter);
4862
4863#endif /* IXGBE_FCOE */
9a799d71
AK		 4864 ixgbe_configure_tx(adapter);
4865 ixgbe_configure_rx(adapter);
2a47fa45 4866 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4867}
4868
0ecc061d 4869/**
e8e26350
PW		 4870 * ixgbe_sfp_link_config - set up SFP+ link
4871 * @adapter: pointer to private adapter struct
4872 **/
4873static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4874{
7086400d 4875 /*
52f33af8 4876 * We are assuming the worst case scenario here, and that
7086400d
AD		 4877 * is that an SFP was inserted/removed after the reset
4878 * but before SFP detection was enabled. As such the best
4879 * solution is to just start searching as soon as we start
4880 */
4881 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4882 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4883
7086400d 4884 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 4885 adapter->sfp_poll_time = 0;
e8e26350
PW		 4886}
4887
4888/**
4889 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4890 * @hw: pointer to private hardware struct
4891 *
4892 * Returns 0 on success, negative on failure
4893 **/
e8e26350 4894static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4895{
3d292265
JH		 4896 u32 speed;
4897 bool autoneg, link_up = false;
a1e869de 4898 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 4899
4900 if (hw->mac.ops.check_link)
3d292265 4901 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4902
4903 if (ret)
e90dd264 4904 return ret;
0ecc061d 4905
3d292265
JH		 4906 speed = hw->phy.autoneg_advertised;
4907 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4908 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4909 &autoneg);
0ecc061d 4910 if (ret)
e90dd264 4911 return ret;
0ecc061d 4912
8620a103 4913 if (hw->mac.ops.setup_link)
fd0326f2 4914 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4915
0ecc061d
PWJ		 4916 return ret;
4917}
4918
a34bcfff 4919static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4920{
9a799d71 4921 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4922 u32 gpie = 0;
9a799d71 4923
9b471446 4924 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4925 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4926 IXGBE_GPIE_OCD;
4927 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4928 /*
4929 * use EIAM to auto-mask when MSI-X interrupt is asserted
4930 * this saves a register write for every interrupt
4931 */
4932 switch (hw->mac.type) {
4933 case ixgbe_mac_82598EB:
4934 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4935 break;
9b471446 4936 case ixgbe_mac_82599EB:
b93a2226 4937 case ixgbe_mac_X540:
9a75a1ac
DS		 4938 case ixgbe_mac_X550:
4939 case ixgbe_mac_X550EM_x:
b93a2226 4940 default:
9b471446
JB		 4941 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4942 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4943 break;
4944 }
4945 } else {
021230d4
AV		 4946 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4947 * specifically only auto mask tx and rx interrupts */
4948 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4949 }
9a799d71 4950
a34bcfff
AD		 4951 /* XXX: to interrupt immediately for EICS writes, enable this */
4952 /* gpie |= IXGBE_GPIE_EIMEN; */
4953
4954 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4955 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4956
4957 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4958 case IXGBE_82599_VMDQ_8Q_MASK:
4959 gpie |= IXGBE_GPIE_VTMODE_16;
4960 break;
4961 case IXGBE_82599_VMDQ_4Q_MASK:
4962 gpie |= IXGBE_GPIE_VTMODE_32;
4963 break;
4964 default:
4965 gpie |= IXGBE_GPIE_VTMODE_64;
4966 break;
4967 }
119fc60a
MC		 4968 }
4969
5fdd31f9 4970 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4971 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4972 switch (adapter->hw.mac.type) {
4973 case ixgbe_mac_82599EB:
9a900eca 4974 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 4975 break;
f3df98ec
DS		 4976 default:
4977 break;
4978 }
4979 }
5fdd31f9 4980
a34bcfff
AD		 4981 /* Enable fan failure interrupt */
4982 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 4983 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 4984
a023bbd0
DS		 4985 switch (hw->mac.type) {
4986 case ixgbe_mac_82599EB:
4987 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
4988 break;
4989 case ixgbe_mac_X550EM_x:
4990 gpie |= IXGBE_SDP0_GPIEN_X540;
4991 break;
4992 default:
4993 break;
2698b208 4994 }
a34bcfff
AD		 4995
4996 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4997}
4998
c7ccde0f 4999static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5000{
5001 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5002 int err;
a34bcfff
AD		 5003 u32 ctrl_ext;
5004
5005 ixgbe_get_hw_control(adapter);
5006 ixgbe_setup_gpie(adapter);
e8e26350 5007
9a799d71
AK		 5008 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5009 ixgbe_configure_msix(adapter);
5010 else
5011 ixgbe_configure_msi_and_legacy(adapter);
5012
ec74a471
ET		 5013 /* enable the optics for 82599 SFP+ fiber */
5014 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5015 hw->mac.ops.enable_tx_laser(hw);
5016
961fac88
DS		 5017 if (hw->phy.ops.set_phy_power)
5018 hw->phy.ops.set_phy_power(hw, true);
5019
4e857c58 5020 smp_mb__before_atomic();
9a799d71 5021 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5022 ixgbe_napi_enable_all(adapter);
5023
73c4b7cd
AD		 5024 if (ixgbe_is_sfp(hw)) {
5025 ixgbe_sfp_link_config(adapter);
5026 } else {
5027 err = ixgbe_non_sfp_link_config(hw);
5028 if (err)
5029 e_err(probe, "link_config FAILED %d\n", err);
5030 }
5031
021230d4
AV		 5032 /* clear any pending interrupts, may auto mask */
5033 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5034 ixgbe_irq_enable(adapter, true, true);
9a799d71 5035
bf069c97
DS		 5036 /*
5037 * If this adapter has a fan, check to see if we had a failure
5038 * before we enabled the interrupt.
5039 */
5040 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5041 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5042 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5043 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5044 }
5045
9a799d71
AK		 5046 /* bring the link up in the watchdog, this could race with our first
5047 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5048 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5049 adapter->link_check_timeout = jiffies;
7086400d 5050 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5051
5052 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5053 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5054 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5055 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5056}
5057
d4f80882
AV		 5058void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5059{
5060 WARN_ON(in_interrupt());
7086400d
AD		 5061 /* put off any impending NetWatchDogTimeout */
5062 adapter->netdev->trans_start = jiffies;
5063
d4f80882 5064 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5065 usleep_range(1000, 2000);
d4f80882 5066 ixgbe_down(adapter);
5809a1ae
GR		 5067 /*
5068 * If SR-IOV enabled then wait a bit before bringing the adapter
5069 * back up to give the VFs time to respond to the reset. The
5070 * two second wait is based upon the watchdog timer cycle in
5071 * the VF driver.
5072 */
5073 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5074 msleep(2000);
d4f80882
AV		 5075 ixgbe_up(adapter);
5076 clear_bit(__IXGBE_RESETTING, &adapter->state);
5077}
5078
c7ccde0f 5079void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5080{
5081 /* hardware has been reset, we need to reload some things */
5082 ixgbe_configure(adapter);
5083
c7ccde0f 5084 ixgbe_up_complete(adapter);
9a799d71
AK		 5085}
5086
5087void ixgbe_reset(struct ixgbe_adapter *adapter)
5088{
c44ade9e 5089 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5090 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5091 int err;
5092
b0483c8f
MR		 5093 if (ixgbe_removed(hw->hw_addr))
5094 return;
7086400d
AD		 5095 /* lock SFP init bit to prevent race conditions with the watchdog */
5096 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5097 usleep_range(1000, 2000);
5098
5099 /* clear all SFP and link config related flags while holding SFP_INIT */
5100 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5101 IXGBE_FLAG2_SFP_NEEDS_RESET);
5102 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5103
8ca783ab 5104 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5105 switch (err) {
5106 case 0:
5107 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5108 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5109 break;
5110 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5111 e_dev_err("master disable timed out\n");
da4dd0f7 5112 break;
794caeb2
PWJ		 5113 case IXGBE_ERR_EEPROM_VERSION:
5114 /* We are running on a pre-production device, log a warning */
849c4542 5115 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5116 "Please be aware there may be issues associated with "
849c4542
ET		 5117 "your hardware. If you are experiencing problems "
5118 "please contact your Intel or hardware "
5119 "representative who provided you with this "
5120 "hardware.\n");
794caeb2 5121 break;
da4dd0f7 5122 default:
849c4542 5123 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5124 }
9a799d71 5125
7086400d 5126 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5127
5128 /* flush entries out of MAC table */
5d7daa35 5129 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5130 __dev_uc_unsync(netdev, NULL);
5131
5132 /* do not flush user set addresses */
c9f53e63 5133 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5134
5135 /* update SAN MAC vmdq pool selection */
5136 if (hw->mac.san_mac_rar_index)
5137 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5138
8fecf67c 5139 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5140 ixgbe_ptp_reset(adapter);
961fac88
DS		 5141
5142 if (hw->phy.ops.set_phy_power) {
5143 if (!netif_running(adapter->netdev) && !adapter->wol)
5144 hw->phy.ops.set_phy_power(hw, false);
5145 else
5146 hw->phy.ops.set_phy_power(hw, true);
5147 }
9a799d71
AK		 5148}
5149
9a799d71
AK		 5150/**
5151 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5152 * @tx_ring: ring to be cleaned
5153 **/
b6ec895e 5154static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5155{
5156 struct ixgbe_tx_buffer *tx_buffer_info;
5157 unsigned long size;
b6ec895e 5158 u16 i;
9a799d71 5159
84418e3b
AD		 5160 /* ring already cleared, nothing to do */
5161 if (!tx_ring->tx_buffer_info)
5162 return;
9a799d71 5163
84418e3b 5164 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5165 for (i = 0; i < tx_ring->count; i++) {
5166 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5167 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5168 }
5169
dad8a3b3
JF		 5170 netdev_tx_reset_queue(txring_txq(tx_ring));
5171
9a799d71
AK		 5172 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5173 memset(tx_ring->tx_buffer_info, 0, size);
5174
5175 /* Zero out the descriptor ring */
5176 memset(tx_ring->desc, 0, tx_ring->size);
5177
5178 tx_ring->next_to_use = 0;
5179 tx_ring->next_to_clean = 0;
9a799d71
AK		 5180}
5181
5182/**
021230d4 5183 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5184 * @adapter: board private structure
5185 **/
021230d4 5186static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5187{
5188 int i;
5189
021230d4 5190 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5191 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5192}
5193
5194/**
021230d4 5195 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5196 * @adapter: board private structure
5197 **/
021230d4 5198static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5199{
5200 int i;
5201
021230d4 5202 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5203 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5204}
5205
e4911d57
AD		 5206static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5207{
b67bfe0d 5208 struct hlist_node *node2;
e4911d57
AD		 5209 struct ixgbe_fdir_filter *filter;
5210
5211 spin_lock(&adapter->fdir_perfect_lock);
5212
b67bfe0d 5213 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5214 &adapter->fdir_filter_list, fdir_node) {
5215 hlist_del(&filter->fdir_node);
5216 kfree(filter);
5217 }
5218 adapter->fdir_filter_count = 0;
5219
5220 spin_unlock(&adapter->fdir_perfect_lock);
5221}
5222
9a799d71
AK		 5223void ixgbe_down(struct ixgbe_adapter *adapter)
5224{
5225 struct net_device *netdev = adapter->netdev;
7f821875 5226 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5227 struct net_device *upper;
5228 struct list_head *iter;
bf29ee6c 5229 int i;
9a799d71
AK		 5230
5231 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5232 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5233 return; /* do nothing if already down */
9a799d71
AK		 5234
5235 /* disable receives */
1f9ac57c 5236 hw->mac.ops.disable_rx(hw);
9a799d71 5237
2d39d576
YZ		 5238 /* disable all enabled rx queues */
5239 for (i = 0; i < adapter->num_rx_queues; i++)
5240 /* this call also flushes the previous write */
5241 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5242
032b4325 5243 usleep_range(10000, 20000);
9a799d71 5244
7f821875
JB		 5245 netif_tx_stop_all_queues(netdev);
5246
7086400d 5247 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5248 netif_carrier_off(netdev);
5249 netif_tx_disable(netdev);
5250
2a47fa45
JF		 5251 /* disable any upper devices */
5252 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5253 if (netif_is_macvlan(upper)) {
5254 struct macvlan_dev *vlan = netdev_priv(upper);
5255
5256 if (vlan->fwd_priv) {
5257 netif_tx_stop_all_queues(upper);
5258 netif_carrier_off(upper);
5259 netif_tx_disable(upper);
5260 }
5261 }
5262 }
5263
c0dfb90e
JF		 5264 ixgbe_irq_disable(adapter);
5265
5266 ixgbe_napi_disable_all(adapter);
5267
d034acf1
AD		 5268 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5269 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5270 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5271
5272 del_timer_sync(&adapter->service_timer);
5273
34cecbbf 5274 if (adapter->num_vfs) {
8e34d1aa
AD		 5275 /* Clear EITR Select mapping */
5276 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5277
5278 /* Mark all the VFs as inactive */
5279 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5280 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5281
34cecbbf
AD		 5282 /* ping all the active vfs to let them know we are going down */
5283 ixgbe_ping_all_vfs(adapter);
5284
5285 /* Disable all VFTE/VFRE TX/RX */
5286 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5287 }
5288
7f821875
JB		 5289 /* disable transmits in the hardware now that interrupts are off */
5290 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5291 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5292 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5293 }
34cecbbf 5294
9a75a1ac 5295 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5296 switch (hw->mac.type) {
5297 case ixgbe_mac_82599EB:
b93a2226 5298 case ixgbe_mac_X540:
9a75a1ac
DS		 5299 case ixgbe_mac_X550:
5300 case ixgbe_mac_X550EM_x:
88512539 5301 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5302 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5303 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5304 break;
5305 default:
5306 break;
5307 }
7f821875 5308
6f4a0e45
PL		 5309 if (!pci_channel_offline(adapter->pdev))
5310 ixgbe_reset(adapter);
c6ecf39a 5311
ec74a471
ET		 5312 /* power down the optics for 82599 SFP+ fiber */
5313 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5314 hw->mac.ops.disable_tx_laser(hw);
5315
9a799d71
AK		 5316 ixgbe_clean_all_tx_rings(adapter);
5317 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5318}
5319
9a799d71
AK		 5320/**
5321 * ixgbe_tx_timeout - Respond to a Tx Hang
5322 * @netdev: network interface device structure
5323 **/
5324static void ixgbe_tx_timeout(struct net_device *netdev)
5325{
5326 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5327
5328 /* Do the reset outside of interrupt context */
c83c6cbd 5329 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5330}
5331
9a799d71
AK		 5332/**
5333 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5334 * @adapter: board private structure to initialize
5335 *
5336 * ixgbe_sw_init initializes the Adapter private data structure.
5337 * Fields are initialized based on PCI device information and
5338 * OS network device settings (MTU size).
5339 **/
9f9a12f8 5340static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5341{
5342 struct ixgbe_hw *hw = &adapter->hw;
5343 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5344 unsigned int rss, fdir;
cb6d0f5e 5345 u32 fwsm;
7a6b6f51 5346#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5347 int j;
5348 struct tc_configuration *tc;
5349#endif
021230d4 5350
c44ade9e
JB		 5351 /* PCI config space info */
5352
5353 hw->vendor_id = pdev->vendor;
5354 hw->device_id = pdev->device;
5355 hw->revision_id = pdev->revision;
5356 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5357 hw->subsystem_device_id = pdev->subsystem_device;
5358
8fc3bb6d 5359 /* Set common capability flags and settings */
0f9b232b 5360 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5361 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5362 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5363 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5364 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5365 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5366 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5367 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5368#ifdef CONFIG_IXGBE_DCA
5369 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5370#endif
5371#ifdef IXGBE_FCOE
5372 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5373 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5374#ifdef CONFIG_IXGBE_DCB
5375 /* Default traffic class to use for FCoE */
5376 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5377#endif /* CONFIG_IXGBE_DCB */
5378#endif /* IXGBE_FCOE */
5379
5d7daa35
JK		 5380 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5381 hw->mac.num_rar_entries,
5382 GFP_ATOMIC);
5383
8fc3bb6d 5384 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5385 switch (hw->mac.type) {
5386 case ixgbe_mac_82598EB:
8fc3bb6d 5387 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5388
bf069c97
DS		 5389 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5390 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5391
49c7ffbe 5392 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5393 adapter->ring_feature[RING_F_FDIR].limit = 0;
5394 adapter->atr_sample_rate = 0;
5395 adapter->fdir_pballoc = 0;
5396#ifdef IXGBE_FCOE
5397 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5398 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5399#ifdef CONFIG_IXGBE_DCB
5400 adapter->fcoe.up = 0;
5401#endif /* IXGBE_DCB */
5402#endif /* IXGBE_FCOE */
5403 break;
5404 case ixgbe_mac_82599EB:
5405 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5406 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5407 break;
b93a2226 5408 case ixgbe_mac_X540:
9a900eca 5409 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5410 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5411 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5412 break;
9a75a1ac
DS		 5413 case ixgbe_mac_X550EM_x:
5414 case ixgbe_mac_X550:
5415#ifdef CONFIG_IXGBE_DCA
5416 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5417#endif
5418#ifdef CONFIG_IXGBE_VXLAN
5419 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5420#endif
5421 break;
bd508178
AD		 5422 default:
5423 break;
f8212f97 5424 }
2f90b865 5425
7c8ae65a
AD		 5426#ifdef IXGBE_FCOE
5427 /* FCoE support exists, always init the FCoE lock */
5428 spin_lock_init(&adapter->fcoe.lock);
5429
5430#endif
1fc5f038
AD		 5431 /* n-tuple support exists, always init our spinlock */
5432 spin_lock_init(&adapter->fdir_perfect_lock);
5433
7a6b6f51 5434#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5435 switch (hw->mac.type) {
5436 case ixgbe_mac_X540:
9a75a1ac
DS		 5437 case ixgbe_mac_X550:
5438 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5439 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5440 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5441 break;
5442 default:
5443 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5444 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5445 break;
5446 }
5447
2f90b865
AD		 5448 /* Configure DCB traffic classes */
5449 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5450 tc = &adapter->dcb_cfg.tc_config[j];
5451 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5452 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5453 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5454 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5455 tc->dcb_pfc = pfc_disabled;
5456 }
4de2a022
JF		 5457
5458 /* Initialize default user to priority mapping, UPx->TC0 */
5459 tc = &adapter->dcb_cfg.tc_config[0];
5460 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5461 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5462
2f90b865
AD		 5463 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5464 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5465 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5466 adapter->dcb_set_bitmap = 0x00;
3032309b 5467 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5468 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5469 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5470
5471#endif
9a799d71
AK		 5472
5473 /* default flow control settings */
cd7664f6 5474 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5475 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5476 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5477 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5478 hw->fc.send_xon = true;
73d80953 5479 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5480
99d74487 5481#ifdef CONFIG_PCI_IOV
170e8543
JK		 5482 if (max_vfs > 0)
5483 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5484
99d74487 5485 /* assign number of SR-IOV VFs */
170e8543 5486 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5487 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5488 adapter->num_vfs = 0;
5489 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5490 } else {
5491 adapter->num_vfs = max_vfs;
5492 }
5493 }
5494#endif /* CONFIG_PCI_IOV */
99d74487 5495
30efa5a3 5496 /* enable itr by default in dynamic mode */
f7554a2b 5497 adapter->rx_itr_setting = 1;
f7554a2b 5498 adapter->tx_itr_setting = 1;
30efa5a3 5499
30efa5a3
JB		 5500 /* set default ring sizes */
5501 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5502 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5503
bd198058 5504 /* set default work limits */
59224555 5505 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5506
9a799d71 5507 /* initialize eeprom parameters */
c44ade9e 5508 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5509 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5510 return -EIO;
5511 }
5512
2a47fa45
JF		 5513 /* PF holds first pool slot */
5514 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5515 set_bit(__IXGBE_DOWN, &adapter->state);
5516
5517 return 0;
5518}
5519
5520/**
5521 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5522 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5523 *
5524 * Return 0 on success, negative on failure
5525 **/
b6ec895e 5526int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5527{
b6ec895e 5528 struct device *dev = tx_ring->dev;
de88eeeb 5529 int orig_node = dev_to_node(dev);
ca8dfe25 5530 int ring_node = -1;
9a799d71
AK		 5531 int size;
5532
3a581073 5533 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5534
5535 if (tx_ring->q_vector)
ca8dfe25 5536 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5537
ca8dfe25 5538 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5539 if (!tx_ring->tx_buffer_info)
89bf67f1 5540 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5541 if (!tx_ring->tx_buffer_info)
5542 goto err;
9a799d71 5543
827da44c
JS		 5544 u64_stats_init(&tx_ring->syncp);
5545
9a799d71 5546 /* round up to nearest 4K */
12207e49 5547 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5548 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5549
ca8dfe25 5550 set_dev_node(dev, ring_node);
de88eeeb
AD		 5551 tx_ring->desc = dma_alloc_coherent(dev,
5552 tx_ring->size,
5553 &tx_ring->dma,
5554 GFP_KERNEL);
5555 set_dev_node(dev, orig_node);
5556 if (!tx_ring->desc)
5557 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5558 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5559 if (!tx_ring->desc)
5560 goto err;
9a799d71 5561
3a581073
JB		 5562 tx_ring->next_to_use = 0;
5563 tx_ring->next_to_clean = 0;
9a799d71 5564 return 0;
e01c31a5
JB		 5565
5566err:
5567 vfree(tx_ring->tx_buffer_info);
5568 tx_ring->tx_buffer_info = NULL;
b6ec895e 5569 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5570 return -ENOMEM;
9a799d71
AK		 5571}
5572
69888674
AD		 5573/**
5574 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5575 * @adapter: board private structure
5576 *
5577 * If this function returns with an error, then it's possible one or
5578 * more of the rings is populated (while the rest are not). It is the
5579 * callers duty to clean those orphaned rings.
5580 *
5581 * Return 0 on success, negative on failure
5582 **/
5583static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5584{
5585 int i, err = 0;
5586
5587 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5588 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5589 if (!err)
5590 continue;
de3d5b94 5591
396e799c 5592 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5593 goto err_setup_tx;
69888674
AD		 5594 }
5595
de3d5b94
AD		 5596 return 0;
5597err_setup_tx:
5598 /* rewind the index freeing the rings as we go */
5599 while (i--)
5600 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5601 return err;
5602}
5603
9a799d71
AK		 5604/**
5605 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5606 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5607 *
5608 * Returns 0 on success, negative on failure
5609 **/
b6ec895e 5610int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5611{
b6ec895e 5612 struct device *dev = rx_ring->dev;
de88eeeb 5613 int orig_node = dev_to_node(dev);
ca8dfe25 5614 int ring_node = -1;
021230d4 5615 int size;
9a799d71 5616
3a581073 5617 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5618
5619 if (rx_ring->q_vector)
ca8dfe25 5620 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5621
ca8dfe25 5622 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5623 if (!rx_ring->rx_buffer_info)
89bf67f1 5624 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5625 if (!rx_ring->rx_buffer_info)
5626 goto err;
9a799d71 5627
827da44c
JS		 5628 u64_stats_init(&rx_ring->syncp);
5629
9a799d71 5630 /* Round up to nearest 4K */
3a581073
JB		 5631 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5632 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5633
ca8dfe25 5634 set_dev_node(dev, ring_node);
de88eeeb
AD		 5635 rx_ring->desc = dma_alloc_coherent(dev,
5636 rx_ring->size,
5637 &rx_ring->dma,
5638 GFP_KERNEL);
5639 set_dev_node(dev, orig_node);
5640 if (!rx_ring->desc)
5641 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5642 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5643 if (!rx_ring->desc)
5644 goto err;
9a799d71 5645
3a581073
JB		 5646 rx_ring->next_to_clean = 0;
5647 rx_ring->next_to_use = 0;
9a799d71
AK		 5648
5649 return 0;
b6ec895e
AD		 5650err:
5651 vfree(rx_ring->rx_buffer_info);
5652 rx_ring->rx_buffer_info = NULL;
5653 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5654 return -ENOMEM;
9a799d71
AK		 5655}
5656
69888674
AD		 5657/**
5658 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5659 * @adapter: board private structure
5660 *
5661 * If this function returns with an error, then it's possible one or
5662 * more of the rings is populated (while the rest are not). It is the
5663 * callers duty to clean those orphaned rings.
5664 *
5665 * Return 0 on success, negative on failure
5666 **/
69888674
AD		 5667static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5668{
5669 int i, err = 0;
5670
5671 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5672 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5673 if (!err)
5674 continue;
de3d5b94 5675
396e799c 5676 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5677 goto err_setup_rx;
69888674
AD		 5678 }
5679
7c8ae65a
AD		 5680#ifdef IXGBE_FCOE
5681 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5682 if (!err)
5683#endif
5684 return 0;
de3d5b94
AD		 5685err_setup_rx:
5686 /* rewind the index freeing the rings as we go */
5687 while (i--)
5688 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5689 return err;
5690}
5691
9a799d71
AK		 5692/**
5693 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5694 * @tx_ring: Tx descriptor ring for a specific queue
5695 *
5696 * Free all transmit software resources
5697 **/
b6ec895e 5698void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5699{
b6ec895e 5700 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5701
5702 vfree(tx_ring->tx_buffer_info);
5703 tx_ring->tx_buffer_info = NULL;
5704
b6ec895e
AD		 5705 /* if not set, then don't free */
5706 if (!tx_ring->desc)
5707 return;
5708
5709 dma_free_coherent(tx_ring->dev, tx_ring->size,
5710 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5711
5712 tx_ring->desc = NULL;
5713}
5714
5715/**
5716 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5717 * @adapter: board private structure
5718 *
5719 * Free all transmit software resources
5720 **/
5721static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5722{
5723 int i;
5724
5725 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5726 if (adapter->tx_ring[i]->desc)
b6ec895e 5727 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5728}
5729
5730/**
b4617240 5731 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5732 * @rx_ring: ring to clean the resources from
5733 *
5734 * Free all receive software resources
5735 **/
b6ec895e 5736void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5737{
b6ec895e 5738 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5739
5740 vfree(rx_ring->rx_buffer_info);
5741 rx_ring->rx_buffer_info = NULL;
5742
b6ec895e
AD		 5743 /* if not set, then don't free */
5744 if (!rx_ring->desc)
5745 return;
5746
5747 dma_free_coherent(rx_ring->dev, rx_ring->size,
5748 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5749
5750 rx_ring->desc = NULL;
5751}
5752
5753/**
5754 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5755 * @adapter: board private structure
5756 *
5757 * Free all receive software resources
5758 **/
5759static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5760{
5761 int i;
5762
7c8ae65a
AD		 5763#ifdef IXGBE_FCOE
5764 ixgbe_free_fcoe_ddp_resources(adapter);
5765
5766#endif
9a799d71 5767 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5768 if (adapter->rx_ring[i]->desc)
b6ec895e 5769 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5770}
5771
9a799d71
AK		 5772/**
5773 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5774 * @netdev: network interface device structure
5775 * @new_mtu: new value for maximum frame size
5776 *
5777 * Returns 0 on success, negative on failure
5778 **/
5779static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5780{
5781 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5782 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5783
42c783c5 5784 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5785 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5786 return -EINVAL;
5787
5788 /*
872844dd
AD		 5789 * For 82599EB we cannot allow legacy VFs to enable their receive
5790 * paths when MTU greater than 1500 is configured. So display a
5791 * warning that legacy VFs will be disabled.
655309e9
AD		 5792 */
5793 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5794 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5795 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5796 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5797
396e799c 5798 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5799
021230d4 5800 /* must set new MTU before calling down or up */
9a799d71
AK		 5801 netdev->mtu = new_mtu;
5802
d4f80882
AV		 5803 if (netif_running(netdev))
5804 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5805
5806 return 0;
5807}
5808
5809/**
5810 * ixgbe_open - Called when a network interface is made active
5811 * @netdev: network interface device structure
5812 *
5813 * Returns 0 on success, negative value on failure
5814 *
5815 * The open entry point is called when a network interface is made
5816 * active by the system (IFF_UP). At this point all resources needed
5817 * for transmit and receive operations are allocated, the interrupt
5818 * handler is registered with the OS, the watchdog timer is started,
5819 * and the stack is notified that the interface is ready.
5820 **/
5821static int ixgbe_open(struct net_device *netdev)
5822{
5823 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5824 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5825 int err, queues;
4bebfaa5
AK		 5826
5827 /* disallow open during test */
5828 if (test_bit(__IXGBE_TESTING, &adapter->state))
5829 return -EBUSY;
9a799d71 5830
54386467
JB		 5831 netif_carrier_off(netdev);
5832
9a799d71
AK		 5833 /* allocate transmit descriptors */
5834 err = ixgbe_setup_all_tx_resources(adapter);
5835 if (err)
5836 goto err_setup_tx;
5837
9a799d71
AK		 5838 /* allocate receive descriptors */
5839 err = ixgbe_setup_all_rx_resources(adapter);
5840 if (err)
5841 goto err_setup_rx;
5842
5843 ixgbe_configure(adapter);
5844
021230d4 5845 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5846 if (err)
5847 goto err_req_irq;
5848
ac802f5d 5849 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5850 if (adapter->num_rx_pools > 1)
5851 queues = adapter->num_rx_queues_per_pool;
5852 else
5853 queues = adapter->num_tx_queues;
5854
5855 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5856 if (err)
5857 goto err_set_queues;
5858
2a47fa45
JF		 5859 if (adapter->num_rx_pools > 1 &&
5860 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5861 queues = IXGBE_MAX_L2A_QUEUES;
5862 else
5863 queues = adapter->num_rx_queues;
5864 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5865 if (err)
5866 goto err_set_queues;
5867
1a71ab24 5868 ixgbe_ptp_init(adapter);
1a71ab24 5869
c7ccde0f 5870 ixgbe_up_complete(adapter);
9a799d71 5871
67359c3c
MR		 5872 ixgbe_clear_vxlan_port(adapter);
5873#ifdef CONFIG_IXGBE_VXLAN
3f207800 5874 vxlan_get_rx_port(netdev);
3f207800 5875#endif
67359c3c 5876
9a799d71
AK		 5877 return 0;
5878
ac802f5d
AD		 5879err_set_queues:
5880 ixgbe_free_irq(adapter);
9a799d71 5881err_req_irq:
a20a1199 5882 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 5883 if (hw->phy.ops.set_phy_power && !adapter->wol)
5884 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 5885err_setup_rx:
a20a1199 5886 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5887err_setup_tx:
9a799d71
AK		 5888 ixgbe_reset(adapter);
5889
5890 return err;
5891}
5892
a0cccce2
JK		 5893static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5894{
5895 ixgbe_ptp_suspend(adapter);
5896
6ac74394
DS		 5897 if (adapter->hw.phy.ops.enter_lplu) {
5898 adapter->hw.phy.reset_disable = true;
5899 ixgbe_down(adapter);
5900 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5901 adapter->hw.phy.reset_disable = false;
5902 } else {
5903 ixgbe_down(adapter);
5904 }
5905
a0cccce2
JK		 5906 ixgbe_free_irq(adapter);
5907
5908 ixgbe_free_all_tx_resources(adapter);
5909 ixgbe_free_all_rx_resources(adapter);
5910}
5911
9a799d71
AK		 5912/**
5913 * ixgbe_close - Disables a network interface
5914 * @netdev: network interface device structure
5915 *
5916 * Returns 0, this is not allowed to fail
5917 *
5918 * The close entry point is called when an interface is de-activated
5919 * by the OS. The hardware is still under the drivers control, but
5920 * needs to be disabled. A global MAC reset is issued to stop the
5921 * hardware, and all transmit and receive resources are freed.
5922 **/
5923static int ixgbe_close(struct net_device *netdev)
5924{
5925 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5926
1a71ab24 5927 ixgbe_ptp_stop(adapter);
1a71ab24 5928
a0cccce2 5929 ixgbe_close_suspend(adapter);
9a799d71 5930
e4911d57
AD		 5931 ixgbe_fdir_filter_exit(adapter);
5932
5eba3699 5933 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5934
5935 return 0;
5936}
5937
b3c8b4ba
AD		 5938#ifdef CONFIG_PM
5939static int ixgbe_resume(struct pci_dev *pdev)
5940{
c60fbb00
AD		 5941 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5942 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5943 u32 err;
5944
0391bbe3 5945 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5946 pci_set_power_state(pdev, PCI_D0);
5947 pci_restore_state(pdev);
656ab817
DS		 5948 /*
5949 * pci_restore_state clears dev->state_saved so call
5950 * pci_save_state to restore it.
5951 */
5952 pci_save_state(pdev);
9ce77666 5953
5954 err = pci_enable_device_mem(pdev);
b3c8b4ba 5955 if (err) {
849c4542 5956 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5957 return err;
5958 }
4e857c58 5959 smp_mb__before_atomic();
41c62843 5960 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5961 pci_set_master(pdev);
5962
dd4d8ca6 5963 pci_wake_from_d3(pdev, false);
b3c8b4ba 5964
b3c8b4ba
AD		 5965 ixgbe_reset(adapter);
5966
495dce12
WJP		 5967 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5968
ac802f5d
AD		 5969 rtnl_lock();
5970 err = ixgbe_init_interrupt_scheme(adapter);
5971 if (!err && netif_running(netdev))
c60fbb00 5972 err = ixgbe_open(netdev);
ac802f5d
AD		 5973
5974 rtnl_unlock();
5975
5976 if (err)
5977 return err;
b3c8b4ba
AD		 5978
5979 netif_device_attach(netdev);
5980
5981 return 0;
5982}
b3c8b4ba 5983#endif /* CONFIG_PM */
9d8d05ae
RW		 5984
5985static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5986{
c60fbb00
AD		 5987 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5988 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5989 struct ixgbe_hw *hw = &adapter->hw;
5990 u32 ctrl, fctrl;
5991 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5992#ifdef CONFIG_PM
5993 int retval = 0;
5994#endif
5995
5996 netif_device_detach(netdev);
5997
499ab5cc 5998 rtnl_lock();
a0cccce2
JK		 5999 if (netif_running(netdev))
6000 ixgbe_close_suspend(adapter);
499ab5cc 6001 rtnl_unlock();
b3c8b4ba 6002
5f5ae6fc
AD		 6003 ixgbe_clear_interrupt_scheme(adapter);
6004
b3c8b4ba
AD		 6005#ifdef CONFIG_PM
6006 retval = pci_save_state(pdev);
6007 if (retval)
6008 return retval;
4df10466 6009
b3c8b4ba 6010#endif
f4f1040a
JK		 6011 if (hw->mac.ops.stop_link_on_d3)
6012 hw->mac.ops.stop_link_on_d3(hw);
6013
e8e26350
PW		 6014 if (wufc) {
6015 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6016
ec74a471
ET		 6017 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6018 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6019 hw->mac.ops.enable_tx_laser(hw);
6020
e8e26350
PW		 6021 /* turn on all-multi mode if wake on multicast is enabled */
6022 if (wufc & IXGBE_WUFC_MC) {
6023 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6024 fctrl |= IXGBE_FCTRL_MPE;
6025 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6026 }
6027
6028 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6029 ctrl |= IXGBE_CTRL_GIO_DIS;
6030 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6031
6032 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6033 } else {
6034 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6035 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6036 }
6037
bd508178
AD		 6038 switch (hw->mac.type) {
6039 case ixgbe_mac_82598EB:
dd4d8ca6 6040 pci_wake_from_d3(pdev, false);
bd508178
AD		 6041 break;
6042 case ixgbe_mac_82599EB:
b93a2226 6043 case ixgbe_mac_X540:
9a75a1ac
DS		 6044 case ixgbe_mac_X550:
6045 case ixgbe_mac_X550EM_x:
bd508178
AD		 6046 pci_wake_from_d3(pdev, !!wufc);
6047 break;
6048 default:
6049 break;
6050 }
b3c8b4ba 6051
9d8d05ae 6052 *enable_wake = !!wufc;
961fac88
DS		 6053 if (hw->phy.ops.set_phy_power && !*enable_wake)
6054 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6055
b3c8b4ba
AD		 6056 ixgbe_release_hw_control(adapter);
6057
41c62843
MR		 6058 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6059 pci_disable_device(pdev);
b3c8b4ba 6060
9d8d05ae
RW		 6061 return 0;
6062}
6063
6064#ifdef CONFIG_PM
6065static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6066{
6067 int retval;
6068 bool wake;
6069
6070 retval = __ixgbe_shutdown(pdev, &wake);
6071 if (retval)
6072 return retval;
6073
6074 if (wake) {
6075 pci_prepare_to_sleep(pdev);
6076 } else {
6077 pci_wake_from_d3(pdev, false);
6078 pci_set_power_state(pdev, PCI_D3hot);
6079 }
b3c8b4ba
AD		 6080
6081 return 0;
6082}
9d8d05ae 6083#endif /* CONFIG_PM */
b3c8b4ba
AD		 6084
6085static void ixgbe_shutdown(struct pci_dev *pdev)
6086{
9d8d05ae
RW		 6087 bool wake;
6088
6089 __ixgbe_shutdown(pdev, &wake);
6090
6091 if (system_state == SYSTEM_POWER_OFF) {
6092 pci_wake_from_d3(pdev, wake);
6093 pci_set_power_state(pdev, PCI_D3hot);
6094 }
b3c8b4ba
AD		 6095}
6096
9a799d71
AK		 6097/**
6098 * ixgbe_update_stats - Update the board statistics counters.
6099 * @adapter: board private structure
6100 **/
6101void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6102{
2d86f139 6103 struct net_device *netdev = adapter->netdev;
9a799d71 6104 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6105 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6106 u64 total_mpc = 0;
6107 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6108 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6109 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6110 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6111
d08935c2
DS		 6112 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6113 test_bit(__IXGBE_RESETTING, &adapter->state))
6114 return;
6115
94b982b2 6116 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6117 u64 rsc_count = 0;
94b982b2 6118 u64 rsc_flush = 0;
94b982b2 6119 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6120 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6121 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6122 }
6123 adapter->rsc_total_count = rsc_count;
6124 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6125 }
6126
5b7da515
AD		 6127 for (i = 0; i < adapter->num_rx_queues; i++) {
6128 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6129 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6130 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6131 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6132 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6133 bytes += rx_ring->stats.bytes;
6134 packets += rx_ring->stats.packets;
6135 }
6136 adapter->non_eop_descs = non_eop_descs;
6137 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6138 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6139 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6140 netdev->stats.rx_bytes = bytes;
6141 netdev->stats.rx_packets = packets;
6142
6143 bytes = 0;
6144 packets = 0;
7ca3bc58 6145 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6146 for (i = 0; i < adapter->num_tx_queues; i++) {
6147 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6148 restart_queue += tx_ring->tx_stats.restart_queue;
6149 tx_busy += tx_ring->tx_stats.tx_busy;
6150 bytes += tx_ring->stats.bytes;
6151 packets += tx_ring->stats.packets;
6152 }
eb985f09 6153 adapter->restart_queue = restart_queue;
5b7da515
AD		 6154 adapter->tx_busy = tx_busy;
6155 netdev->stats.tx_bytes = bytes;
6156 netdev->stats.tx_packets = packets;
7ca3bc58 6157
7ca647bd 6158 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6159
6160 /* 8 register reads */
6f11eef7
AV		 6161 for (i = 0; i < 8; i++) {
6162 /* for packet buffers not used, the register should read 0 */
6163 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6164 missed_rx += mpc;
7ca647bd
JP		 6165 hwstats->mpc[i] += mpc;
6166 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6167 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6168 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6169 switch (hw->mac.type) {
6170 case ixgbe_mac_82598EB:
1a70db4b
ET		 6171 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6172 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6173 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6174 hwstats->pxonrxc[i] +=
6175 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6176 break;
6177 case ixgbe_mac_82599EB:
b93a2226 6178 case ixgbe_mac_X540:
9a75a1ac
DS		 6179 case ixgbe_mac_X550:
6180 case ixgbe_mac_X550EM_x:
bd508178
AD		 6181 hwstats->pxonrxc[i] +=
6182 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6183 break;
6184 default:
6185 break;
e8e26350 6186 }
6f11eef7 6187 }
1a70db4b
ET		 6188
6189 /*16 register reads */
6190 for (i = 0; i < 16; i++) {
6191 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6192 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6193 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6194 (hw->mac.type == ixgbe_mac_X540) ||
6195 (hw->mac.type == ixgbe_mac_X550) ||
6196 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6197 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6198 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6199 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6200 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6201 }
6202 }
6203
7ca647bd 6204 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6205 /* work around hardware counting issue */
7ca647bd 6206 hwstats->gprc -= missed_rx;
6f11eef7 6207
c84d324c
JF		 6208 ixgbe_update_xoff_received(adapter);
6209
6f11eef7 6210 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6211 switch (hw->mac.type) {
6212 case ixgbe_mac_82598EB:
6213 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6214 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6215 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6216 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6217 break;
b93a2226 6218 case ixgbe_mac_X540:
9a75a1ac
DS		 6219 case ixgbe_mac_X550:
6220 case ixgbe_mac_X550EM_x:
6221 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6222 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6223 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6224 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6225 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6226 case ixgbe_mac_82599EB:
a4d4f629
AD		 6227 for (i = 0; i < 16; i++)
6228 adapter->hw_rx_no_dma_resources +=
6229 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6230 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6231 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6232 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6233 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6234 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6235 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6236 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6237 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6238 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6239#ifdef IXGBE_FCOE
7ca647bd
JP		 6240 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6241 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6242 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6243 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6244 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6245 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6246 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6247 if (adapter->fcoe.ddp_pool) {
6248 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6249 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6250 unsigned int cpu;
6251 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6252 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6253 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6254 noddp += ddp_pool->noddp;
6255 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6256 }
5a1ee270
AD		 6257 hwstats->fcoe_noddp = noddp;
6258 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6259 }
6d45522c 6260#endif /* IXGBE_FCOE */
bd508178
AD		 6261 break;
6262 default:
6263 break;
e8e26350 6264 }
9a799d71 6265 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6266 hwstats->bprc += bprc;
6267 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6268 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6269 hwstats->mprc -= bprc;
6270 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6271 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6272 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6273 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6274 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6275 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6276 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6277 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6278 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6279 hwstats->lxontxc += lxon;
6f11eef7 6280 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6281 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6282 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6283 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6284 /*
6285 * 82598 errata - tx of flow control packets is included in tx counters
6286 */
6287 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6288 hwstats->gptc -= xon_off_tot;
6289 hwstats->mptc -= xon_off_tot;
6290 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6291 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6292 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6293 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6294 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6295 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6296 hwstats->ptc64 -= xon_off_tot;
6297 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6298 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6299 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6300 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6301 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6302 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6303
6304 /* Fill out the OS statistics structure */
7ca647bd 6305 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6306
6307 /* Rx Errors */
7ca647bd 6308 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6309 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6310 netdev->stats.rx_length_errors = hwstats->rlec;
6311 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6312 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6313}
6314
6315/**
d034acf1 6316 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6317 * @adapter: pointer to the device adapter structure
9a799d71 6318 **/
d034acf1 6319static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6320{
cf8280ee 6321 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6322 int i;
cf8280ee 6323
d034acf1
AD		 6324 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6325 return;
6326
6327 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6328
d034acf1 6329 /* if interface is down do nothing */
fe49f04a 6330 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6331 return;
6332
6333 /* do nothing if we are not using signature filters */
6334 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6335 return;
6336
6337 adapter->fdir_overflow++;
6338
93c52dd0
AD		 6339 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6340 for (i = 0; i < adapter->num_tx_queues; i++)
6341 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6342 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6343 /* re-enable flow director interrupts */
6344 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6345 } else {
6346 e_err(probe, "failed to finish FDIR re-initialization, "
6347 "ignored adding FDIR ATR filters\n");
6348 }
93c52dd0
AD		 6349}
6350
6351/**
6352 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6353 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6354 *
6355 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6356 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6357 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6358 * determine if a hang has occurred.
93c52dd0
AD		 6359 */
6360static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6361{
cf8280ee 6362 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6363 u64 eics = 0;
6364 int i;
cf8280ee 6365
09f40aed 6366 /* If we're down, removing or resetting, just bail */
93c52dd0 6367 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6368 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6369 test_bit(__IXGBE_RESETTING, &adapter->state))
6370 return;
22d5a71b 6371
93c52dd0
AD		 6372 /* Force detection of hung controller */
6373 if (netif_carrier_ok(adapter->netdev)) {
6374 for (i = 0; i < adapter->num_tx_queues; i++)
6375 set_check_for_tx_hang(adapter->tx_ring[i]);
6376 }
22d5a71b 6377
fe49f04a
AD		 6378 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6379 /*
6380 * for legacy and MSI interrupts don't set any bits
6381 * that are enabled for EIAM, because this operation
6382 * would set *both* EIMS and EICS for any bit in EIAM
6383 */
6384 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6385 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6386 } else {
6387 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6388 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6389 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6390 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6391 eics |= ((u64)1 << i);
6392 }
cf8280ee 6393 }
9a799d71 6394
93c52dd0 6395 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6396 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6397}
6398
e8e26350 6399/**
93c52dd0 6400 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6401 * @adapter: pointer to the device adapter structure
6402 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6403 **/
93c52dd0 6404static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6405{
e8e26350 6406 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6407 u32 link_speed = adapter->link_speed;
6408 bool link_up = adapter->link_up;
041441d0 6409 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6410
93c52dd0
AD		 6411 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6412 return;
6413
6414 if (hw->mac.ops.check_link) {
6415 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6416 } else {
93c52dd0
AD		 6417 /* always assume link is up, if no check link function */
6418 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6419 link_up = true;
c4cf55e5 6420 }
041441d0
AD		 6421
6422 if (adapter->ixgbe_ieee_pfc)
6423 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6424
3ebe8fde 6425 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6426 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6427 ixgbe_set_rx_drop_en(adapter);
6428 }
93c52dd0
AD		 6429
6430 if (link_up ||
6431 time_after(jiffies, (adapter->link_check_timeout +
6432 IXGBE_TRY_LINK_TIMEOUT))) {
6433 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6434 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6435 IXGBE_WRITE_FLUSH(hw);
6436 }
6437
6438 adapter->link_up = link_up;
6439 adapter->link_speed = link_speed;
e8e26350
PW		 6440}
6441
107d3018
AD		 6442static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6443{
6444#ifdef CONFIG_IXGBE_DCB
6445 struct net_device *netdev = adapter->netdev;
6446 struct dcb_app app = {
6447 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6448 .protocol = 0,
6449 };
6450 u8 up = 0;
6451
6452 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6453 up = dcb_ieee_getapp_mask(netdev, &app);
6454
6455 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6456#endif
6457}
6458
e8e26350 6459/**
93c52dd0
AD		 6460 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6461 * print link up message
49ce9c2c 6462 * @adapter: pointer to the device adapter structure
e8e26350 6463 **/
93c52dd0 6464static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6465{
93c52dd0 6466 struct net_device *netdev = adapter->netdev;
e8e26350 6467 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6468 struct net_device *upper;
6469 struct list_head *iter;
93c52dd0 6470 u32 link_speed = adapter->link_speed;
454adb00 6471 const char *speed_str;
93c52dd0 6472 bool flow_rx, flow_tx;
e8e26350 6473
93c52dd0
AD		 6474 /* only continue if link was previously down */
6475 if (netif_carrier_ok(netdev))
a985b6c3 6476 return;
63d6e1d8 6477
93c52dd0 6478 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6479
93c52dd0
AD		 6480 switch (hw->mac.type) {
6481 case ixgbe_mac_82598EB: {
6482 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6483 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6484 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6485 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6486 }
6487 break;
6488 case ixgbe_mac_X540:
9a75a1ac
DS		 6489 case ixgbe_mac_X550:
6490 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6491 case ixgbe_mac_82599EB: {
6492 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6493 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6494 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6495 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6496 }
6497 break;
6498 default:
6499 flow_tx = false;
6500 flow_rx = false;
6501 break;
e8e26350 6502 }
3a6a4eda 6503
6cb562d6
JK		 6504 adapter->last_rx_ptp_check = jiffies;
6505
8fecf67c 6506 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6507 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6508
454adb00
MR		 6509 switch (link_speed) {
6510 case IXGBE_LINK_SPEED_10GB_FULL:
6511 speed_str = "10 Gbps";
6512 break;
6513 case IXGBE_LINK_SPEED_2_5GB_FULL:
6514 speed_str = "2.5 Gbps";
6515 break;
6516 case IXGBE_LINK_SPEED_1GB_FULL:
6517 speed_str = "1 Gbps";
6518 break;
6519 case IXGBE_LINK_SPEED_100_FULL:
6520 speed_str = "100 Mbps";
6521 break;
6522 default:
6523 speed_str = "unknown speed";
6524 break;
6525 }
6526 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6527 ((flow_rx && flow_tx) ? "RX/TX" :
6528 (flow_rx ? "RX" :
6529 (flow_tx ? "TX" : "None"))));
e8e26350 6530
93c52dd0 6531 netif_carrier_on(netdev);
93c52dd0 6532 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6533
cdc04dcc
ET		 6534 /* enable transmits */
6535 netif_tx_wake_all_queues(adapter->netdev);
6536
6537 /* enable any upper devices */
6538 rtnl_lock();
6539 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6540 if (netif_is_macvlan(upper)) {
6541 struct macvlan_dev *vlan = netdev_priv(upper);
6542
6543 if (vlan->fwd_priv)
6544 netif_tx_wake_all_queues(upper);
6545 }
6546 }
6547 rtnl_unlock();
6548
107d3018
AD		 6549 /* update the default user priority for VFs */
6550 ixgbe_update_default_up(adapter);
6551
befa2af7
AD		 6552 /* ping all the active vfs to let them know link has changed */
6553 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6554}
6555
c4cf55e5 6556/**
93c52dd0
AD		 6557 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6558 * print link down message
49ce9c2c 6559 * @adapter: pointer to the adapter structure
c4cf55e5 6560 **/
581330ba 6561static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6562{
cf8280ee 6563 struct net_device *netdev = adapter->netdev;
c4cf55e5 6564 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6565
93c52dd0
AD		 6566 adapter->link_up = false;
6567 adapter->link_speed = 0;
cf8280ee 6568
93c52dd0
AD		 6569 /* only continue if link was up previously */
6570 if (!netif_carrier_ok(netdev))
6571 return;
264857b8 6572
93c52dd0
AD		 6573 /* poll for SFP+ cable when link is down */
6574 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6575 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6576
8fecf67c 6577 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6578 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6579
93c52dd0
AD		 6580 e_info(drv, "NIC Link is Down\n");
6581 netif_carrier_off(netdev);
befa2af7
AD		 6582
6583 /* ping all the active vfs to let them know link has changed */
6584 ixgbe_ping_all_vfs(adapter);
93c52dd0 6585}
e8e26350 6586
07923c17
ET		 6587static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6588{
6589 int i;
6590
6591 for (i = 0; i < adapter->num_tx_queues; i++) {
6592 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6593
6594 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6595 return true;
6596 }
6597
6598 return false;
6599}
6600
6601static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6602{
6603 struct ixgbe_hw *hw = &adapter->hw;
6604 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6605 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6606
6607 int i, j;
6608
6609 if (!adapter->num_vfs)
6610 return false;
6611
9a75a1ac
DS		 6612 /* resetting the PF is only needed for MAC before X550 */
6613 if (hw->mac.type >= ixgbe_mac_X550)
6614 return false;
6615
07923c17
ET		 6616 for (i = 0; i < adapter->num_vfs; i++) {
6617 for (j = 0; j < q_per_pool; j++) {
6618 u32 h, t;
6619
6620 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6621 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6622
6623 if (h != t)
6624 return true;
6625 }
6626 }
6627
6628 return false;
6629}
6630
93c52dd0
AD		 6631/**
6632 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6633 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6634 **/
6635static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6636{
93c52dd0 6637 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6638 if (ixgbe_ring_tx_pending(adapter) ||
6639 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6640 /* We've lost link, so the controller stops DMA,
6641 * but we've got queued Tx work that's never going
6642 * to get done, so reset controller to flush Tx.
6643 * (Do the reset outside of interrupt context).
6644 */
12ff3f3b 6645 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6646 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6647 }
c4cf55e5 6648 }
c4cf55e5
PWJ		 6649}
6650
9079e416
ET		 6651#ifdef CONFIG_PCI_IOV
6652static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6653 struct pci_dev *vfdev)
6654{
6655 if (!pci_wait_for_pending_transaction(vfdev))
6656 e_dev_warn("Issuing VFLR with pending transactions\n");
6657
6658 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6659 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6660
6661 msleep(100);
6662}
6663
6664static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6665{
6666 struct ixgbe_hw *hw = &adapter->hw;
6667 struct pci_dev *pdev = adapter->pdev;
6668 struct pci_dev *vfdev;
6669 u32 gpc;
6670 int pos;
6671 unsigned short vf_id;
6672
6673 if (!(netif_carrier_ok(adapter->netdev)))
6674 return;
6675
6676 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6677 if (gpc) /* If incrementing then no need for the check below */
6678 return;
6679 /* Check to see if a bad DMA write target from an errant or
6680 * malicious VF has caused a PCIe error. If so then we can
6681 * issue a VFLR to the offending VF(s) and then resume without
6682 * requesting a full slot reset.
6683 */
6684
6685 if (!pdev)
6686 return;
6687
6688 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6689 if (!pos)
6690 return;
6691
6692 /* get the device ID for the VF */
6693 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6694
6695 /* check status reg for all VFs owned by this PF */
6696 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6697 while (vfdev) {
6698 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6699 u16 status_reg;
6700
6701 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6702 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6703 /* issue VFLR */
6704 ixgbe_issue_vf_flr(adapter, vfdev);
6705 }
6706
6707 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6708 }
6709}
6710
a985b6c3
GR		 6711static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6712{
6713 u32 ssvpc;
6714
0584d999
GR		 6715 /* Do not perform spoof check for 82598 or if not in IOV mode */
6716 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6717 adapter->num_vfs == 0)
a985b6c3
GR		 6718 return;
6719
6720 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6721
6722 /*
6723 * ssvpc register is cleared on read, if zero then no
6724 * spoofed packets in the last interval.
6725 */
6726 if (!ssvpc)
6727 return;
6728
d6ea0754 6729 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6730}
9079e416
ET		 6731#else
6732static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6733{
6734}
6735
6736static void
6737ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6738{
6739}
6740#endif /* CONFIG_PCI_IOV */
6741
a985b6c3 6742
93c52dd0
AD		 6743/**
6744 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6745 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6746 **/
6747static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6748{
09f40aed 6749 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6750 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6751 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6752 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6753 return;
6754
6755 ixgbe_watchdog_update_link(adapter);
6756
6757 if (adapter->link_up)
6758 ixgbe_watchdog_link_is_up(adapter);
6759 else
6760 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6761
9079e416 6762 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6763 ixgbe_spoof_check(adapter);
9a799d71 6764 ixgbe_update_stats(adapter);
93c52dd0
AD		 6765
6766 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6767}
10eec955 6768
cf8280ee 6769/**
7086400d 6770 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6771 * @adapter: the ixgbe adapter structure
cf8280ee 6772 **/
7086400d 6773static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6774{
cf8280ee 6775 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6776 s32 err;
cf8280ee 6777
7086400d
AD		 6778 /* not searching for SFP so there is nothing to do here */
6779 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6780 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6781 return;
10eec955 6782
58e7cd24
MR		 6783 if (adapter->sfp_poll_time &&
6784 time_after(adapter->sfp_poll_time, jiffies))
6785 return; /* If not yet time to poll for SFP */
6786
7086400d
AD		 6787 /* someone else is in init, wait until next service event */
6788 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6789 return;
cf8280ee 6790
58e7cd24
MR		 6791 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6792
7086400d
AD		 6793 err = hw->phy.ops.identify_sfp(hw);
6794 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6795 goto sfp_out;
264857b8 6796
7086400d
AD		 6797 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6798 /* If no cable is present, then we need to reset
6799 * the next time we find a good cable. */
6800 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6801 }
9a799d71 6802
7086400d
AD		 6803 /* exit on error */
6804 if (err)
6805 goto sfp_out;
e8e26350 6806
7086400d
AD		 6807 /* exit if reset not needed */
6808 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6809 goto sfp_out;
9a799d71 6810
7086400d 6811 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6812
7086400d
AD		 6813 /*
6814 * A module may be identified correctly, but the EEPROM may not have
6815 * support for that module. setup_sfp() will fail in that case, so
6816 * we should not allow that module to load.
6817 */
6818 if (hw->mac.type == ixgbe_mac_82598EB)
6819 err = hw->phy.ops.reset(hw);
6820 else
6821 err = hw->mac.ops.setup_sfp(hw);
6822
6823 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6824 goto sfp_out;
6825
6826 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6827 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6828
6829sfp_out:
6830 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6831
6832 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6833 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6834 e_dev_err("failed to initialize because an unsupported "
6835 "SFP+ module type was detected.\n");
6836 e_dev_err("Reload the driver after installing a "
6837 "supported module.\n");
6838 unregister_netdev(adapter->netdev);
bc59fcda 6839 }
7086400d 6840}
bc59fcda 6841
7086400d
AD		 6842/**
6843 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6844 * @adapter: the ixgbe adapter structure
7086400d
AD		 6845 **/
6846static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6847{
6848 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6849 u32 speed;
6850 bool autoneg = false;
7086400d
AD		 6851
6852 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6853 return;
6854
6855 /* someone else is in init, wait until next service event */
6856 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6857 return;
6858
6859 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6860
3d292265 6861 speed = hw->phy.autoneg_advertised;
ed33ff66 6862 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6863 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6864
6865 /* setup the highest link when no autoneg */
6866 if (!autoneg) {
6867 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6868 speed = IXGBE_LINK_SPEED_10GB_FULL;
6869 }
6870 }
6871
7086400d 6872 if (hw->mac.ops.setup_link)
fd0326f2 6873 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6874
6875 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6876 adapter->link_check_timeout = jiffies;
6877 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6878}
6879
6880/**
6881 * ixgbe_service_timer - Timer Call-back
6882 * @data: pointer to adapter cast into an unsigned long
6883 **/
6884static void ixgbe_service_timer(unsigned long data)
6885{
6886 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6887 unsigned long next_event_offset;
6888
6bb78cfb
AD		 6889 /* poll faster when waiting for link */
6890 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6891 next_event_offset = HZ / 10;
6892 else
6893 next_event_offset = HZ * 2;
83c61fa9 6894
7086400d
AD		 6895 /* Reset the timer */
6896 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6897
9079e416 6898 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6899}
6900
597f22d6
DS		 6901static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6902{
6903 struct ixgbe_hw *hw = &adapter->hw;
6904 u32 status;
6905
6906 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6907 return;
6908
6909 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6910
6911 if (!hw->phy.ops.handle_lasi)
6912 return;
6913
6914 status = hw->phy.ops.handle_lasi(&adapter->hw);
6915 if (status != IXGBE_ERR_OVERTEMP)
6916 return;
6917
6918 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6919}
6920
c83c6cbd
AD		 6921static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6922{
6923 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6924 return;
6925
6926 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6927
09f40aed 6928 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6929 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6930 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6931 test_bit(__IXGBE_RESETTING, &adapter->state))
6932 return;
6933
6934 ixgbe_dump(adapter);
6935 netdev_err(adapter->netdev, "Reset adapter\n");
6936 adapter->tx_timeout_count++;
6937
8f4c5c9f 6938 rtnl_lock();
c83c6cbd 6939 ixgbe_reinit_locked(adapter);
8f4c5c9f 6940 rtnl_unlock();
c83c6cbd
AD		 6941}
6942
7086400d
AD		 6943/**
6944 * ixgbe_service_task - manages and runs subtasks
6945 * @work: pointer to work_struct containing our data
6946 **/
6947static void ixgbe_service_task(struct work_struct *work)
6948{
6949 struct ixgbe_adapter *adapter = container_of(work,
6950 struct ixgbe_adapter,
6951 service_task);
b0483c8f
MR		 6952 if (ixgbe_removed(adapter->hw.hw_addr)) {
6953 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6954 rtnl_lock();
6955 ixgbe_down(adapter);
6956 rtnl_unlock();
6957 }
6958 ixgbe_service_event_complete(adapter);
6959 return;
6960 }
67359c3c
MR		 6961#ifdef CONFIG_IXGBE_VXLAN
6962 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6963 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6964 vxlan_get_rx_port(adapter->netdev);
6965 }
6966#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 6967 ixgbe_reset_subtask(adapter);
597f22d6 6968 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 6969 ixgbe_sfp_detection_subtask(adapter);
6970 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6971 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6972 ixgbe_watchdog_subtask(adapter);
d034acf1 6973 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6974 ixgbe_check_hang_subtask(adapter);
891dc082 6975
8fecf67c 6976 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6977 ixgbe_ptp_overflow_check(adapter);
6978 ixgbe_ptp_rx_hang(adapter);
6979 }
7086400d
AD		 6980
6981 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6982}
6983
fd0db0ed
AD		 6984static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6985 struct ixgbe_tx_buffer *first,
244e27ad 6986 u8 *hdr_len)
897ab156 6987{
fd0db0ed 6988 struct sk_buff *skb = first->skb;
897ab156
AD		 6989 u32 vlan_macip_lens, type_tucmd;
6990 u32 mss_l4len_idx, l4len;
2049e1f6 6991 int err;
9a799d71 6992
8f4fbb9b
AD		 6993 if (skb->ip_summed != CHECKSUM_PARTIAL)
6994 return 0;
6995
897ab156
AD		 6996 if (!skb_is_gso(skb))
6997 return 0;
9a799d71 6998
2049e1f6
FR		 6999 err = skb_cow_head(skb, 0);
7000 if (err < 0)
7001 return err;
9a799d71 7002
897ab156
AD		 7003 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7004 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7005
a1108ffd 7006 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 7007 struct iphdr *iph = ip_hdr(skb);
7008 iph->tot_len = 0;
7009 iph->check = 0;
7010 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7011 iph->daddr, 0,
7012 IPPROTO_TCP,
7013 0);
7014 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 7015 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7016 IXGBE_TX_FLAGS_CSUM |
7017 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 7018 } else if (skb_is_gso_v6(skb)) {
7019 ipv6_hdr(skb)->payload_len = 0;
7020 tcp_hdr(skb)->check =
7021 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7022 &ipv6_hdr(skb)->daddr,
7023 0, IPPROTO_TCP, 0);
244e27ad
AD		 7024 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7025 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7026 }
7027
091a6246 7028 /* compute header lengths */
897ab156
AD		 7029 l4len = tcp_hdrlen(skb);
7030 *hdr_len = skb_transport_offset(skb) + l4len;
7031
091a6246
AD		 7032 /* update gso size and bytecount with header size */
7033 first->gso_segs = skb_shinfo(skb)->gso_segs;
7034 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7035
c44f5f51 7036 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 7037 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7038 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7039
7040 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7041 vlan_macip_lens = skb_network_header_len(skb);
7042 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7043 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7044
7045 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7046 mss_l4len_idx);
897ab156
AD		 7047
7048 return 1;
7049}
7050
244e27ad
AD		 7051static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7052 struct ixgbe_tx_buffer *first)
7ca647bd 7053{
fd0db0ed 7054 struct sk_buff *skb = first->skb;
897ab156
AD		 7055 u32 vlan_macip_lens = 0;
7056 u32 mss_l4len_idx = 0;
7057 u32 type_tucmd = 0;
7ca647bd 7058
897ab156 7059 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 7060 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7061 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7062 return;
f467bc06
MR		 7063 vlan_macip_lens = skb_network_offset(skb) <<
7064 IXGBE_ADVTXD_MACLEN_SHIFT;
897ab156
AD		 7065 } else {
7066 u8 l4_hdr = 0;
f467bc06
MR		 7067 union {
7068 struct iphdr *ipv4;
7069 struct ipv6hdr *ipv6;
7070 u8 *raw;
7071 } network_hdr;
7072 union {
7073 struct tcphdr *tcphdr;
7074 u8 *raw;
7075 } transport_hdr;
7076
7077 if (skb->encapsulation) {
7078 network_hdr.raw = skb_inner_network_header(skb);
7079 transport_hdr.raw = skb_inner_transport_header(skb);
7080 vlan_macip_lens = skb_inner_network_offset(skb) <<
7081 IXGBE_ADVTXD_MACLEN_SHIFT;
7082 } else {
7083 network_hdr.raw = skb_network_header(skb);
7084 transport_hdr.raw = skb_transport_header(skb);
7085 vlan_macip_lens = skb_network_offset(skb) <<
7086 IXGBE_ADVTXD_MACLEN_SHIFT;
7087 }
7088
7089 /* use first 4 bits to determine IP version */
7090 switch (network_hdr.ipv4->version) {
7091 case IPVERSION:
7092 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
897ab156 7093 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
f467bc06 7094 l4_hdr = network_hdr.ipv4->protocol;
7ca647bd 7095 break;
f467bc06
MR		 7096 case 6:
7097 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7098 l4_hdr = network_hdr.ipv6->nexthdr;
897ab156
AD		 7099 break;
7100 default:
7101 if (unlikely(net_ratelimit())) {
7102 dev_warn(tx_ring->dev,
f467bc06
MR		 7103 "partial checksum but version=%d\n",
7104 network_hdr.ipv4->version);
897ab156 7105 }
7ca647bd 7106 }
897ab156
AD		 7107
7108 switch (l4_hdr) {
7ca647bd 7109 case IPPROTO_TCP:
897ab156 7110 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
f467bc06 7111 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
897ab156 7112 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 7113 break;
7114 case IPPROTO_SCTP:
897ab156
AD		 7115 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7116 mss_l4len_idx = sizeof(struct sctphdr) <<
7117 IXGBE_ADVTXD_L4LEN_SHIFT;
7118 break;
7119 case IPPROTO_UDP:
7120 mss_l4len_idx = sizeof(struct udphdr) <<
7121 IXGBE_ADVTXD_L4LEN_SHIFT;
7122 break;
7123 default:
7124 if (unlikely(net_ratelimit())) {
7125 dev_warn(tx_ring->dev,
7126 "partial checksum but l4 proto=%x!\n",
244e27ad 7127 l4_hdr);
897ab156 7128 }
7ca647bd
JP		 7129 break;
7130 }
244e27ad
AD		 7131
7132 /* update TX checksum flag */
7133 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 7134 }
7135
244e27ad 7136 /* vlan_macip_lens: MACLEN, VLAN tag */
244e27ad 7137 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7138
897ab156
AD		 7139 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7140 type_tucmd, mss_l4len_idx);
9a799d71
AK		 7141}
7142
472148c3
AD		 7143#define IXGBE_SET_FLAG(_input, _flag, _result) \
7144 ((_flag <= _result) ? \
7145 ((u32)(_input & _flag) * (_result / _flag)) : \
7146 ((u32)(_input & _flag) / (_flag / _result)))
7147
7148static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7149{
d3d00239 7150 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7151 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7152 IXGBE_ADVTXD_DCMD_DEXT |
7153 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7154
d3d00239 7155 /* set HW vlan bit if vlan is present */
472148c3
AD		 7156 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7157 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7158
d3d00239 7159 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7160 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7161 IXGBE_ADVTXD_DCMD_TSE);
7162
7163 /* set timestamp bit if present */
7164 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7165 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7166
62748b7b 7167 /* insert frame checksum */
472148c3 7168 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7169
d3d00239
AD		 7170 return cmd_type;
7171}
9a799d71 7172
729739b7
AD		 7173static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7174 u32 tx_flags, unsigned int paylen)
d3d00239 7175{
472148c3 7176 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7177
d3d00239 7178 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7179 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7180 IXGBE_TX_FLAGS_CSUM,
7181 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7182
93f5b3c1 7183 /* enble IPv4 checksum for TSO */
472148c3
AD		 7184 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7185 IXGBE_TX_FLAGS_IPV4,
7186 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7187
7f9643fd
AD		 7188 /*
7189 * Check Context must be set if Tx switch is enabled, which it
7190 * always is for case where virtual functions are running
7191 */
472148c3
AD		 7192 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7193 IXGBE_TX_FLAGS_CC,
7194 IXGBE_ADVTXD_CC);
7f9643fd 7195
472148c3 7196 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7197}
44df32c5 7198
2367a173
DB		 7199static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7200{
7201 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7202
7203 /* Herbert's original patch had:
7204 * smp_mb__after_netif_stop_queue();
7205 * but since that doesn't exist yet, just open code it.
7206 */
7207 smp_mb();
7208
7209 /* We need to check again in a case another CPU has just
7210 * made room available.
7211 */
7212 if (likely(ixgbe_desc_unused(tx_ring) < size))
7213 return -EBUSY;
7214
7215 /* A reprieve! - use start_queue because it doesn't call schedule */
7216 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7217 ++tx_ring->tx_stats.restart_queue;
7218 return 0;
7219}
7220
7221static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7222{
7223 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7224 return 0;
7225
7226 return __ixgbe_maybe_stop_tx(tx_ring, size);
7227}
7228
d3d00239
AD		 7229#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7230 IXGBE_TXD_CMD_RS)
7231
7232static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7233 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7234 const u8 hdr_len)
7235{
fd0db0ed 7236 struct sk_buff *skb = first->skb;
729739b7 7237 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7238 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7239 struct skb_frag_struct *frag;
7240 dma_addr_t dma;
7241 unsigned int data_len, size;
244e27ad 7242 u32 tx_flags = first->tx_flags;
472148c3 7243 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7244 u16 i = tx_ring->next_to_use;
d3d00239 7245
729739b7
AD		 7246 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7247
ec718254
AD		 7248 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7249
7250 size = skb_headlen(skb);
7251 data_len = skb->data_len;
729739b7 7252
d3d00239
AD		 7253#ifdef IXGBE_FCOE
7254 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7255 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7256 size -= sizeof(struct fcoe_crc_eof) - data_len;
7257 data_len = 0;
729739b7
AD		 7258 } else {
7259 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7260 }
7261 }
44df32c5 7262
d3d00239 7263#endif
729739b7 7264 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7265
ec718254 7266 tx_buffer = first;
9a799d71 7267
ec718254
AD		 7268 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7269 if (dma_mapping_error(tx_ring->dev, dma))
7270 goto dma_error;
7271
7272 /* record length, and DMA address */
7273 dma_unmap_len_set(tx_buffer, len, size);
7274 dma_unmap_addr_set(tx_buffer, dma, dma);
7275
7276 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7277
729739b7 7278 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7279 tx_desc->read.cmd_type_len =
472148c3 7280 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7281
d3d00239 7282 i++;
729739b7 7283 tx_desc++;
d3d00239 7284 if (i == tx_ring->count) {
e4f74028 7285 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7286 i = 0;
7287 }
ec718254 7288 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7289
7290 dma += IXGBE_MAX_DATA_PER_TXD;
7291 size -= IXGBE_MAX_DATA_PER_TXD;
7292
7293 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7294 }
e5a43549 7295
729739b7
AD		 7296 if (likely(!data_len))
7297 break;
9a799d71 7298
472148c3 7299 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7300
729739b7
AD		 7301 i++;
7302 tx_desc++;
7303 if (i == tx_ring->count) {
7304 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7305 i = 0;
7306 }
ec718254 7307 tx_desc->read.olinfo_status = 0;
9a799d71 7308
d3d00239 7309#ifdef IXGBE_FCOE
9e903e08 7310 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7311#else
9e903e08 7312 size = skb_frag_size(frag);
d3d00239
AD		 7313#endif
7314 data_len -= size;
9a799d71 7315
729739b7
AD		 7316 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7317 DMA_TO_DEVICE);
9a799d71 7318
729739b7 7319 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7320 }
9a799d71 7321
729739b7 7322 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7323 cmd_type |= size | IXGBE_TXD_CMD;
7324 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7325
091a6246 7326 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7327
d3d00239
AD		 7328 /* set the timestamp */
7329 first->time_stamp = jiffies;
9a799d71
AK		 7330
7331 /*
729739b7
AD		 7332 * Force memory writes to complete before letting h/w know there
7333 * are new descriptors to fetch. (Only applicable for weak-ordered
7334 * memory model archs, such as IA-64).
7335 *
7336 * We also need this memory barrier to make certain all of the
7337 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7338 */
7339 wmb();
7340
d3d00239
AD		 7341 /* set next_to_watch value indicating a packet is present */
7342 first->next_to_watch = tx_desc;
7343
729739b7
AD		 7344 i++;
7345 if (i == tx_ring->count)
7346 i = 0;
7347
7348 tx_ring->next_to_use = i;
7349
2367a173
DB		 7350 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7351
7352 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7353 writel(i, tx_ring->tail);
7354
7355 /* we need this if more than one processor can write to our tail
7356 * at a time, it synchronizes IO on IA64/Altix systems
7357 */
7358 mmiowb();
9c938cdd 7359 }
2367a173 7360
d3d00239
AD		 7361 return;
7362dma_error:
729739b7 7363 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7364
7365 /* clear dma mappings for failed tx_buffer_info map */
7366 for (;;) {
729739b7
AD		 7367 tx_buffer = &tx_ring->tx_buffer_info[i];
7368 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7369 if (tx_buffer == first)
d3d00239
AD		 7370 break;
7371 if (i == 0)
7372 i = tx_ring->count;
7373 i--;
7374 }
7375
d3d00239 7376 tx_ring->next_to_use = i;
9a799d71
AK		 7377}
7378
fd0db0ed 7379static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7380 struct ixgbe_tx_buffer *first)
69830529
AD		 7381{
7382 struct ixgbe_q_vector *q_vector = ring->q_vector;
7383 union ixgbe_atr_hash_dword input = { .dword = 0 };
7384 union ixgbe_atr_hash_dword common = { .dword = 0 };
7385 union {
7386 unsigned char *network;
7387 struct iphdr *ipv4;
7388 struct ipv6hdr *ipv6;
7389 } hdr;
ee9e0f0b 7390 struct tcphdr *th;
67359c3c
MR		 7391 struct sk_buff *skb;
7392#ifdef CONFIG_IXGBE_VXLAN
7393 u8 encap = false;
7394#endif /* CONFIG_IXGBE_VXLAN */
905e4a41 7395 __be16 vlan_id;
c4cf55e5 7396
69830529
AD		 7397 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7398 if (!q_vector)
7399 return;
7400
7401 /* do nothing if sampling is disabled */
7402 if (!ring->atr_sample_rate)
d3ead241 7403 return;
c4cf55e5 7404
69830529 7405 ring->atr_count++;
c4cf55e5 7406
69830529 7407 /* snag network header to get L4 type and address */
67359c3c
MR		 7408 skb = first->skb;
7409 hdr.network = skb_network_header(skb);
7410 if (skb->encapsulation) {
7411#ifdef CONFIG_IXGBE_VXLAN
7412 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7413
67359c3c
MR		 7414 if (!adapter->vxlan_port)
7415 return;
7416 if (first->protocol != htons(ETH_P_IP) ||
7417 hdr.ipv4->version != IPVERSION ||
7418 hdr.ipv4->protocol != IPPROTO_UDP) {
7419 return;
7420 }
7421 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7422 return;
7423 encap = true;
7424 hdr.network = skb_inner_network_header(skb);
7425 th = inner_tcp_hdr(skb);
7426#else
69830529 7427 return;
67359c3c
MR		 7428#endif /* CONFIG_IXGBE_VXLAN */
7429 } else {
7430 /* Currently only IPv4/IPv6 with TCP is supported */
7431 if ((first->protocol != htons(ETH_P_IPV6) ||
7432 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7433 (first->protocol != htons(ETH_P_IP) ||
7434 hdr.ipv4->protocol != IPPROTO_TCP))
7435 return;
7436 th = tcp_hdr(skb);
7437 }
c4cf55e5 7438
66f32a8b
AD		 7439 /* skip this packet since it is invalid or the socket is closing */
7440 if (!th || th->fin)
69830529
AD		 7441 return;
7442
7443 /* sample on all syn packets or once every atr sample count */
7444 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7445 return;
7446
7447 /* reset sample count */
7448 ring->atr_count = 0;
7449
244e27ad 7450 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7451
7452 /*
7453 * src and dst are inverted, think how the receiver sees them
7454 *
7455 * The input is broken into two sections, a non-compressed section
7456 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7457 * is XORed together and stored in the compressed dword.
7458 */
7459 input.formatted.vlan_id = vlan_id;
7460
7461 /*
7462 * since src port and flex bytes occupy the same word XOR them together
7463 * and write the value to source port portion of compressed dword
7464 */
244e27ad 7465 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7466 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7467 else
244e27ad 7468 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7469 common.port.dst ^= th->source;
7470
a1108ffd 7471 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7472 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7473 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7474 } else {
7475 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7476 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7477 hdr.ipv6->saddr.s6_addr32[1] ^
7478 hdr.ipv6->saddr.s6_addr32[2] ^
7479 hdr.ipv6->saddr.s6_addr32[3] ^
7480 hdr.ipv6->daddr.s6_addr32[0] ^
7481 hdr.ipv6->daddr.s6_addr32[1] ^
7482 hdr.ipv6->daddr.s6_addr32[2] ^
7483 hdr.ipv6->daddr.s6_addr32[3];
7484 }
c4cf55e5 7485
67359c3c
MR		 7486#ifdef CONFIG_IXGBE_VXLAN
7487 if (encap)
7488 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7489#endif /* CONFIG_IXGBE_VXLAN */
7490
c4cf55e5 7491 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7492 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7493 input, common, ring->queue_index);
c4cf55e5
PWJ		 7494}
7495
f663dd9a 7496static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7497 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7498{
f663dd9a
JW		 7499 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7500#ifdef IXGBE_FCOE
97488bd1
AD		 7501 struct ixgbe_adapter *adapter;
7502 struct ixgbe_ring_feature *f;
7503 int txq;
f663dd9a
JW		 7504#endif
7505
7506 if (fwd_adapter)
7507 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7508
7509#ifdef IXGBE_FCOE
5e09a105 7510
97488bd1
AD		 7511 /*
7512 * only execute the code below if protocol is FCoE
7513 * or FIP and we have FCoE enabled on the adapter
7514 */
7515 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7516 case htons(ETH_P_FCOE):
7517 case htons(ETH_P_FIP):
97488bd1 7518 adapter = netdev_priv(dev);
c087663e 7519
97488bd1
AD		 7520 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7521 break;
7522 default:
99932d4f 7523 return fallback(dev, skb);
97488bd1 7524 }
c087663e 7525
97488bd1 7526 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7527
97488bd1
AD		 7528 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7529 smp_processor_id();
56075a98 7530
97488bd1
AD		 7531 while (txq >= f->indices)
7532 txq -= f->indices;
c4cf55e5 7533
97488bd1 7534 return txq + f->offset;
f663dd9a 7535#else
99932d4f 7536 return fallback(dev, skb);
f663dd9a 7537#endif
09a3b1f8
SH		 7538}
7539
fc77dc3c 7540netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7541 struct ixgbe_adapter *adapter,
7542 struct ixgbe_ring *tx_ring)
9a799d71 7543{
d3d00239 7544 struct ixgbe_tx_buffer *first;
5f715823 7545 int tso;
d3d00239 7546 u32 tx_flags = 0;
a535c30e 7547 unsigned short f;
a535c30e 7548 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7549 __be16 protocol = skb->protocol;
63544e9c 7550 u8 hdr_len = 0;
5e09a105 7551
a535c30e
AD		 7552 /*
7553 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7554 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7555 * + 2 desc gap to keep tail from touching head,
7556 * + 1 desc for context descriptor,
7557 * otherwise try next time
7558 */
a535c30e
AD		 7559 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7560 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7561
a535c30e
AD		 7562 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7563 tx_ring->tx_stats.tx_busy++;
7564 return NETDEV_TX_BUSY;
7565 }
7566
fd0db0ed
AD		 7567 /* record the location of the first descriptor for this packet */
7568 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7569 first->skb = skb;
091a6246
AD		 7570 first->bytecount = skb->len;
7571 first->gso_segs = 1;
fd0db0ed 7572
66f32a8b 7573 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7574 if (skb_vlan_tag_present(skb)) {
7575 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7576 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7577 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7578 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7579 struct vlan_hdr *vhdr, _vhdr;
7580 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7581 if (!vhdr)
7582 goto out_drop;
7583
9e0c5648
AD		 7584 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7585 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7586 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7587 }
0213668f 7588 protocol = vlan_get_protocol(skb);
66f32a8b 7589
d5234933
MR		 7590 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7591 adapter->ptp_clock &&
7592 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7593 &adapter->state)) {
3a6a4eda
JK		 7594 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7595 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7596
7597 /* schedule check for Tx timestamp */
7598 adapter->ptp_tx_skb = skb_get(skb);
7599 adapter->ptp_tx_start = jiffies;
7600 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7601 }
3a6a4eda 7602
ff29a86e
JK		 7603 skb_tx_timestamp(skb);
7604
9e0c5648
AD		 7605#ifdef CONFIG_PCI_IOV
7606 /*
7607 * Use the l2switch_enable flag - would be false if the DMA
7608 * Tx switch had been disabled.
7609 */
7610 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7611 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7612
7613#endif
32701dc2 7614 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7615 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7616 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7617 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7618 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7619 tx_flags |= (skb->priority & 0x7) <<
7620 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7621 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7622 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7623
7624 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7625 goto out_drop;
7626 vhdr = (struct vlan_ethhdr *)skb->data;
7627 vhdr->h_vlan_TCI = htons(tx_flags >>
7628 IXGBE_TX_FLAGS_VLAN_SHIFT);
7629 } else {
7630 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7631 }
9a799d71 7632 }
eacd73f7 7633
244e27ad
AD		 7634 /* record initial flags and protocol */
7635 first->tx_flags = tx_flags;
7636 first->protocol = protocol;
7637
eacd73f7 7638#ifdef IXGBE_FCOE
66f32a8b 7639 /* setup tx offload for FCoE */
a1108ffd 7640 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7641 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7642 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7643 if (tso < 0)
7644 goto out_drop;
9a799d71 7645
66f32a8b 7646 goto xmit_fcoe;
eacd73f7 7647 }
9a799d71 7648
66f32a8b 7649#endif /* IXGBE_FCOE */
244e27ad 7650 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7651 if (tso < 0)
897ab156 7652 goto out_drop;
244e27ad
AD		 7653 else if (!tso)
7654 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7655
7656 /* add the ATR filter if ATR is on */
7657 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7658 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7659
7660#ifdef IXGBE_FCOE
7661xmit_fcoe:
7662#endif /* IXGBE_FCOE */
244e27ad 7663 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7664
9a799d71 7665 return NETDEV_TX_OK;
897ab156
AD		 7666
7667out_drop:
fd0db0ed
AD		 7668 dev_kfree_skb_any(first->skb);
7669 first->skb = NULL;
7670
897ab156 7671 return NETDEV_TX_OK;
9a799d71
AK		 7672}
7673
2a47fa45
JF		 7674static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7675 struct net_device *netdev,
7676 struct ixgbe_ring *ring)
84418e3b
AD		 7677{
7678 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7679 struct ixgbe_ring *tx_ring;
7680
a50c29dd
AD		 7681 /*
7682 * The minimum packet size for olinfo paylen is 17 so pad the skb
7683 * in order to meet this minimum size requirement.
7684 */
a94d9e22
AD		 7685 if (skb_put_padto(skb, 17))
7686 return NETDEV_TX_OK;
a50c29dd 7687
2a47fa45
JF		 7688 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7689
fc77dc3c 7690 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7691}
7692
2a47fa45
JF		 7693static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7694 struct net_device *netdev)
7695{
7696 return __ixgbe_xmit_frame(skb, netdev, NULL);
7697}
7698
9a799d71
AK		 7699/**
7700 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7701 * @netdev: network interface device structure
7702 * @p: pointer to an address structure
7703 *
7704 * Returns 0 on success, negative on failure
7705 **/
7706static int ixgbe_set_mac(struct net_device *netdev, void *p)
7707{
7708 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7709 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7710 struct sockaddr *addr = p;
7711
7712 if (!is_valid_ether_addr(addr->sa_data))
7713 return -EADDRNOTAVAIL;
7714
7715 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7716 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7717
c9f53e63
AD		 7718 ixgbe_mac_set_default_filter(adapter);
7719
7720 return 0;
9a799d71
AK		 7721}
7722
6b73e10d
BH		 7723static int
7724ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7725{
7726 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7727 struct ixgbe_hw *hw = &adapter->hw;
7728 u16 value;
7729 int rc;
7730
7731 if (prtad != hw->phy.mdio.prtad)
7732 return -EINVAL;
7733 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7734 if (!rc)
7735 rc = value;
7736 return rc;
7737}
7738
7739static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7740 u16 addr, u16 value)
7741{
7742 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7743 struct ixgbe_hw *hw = &adapter->hw;
7744
7745 if (prtad != hw->phy.mdio.prtad)
7746 return -EINVAL;
7747 return hw->phy.ops.write_reg(hw, addr, devad, value);
7748}
7749
7750static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7751{
7752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7753
3a6a4eda 7754 switch (cmd) {
3a6a4eda 7755 case SIOCSHWTSTAMP:
93501d48
JK		 7756 return ixgbe_ptp_set_ts_config(adapter, req);
7757 case SIOCGHWTSTAMP:
7758 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7759 default:
7760 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7761 }
6b73e10d
BH		 7762}
7763
0365e6e4
PW		 7764/**
7765 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7766 * netdev->dev_addrs
0365e6e4
PW		 7767 * @netdev: network interface device structure
7768 *
7769 * Returns non-zero on failure
7770 **/
7771static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7772{
7773 int err = 0;
7774 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7775 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7776
7fa7c9dc 7777 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7778 rtnl_lock();
7fa7c9dc 7779 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7780 rtnl_unlock();
7fa7c9dc
AD		 7781
7782 /* update SAN MAC vmdq pool selection */
7783 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7784 }
7785 return err;
7786}
7787
7788/**
7789 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7790 * netdev->dev_addrs
0365e6e4
PW		 7791 * @netdev: network interface device structure
7792 *
7793 * Returns non-zero on failure
7794 **/
7795static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7796{
7797 int err = 0;
7798 struct ixgbe_adapter *adapter = netdev_priv(dev);
7799 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7800
7801 if (is_valid_ether_addr(mac->san_addr)) {
7802 rtnl_lock();
7803 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7804 rtnl_unlock();
7805 }
7806 return err;
7807}
7808
9a799d71
AK		 7809#ifdef CONFIG_NET_POLL_CONTROLLER
7810/*
7811 * Polling 'interrupt' - used by things like netconsole to send skbs
7812 * without having to re-enable interrupts. It's not called while
7813 * the interrupt routine is executing.
7814 */
7815static void ixgbe_netpoll(struct net_device *netdev)
7816{
7817 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7818 int i;
9a799d71 7819
1a647bd2
AD		 7820 /* if interface is down do nothing */
7821 if (test_bit(__IXGBE_DOWN, &adapter->state))
7822 return;
7823
856f606e
AD		 7824 /* loop through and schedule all active queues */
7825 for (i = 0; i < adapter->num_q_vectors; i++)
7826 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 7827}
9a799d71 7828
581330ba 7829#endif
de1036b1
ED		 7830static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7831 struct rtnl_link_stats64 *stats)
7832{
7833 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7834 int i;
7835
1a51502b 7836 rcu_read_lock();
de1036b1 7837 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7838 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7839 u64 bytes, packets;
7840 unsigned int start;
7841
1a51502b
ED		 7842 if (ring) {
7843 do {
57a7744e 7844 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7845 packets = ring->stats.packets;
7846 bytes = ring->stats.bytes;
57a7744e 7847 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7848 stats->rx_packets += packets;
7849 stats->rx_bytes += bytes;
7850 }
de1036b1 7851 }
1ac9ad13
ED		 7852
7853 for (i = 0; i < adapter->num_tx_queues; i++) {
7854 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7855 u64 bytes, packets;
7856 unsigned int start;
7857
7858 if (ring) {
7859 do {
57a7744e 7860 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7861 packets = ring->stats.packets;
7862 bytes = ring->stats.bytes;
57a7744e 7863 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7864 stats->tx_packets += packets;
7865 stats->tx_bytes += bytes;
7866 }
7867 }
1a51502b 7868 rcu_read_unlock();
de1036b1
ED		 7869 /* following stats updated by ixgbe_watchdog_task() */
7870 stats->multicast = netdev->stats.multicast;
7871 stats->rx_errors = netdev->stats.rx_errors;
7872 stats->rx_length_errors = netdev->stats.rx_length_errors;
7873 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7874 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7875 return stats;
7876}
7877
8af3c33f 7878#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7879/**
7880 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7881 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7882 * @tc: number of traffic classes currently enabled
7883 *
7884 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7885 * 802.1Q priority maps to a packet buffer that exists.
7886 */
7887static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7888{
7889 struct ixgbe_hw *hw = &adapter->hw;
7890 u32 reg, rsave;
7891 int i;
7892
7893 /* 82598 have a static priority to TC mapping that can not
7894 * be changed so no validation is needed.
7895 */
7896 if (hw->mac.type == ixgbe_mac_82598EB)
7897 return;
7898
7899 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7900 rsave = reg;
7901
7902 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7903 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7904
7905 /* If up2tc is out of bounds default to zero */
7906 if (up2tc > tc)
7907 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7908 }
7909
7910 if (reg != rsave)
7911 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7912
7913 return;
7914}
7915
02debdc9
AD		 7916/**
7917 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7918 * @adapter: Pointer to adapter struct
7919 *
7920 * Populate the netdev user priority to tc map
7921 */
7922static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7923{
7924 struct net_device *dev = adapter->netdev;
7925 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7926 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7927 u8 prio;
7928
7929 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7930 u8 tc = 0;
7931
7932 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7933 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7934 else if (ets)
7935 tc = ets->prio_tc[prio];
7936
7937 netdev_set_prio_tc_map(dev, prio, tc);
7938 }
7939}
7940
cca73c59 7941#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7942/**
7943 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7944 *
7945 * @netdev: net device to configure
7946 * @tc: number of traffic classes to enable
7947 */
7948int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7949{
8b1c0b24
JF		 7950 struct ixgbe_adapter *adapter = netdev_priv(dev);
7951 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7952 bool pools;
8b1c0b24 7953
8b1c0b24 7954 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 7955 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
7956 return -EINVAL;
7957
7958 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 7959 return -EINVAL;
7960
2a47fa45
JF		 7961 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7962 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7963 return -EBUSY;
7964
8b1c0b24 7965 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7966 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7967 * hardware is not flexible enough to do this dynamically.
7968 */
7969 if (netif_running(dev))
7970 ixgbe_close(dev);
7971 ixgbe_clear_interrupt_scheme(adapter);
7972
cca73c59 7973#ifdef CONFIG_IXGBE_DCB
e7589eab 7974 if (tc) {
8b1c0b24 7975 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7976 ixgbe_set_prio_tc_map(adapter);
7977
e7589eab 7978 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7979
943561d3
AD		 7980 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7981 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7982 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7983 }
e7589eab 7984 } else {
8b1c0b24 7985 netdev_reset_tc(dev);
02debdc9 7986
943561d3
AD		 7987 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7988 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7989
7990 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7991
7992 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7993 adapter->dcb_cfg.pfc_mode_enable = false;
7994 }
7995
8b1c0b24 7996 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7997
7998#endif /* CONFIG_IXGBE_DCB */
7999 ixgbe_init_interrupt_scheme(adapter);
8000
8b1c0b24 8001 if (netif_running(dev))
cca73c59 8002 return ixgbe_open(dev);
8b1c0b24
JF		 8003
8004 return 0;
8005}
de1036b1 8006
da36b647
GR		 8007#ifdef CONFIG_PCI_IOV
8008void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8009{
8010 struct net_device *netdev = adapter->netdev;
8011
8012 rtnl_lock();
da36b647 8013 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 8014 rtnl_unlock();
8015}
8016
8017#endif
082757af
DS		 8018void ixgbe_do_reset(struct net_device *netdev)
8019{
8020 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8021
8022 if (netif_running(netdev))
8023 ixgbe_reinit_locked(adapter);
8024 else
8025 ixgbe_reset(adapter);
8026}
8027
c8f44aff 8028static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 8029 netdev_features_t features)
082757af
DS		 8030{
8031 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8032
082757af 8033 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 8034 if (!(features & NETIF_F_RXCSUM))
8035 features &= ~NETIF_F_LRO;
082757af 8036
567d2de2
AD		 8037 /* Turn off LRO if not RSC capable */
8038 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8039 features &= ~NETIF_F_LRO;
8e2813f5 8040
567d2de2 8041 return features;
082757af
DS		 8042}
8043
c8f44aff 8044static int ixgbe_set_features(struct net_device *netdev,
567d2de2 8045 netdev_features_t features)
082757af
DS		 8046{
8047 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 8048 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 8049 bool need_reset = false;
8050
082757af 8051 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 8052 if (!(features & NETIF_F_LRO)) {
8053 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8054 need_reset = true;
567d2de2
AD		 8055 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8056 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8057 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8058 if (adapter->rx_itr_setting == 1 ||
8059 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8060 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8061 need_reset = true;
8062 } else if ((changed ^ features) & NETIF_F_LRO) {
8063 e_info(probe, "rx-usecs set too low, "
8064 "disabling RSC\n");
082757af
DS		 8065 }
8066 }
8067
8068 /*
8069 * Check if Flow Director n-tuple support was enabled or disabled. If
8070 * the state changed, we need to reset.
8071 */
39cb681b
AD		 8072 switch (features & NETIF_F_NTUPLE) {
8073 case NETIF_F_NTUPLE:
567d2de2 8074 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8075 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8076 need_reset = true;
8077
567d2de2
AD		 8078 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8079 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 8080 break;
8081 default:
8082 /* turn off perfect filters, enable ATR and reset */
8083 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8084 need_reset = true;
8085
8086 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8087
8088 /* We cannot enable ATR if SR-IOV is enabled */
8089 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8090 break;
8091
8092 /* We cannot enable ATR if we have 2 or more traffic classes */
8093 if (netdev_get_num_tc(netdev) > 1)
8094 break;
8095
8096 /* We cannot enable ATR if RSS is disabled */
8097 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8098 break;
8099
8100 /* A sample rate of 0 indicates ATR disabled */
8101 if (!adapter->atr_sample_rate)
8102 break;
8103
8104 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8105 break;
082757af
DS		 8106 }
8107
f646968f 8108 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 8109 ixgbe_vlan_strip_enable(adapter);
8110 else
8111 ixgbe_vlan_strip_disable(adapter);
8112
3f2d1c0f
BG		 8113 if (changed & NETIF_F_RXALL)
8114 need_reset = true;
8115
567d2de2 8116 netdev->features = features;
67359c3c
MR		 8117
8118#ifdef CONFIG_IXGBE_VXLAN
8119 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8120 if (features & NETIF_F_RXCSUM)
8121 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8122 else
8123 ixgbe_clear_vxlan_port(adapter);
8124 }
8125#endif /* CONFIG_IXGBE_VXLAN */
8126
082757af
DS		 8127 if (need_reset)
8128 ixgbe_do_reset(netdev);
8129
8130 return 0;
082757af
DS		 8131}
8132
67359c3c 8133#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8134/**
8135 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8136 * @dev: The port's netdev
8137 * @sa_family: Socket Family that VXLAN is notifiying us about
8138 * @port: New UDP port number that VXLAN started listening to
8139 **/
8140static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8141 __be16 port)
8142{
8143 struct ixgbe_adapter *adapter = netdev_priv(dev);
8144 struct ixgbe_hw *hw = &adapter->hw;
8145 u16 new_port = ntohs(port);
8146
67359c3c
MR		 8147 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8148 return;
8149
3f207800
DS		 8150 if (sa_family == AF_INET6)
8151 return;
8152
67359c3c 8153 if (adapter->vxlan_port == new_port)
3f207800 8154 return;
3f207800
DS		 8155
8156 if (adapter->vxlan_port) {
8157 netdev_info(dev,
67359c3c 8158 "Hit Max num of VXLAN ports, not adding port %d\n",
3f207800
DS		 8159 new_port);
8160 return;
8161 }
8162
8163 adapter->vxlan_port = new_port;
8164 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8165}
8166
8167/**
8168 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8169 * @dev: The port's netdev
8170 * @sa_family: Socket Family that VXLAN is notifying us about
8171 * @port: UDP port number that VXLAN stopped listening to
8172 **/
8173static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8174 __be16 port)
8175{
8176 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800
DS		 8177 u16 new_port = ntohs(port);
8178
67359c3c
MR		 8179 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8180 return;
8181
3f207800
DS		 8182 if (sa_family == AF_INET6)
8183 return;
8184
8185 if (adapter->vxlan_port != new_port) {
8186 netdev_info(dev, "Port %d was not found, not deleting\n",
8187 new_port);
8188 return;
8189 }
8190
67359c3c
MR		 8191 ixgbe_clear_vxlan_port(adapter);
8192 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8193}
67359c3c 8194#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8195
edc7d573 8196static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8197 struct net_device *dev,
f6f6424b 8198 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8199 u16 flags)
8200{
bcfd3432 8201 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8202 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 8203 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
8204 return -ENOMEM;
0f4b0add
JF		 8205 }
8206
f6f6424b 8207 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8208}
8209
219efe97
DS		 8210/**
8211 * ixgbe_configure_bridge_mode - set various bridge modes
8212 * @adapter - the private structure
8213 * @mode - requested bridge mode
8214 *
8215 * Configure some settings require for various bridge modes.
8216 **/
8217static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8218 __u16 mode)
8219{
6d4c96ad
DS		 8220 struct ixgbe_hw *hw = &adapter->hw;
8221 unsigned int p, num_pools;
8222 u32 vmdctl;
8223
219efe97
DS		 8224 switch (mode) {
8225 case BRIDGE_MODE_VEPA:
6d4c96ad 8226 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8227 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8228
8229 /* must enable Rx switching replication to allow multicast
8230 * packet reception on all VFs, and to enable source address
8231 * pruning.
8232 */
8233 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8234 vmdctl |= IXGBE_VT_CTL_REPLEN;
8235 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8236
8237 /* enable Rx source address pruning. Note, this requires
8238 * replication to be enabled or else it does nothing.
8239 */
8240 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8241 for (p = 0; p < num_pools; p++) {
8242 if (hw->mac.ops.set_source_address_pruning)
8243 hw->mac.ops.set_source_address_pruning(hw,
8244 true,
8245 p);
8246 }
219efe97
DS		 8247 break;
8248 case BRIDGE_MODE_VEB:
6d4c96ad 8249 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8250 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8251 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8252
8253 /* disable Rx switching replication unless we have SR-IOV
8254 * virtual functions
8255 */
8256 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8257 if (!adapter->num_vfs)
8258 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8259 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8260
8261 /* disable Rx source address pruning, since we don't expect to
8262 * be receiving external loopback of our transmitted frames.
8263 */
8264 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8265 for (p = 0; p < num_pools; p++) {
8266 if (hw->mac.ops.set_source_address_pruning)
8267 hw->mac.ops.set_source_address_pruning(hw,
8268 false,
8269 p);
8270 }
219efe97
DS		 8271 break;
8272 default:
8273 return -EINVAL;
8274 }
8275
8276 adapter->bridge_mode = mode;
8277
8278 e_info(drv, "enabling bridge mode: %s\n",
8279 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8280
8281 return 0;
8282}
8283
815cccbf 8284static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8285 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8286{
8287 struct ixgbe_adapter *adapter = netdev_priv(dev);
8288 struct nlattr *attr, *br_spec;
8289 int rem;
8290
8291 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8292 return -EOPNOTSUPP;
8293
8294 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8295 if (!br_spec)
8296 return -EINVAL;
815cccbf
JF		 8297
8298 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8299 int status;
815cccbf 8300 __u16 mode;
815cccbf
JF		 8301
8302 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8303 continue;
8304
b7c1a314
TG		 8305 if (nla_len(attr) < sizeof(mode))
8306 return -EINVAL;
8307
815cccbf 8308 mode = nla_get_u16(attr);
219efe97
DS		 8309 status = ixgbe_configure_bridge_mode(adapter, mode);
8310 if (status)
8311 return status;
aa2bacb6
DS		 8312
8313 break;
815cccbf
JF		 8314 }
8315
8316 return 0;
8317}
8318
8319static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8320 struct net_device *dev,
46c264da 8321 u32 filter_mask, int nlflags)
815cccbf
JF		 8322{
8323 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8324
8325 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8326 return 0;
8327
aa2bacb6 8328 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8329 adapter->bridge_mode, 0, 0, nlflags,
8330 filter_mask, NULL);
815cccbf
JF		 8331}
8332
2a47fa45
JF		 8333static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8334{
8335 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8336 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8337 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8338 unsigned int limit;
2a47fa45
JF		 8339 int pool, err;
8340
aac2f1bf
JK		 8341 /* Hardware has a limited number of available pools. Each VF, and the
8342 * PF require a pool. Check to ensure we don't attempt to use more
8343 * then the available number of pools.
8344 */
8345 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8346 return ERR_PTR(-EINVAL);
8347
219354d4
JF		 8348#ifdef CONFIG_RPS
8349 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8350 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8351 vdev->name);
8352 return ERR_PTR(-EINVAL);
8353 }
8354#endif
2a47fa45 8355 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8356 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8357 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8358 netdev_info(pdev,
8359 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8360 pdev->name);
8361 return ERR_PTR(-EINVAL);
8362 }
8363
8364 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8365 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8366 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8367 return ERR_PTR(-EBUSY);
8368
bc52f951 8369 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8370 if (!fwd_adapter)
8371 return ERR_PTR(-ENOMEM);
8372
8373 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8374 adapter->num_rx_pools++;
8375 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8376 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8377
8378 /* Enable VMDq flag so device will be set in VM mode */
8379 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8380 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8381 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8382
8383 /* Force reinit of ring allocation with VMDQ enabled */
8384 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8385 if (err)
8386 goto fwd_add_err;
8387 fwd_adapter->pool = pool;
8388 fwd_adapter->real_adapter = adapter;
8389 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8390 if (err)
8391 goto fwd_add_err;
8392 netif_tx_start_all_queues(vdev);
8393 return fwd_adapter;
8394fwd_add_err:
8395 /* unwind counter and free adapter struct */
8396 netdev_info(pdev,
8397 "%s: dfwd hardware acceleration failed\n", vdev->name);
8398 clear_bit(pool, &adapter->fwd_bitmask);
8399 adapter->num_rx_pools--;
8400 kfree(fwd_adapter);
8401 return ERR_PTR(err);
8402}
8403
8404static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8405{
8406 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8407 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8408 unsigned int limit;
2a47fa45
JF		 8409
8410 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8411 adapter->num_rx_pools--;
8412
51f3773b
JF		 8413 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8414 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8415 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8416 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8417 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8418 fwd_adapter->pool, adapter->num_rx_pools,
8419 fwd_adapter->rx_base_queue,
8420 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8421 adapter->fwd_bitmask);
8422 kfree(fwd_adapter);
8423}
8424
f467bc06
MR		 8425#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8426static netdev_features_t
8427ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8428 netdev_features_t features)
8429{
8430 if (!skb->encapsulation)
8431 return features;
8432
8433 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8434 IXGBE_MAX_TUNNEL_HDR_LEN))
8435 return features & ~NETIF_F_ALL_CSUM;
8436
8437 return features;
8438}
8439
0edc3527 8440static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8441 .ndo_open = ixgbe_open,
0edc3527 8442 .ndo_stop = ixgbe_close,
00829823 8443 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8444 .ndo_select_queue = ixgbe_select_queue,
581330ba 8445 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8446 .ndo_validate_addr = eth_validate_addr,
8447 .ndo_set_mac_address = ixgbe_set_mac,
8448 .ndo_change_mtu = ixgbe_change_mtu,
8449 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8450 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8451 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8452 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8453 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8454 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8455 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8456 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8457 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 8458 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 8459 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8460 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8461#ifdef CONFIG_IXGBE_DCB
24095aa3 8462 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8463#endif
0edc3527
SH		 8464#ifdef CONFIG_NET_POLL_CONTROLLER
8465 .ndo_poll_controller = ixgbe_netpoll,
8466#endif
e0d1095a 8467#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8468 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8469#endif
332d4a7d
YZ		 8470#ifdef IXGBE_FCOE
8471 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8472 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8473 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8474 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8475 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8476 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8477 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8478#endif /* IXGBE_FCOE */
082757af
DS		 8479 .ndo_set_features = ixgbe_set_features,
8480 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8481 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8482 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8483 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8484 .ndo_dfwd_add_station = ixgbe_fwd_add,
8485 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8486#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8487 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8488 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8489#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8490 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8491};
8492
e027d1ae
JK		 8493/**
8494 * ixgbe_enumerate_functions - Get the number of ports this device has
8495 * @adapter: adapter structure
8496 *
8497 * This function enumerates the phsyical functions co-located on a single slot,
8498 * in order to determine how many ports a device has. This is most useful in
8499 * determining the required GT/s of PCIe bandwidth necessary for optimal
8500 * performance.
8501 **/
8502static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8503{
caafb95d 8504 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8505 int physfns = 0;
8506
f1f96579
JK		 8507 /* Some cards can not use the generic count PCIe functions method,
8508 * because they are behind a parent switch, so we hardcode these with
8509 * the correct number of functions.
e027d1ae 8510 */
8818970d 8511 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8512 physfns = 4;
8818970d
JK		 8513
8514 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8515 /* don't count virtual functions */
caafb95d
JK		 8516 if (entry->is_virtfn)
8517 continue;
8518
8519 /* When the devices on the bus don't all match our device ID,
8520 * we can't reliably determine the correct number of
8521 * functions. This can occur if a function has been direct
8522 * attached to a virtual machine using VT-d, for example. In
8523 * this case, simply return -1 to indicate this.
8524 */
8525 if ((entry->vendor != pdev->vendor) ||
8526 (entry->device != pdev->device))
8527 return -1;
8528
8529 physfns++;
e027d1ae
JK		 8530 }
8531
8532 return physfns;
8533}
8534
8e2813f5
JK		 8535/**
8536 * ixgbe_wol_supported - Check whether device supports WoL
8537 * @hw: hw specific details
8538 * @device_id: the device ID
8539 * @subdev_id: the subsystem device ID
8540 *
8541 * This function is used by probe and ethtool to determine
8542 * which devices have WoL support
8543 *
8544 **/
8545int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8546 u16 subdevice_id)
8547{
8548 struct ixgbe_hw *hw = &adapter->hw;
8549 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8550 int is_wol_supported = 0;
8551
8552 switch (device_id) {
8553 case IXGBE_DEV_ID_82599_SFP:
8554 /* Only these subdevices could supports WOL */
8555 switch (subdevice_id) {
87557440 8556 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8557 case IXGBE_SUBDEV_ID_82599_560FLR:
8558 /* only support first port */
8559 if (hw->bus.func != 0)
8560 break;
5700ff26 8561 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8562 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8563 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8564 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8565 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8566 is_wol_supported = 1;
8567 break;
8568 }
8569 break;
5daebbb0
DS		 8570 case IXGBE_DEV_ID_82599EN_SFP:
8571 /* Only this subdevice supports WOL */
8572 switch (subdevice_id) {
8573 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8574 is_wol_supported = 1;
8575 break;
8576 }
8577 break;
8e2813f5
JK		 8578 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8579 /* All except this subdevice support WOL */
8580 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8581 is_wol_supported = 1;
8582 break;
8583 case IXGBE_DEV_ID_82599_KX4:
8584 is_wol_supported = 1;
8585 break;
8586 case IXGBE_DEV_ID_X540T:
df376f0d 8587 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8588 case IXGBE_DEV_ID_X550T:
8589 case IXGBE_DEV_ID_X550EM_X_KX4:
8590 case IXGBE_DEV_ID_X550EM_X_KR:
8591 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8592 /* check eeprom to see if enabled wol */
8593 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8594 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8595 (hw->bus.func == 0))) {
8596 is_wol_supported = 1;
8597 }
8598 break;
8599 }
8600
8601 return is_wol_supported;
8602}
8603
c762dff2
MP		 8604/**
8605 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8606 * @adapter: Pointer to adapter struct
8607 */
8608static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8609{
8610#ifdef CONFIG_OF
8611 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8612 struct ixgbe_hw *hw = &adapter->hw;
8613 const unsigned char *addr;
8614
8615 addr = of_get_mac_address(dp);
8616 if (addr) {
8617 ether_addr_copy(hw->mac.perm_addr, addr);
8618 return;
8619 }
8620#endif /* CONFIG_OF */
8621
8622#ifdef CONFIG_SPARC
8623 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8624#endif /* CONFIG_SPARC */
8625}
8626
9a799d71
AK		 8627/**
8628 * ixgbe_probe - Device Initialization Routine
8629 * @pdev: PCI device information struct
8630 * @ent: entry in ixgbe_pci_tbl
8631 *
8632 * Returns 0 on success, negative on failure
8633 *
8634 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8635 * The OS initialization, configuring of the adapter private structure,
8636 * and a hardware reset occur.
8637 **/
1dd06ae8 8638static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8639{
8640 struct net_device *netdev;
8641 struct ixgbe_adapter *adapter = NULL;
8642 struct ixgbe_hw *hw;
8643 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8644 int i, err, pci_using_dac, expected_gts;
d3cb9869 8645 unsigned int indices = MAX_TX_QUEUES;
289700db 8646 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8647 bool disable_dev = false;
eacd73f7
YZ		 8648#ifdef IXGBE_FCOE
8649 u16 device_caps;
8650#endif
289700db 8651 u32 eec;
9a799d71 8652
bded64a7
AG		 8653 /* Catch broken hardware that put the wrong VF device ID in
8654 * the PCIe SR-IOV capability.
8655 */
8656 if (pdev->is_virtfn) {
8657 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8658 pci_name(pdev), pdev->vendor, pdev->device);
8659 return -EINVAL;
8660 }
8661
9ce77666 8662 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8663 if (err)
8664 return err;
8665
f5f2eda8 8666 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8667 pci_using_dac = 1;
8668 } else {
f5f2eda8 8669 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8670 if (err) {
f5f2eda8
RK		 8671 dev_err(&pdev->dev,
8672 "No usable DMA configuration, aborting\n");
8673 goto err_dma;
9a799d71
AK		 8674 }
8675 pci_using_dac = 0;
8676 }
8677
9ce77666 8678 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8679 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8680 if (err) {
b8bc0421
DC		 8681 dev_err(&pdev->dev,
8682 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8683 goto err_pci_reg;
8684 }
8685
19d5afd4 8686 pci_enable_pcie_error_reporting(pdev);
6fabd715 8687
9a799d71 8688 pci_set_master(pdev);
fb3b27bc 8689 pci_save_state(pdev);
9a799d71 8690
d3cb9869 8691 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8692#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8693 /* 8 TC w/ 4 queues per TC */
8694 indices = 4 * MAX_TRAFFIC_CLASS;
8695#else
8696 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8697#endif
d3cb9869 8698 }
e901acd6 8699
c85a2618 8700 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8701 if (!netdev) {
8702 err = -ENOMEM;
8703 goto err_alloc_etherdev;
8704 }
8705
9a799d71
AK		 8706 SET_NETDEV_DEV(netdev, &pdev->dev);
8707
9a799d71
AK		 8708 adapter = netdev_priv(netdev);
8709
8710 adapter->netdev = netdev;
8711 adapter->pdev = pdev;
8712 hw = &adapter->hw;
8713 hw->back = adapter;
b3f4d599 8714 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8715
05857980 8716 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8717 pci_resource_len(pdev, 0));
2a1a091c 8718 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8719 if (!hw->hw_addr) {
8720 err = -EIO;
8721 goto err_ioremap;
8722 }
8723
0edc3527 8724 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8725 ixgbe_set_ethtool_ops(netdev);
9a799d71 8726 netdev->watchdog_timeo = 5 * HZ;
339de30f 8727 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8728
9a799d71
AK		 8729 /* Setup hw api */
8730 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8731 hw->mac.type = ii->mac;
9a900eca 8732 hw->mvals = ii->mvals;
9a799d71 8733
c44ade9e
JB		 8734 /* EEPROM */
8735 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 8736 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 8737 if (ixgbe_removed(hw->hw_addr)) {
8738 err = -EIO;
8739 goto err_ioremap;
8740 }
c44ade9e
JB		 8741 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8742 if (!(eec & (1 << 8)))
8743 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8744
8745 /* PHY */
8746 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8747 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8748 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8749 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8750 hw->phy.mdio.mmds = 0;
8751 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8752 hw->phy.mdio.dev = netdev;
8753 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8754 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8755
8ca783ab 8756 ii->get_invariants(hw);
9a799d71
AK		 8757
8758 /* setup the private structure */
8759 err = ixgbe_sw_init(adapter);
8760 if (err)
8761 goto err_sw_init;
8762
e86bff0e 8763 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8764 switch (adapter->hw.mac.type) {
8765 case ixgbe_mac_82599EB:
8766 case ixgbe_mac_X540:
9a75a1ac
DS		 8767 case ixgbe_mac_X550:
8768 case ixgbe_mac_X550EM_x:
e86bff0e 8769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8770 break;
8771 default:
8772 break;
8773 }
e86bff0e 8774
bf069c97
DS		 8775 /*
8776 * If there is a fan on this device and it has failed log the
8777 * failure.
8778 */
8779 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8780 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8781 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8782 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8783 }
8784
8ef78adc
PWJ		 8785 if (allow_unsupported_sfp)
8786 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8787
c44ade9e 8788 /* reset_hw fills in the perm_addr as well */
119fc60a 8789 hw->phy.reset_if_overtemp = true;
c44ade9e 8790 err = hw->mac.ops.reset_hw(hw);
119fc60a 8791 hw->phy.reset_if_overtemp = false;
29a8dca1 8792 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 8793 err = 0;
8794 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8795 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8796 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8797 goto err_sw_init;
8798 } else if (err) {
849c4542 8799 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8800 goto err_sw_init;
8801 }
8802
99d74487 8803#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8804 /* SR-IOV not supported on the 82598 */
8805 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8806 goto skip_sriov;
8807 /* Mailbox */
8808 ixgbe_init_mbx_params_pf(hw);
8809 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8810 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8811 ixgbe_enable_sriov(adapter);
60a1a680 8812skip_sriov:
1cdd1ec8 8813
99d74487 8814#endif
396e799c 8815 netdev->features = NETIF_F_SG |
e8e9f696 8816 NETIF_F_IP_CSUM |
082757af 8817 NETIF_F_IPV6_CSUM |
f646968f
PM		 8818 NETIF_F_HW_VLAN_CTAG_TX |
8819 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 8820 NETIF_F_TSO |
8821 NETIF_F_TSO6 |
082757af 8822 NETIF_F_RXHASH |
8bf1264d 8823 NETIF_F_RXCSUM;
9a799d71 8824
8bf1264d 8825 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8826
58be7666
DS		 8827 switch (adapter->hw.mac.type) {
8828 case ixgbe_mac_82599EB:
8829 case ixgbe_mac_X540:
9a75a1ac
DS		 8830 case ixgbe_mac_X550:
8831 case ixgbe_mac_X550EM_x:
45a5ead0 8832 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8833 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8834 NETIF_F_NTUPLE;
58be7666
DS		 8835 break;
8836 default:
8837 break;
8838 }
45a5ead0 8839
3f2d1c0f 8840 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 8841 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 8842
ad31c402
JK		 8843 netdev->vlan_features |= NETIF_F_TSO;
8844 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8845 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8846 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8847 netdev->vlan_features |= NETIF_F_SG;
8848
f467bc06
MR		 8849 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8850 NETIF_F_IPV6_CSUM;
8851
01789349 8852 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8853 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8854
67359c3c 8855#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8856 switch (adapter->hw.mac.type) {
8857 case ixgbe_mac_X550:
8858 case ixgbe_mac_X550EM_x:
67359c3c
MR		 8859 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8860 NETIF_F_IP_CSUM |
8861 NETIF_F_IPV6_CSUM;
3f207800
DS		 8862 break;
8863 default:
8864 break;
8865 }
67359c3c 8866#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8867
7a6b6f51 8868#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8869 netdev->dcbnl_ops = &dcbnl_ops;
8870#endif
8871
eacd73f7 8872#ifdef IXGBE_FCOE
0d551589 8873 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8874 unsigned int fcoe_l;
8875
eacd73f7
YZ		 8876 if (hw->mac.ops.get_device_caps) {
8877 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8878 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8879 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8880 }
7c8ae65a 8881
d3cb9869
AD		 8882
8883 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8884 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8885
a58915c7
AD		 8886 netdev->features |= NETIF_F_FSO |
8887 NETIF_F_FCOE_CRC;
8888
7c8ae65a
AD		 8889 netdev->vlan_features |= NETIF_F_FSO |
8890 NETIF_F_FCOE_CRC |
8891 NETIF_F_FCOE_MTU;
5e09d7f6 8892 }
eacd73f7 8893#endif /* IXGBE_FCOE */
7b872a55 8894 if (pci_using_dac) {
9a799d71 8895 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8896 netdev->vlan_features |= NETIF_F_HIGHDMA;
8897 }
9a799d71 8898
082757af
DS		 8899 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8900 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8901 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8902 netdev->features |= NETIF_F_LRO;
8903
9a799d71 8904 /* make sure the EEPROM is good */
c44ade9e 8905 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8906 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8907 err = -EIO;
35937c05 8908 goto err_sw_init;
9a799d71
AK		 8909 }
8910
c762dff2
MP		 8911 ixgbe_get_platform_mac_addr(adapter);
8912
9a799d71 8913 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8914
aaeb6cdf 8915 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8916 e_dev_err("invalid MAC address\n");
9a799d71 8917 err = -EIO;
35937c05 8918 goto err_sw_init;
9a799d71
AK		 8919 }
8920
c9f53e63 8921 ixgbe_mac_set_default_filter(adapter);
5d7daa35 8922
7086400d 8923 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8924 (unsigned long) adapter);
9a799d71 8925
58cf663f
MR		 8926 if (ixgbe_removed(hw->hw_addr)) {
8927 err = -EIO;
8928 goto err_sw_init;
8929 }
7086400d 8930 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8931 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8932 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8933
021230d4
AV		 8934 err = ixgbe_init_interrupt_scheme(adapter);
8935 if (err)
8936 goto err_sw_init;
9a799d71 8937
8e2813f5 8938 /* WOL not supported for all devices */
c23f5b6b 8939 adapter->wol = 0;
8e2813f5 8940 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8941 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8942 pdev->subsystem_device);
6b92b0ba 8943 if (hw->wol_enabled)
9417c464 8944 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8945
e8e26350
PW		 8946 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8947
15e5209f
ET		 8948 /* save off EEPROM version number */
8949 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8950 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8951
04f165ef 8952 /* pick up the PCI bus settings for reporting later */
e027d1ae 8953 if (ixgbe_pcie_from_parent(hw))
b8e82001 8954 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 8955 else
8956 hw->mac.ops.get_bus_info(hw);
04f165ef 8957
e027d1ae
JK		 8958 /* calculate the expected PCIe bandwidth required for optimal
8959 * performance. Note that some older parts will never have enough
8960 * bandwidth due to being older generation PCIe parts. We clamp these
8961 * parts to ensure no warning is displayed if it can't be fixed.
8962 */
8963 switch (hw->mac.type) {
8964 case ixgbe_mac_82598EB:
8965 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8966 break;
8967 default:
8968 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8969 break;
0c254d86 8970 }
caafb95d
JK		 8971
8972 /* don't check link if we failed to enumerate functions */
8973 if (expected_gts > 0)
8974 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8975
339de30f 8976 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8977 if (err)
339de30f 8978 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8979 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8980 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8981 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8982 part_str);
6a2aae5a
JK		 8983 else
8984 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8985 hw->mac.type, hw->phy.type, part_str);
8986
8987 e_dev_info("%pM\n", netdev->dev_addr);
8988
9a799d71 8989 /* reset the hardware with the new settings */
794caeb2 8990 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8991 if (err == IXGBE_ERR_EEPROM_VERSION) {
8992 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8993 e_dev_warn("This device is a pre-production adapter/LOM. "
8994 "Please be aware there may be issues associated "
8995 "with your hardware. If you are experiencing "
8996 "problems please contact your Intel or hardware "
8997 "representative who provided you with this "
8998 "hardware.\n");
794caeb2 8999 }
9a799d71
AK		 9000 strcpy(netdev->name, "eth%d");
9001 err = register_netdev(netdev);
9002 if (err)
9003 goto err_register;
9004
0fb6a55c
ET		 9005 pci_set_drvdata(pdev, adapter);
9006
ec74a471
ET		 9007 /* power down the optics for 82599 SFP+ fiber */
9008 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 9009 hw->mac.ops.disable_tx_laser(hw);
9010
54386467
JB		 9011 /* carrier off reporting is important to ethtool even BEFORE open */
9012 netif_carrier_off(netdev);
9013
5dd2d332 9014#ifdef CONFIG_IXGBE_DCA
652f093f 9015 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 9016 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 9017 ixgbe_setup_dca(adapter);
9018 }
9019#endif
1cdd1ec8 9020 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 9021 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 9022 for (i = 0; i < adapter->num_vfs; i++)
9023 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9024 }
9025
2466dd9c
JK		 9026 /* firmware requires driver version to be 0xFFFFFFFF
9027 * since os does not support feature
9028 */
9612de92 9029 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 9030 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9031 0xFF);
9612de92 9032
0365e6e4
PW		 9033 /* add san mac addr to netdev */
9034 ixgbe_add_sanmac_netdev(netdev);
9a799d71 9035
ea81875a 9036 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 9037
1210982b 9038#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 9039 if (ixgbe_sysfs_init(adapter))
9040 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 9041#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9042
00949167 9043 ixgbe_dbg_adapter_init(adapter);
00949167 9044
d1a35ee2
ET		 9045 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9046 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 9047 hw->mac.ops.setup_link(hw,
9048 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9049 true);
9050
9a799d71
AK		 9051 return 0;
9052
9053err_register:
5eba3699 9054 ixgbe_release_hw_control(adapter);
7a921c93 9055 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 9056err_sw_init:
99d74487 9057 ixgbe_disable_sriov(adapter);
7086400d 9058 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 9059 iounmap(adapter->io_addr);
5d7daa35 9060 kfree(adapter->mac_table);
9a799d71 9061err_ioremap:
b5b2ffc0 9062 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9063 free_netdev(netdev);
9064err_alloc_etherdev:
e8e9f696
JP		 9065 pci_release_selected_regions(pdev,
9066 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 9067err_pci_reg:
9068err_dma:
b5b2ffc0 9069 if (!adapter || disable_dev)
41c62843 9070 pci_disable_device(pdev);
9a799d71
AK		 9071 return err;
9072}
9073
9074/**
9075 * ixgbe_remove - Device Removal Routine
9076 * @pdev: PCI device information struct
9077 *
9078 * ixgbe_remove is called by the PCI subsystem to alert the driver
9079 * that it should release a PCI device. The could be caused by a
9080 * Hot-Plug event, or because the driver is going to be removed from
9081 * memory.
9082 **/
9f9a12f8 9083static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9084{
c60fbb00 9085 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9086 struct net_device *netdev;
b5b2ffc0 9087 bool disable_dev;
9a799d71 9088
0fb6a55c
ET		 9089 /* if !adapter then we already cleaned up in probe */
9090 if (!adapter)
9091 return;
9092
9093 netdev = adapter->netdev;
00949167 9094 ixgbe_dbg_adapter_exit(adapter);
00949167 9095
09f40aed 9096 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9097 cancel_work_sync(&adapter->service_task);
9a799d71 9098
3a6a4eda 9099
5dd2d332 9100#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9101 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9102 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9103 dca_remove_requester(&pdev->dev);
9de7605e
MR		 9104 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9105 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 9106 }
9107
9108#endif
1210982b 9109#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9110 ixgbe_sysfs_exit(adapter);
1210982b 9111#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9112
0365e6e4
PW		 9113 /* remove the added san mac */
9114 ixgbe_del_sanmac_netdev(netdev);
9115
da36b647 9116#ifdef CONFIG_PCI_IOV
7837e286 9117 ixgbe_disable_sriov(adapter);
da36b647 9118#endif
6b010e9b
AW		 9119 if (netdev->reg_state == NETREG_REGISTERED)
9120 unregister_netdev(netdev);
9121
7a921c93 9122 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9123
021230d4 9124 ixgbe_release_hw_control(adapter);
9a799d71 9125
2b1588c3
AD		 9126#ifdef CONFIG_DCB
9127 kfree(adapter->ixgbe_ieee_pfc);
9128 kfree(adapter->ixgbe_ieee_ets);
9129
9130#endif
2a1a091c 9131 iounmap(adapter->io_addr);
9ce77666 9132 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9133 IORESOURCE_MEM));
9a799d71 9134
849c4542 9135 e_dev_info("complete\n");
021230d4 9136
5d7daa35 9137 kfree(adapter->mac_table);
b5b2ffc0 9138 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9139 free_netdev(netdev);
9140
19d5afd4 9141 pci_disable_pcie_error_reporting(pdev);
6fabd715 9142
b5b2ffc0 9143 if (disable_dev)
41c62843 9144 pci_disable_device(pdev);
9a799d71
AK		 9145}
9146
9147/**
9148 * ixgbe_io_error_detected - called when PCI error is detected
9149 * @pdev: Pointer to PCI device
9150 * @state: The current pci connection state
9151 *
9152 * This function is called after a PCI bus error affecting
9153 * this device has been detected.
9154 */
9155static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9156 pci_channel_state_t state)
9a799d71 9157{
c60fbb00
AD		 9158 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9159 struct net_device *netdev = adapter->netdev;
9a799d71 9160
83c61fa9 9161#ifdef CONFIG_PCI_IOV
14438464 9162 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9163 struct pci_dev *bdev, *vfdev;
9164 u32 dw0, dw1, dw2, dw3;
9165 int vf, pos;
9166 u16 req_id, pf_func;
9167
9168 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9169 adapter->num_vfs == 0)
9170 goto skip_bad_vf_detection;
9171
9172 bdev = pdev->bus->self;
62f87c0e 9173 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9174 bdev = bdev->bus->self;
9175
9176 if (!bdev)
9177 goto skip_bad_vf_detection;
9178
9179 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9180 if (!pos)
9181 goto skip_bad_vf_detection;
9182
14438464
MR		 9183 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9184 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9185 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9186 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9187 if (ixgbe_removed(hw->hw_addr))
9188 goto skip_bad_vf_detection;
83c61fa9
GR		 9189
9190 req_id = dw1 >> 16;
9191 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9192 if (!(req_id & 0x0080))
9193 goto skip_bad_vf_detection;
9194
9195 pf_func = req_id & 0x01;
9196 if ((pf_func & 1) == (pdev->devfn & 1)) {
9197 unsigned int device_id;
9198
9199 vf = (req_id & 0x7F) >> 1;
9200 e_dev_err("VF %d has caused a PCIe error\n", vf);
9201 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9202 "%8.8x\tdw3: %8.8x\n",
9203 dw0, dw1, dw2, dw3);
9204 switch (adapter->hw.mac.type) {
9205 case ixgbe_mac_82599EB:
9206 device_id = IXGBE_82599_VF_DEVICE_ID;
9207 break;
9208 case ixgbe_mac_X540:
9209 device_id = IXGBE_X540_VF_DEVICE_ID;
9210 break;
9a75a1ac
DS		 9211 case ixgbe_mac_X550:
9212 device_id = IXGBE_DEV_ID_X550_VF;
9213 break;
9214 case ixgbe_mac_X550EM_x:
9215 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9216 break;
83c61fa9
GR		 9217 default:
9218 device_id = 0;
9219 break;
9220 }
9221
9222 /* Find the pci device of the offending VF */
36e90319 9223 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9224 while (vfdev) {
9225 if (vfdev->devfn == (req_id & 0xFF))
9226 break;
36e90319 9227 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9228 device_id, vfdev);
9229 }
9230 /*
9231 * There's a slim chance the VF could have been hot plugged,
9232 * so if it is no longer present we don't need to issue the
9233 * VFLR. Just clean up the AER in that case.
9234 */
9235 if (vfdev) {
9079e416 9236 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9237 /* Free device reference count */
9238 pci_dev_put(vfdev);
83c61fa9
GR		 9239 }
9240
9241 pci_cleanup_aer_uncorrect_error_status(pdev);
9242 }
9243
9244 /*
9245 * Even though the error may have occurred on the other port
9246 * we still need to increment the vf error reference count for
9247 * both ports because the I/O resume function will be called
9248 * for both of them.
9249 */
9250 adapter->vferr_refcount++;
9251
9252 return PCI_ERS_RESULT_RECOVERED;
9253
9254skip_bad_vf_detection:
9255#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9256 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9257 return PCI_ERS_RESULT_DISCONNECT;
9258
41c62843 9259 rtnl_lock();
9a799d71
AK		 9260 netif_device_detach(netdev);
9261
41c62843
MR		 9262 if (state == pci_channel_io_perm_failure) {
9263 rtnl_unlock();
3044b8d1 9264 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9265 }
3044b8d1 9266
9a799d71
AK		 9267 if (netif_running(netdev))
9268 ixgbe_down(adapter);
41c62843
MR		 9269
9270 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9271 pci_disable_device(pdev);
9272 rtnl_unlock();
9a799d71 9273
b4617240 9274 /* Request a slot reset. */
9a799d71
AK		 9275 return PCI_ERS_RESULT_NEED_RESET;
9276}
9277
9278/**
9279 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9280 * @pdev: Pointer to PCI device
9281 *
9282 * Restart the card from scratch, as if from a cold-boot.
9283 */
9284static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9285{
c60fbb00 9286 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9287 pci_ers_result_t result;
9288 int err;
9a799d71 9289
9ce77666 9290 if (pci_enable_device_mem(pdev)) {
396e799c 9291 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9292 result = PCI_ERS_RESULT_DISCONNECT;
9293 } else {
4e857c58 9294 smp_mb__before_atomic();
41c62843 9295 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9296 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9297 pci_set_master(pdev);
9298 pci_restore_state(pdev);
c0e1f68b 9299 pci_save_state(pdev);
9a799d71 9300
dd4d8ca6 9301 pci_wake_from_d3(pdev, false);
9a799d71 9302
6fabd715 9303 ixgbe_reset(adapter);
88512539 9304 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9305 result = PCI_ERS_RESULT_RECOVERED;
9306 }
9307
9308 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9309 if (err) {
849c4542
ET		 9310 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9311 "failed 0x%0x\n", err);
6fabd715
PWJ		 9312 /* non-fatal, continue */
9313 }
9a799d71 9314
6fabd715 9315 return result;
9a799d71
AK		 9316}
9317
9318/**
9319 * ixgbe_io_resume - called when traffic can start flowing again.
9320 * @pdev: Pointer to PCI device
9321 *
9322 * This callback is called when the error recovery driver tells us that
9323 * its OK to resume normal operation.
9324 */
9325static void ixgbe_io_resume(struct pci_dev *pdev)
9326{
c60fbb00
AD		 9327 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9328 struct net_device *netdev = adapter->netdev;
9a799d71 9329
83c61fa9
GR		 9330#ifdef CONFIG_PCI_IOV
9331 if (adapter->vferr_refcount) {
9332 e_info(drv, "Resuming after VF err\n");
9333 adapter->vferr_refcount--;
9334 return;
9335 }
9336
9337#endif
c7ccde0f
AD		 9338 if (netif_running(netdev))
9339 ixgbe_up(adapter);
9a799d71
AK		 9340
9341 netif_device_attach(netdev);
9a799d71
AK		 9342}
9343
3646f0e5 9344static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9345 .error_detected = ixgbe_io_error_detected,
9346 .slot_reset = ixgbe_io_slot_reset,
9347 .resume = ixgbe_io_resume,
9348};
9349
9350static struct pci_driver ixgbe_driver = {
9351 .name = ixgbe_driver_name,
9352 .id_table = ixgbe_pci_tbl,
9353 .probe = ixgbe_probe,
9f9a12f8 9354 .remove = ixgbe_remove,
9a799d71
AK		 9355#ifdef CONFIG_PM
9356 .suspend = ixgbe_suspend,
9357 .resume = ixgbe_resume,
9358#endif
9359 .shutdown = ixgbe_shutdown,
da36b647 9360 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9361 .err_handler = &ixgbe_err_handler
9362};
9363
9364/**
9365 * ixgbe_init_module - Driver Registration Routine
9366 *
9367 * ixgbe_init_module is the first routine called when the driver is
9368 * loaded. All it does is register with the PCI subsystem.
9369 **/
9370static int __init ixgbe_init_module(void)
9371{
9372 int ret;
c7689578 9373 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9374 pr_info("%s\n", ixgbe_copyright);
9a799d71 9375
780484d8
MR		 9376 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9377 if (!ixgbe_wq) {
9378 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9379 return -ENOMEM;
9380 }
9381
00949167 9382 ixgbe_dbg_init();
00949167 9383
f01fc1a8
JK		 9384 ret = pci_register_driver(&ixgbe_driver);
9385 if (ret) {
f01fc1a8 9386 ixgbe_dbg_exit();
f01fc1a8
JK		 9387 return ret;
9388 }
9389
5dd2d332 9390#ifdef CONFIG_IXGBE_DCA
bd0362dd 9391 dca_register_notify(&dca_notifier);
bd0362dd 9392#endif
5dd2d332 9393
f01fc1a8 9394 return 0;
9a799d71 9395}
b4617240 9396
9a799d71
AK		 9397module_init(ixgbe_init_module);
9398
9399/**
9400 * ixgbe_exit_module - Driver Exit Cleanup Routine
9401 *
9402 * ixgbe_exit_module is called just before the driver is removed
9403 * from memory.
9404 **/
9405static void __exit ixgbe_exit_module(void)
9406{
5dd2d332 9407#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9408 dca_unregister_notify(&dca_notifier);
9409#endif
9a799d71 9410 pci_unregister_driver(&ixgbe_driver);
00949167 9411
00949167 9412 ixgbe_dbg_exit();
780484d8
MR		 9413 if (ixgbe_wq) {
9414 destroy_workqueue(ixgbe_wq);
9415 ixgbe_wq = NULL;
9416 }
9a799d71 9417}
bd0362dd 9418
5dd2d332 9419#ifdef CONFIG_IXGBE_DCA
bd0362dd 9420static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9421 void *p)
bd0362dd
JC		 9422{
9423 int ret_val;
9424
9425 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9426 __ixgbe_notify_dca);
bd0362dd
JC		 9427
9428 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9429}
b453368d 9430
5dd2d332 9431#endif /* CONFIG_IXGBE_DCA */
849c4542 9432
9a799d71
AK		 9433module_exit(ixgbe_exit_module);
9434
9435/* ixgbe_main.c */
Linux kernel - Deliverables
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