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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
eacd73f7 | 48 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
49 | |
50 | #include "ixgbe.h" | |
51 | #include "ixgbe_common.h" | |
ee5f784a | 52 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 53 | #include "ixgbe_sriov.h" |
9a799d71 AK |
54 | |
55 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 56 | static const char ixgbe_driver_string[] = |
e8e9f696 | 57 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 58 | #ifdef IXGBE_FCOE |
ea81875a NP |
59 | char ixgbe_default_device_descr[] = |
60 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
61 | #else |
62 | static char ixgbe_default_device_descr[] = | |
63 | "Intel(R) 10 Gigabit Network Connection"; | |
64 | #endif | |
75e3d3c6 | 65 | #define MAJ 3 |
8e4f3250 DS |
66 | #define MIN 8 |
67 | #define BUILD 21 | |
75e3d3c6 | 68 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
a38a104d | 69 | __stringify(BUILD) "-k" |
9c8eb720 | 70 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 71 | static const char ixgbe_copyright[] = |
94971820 | 72 | "Copyright (c) 1999-2012 Intel Corporation."; |
9a799d71 AK |
73 | |
74 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 75 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 76 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 77 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
78 | }; |
79 | ||
80 | /* ixgbe_pci_tbl - PCI Device ID Table | |
81 | * | |
82 | * Wildcard entries (PCI_ANY_ID) should come last | |
83 | * Last entry must be all 0s | |
84 | * | |
85 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
86 | * Class, Class Mask, private data (not used) } | |
87 | */ | |
a3aa1884 | 88 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
7d145282 | 115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
9a799d71 AK |
117 | /* required last entry */ |
118 | {0, } | |
119 | }; | |
120 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
121 | ||
5dd2d332 | 122 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 123 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 124 | void *p); |
bd0362dd JC |
125 | static struct notifier_block dca_notifier = { |
126 | .notifier_call = ixgbe_notify_dca, | |
127 | .next = NULL, | |
128 | .priority = 0 | |
129 | }; | |
130 | #endif | |
131 | ||
1cdd1ec8 GR |
132 | #ifdef CONFIG_PCI_IOV |
133 | static unsigned int max_vfs; | |
134 | module_param(max_vfs, uint, 0); | |
e8e9f696 JP |
135 | MODULE_PARM_DESC(max_vfs, |
136 | "Maximum number of virtual functions to allocate per physical function"); | |
1cdd1ec8 GR |
137 | #endif /* CONFIG_PCI_IOV */ |
138 | ||
8ef78adc PWJ |
139 | static unsigned int allow_unsupported_sfp; |
140 | module_param(allow_unsupported_sfp, uint, 0); | |
141 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
142 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
143 | ||
b3f4d599 | 144 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
145 | static int debug = -1; | |
146 | module_param(debug, int, 0); | |
147 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
148 | ||
9a799d71 AK |
149 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
150 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
151 | MODULE_LICENSE("GPL"); | |
152 | MODULE_VERSION(DRV_VERSION); | |
153 | ||
7086400d AD |
154 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
155 | { | |
156 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
157 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
158 | schedule_work(&adapter->service_task); | |
159 | } | |
160 | ||
161 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
162 | { | |
163 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
164 | ||
52f33af8 | 165 | /* flush memory to make sure state is correct before next watchdog */ |
7086400d AD |
166 | smp_mb__before_clear_bit(); |
167 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
168 | } | |
169 | ||
dcd79aeb TI |
170 | struct ixgbe_reg_info { |
171 | u32 ofs; | |
172 | char *name; | |
173 | }; | |
174 | ||
175 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
176 | ||
177 | /* General Registers */ | |
178 | {IXGBE_CTRL, "CTRL"}, | |
179 | {IXGBE_STATUS, "STATUS"}, | |
180 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
181 | ||
182 | /* Interrupt Registers */ | |
183 | {IXGBE_EICR, "EICR"}, | |
184 | ||
185 | /* RX Registers */ | |
186 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
187 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
188 | {IXGBE_RDLEN(0), "RDLEN"}, | |
189 | {IXGBE_RDH(0), "RDH"}, | |
190 | {IXGBE_RDT(0), "RDT"}, | |
191 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
192 | {IXGBE_RDBAL(0), "RDBAL"}, | |
193 | {IXGBE_RDBAH(0), "RDBAH"}, | |
194 | ||
195 | /* TX Registers */ | |
196 | {IXGBE_TDBAL(0), "TDBAL"}, | |
197 | {IXGBE_TDBAH(0), "TDBAH"}, | |
198 | {IXGBE_TDLEN(0), "TDLEN"}, | |
199 | {IXGBE_TDH(0), "TDH"}, | |
200 | {IXGBE_TDT(0), "TDT"}, | |
201 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
202 | ||
203 | /* List Terminator */ | |
204 | {} | |
205 | }; | |
206 | ||
207 | ||
208 | /* | |
209 | * ixgbe_regdump - register printout routine | |
210 | */ | |
211 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
212 | { | |
213 | int i = 0, j = 0; | |
214 | char rname[16]; | |
215 | u32 regs[64]; | |
216 | ||
217 | switch (reginfo->ofs) { | |
218 | case IXGBE_SRRCTL(0): | |
219 | for (i = 0; i < 64; i++) | |
220 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
221 | break; | |
222 | case IXGBE_DCA_RXCTRL(0): | |
223 | for (i = 0; i < 64; i++) | |
224 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
225 | break; | |
226 | case IXGBE_RDLEN(0): | |
227 | for (i = 0; i < 64; i++) | |
228 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
229 | break; | |
230 | case IXGBE_RDH(0): | |
231 | for (i = 0; i < 64; i++) | |
232 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
233 | break; | |
234 | case IXGBE_RDT(0): | |
235 | for (i = 0; i < 64; i++) | |
236 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
237 | break; | |
238 | case IXGBE_RXDCTL(0): | |
239 | for (i = 0; i < 64; i++) | |
240 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
241 | break; | |
242 | case IXGBE_RDBAL(0): | |
243 | for (i = 0; i < 64; i++) | |
244 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
245 | break; | |
246 | case IXGBE_RDBAH(0): | |
247 | for (i = 0; i < 64; i++) | |
248 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
249 | break; | |
250 | case IXGBE_TDBAL(0): | |
251 | for (i = 0; i < 64; i++) | |
252 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
253 | break; | |
254 | case IXGBE_TDBAH(0): | |
255 | for (i = 0; i < 64; i++) | |
256 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
257 | break; | |
258 | case IXGBE_TDLEN(0): | |
259 | for (i = 0; i < 64; i++) | |
260 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
261 | break; | |
262 | case IXGBE_TDH(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
265 | break; | |
266 | case IXGBE_TDT(0): | |
267 | for (i = 0; i < 64; i++) | |
268 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
269 | break; | |
270 | case IXGBE_TXDCTL(0): | |
271 | for (i = 0; i < 64; i++) | |
272 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
273 | break; | |
274 | default: | |
c7689578 | 275 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
276 | IXGBE_READ_REG(hw, reginfo->ofs)); |
277 | return; | |
278 | } | |
279 | ||
280 | for (i = 0; i < 8; i++) { | |
281 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 282 | pr_err("%-15s", rname); |
dcd79aeb | 283 | for (j = 0; j < 8; j++) |
c7689578 JP |
284 | pr_cont(" %08x", regs[i*8+j]); |
285 | pr_cont("\n"); | |
dcd79aeb TI |
286 | } |
287 | ||
288 | } | |
289 | ||
290 | /* | |
291 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
292 | */ | |
293 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
294 | { | |
295 | struct net_device *netdev = adapter->netdev; | |
296 | struct ixgbe_hw *hw = &adapter->hw; | |
297 | struct ixgbe_reg_info *reginfo; | |
298 | int n = 0; | |
299 | struct ixgbe_ring *tx_ring; | |
729739b7 | 300 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
301 | union ixgbe_adv_tx_desc *tx_desc; |
302 | struct my_u0 { u64 a; u64 b; } *u0; | |
303 | struct ixgbe_ring *rx_ring; | |
304 | union ixgbe_adv_rx_desc *rx_desc; | |
305 | struct ixgbe_rx_buffer *rx_buffer_info; | |
306 | u32 staterr; | |
307 | int i = 0; | |
308 | ||
309 | if (!netif_msg_hw(adapter)) | |
310 | return; | |
311 | ||
312 | /* Print netdevice Info */ | |
313 | if (netdev) { | |
314 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 315 | pr_info("Device Name state " |
dcd79aeb | 316 | "trans_start last_rx\n"); |
c7689578 JP |
317 | pr_info("%-15s %016lX %016lX %016lX\n", |
318 | netdev->name, | |
319 | netdev->state, | |
320 | netdev->trans_start, | |
321 | netdev->last_rx); | |
dcd79aeb TI |
322 | } |
323 | ||
324 | /* Print Registers */ | |
325 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 326 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
327 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
328 | reginfo->name; reginfo++) { | |
329 | ixgbe_regdump(hw, reginfo); | |
330 | } | |
331 | ||
332 | /* Print TX Ring Summary */ | |
333 | if (!netdev || !netif_running(netdev)) | |
334 | goto exit; | |
335 | ||
336 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 337 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
338 | for (n = 0; n < adapter->num_tx_queues; n++) { |
339 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 340 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
d3d00239 | 341 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
dcd79aeb | 342 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
343 | (u64)dma_unmap_addr(tx_buffer, dma), |
344 | dma_unmap_len(tx_buffer, len), | |
345 | tx_buffer->next_to_watch, | |
346 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
347 | } |
348 | ||
349 | /* Print TX Rings */ | |
350 | if (!netif_msg_tx_done(adapter)) | |
351 | goto rx_ring_summary; | |
352 | ||
353 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
354 | ||
355 | /* Transmit Descriptor Formats | |
356 | * | |
357 | * Advanced Transmit Descriptor | |
358 | * +--------------------------------------------------------------+ | |
359 | * 0 | Buffer Address [63:0] | | |
360 | * +--------------------------------------------------------------+ | |
361 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
362 | * +--------------------------------------------------------------+ | |
363 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
364 | */ | |
365 | ||
366 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
367 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
368 | pr_info("------------------------------------\n"); |
369 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
370 | pr_info("------------------------------------\n"); | |
371 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
372 | "[PlPOIdStDDt Ln] [bi->dma ] " |
373 | "leng ntw timestamp bi->skb\n"); | |
374 | ||
375 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 376 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 377 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 378 | u0 = (struct my_u0 *)tx_desc; |
c7689578 | 379 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
d3d00239 | 380 | " %04X %p %016llX %p", i, |
dcd79aeb TI |
381 | le64_to_cpu(u0->a), |
382 | le64_to_cpu(u0->b), | |
729739b7 AD |
383 | (u64)dma_unmap_addr(tx_buffer, dma), |
384 | dma_unmap_len(tx_buffer, len), | |
385 | tx_buffer->next_to_watch, | |
386 | (u64)tx_buffer->time_stamp, | |
387 | tx_buffer->skb); | |
dcd79aeb TI |
388 | if (i == tx_ring->next_to_use && |
389 | i == tx_ring->next_to_clean) | |
c7689578 | 390 | pr_cont(" NTC/U\n"); |
dcd79aeb | 391 | else if (i == tx_ring->next_to_use) |
c7689578 | 392 | pr_cont(" NTU\n"); |
dcd79aeb | 393 | else if (i == tx_ring->next_to_clean) |
c7689578 | 394 | pr_cont(" NTC\n"); |
dcd79aeb | 395 | else |
c7689578 | 396 | pr_cont("\n"); |
dcd79aeb TI |
397 | |
398 | if (netif_msg_pktdata(adapter) && | |
729739b7 | 399 | dma_unmap_len(tx_buffer, len) != 0) |
dcd79aeb TI |
400 | print_hex_dump(KERN_INFO, "", |
401 | DUMP_PREFIX_ADDRESS, 16, 1, | |
729739b7 AD |
402 | phys_to_virt(dma_unmap_addr(tx_buffer, |
403 | dma)), | |
404 | dma_unmap_len(tx_buffer, len), | |
405 | true); | |
dcd79aeb TI |
406 | } |
407 | } | |
408 | ||
409 | /* Print RX Rings Summary */ | |
410 | rx_ring_summary: | |
411 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 412 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
413 | for (n = 0; n < adapter->num_rx_queues; n++) { |
414 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
415 | pr_info("%5d %5X %5X\n", |
416 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
417 | } |
418 | ||
419 | /* Print RX Rings */ | |
420 | if (!netif_msg_rx_status(adapter)) | |
421 | goto exit; | |
422 | ||
423 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
424 | ||
425 | /* Advanced Receive Descriptor (Read) Format | |
426 | * 63 1 0 | |
427 | * +-----------------------------------------------------+ | |
428 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
429 | * +----------------------------------------------+------+ | |
430 | * 8 | Header Buffer Address [63:1] | DD | | |
431 | * +-----------------------------------------------------+ | |
432 | * | |
433 | * | |
434 | * Advanced Receive Descriptor (Write-Back) Format | |
435 | * | |
436 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
437 | * +------------------------------------------------------+ | |
438 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
439 | * | Checksum Ident | | | | Type | Type | | |
440 | * +------------------------------------------------------+ | |
441 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
442 | * +------------------------------------------------------+ | |
443 | * 63 48 47 32 31 20 19 0 | |
444 | */ | |
445 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
446 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
447 | pr_info("------------------------------------\n"); |
448 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
449 | pr_info("------------------------------------\n"); | |
450 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
451 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
452 | "<-- Adv Rx Read format\n"); | |
c7689578 | 453 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
454 | "[vl er S cks ln] ---------------- [bi->skb] " |
455 | "<-- Adv Rx Write-Back format\n"); | |
456 | ||
457 | for (i = 0; i < rx_ring->count; i++) { | |
458 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 459 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
460 | u0 = (struct my_u0 *)rx_desc; |
461 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
462 | if (staterr & IXGBE_RXD_STAT_DD) { | |
463 | /* Descriptor Done */ | |
c7689578 | 464 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
465 | "%016llX ---------------- %p", i, |
466 | le64_to_cpu(u0->a), | |
467 | le64_to_cpu(u0->b), | |
468 | rx_buffer_info->skb); | |
469 | } else { | |
c7689578 | 470 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
471 | "%016llX %016llX %p", i, |
472 | le64_to_cpu(u0->a), | |
473 | le64_to_cpu(u0->b), | |
474 | (u64)rx_buffer_info->dma, | |
475 | rx_buffer_info->skb); | |
476 | ||
477 | if (netif_msg_pktdata(adapter)) { | |
478 | print_hex_dump(KERN_INFO, "", | |
479 | DUMP_PREFIX_ADDRESS, 16, 1, | |
480 | phys_to_virt(rx_buffer_info->dma), | |
f800326d | 481 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
482 | } |
483 | } | |
484 | ||
485 | if (i == rx_ring->next_to_use) | |
c7689578 | 486 | pr_cont(" NTU\n"); |
dcd79aeb | 487 | else if (i == rx_ring->next_to_clean) |
c7689578 | 488 | pr_cont(" NTC\n"); |
dcd79aeb | 489 | else |
c7689578 | 490 | pr_cont("\n"); |
dcd79aeb TI |
491 | |
492 | } | |
493 | } | |
494 | ||
495 | exit: | |
496 | return; | |
497 | } | |
498 | ||
5eba3699 AV |
499 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
500 | { | |
501 | u32 ctrl_ext; | |
502 | ||
503 | /* Let firmware take over control of h/w */ | |
504 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
505 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 506 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
507 | } |
508 | ||
509 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
510 | { | |
511 | u32 ctrl_ext; | |
512 | ||
513 | /* Let firmware know the driver has taken over */ | |
514 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
515 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 516 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 517 | } |
9a799d71 | 518 | |
e8e26350 PW |
519 | /* |
520 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
521 | * @adapter: pointer to adapter struct | |
522 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
523 | * @queue: queue to map the corresponding interrupt to | |
524 | * @msix_vector: the vector to map to the corresponding queue | |
525 | * | |
526 | */ | |
527 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 528 | u8 queue, u8 msix_vector) |
9a799d71 AK |
529 | { |
530 | u32 ivar, index; | |
e8e26350 PW |
531 | struct ixgbe_hw *hw = &adapter->hw; |
532 | switch (hw->mac.type) { | |
533 | case ixgbe_mac_82598EB: | |
534 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
535 | if (direction == -1) | |
536 | direction = 0; | |
537 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
538 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
539 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
540 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
541 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
542 | break; | |
543 | case ixgbe_mac_82599EB: | |
b93a2226 | 544 | case ixgbe_mac_X540: |
e8e26350 PW |
545 | if (direction == -1) { |
546 | /* other causes */ | |
547 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
548 | index = ((queue & 1) * 8); | |
549 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
550 | ivar &= ~(0xFF << index); | |
551 | ivar |= (msix_vector << index); | |
552 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
553 | break; | |
554 | } else { | |
555 | /* tx or rx causes */ | |
556 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
557 | index = ((16 * (queue & 1)) + (8 * direction)); | |
558 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
559 | ivar &= ~(0xFF << index); | |
560 | ivar |= (msix_vector << index); | |
561 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
562 | break; | |
563 | } | |
564 | default: | |
565 | break; | |
566 | } | |
9a799d71 AK |
567 | } |
568 | ||
fe49f04a | 569 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 570 | u64 qmask) |
fe49f04a AD |
571 | { |
572 | u32 mask; | |
573 | ||
bd508178 AD |
574 | switch (adapter->hw.mac.type) { |
575 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
576 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
577 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
578 | break; |
579 | case ixgbe_mac_82599EB: | |
b93a2226 | 580 | case ixgbe_mac_X540: |
fe49f04a AD |
581 | mask = (qmask & 0xFFFFFFFF); |
582 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
583 | mask = (qmask >> 32); | |
584 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
585 | break; |
586 | default: | |
587 | break; | |
fe49f04a AD |
588 | } |
589 | } | |
590 | ||
729739b7 AD |
591 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
592 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 593 | { |
729739b7 AD |
594 | if (tx_buffer->skb) { |
595 | dev_kfree_skb_any(tx_buffer->skb); | |
596 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 597 | dma_unmap_single(ring->dev, |
729739b7 AD |
598 | dma_unmap_addr(tx_buffer, dma), |
599 | dma_unmap_len(tx_buffer, len), | |
600 | DMA_TO_DEVICE); | |
601 | } else if (dma_unmap_len(tx_buffer, len)) { | |
602 | dma_unmap_page(ring->dev, | |
603 | dma_unmap_addr(tx_buffer, dma), | |
604 | dma_unmap_len(tx_buffer, len), | |
605 | DMA_TO_DEVICE); | |
e5a43549 | 606 | } |
729739b7 AD |
607 | tx_buffer->next_to_watch = NULL; |
608 | tx_buffer->skb = NULL; | |
609 | dma_unmap_len_set(tx_buffer, len, 0); | |
610 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
611 | } |
612 | ||
c84d324c JF |
613 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) |
614 | { | |
615 | struct ixgbe_hw *hw = &adapter->hw; | |
616 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
617 | u32 data = 0; | |
618 | u32 xoff[8] = {0}; | |
619 | int i; | |
620 | ||
621 | if ((hw->fc.current_mode == ixgbe_fc_full) || | |
622 | (hw->fc.current_mode == ixgbe_fc_rx_pause)) { | |
623 | switch (hw->mac.type) { | |
624 | case ixgbe_mac_82598EB: | |
625 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
6837e895 PW |
626 | break; |
627 | default: | |
c84d324c JF |
628 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); |
629 | } | |
630 | hwstats->lxoffrxc += data; | |
631 | ||
632 | /* refill credits (no tx hang) if we received xoff */ | |
633 | if (!data) | |
634 | return; | |
635 | ||
636 | for (i = 0; i < adapter->num_tx_queues; i++) | |
637 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
638 | &adapter->tx_ring[i]->state); | |
639 | return; | |
640 | } else if (!(adapter->dcb_cfg.pfc_mode_enable)) | |
641 | return; | |
642 | ||
643 | /* update stats for each tc, only valid with PFC enabled */ | |
644 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
645 | switch (hw->mac.type) { | |
646 | case ixgbe_mac_82598EB: | |
647 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 648 | break; |
c84d324c JF |
649 | default: |
650 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 651 | } |
c84d324c JF |
652 | hwstats->pxoffrxc[i] += xoff[i]; |
653 | } | |
654 | ||
655 | /* disarm tx queues that have received xoff frames */ | |
656 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
657 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
fb5475ff | 658 | u8 tc = tx_ring->dcb_tc; |
c84d324c JF |
659 | |
660 | if (xoff[tc]) | |
661 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 662 | } |
26f23d82 YZ |
663 | } |
664 | ||
c84d324c | 665 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 666 | { |
7d7ce682 | 667 | return ring->stats.packets; |
c84d324c JF |
668 | } |
669 | ||
670 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
671 | { | |
672 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 673 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 674 | |
c84d324c JF |
675 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
676 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
677 | ||
678 | if (head != tail) | |
679 | return (head < tail) ? | |
680 | tail - head : (tail + ring->count - head); | |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
685 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
686 | { | |
687 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
688 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
689 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
690 | bool ret = false; | |
691 | ||
7d637bcc | 692 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
693 | |
694 | /* | |
695 | * Check for a hung queue, but be thorough. This verifies | |
696 | * that a transmit has been completed since the previous | |
697 | * check AND there is at least one packet pending. The | |
698 | * ARMED bit is set to indicate a potential hang. The | |
699 | * bit is cleared if a pause frame is received to remove | |
700 | * false hang detection due to PFC or 802.3x frames. By | |
701 | * requiring this to fail twice we avoid races with | |
702 | * pfc clearing the ARMED bit and conditions where we | |
703 | * run the check_tx_hang logic with a transmit completion | |
704 | * pending but without time to complete it yet. | |
705 | */ | |
706 | if ((tx_done_old == tx_done) && tx_pending) { | |
707 | /* make sure it is true for two checks in a row */ | |
708 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
709 | &tx_ring->state); | |
710 | } else { | |
711 | /* update completed stats and continue */ | |
712 | tx_ring->tx_stats.tx_done_old = tx_done; | |
713 | /* reset the countdown */ | |
714 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
715 | } |
716 | ||
c84d324c | 717 | return ret; |
9a799d71 AK |
718 | } |
719 | ||
c83c6cbd AD |
720 | /** |
721 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
722 | * @adapter: driver private struct | |
723 | **/ | |
724 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
725 | { | |
726 | ||
727 | /* Do the reset outside of interrupt context */ | |
728 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
729 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
730 | ixgbe_service_event_schedule(adapter); | |
731 | } | |
732 | } | |
e01c31a5 | 733 | |
9a799d71 AK |
734 | /** |
735 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 736 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 737 | * @tx_ring: tx ring to clean |
9a799d71 | 738 | **/ |
fe49f04a | 739 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 740 | struct ixgbe_ring *tx_ring) |
9a799d71 | 741 | { |
fe49f04a | 742 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
743 | struct ixgbe_tx_buffer *tx_buffer; |
744 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 745 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 746 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
747 | unsigned int i = tx_ring->next_to_clean; |
748 | ||
749 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
750 | return true; | |
9a799d71 | 751 | |
d3d00239 | 752 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 753 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 754 | i -= tx_ring->count; |
12207e49 | 755 | |
729739b7 | 756 | do { |
d3d00239 AD |
757 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
758 | ||
759 | /* if next_to_watch is not set then there is no work pending */ | |
760 | if (!eop_desc) | |
761 | break; | |
762 | ||
7f83a9e6 AD |
763 | /* prevent any other reads prior to eop_desc */ |
764 | rmb(); | |
765 | ||
d3d00239 AD |
766 | /* if DD is not set pending work has not been completed */ |
767 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
768 | break; | |
8ad494b0 | 769 | |
d3d00239 AD |
770 | /* clear next_to_watch to prevent false hangs */ |
771 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 772 | |
091a6246 AD |
773 | /* update the statistics for this packet */ |
774 | total_bytes += tx_buffer->bytecount; | |
775 | total_packets += tx_buffer->gso_segs; | |
776 | ||
fd0db0ed AD |
777 | /* free the skb */ |
778 | dev_kfree_skb_any(tx_buffer->skb); | |
779 | ||
729739b7 AD |
780 | /* unmap skb header data */ |
781 | dma_unmap_single(tx_ring->dev, | |
782 | dma_unmap_addr(tx_buffer, dma), | |
783 | dma_unmap_len(tx_buffer, len), | |
784 | DMA_TO_DEVICE); | |
785 | ||
fd0db0ed AD |
786 | /* clear tx_buffer data */ |
787 | tx_buffer->skb = NULL; | |
729739b7 | 788 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 789 | |
729739b7 AD |
790 | /* unmap remaining buffers */ |
791 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
792 | tx_buffer++; |
793 | tx_desc++; | |
8ad494b0 | 794 | i++; |
729739b7 AD |
795 | if (unlikely(!i)) { |
796 | i -= tx_ring->count; | |
d3d00239 | 797 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 798 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 799 | } |
e01c31a5 | 800 | |
729739b7 AD |
801 | /* unmap any remaining paged data */ |
802 | if (dma_unmap_len(tx_buffer, len)) { | |
803 | dma_unmap_page(tx_ring->dev, | |
804 | dma_unmap_addr(tx_buffer, dma), | |
805 | dma_unmap_len(tx_buffer, len), | |
806 | DMA_TO_DEVICE); | |
807 | dma_unmap_len_set(tx_buffer, len, 0); | |
808 | } | |
809 | } | |
810 | ||
811 | /* move us one more past the eop_desc for start of next pkt */ | |
812 | tx_buffer++; | |
813 | tx_desc++; | |
814 | i++; | |
815 | if (unlikely(!i)) { | |
816 | i -= tx_ring->count; | |
817 | tx_buffer = tx_ring->tx_buffer_info; | |
818 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
819 | } | |
820 | ||
821 | /* issue prefetch for next Tx descriptor */ | |
822 | prefetch(tx_desc); | |
12207e49 | 823 | |
729739b7 AD |
824 | /* update budget accounting */ |
825 | budget--; | |
826 | } while (likely(budget)); | |
827 | ||
828 | i += tx_ring->count; | |
9a799d71 | 829 | tx_ring->next_to_clean = i; |
d3d00239 | 830 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 831 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 832 | tx_ring->stats.packets += total_packets; |
d3d00239 | 833 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
834 | q_vector->tx.total_bytes += total_bytes; |
835 | q_vector->tx.total_packets += total_packets; | |
b953799e | 836 | |
c84d324c JF |
837 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
838 | /* schedule immediate reset if we believe we hung */ | |
839 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
840 | e_err(drv, "Detected Tx Unit Hang\n" |
841 | " Tx Queue <%d>\n" | |
842 | " TDH, TDT <%x>, <%x>\n" | |
843 | " next_to_use <%x>\n" | |
844 | " next_to_clean <%x>\n" | |
845 | "tx_buffer_info[next_to_clean]\n" | |
846 | " time_stamp <%lx>\n" | |
847 | " jiffies <%lx>\n", | |
848 | tx_ring->queue_index, | |
849 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
850 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
851 | tx_ring->next_to_use, i, |
852 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
853 | |
854 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
855 | ||
856 | e_info(probe, | |
857 | "tx hang %d detected on queue %d, resetting adapter\n", | |
858 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
859 | ||
b953799e | 860 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 861 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
862 | |
863 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 864 | return true; |
b953799e | 865 | } |
9a799d71 | 866 | |
b2d96e0a AD |
867 | netdev_tx_completed_queue(txring_txq(tx_ring), |
868 | total_packets, total_bytes); | |
869 | ||
e092be60 | 870 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 871 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 872 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
873 | /* Make sure that anybody stopping the queue after this |
874 | * sees the new next_to_clean. | |
875 | */ | |
876 | smp_mb(); | |
729739b7 AD |
877 | if (__netif_subqueue_stopped(tx_ring->netdev, |
878 | tx_ring->queue_index) | |
879 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
880 | netif_wake_subqueue(tx_ring->netdev, | |
881 | tx_ring->queue_index); | |
5b7da515 | 882 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 883 | } |
e092be60 | 884 | } |
9a799d71 | 885 | |
59224555 | 886 | return !!budget; |
9a799d71 AK |
887 | } |
888 | ||
5dd2d332 | 889 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
890 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
891 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 892 | int cpu) |
bd0362dd | 893 | { |
33cf09c9 | 894 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
895 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
896 | u16 reg_offset; | |
33cf09c9 | 897 | |
33cf09c9 AD |
898 | switch (hw->mac.type) { |
899 | case ixgbe_mac_82598EB: | |
bdda1a61 | 900 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
901 | break; |
902 | case ixgbe_mac_82599EB: | |
b93a2226 | 903 | case ixgbe_mac_X540: |
bdda1a61 AD |
904 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
905 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
906 | break; |
907 | default: | |
bdda1a61 AD |
908 | /* for unknown hardware do not write register */ |
909 | return; | |
bd0362dd | 910 | } |
bdda1a61 AD |
911 | |
912 | /* | |
913 | * We can enable relaxed ordering for reads, but not writes when | |
914 | * DCA is enabled. This is due to a known issue in some chipsets | |
915 | * which will cause the DCA tag to be cleared. | |
916 | */ | |
917 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
918 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
919 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
920 | ||
921 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
922 | } |
923 | ||
bdda1a61 AD |
924 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
925 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 926 | int cpu) |
bd0362dd | 927 | { |
33cf09c9 | 928 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
929 | u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); |
930 | u8 reg_idx = rx_ring->reg_idx; | |
931 | ||
33cf09c9 AD |
932 | |
933 | switch (hw->mac.type) { | |
33cf09c9 | 934 | case ixgbe_mac_82599EB: |
b93a2226 | 935 | case ixgbe_mac_X540: |
bdda1a61 | 936 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
937 | break; |
938 | default: | |
939 | break; | |
940 | } | |
bdda1a61 AD |
941 | |
942 | /* | |
943 | * We can enable relaxed ordering for reads, but not writes when | |
944 | * DCA is enabled. This is due to a known issue in some chipsets | |
945 | * which will cause the DCA tag to be cleared. | |
946 | */ | |
947 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
948 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | | |
949 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; | |
950 | ||
951 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
952 | } |
953 | ||
954 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
955 | { | |
956 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 957 | struct ixgbe_ring *ring; |
bd0362dd | 958 | int cpu = get_cpu(); |
bd0362dd | 959 | |
33cf09c9 AD |
960 | if (q_vector->cpu == cpu) |
961 | goto out_no_update; | |
962 | ||
a557928e | 963 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 964 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 965 | |
a557928e | 966 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 967 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
968 | |
969 | q_vector->cpu = cpu; | |
970 | out_no_update: | |
bd0362dd JC |
971 | put_cpu(); |
972 | } | |
973 | ||
974 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
975 | { | |
33cf09c9 | 976 | int num_q_vectors; |
bd0362dd JC |
977 | int i; |
978 | ||
979 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
980 | return; | |
981 | ||
e35ec126 AD |
982 | /* always use CB2 mode, difference is masked in the CB driver */ |
983 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
984 | ||
33cf09c9 AD |
985 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
986 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
987 | else | |
988 | num_q_vectors = 1; | |
989 | ||
990 | for (i = 0; i < num_q_vectors; i++) { | |
991 | adapter->q_vector[i]->cpu = -1; | |
992 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
993 | } |
994 | } | |
995 | ||
996 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
997 | { | |
c60fbb00 | 998 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
999 | unsigned long event = *(unsigned long *)data; |
1000 | ||
2a72c31e | 1001 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1002 | return 0; |
1003 | ||
bd0362dd JC |
1004 | switch (event) { |
1005 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1006 | /* if we're already enabled, don't do it again */ |
1007 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1008 | break; | |
652f093f | 1009 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1010 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1011 | ixgbe_setup_dca(adapter); |
1012 | break; | |
1013 | } | |
1014 | /* Fall Through since DCA is disabled. */ | |
1015 | case DCA_PROVIDER_REMOVE: | |
1016 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1017 | dca_remove_requester(dev); | |
1018 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1019 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1020 | } | |
1021 | break; | |
1022 | } | |
1023 | ||
652f093f | 1024 | return 0; |
bd0362dd | 1025 | } |
67a74ee2 | 1026 | |
bdda1a61 | 1027 | #endif /* CONFIG_IXGBE_DCA */ |
8a0da21b AD |
1028 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1029 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1030 | struct sk_buff *skb) |
1031 | { | |
8a0da21b AD |
1032 | if (ring->netdev->features & NETIF_F_RXHASH) |
1033 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
67a74ee2 ET |
1034 | } |
1035 | ||
f800326d | 1036 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1037 | /** |
1038 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
1039 | * @adapter: address of board private structure | |
1040 | * @rx_desc: advanced rx descriptor | |
1041 | * | |
1042 | * Returns : true if it is FCoE pkt | |
1043 | */ | |
1044 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter, | |
1045 | union ixgbe_adv_rx_desc *rx_desc) | |
1046 | { | |
1047 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1048 | ||
1049 | return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
1050 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == | |
1051 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1052 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1053 | } | |
1054 | ||
f800326d | 1055 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1056 | /** |
1057 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1058 | * @ring: structure containing ring specific data |
1059 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1060 | * @skb: skb currently being received and modified |
1061 | **/ | |
8a0da21b | 1062 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1063 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1064 | struct sk_buff *skb) |
9a799d71 | 1065 | { |
8a0da21b | 1066 | skb_checksum_none_assert(skb); |
9a799d71 | 1067 | |
712744be | 1068 | /* Rx csum disabled */ |
8a0da21b | 1069 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1070 | return; |
e59bd25d AV |
1071 | |
1072 | /* if IP and error */ | |
f56e0cb1 AD |
1073 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1074 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1075 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1076 | return; |
1077 | } | |
e59bd25d | 1078 | |
f56e0cb1 | 1079 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1080 | return; |
1081 | ||
f56e0cb1 | 1082 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
f800326d | 1083 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
8bae1b2b DS |
1084 | |
1085 | /* | |
1086 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1087 | * checksum errors. | |
1088 | */ | |
8a0da21b AD |
1089 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1090 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1091 | return; |
1092 | ||
8a0da21b | 1093 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1094 | return; |
1095 | } | |
1096 | ||
9a799d71 | 1097 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1098 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1099 | } |
1100 | ||
84ea2591 | 1101 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 | 1102 | { |
f56e0cb1 | 1103 | rx_ring->next_to_use = val; |
f800326d AD |
1104 | |
1105 | /* update next to alloc since we have filled the ring */ | |
1106 | rx_ring->next_to_alloc = val; | |
e8e26350 PW |
1107 | /* |
1108 | * Force memory writes to complete before letting h/w | |
1109 | * know there are new descriptors to fetch. (Only | |
1110 | * applicable for weak-ordered memory model archs, | |
1111 | * such as IA-64). | |
1112 | */ | |
1113 | wmb(); | |
84ea2591 | 1114 | writel(val, rx_ring->tail); |
e8e26350 PW |
1115 | } |
1116 | ||
f990b79b AD |
1117 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1118 | struct ixgbe_rx_buffer *bi) | |
1119 | { | |
1120 | struct page *page = bi->page; | |
f800326d | 1121 | dma_addr_t dma = bi->dma; |
f990b79b | 1122 | |
f800326d AD |
1123 | /* since we are recycling buffers we should seldom need to alloc */ |
1124 | if (likely(dma)) | |
f990b79b AD |
1125 | return true; |
1126 | ||
f800326d AD |
1127 | /* alloc new page for storage */ |
1128 | if (likely(!page)) { | |
1129 | page = alloc_pages(GFP_ATOMIC | __GFP_COLD, | |
1130 | ixgbe_rx_pg_order(rx_ring)); | |
f990b79b AD |
1131 | if (unlikely(!page)) { |
1132 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1133 | return false; | |
1134 | } | |
f800326d | 1135 | bi->page = page; |
f990b79b AD |
1136 | } |
1137 | ||
f800326d AD |
1138 | /* map page for use */ |
1139 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1140 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1141 | ||
1142 | /* | |
1143 | * if mapping failed free memory back to system since | |
1144 | * there isn't much point in holding memory we can't use | |
1145 | */ | |
1146 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
1147 | put_page(page); | |
1148 | bi->page = NULL; | |
f990b79b | 1149 | |
f990b79b AD |
1150 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1151 | return false; | |
1152 | } | |
1153 | ||
f800326d AD |
1154 | bi->dma = dma; |
1155 | bi->page_offset ^= ixgbe_rx_bufsz(rx_ring); | |
1156 | ||
f990b79b AD |
1157 | return true; |
1158 | } | |
1159 | ||
9a799d71 | 1160 | /** |
f990b79b | 1161 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1162 | * @rx_ring: ring to place buffers on |
1163 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1164 | **/ |
fc77dc3c | 1165 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1166 | { |
9a799d71 | 1167 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1168 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1169 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1170 | |
f800326d AD |
1171 | /* nothing to do */ |
1172 | if (!cleaned_count) | |
fc77dc3c AD |
1173 | return; |
1174 | ||
e4f74028 | 1175 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1176 | bi = &rx_ring->rx_buffer_info[i]; |
1177 | i -= rx_ring->count; | |
9a799d71 | 1178 | |
f800326d AD |
1179 | do { |
1180 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1181 | break; |
d5f398ed | 1182 | |
f800326d AD |
1183 | /* |
1184 | * Refresh the desc even if buffer_addrs didn't change | |
1185 | * because each write-back erases this info. | |
1186 | */ | |
1187 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1188 | |
f990b79b AD |
1189 | rx_desc++; |
1190 | bi++; | |
9a799d71 | 1191 | i++; |
f990b79b | 1192 | if (unlikely(!i)) { |
e4f74028 | 1193 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1194 | bi = rx_ring->rx_buffer_info; |
1195 | i -= rx_ring->count; | |
1196 | } | |
1197 | ||
1198 | /* clear the hdr_addr for the next_to_use descriptor */ | |
1199 | rx_desc->read.hdr_addr = 0; | |
f800326d AD |
1200 | |
1201 | cleaned_count--; | |
1202 | } while (cleaned_count); | |
7c6e0a43 | 1203 | |
f990b79b AD |
1204 | i += rx_ring->count; |
1205 | ||
f56e0cb1 | 1206 | if (rx_ring->next_to_use != i) |
84ea2591 | 1207 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1208 | } |
1209 | ||
1d2024f6 AD |
1210 | /** |
1211 | * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE | |
1212 | * @data: pointer to the start of the headers | |
1213 | * @max_len: total length of section to find headers in | |
1214 | * | |
1215 | * This function is meant to determine the length of headers that will | |
1216 | * be recognized by hardware for LRO, GRO, and RSC offloads. The main | |
1217 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
1218 | * packets so that we can do basic things like calculating the gso_size | |
1219 | * based on the average data per packet. | |
1220 | **/ | |
1221 | static unsigned int ixgbe_get_headlen(unsigned char *data, | |
1222 | unsigned int max_len) | |
1223 | { | |
1224 | union { | |
1225 | unsigned char *network; | |
1226 | /* l2 headers */ | |
1227 | struct ethhdr *eth; | |
1228 | struct vlan_hdr *vlan; | |
1229 | /* l3 headers */ | |
1230 | struct iphdr *ipv4; | |
1231 | } hdr; | |
1232 | __be16 protocol; | |
1233 | u8 nexthdr = 0; /* default to not TCP */ | |
1234 | u8 hlen; | |
1235 | ||
1236 | /* this should never happen, but better safe than sorry */ | |
1237 | if (max_len < ETH_HLEN) | |
1238 | return max_len; | |
1239 | ||
1240 | /* initialize network frame pointer */ | |
1241 | hdr.network = data; | |
1242 | ||
1243 | /* set first protocol and move network header forward */ | |
1244 | protocol = hdr.eth->h_proto; | |
1245 | hdr.network += ETH_HLEN; | |
1246 | ||
1247 | /* handle any vlan tag if present */ | |
1248 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
1249 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
1250 | return max_len; | |
1251 | ||
1252 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
1253 | hdr.network += VLAN_HLEN; | |
1254 | } | |
1255 | ||
1256 | /* handle L3 protocols */ | |
1257 | if (protocol == __constant_htons(ETH_P_IP)) { | |
1258 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
1259 | return max_len; | |
1260 | ||
1261 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1262 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1263 | ||
1264 | /* verify hlen meets minimum size requirements */ | |
1265 | if (hlen < sizeof(struct iphdr)) | |
1266 | return hdr.network - data; | |
1267 | ||
1268 | /* record next protocol */ | |
1269 | nexthdr = hdr.ipv4->protocol; | |
1270 | hdr.network += hlen; | |
f800326d | 1271 | #ifdef IXGBE_FCOE |
1d2024f6 AD |
1272 | } else if (protocol == __constant_htons(ETH_P_FCOE)) { |
1273 | if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) | |
1274 | return max_len; | |
1275 | hdr.network += FCOE_HEADER_LEN; | |
1276 | #endif | |
1277 | } else { | |
1278 | return hdr.network - data; | |
1279 | } | |
1280 | ||
1281 | /* finally sort out TCP */ | |
1282 | if (nexthdr == IPPROTO_TCP) { | |
1283 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
1284 | return max_len; | |
1285 | ||
1286 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
1287 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
1288 | ||
1289 | /* verify hlen meets minimum size requirements */ | |
1290 | if (hlen < sizeof(struct tcphdr)) | |
1291 | return hdr.network - data; | |
1292 | ||
1293 | hdr.network += hlen; | |
1294 | } | |
1295 | ||
1296 | /* | |
1297 | * If everything has gone correctly hdr.network should be the | |
1298 | * data section of the packet and will be the end of the header. | |
1299 | * If not then it probably represents the end of the last recognized | |
1300 | * header. | |
1301 | */ | |
1302 | if ((hdr.network - data) < max_len) | |
1303 | return hdr.network - data; | |
1304 | else | |
1305 | return max_len; | |
1306 | } | |
1307 | ||
4c1975d7 AD |
1308 | static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring, |
1309 | union ixgbe_adv_rx_desc *rx_desc, | |
1310 | struct sk_buff *skb) | |
aa80175a | 1311 | { |
4c1975d7 AD |
1312 | __le32 rsc_enabled; |
1313 | u32 rsc_cnt; | |
1314 | ||
1315 | if (!ring_is_rsc_enabled(rx_ring)) | |
1316 | return; | |
1317 | ||
1318 | rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1319 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1320 | ||
1321 | /* If this is an RSC frame rsc_cnt should be non-zero */ | |
1322 | if (!rsc_enabled) | |
1323 | return; | |
1324 | ||
1325 | rsc_cnt = le32_to_cpu(rsc_enabled); | |
1326 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1327 | ||
1328 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
aa80175a | 1329 | } |
43634e82 | 1330 | |
1d2024f6 AD |
1331 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1332 | struct sk_buff *skb) | |
1333 | { | |
f800326d | 1334 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1335 | |
1336 | /* set gso_size to avoid messing up TCP MSS */ | |
1337 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1338 | IXGBE_CB(skb)->append_cnt); | |
1339 | } | |
1340 | ||
1341 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1342 | struct sk_buff *skb) | |
1343 | { | |
1344 | /* if append_cnt is 0 then frame is not RSC */ | |
1345 | if (!IXGBE_CB(skb)->append_cnt) | |
1346 | return; | |
1347 | ||
1348 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1349 | rx_ring->rx_stats.rsc_flush++; | |
1350 | ||
1351 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1352 | ||
1353 | /* gso_size is computed using append_cnt so always clear it last */ | |
1354 | IXGBE_CB(skb)->append_cnt = 0; | |
1355 | } | |
1356 | ||
8a0da21b AD |
1357 | /** |
1358 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1359 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1360 | * @rx_desc: pointer to the EOP Rx descriptor | |
1361 | * @skb: pointer to current skb being populated | |
f8212f97 | 1362 | * |
8a0da21b AD |
1363 | * This function checks the ring, descriptor, and packet information in |
1364 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1365 | * other fields within the skb. | |
f8212f97 | 1366 | **/ |
8a0da21b AD |
1367 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1368 | union ixgbe_adv_rx_desc *rx_desc, | |
1369 | struct sk_buff *skb) | |
f8212f97 | 1370 | { |
8a0da21b AD |
1371 | ixgbe_update_rsc_stats(rx_ring, skb); |
1372 | ||
1373 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1374 | |
8a0da21b AD |
1375 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1376 | ||
1377 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
1378 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
1379 | __vlan_hwaccel_put_tag(skb, vid); | |
f8212f97 AD |
1380 | } |
1381 | ||
8a0da21b | 1382 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1383 | |
8a0da21b | 1384 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
f8212f97 AD |
1385 | } |
1386 | ||
8a0da21b AD |
1387 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1388 | struct sk_buff *skb) | |
aa80175a | 1389 | { |
8a0da21b AD |
1390 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1391 | ||
1392 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1393 | napi_gro_receive(&q_vector->napi, skb); | |
1394 | else | |
1395 | netif_rx(skb); | |
aa80175a | 1396 | } |
43634e82 | 1397 | |
f800326d AD |
1398 | /** |
1399 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1400 | * @rx_ring: Rx ring being processed | |
1401 | * @rx_desc: Rx descriptor for current buffer | |
1402 | * @skb: Current socket buffer containing buffer in progress | |
1403 | * | |
1404 | * This function updates next to clean. If the buffer is an EOP buffer | |
1405 | * this function exits returning false, otherwise it will place the | |
1406 | * sk_buff in the next buffer to be chained and return true indicating | |
1407 | * that this is in fact a non-EOP buffer. | |
1408 | **/ | |
1409 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1410 | union ixgbe_adv_rx_desc *rx_desc, | |
1411 | struct sk_buff *skb) | |
1412 | { | |
1413 | u32 ntc = rx_ring->next_to_clean + 1; | |
1414 | ||
1415 | /* fetch, update, and store next to clean */ | |
1416 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1417 | rx_ring->next_to_clean = ntc; | |
1418 | ||
1419 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1420 | ||
1421 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1422 | return false; | |
1423 | ||
1424 | /* append_cnt indicates packet is RSC, if so fetch nextp */ | |
1425 | if (IXGBE_CB(skb)->append_cnt) { | |
1426 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1427 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1428 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1429 | } | |
1430 | ||
1431 | /* place skb in next buffer to be received */ | |
1432 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1433 | rx_ring->rx_stats.non_eop_descs++; | |
1434 | ||
1435 | return true; | |
1436 | } | |
1437 | ||
1438 | /** | |
1439 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1440 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1441 | * @rx_desc: pointer to the EOP Rx descriptor | |
1442 | * @skb: pointer to current skb being fixed | |
1443 | * | |
1444 | * Check for corrupted packet headers caused by senders on the local L2 | |
1445 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1446 | * should be very rare. | |
1447 | * | |
1448 | * Also address the case where we are pulling data in on pages only | |
1449 | * and as such no data is present in the skb header. | |
1450 | * | |
1451 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1452 | * it is large enough to qualify as a valid Ethernet frame. | |
1453 | * | |
1454 | * Returns true if an error was encountered and skb was freed. | |
1455 | **/ | |
1456 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1457 | union ixgbe_adv_rx_desc *rx_desc, | |
1458 | struct sk_buff *skb) | |
1459 | { | |
1460 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1461 | struct net_device *netdev = rx_ring->netdev; | |
1462 | unsigned char *va; | |
1463 | unsigned int pull_len; | |
1464 | ||
1465 | /* if the page was released unmap it, else just sync our portion */ | |
1466 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1467 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1468 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1469 | IXGBE_CB(skb)->page_released = false; | |
1470 | } else { | |
1471 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1472 | IXGBE_CB(skb)->dma, | |
1473 | frag->page_offset, | |
1474 | ixgbe_rx_bufsz(rx_ring), | |
1475 | DMA_FROM_DEVICE); | |
1476 | } | |
1477 | IXGBE_CB(skb)->dma = 0; | |
1478 | ||
1479 | /* verify that the packet does not have any known errors */ | |
1480 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1481 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1482 | !(netdev->features & NETIF_F_RXALL))) { | |
1483 | dev_kfree_skb_any(skb); | |
1484 | return true; | |
1485 | } | |
1486 | ||
1487 | /* | |
1488 | * it is valid to use page_address instead of kmap since we are | |
1489 | * working with pages allocated out of the lomem pool per | |
1490 | * alloc_page(GFP_ATOMIC) | |
1491 | */ | |
1492 | va = skb_frag_address(frag); | |
1493 | ||
1494 | /* | |
1495 | * we need the header to contain the greater of either ETH_HLEN or | |
1496 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1497 | */ | |
1498 | pull_len = skb_frag_size(frag); | |
1499 | if (pull_len > 256) | |
1500 | pull_len = ixgbe_get_headlen(va, pull_len); | |
1501 | ||
1502 | /* align pull length to size of long to optimize memcpy performance */ | |
1503 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1504 | ||
1505 | /* update all of the pointers */ | |
1506 | skb_frag_size_sub(frag, pull_len); | |
1507 | frag->page_offset += pull_len; | |
1508 | skb->data_len -= pull_len; | |
1509 | skb->tail += pull_len; | |
1510 | ||
1511 | /* | |
1512 | * if we sucked the frag empty then we should free it, | |
1513 | * if there are other frags here something is screwed up in hardware | |
1514 | */ | |
1515 | if (skb_frag_size(frag) == 0) { | |
1516 | BUG_ON(skb_shinfo(skb)->nr_frags != 1); | |
1517 | skb_shinfo(skb)->nr_frags = 0; | |
1518 | __skb_frag_unref(frag); | |
1519 | skb->truesize -= ixgbe_rx_bufsz(rx_ring); | |
1520 | } | |
1521 | ||
1522 | /* if skb_pad returns an error the skb was freed */ | |
1523 | if (unlikely(skb->len < 60)) { | |
1524 | int pad_len = 60 - skb->len; | |
1525 | ||
1526 | if (skb_pad(skb, pad_len)) | |
1527 | return true; | |
1528 | __skb_put(skb, pad_len); | |
1529 | } | |
1530 | ||
1531 | return false; | |
1532 | } | |
1533 | ||
1534 | /** | |
1535 | * ixgbe_can_reuse_page - determine if we can reuse a page | |
1536 | * @rx_buffer: pointer to rx_buffer containing the page we want to reuse | |
1537 | * | |
1538 | * Returns true if page can be reused in another Rx buffer | |
1539 | **/ | |
1540 | static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer) | |
1541 | { | |
1542 | struct page *page = rx_buffer->page; | |
1543 | ||
1544 | /* if we are only owner of page and it is local we can reuse it */ | |
1545 | return likely(page_count(page) == 1) && | |
1546 | likely(page_to_nid(page) == numa_node_id()); | |
1547 | } | |
1548 | ||
1549 | /** | |
1550 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1551 | * @rx_ring: rx descriptor ring to store buffers on | |
1552 | * @old_buff: donor buffer to have page reused | |
1553 | * | |
1554 | * Syncronizes page for reuse by the adapter | |
1555 | **/ | |
1556 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1557 | struct ixgbe_rx_buffer *old_buff) | |
1558 | { | |
1559 | struct ixgbe_rx_buffer *new_buff; | |
1560 | u16 nta = rx_ring->next_to_alloc; | |
1561 | u16 bufsz = ixgbe_rx_bufsz(rx_ring); | |
1562 | ||
1563 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1564 | ||
1565 | /* update, and store next to alloc */ | |
1566 | nta++; | |
1567 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1568 | ||
1569 | /* transfer page from old buffer to new buffer */ | |
1570 | new_buff->page = old_buff->page; | |
1571 | new_buff->dma = old_buff->dma; | |
1572 | ||
1573 | /* flip page offset to other buffer and store to new_buff */ | |
1574 | new_buff->page_offset = old_buff->page_offset ^ bufsz; | |
1575 | ||
1576 | /* sync the buffer for use by the device */ | |
1577 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
1578 | new_buff->page_offset, bufsz, | |
1579 | DMA_FROM_DEVICE); | |
1580 | ||
1581 | /* bump ref count on page before it is given to the stack */ | |
1582 | get_page(new_buff->page); | |
1583 | } | |
1584 | ||
1585 | /** | |
1586 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1587 | * @rx_ring: rx descriptor ring to transact packets on | |
1588 | * @rx_buffer: buffer containing page to add | |
1589 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1590 | * @skb: sk_buff to place the data into | |
1591 | * | |
1592 | * This function is based on skb_add_rx_frag. I would have used that | |
1593 | * function however it doesn't handle the truesize case correctly since we | |
1594 | * are allocating more memory than might be used for a single receive. | |
1595 | **/ | |
1596 | static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, | |
1597 | struct ixgbe_rx_buffer *rx_buffer, | |
1598 | struct sk_buff *skb, int size) | |
1599 | { | |
1600 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
1601 | rx_buffer->page, rx_buffer->page_offset, | |
1602 | size); | |
1603 | skb->len += size; | |
1604 | skb->data_len += size; | |
1605 | skb->truesize += ixgbe_rx_bufsz(rx_ring); | |
1606 | } | |
1607 | ||
1608 | /** | |
1609 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1610 | * @q_vector: structure containing interrupt and ring information | |
1611 | * @rx_ring: rx descriptor ring to transact packets on | |
1612 | * @budget: Total limit on number of packets to process | |
1613 | * | |
1614 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1615 | * processing. The advantage to this is that on systems that have | |
1616 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1617 | * it by maintaining the mapping of the page to the syste. | |
1618 | * | |
1619 | * Returns true if all work is completed without reaching budget | |
1620 | **/ | |
4ff7fb12 | 1621 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1622 | struct ixgbe_ring *rx_ring, |
4ff7fb12 | 1623 | int budget) |
9a799d71 | 1624 | { |
d2f4fbe2 | 1625 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 1626 | #ifdef IXGBE_FCOE |
f800326d | 1627 | struct ixgbe_adapter *adapter = q_vector->adapter; |
3d8fd385 YZ |
1628 | int ddp_bytes = 0; |
1629 | #endif /* IXGBE_FCOE */ | |
f800326d | 1630 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 1631 | |
f800326d AD |
1632 | do { |
1633 | struct ixgbe_rx_buffer *rx_buffer; | |
1634 | union ixgbe_adv_rx_desc *rx_desc; | |
1635 | struct sk_buff *skb; | |
1636 | struct page *page; | |
1637 | u16 ntc; | |
1638 | ||
1639 | /* return some buffers to hardware, one at a time is too slow */ | |
1640 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1641 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1642 | cleaned_count = 0; | |
1643 | } | |
1644 | ||
1645 | ntc = rx_ring->next_to_clean; | |
1646 | rx_desc = IXGBE_RX_DESC(rx_ring, ntc); | |
1647 | rx_buffer = &rx_ring->rx_buffer_info[ntc]; | |
1648 | ||
1649 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) | |
1650 | break; | |
9a799d71 | 1651 | |
f800326d AD |
1652 | /* |
1653 | * This memory barrier is needed to keep us from reading | |
1654 | * any other fields out of the rx_desc until we know the | |
1655 | * RXD_STAT_DD bit is set | |
1656 | */ | |
1657 | rmb(); | |
9a799d71 | 1658 | |
f800326d AD |
1659 | page = rx_buffer->page; |
1660 | prefetchw(page); | |
9a799d71 | 1661 | |
f800326d | 1662 | skb = rx_buffer->skb; |
c267fc16 | 1663 | |
f800326d AD |
1664 | if (likely(!skb)) { |
1665 | void *page_addr = page_address(page) + | |
1666 | rx_buffer->page_offset; | |
9a799d71 | 1667 | |
f800326d AD |
1668 | /* prefetch first cache line of first page */ |
1669 | prefetch(page_addr); | |
1670 | #if L1_CACHE_BYTES < 128 | |
1671 | prefetch(page_addr + L1_CACHE_BYTES); | |
1672 | #endif | |
1673 | ||
1674 | /* allocate a skb to store the frags */ | |
1675 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1676 | IXGBE_RX_HDR_SIZE); | |
1677 | if (unlikely(!skb)) { | |
1678 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1679 | break; | |
c267fc16 AD |
1680 | } |
1681 | ||
f800326d AD |
1682 | /* |
1683 | * we will be copying header into skb->data in | |
1684 | * pskb_may_pull so it is in our interest to prefetch | |
1685 | * it now to avoid a possible cache miss | |
1686 | */ | |
1687 | prefetchw(skb->data); | |
4c1975d7 AD |
1688 | |
1689 | /* | |
1690 | * Delay unmapping of the first packet. It carries the | |
1691 | * header information, HW may still access the header | |
f800326d AD |
1692 | * after the writeback. Only unmap it when EOP is |
1693 | * reached | |
4c1975d7 | 1694 | */ |
f800326d | 1695 | IXGBE_CB(skb)->dma = rx_buffer->dma; |
c267fc16 | 1696 | } else { |
f800326d AD |
1697 | /* we are reusing so sync this buffer for CPU use */ |
1698 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1699 | rx_buffer->dma, | |
1700 | rx_buffer->page_offset, | |
1701 | ixgbe_rx_bufsz(rx_ring), | |
1702 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1703 | } |
1704 | ||
f800326d AD |
1705 | /* pull page into skb */ |
1706 | ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, | |
1707 | le16_to_cpu(rx_desc->wb.upper.length)); | |
9a799d71 | 1708 | |
f800326d AD |
1709 | if (ixgbe_can_reuse_page(rx_buffer)) { |
1710 | /* hand second half of page back to the ring */ | |
1711 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
1712 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
1713 | /* the page has been released from the ring */ | |
1714 | IXGBE_CB(skb)->page_released = true; | |
1715 | } else { | |
1716 | /* we are not reusing the buffer so unmap it */ | |
1717 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
1718 | ixgbe_rx_pg_size(rx_ring), | |
1719 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1720 | } |
1721 | ||
f800326d AD |
1722 | /* clear contents of buffer_info */ |
1723 | rx_buffer->skb = NULL; | |
1724 | rx_buffer->dma = 0; | |
1725 | rx_buffer->page = NULL; | |
4c1975d7 | 1726 | |
f800326d | 1727 | ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb); |
9a799d71 | 1728 | |
9a799d71 | 1729 | cleaned_count++; |
f8212f97 | 1730 | |
f800326d AD |
1731 | /* place incomplete frames back on ring for completion */ |
1732 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
1733 | continue; | |
c267fc16 | 1734 | |
f800326d AD |
1735 | /* verify the packet layout is correct */ |
1736 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
1737 | continue; | |
9a799d71 | 1738 | |
d2f4fbe2 AV |
1739 | /* probably a little skewed due to removing CRC */ |
1740 | total_rx_bytes += skb->len; | |
1741 | total_rx_packets++; | |
1742 | ||
8a0da21b AD |
1743 | /* populate checksum, timestamp, VLAN, and protocol */ |
1744 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
1745 | ||
332d4a7d YZ |
1746 | #ifdef IXGBE_FCOE |
1747 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
ff886dfc | 1748 | if (ixgbe_rx_is_fcoe(adapter, rx_desc)) { |
f56e0cb1 | 1749 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
63d635b2 AD |
1750 | if (!ddp_bytes) { |
1751 | dev_kfree_skb_any(skb); | |
f800326d | 1752 | continue; |
63d635b2 | 1753 | } |
3d8fd385 | 1754 | } |
f800326d | 1755 | |
332d4a7d | 1756 | #endif /* IXGBE_FCOE */ |
8a0da21b | 1757 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 1758 | |
f800326d | 1759 | /* update budget accounting */ |
4ff7fb12 | 1760 | budget--; |
f800326d | 1761 | } while (likely(budget)); |
9a799d71 | 1762 | |
3d8fd385 YZ |
1763 | #ifdef IXGBE_FCOE |
1764 | /* include DDPed FCoE data */ | |
1765 | if (ddp_bytes > 0) { | |
1766 | unsigned int mss; | |
1767 | ||
fc77dc3c | 1768 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1769 | sizeof(struct fc_frame_header) - |
1770 | sizeof(struct fcoe_crc_eof); | |
1771 | if (mss > 512) | |
1772 | mss &= ~511; | |
1773 | total_rx_bytes += ddp_bytes; | |
1774 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1775 | } | |
3d8fd385 | 1776 | |
f800326d | 1777 | #endif /* IXGBE_FCOE */ |
c267fc16 AD |
1778 | u64_stats_update_begin(&rx_ring->syncp); |
1779 | rx_ring->stats.packets += total_rx_packets; | |
1780 | rx_ring->stats.bytes += total_rx_bytes; | |
1781 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1782 | q_vector->rx.total_packets += total_rx_packets; |
1783 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 1784 | |
f800326d AD |
1785 | if (cleaned_count) |
1786 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1787 | ||
4ff7fb12 | 1788 | return !!budget; |
9a799d71 AK |
1789 | } |
1790 | ||
9a799d71 AK |
1791 | /** |
1792 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1793 | * @adapter: board private structure | |
1794 | * | |
1795 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1796 | * interrupts. | |
1797 | **/ | |
1798 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1799 | { | |
021230d4 | 1800 | struct ixgbe_q_vector *q_vector; |
efe3d3c8 | 1801 | int q_vectors, v_idx; |
021230d4 | 1802 | u32 mask; |
9a799d71 | 1803 | |
021230d4 | 1804 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1805 | |
8e34d1aa AD |
1806 | /* Populate MSIX to EITR Select */ |
1807 | if (adapter->num_vfs > 32) { | |
1808 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1809 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1810 | } | |
1811 | ||
4df10466 JB |
1812 | /* |
1813 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1814 | * corresponding register. |
1815 | */ | |
1816 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
efe3d3c8 | 1817 | struct ixgbe_ring *ring; |
7a921c93 | 1818 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1819 | |
a557928e | 1820 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
1821 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
1822 | ||
a557928e | 1823 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
1824 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
1825 | ||
d5bf4f67 ET |
1826 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
1827 | /* tx only vector */ | |
1828 | if (adapter->tx_itr_setting == 1) | |
1829 | q_vector->itr = IXGBE_10K_ITR; | |
1830 | else | |
1831 | q_vector->itr = adapter->tx_itr_setting; | |
1832 | } else { | |
1833 | /* rx or rx/tx vector */ | |
1834 | if (adapter->rx_itr_setting == 1) | |
1835 | q_vector->itr = IXGBE_20K_ITR; | |
1836 | else | |
1837 | q_vector->itr = adapter->rx_itr_setting; | |
1838 | } | |
021230d4 | 1839 | |
fe49f04a | 1840 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1841 | } |
1842 | ||
bd508178 AD |
1843 | switch (adapter->hw.mac.type) { |
1844 | case ixgbe_mac_82598EB: | |
e8e26350 | 1845 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1846 | v_idx); |
bd508178 AD |
1847 | break; |
1848 | case ixgbe_mac_82599EB: | |
b93a2226 | 1849 | case ixgbe_mac_X540: |
e8e26350 | 1850 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 1851 | break; |
bd508178 AD |
1852 | default: |
1853 | break; | |
1854 | } | |
021230d4 AV |
1855 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1856 | ||
41fb9248 | 1857 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1858 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
1859 | mask &= ~(IXGBE_EIMS_OTHER | |
1860 | IXGBE_EIMS_MAILBOX | | |
1861 | IXGBE_EIMS_LSC); | |
1862 | ||
021230d4 | 1863 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1864 | } |
1865 | ||
f494e8fa AV |
1866 | enum latency_range { |
1867 | lowest_latency = 0, | |
1868 | low_latency = 1, | |
1869 | bulk_latency = 2, | |
1870 | latency_invalid = 255 | |
1871 | }; | |
1872 | ||
1873 | /** | |
1874 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
1875 | * @q_vector: structure containing interrupt and ring information |
1876 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
1877 | * |
1878 | * Stores a new ITR value based on packets and byte | |
1879 | * counts during the last interrupt. The advantage of per interrupt | |
1880 | * computation is faster updates and more accurate ITR for the current | |
1881 | * traffic pattern. Constants in this function were computed | |
1882 | * based on theoretical maximum wire speed and thresholds were set based | |
1883 | * on testing data as well as attempting to minimize response time | |
1884 | * while increasing bulk throughput. | |
1885 | * this functionality is controlled by the InterruptThrottleRate module | |
1886 | * parameter (see ixgbe_param.c) | |
1887 | **/ | |
bd198058 AD |
1888 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
1889 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 1890 | { |
bd198058 AD |
1891 | int bytes = ring_container->total_bytes; |
1892 | int packets = ring_container->total_packets; | |
1893 | u32 timepassed_us; | |
621bd70e | 1894 | u64 bytes_perint; |
bd198058 | 1895 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
1896 | |
1897 | if (packets == 0) | |
bd198058 | 1898 | return; |
f494e8fa AV |
1899 | |
1900 | /* simple throttlerate management | |
621bd70e AD |
1901 | * 0-10MB/s lowest (100000 ints/s) |
1902 | * 10-20MB/s low (20000 ints/s) | |
1903 | * 20-1249MB/s bulk (8000 ints/s) | |
f494e8fa AV |
1904 | */ |
1905 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 1906 | timepassed_us = q_vector->itr >> 2; |
f494e8fa AV |
1907 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1908 | ||
1909 | switch (itr_setting) { | |
1910 | case lowest_latency: | |
621bd70e | 1911 | if (bytes_perint > 10) |
bd198058 | 1912 | itr_setting = low_latency; |
f494e8fa AV |
1913 | break; |
1914 | case low_latency: | |
621bd70e | 1915 | if (bytes_perint > 20) |
bd198058 | 1916 | itr_setting = bulk_latency; |
621bd70e | 1917 | else if (bytes_perint <= 10) |
bd198058 | 1918 | itr_setting = lowest_latency; |
f494e8fa AV |
1919 | break; |
1920 | case bulk_latency: | |
621bd70e | 1921 | if (bytes_perint <= 20) |
bd198058 | 1922 | itr_setting = low_latency; |
f494e8fa AV |
1923 | break; |
1924 | } | |
1925 | ||
bd198058 AD |
1926 | /* clear work counters since we have the values we need */ |
1927 | ring_container->total_bytes = 0; | |
1928 | ring_container->total_packets = 0; | |
1929 | ||
1930 | /* write updated itr to ring container */ | |
1931 | ring_container->itr = itr_setting; | |
f494e8fa AV |
1932 | } |
1933 | ||
509ee935 JB |
1934 | /** |
1935 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1936 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1937 | * |
1938 | * This function is made to be called by ethtool and by the driver | |
1939 | * when it needs to update EITR registers at runtime. Hardware | |
1940 | * specific quirks/differences are taken care of here. | |
1941 | */ | |
fe49f04a | 1942 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1943 | { |
fe49f04a | 1944 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1945 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1946 | int v_idx = q_vector->v_idx; |
5d967eb7 | 1947 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 1948 | |
bd508178 AD |
1949 | switch (adapter->hw.mac.type) { |
1950 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1951 | /* must write high and low 16 bits to reset counter */ |
1952 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1953 | break; |
1954 | case ixgbe_mac_82599EB: | |
b93a2226 | 1955 | case ixgbe_mac_X540: |
509ee935 JB |
1956 | /* |
1957 | * set the WDIS bit to not clear the timer bits and cause an | |
1958 | * immediate assertion of the interrupt | |
1959 | */ | |
1960 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1961 | break; |
1962 | default: | |
1963 | break; | |
509ee935 JB |
1964 | } |
1965 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1966 | } | |
1967 | ||
bd198058 | 1968 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 1969 | { |
d5bf4f67 | 1970 | u32 new_itr = q_vector->itr; |
bd198058 | 1971 | u8 current_itr; |
f494e8fa | 1972 | |
bd198058 AD |
1973 | ixgbe_update_itr(q_vector, &q_vector->tx); |
1974 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 1975 | |
08c8833b | 1976 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
1977 | |
1978 | switch (current_itr) { | |
1979 | /* counts and packets in update_itr are dependent on these numbers */ | |
1980 | case lowest_latency: | |
d5bf4f67 | 1981 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
1982 | break; |
1983 | case low_latency: | |
d5bf4f67 | 1984 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
1985 | break; |
1986 | case bulk_latency: | |
d5bf4f67 | 1987 | new_itr = IXGBE_8K_ITR; |
f494e8fa | 1988 | break; |
bd198058 AD |
1989 | default: |
1990 | break; | |
f494e8fa AV |
1991 | } |
1992 | ||
d5bf4f67 | 1993 | if (new_itr != q_vector->itr) { |
fe49f04a | 1994 | /* do an exponential smoothing */ |
d5bf4f67 ET |
1995 | new_itr = (10 * new_itr * q_vector->itr) / |
1996 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 1997 | |
bd198058 | 1998 | /* save the algorithm value here */ |
5d967eb7 | 1999 | q_vector->itr = new_itr; |
fe49f04a AD |
2000 | |
2001 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2002 | } |
f494e8fa AV |
2003 | } |
2004 | ||
119fc60a | 2005 | /** |
de88eeeb | 2006 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2007 | * @adapter: pointer to adapter |
119fc60a | 2008 | **/ |
f0f9778d | 2009 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2010 | { |
119fc60a MC |
2011 | struct ixgbe_hw *hw = &adapter->hw; |
2012 | u32 eicr = adapter->interrupt_event; | |
2013 | ||
f0f9778d | 2014 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2015 | return; |
2016 | ||
f0f9778d AD |
2017 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2018 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2019 | return; | |
2020 | ||
2021 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2022 | ||
7ca647bd | 2023 | switch (hw->device_id) { |
f0f9778d AD |
2024 | case IXGBE_DEV_ID_82599_T3_LOM: |
2025 | /* | |
2026 | * Since the warning interrupt is for both ports | |
2027 | * we don't have to check if: | |
2028 | * - This interrupt wasn't for our port. | |
2029 | * - We may have missed the interrupt so always have to | |
2030 | * check if we got a LSC | |
2031 | */ | |
2032 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
2033 | !(eicr & IXGBE_EICR_LSC)) | |
2034 | return; | |
2035 | ||
2036 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
2037 | u32 autoneg; | |
2038 | bool link_up = false; | |
7ca647bd | 2039 | |
7ca647bd JP |
2040 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
2041 | ||
f0f9778d AD |
2042 | if (link_up) |
2043 | return; | |
2044 | } | |
2045 | ||
2046 | /* Check if this is not due to overtemp */ | |
2047 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2048 | return; | |
2049 | ||
2050 | break; | |
7ca647bd JP |
2051 | default: |
2052 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 2053 | return; |
7ca647bd | 2054 | break; |
119fc60a | 2055 | } |
7ca647bd JP |
2056 | e_crit(drv, |
2057 | "Network adapter has been stopped because it has over heated. " | |
2058 | "Restart the computer. If the problem persists, " | |
2059 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
2060 | |
2061 | adapter->interrupt_event = 0; | |
119fc60a MC |
2062 | } |
2063 | ||
0befdb3e JB |
2064 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2065 | { | |
2066 | struct ixgbe_hw *hw = &adapter->hw; | |
2067 | ||
2068 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
2069 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 2070 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
2071 | /* write to clear the interrupt */ |
2072 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
2073 | } | |
2074 | } | |
cf8280ee | 2075 | |
4f51bf70 JK |
2076 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2077 | { | |
2078 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) | |
2079 | return; | |
2080 | ||
2081 | switch (adapter->hw.mac.type) { | |
2082 | case ixgbe_mac_82599EB: | |
2083 | /* | |
2084 | * Need to check link state so complete overtemp check | |
2085 | * on service task | |
2086 | */ | |
2087 | if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && | |
2088 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { | |
2089 | adapter->interrupt_event = eicr; | |
2090 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2091 | ixgbe_service_event_schedule(adapter); | |
2092 | return; | |
2093 | } | |
2094 | return; | |
2095 | case ixgbe_mac_X540: | |
2096 | if (!(eicr & IXGBE_EICR_TS)) | |
2097 | return; | |
2098 | break; | |
2099 | default: | |
2100 | return; | |
2101 | } | |
2102 | ||
2103 | e_crit(drv, | |
2104 | "Network adapter has been stopped because it has over heated. " | |
2105 | "Restart the computer. If the problem persists, " | |
2106 | "power off the system and replace the adapter\n"); | |
2107 | } | |
2108 | ||
e8e26350 PW |
2109 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2110 | { | |
2111 | struct ixgbe_hw *hw = &adapter->hw; | |
2112 | ||
73c4b7cd AD |
2113 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
2114 | /* Clear the interrupt */ | |
2115 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
2116 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2117 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
2118 | ixgbe_service_event_schedule(adapter); | |
2119 | } | |
73c4b7cd AD |
2120 | } |
2121 | ||
e8e26350 PW |
2122 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
2123 | /* Clear the interrupt */ | |
2124 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
2125 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2126 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2127 | ixgbe_service_event_schedule(adapter); | |
2128 | } | |
e8e26350 PW |
2129 | } |
2130 | } | |
2131 | ||
cf8280ee JB |
2132 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2133 | { | |
2134 | struct ixgbe_hw *hw = &adapter->hw; | |
2135 | ||
2136 | adapter->lsc_int++; | |
2137 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2138 | adapter->link_check_timeout = jiffies; | |
2139 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2140 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2141 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2142 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2143 | } |
2144 | } | |
2145 | ||
fe49f04a AD |
2146 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2147 | u64 qmask) | |
2148 | { | |
2149 | u32 mask; | |
bd508178 | 2150 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2151 | |
bd508178 AD |
2152 | switch (hw->mac.type) { |
2153 | case ixgbe_mac_82598EB: | |
fe49f04a | 2154 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2155 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2156 | break; | |
2157 | case ixgbe_mac_82599EB: | |
b93a2226 | 2158 | case ixgbe_mac_X540: |
fe49f04a | 2159 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2160 | if (mask) |
2161 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2162 | mask = (qmask >> 32); |
bd508178 AD |
2163 | if (mask) |
2164 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2165 | break; | |
2166 | default: | |
2167 | break; | |
fe49f04a AD |
2168 | } |
2169 | /* skip the flush */ | |
2170 | } | |
2171 | ||
2172 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2173 | u64 qmask) |
fe49f04a AD |
2174 | { |
2175 | u32 mask; | |
bd508178 | 2176 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2177 | |
bd508178 AD |
2178 | switch (hw->mac.type) { |
2179 | case ixgbe_mac_82598EB: | |
fe49f04a | 2180 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2181 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2182 | break; | |
2183 | case ixgbe_mac_82599EB: | |
b93a2226 | 2184 | case ixgbe_mac_X540: |
fe49f04a | 2185 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2186 | if (mask) |
2187 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2188 | mask = (qmask >> 32); |
bd508178 AD |
2189 | if (mask) |
2190 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2191 | break; | |
2192 | default: | |
2193 | break; | |
fe49f04a AD |
2194 | } |
2195 | /* skip the flush */ | |
2196 | } | |
2197 | ||
021230d4 | 2198 | /** |
2c4af694 AD |
2199 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2200 | * @adapter: board private structure | |
021230d4 | 2201 | **/ |
2c4af694 AD |
2202 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2203 | bool flush) | |
9a799d71 | 2204 | { |
2c4af694 | 2205 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2206 | |
2c4af694 AD |
2207 | /* don't reenable LSC while waiting for link */ |
2208 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2209 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2210 | |
2c4af694 | 2211 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2212 | switch (adapter->hw.mac.type) { |
2213 | case ixgbe_mac_82599EB: | |
2214 | mask |= IXGBE_EIMS_GPI_SDP0; | |
2215 | break; | |
2216 | case ixgbe_mac_X540: | |
2217 | mask |= IXGBE_EIMS_TS; | |
2218 | break; | |
2219 | default: | |
2220 | break; | |
2221 | } | |
2c4af694 AD |
2222 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2223 | mask |= IXGBE_EIMS_GPI_SDP1; | |
2224 | switch (adapter->hw.mac.type) { | |
2225 | case ixgbe_mac_82599EB: | |
2c4af694 AD |
2226 | mask |= IXGBE_EIMS_GPI_SDP1; |
2227 | mask |= IXGBE_EIMS_GPI_SDP2; | |
858bc081 DS |
2228 | case ixgbe_mac_X540: |
2229 | mask |= IXGBE_EIMS_ECC; | |
2c4af694 AD |
2230 | mask |= IXGBE_EIMS_MAILBOX; |
2231 | break; | |
2232 | default: | |
2233 | break; | |
9a799d71 | 2234 | } |
2c4af694 AD |
2235 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2236 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2237 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2238 | |
2c4af694 AD |
2239 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2240 | if (queues) | |
2241 | ixgbe_irq_enable_queues(adapter, ~0); | |
2242 | if (flush) | |
2243 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2244 | } |
2245 | ||
2c4af694 | 2246 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2247 | { |
a65151ba | 2248 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2249 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2250 | u32 eicr; |
91281fd3 | 2251 | |
54037505 DS |
2252 | /* |
2253 | * Workaround for Silicon errata. Use clear-by-write instead | |
2254 | * of clear-by-read. Reading with EICS will return the | |
2255 | * interrupt causes without clearing, which later be done | |
2256 | * with the write to EICR. | |
2257 | */ | |
2258 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
2259 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 2260 | |
cf8280ee JB |
2261 | if (eicr & IXGBE_EICR_LSC) |
2262 | ixgbe_check_lsc(adapter); | |
f0848276 | 2263 | |
1cdd1ec8 GR |
2264 | if (eicr & IXGBE_EICR_MAILBOX) |
2265 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2266 | |
bd508178 AD |
2267 | switch (hw->mac.type) { |
2268 | case ixgbe_mac_82599EB: | |
b93a2226 | 2269 | case ixgbe_mac_X540: |
2c4af694 AD |
2270 | if (eicr & IXGBE_EICR_ECC) |
2271 | e_info(link, "Received unrecoverable ECC Err, please " | |
2272 | "reboot\n"); | |
c4cf55e5 PWJ |
2273 | /* Handle Flow Director Full threshold interrupt */ |
2274 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2275 | int reinit_count = 0; |
c4cf55e5 | 2276 | int i; |
c4cf55e5 | 2277 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2278 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2279 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2280 | &ring->state)) |
2281 | reinit_count++; | |
2282 | } | |
2283 | if (reinit_count) { | |
2284 | /* no more flow director interrupts until after init */ | |
2285 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2286 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2287 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2288 | } |
2289 | } | |
f0f9778d | 2290 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2291 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2292 | break; |
2293 | default: | |
2294 | break; | |
c4cf55e5 | 2295 | } |
f0848276 | 2296 | |
bd508178 | 2297 | ixgbe_check_fan_failure(adapter, eicr); |
efe3d3c8 | 2298 | |
7086400d | 2299 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2300 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2301 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2302 | |
9a799d71 | 2303 | return IRQ_HANDLED; |
f0848276 | 2304 | } |
91281fd3 | 2305 | |
4ff7fb12 | 2306 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2307 | { |
021230d4 | 2308 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2309 | |
9b471446 | 2310 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2311 | |
4ff7fb12 AD |
2312 | if (q_vector->rx.ring || q_vector->tx.ring) |
2313 | napi_schedule(&q_vector->napi); | |
91281fd3 | 2314 | |
9a799d71 | 2315 | return IRQ_HANDLED; |
91281fd3 AD |
2316 | } |
2317 | ||
eb01b975 AD |
2318 | /** |
2319 | * ixgbe_poll - NAPI Rx polling callback | |
2320 | * @napi: structure for representing this polling device | |
2321 | * @budget: how many packets driver is allowed to clean | |
2322 | * | |
2323 | * This function is used for legacy and MSI, NAPI mode | |
2324 | **/ | |
8af3c33f | 2325 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
2326 | { |
2327 | struct ixgbe_q_vector *q_vector = | |
2328 | container_of(napi, struct ixgbe_q_vector, napi); | |
2329 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2330 | struct ixgbe_ring *ring; | |
2331 | int per_ring_budget; | |
2332 | bool clean_complete = true; | |
2333 | ||
2334 | #ifdef CONFIG_IXGBE_DCA | |
2335 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2336 | ixgbe_update_dca(q_vector); | |
2337 | #endif | |
2338 | ||
2339 | ixgbe_for_each_ring(ring, q_vector->tx) | |
2340 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); | |
2341 | ||
2342 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2343 | * the budget to go below 1 because we'll exit polling */ | |
2344 | if (q_vector->rx.count > 1) | |
2345 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2346 | else | |
2347 | per_ring_budget = budget; | |
2348 | ||
2349 | ixgbe_for_each_ring(ring, q_vector->rx) | |
2350 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, | |
2351 | per_ring_budget); | |
2352 | ||
2353 | /* If all work not completed, return budget and keep polling */ | |
2354 | if (!clean_complete) | |
2355 | return budget; | |
2356 | ||
2357 | /* all work done, exit the polling mode */ | |
2358 | napi_complete(napi); | |
2359 | if (adapter->rx_itr_setting & 1) | |
2360 | ixgbe_set_itr(q_vector); | |
2361 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2362 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2363 | ||
2364 | return 0; | |
2365 | } | |
2366 | ||
021230d4 AV |
2367 | /** |
2368 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2369 | * @adapter: board private structure | |
2370 | * | |
2371 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2372 | * interrupts from the kernel. | |
2373 | **/ | |
2374 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2375 | { | |
2376 | struct net_device *netdev = adapter->netdev; | |
207867f5 AD |
2377 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2378 | int vector, err; | |
e8e9f696 | 2379 | int ri = 0, ti = 0; |
021230d4 | 2380 | |
021230d4 | 2381 | for (vector = 0; vector < q_vectors; vector++) { |
d0759ebb | 2382 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2383 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2384 | |
4ff7fb12 | 2385 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2386 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2387 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2388 | ti++; | |
2389 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2390 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2391 | "%s-%s-%d", netdev->name, "rx", ri++); |
2392 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2393 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2394 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2395 | } else { |
2396 | /* skip this unused q_vector */ | |
2397 | continue; | |
32aa77a4 | 2398 | } |
207867f5 AD |
2399 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2400 | q_vector->name, q_vector); | |
9a799d71 | 2401 | if (err) { |
396e799c | 2402 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2403 | "Error: %d\n", err); |
021230d4 | 2404 | goto free_queue_irqs; |
9a799d71 | 2405 | } |
207867f5 AD |
2406 | /* If Flow Director is enabled, set interrupt affinity */ |
2407 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2408 | /* assign the mask for this irq */ | |
2409 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2410 | &q_vector->affinity_mask); |
207867f5 | 2411 | } |
9a799d71 AK |
2412 | } |
2413 | ||
021230d4 | 2414 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2415 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2416 | if (err) { |
de88eeeb | 2417 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2418 | goto free_queue_irqs; |
9a799d71 AK |
2419 | } |
2420 | ||
9a799d71 AK |
2421 | return 0; |
2422 | ||
021230d4 | 2423 | free_queue_irqs: |
207867f5 AD |
2424 | while (vector) { |
2425 | vector--; | |
2426 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2427 | NULL); | |
2428 | free_irq(adapter->msix_entries[vector].vector, | |
2429 | adapter->q_vector[vector]); | |
2430 | } | |
021230d4 AV |
2431 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2432 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2433 | kfree(adapter->msix_entries); |
2434 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2435 | return err; |
2436 | } | |
2437 | ||
2438 | /** | |
021230d4 | 2439 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2440 | * @irq: interrupt number |
2441 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2442 | **/ |
2443 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2444 | { | |
a65151ba | 2445 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2446 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2447 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2448 | u32 eicr; |
2449 | ||
54037505 | 2450 | /* |
24ddd967 | 2451 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2452 | * before the read of EICR. |
2453 | */ | |
2454 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2455 | ||
021230d4 | 2456 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2457 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2458 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2459 | if (!eicr) { |
6af3b9eb ET |
2460 | /* |
2461 | * shared interrupt alert! | |
f47cf66e | 2462 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2463 | * have disabled interrupts due to EIAM |
2464 | * finish the workaround of silicon errata on 82598. Unmask | |
2465 | * the interrupt that we masked before the EICR read. | |
2466 | */ | |
2467 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2468 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2469 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2470 | } |
9a799d71 | 2471 | |
cf8280ee JB |
2472 | if (eicr & IXGBE_EICR_LSC) |
2473 | ixgbe_check_lsc(adapter); | |
021230d4 | 2474 | |
bd508178 AD |
2475 | switch (hw->mac.type) { |
2476 | case ixgbe_mac_82599EB: | |
e8e26350 | 2477 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2478 | /* Fall through */ |
2479 | case ixgbe_mac_X540: | |
2480 | if (eicr & IXGBE_EICR_ECC) | |
2481 | e_info(link, "Received unrecoverable ECC err, please " | |
2482 | "reboot\n"); | |
4f51bf70 | 2483 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2484 | break; |
2485 | default: | |
2486 | break; | |
2487 | } | |
e8e26350 | 2488 | |
0befdb3e JB |
2489 | ixgbe_check_fan_failure(adapter, eicr); |
2490 | ||
b9f6ed2b AD |
2491 | /* would disable interrupts here but EIAM disabled it */ |
2492 | napi_schedule(&q_vector->napi); | |
9a799d71 | 2493 | |
6af3b9eb ET |
2494 | /* |
2495 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2496 | * ixgbe_poll will re-enable the queue interrupts | |
2497 | */ | |
6af3b9eb ET |
2498 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2499 | ixgbe_irq_enable(adapter, false, false); | |
2500 | ||
9a799d71 AK |
2501 | return IRQ_HANDLED; |
2502 | } | |
2503 | ||
2504 | /** | |
2505 | * ixgbe_request_irq - initialize interrupts | |
2506 | * @adapter: board private structure | |
2507 | * | |
2508 | * Attempts to configure interrupts using the best available | |
2509 | * capabilities of the hardware and kernel. | |
2510 | **/ | |
021230d4 | 2511 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2512 | { |
2513 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2514 | int err; |
9a799d71 | 2515 | |
4cc6df29 | 2516 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2517 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2518 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2519 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2520 | netdev->name, adapter); |
4cc6df29 | 2521 | else |
a0607fd3 | 2522 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2523 | netdev->name, adapter); |
9a799d71 | 2524 | |
de88eeeb | 2525 | if (err) |
396e799c | 2526 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2527 | |
9a799d71 AK |
2528 | return err; |
2529 | } | |
2530 | ||
2531 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2532 | { | |
9a799d71 | 2533 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
021230d4 | 2534 | int i, q_vectors; |
9a799d71 | 2535 | |
021230d4 | 2536 | q_vectors = adapter->num_msix_vectors; |
021230d4 | 2537 | i = q_vectors - 1; |
a65151ba | 2538 | free_irq(adapter->msix_entries[i].vector, adapter); |
021230d4 | 2539 | i--; |
4cc6df29 | 2540 | |
021230d4 | 2541 | for (; i >= 0; i--) { |
894ff7cf | 2542 | /* free only the irqs that were actually requested */ |
4ff7fb12 AD |
2543 | if (!adapter->q_vector[i]->rx.ring && |
2544 | !adapter->q_vector[i]->tx.ring) | |
894ff7cf AD |
2545 | continue; |
2546 | ||
207867f5 AD |
2547 | /* clear the affinity_mask in the IRQ descriptor */ |
2548 | irq_set_affinity_hint(adapter->msix_entries[i].vector, | |
2549 | NULL); | |
2550 | ||
021230d4 | 2551 | free_irq(adapter->msix_entries[i].vector, |
e8e9f696 | 2552 | adapter->q_vector[i]); |
021230d4 | 2553 | } |
021230d4 | 2554 | } else { |
a65151ba | 2555 | free_irq(adapter->pdev->irq, adapter); |
9a799d71 AK |
2556 | } |
2557 | } | |
2558 | ||
22d5a71b JB |
2559 | /** |
2560 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2561 | * @adapter: board private structure | |
2562 | **/ | |
2563 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2564 | { | |
bd508178 AD |
2565 | switch (adapter->hw.mac.type) { |
2566 | case ixgbe_mac_82598EB: | |
835462fc | 2567 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2568 | break; |
2569 | case ixgbe_mac_82599EB: | |
b93a2226 | 2570 | case ixgbe_mac_X540: |
835462fc NS |
2571 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2572 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2573 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2574 | break; |
2575 | default: | |
2576 | break; | |
22d5a71b JB |
2577 | } |
2578 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2579 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2580 | int i; | |
2581 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2582 | synchronize_irq(adapter->msix_entries[i].vector); | |
2583 | } else { | |
2584 | synchronize_irq(adapter->pdev->irq); | |
2585 | } | |
2586 | } | |
2587 | ||
9a799d71 AK |
2588 | /** |
2589 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2590 | * | |
2591 | **/ | |
2592 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2593 | { | |
d5bf4f67 | 2594 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 2595 | |
d5bf4f67 ET |
2596 | /* rx/tx vector */ |
2597 | if (adapter->rx_itr_setting == 1) | |
2598 | q_vector->itr = IXGBE_20K_ITR; | |
2599 | else | |
2600 | q_vector->itr = adapter->rx_itr_setting; | |
2601 | ||
2602 | ixgbe_write_eitr(q_vector); | |
9a799d71 | 2603 | |
e8e26350 PW |
2604 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2605 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2606 | |
396e799c | 2607 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2608 | } |
2609 | ||
43e69bf0 AD |
2610 | /** |
2611 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2612 | * @adapter: board private structure | |
2613 | * @ring: structure containing ring specific data | |
2614 | * | |
2615 | * Configure the Tx descriptor ring after a reset. | |
2616 | **/ | |
84418e3b AD |
2617 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2618 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2619 | { |
2620 | struct ixgbe_hw *hw = &adapter->hw; | |
2621 | u64 tdba = ring->dma; | |
2f1860b8 | 2622 | int wait_loop = 10; |
b88c6de2 | 2623 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2624 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2625 | |
2f1860b8 | 2626 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2627 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2628 | IXGBE_WRITE_FLUSH(hw); |
2629 | ||
43e69bf0 | 2630 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2631 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2632 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2633 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2634 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2635 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2636 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2637 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2638 | |
b88c6de2 AD |
2639 | /* |
2640 | * set WTHRESH to encourage burst writeback, it should not be set | |
2641 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2642 | * | |
2643 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2644 | * to or less than the number of on chip descriptors, which is | |
2645 | * currently 40. | |
2646 | */ | |
e954b374 | 2647 | if (!ring->q_vector || (ring->q_vector->itr < 8)) |
b88c6de2 AD |
2648 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
2649 | else | |
2650 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2651 | ||
e954b374 AD |
2652 | /* |
2653 | * Setting PTHRESH to 32 both improves performance | |
2654 | * and avoids a TX hang with DFP enabled | |
2655 | */ | |
b88c6de2 AD |
2656 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
2657 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2658 | |
2659 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2660 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2661 | adapter->atr_sample_rate) { | |
2662 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2663 | ring->atr_count = 0; | |
2664 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2665 | } else { | |
2666 | ring->atr_sample_rate = 0; | |
2667 | } | |
2f1860b8 | 2668 | |
c84d324c JF |
2669 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2670 | ||
2f1860b8 | 2671 | /* enable queue */ |
2f1860b8 AD |
2672 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2673 | ||
b2d96e0a AD |
2674 | netdev_tx_reset_queue(txring_txq(ring)); |
2675 | ||
2f1860b8 AD |
2676 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ |
2677 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2678 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2679 | return; | |
2680 | ||
2681 | /* poll to verify queue is enabled */ | |
2682 | do { | |
032b4325 | 2683 | usleep_range(1000, 2000); |
2f1860b8 AD |
2684 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2685 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2686 | if (!wait_loop) | |
2687 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2688 | } |
2689 | ||
120ff942 AD |
2690 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2691 | { | |
2692 | struct ixgbe_hw *hw = &adapter->hw; | |
2693 | u32 rttdcs; | |
72a32f1f | 2694 | u32 reg; |
8b1c0b24 | 2695 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2696 | |
2697 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2698 | return; | |
2699 | ||
2700 | /* disable the arbiter while setting MTQC */ | |
2701 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2702 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2703 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2704 | ||
2705 | /* set transmit pool layout */ | |
8b1c0b24 | 2706 | switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
120ff942 AD |
2707 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2708 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2709 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2710 | break; | |
8b1c0b24 JF |
2711 | default: |
2712 | if (!tcs) | |
2713 | reg = IXGBE_MTQC_64Q_1PB; | |
2714 | else if (tcs <= 4) | |
2715 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2716 | else | |
2717 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
120ff942 | 2718 | |
8b1c0b24 | 2719 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); |
120ff942 | 2720 | |
8b1c0b24 JF |
2721 | /* Enable Security TX Buffer IFG for multiple pb */ |
2722 | if (tcs) { | |
2723 | reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2724 | reg |= IXGBE_SECTX_DCB; | |
2725 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); | |
2726 | } | |
120ff942 AD |
2727 | break; |
2728 | } | |
2729 | ||
2730 | /* re-enable the arbiter */ | |
2731 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2732 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2733 | } | |
2734 | ||
9a799d71 | 2735 | /** |
3a581073 | 2736 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2737 | * @adapter: board private structure |
2738 | * | |
2739 | * Configure the Tx unit of the MAC after a reset. | |
2740 | **/ | |
2741 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2742 | { | |
2f1860b8 AD |
2743 | struct ixgbe_hw *hw = &adapter->hw; |
2744 | u32 dmatxctl; | |
43e69bf0 | 2745 | u32 i; |
9a799d71 | 2746 | |
2f1860b8 AD |
2747 | ixgbe_setup_mtqc(adapter); |
2748 | ||
2749 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2750 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2751 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2752 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2753 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2754 | } | |
2755 | ||
9a799d71 | 2756 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2757 | for (i = 0; i < adapter->num_tx_queues; i++) |
2758 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2759 | } |
2760 | ||
e8e26350 | 2761 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2762 | |
a6616b42 | 2763 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2764 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2765 | { |
cc41ac7c | 2766 | u32 srrctl; |
bf29ee6c | 2767 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2768 | |
bd508178 AD |
2769 | switch (adapter->hw.mac.type) { |
2770 | case ixgbe_mac_82598EB: { | |
2771 | struct ixgbe_ring_feature *feature = adapter->ring_feature; | |
2772 | const int mask = feature[RING_F_RSS].mask; | |
bf29ee6c | 2773 | reg_idx = reg_idx & mask; |
cc41ac7c | 2774 | } |
bd508178 AD |
2775 | break; |
2776 | case ixgbe_mac_82599EB: | |
b93a2226 | 2777 | case ixgbe_mac_X540: |
bd508178 AD |
2778 | default: |
2779 | break; | |
2780 | } | |
2781 | ||
bf29ee6c | 2782 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx)); |
cc41ac7c JB |
2783 | |
2784 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2785 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2786 | if (adapter->num_vfs) |
2787 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2788 | |
afafd5b0 AD |
2789 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2790 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2791 | ||
f800326d AD |
2792 | #if PAGE_SIZE > IXGBE_MAX_RXBUFFER |
2793 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
afafd5b0 | 2794 | #else |
f800326d | 2795 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
afafd5b0 | 2796 | #endif |
f800326d | 2797 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 2798 | |
bf29ee6c | 2799 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2800 | } |
9a799d71 | 2801 | |
05abb126 | 2802 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2803 | { |
05abb126 AD |
2804 | struct ixgbe_hw *hw = &adapter->hw; |
2805 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2806 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2807 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2808 | u32 mrqc = 0, reta = 0; |
2809 | u32 rxcsum; | |
2810 | int i, j; | |
8b1c0b24 | 2811 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
86b4db3b JF |
2812 | int maxq = adapter->ring_feature[RING_F_RSS].indices; |
2813 | ||
2814 | if (tcs) | |
2815 | maxq = min(maxq, adapter->num_tx_queues / tcs); | |
0cefafad | 2816 | |
05abb126 AD |
2817 | /* Fill out hash function seeds */ |
2818 | for (i = 0; i < 10; i++) | |
2819 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2820 | ||
2821 | /* Fill out redirection table */ | |
2822 | for (i = 0, j = 0; i < 128; i++, j++) { | |
86b4db3b | 2823 | if (j == maxq) |
05abb126 AD |
2824 | j = 0; |
2825 | /* reta = 4-byte sliding window of | |
2826 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2827 | reta = (reta << 8) | (j * 0x11); | |
2828 | if ((i & 3) == 3) | |
2829 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2830 | } | |
0cefafad | 2831 | |
05abb126 AD |
2832 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2833 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2834 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2835 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2836 | ||
8b1c0b24 JF |
2837 | if (adapter->hw.mac.type == ixgbe_mac_82598EB && |
2838 | (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { | |
0cefafad | 2839 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 JF |
2840 | } else { |
2841 | int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2842 | | IXGBE_FLAG_SRIOV_ENABLED); | |
2843 | ||
2844 | switch (mask) { | |
2845 | case (IXGBE_FLAG_RSS_ENABLED): | |
2846 | if (!tcs) | |
2847 | mrqc = IXGBE_MRQC_RSSEN; | |
2848 | else if (tcs <= 4) | |
2849 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
2850 | else | |
2851 | mrqc = IXGBE_MRQC_RTRSS8TCEN; | |
2852 | break; | |
2853 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2854 | mrqc = IXGBE_MRQC_VMDQEN; | |
2855 | break; | |
2856 | default: | |
2857 | break; | |
2858 | } | |
0cefafad JB |
2859 | } |
2860 | ||
05abb126 AD |
2861 | /* Perform hash on these packet types */ |
2862 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2863 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2864 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2865 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2866 | ||
ef6afc0c AD |
2867 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
2868 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; | |
2869 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) | |
2870 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
2871 | ||
05abb126 | 2872 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
0cefafad JB |
2873 | } |
2874 | ||
bb5a9ad2 NS |
2875 | /** |
2876 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2877 | * @adapter: address of board private structure | |
2878 | * @index: index of ring to set | |
bb5a9ad2 | 2879 | **/ |
082757af | 2880 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2881 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2882 | { |
bb5a9ad2 | 2883 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2884 | u32 rscctrl; |
bf29ee6c | 2885 | u8 reg_idx = ring->reg_idx; |
7367096a | 2886 | |
7d637bcc | 2887 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2888 | return; |
bb5a9ad2 | 2889 | |
7367096a | 2890 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
2891 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2892 | /* | |
2893 | * we must limit the number of descriptors so that the | |
2894 | * total size of max desc * buf_len is not greater | |
642c680e | 2895 | * than 65536 |
bb5a9ad2 | 2896 | */ |
f800326d AD |
2897 | #if (PAGE_SIZE <= 8192) |
2898 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2899 | #elif (PAGE_SIZE <= 16384) | |
2900 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
bb5a9ad2 | 2901 | #else |
f800326d | 2902 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; |
bb5a9ad2 | 2903 | #endif |
7367096a | 2904 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2905 | } |
2906 | ||
9e10e045 AD |
2907 | /** |
2908 | * ixgbe_set_uta - Set unicast filter table address | |
2909 | * @adapter: board private structure | |
2910 | * | |
2911 | * The unicast table address is a register array of 32-bit registers. | |
2912 | * The table is meant to be used in a way similar to how the MTA is used | |
2913 | * however due to certain limitations in the hardware it is necessary to | |
2914 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous | |
2915 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
2916 | **/ | |
2917 | static void ixgbe_set_uta(struct ixgbe_adapter *adapter) | |
2918 | { | |
2919 | struct ixgbe_hw *hw = &adapter->hw; | |
2920 | int i; | |
2921 | ||
2922 | /* The UTA table only exists on 82599 hardware and newer */ | |
2923 | if (hw->mac.type < ixgbe_mac_82599EB) | |
2924 | return; | |
2925 | ||
2926 | /* we only need to do this if VMDq is enabled */ | |
2927 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2928 | return; | |
2929 | ||
2930 | for (i = 0; i < 128; i++) | |
2931 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); | |
2932 | } | |
2933 | ||
2934 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
2935 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2936 | struct ixgbe_ring *ring) | |
2937 | { | |
2938 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
2939 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
2940 | u32 rxdctl; | |
bf29ee6c | 2941 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
2942 | |
2943 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2944 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2945 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2946 | return; | |
2947 | ||
2948 | do { | |
032b4325 | 2949 | usleep_range(1000, 2000); |
9e10e045 AD |
2950 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
2951 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2952 | ||
2953 | if (!wait_loop) { | |
2954 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
2955 | "the polling period\n", reg_idx); | |
2956 | } | |
2957 | } | |
2958 | ||
2d39d576 YZ |
2959 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
2960 | struct ixgbe_ring *ring) | |
2961 | { | |
2962 | struct ixgbe_hw *hw = &adapter->hw; | |
2963 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
2964 | u32 rxdctl; | |
2965 | u8 reg_idx = ring->reg_idx; | |
2966 | ||
2967 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2968 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
2969 | ||
2970 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
2971 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
2972 | ||
2973 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2974 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2975 | return; | |
2976 | ||
2977 | /* the hardware may take up to 100us to really disable the rx queue */ | |
2978 | do { | |
2979 | udelay(10); | |
2980 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2981 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2982 | ||
2983 | if (!wait_loop) { | |
2984 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
2985 | "the polling period\n", reg_idx); | |
2986 | } | |
2987 | } | |
2988 | ||
84418e3b AD |
2989 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
2990 | struct ixgbe_ring *ring) | |
acd37177 AD |
2991 | { |
2992 | struct ixgbe_hw *hw = &adapter->hw; | |
2993 | u64 rdba = ring->dma; | |
9e10e045 | 2994 | u32 rxdctl; |
bf29ee6c | 2995 | u8 reg_idx = ring->reg_idx; |
acd37177 | 2996 | |
9e10e045 AD |
2997 | /* disable queue to avoid issues while updating state */ |
2998 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 2999 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3000 | |
acd37177 AD |
3001 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3002 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3003 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3004 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
3005 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
3006 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 3007 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3008 | |
3009 | ixgbe_configure_srrctl(adapter, ring); | |
3010 | ixgbe_configure_rscctl(adapter, ring); | |
3011 | ||
e9f98072 GR |
3012 | /* If operating in IOV mode set RLPML for X540 */ |
3013 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
3014 | hw->mac.type == ixgbe_mac_X540) { | |
3015 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
3016 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
3017 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
3018 | } | |
3019 | ||
9e10e045 AD |
3020 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3021 | /* | |
3022 | * enable cache line friendly hardware writes: | |
3023 | * PTHRESH=32 descriptors (half the internal cache), | |
3024 | * this also removes ugly rx_no_buffer_count increment | |
3025 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3026 | * WTHRESH=8 burst writeback up to two cache lines | |
3027 | */ | |
3028 | rxdctl &= ~0x3FFFFF; | |
3029 | rxdctl |= 0x080420; | |
3030 | } | |
3031 | ||
3032 | /* enable receive descriptor ring */ | |
3033 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3034 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3035 | ||
3036 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3037 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3038 | } |
3039 | ||
48654521 AD |
3040 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3041 | { | |
3042 | struct ixgbe_hw *hw = &adapter->hw; | |
3043 | int p; | |
3044 | ||
3045 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3046 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3047 | IXGBE_PSRTYPE_UDPHDR | |
3048 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3049 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3050 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3051 | |
3052 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3053 | return; | |
3054 | ||
3055 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
3056 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
3057 | ||
3058 | for (p = 0; p < adapter->num_rx_pools; p++) | |
3059 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
3060 | psrtype); | |
3061 | } | |
3062 | ||
f5b4a52e AD |
3063 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3064 | { | |
3065 | struct ixgbe_hw *hw = &adapter->hw; | |
3066 | u32 gcr_ext; | |
3067 | u32 vt_reg_bits; | |
3068 | u32 reg_offset, vf_shift; | |
3069 | u32 vmdctl; | |
de4c7f65 | 3070 | int i; |
f5b4a52e AD |
3071 | |
3072 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3073 | return; | |
3074 | ||
3075 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
3076 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
3077 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
3078 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
3079 | ||
3080 | vf_shift = adapter->num_vfs % 32; | |
4cd6923d | 3081 | reg_offset = (adapter->num_vfs >= 32) ? 1 : 0; |
f5b4a52e AD |
3082 | |
3083 | /* Enable only the PF's pool for Tx/Rx */ | |
3084 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
3085 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
3086 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
3087 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
3088 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
3089 | ||
3090 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3091 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3092 | ||
3093 | /* | |
3094 | * Set up VF register offsets for selected VT Mode, | |
3095 | * i.e. 32 or 64 VFs for SR-IOV | |
3096 | */ | |
3097 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3098 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
3099 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
3100 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3101 | ||
3102 | /* enable Tx loopback for VF/PF communication */ | |
3103 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 | 3104 | /* Enable MAC Anti-Spoofing */ |
a1cbb15c | 3105 | hw->mac.ops.set_mac_anti_spoofing(hw, |
de4c7f65 | 3106 | (adapter->num_vfs != 0), |
a985b6c3 | 3107 | adapter->num_vfs); |
de4c7f65 GR |
3108 | /* For VFs that have spoof checking turned off */ |
3109 | for (i = 0; i < adapter->num_vfs; i++) { | |
3110 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3111 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
3112 | } | |
f5b4a52e AD |
3113 | } |
3114 | ||
477de6ed | 3115 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3116 | { |
9a799d71 AK |
3117 | struct ixgbe_hw *hw = &adapter->hw; |
3118 | struct net_device *netdev = adapter->netdev; | |
3119 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3120 | struct ixgbe_ring *rx_ring; |
3121 | int i; | |
3122 | u32 mhadd, hlreg0; | |
48654521 | 3123 | |
63f39bd1 | 3124 | #ifdef IXGBE_FCOE |
477de6ed AD |
3125 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3126 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3127 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3128 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3129 | |
477de6ed AD |
3130 | #endif /* IXGBE_FCOE */ |
3131 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3132 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3133 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3134 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3135 | ||
3136 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3137 | } | |
3138 | ||
919e78a6 AD |
3139 | /* MHADD will allow an extra 4 bytes past for vlan tagged frames */ |
3140 | max_frame += VLAN_HLEN; | |
3141 | ||
477de6ed AD |
3142 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
3143 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3144 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3145 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3146 | |
0cefafad JB |
3147 | /* |
3148 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3149 | * the Base and Length of the Rx Descriptor Ring | |
3150 | */ | |
9a799d71 | 3151 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3152 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3153 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3154 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3155 | else |
7d637bcc | 3156 | clear_ring_rsc_enabled(rx_ring); |
63f39bd1 | 3157 | #ifdef IXGBE_FCOE |
e8e9f696 | 3158 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
3159 | struct ixgbe_ring_feature *f; |
3160 | f = &adapter->ring_feature[RING_F_FCOE]; | |
f800326d AD |
3161 | if ((i >= f->mask) && (i < f->mask + f->indices)) |
3162 | set_bit(__IXGBE_RX_FCOE_BUFSZ, &rx_ring->state); | |
63f39bd1 | 3163 | } |
63f39bd1 | 3164 | #endif /* IXGBE_FCOE */ |
477de6ed | 3165 | } |
477de6ed AD |
3166 | } |
3167 | ||
7367096a AD |
3168 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3169 | { | |
3170 | struct ixgbe_hw *hw = &adapter->hw; | |
3171 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3172 | ||
3173 | switch (hw->mac.type) { | |
3174 | case ixgbe_mac_82598EB: | |
3175 | /* | |
3176 | * For VMDq support of different descriptor types or | |
3177 | * buffer sizes through the use of multiple SRRCTL | |
3178 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3179 | * | |
3180 | * also, the manual doesn't mention it clearly but DCA hints | |
3181 | * will only use queue 0's tags unless this bit is set. Side | |
3182 | * effects of setting this bit are only that SRRCTL must be | |
3183 | * fully programmed [0..15] | |
3184 | */ | |
3185 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3186 | break; | |
3187 | case ixgbe_mac_82599EB: | |
b93a2226 | 3188 | case ixgbe_mac_X540: |
7367096a AD |
3189 | /* Disable RSC for ACK packets */ |
3190 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3191 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3192 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3193 | /* hardware requires some bits to be set by default */ | |
3194 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3195 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3196 | break; | |
3197 | default: | |
3198 | /* We should do nothing since we don't know this hardware */ | |
3199 | return; | |
3200 | } | |
3201 | ||
3202 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3203 | } | |
3204 | ||
477de6ed AD |
3205 | /** |
3206 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3207 | * @adapter: board private structure | |
3208 | * | |
3209 | * Configure the Rx unit of the MAC after a reset. | |
3210 | **/ | |
3211 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3212 | { | |
3213 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3214 | int i; |
3215 | u32 rxctrl; | |
477de6ed AD |
3216 | |
3217 | /* disable receives while setting up the descriptors */ | |
3218 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3219 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3220 | ||
3221 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3222 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3223 | |
9e10e045 | 3224 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3225 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3226 | |
9e10e045 AD |
3227 | ixgbe_set_uta(adapter); |
3228 | ||
477de6ed AD |
3229 | /* set_rx_buffer_len must be called before ring initialization */ |
3230 | ixgbe_set_rx_buffer_len(adapter); | |
3231 | ||
3232 | /* | |
3233 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3234 | * the Base and Length of the Rx Descriptor Ring | |
3235 | */ | |
9e10e045 AD |
3236 | for (i = 0; i < adapter->num_rx_queues; i++) |
3237 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3238 | |
9e10e045 AD |
3239 | /* disable drop enable for 82598 parts */ |
3240 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3241 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3242 | ||
3243 | /* enable all receives */ | |
3244 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3245 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3246 | } |
3247 | ||
8e586137 | 3248 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3249 | { |
3250 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3251 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3252 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3253 | |
3254 | /* add VID to filter table */ | |
1ada1b1b | 3255 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3256 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3257 | |
3258 | return 0; | |
068c89b0 DS |
3259 | } |
3260 | ||
8e586137 | 3261 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3262 | { |
3263 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3264 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3265 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3266 | |
068c89b0 | 3267 | /* remove VID from filter table */ |
1ada1b1b | 3268 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3269 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3270 | |
3271 | return 0; | |
068c89b0 DS |
3272 | } |
3273 | ||
5f6c0181 JB |
3274 | /** |
3275 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3276 | * @adapter: driver data | |
3277 | */ | |
3278 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3279 | { | |
3280 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3281 | u32 vlnctrl; |
3282 | ||
3283 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3284 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3285 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3286 | } | |
3287 | ||
3288 | /** | |
3289 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3290 | * @adapter: driver data | |
3291 | */ | |
3292 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3293 | { | |
3294 | struct ixgbe_hw *hw = &adapter->hw; | |
3295 | u32 vlnctrl; | |
3296 | ||
3297 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3298 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3299 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3300 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3301 | } | |
3302 | ||
3303 | /** | |
3304 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3305 | * @adapter: driver data | |
3306 | */ | |
3307 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3308 | { | |
3309 | struct ixgbe_hw *hw = &adapter->hw; | |
3310 | u32 vlnctrl; | |
5f6c0181 JB |
3311 | int i, j; |
3312 | ||
3313 | switch (hw->mac.type) { | |
3314 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3315 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3316 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3317 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3318 | break; | |
3319 | case ixgbe_mac_82599EB: | |
b93a2226 | 3320 | case ixgbe_mac_X540: |
5f6c0181 JB |
3321 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3322 | j = adapter->rx_ring[i]->reg_idx; | |
3323 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3324 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3325 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3326 | } | |
3327 | break; | |
3328 | default: | |
3329 | break; | |
3330 | } | |
3331 | } | |
3332 | ||
3333 | /** | |
f62bbb5e | 3334 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3335 | * @adapter: driver data |
3336 | */ | |
f62bbb5e | 3337 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3338 | { |
3339 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3340 | u32 vlnctrl; |
5f6c0181 JB |
3341 | int i, j; |
3342 | ||
3343 | switch (hw->mac.type) { | |
3344 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3345 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3346 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3347 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3348 | break; | |
3349 | case ixgbe_mac_82599EB: | |
b93a2226 | 3350 | case ixgbe_mac_X540: |
5f6c0181 JB |
3351 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3352 | j = adapter->rx_ring[i]->reg_idx; | |
3353 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3354 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3355 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3356 | } | |
3357 | break; | |
3358 | default: | |
3359 | break; | |
3360 | } | |
3361 | } | |
3362 | ||
9a799d71 AK |
3363 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3364 | { | |
f62bbb5e | 3365 | u16 vid; |
9a799d71 | 3366 | |
f62bbb5e JG |
3367 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3368 | ||
3369 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3370 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3371 | } |
3372 | ||
2850062a AD |
3373 | /** |
3374 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3375 | * @netdev: network interface device structure | |
3376 | * | |
3377 | * Writes unicast address list to the RAR table. | |
3378 | * Returns: -ENOMEM on failure/insufficient address space | |
3379 | * 0 on no addresses written | |
3380 | * X on writing X addresses to the RAR table | |
3381 | **/ | |
3382 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3383 | { | |
3384 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3385 | struct ixgbe_hw *hw = &adapter->hw; | |
3386 | unsigned int vfn = adapter->num_vfs; | |
a1cbb15c | 3387 | unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS; |
2850062a AD |
3388 | int count = 0; |
3389 | ||
3390 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3391 | if (netdev_uc_count(netdev) > rar_entries) | |
3392 | return -ENOMEM; | |
3393 | ||
3394 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3395 | struct netdev_hw_addr *ha; | |
3396 | /* return error if we do not support writing to RAR table */ | |
3397 | if (!hw->mac.ops.set_rar) | |
3398 | return -ENOMEM; | |
3399 | ||
3400 | netdev_for_each_uc_addr(ha, netdev) { | |
3401 | if (!rar_entries) | |
3402 | break; | |
3403 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3404 | vfn, IXGBE_RAH_AV); | |
3405 | count++; | |
3406 | } | |
3407 | } | |
3408 | /* write the addresses in reverse order to avoid write combining */ | |
3409 | for (; rar_entries > 0 ; rar_entries--) | |
3410 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3411 | ||
3412 | return count; | |
3413 | } | |
3414 | ||
9a799d71 | 3415 | /** |
2c5645cf | 3416 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3417 | * @netdev: network interface device structure |
3418 | * | |
2c5645cf CL |
3419 | * The set_rx_method entry point is called whenever the unicast/multicast |
3420 | * address list or the network interface flags are updated. This routine is | |
3421 | * responsible for configuring the hardware for proper unicast, multicast and | |
3422 | * promiscuous mode. | |
9a799d71 | 3423 | **/ |
7f870475 | 3424 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3425 | { |
3426 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3427 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3428 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3429 | int count; | |
9a799d71 AK |
3430 | |
3431 | /* Check for Promiscuous and All Multicast modes */ | |
3432 | ||
3433 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3434 | ||
f5dc442b | 3435 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 3436 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
3437 | fctrl |= IXGBE_FCTRL_BAM; |
3438 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3439 | fctrl |= IXGBE_FCTRL_PMCF; | |
3440 | ||
2850062a AD |
3441 | /* clear the bits we are changing the status of */ |
3442 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3443 | ||
9a799d71 | 3444 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3445 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3446 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3447 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3448 | /* don't hardware filter vlans in promisc mode */ |
3449 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3450 | } else { |
746b9f02 PM |
3451 | if (netdev->flags & IFF_ALLMULTI) { |
3452 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3453 | vmolr |= IXGBE_VMOLR_MPE; |
3454 | } else { | |
3455 | /* | |
3456 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3457 | * then we should just turn on promiscuous mode so |
2850062a AD |
3458 | * that we can at least receive multicast traffic |
3459 | */ | |
3460 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3461 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3462 | } |
5f6c0181 | 3463 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3464 | hw->addr_ctrl.user_set_promisc = false; |
2850062a AD |
3465 | /* |
3466 | * Write addresses to available RAR registers, if there is not | |
3467 | * sufficient space to store all the addresses then enable | |
25985edc | 3468 | * unicast promiscuous mode |
2850062a AD |
3469 | */ |
3470 | count = ixgbe_write_uc_addr_list(netdev); | |
3471 | if (count < 0) { | |
3472 | fctrl |= IXGBE_FCTRL_UPE; | |
3473 | vmolr |= IXGBE_VMOLR_ROPE; | |
3474 | } | |
9a799d71 AK |
3475 | } |
3476 | ||
2850062a | 3477 | if (adapter->num_vfs) { |
1cdd1ec8 | 3478 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3479 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3480 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3481 | IXGBE_VMOLR_ROPE); | |
3482 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3483 | } | |
3484 | ||
3f2d1c0f BG |
3485 | /* This is useful for sniffing bad packets. */ |
3486 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3487 | /* UPE and MPE will be handled by normal PROMISC logic | |
3488 | * in e1000e_set_rx_mode */ | |
3489 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
3490 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
3491 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3492 | ||
3493 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
3494 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
3495 | } | |
3496 | ||
2850062a | 3497 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e JG |
3498 | |
3499 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3500 | ixgbe_vlan_strip_enable(adapter); | |
3501 | else | |
3502 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3503 | } |
3504 | ||
021230d4 AV |
3505 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3506 | { | |
3507 | int q_idx; | |
3508 | struct ixgbe_q_vector *q_vector; | |
3509 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3510 | ||
3511 | /* legacy and MSI only use one vector */ | |
3512 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3513 | q_vectors = 1; | |
3514 | ||
3515 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3516 | q_vector = adapter->q_vector[q_idx]; |
4ff7fb12 | 3517 | napi_enable(&q_vector->napi); |
021230d4 AV |
3518 | } |
3519 | } | |
3520 | ||
3521 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3522 | { | |
3523 | int q_idx; | |
3524 | struct ixgbe_q_vector *q_vector; | |
3525 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3526 | ||
3527 | /* legacy and MSI only use one vector */ | |
3528 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3529 | q_vectors = 1; | |
3530 | ||
3531 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3532 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3533 | napi_disable(&q_vector->napi); |
3534 | } | |
3535 | } | |
3536 | ||
7a6b6f51 | 3537 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3538 | /* |
3539 | * ixgbe_configure_dcb - Configure DCB hardware | |
3540 | * @adapter: ixgbe adapter struct | |
3541 | * | |
3542 | * This is called by the driver on open to configure the DCB hardware. | |
3543 | * This is also called by the gennetlink interface when reconfiguring | |
3544 | * the DCB state. | |
3545 | */ | |
3546 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3547 | { | |
3548 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3549 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3550 | |
67ebd791 AD |
3551 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3552 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3553 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3554 | return; | |
3555 | } | |
3556 | ||
3557 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3558 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3559 | ||
2f90b865 | 3560 | |
2f90b865 | 3561 | /* Enable VLAN tag insert/strip */ |
f62bbb5e | 3562 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3563 | |
2f90b865 | 3564 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 | 3565 | |
971060b1 | 3566 | #ifdef IXGBE_FCOE |
b120818e JF |
3567 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3568 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 3569 | #endif |
b120818e JF |
3570 | |
3571 | /* reconfigure the hardware */ | |
3572 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
3573 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
3574 | DCB_TX_CONFIG); | |
3575 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3576 | DCB_RX_CONFIG); | |
3577 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
3578 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
3579 | ixgbe_dcb_hw_ets(&adapter->hw, | |
3580 | adapter->ixgbe_ieee_ets, | |
3581 | max_frame); | |
3582 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
3583 | adapter->ixgbe_ieee_pfc->pfc_en, | |
3584 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 3585 | } |
8187cd48 JF |
3586 | |
3587 | /* Enable RSS Hash per TC */ | |
3588 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3589 | int i; | |
3590 | u32 reg = 0; | |
3591 | ||
3592 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
3593 | u8 msb = 0; | |
3594 | u8 cnt = adapter->netdev->tc_to_txq[i].count; | |
3595 | ||
3596 | while (cnt >>= 1) | |
3597 | msb++; | |
3598 | ||
3599 | reg |= msb << IXGBE_RQTC_SHIFT_TC(i); | |
3600 | } | |
3601 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); | |
3602 | } | |
2f90b865 | 3603 | } |
9da712d2 JF |
3604 | #endif |
3605 | ||
3606 | /* Additional bittime to account for IXGBE framing */ | |
3607 | #define IXGBE_ETH_FRAMING 20 | |
3608 | ||
3609 | /* | |
3610 | * ixgbe_hpbthresh - calculate high water mark for flow control | |
3611 | * | |
3612 | * @adapter: board private structure to calculate for | |
3613 | * @pb - packet buffer to calculate | |
3614 | */ | |
3615 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
3616 | { | |
3617 | struct ixgbe_hw *hw = &adapter->hw; | |
3618 | struct net_device *dev = adapter->netdev; | |
3619 | int link, tc, kb, marker; | |
3620 | u32 dv_id, rx_pba; | |
3621 | ||
3622 | /* Calculate max LAN frame size */ | |
3623 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
3624 | ||
3625 | #ifdef IXGBE_FCOE | |
3626 | /* FCoE traffic class uses FCOE jumbo frames */ | |
3627 | if (dev->features & NETIF_F_FCOE_MTU) { | |
3628 | int fcoe_pb = 0; | |
2f90b865 | 3629 | |
9da712d2 JF |
3630 | #ifdef CONFIG_IXGBE_DCB |
3631 | fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up); | |
3632 | ||
3633 | #endif | |
3634 | if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
3635 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
3636 | } | |
2f90b865 | 3637 | #endif |
80605c65 | 3638 | |
9da712d2 JF |
3639 | /* Calculate delay value for device */ |
3640 | switch (hw->mac.type) { | |
3641 | case ixgbe_mac_X540: | |
3642 | dv_id = IXGBE_DV_X540(link, tc); | |
3643 | break; | |
3644 | default: | |
3645 | dv_id = IXGBE_DV(link, tc); | |
3646 | break; | |
3647 | } | |
3648 | ||
3649 | /* Loopback switch introduces additional latency */ | |
3650 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3651 | dv_id += IXGBE_B2BT(tc); | |
3652 | ||
3653 | /* Delay value is calculated in bit times convert to KB */ | |
3654 | kb = IXGBE_BT2KB(dv_id); | |
3655 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
3656 | ||
3657 | marker = rx_pba - kb; | |
3658 | ||
3659 | /* It is possible that the packet buffer is not large enough | |
3660 | * to provide required headroom. In this case throw an error | |
3661 | * to user and a do the best we can. | |
3662 | */ | |
3663 | if (marker < 0) { | |
3664 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
3665 | "headroom to support flow control." | |
3666 | "Decrease MTU or number of traffic classes\n", pb); | |
3667 | marker = tc + 1; | |
3668 | } | |
3669 | ||
3670 | return marker; | |
3671 | } | |
3672 | ||
3673 | /* | |
3674 | * ixgbe_lpbthresh - calculate low water mark for for flow control | |
3675 | * | |
3676 | * @adapter: board private structure to calculate for | |
3677 | * @pb - packet buffer to calculate | |
3678 | */ | |
3679 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) | |
3680 | { | |
3681 | struct ixgbe_hw *hw = &adapter->hw; | |
3682 | struct net_device *dev = adapter->netdev; | |
3683 | int tc; | |
3684 | u32 dv_id; | |
3685 | ||
3686 | /* Calculate max LAN frame size */ | |
3687 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
3688 | ||
3689 | /* Calculate delay value for device */ | |
3690 | switch (hw->mac.type) { | |
3691 | case ixgbe_mac_X540: | |
3692 | dv_id = IXGBE_LOW_DV_X540(tc); | |
3693 | break; | |
3694 | default: | |
3695 | dv_id = IXGBE_LOW_DV(tc); | |
3696 | break; | |
3697 | } | |
3698 | ||
3699 | /* Delay value is calculated in bit times convert to KB */ | |
3700 | return IXGBE_BT2KB(dv_id); | |
3701 | } | |
3702 | ||
3703 | /* | |
3704 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
3705 | */ | |
3706 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
3707 | { | |
3708 | struct ixgbe_hw *hw = &adapter->hw; | |
3709 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3710 | int i; | |
3711 | ||
3712 | if (!num_tc) | |
3713 | num_tc = 1; | |
3714 | ||
3715 | hw->fc.low_water = ixgbe_lpbthresh(adapter); | |
3716 | ||
3717 | for (i = 0; i < num_tc; i++) { | |
3718 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
3719 | ||
3720 | /* Low water marks must not be larger than high water marks */ | |
3721 | if (hw->fc.low_water > hw->fc.high_water[i]) | |
3722 | hw->fc.low_water = 0; | |
3723 | } | |
3724 | } | |
3725 | ||
80605c65 JF |
3726 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
3727 | { | |
80605c65 | 3728 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3729 | int hdrm; |
3730 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3731 | |
3732 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3733 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3734 | hdrm = 32 << adapter->fdir_pballoc; |
3735 | else | |
3736 | hdrm = 0; | |
80605c65 | 3737 | |
f7e1027f | 3738 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 3739 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
3740 | } |
3741 | ||
e4911d57 AD |
3742 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3743 | { | |
3744 | struct ixgbe_hw *hw = &adapter->hw; | |
3745 | struct hlist_node *node, *node2; | |
3746 | struct ixgbe_fdir_filter *filter; | |
3747 | ||
3748 | spin_lock(&adapter->fdir_perfect_lock); | |
3749 | ||
3750 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3751 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3752 | ||
3753 | hlist_for_each_entry_safe(filter, node, node2, | |
3754 | &adapter->fdir_filter_list, fdir_node) { | |
3755 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3756 | &filter->filter, |
3757 | filter->sw_idx, | |
3758 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3759 | IXGBE_FDIR_DROP_QUEUE : | |
3760 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3761 | } |
3762 | ||
3763 | spin_unlock(&adapter->fdir_perfect_lock); | |
3764 | } | |
3765 | ||
9a799d71 AK |
3766 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3767 | { | |
d2f5e7f3 AS |
3768 | struct ixgbe_hw *hw = &adapter->hw; |
3769 | ||
80605c65 | 3770 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3771 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3772 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3773 | #endif |
9a799d71 | 3774 | |
4c1d7b4b | 3775 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3776 | ixgbe_restore_vlan(adapter); |
3777 | ||
eacd73f7 YZ |
3778 | #ifdef IXGBE_FCOE |
3779 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3780 | ixgbe_configure_fcoe(adapter); | |
3781 | ||
3782 | #endif /* IXGBE_FCOE */ | |
d2f5e7f3 AS |
3783 | |
3784 | switch (hw->mac.type) { | |
3785 | case ixgbe_mac_82599EB: | |
3786 | case ixgbe_mac_X540: | |
3787 | hw->mac.ops.disable_rx_buff(hw); | |
3788 | break; | |
3789 | default: | |
3790 | break; | |
3791 | } | |
3792 | ||
c4cf55e5 | 3793 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3794 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3795 | adapter->fdir_pballoc); | |
e4911d57 AD |
3796 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3797 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3798 | adapter->fdir_pballoc); | |
3799 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3800 | } |
4c1d7b4b | 3801 | |
d2f5e7f3 AS |
3802 | switch (hw->mac.type) { |
3803 | case ixgbe_mac_82599EB: | |
3804 | case ixgbe_mac_X540: | |
3805 | hw->mac.ops.enable_rx_buff(hw); | |
3806 | break; | |
3807 | default: | |
3808 | break; | |
3809 | } | |
3810 | ||
933d41f1 | 3811 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3812 | |
9a799d71 AK |
3813 | ixgbe_configure_tx(adapter); |
3814 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3815 | } |
3816 | ||
e8e26350 PW |
3817 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3818 | { | |
3819 | switch (hw->phy.type) { | |
3820 | case ixgbe_phy_sfp_avago: | |
3821 | case ixgbe_phy_sfp_ftl: | |
3822 | case ixgbe_phy_sfp_intel: | |
3823 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3824 | case ixgbe_phy_sfp_passive_tyco: |
3825 | case ixgbe_phy_sfp_passive_unknown: | |
3826 | case ixgbe_phy_sfp_active_unknown: | |
3827 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3828 | return true; |
8917b447 AD |
3829 | case ixgbe_phy_nl: |
3830 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3831 | return true; | |
e8e26350 PW |
3832 | default: |
3833 | return false; | |
3834 | } | |
3835 | } | |
3836 | ||
0ecc061d | 3837 | /** |
e8e26350 PW |
3838 | * ixgbe_sfp_link_config - set up SFP+ link |
3839 | * @adapter: pointer to private adapter struct | |
3840 | **/ | |
3841 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3842 | { | |
7086400d | 3843 | /* |
52f33af8 | 3844 | * We are assuming the worst case scenario here, and that |
7086400d AD |
3845 | * is that an SFP was inserted/removed after the reset |
3846 | * but before SFP detection was enabled. As such the best | |
3847 | * solution is to just start searching as soon as we start | |
3848 | */ | |
3849 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3850 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3851 | |
7086400d | 3852 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3853 | } |
3854 | ||
3855 | /** | |
3856 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3857 | * @hw: pointer to private hardware struct |
3858 | * | |
3859 | * Returns 0 on success, negative on failure | |
3860 | **/ | |
e8e26350 | 3861 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3862 | { |
3863 | u32 autoneg; | |
8620a103 | 3864 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3865 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3866 | ||
3867 | if (hw->mac.ops.check_link) | |
3868 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3869 | ||
3870 | if (ret) | |
3871 | goto link_cfg_out; | |
3872 | ||
0b0c2b31 ET |
3873 | autoneg = hw->phy.autoneg_advertised; |
3874 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3875 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3876 | &negotiation); | |
0ecc061d PWJ |
3877 | if (ret) |
3878 | goto link_cfg_out; | |
3879 | ||
8620a103 MC |
3880 | if (hw->mac.ops.setup_link) |
3881 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3882 | link_cfg_out: |
3883 | return ret; | |
3884 | } | |
3885 | ||
a34bcfff | 3886 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3887 | { |
9a799d71 | 3888 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3889 | u32 gpie = 0; |
9a799d71 | 3890 | |
9b471446 | 3891 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3892 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3893 | IXGBE_GPIE_OCD; | |
3894 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3895 | /* |
3896 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3897 | * this saves a register write for every interrupt | |
3898 | */ | |
3899 | switch (hw->mac.type) { | |
3900 | case ixgbe_mac_82598EB: | |
3901 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3902 | break; | |
9b471446 | 3903 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3904 | case ixgbe_mac_X540: |
3905 | default: | |
9b471446 JB |
3906 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3907 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3908 | break; | |
3909 | } | |
3910 | } else { | |
021230d4 AV |
3911 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3912 | * specifically only auto mask tx and rx interrupts */ | |
3913 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3914 | } | |
9a799d71 | 3915 | |
a34bcfff AD |
3916 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3917 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3918 | ||
3919 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3920 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3921 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3922 | } |
3923 | ||
5fdd31f9 | 3924 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
3925 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
3926 | switch (adapter->hw.mac.type) { | |
3927 | case ixgbe_mac_82599EB: | |
3928 | gpie |= IXGBE_SDP0_GPIEN; | |
3929 | break; | |
3930 | case ixgbe_mac_X540: | |
3931 | gpie |= IXGBE_EIMS_TS; | |
3932 | break; | |
3933 | default: | |
3934 | break; | |
3935 | } | |
3936 | } | |
5fdd31f9 | 3937 | |
a34bcfff AD |
3938 | /* Enable fan failure interrupt */ |
3939 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3940 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3941 | |
2698b208 | 3942 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3943 | gpie |= IXGBE_SDP1_GPIEN; |
3944 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3945 | } |
a34bcfff AD |
3946 | |
3947 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3948 | } | |
3949 | ||
c7ccde0f | 3950 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
3951 | { |
3952 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3953 | int err; |
a34bcfff AD |
3954 | u32 ctrl_ext; |
3955 | ||
3956 | ixgbe_get_hw_control(adapter); | |
3957 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3958 | |
9a799d71 AK |
3959 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3960 | ixgbe_configure_msix(adapter); | |
3961 | else | |
3962 | ixgbe_configure_msi_and_legacy(adapter); | |
3963 | ||
c6ecf39a DS |
3964 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3965 | if (hw->mac.ops.enable_tx_laser && | |
3966 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3967 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3968 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3969 | hw->mac.ops.enable_tx_laser(hw); |
3970 | ||
9a799d71 | 3971 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3972 | ixgbe_napi_enable_all(adapter); |
3973 | ||
73c4b7cd AD |
3974 | if (ixgbe_is_sfp(hw)) { |
3975 | ixgbe_sfp_link_config(adapter); | |
3976 | } else { | |
3977 | err = ixgbe_non_sfp_link_config(hw); | |
3978 | if (err) | |
3979 | e_err(probe, "link_config FAILED %d\n", err); | |
3980 | } | |
3981 | ||
021230d4 AV |
3982 | /* clear any pending interrupts, may auto mask */ |
3983 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3984 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3985 | |
bf069c97 DS |
3986 | /* |
3987 | * If this adapter has a fan, check to see if we had a failure | |
3988 | * before we enabled the interrupt. | |
3989 | */ | |
3990 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3991 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3992 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3993 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3994 | } |
3995 | ||
1da100bb | 3996 | /* enable transmits */ |
477de6ed | 3997 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 3998 | |
9a799d71 AK |
3999 | /* bring the link up in the watchdog, this could race with our first |
4000 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
4001 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
4002 | adapter->link_check_timeout = jiffies; | |
7086400d | 4003 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
4004 | |
4005 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
4006 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
4007 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
4008 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
4009 | } |
4010 | ||
d4f80882 AV |
4011 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
4012 | { | |
4013 | WARN_ON(in_interrupt()); | |
7086400d AD |
4014 | /* put off any impending NetWatchDogTimeout */ |
4015 | adapter->netdev->trans_start = jiffies; | |
4016 | ||
d4f80882 | 4017 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 4018 | usleep_range(1000, 2000); |
d4f80882 | 4019 | ixgbe_down(adapter); |
5809a1ae GR |
4020 | /* |
4021 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
4022 | * back up to give the VFs time to respond to the reset. The | |
4023 | * two second wait is based upon the watchdog timer cycle in | |
4024 | * the VF driver. | |
4025 | */ | |
4026 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4027 | msleep(2000); | |
d4f80882 AV |
4028 | ixgbe_up(adapter); |
4029 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
4030 | } | |
4031 | ||
c7ccde0f | 4032 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4033 | { |
4034 | /* hardware has been reset, we need to reload some things */ | |
4035 | ixgbe_configure(adapter); | |
4036 | ||
c7ccde0f | 4037 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4038 | } |
4039 | ||
4040 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
4041 | { | |
c44ade9e | 4042 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
4043 | int err; |
4044 | ||
7086400d AD |
4045 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
4046 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
4047 | usleep_range(1000, 2000); | |
4048 | ||
4049 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
4050 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
4051 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
4052 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
4053 | ||
8ca783ab | 4054 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
4055 | switch (err) { |
4056 | case 0: | |
4057 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 4058 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
4059 | break; |
4060 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 4061 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 4062 | break; |
794caeb2 PWJ |
4063 | case IXGBE_ERR_EEPROM_VERSION: |
4064 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 4065 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 4066 | "Please be aware there may be issues associated with " |
849c4542 ET |
4067 | "your hardware. If you are experiencing problems " |
4068 | "please contact your Intel or hardware " | |
4069 | "representative who provided you with this " | |
4070 | "hardware.\n"); | |
794caeb2 | 4071 | break; |
da4dd0f7 | 4072 | default: |
849c4542 | 4073 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 4074 | } |
9a799d71 | 4075 | |
7086400d AD |
4076 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
4077 | ||
9a799d71 | 4078 | /* reprogram the RAR[0] in case user changed it. */ |
1cdd1ec8 GR |
4079 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
4080 | IXGBE_RAH_AV); | |
9a799d71 AK |
4081 | } |
4082 | ||
f800326d AD |
4083 | /** |
4084 | * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers | |
4085 | * @rx_ring: ring to setup | |
4086 | * | |
4087 | * On many IA platforms the L1 cache has a critical stride of 4K, this | |
4088 | * results in each receive buffer starting in the same cache set. To help | |
4089 | * reduce the pressure on this cache set we can interleave the offsets so | |
4090 | * that only every other buffer will be in the same cache set. | |
4091 | **/ | |
4092 | static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring) | |
4093 | { | |
4094 | struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info; | |
4095 | u16 i; | |
4096 | ||
4097 | for (i = 0; i < rx_ring->count; i += 2) { | |
4098 | rx_buffer[0].page_offset = 0; | |
4099 | rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring); | |
4100 | rx_buffer = &rx_buffer[2]; | |
4101 | } | |
4102 | } | |
4103 | ||
9a799d71 AK |
4104 | /** |
4105 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4106 | * @rx_ring: ring to free buffers from |
4107 | **/ | |
b6ec895e | 4108 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4109 | { |
b6ec895e | 4110 | struct device *dev = rx_ring->dev; |
9a799d71 | 4111 | unsigned long size; |
b6ec895e | 4112 | u16 i; |
9a799d71 | 4113 | |
84418e3b AD |
4114 | /* ring already cleared, nothing to do */ |
4115 | if (!rx_ring->rx_buffer_info) | |
4116 | return; | |
9a799d71 | 4117 | |
84418e3b | 4118 | /* Free all the Rx ring sk_buffs */ |
9a799d71 | 4119 | for (i = 0; i < rx_ring->count; i++) { |
f800326d AD |
4120 | struct ixgbe_rx_buffer *rx_buffer; |
4121 | ||
4122 | rx_buffer = &rx_ring->rx_buffer_info[i]; | |
4123 | if (rx_buffer->skb) { | |
4124 | struct sk_buff *skb = rx_buffer->skb; | |
4125 | if (IXGBE_CB(skb)->page_released) { | |
4126 | dma_unmap_page(dev, | |
4127 | IXGBE_CB(skb)->dma, | |
4128 | ixgbe_rx_bufsz(rx_ring), | |
4129 | DMA_FROM_DEVICE); | |
4130 | IXGBE_CB(skb)->page_released = false; | |
4c1975d7 AD |
4131 | } |
4132 | dev_kfree_skb(skb); | |
9a799d71 | 4133 | } |
f800326d AD |
4134 | rx_buffer->skb = NULL; |
4135 | if (rx_buffer->dma) | |
4136 | dma_unmap_page(dev, rx_buffer->dma, | |
4137 | ixgbe_rx_pg_size(rx_ring), | |
4138 | DMA_FROM_DEVICE); | |
4139 | rx_buffer->dma = 0; | |
4140 | if (rx_buffer->page) | |
4141 | put_page(rx_buffer->page); | |
4142 | rx_buffer->page = NULL; | |
9a799d71 AK |
4143 | } |
4144 | ||
4145 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4146 | memset(rx_ring->rx_buffer_info, 0, size); | |
4147 | ||
f800326d AD |
4148 | ixgbe_init_rx_page_offset(rx_ring); |
4149 | ||
9a799d71 AK |
4150 | /* Zero out the descriptor ring */ |
4151 | memset(rx_ring->desc, 0, rx_ring->size); | |
4152 | ||
f800326d | 4153 | rx_ring->next_to_alloc = 0; |
9a799d71 AK |
4154 | rx_ring->next_to_clean = 0; |
4155 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4156 | } |
4157 | ||
4158 | /** | |
4159 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4160 | * @tx_ring: ring to be cleaned |
4161 | **/ | |
b6ec895e | 4162 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4163 | { |
4164 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4165 | unsigned long size; | |
b6ec895e | 4166 | u16 i; |
9a799d71 | 4167 | |
84418e3b AD |
4168 | /* ring already cleared, nothing to do */ |
4169 | if (!tx_ring->tx_buffer_info) | |
4170 | return; | |
9a799d71 | 4171 | |
84418e3b | 4172 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4173 | for (i = 0; i < tx_ring->count; i++) { |
4174 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4175 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4176 | } |
4177 | ||
4178 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
4179 | memset(tx_ring->tx_buffer_info, 0, size); | |
4180 | ||
4181 | /* Zero out the descriptor ring */ | |
4182 | memset(tx_ring->desc, 0, tx_ring->size); | |
4183 | ||
4184 | tx_ring->next_to_use = 0; | |
4185 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4186 | } |
4187 | ||
4188 | /** | |
021230d4 | 4189 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4190 | * @adapter: board private structure |
4191 | **/ | |
021230d4 | 4192 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4193 | { |
4194 | int i; | |
4195 | ||
021230d4 | 4196 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4197 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4198 | } |
4199 | ||
4200 | /** | |
021230d4 | 4201 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4202 | * @adapter: board private structure |
4203 | **/ | |
021230d4 | 4204 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4205 | { |
4206 | int i; | |
4207 | ||
021230d4 | 4208 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4209 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4210 | } |
4211 | ||
e4911d57 AD |
4212 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
4213 | { | |
4214 | struct hlist_node *node, *node2; | |
4215 | struct ixgbe_fdir_filter *filter; | |
4216 | ||
4217 | spin_lock(&adapter->fdir_perfect_lock); | |
4218 | ||
4219 | hlist_for_each_entry_safe(filter, node, node2, | |
4220 | &adapter->fdir_filter_list, fdir_node) { | |
4221 | hlist_del(&filter->fdir_node); | |
4222 | kfree(filter); | |
4223 | } | |
4224 | adapter->fdir_filter_count = 0; | |
4225 | ||
4226 | spin_unlock(&adapter->fdir_perfect_lock); | |
4227 | } | |
4228 | ||
9a799d71 AK |
4229 | void ixgbe_down(struct ixgbe_adapter *adapter) |
4230 | { | |
4231 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4232 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4233 | u32 rxctrl; |
bf29ee6c | 4234 | int i; |
9a799d71 AK |
4235 | |
4236 | /* signal that we are down to the interrupt handler */ | |
4237 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4238 | ||
4239 | /* disable receives */ | |
7f821875 JB |
4240 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4241 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4242 | |
2d39d576 YZ |
4243 | /* disable all enabled rx queues */ |
4244 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4245 | /* this call also flushes the previous write */ | |
4246 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4247 | ||
032b4325 | 4248 | usleep_range(10000, 20000); |
9a799d71 | 4249 | |
7f821875 JB |
4250 | netif_tx_stop_all_queues(netdev); |
4251 | ||
7086400d | 4252 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4253 | netif_carrier_off(netdev); |
4254 | netif_tx_disable(netdev); | |
4255 | ||
4256 | ixgbe_irq_disable(adapter); | |
4257 | ||
4258 | ixgbe_napi_disable_all(adapter); | |
4259 | ||
d034acf1 AD |
4260 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4261 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4262 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4263 | ||
4264 | del_timer_sync(&adapter->service_timer); | |
4265 | ||
34cecbbf | 4266 | if (adapter->num_vfs) { |
8e34d1aa AD |
4267 | /* Clear EITR Select mapping */ |
4268 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
4269 | |
4270 | /* Mark all the VFs as inactive */ | |
4271 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 4272 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 4273 | |
34cecbbf AD |
4274 | /* ping all the active vfs to let them know we are going down */ |
4275 | ixgbe_ping_all_vfs(adapter); | |
4276 | ||
4277 | /* Disable all VFTE/VFRE TX/RX */ | |
4278 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
4279 | } |
4280 | ||
7f821875 JB |
4281 | /* disable transmits in the hardware now that interrupts are off */ |
4282 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4283 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4284 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4285 | } |
34cecbbf AD |
4286 | |
4287 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4288 | switch (hw->mac.type) { |
4289 | case ixgbe_mac_82599EB: | |
b93a2226 | 4290 | case ixgbe_mac_X540: |
88512539 | 4291 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4292 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4293 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4294 | break; |
4295 | default: | |
4296 | break; | |
4297 | } | |
7f821875 | 4298 | |
6f4a0e45 PL |
4299 | if (!pci_channel_offline(adapter->pdev)) |
4300 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4301 | |
4302 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4303 | if (hw->mac.ops.disable_tx_laser && | |
4304 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4305 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4306 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4307 | hw->mac.ops.disable_tx_laser(hw); | |
4308 | ||
9a799d71 AK |
4309 | ixgbe_clean_all_tx_rings(adapter); |
4310 | ixgbe_clean_all_rx_rings(adapter); | |
4311 | ||
5dd2d332 | 4312 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4313 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4314 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4315 | #endif |
9a799d71 AK |
4316 | } |
4317 | ||
9a799d71 AK |
4318 | /** |
4319 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4320 | * @netdev: network interface device structure | |
4321 | **/ | |
4322 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4323 | { | |
4324 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4325 | ||
4326 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4327 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4328 | } |
4329 | ||
9a799d71 AK |
4330 | /** |
4331 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4332 | * @adapter: board private structure to initialize | |
4333 | * | |
4334 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4335 | * Fields are initialized based on PCI device information and | |
4336 | * OS network device settings (MTU size). | |
4337 | **/ | |
4338 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4339 | { | |
4340 | struct ixgbe_hw *hw = &adapter->hw; | |
4341 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4342 | unsigned int rss; |
7a6b6f51 | 4343 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4344 | int j; |
4345 | struct tc_configuration *tc; | |
4346 | #endif | |
021230d4 | 4347 | |
c44ade9e JB |
4348 | /* PCI config space info */ |
4349 | ||
4350 | hw->vendor_id = pdev->vendor; | |
4351 | hw->device_id = pdev->device; | |
4352 | hw->revision_id = pdev->revision; | |
4353 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4354 | hw->subsystem_device_id = pdev->subsystem_device; | |
4355 | ||
021230d4 | 4356 | /* Set capability flags */ |
3ed69d7e | 4357 | rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); |
021230d4 AV |
4358 | adapter->ring_feature[RING_F_RSS].indices = rss; |
4359 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
bd508178 AD |
4360 | switch (hw->mac.type) { |
4361 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
4362 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
4363 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 4364 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bd508178 | 4365 | break; |
b93a2226 | 4366 | case ixgbe_mac_X540: |
4f51bf70 JK |
4367 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; |
4368 | case ixgbe_mac_82599EB: | |
e8e26350 | 4369 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
4370 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4371 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4372 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4373 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
4374 | /* Flow Director hash filters enabled */ |
4375 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4376 | adapter->atr_sample_rate = 20; | |
c4cf55e5 | 4377 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 4378 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 4379 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 4380 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4381 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4382 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
4383 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 4384 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 4385 | /* Default traffic class to use for FCoE */ |
56075a98 | 4386 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 4387 | #endif |
eacd73f7 | 4388 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
4389 | break; |
4390 | default: | |
4391 | break; | |
f8212f97 | 4392 | } |
2f90b865 | 4393 | |
1fc5f038 AD |
4394 | /* n-tuple support exists, always init our spinlock */ |
4395 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4396 | ||
7a6b6f51 | 4397 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
4398 | switch (hw->mac.type) { |
4399 | case ixgbe_mac_X540: | |
4400 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
4401 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
4402 | break; | |
4403 | default: | |
4404 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
4405 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
4406 | break; | |
4407 | } | |
4408 | ||
2f90b865 AD |
4409 | /* Configure DCB traffic classes */ |
4410 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4411 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4412 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4413 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4414 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4415 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4416 | tc->dcb_pfc = pfc_disabled; | |
4417 | } | |
4de2a022 JF |
4418 | |
4419 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
4420 | tc = &adapter->dcb_cfg.tc_config[0]; | |
4421 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4422 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4423 | ||
2f90b865 AD |
4424 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
4425 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 4426 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 4427 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 4428 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
2f90b865 | 4429 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, |
e5b64635 | 4430 | MAX_TRAFFIC_CLASS); |
2f90b865 AD |
4431 | |
4432 | #endif | |
9a799d71 AK |
4433 | |
4434 | /* default flow control settings */ | |
cd7664f6 | 4435 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4436 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
4437 | #ifdef CONFIG_DCB |
4438 | adapter->last_lfc_mode = hw->fc.current_mode; | |
4439 | #endif | |
9da712d2 | 4440 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
4441 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
4442 | hw->fc.send_xon = true; | |
71fd570b | 4443 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4444 | |
30efa5a3 | 4445 | /* enable itr by default in dynamic mode */ |
f7554a2b | 4446 | adapter->rx_itr_setting = 1; |
f7554a2b | 4447 | adapter->tx_itr_setting = 1; |
30efa5a3 | 4448 | |
30efa5a3 JB |
4449 | /* set default ring sizes */ |
4450 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4451 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4452 | ||
bd198058 | 4453 | /* set default work limits */ |
59224555 | 4454 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 4455 | |
9a799d71 | 4456 | /* initialize eeprom parameters */ |
c44ade9e | 4457 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 4458 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
4459 | return -EIO; |
4460 | } | |
4461 | ||
9a799d71 AK |
4462 | set_bit(__IXGBE_DOWN, &adapter->state); |
4463 | ||
4464 | return 0; | |
4465 | } | |
4466 | ||
4467 | /** | |
4468 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 4469 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4470 | * |
4471 | * Return 0 on success, negative on failure | |
4472 | **/ | |
b6ec895e | 4473 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4474 | { |
b6ec895e | 4475 | struct device *dev = tx_ring->dev; |
de88eeeb AD |
4476 | int orig_node = dev_to_node(dev); |
4477 | int numa_node = -1; | |
9a799d71 AK |
4478 | int size; |
4479 | ||
3a581073 | 4480 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
4481 | |
4482 | if (tx_ring->q_vector) | |
4483 | numa_node = tx_ring->q_vector->numa_node; | |
4484 | ||
4485 | tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4486 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 4487 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
4488 | if (!tx_ring->tx_buffer_info) |
4489 | goto err; | |
9a799d71 AK |
4490 | |
4491 | /* round up to nearest 4K */ | |
12207e49 | 4492 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4493 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4494 | |
de88eeeb AD |
4495 | set_dev_node(dev, numa_node); |
4496 | tx_ring->desc = dma_alloc_coherent(dev, | |
4497 | tx_ring->size, | |
4498 | &tx_ring->dma, | |
4499 | GFP_KERNEL); | |
4500 | set_dev_node(dev, orig_node); | |
4501 | if (!tx_ring->desc) | |
4502 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
4503 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
4504 | if (!tx_ring->desc) |
4505 | goto err; | |
9a799d71 | 4506 | |
3a581073 JB |
4507 | tx_ring->next_to_use = 0; |
4508 | tx_ring->next_to_clean = 0; | |
9a799d71 | 4509 | return 0; |
e01c31a5 JB |
4510 | |
4511 | err: | |
4512 | vfree(tx_ring->tx_buffer_info); | |
4513 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 4514 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 4515 | return -ENOMEM; |
9a799d71 AK |
4516 | } |
4517 | ||
69888674 AD |
4518 | /** |
4519 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4520 | * @adapter: board private structure | |
4521 | * | |
4522 | * If this function returns with an error, then it's possible one or | |
4523 | * more of the rings is populated (while the rest are not). It is the | |
4524 | * callers duty to clean those orphaned rings. | |
4525 | * | |
4526 | * Return 0 on success, negative on failure | |
4527 | **/ | |
4528 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4529 | { | |
4530 | int i, err = 0; | |
4531 | ||
4532 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 4533 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
4534 | if (!err) |
4535 | continue; | |
396e799c | 4536 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
4537 | break; |
4538 | } | |
4539 | ||
4540 | return err; | |
4541 | } | |
4542 | ||
9a799d71 AK |
4543 | /** |
4544 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 4545 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4546 | * |
4547 | * Returns 0 on success, negative on failure | |
4548 | **/ | |
b6ec895e | 4549 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4550 | { |
b6ec895e | 4551 | struct device *dev = rx_ring->dev; |
de88eeeb AD |
4552 | int orig_node = dev_to_node(dev); |
4553 | int numa_node = -1; | |
021230d4 | 4554 | int size; |
9a799d71 | 4555 | |
3a581073 | 4556 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
4557 | |
4558 | if (rx_ring->q_vector) | |
4559 | numa_node = rx_ring->q_vector->numa_node; | |
4560 | ||
4561 | rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4562 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 4563 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
4564 | if (!rx_ring->rx_buffer_info) |
4565 | goto err; | |
9a799d71 | 4566 | |
9a799d71 | 4567 | /* Round up to nearest 4K */ |
3a581073 JB |
4568 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4569 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4570 | |
de88eeeb AD |
4571 | set_dev_node(dev, numa_node); |
4572 | rx_ring->desc = dma_alloc_coherent(dev, | |
4573 | rx_ring->size, | |
4574 | &rx_ring->dma, | |
4575 | GFP_KERNEL); | |
4576 | set_dev_node(dev, orig_node); | |
4577 | if (!rx_ring->desc) | |
4578 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
4579 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
4580 | if (!rx_ring->desc) |
4581 | goto err; | |
9a799d71 | 4582 | |
3a581073 JB |
4583 | rx_ring->next_to_clean = 0; |
4584 | rx_ring->next_to_use = 0; | |
9a799d71 | 4585 | |
f800326d AD |
4586 | ixgbe_init_rx_page_offset(rx_ring); |
4587 | ||
9a799d71 | 4588 | return 0; |
b6ec895e AD |
4589 | err: |
4590 | vfree(rx_ring->rx_buffer_info); | |
4591 | rx_ring->rx_buffer_info = NULL; | |
4592 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 4593 | return -ENOMEM; |
9a799d71 AK |
4594 | } |
4595 | ||
69888674 AD |
4596 | /** |
4597 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4598 | * @adapter: board private structure | |
4599 | * | |
4600 | * If this function returns with an error, then it's possible one or | |
4601 | * more of the rings is populated (while the rest are not). It is the | |
4602 | * callers duty to clean those orphaned rings. | |
4603 | * | |
4604 | * Return 0 on success, negative on failure | |
4605 | **/ | |
69888674 AD |
4606 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
4607 | { | |
4608 | int i, err = 0; | |
4609 | ||
4610 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 4611 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
4612 | if (!err) |
4613 | continue; | |
396e799c | 4614 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
4615 | break; |
4616 | } | |
4617 | ||
4618 | return err; | |
4619 | } | |
4620 | ||
9a799d71 AK |
4621 | /** |
4622 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
4623 | * @tx_ring: Tx descriptor ring for a specific queue |
4624 | * | |
4625 | * Free all transmit software resources | |
4626 | **/ | |
b6ec895e | 4627 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4628 | { |
b6ec895e | 4629 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
4630 | |
4631 | vfree(tx_ring->tx_buffer_info); | |
4632 | tx_ring->tx_buffer_info = NULL; | |
4633 | ||
b6ec895e AD |
4634 | /* if not set, then don't free */ |
4635 | if (!tx_ring->desc) | |
4636 | return; | |
4637 | ||
4638 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
4639 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
4640 | |
4641 | tx_ring->desc = NULL; | |
4642 | } | |
4643 | ||
4644 | /** | |
4645 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4646 | * @adapter: board private structure | |
4647 | * | |
4648 | * Free all transmit software resources | |
4649 | **/ | |
4650 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4651 | { | |
4652 | int i; | |
4653 | ||
4654 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 4655 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 4656 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
4657 | } |
4658 | ||
4659 | /** | |
b4617240 | 4660 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4661 | * @rx_ring: ring to clean the resources from |
4662 | * | |
4663 | * Free all receive software resources | |
4664 | **/ | |
b6ec895e | 4665 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4666 | { |
b6ec895e | 4667 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
4668 | |
4669 | vfree(rx_ring->rx_buffer_info); | |
4670 | rx_ring->rx_buffer_info = NULL; | |
4671 | ||
b6ec895e AD |
4672 | /* if not set, then don't free */ |
4673 | if (!rx_ring->desc) | |
4674 | return; | |
4675 | ||
4676 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
4677 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
4678 | |
4679 | rx_ring->desc = NULL; | |
4680 | } | |
4681 | ||
4682 | /** | |
4683 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4684 | * @adapter: board private structure | |
4685 | * | |
4686 | * Free all receive software resources | |
4687 | **/ | |
4688 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4689 | { | |
4690 | int i; | |
4691 | ||
4692 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4693 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 4694 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
4695 | } |
4696 | ||
9a799d71 AK |
4697 | /** |
4698 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4699 | * @netdev: network interface device structure | |
4700 | * @new_mtu: new value for maximum frame size | |
4701 | * | |
4702 | * Returns 0 on success, negative on failure | |
4703 | **/ | |
4704 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4705 | { | |
4706 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4707 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4708 | ||
42c783c5 | 4709 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
4710 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
4711 | return -EINVAL; | |
4712 | ||
4713 | /* | |
4714 | * For 82599EB we cannot allow PF to change MTU greater than 1500 | |
4715 | * in SR-IOV mode as it may cause buffer overruns in guest VFs that | |
4716 | * don't allocate and chain buffers correctly. | |
4717 | */ | |
4718 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
4719 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
4720 | (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
e9f98072 | 4721 | return -EINVAL; |
9a799d71 | 4722 | |
396e799c | 4723 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 4724 | |
021230d4 | 4725 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4726 | netdev->mtu = new_mtu; |
4727 | ||
d4f80882 AV |
4728 | if (netif_running(netdev)) |
4729 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4730 | |
4731 | return 0; | |
4732 | } | |
4733 | ||
4734 | /** | |
4735 | * ixgbe_open - Called when a network interface is made active | |
4736 | * @netdev: network interface device structure | |
4737 | * | |
4738 | * Returns 0 on success, negative value on failure | |
4739 | * | |
4740 | * The open entry point is called when a network interface is made | |
4741 | * active by the system (IFF_UP). At this point all resources needed | |
4742 | * for transmit and receive operations are allocated, the interrupt | |
4743 | * handler is registered with the OS, the watchdog timer is started, | |
4744 | * and the stack is notified that the interface is ready. | |
4745 | **/ | |
4746 | static int ixgbe_open(struct net_device *netdev) | |
4747 | { | |
4748 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4749 | int err; | |
4bebfaa5 AK |
4750 | |
4751 | /* disallow open during test */ | |
4752 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4753 | return -EBUSY; | |
9a799d71 | 4754 | |
54386467 JB |
4755 | netif_carrier_off(netdev); |
4756 | ||
9a799d71 AK |
4757 | /* allocate transmit descriptors */ |
4758 | err = ixgbe_setup_all_tx_resources(adapter); | |
4759 | if (err) | |
4760 | goto err_setup_tx; | |
4761 | ||
9a799d71 AK |
4762 | /* allocate receive descriptors */ |
4763 | err = ixgbe_setup_all_rx_resources(adapter); | |
4764 | if (err) | |
4765 | goto err_setup_rx; | |
4766 | ||
4767 | ixgbe_configure(adapter); | |
4768 | ||
021230d4 | 4769 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4770 | if (err) |
4771 | goto err_req_irq; | |
4772 | ||
c7ccde0f | 4773 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4774 | |
4775 | return 0; | |
4776 | ||
9a799d71 | 4777 | err_req_irq: |
9a799d71 | 4778 | err_setup_rx: |
a20a1199 | 4779 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 4780 | err_setup_tx: |
a20a1199 | 4781 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
4782 | ixgbe_reset(adapter); |
4783 | ||
4784 | return err; | |
4785 | } | |
4786 | ||
4787 | /** | |
4788 | * ixgbe_close - Disables a network interface | |
4789 | * @netdev: network interface device structure | |
4790 | * | |
4791 | * Returns 0, this is not allowed to fail | |
4792 | * | |
4793 | * The close entry point is called when an interface is de-activated | |
4794 | * by the OS. The hardware is still under the drivers control, but | |
4795 | * needs to be disabled. A global MAC reset is issued to stop the | |
4796 | * hardware, and all transmit and receive resources are freed. | |
4797 | **/ | |
4798 | static int ixgbe_close(struct net_device *netdev) | |
4799 | { | |
4800 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4801 | |
4802 | ixgbe_down(adapter); | |
4803 | ixgbe_free_irq(adapter); | |
4804 | ||
e4911d57 AD |
4805 | ixgbe_fdir_filter_exit(adapter); |
4806 | ||
9a799d71 AK |
4807 | ixgbe_free_all_tx_resources(adapter); |
4808 | ixgbe_free_all_rx_resources(adapter); | |
4809 | ||
5eba3699 | 4810 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4811 | |
4812 | return 0; | |
4813 | } | |
4814 | ||
b3c8b4ba AD |
4815 | #ifdef CONFIG_PM |
4816 | static int ixgbe_resume(struct pci_dev *pdev) | |
4817 | { | |
c60fbb00 AD |
4818 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4819 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
4820 | u32 err; |
4821 | ||
4822 | pci_set_power_state(pdev, PCI_D0); | |
4823 | pci_restore_state(pdev); | |
656ab817 DS |
4824 | /* |
4825 | * pci_restore_state clears dev->state_saved so call | |
4826 | * pci_save_state to restore it. | |
4827 | */ | |
4828 | pci_save_state(pdev); | |
9ce77666 | 4829 | |
4830 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4831 | if (err) { |
849c4542 | 4832 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
4833 | return err; |
4834 | } | |
4835 | pci_set_master(pdev); | |
4836 | ||
dd4d8ca6 | 4837 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
4838 | |
4839 | err = ixgbe_init_interrupt_scheme(adapter); | |
4840 | if (err) { | |
849c4542 | 4841 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
4842 | return err; |
4843 | } | |
4844 | ||
b3c8b4ba AD |
4845 | ixgbe_reset(adapter); |
4846 | ||
495dce12 WJP |
4847 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4848 | ||
b3c8b4ba | 4849 | if (netif_running(netdev)) { |
c60fbb00 | 4850 | err = ixgbe_open(netdev); |
b3c8b4ba AD |
4851 | if (err) |
4852 | return err; | |
4853 | } | |
4854 | ||
4855 | netif_device_attach(netdev); | |
4856 | ||
4857 | return 0; | |
4858 | } | |
b3c8b4ba | 4859 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4860 | |
4861 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 4862 | { |
c60fbb00 AD |
4863 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4864 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
4865 | struct ixgbe_hw *hw = &adapter->hw; |
4866 | u32 ctrl, fctrl; | |
4867 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4868 | #ifdef CONFIG_PM |
4869 | int retval = 0; | |
4870 | #endif | |
4871 | ||
4872 | netif_device_detach(netdev); | |
4873 | ||
4874 | if (netif_running(netdev)) { | |
4875 | ixgbe_down(adapter); | |
4876 | ixgbe_free_irq(adapter); | |
4877 | ixgbe_free_all_tx_resources(adapter); | |
4878 | ixgbe_free_all_rx_resources(adapter); | |
4879 | } | |
b3c8b4ba | 4880 | |
5f5ae6fc | 4881 | ixgbe_clear_interrupt_scheme(adapter); |
d033d526 JF |
4882 | #ifdef CONFIG_DCB |
4883 | kfree(adapter->ixgbe_ieee_pfc); | |
4884 | kfree(adapter->ixgbe_ieee_ets); | |
4885 | #endif | |
5f5ae6fc | 4886 | |
b3c8b4ba AD |
4887 | #ifdef CONFIG_PM |
4888 | retval = pci_save_state(pdev); | |
4889 | if (retval) | |
4890 | return retval; | |
4df10466 | 4891 | |
b3c8b4ba | 4892 | #endif |
e8e26350 PW |
4893 | if (wufc) { |
4894 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4895 | |
e8e26350 PW |
4896 | /* turn on all-multi mode if wake on multicast is enabled */ |
4897 | if (wufc & IXGBE_WUFC_MC) { | |
4898 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4899 | fctrl |= IXGBE_FCTRL_MPE; | |
4900 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4901 | } | |
4902 | ||
4903 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4904 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4905 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4906 | ||
4907 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4908 | } else { | |
4909 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4910 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4911 | } | |
4912 | ||
bd508178 AD |
4913 | switch (hw->mac.type) { |
4914 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 4915 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
4916 | break; |
4917 | case ixgbe_mac_82599EB: | |
b93a2226 | 4918 | case ixgbe_mac_X540: |
bd508178 AD |
4919 | pci_wake_from_d3(pdev, !!wufc); |
4920 | break; | |
4921 | default: | |
4922 | break; | |
4923 | } | |
b3c8b4ba | 4924 | |
9d8d05ae RW |
4925 | *enable_wake = !!wufc; |
4926 | ||
b3c8b4ba AD |
4927 | ixgbe_release_hw_control(adapter); |
4928 | ||
4929 | pci_disable_device(pdev); | |
4930 | ||
9d8d05ae RW |
4931 | return 0; |
4932 | } | |
4933 | ||
4934 | #ifdef CONFIG_PM | |
4935 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4936 | { | |
4937 | int retval; | |
4938 | bool wake; | |
4939 | ||
4940 | retval = __ixgbe_shutdown(pdev, &wake); | |
4941 | if (retval) | |
4942 | return retval; | |
4943 | ||
4944 | if (wake) { | |
4945 | pci_prepare_to_sleep(pdev); | |
4946 | } else { | |
4947 | pci_wake_from_d3(pdev, false); | |
4948 | pci_set_power_state(pdev, PCI_D3hot); | |
4949 | } | |
b3c8b4ba AD |
4950 | |
4951 | return 0; | |
4952 | } | |
9d8d05ae | 4953 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
4954 | |
4955 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
4956 | { | |
9d8d05ae RW |
4957 | bool wake; |
4958 | ||
4959 | __ixgbe_shutdown(pdev, &wake); | |
4960 | ||
4961 | if (system_state == SYSTEM_POWER_OFF) { | |
4962 | pci_wake_from_d3(pdev, wake); | |
4963 | pci_set_power_state(pdev, PCI_D3hot); | |
4964 | } | |
b3c8b4ba AD |
4965 | } |
4966 | ||
9a799d71 AK |
4967 | /** |
4968 | * ixgbe_update_stats - Update the board statistics counters. | |
4969 | * @adapter: board private structure | |
4970 | **/ | |
4971 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
4972 | { | |
2d86f139 | 4973 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 4974 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 4975 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
4976 | u64 total_mpc = 0; |
4977 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
4978 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
4979 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 4980 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
7b859ebc AH |
4981 | #ifdef IXGBE_FCOE |
4982 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
4983 | unsigned int cpu; | |
4984 | u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0; | |
4985 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 4986 | |
d08935c2 DS |
4987 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
4988 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
4989 | return; | |
4990 | ||
94b982b2 | 4991 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 4992 | u64 rsc_count = 0; |
94b982b2 | 4993 | u64 rsc_flush = 0; |
d51019a4 PW |
4994 | for (i = 0; i < 16; i++) |
4995 | adapter->hw_rx_no_dma_resources += | |
7ca647bd | 4996 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); |
94b982b2 | 4997 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
4998 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
4999 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5000 | } |
5001 | adapter->rsc_total_count = rsc_count; | |
5002 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5003 | } |
5004 | ||
5b7da515 AD |
5005 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5006 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5007 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5008 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5009 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 5010 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
5011 | bytes += rx_ring->stats.bytes; |
5012 | packets += rx_ring->stats.packets; | |
5013 | } | |
5014 | adapter->non_eop_descs = non_eop_descs; | |
5015 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5016 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 5017 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
5018 | netdev->stats.rx_bytes = bytes; |
5019 | netdev->stats.rx_packets = packets; | |
5020 | ||
5021 | bytes = 0; | |
5022 | packets = 0; | |
7ca3bc58 | 5023 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5024 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5025 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5026 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5027 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5028 | bytes += tx_ring->stats.bytes; | |
5029 | packets += tx_ring->stats.packets; | |
5030 | } | |
eb985f09 | 5031 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5032 | adapter->tx_busy = tx_busy; |
5033 | netdev->stats.tx_bytes = bytes; | |
5034 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5035 | |
7ca647bd | 5036 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5037 | |
5038 | /* 8 register reads */ | |
6f11eef7 AV |
5039 | for (i = 0; i < 8; i++) { |
5040 | /* for packet buffers not used, the register should read 0 */ | |
5041 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5042 | missed_rx += mpc; | |
7ca647bd JP |
5043 | hwstats->mpc[i] += mpc; |
5044 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5045 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5046 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5047 | switch (hw->mac.type) { |
5048 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5049 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5050 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5051 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5052 | hwstats->pxonrxc[i] += |
5053 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5054 | break; |
5055 | case ixgbe_mac_82599EB: | |
b93a2226 | 5056 | case ixgbe_mac_X540: |
bd508178 AD |
5057 | hwstats->pxonrxc[i] += |
5058 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5059 | break; |
5060 | default: | |
5061 | break; | |
e8e26350 | 5062 | } |
6f11eef7 | 5063 | } |
1a70db4b ET |
5064 | |
5065 | /*16 register reads */ | |
5066 | for (i = 0; i < 16; i++) { | |
5067 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5068 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5069 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5070 | (hw->mac.type == ixgbe_mac_X540)) { | |
5071 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5072 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5073 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5074 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5075 | } | |
5076 | } | |
5077 | ||
7ca647bd | 5078 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5079 | /* work around hardware counting issue */ |
7ca647bd | 5080 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5081 | |
c84d324c JF |
5082 | ixgbe_update_xoff_received(adapter); |
5083 | ||
6f11eef7 | 5084 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5085 | switch (hw->mac.type) { |
5086 | case ixgbe_mac_82598EB: | |
5087 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5088 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5089 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5090 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5091 | break; | |
b93a2226 | 5092 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5093 | /* OS2BMC stats are X540 only*/ |
5094 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5095 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5096 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5097 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5098 | case ixgbe_mac_82599EB: | |
7ca647bd | 5099 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5100 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5101 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5102 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5103 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5104 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5105 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5106 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5107 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5108 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5109 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5110 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5111 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5112 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5113 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5114 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc AH |
5115 | /* Add up per cpu counters for total ddp aloc fail */ |
5116 | if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) { | |
5117 | for_each_possible_cpu(cpu) { | |
5118 | fcoe_noddp_counts_sum += | |
5119 | *per_cpu_ptr(fcoe->pcpu_noddp, cpu); | |
5120 | fcoe_noddp_ext_buff_counts_sum += | |
5121 | *per_cpu_ptr(fcoe-> | |
5122 | pcpu_noddp_ext_buff, cpu); | |
5123 | } | |
5124 | } | |
5125 | hwstats->fcoe_noddp = fcoe_noddp_counts_sum; | |
5126 | hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum; | |
6d45522c | 5127 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5128 | break; |
5129 | default: | |
5130 | break; | |
e8e26350 | 5131 | } |
9a799d71 | 5132 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5133 | hwstats->bprc += bprc; |
5134 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5135 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5136 | hwstats->mprc -= bprc; |
5137 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5138 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5139 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5140 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5141 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5142 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5143 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5144 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5145 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5146 | hwstats->lxontxc += lxon; |
6f11eef7 | 5147 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 5148 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
5149 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
5150 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5151 | /* |
5152 | * 82598 errata - tx of flow control packets is included in tx counters | |
5153 | */ | |
5154 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5155 | hwstats->gptc -= xon_off_tot; |
5156 | hwstats->mptc -= xon_off_tot; | |
5157 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5158 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5159 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5160 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5161 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5162 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5163 | hwstats->ptc64 -= xon_off_tot; | |
5164 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5165 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5166 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5167 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5168 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5169 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5170 | |
5171 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5172 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5173 | |
5174 | /* Rx Errors */ | |
7ca647bd | 5175 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5176 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5177 | netdev->stats.rx_length_errors = hwstats->rlec; |
5178 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5179 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5180 | } |
5181 | ||
5182 | /** | |
d034acf1 AD |
5183 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
5184 | * @adapter - pointer to the device adapter structure | |
9a799d71 | 5185 | **/ |
d034acf1 | 5186 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 5187 | { |
cf8280ee | 5188 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 5189 | int i; |
cf8280ee | 5190 | |
d034acf1 AD |
5191 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
5192 | return; | |
5193 | ||
5194 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 5195 | |
d034acf1 | 5196 | /* if interface is down do nothing */ |
fe49f04a | 5197 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
5198 | return; |
5199 | ||
5200 | /* do nothing if we are not using signature filters */ | |
5201 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
5202 | return; | |
5203 | ||
5204 | adapter->fdir_overflow++; | |
5205 | ||
93c52dd0 AD |
5206 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
5207 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5208 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 5209 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
5210 | /* re-enable flow director interrupts */ |
5211 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
5212 | } else { |
5213 | e_err(probe, "failed to finish FDIR re-initialization, " | |
5214 | "ignored adding FDIR ATR filters\n"); | |
5215 | } | |
93c52dd0 AD |
5216 | } |
5217 | ||
5218 | /** | |
5219 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
5220 | * @adapter - pointer to the device adapter structure | |
5221 | * | |
5222 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 5223 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 5224 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 5225 | * determine if a hang has occurred. |
93c52dd0 AD |
5226 | */ |
5227 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 5228 | { |
cf8280ee | 5229 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5230 | u64 eics = 0; |
5231 | int i; | |
cf8280ee | 5232 | |
93c52dd0 AD |
5233 | /* If we're down or resetting, just bail */ |
5234 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5235 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5236 | return; | |
22d5a71b | 5237 | |
93c52dd0 AD |
5238 | /* Force detection of hung controller */ |
5239 | if (netif_carrier_ok(adapter->netdev)) { | |
5240 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5241 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
5242 | } | |
22d5a71b | 5243 | |
fe49f04a AD |
5244 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5245 | /* | |
5246 | * for legacy and MSI interrupts don't set any bits | |
5247 | * that are enabled for EIAM, because this operation | |
5248 | * would set *both* EIMS and EICS for any bit in EIAM | |
5249 | */ | |
5250 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5251 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
5252 | } else { |
5253 | /* get one bit for every active tx/rx interrupt vector */ | |
5254 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
5255 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
efe3d3c8 | 5256 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
5257 | eics |= ((u64)1 << i); |
5258 | } | |
cf8280ee | 5259 | } |
9a799d71 | 5260 | |
93c52dd0 | 5261 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
5262 | ixgbe_irq_rearm_queues(adapter, eics); |
5263 | ||
cf8280ee JB |
5264 | } |
5265 | ||
e8e26350 | 5266 | /** |
93c52dd0 AD |
5267 | * ixgbe_watchdog_update_link - update the link status |
5268 | * @adapter - pointer to the device adapter structure | |
5269 | * @link_speed - pointer to a u32 to store the link_speed | |
e8e26350 | 5270 | **/ |
93c52dd0 | 5271 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 5272 | { |
e8e26350 | 5273 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5274 | u32 link_speed = adapter->link_speed; |
5275 | bool link_up = adapter->link_up; | |
c4cf55e5 | 5276 | int i; |
e8e26350 | 5277 | |
93c52dd0 AD |
5278 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
5279 | return; | |
5280 | ||
5281 | if (hw->mac.ops.check_link) { | |
5282 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 5283 | } else { |
93c52dd0 AD |
5284 | /* always assume link is up, if no check link function */ |
5285 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
5286 | link_up = true; | |
c4cf55e5 | 5287 | } |
93c52dd0 AD |
5288 | if (link_up) { |
5289 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
5290 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
5291 | hw->mac.ops.fc_enable(hw, i); | |
5292 | } else { | |
5293 | hw->mac.ops.fc_enable(hw, 0); | |
5294 | } | |
5295 | } | |
5296 | ||
5297 | if (link_up || | |
5298 | time_after(jiffies, (adapter->link_check_timeout + | |
5299 | IXGBE_TRY_LINK_TIMEOUT))) { | |
5300 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
5301 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
5302 | IXGBE_WRITE_FLUSH(hw); | |
5303 | } | |
5304 | ||
5305 | adapter->link_up = link_up; | |
5306 | adapter->link_speed = link_speed; | |
e8e26350 PW |
5307 | } |
5308 | ||
5309 | /** | |
93c52dd0 AD |
5310 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
5311 | * print link up message | |
5312 | * @adapter - pointer to the device adapter structure | |
e8e26350 | 5313 | **/ |
93c52dd0 | 5314 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 5315 | { |
93c52dd0 | 5316 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 5317 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5318 | u32 link_speed = adapter->link_speed; |
5319 | bool flow_rx, flow_tx; | |
e8e26350 | 5320 | |
93c52dd0 AD |
5321 | /* only continue if link was previously down */ |
5322 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 5323 | return; |
63d6e1d8 | 5324 | |
93c52dd0 | 5325 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 5326 | |
93c52dd0 AD |
5327 | switch (hw->mac.type) { |
5328 | case ixgbe_mac_82598EB: { | |
5329 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5330 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
5331 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
5332 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
5333 | } | |
5334 | break; | |
5335 | case ixgbe_mac_X540: | |
5336 | case ixgbe_mac_82599EB: { | |
5337 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5338 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
5339 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
5340 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
5341 | } | |
5342 | break; | |
5343 | default: | |
5344 | flow_tx = false; | |
5345 | flow_rx = false; | |
5346 | break; | |
e8e26350 | 5347 | } |
93c52dd0 AD |
5348 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
5349 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5350 | "10 Gbps" : | |
5351 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5352 | "1 Gbps" : | |
5353 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
5354 | "100 Mbps" : | |
5355 | "unknown speed"))), | |
5356 | ((flow_rx && flow_tx) ? "RX/TX" : | |
5357 | (flow_rx ? "RX" : | |
5358 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 5359 | |
93c52dd0 | 5360 | netif_carrier_on(netdev); |
93c52dd0 | 5361 | ixgbe_check_vf_rate_limit(adapter); |
e8e26350 PW |
5362 | } |
5363 | ||
c4cf55e5 | 5364 | /** |
93c52dd0 AD |
5365 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
5366 | * print link down message | |
5367 | * @adapter - pointer to the adapter structure | |
c4cf55e5 | 5368 | **/ |
581330ba | 5369 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 5370 | { |
cf8280ee | 5371 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 5372 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 5373 | |
93c52dd0 AD |
5374 | adapter->link_up = false; |
5375 | adapter->link_speed = 0; | |
cf8280ee | 5376 | |
93c52dd0 AD |
5377 | /* only continue if link was up previously */ |
5378 | if (!netif_carrier_ok(netdev)) | |
5379 | return; | |
264857b8 | 5380 | |
93c52dd0 AD |
5381 | /* poll for SFP+ cable when link is down */ |
5382 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
5383 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 5384 | |
93c52dd0 AD |
5385 | e_info(drv, "NIC Link is Down\n"); |
5386 | netif_carrier_off(netdev); | |
5387 | } | |
e8e26350 | 5388 | |
93c52dd0 AD |
5389 | /** |
5390 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
5391 | * @adapter - pointer to the device adapter structure | |
5392 | **/ | |
5393 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
5394 | { | |
c4cf55e5 | 5395 | int i; |
93c52dd0 | 5396 | int some_tx_pending = 0; |
c4cf55e5 | 5397 | |
93c52dd0 | 5398 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 5399 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 5400 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5401 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5402 | some_tx_pending = 1; | |
5403 | break; | |
5404 | } | |
5405 | } | |
5406 | ||
5407 | if (some_tx_pending) { | |
5408 | /* We've lost link, so the controller stops DMA, | |
5409 | * but we've got queued Tx work that's never going | |
5410 | * to get done, so reset controller to flush Tx. | |
5411 | * (Do the reset outside of interrupt context). | |
5412 | */ | |
c83c6cbd | 5413 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 5414 | } |
c4cf55e5 | 5415 | } |
c4cf55e5 PWJ |
5416 | } |
5417 | ||
a985b6c3 GR |
5418 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
5419 | { | |
5420 | u32 ssvpc; | |
5421 | ||
5422 | /* Do not perform spoof check for 82598 */ | |
5423 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5424 | return; | |
5425 | ||
5426 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
5427 | ||
5428 | /* | |
5429 | * ssvpc register is cleared on read, if zero then no | |
5430 | * spoofed packets in the last interval. | |
5431 | */ | |
5432 | if (!ssvpc) | |
5433 | return; | |
5434 | ||
5435 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
5436 | } | |
5437 | ||
93c52dd0 AD |
5438 | /** |
5439 | * ixgbe_watchdog_subtask - check and bring link up | |
5440 | * @adapter - pointer to the device adapter structure | |
5441 | **/ | |
5442 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
5443 | { | |
5444 | /* if interface is down do nothing */ | |
7edebf9a ET |
5445 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5446 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
93c52dd0 AD |
5447 | return; |
5448 | ||
5449 | ixgbe_watchdog_update_link(adapter); | |
5450 | ||
5451 | if (adapter->link_up) | |
5452 | ixgbe_watchdog_link_is_up(adapter); | |
5453 | else | |
5454 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 5455 | |
a985b6c3 | 5456 | ixgbe_spoof_check(adapter); |
9a799d71 | 5457 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
5458 | |
5459 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 5460 | } |
10eec955 | 5461 | |
cf8280ee | 5462 | /** |
7086400d AD |
5463 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
5464 | * @adapter - the ixgbe adapter structure | |
cf8280ee | 5465 | **/ |
7086400d | 5466 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 5467 | { |
cf8280ee | 5468 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 5469 | s32 err; |
cf8280ee | 5470 | |
7086400d AD |
5471 | /* not searching for SFP so there is nothing to do here */ |
5472 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
5473 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5474 | return; | |
10eec955 | 5475 | |
7086400d AD |
5476 | /* someone else is in init, wait until next service event */ |
5477 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5478 | return; | |
cf8280ee | 5479 | |
7086400d AD |
5480 | err = hw->phy.ops.identify_sfp(hw); |
5481 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5482 | goto sfp_out; | |
264857b8 | 5483 | |
7086400d AD |
5484 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
5485 | /* If no cable is present, then we need to reset | |
5486 | * the next time we find a good cable. */ | |
5487 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 5488 | } |
9a799d71 | 5489 | |
7086400d AD |
5490 | /* exit on error */ |
5491 | if (err) | |
5492 | goto sfp_out; | |
e8e26350 | 5493 | |
7086400d AD |
5494 | /* exit if reset not needed */ |
5495 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5496 | goto sfp_out; | |
9a799d71 | 5497 | |
7086400d | 5498 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 5499 | |
7086400d AD |
5500 | /* |
5501 | * A module may be identified correctly, but the EEPROM may not have | |
5502 | * support for that module. setup_sfp() will fail in that case, so | |
5503 | * we should not allow that module to load. | |
5504 | */ | |
5505 | if (hw->mac.type == ixgbe_mac_82598EB) | |
5506 | err = hw->phy.ops.reset(hw); | |
5507 | else | |
5508 | err = hw->mac.ops.setup_sfp(hw); | |
5509 | ||
5510 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5511 | goto sfp_out; | |
5512 | ||
5513 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
5514 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
5515 | ||
5516 | sfp_out: | |
5517 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5518 | ||
5519 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
5520 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
5521 | e_dev_err("failed to initialize because an unsupported " | |
5522 | "SFP+ module type was detected.\n"); | |
5523 | e_dev_err("Reload the driver after installing a " | |
5524 | "supported module.\n"); | |
5525 | unregister_netdev(adapter->netdev); | |
bc59fcda | 5526 | } |
7086400d | 5527 | } |
bc59fcda | 5528 | |
7086400d AD |
5529 | /** |
5530 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
5531 | * @adapter - the ixgbe adapter structure | |
5532 | **/ | |
5533 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
5534 | { | |
5535 | struct ixgbe_hw *hw = &adapter->hw; | |
5536 | u32 autoneg; | |
5537 | bool negotiation; | |
5538 | ||
5539 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
5540 | return; | |
5541 | ||
5542 | /* someone else is in init, wait until next service event */ | |
5543 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5544 | return; | |
5545 | ||
5546 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5547 | ||
5548 | autoneg = hw->phy.autoneg_advertised; | |
5549 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
5550 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
7086400d AD |
5551 | if (hw->mac.ops.setup_link) |
5552 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
5553 | ||
5554 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
5555 | adapter->link_check_timeout = jiffies; | |
5556 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5557 | } | |
5558 | ||
83c61fa9 GR |
5559 | #ifdef CONFIG_PCI_IOV |
5560 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
5561 | { | |
5562 | int vf; | |
5563 | struct ixgbe_hw *hw = &adapter->hw; | |
5564 | struct net_device *netdev = adapter->netdev; | |
5565 | u32 gpc; | |
5566 | u32 ciaa, ciad; | |
5567 | ||
5568 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
5569 | if (gpc) /* If incrementing then no need for the check below */ | |
5570 | return; | |
5571 | /* | |
5572 | * Check to see if a bad DMA write target from an errant or | |
5573 | * malicious VF has caused a PCIe error. If so then we can | |
5574 | * issue a VFLR to the offending VF(s) and then resume without | |
5575 | * requesting a full slot reset. | |
5576 | */ | |
5577 | ||
5578 | for (vf = 0; vf < adapter->num_vfs; vf++) { | |
5579 | ciaa = (vf << 16) | 0x80000000; | |
5580 | /* 32 bit read so align, we really want status at offset 6 */ | |
5581 | ciaa |= PCI_COMMAND; | |
5582 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5583 | ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); | |
5584 | ciaa &= 0x7FFFFFFF; | |
5585 | /* disable debug mode asap after reading data */ | |
5586 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5587 | /* Get the upper 16 bits which will be the PCI status reg */ | |
5588 | ciad >>= 16; | |
5589 | if (ciad & PCI_STATUS_REC_MASTER_ABORT) { | |
5590 | netdev_err(netdev, "VF %d Hung DMA\n", vf); | |
5591 | /* Issue VFLR */ | |
5592 | ciaa = (vf << 16) | 0x80000000; | |
5593 | ciaa |= 0xA8; | |
5594 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5595 | ciad = 0x00008000; /* VFLR */ | |
5596 | IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); | |
5597 | ciaa &= 0x7FFFFFFF; | |
5598 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5599 | } | |
5600 | } | |
5601 | } | |
5602 | ||
5603 | #endif | |
7086400d AD |
5604 | /** |
5605 | * ixgbe_service_timer - Timer Call-back | |
5606 | * @data: pointer to adapter cast into an unsigned long | |
5607 | **/ | |
5608 | static void ixgbe_service_timer(unsigned long data) | |
5609 | { | |
5610 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5611 | unsigned long next_event_offset; | |
83c61fa9 | 5612 | bool ready = true; |
7086400d | 5613 | |
6bb78cfb AD |
5614 | /* poll faster when waiting for link */ |
5615 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
5616 | next_event_offset = HZ / 10; | |
5617 | else | |
5618 | next_event_offset = HZ * 2; | |
83c61fa9 | 5619 | |
6bb78cfb | 5620 | #ifdef CONFIG_PCI_IOV |
83c61fa9 GR |
5621 | /* |
5622 | * don't bother with SR-IOV VF DMA hang check if there are | |
5623 | * no VFs or the link is down | |
5624 | */ | |
5625 | if (!adapter->num_vfs || | |
6bb78cfb | 5626 | (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
83c61fa9 | 5627 | goto normal_timer_service; |
83c61fa9 GR |
5628 | |
5629 | /* If we have VFs allocated then we must check for DMA hangs */ | |
5630 | ixgbe_check_for_bad_vf(adapter); | |
5631 | next_event_offset = HZ / 50; | |
5632 | adapter->timer_event_accumulator++; | |
5633 | ||
6bb78cfb | 5634 | if (adapter->timer_event_accumulator >= 100) |
83c61fa9 | 5635 | adapter->timer_event_accumulator = 0; |
7086400d | 5636 | else |
6bb78cfb | 5637 | ready = false; |
7086400d | 5638 | |
6bb78cfb | 5639 | normal_timer_service: |
83c61fa9 | 5640 | #endif |
7086400d AD |
5641 | /* Reset the timer */ |
5642 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
5643 | ||
83c61fa9 GR |
5644 | if (ready) |
5645 | ixgbe_service_event_schedule(adapter); | |
7086400d AD |
5646 | } |
5647 | ||
c83c6cbd AD |
5648 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
5649 | { | |
5650 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
5651 | return; | |
5652 | ||
5653 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
5654 | ||
5655 | /* If we're already down or resetting, just bail */ | |
5656 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5657 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5658 | return; | |
5659 | ||
5660 | ixgbe_dump(adapter); | |
5661 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
5662 | adapter->tx_timeout_count++; | |
5663 | ||
5664 | ixgbe_reinit_locked(adapter); | |
5665 | } | |
5666 | ||
7086400d AD |
5667 | /** |
5668 | * ixgbe_service_task - manages and runs subtasks | |
5669 | * @work: pointer to work_struct containing our data | |
5670 | **/ | |
5671 | static void ixgbe_service_task(struct work_struct *work) | |
5672 | { | |
5673 | struct ixgbe_adapter *adapter = container_of(work, | |
5674 | struct ixgbe_adapter, | |
5675 | service_task); | |
5676 | ||
c83c6cbd | 5677 | ixgbe_reset_subtask(adapter); |
7086400d AD |
5678 | ixgbe_sfp_detection_subtask(adapter); |
5679 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 5680 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 5681 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 5682 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 5683 | ixgbe_check_hang_subtask(adapter); |
7086400d AD |
5684 | |
5685 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
5686 | } |
5687 | ||
fd0db0ed AD |
5688 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
5689 | struct ixgbe_tx_buffer *first, | |
244e27ad | 5690 | u8 *hdr_len) |
897ab156 | 5691 | { |
fd0db0ed | 5692 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5693 | u32 vlan_macip_lens, type_tucmd; |
5694 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 5695 | |
897ab156 AD |
5696 | if (!skb_is_gso(skb)) |
5697 | return 0; | |
9a799d71 | 5698 | |
897ab156 | 5699 | if (skb_header_cloned(skb)) { |
244e27ad | 5700 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
897ab156 AD |
5701 | if (err) |
5702 | return err; | |
9a799d71 | 5703 | } |
9a799d71 | 5704 | |
897ab156 AD |
5705 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
5706 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5707 | ||
244e27ad | 5708 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
897ab156 AD |
5709 | struct iphdr *iph = ip_hdr(skb); |
5710 | iph->tot_len = 0; | |
5711 | iph->check = 0; | |
5712 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5713 | iph->daddr, 0, | |
5714 | IPPROTO_TCP, | |
5715 | 0); | |
5716 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
244e27ad AD |
5717 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5718 | IXGBE_TX_FLAGS_CSUM | | |
5719 | IXGBE_TX_FLAGS_IPV4; | |
897ab156 AD |
5720 | } else if (skb_is_gso_v6(skb)) { |
5721 | ipv6_hdr(skb)->payload_len = 0; | |
5722 | tcp_hdr(skb)->check = | |
5723 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
5724 | &ipv6_hdr(skb)->daddr, | |
5725 | 0, IPPROTO_TCP, 0); | |
244e27ad AD |
5726 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5727 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
5728 | } |
5729 | ||
091a6246 | 5730 | /* compute header lengths */ |
897ab156 AD |
5731 | l4len = tcp_hdrlen(skb); |
5732 | *hdr_len = skb_transport_offset(skb) + l4len; | |
5733 | ||
091a6246 AD |
5734 | /* update gso size and bytecount with header size */ |
5735 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
5736 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
5737 | ||
897ab156 AD |
5738 | /* mss_l4len_id: use 1 as index for TSO */ |
5739 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
5740 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
5741 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
5742 | ||
5743 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
5744 | vlan_macip_lens = skb_network_header_len(skb); | |
5745 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 5746 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
5747 | |
5748 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 5749 | mss_l4len_idx); |
897ab156 AD |
5750 | |
5751 | return 1; | |
5752 | } | |
5753 | ||
244e27ad AD |
5754 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
5755 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 5756 | { |
fd0db0ed | 5757 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5758 | u32 vlan_macip_lens = 0; |
5759 | u32 mss_l4len_idx = 0; | |
5760 | u32 type_tucmd = 0; | |
7ca647bd | 5761 | |
897ab156 | 5762 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
244e27ad AD |
5763 | if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
5764 | !(first->tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
5765 | return; | |
897ab156 AD |
5766 | } else { |
5767 | u8 l4_hdr = 0; | |
244e27ad | 5768 | switch (first->protocol) { |
897ab156 AD |
5769 | case __constant_htons(ETH_P_IP): |
5770 | vlan_macip_lens |= skb_network_header_len(skb); | |
5771 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
5772 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 5773 | break; |
897ab156 AD |
5774 | case __constant_htons(ETH_P_IPV6): |
5775 | vlan_macip_lens |= skb_network_header_len(skb); | |
5776 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
5777 | break; | |
5778 | default: | |
5779 | if (unlikely(net_ratelimit())) { | |
5780 | dev_warn(tx_ring->dev, | |
5781 | "partial checksum but proto=%x!\n", | |
244e27ad | 5782 | first->protocol); |
897ab156 | 5783 | } |
7ca647bd JP |
5784 | break; |
5785 | } | |
897ab156 AD |
5786 | |
5787 | switch (l4_hdr) { | |
7ca647bd | 5788 | case IPPROTO_TCP: |
897ab156 AD |
5789 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
5790 | mss_l4len_idx = tcp_hdrlen(skb) << | |
5791 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
5792 | break; |
5793 | case IPPROTO_SCTP: | |
897ab156 AD |
5794 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
5795 | mss_l4len_idx = sizeof(struct sctphdr) << | |
5796 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5797 | break; | |
5798 | case IPPROTO_UDP: | |
5799 | mss_l4len_idx = sizeof(struct udphdr) << | |
5800 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5801 | break; | |
5802 | default: | |
5803 | if (unlikely(net_ratelimit())) { | |
5804 | dev_warn(tx_ring->dev, | |
5805 | "partial checksum but l4 proto=%x!\n", | |
244e27ad | 5806 | l4_hdr); |
897ab156 | 5807 | } |
7ca647bd JP |
5808 | break; |
5809 | } | |
244e27ad AD |
5810 | |
5811 | /* update TX checksum flag */ | |
5812 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7ca647bd JP |
5813 | } |
5814 | ||
244e27ad | 5815 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
897ab156 | 5816 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 5817 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 5818 | |
897ab156 AD |
5819 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
5820 | type_tucmd, mss_l4len_idx); | |
9a799d71 AK |
5821 | } |
5822 | ||
d3d00239 | 5823 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 5824 | { |
d3d00239 AD |
5825 | /* set type for advanced descriptor with frame checksum insertion */ |
5826 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
5827 | IXGBE_ADVTXD_DCMD_IFCS | | |
5828 | IXGBE_ADVTXD_DCMD_DEXT); | |
9a799d71 | 5829 | |
d3d00239 | 5830 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 5831 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 5832 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 5833 | |
d3d00239 AD |
5834 | /* set segmentation enable bits for TSO/FSO */ |
5835 | #ifdef IXGBE_FCOE | |
93f5b3c1 | 5836 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) |
d3d00239 AD |
5837 | #else |
5838 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
5839 | #endif | |
5840 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 5841 | |
d3d00239 AD |
5842 | return cmd_type; |
5843 | } | |
9a799d71 | 5844 | |
729739b7 AD |
5845 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
5846 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 5847 | { |
93f5b3c1 | 5848 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); |
9a799d71 | 5849 | |
d3d00239 AD |
5850 | /* enable L4 checksum for TSO and TX checksum offload */ |
5851 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5852 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 5853 | |
93f5b3c1 AD |
5854 | /* enble IPv4 checksum for TSO */ |
5855 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
5856 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 5857 | |
93f5b3c1 AD |
5858 | /* use index 1 context for TSO/FSO/FCOE */ |
5859 | #ifdef IXGBE_FCOE | |
5860 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) | |
5861 | #else | |
5862 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
d3d00239 | 5863 | #endif |
93f5b3c1 AD |
5864 | olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); |
5865 | ||
7f9643fd AD |
5866 | /* |
5867 | * Check Context must be set if Tx switch is enabled, which it | |
5868 | * always is for case where virtual functions are running | |
5869 | */ | |
93f5b3c1 AD |
5870 | #ifdef IXGBE_FCOE |
5871 | if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) | |
5872 | #else | |
7f9643fd | 5873 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) |
93f5b3c1 | 5874 | #endif |
7f9643fd AD |
5875 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); |
5876 | ||
729739b7 | 5877 | tx_desc->read.olinfo_status = olinfo_status; |
d3d00239 | 5878 | } |
44df32c5 | 5879 | |
d3d00239 AD |
5880 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
5881 | IXGBE_TXD_CMD_RS) | |
5882 | ||
5883 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 5884 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
5885 | const u8 hdr_len) |
5886 | { | |
729739b7 | 5887 | dma_addr_t dma; |
fd0db0ed | 5888 | struct sk_buff *skb = first->skb; |
729739b7 | 5889 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 5890 | union ixgbe_adv_tx_desc *tx_desc; |
729739b7 | 5891 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
d3d00239 AD |
5892 | unsigned int data_len = skb->data_len; |
5893 | unsigned int size = skb_headlen(skb); | |
729739b7 | 5894 | unsigned int paylen = skb->len - hdr_len; |
244e27ad | 5895 | u32 tx_flags = first->tx_flags; |
729739b7 | 5896 | __le32 cmd_type; |
d3d00239 | 5897 | u16 i = tx_ring->next_to_use; |
d3d00239 | 5898 | |
729739b7 AD |
5899 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
5900 | ||
5901 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen); | |
5902 | cmd_type = ixgbe_tx_cmd_type(tx_flags); | |
5903 | ||
d3d00239 AD |
5904 | #ifdef IXGBE_FCOE |
5905 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 5906 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
5907 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
5908 | data_len = 0; | |
729739b7 AD |
5909 | } else { |
5910 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
5911 | } |
5912 | } | |
44df32c5 | 5913 | |
d3d00239 | 5914 | #endif |
729739b7 AD |
5915 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
5916 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 5917 | goto dma_error; |
8ad494b0 | 5918 | |
729739b7 AD |
5919 | /* record length, and DMA address */ |
5920 | dma_unmap_len_set(first, len, size); | |
5921 | dma_unmap_addr_set(first, dma, dma); | |
9a799d71 | 5922 | |
729739b7 | 5923 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
e5a43549 | 5924 | |
d3d00239 | 5925 | for (;;) { |
729739b7 | 5926 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 AD |
5927 | tx_desc->read.cmd_type_len = |
5928 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
e5a43549 | 5929 | |
d3d00239 | 5930 | i++; |
729739b7 | 5931 | tx_desc++; |
d3d00239 | 5932 | if (i == tx_ring->count) { |
e4f74028 | 5933 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
5934 | i = 0; |
5935 | } | |
729739b7 AD |
5936 | |
5937 | dma += IXGBE_MAX_DATA_PER_TXD; | |
5938 | size -= IXGBE_MAX_DATA_PER_TXD; | |
5939 | ||
5940 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
5941 | tx_desc->read.olinfo_status = 0; | |
d3d00239 | 5942 | } |
e5a43549 | 5943 | |
729739b7 AD |
5944 | if (likely(!data_len)) |
5945 | break; | |
9a799d71 | 5946 | |
f43f313e BG |
5947 | if (unlikely(skb->no_fcs)) |
5948 | cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS)); | |
d3d00239 | 5949 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9a799d71 | 5950 | |
729739b7 AD |
5951 | i++; |
5952 | tx_desc++; | |
5953 | if (i == tx_ring->count) { | |
5954 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
5955 | i = 0; | |
5956 | } | |
9a799d71 | 5957 | |
d3d00239 | 5958 | #ifdef IXGBE_FCOE |
9e903e08 | 5959 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 5960 | #else |
9e903e08 | 5961 | size = skb_frag_size(frag); |
d3d00239 AD |
5962 | #endif |
5963 | data_len -= size; | |
9a799d71 | 5964 | |
729739b7 AD |
5965 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
5966 | DMA_TO_DEVICE); | |
5967 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 5968 | goto dma_error; |
9a799d71 | 5969 | |
729739b7 AD |
5970 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
5971 | dma_unmap_len_set(tx_buffer, len, size); | |
5972 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
9a799d71 | 5973 | |
729739b7 AD |
5974 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
5975 | tx_desc->read.olinfo_status = 0; | |
9a799d71 | 5976 | |
729739b7 AD |
5977 | frag++; |
5978 | } | |
9a799d71 | 5979 | |
729739b7 AD |
5980 | /* write last descriptor with RS and EOP bits */ |
5981 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); | |
5982 | tx_desc->read.cmd_type_len = cmd_type; | |
eacd73f7 | 5983 | |
091a6246 | 5984 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 5985 | |
d3d00239 AD |
5986 | /* set the timestamp */ |
5987 | first->time_stamp = jiffies; | |
9a799d71 AK |
5988 | |
5989 | /* | |
729739b7 AD |
5990 | * Force memory writes to complete before letting h/w know there |
5991 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
5992 | * memory model archs, such as IA-64). | |
5993 | * | |
5994 | * We also need this memory barrier to make certain all of the | |
5995 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
5996 | */ |
5997 | wmb(); | |
5998 | ||
d3d00239 AD |
5999 | /* set next_to_watch value indicating a packet is present */ |
6000 | first->next_to_watch = tx_desc; | |
6001 | ||
729739b7 AD |
6002 | i++; |
6003 | if (i == tx_ring->count) | |
6004 | i = 0; | |
6005 | ||
6006 | tx_ring->next_to_use = i; | |
6007 | ||
d3d00239 | 6008 | /* notify HW of packet */ |
84ea2591 | 6009 | writel(i, tx_ring->tail); |
d3d00239 AD |
6010 | |
6011 | return; | |
6012 | dma_error: | |
729739b7 | 6013 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
6014 | |
6015 | /* clear dma mappings for failed tx_buffer_info map */ | |
6016 | for (;;) { | |
729739b7 AD |
6017 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6018 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
6019 | if (tx_buffer == first) | |
d3d00239 AD |
6020 | break; |
6021 | if (i == 0) | |
6022 | i = tx_ring->count; | |
6023 | i--; | |
6024 | } | |
6025 | ||
d3d00239 | 6026 | tx_ring->next_to_use = i; |
9a799d71 AK |
6027 | } |
6028 | ||
fd0db0ed | 6029 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 6030 | struct ixgbe_tx_buffer *first) |
69830529 AD |
6031 | { |
6032 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6033 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6034 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6035 | union { | |
6036 | unsigned char *network; | |
6037 | struct iphdr *ipv4; | |
6038 | struct ipv6hdr *ipv6; | |
6039 | } hdr; | |
ee9e0f0b | 6040 | struct tcphdr *th; |
905e4a41 | 6041 | __be16 vlan_id; |
c4cf55e5 | 6042 | |
69830529 AD |
6043 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6044 | if (!q_vector) | |
6045 | return; | |
6046 | ||
6047 | /* do nothing if sampling is disabled */ | |
6048 | if (!ring->atr_sample_rate) | |
d3ead241 | 6049 | return; |
c4cf55e5 | 6050 | |
69830529 | 6051 | ring->atr_count++; |
c4cf55e5 | 6052 | |
69830529 | 6053 | /* snag network header to get L4 type and address */ |
fd0db0ed | 6054 | hdr.network = skb_network_header(first->skb); |
69830529 AD |
6055 | |
6056 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
244e27ad | 6057 | if ((first->protocol != __constant_htons(ETH_P_IPV6) || |
69830529 | 6058 | hdr.ipv6->nexthdr != IPPROTO_TCP) && |
244e27ad | 6059 | (first->protocol != __constant_htons(ETH_P_IP) || |
69830529 AD |
6060 | hdr.ipv4->protocol != IPPROTO_TCP)) |
6061 | return; | |
ee9e0f0b | 6062 | |
fd0db0ed | 6063 | th = tcp_hdr(first->skb); |
c4cf55e5 | 6064 | |
66f32a8b AD |
6065 | /* skip this packet since it is invalid or the socket is closing */ |
6066 | if (!th || th->fin) | |
69830529 AD |
6067 | return; |
6068 | ||
6069 | /* sample on all syn packets or once every atr sample count */ | |
6070 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6071 | return; | |
6072 | ||
6073 | /* reset sample count */ | |
6074 | ring->atr_count = 0; | |
6075 | ||
244e27ad | 6076 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
6077 | |
6078 | /* | |
6079 | * src and dst are inverted, think how the receiver sees them | |
6080 | * | |
6081 | * The input is broken into two sections, a non-compressed section | |
6082 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6083 | * is XORed together and stored in the compressed dword. | |
6084 | */ | |
6085 | input.formatted.vlan_id = vlan_id; | |
6086 | ||
6087 | /* | |
6088 | * since src port and flex bytes occupy the same word XOR them together | |
6089 | * and write the value to source port portion of compressed dword | |
6090 | */ | |
244e27ad | 6091 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6092 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6093 | else | |
244e27ad | 6094 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
6095 | common.port.dst ^= th->source; |
6096 | ||
244e27ad | 6097 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
69830529 AD |
6098 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
6099 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6100 | } else { | |
6101 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6102 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6103 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6104 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6105 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6106 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6107 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6108 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6109 | hdr.ipv6->daddr.s6_addr32[3]; | |
6110 | } | |
c4cf55e5 PWJ |
6111 | |
6112 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6113 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6114 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6115 | } |
6116 | ||
63544e9c | 6117 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6118 | { |
fc77dc3c | 6119 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6120 | /* Herbert's original patch had: |
6121 | * smp_mb__after_netif_stop_queue(); | |
6122 | * but since that doesn't exist yet, just open code it. */ | |
6123 | smp_mb(); | |
6124 | ||
6125 | /* We need to check again in a case another CPU has just | |
6126 | * made room available. */ | |
7d4987de | 6127 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
6128 | return -EBUSY; |
6129 | ||
6130 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6131 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6132 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6133 | return 0; |
6134 | } | |
6135 | ||
82d4e46e | 6136 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6137 | { |
7d4987de | 6138 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 6139 | return 0; |
fc77dc3c | 6140 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6141 | } |
6142 | ||
09a3b1f8 SH |
6143 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6144 | { | |
6145 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
6146 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
6147 | smp_processor_id(); | |
56075a98 | 6148 | #ifdef IXGBE_FCOE |
6440752c | 6149 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 6150 | |
e5b64635 JF |
6151 | if (((protocol == htons(ETH_P_FCOE)) || |
6152 | (protocol == htons(ETH_P_FIP))) && | |
6153 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
6154 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
6155 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
6156 | return txq; | |
56075a98 JF |
6157 | } |
6158 | #endif | |
6159 | ||
fdd3d631 KK |
6160 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6161 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6162 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6163 | return txq; |
fdd3d631 | 6164 | } |
c4cf55e5 | 6165 | |
09a3b1f8 SH |
6166 | return skb_tx_hash(dev, skb); |
6167 | } | |
6168 | ||
fc77dc3c | 6169 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6170 | struct ixgbe_adapter *adapter, |
6171 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6172 | { |
d3d00239 | 6173 | struct ixgbe_tx_buffer *first; |
5f715823 | 6174 | int tso; |
d3d00239 | 6175 | u32 tx_flags = 0; |
a535c30e AD |
6176 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
6177 | unsigned short f; | |
6178 | #endif | |
a535c30e | 6179 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 6180 | __be16 protocol = skb->protocol; |
63544e9c | 6181 | u8 hdr_len = 0; |
5e09a105 | 6182 | |
a535c30e AD |
6183 | /* |
6184 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 6185 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
6186 | * + 2 desc gap to keep tail from touching head, |
6187 | * + 1 desc for context descriptor, | |
6188 | * otherwise try next time | |
6189 | */ | |
6190 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
6191 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
6192 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
6193 | #else | |
6194 | count += skb_shinfo(skb)->nr_frags; | |
6195 | #endif | |
6196 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
6197 | tx_ring->tx_stats.tx_busy++; | |
6198 | return NETDEV_TX_BUSY; | |
6199 | } | |
6200 | ||
fd0db0ed AD |
6201 | /* record the location of the first descriptor for this packet */ |
6202 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
6203 | first->skb = skb; | |
091a6246 AD |
6204 | first->bytecount = skb->len; |
6205 | first->gso_segs = 1; | |
fd0db0ed | 6206 | |
66f32a8b | 6207 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 6208 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
6209 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
6210 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
6211 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
6212 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6213 | struct vlan_hdr *vhdr, _vhdr; | |
6214 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
6215 | if (!vhdr) | |
6216 | goto out_drop; | |
6217 | ||
6218 | protocol = vhdr->h_vlan_encapsulated_proto; | |
9e0c5648 AD |
6219 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
6220 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
6221 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
6222 | } | |
6223 | ||
9e0c5648 AD |
6224 | #ifdef CONFIG_PCI_IOV |
6225 | /* | |
6226 | * Use the l2switch_enable flag - would be false if the DMA | |
6227 | * Tx switch had been disabled. | |
6228 | */ | |
6229 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6230 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
6231 | ||
6232 | #endif | |
32701dc2 | 6233 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 6234 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
6235 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
6236 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 6237 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
6238 | tx_flags |= (skb->priority & 0x7) << |
6239 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
6240 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
6241 | struct vlan_ethhdr *vhdr; | |
6242 | if (skb_header_cloned(skb) && | |
6243 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
6244 | goto out_drop; | |
6245 | vhdr = (struct vlan_ethhdr *)skb->data; | |
6246 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
6247 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6248 | } else { | |
6249 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 6250 | } |
9a799d71 | 6251 | } |
eacd73f7 | 6252 | |
244e27ad AD |
6253 | /* record initial flags and protocol */ |
6254 | first->tx_flags = tx_flags; | |
6255 | first->protocol = protocol; | |
6256 | ||
eacd73f7 | 6257 | #ifdef IXGBE_FCOE |
66f32a8b AD |
6258 | /* setup tx offload for FCoE */ |
6259 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
6260 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
244e27ad | 6261 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
6262 | if (tso < 0) |
6263 | goto out_drop; | |
9a799d71 | 6264 | |
66f32a8b | 6265 | goto xmit_fcoe; |
eacd73f7 | 6266 | } |
9a799d71 | 6267 | |
66f32a8b | 6268 | #endif /* IXGBE_FCOE */ |
244e27ad | 6269 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 6270 | if (tso < 0) |
897ab156 | 6271 | goto out_drop; |
244e27ad AD |
6272 | else if (!tso) |
6273 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
6274 | |
6275 | /* add the ATR filter if ATR is on */ | |
6276 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 6277 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
6278 | |
6279 | #ifdef IXGBE_FCOE | |
6280 | xmit_fcoe: | |
6281 | #endif /* IXGBE_FCOE */ | |
244e27ad | 6282 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 AD |
6283 | |
6284 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
6285 | |
6286 | return NETDEV_TX_OK; | |
897ab156 AD |
6287 | |
6288 | out_drop: | |
fd0db0ed AD |
6289 | dev_kfree_skb_any(first->skb); |
6290 | first->skb = NULL; | |
6291 | ||
897ab156 | 6292 | return NETDEV_TX_OK; |
9a799d71 AK |
6293 | } |
6294 | ||
a50c29dd AD |
6295 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
6296 | struct net_device *netdev) | |
84418e3b AD |
6297 | { |
6298 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6299 | struct ixgbe_ring *tx_ring; | |
6300 | ||
a50c29dd AD |
6301 | if (skb->len <= 0) { |
6302 | dev_kfree_skb_any(skb); | |
6303 | return NETDEV_TX_OK; | |
6304 | } | |
6305 | ||
6306 | /* | |
6307 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
6308 | * in order to meet this minimum size requirement. | |
6309 | */ | |
6310 | if (skb->len < 17) { | |
6311 | if (skb_padto(skb, 17)) | |
6312 | return NETDEV_TX_OK; | |
6313 | skb->len = 17; | |
6314 | } | |
6315 | ||
84418e3b | 6316 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
fc77dc3c | 6317 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6318 | } |
6319 | ||
9a799d71 AK |
6320 | /** |
6321 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6322 | * @netdev: network interface device structure | |
6323 | * @p: pointer to an address structure | |
6324 | * | |
6325 | * Returns 0 on success, negative on failure | |
6326 | **/ | |
6327 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6328 | { | |
6329 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6330 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6331 | struct sockaddr *addr = p; |
6332 | ||
6333 | if (!is_valid_ether_addr(addr->sa_data)) | |
6334 | return -EADDRNOTAVAIL; | |
6335 | ||
6336 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6337 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6338 | |
1cdd1ec8 GR |
6339 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6340 | IXGBE_RAH_AV); | |
9a799d71 AK |
6341 | |
6342 | return 0; | |
6343 | } | |
6344 | ||
6b73e10d BH |
6345 | static int |
6346 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6347 | { | |
6348 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6349 | struct ixgbe_hw *hw = &adapter->hw; | |
6350 | u16 value; | |
6351 | int rc; | |
6352 | ||
6353 | if (prtad != hw->phy.mdio.prtad) | |
6354 | return -EINVAL; | |
6355 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6356 | if (!rc) | |
6357 | rc = value; | |
6358 | return rc; | |
6359 | } | |
6360 | ||
6361 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6362 | u16 addr, u16 value) | |
6363 | { | |
6364 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6365 | struct ixgbe_hw *hw = &adapter->hw; | |
6366 | ||
6367 | if (prtad != hw->phy.mdio.prtad) | |
6368 | return -EINVAL; | |
6369 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6370 | } | |
6371 | ||
6372 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6373 | { | |
6374 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6375 | ||
6376 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6377 | } | |
6378 | ||
0365e6e4 PW |
6379 | /** |
6380 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6381 | * netdev->dev_addrs |
0365e6e4 PW |
6382 | * @netdev: network interface device structure |
6383 | * | |
6384 | * Returns non-zero on failure | |
6385 | **/ | |
6386 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6387 | { | |
6388 | int err = 0; | |
6389 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6390 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6391 | ||
6392 | if (is_valid_ether_addr(mac->san_addr)) { | |
6393 | rtnl_lock(); | |
6394 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6395 | rtnl_unlock(); | |
6396 | } | |
6397 | return err; | |
6398 | } | |
6399 | ||
6400 | /** | |
6401 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6402 | * netdev->dev_addrs |
0365e6e4 PW |
6403 | * @netdev: network interface device structure |
6404 | * | |
6405 | * Returns non-zero on failure | |
6406 | **/ | |
6407 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6408 | { | |
6409 | int err = 0; | |
6410 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6411 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6412 | ||
6413 | if (is_valid_ether_addr(mac->san_addr)) { | |
6414 | rtnl_lock(); | |
6415 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6416 | rtnl_unlock(); | |
6417 | } | |
6418 | return err; | |
6419 | } | |
6420 | ||
9a799d71 AK |
6421 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6422 | /* | |
6423 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6424 | * without having to re-enable interrupts. It's not called while | |
6425 | * the interrupt routine is executing. | |
6426 | */ | |
6427 | static void ixgbe_netpoll(struct net_device *netdev) | |
6428 | { | |
6429 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6430 | int i; |
9a799d71 | 6431 | |
1a647bd2 AD |
6432 | /* if interface is down do nothing */ |
6433 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6434 | return; | |
6435 | ||
9a799d71 | 6436 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
6437 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
6438 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
6439 | for (i = 0; i < num_q_vectors; i++) { | |
6440 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
4ff7fb12 | 6441 | ixgbe_msix_clean_rings(0, q_vector); |
8f9a7167 PWJ |
6442 | } |
6443 | } else { | |
6444 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6445 | } | |
9a799d71 | 6446 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 | 6447 | } |
9a799d71 | 6448 | |
581330ba | 6449 | #endif |
de1036b1 ED |
6450 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6451 | struct rtnl_link_stats64 *stats) | |
6452 | { | |
6453 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6454 | int i; | |
6455 | ||
1a51502b | 6456 | rcu_read_lock(); |
de1036b1 | 6457 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6458 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6459 | u64 bytes, packets; |
6460 | unsigned int start; | |
6461 | ||
1a51502b ED |
6462 | if (ring) { |
6463 | do { | |
6464 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6465 | packets = ring->stats.packets; | |
6466 | bytes = ring->stats.bytes; | |
6467 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6468 | stats->rx_packets += packets; | |
6469 | stats->rx_bytes += bytes; | |
6470 | } | |
de1036b1 | 6471 | } |
1ac9ad13 ED |
6472 | |
6473 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6474 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
6475 | u64 bytes, packets; | |
6476 | unsigned int start; | |
6477 | ||
6478 | if (ring) { | |
6479 | do { | |
6480 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6481 | packets = ring->stats.packets; | |
6482 | bytes = ring->stats.bytes; | |
6483 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6484 | stats->tx_packets += packets; | |
6485 | stats->tx_bytes += bytes; | |
6486 | } | |
6487 | } | |
1a51502b | 6488 | rcu_read_unlock(); |
de1036b1 ED |
6489 | /* following stats updated by ixgbe_watchdog_task() */ |
6490 | stats->multicast = netdev->stats.multicast; | |
6491 | stats->rx_errors = netdev->stats.rx_errors; | |
6492 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6493 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6494 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6495 | return stats; | |
6496 | } | |
6497 | ||
8af3c33f | 6498 | #ifdef CONFIG_IXGBE_DCB |
8b1c0b24 JF |
6499 | /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. |
6500 | * #adapter: pointer to ixgbe_adapter | |
6501 | * @tc: number of traffic classes currently enabled | |
6502 | * | |
6503 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
6504 | * 802.1Q priority maps to a packet buffer that exists. | |
6505 | */ | |
6506 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
6507 | { | |
6508 | struct ixgbe_hw *hw = &adapter->hw; | |
6509 | u32 reg, rsave; | |
6510 | int i; | |
6511 | ||
6512 | /* 82598 have a static priority to TC mapping that can not | |
6513 | * be changed so no validation is needed. | |
6514 | */ | |
6515 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6516 | return; | |
6517 | ||
6518 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
6519 | rsave = reg; | |
6520 | ||
6521 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
6522 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
6523 | ||
6524 | /* If up2tc is out of bounds default to zero */ | |
6525 | if (up2tc > tc) | |
6526 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
6527 | } | |
6528 | ||
6529 | if (reg != rsave) | |
6530 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
6531 | ||
6532 | return; | |
6533 | } | |
6534 | ||
8b1c0b24 JF |
6535 | /* ixgbe_setup_tc - routine to configure net_device for multiple traffic |
6536 | * classes. | |
6537 | * | |
6538 | * @netdev: net device to configure | |
6539 | * @tc: number of traffic classes to enable | |
6540 | */ | |
6541 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
6542 | { | |
8b1c0b24 JF |
6543 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
6544 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 6545 | |
e7589eab JF |
6546 | /* Multiple traffic classes requires multiple queues */ |
6547 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { | |
6548 | e_err(drv, "Enable failed, needs MSI-X\n"); | |
6549 | return -EINVAL; | |
6550 | } | |
8b1c0b24 JF |
6551 | |
6552 | /* Hardware supports up to 8 traffic classes */ | |
4de2a022 | 6553 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || |
581330ba AD |
6554 | (hw->mac.type == ixgbe_mac_82598EB && |
6555 | tc < MAX_TRAFFIC_CLASS)) | |
8b1c0b24 JF |
6556 | return -EINVAL; |
6557 | ||
6558 | /* Hardware has to reinitialize queues and interrupts to | |
52f33af8 | 6559 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
6560 | * hardware is not flexible enough to do this dynamically. |
6561 | */ | |
6562 | if (netif_running(dev)) | |
6563 | ixgbe_close(dev); | |
6564 | ixgbe_clear_interrupt_scheme(adapter); | |
6565 | ||
e7589eab | 6566 | if (tc) { |
8b1c0b24 | 6567 | netdev_set_num_tc(dev, tc); |
e7589eab | 6568 | adapter->last_lfc_mode = adapter->hw.fc.current_mode; |
e7589eab JF |
6569 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
6570 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6571 | ||
6572 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
6573 | adapter->hw.fc.requested_mode = ixgbe_fc_none; | |
6574 | } else { | |
8b1c0b24 | 6575 | netdev_reset_tc(dev); |
e7589eab JF |
6576 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; |
6577 | ||
6578 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
6579 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6580 | ||
6581 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
6582 | adapter->dcb_cfg.pfc_mode_enable = false; | |
6583 | } | |
6584 | ||
8b1c0b24 JF |
6585 | ixgbe_init_interrupt_scheme(adapter); |
6586 | ixgbe_validate_rtr(adapter, tc); | |
6587 | if (netif_running(dev)) | |
6588 | ixgbe_open(dev); | |
6589 | ||
6590 | return 0; | |
6591 | } | |
de1036b1 | 6592 | |
8af3c33f | 6593 | #endif /* CONFIG_IXGBE_DCB */ |
082757af DS |
6594 | void ixgbe_do_reset(struct net_device *netdev) |
6595 | { | |
6596 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6597 | ||
6598 | if (netif_running(netdev)) | |
6599 | ixgbe_reinit_locked(adapter); | |
6600 | else | |
6601 | ixgbe_reset(adapter); | |
6602 | } | |
6603 | ||
c8f44aff | 6604 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 6605 | netdev_features_t features) |
082757af DS |
6606 | { |
6607 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6608 | ||
6609 | #ifdef CONFIG_DCB | |
6610 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
567d2de2 | 6611 | features &= ~NETIF_F_HW_VLAN_RX; |
082757af DS |
6612 | #endif |
6613 | ||
6614 | /* return error if RXHASH is being enabled when RSS is not supported */ | |
6615 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) | |
567d2de2 | 6616 | features &= ~NETIF_F_RXHASH; |
082757af DS |
6617 | |
6618 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ | |
567d2de2 AD |
6619 | if (!(features & NETIF_F_RXCSUM)) |
6620 | features &= ~NETIF_F_LRO; | |
082757af | 6621 | |
567d2de2 AD |
6622 | /* Turn off LRO if not RSC capable */ |
6623 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
6624 | features &= ~NETIF_F_LRO; | |
6625 | ||
082757af | 6626 | |
567d2de2 | 6627 | return features; |
082757af DS |
6628 | } |
6629 | ||
c8f44aff | 6630 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 6631 | netdev_features_t features) |
082757af DS |
6632 | { |
6633 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 6634 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
6635 | bool need_reset = false; |
6636 | ||
082757af | 6637 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
6638 | if (!(features & NETIF_F_LRO)) { |
6639 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 6640 | need_reset = true; |
567d2de2 AD |
6641 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
6642 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
6643 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
6644 | if (adapter->rx_itr_setting == 1 || | |
6645 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
6646 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
6647 | need_reset = true; | |
6648 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
6649 | e_info(probe, "rx-usecs set too low, " | |
6650 | "disabling RSC\n"); | |
082757af DS |
6651 | } |
6652 | } | |
6653 | ||
6654 | /* | |
6655 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
6656 | * the state changed, we need to reset. | |
6657 | */ | |
567d2de2 AD |
6658 | if (!(features & NETIF_F_NTUPLE)) { |
6659 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
6660 | /* turn off Flow Director, set ATR and reset */ | |
6661 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && | |
6662 | !(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
6663 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
082757af DS |
6664 | need_reset = true; |
6665 | } | |
082757af | 6666 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; |
567d2de2 AD |
6667 | } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { |
6668 | /* turn off ATR, enable perfect filters and reset */ | |
6669 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6670 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
082757af DS |
6671 | need_reset = true; |
6672 | } | |
6673 | ||
3f2d1c0f BG |
6674 | if (changed & NETIF_F_RXALL) |
6675 | need_reset = true; | |
6676 | ||
567d2de2 | 6677 | netdev->features = features; |
082757af DS |
6678 | if (need_reset) |
6679 | ixgbe_do_reset(netdev); | |
6680 | ||
6681 | return 0; | |
082757af DS |
6682 | } |
6683 | ||
0f4b0add JF |
6684 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, |
6685 | struct net_device *dev, | |
6686 | unsigned char *addr, | |
6687 | u16 flags) | |
6688 | { | |
6689 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6690 | int err = -EOPNOTSUPP; | |
6691 | ||
6692 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6693 | pr_info("%s: FDB only supports static addresses\n", | |
6694 | ixgbe_driver_name); | |
6695 | return -EINVAL; | |
6696 | } | |
6697 | ||
6698 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6699 | if (is_unicast_ether_addr(addr)) | |
6700 | err = dev_uc_add_excl(dev, addr); | |
6701 | else if (is_multicast_ether_addr(addr)) | |
6702 | err = dev_mc_add_excl(dev, addr); | |
6703 | else | |
6704 | err = -EINVAL; | |
6705 | } | |
6706 | ||
6707 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
6708 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
6709 | err = 0; | |
6710 | ||
6711 | return err; | |
6712 | } | |
6713 | ||
6714 | static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, | |
6715 | struct net_device *dev, | |
6716 | unsigned char *addr) | |
6717 | { | |
6718 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6719 | int err = -EOPNOTSUPP; | |
6720 | ||
6721 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6722 | pr_info("%s: FDB only supports static addresses\n", | |
6723 | ixgbe_driver_name); | |
6724 | return -EINVAL; | |
6725 | } | |
6726 | ||
6727 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6728 | if (is_unicast_ether_addr(addr)) | |
6729 | err = dev_uc_del(dev, addr); | |
6730 | else if (is_multicast_ether_addr(addr)) | |
6731 | err = dev_mc_del(dev, addr); | |
6732 | else | |
6733 | err = -EINVAL; | |
6734 | } | |
6735 | ||
6736 | return err; | |
6737 | } | |
6738 | ||
6739 | static int ixgbe_ndo_fdb_dump(struct sk_buff *skb, | |
6740 | struct netlink_callback *cb, | |
6741 | struct net_device *dev, | |
6742 | int idx) | |
6743 | { | |
6744 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6745 | ||
6746 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6747 | idx = ndo_dflt_fdb_dump(skb, cb, dev, idx); | |
6748 | ||
6749 | return idx; | |
6750 | } | |
6751 | ||
0edc3527 | 6752 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 6753 | .ndo_open = ixgbe_open, |
0edc3527 | 6754 | .ndo_stop = ixgbe_close, |
00829823 | 6755 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 6756 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 6757 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
6758 | .ndo_validate_addr = eth_validate_addr, |
6759 | .ndo_set_mac_address = ixgbe_set_mac, | |
6760 | .ndo_change_mtu = ixgbe_change_mtu, | |
6761 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
6762 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
6763 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 6764 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
6765 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
6766 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
6767 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
581330ba | 6768 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
7f01648a | 6769 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 6770 | .ndo_get_stats64 = ixgbe_get_stats64, |
8af3c33f | 6771 | #ifdef CONFIG_IXGBE_DCB |
24095aa3 | 6772 | .ndo_setup_tc = ixgbe_setup_tc, |
8af3c33f | 6773 | #endif |
0edc3527 SH |
6774 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6775 | .ndo_poll_controller = ixgbe_netpoll, | |
6776 | #endif | |
332d4a7d YZ |
6777 | #ifdef IXGBE_FCOE |
6778 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 6779 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 6780 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
6781 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
6782 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 6783 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 6784 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 6785 | #endif /* IXGBE_FCOE */ |
082757af DS |
6786 | .ndo_set_features = ixgbe_set_features, |
6787 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add JF |
6788 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
6789 | .ndo_fdb_del = ixgbe_ndo_fdb_del, | |
6790 | .ndo_fdb_dump = ixgbe_ndo_fdb_dump, | |
0edc3527 SH |
6791 | }; |
6792 | ||
1cdd1ec8 | 6793 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
567d2de2 | 6794 | const struct ixgbe_info *ii) |
1cdd1ec8 GR |
6795 | { |
6796 | #ifdef CONFIG_PCI_IOV | |
6797 | struct ixgbe_hw *hw = &adapter->hw; | |
1cdd1ec8 | 6798 | |
c6bda30a | 6799 | if (hw->mac.type == ixgbe_mac_82598EB) |
1cdd1ec8 GR |
6800 | return; |
6801 | ||
6802 | /* The 82599 supports up to 64 VFs per physical function | |
6803 | * but this implementation limits allocation to 63 so that | |
6804 | * basic networking resources are still available to the | |
6805 | * physical function | |
6806 | */ | |
6807 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
c6bda30a | 6808 | ixgbe_enable_sriov(adapter, ii); |
1cdd1ec8 GR |
6809 | #endif /* CONFIG_PCI_IOV */ |
6810 | } | |
6811 | ||
9a799d71 AK |
6812 | /** |
6813 | * ixgbe_probe - Device Initialization Routine | |
6814 | * @pdev: PCI device information struct | |
6815 | * @ent: entry in ixgbe_pci_tbl | |
6816 | * | |
6817 | * Returns 0 on success, negative on failure | |
6818 | * | |
6819 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
6820 | * The OS initialization, configuring of the adapter private structure, | |
6821 | * and a hardware reset occur. | |
6822 | **/ | |
6823 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 6824 | const struct pci_device_id *ent) |
9a799d71 AK |
6825 | { |
6826 | struct net_device *netdev; | |
6827 | struct ixgbe_adapter *adapter = NULL; | |
6828 | struct ixgbe_hw *hw; | |
6829 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
6830 | static int cards_found; |
6831 | int i, err, pci_using_dac; | |
289700db | 6832 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 6833 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
6834 | #ifdef IXGBE_FCOE |
6835 | u16 device_caps; | |
6836 | #endif | |
289700db | 6837 | u32 eec; |
c23f5b6b | 6838 | u16 wol_cap; |
9a799d71 | 6839 | |
bded64a7 AG |
6840 | /* Catch broken hardware that put the wrong VF device ID in |
6841 | * the PCIe SR-IOV capability. | |
6842 | */ | |
6843 | if (pdev->is_virtfn) { | |
6844 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
6845 | pci_name(pdev), pdev->vendor, pdev->device); | |
6846 | return -EINVAL; | |
6847 | } | |
6848 | ||
9ce77666 | 6849 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
6850 | if (err) |
6851 | return err; | |
6852 | ||
1b507730 NN |
6853 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
6854 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
6855 | pci_using_dac = 1; |
6856 | } else { | |
1b507730 | 6857 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 6858 | if (err) { |
1b507730 NN |
6859 | err = dma_set_coherent_mask(&pdev->dev, |
6860 | DMA_BIT_MASK(32)); | |
9a799d71 | 6861 | if (err) { |
b8bc0421 DC |
6862 | dev_err(&pdev->dev, |
6863 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
6864 | goto err_dma; |
6865 | } | |
6866 | } | |
6867 | pci_using_dac = 0; | |
6868 | } | |
6869 | ||
9ce77666 | 6870 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 6871 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 6872 | if (err) { |
b8bc0421 DC |
6873 | dev_err(&pdev->dev, |
6874 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
6875 | goto err_pci_reg; |
6876 | } | |
6877 | ||
19d5afd4 | 6878 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 6879 | |
9a799d71 | 6880 | pci_set_master(pdev); |
fb3b27bc | 6881 | pci_save_state(pdev); |
9a799d71 | 6882 | |
e901acd6 JF |
6883 | #ifdef CONFIG_IXGBE_DCB |
6884 | indices *= MAX_TRAFFIC_CLASS; | |
6885 | #endif | |
6886 | ||
c85a2618 JF |
6887 | if (ii->mac == ixgbe_mac_82598EB) |
6888 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
6889 | else | |
6890 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
6891 | ||
e901acd6 | 6892 | #ifdef IXGBE_FCOE |
c85a2618 JF |
6893 | indices += min_t(unsigned int, num_possible_cpus(), |
6894 | IXGBE_MAX_FCOE_INDICES); | |
6895 | #endif | |
c85a2618 | 6896 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
6897 | if (!netdev) { |
6898 | err = -ENOMEM; | |
6899 | goto err_alloc_etherdev; | |
6900 | } | |
6901 | ||
9a799d71 AK |
6902 | SET_NETDEV_DEV(netdev, &pdev->dev); |
6903 | ||
9a799d71 | 6904 | adapter = netdev_priv(netdev); |
c60fbb00 | 6905 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
6906 | |
6907 | adapter->netdev = netdev; | |
6908 | adapter->pdev = pdev; | |
6909 | hw = &adapter->hw; | |
6910 | hw->back = adapter; | |
b3f4d599 | 6911 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 6912 | |
05857980 | 6913 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 6914 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
6915 | if (!hw->hw_addr) { |
6916 | err = -EIO; | |
6917 | goto err_ioremap; | |
6918 | } | |
6919 | ||
6920 | for (i = 1; i <= 5; i++) { | |
6921 | if (pci_resource_len(pdev, i) == 0) | |
6922 | continue; | |
6923 | } | |
6924 | ||
0edc3527 | 6925 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 6926 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 6927 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 6928 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 6929 | |
9a799d71 AK |
6930 | adapter->bd_number = cards_found; |
6931 | ||
9a799d71 AK |
6932 | /* Setup hw api */ |
6933 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 6934 | hw->mac.type = ii->mac; |
9a799d71 | 6935 | |
c44ade9e JB |
6936 | /* EEPROM */ |
6937 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
6938 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
6939 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
6940 | if (!(eec & (1 << 8))) | |
6941 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
6942 | ||
6943 | /* PHY */ | |
6944 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 6945 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
6946 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
6947 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
6948 | hw->phy.mdio.mmds = 0; | |
6949 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
6950 | hw->phy.mdio.dev = netdev; | |
6951 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
6952 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 6953 | |
8ca783ab | 6954 | ii->get_invariants(hw); |
9a799d71 AK |
6955 | |
6956 | /* setup the private structure */ | |
6957 | err = ixgbe_sw_init(adapter); | |
6958 | if (err) | |
6959 | goto err_sw_init; | |
6960 | ||
e86bff0e | 6961 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
6962 | switch (adapter->hw.mac.type) { |
6963 | case ixgbe_mac_82599EB: | |
6964 | case ixgbe_mac_X540: | |
e86bff0e | 6965 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
6966 | break; |
6967 | default: | |
6968 | break; | |
6969 | } | |
e86bff0e | 6970 | |
bf069c97 DS |
6971 | /* |
6972 | * If there is a fan on this device and it has failed log the | |
6973 | * failure. | |
6974 | */ | |
6975 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
6976 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
6977 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 6978 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
6979 | } |
6980 | ||
8ef78adc PWJ |
6981 | if (allow_unsupported_sfp) |
6982 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
6983 | ||
c44ade9e | 6984 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 6985 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 6986 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 6987 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
6988 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
6989 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
6990 | err = 0; |
6991 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 6992 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
6993 | "module type was detected.\n"); |
6994 | e_dev_err("Reload the driver after installing a supported " | |
6995 | "module.\n"); | |
04f165ef PW |
6996 | goto err_sw_init; |
6997 | } else if (err) { | |
849c4542 | 6998 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
6999 | goto err_sw_init; |
7000 | } | |
7001 | ||
1cdd1ec8 GR |
7002 | ixgbe_probe_vf(adapter, ii); |
7003 | ||
396e799c | 7004 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7005 | NETIF_F_IP_CSUM | |
082757af | 7006 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7007 | NETIF_F_HW_VLAN_TX | |
7008 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7009 | NETIF_F_HW_VLAN_FILTER | |
7010 | NETIF_F_TSO | | |
7011 | NETIF_F_TSO6 | | |
082757af DS |
7012 | NETIF_F_RXHASH | |
7013 | NETIF_F_RXCSUM; | |
9a799d71 | 7014 | |
082757af | 7015 | netdev->hw_features = netdev->features; |
ad31c402 | 7016 | |
58be7666 DS |
7017 | switch (adapter->hw.mac.type) { |
7018 | case ixgbe_mac_82599EB: | |
7019 | case ixgbe_mac_X540: | |
45a5ead0 | 7020 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7021 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7022 | NETIF_F_NTUPLE; | |
58be7666 DS |
7023 | break; |
7024 | default: | |
7025 | break; | |
7026 | } | |
45a5ead0 | 7027 | |
3f2d1c0f BG |
7028 | netdev->hw_features |= NETIF_F_RXALL; |
7029 | ||
ad31c402 JK |
7030 | netdev->vlan_features |= NETIF_F_TSO; |
7031 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7032 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7033 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7034 | netdev->vlan_features |= NETIF_F_SG; |
7035 | ||
01789349 | 7036 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 7037 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 7038 | |
1cdd1ec8 GR |
7039 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7040 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7041 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 | 7042 | |
7a6b6f51 | 7043 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7044 | netdev->dcbnl_ops = &dcbnl_ops; |
7045 | #endif | |
7046 | ||
eacd73f7 | 7047 | #ifdef IXGBE_FCOE |
0d551589 | 7048 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7049 | if (hw->mac.ops.get_device_caps) { |
7050 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7051 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7052 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7053 | } |
7054 | } | |
5e09d7f6 YZ |
7055 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7056 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7057 | netdev->vlan_features |= NETIF_F_FSO; | |
7058 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7059 | } | |
eacd73f7 | 7060 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7061 | if (pci_using_dac) { |
9a799d71 | 7062 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7063 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7064 | } | |
9a799d71 | 7065 | |
082757af DS |
7066 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7067 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7068 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7069 | netdev->features |= NETIF_F_LRO; |
7070 | ||
9a799d71 | 7071 | /* make sure the EEPROM is good */ |
c44ade9e | 7072 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7073 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 7074 | err = -EIO; |
35937c05 | 7075 | goto err_sw_init; |
9a799d71 AK |
7076 | } |
7077 | ||
7078 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7079 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7080 | ||
c44ade9e | 7081 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7082 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 7083 | err = -EIO; |
35937c05 | 7084 | goto err_sw_init; |
9a799d71 AK |
7085 | } |
7086 | ||
7086400d | 7087 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 7088 | (unsigned long) adapter); |
9a799d71 | 7089 | |
7086400d AD |
7090 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7091 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7092 | |
021230d4 AV |
7093 | err = ixgbe_init_interrupt_scheme(adapter); |
7094 | if (err) | |
7095 | goto err_sw_init; | |
9a799d71 | 7096 | |
082757af DS |
7097 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { |
7098 | netdev->hw_features &= ~NETIF_F_RXHASH; | |
67a74ee2 | 7099 | netdev->features &= ~NETIF_F_RXHASH; |
082757af | 7100 | } |
67a74ee2 | 7101 | |
c23f5b6b ET |
7102 | /* WOL not supported for all but the following */ |
7103 | adapter->wol = 0; | |
e8e26350 | 7104 | switch (pdev->device) { |
0b077fea | 7105 | case IXGBE_DEV_ID_82599_SFP: |
0e22d043 DS |
7106 | /* Only these subdevice supports WOL */ |
7107 | switch (pdev->subsystem_device) { | |
7108 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
7109 | /* only support first port */ | |
7110 | if (hw->bus.func != 0) | |
7111 | break; | |
7112 | case IXGBE_SUBDEV_ID_82599_SFP: | |
9417c464 | 7113 | adapter->wol = IXGBE_WUFC_MAG; |
0e22d043 DS |
7114 | break; |
7115 | } | |
0b077fea | 7116 | break; |
50d6c681 AD |
7117 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
7118 | /* All except this subdevice support WOL */ | |
0b077fea | 7119 | if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) |
9417c464 | 7120 | adapter->wol = IXGBE_WUFC_MAG; |
0b077fea | 7121 | break; |
e8e26350 | 7122 | case IXGBE_DEV_ID_82599_KX4: |
9417c464 | 7123 | adapter->wol = IXGBE_WUFC_MAG; |
e8e26350 | 7124 | break; |
c23f5b6b ET |
7125 | case IXGBE_DEV_ID_X540T: |
7126 | /* Check eeprom to see if it is enabled */ | |
7127 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); | |
7128 | wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
7129 | ||
7130 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
7131 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
7132 | (hw->bus.func == 0))) | |
7133 | adapter->wol = IXGBE_WUFC_MAG; | |
e8e26350 PW |
7134 | break; |
7135 | } | |
e8e26350 PW |
7136 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7137 | ||
15e5209f ET |
7138 | /* save off EEPROM version number */ |
7139 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
7140 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
7141 | ||
04f165ef PW |
7142 | /* pick up the PCI bus settings for reporting later */ |
7143 | hw->mac.ops.get_bus_info(hw); | |
7144 | ||
9a799d71 | 7145 | /* print bus type/speed/width info */ |
849c4542 | 7146 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7147 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7148 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7149 | "Unknown"), |
7150 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7151 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7152 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7153 | "Unknown"), | |
7154 | netdev->dev_addr); | |
289700db DS |
7155 | |
7156 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7157 | if (err) | |
9fe93afd | 7158 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7159 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7160 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7161 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7162 | part_str); |
e8e26350 | 7163 | else |
289700db DS |
7164 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7165 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7166 | |
e8e26350 | 7167 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7168 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7169 | "not sufficient for optimal performance.\n"); | |
7170 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7171 | "is required.\n"); | |
0c254d86 AK |
7172 | } |
7173 | ||
9a799d71 | 7174 | /* reset the hardware with the new settings */ |
794caeb2 | 7175 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
7176 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7177 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7178 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7179 | "Please be aware there may be issues associated " | |
7180 | "with your hardware. If you are experiencing " | |
7181 | "problems please contact your Intel or hardware " | |
7182 | "representative who provided you with this " | |
7183 | "hardware.\n"); | |
794caeb2 | 7184 | } |
9a799d71 AK |
7185 | strcpy(netdev->name, "eth%d"); |
7186 | err = register_netdev(netdev); | |
7187 | if (err) | |
7188 | goto err_register; | |
7189 | ||
93d3ce8f ET |
7190 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7191 | if (hw->mac.ops.disable_tx_laser && | |
7192 | ((hw->phy.multispeed_fiber) || | |
7193 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && | |
7194 | (hw->mac.type == ixgbe_mac_82599EB)))) | |
7195 | hw->mac.ops.disable_tx_laser(hw); | |
7196 | ||
54386467 JB |
7197 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7198 | netif_carrier_off(netdev); | |
7199 | ||
5dd2d332 | 7200 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7201 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7202 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7203 | ixgbe_setup_dca(adapter); |
7204 | } | |
7205 | #endif | |
1cdd1ec8 | 7206 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7207 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7208 | for (i = 0; i < adapter->num_vfs; i++) |
7209 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7210 | } | |
7211 | ||
2466dd9c JK |
7212 | /* firmware requires driver version to be 0xFFFFFFFF |
7213 | * since os does not support feature | |
7214 | */ | |
9612de92 | 7215 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
7216 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
7217 | 0xFF); | |
9612de92 | 7218 | |
0365e6e4 PW |
7219 | /* add san mac addr to netdev */ |
7220 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7221 | |
ea81875a | 7222 | e_dev_info("%s\n", ixgbe_default_device_descr); |
9a799d71 AK |
7223 | cards_found++; |
7224 | return 0; | |
7225 | ||
7226 | err_register: | |
5eba3699 | 7227 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7228 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 7229 | err_sw_init: |
1cdd1ec8 GR |
7230 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7231 | ixgbe_disable_sriov(adapter); | |
7086400d | 7232 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
7233 | iounmap(hw->hw_addr); |
7234 | err_ioremap: | |
7235 | free_netdev(netdev); | |
7236 | err_alloc_etherdev: | |
e8e9f696 JP |
7237 | pci_release_selected_regions(pdev, |
7238 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7239 | err_pci_reg: |
7240 | err_dma: | |
7241 | pci_disable_device(pdev); | |
7242 | return err; | |
7243 | } | |
7244 | ||
7245 | /** | |
7246 | * ixgbe_remove - Device Removal Routine | |
7247 | * @pdev: PCI device information struct | |
7248 | * | |
7249 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7250 | * that it should release a PCI device. The could be caused by a | |
7251 | * Hot-Plug event, or because the driver is going to be removed from | |
7252 | * memory. | |
7253 | **/ | |
7254 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7255 | { | |
c60fbb00 AD |
7256 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7257 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7258 | |
7259 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 7260 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 7261 | |
5dd2d332 | 7262 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7263 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7264 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7265 | dca_remove_requester(&pdev->dev); | |
7266 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7267 | } | |
7268 | ||
7269 | #endif | |
332d4a7d YZ |
7270 | #ifdef IXGBE_FCOE |
7271 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7272 | ixgbe_cleanup_fcoe(adapter); | |
7273 | ||
7274 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7275 | |
7276 | /* remove the added san mac */ | |
7277 | ixgbe_del_sanmac_netdev(netdev); | |
7278 | ||
c4900be0 DS |
7279 | if (netdev->reg_state == NETREG_REGISTERED) |
7280 | unregister_netdev(netdev); | |
9a799d71 | 7281 | |
c6bda30a GR |
7282 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
7283 | if (!(ixgbe_check_vf_assignment(adapter))) | |
7284 | ixgbe_disable_sriov(adapter); | |
7285 | else | |
7286 | e_dev_warn("Unloading driver while VFs are assigned " | |
7287 | "- VFs will not be deallocated\n"); | |
7288 | } | |
1cdd1ec8 | 7289 | |
7a921c93 | 7290 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7291 | |
021230d4 | 7292 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
7293 | |
7294 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 7295 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7296 | IORESOURCE_MEM)); |
9a799d71 | 7297 | |
849c4542 | 7298 | e_dev_info("complete\n"); |
021230d4 | 7299 | |
9a799d71 AK |
7300 | free_netdev(netdev); |
7301 | ||
19d5afd4 | 7302 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7303 | |
9a799d71 AK |
7304 | pci_disable_device(pdev); |
7305 | } | |
7306 | ||
7307 | /** | |
7308 | * ixgbe_io_error_detected - called when PCI error is detected | |
7309 | * @pdev: Pointer to PCI device | |
7310 | * @state: The current pci connection state | |
7311 | * | |
7312 | * This function is called after a PCI bus error affecting | |
7313 | * this device has been detected. | |
7314 | */ | |
7315 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7316 | pci_channel_state_t state) |
9a799d71 | 7317 | { |
c60fbb00 AD |
7318 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7319 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7320 | |
83c61fa9 GR |
7321 | #ifdef CONFIG_PCI_IOV |
7322 | struct pci_dev *bdev, *vfdev; | |
7323 | u32 dw0, dw1, dw2, dw3; | |
7324 | int vf, pos; | |
7325 | u16 req_id, pf_func; | |
7326 | ||
7327 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
7328 | adapter->num_vfs == 0) | |
7329 | goto skip_bad_vf_detection; | |
7330 | ||
7331 | bdev = pdev->bus->self; | |
7332 | while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT)) | |
7333 | bdev = bdev->bus->self; | |
7334 | ||
7335 | if (!bdev) | |
7336 | goto skip_bad_vf_detection; | |
7337 | ||
7338 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
7339 | if (!pos) | |
7340 | goto skip_bad_vf_detection; | |
7341 | ||
7342 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); | |
7343 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); | |
7344 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); | |
7345 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); | |
7346 | ||
7347 | req_id = dw1 >> 16; | |
7348 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
7349 | if (!(req_id & 0x0080)) | |
7350 | goto skip_bad_vf_detection; | |
7351 | ||
7352 | pf_func = req_id & 0x01; | |
7353 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
7354 | unsigned int device_id; | |
7355 | ||
7356 | vf = (req_id & 0x7F) >> 1; | |
7357 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
7358 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
7359 | "%8.8x\tdw3: %8.8x\n", | |
7360 | dw0, dw1, dw2, dw3); | |
7361 | switch (adapter->hw.mac.type) { | |
7362 | case ixgbe_mac_82599EB: | |
7363 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
7364 | break; | |
7365 | case ixgbe_mac_X540: | |
7366 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
7367 | break; | |
7368 | default: | |
7369 | device_id = 0; | |
7370 | break; | |
7371 | } | |
7372 | ||
7373 | /* Find the pci device of the offending VF */ | |
7374 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL); | |
7375 | while (vfdev) { | |
7376 | if (vfdev->devfn == (req_id & 0xFF)) | |
7377 | break; | |
7378 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, | |
7379 | device_id, vfdev); | |
7380 | } | |
7381 | /* | |
7382 | * There's a slim chance the VF could have been hot plugged, | |
7383 | * so if it is no longer present we don't need to issue the | |
7384 | * VFLR. Just clean up the AER in that case. | |
7385 | */ | |
7386 | if (vfdev) { | |
7387 | e_dev_err("Issuing VFLR to VF %d\n", vf); | |
7388 | pci_write_config_dword(vfdev, 0xA8, 0x00008000); | |
7389 | } | |
7390 | ||
7391 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
7392 | } | |
7393 | ||
7394 | /* | |
7395 | * Even though the error may have occurred on the other port | |
7396 | * we still need to increment the vf error reference count for | |
7397 | * both ports because the I/O resume function will be called | |
7398 | * for both of them. | |
7399 | */ | |
7400 | adapter->vferr_refcount++; | |
7401 | ||
7402 | return PCI_ERS_RESULT_RECOVERED; | |
7403 | ||
7404 | skip_bad_vf_detection: | |
7405 | #endif /* CONFIG_PCI_IOV */ | |
9a799d71 AK |
7406 | netif_device_detach(netdev); |
7407 | ||
3044b8d1 BL |
7408 | if (state == pci_channel_io_perm_failure) |
7409 | return PCI_ERS_RESULT_DISCONNECT; | |
7410 | ||
9a799d71 AK |
7411 | if (netif_running(netdev)) |
7412 | ixgbe_down(adapter); | |
7413 | pci_disable_device(pdev); | |
7414 | ||
b4617240 | 7415 | /* Request a slot reset. */ |
9a799d71 AK |
7416 | return PCI_ERS_RESULT_NEED_RESET; |
7417 | } | |
7418 | ||
7419 | /** | |
7420 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7421 | * @pdev: Pointer to PCI device | |
7422 | * | |
7423 | * Restart the card from scratch, as if from a cold-boot. | |
7424 | */ | |
7425 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7426 | { | |
c60fbb00 | 7427 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7428 | pci_ers_result_t result; |
7429 | int err; | |
9a799d71 | 7430 | |
9ce77666 | 7431 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7432 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7433 | result = PCI_ERS_RESULT_DISCONNECT; |
7434 | } else { | |
7435 | pci_set_master(pdev); | |
7436 | pci_restore_state(pdev); | |
c0e1f68b | 7437 | pci_save_state(pdev); |
9a799d71 | 7438 | |
dd4d8ca6 | 7439 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7440 | |
6fabd715 | 7441 | ixgbe_reset(adapter); |
88512539 | 7442 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7443 | result = PCI_ERS_RESULT_RECOVERED; |
7444 | } | |
7445 | ||
7446 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7447 | if (err) { | |
849c4542 ET |
7448 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7449 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7450 | /* non-fatal, continue */ |
7451 | } | |
9a799d71 | 7452 | |
6fabd715 | 7453 | return result; |
9a799d71 AK |
7454 | } |
7455 | ||
7456 | /** | |
7457 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7458 | * @pdev: Pointer to PCI device | |
7459 | * | |
7460 | * This callback is called when the error recovery driver tells us that | |
7461 | * its OK to resume normal operation. | |
7462 | */ | |
7463 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7464 | { | |
c60fbb00 AD |
7465 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7466 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7467 | |
83c61fa9 GR |
7468 | #ifdef CONFIG_PCI_IOV |
7469 | if (adapter->vferr_refcount) { | |
7470 | e_info(drv, "Resuming after VF err\n"); | |
7471 | adapter->vferr_refcount--; | |
7472 | return; | |
7473 | } | |
7474 | ||
7475 | #endif | |
c7ccde0f AD |
7476 | if (netif_running(netdev)) |
7477 | ixgbe_up(adapter); | |
9a799d71 AK |
7478 | |
7479 | netif_device_attach(netdev); | |
9a799d71 AK |
7480 | } |
7481 | ||
7482 | static struct pci_error_handlers ixgbe_err_handler = { | |
7483 | .error_detected = ixgbe_io_error_detected, | |
7484 | .slot_reset = ixgbe_io_slot_reset, | |
7485 | .resume = ixgbe_io_resume, | |
7486 | }; | |
7487 | ||
7488 | static struct pci_driver ixgbe_driver = { | |
7489 | .name = ixgbe_driver_name, | |
7490 | .id_table = ixgbe_pci_tbl, | |
7491 | .probe = ixgbe_probe, | |
7492 | .remove = __devexit_p(ixgbe_remove), | |
7493 | #ifdef CONFIG_PM | |
7494 | .suspend = ixgbe_suspend, | |
7495 | .resume = ixgbe_resume, | |
7496 | #endif | |
7497 | .shutdown = ixgbe_shutdown, | |
7498 | .err_handler = &ixgbe_err_handler | |
7499 | }; | |
7500 | ||
7501 | /** | |
7502 | * ixgbe_init_module - Driver Registration Routine | |
7503 | * | |
7504 | * ixgbe_init_module is the first routine called when the driver is | |
7505 | * loaded. All it does is register with the PCI subsystem. | |
7506 | **/ | |
7507 | static int __init ixgbe_init_module(void) | |
7508 | { | |
7509 | int ret; | |
c7689578 | 7510 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7511 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7512 | |
5dd2d332 | 7513 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7514 | dca_register_notify(&dca_notifier); |
bd0362dd | 7515 | #endif |
5dd2d332 | 7516 | |
9a799d71 AK |
7517 | ret = pci_register_driver(&ixgbe_driver); |
7518 | return ret; | |
7519 | } | |
b4617240 | 7520 | |
9a799d71 AK |
7521 | module_init(ixgbe_init_module); |
7522 | ||
7523 | /** | |
7524 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7525 | * | |
7526 | * ixgbe_exit_module is called just before the driver is removed | |
7527 | * from memory. | |
7528 | **/ | |
7529 | static void __exit ixgbe_exit_module(void) | |
7530 | { | |
5dd2d332 | 7531 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7532 | dca_unregister_notify(&dca_notifier); |
7533 | #endif | |
9a799d71 | 7534 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7535 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7536 | } |
bd0362dd | 7537 | |
5dd2d332 | 7538 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7539 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7540 | void *p) |
bd0362dd JC |
7541 | { |
7542 | int ret_val; | |
7543 | ||
7544 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7545 | __ixgbe_notify_dca); |
bd0362dd JC |
7546 | |
7547 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7548 | } | |
b453368d | 7549 | |
5dd2d332 | 7550 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7551 | |
9a799d71 AK |
7552 | module_exit(ixgbe_exit_module); |
7553 | ||
7554 | /* ixgbe_main.c */ |