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ixgbe: Make pull tail function separate from rest of cleanup_headers
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
7086400d
AD		 154static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155{
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159}
160
161static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162{
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
52f33af8 165 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168}
169
dcd79aeb
TI		 170struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173};
174
175static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205};
206
207
208/*
209 * ixgbe_regdump - register printout routine
210 */
211static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212{
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
c7689578 275 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 282 pr_err("%-15s", rname);
dcd79aeb 283 for (j = 0; j < 8; j++)
c7689578
JP		 284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
dcd79aeb
TI		 286 }
287
288}
289
290/*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293static void ixgbe_dump(struct ixgbe_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
729739b7 300 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 315 pr_info("Device Name state "
dcd79aeb 316 "trans_start last_rx\n");
c7689578
JP		 317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
dcd79aeb
TI		 322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 326 pr_info(" Register Name Value\n");
dcd79aeb
TI		 327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
c7689578
JP		 368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 377 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 378 u0 = (struct my_u0 *)tx_desc;
c7689578 379 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 380 " %04X %p %016llX %p", i,
dcd79aeb
TI		 381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
729739b7
AD		 383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
dcd79aeb
TI		 388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
c7689578 390 pr_cont(" NTC/U\n");
dcd79aeb 391 else if (i == tx_ring->next_to_use)
c7689578 392 pr_cont(" NTU\n");
dcd79aeb 393 else if (i == tx_ring->next_to_clean)
c7689578 394 pr_cont(" NTC\n");
dcd79aeb 395 else
c7689578 396 pr_cont("\n");
dcd79aeb
TI		 397
398 if (netif_msg_pktdata(adapter) &&
9c50c035 399 tx_buffer->skb)
dcd79aeb
TI		 400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035 402 tx_buffer->skb->data,
729739b7
AD		 403 dma_unmap_len(tx_buffer, len),
404 true);
dcd79aeb
TI		 405 }
406 }
407
408 /* Print RX Rings Summary */
409rx_ring_summary:
410 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 411 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 412 for (n = 0; n < adapter->num_rx_queues; n++) {
413 rx_ring = adapter->rx_ring[n];
c7689578
JP		 414 pr_info("%5d %5X %5X\n",
415 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 416 }
417
418 /* Print RX Rings */
419 if (!netif_msg_rx_status(adapter))
420 goto exit;
421
422 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
423
424 /* Advanced Receive Descriptor (Read) Format
425 * 63 1 0
426 * +-----------------------------------------------------+
427 * 0 | Packet Buffer Address [63:1] |A0/NSE|
428 * +----------------------------------------------+------+
429 * 8 | Header Buffer Address [63:1] | DD |
430 * +-----------------------------------------------------+
431 *
432 *
433 * Advanced Receive Descriptor (Write-Back) Format
434 *
435 * 63 48 47 32 31 30 21 20 16 15 4 3 0
436 * +------------------------------------------------------+
437 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
438 * | Checksum Ident | | | | Type | Type |
439 * +------------------------------------------------------+
440 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
441 * +------------------------------------------------------+
442 * 63 48 47 32 31 20 19 0
443 */
444 for (n = 0; n < adapter->num_rx_queues; n++) {
445 rx_ring = adapter->rx_ring[n];
c7689578
JP		 446 pr_info("------------------------------------\n");
447 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
448 pr_info("------------------------------------\n");
449 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 450 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
451 "<-- Adv Rx Read format\n");
c7689578 452 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 453 "[vl er S cks ln] ---------------- [bi->skb] "
454 "<-- Adv Rx Write-Back format\n");
455
456 for (i = 0; i < rx_ring->count; i++) {
457 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 458 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 459 u0 = (struct my_u0 *)rx_desc;
460 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
461 if (staterr & IXGBE_RXD_STAT_DD) {
462 /* Descriptor Done */
c7689578 463 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 464 "%016llX ---------------- %p", i,
465 le64_to_cpu(u0->a),
466 le64_to_cpu(u0->b),
467 rx_buffer_info->skb);
468 } else {
c7689578 469 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 470 "%016llX %016llX %p", i,
471 le64_to_cpu(u0->a),
472 le64_to_cpu(u0->b),
473 (u64)rx_buffer_info->dma,
474 rx_buffer_info->skb);
475
9c50c035
ET		 476 if (netif_msg_pktdata(adapter) &&
477 rx_buffer_info->dma) {
dcd79aeb
TI		 478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 480 page_address(rx_buffer_info->page) +
481 rx_buffer_info->page_offset,
f800326d 482 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
49ce9c2c 520/**
e8e26350
PW		 521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
729739b7
AD		 592void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
729739b7
AD		 595 if (tx_buffer->skb) {
596 dev_kfree_skb_any(tx_buffer->skb);
597 if (dma_unmap_len(tx_buffer, len))
d3d00239 598 dma_unmap_single(ring->dev,
729739b7
AD		 599 dma_unmap_addr(tx_buffer, dma),
600 dma_unmap_len(tx_buffer, len),
601 DMA_TO_DEVICE);
602 } else if (dma_unmap_len(tx_buffer, len)) {
603 dma_unmap_page(ring->dev,
604 dma_unmap_addr(tx_buffer, dma),
605 dma_unmap_len(tx_buffer, len),
606 DMA_TO_DEVICE);
e5a43549 607 }
729739b7
AD		 608 tx_buffer->next_to_watch = NULL;
609 tx_buffer->skb = NULL;
610 dma_unmap_len_set(tx_buffer, len, 0);
611 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 612}
613
943561d3 614static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 615{
616 struct ixgbe_hw *hw = &adapter->hw;
617 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 618 int i;
943561d3 619 u32 data;
c84d324c 620
943561d3
AD		 621 if ((hw->fc.current_mode != ixgbe_fc_full) &&
622 (hw->fc.current_mode != ixgbe_fc_rx_pause))
623 return;
c84d324c 624
943561d3
AD		 625 switch (hw->mac.type) {
626 case ixgbe_mac_82598EB:
627 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
628 break;
629 default:
630 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
631 }
632 hwstats->lxoffrxc += data;
c84d324c 633
943561d3
AD		 634 /* refill credits (no tx hang) if we received xoff */
635 if (!data)
c84d324c 636 return;
943561d3
AD		 637
638 for (i = 0; i < adapter->num_tx_queues; i++)
639 clear_bit(__IXGBE_HANG_CHECK_ARMED,
640 &adapter->tx_ring[i]->state);
641}
642
643static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
644{
645 struct ixgbe_hw *hw = &adapter->hw;
646 struct ixgbe_hw_stats *hwstats = &adapter->stats;
647 u32 xoff[8] = {0};
648 int i;
649 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
650
651 if (adapter->ixgbe_ieee_pfc)
652 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
653
654 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
655 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 656 return;
943561d3 657 }
c84d324c
JF		 658
659 /* update stats for each tc, only valid with PFC enabled */
660 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
661 switch (hw->mac.type) {
662 case ixgbe_mac_82598EB:
663 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 664 break;
c84d324c
JF		 665 default:
666 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 667 }
c84d324c
JF		 668 hwstats->pxoffrxc[i] += xoff[i];
669 }
670
671 /* disarm tx queues that have received xoff frames */
672 for (i = 0; i < adapter->num_tx_queues; i++) {
673 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 674 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 675
676 if (xoff[tc])
677 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 678 }
26f23d82
YZ		 679}
680
c84d324c 681static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 682{
7d7ce682 683 return ring->stats.packets;
c84d324c
JF		 684}
685
686static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
687{
688 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 689 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 690
c84d324c
JF		 691 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
692 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
693
694 if (head != tail)
695 return (head < tail) ?
696 tail - head : (tail + ring->count - head);
697
698 return 0;
699}
700
701static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
702{
703 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
704 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
705 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
706 bool ret = false;
707
7d637bcc 708 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 709
710 /*
711 * Check for a hung queue, but be thorough. This verifies
712 * that a transmit has been completed since the previous
713 * check AND there is at least one packet pending. The
714 * ARMED bit is set to indicate a potential hang. The
715 * bit is cleared if a pause frame is received to remove
716 * false hang detection due to PFC or 802.3x frames. By
717 * requiring this to fail twice we avoid races with
718 * pfc clearing the ARMED bit and conditions where we
719 * run the check_tx_hang logic with a transmit completion
720 * pending but without time to complete it yet.
721 */
722 if ((tx_done_old == tx_done) && tx_pending) {
723 /* make sure it is true for two checks in a row */
724 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
725 &tx_ring->state);
726 } else {
727 /* update completed stats and continue */
728 tx_ring->tx_stats.tx_done_old = tx_done;
729 /* reset the countdown */
730 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 731 }
732
c84d324c 733 return ret;
9a799d71
AK		 734}
735
c83c6cbd
AD		 736/**
737 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
738 * @adapter: driver private struct
739 **/
740static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
741{
742
743 /* Do the reset outside of interrupt context */
744 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
745 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
746 ixgbe_service_event_schedule(adapter);
747 }
748}
e01c31a5 749
9a799d71
AK		 750/**
751 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 752 * @q_vector: structure containing interrupt and ring information
e01c31a5 753 * @tx_ring: tx ring to clean
9a799d71 754 **/
fe49f04a 755static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 756 struct ixgbe_ring *tx_ring)
9a799d71 757{
fe49f04a 758 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 759 struct ixgbe_tx_buffer *tx_buffer;
760 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 761 unsigned int total_bytes = 0, total_packets = 0;
59224555 762 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 763 unsigned int i = tx_ring->next_to_clean;
764
765 if (test_bit(__IXGBE_DOWN, &adapter->state))
766 return true;
9a799d71 767
d3d00239 768 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 769 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 770 i -= tx_ring->count;
12207e49 771
729739b7 772 do {
d3d00239
AD		 773 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
774
775 /* if next_to_watch is not set then there is no work pending */
776 if (!eop_desc)
777 break;
778
7f83a9e6
AD		 779 /* prevent any other reads prior to eop_desc */
780 rmb();
781
d3d00239
AD		 782 /* if DD is not set pending work has not been completed */
783 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
784 break;
8ad494b0 785
d3d00239
AD		 786 /* clear next_to_watch to prevent false hangs */
787 tx_buffer->next_to_watch = NULL;
8ad494b0 788
091a6246
AD		 789 /* update the statistics for this packet */
790 total_bytes += tx_buffer->bytecount;
791 total_packets += tx_buffer->gso_segs;
792
3a6a4eda 793#ifdef CONFIG_IXGBE_PTP
0ede4a60
JK		 794 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
795 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
3a6a4eda 796#endif
0ede4a60 797
fd0db0ed
AD		 798 /* free the skb */
799 dev_kfree_skb_any(tx_buffer->skb);
800
729739b7
AD		 801 /* unmap skb header data */
802 dma_unmap_single(tx_ring->dev,
803 dma_unmap_addr(tx_buffer, dma),
804 dma_unmap_len(tx_buffer, len),
805 DMA_TO_DEVICE);
806
fd0db0ed
AD		 807 /* clear tx_buffer data */
808 tx_buffer->skb = NULL;
729739b7 809 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 810
729739b7
AD		 811 /* unmap remaining buffers */
812 while (tx_desc != eop_desc) {
d3d00239
AD		 813 tx_buffer++;
814 tx_desc++;
8ad494b0 815 i++;
729739b7
AD		 816 if (unlikely(!i)) {
817 i -= tx_ring->count;
d3d00239 818 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 819 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 820 }
e01c31a5 821
729739b7
AD		 822 /* unmap any remaining paged data */
823 if (dma_unmap_len(tx_buffer, len)) {
824 dma_unmap_page(tx_ring->dev,
825 dma_unmap_addr(tx_buffer, dma),
826 dma_unmap_len(tx_buffer, len),
827 DMA_TO_DEVICE);
828 dma_unmap_len_set(tx_buffer, len, 0);
829 }
830 }
831
832 /* move us one more past the eop_desc for start of next pkt */
833 tx_buffer++;
834 tx_desc++;
835 i++;
836 if (unlikely(!i)) {
837 i -= tx_ring->count;
838 tx_buffer = tx_ring->tx_buffer_info;
839 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
840 }
841
842 /* issue prefetch for next Tx descriptor */
843 prefetch(tx_desc);
12207e49 844
729739b7
AD		 845 /* update budget accounting */
846 budget--;
847 } while (likely(budget));
848
849 i += tx_ring->count;
9a799d71 850 tx_ring->next_to_clean = i;
d3d00239 851 u64_stats_update_begin(&tx_ring->syncp);
b953799e 852 tx_ring->stats.bytes += total_bytes;
bd198058 853 tx_ring->stats.packets += total_packets;
d3d00239 854 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 855 q_vector->tx.total_bytes += total_bytes;
856 q_vector->tx.total_packets += total_packets;
b953799e 857
c84d324c
JF		 858 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
859 /* schedule immediate reset if we believe we hung */
860 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 861 e_err(drv, "Detected Tx Unit Hang\n"
862 " Tx Queue <%d>\n"
863 " TDH, TDT <%x>, <%x>\n"
864 " next_to_use <%x>\n"
865 " next_to_clean <%x>\n"
866 "tx_buffer_info[next_to_clean]\n"
867 " time_stamp <%lx>\n"
868 " jiffies <%lx>\n",
869 tx_ring->queue_index,
870 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
871 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 872 tx_ring->next_to_use, i,
873 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 874
875 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
876
877 e_info(probe,
878 "tx hang %d detected on queue %d, resetting adapter\n",
879 adapter->tx_timeout_count + 1, tx_ring->queue_index);
880
b953799e 881 /* schedule immediate reset if we believe we hung */
c83c6cbd 882 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 883
884 /* the adapter is about to reset, no point in enabling stuff */
59224555 885 return true;
b953799e 886 }
9a799d71 887
b2d96e0a
AD		 888 netdev_tx_completed_queue(txring_txq(tx_ring),
889 total_packets, total_bytes);
890
e092be60 891#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 892 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 893 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 894 /* Make sure that anybody stopping the queue after this
895 * sees the new next_to_clean.
896 */
897 smp_mb();
729739b7
AD		 898 if (__netif_subqueue_stopped(tx_ring->netdev,
899 tx_ring->queue_index)
900 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
901 netif_wake_subqueue(tx_ring->netdev,
902 tx_ring->queue_index);
5b7da515 903 ++tx_ring->tx_stats.restart_queue;
30eba97a 904 }
e092be60 905 }
9a799d71 906
59224555 907 return !!budget;
9a799d71
AK		 908}
909
5dd2d332 910#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 911static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
912 struct ixgbe_ring *tx_ring,
33cf09c9 913 int cpu)
bd0362dd 914{
33cf09c9 915 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 916 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
917 u16 reg_offset;
33cf09c9 918
33cf09c9
AD		 919 switch (hw->mac.type) {
920 case ixgbe_mac_82598EB:
bdda1a61 921 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 922 break;
923 case ixgbe_mac_82599EB:
b93a2226 924 case ixgbe_mac_X540:
bdda1a61
AD		 925 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
926 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 927 break;
928 default:
bdda1a61
AD		 929 /* for unknown hardware do not write register */
930 return;
bd0362dd 931 }
bdda1a61
AD		 932
933 /*
934 * We can enable relaxed ordering for reads, but not writes when
935 * DCA is enabled. This is due to a known issue in some chipsets
936 * which will cause the DCA tag to be cleared.
937 */
938 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
939 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
940 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
941
942 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 943}
944
bdda1a61
AD		 945static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
946 struct ixgbe_ring *rx_ring,
33cf09c9 947 int cpu)
bd0362dd 948{
33cf09c9 949 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 950 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
951 u8 reg_idx = rx_ring->reg_idx;
952
33cf09c9
AD		 953
954 switch (hw->mac.type) {
33cf09c9 955 case ixgbe_mac_82599EB:
b93a2226 956 case ixgbe_mac_X540:
bdda1a61 957 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 958 break;
959 default:
960 break;
961 }
bdda1a61
AD		 962
963 /*
964 * We can enable relaxed ordering for reads, but not writes when
965 * DCA is enabled. This is due to a known issue in some chipsets
966 * which will cause the DCA tag to be cleared.
967 */
968 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
969 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
970 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
971
972 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 973}
974
975static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
976{
977 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 978 struct ixgbe_ring *ring;
bd0362dd 979 int cpu = get_cpu();
bd0362dd 980
33cf09c9
AD		 981 if (q_vector->cpu == cpu)
982 goto out_no_update;
983
a557928e 984 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 985 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 986
a557928e 987 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 988 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 989
990 q_vector->cpu = cpu;
991out_no_update:
bd0362dd
JC		 992 put_cpu();
993}
994
995static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
996{
997 int i;
998
999 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000 return;
1001
e35ec126
AD		 1002 /* always use CB2 mode, difference is masked in the CB driver */
1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
49c7ffbe 1005 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1006 adapter->q_vector[i]->cpu = -1;
1007 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1008 }
1009}
1010
1011static int __ixgbe_notify_dca(struct device *dev, void *data)
1012{
c60fbb00 1013 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1014 unsigned long event = *(unsigned long *)data;
1015
2a72c31e 1016 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1017 return 0;
1018
bd0362dd
JC		 1019 switch (event) {
1020 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1021 /* if we're already enabled, don't do it again */
1022 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1023 break;
652f093f 1024 if (dca_add_requester(dev) == 0) {
96b0e0f6 1025 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1026 ixgbe_setup_dca(adapter);
1027 break;
1028 }
1029 /* Fall Through since DCA is disabled. */
1030 case DCA_PROVIDER_REMOVE:
1031 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1032 dca_remove_requester(dev);
1033 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1035 }
1036 break;
1037 }
1038
652f093f 1039 return 0;
bd0362dd 1040}
67a74ee2 1041
bdda1a61 1042#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1043static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1044 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1045 struct sk_buff *skb)
1046{
8a0da21b
AD		 1047 if (ring->netdev->features & NETIF_F_RXHASH)
1048 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1049}
1050
f800326d 1051#ifdef IXGBE_FCOE
ff886dfc
AD		 1052/**
1053 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1054 * @ring: structure containing ring specific data
ff886dfc
AD		 1055 * @rx_desc: advanced rx descriptor
1056 *
1057 * Returns : true if it is FCoE pkt
1058 */
57efd44c 1059static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1060 union ixgbe_adv_rx_desc *rx_desc)
1061{
1062 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1063
57efd44c 1064 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1065 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1066 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1067 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1068}
1069
f800326d 1070#endif /* IXGBE_FCOE */
e59bd25d
AV		 1071/**
1072 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1073 * @ring: structure containing ring specific data
1074 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1075 * @skb: skb currently being received and modified
1076 **/
8a0da21b 1077static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1078 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1079 struct sk_buff *skb)
9a799d71 1080{
8a0da21b 1081 skb_checksum_none_assert(skb);
9a799d71 1082
712744be 1083 /* Rx csum disabled */
8a0da21b 1084 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1085 return;
e59bd25d
AV		 1086
1087 /* if IP and error */
f56e0cb1
AD		 1088 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1089 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1090 ring->rx_stats.csum_err++;
9a799d71
AK		 1091 return;
1092 }
e59bd25d 1093
f56e0cb1 1094 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1095 return;
1096
f56e0cb1 1097 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1098 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1099
1100 /*
1101 * 82599 errata, UDP frames with a 0 checksum can be marked as
1102 * checksum errors.
1103 */
8a0da21b
AD		 1104 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1105 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1106 return;
1107
8a0da21b 1108 ring->rx_stats.csum_err++;
e59bd25d
AV		 1109 return;
1110 }
1111
9a799d71 1112 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1113 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1114}
1115
84ea2591 1116static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1117{
f56e0cb1 1118 rx_ring->next_to_use = val;
f800326d
AD		 1119
1120 /* update next to alloc since we have filled the ring */
1121 rx_ring->next_to_alloc = val;
e8e26350
PW		 1122 /*
1123 * Force memory writes to complete before letting h/w
1124 * know there are new descriptors to fetch. (Only
1125 * applicable for weak-ordered memory model archs,
1126 * such as IA-64).
1127 */
1128 wmb();
84ea2591 1129 writel(val, rx_ring->tail);
e8e26350
PW		 1130}
1131
f990b79b
AD		 1132static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1133 struct ixgbe_rx_buffer *bi)
1134{
1135 struct page *page = bi->page;
f800326d 1136 dma_addr_t dma = bi->dma;
f990b79b 1137
f800326d
AD		 1138 /* since we are recycling buffers we should seldom need to alloc */
1139 if (likely(dma))
f990b79b
AD		 1140 return true;
1141
f800326d
AD		 1142 /* alloc new page for storage */
1143 if (likely(!page)) {
0614002b
MG		 1144 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1145 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1146 if (unlikely(!page)) {
1147 rx_ring->rx_stats.alloc_rx_page_failed++;
1148 return false;
1149 }
f800326d 1150 bi->page = page;
f990b79b
AD		 1151 }
1152
f800326d
AD		 1153 /* map page for use */
1154 dma = dma_map_page(rx_ring->dev, page, 0,
1155 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1156
1157 /*
1158 * if mapping failed free memory back to system since
1159 * there isn't much point in holding memory we can't use
1160 */
1161 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1162 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1163 bi->page = NULL;
f990b79b 1164
f990b79b
AD		 1165 rx_ring->rx_stats.alloc_rx_page_failed++;
1166 return false;
1167 }
1168
f800326d 1169 bi->dma = dma;
afaa9459 1170 bi->page_offset = 0;
f800326d 1171
f990b79b
AD		 1172 return true;
1173}
1174
9a799d71 1175/**
f990b79b 1176 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1177 * @rx_ring: ring to place buffers on
1178 * @cleaned_count: number of buffers to replace
9a799d71 1179 **/
fc77dc3c 1180void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1181{
9a799d71 1182 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1183 struct ixgbe_rx_buffer *bi;
d5f398ed 1184 u16 i = rx_ring->next_to_use;
9a799d71 1185
f800326d
AD		 1186 /* nothing to do */
1187 if (!cleaned_count)
fc77dc3c
AD		 1188 return;
1189
e4f74028 1190 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1191 bi = &rx_ring->rx_buffer_info[i];
1192 i -= rx_ring->count;
9a799d71 1193
f800326d
AD		 1194 do {
1195 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1196 break;
d5f398ed 1197
f800326d
AD		 1198 /*
1199 * Refresh the desc even if buffer_addrs didn't change
1200 * because each write-back erases this info.
1201 */
1202 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1203
f990b79b
AD		 1204 rx_desc++;
1205 bi++;
9a799d71 1206 i++;
f990b79b 1207 if (unlikely(!i)) {
e4f74028 1208 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1209 bi = rx_ring->rx_buffer_info;
1210 i -= rx_ring->count;
1211 }
1212
1213 /* clear the hdr_addr for the next_to_use descriptor */
1214 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1215
1216 cleaned_count--;
1217 } while (cleaned_count);
7c6e0a43 1218
f990b79b
AD		 1219 i += rx_ring->count;
1220
f56e0cb1 1221 if (rx_ring->next_to_use != i)
84ea2591 1222 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1223}
1224
1d2024f6
AD		 1225/**
1226 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1227 * @data: pointer to the start of the headers
1228 * @max_len: total length of section to find headers in
1229 *
1230 * This function is meant to determine the length of headers that will
1231 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1232 * motivation of doing this is to only perform one pull for IPv4 TCP
1233 * packets so that we can do basic things like calculating the gso_size
1234 * based on the average data per packet.
1235 **/
1236static unsigned int ixgbe_get_headlen(unsigned char *data,
1237 unsigned int max_len)
1238{
1239 union {
1240 unsigned char *network;
1241 /* l2 headers */
1242 struct ethhdr *eth;
1243 struct vlan_hdr *vlan;
1244 /* l3 headers */
1245 struct iphdr *ipv4;
1246 } hdr;
1247 __be16 protocol;
1248 u8 nexthdr = 0; /* default to not TCP */
1249 u8 hlen;
1250
1251 /* this should never happen, but better safe than sorry */
1252 if (max_len < ETH_HLEN)
1253 return max_len;
1254
1255 /* initialize network frame pointer */
1256 hdr.network = data;
1257
1258 /* set first protocol and move network header forward */
1259 protocol = hdr.eth->h_proto;
1260 hdr.network += ETH_HLEN;
1261
1262 /* handle any vlan tag if present */
1263 if (protocol == __constant_htons(ETH_P_8021Q)) {
1264 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1265 return max_len;
1266
1267 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1268 hdr.network += VLAN_HLEN;
1269 }
1270
1271 /* handle L3 protocols */
1272 if (protocol == __constant_htons(ETH_P_IP)) {
1273 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1274 return max_len;
1275
1276 /* access ihl as a u8 to avoid unaligned access on ia64 */
1277 hlen = (hdr.network[0] & 0x0F) << 2;
1278
1279 /* verify hlen meets minimum size requirements */
1280 if (hlen < sizeof(struct iphdr))
1281 return hdr.network - data;
1282
1283 /* record next protocol */
1284 nexthdr = hdr.ipv4->protocol;
1285 hdr.network += hlen;
f800326d 1286#ifdef IXGBE_FCOE
1d2024f6
AD		 1287 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1288 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1289 return max_len;
1290 hdr.network += FCOE_HEADER_LEN;
1291#endif
1292 } else {
1293 return hdr.network - data;
1294 }
1295
1296 /* finally sort out TCP */
1297 if (nexthdr == IPPROTO_TCP) {
1298 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1299 return max_len;
1300
1301 /* access doff as a u8 to avoid unaligned access on ia64 */
1302 hlen = (hdr.network[12] & 0xF0) >> 2;
1303
1304 /* verify hlen meets minimum size requirements */
1305 if (hlen < sizeof(struct tcphdr))
1306 return hdr.network - data;
1307
1308 hdr.network += hlen;
1309 }
1310
1311 /*
1312 * If everything has gone correctly hdr.network should be the
1313 * data section of the packet and will be the end of the header.
1314 * If not then it probably represents the end of the last recognized
1315 * header.
1316 */
1317 if ((hdr.network - data) < max_len)
1318 return hdr.network - data;
1319 else
1320 return max_len;
1321}
1322
4c1975d7
AD		 1323static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1324 union ixgbe_adv_rx_desc *rx_desc,
1325 struct sk_buff *skb)
aa80175a 1326{
4c1975d7
AD		 1327 __le32 rsc_enabled;
1328 u32 rsc_cnt;
1329
1330 if (!ring_is_rsc_enabled(rx_ring))
1331 return;
1332
1333 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1334 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1335
1336 /* If this is an RSC frame rsc_cnt should be non-zero */
1337 if (!rsc_enabled)
1338 return;
1339
1340 rsc_cnt = le32_to_cpu(rsc_enabled);
1341 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1342
1343 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1344}
43634e82 1345
1d2024f6
AD		 1346static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1347 struct sk_buff *skb)
1348{
f800326d 1349 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1350
1351 /* set gso_size to avoid messing up TCP MSS */
1352 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1353 IXGBE_CB(skb)->append_cnt);
1354}
1355
1356static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1357 struct sk_buff *skb)
1358{
1359 /* if append_cnt is 0 then frame is not RSC */
1360 if (!IXGBE_CB(skb)->append_cnt)
1361 return;
1362
1363 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1364 rx_ring->rx_stats.rsc_flush++;
1365
1366 ixgbe_set_rsc_gso_size(rx_ring, skb);
1367
1368 /* gso_size is computed using append_cnt so always clear it last */
1369 IXGBE_CB(skb)->append_cnt = 0;
1370}
1371
8a0da21b
AD		 1372/**
1373 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1374 * @rx_ring: rx descriptor ring packet is being transacted on
1375 * @rx_desc: pointer to the EOP Rx descriptor
1376 * @skb: pointer to current skb being populated
f8212f97 1377 *
8a0da21b
AD		 1378 * This function checks the ring, descriptor, and packet information in
1379 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1380 * other fields within the skb.
f8212f97 1381 **/
8a0da21b
AD		 1382static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1383 union ixgbe_adv_rx_desc *rx_desc,
1384 struct sk_buff *skb)
f8212f97 1385{
43e95f11
JF		 1386 struct net_device *dev = rx_ring->netdev;
1387
8a0da21b
AD		 1388 ixgbe_update_rsc_stats(rx_ring, skb);
1389
1390 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1391
8a0da21b
AD		 1392 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1393
3a6a4eda 1394#ifdef CONFIG_IXGBE_PTP
1d1a79b5 1395 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda
JK		 1396#endif
1397
43e95f11
JF		 1398 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1399 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1400 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1401 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1402 }
1403
8a0da21b 1404 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1405
43e95f11 1406 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1407}
1408
8a0da21b
AD		 1409static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1410 struct sk_buff *skb)
aa80175a 1411{
8a0da21b
AD		 1412 struct ixgbe_adapter *adapter = q_vector->adapter;
1413
1414 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1415 napi_gro_receive(&q_vector->napi, skb);
1416 else
1417 netif_rx(skb);
aa80175a 1418}
43634e82 1419
f800326d
AD		 1420/**
1421 * ixgbe_is_non_eop - process handling of non-EOP buffers
1422 * @rx_ring: Rx ring being processed
1423 * @rx_desc: Rx descriptor for current buffer
1424 * @skb: Current socket buffer containing buffer in progress
1425 *
1426 * This function updates next to clean. If the buffer is an EOP buffer
1427 * this function exits returning false, otherwise it will place the
1428 * sk_buff in the next buffer to be chained and return true indicating
1429 * that this is in fact a non-EOP buffer.
1430 **/
1431static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1432 union ixgbe_adv_rx_desc *rx_desc,
1433 struct sk_buff *skb)
1434{
1435 u32 ntc = rx_ring->next_to_clean + 1;
1436
1437 /* fetch, update, and store next to clean */
1438 ntc = (ntc < rx_ring->count) ? ntc : 0;
1439 rx_ring->next_to_clean = ntc;
1440
1441 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1442
1443 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1444 return false;
1445
1446 /* append_cnt indicates packet is RSC, if so fetch nextp */
1447 if (IXGBE_CB(skb)->append_cnt) {
1448 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1449 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1450 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1451 }
1452
1453 /* place skb in next buffer to be received */
1454 rx_ring->rx_buffer_info[ntc].skb = skb;
1455 rx_ring->rx_stats.non_eop_descs++;
1456
1457 return true;
1458}
1459
19861ce2
AD		 1460/**
1461 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1462 * @rx_ring: rx descriptor ring packet is being transacted on
1463 * @skb: pointer to current skb being adjusted
1464 *
1465 * This function is an ixgbe specific version of __pskb_pull_tail. The
1466 * main difference between this version and the original function is that
1467 * this function can make several assumptions about the state of things
1468 * that allow for significant optimizations versus the standard function.
1469 * As a result we can do things like drop a frag and maintain an accurate
1470 * truesize for the skb.
1471 */
1472static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1473 struct sk_buff *skb)
1474{
1475 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1476 unsigned char *va;
1477 unsigned int pull_len;
1478
1479 /*
1480 * it is valid to use page_address instead of kmap since we are
1481 * working with pages allocated out of the lomem pool per
1482 * alloc_page(GFP_ATOMIC)
1483 */
1484 va = skb_frag_address(frag);
1485
1486 /*
1487 * we need the header to contain the greater of either ETH_HLEN or
1488 * 60 bytes if the skb->len is less than 60 for skb_pad.
1489 */
1490 pull_len = skb_frag_size(frag);
1491 if (pull_len > IXGBE_RX_HDR_SIZE)
1492 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
1493
1494 /* align pull length to size of long to optimize memcpy performance */
1495 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1496
1497 /* update all of the pointers */
1498 skb_frag_size_sub(frag, pull_len);
1499 frag->page_offset += pull_len;
1500 skb->data_len -= pull_len;
1501 skb->tail += pull_len;
1502
1503 /*
1504 * if we sucked the frag empty then we should free it,
1505 * if there are other frags here something is screwed up in hardware
1506 */
1507 if (skb_frag_size(frag) == 0) {
1508 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1509 skb_shinfo(skb)->nr_frags = 0;
1510 __skb_frag_unref(frag);
1511 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1512 }
1513}
1514
42073d91
AD		 1515/**
1516 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1517 * @rx_ring: rx descriptor ring packet is being transacted on
1518 * @skb: pointer to current skb being updated
1519 *
1520 * This function provides a basic DMA sync up for the first fragment of an
1521 * skb. The reason for doing this is that the first fragment cannot be
1522 * unmapped until we have reached the end of packet descriptor for a buffer
1523 * chain.
1524 */
1525static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1526 struct sk_buff *skb)
1527{
1528 /* if the page was released unmap it, else just sync our portion */
1529 if (unlikely(IXGBE_CB(skb)->page_released)) {
1530 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1531 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1532 IXGBE_CB(skb)->page_released = false;
1533 } else {
1534 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1535
1536 dma_sync_single_range_for_cpu(rx_ring->dev,
1537 IXGBE_CB(skb)->dma,
1538 frag->page_offset,
1539 ixgbe_rx_bufsz(rx_ring),
1540 DMA_FROM_DEVICE);
1541 }
1542 IXGBE_CB(skb)->dma = 0;
1543}
1544
f800326d
AD		 1545/**
1546 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1547 * @rx_ring: rx descriptor ring packet is being transacted on
1548 * @rx_desc: pointer to the EOP Rx descriptor
1549 * @skb: pointer to current skb being fixed
1550 *
1551 * Check for corrupted packet headers caused by senders on the local L2
1552 * embedded NIC switch not setting up their Tx Descriptors right. These
1553 * should be very rare.
1554 *
1555 * Also address the case where we are pulling data in on pages only
1556 * and as such no data is present in the skb header.
1557 *
1558 * In addition if skb is not at least 60 bytes we need to pad it so that
1559 * it is large enough to qualify as a valid Ethernet frame.
1560 *
1561 * Returns true if an error was encountered and skb was freed.
1562 **/
1563static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1564 union ixgbe_adv_rx_desc *rx_desc,
1565 struct sk_buff *skb)
1566{
f800326d 1567 struct net_device *netdev = rx_ring->netdev;
f800326d 1568
f800326d
AD		 1569 /* verify that the packet does not have any known errors */
1570 if (unlikely(ixgbe_test_staterr(rx_desc,
1571 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1572 !(netdev->features & NETIF_F_RXALL))) {
1573 dev_kfree_skb_any(skb);
1574 return true;
1575 }
1576
19861ce2
AD		 1577 /* place header in linear portion of buffer */
1578 ixgbe_pull_tail(rx_ring, skb);
f800326d 1579
57efd44c
AD		 1580#ifdef IXGBE_FCOE
1581 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1582 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1583 return false;
1584
1585#endif
f800326d
AD		 1586 /* if skb_pad returns an error the skb was freed */
1587 if (unlikely(skb->len < 60)) {
1588 int pad_len = 60 - skb->len;
1589
1590 if (skb_pad(skb, pad_len))
1591 return true;
1592 __skb_put(skb, pad_len);
1593 }
1594
1595 return false;
1596}
1597
f800326d
AD		 1598/**
1599 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1600 * @rx_ring: rx descriptor ring to store buffers on
1601 * @old_buff: donor buffer to have page reused
1602 *
0549ae20 1603 * Synchronizes page for reuse by the adapter
f800326d
AD		 1604 **/
1605static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1606 struct ixgbe_rx_buffer *old_buff)
1607{
1608 struct ixgbe_rx_buffer *new_buff;
1609 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1610
1611 new_buff = &rx_ring->rx_buffer_info[nta];
1612
1613 /* update, and store next to alloc */
1614 nta++;
1615 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1616
1617 /* transfer page from old buffer to new buffer */
1618 new_buff->page = old_buff->page;
1619 new_buff->dma = old_buff->dma;
0549ae20 1620 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1621
1622 /* sync the buffer for use by the device */
1623 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1624 new_buff->page_offset,
1625 ixgbe_rx_bufsz(rx_ring),
f800326d 1626 DMA_FROM_DEVICE);
f800326d
AD		 1627}
1628
1629/**
1630 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1631 * @rx_ring: rx descriptor ring to transact packets on
1632 * @rx_buffer: buffer containing page to add
1633 * @rx_desc: descriptor containing length of buffer written by hardware
1634 * @skb: sk_buff to place the data into
1635 *
0549ae20
AD		 1636 * This function will add the data contained in rx_buffer->page to the skb.
1637 * This is done either through a direct copy if the data in the buffer is
1638 * less than the skb header size, otherwise it will just attach the page as
1639 * a frag to the skb.
1640 *
1641 * The function will then update the page offset if necessary and return
1642 * true if the buffer can be reused by the adapter.
f800326d 1643 **/
0549ae20 1644static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1645 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1646 union ixgbe_adv_rx_desc *rx_desc,
1647 struct sk_buff *skb)
f800326d 1648{
0549ae20
AD		 1649 struct page *page = rx_buffer->page;
1650 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1651#if (PAGE_SIZE < 8192)
0549ae20 1652 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1653#else
1654 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1655 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1656 ixgbe_rx_bufsz(rx_ring);
1657#endif
0549ae20
AD		 1658
1659 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1660 rx_buffer->page_offset, size, truesize);
1661
09816fbe
AD		 1662 /* avoid re-using remote pages */
1663 if (unlikely(page_to_nid(page) != numa_node_id()))
1664 return false;
1665
1666#if (PAGE_SIZE < 8192)
1667 /* if we are only owner of page we can reuse it */
1668 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1669 return false;
1670
1671 /* flip page offset to other buffer */
1672 rx_buffer->page_offset ^= truesize;
1673
09816fbe
AD		 1674 /*
1675 * since we are the only owner of the page and we need to
1676 * increment it, just set the value to 2 in order to avoid
1677 * an unecessary locked operation
1678 */
1679 atomic_set(&page->_count, 2);
1680#else
1681 /* move offset up to the next cache line */
1682 rx_buffer->page_offset += truesize;
1683
1684 if (rx_buffer->page_offset > last_offset)
1685 return false;
1686
0549ae20
AD		 1687 /* bump ref count on page before it is given to the stack */
1688 get_page(page);
09816fbe 1689#endif
0549ae20
AD		 1690
1691 return true;
f800326d
AD		 1692}
1693
1694/**
1695 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1696 * @q_vector: structure containing interrupt and ring information
1697 * @rx_ring: rx descriptor ring to transact packets on
1698 * @budget: Total limit on number of packets to process
1699 *
1700 * This function provides a "bounce buffer" approach to Rx interrupt
1701 * processing. The advantage to this is that on systems that have
1702 * expensive overhead for IOMMU access this provides a means of avoiding
1703 * it by maintaining the mapping of the page to the syste.
1704 *
1705 * Returns true if all work is completed without reaching budget
1706 **/
4ff7fb12 1707static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1708 struct ixgbe_ring *rx_ring,
4ff7fb12 1709 int budget)
9a799d71 1710{
d2f4fbe2 1711 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1712#ifdef IXGBE_FCOE
f800326d 1713 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1714 int ddp_bytes = 0;
1715#endif /* IXGBE_FCOE */
f800326d 1716 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1717
f800326d
AD		 1718 do {
1719 struct ixgbe_rx_buffer *rx_buffer;
1720 union ixgbe_adv_rx_desc *rx_desc;
1721 struct sk_buff *skb;
1722 struct page *page;
1723 u16 ntc;
1724
1725 /* return some buffers to hardware, one at a time is too slow */
1726 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1727 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1728 cleaned_count = 0;
1729 }
1730
1731 ntc = rx_ring->next_to_clean;
1732 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1733 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1734
1735 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1736 break;
9a799d71 1737
f800326d
AD		 1738 /*
1739 * This memory barrier is needed to keep us from reading
1740 * any other fields out of the rx_desc until we know the
1741 * RXD_STAT_DD bit is set
1742 */
1743 rmb();
9a799d71 1744
f800326d
AD		 1745 page = rx_buffer->page;
1746 prefetchw(page);
9a799d71 1747
f800326d 1748 skb = rx_buffer->skb;
c267fc16 1749
f800326d
AD		 1750 if (likely(!skb)) {
1751 void *page_addr = page_address(page) +
1752 rx_buffer->page_offset;
9a799d71 1753
f800326d
AD		 1754 /* prefetch first cache line of first page */
1755 prefetch(page_addr);
1756#if L1_CACHE_BYTES < 128
1757 prefetch(page_addr + L1_CACHE_BYTES);
1758#endif
1759
1760 /* allocate a skb to store the frags */
1761 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1762 IXGBE_RX_HDR_SIZE);
1763 if (unlikely(!skb)) {
1764 rx_ring->rx_stats.alloc_rx_buff_failed++;
1765 break;
c267fc16
AD		 1766 }
1767
f800326d
AD		 1768 /*
1769 * we will be copying header into skb->data in
1770 * pskb_may_pull so it is in our interest to prefetch
1771 * it now to avoid a possible cache miss
1772 */
1773 prefetchw(skb->data);
4c1975d7
AD		 1774
1775 /*
1776 * Delay unmapping of the first packet. It carries the
1777 * header information, HW may still access the header
f800326d
AD		 1778 * after the writeback. Only unmap it when EOP is
1779 * reached
4c1975d7 1780 */
42073d91
AD		 1781 if (likely(ixgbe_test_staterr(rx_desc,
1782 IXGBE_RXD_STAT_EOP)))
1783 goto dma_sync;
1784
f800326d 1785 IXGBE_CB(skb)->dma = rx_buffer->dma;
c267fc16 1786 } else {
42073d91
AD		 1787 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1788 ixgbe_dma_sync_frag(rx_ring, skb);
1789
1790dma_sync:
f800326d
AD		 1791 /* we are reusing so sync this buffer for CPU use */
1792 dma_sync_single_range_for_cpu(rx_ring->dev,
1793 rx_buffer->dma,
1794 rx_buffer->page_offset,
1795 ixgbe_rx_bufsz(rx_ring),
1796 DMA_FROM_DEVICE);
9a799d71
AK		 1797 }
1798
f800326d 1799 /* pull page into skb */
0549ae20 1800 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
f800326d
AD		 1801 /* hand second half of page back to the ring */
1802 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1803 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1804 /* the page has been released from the ring */
1805 IXGBE_CB(skb)->page_released = true;
1806 } else {
1807 /* we are not reusing the buffer so unmap it */
1808 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1809 ixgbe_rx_pg_size(rx_ring),
1810 DMA_FROM_DEVICE);
9a799d71
AK		 1811 }
1812
f800326d
AD		 1813 /* clear contents of buffer_info */
1814 rx_buffer->skb = NULL;
1815 rx_buffer->dma = 0;
1816 rx_buffer->page = NULL;
4c1975d7 1817
f800326d 1818 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
9a799d71 1819
9a799d71 1820 cleaned_count++;
f8212f97 1821
f800326d
AD		 1822 /* place incomplete frames back on ring for completion */
1823 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1824 continue;
c267fc16 1825
f800326d
AD		 1826 /* verify the packet layout is correct */
1827 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1828 continue;
9a799d71 1829
d2f4fbe2
AV		 1830 /* probably a little skewed due to removing CRC */
1831 total_rx_bytes += skb->len;
1832 total_rx_packets++;
1833
8a0da21b
AD		 1834 /* populate checksum, timestamp, VLAN, and protocol */
1835 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1836
332d4a7d
YZ		 1837#ifdef IXGBE_FCOE
1838 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1839 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1840 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1841 if (!ddp_bytes) {
1842 dev_kfree_skb_any(skb);
f800326d 1843 continue;
63d635b2 1844 }
3d8fd385 1845 }
f800326d 1846
332d4a7d 1847#endif /* IXGBE_FCOE */
8a0da21b 1848 ixgbe_rx_skb(q_vector, skb);
9a799d71 1849
f800326d 1850 /* update budget accounting */
4ff7fb12 1851 budget--;
f800326d 1852 } while (likely(budget));
9a799d71 1853
3d8fd385
YZ		 1854#ifdef IXGBE_FCOE
1855 /* include DDPed FCoE data */
1856 if (ddp_bytes > 0) {
1857 unsigned int mss;
1858
fc77dc3c 1859 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1860 sizeof(struct fc_frame_header) -
1861 sizeof(struct fcoe_crc_eof);
1862 if (mss > 512)
1863 mss &= ~511;
1864 total_rx_bytes += ddp_bytes;
1865 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1866 }
3d8fd385 1867
f800326d 1868#endif /* IXGBE_FCOE */
c267fc16
AD		 1869 u64_stats_update_begin(&rx_ring->syncp);
1870 rx_ring->stats.packets += total_rx_packets;
1871 rx_ring->stats.bytes += total_rx_bytes;
1872 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1873 q_vector->rx.total_packets += total_rx_packets;
1874 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1875
f800326d
AD		 1876 if (cleaned_count)
1877 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1878
4ff7fb12 1879 return !!budget;
9a799d71
AK		 1880}
1881
9a799d71
AK		 1882/**
1883 * ixgbe_configure_msix - Configure MSI-X hardware
1884 * @adapter: board private structure
1885 *
1886 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1887 * interrupts.
1888 **/
1889static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1890{
021230d4 1891 struct ixgbe_q_vector *q_vector;
49c7ffbe 1892 int v_idx;
021230d4 1893 u32 mask;
9a799d71 1894
8e34d1aa
AD		 1895 /* Populate MSIX to EITR Select */
1896 if (adapter->num_vfs > 32) {
1897 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1899 }
1900
4df10466
JB		 1901 /*
1902 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1903 * corresponding register.
1904 */
49c7ffbe 1905 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1906 struct ixgbe_ring *ring;
7a921c93 1907 q_vector = adapter->q_vector[v_idx];
021230d4 1908
a557928e 1909 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1910 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1911
a557928e 1912 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1913 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1914
d5bf4f67
ET		 1915 if (q_vector->tx.ring && !q_vector->rx.ring) {
1916 /* tx only vector */
1917 if (adapter->tx_itr_setting == 1)
1918 q_vector->itr = IXGBE_10K_ITR;
1919 else
1920 q_vector->itr = adapter->tx_itr_setting;
1921 } else {
1922 /* rx or rx/tx vector */
1923 if (adapter->rx_itr_setting == 1)
1924 q_vector->itr = IXGBE_20K_ITR;
1925 else
1926 q_vector->itr = adapter->rx_itr_setting;
1927 }
021230d4 1928
fe49f04a 1929 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1930 }
1931
bd508178
AD		 1932 switch (adapter->hw.mac.type) {
1933 case ixgbe_mac_82598EB:
e8e26350 1934 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1935 v_idx);
bd508178
AD		 1936 break;
1937 case ixgbe_mac_82599EB:
b93a2226 1938 case ixgbe_mac_X540:
e8e26350 1939 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1940 break;
bd508178
AD		 1941 default:
1942 break;
1943 }
021230d4
AV		 1944 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1945
41fb9248 1946 /* set up to autoclear timer, and the vectors */
021230d4 1947 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1948 mask &= ~(IXGBE_EIMS_OTHER |
1949 IXGBE_EIMS_MAILBOX |
1950 IXGBE_EIMS_LSC);
1951
021230d4 1952 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1953}
1954
f494e8fa
AV		 1955enum latency_range {
1956 lowest_latency = 0,
1957 low_latency = 1,
1958 bulk_latency = 2,
1959 latency_invalid = 255
1960};
1961
1962/**
1963 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1964 * @q_vector: structure containing interrupt and ring information
1965 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1966 *
1967 * Stores a new ITR value based on packets and byte
1968 * counts during the last interrupt. The advantage of per interrupt
1969 * computation is faster updates and more accurate ITR for the current
1970 * traffic pattern. Constants in this function were computed
1971 * based on theoretical maximum wire speed and thresholds were set based
1972 * on testing data as well as attempting to minimize response time
1973 * while increasing bulk throughput.
1974 * this functionality is controlled by the InterruptThrottleRate module
1975 * parameter (see ixgbe_param.c)
1976 **/
bd198058
AD		 1977static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1978 struct ixgbe_ring_container *ring_container)
f494e8fa 1979{
bd198058
AD		 1980 int bytes = ring_container->total_bytes;
1981 int packets = ring_container->total_packets;
1982 u32 timepassed_us;
621bd70e 1983 u64 bytes_perint;
bd198058 1984 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1985
1986 if (packets == 0)
bd198058 1987 return;
f494e8fa
AV		 1988
1989 /* simple throttlerate management
621bd70e
AD		 1990 * 0-10MB/s lowest (100000 ints/s)
1991 * 10-20MB/s low (20000 ints/s)
1992 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1993 */
1994 /* what was last interrupt timeslice? */
d5bf4f67 1995 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1996 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1997
1998 switch (itr_setting) {
1999 case lowest_latency:
621bd70e 2000 if (bytes_perint > 10)
bd198058 2001 itr_setting = low_latency;
f494e8fa
AV		 2002 break;
2003 case low_latency:
621bd70e 2004 if (bytes_perint > 20)
bd198058 2005 itr_setting = bulk_latency;
621bd70e 2006 else if (bytes_perint <= 10)
bd198058 2007 itr_setting = lowest_latency;
f494e8fa
AV		 2008 break;
2009 case bulk_latency:
621bd70e 2010 if (bytes_perint <= 20)
bd198058 2011 itr_setting = low_latency;
f494e8fa
AV		 2012 break;
2013 }
2014
bd198058
AD		 2015 /* clear work counters since we have the values we need */
2016 ring_container->total_bytes = 0;
2017 ring_container->total_packets = 0;
2018
2019 /* write updated itr to ring container */
2020 ring_container->itr = itr_setting;
f494e8fa
AV		 2021}
2022
509ee935
JB		 2023/**
2024 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2025 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2026 *
2027 * This function is made to be called by ethtool and by the driver
2028 * when it needs to update EITR registers at runtime. Hardware
2029 * specific quirks/differences are taken care of here.
2030 */
fe49f04a 2031void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2032{
fe49f04a 2033 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2034 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2035 int v_idx = q_vector->v_idx;
5d967eb7 2036 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2037
bd508178
AD		 2038 switch (adapter->hw.mac.type) {
2039 case ixgbe_mac_82598EB:
509ee935
JB		 2040 /* must write high and low 16 bits to reset counter */
2041 itr_reg |= (itr_reg << 16);
bd508178
AD		 2042 break;
2043 case ixgbe_mac_82599EB:
b93a2226 2044 case ixgbe_mac_X540:
509ee935
JB		 2045 /*
2046 * set the WDIS bit to not clear the timer bits and cause an
2047 * immediate assertion of the interrupt
2048 */
2049 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2050 break;
2051 default:
2052 break;
509ee935
JB		 2053 }
2054 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2055}
2056
bd198058 2057static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2058{
d5bf4f67 2059 u32 new_itr = q_vector->itr;
bd198058 2060 u8 current_itr;
f494e8fa 2061
bd198058
AD		 2062 ixgbe_update_itr(q_vector, &q_vector->tx);
2063 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2064
08c8833b 2065 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2066
2067 switch (current_itr) {
2068 /* counts and packets in update_itr are dependent on these numbers */
2069 case lowest_latency:
d5bf4f67 2070 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2071 break;
2072 case low_latency:
d5bf4f67 2073 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2074 break;
2075 case bulk_latency:
d5bf4f67 2076 new_itr = IXGBE_8K_ITR;
f494e8fa 2077 break;
bd198058
AD		 2078 default:
2079 break;
f494e8fa
AV		 2080 }
2081
d5bf4f67 2082 if (new_itr != q_vector->itr) {
fe49f04a 2083 /* do an exponential smoothing */
d5bf4f67
ET		 2084 new_itr = (10 * new_itr * q_vector->itr) /
2085 ((9 * new_itr) + q_vector->itr);
509ee935 2086
bd198058 2087 /* save the algorithm value here */
5d967eb7 2088 q_vector->itr = new_itr;
fe49f04a
AD		 2089
2090 ixgbe_write_eitr(q_vector);
f494e8fa 2091 }
f494e8fa
AV		 2092}
2093
119fc60a 2094/**
de88eeeb 2095 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2096 * @adapter: pointer to adapter
119fc60a 2097 **/
f0f9778d 2098static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2099{
119fc60a
MC		 2100 struct ixgbe_hw *hw = &adapter->hw;
2101 u32 eicr = adapter->interrupt_event;
2102
f0f9778d 2103 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2104 return;
2105
f0f9778d
AD		 2106 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2107 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2108 return;
2109
2110 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2111
7ca647bd 2112 switch (hw->device_id) {
f0f9778d
AD		 2113 case IXGBE_DEV_ID_82599_T3_LOM:
2114 /*
2115 * Since the warning interrupt is for both ports
2116 * we don't have to check if:
2117 * - This interrupt wasn't for our port.
2118 * - We may have missed the interrupt so always have to
2119 * check if we got a LSC
2120 */
2121 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2122 !(eicr & IXGBE_EICR_LSC))
2123 return;
2124
2125 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2126 u32 autoneg;
2127 bool link_up = false;
7ca647bd 2128
7ca647bd
JP		 2129 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2130
f0f9778d
AD		 2131 if (link_up)
2132 return;
2133 }
2134
2135 /* Check if this is not due to overtemp */
2136 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2137 return;
2138
2139 break;
7ca647bd
JP		 2140 default:
2141 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2142 return;
7ca647bd 2143 break;
119fc60a 2144 }
7ca647bd
JP		 2145 e_crit(drv,
2146 "Network adapter has been stopped because it has over heated. "
2147 "Restart the computer. If the problem persists, "
2148 "power off the system and replace the adapter\n");
f0f9778d
AD		 2149
2150 adapter->interrupt_event = 0;
119fc60a
MC		 2151}
2152
0befdb3e
JB		 2153static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2154{
2155 struct ixgbe_hw *hw = &adapter->hw;
2156
2157 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2158 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2159 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2160 /* write to clear the interrupt */
2161 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2162 }
2163}
cf8280ee 2164
4f51bf70
JK		 2165static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2166{
2167 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2168 return;
2169
2170 switch (adapter->hw.mac.type) {
2171 case ixgbe_mac_82599EB:
2172 /*
2173 * Need to check link state so complete overtemp check
2174 * on service task
2175 */
2176 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2177 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2178 adapter->interrupt_event = eicr;
2179 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2180 ixgbe_service_event_schedule(adapter);
2181 return;
2182 }
2183 return;
2184 case ixgbe_mac_X540:
2185 if (!(eicr & IXGBE_EICR_TS))
2186 return;
2187 break;
2188 default:
2189 return;
2190 }
2191
2192 e_crit(drv,
2193 "Network adapter has been stopped because it has over heated. "
2194 "Restart the computer. If the problem persists, "
2195 "power off the system and replace the adapter\n");
2196}
2197
e8e26350
PW		 2198static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2199{
2200 struct ixgbe_hw *hw = &adapter->hw;
2201
73c4b7cd
AD		 2202 if (eicr & IXGBE_EICR_GPI_SDP2) {
2203 /* Clear the interrupt */
2204 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2205 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2206 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2207 ixgbe_service_event_schedule(adapter);
2208 }
73c4b7cd
AD		 2209 }
2210
e8e26350
PW		 2211 if (eicr & IXGBE_EICR_GPI_SDP1) {
2212 /* Clear the interrupt */
2213 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2214 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2215 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2216 ixgbe_service_event_schedule(adapter);
2217 }
e8e26350
PW		 2218 }
2219}
2220
cf8280ee
JB		 2221static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2222{
2223 struct ixgbe_hw *hw = &adapter->hw;
2224
2225 adapter->lsc_int++;
2226 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2227 adapter->link_check_timeout = jiffies;
2228 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2229 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2230 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2231 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2232 }
2233}
2234
fe49f04a
AD		 2235static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2236 u64 qmask)
2237{
2238 u32 mask;
bd508178 2239 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2240
bd508178
AD		 2241 switch (hw->mac.type) {
2242 case ixgbe_mac_82598EB:
fe49f04a 2243 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2244 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2245 break;
2246 case ixgbe_mac_82599EB:
b93a2226 2247 case ixgbe_mac_X540:
fe49f04a 2248 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2249 if (mask)
2250 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2251 mask = (qmask >> 32);
bd508178
AD		 2252 if (mask)
2253 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2254 break;
2255 default:
2256 break;
fe49f04a
AD		 2257 }
2258 /* skip the flush */
2259}
2260
2261static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2262 u64 qmask)
fe49f04a
AD		 2263{
2264 u32 mask;
bd508178 2265 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2266
bd508178
AD		 2267 switch (hw->mac.type) {
2268 case ixgbe_mac_82598EB:
fe49f04a 2269 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2270 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2271 break;
2272 case ixgbe_mac_82599EB:
b93a2226 2273 case ixgbe_mac_X540:
fe49f04a 2274 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2275 if (mask)
2276 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2277 mask = (qmask >> 32);
bd508178
AD		 2278 if (mask)
2279 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2280 break;
2281 default:
2282 break;
fe49f04a
AD		 2283 }
2284 /* skip the flush */
2285}
2286
021230d4 2287/**
2c4af694
AD		 2288 * ixgbe_irq_enable - Enable default interrupt generation settings
2289 * @adapter: board private structure
021230d4 2290 **/
2c4af694
AD		 2291static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2292 bool flush)
9a799d71 2293{
2c4af694 2294 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2295
2c4af694
AD		 2296 /* don't reenable LSC while waiting for link */
2297 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2298 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2299
2c4af694 2300 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2301 switch (adapter->hw.mac.type) {
2302 case ixgbe_mac_82599EB:
2303 mask |= IXGBE_EIMS_GPI_SDP0;
2304 break;
2305 case ixgbe_mac_X540:
2306 mask |= IXGBE_EIMS_TS;
2307 break;
2308 default:
2309 break;
2310 }
2c4af694
AD		 2311 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2312 mask |= IXGBE_EIMS_GPI_SDP1;
2313 switch (adapter->hw.mac.type) {
2314 case ixgbe_mac_82599EB:
2c4af694
AD		 2315 mask |= IXGBE_EIMS_GPI_SDP1;
2316 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2317 case ixgbe_mac_X540:
2318 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2319 mask |= IXGBE_EIMS_MAILBOX;
2320 break;
2321 default:
2322 break;
9a799d71 2323 }
2c4af694
AD		 2324 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2325 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2326 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2327
2c4af694
AD		 2328 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2329 if (queues)
2330 ixgbe_irq_enable_queues(adapter, ~0);
2331 if (flush)
2332 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2333}
2334
2c4af694 2335static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2336{
a65151ba 2337 struct ixgbe_adapter *adapter = data;
9a799d71 2338 struct ixgbe_hw *hw = &adapter->hw;
54037505 2339 u32 eicr;
91281fd3 2340
54037505
DS		 2341 /*
2342 * Workaround for Silicon errata. Use clear-by-write instead
2343 * of clear-by-read. Reading with EICS will return the
2344 * interrupt causes without clearing, which later be done
2345 * with the write to EICR.
2346 */
2347 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2348 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2349
cf8280ee
JB		 2350 if (eicr & IXGBE_EICR_LSC)
2351 ixgbe_check_lsc(adapter);
f0848276 2352
1cdd1ec8
GR		 2353 if (eicr & IXGBE_EICR_MAILBOX)
2354 ixgbe_msg_task(adapter);
efe3d3c8 2355
bd508178
AD		 2356 switch (hw->mac.type) {
2357 case ixgbe_mac_82599EB:
b93a2226 2358 case ixgbe_mac_X540:
2c4af694
AD		 2359 if (eicr & IXGBE_EICR_ECC)
2360 e_info(link, "Received unrecoverable ECC Err, please "
2361 "reboot\n");
c4cf55e5
PWJ		 2362 /* Handle Flow Director Full threshold interrupt */
2363 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2364 int reinit_count = 0;
c4cf55e5 2365 int i;
c4cf55e5 2366 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2367 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2368 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2369 &ring->state))
2370 reinit_count++;
2371 }
2372 if (reinit_count) {
2373 /* no more flow director interrupts until after init */
2374 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2375 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2376 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2377 }
2378 }
f0f9778d 2379 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2380 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2381 break;
2382 default:
2383 break;
c4cf55e5 2384 }
f0848276 2385
bd508178 2386 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2387#ifdef CONFIG_IXGBE_PTP
2388 ixgbe_ptp_check_pps_event(adapter, eicr);
2389#endif
efe3d3c8 2390
7086400d 2391 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2392 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2393 ixgbe_irq_enable(adapter, false, false);
f0848276 2394
9a799d71 2395 return IRQ_HANDLED;
f0848276 2396}
91281fd3 2397
4ff7fb12 2398static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2399{
021230d4 2400 struct ixgbe_q_vector *q_vector = data;
91281fd3 2401
9b471446 2402 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2403
4ff7fb12
AD		 2404 if (q_vector->rx.ring || q_vector->tx.ring)
2405 napi_schedule(&q_vector->napi);
91281fd3 2406
9a799d71 2407 return IRQ_HANDLED;
91281fd3
AD		 2408}
2409
eb01b975
AD		 2410/**
2411 * ixgbe_poll - NAPI Rx polling callback
2412 * @napi: structure for representing this polling device
2413 * @budget: how many packets driver is allowed to clean
2414 *
2415 * This function is used for legacy and MSI, NAPI mode
2416 **/
8af3c33f 2417int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2418{
2419 struct ixgbe_q_vector *q_vector =
2420 container_of(napi, struct ixgbe_q_vector, napi);
2421 struct ixgbe_adapter *adapter = q_vector->adapter;
2422 struct ixgbe_ring *ring;
2423 int per_ring_budget;
2424 bool clean_complete = true;
2425
2426#ifdef CONFIG_IXGBE_DCA
2427 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2428 ixgbe_update_dca(q_vector);
2429#endif
2430
2431 ixgbe_for_each_ring(ring, q_vector->tx)
2432 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2433
2434 /* attempt to distribute budget to each queue fairly, but don't allow
2435 * the budget to go below 1 because we'll exit polling */
2436 if (q_vector->rx.count > 1)
2437 per_ring_budget = max(budget/q_vector->rx.count, 1);
2438 else
2439 per_ring_budget = budget;
2440
2441 ixgbe_for_each_ring(ring, q_vector->rx)
2442 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2443 per_ring_budget);
2444
2445 /* If all work not completed, return budget and keep polling */
2446 if (!clean_complete)
2447 return budget;
2448
2449 /* all work done, exit the polling mode */
2450 napi_complete(napi);
2451 if (adapter->rx_itr_setting & 1)
2452 ixgbe_set_itr(q_vector);
2453 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2454 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2455
2456 return 0;
2457}
2458
021230d4
AV		 2459/**
2460 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2461 * @adapter: board private structure
2462 *
2463 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2464 * interrupts from the kernel.
2465 **/
2466static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2467{
2468 struct net_device *netdev = adapter->netdev;
207867f5 2469 int vector, err;
e8e9f696 2470 int ri = 0, ti = 0;
021230d4 2471
49c7ffbe 2472 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2473 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2474 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2475
4ff7fb12 2476 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2477 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2478 "%s-%s-%d", netdev->name, "TxRx", ri++);
2479 ti++;
2480 } else if (q_vector->rx.ring) {
9fe93afd 2481 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2482 "%s-%s-%d", netdev->name, "rx", ri++);
2483 } else if (q_vector->tx.ring) {
9fe93afd 2484 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2485 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2486 } else {
2487 /* skip this unused q_vector */
2488 continue;
32aa77a4 2489 }
207867f5
AD		 2490 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2491 q_vector->name, q_vector);
9a799d71 2492 if (err) {
396e799c 2493 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2494 "Error: %d\n", err);
021230d4 2495 goto free_queue_irqs;
9a799d71 2496 }
207867f5
AD		 2497 /* If Flow Director is enabled, set interrupt affinity */
2498 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2499 /* assign the mask for this irq */
2500 irq_set_affinity_hint(entry->vector,
de88eeeb 2501 &q_vector->affinity_mask);
207867f5 2502 }
9a799d71
AK		 2503 }
2504
021230d4 2505 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2506 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2507 if (err) {
de88eeeb 2508 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2509 goto free_queue_irqs;
9a799d71
AK		 2510 }
2511
9a799d71
AK		 2512 return 0;
2513
021230d4 2514free_queue_irqs:
207867f5
AD		 2515 while (vector) {
2516 vector--;
2517 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2518 NULL);
2519 free_irq(adapter->msix_entries[vector].vector,
2520 adapter->q_vector[vector]);
2521 }
021230d4
AV		 2522 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2523 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2524 kfree(adapter->msix_entries);
2525 adapter->msix_entries = NULL;
9a799d71
AK		 2526 return err;
2527}
2528
2529/**
021230d4 2530 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2531 * @irq: interrupt number
2532 * @data: pointer to a network interface device structure
9a799d71
AK		 2533 **/
2534static irqreturn_t ixgbe_intr(int irq, void *data)
2535{
a65151ba 2536 struct ixgbe_adapter *adapter = data;
9a799d71 2537 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2538 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2539 u32 eicr;
2540
54037505 2541 /*
24ddd967 2542 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2543 * before the read of EICR.
2544 */
2545 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2546
021230d4 2547 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2548 * therefore no explicit interrupt disable is necessary */
021230d4 2549 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2550 if (!eicr) {
6af3b9eb
ET		 2551 /*
2552 * shared interrupt alert!
f47cf66e 2553 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2554 * have disabled interrupts due to EIAM
2555 * finish the workaround of silicon errata on 82598. Unmask
2556 * the interrupt that we masked before the EICR read.
2557 */
2558 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2559 ixgbe_irq_enable(adapter, true, true);
9a799d71 2560 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2561 }
9a799d71 2562
cf8280ee
JB		 2563 if (eicr & IXGBE_EICR_LSC)
2564 ixgbe_check_lsc(adapter);
021230d4 2565
bd508178
AD		 2566 switch (hw->mac.type) {
2567 case ixgbe_mac_82599EB:
e8e26350 2568 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2569 /* Fall through */
2570 case ixgbe_mac_X540:
2571 if (eicr & IXGBE_EICR_ECC)
2572 e_info(link, "Received unrecoverable ECC err, please "
2573 "reboot\n");
4f51bf70 2574 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2575 break;
2576 default:
2577 break;
2578 }
e8e26350 2579
0befdb3e 2580 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2581#ifdef CONFIG_IXGBE_PTP
2582 ixgbe_ptp_check_pps_event(adapter, eicr);
2583#endif
0befdb3e 2584
b9f6ed2b
AD		 2585 /* would disable interrupts here but EIAM disabled it */
2586 napi_schedule(&q_vector->napi);
9a799d71 2587
6af3b9eb
ET		 2588 /*
2589 * re-enable link(maybe) and non-queue interrupts, no flush.
2590 * ixgbe_poll will re-enable the queue interrupts
2591 */
6af3b9eb
ET		 2592 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2593 ixgbe_irq_enable(adapter, false, false);
2594
9a799d71
AK		 2595 return IRQ_HANDLED;
2596}
2597
2598/**
2599 * ixgbe_request_irq - initialize interrupts
2600 * @adapter: board private structure
2601 *
2602 * Attempts to configure interrupts using the best available
2603 * capabilities of the hardware and kernel.
2604 **/
021230d4 2605static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2606{
2607 struct net_device *netdev = adapter->netdev;
021230d4 2608 int err;
9a799d71 2609
4cc6df29 2610 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2611 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2612 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2613 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2614 netdev->name, adapter);
4cc6df29 2615 else
a0607fd3 2616 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2617 netdev->name, adapter);
9a799d71 2618
de88eeeb 2619 if (err)
396e799c 2620 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2621
9a799d71
AK		 2622 return err;
2623}
2624
2625static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2626{
49c7ffbe 2627 int vector;
9a799d71 2628
49c7ffbe
AD		 2629 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2630 free_irq(adapter->pdev->irq, adapter);
2631 return;
2632 }
4cc6df29 2633
49c7ffbe
AD		 2634 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2635 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2636 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2637
49c7ffbe
AD		 2638 /* free only the irqs that were actually requested */
2639 if (!q_vector->rx.ring && !q_vector->tx.ring)
2640 continue;
207867f5 2641
49c7ffbe
AD		 2642 /* clear the affinity_mask in the IRQ descriptor */
2643 irq_set_affinity_hint(entry->vector, NULL);
2644
2645 free_irq(entry->vector, q_vector);
9a799d71 2646 }
49c7ffbe
AD		 2647
2648 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2649}
2650
22d5a71b
JB		 2651/**
2652 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2653 * @adapter: board private structure
2654 **/
2655static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2656{
bd508178
AD		 2657 switch (adapter->hw.mac.type) {
2658 case ixgbe_mac_82598EB:
835462fc 2659 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2660 break;
2661 case ixgbe_mac_82599EB:
b93a2226 2662 case ixgbe_mac_X540:
835462fc
NS		 2663 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2664 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2665 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2666 break;
2667 default:
2668 break;
22d5a71b
JB		 2669 }
2670 IXGBE_WRITE_FLUSH(&adapter->hw);
2671 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2672 int vector;
2673
2674 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2675 synchronize_irq(adapter->msix_entries[vector].vector);
2676
2677 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2678 } else {
2679 synchronize_irq(adapter->pdev->irq);
2680 }
2681}
2682
9a799d71
AK		 2683/**
2684 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2685 *
2686 **/
2687static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2688{
d5bf4f67 2689 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2690
d5bf4f67
ET		 2691 /* rx/tx vector */
2692 if (adapter->rx_itr_setting == 1)
2693 q_vector->itr = IXGBE_20K_ITR;
2694 else
2695 q_vector->itr = adapter->rx_itr_setting;
2696
2697 ixgbe_write_eitr(q_vector);
9a799d71 2698
e8e26350
PW		 2699 ixgbe_set_ivar(adapter, 0, 0, 0);
2700 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2701
396e799c 2702 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2703}
2704
43e69bf0
AD		 2705/**
2706 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2707 * @adapter: board private structure
2708 * @ring: structure containing ring specific data
2709 *
2710 * Configure the Tx descriptor ring after a reset.
2711 **/
84418e3b
AD		 2712void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2713 struct ixgbe_ring *ring)
43e69bf0
AD		 2714{
2715 struct ixgbe_hw *hw = &adapter->hw;
2716 u64 tdba = ring->dma;
2f1860b8 2717 int wait_loop = 10;
b88c6de2 2718 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2719 u8 reg_idx = ring->reg_idx;
43e69bf0 2720
2f1860b8 2721 /* disable queue to avoid issues while updating state */
b88c6de2 2722 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2723 IXGBE_WRITE_FLUSH(hw);
2724
43e69bf0 2725 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2726 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2727 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2728 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2729 ring->count * sizeof(union ixgbe_adv_tx_desc));
2730 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2731 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2732 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2733
b88c6de2
AD		 2734 /*
2735 * set WTHRESH to encourage burst writeback, it should not be set
2736 * higher than 1 when ITR is 0 as it could cause false TX hangs
2737 *
2738 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2739 * to or less than the number of on chip descriptors, which is
2740 * currently 40.
2741 */
e954b374 2742 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2743 txdctl |= (1 << 16); /* WTHRESH = 1 */
2744 else
2745 txdctl |= (8 << 16); /* WTHRESH = 8 */
2746
e954b374
AD		 2747 /*
2748 * Setting PTHRESH to 32 both improves performance
2749 * and avoids a TX hang with DFP enabled
2750 */
b88c6de2
AD		 2751 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2752 32; /* PTHRESH = 32 */
2f1860b8
AD		 2753
2754 /* reinitialize flowdirector state */
39cb681b 2755 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2756 ring->atr_sample_rate = adapter->atr_sample_rate;
2757 ring->atr_count = 0;
2758 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2759 } else {
2760 ring->atr_sample_rate = 0;
2761 }
2f1860b8 2762
c84d324c
JF		 2763 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2764
2f1860b8 2765 /* enable queue */
2f1860b8
AD		 2766 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2767
2768 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2769 if (hw->mac.type == ixgbe_mac_82598EB &&
2770 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2771 return;
2772
2773 /* poll to verify queue is enabled */
2774 do {
032b4325 2775 usleep_range(1000, 2000);
2f1860b8
AD		 2776 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2777 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2778 if (!wait_loop)
2779 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2780}
2781
120ff942
AD		 2782static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2783{
2784 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2785 u32 rttdcs, mtqc;
8b1c0b24 2786 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2787
2788 if (hw->mac.type == ixgbe_mac_82598EB)
2789 return;
2790
2791 /* disable the arbiter while setting MTQC */
2792 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2793 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2794 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2795
2796 /* set transmit pool layout */
671c0adb
AD		 2797 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2798 mtqc = IXGBE_MTQC_VT_ENA;
2799 if (tcs > 4)
2800 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2801 else if (tcs > 1)
2802 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2803 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2804 mtqc |= IXGBE_MTQC_32VF;
2805 else
2806 mtqc |= IXGBE_MTQC_64VF;
2807 } else {
2808 if (tcs > 4)
2809 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2810 else if (tcs > 1)
2811 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2812 else
671c0adb
AD		 2813 mtqc = IXGBE_MTQC_64Q_1PB;
2814 }
120ff942 2815
671c0adb 2816 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2817
671c0adb
AD		 2818 /* Enable Security TX Buffer IFG for multiple pb */
2819 if (tcs) {
2820 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2821 sectx |= IXGBE_SECTX_DCB;
2822 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2823 }
2824
2825 /* re-enable the arbiter */
2826 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2827 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2828}
2829
9a799d71 2830/**
3a581073 2831 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2832 * @adapter: board private structure
2833 *
2834 * Configure the Tx unit of the MAC after a reset.
2835 **/
2836static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2837{
2f1860b8
AD		 2838 struct ixgbe_hw *hw = &adapter->hw;
2839 u32 dmatxctl;
43e69bf0 2840 u32 i;
9a799d71 2841
2f1860b8
AD		 2842 ixgbe_setup_mtqc(adapter);
2843
2844 if (hw->mac.type != ixgbe_mac_82598EB) {
2845 /* DMATXCTL.EN must be before Tx queues are enabled */
2846 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2847 dmatxctl |= IXGBE_DMATXCTL_TE;
2848 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2849 }
2850
9a799d71 2851 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2852 for (i = 0; i < adapter->num_tx_queues; i++)
2853 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2854}
2855
3ebe8fde
AD		 2856static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2857 struct ixgbe_ring *ring)
2858{
2859 struct ixgbe_hw *hw = &adapter->hw;
2860 u8 reg_idx = ring->reg_idx;
2861 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2862
2863 srrctl |= IXGBE_SRRCTL_DROP_EN;
2864
2865 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2866}
2867
2868static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2869 struct ixgbe_ring *ring)
2870{
2871 struct ixgbe_hw *hw = &adapter->hw;
2872 u8 reg_idx = ring->reg_idx;
2873 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2874
2875 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2876
2877 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2878}
2879
2880#ifdef CONFIG_IXGBE_DCB
2881void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2882#else
2883static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2884#endif
2885{
2886 int i;
2887 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2888
2889 if (adapter->ixgbe_ieee_pfc)
2890 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2891
2892 /*
2893 * We should set the drop enable bit if:
2894 * SR-IOV is enabled
2895 * or
2896 * Number of Rx queues > 1 and flow control is disabled
2897 *
2898 * This allows us to avoid head of line blocking for security
2899 * and performance reasons.
2900 */
2901 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2902 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2903 for (i = 0; i < adapter->num_rx_queues; i++)
2904 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2905 } else {
2906 for (i = 0; i < adapter->num_rx_queues; i++)
2907 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2908 }
2909}
2910
e8e26350 2911#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2912
a6616b42 2913static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2914 struct ixgbe_ring *rx_ring)
cc41ac7c 2915{
45e9baa5 2916 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2917 u32 srrctl;
bf29ee6c 2918 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2919
45e9baa5
AD		 2920 if (hw->mac.type == ixgbe_mac_82598EB) {
2921 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2922
45e9baa5
AD		 2923 /*
2924 * if VMDq is not active we must program one srrctl register
2925 * per RSS queue since we have enabled RDRXCTL.MVMEN
2926 */
2927 reg_idx &= mask;
2928 }
cc41ac7c 2929
45e9baa5
AD		 2930 /* configure header buffer length, needed for RSC */
2931 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2932
45e9baa5 2933 /* configure the packet buffer length */
f800326d 2934 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 2935
2936 /* configure descriptor type */
f800326d 2937 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2938
45e9baa5 2939 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2940}
9a799d71 2941
05abb126 2942static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2943{
05abb126
AD		 2944 struct ixgbe_hw *hw = &adapter->hw;
2945 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2946 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2947 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2948 u32 mrqc = 0, reta = 0;
2949 u32 rxcsum;
2950 int i, j;
671c0adb
AD		 2951 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2952
671c0adb
AD		 2953 /*
2954 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2955 * make full use of any rings they may have. We will use the
2956 * PSRTYPE register to control how many rings we use within the PF.
2957 */
2958 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
2959 rss_i = 2;
0cefafad 2960
05abb126
AD		 2961 /* Fill out hash function seeds */
2962 for (i = 0; i < 10; i++)
2963 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2964
2965 /* Fill out redirection table */
2966 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 2967 if (j == rss_i)
05abb126
AD		 2968 j = 0;
2969 /* reta = 4-byte sliding window of
2970 * 0x00..(indices-1)(indices-1)00..etc. */
2971 reta = (reta << 8) | (j * 0x11);
2972 if ((i & 3) == 3)
2973 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2974 }
0cefafad 2975
05abb126
AD		 2976 /* Disable indicating checksum in descriptor, enables RSS hash */
2977 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2978 rxcsum |= IXGBE_RXCSUM_PCSD;
2979 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2980
671c0adb 2981 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 2982 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 2983 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2984 } else {
671c0adb
AD		 2985 u8 tcs = netdev_get_num_tc(adapter->netdev);
2986
2987 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2988 if (tcs > 4)
2989 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
2990 else if (tcs > 1)
2991 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
2992 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2993 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 2994 else
671c0adb
AD		 2995 mrqc = IXGBE_MRQC_VMDQRSS64EN;
2996 } else {
2997 if (tcs > 4)
8b1c0b24 2998 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 2999 else if (tcs > 1)
3000 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3001 else
3002 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3003 }
0cefafad
JB		 3004 }
3005
05abb126 3006 /* Perform hash on these packet types */
671c0adb
AD		 3007 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3008 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3009 IXGBE_MRQC_RSS_FIELD_IPV6 |
3010 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3011
ef6afc0c
AD		 3012 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3013 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3014 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3015 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3016
05abb126 3017 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3018}
3019
bb5a9ad2
NS		 3020/**
3021 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3022 * @adapter: address of board private structure
3023 * @index: index of ring to set
bb5a9ad2 3024 **/
082757af 3025static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3026 struct ixgbe_ring *ring)
bb5a9ad2 3027{
bb5a9ad2 3028 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3029 u32 rscctrl;
bf29ee6c 3030 u8 reg_idx = ring->reg_idx;
7367096a 3031
7d637bcc 3032 if (!ring_is_rsc_enabled(ring))
7367096a 3033 return;
bb5a9ad2 3034
7367096a 3035 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3036 rscctrl |= IXGBE_RSCCTL_RSCEN;
3037 /*
3038 * we must limit the number of descriptors so that the
3039 * total size of max desc * buf_len is not greater
642c680e 3040 * than 65536
bb5a9ad2 3041 */
f800326d 3042 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3043 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3044}
3045
9e10e045
AD		 3046#define IXGBE_MAX_RX_DESC_POLL 10
3047static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3048 struct ixgbe_ring *ring)
3049{
3050 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3051 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3052 u32 rxdctl;
bf29ee6c 3053 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3054
3055 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3056 if (hw->mac.type == ixgbe_mac_82598EB &&
3057 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3058 return;
3059
3060 do {
032b4325 3061 usleep_range(1000, 2000);
9e10e045
AD		 3062 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3063 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3064
3065 if (!wait_loop) {
3066 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3067 "the polling period\n", reg_idx);
3068 }
3069}
3070
2d39d576
YZ		 3071void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3072 struct ixgbe_ring *ring)
3073{
3074 struct ixgbe_hw *hw = &adapter->hw;
3075 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3076 u32 rxdctl;
3077 u8 reg_idx = ring->reg_idx;
3078
3079 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3080 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3081
3082 /* write value back with RXDCTL.ENABLE bit cleared */
3083 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3084
3085 if (hw->mac.type == ixgbe_mac_82598EB &&
3086 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3087 return;
3088
3089 /* the hardware may take up to 100us to really disable the rx queue */
3090 do {
3091 udelay(10);
3092 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3093 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3094
3095 if (!wait_loop) {
3096 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3097 "the polling period\n", reg_idx);
3098 }
3099}
3100
84418e3b
AD		 3101void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3102 struct ixgbe_ring *ring)
acd37177
AD		 3103{
3104 struct ixgbe_hw *hw = &adapter->hw;
3105 u64 rdba = ring->dma;
9e10e045 3106 u32 rxdctl;
bf29ee6c 3107 u8 reg_idx = ring->reg_idx;
acd37177 3108
9e10e045
AD		 3109 /* disable queue to avoid issues while updating state */
3110 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3111 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3112
acd37177
AD		 3113 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3114 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3115 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3116 ring->count * sizeof(union ixgbe_adv_rx_desc));
3117 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3118 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3119 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3120
3121 ixgbe_configure_srrctl(adapter, ring);
3122 ixgbe_configure_rscctl(adapter, ring);
3123
e9f98072
GR		 3124 /* If operating in IOV mode set RLPML for X540 */
3125 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3126 hw->mac.type == ixgbe_mac_X540) {
3127 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3128 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3129 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3130 }
3131
9e10e045
AD		 3132 if (hw->mac.type == ixgbe_mac_82598EB) {
3133 /*
3134 * enable cache line friendly hardware writes:
3135 * PTHRESH=32 descriptors (half the internal cache),
3136 * this also removes ugly rx_no_buffer_count increment
3137 * HTHRESH=4 descriptors (to minimize latency on fetch)
3138 * WTHRESH=8 burst writeback up to two cache lines
3139 */
3140 rxdctl &= ~0x3FFFFF;
3141 rxdctl |= 0x080420;
3142 }
3143
3144 /* enable receive descriptor ring */
3145 rxdctl |= IXGBE_RXDCTL_ENABLE;
3146 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3147
3148 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3149 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3150}
3151
48654521
AD		 3152static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3153{
3154 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3155 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3156 int p;
3157
3158 /* PSRTYPE must be initialized in non 82598 adapters */
3159 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3160 IXGBE_PSRTYPE_UDPHDR |
3161 IXGBE_PSRTYPE_IPV4HDR |
48654521 3162 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3163 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3164
3165 if (hw->mac.type == ixgbe_mac_82598EB)
3166 return;
3167
fbe7ca7f
AD		 3168 if (rss_i > 3)
3169 psrtype |= 2 << 29;
3170 else if (rss_i > 1)
3171 psrtype |= 1 << 29;
48654521
AD		 3172
3173 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3174 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3175 psrtype);
3176}
3177
f5b4a52e
AD		 3178static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3179{
3180 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3181 u32 reg_offset, vf_shift;
435b19f6 3182 u32 gcr_ext, vmdctl;
de4c7f65 3183 int i;
f5b4a52e
AD		 3184
3185 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3186 return;
3187
3188 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3189 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3190 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3191 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3192 vmdctl |= IXGBE_VT_CTL_REPLEN;
3193 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3194
1d9c0bfd
AD		 3195 vf_shift = VMDQ_P(0) % 32;
3196 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3197
3198 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3199 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3200 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3201 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3202 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3203 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3204
3205 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3206 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3207
3208 /*
3209 * Set up VF register offsets for selected VT Mode,
3210 * i.e. 32 or 64 VFs for SR-IOV
3211 */
73079ea0
AD		 3212 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3213 case IXGBE_82599_VMDQ_8Q_MASK:
3214 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3215 break;
3216 case IXGBE_82599_VMDQ_4Q_MASK:
3217 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3218 break;
3219 default:
3220 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3221 break;
3222 }
3223
f5b4a52e
AD		 3224 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3225
3226 /* enable Tx loopback for VF/PF communication */
3227 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
435b19f6 3228
a985b6c3 3229 /* Enable MAC Anti-Spoofing */
435b19f6 3230 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3231 adapter->num_vfs);
de4c7f65
GR		 3232 /* For VFs that have spoof checking turned off */
3233 for (i = 0; i < adapter->num_vfs; i++) {
3234 if (!adapter->vfinfo[i].spoofchk_enabled)
3235 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3236 }
f5b4a52e
AD		 3237}
3238
477de6ed 3239static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3240{
9a799d71
AK		 3241 struct ixgbe_hw *hw = &adapter->hw;
3242 struct net_device *netdev = adapter->netdev;
3243 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3244 struct ixgbe_ring *rx_ring;
3245 int i;
3246 u32 mhadd, hlreg0;
48654521 3247
63f39bd1 3248#ifdef IXGBE_FCOE
477de6ed
AD		 3249 /* adjust max frame to be able to do baby jumbo for FCoE */
3250 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3251 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3252 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3253
477de6ed
AD		 3254#endif /* IXGBE_FCOE */
3255 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3256 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3257 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3258 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3259
3260 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3261 }
3262
919e78a6
AD		 3263 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3264 max_frame += VLAN_HLEN;
3265
477de6ed
AD		 3266 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3267 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3268 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3269 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3270
0cefafad
JB		 3271 /*
3272 * Setup the HW Rx Head and Tail Descriptor Pointers and
3273 * the Base and Length of the Rx Descriptor Ring
3274 */
9a799d71 3275 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3276 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3277 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3278 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3279 else
7d637bcc 3280 clear_ring_rsc_enabled(rx_ring);
477de6ed 3281 }
477de6ed
AD		 3282}
3283
7367096a
AD		 3284static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3285{
3286 struct ixgbe_hw *hw = &adapter->hw;
3287 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3288
3289 switch (hw->mac.type) {
3290 case ixgbe_mac_82598EB:
3291 /*
3292 * For VMDq support of different descriptor types or
3293 * buffer sizes through the use of multiple SRRCTL
3294 * registers, RDRXCTL.MVMEN must be set to 1
3295 *
3296 * also, the manual doesn't mention it clearly but DCA hints
3297 * will only use queue 0's tags unless this bit is set. Side
3298 * effects of setting this bit are only that SRRCTL must be
3299 * fully programmed [0..15]
3300 */
3301 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3302 break;
3303 case ixgbe_mac_82599EB:
b93a2226 3304 case ixgbe_mac_X540:
7367096a
AD		 3305 /* Disable RSC for ACK packets */
3306 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3307 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3308 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3309 /* hardware requires some bits to be set by default */
3310 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3311 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3312 break;
3313 default:
3314 /* We should do nothing since we don't know this hardware */
3315 return;
3316 }
3317
3318 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3319}
3320
477de6ed
AD		 3321/**
3322 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3323 * @adapter: board private structure
3324 *
3325 * Configure the Rx unit of the MAC after a reset.
3326 **/
3327static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3328{
3329 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3330 int i;
3331 u32 rxctrl;
477de6ed
AD		 3332
3333 /* disable receives while setting up the descriptors */
3334 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3335 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3336
3337 ixgbe_setup_psrtype(adapter);
7367096a 3338 ixgbe_setup_rdrxctl(adapter);
477de6ed 3339
9e10e045 3340 /* Program registers for the distribution of queues */
f5b4a52e 3341 ixgbe_setup_mrqc(adapter);
f5b4a52e 3342
477de6ed
AD		 3343 /* set_rx_buffer_len must be called before ring initialization */
3344 ixgbe_set_rx_buffer_len(adapter);
3345
3346 /*
3347 * Setup the HW Rx Head and Tail Descriptor Pointers and
3348 * the Base and Length of the Rx Descriptor Ring
3349 */
9e10e045
AD		 3350 for (i = 0; i < adapter->num_rx_queues; i++)
3351 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3352
9e10e045
AD		 3353 /* disable drop enable for 82598 parts */
3354 if (hw->mac.type == ixgbe_mac_82598EB)
3355 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3356
3357 /* enable all receives */
3358 rxctrl |= IXGBE_RXCTRL_RXEN;
3359 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3360}
3361
8e586137 3362static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3363{
3364 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3365 struct ixgbe_hw *hw = &adapter->hw;
3366
3367 /* add VID to filter table */
1d9c0bfd 3368 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3369 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3370
3371 return 0;
068c89b0
DS		 3372}
3373
8e586137 3374static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3375{
3376 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3377 struct ixgbe_hw *hw = &adapter->hw;
3378
068c89b0 3379 /* remove VID from filter table */
1d9c0bfd 3380 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3381 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3382
3383 return 0;
068c89b0
DS		 3384}
3385
5f6c0181
JB		 3386/**
3387 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3388 * @adapter: driver data
3389 */
3390static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3391{
3392 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3393 u32 vlnctrl;
3394
3395 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3396 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3397 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3398}
3399
3400/**
3401 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3402 * @adapter: driver data
3403 */
3404static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3405{
3406 struct ixgbe_hw *hw = &adapter->hw;
3407 u32 vlnctrl;
3408
3409 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3410 vlnctrl |= IXGBE_VLNCTRL_VFE;
3411 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3412 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3413}
3414
3415/**
3416 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3417 * @adapter: driver data
3418 */
3419static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3420{
3421 struct ixgbe_hw *hw = &adapter->hw;
3422 u32 vlnctrl;
5f6c0181
JB		 3423 int i, j;
3424
3425 switch (hw->mac.type) {
3426 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3427 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3428 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3429 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3430 break;
3431 case ixgbe_mac_82599EB:
b93a2226 3432 case ixgbe_mac_X540:
5f6c0181
JB		 3433 for (i = 0; i < adapter->num_rx_queues; i++) {
3434 j = adapter->rx_ring[i]->reg_idx;
3435 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3436 vlnctrl &= ~IXGBE_RXDCTL_VME;
3437 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3438 }
3439 break;
3440 default:
3441 break;
3442 }
3443}
3444
3445/**
f62bbb5e 3446 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3447 * @adapter: driver data
3448 */
f62bbb5e 3449static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3450{
3451 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3452 u32 vlnctrl;
5f6c0181
JB		 3453 int i, j;
3454
3455 switch (hw->mac.type) {
3456 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3457 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3458 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3459 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3460 break;
3461 case ixgbe_mac_82599EB:
b93a2226 3462 case ixgbe_mac_X540:
5f6c0181
JB		 3463 for (i = 0; i < adapter->num_rx_queues; i++) {
3464 j = adapter->rx_ring[i]->reg_idx;
3465 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3466 vlnctrl |= IXGBE_RXDCTL_VME;
3467 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3468 }
3469 break;
3470 default:
3471 break;
3472 }
3473}
3474
9a799d71
AK		 3475static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3476{
f62bbb5e 3477 u16 vid;
9a799d71 3478
f62bbb5e
JG		 3479 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3480
3481 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3482 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3483}
3484
2850062a
AD		 3485/**
3486 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3487 * @netdev: network interface device structure
3488 *
3489 * Writes unicast address list to the RAR table.
3490 * Returns: -ENOMEM on failure/insufficient address space
3491 * 0 on no addresses written
3492 * X on writing X addresses to the RAR table
3493 **/
3494static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3495{
3496 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3497 struct ixgbe_hw *hw = &adapter->hw;
95447461 3498 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3499 int count = 0;
3500
95447461
JF		 3501 /* In SR-IOV mode significantly less RAR entries are available */
3502 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3503 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3504
2850062a
AD		 3505 /* return ENOMEM indicating insufficient memory for addresses */
3506 if (netdev_uc_count(netdev) > rar_entries)
3507 return -ENOMEM;
3508
95447461 3509 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3510 struct netdev_hw_addr *ha;
3511 /* return error if we do not support writing to RAR table */
3512 if (!hw->mac.ops.set_rar)
3513 return -ENOMEM;
3514
3515 netdev_for_each_uc_addr(ha, netdev) {
3516 if (!rar_entries)
3517 break;
3518 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3519 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3520 count++;
3521 }
3522 }
3523 /* write the addresses in reverse order to avoid write combining */
3524 for (; rar_entries > 0 ; rar_entries--)
3525 hw->mac.ops.clear_rar(hw, rar_entries);
3526
3527 return count;
3528}
3529
9a799d71 3530/**
2c5645cf 3531 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3532 * @netdev: network interface device structure
3533 *
2c5645cf
CL		 3534 * The set_rx_method entry point is called whenever the unicast/multicast
3535 * address list or the network interface flags are updated. This routine is
3536 * responsible for configuring the hardware for proper unicast, multicast and
3537 * promiscuous mode.
9a799d71 3538 **/
7f870475 3539void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3540{
3541 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3542 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3543 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3544 int count;
9a799d71
AK		 3545
3546 /* Check for Promiscuous and All Multicast modes */
3547
3548 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3549
f5dc442b 3550 /* set all bits that we expect to always be set */
3f2d1c0f 3551 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3552 fctrl |= IXGBE_FCTRL_BAM;
3553 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3554 fctrl |= IXGBE_FCTRL_PMCF;
3555
2850062a
AD		 3556 /* clear the bits we are changing the status of */
3557 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3558
9a799d71 3559 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3560 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3561 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3562 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3563 /* don't hardware filter vlans in promisc mode */
3564 ixgbe_vlan_filter_disable(adapter);
9a799d71 3565 } else {
746b9f02
PM		 3566 if (netdev->flags & IFF_ALLMULTI) {
3567 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3568 vmolr |= IXGBE_VMOLR_MPE;
3569 } else {
3570 /*
3571 * Write addresses to the MTA, if the attempt fails
25985edc 3572 * then we should just turn on promiscuous mode so
2850062a
AD		 3573 * that we can at least receive multicast traffic
3574 */
3575 hw->mac.ops.update_mc_addr_list(hw, netdev);
3576 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3577 }
5f6c0181 3578 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3579 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3580 }
3581
3582 /*
3583 * Write addresses to available RAR registers, if there is not
3584 * sufficient space to store all the addresses then enable
3585 * unicast promiscuous mode
3586 */
3587 count = ixgbe_write_uc_addr_list(netdev);
3588 if (count < 0) {
3589 fctrl |= IXGBE_FCTRL_UPE;
3590 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3591 }
3592
1d9c0bfd 3593 if (adapter->num_vfs)
1cdd1ec8 3594 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3595
3596 if (hw->mac.type != ixgbe_mac_82598EB) {
3597 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3598 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3599 IXGBE_VMOLR_ROPE);
1d9c0bfd 3600 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3601 }
3602
3f2d1c0f
BG		 3603 /* This is useful for sniffing bad packets. */
3604 if (adapter->netdev->features & NETIF_F_RXALL) {
3605 /* UPE and MPE will be handled by normal PROMISC logic
3606 * in e1000e_set_rx_mode */
3607 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3608 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3609 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3610
3611 fctrl &= ~(IXGBE_FCTRL_DPF);
3612 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3613 }
3614
2850062a 3615 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3616
3617 if (netdev->features & NETIF_F_HW_VLAN_RX)
3618 ixgbe_vlan_strip_enable(adapter);
3619 else
3620 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3621}
3622
021230d4
AV		 3623static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3624{
3625 int q_idx;
021230d4 3626
49c7ffbe
AD		 3627 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3628 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3629}
3630
3631static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3632{
3633 int q_idx;
021230d4 3634
49c7ffbe
AD		 3635 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3636 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3637}
3638
7a6b6f51 3639#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3640/**
2f90b865
AD		 3641 * ixgbe_configure_dcb - Configure DCB hardware
3642 * @adapter: ixgbe adapter struct
3643 *
3644 * This is called by the driver on open to configure the DCB hardware.
3645 * This is also called by the gennetlink interface when reconfiguring
3646 * the DCB state.
3647 */
3648static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3649{
3650 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3651 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3652
67ebd791
AD		 3653 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3654 if (hw->mac.type == ixgbe_mac_82598EB)
3655 netif_set_gso_max_size(adapter->netdev, 65536);
3656 return;
3657 }
3658
3659 if (hw->mac.type == ixgbe_mac_82598EB)
3660 netif_set_gso_max_size(adapter->netdev, 32768);
3661
2f90b865 3662 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3663
971060b1 3664#ifdef IXGBE_FCOE
b120818e
JF		 3665 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3666 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3667#endif
b120818e
JF		 3668
3669 /* reconfigure the hardware */
3670 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3671 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3672 DCB_TX_CONFIG);
3673 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3674 DCB_RX_CONFIG);
3675 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3676 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3677 ixgbe_dcb_hw_ets(&adapter->hw,
3678 adapter->ixgbe_ieee_ets,
3679 max_frame);
3680 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3681 adapter->ixgbe_ieee_pfc->pfc_en,
3682 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3683 }
8187cd48
JF		 3684
3685 /* Enable RSS Hash per TC */
3686 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3687 u32 msb = 0;
3688 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3689
d411a936
AD		 3690 while (rss_i) {
3691 msb++;
3692 rss_i >>= 1;
3693 }
8187cd48 3694
4ae63730
AD		 3695 /* write msb to all 8 TCs in one write */
3696 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3697 }
2f90b865 3698}
9da712d2
JF		 3699#endif
3700
3701/* Additional bittime to account for IXGBE framing */
3702#define IXGBE_ETH_FRAMING 20
3703
49ce9c2c 3704/**
9da712d2
JF		 3705 * ixgbe_hpbthresh - calculate high water mark for flow control
3706 *
3707 * @adapter: board private structure to calculate for
49ce9c2c 3708 * @pb: packet buffer to calculate
9da712d2
JF		 3709 */
3710static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3711{
3712 struct ixgbe_hw *hw = &adapter->hw;
3713 struct net_device *dev = adapter->netdev;
3714 int link, tc, kb, marker;
3715 u32 dv_id, rx_pba;
3716
3717 /* Calculate max LAN frame size */
3718 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3719
3720#ifdef IXGBE_FCOE
3721 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3722 if ((dev->features & NETIF_F_FCOE_MTU) &&
3723 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3724 (pb == ixgbe_fcoe_get_tc(adapter)))
3725 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3726
3727#endif
9da712d2
JF		 3728 /* Calculate delay value for device */
3729 switch (hw->mac.type) {
3730 case ixgbe_mac_X540:
3731 dv_id = IXGBE_DV_X540(link, tc);
3732 break;
3733 default:
3734 dv_id = IXGBE_DV(link, tc);
3735 break;
3736 }
3737
3738 /* Loopback switch introduces additional latency */
3739 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3740 dv_id += IXGBE_B2BT(tc);
3741
3742 /* Delay value is calculated in bit times convert to KB */
3743 kb = IXGBE_BT2KB(dv_id);
3744 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3745
3746 marker = rx_pba - kb;
3747
3748 /* It is possible that the packet buffer is not large enough
3749 * to provide required headroom. In this case throw an error
3750 * to user and a do the best we can.
3751 */
3752 if (marker < 0) {
3753 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3754 "headroom to support flow control."
3755 "Decrease MTU or number of traffic classes\n", pb);
3756 marker = tc + 1;
3757 }
3758
3759 return marker;
3760}
3761
49ce9c2c 3762/**
9da712d2
JF		 3763 * ixgbe_lpbthresh - calculate low water mark for for flow control
3764 *
3765 * @adapter: board private structure to calculate for
49ce9c2c 3766 * @pb: packet buffer to calculate
9da712d2
JF		 3767 */
3768static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3769{
3770 struct ixgbe_hw *hw = &adapter->hw;
3771 struct net_device *dev = adapter->netdev;
3772 int tc;
3773 u32 dv_id;
3774
3775 /* Calculate max LAN frame size */
3776 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3777
3778 /* Calculate delay value for device */
3779 switch (hw->mac.type) {
3780 case ixgbe_mac_X540:
3781 dv_id = IXGBE_LOW_DV_X540(tc);
3782 break;
3783 default:
3784 dv_id = IXGBE_LOW_DV(tc);
3785 break;
3786 }
3787
3788 /* Delay value is calculated in bit times convert to KB */
3789 return IXGBE_BT2KB(dv_id);
3790}
3791
3792/*
3793 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3794 */
3795static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3796{
3797 struct ixgbe_hw *hw = &adapter->hw;
3798 int num_tc = netdev_get_num_tc(adapter->netdev);
3799 int i;
3800
3801 if (!num_tc)
3802 num_tc = 1;
3803
3804 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3805
3806 for (i = 0; i < num_tc; i++) {
3807 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3808
3809 /* Low water marks must not be larger than high water marks */
3810 if (hw->fc.low_water > hw->fc.high_water[i])
3811 hw->fc.low_water = 0;
3812 }
3813}
3814
80605c65
JF		 3815static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3816{
80605c65 3817 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3818 int hdrm;
3819 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3820
3821 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3822 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3823 hdrm = 32 << adapter->fdir_pballoc;
3824 else
3825 hdrm = 0;
80605c65 3826
f7e1027f 3827 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3828 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3829}
3830
e4911d57
AD		 3831static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3832{
3833 struct ixgbe_hw *hw = &adapter->hw;
3834 struct hlist_node *node, *node2;
3835 struct ixgbe_fdir_filter *filter;
3836
3837 spin_lock(&adapter->fdir_perfect_lock);
3838
3839 if (!hlist_empty(&adapter->fdir_filter_list))
3840 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3841
3842 hlist_for_each_entry_safe(filter, node, node2,
3843 &adapter->fdir_filter_list, fdir_node) {
3844 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3845 &filter->filter,
3846 filter->sw_idx,
3847 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3848 IXGBE_FDIR_DROP_QUEUE :
3849 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3850 }
3851
3852 spin_unlock(&adapter->fdir_perfect_lock);
3853}
3854
9a799d71
AK		 3855static void ixgbe_configure(struct ixgbe_adapter *adapter)
3856{
d2f5e7f3
AS		 3857 struct ixgbe_hw *hw = &adapter->hw;
3858
80605c65 3859 ixgbe_configure_pb(adapter);
7a6b6f51 3860#ifdef CONFIG_IXGBE_DCB
67ebd791 3861 ixgbe_configure_dcb(adapter);
2f90b865 3862#endif
9a799d71 3863
4c1d7b4b 3864 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3865 ixgbe_restore_vlan(adapter);
3866
d2f5e7f3
AS		 3867 switch (hw->mac.type) {
3868 case ixgbe_mac_82599EB:
3869 case ixgbe_mac_X540:
3870 hw->mac.ops.disable_rx_buff(hw);
3871 break;
3872 default:
3873 break;
3874 }
3875
c4cf55e5 3876 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3877 ixgbe_init_fdir_signature_82599(&adapter->hw,
3878 adapter->fdir_pballoc);
e4911d57
AD		 3879 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3880 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3881 adapter->fdir_pballoc);
3882 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3883 }
4c1d7b4b 3884
d2f5e7f3
AS		 3885 switch (hw->mac.type) {
3886 case ixgbe_mac_82599EB:
3887 case ixgbe_mac_X540:
3888 hw->mac.ops.enable_rx_buff(hw);
3889 break;
3890 default:
3891 break;
3892 }
3893
933d41f1 3894 ixgbe_configure_virtualization(adapter);
c4cf55e5 3895
7c8ae65a
AD		 3896#ifdef IXGBE_FCOE
3897 /* configure FCoE L2 filters, redirection table, and Rx control */
3898 ixgbe_configure_fcoe(adapter);
3899
3900#endif /* IXGBE_FCOE */
9a799d71
AK		 3901 ixgbe_configure_tx(adapter);
3902 ixgbe_configure_rx(adapter);
9a799d71
AK		 3903}
3904
e8e26350
PW		 3905static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3906{
3907 switch (hw->phy.type) {
3908 case ixgbe_phy_sfp_avago:
3909 case ixgbe_phy_sfp_ftl:
3910 case ixgbe_phy_sfp_intel:
3911 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3912 case ixgbe_phy_sfp_passive_tyco:
3913 case ixgbe_phy_sfp_passive_unknown:
3914 case ixgbe_phy_sfp_active_unknown:
3915 case ixgbe_phy_sfp_ftl_active:
e8e26350 3916 return true;
8917b447
AD		 3917 case ixgbe_phy_nl:
3918 if (hw->mac.type == ixgbe_mac_82598EB)
3919 return true;
e8e26350
PW		 3920 default:
3921 return false;
3922 }
3923}
3924
0ecc061d 3925/**
e8e26350
PW		 3926 * ixgbe_sfp_link_config - set up SFP+ link
3927 * @adapter: pointer to private adapter struct
3928 **/
3929static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3930{
7086400d 3931 /*
52f33af8 3932 * We are assuming the worst case scenario here, and that
7086400d
AD		 3933 * is that an SFP was inserted/removed after the reset
3934 * but before SFP detection was enabled. As such the best
3935 * solution is to just start searching as soon as we start
3936 */
3937 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3938 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3939
7086400d 3940 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3941}
3942
3943/**
3944 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3945 * @hw: pointer to private hardware struct
3946 *
3947 * Returns 0 on success, negative on failure
3948 **/
e8e26350 3949static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3950{
3951 u32 autoneg;
8620a103 3952 bool negotiation, link_up = false;
0ecc061d
PWJ		 3953 u32 ret = IXGBE_ERR_LINK_SETUP;
3954
3955 if (hw->mac.ops.check_link)
3956 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3957
3958 if (ret)
3959 goto link_cfg_out;
3960
0b0c2b31
ET		 3961 autoneg = hw->phy.autoneg_advertised;
3962 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3963 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3964 &negotiation);
0ecc061d
PWJ		 3965 if (ret)
3966 goto link_cfg_out;
3967
8620a103
MC		 3968 if (hw->mac.ops.setup_link)
3969 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3970link_cfg_out:
3971 return ret;
3972}
3973
a34bcfff 3974static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3975{
9a799d71 3976 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3977 u32 gpie = 0;
9a799d71 3978
9b471446 3979 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3980 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3981 IXGBE_GPIE_OCD;
3982 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3983 /*
3984 * use EIAM to auto-mask when MSI-X interrupt is asserted
3985 * this saves a register write for every interrupt
3986 */
3987 switch (hw->mac.type) {
3988 case ixgbe_mac_82598EB:
3989 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3990 break;
9b471446 3991 case ixgbe_mac_82599EB:
b93a2226
DS		 3992 case ixgbe_mac_X540:
3993 default:
9b471446
JB		 3994 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3995 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3996 break;
3997 }
3998 } else {
021230d4
AV		 3999 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4000 * specifically only auto mask tx and rx interrupts */
4001 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4002 }
9a799d71 4003
a34bcfff
AD		 4004 /* XXX: to interrupt immediately for EICS writes, enable this */
4005 /* gpie |= IXGBE_GPIE_EIMEN; */
4006
4007 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4008 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4009
4010 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4011 case IXGBE_82599_VMDQ_8Q_MASK:
4012 gpie |= IXGBE_GPIE_VTMODE_16;
4013 break;
4014 case IXGBE_82599_VMDQ_4Q_MASK:
4015 gpie |= IXGBE_GPIE_VTMODE_32;
4016 break;
4017 default:
4018 gpie |= IXGBE_GPIE_VTMODE_64;
4019 break;
4020 }
119fc60a
MC		 4021 }
4022
5fdd31f9 4023 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4024 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4025 switch (adapter->hw.mac.type) {
4026 case ixgbe_mac_82599EB:
4027 gpie |= IXGBE_SDP0_GPIEN;
4028 break;
4029 case ixgbe_mac_X540:
4030 gpie |= IXGBE_EIMS_TS;
4031 break;
4032 default:
4033 break;
4034 }
4035 }
5fdd31f9 4036
a34bcfff
AD		 4037 /* Enable fan failure interrupt */
4038 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4039 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4040
2698b208 4041 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4042 gpie |= IXGBE_SDP1_GPIEN;
4043 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4044 }
a34bcfff
AD		 4045
4046 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4047}
4048
c7ccde0f 4049static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4050{
4051 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4052 int err;
a34bcfff
AD		 4053 u32 ctrl_ext;
4054
4055 ixgbe_get_hw_control(adapter);
4056 ixgbe_setup_gpie(adapter);
e8e26350 4057
9a799d71
AK		 4058 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4059 ixgbe_configure_msix(adapter);
4060 else
4061 ixgbe_configure_msi_and_legacy(adapter);
4062
c6ecf39a
DS		 4063 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4064 if (hw->mac.ops.enable_tx_laser &&
4065 ((hw->phy.multispeed_fiber) ||
9f911707 4066 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 4067 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 4068 hw->mac.ops.enable_tx_laser(hw);
4069
9a799d71 4070 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4071 ixgbe_napi_enable_all(adapter);
4072
73c4b7cd
AD		 4073 if (ixgbe_is_sfp(hw)) {
4074 ixgbe_sfp_link_config(adapter);
4075 } else {
4076 err = ixgbe_non_sfp_link_config(hw);
4077 if (err)
4078 e_err(probe, "link_config FAILED %d\n", err);
4079 }
4080
021230d4
AV		 4081 /* clear any pending interrupts, may auto mask */
4082 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4083 ixgbe_irq_enable(adapter, true, true);
9a799d71 4084
bf069c97
DS		 4085 /*
4086 * If this adapter has a fan, check to see if we had a failure
4087 * before we enabled the interrupt.
4088 */
4089 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4090 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4091 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4092 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4093 }
4094
1da100bb 4095 /* enable transmits */
477de6ed 4096 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4097
9a799d71
AK		 4098 /* bring the link up in the watchdog, this could race with our first
4099 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4100 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4101 adapter->link_check_timeout = jiffies;
7086400d 4102 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4103
4104 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4105 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4106 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4107 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4108}
4109
d4f80882
AV		 4110void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4111{
4112 WARN_ON(in_interrupt());
7086400d
AD		 4113 /* put off any impending NetWatchDogTimeout */
4114 adapter->netdev->trans_start = jiffies;
4115
d4f80882 4116 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4117 usleep_range(1000, 2000);
d4f80882 4118 ixgbe_down(adapter);
5809a1ae
GR		 4119 /*
4120 * If SR-IOV enabled then wait a bit before bringing the adapter
4121 * back up to give the VFs time to respond to the reset. The
4122 * two second wait is based upon the watchdog timer cycle in
4123 * the VF driver.
4124 */
4125 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4126 msleep(2000);
d4f80882
AV		 4127 ixgbe_up(adapter);
4128 clear_bit(__IXGBE_RESETTING, &adapter->state);
4129}
4130
c7ccde0f 4131void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4132{
4133 /* hardware has been reset, we need to reload some things */
4134 ixgbe_configure(adapter);
4135
c7ccde0f 4136 ixgbe_up_complete(adapter);
9a799d71
AK		 4137}
4138
4139void ixgbe_reset(struct ixgbe_adapter *adapter)
4140{
c44ade9e 4141 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4142 int err;
4143
7086400d
AD		 4144 /* lock SFP init bit to prevent race conditions with the watchdog */
4145 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4146 usleep_range(1000, 2000);
4147
4148 /* clear all SFP and link config related flags while holding SFP_INIT */
4149 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4150 IXGBE_FLAG2_SFP_NEEDS_RESET);
4151 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4152
8ca783ab 4153 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4154 switch (err) {
4155 case 0:
4156 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4157 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4158 break;
4159 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4160 e_dev_err("master disable timed out\n");
da4dd0f7 4161 break;
794caeb2
PWJ		 4162 case IXGBE_ERR_EEPROM_VERSION:
4163 /* We are running on a pre-production device, log a warning */
849c4542 4164 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4165 "Please be aware there may be issues associated with "
849c4542
ET		 4166 "your hardware. If you are experiencing problems "
4167 "please contact your Intel or hardware "
4168 "representative who provided you with this "
4169 "hardware.\n");
794caeb2 4170 break;
da4dd0f7 4171 default:
849c4542 4172 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4173 }
9a799d71 4174
7086400d
AD		 4175 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4176
9a799d71 4177 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4178 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4179
4180 /* update SAN MAC vmdq pool selection */
4181 if (hw->mac.san_mac_rar_index)
4182 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
9a799d71
AK		 4183}
4184
9a799d71
AK		 4185/**
4186 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4187 * @rx_ring: ring to free buffers from
4188 **/
b6ec895e 4189static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4190{
b6ec895e 4191 struct device *dev = rx_ring->dev;
9a799d71 4192 unsigned long size;
b6ec895e 4193 u16 i;
9a799d71 4194
84418e3b
AD		 4195 /* ring already cleared, nothing to do */
4196 if (!rx_ring->rx_buffer_info)
4197 return;
9a799d71 4198
84418e3b 4199 /* Free all the Rx ring sk_buffs */
9a799d71 4200 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4201 struct ixgbe_rx_buffer *rx_buffer;
4202
4203 rx_buffer = &rx_ring->rx_buffer_info[i];
4204 if (rx_buffer->skb) {
4205 struct sk_buff *skb = rx_buffer->skb;
4206 if (IXGBE_CB(skb)->page_released) {
4207 dma_unmap_page(dev,
4208 IXGBE_CB(skb)->dma,
4209 ixgbe_rx_bufsz(rx_ring),
4210 DMA_FROM_DEVICE);
4211 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4212 }
4213 dev_kfree_skb(skb);
9a799d71 4214 }
f800326d
AD		 4215 rx_buffer->skb = NULL;
4216 if (rx_buffer->dma)
4217 dma_unmap_page(dev, rx_buffer->dma,
4218 ixgbe_rx_pg_size(rx_ring),
4219 DMA_FROM_DEVICE);
4220 rx_buffer->dma = 0;
4221 if (rx_buffer->page)
dd411ec4
AD		 4222 __free_pages(rx_buffer->page,
4223 ixgbe_rx_pg_order(rx_ring));
f800326d 4224 rx_buffer->page = NULL;
9a799d71
AK		 4225 }
4226
4227 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4228 memset(rx_ring->rx_buffer_info, 0, size);
4229
4230 /* Zero out the descriptor ring */
4231 memset(rx_ring->desc, 0, rx_ring->size);
4232
f800326d 4233 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4234 rx_ring->next_to_clean = 0;
4235 rx_ring->next_to_use = 0;
9a799d71
AK		 4236}
4237
4238/**
4239 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4240 * @tx_ring: ring to be cleaned
4241 **/
b6ec895e 4242static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4243{
4244 struct ixgbe_tx_buffer *tx_buffer_info;
4245 unsigned long size;
b6ec895e 4246 u16 i;
9a799d71 4247
84418e3b
AD		 4248 /* ring already cleared, nothing to do */
4249 if (!tx_ring->tx_buffer_info)
4250 return;
9a799d71 4251
84418e3b 4252 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4253 for (i = 0; i < tx_ring->count; i++) {
4254 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4255 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4256 }
4257
dad8a3b3
JF		 4258 netdev_tx_reset_queue(txring_txq(tx_ring));
4259
9a799d71
AK		 4260 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4261 memset(tx_ring->tx_buffer_info, 0, size);
4262
4263 /* Zero out the descriptor ring */
4264 memset(tx_ring->desc, 0, tx_ring->size);
4265
4266 tx_ring->next_to_use = 0;
4267 tx_ring->next_to_clean = 0;
9a799d71
AK		 4268}
4269
4270/**
021230d4 4271 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4272 * @adapter: board private structure
4273 **/
021230d4 4274static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4275{
4276 int i;
4277
021230d4 4278 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4279 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4280}
4281
4282/**
021230d4 4283 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4284 * @adapter: board private structure
4285 **/
021230d4 4286static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4287{
4288 int i;
4289
021230d4 4290 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4291 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4292}
4293
e4911d57
AD		 4294static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4295{
4296 struct hlist_node *node, *node2;
4297 struct ixgbe_fdir_filter *filter;
4298
4299 spin_lock(&adapter->fdir_perfect_lock);
4300
4301 hlist_for_each_entry_safe(filter, node, node2,
4302 &adapter->fdir_filter_list, fdir_node) {
4303 hlist_del(&filter->fdir_node);
4304 kfree(filter);
4305 }
4306 adapter->fdir_filter_count = 0;
4307
4308 spin_unlock(&adapter->fdir_perfect_lock);
4309}
4310
9a799d71
AK		 4311void ixgbe_down(struct ixgbe_adapter *adapter)
4312{
4313 struct net_device *netdev = adapter->netdev;
7f821875 4314 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4315 u32 rxctrl;
bf29ee6c 4316 int i;
9a799d71
AK		 4317
4318 /* signal that we are down to the interrupt handler */
4319 set_bit(__IXGBE_DOWN, &adapter->state);
4320
4321 /* disable receives */
7f821875
JB		 4322 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4323 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4324
2d39d576
YZ		 4325 /* disable all enabled rx queues */
4326 for (i = 0; i < adapter->num_rx_queues; i++)
4327 /* this call also flushes the previous write */
4328 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4329
032b4325 4330 usleep_range(10000, 20000);
9a799d71 4331
7f821875
JB		 4332 netif_tx_stop_all_queues(netdev);
4333
7086400d 4334 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4335 netif_carrier_off(netdev);
4336 netif_tx_disable(netdev);
4337
4338 ixgbe_irq_disable(adapter);
4339
4340 ixgbe_napi_disable_all(adapter);
4341
d034acf1
AD		 4342 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4343 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4344 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4345
4346 del_timer_sync(&adapter->service_timer);
4347
34cecbbf 4348 if (adapter->num_vfs) {
8e34d1aa
AD		 4349 /* Clear EITR Select mapping */
4350 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4351
4352 /* Mark all the VFs as inactive */
4353 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4354 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4355
34cecbbf
AD		 4356 /* ping all the active vfs to let them know we are going down */
4357 ixgbe_ping_all_vfs(adapter);
4358
4359 /* Disable all VFTE/VFRE TX/RX */
4360 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4361 }
4362
7f821875
JB		 4363 /* disable transmits in the hardware now that interrupts are off */
4364 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4365 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4366 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4367 }
34cecbbf
AD		 4368
4369 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4370 switch (hw->mac.type) {
4371 case ixgbe_mac_82599EB:
b93a2226 4372 case ixgbe_mac_X540:
88512539 4373 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4374 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4375 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4376 break;
4377 default:
4378 break;
4379 }
7f821875 4380
6f4a0e45
PL		 4381 if (!pci_channel_offline(adapter->pdev))
4382 ixgbe_reset(adapter);
c6ecf39a
DS		 4383
4384 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4385 if (hw->mac.ops.disable_tx_laser &&
4386 ((hw->phy.multispeed_fiber) ||
9f911707 4387 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4388 (hw->mac.type == ixgbe_mac_82599EB))))
4389 hw->mac.ops.disable_tx_laser(hw);
4390
9a799d71
AK		 4391 ixgbe_clean_all_tx_rings(adapter);
4392 ixgbe_clean_all_rx_rings(adapter);
4393
5dd2d332 4394#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4395 /* since we reset the hardware DCA settings were cleared */
e35ec126 4396 ixgbe_setup_dca(adapter);
96b0e0f6 4397#endif
9a799d71
AK		 4398}
4399
9a799d71
AK		 4400/**
4401 * ixgbe_tx_timeout - Respond to a Tx Hang
4402 * @netdev: network interface device structure
4403 **/
4404static void ixgbe_tx_timeout(struct net_device *netdev)
4405{
4406 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4407
4408 /* Do the reset outside of interrupt context */
c83c6cbd 4409 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4410}
4411
9a799d71
AK		 4412/**
4413 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4414 * @adapter: board private structure to initialize
4415 *
4416 * ixgbe_sw_init initializes the Adapter private data structure.
4417 * Fields are initialized based on PCI device information and
4418 * OS network device settings (MTU size).
4419 **/
4420static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4421{
4422 struct ixgbe_hw *hw = &adapter->hw;
4423 struct pci_dev *pdev = adapter->pdev;
021230d4 4424 unsigned int rss;
7a6b6f51 4425#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4426 int j;
4427 struct tc_configuration *tc;
4428#endif
021230d4 4429
c44ade9e
JB		 4430 /* PCI config space info */
4431
4432 hw->vendor_id = pdev->vendor;
4433 hw->device_id = pdev->device;
4434 hw->revision_id = pdev->revision;
4435 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4436 hw->subsystem_device_id = pdev->subsystem_device;
4437
021230d4 4438 /* Set capability flags */
3ed69d7e 4439 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4440 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4441 switch (hw->mac.type) {
4442 case ixgbe_mac_82598EB:
bf069c97
DS		 4443 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4444 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4445 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4446 break;
b93a2226 4447 case ixgbe_mac_X540:
4f51bf70
JK		 4448 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4449 case ixgbe_mac_82599EB:
49c7ffbe 4450 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4451 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4452 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4453 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4454 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4455 /* Flow Director hash filters enabled */
45b9f509 4456 adapter->atr_sample_rate = 20;
c087663e 4457 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4458 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4459 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4460#ifdef IXGBE_FCOE
0d551589
YZ		 4461 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4462 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4463#ifdef CONFIG_IXGBE_DCB
6ee16520 4464 /* Default traffic class to use for FCoE */
56075a98 4465 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4466#endif
eacd73f7 4467#endif /* IXGBE_FCOE */
bd508178
AD		 4468 break;
4469 default:
4470 break;
f8212f97 4471 }
2f90b865 4472
7c8ae65a
AD		 4473#ifdef IXGBE_FCOE
4474 /* FCoE support exists, always init the FCoE lock */
4475 spin_lock_init(&adapter->fcoe.lock);
4476
4477#endif
1fc5f038
AD		 4478 /* n-tuple support exists, always init our spinlock */
4479 spin_lock_init(&adapter->fdir_perfect_lock);
4480
7a6b6f51 4481#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4482 switch (hw->mac.type) {
4483 case ixgbe_mac_X540:
4484 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4485 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4486 break;
4487 default:
4488 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4489 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4490 break;
4491 }
4492
2f90b865
AD		 4493 /* Configure DCB traffic classes */
4494 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4495 tc = &adapter->dcb_cfg.tc_config[j];
4496 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4497 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4498 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4499 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4500 tc->dcb_pfc = pfc_disabled;
4501 }
4de2a022
JF		 4502
4503 /* Initialize default user to priority mapping, UPx->TC0 */
4504 tc = &adapter->dcb_cfg.tc_config[0];
4505 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4506 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4507
2f90b865
AD		 4508 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4509 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4510 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4511 adapter->dcb_set_bitmap = 0x00;
3032309b 4512 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4513 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4514 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4515
4516#endif
9a799d71
AK		 4517
4518 /* default flow control settings */
cd7664f6 4519 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4520 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4521 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4522 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4523 hw->fc.send_xon = true;
71fd570b 4524 hw->fc.disable_fc_autoneg = false;
9a799d71 4525
99d74487
AD		 4526#ifdef CONFIG_PCI_IOV
4527 /* assign number of SR-IOV VFs */
4528 if (hw->mac.type != ixgbe_mac_82598EB)
4529 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4530
4531#endif
30efa5a3 4532 /* enable itr by default in dynamic mode */
f7554a2b 4533 adapter->rx_itr_setting = 1;
f7554a2b 4534 adapter->tx_itr_setting = 1;
30efa5a3 4535
30efa5a3
JB		 4536 /* set default ring sizes */
4537 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4538 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4539
bd198058 4540 /* set default work limits */
59224555 4541 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4542
9a799d71 4543 /* initialize eeprom parameters */
c44ade9e 4544 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4545 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4546 return -EIO;
4547 }
4548
9a799d71
AK		 4549 set_bit(__IXGBE_DOWN, &adapter->state);
4550
4551 return 0;
4552}
4553
4554/**
4555 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4556 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4557 *
4558 * Return 0 on success, negative on failure
4559 **/
b6ec895e 4560int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4561{
b6ec895e 4562 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4563 int orig_node = dev_to_node(dev);
4564 int numa_node = -1;
9a799d71
AK		 4565 int size;
4566
3a581073 4567 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4568
4569 if (tx_ring->q_vector)
4570 numa_node = tx_ring->q_vector->numa_node;
4571
4572 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4573 if (!tx_ring->tx_buffer_info)
89bf67f1 4574 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4575 if (!tx_ring->tx_buffer_info)
4576 goto err;
9a799d71
AK		 4577
4578 /* round up to nearest 4K */
12207e49 4579 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4580 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4581
de88eeeb
AD		 4582 set_dev_node(dev, numa_node);
4583 tx_ring->desc = dma_alloc_coherent(dev,
4584 tx_ring->size,
4585 &tx_ring->dma,
4586 GFP_KERNEL);
4587 set_dev_node(dev, orig_node);
4588 if (!tx_ring->desc)
4589 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4590 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4591 if (!tx_ring->desc)
4592 goto err;
9a799d71 4593
3a581073
JB		 4594 tx_ring->next_to_use = 0;
4595 tx_ring->next_to_clean = 0;
9a799d71 4596 return 0;
e01c31a5
JB		 4597
4598err:
4599 vfree(tx_ring->tx_buffer_info);
4600 tx_ring->tx_buffer_info = NULL;
b6ec895e 4601 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4602 return -ENOMEM;
9a799d71
AK		 4603}
4604
69888674
AD		 4605/**
4606 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4607 * @adapter: board private structure
4608 *
4609 * If this function returns with an error, then it's possible one or
4610 * more of the rings is populated (while the rest are not). It is the
4611 * callers duty to clean those orphaned rings.
4612 *
4613 * Return 0 on success, negative on failure
4614 **/
4615static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4616{
4617 int i, err = 0;
4618
4619 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4620 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4621 if (!err)
4622 continue;
de3d5b94 4623
396e799c 4624 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4625 goto err_setup_tx;
69888674
AD		 4626 }
4627
de3d5b94
AD		 4628 return 0;
4629err_setup_tx:
4630 /* rewind the index freeing the rings as we go */
4631 while (i--)
4632 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4633 return err;
4634}
4635
9a799d71
AK		 4636/**
4637 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4638 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4639 *
4640 * Returns 0 on success, negative on failure
4641 **/
b6ec895e 4642int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4643{
b6ec895e 4644 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4645 int orig_node = dev_to_node(dev);
4646 int numa_node = -1;
021230d4 4647 int size;
9a799d71 4648
3a581073 4649 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4650
4651 if (rx_ring->q_vector)
4652 numa_node = rx_ring->q_vector->numa_node;
4653
4654 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4655 if (!rx_ring->rx_buffer_info)
89bf67f1 4656 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4657 if (!rx_ring->rx_buffer_info)
4658 goto err;
9a799d71 4659
9a799d71 4660 /* Round up to nearest 4K */
3a581073
JB		 4661 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4662 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4663
de88eeeb
AD		 4664 set_dev_node(dev, numa_node);
4665 rx_ring->desc = dma_alloc_coherent(dev,
4666 rx_ring->size,
4667 &rx_ring->dma,
4668 GFP_KERNEL);
4669 set_dev_node(dev, orig_node);
4670 if (!rx_ring->desc)
4671 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4672 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4673 if (!rx_ring->desc)
4674 goto err;
9a799d71 4675
3a581073
JB		 4676 rx_ring->next_to_clean = 0;
4677 rx_ring->next_to_use = 0;
9a799d71
AK		 4678
4679 return 0;
b6ec895e
AD		 4680err:
4681 vfree(rx_ring->rx_buffer_info);
4682 rx_ring->rx_buffer_info = NULL;
4683 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4684 return -ENOMEM;
9a799d71
AK		 4685}
4686
69888674
AD		 4687/**
4688 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4689 * @adapter: board private structure
4690 *
4691 * If this function returns with an error, then it's possible one or
4692 * more of the rings is populated (while the rest are not). It is the
4693 * callers duty to clean those orphaned rings.
4694 *
4695 * Return 0 on success, negative on failure
4696 **/
69888674
AD		 4697static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4698{
4699 int i, err = 0;
4700
4701 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4702 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4703 if (!err)
4704 continue;
de3d5b94 4705
396e799c 4706 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4707 goto err_setup_rx;
69888674
AD		 4708 }
4709
7c8ae65a
AD		 4710#ifdef IXGBE_FCOE
4711 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4712 if (!err)
4713#endif
4714 return 0;
de3d5b94
AD		 4715err_setup_rx:
4716 /* rewind the index freeing the rings as we go */
4717 while (i--)
4718 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4719 return err;
4720}
4721
9a799d71
AK		 4722/**
4723 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4724 * @tx_ring: Tx descriptor ring for a specific queue
4725 *
4726 * Free all transmit software resources
4727 **/
b6ec895e 4728void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4729{
b6ec895e 4730 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4731
4732 vfree(tx_ring->tx_buffer_info);
4733 tx_ring->tx_buffer_info = NULL;
4734
b6ec895e
AD		 4735 /* if not set, then don't free */
4736 if (!tx_ring->desc)
4737 return;
4738
4739 dma_free_coherent(tx_ring->dev, tx_ring->size,
4740 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4741
4742 tx_ring->desc = NULL;
4743}
4744
4745/**
4746 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4747 * @adapter: board private structure
4748 *
4749 * Free all transmit software resources
4750 **/
4751static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4752{
4753 int i;
4754
4755 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4756 if (adapter->tx_ring[i]->desc)
b6ec895e 4757 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4758}
4759
4760/**
b4617240 4761 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4762 * @rx_ring: ring to clean the resources from
4763 *
4764 * Free all receive software resources
4765 **/
b6ec895e 4766void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4767{
b6ec895e 4768 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4769
4770 vfree(rx_ring->rx_buffer_info);
4771 rx_ring->rx_buffer_info = NULL;
4772
b6ec895e
AD		 4773 /* if not set, then don't free */
4774 if (!rx_ring->desc)
4775 return;
4776
4777 dma_free_coherent(rx_ring->dev, rx_ring->size,
4778 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4779
4780 rx_ring->desc = NULL;
4781}
4782
4783/**
4784 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4785 * @adapter: board private structure
4786 *
4787 * Free all receive software resources
4788 **/
4789static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4790{
4791 int i;
4792
7c8ae65a
AD		 4793#ifdef IXGBE_FCOE
4794 ixgbe_free_fcoe_ddp_resources(adapter);
4795
4796#endif
9a799d71 4797 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4798 if (adapter->rx_ring[i]->desc)
b6ec895e 4799 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4800}
4801
9a799d71
AK		 4802/**
4803 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4804 * @netdev: network interface device structure
4805 * @new_mtu: new value for maximum frame size
4806 *
4807 * Returns 0 on success, negative on failure
4808 **/
4809static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4810{
4811 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4812 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4813
42c783c5 4814 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4815 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4816 return -EINVAL;
4817
4818 /*
4819 * For 82599EB we cannot allow PF to change MTU greater than 1500
4820 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4821 * don't allocate and chain buffers correctly.
4822 */
4823 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4824 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4825 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 4826 return -EINVAL;
9a799d71 4827
396e799c 4828 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4829
021230d4 4830 /* must set new MTU before calling down or up */
9a799d71
AK		 4831 netdev->mtu = new_mtu;
4832
d4f80882
AV		 4833 if (netif_running(netdev))
4834 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4835
4836 return 0;
4837}
4838
4839/**
4840 * ixgbe_open - Called when a network interface is made active
4841 * @netdev: network interface device structure
4842 *
4843 * Returns 0 on success, negative value on failure
4844 *
4845 * The open entry point is called when a network interface is made
4846 * active by the system (IFF_UP). At this point all resources needed
4847 * for transmit and receive operations are allocated, the interrupt
4848 * handler is registered with the OS, the watchdog timer is started,
4849 * and the stack is notified that the interface is ready.
4850 **/
4851static int ixgbe_open(struct net_device *netdev)
4852{
4853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4854 int err;
4bebfaa5
AK		 4855
4856 /* disallow open during test */
4857 if (test_bit(__IXGBE_TESTING, &adapter->state))
4858 return -EBUSY;
9a799d71 4859
54386467
JB		 4860 netif_carrier_off(netdev);
4861
9a799d71
AK		 4862 /* allocate transmit descriptors */
4863 err = ixgbe_setup_all_tx_resources(adapter);
4864 if (err)
4865 goto err_setup_tx;
4866
9a799d71
AK		 4867 /* allocate receive descriptors */
4868 err = ixgbe_setup_all_rx_resources(adapter);
4869 if (err)
4870 goto err_setup_rx;
4871
4872 ixgbe_configure(adapter);
4873
021230d4 4874 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4875 if (err)
4876 goto err_req_irq;
4877
ac802f5d
AD		 4878 /* Notify the stack of the actual queue counts. */
4879 err = netif_set_real_num_tx_queues(netdev,
4880 adapter->num_rx_pools > 1 ? 1 :
4881 adapter->num_tx_queues);
4882 if (err)
4883 goto err_set_queues;
4884
4885
4886 err = netif_set_real_num_rx_queues(netdev,
4887 adapter->num_rx_pools > 1 ? 1 :
4888 adapter->num_rx_queues);
4889 if (err)
4890 goto err_set_queues;
4891
c7ccde0f 4892 ixgbe_up_complete(adapter);
9a799d71
AK		 4893
4894 return 0;
4895
ac802f5d
AD		 4896err_set_queues:
4897 ixgbe_free_irq(adapter);
9a799d71 4898err_req_irq:
a20a1199 4899 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4900err_setup_rx:
a20a1199 4901 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4902err_setup_tx:
9a799d71
AK		 4903 ixgbe_reset(adapter);
4904
4905 return err;
4906}
4907
4908/**
4909 * ixgbe_close - Disables a network interface
4910 * @netdev: network interface device structure
4911 *
4912 * Returns 0, this is not allowed to fail
4913 *
4914 * The close entry point is called when an interface is de-activated
4915 * by the OS. The hardware is still under the drivers control, but
4916 * needs to be disabled. A global MAC reset is issued to stop the
4917 * hardware, and all transmit and receive resources are freed.
4918 **/
4919static int ixgbe_close(struct net_device *netdev)
4920{
4921 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4922
4923 ixgbe_down(adapter);
4924 ixgbe_free_irq(adapter);
4925
e4911d57
AD		 4926 ixgbe_fdir_filter_exit(adapter);
4927
9a799d71
AK		 4928 ixgbe_free_all_tx_resources(adapter);
4929 ixgbe_free_all_rx_resources(adapter);
4930
5eba3699 4931 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4932
4933 return 0;
4934}
4935
b3c8b4ba
AD		 4936#ifdef CONFIG_PM
4937static int ixgbe_resume(struct pci_dev *pdev)
4938{
c60fbb00
AD		 4939 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4940 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4941 u32 err;
4942
4943 pci_set_power_state(pdev, PCI_D0);
4944 pci_restore_state(pdev);
656ab817
DS		 4945 /*
4946 * pci_restore_state clears dev->state_saved so call
4947 * pci_save_state to restore it.
4948 */
4949 pci_save_state(pdev);
9ce77666 4950
4951 err = pci_enable_device_mem(pdev);
b3c8b4ba 4952 if (err) {
849c4542 4953 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4954 return err;
4955 }
4956 pci_set_master(pdev);
4957
dd4d8ca6 4958 pci_wake_from_d3(pdev, false);
b3c8b4ba 4959
b3c8b4ba
AD		 4960 ixgbe_reset(adapter);
4961
495dce12
WJP		 4962 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4963
ac802f5d
AD		 4964 rtnl_lock();
4965 err = ixgbe_init_interrupt_scheme(adapter);
4966 if (!err && netif_running(netdev))
c60fbb00 4967 err = ixgbe_open(netdev);
ac802f5d
AD		 4968
4969 rtnl_unlock();
4970
4971 if (err)
4972 return err;
b3c8b4ba
AD		 4973
4974 netif_device_attach(netdev);
4975
4976 return 0;
4977}
b3c8b4ba 4978#endif /* CONFIG_PM */
9d8d05ae
RW		 4979
4980static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 4981{
c60fbb00
AD		 4982 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4983 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 4984 struct ixgbe_hw *hw = &adapter->hw;
4985 u32 ctrl, fctrl;
4986 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4987#ifdef CONFIG_PM
4988 int retval = 0;
4989#endif
4990
4991 netif_device_detach(netdev);
4992
4993 if (netif_running(netdev)) {
ab6039a7 4994 rtnl_lock();
b3c8b4ba
AD		 4995 ixgbe_down(adapter);
4996 ixgbe_free_irq(adapter);
4997 ixgbe_free_all_tx_resources(adapter);
4998 ixgbe_free_all_rx_resources(adapter);
ab6039a7 4999 rtnl_unlock();
b3c8b4ba 5000 }
b3c8b4ba 5001
5f5ae6fc
AD		 5002 ixgbe_clear_interrupt_scheme(adapter);
5003
b3c8b4ba
AD		 5004#ifdef CONFIG_PM
5005 retval = pci_save_state(pdev);
5006 if (retval)
5007 return retval;
4df10466 5008
b3c8b4ba 5009#endif
e8e26350
PW		 5010 if (wufc) {
5011 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5012
c509e754
DS		 5013 /*
5014 * enable the optics for both mult-speed fiber and
5015 * 82599 SFP+ fiber as we can WoL.
5016 */
5017 if (hw->mac.ops.enable_tx_laser &&
5018 (hw->phy.multispeed_fiber ||
5019 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
5020 hw->mac.type == ixgbe_mac_82599EB)))
5021 hw->mac.ops.enable_tx_laser(hw);
5022
e8e26350
PW		 5023 /* turn on all-multi mode if wake on multicast is enabled */
5024 if (wufc & IXGBE_WUFC_MC) {
5025 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5026 fctrl |= IXGBE_FCTRL_MPE;
5027 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5028 }
5029
5030 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5031 ctrl |= IXGBE_CTRL_GIO_DIS;
5032 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5033
5034 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5035 } else {
5036 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5037 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5038 }
5039
bd508178
AD		 5040 switch (hw->mac.type) {
5041 case ixgbe_mac_82598EB:
dd4d8ca6 5042 pci_wake_from_d3(pdev, false);
bd508178
AD		 5043 break;
5044 case ixgbe_mac_82599EB:
b93a2226 5045 case ixgbe_mac_X540:
bd508178
AD		 5046 pci_wake_from_d3(pdev, !!wufc);
5047 break;
5048 default:
5049 break;
5050 }
b3c8b4ba 5051
9d8d05ae
RW		 5052 *enable_wake = !!wufc;
5053
b3c8b4ba
AD		 5054 ixgbe_release_hw_control(adapter);
5055
5056 pci_disable_device(pdev);
5057
9d8d05ae
RW		 5058 return 0;
5059}
5060
5061#ifdef CONFIG_PM
5062static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5063{
5064 int retval;
5065 bool wake;
5066
5067 retval = __ixgbe_shutdown(pdev, &wake);
5068 if (retval)
5069 return retval;
5070
5071 if (wake) {
5072 pci_prepare_to_sleep(pdev);
5073 } else {
5074 pci_wake_from_d3(pdev, false);
5075 pci_set_power_state(pdev, PCI_D3hot);
5076 }
b3c8b4ba
AD		 5077
5078 return 0;
5079}
9d8d05ae 5080#endif /* CONFIG_PM */
b3c8b4ba
AD		 5081
5082static void ixgbe_shutdown(struct pci_dev *pdev)
5083{
9d8d05ae
RW		 5084 bool wake;
5085
5086 __ixgbe_shutdown(pdev, &wake);
5087
5088 if (system_state == SYSTEM_POWER_OFF) {
5089 pci_wake_from_d3(pdev, wake);
5090 pci_set_power_state(pdev, PCI_D3hot);
5091 }
b3c8b4ba
AD		 5092}
5093
9a799d71
AK		 5094/**
5095 * ixgbe_update_stats - Update the board statistics counters.
5096 * @adapter: board private structure
5097 **/
5098void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5099{
2d86f139 5100 struct net_device *netdev = adapter->netdev;
9a799d71 5101 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5102 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5103 u64 total_mpc = 0;
5104 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5105 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5106 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5107 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5108
d08935c2
DS		 5109 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5110 test_bit(__IXGBE_RESETTING, &adapter->state))
5111 return;
5112
94b982b2 5113 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5114 u64 rsc_count = 0;
94b982b2 5115 u64 rsc_flush = 0;
94b982b2 5116 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5117 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5118 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5119 }
5120 adapter->rsc_total_count = rsc_count;
5121 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5122 }
5123
5b7da515
AD		 5124 for (i = 0; i < adapter->num_rx_queues; i++) {
5125 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5126 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5127 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5128 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5129 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5130 bytes += rx_ring->stats.bytes;
5131 packets += rx_ring->stats.packets;
5132 }
5133 adapter->non_eop_descs = non_eop_descs;
5134 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5135 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5136 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5137 netdev->stats.rx_bytes = bytes;
5138 netdev->stats.rx_packets = packets;
5139
5140 bytes = 0;
5141 packets = 0;
7ca3bc58 5142 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5143 for (i = 0; i < adapter->num_tx_queues; i++) {
5144 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5145 restart_queue += tx_ring->tx_stats.restart_queue;
5146 tx_busy += tx_ring->tx_stats.tx_busy;
5147 bytes += tx_ring->stats.bytes;
5148 packets += tx_ring->stats.packets;
5149 }
eb985f09 5150 adapter->restart_queue = restart_queue;
5b7da515
AD		 5151 adapter->tx_busy = tx_busy;
5152 netdev->stats.tx_bytes = bytes;
5153 netdev->stats.tx_packets = packets;
7ca3bc58 5154
7ca647bd 5155 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5156
5157 /* 8 register reads */
6f11eef7
AV		 5158 for (i = 0; i < 8; i++) {
5159 /* for packet buffers not used, the register should read 0 */
5160 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5161 missed_rx += mpc;
7ca647bd
JP		 5162 hwstats->mpc[i] += mpc;
5163 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5164 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5165 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5166 switch (hw->mac.type) {
5167 case ixgbe_mac_82598EB:
1a70db4b
ET		 5168 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5169 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5170 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5171 hwstats->pxonrxc[i] +=
5172 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5173 break;
5174 case ixgbe_mac_82599EB:
b93a2226 5175 case ixgbe_mac_X540:
bd508178
AD		 5176 hwstats->pxonrxc[i] +=
5177 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5178 break;
5179 default:
5180 break;
e8e26350 5181 }
6f11eef7 5182 }
1a70db4b
ET		 5183
5184 /*16 register reads */
5185 for (i = 0; i < 16; i++) {
5186 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5187 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5188 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5189 (hw->mac.type == ixgbe_mac_X540)) {
5190 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5191 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5192 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5193 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5194 }
5195 }
5196
7ca647bd 5197 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5198 /* work around hardware counting issue */
7ca647bd 5199 hwstats->gprc -= missed_rx;
6f11eef7 5200
c84d324c
JF		 5201 ixgbe_update_xoff_received(adapter);
5202
6f11eef7 5203 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5204 switch (hw->mac.type) {
5205 case ixgbe_mac_82598EB:
5206 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5207 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5208 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5209 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5210 break;
b93a2226 5211 case ixgbe_mac_X540:
58f6bcf9
ET		 5212 /* OS2BMC stats are X540 only*/
5213 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5214 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5215 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5216 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5217 case ixgbe_mac_82599EB:
a4d4f629
AD		 5218 for (i = 0; i < 16; i++)
5219 adapter->hw_rx_no_dma_resources +=
5220 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5221 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5222 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5223 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5224 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5225 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5226 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5227 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5228 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5229 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5230#ifdef IXGBE_FCOE
7ca647bd
JP		 5231 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5232 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5233 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5234 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5235 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5236 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5237 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5238 if (adapter->fcoe.ddp_pool) {
5239 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5240 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5241 unsigned int cpu;
5242 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5243 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5244 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5245 noddp += ddp_pool->noddp;
5246 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5247 }
5a1ee270
AD		 5248 hwstats->fcoe_noddp = noddp;
5249 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5250 }
6d45522c 5251#endif /* IXGBE_FCOE */
bd508178
AD		 5252 break;
5253 default:
5254 break;
e8e26350 5255 }
9a799d71 5256 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5257 hwstats->bprc += bprc;
5258 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5259 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5260 hwstats->mprc -= bprc;
5261 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5262 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5263 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5264 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5265 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5266 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5267 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5268 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5269 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5270 hwstats->lxontxc += lxon;
6f11eef7 5271 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5272 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5273 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5274 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5275 /*
5276 * 82598 errata - tx of flow control packets is included in tx counters
5277 */
5278 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5279 hwstats->gptc -= xon_off_tot;
5280 hwstats->mptc -= xon_off_tot;
5281 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5282 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5283 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5284 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5285 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5286 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5287 hwstats->ptc64 -= xon_off_tot;
5288 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5289 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5290 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5291 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5292 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5293 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5294
5295 /* Fill out the OS statistics structure */
7ca647bd 5296 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5297
5298 /* Rx Errors */
7ca647bd 5299 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5300 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5301 netdev->stats.rx_length_errors = hwstats->rlec;
5302 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5303 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5304}
5305
5306/**
d034acf1 5307 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5308 * @adapter: pointer to the device adapter structure
9a799d71 5309 **/
d034acf1 5310static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5311{
cf8280ee 5312 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5313 int i;
cf8280ee 5314
d034acf1
AD		 5315 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5316 return;
5317
5318 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5319
d034acf1 5320 /* if interface is down do nothing */
fe49f04a 5321 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5322 return;
5323
5324 /* do nothing if we are not using signature filters */
5325 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5326 return;
5327
5328 adapter->fdir_overflow++;
5329
93c52dd0
AD		 5330 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5331 for (i = 0; i < adapter->num_tx_queues; i++)
5332 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5333 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5334 /* re-enable flow director interrupts */
5335 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5336 } else {
5337 e_err(probe, "failed to finish FDIR re-initialization, "
5338 "ignored adding FDIR ATR filters\n");
5339 }
93c52dd0
AD		 5340}
5341
5342/**
5343 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5344 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5345 *
5346 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5347 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5348 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5349 * determine if a hang has occurred.
93c52dd0
AD		 5350 */
5351static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5352{
cf8280ee 5353 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5354 u64 eics = 0;
5355 int i;
cf8280ee 5356
93c52dd0
AD		 5357 /* If we're down or resetting, just bail */
5358 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5359 test_bit(__IXGBE_RESETTING, &adapter->state))
5360 return;
22d5a71b 5361
93c52dd0
AD		 5362 /* Force detection of hung controller */
5363 if (netif_carrier_ok(adapter->netdev)) {
5364 for (i = 0; i < adapter->num_tx_queues; i++)
5365 set_check_for_tx_hang(adapter->tx_ring[i]);
5366 }
22d5a71b 5367
fe49f04a
AD		 5368 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5369 /*
5370 * for legacy and MSI interrupts don't set any bits
5371 * that are enabled for EIAM, because this operation
5372 * would set *both* EIMS and EICS for any bit in EIAM
5373 */
5374 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5375 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5376 } else {
5377 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5378 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5379 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5380 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5381 eics |= ((u64)1 << i);
5382 }
cf8280ee 5383 }
9a799d71 5384
93c52dd0 5385 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5386 ixgbe_irq_rearm_queues(adapter, eics);
5387
cf8280ee
JB		 5388}
5389
e8e26350 5390/**
93c52dd0 5391 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5392 * @adapter: pointer to the device adapter structure
5393 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5394 **/
93c52dd0 5395static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5396{
e8e26350 5397 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5398 u32 link_speed = adapter->link_speed;
5399 bool link_up = adapter->link_up;
041441d0 5400 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5401
93c52dd0
AD		 5402 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5403 return;
5404
5405 if (hw->mac.ops.check_link) {
5406 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5407 } else {
93c52dd0
AD		 5408 /* always assume link is up, if no check link function */
5409 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5410 link_up = true;
c4cf55e5 5411 }
041441d0
AD		 5412
5413 if (adapter->ixgbe_ieee_pfc)
5414 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5415
3ebe8fde 5416 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5417 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5418 ixgbe_set_rx_drop_en(adapter);
5419 }
93c52dd0
AD		 5420
5421 if (link_up ||
5422 time_after(jiffies, (adapter->link_check_timeout +
5423 IXGBE_TRY_LINK_TIMEOUT))) {
5424 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5425 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5426 IXGBE_WRITE_FLUSH(hw);
5427 }
5428
5429 adapter->link_up = link_up;
5430 adapter->link_speed = link_speed;
e8e26350
PW		 5431}
5432
5433/**
93c52dd0
AD		 5434 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5435 * print link up message
49ce9c2c 5436 * @adapter: pointer to the device adapter structure
e8e26350 5437 **/
93c52dd0 5438static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5439{
93c52dd0 5440 struct net_device *netdev = adapter->netdev;
e8e26350 5441 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5442 u32 link_speed = adapter->link_speed;
5443 bool flow_rx, flow_tx;
e8e26350 5444
93c52dd0
AD		 5445 /* only continue if link was previously down */
5446 if (netif_carrier_ok(netdev))
a985b6c3 5447 return;
63d6e1d8 5448
93c52dd0 5449 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5450
93c52dd0
AD		 5451 switch (hw->mac.type) {
5452 case ixgbe_mac_82598EB: {
5453 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5454 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5455 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5456 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5457 }
5458 break;
5459 case ixgbe_mac_X540:
5460 case ixgbe_mac_82599EB: {
5461 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5462 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5463 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5464 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5465 }
5466 break;
5467 default:
5468 flow_tx = false;
5469 flow_rx = false;
5470 break;
e8e26350 5471 }
3a6a4eda
JK		 5472
5473#ifdef CONFIG_IXGBE_PTP
5474 ixgbe_ptp_start_cyclecounter(adapter);
5475#endif
5476
93c52dd0
AD		 5477 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5478 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5479 "10 Gbps" :
5480 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5481 "1 Gbps" :
5482 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5483 "100 Mbps" :
5484 "unknown speed"))),
5485 ((flow_rx && flow_tx) ? "RX/TX" :
5486 (flow_rx ? "RX" :
5487 (flow_tx ? "TX" : "None"))));
e8e26350 5488
93c52dd0 5489 netif_carrier_on(netdev);
93c52dd0 5490 ixgbe_check_vf_rate_limit(adapter);
befa2af7
AD		 5491
5492 /* ping all the active vfs to let them know link has changed */
5493 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5494}
5495
c4cf55e5 5496/**
93c52dd0
AD		 5497 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5498 * print link down message
49ce9c2c 5499 * @adapter: pointer to the adapter structure
c4cf55e5 5500 **/
581330ba 5501static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5502{
cf8280ee 5503 struct net_device *netdev = adapter->netdev;
c4cf55e5 5504 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5505
93c52dd0
AD		 5506 adapter->link_up = false;
5507 adapter->link_speed = 0;
cf8280ee 5508
93c52dd0
AD		 5509 /* only continue if link was up previously */
5510 if (!netif_carrier_ok(netdev))
5511 return;
264857b8 5512
93c52dd0
AD		 5513 /* poll for SFP+ cable when link is down */
5514 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5515 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5516
3a6a4eda
JK		 5517#ifdef CONFIG_IXGBE_PTP
5518 ixgbe_ptp_start_cyclecounter(adapter);
5519#endif
5520
93c52dd0
AD		 5521 e_info(drv, "NIC Link is Down\n");
5522 netif_carrier_off(netdev);
befa2af7
AD		 5523
5524 /* ping all the active vfs to let them know link has changed */
5525 ixgbe_ping_all_vfs(adapter);
93c52dd0 5526}
e8e26350 5527
93c52dd0
AD		 5528/**
5529 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5530 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5531 **/
5532static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5533{
c4cf55e5 5534 int i;
93c52dd0 5535 int some_tx_pending = 0;
c4cf55e5 5536
93c52dd0 5537 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5538 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5539 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5540 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5541 some_tx_pending = 1;
5542 break;
5543 }
5544 }
5545
5546 if (some_tx_pending) {
5547 /* We've lost link, so the controller stops DMA,
5548 * but we've got queued Tx work that's never going
5549 * to get done, so reset controller to flush Tx.
5550 * (Do the reset outside of interrupt context).
5551 */
c83c6cbd 5552 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5553 }
c4cf55e5 5554 }
c4cf55e5
PWJ		 5555}
5556
a985b6c3
GR		 5557static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5558{
5559 u32 ssvpc;
5560
5561 /* Do not perform spoof check for 82598 */
5562 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5563 return;
5564
5565 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5566
5567 /*
5568 * ssvpc register is cleared on read, if zero then no
5569 * spoofed packets in the last interval.
5570 */
5571 if (!ssvpc)
5572 return;
5573
5574 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5575}
5576
93c52dd0
AD		 5577/**
5578 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5579 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5580 **/
5581static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5582{
5583 /* if interface is down do nothing */
7edebf9a
ET		 5584 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5585 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5586 return;
5587
5588 ixgbe_watchdog_update_link(adapter);
5589
5590 if (adapter->link_up)
5591 ixgbe_watchdog_link_is_up(adapter);
5592 else
5593 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5594
a985b6c3 5595 ixgbe_spoof_check(adapter);
9a799d71 5596 ixgbe_update_stats(adapter);
93c52dd0
AD		 5597
5598 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5599}
10eec955 5600
cf8280ee 5601/**
7086400d 5602 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5603 * @adapter: the ixgbe adapter structure
cf8280ee 5604 **/
7086400d 5605static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5606{
cf8280ee 5607 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5608 s32 err;
cf8280ee 5609
7086400d
AD		 5610 /* not searching for SFP so there is nothing to do here */
5611 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5612 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5613 return;
10eec955 5614
7086400d
AD		 5615 /* someone else is in init, wait until next service event */
5616 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5617 return;
cf8280ee 5618
7086400d
AD		 5619 err = hw->phy.ops.identify_sfp(hw);
5620 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5621 goto sfp_out;
264857b8 5622
7086400d
AD		 5623 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5624 /* If no cable is present, then we need to reset
5625 * the next time we find a good cable. */
5626 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5627 }
9a799d71 5628
7086400d
AD		 5629 /* exit on error */
5630 if (err)
5631 goto sfp_out;
e8e26350 5632
7086400d
AD		 5633 /* exit if reset not needed */
5634 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5635 goto sfp_out;
9a799d71 5636
7086400d 5637 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5638
7086400d
AD		 5639 /*
5640 * A module may be identified correctly, but the EEPROM may not have
5641 * support for that module. setup_sfp() will fail in that case, so
5642 * we should not allow that module to load.
5643 */
5644 if (hw->mac.type == ixgbe_mac_82598EB)
5645 err = hw->phy.ops.reset(hw);
5646 else
5647 err = hw->mac.ops.setup_sfp(hw);
5648
5649 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5650 goto sfp_out;
5651
5652 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5653 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5654
5655sfp_out:
5656 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5657
5658 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5659 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5660 e_dev_err("failed to initialize because an unsupported "
5661 "SFP+ module type was detected.\n");
5662 e_dev_err("Reload the driver after installing a "
5663 "supported module.\n");
5664 unregister_netdev(adapter->netdev);
bc59fcda 5665 }
7086400d 5666}
bc59fcda 5667
7086400d
AD		 5668/**
5669 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5670 * @adapter: the ixgbe adapter structure
7086400d
AD		 5671 **/
5672static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5673{
5674 struct ixgbe_hw *hw = &adapter->hw;
5675 u32 autoneg;
5676 bool negotiation;
5677
5678 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5679 return;
5680
5681 /* someone else is in init, wait until next service event */
5682 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5683 return;
5684
5685 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5686
5687 autoneg = hw->phy.autoneg_advertised;
5688 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5689 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5690 if (hw->mac.ops.setup_link)
5691 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5692
5693 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5694 adapter->link_check_timeout = jiffies;
5695 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5696}
5697
83c61fa9
GR		 5698#ifdef CONFIG_PCI_IOV
5699static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5700{
5701 int vf;
5702 struct ixgbe_hw *hw = &adapter->hw;
5703 struct net_device *netdev = adapter->netdev;
5704 u32 gpc;
5705 u32 ciaa, ciad;
5706
5707 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5708 if (gpc) /* If incrementing then no need for the check below */
5709 return;
5710 /*
5711 * Check to see if a bad DMA write target from an errant or
5712 * malicious VF has caused a PCIe error. If so then we can
5713 * issue a VFLR to the offending VF(s) and then resume without
5714 * requesting a full slot reset.
5715 */
5716
5717 for (vf = 0; vf < adapter->num_vfs; vf++) {
5718 ciaa = (vf << 16) | 0x80000000;
5719 /* 32 bit read so align, we really want status at offset 6 */
5720 ciaa |= PCI_COMMAND;
5721 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5722 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5723 ciaa &= 0x7FFFFFFF;
5724 /* disable debug mode asap after reading data */
5725 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5726 /* Get the upper 16 bits which will be the PCI status reg */
5727 ciad >>= 16;
5728 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5729 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5730 /* Issue VFLR */
5731 ciaa = (vf << 16) | 0x80000000;
5732 ciaa |= 0xA8;
5733 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5734 ciad = 0x00008000; /* VFLR */
5735 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5736 ciaa &= 0x7FFFFFFF;
5737 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5738 }
5739 }
5740}
5741
5742#endif
7086400d
AD		 5743/**
5744 * ixgbe_service_timer - Timer Call-back
5745 * @data: pointer to adapter cast into an unsigned long
5746 **/
5747static void ixgbe_service_timer(unsigned long data)
5748{
5749 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5750 unsigned long next_event_offset;
83c61fa9 5751 bool ready = true;
7086400d 5752
6bb78cfb
AD		 5753 /* poll faster when waiting for link */
5754 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5755 next_event_offset = HZ / 10;
5756 else
5757 next_event_offset = HZ * 2;
83c61fa9 5758
6bb78cfb 5759#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5760 /*
5761 * don't bother with SR-IOV VF DMA hang check if there are
5762 * no VFs or the link is down
5763 */
5764 if (!adapter->num_vfs ||
6bb78cfb 5765 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5766 goto normal_timer_service;
83c61fa9
GR		 5767
5768 /* If we have VFs allocated then we must check for DMA hangs */
5769 ixgbe_check_for_bad_vf(adapter);
5770 next_event_offset = HZ / 50;
5771 adapter->timer_event_accumulator++;
5772
6bb78cfb 5773 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5774 adapter->timer_event_accumulator = 0;
7086400d 5775 else
6bb78cfb 5776 ready = false;
7086400d 5777
6bb78cfb 5778normal_timer_service:
83c61fa9 5779#endif
7086400d
AD		 5780 /* Reset the timer */
5781 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5782
83c61fa9
GR		 5783 if (ready)
5784 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5785}
5786
c83c6cbd
AD		 5787static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5788{
5789 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5790 return;
5791
5792 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5793
5794 /* If we're already down or resetting, just bail */
5795 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5796 test_bit(__IXGBE_RESETTING, &adapter->state))
5797 return;
5798
5799 ixgbe_dump(adapter);
5800 netdev_err(adapter->netdev, "Reset adapter\n");
5801 adapter->tx_timeout_count++;
5802
5803 ixgbe_reinit_locked(adapter);
5804}
5805
7086400d
AD		 5806/**
5807 * ixgbe_service_task - manages and runs subtasks
5808 * @work: pointer to work_struct containing our data
5809 **/
5810static void ixgbe_service_task(struct work_struct *work)
5811{
5812 struct ixgbe_adapter *adapter = container_of(work,
5813 struct ixgbe_adapter,
5814 service_task);
5815
c83c6cbd 5816 ixgbe_reset_subtask(adapter);
7086400d
AD		 5817 ixgbe_sfp_detection_subtask(adapter);
5818 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5819 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5820 ixgbe_watchdog_subtask(adapter);
d034acf1 5821 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5822 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5823#ifdef CONFIG_IXGBE_PTP
5824 ixgbe_ptp_overflow_check(adapter);
5825#endif
7086400d
AD		 5826
5827 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5828}
5829
fd0db0ed
AD		 5830static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5831 struct ixgbe_tx_buffer *first,
244e27ad 5832 u8 *hdr_len)
897ab156 5833{
fd0db0ed 5834 struct sk_buff *skb = first->skb;
897ab156
AD		 5835 u32 vlan_macip_lens, type_tucmd;
5836 u32 mss_l4len_idx, l4len;
9a799d71 5837
897ab156
AD		 5838 if (!skb_is_gso(skb))
5839 return 0;
9a799d71 5840
897ab156 5841 if (skb_header_cloned(skb)) {
244e27ad 5842 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5843 if (err)
5844 return err;
9a799d71 5845 }
9a799d71 5846
897ab156
AD		 5847 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5848 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5849
244e27ad 5850 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5851 struct iphdr *iph = ip_hdr(skb);
5852 iph->tot_len = 0;
5853 iph->check = 0;
5854 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5855 iph->daddr, 0,
5856 IPPROTO_TCP,
5857 0);
5858 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5859 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5860 IXGBE_TX_FLAGS_CSUM |
5861 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5862 } else if (skb_is_gso_v6(skb)) {
5863 ipv6_hdr(skb)->payload_len = 0;
5864 tcp_hdr(skb)->check =
5865 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5866 &ipv6_hdr(skb)->daddr,
5867 0, IPPROTO_TCP, 0);
244e27ad
AD		 5868 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5869 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5870 }
5871
091a6246 5872 /* compute header lengths */
897ab156
AD		 5873 l4len = tcp_hdrlen(skb);
5874 *hdr_len = skb_transport_offset(skb) + l4len;
5875
091a6246
AD		 5876 /* update gso size and bytecount with header size */
5877 first->gso_segs = skb_shinfo(skb)->gso_segs;
5878 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5879
897ab156
AD		 5880 /* mss_l4len_id: use 1 as index for TSO */
5881 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5882 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5883 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5884
5885 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5886 vlan_macip_lens = skb_network_header_len(skb);
5887 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5888 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5889
5890 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5891 mss_l4len_idx);
897ab156
AD		 5892
5893 return 1;
5894}
5895
244e27ad
AD		 5896static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5897 struct ixgbe_tx_buffer *first)
7ca647bd 5898{
fd0db0ed 5899 struct sk_buff *skb = first->skb;
897ab156
AD		 5900 u32 vlan_macip_lens = 0;
5901 u32 mss_l4len_idx = 0;
5902 u32 type_tucmd = 0;
7ca647bd 5903
897ab156 5904 if (skb->ip_summed != CHECKSUM_PARTIAL) {
244e27ad
AD		 5905 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5906 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5907 return;
897ab156
AD		 5908 } else {
5909 u8 l4_hdr = 0;
244e27ad 5910 switch (first->protocol) {
897ab156
AD		 5911 case __constant_htons(ETH_P_IP):
5912 vlan_macip_lens |= skb_network_header_len(skb);
5913 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5914 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5915 break;
897ab156
AD		 5916 case __constant_htons(ETH_P_IPV6):
5917 vlan_macip_lens |= skb_network_header_len(skb);
5918 l4_hdr = ipv6_hdr(skb)->nexthdr;
5919 break;
5920 default:
5921 if (unlikely(net_ratelimit())) {
5922 dev_warn(tx_ring->dev,
5923 "partial checksum but proto=%x!\n",
244e27ad 5924 first->protocol);
897ab156 5925 }
7ca647bd
JP		 5926 break;
5927 }
897ab156
AD		 5928
5929 switch (l4_hdr) {
7ca647bd 5930 case IPPROTO_TCP:
897ab156
AD		 5931 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5932 mss_l4len_idx = tcp_hdrlen(skb) <<
5933 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5934 break;
5935 case IPPROTO_SCTP:
897ab156
AD		 5936 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5937 mss_l4len_idx = sizeof(struct sctphdr) <<
5938 IXGBE_ADVTXD_L4LEN_SHIFT;
5939 break;
5940 case IPPROTO_UDP:
5941 mss_l4len_idx = sizeof(struct udphdr) <<
5942 IXGBE_ADVTXD_L4LEN_SHIFT;
5943 break;
5944 default:
5945 if (unlikely(net_ratelimit())) {
5946 dev_warn(tx_ring->dev,
5947 "partial checksum but l4 proto=%x!\n",
244e27ad 5948 l4_hdr);
897ab156 5949 }
7ca647bd
JP		 5950 break;
5951 }
244e27ad
AD		 5952
5953 /* update TX checksum flag */
5954 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 5955 }
5956
244e27ad 5957 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 5958 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5959 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 5960
897ab156
AD		 5961 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5962 type_tucmd, mss_l4len_idx);
9a799d71
AK		 5963}
5964
d3d00239 5965static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 5966{
d3d00239
AD		 5967 /* set type for advanced descriptor with frame checksum insertion */
5968 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5969 IXGBE_ADVTXD_DCMD_IFCS |
5970 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 5971
d3d00239 5972 /* set HW vlan bit if vlan is present */
66f32a8b 5973 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 5974 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 5975
3a6a4eda
JK		 5976#ifdef CONFIG_IXGBE_PTP
5977 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5978 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5979#endif
5980
d3d00239
AD		 5981 /* set segmentation enable bits for TSO/FSO */
5982#ifdef IXGBE_FCOE
93f5b3c1 5983 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 5984#else
5985 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5986#endif
5987 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 5988
d3d00239
AD		 5989 return cmd_type;
5990}
9a799d71 5991
729739b7
AD		 5992static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5993 u32 tx_flags, unsigned int paylen)
d3d00239 5994{
93f5b3c1 5995 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 5996
d3d00239
AD		 5997 /* enable L4 checksum for TSO and TX checksum offload */
5998 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5999 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6000
93f5b3c1
AD		 6001 /* enble IPv4 checksum for TSO */
6002 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6003 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6004
93f5b3c1
AD		 6005 /* use index 1 context for TSO/FSO/FCOE */
6006#ifdef IXGBE_FCOE
6007 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6008#else
6009 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 6010#endif
93f5b3c1
AD		 6011 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6012
7f9643fd
AD		 6013 /*
6014 * Check Context must be set if Tx switch is enabled, which it
6015 * always is for case where virtual functions are running
6016 */
93f5b3c1
AD		 6017#ifdef IXGBE_FCOE
6018 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6019#else
7f9643fd 6020 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 6021#endif
7f9643fd
AD		 6022 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6023
729739b7 6024 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 6025}
44df32c5 6026
d3d00239
AD		 6027#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6028 IXGBE_TXD_CMD_RS)
6029
6030static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6031 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6032 const u8 hdr_len)
6033{
729739b7 6034 dma_addr_t dma;
fd0db0ed 6035 struct sk_buff *skb = first->skb;
729739b7 6036 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6037 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6038 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6039 unsigned int data_len = skb->data_len;
6040 unsigned int size = skb_headlen(skb);
729739b7 6041 unsigned int paylen = skb->len - hdr_len;
244e27ad 6042 u32 tx_flags = first->tx_flags;
729739b7 6043 __le32 cmd_type;
d3d00239 6044 u16 i = tx_ring->next_to_use;
d3d00239 6045
729739b7
AD		 6046 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6047
6048 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6049 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6050
d3d00239
AD		 6051#ifdef IXGBE_FCOE
6052 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6053 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6054 size -= sizeof(struct fcoe_crc_eof) - data_len;
6055 data_len = 0;
729739b7
AD		 6056 } else {
6057 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6058 }
6059 }
44df32c5 6060
d3d00239 6061#endif
729739b7
AD		 6062 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6063 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6064 goto dma_error;
8ad494b0 6065
729739b7
AD		 6066 /* record length, and DMA address */
6067 dma_unmap_len_set(first, len, size);
6068 dma_unmap_addr_set(first, dma, dma);
9a799d71 6069
729739b7 6070 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6071
d3d00239 6072 for (;;) {
729739b7 6073 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6074 tx_desc->read.cmd_type_len =
6075 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6076
d3d00239 6077 i++;
729739b7 6078 tx_desc++;
d3d00239 6079 if (i == tx_ring->count) {
e4f74028 6080 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6081 i = 0;
6082 }
729739b7
AD		 6083
6084 dma += IXGBE_MAX_DATA_PER_TXD;
6085 size -= IXGBE_MAX_DATA_PER_TXD;
6086
6087 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6088 tx_desc->read.olinfo_status = 0;
d3d00239 6089 }
e5a43549 6090
729739b7
AD		 6091 if (likely(!data_len))
6092 break;
9a799d71 6093
f43f313e
BG		 6094 if (unlikely(skb->no_fcs))
6095 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239 6096 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6097
729739b7
AD		 6098 i++;
6099 tx_desc++;
6100 if (i == tx_ring->count) {
6101 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6102 i = 0;
6103 }
9a799d71 6104
d3d00239 6105#ifdef IXGBE_FCOE
9e903e08 6106 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6107#else
9e903e08 6108 size = skb_frag_size(frag);
d3d00239
AD		 6109#endif
6110 data_len -= size;
9a799d71 6111
729739b7
AD		 6112 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6113 DMA_TO_DEVICE);
6114 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6115 goto dma_error;
9a799d71 6116
729739b7
AD		 6117 tx_buffer = &tx_ring->tx_buffer_info[i];
6118 dma_unmap_len_set(tx_buffer, len, size);
6119 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6120
729739b7
AD		 6121 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6122 tx_desc->read.olinfo_status = 0;
9a799d71 6123
729739b7
AD		 6124 frag++;
6125 }
9a799d71 6126
729739b7
AD		 6127 /* write last descriptor with RS and EOP bits */
6128 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6129 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6130
091a6246 6131 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6132
d3d00239
AD		 6133 /* set the timestamp */
6134 first->time_stamp = jiffies;
9a799d71
AK		 6135
6136 /*
729739b7
AD		 6137 * Force memory writes to complete before letting h/w know there
6138 * are new descriptors to fetch. (Only applicable for weak-ordered
6139 * memory model archs, such as IA-64).
6140 *
6141 * We also need this memory barrier to make certain all of the
6142 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6143 */
6144 wmb();
6145
d3d00239
AD		 6146 /* set next_to_watch value indicating a packet is present */
6147 first->next_to_watch = tx_desc;
6148
729739b7
AD		 6149 i++;
6150 if (i == tx_ring->count)
6151 i = 0;
6152
6153 tx_ring->next_to_use = i;
6154
d3d00239 6155 /* notify HW of packet */
84ea2591 6156 writel(i, tx_ring->tail);
d3d00239
AD		 6157
6158 return;
6159dma_error:
729739b7 6160 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6161
6162 /* clear dma mappings for failed tx_buffer_info map */
6163 for (;;) {
729739b7
AD		 6164 tx_buffer = &tx_ring->tx_buffer_info[i];
6165 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6166 if (tx_buffer == first)
d3d00239
AD		 6167 break;
6168 if (i == 0)
6169 i = tx_ring->count;
6170 i--;
6171 }
6172
d3d00239 6173 tx_ring->next_to_use = i;
9a799d71
AK		 6174}
6175
fd0db0ed 6176static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6177 struct ixgbe_tx_buffer *first)
69830529
AD		 6178{
6179 struct ixgbe_q_vector *q_vector = ring->q_vector;
6180 union ixgbe_atr_hash_dword input = { .dword = 0 };
6181 union ixgbe_atr_hash_dword common = { .dword = 0 };
6182 union {
6183 unsigned char *network;
6184 struct iphdr *ipv4;
6185 struct ipv6hdr *ipv6;
6186 } hdr;
ee9e0f0b 6187 struct tcphdr *th;
905e4a41 6188 __be16 vlan_id;
c4cf55e5 6189
69830529
AD		 6190 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6191 if (!q_vector)
6192 return;
6193
6194 /* do nothing if sampling is disabled */
6195 if (!ring->atr_sample_rate)
d3ead241 6196 return;
c4cf55e5 6197
69830529 6198 ring->atr_count++;
c4cf55e5 6199
69830529 6200 /* snag network header to get L4 type and address */
fd0db0ed 6201 hdr.network = skb_network_header(first->skb);
69830529
AD		 6202
6203 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6204 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6205 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6206 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6207 hdr.ipv4->protocol != IPPROTO_TCP))
6208 return;
ee9e0f0b 6209
fd0db0ed 6210 th = tcp_hdr(first->skb);
c4cf55e5 6211
66f32a8b
AD		 6212 /* skip this packet since it is invalid or the socket is closing */
6213 if (!th || th->fin)
69830529
AD		 6214 return;
6215
6216 /* sample on all syn packets or once every atr sample count */
6217 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6218 return;
6219
6220 /* reset sample count */
6221 ring->atr_count = 0;
6222
244e27ad 6223 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6224
6225 /*
6226 * src and dst are inverted, think how the receiver sees them
6227 *
6228 * The input is broken into two sections, a non-compressed section
6229 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6230 * is XORed together and stored in the compressed dword.
6231 */
6232 input.formatted.vlan_id = vlan_id;
6233
6234 /*
6235 * since src port and flex bytes occupy the same word XOR them together
6236 * and write the value to source port portion of compressed dword
6237 */
244e27ad 6238 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6239 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6240 else
244e27ad 6241 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6242 common.port.dst ^= th->source;
6243
244e27ad 6244 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6245 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6246 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6247 } else {
6248 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6249 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6250 hdr.ipv6->saddr.s6_addr32[1] ^
6251 hdr.ipv6->saddr.s6_addr32[2] ^
6252 hdr.ipv6->saddr.s6_addr32[3] ^
6253 hdr.ipv6->daddr.s6_addr32[0] ^
6254 hdr.ipv6->daddr.s6_addr32[1] ^
6255 hdr.ipv6->daddr.s6_addr32[2] ^
6256 hdr.ipv6->daddr.s6_addr32[3];
6257 }
c4cf55e5
PWJ		 6258
6259 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6260 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6261 input, common, ring->queue_index);
c4cf55e5
PWJ		 6262}
6263
63544e9c 6264static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6265{
fc77dc3c 6266 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6267 /* Herbert's original patch had:
6268 * smp_mb__after_netif_stop_queue();
6269 * but since that doesn't exist yet, just open code it. */
6270 smp_mb();
6271
6272 /* We need to check again in a case another CPU has just
6273 * made room available. */
7d4987de 6274 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6275 return -EBUSY;
6276
6277 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6278 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6279 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6280 return 0;
6281}
6282
82d4e46e 6283static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6284{
7d4987de 6285 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6286 return 0;
fc77dc3c 6287 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6288}
6289
09a3b1f8
SH		 6290static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6291{
6292 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6293 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6294 smp_processor_id();
56075a98 6295#ifdef IXGBE_FCOE
6440752c 6296 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6297
e5b64635
JF		 6298 if (((protocol == htons(ETH_P_FCOE)) ||
6299 (protocol == htons(ETH_P_FIP))) &&
6300 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6301 struct ixgbe_ring_feature *f;
6302
6303 f = &adapter->ring_feature[RING_F_FCOE];
6304
6305 while (txq >= f->indices)
6306 txq -= f->indices;
e4b317e9 6307 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6308
e5b64635 6309 return txq;
56075a98
JF		 6310 }
6311#endif
6312
fdd3d631
KK		 6313 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6314 while (unlikely(txq >= dev->real_num_tx_queues))
6315 txq -= dev->real_num_tx_queues;
5f715823 6316 return txq;
fdd3d631 6317 }
c4cf55e5 6318
09a3b1f8
SH		 6319 return skb_tx_hash(dev, skb);
6320}
6321
fc77dc3c 6322netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6323 struct ixgbe_adapter *adapter,
6324 struct ixgbe_ring *tx_ring)
9a799d71 6325{
d3d00239 6326 struct ixgbe_tx_buffer *first;
5f715823 6327 int tso;
d3d00239 6328 u32 tx_flags = 0;
a535c30e
AD		 6329#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6330 unsigned short f;
6331#endif
a535c30e 6332 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6333 __be16 protocol = skb->protocol;
63544e9c 6334 u8 hdr_len = 0;
5e09a105 6335
a535c30e
AD		 6336 /*
6337 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6338 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6339 * + 2 desc gap to keep tail from touching head,
6340 * + 1 desc for context descriptor,
6341 * otherwise try next time
6342 */
6343#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6344 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6345 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6346#else
6347 count += skb_shinfo(skb)->nr_frags;
6348#endif
6349 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6350 tx_ring->tx_stats.tx_busy++;
6351 return NETDEV_TX_BUSY;
6352 }
6353
fd0db0ed
AD		 6354 /* record the location of the first descriptor for this packet */
6355 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6356 first->skb = skb;
091a6246
AD		 6357 first->bytecount = skb->len;
6358 first->gso_segs = 1;
fd0db0ed 6359
66f32a8b 6360 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6361 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6362 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6363 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6364 /* else if it is a SW VLAN check the next protocol and store the tag */
6365 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6366 struct vlan_hdr *vhdr, _vhdr;
6367 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6368 if (!vhdr)
6369 goto out_drop;
6370
6371 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6372 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6373 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6374 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6375 }
6376
aa7bd467
JK		 6377 skb_tx_timestamp(skb);
6378
3a6a4eda
JK		 6379#ifdef CONFIG_IXGBE_PTP
6380 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6381 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6382 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6383 }
6384#endif
6385
9e0c5648
AD		 6386#ifdef CONFIG_PCI_IOV
6387 /*
6388 * Use the l2switch_enable flag - would be false if the DMA
6389 * Tx switch had been disabled.
6390 */
6391 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6392 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6393
6394#endif
32701dc2 6395 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6396 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6397 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6398 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6399 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6400 tx_flags |= (skb->priority & 0x7) <<
6401 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6402 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6403 struct vlan_ethhdr *vhdr;
6404 if (skb_header_cloned(skb) &&
6405 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6406 goto out_drop;
6407 vhdr = (struct vlan_ethhdr *)skb->data;
6408 vhdr->h_vlan_TCI = htons(tx_flags >>
6409 IXGBE_TX_FLAGS_VLAN_SHIFT);
6410 } else {
6411 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6412 }
9a799d71 6413 }
eacd73f7 6414
244e27ad
AD		 6415 /* record initial flags and protocol */
6416 first->tx_flags = tx_flags;
6417 first->protocol = protocol;
6418
eacd73f7 6419#ifdef IXGBE_FCOE
66f32a8b
AD		 6420 /* setup tx offload for FCoE */
6421 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6422 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6423 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6424 if (tso < 0)
6425 goto out_drop;
9a799d71 6426
66f32a8b 6427 goto xmit_fcoe;
eacd73f7 6428 }
9a799d71 6429
66f32a8b 6430#endif /* IXGBE_FCOE */
244e27ad 6431 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6432 if (tso < 0)
897ab156 6433 goto out_drop;
244e27ad
AD		 6434 else if (!tso)
6435 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6436
6437 /* add the ATR filter if ATR is on */
6438 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6439 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6440
6441#ifdef IXGBE_FCOE
6442xmit_fcoe:
6443#endif /* IXGBE_FCOE */
244e27ad 6444 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6445
6446 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6447
6448 return NETDEV_TX_OK;
897ab156
AD		 6449
6450out_drop:
fd0db0ed
AD		 6451 dev_kfree_skb_any(first->skb);
6452 first->skb = NULL;
6453
897ab156 6454 return NETDEV_TX_OK;
9a799d71
AK		 6455}
6456
a50c29dd
AD		 6457static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6458 struct net_device *netdev)
84418e3b
AD		 6459{
6460 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6461 struct ixgbe_ring *tx_ring;
6462
a50c29dd
AD		 6463 /*
6464 * The minimum packet size for olinfo paylen is 17 so pad the skb
6465 * in order to meet this minimum size requirement.
6466 */
f73332fc
SH		 6467 if (unlikely(skb->len < 17)) {
6468 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6469 return NETDEV_TX_OK;
6470 skb->len = 17;
6471 }
6472
84418e3b 6473 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6474 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6475}
6476
9a799d71
AK		 6477/**
6478 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6479 * @netdev: network interface device structure
6480 * @p: pointer to an address structure
6481 *
6482 * Returns 0 on success, negative on failure
6483 **/
6484static int ixgbe_set_mac(struct net_device *netdev, void *p)
6485{
6486 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6487 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6488 struct sockaddr *addr = p;
6489
6490 if (!is_valid_ether_addr(addr->sa_data))
6491 return -EADDRNOTAVAIL;
6492
6493 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6494 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6495
1d9c0bfd 6496 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6497
6498 return 0;
6499}
6500
6b73e10d
BH		 6501static int
6502ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6503{
6504 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6505 struct ixgbe_hw *hw = &adapter->hw;
6506 u16 value;
6507 int rc;
6508
6509 if (prtad != hw->phy.mdio.prtad)
6510 return -EINVAL;
6511 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6512 if (!rc)
6513 rc = value;
6514 return rc;
6515}
6516
6517static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6518 u16 addr, u16 value)
6519{
6520 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6521 struct ixgbe_hw *hw = &adapter->hw;
6522
6523 if (prtad != hw->phy.mdio.prtad)
6524 return -EINVAL;
6525 return hw->phy.ops.write_reg(hw, addr, devad, value);
6526}
6527
6528static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6529{
6530 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6531
3a6a4eda
JK		 6532 switch (cmd) {
6533#ifdef CONFIG_IXGBE_PTP
6534 case SIOCSHWTSTAMP:
6535 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6536#endif
6537 default:
6538 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6539 }
6b73e10d
BH		 6540}
6541
0365e6e4
PW		 6542/**
6543 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6544 * netdev->dev_addrs
0365e6e4
PW		 6545 * @netdev: network interface device structure
6546 *
6547 * Returns non-zero on failure
6548 **/
6549static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6550{
6551 int err = 0;
6552 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6553 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6554
7fa7c9dc 6555 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6556 rtnl_lock();
7fa7c9dc 6557 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6558 rtnl_unlock();
7fa7c9dc
AD		 6559
6560 /* update SAN MAC vmdq pool selection */
6561 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6562 }
6563 return err;
6564}
6565
6566/**
6567 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6568 * netdev->dev_addrs
0365e6e4
PW		 6569 * @netdev: network interface device structure
6570 *
6571 * Returns non-zero on failure
6572 **/
6573static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6574{
6575 int err = 0;
6576 struct ixgbe_adapter *adapter = netdev_priv(dev);
6577 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6578
6579 if (is_valid_ether_addr(mac->san_addr)) {
6580 rtnl_lock();
6581 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6582 rtnl_unlock();
6583 }
6584 return err;
6585}
6586
9a799d71
AK		 6587#ifdef CONFIG_NET_POLL_CONTROLLER
6588/*
6589 * Polling 'interrupt' - used by things like netconsole to send skbs
6590 * without having to re-enable interrupts. It's not called while
6591 * the interrupt routine is executing.
6592 */
6593static void ixgbe_netpoll(struct net_device *netdev)
6594{
6595 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6596 int i;
9a799d71 6597
1a647bd2
AD		 6598 /* if interface is down do nothing */
6599 if (test_bit(__IXGBE_DOWN, &adapter->state))
6600 return;
6601
9a799d71 6602 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6603 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6604 for (i = 0; i < adapter->num_q_vectors; i++)
6605 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6606 } else {
6607 ixgbe_intr(adapter->pdev->irq, netdev);
6608 }
9a799d71 6609 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6610}
9a799d71 6611
581330ba 6612#endif
de1036b1
ED		 6613static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6614 struct rtnl_link_stats64 *stats)
6615{
6616 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6617 int i;
6618
1a51502b 6619 rcu_read_lock();
de1036b1 6620 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6621 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6622 u64 bytes, packets;
6623 unsigned int start;
6624
1a51502b
ED		 6625 if (ring) {
6626 do {
6627 start = u64_stats_fetch_begin_bh(&ring->syncp);
6628 packets = ring->stats.packets;
6629 bytes = ring->stats.bytes;
6630 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6631 stats->rx_packets += packets;
6632 stats->rx_bytes += bytes;
6633 }
de1036b1 6634 }
1ac9ad13
ED		 6635
6636 for (i = 0; i < adapter->num_tx_queues; i++) {
6637 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6638 u64 bytes, packets;
6639 unsigned int start;
6640
6641 if (ring) {
6642 do {
6643 start = u64_stats_fetch_begin_bh(&ring->syncp);
6644 packets = ring->stats.packets;
6645 bytes = ring->stats.bytes;
6646 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6647 stats->tx_packets += packets;
6648 stats->tx_bytes += bytes;
6649 }
6650 }
1a51502b 6651 rcu_read_unlock();
de1036b1
ED		 6652 /* following stats updated by ixgbe_watchdog_task() */
6653 stats->multicast = netdev->stats.multicast;
6654 stats->rx_errors = netdev->stats.rx_errors;
6655 stats->rx_length_errors = netdev->stats.rx_length_errors;
6656 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6657 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6658 return stats;
6659}
6660
8af3c33f 6661#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6662/**
6663 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6664 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6665 * @tc: number of traffic classes currently enabled
6666 *
6667 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6668 * 802.1Q priority maps to a packet buffer that exists.
6669 */
6670static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6671{
6672 struct ixgbe_hw *hw = &adapter->hw;
6673 u32 reg, rsave;
6674 int i;
6675
6676 /* 82598 have a static priority to TC mapping that can not
6677 * be changed so no validation is needed.
6678 */
6679 if (hw->mac.type == ixgbe_mac_82598EB)
6680 return;
6681
6682 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6683 rsave = reg;
6684
6685 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6686 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6687
6688 /* If up2tc is out of bounds default to zero */
6689 if (up2tc > tc)
6690 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6691 }
6692
6693 if (reg != rsave)
6694 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6695
6696 return;
6697}
6698
02debdc9
AD		 6699/**
6700 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6701 * @adapter: Pointer to adapter struct
6702 *
6703 * Populate the netdev user priority to tc map
6704 */
6705static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6706{
6707 struct net_device *dev = adapter->netdev;
6708 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6709 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6710 u8 prio;
6711
6712 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6713 u8 tc = 0;
6714
6715 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6716 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6717 else if (ets)
6718 tc = ets->prio_tc[prio];
6719
6720 netdev_set_prio_tc_map(dev, prio, tc);
6721 }
6722}
6723
49ce9c2c
BH		 6724/**
6725 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6726 *
6727 * @netdev: net device to configure
6728 * @tc: number of traffic classes to enable
6729 */
6730int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6731{
8b1c0b24
JF		 6732 struct ixgbe_adapter *adapter = netdev_priv(dev);
6733 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6734
8b1c0b24 6735 /* Hardware supports up to 8 traffic classes */
4de2a022 6736 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6737 (hw->mac.type == ixgbe_mac_82598EB &&
6738 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6739 return -EINVAL;
6740
6741 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6742 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6743 * hardware is not flexible enough to do this dynamically.
6744 */
6745 if (netif_running(dev))
6746 ixgbe_close(dev);
6747 ixgbe_clear_interrupt_scheme(adapter);
6748
e7589eab 6749 if (tc) {
8b1c0b24 6750 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6751 ixgbe_set_prio_tc_map(adapter);
6752
e7589eab 6753 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6754
943561d3
AD		 6755 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6756 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6757 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6758 }
e7589eab 6759 } else {
8b1c0b24 6760 netdev_reset_tc(dev);
02debdc9 6761
943561d3
AD		 6762 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6763 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6764
6765 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6766
6767 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6768 adapter->dcb_cfg.pfc_mode_enable = false;
6769 }
6770
8b1c0b24
JF		 6771 ixgbe_init_interrupt_scheme(adapter);
6772 ixgbe_validate_rtr(adapter, tc);
6773 if (netif_running(dev))
6774 ixgbe_open(dev);
6775
6776 return 0;
6777}
de1036b1 6778
8af3c33f 6779#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6780void ixgbe_do_reset(struct net_device *netdev)
6781{
6782 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6783
6784 if (netif_running(netdev))
6785 ixgbe_reinit_locked(adapter);
6786 else
6787 ixgbe_reset(adapter);
6788}
6789
c8f44aff 6790static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6791 netdev_features_t features)
082757af
DS		 6792{
6793 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6794
082757af 6795 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6796 if (!(features & NETIF_F_RXCSUM))
6797 features &= ~NETIF_F_LRO;
082757af 6798
567d2de2
AD		 6799 /* Turn off LRO if not RSC capable */
6800 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6801 features &= ~NETIF_F_LRO;
8e2813f5 6802
567d2de2 6803 return features;
082757af
DS		 6804}
6805
c8f44aff 6806static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6807 netdev_features_t features)
082757af
DS		 6808{
6809 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6810 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6811 bool need_reset = false;
6812
082757af 6813 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6814 if (!(features & NETIF_F_LRO)) {
6815 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6816 need_reset = true;
567d2de2
AD		 6817 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6818 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6819 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6820 if (adapter->rx_itr_setting == 1 ||
6821 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6822 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6823 need_reset = true;
6824 } else if ((changed ^ features) & NETIF_F_LRO) {
6825 e_info(probe, "rx-usecs set too low, "
6826 "disabling RSC\n");
082757af
DS		 6827 }
6828 }
6829
6830 /*
6831 * Check if Flow Director n-tuple support was enabled or disabled. If
6832 * the state changed, we need to reset.
6833 */
39cb681b
AD		 6834 switch (features & NETIF_F_NTUPLE) {
6835 case NETIF_F_NTUPLE:
567d2de2 6836 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6837 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6838 need_reset = true;
6839
567d2de2
AD		 6840 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6841 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6842 break;
6843 default:
6844 /* turn off perfect filters, enable ATR and reset */
6845 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6846 need_reset = true;
6847
6848 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6849
6850 /* We cannot enable ATR if SR-IOV is enabled */
6851 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6852 break;
6853
6854 /* We cannot enable ATR if we have 2 or more traffic classes */
6855 if (netdev_get_num_tc(netdev) > 1)
6856 break;
6857
6858 /* We cannot enable ATR if RSS is disabled */
6859 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6860 break;
6861
6862 /* A sample rate of 0 indicates ATR disabled */
6863 if (!adapter->atr_sample_rate)
6864 break;
6865
6866 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6867 break;
082757af
DS		 6868 }
6869
146d4cc9
JF		 6870 if (features & NETIF_F_HW_VLAN_RX)
6871 ixgbe_vlan_strip_enable(adapter);
6872 else
6873 ixgbe_vlan_strip_disable(adapter);
6874
3f2d1c0f
BG		 6875 if (changed & NETIF_F_RXALL)
6876 need_reset = true;
6877
567d2de2 6878 netdev->features = features;
082757af
DS		 6879 if (need_reset)
6880 ixgbe_do_reset(netdev);
6881
6882 return 0;
082757af
DS		 6883}
6884
0f4b0add
JF		 6885static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6886 struct net_device *dev,
6887 unsigned char *addr,
6888 u16 flags)
6889{
6890 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6891 int err;
6892
6893 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6894 return -EOPNOTSUPP;
0f4b0add
JF		 6895
6896 if (ndm->ndm_state & NUD_PERMANENT) {
6897 pr_info("%s: FDB only supports static addresses\n",
6898 ixgbe_driver_name);
6899 return -EINVAL;
6900 }
6901
95447461
JF		 6902 if (is_unicast_ether_addr(addr)) {
6903 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6904
6905 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6906 err = dev_uc_add_excl(dev, addr);
0f4b0add 6907 else
95447461
JF		 6908 err = -ENOMEM;
6909 } else if (is_multicast_ether_addr(addr)) {
6910 err = dev_mc_add_excl(dev, addr);
6911 } else {
6912 err = -EINVAL;
0f4b0add
JF		 6913 }
6914
6915 /* Only return duplicate errors if NLM_F_EXCL is set */
6916 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6917 err = 0;
6918
6919 return err;
6920}
6921
6922static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6923 struct net_device *dev,
6924 unsigned char *addr)
6925{
6926 struct ixgbe_adapter *adapter = netdev_priv(dev);
6927 int err = -EOPNOTSUPP;
6928
6929 if (ndm->ndm_state & NUD_PERMANENT) {
6930 pr_info("%s: FDB only supports static addresses\n",
6931 ixgbe_driver_name);
6932 return -EINVAL;
6933 }
6934
6935 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6936 if (is_unicast_ether_addr(addr))
6937 err = dev_uc_del(dev, addr);
6938 else if (is_multicast_ether_addr(addr))
6939 err = dev_mc_del(dev, addr);
6940 else
6941 err = -EINVAL;
6942 }
6943
6944 return err;
6945}
6946
6947static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6948 struct netlink_callback *cb,
6949 struct net_device *dev,
6950 int idx)
6951{
6952 struct ixgbe_adapter *adapter = netdev_priv(dev);
6953
6954 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6955 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6956
6957 return idx;
6958}
6959
0edc3527 6960static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6961 .ndo_open = ixgbe_open,
0edc3527 6962 .ndo_stop = ixgbe_close,
00829823 6963 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6964 .ndo_select_queue = ixgbe_select_queue,
581330ba 6965 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6966 .ndo_validate_addr = eth_validate_addr,
6967 .ndo_set_mac_address = ixgbe_set_mac,
6968 .ndo_change_mtu = ixgbe_change_mtu,
6969 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6970 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6971 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6972 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6973 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6974 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6975 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 6976 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 6977 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6978 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 6979#ifdef CONFIG_IXGBE_DCB
24095aa3 6980 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 6981#endif
0edc3527
SH		 6982#ifdef CONFIG_NET_POLL_CONTROLLER
6983 .ndo_poll_controller = ixgbe_netpoll,
6984#endif
332d4a7d
YZ		 6985#ifdef IXGBE_FCOE
6986 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 6987 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 6988 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6989 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6990 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6991 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 6992 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 6993#endif /* IXGBE_FCOE */
082757af
DS		 6994 .ndo_set_features = ixgbe_set_features,
6995 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 6996 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6997 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6998 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 6999};
7000
8e2813f5
JK		 7001/**
7002 * ixgbe_wol_supported - Check whether device supports WoL
7003 * @hw: hw specific details
7004 * @device_id: the device ID
7005 * @subdev_id: the subsystem device ID
7006 *
7007 * This function is used by probe and ethtool to determine
7008 * which devices have WoL support
7009 *
7010 **/
7011int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7012 u16 subdevice_id)
7013{
7014 struct ixgbe_hw *hw = &adapter->hw;
7015 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7016 int is_wol_supported = 0;
7017
7018 switch (device_id) {
7019 case IXGBE_DEV_ID_82599_SFP:
7020 /* Only these subdevices could supports WOL */
7021 switch (subdevice_id) {
7022 case IXGBE_SUBDEV_ID_82599_560FLR:
7023 /* only support first port */
7024 if (hw->bus.func != 0)
7025 break;
7026 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7027 case IXGBE_SUBDEV_ID_82599_RNDC:
8e2813f5
JK		 7028 is_wol_supported = 1;
7029 break;
7030 }
7031 break;
7032 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7033 /* All except this subdevice support WOL */
7034 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7035 is_wol_supported = 1;
7036 break;
7037 case IXGBE_DEV_ID_82599_KX4:
7038 is_wol_supported = 1;
7039 break;
7040 case IXGBE_DEV_ID_X540T:
7041 /* check eeprom to see if enabled wol */
7042 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7043 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7044 (hw->bus.func == 0))) {
7045 is_wol_supported = 1;
7046 }
7047 break;
7048 }
7049
7050 return is_wol_supported;
7051}
7052
9a799d71
AK		 7053/**
7054 * ixgbe_probe - Device Initialization Routine
7055 * @pdev: PCI device information struct
7056 * @ent: entry in ixgbe_pci_tbl
7057 *
7058 * Returns 0 on success, negative on failure
7059 *
7060 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7061 * The OS initialization, configuring of the adapter private structure,
7062 * and a hardware reset occur.
7063 **/
7064static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7065 const struct pci_device_id *ent)
9a799d71
AK		 7066{
7067 struct net_device *netdev;
7068 struct ixgbe_adapter *adapter = NULL;
7069 struct ixgbe_hw *hw;
7070 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7071 static int cards_found;
7072 int i, err, pci_using_dac;
289700db 7073 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7074 unsigned int indices = num_possible_cpus();
3f4a6f00 7075 unsigned int dcb_max = 0;
eacd73f7
YZ		 7076#ifdef IXGBE_FCOE
7077 u16 device_caps;
7078#endif
289700db 7079 u32 eec;
9a799d71 7080
bded64a7
AG		 7081 /* Catch broken hardware that put the wrong VF device ID in
7082 * the PCIe SR-IOV capability.
7083 */
7084 if (pdev->is_virtfn) {
7085 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7086 pci_name(pdev), pdev->vendor, pdev->device);
7087 return -EINVAL;
7088 }
7089
9ce77666 7090 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7091 if (err)
7092 return err;
7093
1b507730
NN		 7094 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7095 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7096 pci_using_dac = 1;
7097 } else {
1b507730 7098 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7099 if (err) {
1b507730
NN		 7100 err = dma_set_coherent_mask(&pdev->dev,
7101 DMA_BIT_MASK(32));
9a799d71 7102 if (err) {
b8bc0421
DC		 7103 dev_err(&pdev->dev,
7104 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7105 goto err_dma;
7106 }
7107 }
7108 pci_using_dac = 0;
7109 }
7110
9ce77666 7111 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7112 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7113 if (err) {
b8bc0421
DC		 7114 dev_err(&pdev->dev,
7115 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7116 goto err_pci_reg;
7117 }
7118
19d5afd4 7119 pci_enable_pcie_error_reporting(pdev);
6fabd715 7120
9a799d71 7121 pci_set_master(pdev);
fb3b27bc 7122 pci_save_state(pdev);
9a799d71 7123
e901acd6 7124#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7125 if (ii->mac == ixgbe_mac_82598EB)
7126 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7127 IXGBE_MAX_RSS_INDICES);
7128 else
7129 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7130 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7131#endif
7132
c85a2618
JF		 7133 if (ii->mac == ixgbe_mac_82598EB)
7134 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7135 else
7136 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7137
e901acd6 7138#ifdef IXGBE_FCOE
c85a2618
JF		 7139 indices += min_t(unsigned int, num_possible_cpus(),
7140 IXGBE_MAX_FCOE_INDICES);
7141#endif
3f4a6f00 7142 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7143 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7144 if (!netdev) {
7145 err = -ENOMEM;
7146 goto err_alloc_etherdev;
7147 }
7148
9a799d71
AK		 7149 SET_NETDEV_DEV(netdev, &pdev->dev);
7150
9a799d71 7151 adapter = netdev_priv(netdev);
c60fbb00 7152 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7153
7154 adapter->netdev = netdev;
7155 adapter->pdev = pdev;
7156 hw = &adapter->hw;
7157 hw->back = adapter;
b3f4d599 7158 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7159
05857980 7160 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7161 pci_resource_len(pdev, 0));
9a799d71
AK		 7162 if (!hw->hw_addr) {
7163 err = -EIO;
7164 goto err_ioremap;
7165 }
7166
7167 for (i = 1; i <= 5; i++) {
7168 if (pci_resource_len(pdev, i) == 0)
7169 continue;
7170 }
7171
0edc3527 7172 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7173 ixgbe_set_ethtool_ops(netdev);
9a799d71 7174 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7175 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7176
9a799d71
AK		 7177 adapter->bd_number = cards_found;
7178
9a799d71
AK		 7179 /* Setup hw api */
7180 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7181 hw->mac.type = ii->mac;
9a799d71 7182
c44ade9e
JB		 7183 /* EEPROM */
7184 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7185 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7186 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7187 if (!(eec & (1 << 8)))
7188 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7189
7190 /* PHY */
7191 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7192 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7193 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7194 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7195 hw->phy.mdio.mmds = 0;
7196 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7197 hw->phy.mdio.dev = netdev;
7198 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7199 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7200
8ca783ab 7201 ii->get_invariants(hw);
9a799d71
AK		 7202
7203 /* setup the private structure */
7204 err = ixgbe_sw_init(adapter);
7205 if (err)
7206 goto err_sw_init;
7207
e86bff0e 7208 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7209 switch (adapter->hw.mac.type) {
7210 case ixgbe_mac_82599EB:
7211 case ixgbe_mac_X540:
e86bff0e 7212 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7213 break;
7214 default:
7215 break;
7216 }
e86bff0e 7217
bf069c97
DS		 7218 /*
7219 * If there is a fan on this device and it has failed log the
7220 * failure.
7221 */
7222 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7223 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7224 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7225 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7226 }
7227
8ef78adc
PWJ		 7228 if (allow_unsupported_sfp)
7229 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7230
c44ade9e 7231 /* reset_hw fills in the perm_addr as well */
119fc60a 7232 hw->phy.reset_if_overtemp = true;
c44ade9e 7233 err = hw->mac.ops.reset_hw(hw);
119fc60a 7234 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7235 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7236 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7237 err = 0;
7238 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7239 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7240 "module type was detected.\n");
7241 e_dev_err("Reload the driver after installing a supported "
7242 "module.\n");
04f165ef
PW		 7243 goto err_sw_init;
7244 } else if (err) {
849c4542 7245 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7246 goto err_sw_init;
7247 }
7248
99d74487
AD		 7249#ifdef CONFIG_PCI_IOV
7250 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7251
99d74487 7252#endif
396e799c 7253 netdev->features = NETIF_F_SG |
e8e9f696 7254 NETIF_F_IP_CSUM |
082757af 7255 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7256 NETIF_F_HW_VLAN_TX |
7257 NETIF_F_HW_VLAN_RX |
082757af
DS		 7258 NETIF_F_HW_VLAN_FILTER |
7259 NETIF_F_TSO |
7260 NETIF_F_TSO6 |
082757af
DS		 7261 NETIF_F_RXHASH |
7262 NETIF_F_RXCSUM;
9a799d71 7263
082757af 7264 netdev->hw_features = netdev->features;
ad31c402 7265
58be7666
DS		 7266 switch (adapter->hw.mac.type) {
7267 case ixgbe_mac_82599EB:
7268 case ixgbe_mac_X540:
45a5ead0 7269 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7270 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7271 NETIF_F_NTUPLE;
58be7666
DS		 7272 break;
7273 default:
7274 break;
7275 }
45a5ead0 7276
3f2d1c0f
BG		 7277 netdev->hw_features |= NETIF_F_RXALL;
7278
ad31c402
JK		 7279 netdev->vlan_features |= NETIF_F_TSO;
7280 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7281 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7282 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7283 netdev->vlan_features |= NETIF_F_SG;
7284
01789349 7285 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7286 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7287
7a6b6f51 7288#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7289 netdev->dcbnl_ops = &dcbnl_ops;
7290#endif
7291
eacd73f7 7292#ifdef IXGBE_FCOE
0d551589 7293 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7294 if (hw->mac.ops.get_device_caps) {
7295 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7296 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7297 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7298 }
7c8ae65a
AD		 7299
7300 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7301
a58915c7
AD		 7302 netdev->features |= NETIF_F_FSO |
7303 NETIF_F_FCOE_CRC;
7304
7c8ae65a
AD		 7305 netdev->vlan_features |= NETIF_F_FSO |
7306 NETIF_F_FCOE_CRC |
7307 NETIF_F_FCOE_MTU;
5e09d7f6 7308 }
eacd73f7 7309#endif /* IXGBE_FCOE */
7b872a55 7310 if (pci_using_dac) {
9a799d71 7311 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7312 netdev->vlan_features |= NETIF_F_HIGHDMA;
7313 }
9a799d71 7314
082757af
DS		 7315 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7316 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7317 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7318 netdev->features |= NETIF_F_LRO;
7319
9a799d71 7320 /* make sure the EEPROM is good */
c44ade9e 7321 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7322 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7323 err = -EIO;
35937c05 7324 goto err_sw_init;
9a799d71
AK		 7325 }
7326
7327 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7328 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7329
c44ade9e 7330 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7331 e_dev_err("invalid MAC address\n");
9a799d71 7332 err = -EIO;
35937c05 7333 goto err_sw_init;
9a799d71
AK		 7334 }
7335
7086400d 7336 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7337 (unsigned long) adapter);
9a799d71 7338
7086400d
AD		 7339 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7340 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7341
021230d4
AV		 7342 err = ixgbe_init_interrupt_scheme(adapter);
7343 if (err)
7344 goto err_sw_init;
9a799d71 7345
8e2813f5 7346 /* WOL not supported for all devices */
c23f5b6b 7347 adapter->wol = 0;
8e2813f5
JK		 7348 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7349 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7350 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7351
e8e26350
PW		 7352 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7353
3a6a4eda
JK		 7354#ifdef CONFIG_IXGBE_PTP
7355 ixgbe_ptp_init(adapter);
7356#endif /* CONFIG_IXGBE_PTP*/
7357
15e5209f
ET		 7358 /* save off EEPROM version number */
7359 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7360 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7361
04f165ef
PW		 7362 /* pick up the PCI bus settings for reporting later */
7363 hw->mac.ops.get_bus_info(hw);
7364
9a799d71 7365 /* print bus type/speed/width info */
849c4542 7366 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7367 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7368 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7369 "Unknown"),
7370 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7371 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7372 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7373 "Unknown"),
7374 netdev->dev_addr);
289700db
DS		 7375
7376 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7377 if (err)
9fe93afd 7378 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7379 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7380 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7381 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7382 part_str);
e8e26350 7383 else
289700db
DS		 7384 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7385 hw->mac.type, hw->phy.type, part_str);
9a799d71 7386
e8e26350 7387 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7388 e_dev_warn("PCI-Express bandwidth available for this card is "
7389 "not sufficient for optimal performance.\n");
7390 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7391 "is required.\n");
0c254d86
AK		 7392 }
7393
9a799d71 7394 /* reset the hardware with the new settings */
794caeb2 7395 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7396 if (err == IXGBE_ERR_EEPROM_VERSION) {
7397 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7398 e_dev_warn("This device is a pre-production adapter/LOM. "
7399 "Please be aware there may be issues associated "
7400 "with your hardware. If you are experiencing "
7401 "problems please contact your Intel or hardware "
7402 "representative who provided you with this "
7403 "hardware.\n");
794caeb2 7404 }
9a799d71
AK		 7405 strcpy(netdev->name, "eth%d");
7406 err = register_netdev(netdev);
7407 if (err)
7408 goto err_register;
7409
93d3ce8f
ET		 7410 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7411 if (hw->mac.ops.disable_tx_laser &&
7412 ((hw->phy.multispeed_fiber) ||
7413 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7414 (hw->mac.type == ixgbe_mac_82599EB))))
7415 hw->mac.ops.disable_tx_laser(hw);
7416
54386467
JB		 7417 /* carrier off reporting is important to ethtool even BEFORE open */
7418 netif_carrier_off(netdev);
7419
5dd2d332 7420#ifdef CONFIG_IXGBE_DCA
652f093f 7421 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7422 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7423 ixgbe_setup_dca(adapter);
7424 }
7425#endif
1cdd1ec8 7426 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7427 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7428 for (i = 0; i < adapter->num_vfs; i++)
7429 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7430 }
7431
2466dd9c
JK		 7432 /* firmware requires driver version to be 0xFFFFFFFF
7433 * since os does not support feature
7434 */
9612de92 7435 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7436 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7437 0xFF);
9612de92 7438
0365e6e4
PW		 7439 /* add san mac addr to netdev */
7440 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7441
ea81875a 7442 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7443 cards_found++;
3ca8bc6d 7444
1210982b 7445#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7446 if (ixgbe_sysfs_init(adapter))
7447 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7448#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7449
9a799d71
AK		 7450 return 0;
7451
7452err_register:
5eba3699 7453 ixgbe_release_hw_control(adapter);
7a921c93 7454 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7455err_sw_init:
99d74487 7456 ixgbe_disable_sriov(adapter);
7086400d 7457 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7458 iounmap(hw->hw_addr);
7459err_ioremap:
7460 free_netdev(netdev);
7461err_alloc_etherdev:
e8e9f696
JP		 7462 pci_release_selected_regions(pdev,
7463 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7464err_pci_reg:
7465err_dma:
7466 pci_disable_device(pdev);
7467 return err;
7468}
7469
7470/**
7471 * ixgbe_remove - Device Removal Routine
7472 * @pdev: PCI device information struct
7473 *
7474 * ixgbe_remove is called by the PCI subsystem to alert the driver
7475 * that it should release a PCI device. The could be caused by a
7476 * Hot-Plug event, or because the driver is going to be removed from
7477 * memory.
7478 **/
7479static void __devexit ixgbe_remove(struct pci_dev *pdev)
7480{
c60fbb00
AD		 7481 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7482 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7483
7484 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7485 cancel_work_sync(&adapter->service_task);
9a799d71 7486
3a6a4eda
JK		 7487#ifdef CONFIG_IXGBE_PTP
7488 ixgbe_ptp_stop(adapter);
7489#endif
7490
5dd2d332 7491#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7492 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7493 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7494 dca_remove_requester(&pdev->dev);
7495 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7496 }
7497
7498#endif
1210982b 7499#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7500 ixgbe_sysfs_exit(adapter);
1210982b 7501#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7502
0365e6e4
PW		 7503 /* remove the added san mac */
7504 ixgbe_del_sanmac_netdev(netdev);
7505
c4900be0
DS		 7506 if (netdev->reg_state == NETREG_REGISTERED)
7507 unregister_netdev(netdev);
9a799d71 7508
9297127b 7509 ixgbe_disable_sriov(adapter);
1cdd1ec8 7510
7a921c93 7511 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7512
021230d4 7513 ixgbe_release_hw_control(adapter);
9a799d71 7514
2b1588c3
AD		 7515#ifdef CONFIG_DCB
7516 kfree(adapter->ixgbe_ieee_pfc);
7517 kfree(adapter->ixgbe_ieee_ets);
7518
7519#endif
9a799d71 7520 iounmap(adapter->hw.hw_addr);
9ce77666 7521 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7522 IORESOURCE_MEM));
9a799d71 7523
849c4542 7524 e_dev_info("complete\n");
021230d4 7525
9a799d71
AK		 7526 free_netdev(netdev);
7527
19d5afd4 7528 pci_disable_pcie_error_reporting(pdev);
6fabd715 7529
9a799d71
AK		 7530 pci_disable_device(pdev);
7531}
7532
7533/**
7534 * ixgbe_io_error_detected - called when PCI error is detected
7535 * @pdev: Pointer to PCI device
7536 * @state: The current pci connection state
7537 *
7538 * This function is called after a PCI bus error affecting
7539 * this device has been detected.
7540 */
7541static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7542 pci_channel_state_t state)
9a799d71 7543{
c60fbb00
AD		 7544 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7545 struct net_device *netdev = adapter->netdev;
9a799d71 7546
83c61fa9
GR		 7547#ifdef CONFIG_PCI_IOV
7548 struct pci_dev *bdev, *vfdev;
7549 u32 dw0, dw1, dw2, dw3;
7550 int vf, pos;
7551 u16 req_id, pf_func;
7552
7553 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7554 adapter->num_vfs == 0)
7555 goto skip_bad_vf_detection;
7556
7557 bdev = pdev->bus->self;
7558 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7559 bdev = bdev->bus->self;
7560
7561 if (!bdev)
7562 goto skip_bad_vf_detection;
7563
7564 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7565 if (!pos)
7566 goto skip_bad_vf_detection;
7567
7568 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7569 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7570 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7571 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7572
7573 req_id = dw1 >> 16;
7574 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7575 if (!(req_id & 0x0080))
7576 goto skip_bad_vf_detection;
7577
7578 pf_func = req_id & 0x01;
7579 if ((pf_func & 1) == (pdev->devfn & 1)) {
7580 unsigned int device_id;
7581
7582 vf = (req_id & 0x7F) >> 1;
7583 e_dev_err("VF %d has caused a PCIe error\n", vf);
7584 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7585 "%8.8x\tdw3: %8.8x\n",
7586 dw0, dw1, dw2, dw3);
7587 switch (adapter->hw.mac.type) {
7588 case ixgbe_mac_82599EB:
7589 device_id = IXGBE_82599_VF_DEVICE_ID;
7590 break;
7591 case ixgbe_mac_X540:
7592 device_id = IXGBE_X540_VF_DEVICE_ID;
7593 break;
7594 default:
7595 device_id = 0;
7596 break;
7597 }
7598
7599 /* Find the pci device of the offending VF */
36e90319 7600 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7601 while (vfdev) {
7602 if (vfdev->devfn == (req_id & 0xFF))
7603 break;
36e90319 7604 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7605 device_id, vfdev);
7606 }
7607 /*
7608 * There's a slim chance the VF could have been hot plugged,
7609 * so if it is no longer present we don't need to issue the
7610 * VFLR. Just clean up the AER in that case.
7611 */
7612 if (vfdev) {
7613 e_dev_err("Issuing VFLR to VF %d\n", vf);
7614 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7615 }
7616
7617 pci_cleanup_aer_uncorrect_error_status(pdev);
7618 }
7619
7620 /*
7621 * Even though the error may have occurred on the other port
7622 * we still need to increment the vf error reference count for
7623 * both ports because the I/O resume function will be called
7624 * for both of them.
7625 */
7626 adapter->vferr_refcount++;
7627
7628 return PCI_ERS_RESULT_RECOVERED;
7629
7630skip_bad_vf_detection:
7631#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7632 netif_device_detach(netdev);
7633
3044b8d1
BL		 7634 if (state == pci_channel_io_perm_failure)
7635 return PCI_ERS_RESULT_DISCONNECT;
7636
9a799d71
AK		 7637 if (netif_running(netdev))
7638 ixgbe_down(adapter);
7639 pci_disable_device(pdev);
7640
b4617240 7641 /* Request a slot reset. */
9a799d71
AK		 7642 return PCI_ERS_RESULT_NEED_RESET;
7643}
7644
7645/**
7646 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7647 * @pdev: Pointer to PCI device
7648 *
7649 * Restart the card from scratch, as if from a cold-boot.
7650 */
7651static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7652{
c60fbb00 7653 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7654 pci_ers_result_t result;
7655 int err;
9a799d71 7656
9ce77666 7657 if (pci_enable_device_mem(pdev)) {
396e799c 7658 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7659 result = PCI_ERS_RESULT_DISCONNECT;
7660 } else {
7661 pci_set_master(pdev);
7662 pci_restore_state(pdev);
c0e1f68b 7663 pci_save_state(pdev);
9a799d71 7664
dd4d8ca6 7665 pci_wake_from_d3(pdev, false);
9a799d71 7666
6fabd715 7667 ixgbe_reset(adapter);
88512539 7668 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7669 result = PCI_ERS_RESULT_RECOVERED;
7670 }
7671
7672 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7673 if (err) {
849c4542
ET		 7674 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7675 "failed 0x%0x\n", err);
6fabd715
PWJ		 7676 /* non-fatal, continue */
7677 }
9a799d71 7678
6fabd715 7679 return result;
9a799d71
AK		 7680}
7681
7682/**
7683 * ixgbe_io_resume - called when traffic can start flowing again.
7684 * @pdev: Pointer to PCI device
7685 *
7686 * This callback is called when the error recovery driver tells us that
7687 * its OK to resume normal operation.
7688 */
7689static void ixgbe_io_resume(struct pci_dev *pdev)
7690{
c60fbb00
AD		 7691 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7692 struct net_device *netdev = adapter->netdev;
9a799d71 7693
83c61fa9
GR		 7694#ifdef CONFIG_PCI_IOV
7695 if (adapter->vferr_refcount) {
7696 e_info(drv, "Resuming after VF err\n");
7697 adapter->vferr_refcount--;
7698 return;
7699 }
7700
7701#endif
c7ccde0f
AD		 7702 if (netif_running(netdev))
7703 ixgbe_up(adapter);
9a799d71
AK		 7704
7705 netif_device_attach(netdev);
9a799d71
AK		 7706}
7707
7708static struct pci_error_handlers ixgbe_err_handler = {
7709 .error_detected = ixgbe_io_error_detected,
7710 .slot_reset = ixgbe_io_slot_reset,
7711 .resume = ixgbe_io_resume,
7712};
7713
7714static struct pci_driver ixgbe_driver = {
7715 .name = ixgbe_driver_name,
7716 .id_table = ixgbe_pci_tbl,
7717 .probe = ixgbe_probe,
7718 .remove = __devexit_p(ixgbe_remove),
7719#ifdef CONFIG_PM
7720 .suspend = ixgbe_suspend,
7721 .resume = ixgbe_resume,
7722#endif
7723 .shutdown = ixgbe_shutdown,
7724 .err_handler = &ixgbe_err_handler
7725};
7726
7727/**
7728 * ixgbe_init_module - Driver Registration Routine
7729 *
7730 * ixgbe_init_module is the first routine called when the driver is
7731 * loaded. All it does is register with the PCI subsystem.
7732 **/
7733static int __init ixgbe_init_module(void)
7734{
7735 int ret;
c7689578 7736 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7737 pr_info("%s\n", ixgbe_copyright);
9a799d71 7738
5dd2d332 7739#ifdef CONFIG_IXGBE_DCA
bd0362dd 7740 dca_register_notify(&dca_notifier);
bd0362dd 7741#endif
5dd2d332 7742
9a799d71
AK		 7743 ret = pci_register_driver(&ixgbe_driver);
7744 return ret;
7745}
b4617240 7746
9a799d71
AK		 7747module_init(ixgbe_init_module);
7748
7749/**
7750 * ixgbe_exit_module - Driver Exit Cleanup Routine
7751 *
7752 * ixgbe_exit_module is called just before the driver is removed
7753 * from memory.
7754 **/
7755static void __exit ixgbe_exit_module(void)
7756{
5dd2d332 7757#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7758 dca_unregister_notify(&dca_notifier);
7759#endif
9a799d71 7760 pci_unregister_driver(&ixgbe_driver);
1a51502b 7761 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7762}
bd0362dd 7763
5dd2d332 7764#ifdef CONFIG_IXGBE_DCA
bd0362dd 7765static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7766 void *p)
bd0362dd
JC		 7767{
7768 int ret_val;
7769
7770 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7771 __ixgbe_notify_dca);
bd0362dd
JC		 7772
7773 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7774}
b453368d 7775
5dd2d332 7776#endif /* CONFIG_IXGBE_DCA */
849c4542 7777
9a799d71
AK		 7778module_exit(ixgbe_exit_module);
7779
7780/* ixgbe_main.c */
Linux kernel - Deliverables
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