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igb: use new eth_get_headlen interface
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/ethtool.h>
01789349 46#include <linux/if.h>
9a799d71 47#include <linux/if_vlan.h>
2a47fa45 48#include <linux/if_macvlan.h>
815cccbf 49#include <linux/if_bridge.h>
70c71606 50#include <linux/prefetch.h>
eacd73f7 51#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 52
53#include "ixgbe.h"
54#include "ixgbe_common.h"
ee5f784a 55#include "ixgbe_dcb_82599.h"
1cdd1ec8 56#include "ixgbe_sriov.h"
9a799d71
AK		 57
58char ixgbe_driver_name[] = "ixgbe";
9c8eb720 59static const char ixgbe_driver_string[] =
e8e9f696 60 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 61#ifdef IXGBE_FCOE
ea81875a
NP		 62char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 64#else
65static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67#endif
f341c4e0 68#define DRV_VERSION "3.19.1-k"
9c8eb720 69const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 70static const char ixgbe_copyright[] =
0391bbe3 71 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 72
73static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 74 [board_82598] = &ixgbe_82598_info,
e8e26350 75 [board_82599] = &ixgbe_82599_info,
fe15e8e1 76 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 77};
78
79/* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
9baa3c34 87static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 118 /* required last entry */
119 {0, }
120};
121MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
5dd2d332 123#ifdef CONFIG_IXGBE_DCA
bd0362dd 124static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 125 void *p);
bd0362dd
JC		 126static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130};
131#endif
132
1cdd1ec8
GR		 133#ifdef CONFIG_PCI_IOV
134static unsigned int max_vfs;
135module_param(max_vfs, uint, 0);
e8e9f696 136MODULE_PARM_DESC(max_vfs,
170e8543 137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 138#endif /* CONFIG_PCI_IOV */
139
8ef78adc
PWJ		 140static unsigned int allow_unsupported_sfp;
141module_param(allow_unsupported_sfp, uint, 0);
142MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
b3f4d599 145#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146static int debug = -1;
147module_param(debug, int, 0);
148MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
9a799d71
AK		 150MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
14438464
MR		 155static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
b8e82001
JK		 157static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159{
b8e82001
JK		 160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
c0798edf 171 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 172 return -1;
173
c0798edf 174 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
b8e82001
JK		 178 return 0;
179}
180
181static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182{
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202}
203
e027d1ae
JK		 204/**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214{
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 218 return true;
219 default:
220 return false;
221 }
222}
223
224static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226{
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
9f0a433c 255 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 273 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282}
283
7086400d
AD		 284static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285{
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290}
291
2a1a091c
MR		 292static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293{
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
58cf663f
MR		 300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 302}
303
f8e2472f 304static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 305{
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321}
322
f8e2472f
MR		 323/**
324 * ixgbe_read_reg - Read from device register
325 * @hw: hw specific details
326 * @reg: offset of register to read
327 *
328 * Returns : value read or IXGBE_FAILED_READ_REG if removed
329 *
330 * This function is used to read device registers. It checks for device
331 * removal by confirming any read that returns all ones by checking the
332 * status register value for all ones. This function avoids reading from
333 * the hardware if a removal was previously detected in which case it
334 * returns IXGBE_FAILED_READ_REG (all ones).
335 */
336u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337{
338 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 u32 value;
340
341 if (ixgbe_removed(reg_addr))
342 return IXGBE_FAILED_READ_REG;
343 value = readl(reg_addr + reg);
344 if (unlikely(value == IXGBE_FAILED_READ_REG))
345 ixgbe_check_remove(hw, reg);
346 return value;
347}
348
14438464
MR		 349static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350{
351 u16 value;
352
353 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 ixgbe_remove_adapter(hw);
356 return true;
357 }
358 return false;
359}
360
361u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362{
363 struct ixgbe_adapter *adapter = hw->back;
364 u16 value;
365
366 if (ixgbe_removed(hw->hw_addr))
367 return IXGBE_FAILED_READ_CFG_WORD;
368 pci_read_config_word(adapter->pdev, reg, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 ixgbe_check_cfg_remove(hw, adapter->pdev))
371 return IXGBE_FAILED_READ_CFG_WORD;
372 return value;
373}
374
375#ifdef CONFIG_PCI_IOV
376static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377{
378 struct ixgbe_adapter *adapter = hw->back;
379 u32 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_DWORD;
383 pci_read_config_dword(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_DWORD;
387 return value;
388}
389#endif /* CONFIG_PCI_IOV */
390
ed19231c
JK		 391void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392{
393 struct ixgbe_adapter *adapter = hw->back;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return;
397 pci_write_config_word(adapter->pdev, reg, value);
398}
399
7086400d
AD		 400static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401{
402 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403
52f33af8 404 /* flush memory to make sure state is correct before next watchdog */
4e857c58 405 smp_mb__before_atomic();
7086400d
AD		 406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407}
408
dcd79aeb
TI		 409struct ixgbe_reg_info {
410 u32 ofs;
411 char *name;
412};
413
414static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415
416 /* General Registers */
417 {IXGBE_CTRL, "CTRL"},
418 {IXGBE_STATUS, "STATUS"},
419 {IXGBE_CTRL_EXT, "CTRL_EXT"},
420
421 /* Interrupt Registers */
422 {IXGBE_EICR, "EICR"},
423
424 /* RX Registers */
425 {IXGBE_SRRCTL(0), "SRRCTL"},
426 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 {IXGBE_RDLEN(0), "RDLEN"},
428 {IXGBE_RDH(0), "RDH"},
429 {IXGBE_RDT(0), "RDT"},
430 {IXGBE_RXDCTL(0), "RXDCTL"},
431 {IXGBE_RDBAL(0), "RDBAL"},
432 {IXGBE_RDBAH(0), "RDBAH"},
433
434 /* TX Registers */
435 {IXGBE_TDBAL(0), "TDBAL"},
436 {IXGBE_TDBAH(0), "TDBAH"},
437 {IXGBE_TDLEN(0), "TDLEN"},
438 {IXGBE_TDH(0), "TDH"},
439 {IXGBE_TDT(0), "TDT"},
440 {IXGBE_TXDCTL(0), "TXDCTL"},
441
442 /* List Terminator */
443 {}
444};
445
446
447/*
448 * ixgbe_regdump - register printout routine
449 */
450static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451{
452 int i = 0, j = 0;
453 char rname[16];
454 u32 regs[64];
455
456 switch (reginfo->ofs) {
457 case IXGBE_SRRCTL(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 break;
461 case IXGBE_DCA_RXCTRL(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 break;
465 case IXGBE_RDLEN(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 break;
469 case IXGBE_RDH(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 break;
473 case IXGBE_RDT(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 break;
477 case IXGBE_RXDCTL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 break;
481 case IXGBE_RDBAL(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 break;
485 case IXGBE_RDBAH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 break;
489 case IXGBE_TDBAL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 break;
493 case IXGBE_TDBAH(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 break;
497 case IXGBE_TDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 break;
501 case IXGBE_TDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 break;
505 case IXGBE_TDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 break;
509 case IXGBE_TXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 break;
513 default:
c7689578 514 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 515 IXGBE_READ_REG(hw, reginfo->ofs));
516 return;
517 }
518
519 for (i = 0; i < 8; i++) {
520 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 521 pr_err("%-15s", rname);
dcd79aeb 522 for (j = 0; j < 8; j++)
c7689578
JP		 523 pr_cont(" %08x", regs[i*8+j]);
524 pr_cont("\n");
dcd79aeb
TI		 525 }
526
527}
528
529/*
530 * ixgbe_dump - Print registers, tx-rings and rx-rings
531 */
532static void ixgbe_dump(struct ixgbe_adapter *adapter)
533{
534 struct net_device *netdev = adapter->netdev;
535 struct ixgbe_hw *hw = &adapter->hw;
536 struct ixgbe_reg_info *reginfo;
537 int n = 0;
538 struct ixgbe_ring *tx_ring;
729739b7 539 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 540 union ixgbe_adv_tx_desc *tx_desc;
541 struct my_u0 { u64 a; u64 b; } *u0;
542 struct ixgbe_ring *rx_ring;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *rx_buffer_info;
545 u32 staterr;
546 int i = 0;
547
548 if (!netif_msg_hw(adapter))
549 return;
550
551 /* Print netdevice Info */
552 if (netdev) {
553 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 554 pr_info("Device Name state "
dcd79aeb 555 "trans_start last_rx\n");
c7689578
JP		 556 pr_info("%-15s %016lX %016lX %016lX\n",
557 netdev->name,
558 netdev->state,
559 netdev->trans_start,
560 netdev->last_rx);
dcd79aeb
TI		 561 }
562
563 /* Print Registers */
564 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 565 pr_info(" Register Name Value\n");
dcd79aeb
TI		 566 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 reginfo->name; reginfo++) {
568 ixgbe_regdump(hw, reginfo);
569 }
570
571 /* Print TX Ring Summary */
572 if (!netdev || !netif_running(netdev))
e90dd264 573 return;
dcd79aeb
TI		 574
575 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 576 pr_info(" %s %s %s %s\n",
577 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
578 "leng", "ntw", "timestamp");
dcd79aeb
TI		 579 for (n = 0; n < adapter->num_tx_queues; n++) {
580 tx_ring = adapter->tx_ring[n];
729739b7 581 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 582 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 583 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 584 (u64)dma_unmap_addr(tx_buffer, dma),
585 dma_unmap_len(tx_buffer, len),
586 tx_buffer->next_to_watch,
587 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 588 }
589
590 /* Print TX Rings */
591 if (!netif_msg_tx_done(adapter))
592 goto rx_ring_summary;
593
594 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595
596 /* Transmit Descriptor Formats
597 *
39ac868a 598 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 599 * +--------------------------------------------------------------+
600 * 0 | Buffer Address [63:0] |
601 * +--------------------------------------------------------------+
39ac868a 602 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 603 * +--------------------------------------------------------------+
604 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 605 *
606 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 * +--------------------------------------------------------------+
608 * 0 | RSV [63:0] |
609 * +--------------------------------------------------------------+
610 * 8 | RSV | STA | NXTSEQ |
611 * +--------------------------------------------------------------+
612 * 63 36 35 32 31 0
613 *
614 * 82599+ Advanced Transmit Descriptor
615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
618 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
621 *
622 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | RSV |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
dcd79aeb
TI		 629 */
630
631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
c7689578
JP		 633 pr_info("------------------------------------\n");
634 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 pr_info("------------------------------------\n");
8ad88e37
JH		 636 pr_info("%s%s %s %s %s %s\n",
637 "T [desc] [address 63:0 ] ",
638 "[PlPOIdStDDt Ln] [bi->dma ] ",
639 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 640
641 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 642 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 643 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 644 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 645 if (dma_unmap_len(tx_buffer, len) > 0) {
646 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
647 i,
648 le64_to_cpu(u0->a),
649 le64_to_cpu(u0->b),
650 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 651 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 652 tx_buffer->next_to_watch,
653 (u64)tx_buffer->time_stamp,
654 tx_buffer->skb);
655 if (i == tx_ring->next_to_use &&
656 i == tx_ring->next_to_clean)
657 pr_cont(" NTC/U\n");
658 else if (i == tx_ring->next_to_use)
659 pr_cont(" NTU\n");
660 else if (i == tx_ring->next_to_clean)
661 pr_cont(" NTC\n");
662 else
663 pr_cont("\n");
664
665 if (netif_msg_pktdata(adapter) &&
666 tx_buffer->skb)
667 print_hex_dump(KERN_INFO, "",
668 DUMP_PREFIX_ADDRESS, 16, 1,
669 tx_buffer->skb->data,
670 dma_unmap_len(tx_buffer, len),
671 true);
672 }
dcd79aeb
TI		 673 }
674 }
675
676 /* Print RX Rings Summary */
677rx_ring_summary:
678 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 679 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 680 for (n = 0; n < adapter->num_rx_queues; n++) {
681 rx_ring = adapter->rx_ring[n];
c7689578
JP		 682 pr_info("%5d %5X %5X\n",
683 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 684 }
685
686 /* Print RX Rings */
687 if (!netif_msg_rx_status(adapter))
e90dd264 688 return;
dcd79aeb
TI		 689
690 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691
39ac868a
JH		 692 /* Receive Descriptor Formats
693 *
694 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 695 * 63 1 0
696 * +-----------------------------------------------------+
697 * 0 | Packet Buffer Address [63:1] |A0/NSE|
698 * +----------------------------------------------+------+
699 * 8 | Header Buffer Address [63:1] | DD |
700 * +-----------------------------------------------------+
701 *
702 *
39ac868a 703 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 704 *
705 * 63 48 47 32 31 30 21 20 16 15 4 3 0
706 * +------------------------------------------------------+
39ac868a
JH		 707 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
708 * | Packet | IP | | | | Type | Type |
709 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 710 * +------------------------------------------------------+
711 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 * +------------------------------------------------------+
713 * 63 48 47 32 31 20 19 0
39ac868a
JH		 714 *
715 * 82599+ Advanced Receive Descriptor (Read) Format
716 * 63 1 0
717 * +-----------------------------------------------------+
718 * 0 | Packet Buffer Address [63:1] |A0/NSE|
719 * +----------------------------------------------+------+
720 * 8 | Header Buffer Address [63:1] | DD |
721 * +-----------------------------------------------------+
722 *
723 *
724 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 *
726 * 63 48 47 32 31 30 21 20 17 16 4 3 0
727 * +------------------------------------------------------+
728 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
729 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
730 * |/ Flow Dir Flt ID | | | | | |
731 * +------------------------------------------------------+
732 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 * +------------------------------------------------------+
734 * 63 48 47 32 31 20 19 0
dcd79aeb 735 */
39ac868a 736
dcd79aeb
TI		 737 for (n = 0; n < adapter->num_rx_queues; n++) {
738 rx_ring = adapter->rx_ring[n];
c7689578
JP		 739 pr_info("------------------------------------\n");
740 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 pr_info("------------------------------------\n");
8ad88e37
JH		 742 pr_info("%s%s%s",
743 "R [desc] [ PktBuf A0] ",
744 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 745 "<-- Adv Rx Read format\n");
8ad88e37
JH		 746 pr_info("%s%s%s",
747 "RWB[desc] [PcsmIpSHl PtRs] ",
748 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 749 "<-- Adv Rx Write-Back format\n");
750
751 for (i = 0; i < rx_ring->count; i++) {
752 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 753 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 754 u0 = (struct my_u0 *)rx_desc;
755 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 if (staterr & IXGBE_RXD_STAT_DD) {
757 /* Descriptor Done */
c7689578 758 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 759 "%016llX ---------------- %p", i,
760 le64_to_cpu(u0->a),
761 le64_to_cpu(u0->b),
762 rx_buffer_info->skb);
763 } else {
c7689578 764 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 765 "%016llX %016llX %p", i,
766 le64_to_cpu(u0->a),
767 le64_to_cpu(u0->b),
768 (u64)rx_buffer_info->dma,
769 rx_buffer_info->skb);
770
9c50c035
ET		 771 if (netif_msg_pktdata(adapter) &&
772 rx_buffer_info->dma) {
dcd79aeb
TI		 773 print_hex_dump(KERN_INFO, "",
774 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 775 page_address(rx_buffer_info->page) +
776 rx_buffer_info->page_offset,
f800326d 777 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 778 }
779 }
780
781 if (i == rx_ring->next_to_use)
c7689578 782 pr_cont(" NTU\n");
dcd79aeb 783 else if (i == rx_ring->next_to_clean)
c7689578 784 pr_cont(" NTC\n");
dcd79aeb 785 else
c7689578 786 pr_cont("\n");
dcd79aeb
TI		 787
788 }
789 }
dcd79aeb
TI		 790}
791
5eba3699
AV		 792static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
793{
794 u32 ctrl_ext;
795
796 /* Let firmware take over control of h/w */
797 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
798 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 799 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 800}
801
802static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
803{
804 u32 ctrl_ext;
805
806 /* Let firmware know the driver has taken over */
807 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 809 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 810}
9a799d71 811
49ce9c2c 812/**
e8e26350
PW		 813 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
814 * @adapter: pointer to adapter struct
815 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
816 * @queue: queue to map the corresponding interrupt to
817 * @msix_vector: the vector to map to the corresponding queue
818 *
819 */
820static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 821 u8 queue, u8 msix_vector)
9a799d71
AK		 822{
823 u32 ivar, index;
e8e26350
PW		 824 struct ixgbe_hw *hw = &adapter->hw;
825 switch (hw->mac.type) {
826 case ixgbe_mac_82598EB:
827 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
828 if (direction == -1)
829 direction = 0;
830 index = (((direction * 64) + queue) >> 2) & 0x1F;
831 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
832 ivar &= ~(0xFF << (8 * (queue & 0x3)));
833 ivar |= (msix_vector << (8 * (queue & 0x3)));
834 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
835 break;
836 case ixgbe_mac_82599EB:
b93a2226 837 case ixgbe_mac_X540:
e8e26350
PW		 838 if (direction == -1) {
839 /* other causes */
840 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
841 index = ((queue & 1) * 8);
842 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
843 ivar &= ~(0xFF << index);
844 ivar |= (msix_vector << index);
845 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
846 break;
847 } else {
848 /* tx or rx causes */
849 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
850 index = ((16 * (queue & 1)) + (8 * direction));
851 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
852 ivar &= ~(0xFF << index);
853 ivar |= (msix_vector << index);
854 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
855 break;
856 }
857 default:
858 break;
859 }
9a799d71
AK		 860}
861
fe49f04a 862static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 863 u64 qmask)
fe49f04a
AD		 864{
865 u32 mask;
866
bd508178
AD		 867 switch (adapter->hw.mac.type) {
868 case ixgbe_mac_82598EB:
fe49f04a
AD		 869 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
870 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 871 break;
872 case ixgbe_mac_82599EB:
b93a2226 873 case ixgbe_mac_X540:
fe49f04a
AD		 874 mask = (qmask & 0xFFFFFFFF);
875 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
876 mask = (qmask >> 32);
877 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 878 break;
879 default:
880 break;
fe49f04a
AD		 881 }
882}
883
729739b7
AD		 884void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
885 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 886{
729739b7
AD		 887 if (tx_buffer->skb) {
888 dev_kfree_skb_any(tx_buffer->skb);
889 if (dma_unmap_len(tx_buffer, len))
d3d00239 890 dma_unmap_single(ring->dev,
729739b7
AD		 891 dma_unmap_addr(tx_buffer, dma),
892 dma_unmap_len(tx_buffer, len),
893 DMA_TO_DEVICE);
894 } else if (dma_unmap_len(tx_buffer, len)) {
895 dma_unmap_page(ring->dev,
896 dma_unmap_addr(tx_buffer, dma),
897 dma_unmap_len(tx_buffer, len),
898 DMA_TO_DEVICE);
e5a43549 899 }
729739b7
AD		 900 tx_buffer->next_to_watch = NULL;
901 tx_buffer->skb = NULL;
902 dma_unmap_len_set(tx_buffer, len, 0);
903 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 904}
905
943561d3 906static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 907{
908 struct ixgbe_hw *hw = &adapter->hw;
909 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 910 int i;
943561d3 911 u32 data;
c84d324c 912
943561d3
AD		 913 if ((hw->fc.current_mode != ixgbe_fc_full) &&
914 (hw->fc.current_mode != ixgbe_fc_rx_pause))
915 return;
c84d324c 916
943561d3
AD		 917 switch (hw->mac.type) {
918 case ixgbe_mac_82598EB:
919 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
920 break;
921 default:
922 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
923 }
924 hwstats->lxoffrxc += data;
c84d324c 925
943561d3
AD		 926 /* refill credits (no tx hang) if we received xoff */
927 if (!data)
c84d324c 928 return;
943561d3
AD		 929
930 for (i = 0; i < adapter->num_tx_queues; i++)
931 clear_bit(__IXGBE_HANG_CHECK_ARMED,
932 &adapter->tx_ring[i]->state);
933}
934
935static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
936{
937 struct ixgbe_hw *hw = &adapter->hw;
938 struct ixgbe_hw_stats *hwstats = &adapter->stats;
939 u32 xoff[8] = {0};
2afaa00d 940 u8 tc;
943561d3
AD		 941 int i;
942 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
943
944 if (adapter->ixgbe_ieee_pfc)
945 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
946
947 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
948 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 949 return;
943561d3 950 }
c84d324c
JF		 951
952 /* update stats for each tc, only valid with PFC enabled */
953 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 954 u32 pxoffrxc;
955
c84d324c
JF		 956 switch (hw->mac.type) {
957 case ixgbe_mac_82598EB:
2afaa00d 958 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 959 break;
c84d324c 960 default:
2afaa00d 961 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 962 }
2afaa00d
PN		 963 hwstats->pxoffrxc[i] += pxoffrxc;
964 /* Get the TC for given UP */
965 tc = netdev_get_prio_tc_map(adapter->netdev, i);
966 xoff[tc] += pxoffrxc;
c84d324c
JF		 967 }
968
969 /* disarm tx queues that have received xoff frames */
970 for (i = 0; i < adapter->num_tx_queues; i++) {
971 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 972
2afaa00d 973 tc = tx_ring->dcb_tc;
c84d324c
JF		 974 if (xoff[tc])
975 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 976 }
26f23d82
YZ		 977}
978
c84d324c 979static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 980{
7d7ce682 981 return ring->stats.packets;
c84d324c
JF		 982}
983
984static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
985{
2a47fa45
JF		 986 struct ixgbe_adapter *adapter;
987 struct ixgbe_hw *hw;
988 u32 head, tail;
989
990 if (ring->l2_accel_priv)
991 adapter = ring->l2_accel_priv->real_adapter;
992 else
993 adapter = netdev_priv(ring->netdev);
e01c31a5 994
2a47fa45
JF		 995 hw = &adapter->hw;
996 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
997 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 998
999 if (head != tail)
1000 return (head < tail) ?
1001 tail - head : (tail + ring->count - head);
1002
1003 return 0;
1004}
1005
1006static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1007{
1008 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1009 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1010 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1011
7d637bcc 1012 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1013
1014 /*
1015 * Check for a hung queue, but be thorough. This verifies
1016 * that a transmit has been completed since the previous
1017 * check AND there is at least one packet pending. The
1018 * ARMED bit is set to indicate a potential hang. The
1019 * bit is cleared if a pause frame is received to remove
1020 * false hang detection due to PFC or 802.3x frames. By
1021 * requiring this to fail twice we avoid races with
1022 * pfc clearing the ARMED bit and conditions where we
1023 * run the check_tx_hang logic with a transmit completion
1024 * pending but without time to complete it yet.
1025 */
e90dd264 1026 if (tx_done_old == tx_done && tx_pending)
c84d324c 1027 /* make sure it is true for two checks in a row */
e90dd264
MR		 1028 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1029 &tx_ring->state);
1030 /* update completed stats and continue */
1031 tx_ring->tx_stats.tx_done_old = tx_done;
1032 /* reset the countdown */
1033 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1034
e90dd264 1035 return false;
9a799d71
AK		 1036}
1037
c83c6cbd
AD		 1038/**
1039 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1040 * @adapter: driver private struct
1041 **/
1042static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1043{
1044
1045 /* Do the reset outside of interrupt context */
1046 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1047 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1048 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1049 ixgbe_service_event_schedule(adapter);
1050 }
1051}
e01c31a5 1052
9a799d71
AK		 1053/**
1054 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1055 * @q_vector: structure containing interrupt and ring information
e01c31a5 1056 * @tx_ring: tx ring to clean
9a799d71 1057 **/
fe49f04a 1058static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1059 struct ixgbe_ring *tx_ring)
9a799d71 1060{
fe49f04a 1061 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1062 struct ixgbe_tx_buffer *tx_buffer;
1063 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1064 unsigned int total_bytes = 0, total_packets = 0;
59224555 1065 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1066 unsigned int i = tx_ring->next_to_clean;
1067
1068 if (test_bit(__IXGBE_DOWN, &adapter->state))
1069 return true;
9a799d71 1070
d3d00239 1071 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1072 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1073 i -= tx_ring->count;
12207e49 1074
729739b7 1075 do {
d3d00239
AD		 1076 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1077
1078 /* if next_to_watch is not set then there is no work pending */
1079 if (!eop_desc)
1080 break;
1081
7f83a9e6 1082 /* prevent any other reads prior to eop_desc */
7e63bf49 1083 read_barrier_depends();
7f83a9e6 1084
d3d00239
AD		 1085 /* if DD is not set pending work has not been completed */
1086 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1087 break;
8ad494b0 1088
d3d00239
AD		 1089 /* clear next_to_watch to prevent false hangs */
1090 tx_buffer->next_to_watch = NULL;
8ad494b0 1091
091a6246
AD		 1092 /* update the statistics for this packet */
1093 total_bytes += tx_buffer->bytecount;
1094 total_packets += tx_buffer->gso_segs;
1095
fd0db0ed
AD		 1096 /* free the skb */
1097 dev_kfree_skb_any(tx_buffer->skb);
1098
729739b7
AD		 1099 /* unmap skb header data */
1100 dma_unmap_single(tx_ring->dev,
1101 dma_unmap_addr(tx_buffer, dma),
1102 dma_unmap_len(tx_buffer, len),
1103 DMA_TO_DEVICE);
1104
fd0db0ed
AD		 1105 /* clear tx_buffer data */
1106 tx_buffer->skb = NULL;
729739b7 1107 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1108
729739b7
AD		 1109 /* unmap remaining buffers */
1110 while (tx_desc != eop_desc) {
d3d00239
AD		 1111 tx_buffer++;
1112 tx_desc++;
8ad494b0 1113 i++;
729739b7
AD		 1114 if (unlikely(!i)) {
1115 i -= tx_ring->count;
d3d00239 1116 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1117 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1118 }
e01c31a5 1119
729739b7
AD		 1120 /* unmap any remaining paged data */
1121 if (dma_unmap_len(tx_buffer, len)) {
1122 dma_unmap_page(tx_ring->dev,
1123 dma_unmap_addr(tx_buffer, dma),
1124 dma_unmap_len(tx_buffer, len),
1125 DMA_TO_DEVICE);
1126 dma_unmap_len_set(tx_buffer, len, 0);
1127 }
1128 }
1129
1130 /* move us one more past the eop_desc for start of next pkt */
1131 tx_buffer++;
1132 tx_desc++;
1133 i++;
1134 if (unlikely(!i)) {
1135 i -= tx_ring->count;
1136 tx_buffer = tx_ring->tx_buffer_info;
1137 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1138 }
1139
1140 /* issue prefetch for next Tx descriptor */
1141 prefetch(tx_desc);
12207e49 1142
729739b7
AD		 1143 /* update budget accounting */
1144 budget--;
1145 } while (likely(budget));
1146
1147 i += tx_ring->count;
9a799d71 1148 tx_ring->next_to_clean = i;
d3d00239 1149 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1150 tx_ring->stats.bytes += total_bytes;
bd198058 1151 tx_ring->stats.packets += total_packets;
d3d00239 1152 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1153 q_vector->tx.total_bytes += total_bytes;
1154 q_vector->tx.total_packets += total_packets;
b953799e 1155
c84d324c
JF		 1156 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1157 /* schedule immediate reset if we believe we hung */
1158 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1159 e_err(drv, "Detected Tx Unit Hang\n"
1160 " Tx Queue <%d>\n"
1161 " TDH, TDT <%x>, <%x>\n"
1162 " next_to_use <%x>\n"
1163 " next_to_clean <%x>\n"
1164 "tx_buffer_info[next_to_clean]\n"
1165 " time_stamp <%lx>\n"
1166 " jiffies <%lx>\n",
1167 tx_ring->queue_index,
1168 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1169 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1170 tx_ring->next_to_use, i,
1171 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1172
1173 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1174
1175 e_info(probe,
1176 "tx hang %d detected on queue %d, resetting adapter\n",
1177 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1178
b953799e 1179 /* schedule immediate reset if we believe we hung */
c83c6cbd 1180 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1181
1182 /* the adapter is about to reset, no point in enabling stuff */
59224555 1183 return true;
b953799e 1184 }
9a799d71 1185
b2d96e0a
AD		 1186 netdev_tx_completed_queue(txring_txq(tx_ring),
1187 total_packets, total_bytes);
1188
e092be60 1189#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1190 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1191 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1192 /* Make sure that anybody stopping the queue after this
1193 * sees the new next_to_clean.
1194 */
1195 smp_mb();
729739b7
AD		 1196 if (__netif_subqueue_stopped(tx_ring->netdev,
1197 tx_ring->queue_index)
1198 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1199 netif_wake_subqueue(tx_ring->netdev,
1200 tx_ring->queue_index);
5b7da515 1201 ++tx_ring->tx_stats.restart_queue;
30eba97a 1202 }
e092be60 1203 }
9a799d71 1204
59224555 1205 return !!budget;
9a799d71
AK		 1206}
1207
5dd2d332 1208#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1209static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1210 struct ixgbe_ring *tx_ring,
33cf09c9 1211 int cpu)
bd0362dd 1212{
33cf09c9 1213 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1214 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1215 u16 reg_offset;
33cf09c9 1216
33cf09c9
AD		 1217 switch (hw->mac.type) {
1218 case ixgbe_mac_82598EB:
bdda1a61 1219 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1220 break;
1221 case ixgbe_mac_82599EB:
b93a2226 1222 case ixgbe_mac_X540:
bdda1a61
AD		 1223 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1224 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1225 break;
1226 default:
bdda1a61
AD		 1227 /* for unknown hardware do not write register */
1228 return;
bd0362dd 1229 }
bdda1a61
AD		 1230
1231 /*
1232 * We can enable relaxed ordering for reads, but not writes when
1233 * DCA is enabled. This is due to a known issue in some chipsets
1234 * which will cause the DCA tag to be cleared.
1235 */
1236 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1237 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1238 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1239
1240 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1241}
1242
bdda1a61
AD		 1243static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1244 struct ixgbe_ring *rx_ring,
33cf09c9 1245 int cpu)
bd0362dd 1246{
33cf09c9 1247 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1248 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1249 u8 reg_idx = rx_ring->reg_idx;
1250
33cf09c9
AD		 1251
1252 switch (hw->mac.type) {
33cf09c9 1253 case ixgbe_mac_82599EB:
b93a2226 1254 case ixgbe_mac_X540:
bdda1a61 1255 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1256 break;
1257 default:
1258 break;
1259 }
bdda1a61
AD		 1260
1261 /*
1262 * We can enable relaxed ordering for reads, but not writes when
1263 * DCA is enabled. This is due to a known issue in some chipsets
1264 * which will cause the DCA tag to be cleared.
1265 */
1266 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1267 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1268
1269 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1270}
1271
1272static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1273{
1274 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1275 struct ixgbe_ring *ring;
bd0362dd 1276 int cpu = get_cpu();
bd0362dd 1277
33cf09c9
AD		 1278 if (q_vector->cpu == cpu)
1279 goto out_no_update;
1280
a557928e 1281 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1282 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1283
a557928e 1284 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1285 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1286
1287 q_vector->cpu = cpu;
1288out_no_update:
bd0362dd
JC		 1289 put_cpu();
1290}
1291
1292static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1293{
1294 int i;
1295
1296 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1297 return;
1298
e35ec126
AD		 1299 /* always use CB2 mode, difference is masked in the CB driver */
1300 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1301
49c7ffbe 1302 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1303 adapter->q_vector[i]->cpu = -1;
1304 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1305 }
1306}
1307
1308static int __ixgbe_notify_dca(struct device *dev, void *data)
1309{
c60fbb00 1310 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1311 unsigned long event = *(unsigned long *)data;
1312
2a72c31e 1313 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1314 return 0;
1315
bd0362dd
JC		 1316 switch (event) {
1317 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1318 /* if we're already enabled, don't do it again */
1319 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1320 break;
652f093f 1321 if (dca_add_requester(dev) == 0) {
96b0e0f6 1322 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1323 ixgbe_setup_dca(adapter);
1324 break;
1325 }
1326 /* Fall Through since DCA is disabled. */
1327 case DCA_PROVIDER_REMOVE:
1328 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1329 dca_remove_requester(dev);
1330 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1332 }
1333 break;
1334 }
1335
652f093f 1336 return 0;
bd0362dd 1337}
67a74ee2 1338
bdda1a61 1339#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1340static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1341 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1342 struct sk_buff *skb)
1343{
8a0da21b 1344 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1345 skb_set_hash(skb,
1346 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1347 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1348}
1349
f800326d 1350#ifdef IXGBE_FCOE
ff886dfc
AD		 1351/**
1352 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1353 * @ring: structure containing ring specific data
ff886dfc
AD		 1354 * @rx_desc: advanced rx descriptor
1355 *
1356 * Returns : true if it is FCoE pkt
1357 */
57efd44c 1358static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1359 union ixgbe_adv_rx_desc *rx_desc)
1360{
1361 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1362
57efd44c 1363 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1364 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1365 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1366 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1367}
1368
f800326d 1369#endif /* IXGBE_FCOE */
e59bd25d
AV		 1370/**
1371 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1372 * @ring: structure containing ring specific data
1373 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1374 * @skb: skb currently being received and modified
1375 **/
8a0da21b 1376static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1377 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1378 struct sk_buff *skb)
9a799d71 1379{
8a0da21b 1380 skb_checksum_none_assert(skb);
9a799d71 1381
712744be 1382 /* Rx csum disabled */
8a0da21b 1383 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1384 return;
e59bd25d
AV		 1385
1386 /* if IP and error */
f56e0cb1
AD		 1387 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1388 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1389 ring->rx_stats.csum_err++;
9a799d71
AK		 1390 return;
1391 }
e59bd25d 1392
f56e0cb1 1393 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1394 return;
1395
f56e0cb1 1396 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1397 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1398
1399 /*
1400 * 82599 errata, UDP frames with a 0 checksum can be marked as
1401 * checksum errors.
1402 */
8a0da21b
AD		 1403 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1404 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1405 return;
1406
8a0da21b 1407 ring->rx_stats.csum_err++;
e59bd25d
AV		 1408 return;
1409 }
1410
9a799d71 1411 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1412 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1413}
1414
84ea2591 1415static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1416{
f56e0cb1 1417 rx_ring->next_to_use = val;
f800326d
AD		 1418
1419 /* update next to alloc since we have filled the ring */
1420 rx_ring->next_to_alloc = val;
e8e26350
PW		 1421 /*
1422 * Force memory writes to complete before letting h/w
1423 * know there are new descriptors to fetch. (Only
1424 * applicable for weak-ordered memory model archs,
1425 * such as IA-64).
1426 */
1427 wmb();
84227bcd 1428 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1429}
1430
f990b79b
AD		 1431static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1432 struct ixgbe_rx_buffer *bi)
1433{
1434 struct page *page = bi->page;
f800326d 1435 dma_addr_t dma = bi->dma;
f990b79b 1436
f800326d
AD		 1437 /* since we are recycling buffers we should seldom need to alloc */
1438 if (likely(dma))
f990b79b
AD		 1439 return true;
1440
f800326d
AD		 1441 /* alloc new page for storage */
1442 if (likely(!page)) {
0614002b
MG		 1443 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1444 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1445 if (unlikely(!page)) {
1446 rx_ring->rx_stats.alloc_rx_page_failed++;
1447 return false;
1448 }
f800326d 1449 bi->page = page;
f990b79b
AD		 1450 }
1451
f800326d
AD		 1452 /* map page for use */
1453 dma = dma_map_page(rx_ring->dev, page, 0,
1454 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1455
1456 /*
1457 * if mapping failed free memory back to system since
1458 * there isn't much point in holding memory we can't use
1459 */
1460 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1461 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1462 bi->page = NULL;
f990b79b 1463
f990b79b
AD		 1464 rx_ring->rx_stats.alloc_rx_page_failed++;
1465 return false;
1466 }
1467
f800326d 1468 bi->dma = dma;
afaa9459 1469 bi->page_offset = 0;
f800326d 1470
f990b79b
AD		 1471 return true;
1472}
1473
9a799d71 1474/**
f990b79b 1475 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1476 * @rx_ring: ring to place buffers on
1477 * @cleaned_count: number of buffers to replace
9a799d71 1478 **/
fc77dc3c 1479void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1480{
9a799d71 1481 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1482 struct ixgbe_rx_buffer *bi;
d5f398ed 1483 u16 i = rx_ring->next_to_use;
9a799d71 1484
f800326d
AD		 1485 /* nothing to do */
1486 if (!cleaned_count)
fc77dc3c
AD		 1487 return;
1488
e4f74028 1489 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1490 bi = &rx_ring->rx_buffer_info[i];
1491 i -= rx_ring->count;
9a799d71 1492
f800326d
AD		 1493 do {
1494 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1495 break;
d5f398ed 1496
f800326d
AD		 1497 /*
1498 * Refresh the desc even if buffer_addrs didn't change
1499 * because each write-back erases this info.
1500 */
1501 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1502
f990b79b
AD		 1503 rx_desc++;
1504 bi++;
9a799d71 1505 i++;
f990b79b 1506 if (unlikely(!i)) {
e4f74028 1507 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1508 bi = rx_ring->rx_buffer_info;
1509 i -= rx_ring->count;
1510 }
1511
1512 /* clear the hdr_addr for the next_to_use descriptor */
1513 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1514
1515 cleaned_count--;
1516 } while (cleaned_count);
7c6e0a43 1517
f990b79b
AD		 1518 i += rx_ring->count;
1519
f56e0cb1 1520 if (rx_ring->next_to_use != i)
84ea2591 1521 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1522}
1523
1d2024f6
AD		 1524/**
1525 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1526 * @data: pointer to the start of the headers
1527 * @max_len: total length of section to find headers in
1528 *
1529 * This function is meant to determine the length of headers that will
1530 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1531 * motivation of doing this is to only perform one pull for IPv4 TCP
1532 * packets so that we can do basic things like calculating the gso_size
1533 * based on the average data per packet.
1534 **/
1535static unsigned int ixgbe_get_headlen(unsigned char *data,
1536 unsigned int max_len)
1537{
1538 union {
1539 unsigned char *network;
1540 /* l2 headers */
1541 struct ethhdr *eth;
1542 struct vlan_hdr *vlan;
1543 /* l3 headers */
1544 struct iphdr *ipv4;
a048b40e 1545 struct ipv6hdr *ipv6;
1d2024f6
AD		 1546 } hdr;
1547 __be16 protocol;
1548 u8 nexthdr = 0; /* default to not TCP */
1549 u8 hlen;
1550
1551 /* this should never happen, but better safe than sorry */
1552 if (max_len < ETH_HLEN)
1553 return max_len;
1554
1555 /* initialize network frame pointer */
1556 hdr.network = data;
1557
1558 /* set first protocol and move network header forward */
1559 protocol = hdr.eth->h_proto;
1560 hdr.network += ETH_HLEN;
1561
1562 /* handle any vlan tag if present */
a1108ffd 1563 if (protocol == htons(ETH_P_8021Q)) {
1d2024f6
AD		 1564 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1565 return max_len;
1566
1567 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1568 hdr.network += VLAN_HLEN;
1569 }
1570
1571 /* handle L3 protocols */
a1108ffd 1572 if (protocol == htons(ETH_P_IP)) {
1d2024f6
AD		 1573 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1574 return max_len;
1575
1576 /* access ihl as a u8 to avoid unaligned access on ia64 */
1577 hlen = (hdr.network[0] & 0x0F) << 2;
1578
1579 /* verify hlen meets minimum size requirements */
1580 if (hlen < sizeof(struct iphdr))
1581 return hdr.network - data;
1582
ed83da12 1583 /* record next protocol if header is present */
20967f42 1584 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1585 nexthdr = hdr.ipv4->protocol;
a1108ffd 1586 } else if (protocol == htons(ETH_P_IPV6)) {
a048b40e
AD		 1587 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1588 return max_len;
1589
1590 /* record next protocol */
1591 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1592 hlen = sizeof(struct ipv6hdr);
f800326d 1593#ifdef IXGBE_FCOE
a1108ffd 1594 } else if (protocol == htons(ETH_P_FCOE)) {
1d2024f6
AD		 1595 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1596 return max_len;
ed83da12 1597 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1598#endif
1599 } else {
1600 return hdr.network - data;
1601 }
1602
ed83da12
AD		 1603 /* relocate pointer to start of L4 header */
1604 hdr.network += hlen;
1605
a048b40e 1606 /* finally sort out TCP/UDP */
1d2024f6
AD		 1607 if (nexthdr == IPPROTO_TCP) {
1608 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1609 return max_len;
1610
1611 /* access doff as a u8 to avoid unaligned access on ia64 */
1612 hlen = (hdr.network[12] & 0xF0) >> 2;
1613
1614 /* verify hlen meets minimum size requirements */
1615 if (hlen < sizeof(struct tcphdr))
1616 return hdr.network - data;
1617
1618 hdr.network += hlen;
a048b40e
AD		 1619 } else if (nexthdr == IPPROTO_UDP) {
1620 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1621 return max_len;
1622
1623 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1624 }
1625
1626 /*
1627 * If everything has gone correctly hdr.network should be the
1628 * data section of the packet and will be the end of the header.
1629 * If not then it probably represents the end of the last recognized
1630 * header.
1631 */
1632 if ((hdr.network - data) < max_len)
1633 return hdr.network - data;
1634 else
1635 return max_len;
1636}
1637
1d2024f6
AD		 1638static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1639 struct sk_buff *skb)
1640{
f800326d 1641 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1642
1643 /* set gso_size to avoid messing up TCP MSS */
1644 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1645 IXGBE_CB(skb)->append_cnt);
96be80ab 1646 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1647}
1648
1649static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1650 struct sk_buff *skb)
1651{
1652 /* if append_cnt is 0 then frame is not RSC */
1653 if (!IXGBE_CB(skb)->append_cnt)
1654 return;
1655
1656 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1657 rx_ring->rx_stats.rsc_flush++;
1658
1659 ixgbe_set_rsc_gso_size(rx_ring, skb);
1660
1661 /* gso_size is computed using append_cnt so always clear it last */
1662 IXGBE_CB(skb)->append_cnt = 0;
1663}
1664
8a0da21b
AD		 1665/**
1666 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1667 * @rx_ring: rx descriptor ring packet is being transacted on
1668 * @rx_desc: pointer to the EOP Rx descriptor
1669 * @skb: pointer to current skb being populated
f8212f97 1670 *
8a0da21b
AD		 1671 * This function checks the ring, descriptor, and packet information in
1672 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1673 * other fields within the skb.
f8212f97 1674 **/
8a0da21b
AD		 1675static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1676 union ixgbe_adv_rx_desc *rx_desc,
1677 struct sk_buff *skb)
f8212f97 1678{
43e95f11
JF		 1679 struct net_device *dev = rx_ring->netdev;
1680
8a0da21b
AD		 1681 ixgbe_update_rsc_stats(rx_ring, skb);
1682
1683 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1684
8a0da21b
AD		 1685 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1686
eda183c2
JK		 1687 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1688 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1689
f646968f 1690 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1691 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1692 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1693 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1694 }
1695
8a0da21b 1696 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1697
43e95f11 1698 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1699}
1700
8a0da21b
AD		 1701static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1702 struct sk_buff *skb)
aa80175a 1703{
8a0da21b
AD		 1704 struct ixgbe_adapter *adapter = q_vector->adapter;
1705
b4640030 1706 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1707 netif_receive_skb(skb);
1708 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1709 napi_gro_receive(&q_vector->napi, skb);
1710 else
1711 netif_rx(skb);
aa80175a 1712}
43634e82 1713
f800326d
AD		 1714/**
1715 * ixgbe_is_non_eop - process handling of non-EOP buffers
1716 * @rx_ring: Rx ring being processed
1717 * @rx_desc: Rx descriptor for current buffer
1718 * @skb: Current socket buffer containing buffer in progress
1719 *
1720 * This function updates next to clean. If the buffer is an EOP buffer
1721 * this function exits returning false, otherwise it will place the
1722 * sk_buff in the next buffer to be chained and return true indicating
1723 * that this is in fact a non-EOP buffer.
1724 **/
1725static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1726 union ixgbe_adv_rx_desc *rx_desc,
1727 struct sk_buff *skb)
1728{
1729 u32 ntc = rx_ring->next_to_clean + 1;
1730
1731 /* fetch, update, and store next to clean */
1732 ntc = (ntc < rx_ring->count) ? ntc : 0;
1733 rx_ring->next_to_clean = ntc;
1734
1735 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1736
5a02cbd1
AD		 1737 /* update RSC append count if present */
1738 if (ring_is_rsc_enabled(rx_ring)) {
1739 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1740 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1741
1742 if (unlikely(rsc_enabled)) {
1743 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1744
1745 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1746 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1747
5a02cbd1
AD		 1748 /* update ntc based on RSC value */
1749 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1750 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1751 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1752 }
f800326d
AD		 1753 }
1754
5a02cbd1
AD		 1755 /* if we are the last buffer then there is nothing else to do */
1756 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1757 return false;
1758
f800326d
AD		 1759 /* place skb in next buffer to be received */
1760 rx_ring->rx_buffer_info[ntc].skb = skb;
1761 rx_ring->rx_stats.non_eop_descs++;
1762
1763 return true;
1764}
1765
19861ce2
AD		 1766/**
1767 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1768 * @rx_ring: rx descriptor ring packet is being transacted on
1769 * @skb: pointer to current skb being adjusted
1770 *
1771 * This function is an ixgbe specific version of __pskb_pull_tail. The
1772 * main difference between this version and the original function is that
1773 * this function can make several assumptions about the state of things
1774 * that allow for significant optimizations versus the standard function.
1775 * As a result we can do things like drop a frag and maintain an accurate
1776 * truesize for the skb.
1777 */
1778static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1779 struct sk_buff *skb)
1780{
1781 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1782 unsigned char *va;
1783 unsigned int pull_len;
1784
1785 /*
1786 * it is valid to use page_address instead of kmap since we are
1787 * working with pages allocated out of the lomem pool per
1788 * alloc_page(GFP_ATOMIC)
1789 */
1790 va = skb_frag_address(frag);
1791
1792 /*
1793 * we need the header to contain the greater of either ETH_HLEN or
1794 * 60 bytes if the skb->len is less than 60 for skb_pad.
1795 */
cf3fe7ac 1796 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1797
1798 /* align pull length to size of long to optimize memcpy performance */
1799 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1800
1801 /* update all of the pointers */
1802 skb_frag_size_sub(frag, pull_len);
1803 frag->page_offset += pull_len;
1804 skb->data_len -= pull_len;
1805 skb->tail += pull_len;
19861ce2
AD		 1806}
1807
42073d91
AD		 1808/**
1809 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1810 * @rx_ring: rx descriptor ring packet is being transacted on
1811 * @skb: pointer to current skb being updated
1812 *
1813 * This function provides a basic DMA sync up for the first fragment of an
1814 * skb. The reason for doing this is that the first fragment cannot be
1815 * unmapped until we have reached the end of packet descriptor for a buffer
1816 * chain.
1817 */
1818static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1819 struct sk_buff *skb)
1820{
1821 /* if the page was released unmap it, else just sync our portion */
1822 if (unlikely(IXGBE_CB(skb)->page_released)) {
1823 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1824 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1825 IXGBE_CB(skb)->page_released = false;
1826 } else {
1827 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1828
1829 dma_sync_single_range_for_cpu(rx_ring->dev,
1830 IXGBE_CB(skb)->dma,
1831 frag->page_offset,
1832 ixgbe_rx_bufsz(rx_ring),
1833 DMA_FROM_DEVICE);
1834 }
1835 IXGBE_CB(skb)->dma = 0;
1836}
1837
f800326d
AD		 1838/**
1839 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1840 * @rx_ring: rx descriptor ring packet is being transacted on
1841 * @rx_desc: pointer to the EOP Rx descriptor
1842 * @skb: pointer to current skb being fixed
1843 *
1844 * Check for corrupted packet headers caused by senders on the local L2
1845 * embedded NIC switch not setting up their Tx Descriptors right. These
1846 * should be very rare.
1847 *
1848 * Also address the case where we are pulling data in on pages only
1849 * and as such no data is present in the skb header.
1850 *
1851 * In addition if skb is not at least 60 bytes we need to pad it so that
1852 * it is large enough to qualify as a valid Ethernet frame.
1853 *
1854 * Returns true if an error was encountered and skb was freed.
1855 **/
1856static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1857 union ixgbe_adv_rx_desc *rx_desc,
1858 struct sk_buff *skb)
1859{
f800326d 1860 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1861
1862 /* verify that the packet does not have any known errors */
1863 if (unlikely(ixgbe_test_staterr(rx_desc,
1864 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1865 !(netdev->features & NETIF_F_RXALL))) {
1866 dev_kfree_skb_any(skb);
1867 return true;
1868 }
1869
19861ce2 1870 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1871 if (skb_is_nonlinear(skb))
1872 ixgbe_pull_tail(rx_ring, skb);
f800326d 1873
57efd44c
AD		 1874#ifdef IXGBE_FCOE
1875 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1876 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1877 return false;
1878
1879#endif
f800326d
AD		 1880 /* if skb_pad returns an error the skb was freed */
1881 if (unlikely(skb->len < 60)) {
1882 int pad_len = 60 - skb->len;
1883
1884 if (skb_pad(skb, pad_len))
1885 return true;
1886 __skb_put(skb, pad_len);
1887 }
1888
1889 return false;
1890}
1891
f800326d
AD		 1892/**
1893 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1894 * @rx_ring: rx descriptor ring to store buffers on
1895 * @old_buff: donor buffer to have page reused
1896 *
0549ae20 1897 * Synchronizes page for reuse by the adapter
f800326d
AD		 1898 **/
1899static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1900 struct ixgbe_rx_buffer *old_buff)
1901{
1902 struct ixgbe_rx_buffer *new_buff;
1903 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1904
1905 new_buff = &rx_ring->rx_buffer_info[nta];
1906
1907 /* update, and store next to alloc */
1908 nta++;
1909 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1910
1911 /* transfer page from old buffer to new buffer */
1912 new_buff->page = old_buff->page;
1913 new_buff->dma = old_buff->dma;
0549ae20 1914 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1915
1916 /* sync the buffer for use by the device */
1917 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1918 new_buff->page_offset,
1919 ixgbe_rx_bufsz(rx_ring),
f800326d 1920 DMA_FROM_DEVICE);
f800326d
AD		 1921}
1922
1923/**
1924 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1925 * @rx_ring: rx descriptor ring to transact packets on
1926 * @rx_buffer: buffer containing page to add
1927 * @rx_desc: descriptor containing length of buffer written by hardware
1928 * @skb: sk_buff to place the data into
1929 *
0549ae20
AD		 1930 * This function will add the data contained in rx_buffer->page to the skb.
1931 * This is done either through a direct copy if the data in the buffer is
1932 * less than the skb header size, otherwise it will just attach the page as
1933 * a frag to the skb.
1934 *
1935 * The function will then update the page offset if necessary and return
1936 * true if the buffer can be reused by the adapter.
f800326d 1937 **/
0549ae20 1938static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1939 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1940 union ixgbe_adv_rx_desc *rx_desc,
1941 struct sk_buff *skb)
f800326d 1942{
0549ae20
AD		 1943 struct page *page = rx_buffer->page;
1944 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1945#if (PAGE_SIZE < 8192)
0549ae20 1946 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1947#else
1948 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1949 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1950 ixgbe_rx_bufsz(rx_ring);
1951#endif
0549ae20 1952
cf3fe7ac
AD		 1953 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1954 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1955
1956 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1957
1958 /* we can reuse buffer as-is, just make sure it is local */
1959 if (likely(page_to_nid(page) == numa_node_id()))
1960 return true;
1961
1962 /* this page cannot be reused so discard it */
1963 put_page(page);
1964 return false;
1965 }
1966
0549ae20
AD		 1967 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1968 rx_buffer->page_offset, size, truesize);
1969
09816fbe
AD		 1970 /* avoid re-using remote pages */
1971 if (unlikely(page_to_nid(page) != numa_node_id()))
1972 return false;
1973
1974#if (PAGE_SIZE < 8192)
1975 /* if we are only owner of page we can reuse it */
1976 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1977 return false;
1978
1979 /* flip page offset to other buffer */
1980 rx_buffer->page_offset ^= truesize;
1981
09816fbe
AD		 1982 /*
1983 * since we are the only owner of the page and we need to
1984 * increment it, just set the value to 2 in order to avoid
1985 * an unecessary locked operation
1986 */
1987 atomic_set(&page->_count, 2);
1988#else
1989 /* move offset up to the next cache line */
1990 rx_buffer->page_offset += truesize;
1991
1992 if (rx_buffer->page_offset > last_offset)
1993 return false;
1994
0549ae20
AD		 1995 /* bump ref count on page before it is given to the stack */
1996 get_page(page);
09816fbe 1997#endif
0549ae20
AD		 1998
1999 return true;
f800326d
AD		 2000}
2001
18806c9e
AD		 2002static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
2003 union ixgbe_adv_rx_desc *rx_desc)
2004{
2005 struct ixgbe_rx_buffer *rx_buffer;
2006 struct sk_buff *skb;
2007 struct page *page;
2008
2009 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2010 page = rx_buffer->page;
2011 prefetchw(page);
2012
2013 skb = rx_buffer->skb;
2014
2015 if (likely(!skb)) {
2016 void *page_addr = page_address(page) +
2017 rx_buffer->page_offset;
2018
2019 /* prefetch first cache line of first page */
2020 prefetch(page_addr);
2021#if L1_CACHE_BYTES < 128
2022 prefetch(page_addr + L1_CACHE_BYTES);
2023#endif
2024
2025 /* allocate a skb to store the frags */
2026 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
2027 IXGBE_RX_HDR_SIZE);
2028 if (unlikely(!skb)) {
2029 rx_ring->rx_stats.alloc_rx_buff_failed++;
2030 return NULL;
2031 }
2032
2033 /*
2034 * we will be copying header into skb->data in
2035 * pskb_may_pull so it is in our interest to prefetch
2036 * it now to avoid a possible cache miss
2037 */
2038 prefetchw(skb->data);
2039
2040 /*
2041 * Delay unmapping of the first packet. It carries the
2042 * header information, HW may still access the header
2043 * after the writeback. Only unmap it when EOP is
2044 * reached
2045 */
2046 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2047 goto dma_sync;
2048
2049 IXGBE_CB(skb)->dma = rx_buffer->dma;
2050 } else {
2051 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2052 ixgbe_dma_sync_frag(rx_ring, skb);
2053
2054dma_sync:
2055 /* we are reusing so sync this buffer for CPU use */
2056 dma_sync_single_range_for_cpu(rx_ring->dev,
2057 rx_buffer->dma,
2058 rx_buffer->page_offset,
2059 ixgbe_rx_bufsz(rx_ring),
2060 DMA_FROM_DEVICE);
2061 }
2062
2063 /* pull page into skb */
2064 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2065 /* hand second half of page back to the ring */
2066 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2067 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2068 /* the page has been released from the ring */
2069 IXGBE_CB(skb)->page_released = true;
2070 } else {
2071 /* we are not reusing the buffer so unmap it */
2072 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2073 ixgbe_rx_pg_size(rx_ring),
2074 DMA_FROM_DEVICE);
2075 }
2076
2077 /* clear contents of buffer_info */
2078 rx_buffer->skb = NULL;
2079 rx_buffer->dma = 0;
2080 rx_buffer->page = NULL;
2081
2082 return skb;
f800326d
AD		 2083}
2084
2085/**
2086 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2087 * @q_vector: structure containing interrupt and ring information
2088 * @rx_ring: rx descriptor ring to transact packets on
2089 * @budget: Total limit on number of packets to process
2090 *
2091 * This function provides a "bounce buffer" approach to Rx interrupt
2092 * processing. The advantage to this is that on systems that have
2093 * expensive overhead for IOMMU access this provides a means of avoiding
2094 * it by maintaining the mapping of the page to the syste.
2095 *
5a85e737 2096 * Returns amount of work completed
f800326d 2097 **/
5a85e737 2098static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2099 struct ixgbe_ring *rx_ring,
f4de00ed 2100 const int budget)
9a799d71 2101{
d2f4fbe2 2102 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2103#ifdef IXGBE_FCOE
f800326d 2104 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2105 int ddp_bytes;
2106 unsigned int mss = 0;
3d8fd385 2107#endif /* IXGBE_FCOE */
f800326d 2108 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2109
fdabfc8a 2110 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2111 union ixgbe_adv_rx_desc *rx_desc;
2112 struct sk_buff *skb;
f800326d
AD		 2113
2114 /* return some buffers to hardware, one at a time is too slow */
2115 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2116 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2117 cleaned_count = 0;
2118 }
2119
18806c9e 2120 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2121
2122 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2123 break;
9a799d71 2124
f800326d
AD		 2125 /*
2126 * This memory barrier is needed to keep us from reading
2127 * any other fields out of the rx_desc until we know the
2128 * RXD_STAT_DD bit is set
2129 */
2130 rmb();
9a799d71 2131
18806c9e
AD		 2132 /* retrieve a buffer from the ring */
2133 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2134
18806c9e
AD		 2135 /* exit if we failed to retrieve a buffer */
2136 if (!skb)
2137 break;
9a799d71 2138
9a799d71 2139 cleaned_count++;
f8212f97 2140
f800326d
AD		 2141 /* place incomplete frames back on ring for completion */
2142 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2143 continue;
c267fc16 2144
f800326d
AD		 2145 /* verify the packet layout is correct */
2146 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2147 continue;
9a799d71 2148
d2f4fbe2
AV		 2149 /* probably a little skewed due to removing CRC */
2150 total_rx_bytes += skb->len;
d2f4fbe2 2151
8a0da21b
AD		 2152 /* populate checksum, timestamp, VLAN, and protocol */
2153 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2154
332d4a7d
YZ		 2155#ifdef IXGBE_FCOE
2156 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2157 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2158 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2159 /* include DDPed FCoE data */
2160 if (ddp_bytes > 0) {
2161 if (!mss) {
2162 mss = rx_ring->netdev->mtu -
2163 sizeof(struct fcoe_hdr) -
2164 sizeof(struct fc_frame_header) -
2165 sizeof(struct fcoe_crc_eof);
2166 if (mss > 512)
2167 mss &= ~511;
2168 }
2169 total_rx_bytes += ddp_bytes;
2170 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2171 mss);
2172 }
63d635b2
AD		 2173 if (!ddp_bytes) {
2174 dev_kfree_skb_any(skb);
f800326d 2175 continue;
63d635b2 2176 }
3d8fd385 2177 }
f800326d 2178
332d4a7d 2179#endif /* IXGBE_FCOE */
8b80cda5 2180 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2181 ixgbe_rx_skb(q_vector, skb);
9a799d71 2182
f800326d 2183 /* update budget accounting */
f4de00ed 2184 total_rx_packets++;
fdabfc8a 2185 }
9a799d71 2186
c267fc16
AD		 2187 u64_stats_update_begin(&rx_ring->syncp);
2188 rx_ring->stats.packets += total_rx_packets;
2189 rx_ring->stats.bytes += total_rx_bytes;
2190 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2191 q_vector->rx.total_packets += total_rx_packets;
2192 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2193
f800326d
AD		 2194 if (cleaned_count)
2195 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2196
5a85e737 2197 return total_rx_packets;
9a799d71
AK		 2198}
2199
e0d1095a 2200#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2201/* must be called with local_bh_disable()d */
2202static int ixgbe_low_latency_recv(struct napi_struct *napi)
2203{
2204 struct ixgbe_q_vector *q_vector =
2205 container_of(napi, struct ixgbe_q_vector, napi);
2206 struct ixgbe_adapter *adapter = q_vector->adapter;
2207 struct ixgbe_ring *ring;
2208 int found = 0;
2209
2210 if (test_bit(__IXGBE_DOWN, &adapter->state))
2211 return LL_FLUSH_FAILED;
2212
2213 if (!ixgbe_qv_lock_poll(q_vector))
2214 return LL_FLUSH_BUSY;
2215
2216 ixgbe_for_each_ring(ring, q_vector->rx) {
2217 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2218#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2219 if (found)
2220 ring->stats.cleaned += found;
2221 else
2222 ring->stats.misses++;
2223#endif
5a85e737
ET		 2224 if (found)
2225 break;
2226 }
2227
2228 ixgbe_qv_unlock_poll(q_vector);
2229
2230 return found;
2231}
e0d1095a 2232#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2233
9a799d71
AK		 2234/**
2235 * ixgbe_configure_msix - Configure MSI-X hardware
2236 * @adapter: board private structure
2237 *
2238 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2239 * interrupts.
2240 **/
2241static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2242{
021230d4 2243 struct ixgbe_q_vector *q_vector;
49c7ffbe 2244 int v_idx;
021230d4 2245 u32 mask;
9a799d71 2246
8e34d1aa
AD		 2247 /* Populate MSIX to EITR Select */
2248 if (adapter->num_vfs > 32) {
2249 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2250 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2251 }
2252
4df10466
JB		 2253 /*
2254 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2255 * corresponding register.
2256 */
49c7ffbe 2257 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2258 struct ixgbe_ring *ring;
7a921c93 2259 q_vector = adapter->q_vector[v_idx];
021230d4 2260
a557928e 2261 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2262 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2263
a557928e 2264 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2265 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2266
fe49f04a 2267 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2268 }
2269
bd508178
AD		 2270 switch (adapter->hw.mac.type) {
2271 case ixgbe_mac_82598EB:
e8e26350 2272 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2273 v_idx);
bd508178
AD		 2274 break;
2275 case ixgbe_mac_82599EB:
b93a2226 2276 case ixgbe_mac_X540:
e8e26350 2277 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2278 break;
bd508178
AD		 2279 default:
2280 break;
2281 }
021230d4
AV		 2282 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2283
41fb9248 2284 /* set up to autoclear timer, and the vectors */
021230d4 2285 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2286 mask &= ~(IXGBE_EIMS_OTHER |
2287 IXGBE_EIMS_MAILBOX |
2288 IXGBE_EIMS_LSC);
2289
021230d4 2290 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2291}
2292
f494e8fa
AV		 2293enum latency_range {
2294 lowest_latency = 0,
2295 low_latency = 1,
2296 bulk_latency = 2,
2297 latency_invalid = 255
2298};
2299
2300/**
2301 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2302 * @q_vector: structure containing interrupt and ring information
2303 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2304 *
2305 * Stores a new ITR value based on packets and byte
2306 * counts during the last interrupt. The advantage of per interrupt
2307 * computation is faster updates and more accurate ITR for the current
2308 * traffic pattern. Constants in this function were computed
2309 * based on theoretical maximum wire speed and thresholds were set based
2310 * on testing data as well as attempting to minimize response time
2311 * while increasing bulk throughput.
2312 * this functionality is controlled by the InterruptThrottleRate module
2313 * parameter (see ixgbe_param.c)
2314 **/
bd198058
AD		 2315static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2316 struct ixgbe_ring_container *ring_container)
f494e8fa 2317{
bd198058
AD		 2318 int bytes = ring_container->total_bytes;
2319 int packets = ring_container->total_packets;
2320 u32 timepassed_us;
621bd70e 2321 u64 bytes_perint;
bd198058 2322 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2323
2324 if (packets == 0)
bd198058 2325 return;
f494e8fa
AV		 2326
2327 /* simple throttlerate management
621bd70e
AD		 2328 * 0-10MB/s lowest (100000 ints/s)
2329 * 10-20MB/s low (20000 ints/s)
2330 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2331 */
2332 /* what was last interrupt timeslice? */
d5bf4f67 2333 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2334 if (timepassed_us == 0)
2335 return;
2336
f494e8fa
AV		 2337 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2338
2339 switch (itr_setting) {
2340 case lowest_latency:
621bd70e 2341 if (bytes_perint > 10)
bd198058 2342 itr_setting = low_latency;
f494e8fa
AV		 2343 break;
2344 case low_latency:
621bd70e 2345 if (bytes_perint > 20)
bd198058 2346 itr_setting = bulk_latency;
621bd70e 2347 else if (bytes_perint <= 10)
bd198058 2348 itr_setting = lowest_latency;
f494e8fa
AV		 2349 break;
2350 case bulk_latency:
621bd70e 2351 if (bytes_perint <= 20)
bd198058 2352 itr_setting = low_latency;
f494e8fa
AV		 2353 break;
2354 }
2355
bd198058
AD		 2356 /* clear work counters since we have the values we need */
2357 ring_container->total_bytes = 0;
2358 ring_container->total_packets = 0;
2359
2360 /* write updated itr to ring container */
2361 ring_container->itr = itr_setting;
f494e8fa
AV		 2362}
2363
509ee935
JB		 2364/**
2365 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2366 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2367 *
2368 * This function is made to be called by ethtool and by the driver
2369 * when it needs to update EITR registers at runtime. Hardware
2370 * specific quirks/differences are taken care of here.
2371 */
fe49f04a 2372void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2373{
fe49f04a 2374 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2375 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2376 int v_idx = q_vector->v_idx;
5d967eb7 2377 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2378
bd508178
AD		 2379 switch (adapter->hw.mac.type) {
2380 case ixgbe_mac_82598EB:
509ee935
JB		 2381 /* must write high and low 16 bits to reset counter */
2382 itr_reg |= (itr_reg << 16);
bd508178
AD		 2383 break;
2384 case ixgbe_mac_82599EB:
b93a2226 2385 case ixgbe_mac_X540:
509ee935
JB		 2386 /*
2387 * set the WDIS bit to not clear the timer bits and cause an
2388 * immediate assertion of the interrupt
2389 */
2390 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2391 break;
2392 default:
2393 break;
509ee935
JB		 2394 }
2395 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2396}
2397
bd198058 2398static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2399{
d5bf4f67 2400 u32 new_itr = q_vector->itr;
bd198058 2401 u8 current_itr;
f494e8fa 2402
bd198058
AD		 2403 ixgbe_update_itr(q_vector, &q_vector->tx);
2404 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2405
08c8833b 2406 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2407
2408 switch (current_itr) {
2409 /* counts and packets in update_itr are dependent on these numbers */
2410 case lowest_latency:
d5bf4f67 2411 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2412 break;
2413 case low_latency:
d5bf4f67 2414 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2415 break;
2416 case bulk_latency:
d5bf4f67 2417 new_itr = IXGBE_8K_ITR;
f494e8fa 2418 break;
bd198058
AD		 2419 default:
2420 break;
f494e8fa
AV		 2421 }
2422
d5bf4f67 2423 if (new_itr != q_vector->itr) {
fe49f04a 2424 /* do an exponential smoothing */
d5bf4f67
ET		 2425 new_itr = (10 * new_itr * q_vector->itr) /
2426 ((9 * new_itr) + q_vector->itr);
509ee935 2427
bd198058 2428 /* save the algorithm value here */
5d967eb7 2429 q_vector->itr = new_itr;
fe49f04a
AD		 2430
2431 ixgbe_write_eitr(q_vector);
f494e8fa 2432 }
f494e8fa
AV		 2433}
2434
119fc60a 2435/**
de88eeeb 2436 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2437 * @adapter: pointer to adapter
119fc60a 2438 **/
f0f9778d 2439static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2440{
119fc60a
MC		 2441 struct ixgbe_hw *hw = &adapter->hw;
2442 u32 eicr = adapter->interrupt_event;
2443
f0f9778d 2444 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2445 return;
2446
f0f9778d
AD		 2447 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2448 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2449 return;
2450
2451 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2452
7ca647bd 2453 switch (hw->device_id) {
f0f9778d
AD		 2454 case IXGBE_DEV_ID_82599_T3_LOM:
2455 /*
2456 * Since the warning interrupt is for both ports
2457 * we don't have to check if:
2458 * - This interrupt wasn't for our port.
2459 * - We may have missed the interrupt so always have to
2460 * check if we got a LSC
2461 */
2462 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2463 !(eicr & IXGBE_EICR_LSC))
2464 return;
2465
2466 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2467 u32 speed;
f0f9778d 2468 bool link_up = false;
7ca647bd 2469
3d292265 2470 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2471
f0f9778d
AD		 2472 if (link_up)
2473 return;
2474 }
2475
2476 /* Check if this is not due to overtemp */
2477 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2478 return;
2479
2480 break;
7ca647bd
JP		 2481 default:
2482 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2483 return;
7ca647bd 2484 break;
119fc60a 2485 }
7ca647bd
JP		 2486 e_crit(drv,
2487 "Network adapter has been stopped because it has over heated. "
2488 "Restart the computer. If the problem persists, "
2489 "power off the system and replace the adapter\n");
f0f9778d
AD		 2490
2491 adapter->interrupt_event = 0;
119fc60a
MC		 2492}
2493
0befdb3e
JB		 2494static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2495{
2496 struct ixgbe_hw *hw = &adapter->hw;
2497
2498 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2499 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2500 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2501 /* write to clear the interrupt */
2502 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2503 }
2504}
cf8280ee 2505
4f51bf70
JK		 2506static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2507{
2508 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2509 return;
2510
2511 switch (adapter->hw.mac.type) {
2512 case ixgbe_mac_82599EB:
2513 /*
2514 * Need to check link state so complete overtemp check
2515 * on service task
2516 */
2517 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2518 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2519 adapter->interrupt_event = eicr;
2520 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2521 ixgbe_service_event_schedule(adapter);
2522 return;
2523 }
2524 return;
2525 case ixgbe_mac_X540:
2526 if (!(eicr & IXGBE_EICR_TS))
2527 return;
2528 break;
2529 default:
2530 return;
2531 }
2532
2533 e_crit(drv,
2534 "Network adapter has been stopped because it has over heated. "
2535 "Restart the computer. If the problem persists, "
2536 "power off the system and replace the adapter\n");
2537}
2538
e8e26350
PW		 2539static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2540{
2541 struct ixgbe_hw *hw = &adapter->hw;
2542
73c4b7cd
AD		 2543 if (eicr & IXGBE_EICR_GPI_SDP2) {
2544 /* Clear the interrupt */
2545 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2546 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2547 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2548 ixgbe_service_event_schedule(adapter);
2549 }
73c4b7cd
AD		 2550 }
2551
e8e26350
PW		 2552 if (eicr & IXGBE_EICR_GPI_SDP1) {
2553 /* Clear the interrupt */
2554 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2555 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2556 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2557 ixgbe_service_event_schedule(adapter);
2558 }
e8e26350
PW		 2559 }
2560}
2561
cf8280ee
JB		 2562static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2563{
2564 struct ixgbe_hw *hw = &adapter->hw;
2565
2566 adapter->lsc_int++;
2567 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2568 adapter->link_check_timeout = jiffies;
2569 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2571 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2572 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2573 }
2574}
2575
fe49f04a
AD		 2576static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2577 u64 qmask)
2578{
2579 u32 mask;
bd508178 2580 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2581
bd508178
AD		 2582 switch (hw->mac.type) {
2583 case ixgbe_mac_82598EB:
fe49f04a 2584 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2585 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2586 break;
2587 case ixgbe_mac_82599EB:
b93a2226 2588 case ixgbe_mac_X540:
fe49f04a 2589 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2590 if (mask)
2591 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2592 mask = (qmask >> 32);
bd508178
AD		 2593 if (mask)
2594 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2595 break;
2596 default:
2597 break;
fe49f04a
AD		 2598 }
2599 /* skip the flush */
2600}
2601
2602static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2603 u64 qmask)
fe49f04a
AD		 2604{
2605 u32 mask;
bd508178 2606 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2607
bd508178
AD		 2608 switch (hw->mac.type) {
2609 case ixgbe_mac_82598EB:
fe49f04a 2610 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2611 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2612 break;
2613 case ixgbe_mac_82599EB:
b93a2226 2614 case ixgbe_mac_X540:
fe49f04a 2615 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2616 if (mask)
2617 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2618 mask = (qmask >> 32);
bd508178
AD		 2619 if (mask)
2620 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2621 break;
2622 default:
2623 break;
fe49f04a
AD		 2624 }
2625 /* skip the flush */
2626}
2627
021230d4 2628/**
2c4af694
AD		 2629 * ixgbe_irq_enable - Enable default interrupt generation settings
2630 * @adapter: board private structure
021230d4 2631 **/
2c4af694
AD		 2632static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2633 bool flush)
9a799d71 2634{
2c4af694 2635 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2636
2c4af694
AD		 2637 /* don't reenable LSC while waiting for link */
2638 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2639 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2640
2c4af694 2641 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2642 switch (adapter->hw.mac.type) {
2643 case ixgbe_mac_82599EB:
2644 mask |= IXGBE_EIMS_GPI_SDP0;
2645 break;
2646 case ixgbe_mac_X540:
2647 mask |= IXGBE_EIMS_TS;
2648 break;
2649 default:
2650 break;
2651 }
2c4af694
AD		 2652 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2653 mask |= IXGBE_EIMS_GPI_SDP1;
2654 switch (adapter->hw.mac.type) {
2655 case ixgbe_mac_82599EB:
2c4af694
AD		 2656 mask |= IXGBE_EIMS_GPI_SDP1;
2657 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2658 case ixgbe_mac_X540:
2659 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2660 mask |= IXGBE_EIMS_MAILBOX;
2661 break;
2662 default:
2663 break;
9a799d71 2664 }
db0677fa 2665
db0677fa
JK		 2666 if (adapter->hw.mac.type == ixgbe_mac_X540)
2667 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2668
2c4af694
AD		 2669 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2670 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2671 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2672
2c4af694
AD		 2673 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2674 if (queues)
2675 ixgbe_irq_enable_queues(adapter, ~0);
2676 if (flush)
2677 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2678}
2679
2c4af694 2680static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2681{
a65151ba 2682 struct ixgbe_adapter *adapter = data;
9a799d71 2683 struct ixgbe_hw *hw = &adapter->hw;
54037505 2684 u32 eicr;
91281fd3 2685
54037505
DS		 2686 /*
2687 * Workaround for Silicon errata. Use clear-by-write instead
2688 * of clear-by-read. Reading with EICS will return the
2689 * interrupt causes without clearing, which later be done
2690 * with the write to EICR.
2691 */
2692 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2693
2694 /* The lower 16bits of the EICR register are for the queue interrupts
2695 * which should be masked here in order to not accidently clear them if
2696 * the bits are high when ixgbe_msix_other is called. There is a race
2697 * condition otherwise which results in possible performance loss
2698 * especially if the ixgbe_msix_other interrupt is triggering
2699 * consistently (as it would when PPS is turned on for the X540 device)
2700 */
2701 eicr &= 0xFFFF0000;
2702
54037505 2703 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2704
cf8280ee
JB		 2705 if (eicr & IXGBE_EICR_LSC)
2706 ixgbe_check_lsc(adapter);
f0848276 2707
1cdd1ec8
GR		 2708 if (eicr & IXGBE_EICR_MAILBOX)
2709 ixgbe_msg_task(adapter);
efe3d3c8 2710
bd508178
AD		 2711 switch (hw->mac.type) {
2712 case ixgbe_mac_82599EB:
b93a2226 2713 case ixgbe_mac_X540:
d773ce2d
DS		 2714 if (eicr & IXGBE_EICR_ECC) {
2715 e_info(link, "Received ECC Err, initiating reset\n");
2716 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2717 ixgbe_service_event_schedule(adapter);
2718 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2719 }
c4cf55e5
PWJ		 2720 /* Handle Flow Director Full threshold interrupt */
2721 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2722 int reinit_count = 0;
c4cf55e5 2723 int i;
c4cf55e5 2724 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2725 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2726 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2727 &ring->state))
2728 reinit_count++;
2729 }
2730 if (reinit_count) {
2731 /* no more flow director interrupts until after init */
2732 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2733 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2734 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2735 }
2736 }
f0f9778d 2737 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2738 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2739 break;
2740 default:
2741 break;
c4cf55e5 2742 }
f0848276 2743
bd508178 2744 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2745
db0677fa
JK		 2746 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2747 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2748
7086400d 2749 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2750 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2751 ixgbe_irq_enable(adapter, false, false);
f0848276 2752
9a799d71 2753 return IRQ_HANDLED;
f0848276 2754}
91281fd3 2755
4ff7fb12 2756static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2757{
021230d4 2758 struct ixgbe_q_vector *q_vector = data;
91281fd3 2759
9b471446 2760 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2761
4ff7fb12
AD		 2762 if (q_vector->rx.ring || q_vector->tx.ring)
2763 napi_schedule(&q_vector->napi);
91281fd3 2764
9a799d71 2765 return IRQ_HANDLED;
91281fd3
AD		 2766}
2767
eb01b975
AD		 2768/**
2769 * ixgbe_poll - NAPI Rx polling callback
2770 * @napi: structure for representing this polling device
2771 * @budget: how many packets driver is allowed to clean
2772 *
2773 * This function is used for legacy and MSI, NAPI mode
2774 **/
8af3c33f 2775int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2776{
2777 struct ixgbe_q_vector *q_vector =
2778 container_of(napi, struct ixgbe_q_vector, napi);
2779 struct ixgbe_adapter *adapter = q_vector->adapter;
2780 struct ixgbe_ring *ring;
2781 int per_ring_budget;
2782 bool clean_complete = true;
2783
2784#ifdef CONFIG_IXGBE_DCA
2785 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2786 ixgbe_update_dca(q_vector);
2787#endif
2788
2789 ixgbe_for_each_ring(ring, q_vector->tx)
2790 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2791
5a85e737
ET		 2792 if (!ixgbe_qv_lock_napi(q_vector))
2793 return budget;
2794
eb01b975
AD		 2795 /* attempt to distribute budget to each queue fairly, but don't allow
2796 * the budget to go below 1 because we'll exit polling */
2797 if (q_vector->rx.count > 1)
2798 per_ring_budget = max(budget/q_vector->rx.count, 1);
2799 else
2800 per_ring_budget = budget;
2801
2802 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2803 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2804 per_ring_budget) < per_ring_budget);
eb01b975 2805
5a85e737 2806 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2807 /* If all work not completed, return budget and keep polling */
2808 if (!clean_complete)
2809 return budget;
2810
2811 /* all work done, exit the polling mode */
2812 napi_complete(napi);
2813 if (adapter->rx_itr_setting & 1)
2814 ixgbe_set_itr(q_vector);
2815 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2816 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2817
2818 return 0;
2819}
2820
021230d4
AV		 2821/**
2822 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2823 * @adapter: board private structure
2824 *
2825 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2826 * interrupts from the kernel.
2827 **/
2828static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2829{
2830 struct net_device *netdev = adapter->netdev;
207867f5 2831 int vector, err;
e8e9f696 2832 int ri = 0, ti = 0;
021230d4 2833
49c7ffbe 2834 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2835 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2836 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2837
4ff7fb12 2838 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2839 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2840 "%s-%s-%d", netdev->name, "TxRx", ri++);
2841 ti++;
2842 } else if (q_vector->rx.ring) {
9fe93afd 2843 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2844 "%s-%s-%d", netdev->name, "rx", ri++);
2845 } else if (q_vector->tx.ring) {
9fe93afd 2846 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2847 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2848 } else {
2849 /* skip this unused q_vector */
2850 continue;
32aa77a4 2851 }
207867f5
AD		 2852 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2853 q_vector->name, q_vector);
9a799d71 2854 if (err) {
396e799c 2855 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2856 "Error: %d\n", err);
021230d4 2857 goto free_queue_irqs;
9a799d71 2858 }
207867f5
AD		 2859 /* If Flow Director is enabled, set interrupt affinity */
2860 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2861 /* assign the mask for this irq */
2862 irq_set_affinity_hint(entry->vector,
de88eeeb 2863 &q_vector->affinity_mask);
207867f5 2864 }
9a799d71
AK		 2865 }
2866
021230d4 2867 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2868 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2869 if (err) {
de88eeeb 2870 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2871 goto free_queue_irqs;
9a799d71
AK		 2872 }
2873
9a799d71
AK		 2874 return 0;
2875
021230d4 2876free_queue_irqs:
207867f5
AD		 2877 while (vector) {
2878 vector--;
2879 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2880 NULL);
2881 free_irq(adapter->msix_entries[vector].vector,
2882 adapter->q_vector[vector]);
2883 }
021230d4
AV		 2884 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2885 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2886 kfree(adapter->msix_entries);
2887 adapter->msix_entries = NULL;
9a799d71
AK		 2888 return err;
2889}
2890
2891/**
021230d4 2892 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2893 * @irq: interrupt number
2894 * @data: pointer to a network interface device structure
9a799d71
AK		 2895 **/
2896static irqreturn_t ixgbe_intr(int irq, void *data)
2897{
a65151ba 2898 struct ixgbe_adapter *adapter = data;
9a799d71 2899 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2900 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2901 u32 eicr;
2902
54037505 2903 /*
24ddd967 2904 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2905 * before the read of EICR.
2906 */
2907 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2908
021230d4 2909 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2910 * therefore no explicit interrupt disable is necessary */
021230d4 2911 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2912 if (!eicr) {
6af3b9eb
ET		 2913 /*
2914 * shared interrupt alert!
f47cf66e 2915 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2916 * have disabled interrupts due to EIAM
2917 * finish the workaround of silicon errata on 82598. Unmask
2918 * the interrupt that we masked before the EICR read.
2919 */
2920 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2921 ixgbe_irq_enable(adapter, true, true);
9a799d71 2922 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2923 }
9a799d71 2924
cf8280ee
JB		 2925 if (eicr & IXGBE_EICR_LSC)
2926 ixgbe_check_lsc(adapter);
021230d4 2927
bd508178
AD		 2928 switch (hw->mac.type) {
2929 case ixgbe_mac_82599EB:
e8e26350 2930 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2931 /* Fall through */
2932 case ixgbe_mac_X540:
d773ce2d
DS		 2933 if (eicr & IXGBE_EICR_ECC) {
2934 e_info(link, "Received ECC Err, initiating reset\n");
2935 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2936 ixgbe_service_event_schedule(adapter);
2937 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2938 }
4f51bf70 2939 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2940 break;
2941 default:
2942 break;
2943 }
e8e26350 2944
0befdb3e 2945 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2946 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2947 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2948
b9f6ed2b
AD		 2949 /* would disable interrupts here but EIAM disabled it */
2950 napi_schedule(&q_vector->napi);
9a799d71 2951
6af3b9eb
ET		 2952 /*
2953 * re-enable link(maybe) and non-queue interrupts, no flush.
2954 * ixgbe_poll will re-enable the queue interrupts
2955 */
6af3b9eb
ET		 2956 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2957 ixgbe_irq_enable(adapter, false, false);
2958
9a799d71
AK		 2959 return IRQ_HANDLED;
2960}
2961
2962/**
2963 * ixgbe_request_irq - initialize interrupts
2964 * @adapter: board private structure
2965 *
2966 * Attempts to configure interrupts using the best available
2967 * capabilities of the hardware and kernel.
2968 **/
021230d4 2969static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2970{
2971 struct net_device *netdev = adapter->netdev;
021230d4 2972 int err;
9a799d71 2973
4cc6df29 2974 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2975 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2976 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2977 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2978 netdev->name, adapter);
4cc6df29 2979 else
a0607fd3 2980 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2981 netdev->name, adapter);
9a799d71 2982
de88eeeb 2983 if (err)
396e799c 2984 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2985
9a799d71
AK		 2986 return err;
2987}
2988
2989static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2990{
49c7ffbe 2991 int vector;
9a799d71 2992
49c7ffbe
AD		 2993 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2994 free_irq(adapter->pdev->irq, adapter);
2995 return;
2996 }
4cc6df29 2997
49c7ffbe
AD		 2998 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2999 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3000 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3001
49c7ffbe
AD		 3002 /* free only the irqs that were actually requested */
3003 if (!q_vector->rx.ring && !q_vector->tx.ring)
3004 continue;
207867f5 3005
49c7ffbe
AD		 3006 /* clear the affinity_mask in the IRQ descriptor */
3007 irq_set_affinity_hint(entry->vector, NULL);
3008
3009 free_irq(entry->vector, q_vector);
9a799d71 3010 }
49c7ffbe
AD		 3011
3012 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3013}
3014
22d5a71b
JB		 3015/**
3016 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3017 * @adapter: board private structure
3018 **/
3019static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3020{
bd508178
AD		 3021 switch (adapter->hw.mac.type) {
3022 case ixgbe_mac_82598EB:
835462fc 3023 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3024 break;
3025 case ixgbe_mac_82599EB:
b93a2226 3026 case ixgbe_mac_X540:
835462fc
NS		 3027 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3029 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3030 break;
3031 default:
3032 break;
22d5a71b
JB		 3033 }
3034 IXGBE_WRITE_FLUSH(&adapter->hw);
3035 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3036 int vector;
3037
3038 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3039 synchronize_irq(adapter->msix_entries[vector].vector);
3040
3041 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3042 } else {
3043 synchronize_irq(adapter->pdev->irq);
3044 }
3045}
3046
9a799d71
AK		 3047/**
3048 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3049 *
3050 **/
3051static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3052{
d5bf4f67 3053 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3054
d5bf4f67 3055 ixgbe_write_eitr(q_vector);
9a799d71 3056
e8e26350
PW		 3057 ixgbe_set_ivar(adapter, 0, 0, 0);
3058 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3059
396e799c 3060 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3061}
3062
43e69bf0
AD		 3063/**
3064 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3065 * @adapter: board private structure
3066 * @ring: structure containing ring specific data
3067 *
3068 * Configure the Tx descriptor ring after a reset.
3069 **/
84418e3b
AD		 3070void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3071 struct ixgbe_ring *ring)
43e69bf0
AD		 3072{
3073 struct ixgbe_hw *hw = &adapter->hw;
3074 u64 tdba = ring->dma;
2f1860b8 3075 int wait_loop = 10;
b88c6de2 3076 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3077 u8 reg_idx = ring->reg_idx;
43e69bf0 3078
2f1860b8 3079 /* disable queue to avoid issues while updating state */
b88c6de2 3080 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3081 IXGBE_WRITE_FLUSH(hw);
3082
43e69bf0 3083 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3084 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3085 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3086 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3087 ring->count * sizeof(union ixgbe_adv_tx_desc));
3088 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3089 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3090 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3091
b88c6de2
AD		 3092 /*
3093 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3094 * higher than 1 when:
3095 * - ITR is 0 as it could cause false TX hangs
3096 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3097 *
3098 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3099 * to or less than the number of on chip descriptors, which is
3100 * currently 40.
3101 */
67da097e
ET		 3102#if IS_ENABLED(CONFIG_BQL)
3103 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3104#else
e954b374 3105 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 3106#endif
b88c6de2
AD		 3107 txdctl |= (1 << 16); /* WTHRESH = 1 */
3108 else
3109 txdctl |= (8 << 16); /* WTHRESH = 8 */
3110
e954b374
AD		 3111 /*
3112 * Setting PTHRESH to 32 both improves performance
3113 * and avoids a TX hang with DFP enabled
3114 */
b88c6de2
AD		 3115 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3116 32; /* PTHRESH = 32 */
2f1860b8
AD		 3117
3118 /* reinitialize flowdirector state */
39cb681b 3119 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3120 ring->atr_sample_rate = adapter->atr_sample_rate;
3121 ring->atr_count = 0;
3122 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3123 } else {
3124 ring->atr_sample_rate = 0;
3125 }
2f1860b8 3126
fd786b7b
AD		 3127 /* initialize XPS */
3128 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3129 struct ixgbe_q_vector *q_vector = ring->q_vector;
3130
3131 if (q_vector)
2a47fa45 3132 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3133 &q_vector->affinity_mask,
3134 ring->queue_index);
3135 }
3136
c84d324c
JF		 3137 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3138
2f1860b8 3139 /* enable queue */
2f1860b8
AD		 3140 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3141
3142 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3143 if (hw->mac.type == ixgbe_mac_82598EB &&
3144 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3145 return;
3146
3147 /* poll to verify queue is enabled */
3148 do {
032b4325 3149 usleep_range(1000, 2000);
2f1860b8
AD		 3150 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3151 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3152 if (!wait_loop)
3153 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3154}
3155
120ff942
AD		 3156static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3157{
3158 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3159 u32 rttdcs, mtqc;
8b1c0b24 3160 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3161
3162 if (hw->mac.type == ixgbe_mac_82598EB)
3163 return;
3164
3165 /* disable the arbiter while setting MTQC */
3166 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3167 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3168 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3169
3170 /* set transmit pool layout */
671c0adb
AD		 3171 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3172 mtqc = IXGBE_MTQC_VT_ENA;
3173 if (tcs > 4)
3174 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3175 else if (tcs > 1)
3176 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3177 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3178 mtqc |= IXGBE_MTQC_32VF;
3179 else
3180 mtqc |= IXGBE_MTQC_64VF;
3181 } else {
3182 if (tcs > 4)
3183 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3184 else if (tcs > 1)
3185 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3186 else
671c0adb
AD		 3187 mtqc = IXGBE_MTQC_64Q_1PB;
3188 }
120ff942 3189
671c0adb 3190 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3191
671c0adb
AD		 3192 /* Enable Security TX Buffer IFG for multiple pb */
3193 if (tcs) {
3194 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3195 sectx |= IXGBE_SECTX_DCB;
3196 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3197 }
3198
3199 /* re-enable the arbiter */
3200 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3201 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3202}
3203
9a799d71 3204/**
3a581073 3205 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3206 * @adapter: board private structure
3207 *
3208 * Configure the Tx unit of the MAC after a reset.
3209 **/
3210static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3211{
2f1860b8
AD		 3212 struct ixgbe_hw *hw = &adapter->hw;
3213 u32 dmatxctl;
43e69bf0 3214 u32 i;
9a799d71 3215
2f1860b8
AD		 3216 ixgbe_setup_mtqc(adapter);
3217
3218 if (hw->mac.type != ixgbe_mac_82598EB) {
3219 /* DMATXCTL.EN must be before Tx queues are enabled */
3220 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3221 dmatxctl |= IXGBE_DMATXCTL_TE;
3222 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3223 }
3224
9a799d71 3225 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3226 for (i = 0; i < adapter->num_tx_queues; i++)
3227 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3228}
3229
3ebe8fde
AD		 3230static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3231 struct ixgbe_ring *ring)
3232{
3233 struct ixgbe_hw *hw = &adapter->hw;
3234 u8 reg_idx = ring->reg_idx;
3235 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3236
3237 srrctl |= IXGBE_SRRCTL_DROP_EN;
3238
3239 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3240}
3241
3242static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3243 struct ixgbe_ring *ring)
3244{
3245 struct ixgbe_hw *hw = &adapter->hw;
3246 u8 reg_idx = ring->reg_idx;
3247 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3248
3249 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3250
3251 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3252}
3253
3254#ifdef CONFIG_IXGBE_DCB
3255void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3256#else
3257static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3258#endif
3259{
3260 int i;
3261 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3262
3263 if (adapter->ixgbe_ieee_pfc)
3264 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3265
3266 /*
3267 * We should set the drop enable bit if:
3268 * SR-IOV is enabled
3269 * or
3270 * Number of Rx queues > 1 and flow control is disabled
3271 *
3272 * This allows us to avoid head of line blocking for security
3273 * and performance reasons.
3274 */
3275 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3276 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3277 for (i = 0; i < adapter->num_rx_queues; i++)
3278 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3279 } else {
3280 for (i = 0; i < adapter->num_rx_queues; i++)
3281 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3282 }
3283}
3284
e8e26350 3285#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3286
a6616b42 3287static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3288 struct ixgbe_ring *rx_ring)
cc41ac7c 3289{
45e9baa5 3290 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3291 u32 srrctl;
bf29ee6c 3292 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3293
45e9baa5
AD		 3294 if (hw->mac.type == ixgbe_mac_82598EB) {
3295 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3296
45e9baa5
AD		 3297 /*
3298 * if VMDq is not active we must program one srrctl register
3299 * per RSS queue since we have enabled RDRXCTL.MVMEN
3300 */
3301 reg_idx &= mask;
3302 }
cc41ac7c 3303
45e9baa5
AD		 3304 /* configure header buffer length, needed for RSC */
3305 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3306
45e9baa5 3307 /* configure the packet buffer length */
f800326d 3308 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3309
3310 /* configure descriptor type */
f800326d 3311 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3312
45e9baa5 3313 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3314}
9a799d71 3315
05abb126 3316static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3317{
05abb126
AD		 3318 struct ixgbe_hw *hw = &adapter->hw;
3319 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3320 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3321 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3322 u32 mrqc = 0, reta = 0;
3323 u32 rxcsum;
3324 int i, j;
671c0adb
AD		 3325 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3326
671c0adb
AD		 3327 /*
3328 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3329 * make full use of any rings they may have. We will use the
3330 * PSRTYPE register to control how many rings we use within the PF.
3331 */
3332 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3333 rss_i = 2;
0cefafad 3334
05abb126
AD		 3335 /* Fill out hash function seeds */
3336 for (i = 0; i < 10; i++)
3337 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3338
3339 /* Fill out redirection table */
3340 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3341 if (j == rss_i)
05abb126
AD		 3342 j = 0;
3343 /* reta = 4-byte sliding window of
3344 * 0x00..(indices-1)(indices-1)00..etc. */
3345 reta = (reta << 8) | (j * 0x11);
3346 if ((i & 3) == 3)
3347 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3348 }
0cefafad 3349
05abb126
AD		 3350 /* Disable indicating checksum in descriptor, enables RSS hash */
3351 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3352 rxcsum |= IXGBE_RXCSUM_PCSD;
3353 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3354
671c0adb 3355 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3356 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3357 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3358 } else {
671c0adb
AD		 3359 u8 tcs = netdev_get_num_tc(adapter->netdev);
3360
3361 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3362 if (tcs > 4)
3363 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3364 else if (tcs > 1)
3365 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3366 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3367 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3368 else
671c0adb
AD		 3369 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3370 } else {
3371 if (tcs > 4)
8b1c0b24 3372 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3373 else if (tcs > 1)
3374 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3375 else
3376 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3377 }
0cefafad
JB		 3378 }
3379
05abb126 3380 /* Perform hash on these packet types */
671c0adb
AD		 3381 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3382 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3383 IXGBE_MRQC_RSS_FIELD_IPV6 |
3384 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3385
ef6afc0c
AD		 3386 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3387 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3388 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3389 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3390
05abb126 3391 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3392}
3393
bb5a9ad2
NS		 3394/**
3395 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3396 * @adapter: address of board private structure
3397 * @index: index of ring to set
bb5a9ad2 3398 **/
082757af 3399static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3400 struct ixgbe_ring *ring)
bb5a9ad2 3401{
bb5a9ad2 3402 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3403 u32 rscctrl;
bf29ee6c 3404 u8 reg_idx = ring->reg_idx;
7367096a 3405
7d637bcc 3406 if (!ring_is_rsc_enabled(ring))
7367096a 3407 return;
bb5a9ad2 3408
7367096a 3409 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3410 rscctrl |= IXGBE_RSCCTL_RSCEN;
3411 /*
3412 * we must limit the number of descriptors so that the
3413 * total size of max desc * buf_len is not greater
642c680e 3414 * than 65536
bb5a9ad2 3415 */
f800326d 3416 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3417 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3418}
3419
9e10e045
AD		 3420#define IXGBE_MAX_RX_DESC_POLL 10
3421static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3422 struct ixgbe_ring *ring)
3423{
3424 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3425 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3426 u32 rxdctl;
bf29ee6c 3427 u8 reg_idx = ring->reg_idx;
9e10e045 3428
b0483c8f
MR		 3429 if (ixgbe_removed(hw->hw_addr))
3430 return;
9e10e045
AD		 3431 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3432 if (hw->mac.type == ixgbe_mac_82598EB &&
3433 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3434 return;
3435
3436 do {
032b4325 3437 usleep_range(1000, 2000);
9e10e045
AD		 3438 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3439 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3440
3441 if (!wait_loop) {
3442 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3443 "the polling period\n", reg_idx);
3444 }
3445}
3446
2d39d576
YZ		 3447void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3448 struct ixgbe_ring *ring)
3449{
3450 struct ixgbe_hw *hw = &adapter->hw;
3451 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3452 u32 rxdctl;
3453 u8 reg_idx = ring->reg_idx;
3454
b0483c8f
MR		 3455 if (ixgbe_removed(hw->hw_addr))
3456 return;
2d39d576
YZ		 3457 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3458 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3459
3460 /* write value back with RXDCTL.ENABLE bit cleared */
3461 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3462
3463 if (hw->mac.type == ixgbe_mac_82598EB &&
3464 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3465 return;
3466
3467 /* the hardware may take up to 100us to really disable the rx queue */
3468 do {
3469 udelay(10);
3470 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3471 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3472
3473 if (!wait_loop) {
3474 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3475 "the polling period\n", reg_idx);
3476 }
3477}
3478
84418e3b
AD		 3479void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3480 struct ixgbe_ring *ring)
acd37177
AD		 3481{
3482 struct ixgbe_hw *hw = &adapter->hw;
3483 u64 rdba = ring->dma;
9e10e045 3484 u32 rxdctl;
bf29ee6c 3485 u8 reg_idx = ring->reg_idx;
acd37177 3486
9e10e045
AD		 3487 /* disable queue to avoid issues while updating state */
3488 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3489 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3490
acd37177
AD		 3491 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3492 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3493 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3494 ring->count * sizeof(union ixgbe_adv_rx_desc));
3495 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3496 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3497 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3498
3499 ixgbe_configure_srrctl(adapter, ring);
3500 ixgbe_configure_rscctl(adapter, ring);
3501
3502 if (hw->mac.type == ixgbe_mac_82598EB) {
3503 /*
3504 * enable cache line friendly hardware writes:
3505 * PTHRESH=32 descriptors (half the internal cache),
3506 * this also removes ugly rx_no_buffer_count increment
3507 * HTHRESH=4 descriptors (to minimize latency on fetch)
3508 * WTHRESH=8 burst writeback up to two cache lines
3509 */
3510 rxdctl &= ~0x3FFFFF;
3511 rxdctl |= 0x080420;
3512 }
3513
3514 /* enable receive descriptor ring */
3515 rxdctl |= IXGBE_RXDCTL_ENABLE;
3516 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3517
3518 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3519 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3520}
3521
48654521
AD		 3522static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3523{
3524 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3525 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3526 u16 pool;
48654521
AD		 3527
3528 /* PSRTYPE must be initialized in non 82598 adapters */
3529 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3530 IXGBE_PSRTYPE_UDPHDR |
3531 IXGBE_PSRTYPE_IPV4HDR |
48654521 3532 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3533 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3534
3535 if (hw->mac.type == ixgbe_mac_82598EB)
3536 return;
3537
fbe7ca7f
AD		 3538 if (rss_i > 3)
3539 psrtype |= 2 << 29;
3540 else if (rss_i > 1)
3541 psrtype |= 1 << 29;
48654521 3542
2a47fa45
JF		 3543 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3544 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3545}
3546
f5b4a52e
AD		 3547static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3548{
3549 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3550 u32 reg_offset, vf_shift;
435b19f6 3551 u32 gcr_ext, vmdctl;
de4c7f65 3552 int i;
f5b4a52e
AD		 3553
3554 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3555 return;
3556
3557 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3558 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3559 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3560 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3561 vmdctl |= IXGBE_VT_CTL_REPLEN;
3562 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3563
1d9c0bfd
AD		 3564 vf_shift = VMDQ_P(0) % 32;
3565 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3566
3567 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3568 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3569 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3570 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3571 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3572 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3573 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3574
3575 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3576 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3577
3578 /*
3579 * Set up VF register offsets for selected VT Mode,
3580 * i.e. 32 or 64 VFs for SR-IOV
3581 */
73079ea0
AD		 3582 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3583 case IXGBE_82599_VMDQ_8Q_MASK:
3584 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3585 break;
3586 case IXGBE_82599_VMDQ_4Q_MASK:
3587 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3588 break;
3589 default:
3590 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3591 break;
3592 }
3593
f5b4a52e
AD		 3594 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3595
435b19f6 3596
a985b6c3 3597 /* Enable MAC Anti-Spoofing */
435b19f6 3598 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3599 adapter->num_vfs);
de4c7f65
GR		 3600 /* For VFs that have spoof checking turned off */
3601 for (i = 0; i < adapter->num_vfs; i++) {
3602 if (!adapter->vfinfo[i].spoofchk_enabled)
3603 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3604 }
f5b4a52e
AD		 3605}
3606
477de6ed 3607static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3608{
9a799d71
AK		 3609 struct ixgbe_hw *hw = &adapter->hw;
3610 struct net_device *netdev = adapter->netdev;
3611 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3612 struct ixgbe_ring *rx_ring;
3613 int i;
3614 u32 mhadd, hlreg0;
48654521 3615
63f39bd1 3616#ifdef IXGBE_FCOE
477de6ed
AD		 3617 /* adjust max frame to be able to do baby jumbo for FCoE */
3618 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3619 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3620 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3621
477de6ed 3622#endif /* IXGBE_FCOE */
872844dd
AD		 3623
3624 /* adjust max frame to be at least the size of a standard frame */
3625 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3626 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3627
477de6ed
AD		 3628 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3629 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3630 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3631 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3632
3633 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3634 }
3635
3636 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3637 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3638 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3639 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3640
0cefafad
JB		 3641 /*
3642 * Setup the HW Rx Head and Tail Descriptor Pointers and
3643 * the Base and Length of the Rx Descriptor Ring
3644 */
9a799d71 3645 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3646 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3647 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3648 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3649 else
7d637bcc 3650 clear_ring_rsc_enabled(rx_ring);
477de6ed 3651 }
477de6ed
AD		 3652}
3653
7367096a
AD		 3654static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3655{
3656 struct ixgbe_hw *hw = &adapter->hw;
3657 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3658
3659 switch (hw->mac.type) {
3660 case ixgbe_mac_82598EB:
3661 /*
3662 * For VMDq support of different descriptor types or
3663 * buffer sizes through the use of multiple SRRCTL
3664 * registers, RDRXCTL.MVMEN must be set to 1
3665 *
3666 * also, the manual doesn't mention it clearly but DCA hints
3667 * will only use queue 0's tags unless this bit is set. Side
3668 * effects of setting this bit are only that SRRCTL must be
3669 * fully programmed [0..15]
3670 */
3671 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3672 break;
3673 case ixgbe_mac_82599EB:
b93a2226 3674 case ixgbe_mac_X540:
7367096a
AD		 3675 /* Disable RSC for ACK packets */
3676 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3677 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3678 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3679 /* hardware requires some bits to be set by default */
3680 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3681 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3682 break;
3683 default:
3684 /* We should do nothing since we don't know this hardware */
3685 return;
3686 }
3687
3688 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3689}
3690
477de6ed
AD		 3691/**
3692 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3693 * @adapter: board private structure
3694 *
3695 * Configure the Rx unit of the MAC after a reset.
3696 **/
3697static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3698{
3699 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3700 int i;
6dcc28b9 3701 u32 rxctrl, rfctl;
477de6ed
AD		 3702
3703 /* disable receives while setting up the descriptors */
3704 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3705 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3706
3707 ixgbe_setup_psrtype(adapter);
7367096a 3708 ixgbe_setup_rdrxctl(adapter);
477de6ed 3709
6dcc28b9
JK		 3710 /* RSC Setup */
3711 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3712 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3713 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3714 rfctl |= IXGBE_RFCTL_RSC_DIS;
3715 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3716
9e10e045 3717 /* Program registers for the distribution of queues */
f5b4a52e 3718 ixgbe_setup_mrqc(adapter);
f5b4a52e 3719
477de6ed
AD		 3720 /* set_rx_buffer_len must be called before ring initialization */
3721 ixgbe_set_rx_buffer_len(adapter);
3722
3723 /*
3724 * Setup the HW Rx Head and Tail Descriptor Pointers and
3725 * the Base and Length of the Rx Descriptor Ring
3726 */
9e10e045
AD		 3727 for (i = 0; i < adapter->num_rx_queues; i++)
3728 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3729
9e10e045
AD		 3730 /* disable drop enable for 82598 parts */
3731 if (hw->mac.type == ixgbe_mac_82598EB)
3732 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3733
3734 /* enable all receives */
3735 rxctrl |= IXGBE_RXCTRL_RXEN;
3736 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3737}
3738
80d5c368
PM		 3739static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3740 __be16 proto, u16 vid)
068c89b0
DS		 3741{
3742 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3743 struct ixgbe_hw *hw = &adapter->hw;
3744
3745 /* add VID to filter table */
1d9c0bfd 3746 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3747 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3748
3749 return 0;
068c89b0
DS		 3750}
3751
80d5c368
PM		 3752static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3753 __be16 proto, u16 vid)
068c89b0
DS		 3754{
3755 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3756 struct ixgbe_hw *hw = &adapter->hw;
3757
068c89b0 3758 /* remove VID from filter table */
1d9c0bfd 3759 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3760 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3761
3762 return 0;
068c89b0
DS		 3763}
3764
f62bbb5e
JG		 3765/**
3766 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3767 * @adapter: driver data
3768 */
3769static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3770{
3771 struct ixgbe_hw *hw = &adapter->hw;
3772 u32 vlnctrl;
5f6c0181
JB		 3773 int i, j;
3774
3775 switch (hw->mac.type) {
3776 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3777 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3778 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3779 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3780 break;
3781 case ixgbe_mac_82599EB:
b93a2226 3782 case ixgbe_mac_X540:
5f6c0181 3783 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3784 struct ixgbe_ring *ring = adapter->rx_ring[i];
3785
3786 if (ring->l2_accel_priv)
3787 continue;
3788 j = ring->reg_idx;
5f6c0181
JB		 3789 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3790 vlnctrl &= ~IXGBE_RXDCTL_VME;
3791 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3792 }
3793 break;
3794 default:
3795 break;
3796 }
3797}
3798
3799/**
f62bbb5e 3800 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3801 * @adapter: driver data
3802 */
f62bbb5e 3803static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3804{
3805 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3806 u32 vlnctrl;
5f6c0181
JB		 3807 int i, j;
3808
3809 switch (hw->mac.type) {
3810 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3811 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3812 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3813 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3814 break;
3815 case ixgbe_mac_82599EB:
b93a2226 3816 case ixgbe_mac_X540:
5f6c0181 3817 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3818 struct ixgbe_ring *ring = adapter->rx_ring[i];
3819
3820 if (ring->l2_accel_priv)
3821 continue;
3822 j = ring->reg_idx;
5f6c0181
JB		 3823 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3824 vlnctrl |= IXGBE_RXDCTL_VME;
3825 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3826 }
3827 break;
3828 default:
3829 break;
3830 }
3831}
3832
9a799d71
AK		 3833static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3834{
f62bbb5e 3835 u16 vid;
9a799d71 3836
80d5c368 3837 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3838
3839 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3840 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3841}
3842
b335e75b
JK		 3843/**
3844 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3845 * @netdev: network interface device structure
3846 *
3847 * Writes multicast address list to the MTA hash table.
3848 * Returns: -ENOMEM on failure
3849 * 0 on no addresses written
3850 * X on writing X addresses to MTA
3851 **/
3852static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3853{
3854 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3855 struct ixgbe_hw *hw = &adapter->hw;
3856
3857 if (!netif_running(netdev))
3858 return 0;
3859
3860 if (hw->mac.ops.update_mc_addr_list)
3861 hw->mac.ops.update_mc_addr_list(hw, netdev);
3862 else
3863 return -ENOMEM;
3864
3865#ifdef CONFIG_PCI_IOV
5d7daa35 3866 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 3867#endif
3868
3869 return netdev_mc_count(netdev);
3870}
3871
5d7daa35
JK		 3872#ifdef CONFIG_PCI_IOV
3873void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3874{
3875 struct ixgbe_hw *hw = &adapter->hw;
3876 int i;
3877 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3878 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3879 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3880 adapter->mac_table[i].queue,
3881 IXGBE_RAH_AV);
3882 else
3883 hw->mac.ops.clear_rar(hw, i);
3884
3885 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3886 }
3887}
3888#endif
3889
3890static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3891{
3892 struct ixgbe_hw *hw = &adapter->hw;
3893 int i;
3894 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3895 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3896 if (adapter->mac_table[i].state &
3897 IXGBE_MAC_STATE_IN_USE)
3898 hw->mac.ops.set_rar(hw, i,
3899 adapter->mac_table[i].addr,
3900 adapter->mac_table[i].queue,
3901 IXGBE_RAH_AV);
3902 else
3903 hw->mac.ops.clear_rar(hw, i);
3904
3905 adapter->mac_table[i].state &=
3906 ~(IXGBE_MAC_STATE_MODIFIED);
3907 }
3908 }
3909}
3910
3911static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3912{
3913 int i;
3914 struct ixgbe_hw *hw = &adapter->hw;
3915
3916 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3917 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3918 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3919 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3920 adapter->mac_table[i].queue = 0;
3921 }
3922 ixgbe_sync_mac_table(adapter);
3923}
3924
3925static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3926{
3927 struct ixgbe_hw *hw = &adapter->hw;
3928 int i, count = 0;
3929
3930 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3931 if (adapter->mac_table[i].state == 0)
3932 count++;
3933 }
3934 return count;
3935}
3936
3937/* this function destroys the first RAR entry */
3938static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3939 u8 *addr)
3940{
3941 struct ixgbe_hw *hw = &adapter->hw;
3942
3943 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3944 adapter->mac_table[0].queue = VMDQ_P(0);
3945 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3946 IXGBE_MAC_STATE_IN_USE);
3947 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3948 adapter->mac_table[0].queue,
3949 IXGBE_RAH_AV);
3950}
3951
3952int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3953{
3954 struct ixgbe_hw *hw = &adapter->hw;
3955 int i;
3956
3957 if (is_zero_ether_addr(addr))
3958 return -EINVAL;
3959
3960 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3961 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3962 continue;
3963 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3964 IXGBE_MAC_STATE_IN_USE);
3965 ether_addr_copy(adapter->mac_table[i].addr, addr);
3966 adapter->mac_table[i].queue = queue;
3967 ixgbe_sync_mac_table(adapter);
3968 return i;
3969 }
3970 return -ENOMEM;
3971}
3972
3973int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3974{
3975 /* search table for addr, if found, set to 0 and sync */
3976 int i;
3977 struct ixgbe_hw *hw = &adapter->hw;
3978
3979 if (is_zero_ether_addr(addr))
3980 return -EINVAL;
3981
3982 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3983 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3984 adapter->mac_table[i].queue == queue) {
3985 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3986 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3987 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3988 adapter->mac_table[i].queue = 0;
3989 ixgbe_sync_mac_table(adapter);
3990 return 0;
3991 }
3992 }
3993 return -ENOMEM;
3994}
2850062a
AD		 3995/**
3996 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3997 * @netdev: network interface device structure
3998 *
3999 * Writes unicast address list to the RAR table.
4000 * Returns: -ENOMEM on failure/insufficient address space
4001 * 0 on no addresses written
4002 * X on writing X addresses to the RAR table
4003 **/
5d7daa35 4004static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4005{
4006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4007 int count = 0;
4008
4009 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4010 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4011 return -ENOMEM;
4012
95447461 4013 if (!netdev_uc_empty(netdev)) {
2850062a 4014 struct netdev_hw_addr *ha;
2850062a 4015 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4016 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4017 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4018 count++;
4019 }
4020 }
2850062a
AD		 4021 return count;
4022}
4023
9a799d71 4024/**
2c5645cf 4025 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4026 * @netdev: network interface device structure
4027 *
2c5645cf
CL		 4028 * The set_rx_method entry point is called whenever the unicast/multicast
4029 * address list or the network interface flags are updated. This routine is
4030 * responsible for configuring the hardware for proper unicast, multicast and
4031 * promiscuous mode.
9a799d71 4032 **/
7f870475 4033void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4034{
4035 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4036 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4037 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4038 u32 vlnctrl;
2850062a 4039 int count;
9a799d71
AK		 4040
4041 /* Check for Promiscuous and All Multicast modes */
9a799d71 4042 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4043 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4044
f5dc442b 4045 /* set all bits that we expect to always be set */
3f2d1c0f 4046 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4047 fctrl |= IXGBE_FCTRL_BAM;
4048 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4049 fctrl |= IXGBE_FCTRL_PMCF;
4050
2850062a
AD		 4051 /* clear the bits we are changing the status of */
4052 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4053 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4054 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4055 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4056 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4057 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4058 /* Only disable hardware filter vlans in promiscuous mode
4059 * if SR-IOV and VMDQ are disabled - otherwise ensure
4060 * that hardware VLAN filters remain enabled.
4061 */
4062 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4063 IXGBE_FLAG_SRIOV_ENABLED)))
a9b8943e 4064 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4065 } else {
746b9f02
PM		 4066 if (netdev->flags & IFF_ALLMULTI) {
4067 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4068 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4069 }
a9b8943e 4070 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4071 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4072 }
4073
4074 /*
4075 * Write addresses to available RAR registers, if there is not
4076 * sufficient space to store all the addresses then enable
4077 * unicast promiscuous mode
4078 */
5d7daa35 4079 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4080 if (count < 0) {
4081 fctrl |= IXGBE_FCTRL_UPE;
4082 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4083 }
4084
cf78959c
ET		 4085 /* Write addresses to the MTA, if the attempt fails
4086 * then we should just turn on promiscuous mode so
4087 * that we can at least receive multicast traffic
4088 */
b335e75b
JK		 4089 count = ixgbe_write_mc_addr_list(netdev);
4090 if (count < 0) {
4091 fctrl |= IXGBE_FCTRL_MPE;
4092 vmolr |= IXGBE_VMOLR_MPE;
4093 } else if (count) {
4094 vmolr |= IXGBE_VMOLR_ROMPE;
4095 }
1d9c0bfd
AD		 4096
4097 if (hw->mac.type != ixgbe_mac_82598EB) {
4098 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4099 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4100 IXGBE_VMOLR_ROPE);
1d9c0bfd 4101 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4102 }
4103
3f2d1c0f
BG		 4104 /* This is useful for sniffing bad packets. */
4105 if (adapter->netdev->features & NETIF_F_RXALL) {
4106 /* UPE and MPE will be handled by normal PROMISC logic
4107 * in e1000e_set_rx_mode */
4108 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4109 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4110 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4111
4112 fctrl &= ~(IXGBE_FCTRL_DPF);
4113 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4114 }
4115
a9b8943e 4116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4117 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4118
f646968f 4119 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4120 ixgbe_vlan_strip_enable(adapter);
4121 else
4122 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4123}
4124
021230d4
AV		 4125static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4126{
4127 int q_idx;
021230d4 4128
5a85e737
ET		 4129 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4130 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4131 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4132 }
021230d4
AV		 4133}
4134
4135static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4136{
4137 int q_idx;
021230d4 4138
5a85e737 4139 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4140 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4141 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4142 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4143 usleep_range(1000, 20000);
5a85e737
ET		 4144 }
4145 }
021230d4
AV		 4146}
4147
7a6b6f51 4148#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4149/**
2f90b865
AD		 4150 * ixgbe_configure_dcb - Configure DCB hardware
4151 * @adapter: ixgbe adapter struct
4152 *
4153 * This is called by the driver on open to configure the DCB hardware.
4154 * This is also called by the gennetlink interface when reconfiguring
4155 * the DCB state.
4156 */
4157static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4158{
4159 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4160 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4161
67ebd791
AD		 4162 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4163 if (hw->mac.type == ixgbe_mac_82598EB)
4164 netif_set_gso_max_size(adapter->netdev, 65536);
4165 return;
4166 }
4167
4168 if (hw->mac.type == ixgbe_mac_82598EB)
4169 netif_set_gso_max_size(adapter->netdev, 32768);
4170
971060b1 4171#ifdef IXGBE_FCOE
b120818e
JF		 4172 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4173 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4174#endif
b120818e
JF		 4175
4176 /* reconfigure the hardware */
4177 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4178 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4179 DCB_TX_CONFIG);
4180 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4181 DCB_RX_CONFIG);
4182 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4183 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4184 ixgbe_dcb_hw_ets(&adapter->hw,
4185 adapter->ixgbe_ieee_ets,
4186 max_frame);
4187 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4188 adapter->ixgbe_ieee_pfc->pfc_en,
4189 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4190 }
8187cd48
JF		 4191
4192 /* Enable RSS Hash per TC */
4193 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4194 u32 msb = 0;
4195 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4196
d411a936
AD		 4197 while (rss_i) {
4198 msb++;
4199 rss_i >>= 1;
4200 }
8187cd48 4201
4ae63730
AD		 4202 /* write msb to all 8 TCs in one write */
4203 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4204 }
2f90b865 4205}
9da712d2
JF		 4206#endif
4207
4208/* Additional bittime to account for IXGBE framing */
4209#define IXGBE_ETH_FRAMING 20
4210
49ce9c2c 4211/**
9da712d2
JF		 4212 * ixgbe_hpbthresh - calculate high water mark for flow control
4213 *
4214 * @adapter: board private structure to calculate for
49ce9c2c 4215 * @pb: packet buffer to calculate
9da712d2
JF		 4216 */
4217static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4218{
4219 struct ixgbe_hw *hw = &adapter->hw;
4220 struct net_device *dev = adapter->netdev;
4221 int link, tc, kb, marker;
4222 u32 dv_id, rx_pba;
4223
4224 /* Calculate max LAN frame size */
4225 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4226
4227#ifdef IXGBE_FCOE
4228 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4229 if ((dev->features & NETIF_F_FCOE_MTU) &&
4230 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4231 (pb == ixgbe_fcoe_get_tc(adapter)))
4232 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4233#endif
e5776620 4234
9da712d2
JF		 4235 /* Calculate delay value for device */
4236 switch (hw->mac.type) {
4237 case ixgbe_mac_X540:
4238 dv_id = IXGBE_DV_X540(link, tc);
4239 break;
4240 default:
4241 dv_id = IXGBE_DV(link, tc);
4242 break;
4243 }
4244
4245 /* Loopback switch introduces additional latency */
4246 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4247 dv_id += IXGBE_B2BT(tc);
4248
4249 /* Delay value is calculated in bit times convert to KB */
4250 kb = IXGBE_BT2KB(dv_id);
4251 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4252
4253 marker = rx_pba - kb;
4254
4255 /* It is possible that the packet buffer is not large enough
4256 * to provide required headroom. In this case throw an error
4257 * to user and a do the best we can.
4258 */
4259 if (marker < 0) {
4260 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4261 "headroom to support flow control."
4262 "Decrease MTU or number of traffic classes\n", pb);
4263 marker = tc + 1;
4264 }
4265
4266 return marker;
4267}
4268
49ce9c2c 4269/**
9da712d2
JF		 4270 * ixgbe_lpbthresh - calculate low water mark for for flow control
4271 *
4272 * @adapter: board private structure to calculate for
49ce9c2c 4273 * @pb: packet buffer to calculate
9da712d2 4274 */
e5776620 4275static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4276{
4277 struct ixgbe_hw *hw = &adapter->hw;
4278 struct net_device *dev = adapter->netdev;
4279 int tc;
4280 u32 dv_id;
4281
4282 /* Calculate max LAN frame size */
4283 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4284
e5776620
JK		 4285#ifdef IXGBE_FCOE
4286 /* FCoE traffic class uses FCOE jumbo frames */
4287 if ((dev->features & NETIF_F_FCOE_MTU) &&
4288 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4289 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4290 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4291#endif
4292
9da712d2
JF		 4293 /* Calculate delay value for device */
4294 switch (hw->mac.type) {
4295 case ixgbe_mac_X540:
4296 dv_id = IXGBE_LOW_DV_X540(tc);
4297 break;
4298 default:
4299 dv_id = IXGBE_LOW_DV(tc);
4300 break;
4301 }
4302
4303 /* Delay value is calculated in bit times convert to KB */
4304 return IXGBE_BT2KB(dv_id);
4305}
4306
4307/*
4308 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4309 */
4310static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4311{
4312 struct ixgbe_hw *hw = &adapter->hw;
4313 int num_tc = netdev_get_num_tc(adapter->netdev);
4314 int i;
4315
4316 if (!num_tc)
4317 num_tc = 1;
4318
9da712d2
JF		 4319 for (i = 0; i < num_tc; i++) {
4320 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4321 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4322
4323 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4324 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4325 hw->fc.low_water[i] = 0;
9da712d2 4326 }
e5776620
JK		 4327
4328 for (; i < MAX_TRAFFIC_CLASS; i++)
4329 hw->fc.high_water[i] = 0;
9da712d2
JF		 4330}
4331
80605c65
JF		 4332static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4333{
80605c65 4334 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4335 int hdrm;
4336 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4337
4338 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4339 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4340 hdrm = 32 << adapter->fdir_pballoc;
4341 else
4342 hdrm = 0;
80605c65 4343
f7e1027f 4344 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4345 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4346}
4347
e4911d57
AD		 4348static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4349{
4350 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4351 struct hlist_node *node2;
e4911d57
AD		 4352 struct ixgbe_fdir_filter *filter;
4353
4354 spin_lock(&adapter->fdir_perfect_lock);
4355
4356 if (!hlist_empty(&adapter->fdir_filter_list))
4357 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4358
b67bfe0d 4359 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4360 &adapter->fdir_filter_list, fdir_node) {
4361 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4362 &filter->filter,
4363 filter->sw_idx,
4364 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4365 IXGBE_FDIR_DROP_QUEUE :
4366 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4367 }
4368
4369 spin_unlock(&adapter->fdir_perfect_lock);
4370}
4371
2a47fa45
JF		 4372static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4373 struct ixgbe_adapter *adapter)
4374{
4375 struct ixgbe_hw *hw = &adapter->hw;
4376 u32 vmolr;
4377
4378 /* No unicast promiscuous support for VMDQ devices. */
4379 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4380 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4381
4382 /* clear the affected bit */
4383 vmolr &= ~IXGBE_VMOLR_MPE;
4384
4385 if (dev->flags & IFF_ALLMULTI) {
4386 vmolr |= IXGBE_VMOLR_MPE;
4387 } else {
4388 vmolr |= IXGBE_VMOLR_ROMPE;
4389 hw->mac.ops.update_mc_addr_list(hw, dev);
4390 }
5d7daa35 4391 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4392 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4393}
4394
2a47fa45
JF		 4395static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4396{
4397 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4398 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4399 struct ixgbe_hw *hw = &adapter->hw;
4400 u16 pool = vadapter->pool;
4401 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4402 IXGBE_PSRTYPE_UDPHDR |
4403 IXGBE_PSRTYPE_IPV4HDR |
4404 IXGBE_PSRTYPE_L2HDR |
4405 IXGBE_PSRTYPE_IPV6HDR;
4406
4407 if (hw->mac.type == ixgbe_mac_82598EB)
4408 return;
4409
4410 if (rss_i > 3)
4411 psrtype |= 2 << 29;
4412 else if (rss_i > 1)
4413 psrtype |= 1 << 29;
4414
4415 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4416}
4417
4418/**
4419 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4420 * @rx_ring: ring to free buffers from
4421 **/
4422static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4423{
4424 struct device *dev = rx_ring->dev;
4425 unsigned long size;
4426 u16 i;
4427
4428 /* ring already cleared, nothing to do */
4429 if (!rx_ring->rx_buffer_info)
4430 return;
4431
4432 /* Free all the Rx ring sk_buffs */
4433 for (i = 0; i < rx_ring->count; i++) {
4434 struct ixgbe_rx_buffer *rx_buffer;
4435
4436 rx_buffer = &rx_ring->rx_buffer_info[i];
4437 if (rx_buffer->skb) {
4438 struct sk_buff *skb = rx_buffer->skb;
4439 if (IXGBE_CB(skb)->page_released) {
4440 dma_unmap_page(dev,
4441 IXGBE_CB(skb)->dma,
4442 ixgbe_rx_bufsz(rx_ring),
4443 DMA_FROM_DEVICE);
4444 IXGBE_CB(skb)->page_released = false;
4445 }
4446 dev_kfree_skb(skb);
4447 }
4448 rx_buffer->skb = NULL;
4449 if (rx_buffer->dma)
4450 dma_unmap_page(dev, rx_buffer->dma,
4451 ixgbe_rx_pg_size(rx_ring),
4452 DMA_FROM_DEVICE);
4453 rx_buffer->dma = 0;
4454 if (rx_buffer->page)
4455 __free_pages(rx_buffer->page,
4456 ixgbe_rx_pg_order(rx_ring));
4457 rx_buffer->page = NULL;
4458 }
4459
4460 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4461 memset(rx_ring->rx_buffer_info, 0, size);
4462
4463 /* Zero out the descriptor ring */
4464 memset(rx_ring->desc, 0, rx_ring->size);
4465
4466 rx_ring->next_to_alloc = 0;
4467 rx_ring->next_to_clean = 0;
4468 rx_ring->next_to_use = 0;
4469}
4470
4471static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4472 struct ixgbe_ring *rx_ring)
4473{
4474 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4475 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4476
4477 /* shutdown specific queue receive and wait for dma to settle */
4478 ixgbe_disable_rx_queue(adapter, rx_ring);
4479 usleep_range(10000, 20000);
4480 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4481 ixgbe_clean_rx_ring(rx_ring);
4482 rx_ring->l2_accel_priv = NULL;
4483}
4484
ae72c8d0
JF		 4485static int ixgbe_fwd_ring_down(struct net_device *vdev,
4486 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4487{
4488 struct ixgbe_adapter *adapter = accel->real_adapter;
4489 unsigned int rxbase = accel->rx_base_queue;
4490 unsigned int txbase = accel->tx_base_queue;
4491 int i;
4492
4493 netif_tx_stop_all_queues(vdev);
4494
4495 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4496 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4497 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4498 }
4499
4500 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4501 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4502 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4503 }
4504
4505
4506 return 0;
4507}
4508
4509static int ixgbe_fwd_ring_up(struct net_device *vdev,
4510 struct ixgbe_fwd_adapter *accel)
4511{
4512 struct ixgbe_adapter *adapter = accel->real_adapter;
4513 unsigned int rxbase, txbase, queues;
4514 int i, baseq, err = 0;
4515
4516 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4517 return 0;
4518
4519 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4520 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4521 accel->pool, adapter->num_rx_pools,
4522 baseq, baseq + adapter->num_rx_queues_per_pool,
4523 adapter->fwd_bitmask);
4524
4525 accel->netdev = vdev;
4526 accel->rx_base_queue = rxbase = baseq;
4527 accel->tx_base_queue = txbase = baseq;
4528
4529 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4530 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4531
4532 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4533 adapter->rx_ring[rxbase + i]->netdev = vdev;
4534 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4535 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4536 }
4537
4538 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4539 adapter->tx_ring[txbase + i]->netdev = vdev;
4540 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4541 }
4542
4543 queues = min_t(unsigned int,
4544 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4545 err = netif_set_real_num_tx_queues(vdev, queues);
4546 if (err)
4547 goto fwd_queue_err;
4548
2a47fa45
JF		 4549 err = netif_set_real_num_rx_queues(vdev, queues);
4550 if (err)
4551 goto fwd_queue_err;
4552
4553 if (is_valid_ether_addr(vdev->dev_addr))
4554 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4555
4556 ixgbe_fwd_psrtype(accel);
4557 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4558 return err;
4559fwd_queue_err:
4560 ixgbe_fwd_ring_down(vdev, accel);
4561 return err;
4562}
4563
4564static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4565{
4566 struct net_device *upper;
4567 struct list_head *iter;
4568 int err;
4569
4570 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4571 if (netif_is_macvlan(upper)) {
4572 struct macvlan_dev *dfwd = netdev_priv(upper);
4573 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4574
4575 if (dfwd->fwd_priv) {
4576 err = ixgbe_fwd_ring_up(upper, vadapter);
4577 if (err)
4578 continue;
4579 }
4580 }
4581 }
4582}
4583
9a799d71
AK		 4584static void ixgbe_configure(struct ixgbe_adapter *adapter)
4585{
d2f5e7f3
AS		 4586 struct ixgbe_hw *hw = &adapter->hw;
4587
80605c65 4588 ixgbe_configure_pb(adapter);
7a6b6f51 4589#ifdef CONFIG_IXGBE_DCB
67ebd791 4590 ixgbe_configure_dcb(adapter);
2f90b865 4591#endif
b35d4d42
AD		 4592 /*
4593 * We must restore virtualization before VLANs or else
4594 * the VLVF registers will not be populated
4595 */
4596 ixgbe_configure_virtualization(adapter);
9a799d71 4597
4c1d7b4b 4598 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4599 ixgbe_restore_vlan(adapter);
4600
d2f5e7f3
AS		 4601 switch (hw->mac.type) {
4602 case ixgbe_mac_82599EB:
4603 case ixgbe_mac_X540:
4604 hw->mac.ops.disable_rx_buff(hw);
4605 break;
4606 default:
4607 break;
4608 }
4609
c4cf55e5 4610 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4611 ixgbe_init_fdir_signature_82599(&adapter->hw,
4612 adapter->fdir_pballoc);
e4911d57
AD		 4613 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4614 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4615 adapter->fdir_pballoc);
4616 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4617 }
4c1d7b4b 4618
d2f5e7f3
AS		 4619 switch (hw->mac.type) {
4620 case ixgbe_mac_82599EB:
4621 case ixgbe_mac_X540:
4622 hw->mac.ops.enable_rx_buff(hw);
4623 break;
4624 default:
4625 break;
4626 }
4627
7c8ae65a
AD		 4628#ifdef IXGBE_FCOE
4629 /* configure FCoE L2 filters, redirection table, and Rx control */
4630 ixgbe_configure_fcoe(adapter);
4631
4632#endif /* IXGBE_FCOE */
9a799d71
AK		 4633 ixgbe_configure_tx(adapter);
4634 ixgbe_configure_rx(adapter);
2a47fa45 4635 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4636}
4637
e8e26350
PW		 4638static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4639{
4640 switch (hw->phy.type) {
4641 case ixgbe_phy_sfp_avago:
4642 case ixgbe_phy_sfp_ftl:
4643 case ixgbe_phy_sfp_intel:
4644 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4645 case ixgbe_phy_sfp_passive_tyco:
4646 case ixgbe_phy_sfp_passive_unknown:
4647 case ixgbe_phy_sfp_active_unknown:
4648 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4649 case ixgbe_phy_qsfp_passive_unknown:
4650 case ixgbe_phy_qsfp_active_unknown:
4651 case ixgbe_phy_qsfp_intel:
4652 case ixgbe_phy_qsfp_unknown:
d9cd46cd
ET		 4653 /* ixgbe_phy_none is set when no SFP module is present */
4654 case ixgbe_phy_none:
e8e26350 4655 return true;
8917b447
AD		 4656 case ixgbe_phy_nl:
4657 if (hw->mac.type == ixgbe_mac_82598EB)
4658 return true;
e8e26350
PW		 4659 default:
4660 return false;
4661 }
4662}
4663
0ecc061d 4664/**
e8e26350
PW		 4665 * ixgbe_sfp_link_config - set up SFP+ link
4666 * @adapter: pointer to private adapter struct
4667 **/
4668static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4669{
7086400d 4670 /*
52f33af8 4671 * We are assuming the worst case scenario here, and that
7086400d
AD		 4672 * is that an SFP was inserted/removed after the reset
4673 * but before SFP detection was enabled. As such the best
4674 * solution is to just start searching as soon as we start
4675 */
4676 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4677 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4678
7086400d 4679 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4680}
4681
4682/**
4683 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4684 * @hw: pointer to private hardware struct
4685 *
4686 * Returns 0 on success, negative on failure
4687 **/
e8e26350 4688static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4689{
3d292265
JH		 4690 u32 speed;
4691 bool autoneg, link_up = false;
0ecc061d
PWJ		 4692 u32 ret = IXGBE_ERR_LINK_SETUP;
4693
4694 if (hw->mac.ops.check_link)
3d292265 4695 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4696
4697 if (ret)
e90dd264 4698 return ret;
0ecc061d 4699
3d292265
JH		 4700 speed = hw->phy.autoneg_advertised;
4701 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4702 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4703 &autoneg);
0ecc061d 4704 if (ret)
e90dd264 4705 return ret;
0ecc061d 4706
8620a103 4707 if (hw->mac.ops.setup_link)
fd0326f2 4708 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4709
0ecc061d
PWJ		 4710 return ret;
4711}
4712
a34bcfff 4713static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4714{
9a799d71 4715 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4716 u32 gpie = 0;
9a799d71 4717
9b471446 4718 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4719 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4720 IXGBE_GPIE_OCD;
4721 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4722 /*
4723 * use EIAM to auto-mask when MSI-X interrupt is asserted
4724 * this saves a register write for every interrupt
4725 */
4726 switch (hw->mac.type) {
4727 case ixgbe_mac_82598EB:
4728 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4729 break;
9b471446 4730 case ixgbe_mac_82599EB:
b93a2226
DS		 4731 case ixgbe_mac_X540:
4732 default:
9b471446
JB		 4733 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4734 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4735 break;
4736 }
4737 } else {
021230d4
AV		 4738 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4739 * specifically only auto mask tx and rx interrupts */
4740 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4741 }
9a799d71 4742
a34bcfff
AD		 4743 /* XXX: to interrupt immediately for EICS writes, enable this */
4744 /* gpie |= IXGBE_GPIE_EIMEN; */
4745
4746 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4747 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4748
4749 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4750 case IXGBE_82599_VMDQ_8Q_MASK:
4751 gpie |= IXGBE_GPIE_VTMODE_16;
4752 break;
4753 case IXGBE_82599_VMDQ_4Q_MASK:
4754 gpie |= IXGBE_GPIE_VTMODE_32;
4755 break;
4756 default:
4757 gpie |= IXGBE_GPIE_VTMODE_64;
4758 break;
4759 }
119fc60a
MC		 4760 }
4761
5fdd31f9 4762 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4763 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4764 switch (adapter->hw.mac.type) {
4765 case ixgbe_mac_82599EB:
4766 gpie |= IXGBE_SDP0_GPIEN;
4767 break;
4768 case ixgbe_mac_X540:
4769 gpie |= IXGBE_EIMS_TS;
4770 break;
4771 default:
4772 break;
4773 }
4774 }
5fdd31f9 4775
a34bcfff
AD		 4776 /* Enable fan failure interrupt */
4777 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4778 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4779
2698b208 4780 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4781 gpie |= IXGBE_SDP1_GPIEN;
4782 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4783 }
a34bcfff
AD		 4784
4785 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4786}
4787
c7ccde0f 4788static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4789{
4790 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4791 int err;
a34bcfff
AD		 4792 u32 ctrl_ext;
4793
4794 ixgbe_get_hw_control(adapter);
4795 ixgbe_setup_gpie(adapter);
e8e26350 4796
9a799d71
AK		 4797 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4798 ixgbe_configure_msix(adapter);
4799 else
4800 ixgbe_configure_msi_and_legacy(adapter);
4801
ec74a471
ET		 4802 /* enable the optics for 82599 SFP+ fiber */
4803 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4804 hw->mac.ops.enable_tx_laser(hw);
4805
4e857c58 4806 smp_mb__before_atomic();
9a799d71 4807 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4808 ixgbe_napi_enable_all(adapter);
4809
73c4b7cd
AD		 4810 if (ixgbe_is_sfp(hw)) {
4811 ixgbe_sfp_link_config(adapter);
4812 } else {
4813 err = ixgbe_non_sfp_link_config(hw);
4814 if (err)
4815 e_err(probe, "link_config FAILED %d\n", err);
4816 }
4817
021230d4
AV		 4818 /* clear any pending interrupts, may auto mask */
4819 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4820 ixgbe_irq_enable(adapter, true, true);
9a799d71 4821
bf069c97
DS		 4822 /*
4823 * If this adapter has a fan, check to see if we had a failure
4824 * before we enabled the interrupt.
4825 */
4826 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4827 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4828 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4829 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4830 }
4831
9a799d71
AK		 4832 /* bring the link up in the watchdog, this could race with our first
4833 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4834 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4835 adapter->link_check_timeout = jiffies;
7086400d 4836 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4837
4838 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4839 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4840 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4841 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4842}
4843
d4f80882
AV		 4844void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4845{
4846 WARN_ON(in_interrupt());
7086400d
AD		 4847 /* put off any impending NetWatchDogTimeout */
4848 adapter->netdev->trans_start = jiffies;
4849
d4f80882 4850 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4851 usleep_range(1000, 2000);
d4f80882 4852 ixgbe_down(adapter);
5809a1ae
GR		 4853 /*
4854 * If SR-IOV enabled then wait a bit before bringing the adapter
4855 * back up to give the VFs time to respond to the reset. The
4856 * two second wait is based upon the watchdog timer cycle in
4857 * the VF driver.
4858 */
4859 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4860 msleep(2000);
d4f80882
AV		 4861 ixgbe_up(adapter);
4862 clear_bit(__IXGBE_RESETTING, &adapter->state);
4863}
4864
c7ccde0f 4865void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4866{
4867 /* hardware has been reset, we need to reload some things */
4868 ixgbe_configure(adapter);
4869
c7ccde0f 4870 ixgbe_up_complete(adapter);
9a799d71
AK		 4871}
4872
4873void ixgbe_reset(struct ixgbe_adapter *adapter)
4874{
c44ade9e 4875 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 4876 struct net_device *netdev = adapter->netdev;
8ca783ab 4877 int err;
5d7daa35 4878 u8 old_addr[ETH_ALEN];
8ca783ab 4879
b0483c8f
MR		 4880 if (ixgbe_removed(hw->hw_addr))
4881 return;
7086400d
AD		 4882 /* lock SFP init bit to prevent race conditions with the watchdog */
4883 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4884 usleep_range(1000, 2000);
4885
4886 /* clear all SFP and link config related flags while holding SFP_INIT */
4887 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4888 IXGBE_FLAG2_SFP_NEEDS_RESET);
4889 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4890
8ca783ab 4891 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4892 switch (err) {
4893 case 0:
4894 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4895 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4896 break;
4897 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4898 e_dev_err("master disable timed out\n");
da4dd0f7 4899 break;
794caeb2
PWJ		 4900 case IXGBE_ERR_EEPROM_VERSION:
4901 /* We are running on a pre-production device, log a warning */
849c4542 4902 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4903 "Please be aware there may be issues associated with "
849c4542
ET		 4904 "your hardware. If you are experiencing problems "
4905 "please contact your Intel or hardware "
4906 "representative who provided you with this "
4907 "hardware.\n");
794caeb2 4908 break;
da4dd0f7 4909 default:
849c4542 4910 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4911 }
9a799d71 4912
7086400d 4913 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 4914 /* do not flush user set addresses */
4915 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4916 ixgbe_flush_sw_mac_table(adapter);
4917 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 4918
4919 /* update SAN MAC vmdq pool selection */
4920 if (hw->mac.san_mac_rar_index)
4921 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4922
8fecf67c 4923 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4924 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4925}
4926
9a799d71
AK		 4927/**
4928 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4929 * @tx_ring: ring to be cleaned
4930 **/
b6ec895e 4931static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4932{
4933 struct ixgbe_tx_buffer *tx_buffer_info;
4934 unsigned long size;
b6ec895e 4935 u16 i;
9a799d71 4936
84418e3b
AD		 4937 /* ring already cleared, nothing to do */
4938 if (!tx_ring->tx_buffer_info)
4939 return;
9a799d71 4940
84418e3b 4941 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4942 for (i = 0; i < tx_ring->count; i++) {
4943 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4944 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4945 }
4946
dad8a3b3
JF		 4947 netdev_tx_reset_queue(txring_txq(tx_ring));
4948
9a799d71
AK		 4949 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4950 memset(tx_ring->tx_buffer_info, 0, size);
4951
4952 /* Zero out the descriptor ring */
4953 memset(tx_ring->desc, 0, tx_ring->size);
4954
4955 tx_ring->next_to_use = 0;
4956 tx_ring->next_to_clean = 0;
9a799d71
AK		 4957}
4958
4959/**
021230d4 4960 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4961 * @adapter: board private structure
4962 **/
021230d4 4963static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4964{
4965 int i;
4966
021230d4 4967 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4968 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4969}
4970
4971/**
021230d4 4972 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4973 * @adapter: board private structure
4974 **/
021230d4 4975static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4976{
4977 int i;
4978
021230d4 4979 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4980 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4981}
4982
e4911d57
AD		 4983static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4984{
b67bfe0d 4985 struct hlist_node *node2;
e4911d57
AD		 4986 struct ixgbe_fdir_filter *filter;
4987
4988 spin_lock(&adapter->fdir_perfect_lock);
4989
b67bfe0d 4990 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4991 &adapter->fdir_filter_list, fdir_node) {
4992 hlist_del(&filter->fdir_node);
4993 kfree(filter);
4994 }
4995 adapter->fdir_filter_count = 0;
4996
4997 spin_unlock(&adapter->fdir_perfect_lock);
4998}
4999
9a799d71
AK		 5000void ixgbe_down(struct ixgbe_adapter *adapter)
5001{
5002 struct net_device *netdev = adapter->netdev;
7f821875 5003 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5004 struct net_device *upper;
5005 struct list_head *iter;
9a799d71 5006 u32 rxctrl;
bf29ee6c 5007 int i;
9a799d71
AK		 5008
5009 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5010 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5011 return; /* do nothing if already down */
9a799d71
AK		 5012
5013 /* disable receives */
7f821875
JB		 5014 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5015 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 5016
2d39d576
YZ		 5017 /* disable all enabled rx queues */
5018 for (i = 0; i < adapter->num_rx_queues; i++)
5019 /* this call also flushes the previous write */
5020 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5021
032b4325 5022 usleep_range(10000, 20000);
9a799d71 5023
7f821875
JB		 5024 netif_tx_stop_all_queues(netdev);
5025
7086400d 5026 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5027 netif_carrier_off(netdev);
5028 netif_tx_disable(netdev);
5029
2a47fa45
JF		 5030 /* disable any upper devices */
5031 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5032 if (netif_is_macvlan(upper)) {
5033 struct macvlan_dev *vlan = netdev_priv(upper);
5034
5035 if (vlan->fwd_priv) {
5036 netif_tx_stop_all_queues(upper);
5037 netif_carrier_off(upper);
5038 netif_tx_disable(upper);
5039 }
5040 }
5041 }
5042
c0dfb90e
JF		 5043 ixgbe_irq_disable(adapter);
5044
5045 ixgbe_napi_disable_all(adapter);
5046
d034acf1
AD		 5047 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5048 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5049 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5050
5051 del_timer_sync(&adapter->service_timer);
5052
34cecbbf 5053 if (adapter->num_vfs) {
8e34d1aa
AD		 5054 /* Clear EITR Select mapping */
5055 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5056
5057 /* Mark all the VFs as inactive */
5058 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5059 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5060
34cecbbf
AD		 5061 /* ping all the active vfs to let them know we are going down */
5062 ixgbe_ping_all_vfs(adapter);
5063
5064 /* Disable all VFTE/VFRE TX/RX */
5065 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5066 }
5067
7f821875
JB		 5068 /* disable transmits in the hardware now that interrupts are off */
5069 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5070 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5071 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5072 }
34cecbbf
AD		 5073
5074 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 5075 switch (hw->mac.type) {
5076 case ixgbe_mac_82599EB:
b93a2226 5077 case ixgbe_mac_X540:
88512539 5078 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5079 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5080 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5081 break;
5082 default:
5083 break;
5084 }
7f821875 5085
6f4a0e45
PL		 5086 if (!pci_channel_offline(adapter->pdev))
5087 ixgbe_reset(adapter);
c6ecf39a 5088
ec74a471
ET		 5089 /* power down the optics for 82599 SFP+ fiber */
5090 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5091 hw->mac.ops.disable_tx_laser(hw);
5092
9a799d71
AK		 5093 ixgbe_clean_all_tx_rings(adapter);
5094 ixgbe_clean_all_rx_rings(adapter);
5095
5dd2d332 5096#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5097 /* since we reset the hardware DCA settings were cleared */
e35ec126 5098 ixgbe_setup_dca(adapter);
96b0e0f6 5099#endif
9a799d71
AK		 5100}
5101
9a799d71
AK		 5102/**
5103 * ixgbe_tx_timeout - Respond to a Tx Hang
5104 * @netdev: network interface device structure
5105 **/
5106static void ixgbe_tx_timeout(struct net_device *netdev)
5107{
5108 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5109
5110 /* Do the reset outside of interrupt context */
c83c6cbd 5111 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5112}
5113
9a799d71
AK		 5114/**
5115 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5116 * @adapter: board private structure to initialize
5117 *
5118 * ixgbe_sw_init initializes the Adapter private data structure.
5119 * Fields are initialized based on PCI device information and
5120 * OS network device settings (MTU size).
5121 **/
9f9a12f8 5122static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5123{
5124 struct ixgbe_hw *hw = &adapter->hw;
5125 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5126 unsigned int rss, fdir;
cb6d0f5e 5127 u32 fwsm;
7a6b6f51 5128#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5129 int j;
5130 struct tc_configuration *tc;
5131#endif
021230d4 5132
c44ade9e
JB		 5133 /* PCI config space info */
5134
5135 hw->vendor_id = pdev->vendor;
5136 hw->device_id = pdev->device;
5137 hw->revision_id = pdev->revision;
5138 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5139 hw->subsystem_device_id = pdev->subsystem_device;
5140
8fc3bb6d 5141 /* Set common capability flags and settings */
3ed69d7e 5142 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5143 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5144 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5145 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5146 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5147 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5148 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5149 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5150 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5151#ifdef CONFIG_IXGBE_DCA
5152 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5153#endif
5154#ifdef IXGBE_FCOE
5155 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5156 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5157#ifdef CONFIG_IXGBE_DCB
5158 /* Default traffic class to use for FCoE */
5159 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5160#endif /* CONFIG_IXGBE_DCB */
5161#endif /* IXGBE_FCOE */
5162
5d7daa35
JK		 5163 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5164 hw->mac.num_rar_entries,
5165 GFP_ATOMIC);
5166
8fc3bb6d 5167 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5168 switch (hw->mac.type) {
5169 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5170 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5171 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5172
bf069c97
DS		 5173 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5174 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5175
49c7ffbe 5176 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5177 adapter->ring_feature[RING_F_FDIR].limit = 0;
5178 adapter->atr_sample_rate = 0;
5179 adapter->fdir_pballoc = 0;
5180#ifdef IXGBE_FCOE
5181 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5182 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5183#ifdef CONFIG_IXGBE_DCB
5184 adapter->fcoe.up = 0;
5185#endif /* IXGBE_DCB */
5186#endif /* IXGBE_FCOE */
5187 break;
5188 case ixgbe_mac_82599EB:
5189 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5190 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5191 break;
b93a2226 5192 case ixgbe_mac_X540:
cb6d0f5e
JK		 5193 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5194 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5195 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 5196 break;
5197 default:
5198 break;
f8212f97 5199 }
2f90b865 5200
7c8ae65a
AD		 5201#ifdef IXGBE_FCOE
5202 /* FCoE support exists, always init the FCoE lock */
5203 spin_lock_init(&adapter->fcoe.lock);
5204
5205#endif
1fc5f038
AD		 5206 /* n-tuple support exists, always init our spinlock */
5207 spin_lock_init(&adapter->fdir_perfect_lock);
5208
7a6b6f51 5209#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5210 switch (hw->mac.type) {
5211 case ixgbe_mac_X540:
5212 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5213 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5214 break;
5215 default:
5216 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5217 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5218 break;
5219 }
5220
2f90b865
AD		 5221 /* Configure DCB traffic classes */
5222 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5223 tc = &adapter->dcb_cfg.tc_config[j];
5224 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5225 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5226 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5227 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5228 tc->dcb_pfc = pfc_disabled;
5229 }
4de2a022
JF		 5230
5231 /* Initialize default user to priority mapping, UPx->TC0 */
5232 tc = &adapter->dcb_cfg.tc_config[0];
5233 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5234 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5235
2f90b865
AD		 5236 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5237 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5238 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5239 adapter->dcb_set_bitmap = 0x00;
3032309b 5240 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5241 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5242 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5243
5244#endif
9a799d71
AK		 5245
5246 /* default flow control settings */
cd7664f6 5247 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5248 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5249 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5250 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5251 hw->fc.send_xon = true;
73d80953 5252 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5253
99d74487 5254#ifdef CONFIG_PCI_IOV
170e8543
JK		 5255 if (max_vfs > 0)
5256 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5257
99d74487 5258 /* assign number of SR-IOV VFs */
170e8543 5259 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5260 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5261 adapter->num_vfs = 0;
5262 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5263 } else {
5264 adapter->num_vfs = max_vfs;
5265 }
5266 }
5267#endif /* CONFIG_PCI_IOV */
99d74487 5268
30efa5a3 5269 /* enable itr by default in dynamic mode */
f7554a2b 5270 adapter->rx_itr_setting = 1;
f7554a2b 5271 adapter->tx_itr_setting = 1;
30efa5a3 5272
30efa5a3
JB		 5273 /* set default ring sizes */
5274 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5275 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5276
bd198058 5277 /* set default work limits */
59224555 5278 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5279
9a799d71 5280 /* initialize eeprom parameters */
c44ade9e 5281 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5282 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5283 return -EIO;
5284 }
5285
2a47fa45
JF		 5286 /* PF holds first pool slot */
5287 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5288 set_bit(__IXGBE_DOWN, &adapter->state);
5289
5290 return 0;
5291}
5292
5293/**
5294 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5295 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5296 *
5297 * Return 0 on success, negative on failure
5298 **/
b6ec895e 5299int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5300{
b6ec895e 5301 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5302 int orig_node = dev_to_node(dev);
5303 int numa_node = -1;
9a799d71
AK		 5304 int size;
5305
3a581073 5306 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5307
5308 if (tx_ring->q_vector)
5309 numa_node = tx_ring->q_vector->numa_node;
5310
5311 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5312 if (!tx_ring->tx_buffer_info)
89bf67f1 5313 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5314 if (!tx_ring->tx_buffer_info)
5315 goto err;
9a799d71 5316
827da44c
JS		 5317 u64_stats_init(&tx_ring->syncp);
5318
9a799d71 5319 /* round up to nearest 4K */
12207e49 5320 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5321 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5322
de88eeeb
AD		 5323 set_dev_node(dev, numa_node);
5324 tx_ring->desc = dma_alloc_coherent(dev,
5325 tx_ring->size,
5326 &tx_ring->dma,
5327 GFP_KERNEL);
5328 set_dev_node(dev, orig_node);
5329 if (!tx_ring->desc)
5330 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5331 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5332 if (!tx_ring->desc)
5333 goto err;
9a799d71 5334
3a581073
JB		 5335 tx_ring->next_to_use = 0;
5336 tx_ring->next_to_clean = 0;
9a799d71 5337 return 0;
e01c31a5
JB		 5338
5339err:
5340 vfree(tx_ring->tx_buffer_info);
5341 tx_ring->tx_buffer_info = NULL;
b6ec895e 5342 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5343 return -ENOMEM;
9a799d71
AK		 5344}
5345
69888674
AD		 5346/**
5347 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5348 * @adapter: board private structure
5349 *
5350 * If this function returns with an error, then it's possible one or
5351 * more of the rings is populated (while the rest are not). It is the
5352 * callers duty to clean those orphaned rings.
5353 *
5354 * Return 0 on success, negative on failure
5355 **/
5356static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5357{
5358 int i, err = 0;
5359
5360 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5361 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5362 if (!err)
5363 continue;
de3d5b94 5364
396e799c 5365 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5366 goto err_setup_tx;
69888674
AD		 5367 }
5368
de3d5b94
AD		 5369 return 0;
5370err_setup_tx:
5371 /* rewind the index freeing the rings as we go */
5372 while (i--)
5373 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5374 return err;
5375}
5376
9a799d71
AK		 5377/**
5378 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5379 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5380 *
5381 * Returns 0 on success, negative on failure
5382 **/
b6ec895e 5383int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5384{
b6ec895e 5385 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5386 int orig_node = dev_to_node(dev);
5387 int numa_node = -1;
021230d4 5388 int size;
9a799d71 5389
3a581073 5390 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5391
5392 if (rx_ring->q_vector)
5393 numa_node = rx_ring->q_vector->numa_node;
5394
5395 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5396 if (!rx_ring->rx_buffer_info)
89bf67f1 5397 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5398 if (!rx_ring->rx_buffer_info)
5399 goto err;
9a799d71 5400
827da44c
JS		 5401 u64_stats_init(&rx_ring->syncp);
5402
9a799d71 5403 /* Round up to nearest 4K */
3a581073
JB		 5404 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5405 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5406
de88eeeb
AD		 5407 set_dev_node(dev, numa_node);
5408 rx_ring->desc = dma_alloc_coherent(dev,
5409 rx_ring->size,
5410 &rx_ring->dma,
5411 GFP_KERNEL);
5412 set_dev_node(dev, orig_node);
5413 if (!rx_ring->desc)
5414 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5415 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5416 if (!rx_ring->desc)
5417 goto err;
9a799d71 5418
3a581073
JB		 5419 rx_ring->next_to_clean = 0;
5420 rx_ring->next_to_use = 0;
9a799d71
AK		 5421
5422 return 0;
b6ec895e
AD		 5423err:
5424 vfree(rx_ring->rx_buffer_info);
5425 rx_ring->rx_buffer_info = NULL;
5426 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5427 return -ENOMEM;
9a799d71
AK		 5428}
5429
69888674
AD		 5430/**
5431 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5432 * @adapter: board private structure
5433 *
5434 * If this function returns with an error, then it's possible one or
5435 * more of the rings is populated (while the rest are not). It is the
5436 * callers duty to clean those orphaned rings.
5437 *
5438 * Return 0 on success, negative on failure
5439 **/
69888674
AD		 5440static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5441{
5442 int i, err = 0;
5443
5444 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5445 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5446 if (!err)
5447 continue;
de3d5b94 5448
396e799c 5449 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5450 goto err_setup_rx;
69888674
AD		 5451 }
5452
7c8ae65a
AD		 5453#ifdef IXGBE_FCOE
5454 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5455 if (!err)
5456#endif
5457 return 0;
de3d5b94
AD		 5458err_setup_rx:
5459 /* rewind the index freeing the rings as we go */
5460 while (i--)
5461 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5462 return err;
5463}
5464
9a799d71
AK		 5465/**
5466 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5467 * @tx_ring: Tx descriptor ring for a specific queue
5468 *
5469 * Free all transmit software resources
5470 **/
b6ec895e 5471void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5472{
b6ec895e 5473 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5474
5475 vfree(tx_ring->tx_buffer_info);
5476 tx_ring->tx_buffer_info = NULL;
5477
b6ec895e
AD		 5478 /* if not set, then don't free */
5479 if (!tx_ring->desc)
5480 return;
5481
5482 dma_free_coherent(tx_ring->dev, tx_ring->size,
5483 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5484
5485 tx_ring->desc = NULL;
5486}
5487
5488/**
5489 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5490 * @adapter: board private structure
5491 *
5492 * Free all transmit software resources
5493 **/
5494static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5495{
5496 int i;
5497
5498 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5499 if (adapter->tx_ring[i]->desc)
b6ec895e 5500 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5501}
5502
5503/**
b4617240 5504 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5505 * @rx_ring: ring to clean the resources from
5506 *
5507 * Free all receive software resources
5508 **/
b6ec895e 5509void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5510{
b6ec895e 5511 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5512
5513 vfree(rx_ring->rx_buffer_info);
5514 rx_ring->rx_buffer_info = NULL;
5515
b6ec895e
AD		 5516 /* if not set, then don't free */
5517 if (!rx_ring->desc)
5518 return;
5519
5520 dma_free_coherent(rx_ring->dev, rx_ring->size,
5521 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5522
5523 rx_ring->desc = NULL;
5524}
5525
5526/**
5527 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5528 * @adapter: board private structure
5529 *
5530 * Free all receive software resources
5531 **/
5532static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5533{
5534 int i;
5535
7c8ae65a
AD		 5536#ifdef IXGBE_FCOE
5537 ixgbe_free_fcoe_ddp_resources(adapter);
5538
5539#endif
9a799d71 5540 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5541 if (adapter->rx_ring[i]->desc)
b6ec895e 5542 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5543}
5544
9a799d71
AK		 5545/**
5546 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5547 * @netdev: network interface device structure
5548 * @new_mtu: new value for maximum frame size
5549 *
5550 * Returns 0 on success, negative on failure
5551 **/
5552static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5553{
5554 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5555 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5556
42c783c5 5557 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5558 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5559 return -EINVAL;
5560
5561 /*
872844dd
AD		 5562 * For 82599EB we cannot allow legacy VFs to enable their receive
5563 * paths when MTU greater than 1500 is configured. So display a
5564 * warning that legacy VFs will be disabled.
655309e9
AD		 5565 */
5566 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5567 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5568 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5569 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5570
396e799c 5571 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5572
021230d4 5573 /* must set new MTU before calling down or up */
9a799d71
AK		 5574 netdev->mtu = new_mtu;
5575
d4f80882
AV		 5576 if (netif_running(netdev))
5577 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5578
5579 return 0;
5580}
5581
5582/**
5583 * ixgbe_open - Called when a network interface is made active
5584 * @netdev: network interface device structure
5585 *
5586 * Returns 0 on success, negative value on failure
5587 *
5588 * The open entry point is called when a network interface is made
5589 * active by the system (IFF_UP). At this point all resources needed
5590 * for transmit and receive operations are allocated, the interrupt
5591 * handler is registered with the OS, the watchdog timer is started,
5592 * and the stack is notified that the interface is ready.
5593 **/
5594static int ixgbe_open(struct net_device *netdev)
5595{
5596 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5597 int err, queues;
4bebfaa5
AK		 5598
5599 /* disallow open during test */
5600 if (test_bit(__IXGBE_TESTING, &adapter->state))
5601 return -EBUSY;
9a799d71 5602
54386467
JB		 5603 netif_carrier_off(netdev);
5604
9a799d71
AK		 5605 /* allocate transmit descriptors */
5606 err = ixgbe_setup_all_tx_resources(adapter);
5607 if (err)
5608 goto err_setup_tx;
5609
9a799d71
AK		 5610 /* allocate receive descriptors */
5611 err = ixgbe_setup_all_rx_resources(adapter);
5612 if (err)
5613 goto err_setup_rx;
5614
5615 ixgbe_configure(adapter);
5616
021230d4 5617 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5618 if (err)
5619 goto err_req_irq;
5620
ac802f5d 5621 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5622 if (adapter->num_rx_pools > 1)
5623 queues = adapter->num_rx_queues_per_pool;
5624 else
5625 queues = adapter->num_tx_queues;
5626
5627 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5628 if (err)
5629 goto err_set_queues;
5630
2a47fa45
JF		 5631 if (adapter->num_rx_pools > 1 &&
5632 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5633 queues = IXGBE_MAX_L2A_QUEUES;
5634 else
5635 queues = adapter->num_rx_queues;
5636 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5637 if (err)
5638 goto err_set_queues;
5639
1a71ab24 5640 ixgbe_ptp_init(adapter);
1a71ab24 5641
c7ccde0f 5642 ixgbe_up_complete(adapter);
9a799d71
AK		 5643
5644 return 0;
5645
ac802f5d
AD		 5646err_set_queues:
5647 ixgbe_free_irq(adapter);
9a799d71 5648err_req_irq:
a20a1199 5649 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5650err_setup_rx:
a20a1199 5651 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5652err_setup_tx:
9a799d71
AK		 5653 ixgbe_reset(adapter);
5654
5655 return err;
5656}
5657
a0cccce2
JK		 5658static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5659{
5660 ixgbe_ptp_suspend(adapter);
5661
5662 ixgbe_down(adapter);
5663 ixgbe_free_irq(adapter);
5664
5665 ixgbe_free_all_tx_resources(adapter);
5666 ixgbe_free_all_rx_resources(adapter);
5667}
5668
9a799d71
AK		 5669/**
5670 * ixgbe_close - Disables a network interface
5671 * @netdev: network interface device structure
5672 *
5673 * Returns 0, this is not allowed to fail
5674 *
5675 * The close entry point is called when an interface is de-activated
5676 * by the OS. The hardware is still under the drivers control, but
5677 * needs to be disabled. A global MAC reset is issued to stop the
5678 * hardware, and all transmit and receive resources are freed.
5679 **/
5680static int ixgbe_close(struct net_device *netdev)
5681{
5682 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5683
1a71ab24 5684 ixgbe_ptp_stop(adapter);
1a71ab24 5685
a0cccce2 5686 ixgbe_close_suspend(adapter);
9a799d71 5687
e4911d57
AD		 5688 ixgbe_fdir_filter_exit(adapter);
5689
5eba3699 5690 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5691
5692 return 0;
5693}
5694
b3c8b4ba
AD		 5695#ifdef CONFIG_PM
5696static int ixgbe_resume(struct pci_dev *pdev)
5697{
c60fbb00
AD		 5698 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5699 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5700 u32 err;
5701
0391bbe3 5702 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5703 pci_set_power_state(pdev, PCI_D0);
5704 pci_restore_state(pdev);
656ab817
DS		 5705 /*
5706 * pci_restore_state clears dev->state_saved so call
5707 * pci_save_state to restore it.
5708 */
5709 pci_save_state(pdev);
9ce77666 5710
5711 err = pci_enable_device_mem(pdev);
b3c8b4ba 5712 if (err) {
849c4542 5713 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5714 return err;
5715 }
4e857c58 5716 smp_mb__before_atomic();
41c62843 5717 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5718 pci_set_master(pdev);
5719
dd4d8ca6 5720 pci_wake_from_d3(pdev, false);
b3c8b4ba 5721
b3c8b4ba
AD		 5722 ixgbe_reset(adapter);
5723
495dce12
WJP		 5724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5725
ac802f5d
AD		 5726 rtnl_lock();
5727 err = ixgbe_init_interrupt_scheme(adapter);
5728 if (!err && netif_running(netdev))
c60fbb00 5729 err = ixgbe_open(netdev);
ac802f5d
AD		 5730
5731 rtnl_unlock();
5732
5733 if (err)
5734 return err;
b3c8b4ba
AD		 5735
5736 netif_device_attach(netdev);
5737
5738 return 0;
5739}
b3c8b4ba 5740#endif /* CONFIG_PM */
9d8d05ae
RW		 5741
5742static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5743{
c60fbb00
AD		 5744 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5745 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5746 struct ixgbe_hw *hw = &adapter->hw;
5747 u32 ctrl, fctrl;
5748 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5749#ifdef CONFIG_PM
5750 int retval = 0;
5751#endif
5752
5753 netif_device_detach(netdev);
5754
499ab5cc 5755 rtnl_lock();
a0cccce2
JK		 5756 if (netif_running(netdev))
5757 ixgbe_close_suspend(adapter);
499ab5cc 5758 rtnl_unlock();
b3c8b4ba 5759
5f5ae6fc
AD		 5760 ixgbe_clear_interrupt_scheme(adapter);
5761
b3c8b4ba
AD		 5762#ifdef CONFIG_PM
5763 retval = pci_save_state(pdev);
5764 if (retval)
5765 return retval;
4df10466 5766
b3c8b4ba 5767#endif
f4f1040a
JK		 5768 if (hw->mac.ops.stop_link_on_d3)
5769 hw->mac.ops.stop_link_on_d3(hw);
5770
e8e26350
PW		 5771 if (wufc) {
5772 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5773
ec74a471
ET		 5774 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5775 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5776 hw->mac.ops.enable_tx_laser(hw);
5777
e8e26350
PW		 5778 /* turn on all-multi mode if wake on multicast is enabled */
5779 if (wufc & IXGBE_WUFC_MC) {
5780 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5781 fctrl |= IXGBE_FCTRL_MPE;
5782 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5783 }
5784
5785 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5786 ctrl |= IXGBE_CTRL_GIO_DIS;
5787 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5788
5789 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5790 } else {
5791 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5792 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5793 }
5794
bd508178
AD		 5795 switch (hw->mac.type) {
5796 case ixgbe_mac_82598EB:
dd4d8ca6 5797 pci_wake_from_d3(pdev, false);
bd508178
AD		 5798 break;
5799 case ixgbe_mac_82599EB:
b93a2226 5800 case ixgbe_mac_X540:
bd508178
AD		 5801 pci_wake_from_d3(pdev, !!wufc);
5802 break;
5803 default:
5804 break;
5805 }
b3c8b4ba 5806
9d8d05ae
RW		 5807 *enable_wake = !!wufc;
5808
b3c8b4ba
AD		 5809 ixgbe_release_hw_control(adapter);
5810
41c62843
MR		 5811 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5812 pci_disable_device(pdev);
b3c8b4ba 5813
9d8d05ae
RW		 5814 return 0;
5815}
5816
5817#ifdef CONFIG_PM
5818static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5819{
5820 int retval;
5821 bool wake;
5822
5823 retval = __ixgbe_shutdown(pdev, &wake);
5824 if (retval)
5825 return retval;
5826
5827 if (wake) {
5828 pci_prepare_to_sleep(pdev);
5829 } else {
5830 pci_wake_from_d3(pdev, false);
5831 pci_set_power_state(pdev, PCI_D3hot);
5832 }
b3c8b4ba
AD		 5833
5834 return 0;
5835}
9d8d05ae 5836#endif /* CONFIG_PM */
b3c8b4ba
AD		 5837
5838static void ixgbe_shutdown(struct pci_dev *pdev)
5839{
9d8d05ae
RW		 5840 bool wake;
5841
5842 __ixgbe_shutdown(pdev, &wake);
5843
5844 if (system_state == SYSTEM_POWER_OFF) {
5845 pci_wake_from_d3(pdev, wake);
5846 pci_set_power_state(pdev, PCI_D3hot);
5847 }
b3c8b4ba
AD		 5848}
5849
9a799d71
AK		 5850/**
5851 * ixgbe_update_stats - Update the board statistics counters.
5852 * @adapter: board private structure
5853 **/
5854void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5855{
2d86f139 5856 struct net_device *netdev = adapter->netdev;
9a799d71 5857 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5858 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5859 u64 total_mpc = 0;
5860 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5861 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5862 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5863 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5864
d08935c2
DS		 5865 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5866 test_bit(__IXGBE_RESETTING, &adapter->state))
5867 return;
5868
94b982b2 5869 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5870 u64 rsc_count = 0;
94b982b2 5871 u64 rsc_flush = 0;
94b982b2 5872 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5873 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5874 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5875 }
5876 adapter->rsc_total_count = rsc_count;
5877 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5878 }
5879
5b7da515
AD		 5880 for (i = 0; i < adapter->num_rx_queues; i++) {
5881 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5882 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5883 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5884 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5885 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5886 bytes += rx_ring->stats.bytes;
5887 packets += rx_ring->stats.packets;
5888 }
5889 adapter->non_eop_descs = non_eop_descs;
5890 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5891 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5892 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5893 netdev->stats.rx_bytes = bytes;
5894 netdev->stats.rx_packets = packets;
5895
5896 bytes = 0;
5897 packets = 0;
7ca3bc58 5898 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5899 for (i = 0; i < adapter->num_tx_queues; i++) {
5900 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5901 restart_queue += tx_ring->tx_stats.restart_queue;
5902 tx_busy += tx_ring->tx_stats.tx_busy;
5903 bytes += tx_ring->stats.bytes;
5904 packets += tx_ring->stats.packets;
5905 }
eb985f09 5906 adapter->restart_queue = restart_queue;
5b7da515
AD		 5907 adapter->tx_busy = tx_busy;
5908 netdev->stats.tx_bytes = bytes;
5909 netdev->stats.tx_packets = packets;
7ca3bc58 5910
7ca647bd 5911 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5912
5913 /* 8 register reads */
6f11eef7
AV		 5914 for (i = 0; i < 8; i++) {
5915 /* for packet buffers not used, the register should read 0 */
5916 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5917 missed_rx += mpc;
7ca647bd
JP		 5918 hwstats->mpc[i] += mpc;
5919 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5920 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5921 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5922 switch (hw->mac.type) {
5923 case ixgbe_mac_82598EB:
1a70db4b
ET		 5924 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5925 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5926 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5927 hwstats->pxonrxc[i] +=
5928 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5929 break;
5930 case ixgbe_mac_82599EB:
b93a2226 5931 case ixgbe_mac_X540:
bd508178
AD		 5932 hwstats->pxonrxc[i] +=
5933 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5934 break;
5935 default:
5936 break;
e8e26350 5937 }
6f11eef7 5938 }
1a70db4b
ET		 5939
5940 /*16 register reads */
5941 for (i = 0; i < 16; i++) {
5942 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5943 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5944 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5945 (hw->mac.type == ixgbe_mac_X540)) {
5946 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5947 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5948 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5949 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5950 }
5951 }
5952
7ca647bd 5953 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5954 /* work around hardware counting issue */
7ca647bd 5955 hwstats->gprc -= missed_rx;
6f11eef7 5956
c84d324c
JF		 5957 ixgbe_update_xoff_received(adapter);
5958
6f11eef7 5959 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5960 switch (hw->mac.type) {
5961 case ixgbe_mac_82598EB:
5962 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5963 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5964 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5965 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5966 break;
b93a2226 5967 case ixgbe_mac_X540:
58f6bcf9
ET		 5968 /* OS2BMC stats are X540 only*/
5969 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5970 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5971 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5972 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5973 case ixgbe_mac_82599EB:
a4d4f629
AD		 5974 for (i = 0; i < 16; i++)
5975 adapter->hw_rx_no_dma_resources +=
5976 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5977 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5978 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5979 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5980 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5981 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5982 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5983 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5984 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5985 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5986#ifdef IXGBE_FCOE
7ca647bd
JP		 5987 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5988 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5989 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5990 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5991 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5992 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5993 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5994 if (adapter->fcoe.ddp_pool) {
5995 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5996 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5997 unsigned int cpu;
5998 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5999 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6000 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6001 noddp += ddp_pool->noddp;
6002 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6003 }
5a1ee270
AD		 6004 hwstats->fcoe_noddp = noddp;
6005 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6006 }
6d45522c 6007#endif /* IXGBE_FCOE */
bd508178
AD		 6008 break;
6009 default:
6010 break;
e8e26350 6011 }
9a799d71 6012 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6013 hwstats->bprc += bprc;
6014 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6015 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6016 hwstats->mprc -= bprc;
6017 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6018 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6019 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6020 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6021 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6022 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6023 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6024 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6025 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6026 hwstats->lxontxc += lxon;
6f11eef7 6027 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6028 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6029 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6030 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6031 /*
6032 * 82598 errata - tx of flow control packets is included in tx counters
6033 */
6034 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6035 hwstats->gptc -= xon_off_tot;
6036 hwstats->mptc -= xon_off_tot;
6037 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6038 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6039 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6040 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6041 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6042 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6043 hwstats->ptc64 -= xon_off_tot;
6044 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6045 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6046 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6047 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6048 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6049 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6050
6051 /* Fill out the OS statistics structure */
7ca647bd 6052 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6053
6054 /* Rx Errors */
7ca647bd 6055 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6056 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6057 netdev->stats.rx_length_errors = hwstats->rlec;
6058 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6059 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6060}
6061
6062/**
d034acf1 6063 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6064 * @adapter: pointer to the device adapter structure
9a799d71 6065 **/
d034acf1 6066static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6067{
cf8280ee 6068 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6069 int i;
cf8280ee 6070
d034acf1
AD		 6071 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6072 return;
6073
6074 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6075
d034acf1 6076 /* if interface is down do nothing */
fe49f04a 6077 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6078 return;
6079
6080 /* do nothing if we are not using signature filters */
6081 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6082 return;
6083
6084 adapter->fdir_overflow++;
6085
93c52dd0
AD		 6086 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6087 for (i = 0; i < adapter->num_tx_queues; i++)
6088 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6089 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6090 /* re-enable flow director interrupts */
6091 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6092 } else {
6093 e_err(probe, "failed to finish FDIR re-initialization, "
6094 "ignored adding FDIR ATR filters\n");
6095 }
93c52dd0
AD		 6096}
6097
6098/**
6099 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6100 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6101 *
6102 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6103 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6104 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6105 * determine if a hang has occurred.
93c52dd0
AD		 6106 */
6107static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6108{
cf8280ee 6109 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6110 u64 eics = 0;
6111 int i;
cf8280ee 6112
09f40aed 6113 /* If we're down, removing or resetting, just bail */
93c52dd0 6114 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6115 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6116 test_bit(__IXGBE_RESETTING, &adapter->state))
6117 return;
22d5a71b 6118
93c52dd0
AD		 6119 /* Force detection of hung controller */
6120 if (netif_carrier_ok(adapter->netdev)) {
6121 for (i = 0; i < adapter->num_tx_queues; i++)
6122 set_check_for_tx_hang(adapter->tx_ring[i]);
6123 }
22d5a71b 6124
fe49f04a
AD		 6125 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6126 /*
6127 * for legacy and MSI interrupts don't set any bits
6128 * that are enabled for EIAM, because this operation
6129 * would set *both* EIMS and EICS for any bit in EIAM
6130 */
6131 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6132 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6133 } else {
6134 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6135 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6136 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6137 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6138 eics |= ((u64)1 << i);
6139 }
cf8280ee 6140 }
9a799d71 6141
93c52dd0 6142 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6143 ixgbe_irq_rearm_queues(adapter, eics);
6144
cf8280ee
JB		 6145}
6146
e8e26350 6147/**
93c52dd0 6148 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6149 * @adapter: pointer to the device adapter structure
6150 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6151 **/
93c52dd0 6152static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6153{
e8e26350 6154 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6155 u32 link_speed = adapter->link_speed;
6156 bool link_up = adapter->link_up;
041441d0 6157 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6158
93c52dd0
AD		 6159 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6160 return;
6161
6162 if (hw->mac.ops.check_link) {
6163 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6164 } else {
93c52dd0
AD		 6165 /* always assume link is up, if no check link function */
6166 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6167 link_up = true;
c4cf55e5 6168 }
041441d0
AD		 6169
6170 if (adapter->ixgbe_ieee_pfc)
6171 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6172
3ebe8fde 6173 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6174 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6175 ixgbe_set_rx_drop_en(adapter);
6176 }
93c52dd0
AD		 6177
6178 if (link_up ||
6179 time_after(jiffies, (adapter->link_check_timeout +
6180 IXGBE_TRY_LINK_TIMEOUT))) {
6181 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6182 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6183 IXGBE_WRITE_FLUSH(hw);
6184 }
6185
6186 adapter->link_up = link_up;
6187 adapter->link_speed = link_speed;
e8e26350
PW		 6188}
6189
107d3018
AD		 6190static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6191{
6192#ifdef CONFIG_IXGBE_DCB
6193 struct net_device *netdev = adapter->netdev;
6194 struct dcb_app app = {
6195 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6196 .protocol = 0,
6197 };
6198 u8 up = 0;
6199
6200 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6201 up = dcb_ieee_getapp_mask(netdev, &app);
6202
6203 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6204#endif
6205}
6206
e8e26350 6207/**
93c52dd0
AD		 6208 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6209 * print link up message
49ce9c2c 6210 * @adapter: pointer to the device adapter structure
e8e26350 6211 **/
93c52dd0 6212static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6213{
93c52dd0 6214 struct net_device *netdev = adapter->netdev;
e8e26350 6215 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6216 struct net_device *upper;
6217 struct list_head *iter;
93c52dd0
AD		 6218 u32 link_speed = adapter->link_speed;
6219 bool flow_rx, flow_tx;
e8e26350 6220
93c52dd0
AD		 6221 /* only continue if link was previously down */
6222 if (netif_carrier_ok(netdev))
a985b6c3 6223 return;
63d6e1d8 6224
93c52dd0 6225 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6226
93c52dd0
AD		 6227 switch (hw->mac.type) {
6228 case ixgbe_mac_82598EB: {
6229 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6230 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6231 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6232 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6233 }
6234 break;
6235 case ixgbe_mac_X540:
6236 case ixgbe_mac_82599EB: {
6237 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6238 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6239 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6240 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6241 }
6242 break;
6243 default:
6244 flow_tx = false;
6245 flow_rx = false;
6246 break;
e8e26350 6247 }
3a6a4eda 6248
6cb562d6
JK		 6249 adapter->last_rx_ptp_check = jiffies;
6250
8fecf67c 6251 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6252 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6253
93c52dd0
AD		 6254 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6255 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6256 "10 Gbps" :
6257 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6258 "1 Gbps" :
6259 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6260 "100 Mbps" :
6261 "unknown speed"))),
6262 ((flow_rx && flow_tx) ? "RX/TX" :
6263 (flow_rx ? "RX" :
6264 (flow_tx ? "TX" : "None"))));
e8e26350 6265
93c52dd0 6266 netif_carrier_on(netdev);
93c52dd0 6267 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6268
cdc04dcc
ET		 6269 /* enable transmits */
6270 netif_tx_wake_all_queues(adapter->netdev);
6271
6272 /* enable any upper devices */
6273 rtnl_lock();
6274 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6275 if (netif_is_macvlan(upper)) {
6276 struct macvlan_dev *vlan = netdev_priv(upper);
6277
6278 if (vlan->fwd_priv)
6279 netif_tx_wake_all_queues(upper);
6280 }
6281 }
6282 rtnl_unlock();
6283
107d3018
AD		 6284 /* update the default user priority for VFs */
6285 ixgbe_update_default_up(adapter);
6286
befa2af7
AD		 6287 /* ping all the active vfs to let them know link has changed */
6288 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6289}
6290
c4cf55e5 6291/**
93c52dd0
AD		 6292 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6293 * print link down message
49ce9c2c 6294 * @adapter: pointer to the adapter structure
c4cf55e5 6295 **/
581330ba 6296static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6297{
cf8280ee 6298 struct net_device *netdev = adapter->netdev;
c4cf55e5 6299 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6300
93c52dd0
AD		 6301 adapter->link_up = false;
6302 adapter->link_speed = 0;
cf8280ee 6303
93c52dd0
AD		 6304 /* only continue if link was up previously */
6305 if (!netif_carrier_ok(netdev))
6306 return;
264857b8 6307
93c52dd0
AD		 6308 /* poll for SFP+ cable when link is down */
6309 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6310 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6311
8fecf67c 6312 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6313 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6314
93c52dd0
AD		 6315 e_info(drv, "NIC Link is Down\n");
6316 netif_carrier_off(netdev);
befa2af7
AD		 6317
6318 /* ping all the active vfs to let them know link has changed */
6319 ixgbe_ping_all_vfs(adapter);
93c52dd0 6320}
e8e26350 6321
07923c17
ET		 6322static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6323{
6324 int i;
6325
6326 for (i = 0; i < adapter->num_tx_queues; i++) {
6327 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6328
6329 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6330 return true;
6331 }
6332
6333 return false;
6334}
6335
6336static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6337{
6338 struct ixgbe_hw *hw = &adapter->hw;
6339 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6340 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6341
6342 int i, j;
6343
6344 if (!adapter->num_vfs)
6345 return false;
6346
6347 for (i = 0; i < adapter->num_vfs; i++) {
6348 for (j = 0; j < q_per_pool; j++) {
6349 u32 h, t;
6350
6351 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6352 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6353
6354 if (h != t)
6355 return true;
6356 }
6357 }
6358
6359 return false;
6360}
6361
93c52dd0
AD		 6362/**
6363 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6364 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6365 **/
6366static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6367{
93c52dd0 6368 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6369 if (ixgbe_ring_tx_pending(adapter) ||
6370 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6371 /* We've lost link, so the controller stops DMA,
6372 * but we've got queued Tx work that's never going
6373 * to get done, so reset controller to flush Tx.
6374 * (Do the reset outside of interrupt context).
6375 */
12ff3f3b 6376 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6377 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6378 }
c4cf55e5 6379 }
c4cf55e5
PWJ		 6380}
6381
a985b6c3
GR		 6382static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6383{
6384 u32 ssvpc;
6385
0584d999
GR		 6386 /* Do not perform spoof check for 82598 or if not in IOV mode */
6387 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6388 adapter->num_vfs == 0)
a985b6c3
GR		 6389 return;
6390
6391 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6392
6393 /*
6394 * ssvpc register is cleared on read, if zero then no
6395 * spoofed packets in the last interval.
6396 */
6397 if (!ssvpc)
6398 return;
6399
d6ea0754 6400 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6401}
6402
93c52dd0
AD		 6403/**
6404 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6405 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6406 **/
6407static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6408{
09f40aed 6409 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6410 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6411 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6412 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6413 return;
6414
6415 ixgbe_watchdog_update_link(adapter);
6416
6417 if (adapter->link_up)
6418 ixgbe_watchdog_link_is_up(adapter);
6419 else
6420 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6421
a985b6c3 6422 ixgbe_spoof_check(adapter);
9a799d71 6423 ixgbe_update_stats(adapter);
93c52dd0
AD		 6424
6425 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6426}
10eec955 6427
cf8280ee 6428/**
7086400d 6429 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6430 * @adapter: the ixgbe adapter structure
cf8280ee 6431 **/
7086400d 6432static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6433{
cf8280ee 6434 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6435 s32 err;
cf8280ee 6436
7086400d
AD		 6437 /* not searching for SFP so there is nothing to do here */
6438 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6439 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6440 return;
10eec955 6441
7086400d
AD		 6442 /* someone else is in init, wait until next service event */
6443 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6444 return;
cf8280ee 6445
7086400d
AD		 6446 err = hw->phy.ops.identify_sfp(hw);
6447 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6448 goto sfp_out;
264857b8 6449
7086400d
AD		 6450 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6451 /* If no cable is present, then we need to reset
6452 * the next time we find a good cable. */
6453 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6454 }
9a799d71 6455
7086400d
AD		 6456 /* exit on error */
6457 if (err)
6458 goto sfp_out;
e8e26350 6459
7086400d
AD		 6460 /* exit if reset not needed */
6461 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6462 goto sfp_out;
9a799d71 6463
7086400d 6464 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6465
7086400d
AD		 6466 /*
6467 * A module may be identified correctly, but the EEPROM may not have
6468 * support for that module. setup_sfp() will fail in that case, so
6469 * we should not allow that module to load.
6470 */
6471 if (hw->mac.type == ixgbe_mac_82598EB)
6472 err = hw->phy.ops.reset(hw);
6473 else
6474 err = hw->mac.ops.setup_sfp(hw);
6475
6476 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6477 goto sfp_out;
6478
6479 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6480 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6481
6482sfp_out:
6483 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6484
6485 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6486 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6487 e_dev_err("failed to initialize because an unsupported "
6488 "SFP+ module type was detected.\n");
6489 e_dev_err("Reload the driver after installing a "
6490 "supported module.\n");
6491 unregister_netdev(adapter->netdev);
bc59fcda 6492 }
7086400d 6493}
bc59fcda 6494
7086400d
AD		 6495/**
6496 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6497 * @adapter: the ixgbe adapter structure
7086400d
AD		 6498 **/
6499static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6500{
6501 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6502 u32 speed;
6503 bool autoneg = false;
7086400d
AD		 6504
6505 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6506 return;
6507
6508 /* someone else is in init, wait until next service event */
6509 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6510 return;
6511
6512 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6513
3d292265 6514 speed = hw->phy.autoneg_advertised;
ed33ff66 6515 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6516 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6517
6518 /* setup the highest link when no autoneg */
6519 if (!autoneg) {
6520 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6521 speed = IXGBE_LINK_SPEED_10GB_FULL;
6522 }
6523 }
6524
7086400d 6525 if (hw->mac.ops.setup_link)
fd0326f2 6526 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6527
6528 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6529 adapter->link_check_timeout = jiffies;
6530 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6531}
6532
83c61fa9
GR		 6533#ifdef CONFIG_PCI_IOV
6534static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6535{
6536 int vf;
6537 struct ixgbe_hw *hw = &adapter->hw;
6538 struct net_device *netdev = adapter->netdev;
6539 u32 gpc;
6540 u32 ciaa, ciad;
6541
6542 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6543 if (gpc) /* If incrementing then no need for the check below */
6544 return;
6545 /*
6546 * Check to see if a bad DMA write target from an errant or
6547 * malicious VF has caused a PCIe error. If so then we can
6548 * issue a VFLR to the offending VF(s) and then resume without
6549 * requesting a full slot reset.
6550 */
6551
6552 for (vf = 0; vf < adapter->num_vfs; vf++) {
6553 ciaa = (vf << 16) | 0x80000000;
6554 /* 32 bit read so align, we really want status at offset 6 */
6555 ciaa |= PCI_COMMAND;
6556 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6557 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6558 ciaa &= 0x7FFFFFFF;
6559 /* disable debug mode asap after reading data */
6560 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6561 /* Get the upper 16 bits which will be the PCI status reg */
6562 ciad >>= 16;
6563 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6564 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6565 /* Issue VFLR */
6566 ciaa = (vf << 16) | 0x80000000;
6567 ciaa |= 0xA8;
6568 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6569 ciad = 0x00008000; /* VFLR */
6570 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6571 ciaa &= 0x7FFFFFFF;
6572 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6573 }
6574 }
6575}
6576
6577#endif
7086400d
AD		 6578/**
6579 * ixgbe_service_timer - Timer Call-back
6580 * @data: pointer to adapter cast into an unsigned long
6581 **/
6582static void ixgbe_service_timer(unsigned long data)
6583{
6584 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6585 unsigned long next_event_offset;
83c61fa9 6586 bool ready = true;
7086400d 6587
6bb78cfb
AD		 6588 /* poll faster when waiting for link */
6589 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6590 next_event_offset = HZ / 10;
6591 else
6592 next_event_offset = HZ * 2;
83c61fa9 6593
6bb78cfb 6594#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6595 /*
6596 * don't bother with SR-IOV VF DMA hang check if there are
6597 * no VFs or the link is down
6598 */
6599 if (!adapter->num_vfs ||
6bb78cfb 6600 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6601 goto normal_timer_service;
83c61fa9
GR		 6602
6603 /* If we have VFs allocated then we must check for DMA hangs */
6604 ixgbe_check_for_bad_vf(adapter);
6605 next_event_offset = HZ / 50;
6606 adapter->timer_event_accumulator++;
6607
6bb78cfb 6608 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6609 adapter->timer_event_accumulator = 0;
7086400d 6610 else
6bb78cfb 6611 ready = false;
7086400d 6612
6bb78cfb 6613normal_timer_service:
83c61fa9 6614#endif
7086400d
AD		 6615 /* Reset the timer */
6616 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6617
83c61fa9
GR		 6618 if (ready)
6619 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6620}
6621
c83c6cbd
AD		 6622static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6623{
6624 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6625 return;
6626
6627 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6628
09f40aed 6629 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6630 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6631 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6632 test_bit(__IXGBE_RESETTING, &adapter->state))
6633 return;
6634
6635 ixgbe_dump(adapter);
6636 netdev_err(adapter->netdev, "Reset adapter\n");
6637 adapter->tx_timeout_count++;
6638
8f4c5c9f 6639 rtnl_lock();
c83c6cbd 6640 ixgbe_reinit_locked(adapter);
8f4c5c9f 6641 rtnl_unlock();
c83c6cbd
AD		 6642}
6643
7086400d
AD		 6644/**
6645 * ixgbe_service_task - manages and runs subtasks
6646 * @work: pointer to work_struct containing our data
6647 **/
6648static void ixgbe_service_task(struct work_struct *work)
6649{
6650 struct ixgbe_adapter *adapter = container_of(work,
6651 struct ixgbe_adapter,
6652 service_task);
b0483c8f
MR		 6653 if (ixgbe_removed(adapter->hw.hw_addr)) {
6654 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6655 rtnl_lock();
6656 ixgbe_down(adapter);
6657 rtnl_unlock();
6658 }
6659 ixgbe_service_event_complete(adapter);
6660 return;
6661 }
c83c6cbd 6662 ixgbe_reset_subtask(adapter);
7086400d
AD		 6663 ixgbe_sfp_detection_subtask(adapter);
6664 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6665 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6666 ixgbe_watchdog_subtask(adapter);
d034acf1 6667 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6668 ixgbe_check_hang_subtask(adapter);
891dc082 6669
8fecf67c 6670 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6671 ixgbe_ptp_overflow_check(adapter);
6672 ixgbe_ptp_rx_hang(adapter);
6673 }
7086400d
AD		 6674
6675 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6676}
6677
fd0db0ed
AD		 6678static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6679 struct ixgbe_tx_buffer *first,
244e27ad 6680 u8 *hdr_len)
897ab156 6681{
fd0db0ed 6682 struct sk_buff *skb = first->skb;
897ab156
AD		 6683 u32 vlan_macip_lens, type_tucmd;
6684 u32 mss_l4len_idx, l4len;
2049e1f6 6685 int err;
9a799d71 6686
8f4fbb9b
AD		 6687 if (skb->ip_summed != CHECKSUM_PARTIAL)
6688 return 0;
6689
897ab156
AD		 6690 if (!skb_is_gso(skb))
6691 return 0;
9a799d71 6692
2049e1f6
FR		 6693 err = skb_cow_head(skb, 0);
6694 if (err < 0)
6695 return err;
9a799d71 6696
897ab156
AD		 6697 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6698 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6699
a1108ffd 6700 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6701 struct iphdr *iph = ip_hdr(skb);
6702 iph->tot_len = 0;
6703 iph->check = 0;
6704 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6705 iph->daddr, 0,
6706 IPPROTO_TCP,
6707 0);
6708 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6709 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6710 IXGBE_TX_FLAGS_CSUM |
6711 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6712 } else if (skb_is_gso_v6(skb)) {
6713 ipv6_hdr(skb)->payload_len = 0;
6714 tcp_hdr(skb)->check =
6715 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6716 &ipv6_hdr(skb)->daddr,
6717 0, IPPROTO_TCP, 0);
244e27ad
AD		 6718 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6719 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6720 }
6721
091a6246 6722 /* compute header lengths */
897ab156
AD		 6723 l4len = tcp_hdrlen(skb);
6724 *hdr_len = skb_transport_offset(skb) + l4len;
6725
091a6246
AD		 6726 /* update gso size and bytecount with header size */
6727 first->gso_segs = skb_shinfo(skb)->gso_segs;
6728 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6729
c44f5f51 6730 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6731 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6732 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6733
6734 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6735 vlan_macip_lens = skb_network_header_len(skb);
6736 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6737 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6738
6739 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6740 mss_l4len_idx);
897ab156
AD		 6741
6742 return 1;
6743}
6744
244e27ad
AD		 6745static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6746 struct ixgbe_tx_buffer *first)
7ca647bd 6747{
fd0db0ed 6748 struct sk_buff *skb = first->skb;
897ab156
AD		 6749 u32 vlan_macip_lens = 0;
6750 u32 mss_l4len_idx = 0;
6751 u32 type_tucmd = 0;
7ca647bd 6752
897ab156 6753 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6754 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6755 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6756 return;
897ab156
AD		 6757 } else {
6758 u8 l4_hdr = 0;
244e27ad 6759 switch (first->protocol) {
a1108ffd 6760 case htons(ETH_P_IP):
897ab156
AD		 6761 vlan_macip_lens |= skb_network_header_len(skb);
6762 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6763 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6764 break;
a1108ffd 6765 case htons(ETH_P_IPV6):
897ab156
AD		 6766 vlan_macip_lens |= skb_network_header_len(skb);
6767 l4_hdr = ipv6_hdr(skb)->nexthdr;
6768 break;
6769 default:
6770 if (unlikely(net_ratelimit())) {
6771 dev_warn(tx_ring->dev,
6772 "partial checksum but proto=%x!\n",
244e27ad 6773 first->protocol);
897ab156 6774 }
7ca647bd
JP		 6775 break;
6776 }
897ab156
AD		 6777
6778 switch (l4_hdr) {
7ca647bd 6779 case IPPROTO_TCP:
897ab156
AD		 6780 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6781 mss_l4len_idx = tcp_hdrlen(skb) <<
6782 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6783 break;
6784 case IPPROTO_SCTP:
897ab156
AD		 6785 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6786 mss_l4len_idx = sizeof(struct sctphdr) <<
6787 IXGBE_ADVTXD_L4LEN_SHIFT;
6788 break;
6789 case IPPROTO_UDP:
6790 mss_l4len_idx = sizeof(struct udphdr) <<
6791 IXGBE_ADVTXD_L4LEN_SHIFT;
6792 break;
6793 default:
6794 if (unlikely(net_ratelimit())) {
6795 dev_warn(tx_ring->dev,
6796 "partial checksum but l4 proto=%x!\n",
244e27ad 6797 l4_hdr);
897ab156 6798 }
7ca647bd
JP		 6799 break;
6800 }
244e27ad
AD		 6801
6802 /* update TX checksum flag */
6803 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6804 }
6805
244e27ad 6806 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6807 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6808 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6809
897ab156
AD		 6810 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6811 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6812}
6813
472148c3
AD		 6814#define IXGBE_SET_FLAG(_input, _flag, _result) \
6815 ((_flag <= _result) ? \
6816 ((u32)(_input & _flag) * (_result / _flag)) : \
6817 ((u32)(_input & _flag) / (_flag / _result)))
6818
6819static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6820{
d3d00239 6821 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6822 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6823 IXGBE_ADVTXD_DCMD_DEXT |
6824 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6825
d3d00239 6826 /* set HW vlan bit if vlan is present */
472148c3
AD		 6827 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6828 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6829
d3d00239 6830 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6831 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6832 IXGBE_ADVTXD_DCMD_TSE);
6833
6834 /* set timestamp bit if present */
6835 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6836 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6837
62748b7b 6838 /* insert frame checksum */
472148c3 6839 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6840
d3d00239
AD		 6841 return cmd_type;
6842}
9a799d71 6843
729739b7
AD		 6844static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6845 u32 tx_flags, unsigned int paylen)
d3d00239 6846{
472148c3 6847 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6848
d3d00239 6849 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6850 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6851 IXGBE_TX_FLAGS_CSUM,
6852 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6853
93f5b3c1 6854 /* enble IPv4 checksum for TSO */
472148c3
AD		 6855 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6856 IXGBE_TX_FLAGS_IPV4,
6857 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6858
7f9643fd
AD		 6859 /*
6860 * Check Context must be set if Tx switch is enabled, which it
6861 * always is for case where virtual functions are running
6862 */
472148c3
AD		 6863 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6864 IXGBE_TX_FLAGS_CC,
6865 IXGBE_ADVTXD_CC);
7f9643fd 6866
472148c3 6867 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6868}
44df32c5 6869
2367a173
DB		 6870static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6871{
6872 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6873
6874 /* Herbert's original patch had:
6875 * smp_mb__after_netif_stop_queue();
6876 * but since that doesn't exist yet, just open code it.
6877 */
6878 smp_mb();
6879
6880 /* We need to check again in a case another CPU has just
6881 * made room available.
6882 */
6883 if (likely(ixgbe_desc_unused(tx_ring) < size))
6884 return -EBUSY;
6885
6886 /* A reprieve! - use start_queue because it doesn't call schedule */
6887 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6888 ++tx_ring->tx_stats.restart_queue;
6889 return 0;
6890}
6891
6892static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6893{
6894 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6895 return 0;
6896
6897 return __ixgbe_maybe_stop_tx(tx_ring, size);
6898}
6899
d3d00239
AD		 6900#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6901 IXGBE_TXD_CMD_RS)
6902
6903static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6904 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6905 const u8 hdr_len)
6906{
fd0db0ed 6907 struct sk_buff *skb = first->skb;
729739b7 6908 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6909 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6910 struct skb_frag_struct *frag;
6911 dma_addr_t dma;
6912 unsigned int data_len, size;
244e27ad 6913 u32 tx_flags = first->tx_flags;
472148c3 6914 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6915 u16 i = tx_ring->next_to_use;
d3d00239 6916
729739b7
AD		 6917 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6918
ec718254
AD		 6919 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6920
6921 size = skb_headlen(skb);
6922 data_len = skb->data_len;
729739b7 6923
d3d00239
AD		 6924#ifdef IXGBE_FCOE
6925 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6926 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6927 size -= sizeof(struct fcoe_crc_eof) - data_len;
6928 data_len = 0;
729739b7
AD		 6929 } else {
6930 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6931 }
6932 }
44df32c5 6933
d3d00239 6934#endif
729739b7 6935 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6936
ec718254 6937 tx_buffer = first;
9a799d71 6938
ec718254
AD		 6939 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6940 if (dma_mapping_error(tx_ring->dev, dma))
6941 goto dma_error;
6942
6943 /* record length, and DMA address */
6944 dma_unmap_len_set(tx_buffer, len, size);
6945 dma_unmap_addr_set(tx_buffer, dma, dma);
6946
6947 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6948
729739b7 6949 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6950 tx_desc->read.cmd_type_len =
472148c3 6951 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6952
d3d00239 6953 i++;
729739b7 6954 tx_desc++;
d3d00239 6955 if (i == tx_ring->count) {
e4f74028 6956 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6957 i = 0;
6958 }
ec718254 6959 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6960
6961 dma += IXGBE_MAX_DATA_PER_TXD;
6962 size -= IXGBE_MAX_DATA_PER_TXD;
6963
6964 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6965 }
e5a43549 6966
729739b7
AD		 6967 if (likely(!data_len))
6968 break;
9a799d71 6969
472148c3 6970 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6971
729739b7
AD		 6972 i++;
6973 tx_desc++;
6974 if (i == tx_ring->count) {
6975 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6976 i = 0;
6977 }
ec718254 6978 tx_desc->read.olinfo_status = 0;
9a799d71 6979
d3d00239 6980#ifdef IXGBE_FCOE
9e903e08 6981 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6982#else
9e903e08 6983 size = skb_frag_size(frag);
d3d00239
AD		 6984#endif
6985 data_len -= size;
9a799d71 6986
729739b7
AD		 6987 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6988 DMA_TO_DEVICE);
9a799d71 6989
729739b7 6990 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6991 }
9a799d71 6992
729739b7 6993 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6994 cmd_type |= size | IXGBE_TXD_CMD;
6995 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6996
091a6246 6997 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6998
d3d00239
AD		 6999 /* set the timestamp */
7000 first->time_stamp = jiffies;
9a799d71
AK		 7001
7002 /*
729739b7
AD		 7003 * Force memory writes to complete before letting h/w know there
7004 * are new descriptors to fetch. (Only applicable for weak-ordered
7005 * memory model archs, such as IA-64).
7006 *
7007 * We also need this memory barrier to make certain all of the
7008 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7009 */
7010 wmb();
7011
d3d00239
AD		 7012 /* set next_to_watch value indicating a packet is present */
7013 first->next_to_watch = tx_desc;
7014
729739b7
AD		 7015 i++;
7016 if (i == tx_ring->count)
7017 i = 0;
7018
7019 tx_ring->next_to_use = i;
7020
2367a173
DB		 7021 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7022
7023 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
9c938cdd
DB		 7024 /* notify HW of packet */
7025 ixgbe_write_tail(tx_ring, i);
7026 }
2367a173 7027
d3d00239
AD		 7028 return;
7029dma_error:
729739b7 7030 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7031
7032 /* clear dma mappings for failed tx_buffer_info map */
7033 for (;;) {
729739b7
AD		 7034 tx_buffer = &tx_ring->tx_buffer_info[i];
7035 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7036 if (tx_buffer == first)
d3d00239
AD		 7037 break;
7038 if (i == 0)
7039 i = tx_ring->count;
7040 i--;
7041 }
7042
d3d00239 7043 tx_ring->next_to_use = i;
9a799d71
AK		 7044}
7045
fd0db0ed 7046static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7047 struct ixgbe_tx_buffer *first)
69830529
AD		 7048{
7049 struct ixgbe_q_vector *q_vector = ring->q_vector;
7050 union ixgbe_atr_hash_dword input = { .dword = 0 };
7051 union ixgbe_atr_hash_dword common = { .dword = 0 };
7052 union {
7053 unsigned char *network;
7054 struct iphdr *ipv4;
7055 struct ipv6hdr *ipv6;
7056 } hdr;
ee9e0f0b 7057 struct tcphdr *th;
905e4a41 7058 __be16 vlan_id;
c4cf55e5 7059
69830529
AD		 7060 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7061 if (!q_vector)
7062 return;
7063
7064 /* do nothing if sampling is disabled */
7065 if (!ring->atr_sample_rate)
d3ead241 7066 return;
c4cf55e5 7067
69830529 7068 ring->atr_count++;
c4cf55e5 7069
69830529 7070 /* snag network header to get L4 type and address */
fd0db0ed 7071 hdr.network = skb_network_header(first->skb);
69830529
AD		 7072
7073 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 7074 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 7075 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 7076 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 7077 hdr.ipv4->protocol != IPPROTO_TCP))
7078 return;
ee9e0f0b 7079
fd0db0ed 7080 th = tcp_hdr(first->skb);
c4cf55e5 7081
66f32a8b
AD		 7082 /* skip this packet since it is invalid or the socket is closing */
7083 if (!th || th->fin)
69830529
AD		 7084 return;
7085
7086 /* sample on all syn packets or once every atr sample count */
7087 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7088 return;
7089
7090 /* reset sample count */
7091 ring->atr_count = 0;
7092
244e27ad 7093 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7094
7095 /*
7096 * src and dst are inverted, think how the receiver sees them
7097 *
7098 * The input is broken into two sections, a non-compressed section
7099 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7100 * is XORed together and stored in the compressed dword.
7101 */
7102 input.formatted.vlan_id = vlan_id;
7103
7104 /*
7105 * since src port and flex bytes occupy the same word XOR them together
7106 * and write the value to source port portion of compressed dword
7107 */
244e27ad 7108 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7109 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7110 else
244e27ad 7111 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7112 common.port.dst ^= th->source;
7113
a1108ffd 7114 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7115 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7116 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7117 } else {
7118 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7119 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7120 hdr.ipv6->saddr.s6_addr32[1] ^
7121 hdr.ipv6->saddr.s6_addr32[2] ^
7122 hdr.ipv6->saddr.s6_addr32[3] ^
7123 hdr.ipv6->daddr.s6_addr32[0] ^
7124 hdr.ipv6->daddr.s6_addr32[1] ^
7125 hdr.ipv6->daddr.s6_addr32[2] ^
7126 hdr.ipv6->daddr.s6_addr32[3];
7127 }
c4cf55e5
PWJ		 7128
7129 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7130 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7131 input, common, ring->queue_index);
c4cf55e5
PWJ		 7132}
7133
f663dd9a 7134static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7135 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7136{
f663dd9a
JW		 7137 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7138#ifdef IXGBE_FCOE
97488bd1
AD		 7139 struct ixgbe_adapter *adapter;
7140 struct ixgbe_ring_feature *f;
7141 int txq;
f663dd9a
JW		 7142#endif
7143
7144 if (fwd_adapter)
7145 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7146
7147#ifdef IXGBE_FCOE
5e09a105 7148
97488bd1
AD		 7149 /*
7150 * only execute the code below if protocol is FCoE
7151 * or FIP and we have FCoE enabled on the adapter
7152 */
7153 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7154 case htons(ETH_P_FCOE):
7155 case htons(ETH_P_FIP):
97488bd1 7156 adapter = netdev_priv(dev);
c087663e 7157
97488bd1
AD		 7158 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7159 break;
7160 default:
99932d4f 7161 return fallback(dev, skb);
97488bd1 7162 }
c087663e 7163
97488bd1 7164 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7165
97488bd1
AD		 7166 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7167 smp_processor_id();
56075a98 7168
97488bd1
AD		 7169 while (txq >= f->indices)
7170 txq -= f->indices;
c4cf55e5 7171
97488bd1 7172 return txq + f->offset;
f663dd9a 7173#else
99932d4f 7174 return fallback(dev, skb);
f663dd9a 7175#endif
09a3b1f8
SH		 7176}
7177
fc77dc3c 7178netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7179 struct ixgbe_adapter *adapter,
7180 struct ixgbe_ring *tx_ring)
9a799d71 7181{
d3d00239 7182 struct ixgbe_tx_buffer *first;
5f715823 7183 int tso;
d3d00239 7184 u32 tx_flags = 0;
a535c30e 7185 unsigned short f;
a535c30e 7186 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7187 __be16 protocol = skb->protocol;
63544e9c 7188 u8 hdr_len = 0;
5e09a105 7189
a535c30e
AD		 7190 /*
7191 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7192 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7193 * + 2 desc gap to keep tail from touching head,
7194 * + 1 desc for context descriptor,
7195 * otherwise try next time
7196 */
a535c30e
AD		 7197 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7198 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7199
a535c30e
AD		 7200 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7201 tx_ring->tx_stats.tx_busy++;
7202 return NETDEV_TX_BUSY;
7203 }
7204
fd0db0ed
AD		 7205 /* record the location of the first descriptor for this packet */
7206 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7207 first->skb = skb;
091a6246
AD		 7208 first->bytecount = skb->len;
7209 first->gso_segs = 1;
fd0db0ed 7210
66f32a8b 7211 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7212 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7213 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7214 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7215 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7216 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7217 struct vlan_hdr *vhdr, _vhdr;
7218 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7219 if (!vhdr)
7220 goto out_drop;
7221
7222 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7223 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7224 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7225 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7226 }
7227
151b260c
JK		 7228 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
7229 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7230 &adapter->state))) {
3a6a4eda
JK		 7231 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7232 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7233
7234 /* schedule check for Tx timestamp */
7235 adapter->ptp_tx_skb = skb_get(skb);
7236 adapter->ptp_tx_start = jiffies;
7237 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7238 }
3a6a4eda 7239
ff29a86e
JK		 7240 skb_tx_timestamp(skb);
7241
9e0c5648
AD		 7242#ifdef CONFIG_PCI_IOV
7243 /*
7244 * Use the l2switch_enable flag - would be false if the DMA
7245 * Tx switch had been disabled.
7246 */
7247 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7248 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7249
7250#endif
32701dc2 7251 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7252 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7253 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7254 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7255 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7256 tx_flags |= (skb->priority & 0x7) <<
7257 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7258 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7259 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7260
7261 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7262 goto out_drop;
7263 vhdr = (struct vlan_ethhdr *)skb->data;
7264 vhdr->h_vlan_TCI = htons(tx_flags >>
7265 IXGBE_TX_FLAGS_VLAN_SHIFT);
7266 } else {
7267 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7268 }
9a799d71 7269 }
eacd73f7 7270
244e27ad
AD		 7271 /* record initial flags and protocol */
7272 first->tx_flags = tx_flags;
7273 first->protocol = protocol;
7274
eacd73f7 7275#ifdef IXGBE_FCOE
66f32a8b 7276 /* setup tx offload for FCoE */
a1108ffd 7277 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7278 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7279 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7280 if (tso < 0)
7281 goto out_drop;
9a799d71 7282
66f32a8b 7283 goto xmit_fcoe;
eacd73f7 7284 }
9a799d71 7285
66f32a8b 7286#endif /* IXGBE_FCOE */
244e27ad 7287 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7288 if (tso < 0)
897ab156 7289 goto out_drop;
244e27ad
AD		 7290 else if (!tso)
7291 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7292
7293 /* add the ATR filter if ATR is on */
7294 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7295 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7296
7297#ifdef IXGBE_FCOE
7298xmit_fcoe:
7299#endif /* IXGBE_FCOE */
244e27ad 7300 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7301
9a799d71 7302 return NETDEV_TX_OK;
897ab156
AD		 7303
7304out_drop:
fd0db0ed
AD		 7305 dev_kfree_skb_any(first->skb);
7306 first->skb = NULL;
7307
897ab156 7308 return NETDEV_TX_OK;
9a799d71
AK		 7309}
7310
2a47fa45
JF		 7311static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7312 struct net_device *netdev,
7313 struct ixgbe_ring *ring)
84418e3b
AD		 7314{
7315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7316 struct ixgbe_ring *tx_ring;
7317
a50c29dd
AD		 7318 /*
7319 * The minimum packet size for olinfo paylen is 17 so pad the skb
7320 * in order to meet this minimum size requirement.
7321 */
f73332fc
SH		 7322 if (unlikely(skb->len < 17)) {
7323 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7324 return NETDEV_TX_OK;
7325 skb->len = 17;
71a49f77 7326 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7327 }
7328
2a47fa45
JF		 7329 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7330
fc77dc3c 7331 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7332}
7333
2a47fa45
JF		 7334static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7335 struct net_device *netdev)
7336{
7337 return __ixgbe_xmit_frame(skb, netdev, NULL);
7338}
7339
9a799d71
AK		 7340/**
7341 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7342 * @netdev: network interface device structure
7343 * @p: pointer to an address structure
7344 *
7345 * Returns 0 on success, negative on failure
7346 **/
7347static int ixgbe_set_mac(struct net_device *netdev, void *p)
7348{
7349 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7350 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7351 struct sockaddr *addr = p;
5d7daa35 7352 int ret;
9a799d71
AK		 7353
7354 if (!is_valid_ether_addr(addr->sa_data))
7355 return -EADDRNOTAVAIL;
7356
5d7daa35 7357 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7358 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7359 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7360
5d7daa35
JK		 7361 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7362 return ret > 0 ? 0 : ret;
9a799d71
AK		 7363}
7364
6b73e10d
BH		 7365static int
7366ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7367{
7368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7369 struct ixgbe_hw *hw = &adapter->hw;
7370 u16 value;
7371 int rc;
7372
7373 if (prtad != hw->phy.mdio.prtad)
7374 return -EINVAL;
7375 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7376 if (!rc)
7377 rc = value;
7378 return rc;
7379}
7380
7381static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7382 u16 addr, u16 value)
7383{
7384 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7385 struct ixgbe_hw *hw = &adapter->hw;
7386
7387 if (prtad != hw->phy.mdio.prtad)
7388 return -EINVAL;
7389 return hw->phy.ops.write_reg(hw, addr, devad, value);
7390}
7391
7392static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7393{
7394 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7395
3a6a4eda 7396 switch (cmd) {
3a6a4eda 7397 case SIOCSHWTSTAMP:
93501d48
JK		 7398 return ixgbe_ptp_set_ts_config(adapter, req);
7399 case SIOCGHWTSTAMP:
7400 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7401 default:
7402 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7403 }
6b73e10d
BH		 7404}
7405
0365e6e4
PW		 7406/**
7407 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7408 * netdev->dev_addrs
0365e6e4
PW		 7409 * @netdev: network interface device structure
7410 *
7411 * Returns non-zero on failure
7412 **/
7413static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7414{
7415 int err = 0;
7416 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7417 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7418
7fa7c9dc 7419 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7420 rtnl_lock();
7fa7c9dc 7421 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7422 rtnl_unlock();
7fa7c9dc
AD		 7423
7424 /* update SAN MAC vmdq pool selection */
7425 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7426 }
7427 return err;
7428}
7429
7430/**
7431 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7432 * netdev->dev_addrs
0365e6e4
PW		 7433 * @netdev: network interface device structure
7434 *
7435 * Returns non-zero on failure
7436 **/
7437static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7438{
7439 int err = 0;
7440 struct ixgbe_adapter *adapter = netdev_priv(dev);
7441 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7442
7443 if (is_valid_ether_addr(mac->san_addr)) {
7444 rtnl_lock();
7445 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7446 rtnl_unlock();
7447 }
7448 return err;
7449}
7450
9a799d71
AK		 7451#ifdef CONFIG_NET_POLL_CONTROLLER
7452/*
7453 * Polling 'interrupt' - used by things like netconsole to send skbs
7454 * without having to re-enable interrupts. It's not called while
7455 * the interrupt routine is executing.
7456 */
7457static void ixgbe_netpoll(struct net_device *netdev)
7458{
7459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7460 int i;
9a799d71 7461
1a647bd2
AD		 7462 /* if interface is down do nothing */
7463 if (test_bit(__IXGBE_DOWN, &adapter->state))
7464 return;
7465
9a799d71 7466 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7467 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7468 for (i = 0; i < adapter->num_q_vectors; i++)
7469 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7470 } else {
7471 ixgbe_intr(adapter->pdev->irq, netdev);
7472 }
9a799d71 7473 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7474}
9a799d71 7475
581330ba 7476#endif
de1036b1
ED		 7477static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7478 struct rtnl_link_stats64 *stats)
7479{
7480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7481 int i;
7482
1a51502b 7483 rcu_read_lock();
de1036b1 7484 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7485 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7486 u64 bytes, packets;
7487 unsigned int start;
7488
1a51502b
ED		 7489 if (ring) {
7490 do {
57a7744e 7491 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7492 packets = ring->stats.packets;
7493 bytes = ring->stats.bytes;
57a7744e 7494 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7495 stats->rx_packets += packets;
7496 stats->rx_bytes += bytes;
7497 }
de1036b1 7498 }
1ac9ad13
ED		 7499
7500 for (i = 0; i < adapter->num_tx_queues; i++) {
7501 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7502 u64 bytes, packets;
7503 unsigned int start;
7504
7505 if (ring) {
7506 do {
57a7744e 7507 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7508 packets = ring->stats.packets;
7509 bytes = ring->stats.bytes;
57a7744e 7510 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7511 stats->tx_packets += packets;
7512 stats->tx_bytes += bytes;
7513 }
7514 }
1a51502b 7515 rcu_read_unlock();
de1036b1
ED		 7516 /* following stats updated by ixgbe_watchdog_task() */
7517 stats->multicast = netdev->stats.multicast;
7518 stats->rx_errors = netdev->stats.rx_errors;
7519 stats->rx_length_errors = netdev->stats.rx_length_errors;
7520 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7521 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7522 return stats;
7523}
7524
8af3c33f 7525#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7526/**
7527 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7528 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7529 * @tc: number of traffic classes currently enabled
7530 *
7531 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7532 * 802.1Q priority maps to a packet buffer that exists.
7533 */
7534static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7535{
7536 struct ixgbe_hw *hw = &adapter->hw;
7537 u32 reg, rsave;
7538 int i;
7539
7540 /* 82598 have a static priority to TC mapping that can not
7541 * be changed so no validation is needed.
7542 */
7543 if (hw->mac.type == ixgbe_mac_82598EB)
7544 return;
7545
7546 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7547 rsave = reg;
7548
7549 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7550 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7551
7552 /* If up2tc is out of bounds default to zero */
7553 if (up2tc > tc)
7554 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7555 }
7556
7557 if (reg != rsave)
7558 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7559
7560 return;
7561}
7562
02debdc9
AD		 7563/**
7564 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7565 * @adapter: Pointer to adapter struct
7566 *
7567 * Populate the netdev user priority to tc map
7568 */
7569static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7570{
7571 struct net_device *dev = adapter->netdev;
7572 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7573 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7574 u8 prio;
7575
7576 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7577 u8 tc = 0;
7578
7579 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7580 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7581 else if (ets)
7582 tc = ets->prio_tc[prio];
7583
7584 netdev_set_prio_tc_map(dev, prio, tc);
7585 }
7586}
7587
cca73c59 7588#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7589/**
7590 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7591 *
7592 * @netdev: net device to configure
7593 * @tc: number of traffic classes to enable
7594 */
7595int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7596{
8b1c0b24
JF		 7597 struct ixgbe_adapter *adapter = netdev_priv(dev);
7598 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7599 bool pools;
8b1c0b24 7600
8b1c0b24 7601 /* Hardware supports up to 8 traffic classes */
4de2a022 7602 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7603 (hw->mac.type == ixgbe_mac_82598EB &&
7604 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7605 return -EINVAL;
7606
2a47fa45
JF		 7607 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7608 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7609 return -EBUSY;
7610
8b1c0b24 7611 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7612 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7613 * hardware is not flexible enough to do this dynamically.
7614 */
7615 if (netif_running(dev))
7616 ixgbe_close(dev);
7617 ixgbe_clear_interrupt_scheme(adapter);
7618
cca73c59 7619#ifdef CONFIG_IXGBE_DCB
e7589eab 7620 if (tc) {
8b1c0b24 7621 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7622 ixgbe_set_prio_tc_map(adapter);
7623
e7589eab 7624 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7625
943561d3
AD		 7626 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7627 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7628 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7629 }
e7589eab 7630 } else {
8b1c0b24 7631 netdev_reset_tc(dev);
02debdc9 7632
943561d3
AD		 7633 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7634 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7635
7636 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7637
7638 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7639 adapter->dcb_cfg.pfc_mode_enable = false;
7640 }
7641
8b1c0b24 7642 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7643
7644#endif /* CONFIG_IXGBE_DCB */
7645 ixgbe_init_interrupt_scheme(adapter);
7646
8b1c0b24 7647 if (netif_running(dev))
cca73c59 7648 return ixgbe_open(dev);
8b1c0b24
JF		 7649
7650 return 0;
7651}
de1036b1 7652
da36b647
GR		 7653#ifdef CONFIG_PCI_IOV
7654void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7655{
7656 struct net_device *netdev = adapter->netdev;
7657
7658 rtnl_lock();
da36b647 7659 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7660 rtnl_unlock();
7661}
7662
7663#endif
082757af
DS		 7664void ixgbe_do_reset(struct net_device *netdev)
7665{
7666 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7667
7668 if (netif_running(netdev))
7669 ixgbe_reinit_locked(adapter);
7670 else
7671 ixgbe_reset(adapter);
7672}
7673
c8f44aff 7674static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7675 netdev_features_t features)
082757af
DS		 7676{
7677 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7678
082757af 7679 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7680 if (!(features & NETIF_F_RXCSUM))
7681 features &= ~NETIF_F_LRO;
082757af 7682
567d2de2
AD		 7683 /* Turn off LRO if not RSC capable */
7684 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7685 features &= ~NETIF_F_LRO;
8e2813f5 7686
567d2de2 7687 return features;
082757af
DS		 7688}
7689
c8f44aff 7690static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7691 netdev_features_t features)
082757af
DS		 7692{
7693 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7694 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7695 bool need_reset = false;
7696
082757af 7697 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7698 if (!(features & NETIF_F_LRO)) {
7699 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7700 need_reset = true;
567d2de2
AD		 7701 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7702 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7703 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7704 if (adapter->rx_itr_setting == 1 ||
7705 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7706 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7707 need_reset = true;
7708 } else if ((changed ^ features) & NETIF_F_LRO) {
7709 e_info(probe, "rx-usecs set too low, "
7710 "disabling RSC\n");
082757af
DS		 7711 }
7712 }
7713
7714 /*
7715 * Check if Flow Director n-tuple support was enabled or disabled. If
7716 * the state changed, we need to reset.
7717 */
39cb681b
AD		 7718 switch (features & NETIF_F_NTUPLE) {
7719 case NETIF_F_NTUPLE:
567d2de2 7720 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7721 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7722 need_reset = true;
7723
567d2de2
AD		 7724 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7725 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7726 break;
7727 default:
7728 /* turn off perfect filters, enable ATR and reset */
7729 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7730 need_reset = true;
7731
7732 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7733
7734 /* We cannot enable ATR if SR-IOV is enabled */
7735 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7736 break;
7737
7738 /* We cannot enable ATR if we have 2 or more traffic classes */
7739 if (netdev_get_num_tc(netdev) > 1)
7740 break;
7741
7742 /* We cannot enable ATR if RSS is disabled */
7743 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7744 break;
7745
7746 /* A sample rate of 0 indicates ATR disabled */
7747 if (!adapter->atr_sample_rate)
7748 break;
7749
7750 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7751 break;
082757af
DS		 7752 }
7753
f646968f 7754 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7755 ixgbe_vlan_strip_enable(adapter);
7756 else
7757 ixgbe_vlan_strip_disable(adapter);
7758
3f2d1c0f
BG		 7759 if (changed & NETIF_F_RXALL)
7760 need_reset = true;
7761
567d2de2 7762 netdev->features = features;
082757af
DS		 7763 if (need_reset)
7764 ixgbe_do_reset(netdev);
7765
7766 return 0;
082757af
DS		 7767}
7768
edc7d573 7769static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7770 struct net_device *dev,
6b6e2725 7771 const unsigned char *addr,
0f4b0add
JF		 7772 u16 flags)
7773{
bcfd3432 7774 /* guarantee we can provide a unique filter for the unicast address */
46acc460 7775 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 7776 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
7777 return -ENOMEM;
0f4b0add
JF		 7778 }
7779
bcfd3432 7780 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add
JF		 7781}
7782
815cccbf
JF		 7783static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7784 struct nlmsghdr *nlh)
7785{
7786 struct ixgbe_adapter *adapter = netdev_priv(dev);
7787 struct nlattr *attr, *br_spec;
7788 int rem;
7789
7790 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7791 return -EOPNOTSUPP;
7792
7793 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7794
7795 nla_for_each_nested(attr, br_spec, rem) {
7796 __u16 mode;
7797 u32 reg = 0;
7798
7799 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7800 continue;
7801
7802 mode = nla_get_u16(attr);
9b735984 7803 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7804 reg = 0;
9b735984
GR		 7805 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7806 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7807 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7808 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7809 } else
815cccbf
JF		 7810 return -EINVAL;
7811
7812 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7813
7814 e_info(drv, "enabling bridge mode: %s\n",
7815 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7816 }
7817
7818 return 0;
7819}
7820
7821static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7822 struct net_device *dev,
7823 u32 filter_mask)
815cccbf
JF		 7824{
7825 struct ixgbe_adapter *adapter = netdev_priv(dev);
7826 u16 mode;
7827
7828 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7829 return 0;
7830
9b735984 7831 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7832 mode = BRIDGE_MODE_VEB;
7833 else
7834 mode = BRIDGE_MODE_VEPA;
7835
7836 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7837}
7838
2a47fa45
JF		 7839static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7840{
7841 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7842 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 7843 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 7844 unsigned int limit;
2a47fa45
JF		 7845 int pool, err;
7846
aac2f1bf
JK		 7847 /* Hardware has a limited number of available pools. Each VF, and the
7848 * PF require a pool. Check to ensure we don't attempt to use more
7849 * then the available number of pools.
7850 */
7851 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
7852 return ERR_PTR(-EINVAL);
7853
219354d4
JF		 7854#ifdef CONFIG_RPS
7855 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7856 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7857 vdev->name);
7858 return ERR_PTR(-EINVAL);
7859 }
7860#endif
2a47fa45 7861 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7862 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7863 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7864 netdev_info(pdev,
7865 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7866 pdev->name);
7867 return ERR_PTR(-EINVAL);
7868 }
7869
7870 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7871 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7872 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7873 return ERR_PTR(-EBUSY);
7874
7875 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7876 if (!fwd_adapter)
7877 return ERR_PTR(-ENOMEM);
7878
7879 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7880 adapter->num_rx_pools++;
7881 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7882 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7883
7884 /* Enable VMDq flag so device will be set in VM mode */
7885 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7886 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7887 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7888
7889 /* Force reinit of ring allocation with VMDQ enabled */
7890 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7891 if (err)
7892 goto fwd_add_err;
7893 fwd_adapter->pool = pool;
7894 fwd_adapter->real_adapter = adapter;
7895 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7896 if (err)
7897 goto fwd_add_err;
7898 netif_tx_start_all_queues(vdev);
7899 return fwd_adapter;
7900fwd_add_err:
7901 /* unwind counter and free adapter struct */
7902 netdev_info(pdev,
7903 "%s: dfwd hardware acceleration failed\n", vdev->name);
7904 clear_bit(pool, &adapter->fwd_bitmask);
7905 adapter->num_rx_pools--;
7906 kfree(fwd_adapter);
7907 return ERR_PTR(err);
7908}
7909
7910static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7911{
7912 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7913 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7914 unsigned int limit;
2a47fa45
JF		 7915
7916 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7917 adapter->num_rx_pools--;
7918
51f3773b
JF		 7919 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7920 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7921 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7922 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7923 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7924 fwd_adapter->pool, adapter->num_rx_pools,
7925 fwd_adapter->rx_base_queue,
7926 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7927 adapter->fwd_bitmask);
7928 kfree(fwd_adapter);
7929}
7930
0edc3527 7931static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7932 .ndo_open = ixgbe_open,
0edc3527 7933 .ndo_stop = ixgbe_close,
00829823 7934 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7935 .ndo_select_queue = ixgbe_select_queue,
581330ba 7936 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7937 .ndo_validate_addr = eth_validate_addr,
7938 .ndo_set_mac_address = ixgbe_set_mac,
7939 .ndo_change_mtu = ixgbe_change_mtu,
7940 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7941 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7942 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7943 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7944 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7945 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 7946 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 7947 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7948 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7949 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7950#ifdef CONFIG_IXGBE_DCB
24095aa3 7951 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7952#endif
0edc3527
SH		 7953#ifdef CONFIG_NET_POLL_CONTROLLER
7954 .ndo_poll_controller = ixgbe_netpoll,
7955#endif
e0d1095a 7956#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7957 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7958#endif
332d4a7d
YZ		 7959#ifdef IXGBE_FCOE
7960 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7961 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7962 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7963 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7964 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7965 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7966 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7967#endif /* IXGBE_FCOE */
082757af
DS		 7968 .ndo_set_features = ixgbe_set_features,
7969 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7970 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7971 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7972 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7973 .ndo_dfwd_add_station = ixgbe_fwd_add,
7974 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7975};
7976
e027d1ae
JK		 7977/**
7978 * ixgbe_enumerate_functions - Get the number of ports this device has
7979 * @adapter: adapter structure
7980 *
7981 * This function enumerates the phsyical functions co-located on a single slot,
7982 * in order to determine how many ports a device has. This is most useful in
7983 * determining the required GT/s of PCIe bandwidth necessary for optimal
7984 * performance.
7985 **/
7986static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7987{
caafb95d 7988 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 7989 int physfns = 0;
7990
f1f96579
JK		 7991 /* Some cards can not use the generic count PCIe functions method,
7992 * because they are behind a parent switch, so we hardcode these with
7993 * the correct number of functions.
e027d1ae 7994 */
8818970d 7995 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 7996 physfns = 4;
8818970d
JK		 7997
7998 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
7999 /* don't count virtual functions */
caafb95d
JK		 8000 if (entry->is_virtfn)
8001 continue;
8002
8003 /* When the devices on the bus don't all match our device ID,
8004 * we can't reliably determine the correct number of
8005 * functions. This can occur if a function has been direct
8006 * attached to a virtual machine using VT-d, for example. In
8007 * this case, simply return -1 to indicate this.
8008 */
8009 if ((entry->vendor != pdev->vendor) ||
8010 (entry->device != pdev->device))
8011 return -1;
8012
8013 physfns++;
e027d1ae
JK		 8014 }
8015
8016 return physfns;
8017}
8018
8e2813f5
JK		 8019/**
8020 * ixgbe_wol_supported - Check whether device supports WoL
8021 * @hw: hw specific details
8022 * @device_id: the device ID
8023 * @subdev_id: the subsystem device ID
8024 *
8025 * This function is used by probe and ethtool to determine
8026 * which devices have WoL support
8027 *
8028 **/
8029int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8030 u16 subdevice_id)
8031{
8032 struct ixgbe_hw *hw = &adapter->hw;
8033 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8034 int is_wol_supported = 0;
8035
8036 switch (device_id) {
8037 case IXGBE_DEV_ID_82599_SFP:
8038 /* Only these subdevices could supports WOL */
8039 switch (subdevice_id) {
87557440 8040 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8041 case IXGBE_SUBDEV_ID_82599_560FLR:
8042 /* only support first port */
8043 if (hw->bus.func != 0)
8044 break;
5700ff26 8045 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8046 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8047 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8048 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8049 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8050 is_wol_supported = 1;
8051 break;
8052 }
8053 break;
5daebbb0
DS		 8054 case IXGBE_DEV_ID_82599EN_SFP:
8055 /* Only this subdevice supports WOL */
8056 switch (subdevice_id) {
8057 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8058 is_wol_supported = 1;
8059 break;
8060 }
8061 break;
8e2813f5
JK		 8062 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8063 /* All except this subdevice support WOL */
8064 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8065 is_wol_supported = 1;
8066 break;
8067 case IXGBE_DEV_ID_82599_KX4:
8068 is_wol_supported = 1;
8069 break;
8070 case IXGBE_DEV_ID_X540T:
df376f0d 8071 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 8072 /* check eeprom to see if enabled wol */
8073 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8074 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8075 (hw->bus.func == 0))) {
8076 is_wol_supported = 1;
8077 }
8078 break;
8079 }
8080
8081 return is_wol_supported;
8082}
8083
9a799d71
AK		 8084/**
8085 * ixgbe_probe - Device Initialization Routine
8086 * @pdev: PCI device information struct
8087 * @ent: entry in ixgbe_pci_tbl
8088 *
8089 * Returns 0 on success, negative on failure
8090 *
8091 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8092 * The OS initialization, configuring of the adapter private structure,
8093 * and a hardware reset occur.
8094 **/
1dd06ae8 8095static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8096{
8097 struct net_device *netdev;
8098 struct ixgbe_adapter *adapter = NULL;
8099 struct ixgbe_hw *hw;
8100 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 8101 static int cards_found;
e027d1ae 8102 int i, err, pci_using_dac, expected_gts;
d3cb9869 8103 unsigned int indices = MAX_TX_QUEUES;
289700db 8104 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 8105#ifdef IXGBE_FCOE
8106 u16 device_caps;
8107#endif
289700db 8108 u32 eec;
9a799d71 8109
bded64a7
AG		 8110 /* Catch broken hardware that put the wrong VF device ID in
8111 * the PCIe SR-IOV capability.
8112 */
8113 if (pdev->is_virtfn) {
8114 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8115 pci_name(pdev), pdev->vendor, pdev->device);
8116 return -EINVAL;
8117 }
8118
9ce77666 8119 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8120 if (err)
8121 return err;
8122
f5f2eda8 8123 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8124 pci_using_dac = 1;
8125 } else {
f5f2eda8 8126 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8127 if (err) {
f5f2eda8
RK		 8128 dev_err(&pdev->dev,
8129 "No usable DMA configuration, aborting\n");
8130 goto err_dma;
9a799d71
AK		 8131 }
8132 pci_using_dac = 0;
8133 }
8134
9ce77666 8135 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8136 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8137 if (err) {
b8bc0421
DC		 8138 dev_err(&pdev->dev,
8139 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8140 goto err_pci_reg;
8141 }
8142
19d5afd4 8143 pci_enable_pcie_error_reporting(pdev);
6fabd715 8144
9a799d71 8145 pci_set_master(pdev);
fb3b27bc 8146 pci_save_state(pdev);
9a799d71 8147
d3cb9869 8148 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8149#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8150 /* 8 TC w/ 4 queues per TC */
8151 indices = 4 * MAX_TRAFFIC_CLASS;
8152#else
8153 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8154#endif
d3cb9869 8155 }
e901acd6 8156
c85a2618 8157 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8158 if (!netdev) {
8159 err = -ENOMEM;
8160 goto err_alloc_etherdev;
8161 }
8162
9a799d71
AK		 8163 SET_NETDEV_DEV(netdev, &pdev->dev);
8164
9a799d71 8165 adapter = netdev_priv(netdev);
c60fbb00 8166 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 8167
8168 adapter->netdev = netdev;
8169 adapter->pdev = pdev;
8170 hw = &adapter->hw;
8171 hw->back = adapter;
b3f4d599 8172 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8173
05857980 8174 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8175 pci_resource_len(pdev, 0));
2a1a091c 8176 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8177 if (!hw->hw_addr) {
8178 err = -EIO;
8179 goto err_ioremap;
8180 }
8181
0edc3527 8182 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8183 ixgbe_set_ethtool_ops(netdev);
9a799d71 8184 netdev->watchdog_timeo = 5 * HZ;
339de30f 8185 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8186
9a799d71
AK		 8187 adapter->bd_number = cards_found;
8188
9a799d71
AK		 8189 /* Setup hw api */
8190 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8191 hw->mac.type = ii->mac;
9a799d71 8192
c44ade9e
JB		 8193 /* EEPROM */
8194 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8195 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
58cf663f
MR		 8196 if (ixgbe_removed(hw->hw_addr)) {
8197 err = -EIO;
8198 goto err_ioremap;
8199 }
c44ade9e
JB		 8200 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8201 if (!(eec & (1 << 8)))
8202 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8203
8204 /* PHY */
8205 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8206 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8207 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8208 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8209 hw->phy.mdio.mmds = 0;
8210 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8211 hw->phy.mdio.dev = netdev;
8212 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8213 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8214
8ca783ab 8215 ii->get_invariants(hw);
9a799d71
AK		 8216
8217 /* setup the private structure */
8218 err = ixgbe_sw_init(adapter);
8219 if (err)
8220 goto err_sw_init;
8221
e86bff0e 8222 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8223 switch (adapter->hw.mac.type) {
8224 case ixgbe_mac_82599EB:
8225 case ixgbe_mac_X540:
e86bff0e 8226 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8227 break;
8228 default:
8229 break;
8230 }
e86bff0e 8231
bf069c97
DS		 8232 /*
8233 * If there is a fan on this device and it has failed log the
8234 * failure.
8235 */
8236 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8237 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8238 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8239 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8240 }
8241
8ef78adc
PWJ		 8242 if (allow_unsupported_sfp)
8243 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8244
c44ade9e 8245 /* reset_hw fills in the perm_addr as well */
119fc60a 8246 hw->phy.reset_if_overtemp = true;
c44ade9e 8247 err = hw->mac.ops.reset_hw(hw);
119fc60a 8248 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8249 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8250 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8251 err = 0;
8252 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8253 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8254 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8255 goto err_sw_init;
8256 } else if (err) {
849c4542 8257 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8258 goto err_sw_init;
8259 }
8260
99d74487 8261#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8262 /* SR-IOV not supported on the 82598 */
8263 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8264 goto skip_sriov;
8265 /* Mailbox */
8266 ixgbe_init_mbx_params_pf(hw);
8267 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8268 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8269 ixgbe_enable_sriov(adapter);
60a1a680 8270skip_sriov:
1cdd1ec8 8271
99d74487 8272#endif
396e799c 8273 netdev->features = NETIF_F_SG |
e8e9f696 8274 NETIF_F_IP_CSUM |
082757af 8275 NETIF_F_IPV6_CSUM |
f646968f
PM		 8276 NETIF_F_HW_VLAN_CTAG_TX |
8277 NETIF_F_HW_VLAN_CTAG_RX |
8278 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8279 NETIF_F_TSO |
8280 NETIF_F_TSO6 |
082757af 8281 NETIF_F_RXHASH |
8bf1264d 8282 NETIF_F_RXCSUM;
9a799d71 8283
8bf1264d 8284 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8285
58be7666
DS		 8286 switch (adapter->hw.mac.type) {
8287 case ixgbe_mac_82599EB:
8288 case ixgbe_mac_X540:
45a5ead0 8289 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8290 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8291 NETIF_F_NTUPLE;
58be7666
DS		 8292 break;
8293 default:
8294 break;
8295 }
45a5ead0 8296
3f2d1c0f
BG		 8297 netdev->hw_features |= NETIF_F_RXALL;
8298
ad31c402
JK		 8299 netdev->vlan_features |= NETIF_F_TSO;
8300 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8301 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8302 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8303 netdev->vlan_features |= NETIF_F_SG;
8304
01789349 8305 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8306 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8307
7a6b6f51 8308#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8309 netdev->dcbnl_ops = &dcbnl_ops;
8310#endif
8311
eacd73f7 8312#ifdef IXGBE_FCOE
0d551589 8313 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8314 unsigned int fcoe_l;
8315
eacd73f7
YZ		 8316 if (hw->mac.ops.get_device_caps) {
8317 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8318 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8319 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8320 }
7c8ae65a 8321
d3cb9869
AD		 8322
8323 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8324 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8325
a58915c7
AD		 8326 netdev->features |= NETIF_F_FSO |
8327 NETIF_F_FCOE_CRC;
8328
7c8ae65a
AD		 8329 netdev->vlan_features |= NETIF_F_FSO |
8330 NETIF_F_FCOE_CRC |
8331 NETIF_F_FCOE_MTU;
5e09d7f6 8332 }
eacd73f7 8333#endif /* IXGBE_FCOE */
7b872a55 8334 if (pci_using_dac) {
9a799d71 8335 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8336 netdev->vlan_features |= NETIF_F_HIGHDMA;
8337 }
9a799d71 8338
082757af
DS		 8339 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8340 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8341 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8342 netdev->features |= NETIF_F_LRO;
8343
9a799d71 8344 /* make sure the EEPROM is good */
c44ade9e 8345 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8346 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8347 err = -EIO;
35937c05 8348 goto err_sw_init;
9a799d71
AK		 8349 }
8350
8351 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8352
aaeb6cdf 8353 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8354 e_dev_err("invalid MAC address\n");
9a799d71 8355 err = -EIO;
35937c05 8356 goto err_sw_init;
9a799d71
AK		 8357 }
8358
5d7daa35
JK		 8359 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8360
7086400d 8361 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8362 (unsigned long) adapter);
9a799d71 8363
58cf663f
MR		 8364 if (ixgbe_removed(hw->hw_addr)) {
8365 err = -EIO;
8366 goto err_sw_init;
8367 }
7086400d 8368 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8369 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8370 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8371
021230d4
AV		 8372 err = ixgbe_init_interrupt_scheme(adapter);
8373 if (err)
8374 goto err_sw_init;
9a799d71 8375
8e2813f5 8376 /* WOL not supported for all devices */
c23f5b6b 8377 adapter->wol = 0;
8e2813f5 8378 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8379 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8380 pdev->subsystem_device);
6b92b0ba 8381 if (hw->wol_enabled)
9417c464 8382 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8383
e8e26350
PW		 8384 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8385
15e5209f
ET		 8386 /* save off EEPROM version number */
8387 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8388 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8389
04f165ef
PW		 8390 /* pick up the PCI bus settings for reporting later */
8391 hw->mac.ops.get_bus_info(hw);
e027d1ae 8392 if (ixgbe_pcie_from_parent(hw))
b8e82001 8393 ixgbe_get_parent_bus_info(adapter);
04f165ef 8394
e027d1ae
JK		 8395 /* calculate the expected PCIe bandwidth required for optimal
8396 * performance. Note that some older parts will never have enough
8397 * bandwidth due to being older generation PCIe parts. We clamp these
8398 * parts to ensure no warning is displayed if it can't be fixed.
8399 */
8400 switch (hw->mac.type) {
8401 case ixgbe_mac_82598EB:
8402 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8403 break;
8404 default:
8405 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8406 break;
0c254d86 8407 }
caafb95d
JK		 8408
8409 /* don't check link if we failed to enumerate functions */
8410 if (expected_gts > 0)
8411 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8412
339de30f 8413 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8414 if (err)
339de30f 8415 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8416 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8417 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8418 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8419 part_str);
6a2aae5a
JK		 8420 else
8421 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8422 hw->mac.type, hw->phy.type, part_str);
8423
8424 e_dev_info("%pM\n", netdev->dev_addr);
8425
9a799d71 8426 /* reset the hardware with the new settings */
794caeb2 8427 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8428 if (err == IXGBE_ERR_EEPROM_VERSION) {
8429 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8430 e_dev_warn("This device is a pre-production adapter/LOM. "
8431 "Please be aware there may be issues associated "
8432 "with your hardware. If you are experiencing "
8433 "problems please contact your Intel or hardware "
8434 "representative who provided you with this "
8435 "hardware.\n");
794caeb2 8436 }
9a799d71
AK		 8437 strcpy(netdev->name, "eth%d");
8438 err = register_netdev(netdev);
8439 if (err)
8440 goto err_register;
8441
ec74a471
ET		 8442 /* power down the optics for 82599 SFP+ fiber */
8443 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8444 hw->mac.ops.disable_tx_laser(hw);
8445
54386467
JB		 8446 /* carrier off reporting is important to ethtool even BEFORE open */
8447 netif_carrier_off(netdev);
8448
5dd2d332 8449#ifdef CONFIG_IXGBE_DCA
652f093f 8450 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8451 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8452 ixgbe_setup_dca(adapter);
8453 }
8454#endif
1cdd1ec8 8455 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8456 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8457 for (i = 0; i < adapter->num_vfs; i++)
8458 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8459 }
8460
2466dd9c
JK		 8461 /* firmware requires driver version to be 0xFFFFFFFF
8462 * since os does not support feature
8463 */
9612de92 8464 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8465 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8466 0xFF);
9612de92 8467
0365e6e4
PW		 8468 /* add san mac addr to netdev */
8469 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8470
ea81875a 8471 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8472 cards_found++;
3ca8bc6d 8473
1210982b 8474#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8475 if (ixgbe_sysfs_init(adapter))
8476 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8477#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8478
00949167 8479 ixgbe_dbg_adapter_init(adapter);
00949167 8480
d1a35ee2
ET		 8481 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8482 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8483 hw->mac.ops.setup_link(hw,
8484 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8485 true);
8486
9a799d71
AK		 8487 return 0;
8488
8489err_register:
5eba3699 8490 ixgbe_release_hw_control(adapter);
7a921c93 8491 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8492err_sw_init:
99d74487 8493 ixgbe_disable_sriov(adapter);
7086400d 8494 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8495 iounmap(adapter->io_addr);
5d7daa35 8496 kfree(adapter->mac_table);
9a799d71
AK		 8497err_ioremap:
8498 free_netdev(netdev);
8499err_alloc_etherdev:
e8e9f696
JP		 8500 pci_release_selected_regions(pdev,
8501 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8502err_pci_reg:
8503err_dma:
508a8c9e 8504 if (!adapter || !test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
41c62843 8505 pci_disable_device(pdev);
9a799d71
AK		 8506 return err;
8507}
8508
8509/**
8510 * ixgbe_remove - Device Removal Routine
8511 * @pdev: PCI device information struct
8512 *
8513 * ixgbe_remove is called by the PCI subsystem to alert the driver
8514 * that it should release a PCI device. The could be caused by a
8515 * Hot-Plug event, or because the driver is going to be removed from
8516 * memory.
8517 **/
9f9a12f8 8518static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8519{
c60fbb00
AD		 8520 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8521 struct net_device *netdev = adapter->netdev;
9a799d71 8522
00949167 8523 ixgbe_dbg_adapter_exit(adapter);
00949167 8524
09f40aed 8525 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8526 cancel_work_sync(&adapter->service_task);
9a799d71 8527
3a6a4eda 8528
5dd2d332 8529#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8530 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8531 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8532 dca_remove_requester(&pdev->dev);
8533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8534 }
8535
8536#endif
1210982b 8537#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8538 ixgbe_sysfs_exit(adapter);
1210982b 8539#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8540
0365e6e4
PW		 8541 /* remove the added san mac */
8542 ixgbe_del_sanmac_netdev(netdev);
8543
c4900be0
DS		 8544 if (netdev->reg_state == NETREG_REGISTERED)
8545 unregister_netdev(netdev);
9a799d71 8546
da36b647
GR		 8547#ifdef CONFIG_PCI_IOV
8548 /*
8549 * Only disable SR-IOV on unload if the user specified the now
8550 * deprecated max_vfs module parameter.
8551 */
8552 if (max_vfs)
8553 ixgbe_disable_sriov(adapter);
8554#endif
7a921c93 8555 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8556
021230d4 8557 ixgbe_release_hw_control(adapter);
9a799d71 8558
2b1588c3
AD		 8559#ifdef CONFIG_DCB
8560 kfree(adapter->ixgbe_ieee_pfc);
8561 kfree(adapter->ixgbe_ieee_ets);
8562
8563#endif
2a1a091c 8564 iounmap(adapter->io_addr);
9ce77666 8565 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8566 IORESOURCE_MEM));
9a799d71 8567
849c4542 8568 e_dev_info("complete\n");
021230d4 8569
5d7daa35 8570 kfree(adapter->mac_table);
9a799d71
AK		 8571 free_netdev(netdev);
8572
19d5afd4 8573 pci_disable_pcie_error_reporting(pdev);
6fabd715 8574
41c62843
MR		 8575 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8576 pci_disable_device(pdev);
9a799d71
AK		 8577}
8578
8579/**
8580 * ixgbe_io_error_detected - called when PCI error is detected
8581 * @pdev: Pointer to PCI device
8582 * @state: The current pci connection state
8583 *
8584 * This function is called after a PCI bus error affecting
8585 * this device has been detected.
8586 */
8587static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8588 pci_channel_state_t state)
9a799d71 8589{
c60fbb00
AD		 8590 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8591 struct net_device *netdev = adapter->netdev;
9a799d71 8592
83c61fa9 8593#ifdef CONFIG_PCI_IOV
14438464 8594 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8595 struct pci_dev *bdev, *vfdev;
8596 u32 dw0, dw1, dw2, dw3;
8597 int vf, pos;
8598 u16 req_id, pf_func;
8599
8600 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8601 adapter->num_vfs == 0)
8602 goto skip_bad_vf_detection;
8603
8604 bdev = pdev->bus->self;
62f87c0e 8605 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8606 bdev = bdev->bus->self;
8607
8608 if (!bdev)
8609 goto skip_bad_vf_detection;
8610
8611 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8612 if (!pos)
8613 goto skip_bad_vf_detection;
8614
14438464
MR		 8615 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8616 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8617 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8618 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8619 if (ixgbe_removed(hw->hw_addr))
8620 goto skip_bad_vf_detection;
83c61fa9
GR		 8621
8622 req_id = dw1 >> 16;
8623 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8624 if (!(req_id & 0x0080))
8625 goto skip_bad_vf_detection;
8626
8627 pf_func = req_id & 0x01;
8628 if ((pf_func & 1) == (pdev->devfn & 1)) {
8629 unsigned int device_id;
8630
8631 vf = (req_id & 0x7F) >> 1;
8632 e_dev_err("VF %d has caused a PCIe error\n", vf);
8633 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8634 "%8.8x\tdw3: %8.8x\n",
8635 dw0, dw1, dw2, dw3);
8636 switch (adapter->hw.mac.type) {
8637 case ixgbe_mac_82599EB:
8638 device_id = IXGBE_82599_VF_DEVICE_ID;
8639 break;
8640 case ixgbe_mac_X540:
8641 device_id = IXGBE_X540_VF_DEVICE_ID;
8642 break;
8643 default:
8644 device_id = 0;
8645 break;
8646 }
8647
8648 /* Find the pci device of the offending VF */
36e90319 8649 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8650 while (vfdev) {
8651 if (vfdev->devfn == (req_id & 0xFF))
8652 break;
36e90319 8653 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8654 device_id, vfdev);
8655 }
8656 /*
8657 * There's a slim chance the VF could have been hot plugged,
8658 * so if it is no longer present we don't need to issue the
8659 * VFLR. Just clean up the AER in that case.
8660 */
8661 if (vfdev) {
8662 e_dev_err("Issuing VFLR to VF %d\n", vf);
8663 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8664 /* Free device reference count */
8665 pci_dev_put(vfdev);
83c61fa9
GR		 8666 }
8667
8668 pci_cleanup_aer_uncorrect_error_status(pdev);
8669 }
8670
8671 /*
8672 * Even though the error may have occurred on the other port
8673 * we still need to increment the vf error reference count for
8674 * both ports because the I/O resume function will be called
8675 * for both of them.
8676 */
8677 adapter->vferr_refcount++;
8678
8679 return PCI_ERS_RESULT_RECOVERED;
8680
8681skip_bad_vf_detection:
8682#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 8683 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8684 return PCI_ERS_RESULT_DISCONNECT;
8685
41c62843 8686 rtnl_lock();
9a799d71
AK		 8687 netif_device_detach(netdev);
8688
41c62843
MR		 8689 if (state == pci_channel_io_perm_failure) {
8690 rtnl_unlock();
3044b8d1 8691 return PCI_ERS_RESULT_DISCONNECT;
41c62843 8692 }
3044b8d1 8693
9a799d71
AK		 8694 if (netif_running(netdev))
8695 ixgbe_down(adapter);
41c62843
MR		 8696
8697 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8698 pci_disable_device(pdev);
8699 rtnl_unlock();
9a799d71 8700
b4617240 8701 /* Request a slot reset. */
9a799d71
AK		 8702 return PCI_ERS_RESULT_NEED_RESET;
8703}
8704
8705/**
8706 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8707 * @pdev: Pointer to PCI device
8708 *
8709 * Restart the card from scratch, as if from a cold-boot.
8710 */
8711static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8712{
c60fbb00 8713 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8714 pci_ers_result_t result;
8715 int err;
9a799d71 8716
9ce77666 8717 if (pci_enable_device_mem(pdev)) {
396e799c 8718 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8719 result = PCI_ERS_RESULT_DISCONNECT;
8720 } else {
4e857c58 8721 smp_mb__before_atomic();
41c62843 8722 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 8723 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8724 pci_set_master(pdev);
8725 pci_restore_state(pdev);
c0e1f68b 8726 pci_save_state(pdev);
9a799d71 8727
dd4d8ca6 8728 pci_wake_from_d3(pdev, false);
9a799d71 8729
6fabd715 8730 ixgbe_reset(adapter);
88512539 8731 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8732 result = PCI_ERS_RESULT_RECOVERED;
8733 }
8734
8735 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8736 if (err) {
849c4542
ET		 8737 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8738 "failed 0x%0x\n", err);
6fabd715
PWJ		 8739 /* non-fatal, continue */
8740 }
9a799d71 8741
6fabd715 8742 return result;
9a799d71
AK		 8743}
8744
8745/**
8746 * ixgbe_io_resume - called when traffic can start flowing again.
8747 * @pdev: Pointer to PCI device
8748 *
8749 * This callback is called when the error recovery driver tells us that
8750 * its OK to resume normal operation.
8751 */
8752static void ixgbe_io_resume(struct pci_dev *pdev)
8753{
c60fbb00
AD		 8754 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8755 struct net_device *netdev = adapter->netdev;
9a799d71 8756
83c61fa9
GR		 8757#ifdef CONFIG_PCI_IOV
8758 if (adapter->vferr_refcount) {
8759 e_info(drv, "Resuming after VF err\n");
8760 adapter->vferr_refcount--;
8761 return;
8762 }
8763
8764#endif
c7ccde0f
AD		 8765 if (netif_running(netdev))
8766 ixgbe_up(adapter);
9a799d71
AK		 8767
8768 netif_device_attach(netdev);
9a799d71
AK		 8769}
8770
3646f0e5 8771static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8772 .error_detected = ixgbe_io_error_detected,
8773 .slot_reset = ixgbe_io_slot_reset,
8774 .resume = ixgbe_io_resume,
8775};
8776
8777static struct pci_driver ixgbe_driver = {
8778 .name = ixgbe_driver_name,
8779 .id_table = ixgbe_pci_tbl,
8780 .probe = ixgbe_probe,
9f9a12f8 8781 .remove = ixgbe_remove,
9a799d71
AK		 8782#ifdef CONFIG_PM
8783 .suspend = ixgbe_suspend,
8784 .resume = ixgbe_resume,
8785#endif
8786 .shutdown = ixgbe_shutdown,
da36b647 8787 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8788 .err_handler = &ixgbe_err_handler
8789};
8790
8791/**
8792 * ixgbe_init_module - Driver Registration Routine
8793 *
8794 * ixgbe_init_module is the first routine called when the driver is
8795 * loaded. All it does is register with the PCI subsystem.
8796 **/
8797static int __init ixgbe_init_module(void)
8798{
8799 int ret;
c7689578 8800 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8801 pr_info("%s\n", ixgbe_copyright);
9a799d71 8802
00949167 8803 ixgbe_dbg_init();
00949167 8804
f01fc1a8
JK		 8805 ret = pci_register_driver(&ixgbe_driver);
8806 if (ret) {
f01fc1a8 8807 ixgbe_dbg_exit();
f01fc1a8
JK		 8808 return ret;
8809 }
8810
5dd2d332 8811#ifdef CONFIG_IXGBE_DCA
bd0362dd 8812 dca_register_notify(&dca_notifier);
bd0362dd 8813#endif
5dd2d332 8814
f01fc1a8 8815 return 0;
9a799d71 8816}
b4617240 8817
9a799d71
AK		 8818module_init(ixgbe_init_module);
8819
8820/**
8821 * ixgbe_exit_module - Driver Exit Cleanup Routine
8822 *
8823 * ixgbe_exit_module is called just before the driver is removed
8824 * from memory.
8825 **/
8826static void __exit ixgbe_exit_module(void)
8827{
5dd2d332 8828#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8829 dca_unregister_notify(&dca_notifier);
8830#endif
9a799d71 8831 pci_unregister_driver(&ixgbe_driver);
00949167 8832
00949167 8833 ixgbe_dbg_exit();
00949167 8834
1a51502b 8835 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8836}
bd0362dd 8837
5dd2d332 8838#ifdef CONFIG_IXGBE_DCA
bd0362dd 8839static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8840 void *p)
bd0362dd
JC		 8841{
8842 int ret_val;
8843
8844 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8845 __ixgbe_notify_dca);
bd0362dd
JC		 8846
8847 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8848}
b453368d 8849
5dd2d332 8850#endif /* CONFIG_IXGBE_DCA */
849c4542 8851
9a799d71
AK		 8852module_exit(ixgbe_exit_module);
8853
8854/* ixgbe_main.c */
Linux kernel - Deliverables
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