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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
67359c3c | 4 | Copyright(c) 1999 - 2015 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/types.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/vmalloc.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/in.h> | |
a6b7a407 | 36 | #include <linux/interrupt.h> |
9a799d71 AK |
37 | #include <linux/ip.h> |
38 | #include <linux/tcp.h> | |
897ab156 | 39 | #include <linux/sctp.h> |
60127865 | 40 | #include <linux/pkt_sched.h> |
9a799d71 | 41 | #include <linux/ipv6.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
9a799d71 AK |
43 | #include <net/checksum.h> |
44 | #include <net/ip6_checksum.h> | |
c762dff2 | 45 | #include <linux/etherdevice.h> |
9a799d71 | 46 | #include <linux/ethtool.h> |
01789349 | 47 | #include <linux/if.h> |
9a799d71 | 48 | #include <linux/if_vlan.h> |
2a47fa45 | 49 | #include <linux/if_macvlan.h> |
815cccbf | 50 | #include <linux/if_bridge.h> |
70c71606 | 51 | #include <linux/prefetch.h> |
eacd73f7 | 52 | #include <scsi/fc/fc_fcoe.h> |
3f207800 | 53 | #include <net/vxlan.h> |
b82b17d9 JF |
54 | #include <net/pkt_cls.h> |
55 | #include <net/tc_act/tc_gact.h> | |
9a799d71 | 56 | |
c762dff2 MP |
57 | #ifdef CONFIG_OF |
58 | #include <linux/of_net.h> | |
59 | #endif | |
60 | ||
61 | #ifdef CONFIG_SPARC | |
62 | #include <asm/idprom.h> | |
63 | #include <asm/prom.h> | |
64 | #endif | |
65 | ||
9a799d71 AK |
66 | #include "ixgbe.h" |
67 | #include "ixgbe_common.h" | |
ee5f784a | 68 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 69 | #include "ixgbe_sriov.h" |
b82b17d9 | 70 | #include "ixgbe_model.h" |
9a799d71 AK |
71 | |
72 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 73 | static const char ixgbe_driver_string[] = |
e8e9f696 | 74 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 75 | #ifdef IXGBE_FCOE |
ea81875a NP |
76 | char ixgbe_default_device_descr[] = |
77 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
78 | #else |
79 | static char ixgbe_default_device_descr[] = | |
80 | "Intel(R) 10 Gigabit Network Connection"; | |
81 | #endif | |
21dd5601 | 82 | #define DRV_VERSION "4.2.1-k" |
9c8eb720 | 83 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 84 | static const char ixgbe_copyright[] = |
67359c3c | 85 | "Copyright (c) 1999-2015 Intel Corporation."; |
9a799d71 | 86 | |
f44e751b DS |
87 | static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; |
88 | ||
9a799d71 | 89 | static const struct ixgbe_info *ixgbe_info_tbl[] = { |
6a14ee0c DS |
90 | [board_82598] = &ixgbe_82598_info, |
91 | [board_82599] = &ixgbe_82599_info, | |
92 | [board_X540] = &ixgbe_X540_info, | |
93 | [board_X550] = &ixgbe_X550_info, | |
94 | [board_X550EM_x] = &ixgbe_X550EM_x_info, | |
9a799d71 AK |
95 | }; |
96 | ||
97 | /* ixgbe_pci_tbl - PCI Device ID Table | |
98 | * | |
99 | * Wildcard entries (PCI_ANY_ID) should come last | |
100 | * Last entry must be all 0s | |
101 | * | |
102 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
103 | * Class, Class Mask, private data (not used) } | |
104 | */ | |
9baa3c34 | 105 | static const struct pci_device_id ixgbe_pci_tbl[] = { |
54239c67 AD |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
117 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
118 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
119 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
120 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
121 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
122 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
123 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
124 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
125 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
126 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
127 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
128 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
129 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
130 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
131 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
8f58332b | 132 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, |
7d145282 | 133 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 134 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
df376f0d | 135 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, |
6a14ee0c DS |
136 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, |
137 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, | |
138 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, | |
deda562a | 139 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, |
018d7146 | 140 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, |
9a799d71 AK |
141 | /* required last entry */ |
142 | {0, } | |
143 | }; | |
144 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
145 | ||
5dd2d332 | 146 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 147 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 148 | void *p); |
bd0362dd JC |
149 | static struct notifier_block dca_notifier = { |
150 | .notifier_call = ixgbe_notify_dca, | |
151 | .next = NULL, | |
152 | .priority = 0 | |
153 | }; | |
154 | #endif | |
155 | ||
1cdd1ec8 GR |
156 | #ifdef CONFIG_PCI_IOV |
157 | static unsigned int max_vfs; | |
158 | module_param(max_vfs, uint, 0); | |
e8e9f696 | 159 | MODULE_PARM_DESC(max_vfs, |
170e8543 | 160 | "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); |
1cdd1ec8 GR |
161 | #endif /* CONFIG_PCI_IOV */ |
162 | ||
8ef78adc PWJ |
163 | static unsigned int allow_unsupported_sfp; |
164 | module_param(allow_unsupported_sfp, uint, 0); | |
165 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
166 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
167 | ||
b3f4d599 | 168 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
169 | static int debug = -1; | |
170 | module_param(debug, int, 0); | |
171 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
172 | ||
9a799d71 AK |
173 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
174 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
175 | MODULE_LICENSE("GPL"); | |
176 | MODULE_VERSION(DRV_VERSION); | |
177 | ||
780484d8 MR |
178 | static struct workqueue_struct *ixgbe_wq; |
179 | ||
14438464 MR |
180 | static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); |
181 | ||
b8e82001 JK |
182 | static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, |
183 | u32 reg, u16 *value) | |
184 | { | |
b8e82001 JK |
185 | struct pci_dev *parent_dev; |
186 | struct pci_bus *parent_bus; | |
187 | ||
188 | parent_bus = adapter->pdev->bus->parent; | |
189 | if (!parent_bus) | |
190 | return -1; | |
191 | ||
192 | parent_dev = parent_bus->self; | |
193 | if (!parent_dev) | |
194 | return -1; | |
195 | ||
c0798edf | 196 | if (!pci_is_pcie(parent_dev)) |
b8e82001 JK |
197 | return -1; |
198 | ||
c0798edf | 199 | pcie_capability_read_word(parent_dev, reg, value); |
14438464 MR |
200 | if (*value == IXGBE_FAILED_READ_CFG_WORD && |
201 | ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) | |
202 | return -1; | |
b8e82001 JK |
203 | return 0; |
204 | } | |
205 | ||
206 | static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) | |
207 | { | |
208 | struct ixgbe_hw *hw = &adapter->hw; | |
209 | u16 link_status = 0; | |
210 | int err; | |
211 | ||
212 | hw->bus.type = ixgbe_bus_type_pci_express; | |
213 | ||
214 | /* Get the negotiated link width and speed from PCI config space of the | |
215 | * parent, as this device is behind a switch | |
216 | */ | |
217 | err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); | |
218 | ||
219 | /* assume caller will handle error case */ | |
220 | if (err) | |
221 | return err; | |
222 | ||
223 | hw->bus.width = ixgbe_convert_bus_width(link_status); | |
224 | hw->bus.speed = ixgbe_convert_bus_speed(link_status); | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
e027d1ae JK |
229 | /** |
230 | * ixgbe_check_from_parent - Determine whether PCIe info should come from parent | |
231 | * @hw: hw specific details | |
232 | * | |
233 | * This function is used by probe to determine whether a device's PCI-Express | |
234 | * bandwidth details should be gathered from the parent bus instead of from the | |
235 | * device. Used to ensure that various locations all have the correct device ID | |
236 | * checks. | |
237 | */ | |
238 | static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) | |
239 | { | |
240 | switch (hw->device_id) { | |
241 | case IXGBE_DEV_ID_82599_SFP_SF_QP: | |
8f58332b | 242 | case IXGBE_DEV_ID_82599_QSFP_SF_QP: |
e027d1ae JK |
243 | return true; |
244 | default: | |
245 | return false; | |
246 | } | |
247 | } | |
248 | ||
249 | static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, | |
250 | int expected_gts) | |
251 | { | |
f9328bc6 | 252 | struct ixgbe_hw *hw = &adapter->hw; |
e027d1ae JK |
253 | int max_gts = 0; |
254 | enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; | |
255 | enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; | |
256 | struct pci_dev *pdev; | |
257 | ||
f9328bc6 DS |
258 | /* Some devices are not connected over PCIe and thus do not negotiate |
259 | * speed. These devices do not have valid bus info, and thus any report | |
260 | * we generate may not be correct. | |
261 | */ | |
262 | if (hw->bus.type == ixgbe_bus_type_internal) | |
263 | return; | |
264 | ||
56d1392f | 265 | /* determine whether to use the parent device */ |
e027d1ae JK |
266 | if (ixgbe_pcie_from_parent(&adapter->hw)) |
267 | pdev = adapter->pdev->bus->parent->self; | |
268 | else | |
269 | pdev = adapter->pdev; | |
270 | ||
271 | if (pcie_get_minimum_link(pdev, &speed, &width) || | |
272 | speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { | |
273 | e_dev_warn("Unable to determine PCI Express bandwidth.\n"); | |
274 | return; | |
275 | } | |
276 | ||
277 | switch (speed) { | |
278 | case PCIE_SPEED_2_5GT: | |
279 | /* 8b/10b encoding reduces max throughput by 20% */ | |
280 | max_gts = 2 * width; | |
281 | break; | |
282 | case PCIE_SPEED_5_0GT: | |
283 | /* 8b/10b encoding reduces max throughput by 20% */ | |
284 | max_gts = 4 * width; | |
285 | break; | |
286 | case PCIE_SPEED_8_0GT: | |
9f0a433c | 287 | /* 128b/130b encoding reduces throughput by less than 2% */ |
e027d1ae JK |
288 | max_gts = 8 * width; |
289 | break; | |
290 | default: | |
291 | e_dev_warn("Unable to determine PCI Express bandwidth.\n"); | |
292 | return; | |
293 | } | |
294 | ||
295 | e_dev_info("PCI Express bandwidth of %dGT/s available\n", | |
296 | max_gts); | |
297 | e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", | |
298 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : | |
299 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : | |
300 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : | |
301 | "Unknown"), | |
302 | width, | |
303 | (speed == PCIE_SPEED_2_5GT ? "20%" : | |
304 | speed == PCIE_SPEED_5_0GT ? "20%" : | |
9f0a433c | 305 | speed == PCIE_SPEED_8_0GT ? "<2%" : |
e027d1ae JK |
306 | "Unknown")); |
307 | ||
308 | if (max_gts < expected_gts) { | |
309 | e_dev_warn("This is not sufficient for optimal performance of this card.\n"); | |
310 | e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", | |
311 | expected_gts); | |
312 | e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); | |
313 | } | |
314 | } | |
315 | ||
7086400d AD |
316 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
317 | { | |
318 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
09f40aed | 319 | !test_bit(__IXGBE_REMOVING, &adapter->state) && |
7086400d | 320 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) |
780484d8 | 321 | queue_work(ixgbe_wq, &adapter->service_task); |
7086400d AD |
322 | } |
323 | ||
2a1a091c MR |
324 | static void ixgbe_remove_adapter(struct ixgbe_hw *hw) |
325 | { | |
326 | struct ixgbe_adapter *adapter = hw->back; | |
327 | ||
328 | if (!hw->hw_addr) | |
329 | return; | |
330 | hw->hw_addr = NULL; | |
331 | e_dev_err("Adapter removed\n"); | |
58cf663f MR |
332 | if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) |
333 | ixgbe_service_event_schedule(adapter); | |
2a1a091c MR |
334 | } |
335 | ||
f8e2472f | 336 | static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) |
2a1a091c MR |
337 | { |
338 | u32 value; | |
339 | ||
340 | /* The following check not only optimizes a bit by not | |
341 | * performing a read on the status register when the | |
342 | * register just read was a status register read that | |
343 | * returned IXGBE_FAILED_READ_REG. It also blocks any | |
344 | * potential recursion. | |
345 | */ | |
346 | if (reg == IXGBE_STATUS) { | |
347 | ixgbe_remove_adapter(hw); | |
348 | return; | |
349 | } | |
350 | value = ixgbe_read_reg(hw, IXGBE_STATUS); | |
351 | if (value == IXGBE_FAILED_READ_REG) | |
352 | ixgbe_remove_adapter(hw); | |
353 | } | |
354 | ||
f8e2472f MR |
355 | /** |
356 | * ixgbe_read_reg - Read from device register | |
357 | * @hw: hw specific details | |
358 | * @reg: offset of register to read | |
359 | * | |
360 | * Returns : value read or IXGBE_FAILED_READ_REG if removed | |
361 | * | |
362 | * This function is used to read device registers. It checks for device | |
363 | * removal by confirming any read that returns all ones by checking the | |
364 | * status register value for all ones. This function avoids reading from | |
365 | * the hardware if a removal was previously detected in which case it | |
366 | * returns IXGBE_FAILED_READ_REG (all ones). | |
367 | */ | |
368 | u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) | |
369 | { | |
370 | u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); | |
371 | u32 value; | |
372 | ||
373 | if (ixgbe_removed(reg_addr)) | |
374 | return IXGBE_FAILED_READ_REG; | |
375 | value = readl(reg_addr + reg); | |
376 | if (unlikely(value == IXGBE_FAILED_READ_REG)) | |
377 | ixgbe_check_remove(hw, reg); | |
378 | return value; | |
379 | } | |
380 | ||
14438464 MR |
381 | static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) |
382 | { | |
383 | u16 value; | |
384 | ||
385 | pci_read_config_word(pdev, PCI_VENDOR_ID, &value); | |
386 | if (value == IXGBE_FAILED_READ_CFG_WORD) { | |
387 | ixgbe_remove_adapter(hw); | |
388 | return true; | |
389 | } | |
390 | return false; | |
391 | } | |
392 | ||
393 | u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) | |
394 | { | |
395 | struct ixgbe_adapter *adapter = hw->back; | |
396 | u16 value; | |
397 | ||
398 | if (ixgbe_removed(hw->hw_addr)) | |
399 | return IXGBE_FAILED_READ_CFG_WORD; | |
400 | pci_read_config_word(adapter->pdev, reg, &value); | |
401 | if (value == IXGBE_FAILED_READ_CFG_WORD && | |
402 | ixgbe_check_cfg_remove(hw, adapter->pdev)) | |
403 | return IXGBE_FAILED_READ_CFG_WORD; | |
404 | return value; | |
405 | } | |
406 | ||
407 | #ifdef CONFIG_PCI_IOV | |
408 | static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) | |
409 | { | |
410 | struct ixgbe_adapter *adapter = hw->back; | |
411 | u32 value; | |
412 | ||
413 | if (ixgbe_removed(hw->hw_addr)) | |
414 | return IXGBE_FAILED_READ_CFG_DWORD; | |
415 | pci_read_config_dword(adapter->pdev, reg, &value); | |
416 | if (value == IXGBE_FAILED_READ_CFG_DWORD && | |
417 | ixgbe_check_cfg_remove(hw, adapter->pdev)) | |
418 | return IXGBE_FAILED_READ_CFG_DWORD; | |
419 | return value; | |
420 | } | |
421 | #endif /* CONFIG_PCI_IOV */ | |
422 | ||
ed19231c JK |
423 | void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) |
424 | { | |
425 | struct ixgbe_adapter *adapter = hw->back; | |
426 | ||
427 | if (ixgbe_removed(hw->hw_addr)) | |
428 | return; | |
429 | pci_write_config_word(adapter->pdev, reg, value); | |
430 | } | |
431 | ||
7086400d AD |
432 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) |
433 | { | |
434 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
435 | ||
52f33af8 | 436 | /* flush memory to make sure state is correct before next watchdog */ |
4e857c58 | 437 | smp_mb__before_atomic(); |
7086400d AD |
438 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); |
439 | } | |
440 | ||
dcd79aeb TI |
441 | struct ixgbe_reg_info { |
442 | u32 ofs; | |
443 | char *name; | |
444 | }; | |
445 | ||
446 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
447 | ||
448 | /* General Registers */ | |
449 | {IXGBE_CTRL, "CTRL"}, | |
450 | {IXGBE_STATUS, "STATUS"}, | |
451 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
452 | ||
453 | /* Interrupt Registers */ | |
454 | {IXGBE_EICR, "EICR"}, | |
455 | ||
456 | /* RX Registers */ | |
457 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
458 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
459 | {IXGBE_RDLEN(0), "RDLEN"}, | |
460 | {IXGBE_RDH(0), "RDH"}, | |
461 | {IXGBE_RDT(0), "RDT"}, | |
462 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
463 | {IXGBE_RDBAL(0), "RDBAL"}, | |
464 | {IXGBE_RDBAH(0), "RDBAH"}, | |
465 | ||
466 | /* TX Registers */ | |
467 | {IXGBE_TDBAL(0), "TDBAL"}, | |
468 | {IXGBE_TDBAH(0), "TDBAH"}, | |
469 | {IXGBE_TDLEN(0), "TDLEN"}, | |
470 | {IXGBE_TDH(0), "TDH"}, | |
471 | {IXGBE_TDT(0), "TDT"}, | |
472 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
473 | ||
474 | /* List Terminator */ | |
ca8dfe25 | 475 | { .name = NULL } |
dcd79aeb TI |
476 | }; |
477 | ||
478 | ||
479 | /* | |
480 | * ixgbe_regdump - register printout routine | |
481 | */ | |
482 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
483 | { | |
484 | int i = 0, j = 0; | |
485 | char rname[16]; | |
486 | u32 regs[64]; | |
487 | ||
488 | switch (reginfo->ofs) { | |
489 | case IXGBE_SRRCTL(0): | |
490 | for (i = 0; i < 64; i++) | |
491 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
492 | break; | |
493 | case IXGBE_DCA_RXCTRL(0): | |
494 | for (i = 0; i < 64; i++) | |
495 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
496 | break; | |
497 | case IXGBE_RDLEN(0): | |
498 | for (i = 0; i < 64; i++) | |
499 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
500 | break; | |
501 | case IXGBE_RDH(0): | |
502 | for (i = 0; i < 64; i++) | |
503 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
504 | break; | |
505 | case IXGBE_RDT(0): | |
506 | for (i = 0; i < 64; i++) | |
507 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
508 | break; | |
509 | case IXGBE_RXDCTL(0): | |
510 | for (i = 0; i < 64; i++) | |
511 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
512 | break; | |
513 | case IXGBE_RDBAL(0): | |
514 | for (i = 0; i < 64; i++) | |
515 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
516 | break; | |
517 | case IXGBE_RDBAH(0): | |
518 | for (i = 0; i < 64; i++) | |
519 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
520 | break; | |
521 | case IXGBE_TDBAL(0): | |
522 | for (i = 0; i < 64; i++) | |
523 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
524 | break; | |
525 | case IXGBE_TDBAH(0): | |
526 | for (i = 0; i < 64; i++) | |
527 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
528 | break; | |
529 | case IXGBE_TDLEN(0): | |
530 | for (i = 0; i < 64; i++) | |
531 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
532 | break; | |
533 | case IXGBE_TDH(0): | |
534 | for (i = 0; i < 64; i++) | |
535 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
536 | break; | |
537 | case IXGBE_TDT(0): | |
538 | for (i = 0; i < 64; i++) | |
539 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
540 | break; | |
541 | case IXGBE_TXDCTL(0): | |
542 | for (i = 0; i < 64; i++) | |
543 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
544 | break; | |
545 | default: | |
c7689578 | 546 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
547 | IXGBE_READ_REG(hw, reginfo->ofs)); |
548 | return; | |
549 | } | |
550 | ||
551 | for (i = 0; i < 8; i++) { | |
552 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 553 | pr_err("%-15s", rname); |
dcd79aeb | 554 | for (j = 0; j < 8; j++) |
c7689578 JP |
555 | pr_cont(" %08x", regs[i*8+j]); |
556 | pr_cont("\n"); | |
dcd79aeb TI |
557 | } |
558 | ||
559 | } | |
560 | ||
561 | /* | |
562 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
563 | */ | |
564 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
565 | { | |
566 | struct net_device *netdev = adapter->netdev; | |
567 | struct ixgbe_hw *hw = &adapter->hw; | |
568 | struct ixgbe_reg_info *reginfo; | |
569 | int n = 0; | |
570 | struct ixgbe_ring *tx_ring; | |
729739b7 | 571 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
572 | union ixgbe_adv_tx_desc *tx_desc; |
573 | struct my_u0 { u64 a; u64 b; } *u0; | |
574 | struct ixgbe_ring *rx_ring; | |
575 | union ixgbe_adv_rx_desc *rx_desc; | |
576 | struct ixgbe_rx_buffer *rx_buffer_info; | |
577 | u32 staterr; | |
578 | int i = 0; | |
579 | ||
580 | if (!netif_msg_hw(adapter)) | |
581 | return; | |
582 | ||
583 | /* Print netdevice Info */ | |
584 | if (netdev) { | |
585 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 586 | pr_info("Device Name state " |
dcd79aeb | 587 | "trans_start last_rx\n"); |
c7689578 JP |
588 | pr_info("%-15s %016lX %016lX %016lX\n", |
589 | netdev->name, | |
590 | netdev->state, | |
591 | netdev->trans_start, | |
592 | netdev->last_rx); | |
dcd79aeb TI |
593 | } |
594 | ||
595 | /* Print Registers */ | |
596 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 597 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
598 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
599 | reginfo->name; reginfo++) { | |
600 | ixgbe_regdump(hw, reginfo); | |
601 | } | |
602 | ||
603 | /* Print TX Ring Summary */ | |
604 | if (!netdev || !netif_running(netdev)) | |
e90dd264 | 605 | return; |
dcd79aeb TI |
606 | |
607 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
8ad88e37 JH |
608 | pr_info(" %s %s %s %s\n", |
609 | "Queue [NTU] [NTC] [bi(ntc)->dma ]", | |
610 | "leng", "ntw", "timestamp"); | |
dcd79aeb TI |
611 | for (n = 0; n < adapter->num_tx_queues; n++) { |
612 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 613 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
8ad88e37 | 614 | pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", |
dcd79aeb | 615 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
616 | (u64)dma_unmap_addr(tx_buffer, dma), |
617 | dma_unmap_len(tx_buffer, len), | |
618 | tx_buffer->next_to_watch, | |
619 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
620 | } |
621 | ||
622 | /* Print TX Rings */ | |
623 | if (!netif_msg_tx_done(adapter)) | |
624 | goto rx_ring_summary; | |
625 | ||
626 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
627 | ||
628 | /* Transmit Descriptor Formats | |
629 | * | |
39ac868a | 630 | * 82598 Advanced Transmit Descriptor |
dcd79aeb TI |
631 | * +--------------------------------------------------------------+ |
632 | * 0 | Buffer Address [63:0] | | |
633 | * +--------------------------------------------------------------+ | |
39ac868a | 634 | * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | |
dcd79aeb TI |
635 | * +--------------------------------------------------------------+ |
636 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
39ac868a JH |
637 | * |
638 | * 82598 Advanced Transmit Descriptor (Write-Back Format) | |
639 | * +--------------------------------------------------------------+ | |
640 | * 0 | RSV [63:0] | | |
641 | * +--------------------------------------------------------------+ | |
642 | * 8 | RSV | STA | NXTSEQ | | |
643 | * +--------------------------------------------------------------+ | |
644 | * 63 36 35 32 31 0 | |
645 | * | |
646 | * 82599+ Advanced Transmit Descriptor | |
647 | * +--------------------------------------------------------------+ | |
648 | * 0 | Buffer Address [63:0] | | |
649 | * +--------------------------------------------------------------+ | |
650 | * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | | |
651 | * +--------------------------------------------------------------+ | |
652 | * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 | |
653 | * | |
654 | * 82599+ Advanced Transmit Descriptor (Write-Back Format) | |
655 | * +--------------------------------------------------------------+ | |
656 | * 0 | RSV [63:0] | | |
657 | * +--------------------------------------------------------------+ | |
658 | * 8 | RSV | STA | RSV | | |
659 | * +--------------------------------------------------------------+ | |
660 | * 63 36 35 32 31 0 | |
dcd79aeb TI |
661 | */ |
662 | ||
663 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
664 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
665 | pr_info("------------------------------------\n"); |
666 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
667 | pr_info("------------------------------------\n"); | |
8ad88e37 JH |
668 | pr_info("%s%s %s %s %s %s\n", |
669 | "T [desc] [address 63:0 ] ", | |
670 | "[PlPOIdStDDt Ln] [bi->dma ] ", | |
671 | "leng", "ntw", "timestamp", "bi->skb"); | |
dcd79aeb TI |
672 | |
673 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 674 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 675 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 676 | u0 = (struct my_u0 *)tx_desc; |
8ad88e37 JH |
677 | if (dma_unmap_len(tx_buffer, len) > 0) { |
678 | pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", | |
679 | i, | |
680 | le64_to_cpu(u0->a), | |
681 | le64_to_cpu(u0->b), | |
682 | (u64)dma_unmap_addr(tx_buffer, dma), | |
729739b7 | 683 | dma_unmap_len(tx_buffer, len), |
8ad88e37 JH |
684 | tx_buffer->next_to_watch, |
685 | (u64)tx_buffer->time_stamp, | |
686 | tx_buffer->skb); | |
687 | if (i == tx_ring->next_to_use && | |
688 | i == tx_ring->next_to_clean) | |
689 | pr_cont(" NTC/U\n"); | |
690 | else if (i == tx_ring->next_to_use) | |
691 | pr_cont(" NTU\n"); | |
692 | else if (i == tx_ring->next_to_clean) | |
693 | pr_cont(" NTC\n"); | |
694 | else | |
695 | pr_cont("\n"); | |
696 | ||
697 | if (netif_msg_pktdata(adapter) && | |
698 | tx_buffer->skb) | |
699 | print_hex_dump(KERN_INFO, "", | |
700 | DUMP_PREFIX_ADDRESS, 16, 1, | |
701 | tx_buffer->skb->data, | |
702 | dma_unmap_len(tx_buffer, len), | |
703 | true); | |
704 | } | |
dcd79aeb TI |
705 | } |
706 | } | |
707 | ||
708 | /* Print RX Rings Summary */ | |
709 | rx_ring_summary: | |
710 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 711 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
712 | for (n = 0; n < adapter->num_rx_queues; n++) { |
713 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
714 | pr_info("%5d %5X %5X\n", |
715 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
716 | } |
717 | ||
718 | /* Print RX Rings */ | |
719 | if (!netif_msg_rx_status(adapter)) | |
e90dd264 | 720 | return; |
dcd79aeb TI |
721 | |
722 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
723 | ||
39ac868a JH |
724 | /* Receive Descriptor Formats |
725 | * | |
726 | * 82598 Advanced Receive Descriptor (Read) Format | |
dcd79aeb TI |
727 | * 63 1 0 |
728 | * +-----------------------------------------------------+ | |
729 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
730 | * +----------------------------------------------+------+ | |
731 | * 8 | Header Buffer Address [63:1] | DD | | |
732 | * +-----------------------------------------------------+ | |
733 | * | |
734 | * | |
39ac868a | 735 | * 82598 Advanced Receive Descriptor (Write-Back) Format |
dcd79aeb TI |
736 | * |
737 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
738 | * +------------------------------------------------------+ | |
39ac868a JH |
739 | * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | |
740 | * | Packet | IP | | | | Type | Type | | |
741 | * | Checksum | Ident | | | | | | | |
dcd79aeb TI |
742 | * +------------------------------------------------------+ |
743 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
744 | * +------------------------------------------------------+ | |
745 | * 63 48 47 32 31 20 19 0 | |
39ac868a JH |
746 | * |
747 | * 82599+ Advanced Receive Descriptor (Read) Format | |
748 | * 63 1 0 | |
749 | * +-----------------------------------------------------+ | |
750 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
751 | * +----------------------------------------------+------+ | |
752 | * 8 | Header Buffer Address [63:1] | DD | | |
753 | * +-----------------------------------------------------+ | |
754 | * | |
755 | * | |
756 | * 82599+ Advanced Receive Descriptor (Write-Back) Format | |
757 | * | |
758 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
759 | * +------------------------------------------------------+ | |
760 | * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | | |
761 | * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | | |
762 | * |/ Flow Dir Flt ID | | | | | | | |
763 | * +------------------------------------------------------+ | |
764 | * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | | |
765 | * +------------------------------------------------------+ | |
766 | * 63 48 47 32 31 20 19 0 | |
dcd79aeb | 767 | */ |
39ac868a | 768 | |
dcd79aeb TI |
769 | for (n = 0; n < adapter->num_rx_queues; n++) { |
770 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
771 | pr_info("------------------------------------\n"); |
772 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
773 | pr_info("------------------------------------\n"); | |
8ad88e37 JH |
774 | pr_info("%s%s%s", |
775 | "R [desc] [ PktBuf A0] ", | |
776 | "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", | |
dcd79aeb | 777 | "<-- Adv Rx Read format\n"); |
8ad88e37 JH |
778 | pr_info("%s%s%s", |
779 | "RWB[desc] [PcsmIpSHl PtRs] ", | |
780 | "[vl er S cks ln] ---------------- [bi->skb ] ", | |
dcd79aeb TI |
781 | "<-- Adv Rx Write-Back format\n"); |
782 | ||
783 | for (i = 0; i < rx_ring->count; i++) { | |
784 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 785 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
786 | u0 = (struct my_u0 *)rx_desc; |
787 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
788 | if (staterr & IXGBE_RXD_STAT_DD) { | |
789 | /* Descriptor Done */ | |
c7689578 | 790 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
791 | "%016llX ---------------- %p", i, |
792 | le64_to_cpu(u0->a), | |
793 | le64_to_cpu(u0->b), | |
794 | rx_buffer_info->skb); | |
795 | } else { | |
c7689578 | 796 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
797 | "%016llX %016llX %p", i, |
798 | le64_to_cpu(u0->a), | |
799 | le64_to_cpu(u0->b), | |
800 | (u64)rx_buffer_info->dma, | |
801 | rx_buffer_info->skb); | |
802 | ||
9c50c035 ET |
803 | if (netif_msg_pktdata(adapter) && |
804 | rx_buffer_info->dma) { | |
dcd79aeb TI |
805 | print_hex_dump(KERN_INFO, "", |
806 | DUMP_PREFIX_ADDRESS, 16, 1, | |
9c50c035 ET |
807 | page_address(rx_buffer_info->page) + |
808 | rx_buffer_info->page_offset, | |
f800326d | 809 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
810 | } |
811 | } | |
812 | ||
813 | if (i == rx_ring->next_to_use) | |
c7689578 | 814 | pr_cont(" NTU\n"); |
dcd79aeb | 815 | else if (i == rx_ring->next_to_clean) |
c7689578 | 816 | pr_cont(" NTC\n"); |
dcd79aeb | 817 | else |
c7689578 | 818 | pr_cont("\n"); |
dcd79aeb TI |
819 | |
820 | } | |
821 | } | |
dcd79aeb TI |
822 | } |
823 | ||
5eba3699 AV |
824 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
825 | { | |
826 | u32 ctrl_ext; | |
827 | ||
828 | /* Let firmware take over control of h/w */ | |
829 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
830 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 831 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
832 | } |
833 | ||
834 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
835 | { | |
836 | u32 ctrl_ext; | |
837 | ||
838 | /* Let firmware know the driver has taken over */ | |
839 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
840 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 841 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 842 | } |
9a799d71 | 843 | |
49ce9c2c | 844 | /** |
e8e26350 PW |
845 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors |
846 | * @adapter: pointer to adapter struct | |
847 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
848 | * @queue: queue to map the corresponding interrupt to | |
849 | * @msix_vector: the vector to map to the corresponding queue | |
850 | * | |
851 | */ | |
852 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 853 | u8 queue, u8 msix_vector) |
9a799d71 AK |
854 | { |
855 | u32 ivar, index; | |
e8e26350 PW |
856 | struct ixgbe_hw *hw = &adapter->hw; |
857 | switch (hw->mac.type) { | |
858 | case ixgbe_mac_82598EB: | |
859 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
860 | if (direction == -1) | |
861 | direction = 0; | |
862 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
863 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
864 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
865 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
866 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
867 | break; | |
868 | case ixgbe_mac_82599EB: | |
b93a2226 | 869 | case ixgbe_mac_X540: |
9a75a1ac DS |
870 | case ixgbe_mac_X550: |
871 | case ixgbe_mac_X550EM_x: | |
e8e26350 PW |
872 | if (direction == -1) { |
873 | /* other causes */ | |
874 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
875 | index = ((queue & 1) * 8); | |
876 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
877 | ivar &= ~(0xFF << index); | |
878 | ivar |= (msix_vector << index); | |
879 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
880 | break; | |
881 | } else { | |
882 | /* tx or rx causes */ | |
883 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
884 | index = ((16 * (queue & 1)) + (8 * direction)); | |
885 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
886 | ivar &= ~(0xFF << index); | |
887 | ivar |= (msix_vector << index); | |
888 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
889 | break; | |
890 | } | |
891 | default: | |
892 | break; | |
893 | } | |
9a799d71 AK |
894 | } |
895 | ||
fe49f04a | 896 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 897 | u64 qmask) |
fe49f04a AD |
898 | { |
899 | u32 mask; | |
900 | ||
bd508178 AD |
901 | switch (adapter->hw.mac.type) { |
902 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
903 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
904 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
905 | break; |
906 | case ixgbe_mac_82599EB: | |
b93a2226 | 907 | case ixgbe_mac_X540: |
9a75a1ac DS |
908 | case ixgbe_mac_X550: |
909 | case ixgbe_mac_X550EM_x: | |
fe49f04a AD |
910 | mask = (qmask & 0xFFFFFFFF); |
911 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
912 | mask = (qmask >> 32); | |
913 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
914 | break; |
915 | default: | |
916 | break; | |
fe49f04a AD |
917 | } |
918 | } | |
919 | ||
729739b7 AD |
920 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
921 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 922 | { |
729739b7 AD |
923 | if (tx_buffer->skb) { |
924 | dev_kfree_skb_any(tx_buffer->skb); | |
925 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 926 | dma_unmap_single(ring->dev, |
729739b7 AD |
927 | dma_unmap_addr(tx_buffer, dma), |
928 | dma_unmap_len(tx_buffer, len), | |
929 | DMA_TO_DEVICE); | |
930 | } else if (dma_unmap_len(tx_buffer, len)) { | |
931 | dma_unmap_page(ring->dev, | |
932 | dma_unmap_addr(tx_buffer, dma), | |
933 | dma_unmap_len(tx_buffer, len), | |
934 | DMA_TO_DEVICE); | |
e5a43549 | 935 | } |
729739b7 AD |
936 | tx_buffer->next_to_watch = NULL; |
937 | tx_buffer->skb = NULL; | |
938 | dma_unmap_len_set(tx_buffer, len, 0); | |
939 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
940 | } |
941 | ||
943561d3 | 942 | static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) |
c84d324c JF |
943 | { |
944 | struct ixgbe_hw *hw = &adapter->hw; | |
945 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
c84d324c | 946 | int i; |
943561d3 | 947 | u32 data; |
c84d324c | 948 | |
943561d3 AD |
949 | if ((hw->fc.current_mode != ixgbe_fc_full) && |
950 | (hw->fc.current_mode != ixgbe_fc_rx_pause)) | |
951 | return; | |
c84d324c | 952 | |
943561d3 AD |
953 | switch (hw->mac.type) { |
954 | case ixgbe_mac_82598EB: | |
955 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
956 | break; | |
957 | default: | |
958 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
959 | } | |
960 | hwstats->lxoffrxc += data; | |
c84d324c | 961 | |
943561d3 AD |
962 | /* refill credits (no tx hang) if we received xoff */ |
963 | if (!data) | |
c84d324c | 964 | return; |
943561d3 AD |
965 | |
966 | for (i = 0; i < adapter->num_tx_queues; i++) | |
967 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
968 | &adapter->tx_ring[i]->state); | |
969 | } | |
970 | ||
971 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
972 | { | |
973 | struct ixgbe_hw *hw = &adapter->hw; | |
974 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
975 | u32 xoff[8] = {0}; | |
2afaa00d | 976 | u8 tc; |
943561d3 AD |
977 | int i; |
978 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
979 | ||
980 | if (adapter->ixgbe_ieee_pfc) | |
981 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
982 | ||
983 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { | |
984 | ixgbe_update_xoff_rx_lfc(adapter); | |
c84d324c | 985 | return; |
943561d3 | 986 | } |
c84d324c JF |
987 | |
988 | /* update stats for each tc, only valid with PFC enabled */ | |
989 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
2afaa00d PN |
990 | u32 pxoffrxc; |
991 | ||
c84d324c JF |
992 | switch (hw->mac.type) { |
993 | case ixgbe_mac_82598EB: | |
2afaa00d | 994 | pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); |
bd508178 | 995 | break; |
c84d324c | 996 | default: |
2afaa00d | 997 | pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); |
26f23d82 | 998 | } |
2afaa00d PN |
999 | hwstats->pxoffrxc[i] += pxoffrxc; |
1000 | /* Get the TC for given UP */ | |
1001 | tc = netdev_get_prio_tc_map(adapter->netdev, i); | |
1002 | xoff[tc] += pxoffrxc; | |
c84d324c JF |
1003 | } |
1004 | ||
1005 | /* disarm tx queues that have received xoff frames */ | |
1006 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1007 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
c84d324c | 1008 | |
2afaa00d | 1009 | tc = tx_ring->dcb_tc; |
c84d324c JF |
1010 | if (xoff[tc]) |
1011 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 1012 | } |
26f23d82 YZ |
1013 | } |
1014 | ||
c84d324c | 1015 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 1016 | { |
7d7ce682 | 1017 | return ring->stats.packets; |
c84d324c JF |
1018 | } |
1019 | ||
1020 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
1021 | { | |
2a47fa45 JF |
1022 | struct ixgbe_adapter *adapter; |
1023 | struct ixgbe_hw *hw; | |
1024 | u32 head, tail; | |
1025 | ||
1026 | if (ring->l2_accel_priv) | |
1027 | adapter = ring->l2_accel_priv->real_adapter; | |
1028 | else | |
1029 | adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 1030 | |
2a47fa45 JF |
1031 | hw = &adapter->hw; |
1032 | head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); | |
1033 | tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
c84d324c JF |
1034 | |
1035 | if (head != tail) | |
1036 | return (head < tail) ? | |
1037 | tail - head : (tail + ring->count - head); | |
1038 | ||
1039 | return 0; | |
1040 | } | |
1041 | ||
1042 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
1043 | { | |
1044 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
1045 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
1046 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
c84d324c | 1047 | |
7d637bcc | 1048 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
1049 | |
1050 | /* | |
1051 | * Check for a hung queue, but be thorough. This verifies | |
1052 | * that a transmit has been completed since the previous | |
1053 | * check AND there is at least one packet pending. The | |
1054 | * ARMED bit is set to indicate a potential hang. The | |
1055 | * bit is cleared if a pause frame is received to remove | |
1056 | * false hang detection due to PFC or 802.3x frames. By | |
1057 | * requiring this to fail twice we avoid races with | |
1058 | * pfc clearing the ARMED bit and conditions where we | |
1059 | * run the check_tx_hang logic with a transmit completion | |
1060 | * pending but without time to complete it yet. | |
1061 | */ | |
e90dd264 | 1062 | if (tx_done_old == tx_done && tx_pending) |
c84d324c | 1063 | /* make sure it is true for two checks in a row */ |
e90dd264 MR |
1064 | return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, |
1065 | &tx_ring->state); | |
1066 | /* update completed stats and continue */ | |
1067 | tx_ring->tx_stats.tx_done_old = tx_done; | |
1068 | /* reset the countdown */ | |
1069 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 | 1070 | |
e90dd264 | 1071 | return false; |
9a799d71 AK |
1072 | } |
1073 | ||
c83c6cbd AD |
1074 | /** |
1075 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
1076 | * @adapter: driver private struct | |
1077 | **/ | |
1078 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
1079 | { | |
1080 | ||
1081 | /* Do the reset outside of interrupt context */ | |
1082 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1083 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
12ff3f3b | 1084 | e_warn(drv, "initiating reset due to tx timeout\n"); |
c83c6cbd AD |
1085 | ixgbe_service_event_schedule(adapter); |
1086 | } | |
1087 | } | |
e01c31a5 | 1088 | |
9a799d71 AK |
1089 | /** |
1090 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 1091 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 1092 | * @tx_ring: tx ring to clean |
9a799d71 | 1093 | **/ |
fe49f04a | 1094 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
a3a8749d | 1095 | struct ixgbe_ring *tx_ring, int napi_budget) |
9a799d71 | 1096 | { |
fe49f04a | 1097 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
1098 | struct ixgbe_tx_buffer *tx_buffer; |
1099 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 1100 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 1101 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
1102 | unsigned int i = tx_ring->next_to_clean; |
1103 | ||
1104 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
1105 | return true; | |
9a799d71 | 1106 | |
d3d00239 | 1107 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 1108 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 1109 | i -= tx_ring->count; |
12207e49 | 1110 | |
729739b7 | 1111 | do { |
d3d00239 AD |
1112 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
1113 | ||
1114 | /* if next_to_watch is not set then there is no work pending */ | |
1115 | if (!eop_desc) | |
1116 | break; | |
1117 | ||
7f83a9e6 | 1118 | /* prevent any other reads prior to eop_desc */ |
7e63bf49 | 1119 | read_barrier_depends(); |
7f83a9e6 | 1120 | |
d3d00239 AD |
1121 | /* if DD is not set pending work has not been completed */ |
1122 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
1123 | break; | |
8ad494b0 | 1124 | |
d3d00239 AD |
1125 | /* clear next_to_watch to prevent false hangs */ |
1126 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 1127 | |
091a6246 AD |
1128 | /* update the statistics for this packet */ |
1129 | total_bytes += tx_buffer->bytecount; | |
1130 | total_packets += tx_buffer->gso_segs; | |
1131 | ||
fd0db0ed | 1132 | /* free the skb */ |
a3a8749d | 1133 | napi_consume_skb(tx_buffer->skb, napi_budget); |
fd0db0ed | 1134 | |
729739b7 AD |
1135 | /* unmap skb header data */ |
1136 | dma_unmap_single(tx_ring->dev, | |
1137 | dma_unmap_addr(tx_buffer, dma), | |
1138 | dma_unmap_len(tx_buffer, len), | |
1139 | DMA_TO_DEVICE); | |
1140 | ||
fd0db0ed AD |
1141 | /* clear tx_buffer data */ |
1142 | tx_buffer->skb = NULL; | |
729739b7 | 1143 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 1144 | |
729739b7 AD |
1145 | /* unmap remaining buffers */ |
1146 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
1147 | tx_buffer++; |
1148 | tx_desc++; | |
8ad494b0 | 1149 | i++; |
729739b7 AD |
1150 | if (unlikely(!i)) { |
1151 | i -= tx_ring->count; | |
d3d00239 | 1152 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 1153 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 1154 | } |
e01c31a5 | 1155 | |
729739b7 AD |
1156 | /* unmap any remaining paged data */ |
1157 | if (dma_unmap_len(tx_buffer, len)) { | |
1158 | dma_unmap_page(tx_ring->dev, | |
1159 | dma_unmap_addr(tx_buffer, dma), | |
1160 | dma_unmap_len(tx_buffer, len), | |
1161 | DMA_TO_DEVICE); | |
1162 | dma_unmap_len_set(tx_buffer, len, 0); | |
1163 | } | |
1164 | } | |
1165 | ||
1166 | /* move us one more past the eop_desc for start of next pkt */ | |
1167 | tx_buffer++; | |
1168 | tx_desc++; | |
1169 | i++; | |
1170 | if (unlikely(!i)) { | |
1171 | i -= tx_ring->count; | |
1172 | tx_buffer = tx_ring->tx_buffer_info; | |
1173 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
1174 | } | |
1175 | ||
1176 | /* issue prefetch for next Tx descriptor */ | |
1177 | prefetch(tx_desc); | |
12207e49 | 1178 | |
729739b7 AD |
1179 | /* update budget accounting */ |
1180 | budget--; | |
1181 | } while (likely(budget)); | |
1182 | ||
1183 | i += tx_ring->count; | |
9a799d71 | 1184 | tx_ring->next_to_clean = i; |
d3d00239 | 1185 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 1186 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 1187 | tx_ring->stats.packets += total_packets; |
d3d00239 | 1188 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
1189 | q_vector->tx.total_bytes += total_bytes; |
1190 | q_vector->tx.total_packets += total_packets; | |
b953799e | 1191 | |
c84d324c JF |
1192 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
1193 | /* schedule immediate reset if we believe we hung */ | |
1194 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
1195 | e_err(drv, "Detected Tx Unit Hang\n" |
1196 | " Tx Queue <%d>\n" | |
1197 | " TDH, TDT <%x>, <%x>\n" | |
1198 | " next_to_use <%x>\n" | |
1199 | " next_to_clean <%x>\n" | |
1200 | "tx_buffer_info[next_to_clean]\n" | |
1201 | " time_stamp <%lx>\n" | |
1202 | " jiffies <%lx>\n", | |
1203 | tx_ring->queue_index, | |
1204 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
1205 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
1206 | tx_ring->next_to_use, i, |
1207 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
1208 | |
1209 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
1210 | ||
1211 | e_info(probe, | |
1212 | "tx hang %d detected on queue %d, resetting adapter\n", | |
1213 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
1214 | ||
b953799e | 1215 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 1216 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
1217 | |
1218 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 1219 | return true; |
b953799e | 1220 | } |
9a799d71 | 1221 | |
b2d96e0a AD |
1222 | netdev_tx_completed_queue(txring_txq(tx_ring), |
1223 | total_packets, total_bytes); | |
1224 | ||
e092be60 | 1225 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 1226 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 1227 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
1228 | /* Make sure that anybody stopping the queue after this |
1229 | * sees the new next_to_clean. | |
1230 | */ | |
1231 | smp_mb(); | |
729739b7 AD |
1232 | if (__netif_subqueue_stopped(tx_ring->netdev, |
1233 | tx_ring->queue_index) | |
1234 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1235 | netif_wake_subqueue(tx_ring->netdev, | |
1236 | tx_ring->queue_index); | |
5b7da515 | 1237 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 1238 | } |
e092be60 | 1239 | } |
9a799d71 | 1240 | |
59224555 | 1241 | return !!budget; |
9a799d71 AK |
1242 | } |
1243 | ||
5dd2d332 | 1244 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
1245 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
1246 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 1247 | int cpu) |
bd0362dd | 1248 | { |
33cf09c9 | 1249 | struct ixgbe_hw *hw = &adapter->hw; |
9de7605e | 1250 | u32 txctrl = 0; |
bdda1a61 | 1251 | u16 reg_offset; |
33cf09c9 | 1252 | |
9de7605e MR |
1253 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1254 | txctrl = dca3_get_tag(tx_ring->dev, cpu); | |
1255 | ||
33cf09c9 AD |
1256 | switch (hw->mac.type) { |
1257 | case ixgbe_mac_82598EB: | |
bdda1a61 | 1258 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
1259 | break; |
1260 | case ixgbe_mac_82599EB: | |
b93a2226 | 1261 | case ixgbe_mac_X540: |
bdda1a61 AD |
1262 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
1263 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
1264 | break; |
1265 | default: | |
bdda1a61 AD |
1266 | /* for unknown hardware do not write register */ |
1267 | return; | |
bd0362dd | 1268 | } |
bdda1a61 AD |
1269 | |
1270 | /* | |
1271 | * We can enable relaxed ordering for reads, but not writes when | |
1272 | * DCA is enabled. This is due to a known issue in some chipsets | |
1273 | * which will cause the DCA tag to be cleared. | |
1274 | */ | |
1275 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
1276 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
1277 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
1278 | ||
1279 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
1280 | } |
1281 | ||
bdda1a61 AD |
1282 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
1283 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 1284 | int cpu) |
bd0362dd | 1285 | { |
33cf09c9 | 1286 | struct ixgbe_hw *hw = &adapter->hw; |
9de7605e | 1287 | u32 rxctrl = 0; |
bdda1a61 AD |
1288 | u8 reg_idx = rx_ring->reg_idx; |
1289 | ||
9de7605e MR |
1290 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1291 | rxctrl = dca3_get_tag(rx_ring->dev, cpu); | |
33cf09c9 AD |
1292 | |
1293 | switch (hw->mac.type) { | |
33cf09c9 | 1294 | case ixgbe_mac_82599EB: |
b93a2226 | 1295 | case ixgbe_mac_X540: |
bdda1a61 | 1296 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
1297 | break; |
1298 | default: | |
1299 | break; | |
1300 | } | |
bdda1a61 AD |
1301 | |
1302 | /* | |
1303 | * We can enable relaxed ordering for reads, but not writes when | |
1304 | * DCA is enabled. This is due to a known issue in some chipsets | |
1305 | * which will cause the DCA tag to be cleared. | |
1306 | */ | |
1307 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
9de7605e | 1308 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | |
bdda1a61 AD |
1309 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
1310 | ||
1311 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
1312 | } |
1313 | ||
1314 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
1315 | { | |
1316 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 1317 | struct ixgbe_ring *ring; |
bd0362dd | 1318 | int cpu = get_cpu(); |
bd0362dd | 1319 | |
33cf09c9 AD |
1320 | if (q_vector->cpu == cpu) |
1321 | goto out_no_update; | |
1322 | ||
a557928e | 1323 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 1324 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 1325 | |
a557928e | 1326 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 1327 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
1328 | |
1329 | q_vector->cpu = cpu; | |
1330 | out_no_update: | |
bd0362dd JC |
1331 | put_cpu(); |
1332 | } | |
1333 | ||
1334 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
1335 | { | |
1336 | int i; | |
1337 | ||
e35ec126 | 1338 | /* always use CB2 mode, difference is masked in the CB driver */ |
9de7605e MR |
1339 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1340 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, | |
1341 | IXGBE_DCA_CTRL_DCA_MODE_CB2); | |
1342 | else | |
1343 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, | |
1344 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
e35ec126 | 1345 | |
49c7ffbe | 1346 | for (i = 0; i < adapter->num_q_vectors; i++) { |
33cf09c9 AD |
1347 | adapter->q_vector[i]->cpu = -1; |
1348 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1349 | } |
1350 | } | |
1351 | ||
1352 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1353 | { | |
c60fbb00 | 1354 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1355 | unsigned long event = *(unsigned long *)data; |
1356 | ||
2a72c31e | 1357 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1358 | return 0; |
1359 | ||
bd0362dd JC |
1360 | switch (event) { |
1361 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1362 | /* if we're already enabled, don't do it again */ |
1363 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1364 | break; | |
652f093f | 1365 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1366 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
9de7605e MR |
1367 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
1368 | IXGBE_DCA_CTRL_DCA_MODE_CB2); | |
bd0362dd JC |
1369 | break; |
1370 | } | |
1371 | /* Fall Through since DCA is disabled. */ | |
1372 | case DCA_PROVIDER_REMOVE: | |
1373 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1374 | dca_remove_requester(dev); | |
1375 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
9de7605e MR |
1376 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
1377 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
bd0362dd JC |
1378 | } |
1379 | break; | |
1380 | } | |
1381 | ||
652f093f | 1382 | return 0; |
bd0362dd | 1383 | } |
67a74ee2 | 1384 | |
bdda1a61 | 1385 | #endif /* CONFIG_IXGBE_DCA */ |
7edda4b8 FD |
1386 | |
1387 | #define IXGBE_RSS_L4_TYPES_MASK \ | |
1388 | ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ | |
1389 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ | |
1390 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ | |
1391 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) | |
1392 | ||
8a0da21b AD |
1393 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1394 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1395 | struct sk_buff *skb) |
1396 | { | |
7edda4b8 FD |
1397 | u16 rss_type; |
1398 | ||
1399 | if (!(ring->netdev->features & NETIF_F_RXHASH)) | |
1400 | return; | |
1401 | ||
1402 | rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & | |
1403 | IXGBE_RXDADV_RSSTYPE_MASK; | |
1404 | ||
1405 | if (!rss_type) | |
1406 | return; | |
1407 | ||
1408 | skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), | |
1409 | (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? | |
1410 | PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); | |
67a74ee2 ET |
1411 | } |
1412 | ||
f800326d | 1413 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1414 | /** |
1415 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
57efd44c | 1416 | * @ring: structure containing ring specific data |
ff886dfc AD |
1417 | * @rx_desc: advanced rx descriptor |
1418 | * | |
1419 | * Returns : true if it is FCoE pkt | |
1420 | */ | |
57efd44c | 1421 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, |
ff886dfc AD |
1422 | union ixgbe_adv_rx_desc *rx_desc) |
1423 | { | |
1424 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1425 | ||
57efd44c | 1426 | return test_bit(__IXGBE_RX_FCOE, &ring->state) && |
ff886dfc AD |
1427 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == |
1428 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1429 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1430 | } | |
1431 | ||
f800326d | 1432 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1433 | /** |
1434 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1435 | * @ring: structure containing ring specific data |
1436 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1437 | * @skb: skb currently being received and modified |
1438 | **/ | |
8a0da21b | 1439 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1440 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1441 | struct sk_buff *skb) |
9a799d71 | 1442 | { |
3f207800 DS |
1443 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
1444 | __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
1445 | bool encap_pkt = false; | |
1446 | ||
8a0da21b | 1447 | skb_checksum_none_assert(skb); |
9a799d71 | 1448 | |
712744be | 1449 | /* Rx csum disabled */ |
8a0da21b | 1450 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1451 | return; |
e59bd25d | 1452 | |
3f207800 DS |
1453 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) && |
1454 | (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) { | |
1455 | encap_pkt = true; | |
1456 | skb->encapsulation = 1; | |
3f207800 DS |
1457 | } |
1458 | ||
e59bd25d | 1459 | /* if IP and error */ |
f56e0cb1 AD |
1460 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1461 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1462 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1463 | return; |
1464 | } | |
e59bd25d | 1465 | |
f56e0cb1 | 1466 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1467 | return; |
1468 | ||
f56e0cb1 | 1469 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
8bae1b2b DS |
1470 | /* |
1471 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1472 | * checksum errors. | |
1473 | */ | |
8a0da21b AD |
1474 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1475 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1476 | return; |
1477 | ||
8a0da21b | 1478 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1479 | return; |
1480 | } | |
1481 | ||
9a799d71 | 1482 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1483 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
3f207800 DS |
1484 | if (encap_pkt) { |
1485 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) | |
1486 | return; | |
1487 | ||
1488 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { | |
d469251b | 1489 | skb->ip_summed = CHECKSUM_NONE; |
3f207800 DS |
1490 | return; |
1491 | } | |
1492 | /* If we checked the outer header let the stack know */ | |
1493 | skb->csum_level = 1; | |
1494 | } | |
9a799d71 AK |
1495 | } |
1496 | ||
f990b79b AD |
1497 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1498 | struct ixgbe_rx_buffer *bi) | |
1499 | { | |
1500 | struct page *page = bi->page; | |
18cb652a | 1501 | dma_addr_t dma; |
f990b79b | 1502 | |
f800326d | 1503 | /* since we are recycling buffers we should seldom need to alloc */ |
18cb652a | 1504 | if (likely(page)) |
f990b79b AD |
1505 | return true; |
1506 | ||
f800326d | 1507 | /* alloc new page for storage */ |
18cb652a AD |
1508 | page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); |
1509 | if (unlikely(!page)) { | |
1510 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1511 | return false; | |
f990b79b AD |
1512 | } |
1513 | ||
f800326d AD |
1514 | /* map page for use */ |
1515 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1516 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1517 | ||
1518 | /* | |
1519 | * if mapping failed free memory back to system since | |
1520 | * there isn't much point in holding memory we can't use | |
1521 | */ | |
1522 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
dd411ec4 | 1523 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
f990b79b | 1524 | |
f990b79b AD |
1525 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1526 | return false; | |
1527 | } | |
1528 | ||
f800326d | 1529 | bi->dma = dma; |
18cb652a | 1530 | bi->page = page; |
afaa9459 | 1531 | bi->page_offset = 0; |
f800326d | 1532 | |
f990b79b AD |
1533 | return true; |
1534 | } | |
1535 | ||
9a799d71 | 1536 | /** |
f990b79b | 1537 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1538 | * @rx_ring: ring to place buffers on |
1539 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1540 | **/ |
fc77dc3c | 1541 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1542 | { |
9a799d71 | 1543 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1544 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1545 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1546 | |
f800326d AD |
1547 | /* nothing to do */ |
1548 | if (!cleaned_count) | |
fc77dc3c AD |
1549 | return; |
1550 | ||
e4f74028 | 1551 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1552 | bi = &rx_ring->rx_buffer_info[i]; |
1553 | i -= rx_ring->count; | |
9a799d71 | 1554 | |
f800326d AD |
1555 | do { |
1556 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1557 | break; |
d5f398ed | 1558 | |
f800326d AD |
1559 | /* |
1560 | * Refresh the desc even if buffer_addrs didn't change | |
1561 | * because each write-back erases this info. | |
1562 | */ | |
1563 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1564 | |
f990b79b AD |
1565 | rx_desc++; |
1566 | bi++; | |
9a799d71 | 1567 | i++; |
f990b79b | 1568 | if (unlikely(!i)) { |
e4f74028 | 1569 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1570 | bi = rx_ring->rx_buffer_info; |
1571 | i -= rx_ring->count; | |
1572 | } | |
1573 | ||
18cb652a AD |
1574 | /* clear the status bits for the next_to_use descriptor */ |
1575 | rx_desc->wb.upper.status_error = 0; | |
f800326d AD |
1576 | |
1577 | cleaned_count--; | |
1578 | } while (cleaned_count); | |
7c6e0a43 | 1579 | |
f990b79b AD |
1580 | i += rx_ring->count; |
1581 | ||
ad435ec6 AD |
1582 | if (rx_ring->next_to_use != i) { |
1583 | rx_ring->next_to_use = i; | |
1584 | ||
1585 | /* update next to alloc since we have filled the ring */ | |
1586 | rx_ring->next_to_alloc = i; | |
1587 | ||
1588 | /* Force memory writes to complete before letting h/w | |
1589 | * know there are new descriptors to fetch. (Only | |
1590 | * applicable for weak-ordered memory model archs, | |
1591 | * such as IA-64). | |
1592 | */ | |
1593 | wmb(); | |
1594 | writel(i, rx_ring->tail); | |
1595 | } | |
9a799d71 AK |
1596 | } |
1597 | ||
1d2024f6 AD |
1598 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1599 | struct sk_buff *skb) | |
1600 | { | |
f800326d | 1601 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1602 | |
1603 | /* set gso_size to avoid messing up TCP MSS */ | |
1604 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1605 | IXGBE_CB(skb)->append_cnt); | |
96be80ab | 1606 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; |
1d2024f6 AD |
1607 | } |
1608 | ||
1609 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1610 | struct sk_buff *skb) | |
1611 | { | |
1612 | /* if append_cnt is 0 then frame is not RSC */ | |
1613 | if (!IXGBE_CB(skb)->append_cnt) | |
1614 | return; | |
1615 | ||
1616 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1617 | rx_ring->rx_stats.rsc_flush++; | |
1618 | ||
1619 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1620 | ||
1621 | /* gso_size is computed using append_cnt so always clear it last */ | |
1622 | IXGBE_CB(skb)->append_cnt = 0; | |
1623 | } | |
1624 | ||
8a0da21b AD |
1625 | /** |
1626 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1627 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1628 | * @rx_desc: pointer to the EOP Rx descriptor | |
1629 | * @skb: pointer to current skb being populated | |
f8212f97 | 1630 | * |
8a0da21b AD |
1631 | * This function checks the ring, descriptor, and packet information in |
1632 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1633 | * other fields within the skb. | |
f8212f97 | 1634 | **/ |
8a0da21b AD |
1635 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1636 | union ixgbe_adv_rx_desc *rx_desc, | |
1637 | struct sk_buff *skb) | |
f8212f97 | 1638 | { |
43e95f11 | 1639 | struct net_device *dev = rx_ring->netdev; |
a9763f3c | 1640 | u32 flags = rx_ring->q_vector->adapter->flags; |
43e95f11 | 1641 | |
8a0da21b AD |
1642 | ixgbe_update_rsc_stats(rx_ring, skb); |
1643 | ||
1644 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1645 | |
8a0da21b AD |
1646 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1647 | ||
a9763f3c MR |
1648 | if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) |
1649 | ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); | |
3a6a4eda | 1650 | |
f646968f | 1651 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
43e95f11 | 1652 | ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { |
8a0da21b | 1653 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); |
86a9bad3 | 1654 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
f8212f97 AD |
1655 | } |
1656 | ||
8a0da21b | 1657 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1658 | |
43e95f11 | 1659 | skb->protocol = eth_type_trans(skb, dev); |
f8212f97 AD |
1660 | } |
1661 | ||
8a0da21b AD |
1662 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1663 | struct sk_buff *skb) | |
aa80175a | 1664 | { |
93f93a44 | 1665 | skb_mark_napi_id(skb, &q_vector->napi); |
b4640030 | 1666 | if (ixgbe_qv_busy_polling(q_vector)) |
5a85e737 | 1667 | netif_receive_skb(skb); |
8a0da21b | 1668 | else |
856f606e | 1669 | napi_gro_receive(&q_vector->napi, skb); |
aa80175a | 1670 | } |
43634e82 | 1671 | |
f800326d AD |
1672 | /** |
1673 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1674 | * @rx_ring: Rx ring being processed | |
1675 | * @rx_desc: Rx descriptor for current buffer | |
1676 | * @skb: Current socket buffer containing buffer in progress | |
1677 | * | |
1678 | * This function updates next to clean. If the buffer is an EOP buffer | |
1679 | * this function exits returning false, otherwise it will place the | |
1680 | * sk_buff in the next buffer to be chained and return true indicating | |
1681 | * that this is in fact a non-EOP buffer. | |
1682 | **/ | |
1683 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1684 | union ixgbe_adv_rx_desc *rx_desc, | |
1685 | struct sk_buff *skb) | |
1686 | { | |
1687 | u32 ntc = rx_ring->next_to_clean + 1; | |
1688 | ||
1689 | /* fetch, update, and store next to clean */ | |
1690 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1691 | rx_ring->next_to_clean = ntc; | |
1692 | ||
1693 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1694 | ||
5a02cbd1 AD |
1695 | /* update RSC append count if present */ |
1696 | if (ring_is_rsc_enabled(rx_ring)) { | |
1697 | __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1698 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1699 | ||
1700 | if (unlikely(rsc_enabled)) { | |
1701 | u32 rsc_cnt = le32_to_cpu(rsc_enabled); | |
1702 | ||
1703 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1704 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
f800326d | 1705 | |
5a02cbd1 AD |
1706 | /* update ntc based on RSC value */ |
1707 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1708 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1709 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1710 | } | |
f800326d AD |
1711 | } |
1712 | ||
5a02cbd1 AD |
1713 | /* if we are the last buffer then there is nothing else to do */ |
1714 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1715 | return false; | |
1716 | ||
f800326d AD |
1717 | /* place skb in next buffer to be received */ |
1718 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1719 | rx_ring->rx_stats.non_eop_descs++; | |
1720 | ||
1721 | return true; | |
1722 | } | |
1723 | ||
19861ce2 AD |
1724 | /** |
1725 | * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail | |
1726 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1727 | * @skb: pointer to current skb being adjusted | |
1728 | * | |
1729 | * This function is an ixgbe specific version of __pskb_pull_tail. The | |
1730 | * main difference between this version and the original function is that | |
1731 | * this function can make several assumptions about the state of things | |
1732 | * that allow for significant optimizations versus the standard function. | |
1733 | * As a result we can do things like drop a frag and maintain an accurate | |
1734 | * truesize for the skb. | |
1735 | */ | |
1736 | static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, | |
1737 | struct sk_buff *skb) | |
1738 | { | |
1739 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1740 | unsigned char *va; | |
1741 | unsigned int pull_len; | |
1742 | ||
1743 | /* | |
1744 | * it is valid to use page_address instead of kmap since we are | |
1745 | * working with pages allocated out of the lomem pool per | |
1746 | * alloc_page(GFP_ATOMIC) | |
1747 | */ | |
1748 | va = skb_frag_address(frag); | |
1749 | ||
1750 | /* | |
1751 | * we need the header to contain the greater of either ETH_HLEN or | |
1752 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1753 | */ | |
8496e338 | 1754 | pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); |
19861ce2 AD |
1755 | |
1756 | /* align pull length to size of long to optimize memcpy performance */ | |
1757 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1758 | ||
1759 | /* update all of the pointers */ | |
1760 | skb_frag_size_sub(frag, pull_len); | |
1761 | frag->page_offset += pull_len; | |
1762 | skb->data_len -= pull_len; | |
1763 | skb->tail += pull_len; | |
19861ce2 AD |
1764 | } |
1765 | ||
42073d91 AD |
1766 | /** |
1767 | * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB | |
1768 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1769 | * @skb: pointer to current skb being updated | |
1770 | * | |
1771 | * This function provides a basic DMA sync up for the first fragment of an | |
1772 | * skb. The reason for doing this is that the first fragment cannot be | |
1773 | * unmapped until we have reached the end of packet descriptor for a buffer | |
1774 | * chain. | |
1775 | */ | |
1776 | static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, | |
1777 | struct sk_buff *skb) | |
1778 | { | |
1779 | /* if the page was released unmap it, else just sync our portion */ | |
1780 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1781 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1782 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1783 | IXGBE_CB(skb)->page_released = false; | |
1784 | } else { | |
1785 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1786 | ||
1787 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1788 | IXGBE_CB(skb)->dma, | |
1789 | frag->page_offset, | |
1790 | ixgbe_rx_bufsz(rx_ring), | |
1791 | DMA_FROM_DEVICE); | |
1792 | } | |
1793 | IXGBE_CB(skb)->dma = 0; | |
1794 | } | |
1795 | ||
f800326d AD |
1796 | /** |
1797 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1798 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1799 | * @rx_desc: pointer to the EOP Rx descriptor | |
1800 | * @skb: pointer to current skb being fixed | |
1801 | * | |
1802 | * Check for corrupted packet headers caused by senders on the local L2 | |
1803 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1804 | * should be very rare. | |
1805 | * | |
1806 | * Also address the case where we are pulling data in on pages only | |
1807 | * and as such no data is present in the skb header. | |
1808 | * | |
1809 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1810 | * it is large enough to qualify as a valid Ethernet frame. | |
1811 | * | |
1812 | * Returns true if an error was encountered and skb was freed. | |
1813 | **/ | |
1814 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1815 | union ixgbe_adv_rx_desc *rx_desc, | |
1816 | struct sk_buff *skb) | |
1817 | { | |
f800326d | 1818 | struct net_device *netdev = rx_ring->netdev; |
f800326d AD |
1819 | |
1820 | /* verify that the packet does not have any known errors */ | |
1821 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1822 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1823 | !(netdev->features & NETIF_F_RXALL))) { | |
1824 | dev_kfree_skb_any(skb); | |
1825 | return true; | |
1826 | } | |
1827 | ||
19861ce2 | 1828 | /* place header in linear portion of buffer */ |
cf3fe7ac AD |
1829 | if (skb_is_nonlinear(skb)) |
1830 | ixgbe_pull_tail(rx_ring, skb); | |
f800326d | 1831 | |
57efd44c AD |
1832 | #ifdef IXGBE_FCOE |
1833 | /* do not attempt to pad FCoE Frames as this will disrupt DDP */ | |
1834 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) | |
1835 | return false; | |
1836 | ||
1837 | #endif | |
a94d9e22 AD |
1838 | /* if eth_skb_pad returns an error the skb was freed */ |
1839 | if (eth_skb_pad(skb)) | |
1840 | return true; | |
f800326d AD |
1841 | |
1842 | return false; | |
1843 | } | |
1844 | ||
f800326d AD |
1845 | /** |
1846 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1847 | * @rx_ring: rx descriptor ring to store buffers on | |
1848 | * @old_buff: donor buffer to have page reused | |
1849 | * | |
0549ae20 | 1850 | * Synchronizes page for reuse by the adapter |
f800326d AD |
1851 | **/ |
1852 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1853 | struct ixgbe_rx_buffer *old_buff) | |
1854 | { | |
1855 | struct ixgbe_rx_buffer *new_buff; | |
1856 | u16 nta = rx_ring->next_to_alloc; | |
f800326d AD |
1857 | |
1858 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1859 | ||
1860 | /* update, and store next to alloc */ | |
1861 | nta++; | |
1862 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1863 | ||
1864 | /* transfer page from old buffer to new buffer */ | |
18cb652a | 1865 | *new_buff = *old_buff; |
f800326d AD |
1866 | |
1867 | /* sync the buffer for use by the device */ | |
1868 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
0549ae20 AD |
1869 | new_buff->page_offset, |
1870 | ixgbe_rx_bufsz(rx_ring), | |
f800326d | 1871 | DMA_FROM_DEVICE); |
f800326d AD |
1872 | } |
1873 | ||
18cb652a AD |
1874 | static inline bool ixgbe_page_is_reserved(struct page *page) |
1875 | { | |
2f064f34 | 1876 | return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); |
18cb652a AD |
1877 | } |
1878 | ||
f800326d AD |
1879 | /** |
1880 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1881 | * @rx_ring: rx descriptor ring to transact packets on | |
1882 | * @rx_buffer: buffer containing page to add | |
1883 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1884 | * @skb: sk_buff to place the data into | |
1885 | * | |
0549ae20 AD |
1886 | * This function will add the data contained in rx_buffer->page to the skb. |
1887 | * This is done either through a direct copy if the data in the buffer is | |
1888 | * less than the skb header size, otherwise it will just attach the page as | |
1889 | * a frag to the skb. | |
1890 | * | |
1891 | * The function will then update the page offset if necessary and return | |
1892 | * true if the buffer can be reused by the adapter. | |
f800326d | 1893 | **/ |
0549ae20 | 1894 | static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, |
f800326d | 1895 | struct ixgbe_rx_buffer *rx_buffer, |
0549ae20 AD |
1896 | union ixgbe_adv_rx_desc *rx_desc, |
1897 | struct sk_buff *skb) | |
f800326d | 1898 | { |
0549ae20 AD |
1899 | struct page *page = rx_buffer->page; |
1900 | unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); | |
09816fbe | 1901 | #if (PAGE_SIZE < 8192) |
0549ae20 | 1902 | unsigned int truesize = ixgbe_rx_bufsz(rx_ring); |
09816fbe AD |
1903 | #else |
1904 | unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); | |
1905 | unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - | |
1906 | ixgbe_rx_bufsz(rx_ring); | |
1907 | #endif | |
0549ae20 | 1908 | |
cf3fe7ac AD |
1909 | if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { |
1910 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
1911 | ||
1912 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); | |
1913 | ||
18cb652a AD |
1914 | /* page is not reserved, we can reuse buffer as-is */ |
1915 | if (likely(!ixgbe_page_is_reserved(page))) | |
cf3fe7ac AD |
1916 | return true; |
1917 | ||
1918 | /* this page cannot be reused so discard it */ | |
18cb652a | 1919 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
cf3fe7ac AD |
1920 | return false; |
1921 | } | |
1922 | ||
0549ae20 AD |
1923 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, |
1924 | rx_buffer->page_offset, size, truesize); | |
1925 | ||
09816fbe | 1926 | /* avoid re-using remote pages */ |
18cb652a | 1927 | if (unlikely(ixgbe_page_is_reserved(page))) |
09816fbe AD |
1928 | return false; |
1929 | ||
1930 | #if (PAGE_SIZE < 8192) | |
1931 | /* if we are only owner of page we can reuse it */ | |
1932 | if (unlikely(page_count(page) != 1)) | |
0549ae20 AD |
1933 | return false; |
1934 | ||
1935 | /* flip page offset to other buffer */ | |
1936 | rx_buffer->page_offset ^= truesize; | |
09816fbe AD |
1937 | #else |
1938 | /* move offset up to the next cache line */ | |
1939 | rx_buffer->page_offset += truesize; | |
1940 | ||
1941 | if (rx_buffer->page_offset > last_offset) | |
1942 | return false; | |
09816fbe | 1943 | #endif |
0549ae20 | 1944 | |
18cb652a AD |
1945 | /* Even if we own the page, we are not allowed to use atomic_set() |
1946 | * This would break get_page_unless_zero() users. | |
1947 | */ | |
1948 | atomic_inc(&page->_count); | |
1949 | ||
0549ae20 | 1950 | return true; |
f800326d AD |
1951 | } |
1952 | ||
18806c9e AD |
1953 | static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, |
1954 | union ixgbe_adv_rx_desc *rx_desc) | |
1955 | { | |
1956 | struct ixgbe_rx_buffer *rx_buffer; | |
1957 | struct sk_buff *skb; | |
1958 | struct page *page; | |
1959 | ||
1960 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
1961 | page = rx_buffer->page; | |
1962 | prefetchw(page); | |
1963 | ||
1964 | skb = rx_buffer->skb; | |
1965 | ||
1966 | if (likely(!skb)) { | |
1967 | void *page_addr = page_address(page) + | |
1968 | rx_buffer->page_offset; | |
1969 | ||
1970 | /* prefetch first cache line of first page */ | |
1971 | prefetch(page_addr); | |
1972 | #if L1_CACHE_BYTES < 128 | |
1973 | prefetch(page_addr + L1_CACHE_BYTES); | |
1974 | #endif | |
1975 | ||
1976 | /* allocate a skb to store the frags */ | |
67fd893e AD |
1977 | skb = napi_alloc_skb(&rx_ring->q_vector->napi, |
1978 | IXGBE_RX_HDR_SIZE); | |
18806c9e AD |
1979 | if (unlikely(!skb)) { |
1980 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1981 | return NULL; | |
1982 | } | |
1983 | ||
1984 | /* | |
1985 | * we will be copying header into skb->data in | |
1986 | * pskb_may_pull so it is in our interest to prefetch | |
1987 | * it now to avoid a possible cache miss | |
1988 | */ | |
1989 | prefetchw(skb->data); | |
1990 | ||
1991 | /* | |
1992 | * Delay unmapping of the first packet. It carries the | |
1993 | * header information, HW may still access the header | |
1994 | * after the writeback. Only unmap it when EOP is | |
1995 | * reached | |
1996 | */ | |
1997 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1998 | goto dma_sync; | |
1999 | ||
2000 | IXGBE_CB(skb)->dma = rx_buffer->dma; | |
2001 | } else { | |
2002 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) | |
2003 | ixgbe_dma_sync_frag(rx_ring, skb); | |
2004 | ||
2005 | dma_sync: | |
2006 | /* we are reusing so sync this buffer for CPU use */ | |
2007 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
2008 | rx_buffer->dma, | |
2009 | rx_buffer->page_offset, | |
2010 | ixgbe_rx_bufsz(rx_ring), | |
2011 | DMA_FROM_DEVICE); | |
18cb652a AD |
2012 | |
2013 | rx_buffer->skb = NULL; | |
18806c9e AD |
2014 | } |
2015 | ||
2016 | /* pull page into skb */ | |
2017 | if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
2018 | /* hand second half of page back to the ring */ | |
2019 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
2020 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
2021 | /* the page has been released from the ring */ | |
2022 | IXGBE_CB(skb)->page_released = true; | |
2023 | } else { | |
2024 | /* we are not reusing the buffer so unmap it */ | |
2025 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
2026 | ixgbe_rx_pg_size(rx_ring), | |
2027 | DMA_FROM_DEVICE); | |
2028 | } | |
2029 | ||
2030 | /* clear contents of buffer_info */ | |
18806c9e AD |
2031 | rx_buffer->page = NULL; |
2032 | ||
2033 | return skb; | |
f800326d AD |
2034 | } |
2035 | ||
2036 | /** | |
2037 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
2038 | * @q_vector: structure containing interrupt and ring information | |
2039 | * @rx_ring: rx descriptor ring to transact packets on | |
2040 | * @budget: Total limit on number of packets to process | |
2041 | * | |
2042 | * This function provides a "bounce buffer" approach to Rx interrupt | |
2043 | * processing. The advantage to this is that on systems that have | |
2044 | * expensive overhead for IOMMU access this provides a means of avoiding | |
2045 | * it by maintaining the mapping of the page to the syste. | |
2046 | * | |
5a85e737 | 2047 | * Returns amount of work completed |
f800326d | 2048 | **/ |
5a85e737 | 2049 | static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 2050 | struct ixgbe_ring *rx_ring, |
f4de00ed | 2051 | const int budget) |
9a799d71 | 2052 | { |
d2f4fbe2 | 2053 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 2054 | #ifdef IXGBE_FCOE |
f800326d | 2055 | struct ixgbe_adapter *adapter = q_vector->adapter; |
4ffdf91a MR |
2056 | int ddp_bytes; |
2057 | unsigned int mss = 0; | |
3d8fd385 | 2058 | #endif /* IXGBE_FCOE */ |
f800326d | 2059 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 2060 | |
fdabfc8a | 2061 | while (likely(total_rx_packets < budget)) { |
f800326d AD |
2062 | union ixgbe_adv_rx_desc *rx_desc; |
2063 | struct sk_buff *skb; | |
f800326d AD |
2064 | |
2065 | /* return some buffers to hardware, one at a time is too slow */ | |
2066 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
2067 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
2068 | cleaned_count = 0; | |
2069 | } | |
2070 | ||
18806c9e | 2071 | rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); |
f800326d | 2072 | |
124b74c1 | 2073 | if (!rx_desc->wb.upper.status_error) |
f800326d | 2074 | break; |
9a799d71 | 2075 | |
124b74c1 | 2076 | /* This memory barrier is needed to keep us from reading |
f800326d | 2077 | * any other fields out of the rx_desc until we know the |
124b74c1 | 2078 | * descriptor has been written back |
f800326d | 2079 | */ |
124b74c1 | 2080 | dma_rmb(); |
9a799d71 | 2081 | |
18806c9e AD |
2082 | /* retrieve a buffer from the ring */ |
2083 | skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); | |
f800326d | 2084 | |
18806c9e AD |
2085 | /* exit if we failed to retrieve a buffer */ |
2086 | if (!skb) | |
2087 | break; | |
9a799d71 | 2088 | |
9a799d71 | 2089 | cleaned_count++; |
f8212f97 | 2090 | |
f800326d AD |
2091 | /* place incomplete frames back on ring for completion */ |
2092 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
2093 | continue; | |
c267fc16 | 2094 | |
f800326d AD |
2095 | /* verify the packet layout is correct */ |
2096 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
2097 | continue; | |
9a799d71 | 2098 | |
d2f4fbe2 AV |
2099 | /* probably a little skewed due to removing CRC */ |
2100 | total_rx_bytes += skb->len; | |
d2f4fbe2 | 2101 | |
8a0da21b AD |
2102 | /* populate checksum, timestamp, VLAN, and protocol */ |
2103 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
2104 | ||
332d4a7d YZ |
2105 | #ifdef IXGBE_FCOE |
2106 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
57efd44c | 2107 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { |
f56e0cb1 | 2108 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
4ffdf91a MR |
2109 | /* include DDPed FCoE data */ |
2110 | if (ddp_bytes > 0) { | |
2111 | if (!mss) { | |
2112 | mss = rx_ring->netdev->mtu - | |
2113 | sizeof(struct fcoe_hdr) - | |
2114 | sizeof(struct fc_frame_header) - | |
2115 | sizeof(struct fcoe_crc_eof); | |
2116 | if (mss > 512) | |
2117 | mss &= ~511; | |
2118 | } | |
2119 | total_rx_bytes += ddp_bytes; | |
2120 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, | |
2121 | mss); | |
2122 | } | |
63d635b2 AD |
2123 | if (!ddp_bytes) { |
2124 | dev_kfree_skb_any(skb); | |
f800326d | 2125 | continue; |
63d635b2 | 2126 | } |
3d8fd385 | 2127 | } |
f800326d | 2128 | |
332d4a7d | 2129 | #endif /* IXGBE_FCOE */ |
8a0da21b | 2130 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 2131 | |
f800326d | 2132 | /* update budget accounting */ |
f4de00ed | 2133 | total_rx_packets++; |
fdabfc8a | 2134 | } |
9a799d71 | 2135 | |
c267fc16 AD |
2136 | u64_stats_update_begin(&rx_ring->syncp); |
2137 | rx_ring->stats.packets += total_rx_packets; | |
2138 | rx_ring->stats.bytes += total_rx_bytes; | |
2139 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
2140 | q_vector->rx.total_packets += total_rx_packets; |
2141 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 2142 | |
5a85e737 | 2143 | return total_rx_packets; |
9a799d71 AK |
2144 | } |
2145 | ||
e0d1095a | 2146 | #ifdef CONFIG_NET_RX_BUSY_POLL |
5a85e737 ET |
2147 | /* must be called with local_bh_disable()d */ |
2148 | static int ixgbe_low_latency_recv(struct napi_struct *napi) | |
2149 | { | |
2150 | struct ixgbe_q_vector *q_vector = | |
2151 | container_of(napi, struct ixgbe_q_vector, napi); | |
2152 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2153 | struct ixgbe_ring *ring; | |
2154 | int found = 0; | |
2155 | ||
2156 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
2157 | return LL_FLUSH_FAILED; | |
2158 | ||
2159 | if (!ixgbe_qv_lock_poll(q_vector)) | |
2160 | return LL_FLUSH_BUSY; | |
2161 | ||
2162 | ixgbe_for_each_ring(ring, q_vector->rx) { | |
2163 | found = ixgbe_clean_rx_irq(q_vector, ring, 4); | |
b4640030 | 2164 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
2165 | if (found) |
2166 | ring->stats.cleaned += found; | |
2167 | else | |
2168 | ring->stats.misses++; | |
2169 | #endif | |
5a85e737 ET |
2170 | if (found) |
2171 | break; | |
2172 | } | |
2173 | ||
2174 | ixgbe_qv_unlock_poll(q_vector); | |
2175 | ||
2176 | return found; | |
2177 | } | |
e0d1095a | 2178 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 2179 | |
9a799d71 AK |
2180 | /** |
2181 | * ixgbe_configure_msix - Configure MSI-X hardware | |
2182 | * @adapter: board private structure | |
2183 | * | |
2184 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
2185 | * interrupts. | |
2186 | **/ | |
2187 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
2188 | { | |
021230d4 | 2189 | struct ixgbe_q_vector *q_vector; |
49c7ffbe | 2190 | int v_idx; |
021230d4 | 2191 | u32 mask; |
9a799d71 | 2192 | |
8e34d1aa AD |
2193 | /* Populate MSIX to EITR Select */ |
2194 | if (adapter->num_vfs > 32) { | |
2195 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
2196 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
2197 | } | |
2198 | ||
4df10466 JB |
2199 | /* |
2200 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
2201 | * corresponding register. |
2202 | */ | |
49c7ffbe | 2203 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { |
efe3d3c8 | 2204 | struct ixgbe_ring *ring; |
7a921c93 | 2205 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 2206 | |
a557928e | 2207 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
2208 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
2209 | ||
a557928e | 2210 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
2211 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
2212 | ||
fe49f04a | 2213 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
2214 | } |
2215 | ||
bd508178 AD |
2216 | switch (adapter->hw.mac.type) { |
2217 | case ixgbe_mac_82598EB: | |
e8e26350 | 2218 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 2219 | v_idx); |
bd508178 AD |
2220 | break; |
2221 | case ixgbe_mac_82599EB: | |
b93a2226 | 2222 | case ixgbe_mac_X540: |
9a75a1ac DS |
2223 | case ixgbe_mac_X550: |
2224 | case ixgbe_mac_X550EM_x: | |
e8e26350 | 2225 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 2226 | break; |
bd508178 AD |
2227 | default: |
2228 | break; | |
2229 | } | |
021230d4 AV |
2230 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
2231 | ||
41fb9248 | 2232 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 2233 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
2234 | mask &= ~(IXGBE_EIMS_OTHER | |
2235 | IXGBE_EIMS_MAILBOX | | |
2236 | IXGBE_EIMS_LSC); | |
2237 | ||
021230d4 | 2238 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
2239 | } |
2240 | ||
f494e8fa AV |
2241 | enum latency_range { |
2242 | lowest_latency = 0, | |
2243 | low_latency = 1, | |
2244 | bulk_latency = 2, | |
2245 | latency_invalid = 255 | |
2246 | }; | |
2247 | ||
2248 | /** | |
2249 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
2250 | * @q_vector: structure containing interrupt and ring information |
2251 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
2252 | * |
2253 | * Stores a new ITR value based on packets and byte | |
2254 | * counts during the last interrupt. The advantage of per interrupt | |
2255 | * computation is faster updates and more accurate ITR for the current | |
2256 | * traffic pattern. Constants in this function were computed | |
2257 | * based on theoretical maximum wire speed and thresholds were set based | |
2258 | * on testing data as well as attempting to minimize response time | |
2259 | * while increasing bulk throughput. | |
2260 | * this functionality is controlled by the InterruptThrottleRate module | |
2261 | * parameter (see ixgbe_param.c) | |
2262 | **/ | |
bd198058 AD |
2263 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
2264 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 2265 | { |
bd198058 AD |
2266 | int bytes = ring_container->total_bytes; |
2267 | int packets = ring_container->total_packets; | |
2268 | u32 timepassed_us; | |
621bd70e | 2269 | u64 bytes_perint; |
bd198058 | 2270 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
2271 | |
2272 | if (packets == 0) | |
bd198058 | 2273 | return; |
f494e8fa AV |
2274 | |
2275 | /* simple throttlerate management | |
621bd70e AD |
2276 | * 0-10MB/s lowest (100000 ints/s) |
2277 | * 10-20MB/s low (20000 ints/s) | |
8ac34f10 | 2278 | * 20-1249MB/s bulk (12000 ints/s) |
f494e8fa AV |
2279 | */ |
2280 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 2281 | timepassed_us = q_vector->itr >> 2; |
bdbeefe8 DS |
2282 | if (timepassed_us == 0) |
2283 | return; | |
2284 | ||
f494e8fa AV |
2285 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
2286 | ||
2287 | switch (itr_setting) { | |
2288 | case lowest_latency: | |
621bd70e | 2289 | if (bytes_perint > 10) |
bd198058 | 2290 | itr_setting = low_latency; |
f494e8fa AV |
2291 | break; |
2292 | case low_latency: | |
621bd70e | 2293 | if (bytes_perint > 20) |
bd198058 | 2294 | itr_setting = bulk_latency; |
621bd70e | 2295 | else if (bytes_perint <= 10) |
bd198058 | 2296 | itr_setting = lowest_latency; |
f494e8fa AV |
2297 | break; |
2298 | case bulk_latency: | |
621bd70e | 2299 | if (bytes_perint <= 20) |
bd198058 | 2300 | itr_setting = low_latency; |
f494e8fa AV |
2301 | break; |
2302 | } | |
2303 | ||
bd198058 AD |
2304 | /* clear work counters since we have the values we need */ |
2305 | ring_container->total_bytes = 0; | |
2306 | ring_container->total_packets = 0; | |
2307 | ||
2308 | /* write updated itr to ring container */ | |
2309 | ring_container->itr = itr_setting; | |
f494e8fa AV |
2310 | } |
2311 | ||
509ee935 JB |
2312 | /** |
2313 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 2314 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
2315 | * |
2316 | * This function is made to be called by ethtool and by the driver | |
2317 | * when it needs to update EITR registers at runtime. Hardware | |
2318 | * specific quirks/differences are taken care of here. | |
2319 | */ | |
fe49f04a | 2320 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 2321 | { |
fe49f04a | 2322 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 2323 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2324 | int v_idx = q_vector->v_idx; |
5d967eb7 | 2325 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 2326 | |
bd508178 AD |
2327 | switch (adapter->hw.mac.type) { |
2328 | case ixgbe_mac_82598EB: | |
509ee935 JB |
2329 | /* must write high and low 16 bits to reset counter */ |
2330 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
2331 | break; |
2332 | case ixgbe_mac_82599EB: | |
b93a2226 | 2333 | case ixgbe_mac_X540: |
9a75a1ac DS |
2334 | case ixgbe_mac_X550: |
2335 | case ixgbe_mac_X550EM_x: | |
509ee935 JB |
2336 | /* |
2337 | * set the WDIS bit to not clear the timer bits and cause an | |
2338 | * immediate assertion of the interrupt | |
2339 | */ | |
2340 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
2341 | break; |
2342 | default: | |
2343 | break; | |
509ee935 JB |
2344 | } |
2345 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
2346 | } | |
2347 | ||
bd198058 | 2348 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 2349 | { |
d5bf4f67 | 2350 | u32 new_itr = q_vector->itr; |
bd198058 | 2351 | u8 current_itr; |
f494e8fa | 2352 | |
bd198058 AD |
2353 | ixgbe_update_itr(q_vector, &q_vector->tx); |
2354 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 2355 | |
08c8833b | 2356 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
2357 | |
2358 | switch (current_itr) { | |
2359 | /* counts and packets in update_itr are dependent on these numbers */ | |
2360 | case lowest_latency: | |
d5bf4f67 | 2361 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
2362 | break; |
2363 | case low_latency: | |
d5bf4f67 | 2364 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
2365 | break; |
2366 | case bulk_latency: | |
8ac34f10 | 2367 | new_itr = IXGBE_12K_ITR; |
f494e8fa | 2368 | break; |
bd198058 AD |
2369 | default: |
2370 | break; | |
f494e8fa AV |
2371 | } |
2372 | ||
d5bf4f67 | 2373 | if (new_itr != q_vector->itr) { |
fe49f04a | 2374 | /* do an exponential smoothing */ |
d5bf4f67 ET |
2375 | new_itr = (10 * new_itr * q_vector->itr) / |
2376 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 2377 | |
bd198058 | 2378 | /* save the algorithm value here */ |
5d967eb7 | 2379 | q_vector->itr = new_itr; |
fe49f04a AD |
2380 | |
2381 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2382 | } |
f494e8fa AV |
2383 | } |
2384 | ||
119fc60a | 2385 | /** |
de88eeeb | 2386 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2387 | * @adapter: pointer to adapter |
119fc60a | 2388 | **/ |
f0f9778d | 2389 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2390 | { |
119fc60a MC |
2391 | struct ixgbe_hw *hw = &adapter->hw; |
2392 | u32 eicr = adapter->interrupt_event; | |
2393 | ||
f0f9778d | 2394 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2395 | return; |
2396 | ||
f0f9778d AD |
2397 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2398 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2399 | return; | |
2400 | ||
2401 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2402 | ||
7ca647bd | 2403 | switch (hw->device_id) { |
f0f9778d AD |
2404 | case IXGBE_DEV_ID_82599_T3_LOM: |
2405 | /* | |
2406 | * Since the warning interrupt is for both ports | |
2407 | * we don't have to check if: | |
2408 | * - This interrupt wasn't for our port. | |
2409 | * - We may have missed the interrupt so always have to | |
2410 | * check if we got a LSC | |
2411 | */ | |
9a900eca | 2412 | if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && |
f0f9778d AD |
2413 | !(eicr & IXGBE_EICR_LSC)) |
2414 | return; | |
2415 | ||
2416 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
3d292265 | 2417 | u32 speed; |
f0f9778d | 2418 | bool link_up = false; |
7ca647bd | 2419 | |
3d292265 | 2420 | hw->mac.ops.check_link(hw, &speed, &link_up, false); |
7ca647bd | 2421 | |
f0f9778d AD |
2422 | if (link_up) |
2423 | return; | |
2424 | } | |
2425 | ||
2426 | /* Check if this is not due to overtemp */ | |
2427 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2428 | return; | |
2429 | ||
2430 | break; | |
7ca647bd | 2431 | default: |
597f22d6 DS |
2432 | if (adapter->hw.mac.type >= ixgbe_mac_X540) |
2433 | return; | |
9a900eca | 2434 | if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) |
119fc60a | 2435 | return; |
7ca647bd | 2436 | break; |
119fc60a | 2437 | } |
f44e751b | 2438 | e_crit(drv, "%s\n", ixgbe_overheat_msg); |
f0f9778d AD |
2439 | |
2440 | adapter->interrupt_event = 0; | |
119fc60a MC |
2441 | } |
2442 | ||
0befdb3e JB |
2443 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2444 | { | |
2445 | struct ixgbe_hw *hw = &adapter->hw; | |
2446 | ||
2447 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
9a900eca | 2448 | (eicr & IXGBE_EICR_GPI_SDP1(hw))) { |
396e799c | 2449 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e | 2450 | /* write to clear the interrupt */ |
9a900eca | 2451 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); |
0befdb3e JB |
2452 | } |
2453 | } | |
cf8280ee | 2454 | |
4f51bf70 JK |
2455 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2456 | { | |
9a900eca DS |
2457 | struct ixgbe_hw *hw = &adapter->hw; |
2458 | ||
4f51bf70 JK |
2459 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) |
2460 | return; | |
2461 | ||
2462 | switch (adapter->hw.mac.type) { | |
2463 | case ixgbe_mac_82599EB: | |
2464 | /* | |
2465 | * Need to check link state so complete overtemp check | |
2466 | * on service task | |
2467 | */ | |
9a900eca DS |
2468 | if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || |
2469 | (eicr & IXGBE_EICR_LSC)) && | |
4f51bf70 JK |
2470 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { |
2471 | adapter->interrupt_event = eicr; | |
2472 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2473 | ixgbe_service_event_schedule(adapter); | |
2474 | return; | |
2475 | } | |
2476 | return; | |
2477 | case ixgbe_mac_X540: | |
2478 | if (!(eicr & IXGBE_EICR_TS)) | |
2479 | return; | |
2480 | break; | |
2481 | default: | |
2482 | return; | |
2483 | } | |
2484 | ||
f44e751b | 2485 | e_crit(drv, "%s\n", ixgbe_overheat_msg); |
4f51bf70 JK |
2486 | } |
2487 | ||
45788d2a DS |
2488 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2489 | { | |
2490 | switch (hw->mac.type) { | |
2491 | case ixgbe_mac_82598EB: | |
2492 | if (hw->phy.type == ixgbe_phy_nl) | |
2493 | return true; | |
2494 | return false; | |
2495 | case ixgbe_mac_82599EB: | |
2496 | case ixgbe_mac_X550EM_x: | |
2497 | switch (hw->mac.ops.get_media_type(hw)) { | |
2498 | case ixgbe_media_type_fiber: | |
2499 | case ixgbe_media_type_fiber_qsfp: | |
2500 | return true; | |
2501 | default: | |
2502 | return false; | |
2503 | } | |
2504 | default: | |
2505 | return false; | |
2506 | } | |
2507 | } | |
2508 | ||
e8e26350 PW |
2509 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2510 | { | |
2511 | struct ixgbe_hw *hw = &adapter->hw; | |
4ccc650c | 2512 | u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); |
e8e26350 | 2513 | |
4ccc650c DS |
2514 | if (!ixgbe_is_sfp(hw)) |
2515 | return; | |
2516 | ||
2517 | /* Later MAC's use different SDP */ | |
2518 | if (hw->mac.type >= ixgbe_mac_X540) | |
2519 | eicr_mask = IXGBE_EICR_GPI_SDP0_X540; | |
2520 | ||
2521 | if (eicr & eicr_mask) { | |
73c4b7cd | 2522 | /* Clear the interrupt */ |
4ccc650c | 2523 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); |
7086400d AD |
2524 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2525 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
58e7cd24 | 2526 | adapter->sfp_poll_time = 0; |
7086400d AD |
2527 | ixgbe_service_event_schedule(adapter); |
2528 | } | |
73c4b7cd AD |
2529 | } |
2530 | ||
4ccc650c DS |
2531 | if (adapter->hw.mac.type == ixgbe_mac_82599EB && |
2532 | (eicr & IXGBE_EICR_GPI_SDP1(hw))) { | |
e8e26350 | 2533 | /* Clear the interrupt */ |
9a900eca | 2534 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); |
7086400d AD |
2535 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2536 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2537 | ixgbe_service_event_schedule(adapter); | |
2538 | } | |
e8e26350 PW |
2539 | } |
2540 | } | |
2541 | ||
cf8280ee JB |
2542 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2543 | { | |
2544 | struct ixgbe_hw *hw = &adapter->hw; | |
2545 | ||
2546 | adapter->lsc_int++; | |
2547 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2548 | adapter->link_check_timeout = jiffies; | |
2549 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2550 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2551 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2552 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2553 | } |
2554 | } | |
2555 | ||
fe49f04a AD |
2556 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2557 | u64 qmask) | |
2558 | { | |
2559 | u32 mask; | |
bd508178 | 2560 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2561 | |
bd508178 AD |
2562 | switch (hw->mac.type) { |
2563 | case ixgbe_mac_82598EB: | |
fe49f04a | 2564 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2565 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2566 | break; | |
2567 | case ixgbe_mac_82599EB: | |
b93a2226 | 2568 | case ixgbe_mac_X540: |
9a75a1ac DS |
2569 | case ixgbe_mac_X550: |
2570 | case ixgbe_mac_X550EM_x: | |
fe49f04a | 2571 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2572 | if (mask) |
2573 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2574 | mask = (qmask >> 32); |
bd508178 AD |
2575 | if (mask) |
2576 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2577 | break; | |
2578 | default: | |
2579 | break; | |
fe49f04a AD |
2580 | } |
2581 | /* skip the flush */ | |
2582 | } | |
2583 | ||
2584 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2585 | u64 qmask) |
fe49f04a AD |
2586 | { |
2587 | u32 mask; | |
bd508178 | 2588 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2589 | |
bd508178 AD |
2590 | switch (hw->mac.type) { |
2591 | case ixgbe_mac_82598EB: | |
fe49f04a | 2592 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2593 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2594 | break; | |
2595 | case ixgbe_mac_82599EB: | |
b93a2226 | 2596 | case ixgbe_mac_X540: |
9a75a1ac DS |
2597 | case ixgbe_mac_X550: |
2598 | case ixgbe_mac_X550EM_x: | |
fe49f04a | 2599 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2600 | if (mask) |
2601 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2602 | mask = (qmask >> 32); |
bd508178 AD |
2603 | if (mask) |
2604 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2605 | break; | |
2606 | default: | |
2607 | break; | |
fe49f04a AD |
2608 | } |
2609 | /* skip the flush */ | |
2610 | } | |
2611 | ||
021230d4 | 2612 | /** |
2c4af694 AD |
2613 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2614 | * @adapter: board private structure | |
021230d4 | 2615 | **/ |
2c4af694 AD |
2616 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2617 | bool flush) | |
9a799d71 | 2618 | { |
9a900eca | 2619 | struct ixgbe_hw *hw = &adapter->hw; |
2c4af694 | 2620 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2621 | |
2c4af694 AD |
2622 | /* don't reenable LSC while waiting for link */ |
2623 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2624 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2625 | |
2c4af694 | 2626 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2627 | switch (adapter->hw.mac.type) { |
2628 | case ixgbe_mac_82599EB: | |
9a900eca | 2629 | mask |= IXGBE_EIMS_GPI_SDP0(hw); |
4f51bf70 JK |
2630 | break; |
2631 | case ixgbe_mac_X540: | |
9a75a1ac DS |
2632 | case ixgbe_mac_X550: |
2633 | case ixgbe_mac_X550EM_x: | |
4f51bf70 JK |
2634 | mask |= IXGBE_EIMS_TS; |
2635 | break; | |
2636 | default: | |
2637 | break; | |
2638 | } | |
2c4af694 | 2639 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
9a900eca | 2640 | mask |= IXGBE_EIMS_GPI_SDP1(hw); |
2c4af694 AD |
2641 | switch (adapter->hw.mac.type) { |
2642 | case ixgbe_mac_82599EB: | |
9a900eca DS |
2643 | mask |= IXGBE_EIMS_GPI_SDP1(hw); |
2644 | mask |= IXGBE_EIMS_GPI_SDP2(hw); | |
9a75a1ac | 2645 | /* fall through */ |
858bc081 | 2646 | case ixgbe_mac_X540: |
9a75a1ac DS |
2647 | case ixgbe_mac_X550: |
2648 | case ixgbe_mac_X550EM_x: | |
cbd45ec7 MR |
2649 | if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP) |
2650 | mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); | |
597f22d6 DS |
2651 | if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) |
2652 | mask |= IXGBE_EICR_GPI_SDP0_X540; | |
858bc081 | 2653 | mask |= IXGBE_EIMS_ECC; |
2c4af694 AD |
2654 | mask |= IXGBE_EIMS_MAILBOX; |
2655 | break; | |
2656 | default: | |
2657 | break; | |
9a799d71 | 2658 | } |
db0677fa | 2659 | |
2c4af694 AD |
2660 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2661 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2662 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2663 | |
2c4af694 AD |
2664 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2665 | if (queues) | |
2666 | ixgbe_irq_enable_queues(adapter, ~0); | |
2667 | if (flush) | |
2668 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2669 | } |
2670 | ||
2c4af694 | 2671 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2672 | { |
a65151ba | 2673 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2674 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2675 | u32 eicr; |
91281fd3 | 2676 | |
54037505 DS |
2677 | /* |
2678 | * Workaround for Silicon errata. Use clear-by-write instead | |
2679 | * of clear-by-read. Reading with EICS will return the | |
2680 | * interrupt causes without clearing, which later be done | |
2681 | * with the write to EICR. | |
2682 | */ | |
2683 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
d87d8307 JK |
2684 | |
2685 | /* The lower 16bits of the EICR register are for the queue interrupts | |
dbedd44e | 2686 | * which should be masked here in order to not accidentally clear them if |
d87d8307 JK |
2687 | * the bits are high when ixgbe_msix_other is called. There is a race |
2688 | * condition otherwise which results in possible performance loss | |
2689 | * especially if the ixgbe_msix_other interrupt is triggering | |
2690 | * consistently (as it would when PPS is turned on for the X540 device) | |
2691 | */ | |
2692 | eicr &= 0xFFFF0000; | |
2693 | ||
54037505 | 2694 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); |
33cf09c9 | 2695 | |
cf8280ee JB |
2696 | if (eicr & IXGBE_EICR_LSC) |
2697 | ixgbe_check_lsc(adapter); | |
f0848276 | 2698 | |
1cdd1ec8 GR |
2699 | if (eicr & IXGBE_EICR_MAILBOX) |
2700 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2701 | |
bd508178 AD |
2702 | switch (hw->mac.type) { |
2703 | case ixgbe_mac_82599EB: | |
b93a2226 | 2704 | case ixgbe_mac_X540: |
9a75a1ac DS |
2705 | case ixgbe_mac_X550: |
2706 | case ixgbe_mac_X550EM_x: | |
597f22d6 DS |
2707 | if (hw->phy.type == ixgbe_phy_x550em_ext_t && |
2708 | (eicr & IXGBE_EICR_GPI_SDP0_X540)) { | |
2709 | adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; | |
2710 | ixgbe_service_event_schedule(adapter); | |
2711 | IXGBE_WRITE_REG(hw, IXGBE_EICR, | |
2712 | IXGBE_EICR_GPI_SDP0_X540); | |
2713 | } | |
d773ce2d DS |
2714 | if (eicr & IXGBE_EICR_ECC) { |
2715 | e_info(link, "Received ECC Err, initiating reset\n"); | |
2716 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
2717 | ixgbe_service_event_schedule(adapter); | |
2718 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); | |
2719 | } | |
c4cf55e5 PWJ |
2720 | /* Handle Flow Director Full threshold interrupt */ |
2721 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2722 | int reinit_count = 0; |
c4cf55e5 | 2723 | int i; |
c4cf55e5 | 2724 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2725 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2726 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2727 | &ring->state)) |
2728 | reinit_count++; | |
2729 | } | |
2730 | if (reinit_count) { | |
2731 | /* no more flow director interrupts until after init */ | |
2732 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2733 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2734 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2735 | } |
2736 | } | |
f0f9778d | 2737 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2738 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2739 | break; |
2740 | default: | |
2741 | break; | |
c4cf55e5 | 2742 | } |
f0848276 | 2743 | |
bd508178 | 2744 | ixgbe_check_fan_failure(adapter, eicr); |
db0677fa | 2745 | |
db0677fa | 2746 | if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) |
a9763f3c | 2747 | ixgbe_ptp_check_pps_event(adapter); |
efe3d3c8 | 2748 | |
7086400d | 2749 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2750 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2751 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2752 | |
9a799d71 | 2753 | return IRQ_HANDLED; |
f0848276 | 2754 | } |
91281fd3 | 2755 | |
4ff7fb12 | 2756 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2757 | { |
021230d4 | 2758 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2759 | |
9b471446 | 2760 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2761 | |
4ff7fb12 | 2762 | if (q_vector->rx.ring || q_vector->tx.ring) |
ef2662b2 | 2763 | napi_schedule_irqoff(&q_vector->napi); |
91281fd3 | 2764 | |
9a799d71 | 2765 | return IRQ_HANDLED; |
91281fd3 AD |
2766 | } |
2767 | ||
eb01b975 AD |
2768 | /** |
2769 | * ixgbe_poll - NAPI Rx polling callback | |
2770 | * @napi: structure for representing this polling device | |
2771 | * @budget: how many packets driver is allowed to clean | |
2772 | * | |
2773 | * This function is used for legacy and MSI, NAPI mode | |
2774 | **/ | |
8af3c33f | 2775 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
2776 | { |
2777 | struct ixgbe_q_vector *q_vector = | |
2778 | container_of(napi, struct ixgbe_q_vector, napi); | |
2779 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2780 | struct ixgbe_ring *ring; | |
32b3e08f | 2781 | int per_ring_budget, work_done = 0; |
eb01b975 AD |
2782 | bool clean_complete = true; |
2783 | ||
2784 | #ifdef CONFIG_IXGBE_DCA | |
2785 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2786 | ixgbe_update_dca(q_vector); | |
2787 | #endif | |
2788 | ||
2789 | ixgbe_for_each_ring(ring, q_vector->tx) | |
a3a8749d | 2790 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring, budget); |
eb01b975 | 2791 | |
5d6002b7 AD |
2792 | /* Exit if we are called by netpoll or busy polling is active */ |
2793 | if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector)) | |
5a85e737 ET |
2794 | return budget; |
2795 | ||
eb01b975 AD |
2796 | /* attempt to distribute budget to each queue fairly, but don't allow |
2797 | * the budget to go below 1 because we'll exit polling */ | |
2798 | if (q_vector->rx.count > 1) | |
2799 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2800 | else | |
2801 | per_ring_budget = budget; | |
2802 | ||
32b3e08f JB |
2803 | ixgbe_for_each_ring(ring, q_vector->rx) { |
2804 | int cleaned = ixgbe_clean_rx_irq(q_vector, ring, | |
2805 | per_ring_budget); | |
2806 | ||
2807 | work_done += cleaned; | |
2808 | clean_complete &= (cleaned < per_ring_budget); | |
2809 | } | |
eb01b975 | 2810 | |
5a85e737 | 2811 | ixgbe_qv_unlock_napi(q_vector); |
eb01b975 AD |
2812 | /* If all work not completed, return budget and keep polling */ |
2813 | if (!clean_complete) | |
2814 | return budget; | |
2815 | ||
2816 | /* all work done, exit the polling mode */ | |
32b3e08f | 2817 | napi_complete_done(napi, work_done); |
eb01b975 AD |
2818 | if (adapter->rx_itr_setting & 1) |
2819 | ixgbe_set_itr(q_vector); | |
2820 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2821 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2822 | ||
2823 | return 0; | |
2824 | } | |
2825 | ||
021230d4 AV |
2826 | /** |
2827 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2828 | * @adapter: board private structure | |
2829 | * | |
2830 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2831 | * interrupts from the kernel. | |
2832 | **/ | |
2833 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2834 | { | |
2835 | struct net_device *netdev = adapter->netdev; | |
207867f5 | 2836 | int vector, err; |
e8e9f696 | 2837 | int ri = 0, ti = 0; |
021230d4 | 2838 | |
49c7ffbe | 2839 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
d0759ebb | 2840 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2841 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2842 | |
4ff7fb12 | 2843 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2844 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2845 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2846 | ti++; | |
2847 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2848 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2849 | "%s-%s-%d", netdev->name, "rx", ri++); |
2850 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2851 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2852 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2853 | } else { |
2854 | /* skip this unused q_vector */ | |
2855 | continue; | |
32aa77a4 | 2856 | } |
207867f5 AD |
2857 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2858 | q_vector->name, q_vector); | |
9a799d71 | 2859 | if (err) { |
396e799c | 2860 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2861 | "Error: %d\n", err); |
021230d4 | 2862 | goto free_queue_irqs; |
9a799d71 | 2863 | } |
207867f5 AD |
2864 | /* If Flow Director is enabled, set interrupt affinity */ |
2865 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2866 | /* assign the mask for this irq */ | |
2867 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2868 | &q_vector->affinity_mask); |
207867f5 | 2869 | } |
9a799d71 AK |
2870 | } |
2871 | ||
021230d4 | 2872 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2873 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2874 | if (err) { |
de88eeeb | 2875 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2876 | goto free_queue_irqs; |
9a799d71 AK |
2877 | } |
2878 | ||
9a799d71 AK |
2879 | return 0; |
2880 | ||
021230d4 | 2881 | free_queue_irqs: |
207867f5 AD |
2882 | while (vector) { |
2883 | vector--; | |
2884 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2885 | NULL); | |
2886 | free_irq(adapter->msix_entries[vector].vector, | |
2887 | adapter->q_vector[vector]); | |
2888 | } | |
021230d4 AV |
2889 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2890 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2891 | kfree(adapter->msix_entries); |
2892 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2893 | return err; |
2894 | } | |
2895 | ||
2896 | /** | |
021230d4 | 2897 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2898 | * @irq: interrupt number |
2899 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2900 | **/ |
2901 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2902 | { | |
a65151ba | 2903 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2904 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2905 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2906 | u32 eicr; |
2907 | ||
54037505 | 2908 | /* |
24ddd967 | 2909 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2910 | * before the read of EICR. |
2911 | */ | |
2912 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2913 | ||
021230d4 | 2914 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2915 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2916 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2917 | if (!eicr) { |
6af3b9eb ET |
2918 | /* |
2919 | * shared interrupt alert! | |
f47cf66e | 2920 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2921 | * have disabled interrupts due to EIAM |
2922 | * finish the workaround of silicon errata on 82598. Unmask | |
2923 | * the interrupt that we masked before the EICR read. | |
2924 | */ | |
2925 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2926 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2927 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2928 | } |
9a799d71 | 2929 | |
cf8280ee JB |
2930 | if (eicr & IXGBE_EICR_LSC) |
2931 | ixgbe_check_lsc(adapter); | |
021230d4 | 2932 | |
bd508178 AD |
2933 | switch (hw->mac.type) { |
2934 | case ixgbe_mac_82599EB: | |
e8e26350 | 2935 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2936 | /* Fall through */ |
2937 | case ixgbe_mac_X540: | |
9a75a1ac DS |
2938 | case ixgbe_mac_X550: |
2939 | case ixgbe_mac_X550EM_x: | |
d773ce2d DS |
2940 | if (eicr & IXGBE_EICR_ECC) { |
2941 | e_info(link, "Received ECC Err, initiating reset\n"); | |
2942 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
2943 | ixgbe_service_event_schedule(adapter); | |
2944 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); | |
2945 | } | |
4f51bf70 | 2946 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2947 | break; |
2948 | default: | |
2949 | break; | |
2950 | } | |
e8e26350 | 2951 | |
0befdb3e | 2952 | ixgbe_check_fan_failure(adapter, eicr); |
db0677fa | 2953 | if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) |
a9763f3c | 2954 | ixgbe_ptp_check_pps_event(adapter); |
0befdb3e | 2955 | |
b9f6ed2b | 2956 | /* would disable interrupts here but EIAM disabled it */ |
ef2662b2 | 2957 | napi_schedule_irqoff(&q_vector->napi); |
9a799d71 | 2958 | |
6af3b9eb ET |
2959 | /* |
2960 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2961 | * ixgbe_poll will re-enable the queue interrupts | |
2962 | */ | |
6af3b9eb ET |
2963 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2964 | ixgbe_irq_enable(adapter, false, false); | |
2965 | ||
9a799d71 AK |
2966 | return IRQ_HANDLED; |
2967 | } | |
2968 | ||
2969 | /** | |
2970 | * ixgbe_request_irq - initialize interrupts | |
2971 | * @adapter: board private structure | |
2972 | * | |
2973 | * Attempts to configure interrupts using the best available | |
2974 | * capabilities of the hardware and kernel. | |
2975 | **/ | |
021230d4 | 2976 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2977 | { |
2978 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2979 | int err; |
9a799d71 | 2980 | |
4cc6df29 | 2981 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2982 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2983 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2984 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2985 | netdev->name, adapter); |
4cc6df29 | 2986 | else |
a0607fd3 | 2987 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2988 | netdev->name, adapter); |
9a799d71 | 2989 | |
de88eeeb | 2990 | if (err) |
396e799c | 2991 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2992 | |
9a799d71 AK |
2993 | return err; |
2994 | } | |
2995 | ||
2996 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2997 | { | |
49c7ffbe | 2998 | int vector; |
9a799d71 | 2999 | |
49c7ffbe AD |
3000 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
3001 | free_irq(adapter->pdev->irq, adapter); | |
3002 | return; | |
3003 | } | |
4cc6df29 | 3004 | |
49c7ffbe AD |
3005 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
3006 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; | |
3007 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
894ff7cf | 3008 | |
49c7ffbe AD |
3009 | /* free only the irqs that were actually requested */ |
3010 | if (!q_vector->rx.ring && !q_vector->tx.ring) | |
3011 | continue; | |
207867f5 | 3012 | |
49c7ffbe AD |
3013 | /* clear the affinity_mask in the IRQ descriptor */ |
3014 | irq_set_affinity_hint(entry->vector, NULL); | |
3015 | ||
3016 | free_irq(entry->vector, q_vector); | |
9a799d71 | 3017 | } |
49c7ffbe AD |
3018 | |
3019 | free_irq(adapter->msix_entries[vector++].vector, adapter); | |
9a799d71 AK |
3020 | } |
3021 | ||
22d5a71b JB |
3022 | /** |
3023 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
3024 | * @adapter: board private structure | |
3025 | **/ | |
3026 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
3027 | { | |
bd508178 AD |
3028 | switch (adapter->hw.mac.type) { |
3029 | case ixgbe_mac_82598EB: | |
835462fc | 3030 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
3031 | break; |
3032 | case ixgbe_mac_82599EB: | |
b93a2226 | 3033 | case ixgbe_mac_X540: |
9a75a1ac DS |
3034 | case ixgbe_mac_X550: |
3035 | case ixgbe_mac_X550EM_x: | |
835462fc NS |
3036 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
3037 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 3038 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
3039 | break; |
3040 | default: | |
3041 | break; | |
22d5a71b JB |
3042 | } |
3043 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
3044 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
49c7ffbe AD |
3045 | int vector; |
3046 | ||
3047 | for (vector = 0; vector < adapter->num_q_vectors; vector++) | |
3048 | synchronize_irq(adapter->msix_entries[vector].vector); | |
3049 | ||
3050 | synchronize_irq(adapter->msix_entries[vector++].vector); | |
22d5a71b JB |
3051 | } else { |
3052 | synchronize_irq(adapter->pdev->irq); | |
3053 | } | |
3054 | } | |
3055 | ||
9a799d71 AK |
3056 | /** |
3057 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
3058 | * | |
3059 | **/ | |
3060 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
3061 | { | |
d5bf4f67 | 3062 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 3063 | |
d5bf4f67 | 3064 | ixgbe_write_eitr(q_vector); |
9a799d71 | 3065 | |
e8e26350 PW |
3066 | ixgbe_set_ivar(adapter, 0, 0, 0); |
3067 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 3068 | |
396e799c | 3069 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
3070 | } |
3071 | ||
43e69bf0 AD |
3072 | /** |
3073 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
3074 | * @adapter: board private structure | |
3075 | * @ring: structure containing ring specific data | |
3076 | * | |
3077 | * Configure the Tx descriptor ring after a reset. | |
3078 | **/ | |
84418e3b AD |
3079 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
3080 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
3081 | { |
3082 | struct ixgbe_hw *hw = &adapter->hw; | |
3083 | u64 tdba = ring->dma; | |
2f1860b8 | 3084 | int wait_loop = 10; |
b88c6de2 | 3085 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 3086 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 3087 | |
2f1860b8 | 3088 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 3089 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
3090 | IXGBE_WRITE_FLUSH(hw); |
3091 | ||
43e69bf0 | 3092 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 3093 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
3094 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
3095 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
3096 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
3097 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
3098 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
2a1a091c | 3099 | ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 3100 | |
b88c6de2 AD |
3101 | /* |
3102 | * set WTHRESH to encourage burst writeback, it should not be set | |
67da097e ET |
3103 | * higher than 1 when: |
3104 | * - ITR is 0 as it could cause false TX hangs | |
3105 | * - ITR is set to > 100k int/sec and BQL is enabled | |
b88c6de2 AD |
3106 | * |
3107 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
3108 | * to or less than the number of on chip descriptors, which is | |
3109 | * currently 40. | |
3110 | */ | |
67da097e | 3111 | if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) |
b88c6de2 AD |
3112 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
3113 | else | |
3114 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
3115 | ||
e954b374 AD |
3116 | /* |
3117 | * Setting PTHRESH to 32 both improves performance | |
3118 | * and avoids a TX hang with DFP enabled | |
3119 | */ | |
b88c6de2 AD |
3120 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
3121 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
3122 | |
3123 | /* reinitialize flowdirector state */ | |
39cb681b | 3124 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
ee9e0f0b AD |
3125 | ring->atr_sample_rate = adapter->atr_sample_rate; |
3126 | ring->atr_count = 0; | |
3127 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
3128 | } else { | |
3129 | ring->atr_sample_rate = 0; | |
3130 | } | |
2f1860b8 | 3131 | |
fd786b7b AD |
3132 | /* initialize XPS */ |
3133 | if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { | |
3134 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
3135 | ||
3136 | if (q_vector) | |
2a47fa45 | 3137 | netif_set_xps_queue(ring->netdev, |
fd786b7b AD |
3138 | &q_vector->affinity_mask, |
3139 | ring->queue_index); | |
3140 | } | |
3141 | ||
c84d324c JF |
3142 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
3143 | ||
2f1860b8 | 3144 | /* enable queue */ |
2f1860b8 AD |
3145 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
3146 | ||
3147 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3148 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3149 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3150 | return; | |
3151 | ||
3152 | /* poll to verify queue is enabled */ | |
3153 | do { | |
032b4325 | 3154 | usleep_range(1000, 2000); |
2f1860b8 AD |
3155 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
3156 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
3157 | if (!wait_loop) | |
3158 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
3159 | } |
3160 | ||
120ff942 AD |
3161 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
3162 | { | |
3163 | struct ixgbe_hw *hw = &adapter->hw; | |
671c0adb | 3164 | u32 rttdcs, mtqc; |
8b1c0b24 | 3165 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
3166 | |
3167 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3168 | return; | |
3169 | ||
3170 | /* disable the arbiter while setting MTQC */ | |
3171 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
3172 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
3173 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
3174 | ||
3175 | /* set transmit pool layout */ | |
671c0adb AD |
3176 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
3177 | mtqc = IXGBE_MTQC_VT_ENA; | |
3178 | if (tcs > 4) | |
3179 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
3180 | else if (tcs > 1) | |
3181 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
3182 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
3183 | mtqc |= IXGBE_MTQC_32VF; | |
3184 | else | |
3185 | mtqc |= IXGBE_MTQC_64VF; | |
3186 | } else { | |
3187 | if (tcs > 4) | |
3188 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
3189 | else if (tcs > 1) | |
3190 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
8b1c0b24 | 3191 | else |
671c0adb AD |
3192 | mtqc = IXGBE_MTQC_64Q_1PB; |
3193 | } | |
120ff942 | 3194 | |
671c0adb | 3195 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); |
120ff942 | 3196 | |
671c0adb AD |
3197 | /* Enable Security TX Buffer IFG for multiple pb */ |
3198 | if (tcs) { | |
3199 | u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
3200 | sectx |= IXGBE_SECTX_DCB; | |
3201 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); | |
120ff942 AD |
3202 | } |
3203 | ||
3204 | /* re-enable the arbiter */ | |
3205 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
3206 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
3207 | } | |
3208 | ||
9a799d71 | 3209 | /** |
3a581073 | 3210 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
3211 | * @adapter: board private structure |
3212 | * | |
3213 | * Configure the Tx unit of the MAC after a reset. | |
3214 | **/ | |
3215 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
3216 | { | |
2f1860b8 AD |
3217 | struct ixgbe_hw *hw = &adapter->hw; |
3218 | u32 dmatxctl; | |
43e69bf0 | 3219 | u32 i; |
9a799d71 | 3220 | |
2f1860b8 AD |
3221 | ixgbe_setup_mtqc(adapter); |
3222 | ||
3223 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3224 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
3225 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
3226 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
3227 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
3228 | } | |
3229 | ||
9a799d71 | 3230 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
3231 | for (i = 0; i < adapter->num_tx_queues; i++) |
3232 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
3233 | } |
3234 | ||
3ebe8fde AD |
3235 | static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, |
3236 | struct ixgbe_ring *ring) | |
3237 | { | |
3238 | struct ixgbe_hw *hw = &adapter->hw; | |
3239 | u8 reg_idx = ring->reg_idx; | |
3240 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
3241 | ||
3242 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
3243 | ||
3244 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
3245 | } | |
3246 | ||
3247 | static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, | |
3248 | struct ixgbe_ring *ring) | |
3249 | { | |
3250 | struct ixgbe_hw *hw = &adapter->hw; | |
3251 | u8 reg_idx = ring->reg_idx; | |
3252 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
3253 | ||
3254 | srrctl &= ~IXGBE_SRRCTL_DROP_EN; | |
3255 | ||
3256 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
3257 | } | |
3258 | ||
3259 | #ifdef CONFIG_IXGBE_DCB | |
3260 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
3261 | #else | |
3262 | static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
3263 | #endif | |
3264 | { | |
3265 | int i; | |
3266 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
3267 | ||
3268 | if (adapter->ixgbe_ieee_pfc) | |
3269 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
3270 | ||
3271 | /* | |
3272 | * We should set the drop enable bit if: | |
3273 | * SR-IOV is enabled | |
3274 | * or | |
3275 | * Number of Rx queues > 1 and flow control is disabled | |
3276 | * | |
3277 | * This allows us to avoid head of line blocking for security | |
3278 | * and performance reasons. | |
3279 | */ | |
3280 | if (adapter->num_vfs || (adapter->num_rx_queues > 1 && | |
3281 | !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { | |
3282 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3283 | ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); | |
3284 | } else { | |
3285 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3286 | ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); | |
3287 | } | |
3288 | } | |
3289 | ||
e8e26350 | 3290 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 3291 | |
a6616b42 | 3292 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 3293 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 3294 | { |
45e9baa5 | 3295 | struct ixgbe_hw *hw = &adapter->hw; |
cc41ac7c | 3296 | u32 srrctl; |
bf29ee6c | 3297 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 3298 | |
45e9baa5 AD |
3299 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3300 | u16 mask = adapter->ring_feature[RING_F_RSS].mask; | |
cc41ac7c | 3301 | |
45e9baa5 AD |
3302 | /* |
3303 | * if VMDq is not active we must program one srrctl register | |
3304 | * per RSS queue since we have enabled RDRXCTL.MVMEN | |
3305 | */ | |
3306 | reg_idx &= mask; | |
3307 | } | |
cc41ac7c | 3308 | |
45e9baa5 AD |
3309 | /* configure header buffer length, needed for RSC */ |
3310 | srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; | |
afafd5b0 | 3311 | |
45e9baa5 | 3312 | /* configure the packet buffer length */ |
f800326d | 3313 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
45e9baa5 AD |
3314 | |
3315 | /* configure descriptor type */ | |
f800326d | 3316 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 3317 | |
45e9baa5 | 3318 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 3319 | } |
9a799d71 | 3320 | |
dfaf891d | 3321 | /** |
a897a2ad | 3322 | * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries |
dfaf891d VZ |
3323 | * @adapter: device handle |
3324 | * | |
3325 | * - 82598/82599/X540: 128 | |
3326 | * - X550(non-SRIOV mode): 512 | |
3327 | * - X550(SRIOV mode): 64 | |
3328 | */ | |
7f276efb | 3329 | u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) |
dfaf891d VZ |
3330 | { |
3331 | if (adapter->hw.mac.type < ixgbe_mac_X550) | |
3332 | return 128; | |
3333 | else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3334 | return 64; | |
3335 | else | |
3336 | return 512; | |
3337 | } | |
3338 | ||
3339 | /** | |
a897a2ad | 3340 | * ixgbe_store_reta - Write the RETA table to HW |
dfaf891d VZ |
3341 | * @adapter: device handle |
3342 | * | |
3343 | * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. | |
3344 | */ | |
1c7cf078 | 3345 | void ixgbe_store_reta(struct ixgbe_adapter *adapter) |
0cefafad | 3346 | { |
dfaf891d | 3347 | u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); |
05abb126 | 3348 | struct ixgbe_hw *hw = &adapter->hw; |
d1b849b9 | 3349 | u32 reta = 0; |
dfaf891d VZ |
3350 | u32 indices_multi; |
3351 | u8 *indir_tbl = adapter->rss_indir_tbl; | |
05abb126 | 3352 | |
0f9b232b | 3353 | /* Fill out the redirection table as follows: |
dfaf891d VZ |
3354 | * - 82598: 8 bit wide entries containing pair of 4 bit RSS |
3355 | * indices. | |
3356 | * - 82599/X540: 8 bit wide entries containing 4 bit RSS index | |
3357 | * - X550: 8 bit wide entries containing 6 bit RSS index | |
0f9b232b DS |
3358 | */ |
3359 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3360 | indices_multi = 0x11; | |
3361 | else | |
3362 | indices_multi = 0x1; | |
3363 | ||
dfaf891d VZ |
3364 | /* Write redirection table to HW */ |
3365 | for (i = 0; i < reta_entries; i++) { | |
3366 | reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; | |
0f9b232b DS |
3367 | if ((i & 3) == 3) { |
3368 | if (i < 128) | |
3369 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
3370 | else | |
3371 | IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), | |
3372 | reta); | |
dfaf891d | 3373 | reta = 0; |
0f9b232b DS |
3374 | } |
3375 | } | |
3376 | } | |
3377 | ||
dfaf891d | 3378 | /** |
a897a2ad | 3379 | * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) |
dfaf891d VZ |
3380 | * @adapter: device handle |
3381 | * | |
3382 | * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. | |
3383 | */ | |
3384 | static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) | |
0f9b232b | 3385 | { |
dfaf891d | 3386 | u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); |
0f9b232b DS |
3387 | struct ixgbe_hw *hw = &adapter->hw; |
3388 | u32 vfreta = 0; | |
dfaf891d VZ |
3389 | unsigned int pf_pool = adapter->num_vfs; |
3390 | ||
3391 | /* Write redirection table to HW */ | |
3392 | for (i = 0; i < reta_entries; i++) { | |
3393 | vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; | |
3394 | if ((i & 3) == 3) { | |
3395 | IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), | |
3396 | vfreta); | |
3397 | vfreta = 0; | |
3398 | } | |
3399 | } | |
3400 | } | |
3401 | ||
3402 | static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) | |
3403 | { | |
3404 | struct ixgbe_hw *hw = &adapter->hw; | |
3405 | u32 i, j; | |
3406 | u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); | |
3407 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; | |
3408 | ||
3409 | /* Program table for at least 2 queues w/ SR-IOV so that VFs can | |
3410 | * make full use of any rings they may have. We will use the | |
3411 | * PSRTYPE register to control how many rings we use within the PF. | |
3412 | */ | |
3413 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) | |
3414 | rss_i = 2; | |
3415 | ||
3416 | /* Fill out hash function seeds */ | |
3417 | for (i = 0; i < 10; i++) | |
3418 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); | |
3419 | ||
3420 | /* Fill out redirection table */ | |
3421 | memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); | |
3422 | ||
3423 | for (i = 0, j = 0; i < reta_entries; i++, j++) { | |
3424 | if (j == rss_i) | |
3425 | j = 0; | |
3426 | ||
3427 | adapter->rss_indir_tbl[i] = j; | |
3428 | } | |
3429 | ||
3430 | ixgbe_store_reta(adapter); | |
3431 | } | |
3432 | ||
3433 | static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) | |
3434 | { | |
3435 | struct ixgbe_hw *hw = &adapter->hw; | |
0f9b232b DS |
3436 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; |
3437 | unsigned int pf_pool = adapter->num_vfs; | |
3438 | int i, j; | |
3439 | ||
3440 | /* Fill out hash function seeds */ | |
3441 | for (i = 0; i < 10; i++) | |
dfaf891d VZ |
3442 | IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), |
3443 | adapter->rss_key[i]); | |
0f9b232b DS |
3444 | |
3445 | /* Fill out the redirection table */ | |
3446 | for (i = 0, j = 0; i < 64; i++, j++) { | |
671c0adb | 3447 | if (j == rss_i) |
05abb126 | 3448 | j = 0; |
dfaf891d VZ |
3449 | |
3450 | adapter->rss_indir_tbl[i] = j; | |
05abb126 | 3451 | } |
dfaf891d VZ |
3452 | |
3453 | ixgbe_store_vfreta(adapter); | |
d1b849b9 DS |
3454 | } |
3455 | ||
3456 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) | |
3457 | { | |
3458 | struct ixgbe_hw *hw = &adapter->hw; | |
0f9b232b | 3459 | u32 mrqc = 0, rss_field = 0, vfmrqc = 0; |
d1b849b9 | 3460 | u32 rxcsum; |
0cefafad | 3461 | |
05abb126 AD |
3462 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
3463 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
3464 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
3465 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
3466 | ||
671c0adb | 3467 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
fbe7ca7f | 3468 | if (adapter->ring_feature[RING_F_RSS].mask) |
671c0adb | 3469 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 | 3470 | } else { |
671c0adb AD |
3471 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
3472 | ||
3473 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3474 | if (tcs > 4) | |
3475 | mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ | |
3476 | else if (tcs > 1) | |
3477 | mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ | |
3478 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
3479 | mrqc = IXGBE_MRQC_VMDQRSS32EN; | |
8b1c0b24 | 3480 | else |
671c0adb AD |
3481 | mrqc = IXGBE_MRQC_VMDQRSS64EN; |
3482 | } else { | |
3483 | if (tcs > 4) | |
8b1c0b24 | 3484 | mrqc = IXGBE_MRQC_RTRSS8TCEN; |
671c0adb AD |
3485 | else if (tcs > 1) |
3486 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
3487 | else | |
3488 | mrqc = IXGBE_MRQC_RSSEN; | |
8b1c0b24 | 3489 | } |
0cefafad JB |
3490 | } |
3491 | ||
05abb126 | 3492 | /* Perform hash on these packet types */ |
d1b849b9 DS |
3493 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
3494 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | | |
3495 | IXGBE_MRQC_RSS_FIELD_IPV6 | | |
3496 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
05abb126 | 3497 | |
ef6afc0c | 3498 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
d1b849b9 | 3499 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; |
ef6afc0c | 3500 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) |
d1b849b9 | 3501 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; |
ef6afc0c | 3502 | |
dfaf891d | 3503 | netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key)); |
0f9b232b DS |
3504 | if ((hw->mac.type >= ixgbe_mac_X550) && |
3505 | (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { | |
3506 | unsigned int pf_pool = adapter->num_vfs; | |
3507 | ||
3508 | /* Enable VF RSS mode */ | |
3509 | mrqc |= IXGBE_MRQC_MULTIPLE_RSS; | |
3510 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
3511 | ||
3512 | /* Setup RSS through the VF registers */ | |
dfaf891d | 3513 | ixgbe_setup_vfreta(adapter); |
0f9b232b DS |
3514 | vfmrqc = IXGBE_MRQC_RSSEN; |
3515 | vfmrqc |= rss_field; | |
3516 | IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); | |
3517 | } else { | |
dfaf891d | 3518 | ixgbe_setup_reta(adapter); |
0f9b232b DS |
3519 | mrqc |= rss_field; |
3520 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
3521 | } | |
0cefafad JB |
3522 | } |
3523 | ||
bb5a9ad2 NS |
3524 | /** |
3525 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
3526 | * @adapter: address of board private structure | |
3527 | * @index: index of ring to set | |
bb5a9ad2 | 3528 | **/ |
082757af | 3529 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 3530 | struct ixgbe_ring *ring) |
bb5a9ad2 | 3531 | { |
bb5a9ad2 | 3532 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 3533 | u32 rscctrl; |
bf29ee6c | 3534 | u8 reg_idx = ring->reg_idx; |
7367096a | 3535 | |
7d637bcc | 3536 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 3537 | return; |
bb5a9ad2 | 3538 | |
7367096a | 3539 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
3540 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
3541 | /* | |
3542 | * we must limit the number of descriptors so that the | |
3543 | * total size of max desc * buf_len is not greater | |
642c680e | 3544 | * than 65536 |
bb5a9ad2 | 3545 | */ |
f800326d | 3546 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; |
7367096a | 3547 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
3548 | } |
3549 | ||
9e10e045 AD |
3550 | #define IXGBE_MAX_RX_DESC_POLL 10 |
3551 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
3552 | struct ixgbe_ring *ring) | |
3553 | { | |
3554 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
3555 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
3556 | u32 rxdctl; | |
bf29ee6c | 3557 | u8 reg_idx = ring->reg_idx; |
9e10e045 | 3558 | |
b0483c8f MR |
3559 | if (ixgbe_removed(hw->hw_addr)) |
3560 | return; | |
9e10e045 AD |
3561 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ |
3562 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3563 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3564 | return; | |
3565 | ||
3566 | do { | |
032b4325 | 3567 | usleep_range(1000, 2000); |
9e10e045 AD |
3568 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3569 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3570 | ||
3571 | if (!wait_loop) { | |
3572 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3573 | "the polling period\n", reg_idx); | |
3574 | } | |
3575 | } | |
3576 | ||
2d39d576 YZ |
3577 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3578 | struct ixgbe_ring *ring) | |
3579 | { | |
3580 | struct ixgbe_hw *hw = &adapter->hw; | |
3581 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3582 | u32 rxdctl; | |
3583 | u8 reg_idx = ring->reg_idx; | |
3584 | ||
b0483c8f MR |
3585 | if (ixgbe_removed(hw->hw_addr)) |
3586 | return; | |
2d39d576 YZ |
3587 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3588 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3589 | ||
3590 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3591 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3592 | ||
3593 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3594 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3595 | return; | |
3596 | ||
3597 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3598 | do { | |
3599 | udelay(10); | |
3600 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3601 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3602 | ||
3603 | if (!wait_loop) { | |
3604 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3605 | "the polling period\n", reg_idx); | |
3606 | } | |
3607 | } | |
3608 | ||
84418e3b AD |
3609 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3610 | struct ixgbe_ring *ring) | |
acd37177 AD |
3611 | { |
3612 | struct ixgbe_hw *hw = &adapter->hw; | |
3613 | u64 rdba = ring->dma; | |
9e10e045 | 3614 | u32 rxdctl; |
bf29ee6c | 3615 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3616 | |
9e10e045 AD |
3617 | /* disable queue to avoid issues while updating state */ |
3618 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3619 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3620 | |
acd37177 AD |
3621 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3622 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3623 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3624 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
8b75451b NP |
3625 | /* Force flushing of IXGBE_RDLEN to prevent MDD */ |
3626 | IXGBE_WRITE_FLUSH(hw); | |
3627 | ||
acd37177 AD |
3628 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); |
3629 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
2a1a091c | 3630 | ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3631 | |
3632 | ixgbe_configure_srrctl(adapter, ring); | |
3633 | ixgbe_configure_rscctl(adapter, ring); | |
3634 | ||
3635 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
3636 | /* | |
3637 | * enable cache line friendly hardware writes: | |
3638 | * PTHRESH=32 descriptors (half the internal cache), | |
3639 | * this also removes ugly rx_no_buffer_count increment | |
3640 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3641 | * WTHRESH=8 burst writeback up to two cache lines | |
3642 | */ | |
3643 | rxdctl &= ~0x3FFFFF; | |
3644 | rxdctl |= 0x080420; | |
3645 | } | |
3646 | ||
3647 | /* enable receive descriptor ring */ | |
3648 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3649 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3650 | ||
3651 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3652 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3653 | } |
3654 | ||
48654521 AD |
3655 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3656 | { | |
3657 | struct ixgbe_hw *hw = &adapter->hw; | |
fbe7ca7f | 3658 | int rss_i = adapter->ring_feature[RING_F_RSS].indices; |
2a47fa45 | 3659 | u16 pool; |
48654521 AD |
3660 | |
3661 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3662 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3663 | IXGBE_PSRTYPE_UDPHDR | |
3664 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3665 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3666 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3667 | |
3668 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3669 | return; | |
3670 | ||
fbe7ca7f AD |
3671 | if (rss_i > 3) |
3672 | psrtype |= 2 << 29; | |
3673 | else if (rss_i > 1) | |
3674 | psrtype |= 1 << 29; | |
48654521 | 3675 | |
2a47fa45 JF |
3676 | for_each_set_bit(pool, &adapter->fwd_bitmask, 32) |
3677 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); | |
48654521 AD |
3678 | } |
3679 | ||
f5b4a52e AD |
3680 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3681 | { | |
3682 | struct ixgbe_hw *hw = &adapter->hw; | |
f5b4a52e | 3683 | u32 reg_offset, vf_shift; |
435b19f6 | 3684 | u32 gcr_ext, vmdctl; |
de4c7f65 | 3685 | int i; |
f5b4a52e AD |
3686 | |
3687 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3688 | return; | |
3689 | ||
3690 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
435b19f6 AD |
3691 | vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; |
3692 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
1d9c0bfd | 3693 | vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; |
435b19f6 AD |
3694 | vmdctl |= IXGBE_VT_CTL_REPLEN; |
3695 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
f5b4a52e | 3696 | |
1d9c0bfd AD |
3697 | vf_shift = VMDQ_P(0) % 32; |
3698 | reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; | |
f5b4a52e AD |
3699 | |
3700 | /* Enable only the PF's pool for Tx/Rx */ | |
435b19f6 AD |
3701 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift); |
3702 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); | |
3703 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift); | |
3704 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); | |
aa2bacb6 | 3705 | if (adapter->bridge_mode == BRIDGE_MODE_VEB) |
9b735984 | 3706 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); |
f5b4a52e AD |
3707 | |
3708 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
1d9c0bfd | 3709 | hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); |
f5b4a52e | 3710 | |
16369564 AD |
3711 | /* clear VLAN promisc flag so VFTA will be updated if necessary */ |
3712 | adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; | |
3713 | ||
f5b4a52e AD |
3714 | /* |
3715 | * Set up VF register offsets for selected VT Mode, | |
3716 | * i.e. 32 or 64 VFs for SR-IOV | |
3717 | */ | |
73079ea0 AD |
3718 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { |
3719 | case IXGBE_82599_VMDQ_8Q_MASK: | |
3720 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; | |
3721 | break; | |
3722 | case IXGBE_82599_VMDQ_4Q_MASK: | |
3723 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; | |
3724 | break; | |
3725 | default: | |
3726 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; | |
3727 | break; | |
3728 | } | |
3729 | ||
f5b4a52e AD |
3730 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); |
3731 | ||
435b19f6 | 3732 | |
a985b6c3 | 3733 | /* Enable MAC Anti-Spoofing */ |
435b19f6 | 3734 | hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0), |
a985b6c3 | 3735 | adapter->num_vfs); |
5b7f000f | 3736 | |
f079fa00 | 3737 | /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be |
5b7f000f DS |
3738 | * calling set_ethertype_anti_spoofing for each VF in loop below |
3739 | */ | |
f079fa00 | 3740 | if (hw->mac.ops.set_ethertype_anti_spoofing) { |
5b7f000f | 3741 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP), |
f079fa00 ET |
3742 | (IXGBE_ETQF_FILTER_EN | |
3743 | IXGBE_ETQF_TX_ANTISPOOF | | |
3744 | IXGBE_ETH_P_LLDP)); | |
3745 | ||
3746 | IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC), | |
3747 | (IXGBE_ETQF_FILTER_EN | | |
3748 | IXGBE_ETQF_TX_ANTISPOOF | | |
3749 | ETH_P_PAUSE)); | |
3750 | } | |
5b7f000f | 3751 | |
de4c7f65 GR |
3752 | /* For VFs that have spoof checking turned off */ |
3753 | for (i = 0; i < adapter->num_vfs; i++) { | |
3754 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3755 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
5b7f000f DS |
3756 | |
3757 | /* enable ethertype anti spoofing if hw supports it */ | |
3758 | if (hw->mac.ops.set_ethertype_anti_spoofing) | |
3759 | hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i); | |
e65ce0d3 VZ |
3760 | |
3761 | /* Enable/Disable RSS query feature */ | |
3762 | ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, | |
3763 | adapter->vfinfo[i].rss_query_enabled); | |
de4c7f65 | 3764 | } |
f5b4a52e AD |
3765 | } |
3766 | ||
477de6ed | 3767 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3768 | { |
9a799d71 AK |
3769 | struct ixgbe_hw *hw = &adapter->hw; |
3770 | struct net_device *netdev = adapter->netdev; | |
3771 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3772 | struct ixgbe_ring *rx_ring; |
3773 | int i; | |
3774 | u32 mhadd, hlreg0; | |
48654521 | 3775 | |
63f39bd1 | 3776 | #ifdef IXGBE_FCOE |
477de6ed AD |
3777 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3778 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3779 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3780 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3781 | |
477de6ed | 3782 | #endif /* IXGBE_FCOE */ |
872844dd AD |
3783 | |
3784 | /* adjust max frame to be at least the size of a standard frame */ | |
3785 | if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) | |
3786 | max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); | |
3787 | ||
477de6ed AD |
3788 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
3789 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3790 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3791 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3792 | ||
3793 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3794 | } | |
3795 | ||
3796 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
3797 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3798 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3799 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3800 | |
0cefafad JB |
3801 | /* |
3802 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3803 | * the Base and Length of the Rx Descriptor Ring | |
3804 | */ | |
9a799d71 | 3805 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3806 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3807 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3808 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3809 | else |
7d637bcc | 3810 | clear_ring_rsc_enabled(rx_ring); |
477de6ed | 3811 | } |
477de6ed AD |
3812 | } |
3813 | ||
7367096a AD |
3814 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3815 | { | |
3816 | struct ixgbe_hw *hw = &adapter->hw; | |
3817 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3818 | ||
3819 | switch (hw->mac.type) { | |
3820 | case ixgbe_mac_82598EB: | |
3821 | /* | |
3822 | * For VMDq support of different descriptor types or | |
3823 | * buffer sizes through the use of multiple SRRCTL | |
3824 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3825 | * | |
3826 | * also, the manual doesn't mention it clearly but DCA hints | |
3827 | * will only use queue 0's tags unless this bit is set. Side | |
3828 | * effects of setting this bit are only that SRRCTL must be | |
3829 | * fully programmed [0..15] | |
3830 | */ | |
3831 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3832 | break; | |
052a1a72 MR |
3833 | case ixgbe_mac_X550: |
3834 | case ixgbe_mac_X550EM_x: | |
f961ddae MR |
3835 | if (adapter->num_vfs) |
3836 | rdrxctl |= IXGBE_RDRXCTL_PSP; | |
3837 | /* fall through for older HW */ | |
7367096a | 3838 | case ixgbe_mac_82599EB: |
b93a2226 | 3839 | case ixgbe_mac_X540: |
7367096a AD |
3840 | /* Disable RSC for ACK packets */ |
3841 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3842 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3843 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3844 | /* hardware requires some bits to be set by default */ | |
3845 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3846 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3847 | break; | |
3848 | default: | |
3849 | /* We should do nothing since we don't know this hardware */ | |
3850 | return; | |
3851 | } | |
3852 | ||
3853 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3854 | } | |
3855 | ||
477de6ed AD |
3856 | /** |
3857 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3858 | * @adapter: board private structure | |
3859 | * | |
3860 | * Configure the Rx unit of the MAC after a reset. | |
3861 | **/ | |
3862 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3863 | { | |
3864 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed | 3865 | int i; |
6dcc28b9 | 3866 | u32 rxctrl, rfctl; |
477de6ed AD |
3867 | |
3868 | /* disable receives while setting up the descriptors */ | |
1f9ac57c | 3869 | hw->mac.ops.disable_rx(hw); |
477de6ed AD |
3870 | |
3871 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3872 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3873 | |
6dcc28b9 JK |
3874 | /* RSC Setup */ |
3875 | rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); | |
3876 | rfctl &= ~IXGBE_RFCTL_RSC_DIS; | |
3877 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
3878 | rfctl |= IXGBE_RFCTL_RSC_DIS; | |
3879 | IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); | |
3880 | ||
9e10e045 | 3881 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3882 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3883 | |
477de6ed AD |
3884 | /* set_rx_buffer_len must be called before ring initialization */ |
3885 | ixgbe_set_rx_buffer_len(adapter); | |
3886 | ||
3887 | /* | |
3888 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3889 | * the Base and Length of the Rx Descriptor Ring | |
3890 | */ | |
9e10e045 AD |
3891 | for (i = 0; i < adapter->num_rx_queues; i++) |
3892 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3893 | |
1f9ac57c | 3894 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
9e10e045 AD |
3895 | /* disable drop enable for 82598 parts */ |
3896 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3897 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3898 | ||
3899 | /* enable all receives */ | |
3900 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3901 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3902 | } |
3903 | ||
80d5c368 PM |
3904 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, |
3905 | __be16 proto, u16 vid) | |
068c89b0 DS |
3906 | { |
3907 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3908 | struct ixgbe_hw *hw = &adapter->hw; | |
3909 | ||
3910 | /* add VID to filter table */ | |
b6488b66 | 3911 | hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, true); |
f62bbb5e | 3912 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3913 | |
3914 | return 0; | |
068c89b0 DS |
3915 | } |
3916 | ||
e1d0a2af AD |
3917 | static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) |
3918 | { | |
3919 | u32 vlvf; | |
3920 | int idx; | |
3921 | ||
3922 | /* short cut the special case */ | |
3923 | if (vlan == 0) | |
3924 | return 0; | |
3925 | ||
3926 | /* Search for the vlan id in the VLVF entries */ | |
3927 | for (idx = IXGBE_VLVF_ENTRIES; --idx;) { | |
3928 | vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); | |
3929 | if ((vlvf & VLAN_VID_MASK) == vlan) | |
3930 | break; | |
3931 | } | |
3932 | ||
3933 | return idx; | |
3934 | } | |
3935 | ||
3936 | void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) | |
3937 | { | |
3938 | struct ixgbe_hw *hw = &adapter->hw; | |
3939 | u32 bits, word; | |
3940 | int idx; | |
3941 | ||
3942 | idx = ixgbe_find_vlvf_entry(hw, vid); | |
3943 | if (!idx) | |
3944 | return; | |
3945 | ||
3946 | /* See if any other pools are set for this VLAN filter | |
3947 | * entry other than the PF. | |
3948 | */ | |
3949 | word = idx * 2 + (VMDQ_P(0) / 32); | |
3950 | bits = ~(1 << (VMDQ_P(0)) % 32); | |
3951 | bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); | |
3952 | ||
3953 | /* Disable the filter so this falls into the default pool. */ | |
3954 | if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { | |
3955 | if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) | |
3956 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); | |
3957 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); | |
3958 | } | |
3959 | } | |
3960 | ||
80d5c368 PM |
3961 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, |
3962 | __be16 proto, u16 vid) | |
068c89b0 DS |
3963 | { |
3964 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3965 | struct ixgbe_hw *hw = &adapter->hw; | |
3966 | ||
068c89b0 | 3967 | /* remove VID from filter table */ |
e1d0a2af AD |
3968 | if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) |
3969 | ixgbe_update_pf_promisc_vlvf(adapter, vid); | |
3970 | else | |
3971 | hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); | |
3972 | ||
f62bbb5e | 3973 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3974 | |
3975 | return 0; | |
068c89b0 DS |
3976 | } |
3977 | ||
f62bbb5e JG |
3978 | /** |
3979 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3980 | * @adapter: driver data | |
3981 | */ | |
3982 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3983 | { | |
3984 | struct ixgbe_hw *hw = &adapter->hw; | |
3985 | u32 vlnctrl; | |
5f6c0181 JB |
3986 | int i, j; |
3987 | ||
3988 | switch (hw->mac.type) { | |
3989 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3990 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3991 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3992 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3993 | break; | |
3994 | case ixgbe_mac_82599EB: | |
b93a2226 | 3995 | case ixgbe_mac_X540: |
9a75a1ac DS |
3996 | case ixgbe_mac_X550: |
3997 | case ixgbe_mac_X550EM_x: | |
5f6c0181 | 3998 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2a47fa45 JF |
3999 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4000 | ||
4001 | if (ring->l2_accel_priv) | |
4002 | continue; | |
4003 | j = ring->reg_idx; | |
5f6c0181 JB |
4004 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
4005 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
4006 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
4007 | } | |
4008 | break; | |
4009 | default: | |
4010 | break; | |
4011 | } | |
4012 | } | |
4013 | ||
4014 | /** | |
f62bbb5e | 4015 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
4016 | * @adapter: driver data |
4017 | */ | |
f62bbb5e | 4018 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
4019 | { |
4020 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 4021 | u32 vlnctrl; |
5f6c0181 JB |
4022 | int i, j; |
4023 | ||
4024 | switch (hw->mac.type) { | |
4025 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
4026 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
4027 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
4028 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
4029 | break; | |
4030 | case ixgbe_mac_82599EB: | |
b93a2226 | 4031 | case ixgbe_mac_X540: |
9a75a1ac DS |
4032 | case ixgbe_mac_X550: |
4033 | case ixgbe_mac_X550EM_x: | |
5f6c0181 | 4034 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2a47fa45 JF |
4035 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4036 | ||
4037 | if (ring->l2_accel_priv) | |
4038 | continue; | |
4039 | j = ring->reg_idx; | |
5f6c0181 JB |
4040 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
4041 | vlnctrl |= IXGBE_RXDCTL_VME; | |
4042 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
4043 | } | |
4044 | break; | |
4045 | default: | |
4046 | break; | |
4047 | } | |
4048 | } | |
4049 | ||
16369564 AD |
4050 | static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) |
4051 | { | |
4052 | struct ixgbe_hw *hw = &adapter->hw; | |
4053 | u32 vlnctrl, i; | |
4054 | ||
4055 | switch (hw->mac.type) { | |
4056 | case ixgbe_mac_82599EB: | |
4057 | case ixgbe_mac_X540: | |
4058 | case ixgbe_mac_X550: | |
4059 | case ixgbe_mac_X550EM_x: | |
4060 | default: | |
4061 | if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) | |
4062 | break; | |
4063 | /* fall through */ | |
4064 | case ixgbe_mac_82598EB: | |
4065 | /* legacy case, we can just disable VLAN filtering */ | |
4066 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
4067 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
4068 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
4069 | return; | |
4070 | } | |
4071 | ||
4072 | /* We are already in VLAN promisc, nothing to do */ | |
4073 | if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) | |
4074 | return; | |
4075 | ||
4076 | /* Set flag so we don't redo unnecessary work */ | |
4077 | adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; | |
4078 | ||
4079 | /* Add PF to all active pools */ | |
4080 | for (i = IXGBE_VLVF_ENTRIES; --i;) { | |
4081 | u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); | |
4082 | u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); | |
4083 | ||
4084 | vlvfb |= 1 << (VMDQ_P(0) % 32); | |
4085 | IXGBE_WRITE_REG(hw, reg_offset, vlvfb); | |
4086 | } | |
4087 | ||
4088 | /* Set all bits in the VLAN filter table array */ | |
4089 | for (i = hw->mac.vft_size; i--;) | |
4090 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); | |
4091 | } | |
4092 | ||
4093 | #define VFTA_BLOCK_SIZE 8 | |
4094 | static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) | |
4095 | { | |
4096 | struct ixgbe_hw *hw = &adapter->hw; | |
4097 | u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; | |
4098 | u32 vid_start = vfta_offset * 32; | |
4099 | u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); | |
4100 | u32 i, vid, word, bits; | |
4101 | ||
4102 | for (i = IXGBE_VLVF_ENTRIES; --i;) { | |
4103 | u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); | |
4104 | ||
4105 | /* pull VLAN ID from VLVF */ | |
4106 | vid = vlvf & VLAN_VID_MASK; | |
4107 | ||
4108 | /* only concern outselves with a certain range */ | |
4109 | if (vid < vid_start || vid >= vid_end) | |
4110 | continue; | |
4111 | ||
4112 | if (vlvf) { | |
4113 | /* record VLAN ID in VFTA */ | |
4114 | vfta[(vid - vid_start) / 32] |= 1 << (vid % 32); | |
4115 | ||
4116 | /* if PF is part of this then continue */ | |
4117 | if (test_bit(vid, adapter->active_vlans)) | |
4118 | continue; | |
4119 | } | |
4120 | ||
4121 | /* remove PF from the pool */ | |
4122 | word = i * 2 + VMDQ_P(0) / 32; | |
4123 | bits = ~(1 << (VMDQ_P(0) % 32)); | |
4124 | bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); | |
4125 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); | |
4126 | } | |
4127 | ||
4128 | /* extract values from active_vlans and write back to VFTA */ | |
4129 | for (i = VFTA_BLOCK_SIZE; i--;) { | |
4130 | vid = (vfta_offset + i) * 32; | |
4131 | word = vid / BITS_PER_LONG; | |
4132 | bits = vid % BITS_PER_LONG; | |
4133 | ||
4134 | vfta[i] |= adapter->active_vlans[word] >> bits; | |
4135 | ||
4136 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); | |
4137 | } | |
4138 | } | |
4139 | ||
4140 | static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) | |
4141 | { | |
4142 | struct ixgbe_hw *hw = &adapter->hw; | |
4143 | u32 vlnctrl, i; | |
4144 | ||
4145 | switch (hw->mac.type) { | |
4146 | case ixgbe_mac_82599EB: | |
4147 | case ixgbe_mac_X540: | |
4148 | case ixgbe_mac_X550: | |
4149 | case ixgbe_mac_X550EM_x: | |
4150 | default: | |
4151 | if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) | |
4152 | break; | |
4153 | /* fall through */ | |
4154 | case ixgbe_mac_82598EB: | |
4155 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
4156 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
4157 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
4158 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
4159 | return; | |
4160 | } | |
4161 | ||
4162 | /* We are not in VLAN promisc, nothing to do */ | |
4163 | if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) | |
4164 | return; | |
4165 | ||
4166 | /* Set flag so we don't redo unnecessary work */ | |
4167 | adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; | |
4168 | ||
4169 | for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) | |
4170 | ixgbe_scrub_vfta(adapter, i); | |
4171 | } | |
4172 | ||
9a799d71 AK |
4173 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
4174 | { | |
f62bbb5e | 4175 | u16 vid; |
9a799d71 | 4176 | |
80d5c368 | 4177 | ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); |
f62bbb5e JG |
4178 | |
4179 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
80d5c368 | 4180 | ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); |
9a799d71 AK |
4181 | } |
4182 | ||
b335e75b JK |
4183 | /** |
4184 | * ixgbe_write_mc_addr_list - write multicast addresses to MTA | |
4185 | * @netdev: network interface device structure | |
4186 | * | |
4187 | * Writes multicast address list to the MTA hash table. | |
4188 | * Returns: -ENOMEM on failure | |
4189 | * 0 on no addresses written | |
4190 | * X on writing X addresses to MTA | |
4191 | **/ | |
4192 | static int ixgbe_write_mc_addr_list(struct net_device *netdev) | |
4193 | { | |
4194 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4195 | struct ixgbe_hw *hw = &adapter->hw; | |
4196 | ||
4197 | if (!netif_running(netdev)) | |
4198 | return 0; | |
4199 | ||
4200 | if (hw->mac.ops.update_mc_addr_list) | |
4201 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
4202 | else | |
4203 | return -ENOMEM; | |
4204 | ||
4205 | #ifdef CONFIG_PCI_IOV | |
5d7daa35 | 4206 | ixgbe_restore_vf_multicasts(adapter); |
b335e75b JK |
4207 | #endif |
4208 | ||
4209 | return netdev_mc_count(netdev); | |
4210 | } | |
4211 | ||
5d7daa35 JK |
4212 | #ifdef CONFIG_PCI_IOV |
4213 | void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) | |
4214 | { | |
c9f53e63 | 4215 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4216 | struct ixgbe_hw *hw = &adapter->hw; |
4217 | int i; | |
c9f53e63 AD |
4218 | |
4219 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { | |
4220 | mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; | |
4221 | ||
4222 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
4223 | hw->mac.ops.set_rar(hw, i, | |
4224 | mac_table->addr, | |
4225 | mac_table->pool, | |
5d7daa35 JK |
4226 | IXGBE_RAH_AV); |
4227 | else | |
4228 | hw->mac.ops.clear_rar(hw, i); | |
5d7daa35 JK |
4229 | } |
4230 | } | |
5d7daa35 | 4231 | |
c9f53e63 | 4232 | #endif |
5d7daa35 JK |
4233 | static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) |
4234 | { | |
c9f53e63 | 4235 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4236 | struct ixgbe_hw *hw = &adapter->hw; |
4237 | int i; | |
5d7daa35 | 4238 | |
c9f53e63 AD |
4239 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4240 | if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) | |
4241 | continue; | |
4242 | ||
4243 | mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; | |
4244 | ||
4245 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
4246 | hw->mac.ops.set_rar(hw, i, | |
4247 | mac_table->addr, | |
4248 | mac_table->pool, | |
4249 | IXGBE_RAH_AV); | |
4250 | else | |
4251 | hw->mac.ops.clear_rar(hw, i); | |
5d7daa35 JK |
4252 | } |
4253 | } | |
4254 | ||
4255 | static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) | |
4256 | { | |
c9f53e63 | 4257 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 | 4258 | struct ixgbe_hw *hw = &adapter->hw; |
c9f53e63 | 4259 | int i; |
5d7daa35 | 4260 | |
c9f53e63 AD |
4261 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4262 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED; | |
4263 | mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; | |
5d7daa35 | 4264 | } |
c9f53e63 | 4265 | |
5d7daa35 JK |
4266 | ixgbe_sync_mac_table(adapter); |
4267 | } | |
4268 | ||
c9f53e63 | 4269 | static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) |
5d7daa35 | 4270 | { |
c9f53e63 | 4271 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4272 | struct ixgbe_hw *hw = &adapter->hw; |
4273 | int i, count = 0; | |
4274 | ||
c9f53e63 AD |
4275 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4276 | /* do not count default RAR as available */ | |
4277 | if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) | |
4278 | continue; | |
4279 | ||
4280 | /* only count unused and addresses that belong to us */ | |
4281 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { | |
4282 | if (mac_table->pool != pool) | |
4283 | continue; | |
4284 | } | |
4285 | ||
4286 | count++; | |
5d7daa35 | 4287 | } |
c9f53e63 | 4288 | |
5d7daa35 JK |
4289 | return count; |
4290 | } | |
4291 | ||
4292 | /* this function destroys the first RAR entry */ | |
c9f53e63 | 4293 | static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) |
5d7daa35 | 4294 | { |
c9f53e63 | 4295 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4296 | struct ixgbe_hw *hw = &adapter->hw; |
4297 | ||
c9f53e63 AD |
4298 | memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); |
4299 | mac_table->pool = VMDQ_P(0); | |
4300 | ||
4301 | mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; | |
4302 | ||
4303 | hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, | |
5d7daa35 JK |
4304 | IXGBE_RAH_AV); |
4305 | } | |
4306 | ||
c9f53e63 AD |
4307 | int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, |
4308 | const u8 *addr, u16 pool) | |
5d7daa35 | 4309 | { |
c9f53e63 | 4310 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4311 | struct ixgbe_hw *hw = &adapter->hw; |
4312 | int i; | |
4313 | ||
4314 | if (is_zero_ether_addr(addr)) | |
4315 | return -EINVAL; | |
4316 | ||
c9f53e63 AD |
4317 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4318 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
5d7daa35 | 4319 | continue; |
c9f53e63 AD |
4320 | |
4321 | ether_addr_copy(mac_table->addr, addr); | |
4322 | mac_table->pool = pool; | |
4323 | ||
4324 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED | | |
4325 | IXGBE_MAC_STATE_IN_USE; | |
4326 | ||
5d7daa35 | 4327 | ixgbe_sync_mac_table(adapter); |
c9f53e63 | 4328 | |
5d7daa35 JK |
4329 | return i; |
4330 | } | |
c9f53e63 | 4331 | |
5d7daa35 JK |
4332 | return -ENOMEM; |
4333 | } | |
4334 | ||
c9f53e63 AD |
4335 | int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, |
4336 | const u8 *addr, u16 pool) | |
5d7daa35 | 4337 | { |
c9f53e63 | 4338 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 | 4339 | struct ixgbe_hw *hw = &adapter->hw; |
c9f53e63 | 4340 | int i; |
5d7daa35 JK |
4341 | |
4342 | if (is_zero_ether_addr(addr)) | |
4343 | return -EINVAL; | |
4344 | ||
c9f53e63 AD |
4345 | /* search table for addr, if found clear IN_USE flag and sync */ |
4346 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { | |
4347 | /* we can only delete an entry if it is in use */ | |
4348 | if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) | |
4349 | continue; | |
4350 | /* we only care about entries that belong to the given pool */ | |
4351 | if (mac_table->pool != pool) | |
4352 | continue; | |
4353 | /* we only care about a specific MAC address */ | |
4354 | if (!ether_addr_equal(addr, mac_table->addr)) | |
4355 | continue; | |
4356 | ||
4357 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED; | |
4358 | mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; | |
4359 | ||
4360 | ixgbe_sync_mac_table(adapter); | |
4361 | ||
4362 | return 0; | |
5d7daa35 | 4363 | } |
c9f53e63 | 4364 | |
5d7daa35 JK |
4365 | return -ENOMEM; |
4366 | } | |
2850062a AD |
4367 | /** |
4368 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
4369 | * @netdev: network interface device structure | |
4370 | * | |
4371 | * Writes unicast address list to the RAR table. | |
4372 | * Returns: -ENOMEM on failure/insufficient address space | |
4373 | * 0 on no addresses written | |
4374 | * X on writing X addresses to the RAR table | |
4375 | **/ | |
5d7daa35 | 4376 | static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) |
2850062a AD |
4377 | { |
4378 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2850062a AD |
4379 | int count = 0; |
4380 | ||
4381 | /* return ENOMEM indicating insufficient memory for addresses */ | |
c9f53e63 | 4382 | if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) |
2850062a AD |
4383 | return -ENOMEM; |
4384 | ||
95447461 | 4385 | if (!netdev_uc_empty(netdev)) { |
2850062a | 4386 | struct netdev_hw_addr *ha; |
2850062a | 4387 | netdev_for_each_uc_addr(ha, netdev) { |
5d7daa35 JK |
4388 | ixgbe_del_mac_filter(adapter, ha->addr, vfn); |
4389 | ixgbe_add_mac_filter(adapter, ha->addr, vfn); | |
2850062a AD |
4390 | count++; |
4391 | } | |
4392 | } | |
2850062a AD |
4393 | return count; |
4394 | } | |
4395 | ||
0f079d22 AD |
4396 | static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) |
4397 | { | |
4398 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4399 | int ret; | |
4400 | ||
4401 | ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); | |
4402 | ||
4403 | return min_t(int, ret, 0); | |
4404 | } | |
4405 | ||
4406 | static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) | |
4407 | { | |
4408 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4409 | ||
4410 | ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); | |
4411 | ||
4412 | return 0; | |
4413 | } | |
4414 | ||
9a799d71 | 4415 | /** |
2c5645cf | 4416 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
4417 | * @netdev: network interface device structure |
4418 | * | |
2c5645cf CL |
4419 | * The set_rx_method entry point is called whenever the unicast/multicast |
4420 | * address list or the network interface flags are updated. This routine is | |
4421 | * responsible for configuring the hardware for proper unicast, multicast and | |
4422 | * promiscuous mode. | |
9a799d71 | 4423 | **/ |
7f870475 | 4424 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
4425 | { |
4426 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4427 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
4428 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
4429 | int count; | |
9a799d71 AK |
4430 | |
4431 | /* Check for Promiscuous and All Multicast modes */ | |
9a799d71 AK |
4432 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
4433 | ||
f5dc442b | 4434 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 4435 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
4436 | fctrl |= IXGBE_FCTRL_BAM; |
4437 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
4438 | fctrl |= IXGBE_FCTRL_PMCF; | |
4439 | ||
2850062a AD |
4440 | /* clear the bits we are changing the status of */ |
4441 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
9a799d71 | 4442 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 4443 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 4444 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
b335e75b | 4445 | vmolr |= IXGBE_VMOLR_MPE; |
16369564 | 4446 | ixgbe_vlan_promisc_enable(adapter); |
9a799d71 | 4447 | } else { |
746b9f02 PM |
4448 | if (netdev->flags & IFF_ALLMULTI) { |
4449 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a | 4450 | vmolr |= IXGBE_VMOLR_MPE; |
746b9f02 | 4451 | } |
e433ea1f | 4452 | hw->addr_ctrl.user_set_promisc = false; |
16369564 | 4453 | ixgbe_vlan_promisc_disable(adapter); |
9dcb373c JF |
4454 | } |
4455 | ||
4456 | /* | |
4457 | * Write addresses to available RAR registers, if there is not | |
4458 | * sufficient space to store all the addresses then enable | |
4459 | * unicast promiscuous mode | |
4460 | */ | |
0f079d22 | 4461 | if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { |
9dcb373c JF |
4462 | fctrl |= IXGBE_FCTRL_UPE; |
4463 | vmolr |= IXGBE_VMOLR_ROPE; | |
9a799d71 AK |
4464 | } |
4465 | ||
cf78959c ET |
4466 | /* Write addresses to the MTA, if the attempt fails |
4467 | * then we should just turn on promiscuous mode so | |
4468 | * that we can at least receive multicast traffic | |
4469 | */ | |
b335e75b JK |
4470 | count = ixgbe_write_mc_addr_list(netdev); |
4471 | if (count < 0) { | |
4472 | fctrl |= IXGBE_FCTRL_MPE; | |
4473 | vmolr |= IXGBE_VMOLR_MPE; | |
4474 | } else if (count) { | |
4475 | vmolr |= IXGBE_VMOLR_ROMPE; | |
4476 | } | |
1d9c0bfd AD |
4477 | |
4478 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4479 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & | |
2850062a AD |
4480 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | |
4481 | IXGBE_VMOLR_ROPE); | |
1d9c0bfd | 4482 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); |
2850062a AD |
4483 | } |
4484 | ||
3f2d1c0f BG |
4485 | /* This is useful for sniffing bad packets. */ |
4486 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
4487 | /* UPE and MPE will be handled by normal PROMISC logic | |
4488 | * in e1000e_set_rx_mode */ | |
4489 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
4490 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
4491 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
4492 | ||
4493 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
4494 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
4495 | } | |
4496 | ||
2850062a | 4497 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e | 4498 | |
f646968f | 4499 | if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) |
f62bbb5e JG |
4500 | ixgbe_vlan_strip_enable(adapter); |
4501 | else | |
4502 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
4503 | } |
4504 | ||
021230d4 AV |
4505 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
4506 | { | |
4507 | int q_idx; | |
021230d4 | 4508 | |
5a85e737 ET |
4509 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { |
4510 | ixgbe_qv_init_lock(adapter->q_vector[q_idx]); | |
49c7ffbe | 4511 | napi_enable(&adapter->q_vector[q_idx]->napi); |
5a85e737 | 4512 | } |
021230d4 AV |
4513 | } |
4514 | ||
4515 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
4516 | { | |
4517 | int q_idx; | |
021230d4 | 4518 | |
5a85e737 | 4519 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { |
49c7ffbe | 4520 | napi_disable(&adapter->q_vector[q_idx]->napi); |
27d9ce4f | 4521 | while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { |
5a85e737 | 4522 | pr_info("QV %d locked\n", q_idx); |
27d9ce4f | 4523 | usleep_range(1000, 20000); |
5a85e737 ET |
4524 | } |
4525 | } | |
021230d4 AV |
4526 | } |
4527 | ||
67359c3c MR |
4528 | static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter) |
4529 | { | |
4530 | switch (adapter->hw.mac.type) { | |
4531 | case ixgbe_mac_X550: | |
4532 | case ixgbe_mac_X550EM_x: | |
4533 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0); | |
4534 | #ifdef CONFIG_IXGBE_VXLAN | |
4535 | adapter->vxlan_port = 0; | |
4536 | #endif | |
4537 | break; | |
4538 | default: | |
4539 | break; | |
4540 | } | |
4541 | } | |
4542 | ||
7a6b6f51 | 4543 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c | 4544 | /** |
2f90b865 AD |
4545 | * ixgbe_configure_dcb - Configure DCB hardware |
4546 | * @adapter: ixgbe adapter struct | |
4547 | * | |
4548 | * This is called by the driver on open to configure the DCB hardware. | |
4549 | * This is also called by the gennetlink interface when reconfiguring | |
4550 | * the DCB state. | |
4551 | */ | |
4552 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
4553 | { | |
4554 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 4555 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 4556 | |
67ebd791 AD |
4557 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
4558 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4559 | netif_set_gso_max_size(adapter->netdev, 65536); | |
4560 | return; | |
4561 | } | |
4562 | ||
4563 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4564 | netif_set_gso_max_size(adapter->netdev, 32768); | |
4565 | ||
971060b1 | 4566 | #ifdef IXGBE_FCOE |
b120818e JF |
4567 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
4568 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 4569 | #endif |
b120818e JF |
4570 | |
4571 | /* reconfigure the hardware */ | |
4572 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
4573 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
4574 | DCB_TX_CONFIG); | |
4575 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
4576 | DCB_RX_CONFIG); | |
4577 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
4578 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
4579 | ixgbe_dcb_hw_ets(&adapter->hw, | |
4580 | adapter->ixgbe_ieee_ets, | |
4581 | max_frame); | |
4582 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
4583 | adapter->ixgbe_ieee_pfc->pfc_en, | |
4584 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 4585 | } |
8187cd48 JF |
4586 | |
4587 | /* Enable RSS Hash per TC */ | |
4588 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4ae63730 AD |
4589 | u32 msb = 0; |
4590 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; | |
8187cd48 | 4591 | |
d411a936 AD |
4592 | while (rss_i) { |
4593 | msb++; | |
4594 | rss_i >>= 1; | |
4595 | } | |
8187cd48 | 4596 | |
4ae63730 AD |
4597 | /* write msb to all 8 TCs in one write */ |
4598 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); | |
8187cd48 | 4599 | } |
2f90b865 | 4600 | } |
9da712d2 JF |
4601 | #endif |
4602 | ||
4603 | /* Additional bittime to account for IXGBE framing */ | |
4604 | #define IXGBE_ETH_FRAMING 20 | |
4605 | ||
49ce9c2c | 4606 | /** |
9da712d2 JF |
4607 | * ixgbe_hpbthresh - calculate high water mark for flow control |
4608 | * | |
4609 | * @adapter: board private structure to calculate for | |
49ce9c2c | 4610 | * @pb: packet buffer to calculate |
9da712d2 JF |
4611 | */ |
4612 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
4613 | { | |
4614 | struct ixgbe_hw *hw = &adapter->hw; | |
4615 | struct net_device *dev = adapter->netdev; | |
4616 | int link, tc, kb, marker; | |
4617 | u32 dv_id, rx_pba; | |
4618 | ||
4619 | /* Calculate max LAN frame size */ | |
4620 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
4621 | ||
4622 | #ifdef IXGBE_FCOE | |
4623 | /* FCoE traffic class uses FCOE jumbo frames */ | |
800bd607 AD |
4624 | if ((dev->features & NETIF_F_FCOE_MTU) && |
4625 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
4626 | (pb == ixgbe_fcoe_get_tc(adapter))) | |
4627 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9da712d2 | 4628 | #endif |
e5776620 | 4629 | |
9da712d2 JF |
4630 | /* Calculate delay value for device */ |
4631 | switch (hw->mac.type) { | |
4632 | case ixgbe_mac_X540: | |
9a75a1ac DS |
4633 | case ixgbe_mac_X550: |
4634 | case ixgbe_mac_X550EM_x: | |
9da712d2 JF |
4635 | dv_id = IXGBE_DV_X540(link, tc); |
4636 | break; | |
4637 | default: | |
4638 | dv_id = IXGBE_DV(link, tc); | |
4639 | break; | |
4640 | } | |
4641 | ||
4642 | /* Loopback switch introduces additional latency */ | |
4643 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4644 | dv_id += IXGBE_B2BT(tc); | |
4645 | ||
4646 | /* Delay value is calculated in bit times convert to KB */ | |
4647 | kb = IXGBE_BT2KB(dv_id); | |
4648 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
4649 | ||
4650 | marker = rx_pba - kb; | |
4651 | ||
4652 | /* It is possible that the packet buffer is not large enough | |
4653 | * to provide required headroom. In this case throw an error | |
4654 | * to user and a do the best we can. | |
4655 | */ | |
4656 | if (marker < 0) { | |
4657 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
4658 | "headroom to support flow control." | |
4659 | "Decrease MTU or number of traffic classes\n", pb); | |
4660 | marker = tc + 1; | |
4661 | } | |
4662 | ||
4663 | return marker; | |
4664 | } | |
4665 | ||
49ce9c2c | 4666 | /** |
9da712d2 JF |
4667 | * ixgbe_lpbthresh - calculate low water mark for for flow control |
4668 | * | |
4669 | * @adapter: board private structure to calculate for | |
49ce9c2c | 4670 | * @pb: packet buffer to calculate |
9da712d2 | 4671 | */ |
e5776620 | 4672 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) |
9da712d2 JF |
4673 | { |
4674 | struct ixgbe_hw *hw = &adapter->hw; | |
4675 | struct net_device *dev = adapter->netdev; | |
4676 | int tc; | |
4677 | u32 dv_id; | |
4678 | ||
4679 | /* Calculate max LAN frame size */ | |
4680 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
4681 | ||
e5776620 JK |
4682 | #ifdef IXGBE_FCOE |
4683 | /* FCoE traffic class uses FCOE jumbo frames */ | |
4684 | if ((dev->features & NETIF_F_FCOE_MTU) && | |
4685 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
4686 | (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) | |
4687 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
4688 | #endif | |
4689 | ||
9da712d2 JF |
4690 | /* Calculate delay value for device */ |
4691 | switch (hw->mac.type) { | |
4692 | case ixgbe_mac_X540: | |
9a75a1ac DS |
4693 | case ixgbe_mac_X550: |
4694 | case ixgbe_mac_X550EM_x: | |
9da712d2 JF |
4695 | dv_id = IXGBE_LOW_DV_X540(tc); |
4696 | break; | |
4697 | default: | |
4698 | dv_id = IXGBE_LOW_DV(tc); | |
4699 | break; | |
4700 | } | |
4701 | ||
4702 | /* Delay value is calculated in bit times convert to KB */ | |
4703 | return IXGBE_BT2KB(dv_id); | |
4704 | } | |
4705 | ||
4706 | /* | |
4707 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
4708 | */ | |
4709 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
4710 | { | |
4711 | struct ixgbe_hw *hw = &adapter->hw; | |
4712 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
4713 | int i; | |
4714 | ||
4715 | if (!num_tc) | |
4716 | num_tc = 1; | |
4717 | ||
9da712d2 JF |
4718 | for (i = 0; i < num_tc; i++) { |
4719 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
e5776620 | 4720 | hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); |
9da712d2 JF |
4721 | |
4722 | /* Low water marks must not be larger than high water marks */ | |
e5776620 JK |
4723 | if (hw->fc.low_water[i] > hw->fc.high_water[i]) |
4724 | hw->fc.low_water[i] = 0; | |
9da712d2 | 4725 | } |
e5776620 JK |
4726 | |
4727 | for (; i < MAX_TRAFFIC_CLASS; i++) | |
4728 | hw->fc.high_water[i] = 0; | |
9da712d2 JF |
4729 | } |
4730 | ||
80605c65 JF |
4731 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
4732 | { | |
80605c65 | 4733 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
4734 | int hdrm; |
4735 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
4736 | |
4737 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
4738 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
4739 | hdrm = 32 << adapter->fdir_pballoc; |
4740 | else | |
4741 | hdrm = 0; | |
80605c65 | 4742 | |
f7e1027f | 4743 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 4744 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
4745 | } |
4746 | ||
e4911d57 AD |
4747 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
4748 | { | |
4749 | struct ixgbe_hw *hw = &adapter->hw; | |
b67bfe0d | 4750 | struct hlist_node *node2; |
e4911d57 AD |
4751 | struct ixgbe_fdir_filter *filter; |
4752 | ||
4753 | spin_lock(&adapter->fdir_perfect_lock); | |
4754 | ||
4755 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
4756 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
4757 | ||
b67bfe0d | 4758 | hlist_for_each_entry_safe(filter, node2, |
e4911d57 AD |
4759 | &adapter->fdir_filter_list, fdir_node) { |
4760 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
4761 | &filter->filter, |
4762 | filter->sw_idx, | |
4763 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
4764 | IXGBE_FDIR_DROP_QUEUE : | |
4765 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
4766 | } |
4767 | ||
4768 | spin_unlock(&adapter->fdir_perfect_lock); | |
4769 | } | |
4770 | ||
2a47fa45 JF |
4771 | static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, |
4772 | struct ixgbe_adapter *adapter) | |
4773 | { | |
4774 | struct ixgbe_hw *hw = &adapter->hw; | |
4775 | u32 vmolr; | |
4776 | ||
4777 | /* No unicast promiscuous support for VMDQ devices. */ | |
4778 | vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); | |
4779 | vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); | |
4780 | ||
4781 | /* clear the affected bit */ | |
4782 | vmolr &= ~IXGBE_VMOLR_MPE; | |
4783 | ||
4784 | if (dev->flags & IFF_ALLMULTI) { | |
4785 | vmolr |= IXGBE_VMOLR_MPE; | |
4786 | } else { | |
4787 | vmolr |= IXGBE_VMOLR_ROMPE; | |
4788 | hw->mac.ops.update_mc_addr_list(hw, dev); | |
4789 | } | |
5d7daa35 | 4790 | ixgbe_write_uc_addr_list(adapter->netdev, pool); |
2a47fa45 JF |
4791 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); |
4792 | } | |
4793 | ||
2a47fa45 JF |
4794 | static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) |
4795 | { | |
4796 | struct ixgbe_adapter *adapter = vadapter->real_adapter; | |
219354d4 | 4797 | int rss_i = adapter->num_rx_queues_per_pool; |
2a47fa45 JF |
4798 | struct ixgbe_hw *hw = &adapter->hw; |
4799 | u16 pool = vadapter->pool; | |
4800 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
4801 | IXGBE_PSRTYPE_UDPHDR | | |
4802 | IXGBE_PSRTYPE_IPV4HDR | | |
4803 | IXGBE_PSRTYPE_L2HDR | | |
4804 | IXGBE_PSRTYPE_IPV6HDR; | |
4805 | ||
4806 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4807 | return; | |
4808 | ||
4809 | if (rss_i > 3) | |
4810 | psrtype |= 2 << 29; | |
4811 | else if (rss_i > 1) | |
4812 | psrtype |= 1 << 29; | |
4813 | ||
4814 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); | |
4815 | } | |
4816 | ||
4817 | /** | |
4818 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
4819 | * @rx_ring: ring to free buffers from | |
4820 | **/ | |
4821 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) | |
4822 | { | |
4823 | struct device *dev = rx_ring->dev; | |
4824 | unsigned long size; | |
4825 | u16 i; | |
4826 | ||
4827 | /* ring already cleared, nothing to do */ | |
4828 | if (!rx_ring->rx_buffer_info) | |
4829 | return; | |
4830 | ||
4831 | /* Free all the Rx ring sk_buffs */ | |
4832 | for (i = 0; i < rx_ring->count; i++) { | |
18cb652a | 4833 | struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; |
2a47fa45 | 4834 | |
2a47fa45 JF |
4835 | if (rx_buffer->skb) { |
4836 | struct sk_buff *skb = rx_buffer->skb; | |
18cb652a | 4837 | if (IXGBE_CB(skb)->page_released) |
2a47fa45 JF |
4838 | dma_unmap_page(dev, |
4839 | IXGBE_CB(skb)->dma, | |
4840 | ixgbe_rx_bufsz(rx_ring), | |
4841 | DMA_FROM_DEVICE); | |
2a47fa45 | 4842 | dev_kfree_skb(skb); |
4d2fcfbc | 4843 | rx_buffer->skb = NULL; |
2a47fa45 | 4844 | } |
18cb652a AD |
4845 | |
4846 | if (!rx_buffer->page) | |
4847 | continue; | |
4848 | ||
4849 | dma_unmap_page(dev, rx_buffer->dma, | |
4850 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
4851 | __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); | |
4852 | ||
2a47fa45 JF |
4853 | rx_buffer->page = NULL; |
4854 | } | |
4855 | ||
4856 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4857 | memset(rx_ring->rx_buffer_info, 0, size); | |
4858 | ||
4859 | /* Zero out the descriptor ring */ | |
4860 | memset(rx_ring->desc, 0, rx_ring->size); | |
4861 | ||
4862 | rx_ring->next_to_alloc = 0; | |
4863 | rx_ring->next_to_clean = 0; | |
4864 | rx_ring->next_to_use = 0; | |
4865 | } | |
4866 | ||
4867 | static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, | |
4868 | struct ixgbe_ring *rx_ring) | |
4869 | { | |
4870 | struct ixgbe_adapter *adapter = vadapter->real_adapter; | |
4871 | int index = rx_ring->queue_index + vadapter->rx_base_queue; | |
4872 | ||
4873 | /* shutdown specific queue receive and wait for dma to settle */ | |
4874 | ixgbe_disable_rx_queue(adapter, rx_ring); | |
4875 | usleep_range(10000, 20000); | |
4876 | ixgbe_irq_disable_queues(adapter, ((u64)1 << index)); | |
4877 | ixgbe_clean_rx_ring(rx_ring); | |
4878 | rx_ring->l2_accel_priv = NULL; | |
4879 | } | |
4880 | ||
ae72c8d0 JF |
4881 | static int ixgbe_fwd_ring_down(struct net_device *vdev, |
4882 | struct ixgbe_fwd_adapter *accel) | |
2a47fa45 JF |
4883 | { |
4884 | struct ixgbe_adapter *adapter = accel->real_adapter; | |
4885 | unsigned int rxbase = accel->rx_base_queue; | |
4886 | unsigned int txbase = accel->tx_base_queue; | |
4887 | int i; | |
4888 | ||
4889 | netif_tx_stop_all_queues(vdev); | |
4890 | ||
4891 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
4892 | ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); | |
4893 | adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; | |
4894 | } | |
4895 | ||
4896 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
4897 | adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; | |
4898 | adapter->tx_ring[txbase + i]->netdev = adapter->netdev; | |
4899 | } | |
4900 | ||
4901 | ||
4902 | return 0; | |
4903 | } | |
4904 | ||
4905 | static int ixgbe_fwd_ring_up(struct net_device *vdev, | |
4906 | struct ixgbe_fwd_adapter *accel) | |
4907 | { | |
4908 | struct ixgbe_adapter *adapter = accel->real_adapter; | |
4909 | unsigned int rxbase, txbase, queues; | |
4910 | int i, baseq, err = 0; | |
4911 | ||
4912 | if (!test_bit(accel->pool, &adapter->fwd_bitmask)) | |
4913 | return 0; | |
4914 | ||
4915 | baseq = accel->pool * adapter->num_rx_queues_per_pool; | |
4916 | netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", | |
4917 | accel->pool, adapter->num_rx_pools, | |
4918 | baseq, baseq + adapter->num_rx_queues_per_pool, | |
4919 | adapter->fwd_bitmask); | |
4920 | ||
4921 | accel->netdev = vdev; | |
4922 | accel->rx_base_queue = rxbase = baseq; | |
4923 | accel->tx_base_queue = txbase = baseq; | |
4924 | ||
4925 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) | |
4926 | ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); | |
4927 | ||
4928 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
4929 | adapter->rx_ring[rxbase + i]->netdev = vdev; | |
4930 | adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; | |
4931 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); | |
4932 | } | |
4933 | ||
4934 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
4935 | adapter->tx_ring[txbase + i]->netdev = vdev; | |
4936 | adapter->tx_ring[txbase + i]->l2_accel_priv = accel; | |
4937 | } | |
4938 | ||
4939 | queues = min_t(unsigned int, | |
4940 | adapter->num_rx_queues_per_pool, vdev->num_tx_queues); | |
4941 | err = netif_set_real_num_tx_queues(vdev, queues); | |
4942 | if (err) | |
4943 | goto fwd_queue_err; | |
4944 | ||
2a47fa45 JF |
4945 | err = netif_set_real_num_rx_queues(vdev, queues); |
4946 | if (err) | |
4947 | goto fwd_queue_err; | |
4948 | ||
4949 | if (is_valid_ether_addr(vdev->dev_addr)) | |
4950 | ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); | |
4951 | ||
4952 | ixgbe_fwd_psrtype(accel); | |
4953 | ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); | |
4954 | return err; | |
4955 | fwd_queue_err: | |
4956 | ixgbe_fwd_ring_down(vdev, accel); | |
4957 | return err; | |
4958 | } | |
4959 | ||
4960 | static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) | |
4961 | { | |
4962 | struct net_device *upper; | |
4963 | struct list_head *iter; | |
4964 | int err; | |
4965 | ||
4966 | netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { | |
4967 | if (netif_is_macvlan(upper)) { | |
4968 | struct macvlan_dev *dfwd = netdev_priv(upper); | |
4969 | struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; | |
4970 | ||
4971 | if (dfwd->fwd_priv) { | |
4972 | err = ixgbe_fwd_ring_up(upper, vadapter); | |
4973 | if (err) | |
4974 | continue; | |
4975 | } | |
4976 | } | |
4977 | } | |
4978 | } | |
4979 | ||
9a799d71 AK |
4980 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
4981 | { | |
d2f5e7f3 AS |
4982 | struct ixgbe_hw *hw = &adapter->hw; |
4983 | ||
80605c65 | 4984 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 4985 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 4986 | ixgbe_configure_dcb(adapter); |
2f90b865 | 4987 | #endif |
b35d4d42 AD |
4988 | /* |
4989 | * We must restore virtualization before VLANs or else | |
4990 | * the VLVF registers will not be populated | |
4991 | */ | |
4992 | ixgbe_configure_virtualization(adapter); | |
9a799d71 | 4993 | |
4c1d7b4b | 4994 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
4995 | ixgbe_restore_vlan(adapter); |
4996 | ||
d2f5e7f3 AS |
4997 | switch (hw->mac.type) { |
4998 | case ixgbe_mac_82599EB: | |
4999 | case ixgbe_mac_X540: | |
5000 | hw->mac.ops.disable_rx_buff(hw); | |
5001 | break; | |
5002 | default: | |
5003 | break; | |
5004 | } | |
5005 | ||
c4cf55e5 | 5006 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
5007 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
5008 | adapter->fdir_pballoc); | |
e4911d57 AD |
5009 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
5010 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
5011 | adapter->fdir_pballoc); | |
5012 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 5013 | } |
4c1d7b4b | 5014 | |
d2f5e7f3 AS |
5015 | switch (hw->mac.type) { |
5016 | case ixgbe_mac_82599EB: | |
5017 | case ixgbe_mac_X540: | |
5018 | hw->mac.ops.enable_rx_buff(hw); | |
5019 | break; | |
5020 | default: | |
5021 | break; | |
5022 | } | |
5023 | ||
9de7605e MR |
5024 | #ifdef CONFIG_IXGBE_DCA |
5025 | /* configure DCA */ | |
5026 | if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) | |
5027 | ixgbe_setup_dca(adapter); | |
5028 | #endif /* CONFIG_IXGBE_DCA */ | |
5029 | ||
7c8ae65a AD |
5030 | #ifdef IXGBE_FCOE |
5031 | /* configure FCoE L2 filters, redirection table, and Rx control */ | |
5032 | ixgbe_configure_fcoe(adapter); | |
5033 | ||
5034 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5035 | ixgbe_configure_tx(adapter); |
5036 | ixgbe_configure_rx(adapter); | |
2a47fa45 | 5037 | ixgbe_configure_dfwd(adapter); |
9a799d71 AK |
5038 | } |
5039 | ||
0ecc061d | 5040 | /** |
e8e26350 PW |
5041 | * ixgbe_sfp_link_config - set up SFP+ link |
5042 | * @adapter: pointer to private adapter struct | |
5043 | **/ | |
5044 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
5045 | { | |
7086400d | 5046 | /* |
52f33af8 | 5047 | * We are assuming the worst case scenario here, and that |
7086400d AD |
5048 | * is that an SFP was inserted/removed after the reset |
5049 | * but before SFP detection was enabled. As such the best | |
5050 | * solution is to just start searching as soon as we start | |
5051 | */ | |
5052 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5053 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 5054 | |
7086400d | 5055 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
58e7cd24 | 5056 | adapter->sfp_poll_time = 0; |
e8e26350 PW |
5057 | } |
5058 | ||
5059 | /** | |
5060 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
5061 | * @hw: pointer to private hardware struct |
5062 | * | |
5063 | * Returns 0 on success, negative on failure | |
5064 | **/ | |
e8e26350 | 5065 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d | 5066 | { |
3d292265 JH |
5067 | u32 speed; |
5068 | bool autoneg, link_up = false; | |
a1e869de | 5069 | int ret = IXGBE_ERR_LINK_SETUP; |
0ecc061d PWJ |
5070 | |
5071 | if (hw->mac.ops.check_link) | |
3d292265 | 5072 | ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); |
0ecc061d PWJ |
5073 | |
5074 | if (ret) | |
e90dd264 | 5075 | return ret; |
0ecc061d | 5076 | |
3d292265 JH |
5077 | speed = hw->phy.autoneg_advertised; |
5078 | if ((!speed) && (hw->mac.ops.get_link_capabilities)) | |
5079 | ret = hw->mac.ops.get_link_capabilities(hw, &speed, | |
5080 | &autoneg); | |
0ecc061d | 5081 | if (ret) |
e90dd264 | 5082 | return ret; |
0ecc061d | 5083 | |
8620a103 | 5084 | if (hw->mac.ops.setup_link) |
fd0326f2 | 5085 | ret = hw->mac.ops.setup_link(hw, speed, link_up); |
e90dd264 | 5086 | |
0ecc061d PWJ |
5087 | return ret; |
5088 | } | |
5089 | ||
a34bcfff | 5090 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 5091 | { |
9a799d71 | 5092 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 5093 | u32 gpie = 0; |
9a799d71 | 5094 | |
9b471446 | 5095 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
5096 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
5097 | IXGBE_GPIE_OCD; | |
5098 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
5099 | /* |
5100 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
5101 | * this saves a register write for every interrupt | |
5102 | */ | |
5103 | switch (hw->mac.type) { | |
5104 | case ixgbe_mac_82598EB: | |
5105 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
5106 | break; | |
9b471446 | 5107 | case ixgbe_mac_82599EB: |
b93a2226 | 5108 | case ixgbe_mac_X540: |
9a75a1ac DS |
5109 | case ixgbe_mac_X550: |
5110 | case ixgbe_mac_X550EM_x: | |
b93a2226 | 5111 | default: |
9b471446 JB |
5112 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
5113 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
5114 | break; | |
5115 | } | |
5116 | } else { | |
021230d4 AV |
5117 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
5118 | * specifically only auto mask tx and rx interrupts */ | |
5119 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
5120 | } | |
9a799d71 | 5121 | |
a34bcfff AD |
5122 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
5123 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
5124 | ||
5125 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
5126 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
73079ea0 AD |
5127 | |
5128 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { | |
5129 | case IXGBE_82599_VMDQ_8Q_MASK: | |
5130 | gpie |= IXGBE_GPIE_VTMODE_16; | |
5131 | break; | |
5132 | case IXGBE_82599_VMDQ_4Q_MASK: | |
5133 | gpie |= IXGBE_GPIE_VTMODE_32; | |
5134 | break; | |
5135 | default: | |
5136 | gpie |= IXGBE_GPIE_VTMODE_64; | |
5137 | break; | |
5138 | } | |
119fc60a MC |
5139 | } |
5140 | ||
5fdd31f9 | 5141 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
5142 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
5143 | switch (adapter->hw.mac.type) { | |
5144 | case ixgbe_mac_82599EB: | |
9a900eca | 5145 | gpie |= IXGBE_SDP0_GPIEN_8259X; |
f3df98ec | 5146 | break; |
f3df98ec DS |
5147 | default: |
5148 | break; | |
5149 | } | |
5150 | } | |
5fdd31f9 | 5151 | |
a34bcfff AD |
5152 | /* Enable fan failure interrupt */ |
5153 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
9a900eca | 5154 | gpie |= IXGBE_SDP1_GPIEN(hw); |
0befdb3e | 5155 | |
a023bbd0 DS |
5156 | switch (hw->mac.type) { |
5157 | case ixgbe_mac_82599EB: | |
5158 | gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; | |
5159 | break; | |
5160 | case ixgbe_mac_X550EM_x: | |
5161 | gpie |= IXGBE_SDP0_GPIEN_X540; | |
5162 | break; | |
5163 | default: | |
5164 | break; | |
2698b208 | 5165 | } |
a34bcfff AD |
5166 | |
5167 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
5168 | } | |
5169 | ||
c7ccde0f | 5170 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
5171 | { |
5172 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 5173 | int err; |
a34bcfff AD |
5174 | u32 ctrl_ext; |
5175 | ||
5176 | ixgbe_get_hw_control(adapter); | |
5177 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 5178 | |
9a799d71 AK |
5179 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
5180 | ixgbe_configure_msix(adapter); | |
5181 | else | |
5182 | ixgbe_configure_msi_and_legacy(adapter); | |
5183 | ||
ec74a471 ET |
5184 | /* enable the optics for 82599 SFP+ fiber */ |
5185 | if (hw->mac.ops.enable_tx_laser) | |
61fac744 PW |
5186 | hw->mac.ops.enable_tx_laser(hw); |
5187 | ||
961fac88 DS |
5188 | if (hw->phy.ops.set_phy_power) |
5189 | hw->phy.ops.set_phy_power(hw, true); | |
5190 | ||
4e857c58 | 5191 | smp_mb__before_atomic(); |
9a799d71 | 5192 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
5193 | ixgbe_napi_enable_all(adapter); |
5194 | ||
73c4b7cd AD |
5195 | if (ixgbe_is_sfp(hw)) { |
5196 | ixgbe_sfp_link_config(adapter); | |
5197 | } else { | |
5198 | err = ixgbe_non_sfp_link_config(hw); | |
5199 | if (err) | |
5200 | e_err(probe, "link_config FAILED %d\n", err); | |
5201 | } | |
5202 | ||
021230d4 AV |
5203 | /* clear any pending interrupts, may auto mask */ |
5204 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 5205 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 5206 | |
bf069c97 DS |
5207 | /* |
5208 | * If this adapter has a fan, check to see if we had a failure | |
5209 | * before we enabled the interrupt. | |
5210 | */ | |
5211 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5212 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5213 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 5214 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
5215 | } |
5216 | ||
9a799d71 AK |
5217 | /* bring the link up in the watchdog, this could race with our first |
5218 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
5219 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
5220 | adapter->link_check_timeout = jiffies; | |
7086400d | 5221 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
5222 | |
5223 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
5224 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
5225 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
5226 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
5227 | } |
5228 | ||
d4f80882 AV |
5229 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
5230 | { | |
5231 | WARN_ON(in_interrupt()); | |
7086400d AD |
5232 | /* put off any impending NetWatchDogTimeout */ |
5233 | adapter->netdev->trans_start = jiffies; | |
5234 | ||
d4f80882 | 5235 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 5236 | usleep_range(1000, 2000); |
d4f80882 | 5237 | ixgbe_down(adapter); |
5809a1ae GR |
5238 | /* |
5239 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
5240 | * back up to give the VFs time to respond to the reset. The | |
5241 | * two second wait is based upon the watchdog timer cycle in | |
5242 | * the VF driver. | |
5243 | */ | |
5244 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
5245 | msleep(2000); | |
d4f80882 AV |
5246 | ixgbe_up(adapter); |
5247 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
5248 | } | |
5249 | ||
c7ccde0f | 5250 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5251 | { |
5252 | /* hardware has been reset, we need to reload some things */ | |
5253 | ixgbe_configure(adapter); | |
5254 | ||
c7ccde0f | 5255 | ixgbe_up_complete(adapter); |
9a799d71 AK |
5256 | } |
5257 | ||
5258 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
5259 | { | |
c44ade9e | 5260 | struct ixgbe_hw *hw = &adapter->hw; |
5d7daa35 | 5261 | struct net_device *netdev = adapter->netdev; |
8ca783ab DS |
5262 | int err; |
5263 | ||
b0483c8f MR |
5264 | if (ixgbe_removed(hw->hw_addr)) |
5265 | return; | |
7086400d AD |
5266 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
5267 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5268 | usleep_range(1000, 2000); | |
5269 | ||
5270 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
5271 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
5272 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
5273 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5274 | ||
8ca783ab | 5275 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
5276 | switch (err) { |
5277 | case 0: | |
5278 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 5279 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
5280 | break; |
5281 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 5282 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 5283 | break; |
794caeb2 PWJ |
5284 | case IXGBE_ERR_EEPROM_VERSION: |
5285 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 5286 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 5287 | "Please be aware there may be issues associated with " |
849c4542 ET |
5288 | "your hardware. If you are experiencing problems " |
5289 | "please contact your Intel or hardware " | |
5290 | "representative who provided you with this " | |
5291 | "hardware.\n"); | |
794caeb2 | 5292 | break; |
da4dd0f7 | 5293 | default: |
849c4542 | 5294 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 5295 | } |
9a799d71 | 5296 | |
7086400d | 5297 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
0f079d22 AD |
5298 | |
5299 | /* flush entries out of MAC table */ | |
5d7daa35 | 5300 | ixgbe_flush_sw_mac_table(adapter); |
0f079d22 AD |
5301 | __dev_uc_unsync(netdev, NULL); |
5302 | ||
5303 | /* do not flush user set addresses */ | |
c9f53e63 | 5304 | ixgbe_mac_set_default_filter(adapter); |
7fa7c9dc AD |
5305 | |
5306 | /* update SAN MAC vmdq pool selection */ | |
5307 | if (hw->mac.san_mac_rar_index) | |
5308 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
1a71ab24 | 5309 | |
8fecf67c | 5310 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 5311 | ixgbe_ptp_reset(adapter); |
961fac88 DS |
5312 | |
5313 | if (hw->phy.ops.set_phy_power) { | |
5314 | if (!netif_running(adapter->netdev) && !adapter->wol) | |
5315 | hw->phy.ops.set_phy_power(hw, false); | |
5316 | else | |
5317 | hw->phy.ops.set_phy_power(hw, true); | |
5318 | } | |
9a799d71 AK |
5319 | } |
5320 | ||
9a799d71 AK |
5321 | /** |
5322 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
5323 | * @tx_ring: ring to be cleaned |
5324 | **/ | |
b6ec895e | 5325 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
5326 | { |
5327 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5328 | unsigned long size; | |
b6ec895e | 5329 | u16 i; |
9a799d71 | 5330 | |
84418e3b AD |
5331 | /* ring already cleared, nothing to do */ |
5332 | if (!tx_ring->tx_buffer_info) | |
5333 | return; | |
9a799d71 | 5334 | |
84418e3b | 5335 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
5336 | for (i = 0; i < tx_ring->count; i++) { |
5337 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 5338 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
5339 | } |
5340 | ||
dad8a3b3 JF |
5341 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
5342 | ||
9a799d71 AK |
5343 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
5344 | memset(tx_ring->tx_buffer_info, 0, size); | |
5345 | ||
5346 | /* Zero out the descriptor ring */ | |
5347 | memset(tx_ring->desc, 0, tx_ring->size); | |
5348 | ||
5349 | tx_ring->next_to_use = 0; | |
5350 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
5351 | } |
5352 | ||
5353 | /** | |
021230d4 | 5354 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
5355 | * @adapter: board private structure |
5356 | **/ | |
021230d4 | 5357 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5358 | { |
5359 | int i; | |
5360 | ||
021230d4 | 5361 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 5362 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
5363 | } |
5364 | ||
5365 | /** | |
021230d4 | 5366 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
5367 | * @adapter: board private structure |
5368 | **/ | |
021230d4 | 5369 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5370 | { |
5371 | int i; | |
5372 | ||
021230d4 | 5373 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 5374 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
5375 | } |
5376 | ||
e4911d57 AD |
5377 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
5378 | { | |
b67bfe0d | 5379 | struct hlist_node *node2; |
e4911d57 AD |
5380 | struct ixgbe_fdir_filter *filter; |
5381 | ||
5382 | spin_lock(&adapter->fdir_perfect_lock); | |
5383 | ||
b67bfe0d | 5384 | hlist_for_each_entry_safe(filter, node2, |
e4911d57 AD |
5385 | &adapter->fdir_filter_list, fdir_node) { |
5386 | hlist_del(&filter->fdir_node); | |
5387 | kfree(filter); | |
5388 | } | |
5389 | adapter->fdir_filter_count = 0; | |
5390 | ||
5391 | spin_unlock(&adapter->fdir_perfect_lock); | |
5392 | } | |
5393 | ||
9a799d71 AK |
5394 | void ixgbe_down(struct ixgbe_adapter *adapter) |
5395 | { | |
5396 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 5397 | struct ixgbe_hw *hw = &adapter->hw; |
2a47fa45 JF |
5398 | struct net_device *upper; |
5399 | struct list_head *iter; | |
bf29ee6c | 5400 | int i; |
9a799d71 AK |
5401 | |
5402 | /* signal that we are down to the interrupt handler */ | |
c3049c8f MR |
5403 | if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) |
5404 | return; /* do nothing if already down */ | |
9a799d71 AK |
5405 | |
5406 | /* disable receives */ | |
1f9ac57c | 5407 | hw->mac.ops.disable_rx(hw); |
9a799d71 | 5408 | |
2d39d576 YZ |
5409 | /* disable all enabled rx queues */ |
5410 | for (i = 0; i < adapter->num_rx_queues; i++) | |
5411 | /* this call also flushes the previous write */ | |
5412 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
5413 | ||
032b4325 | 5414 | usleep_range(10000, 20000); |
9a799d71 | 5415 | |
7f821875 JB |
5416 | netif_tx_stop_all_queues(netdev); |
5417 | ||
7086400d | 5418 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
5419 | netif_carrier_off(netdev); |
5420 | netif_tx_disable(netdev); | |
5421 | ||
2a47fa45 JF |
5422 | /* disable any upper devices */ |
5423 | netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { | |
5424 | if (netif_is_macvlan(upper)) { | |
5425 | struct macvlan_dev *vlan = netdev_priv(upper); | |
5426 | ||
5427 | if (vlan->fwd_priv) { | |
5428 | netif_tx_stop_all_queues(upper); | |
5429 | netif_carrier_off(upper); | |
5430 | netif_tx_disable(upper); | |
5431 | } | |
5432 | } | |
5433 | } | |
5434 | ||
c0dfb90e JF |
5435 | ixgbe_irq_disable(adapter); |
5436 | ||
5437 | ixgbe_napi_disable_all(adapter); | |
5438 | ||
d034acf1 AD |
5439 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
5440 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
5441 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
5442 | ||
5443 | del_timer_sync(&adapter->service_timer); | |
5444 | ||
34cecbbf | 5445 | if (adapter->num_vfs) { |
8e34d1aa AD |
5446 | /* Clear EITR Select mapping */ |
5447 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
5448 | |
5449 | /* Mark all the VFs as inactive */ | |
5450 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 5451 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 5452 | |
34cecbbf AD |
5453 | /* ping all the active vfs to let them know we are going down */ |
5454 | ixgbe_ping_all_vfs(adapter); | |
5455 | ||
5456 | /* Disable all VFTE/VFRE TX/RX */ | |
5457 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
5458 | } |
5459 | ||
7f821875 JB |
5460 | /* disable transmits in the hardware now that interrupts are off */ |
5461 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 5462 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 5463 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 5464 | } |
34cecbbf | 5465 | |
9a75a1ac | 5466 | /* Disable the Tx DMA engine on 82599 and later MAC */ |
bd508178 AD |
5467 | switch (hw->mac.type) { |
5468 | case ixgbe_mac_82599EB: | |
b93a2226 | 5469 | case ixgbe_mac_X540: |
9a75a1ac DS |
5470 | case ixgbe_mac_X550: |
5471 | case ixgbe_mac_X550EM_x: | |
88512539 | 5472 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
5473 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
5474 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
5475 | break; |
5476 | default: | |
5477 | break; | |
5478 | } | |
7f821875 | 5479 | |
6f4a0e45 PL |
5480 | if (!pci_channel_offline(adapter->pdev)) |
5481 | ixgbe_reset(adapter); | |
c6ecf39a | 5482 | |
ec74a471 ET |
5483 | /* power down the optics for 82599 SFP+ fiber */ |
5484 | if (hw->mac.ops.disable_tx_laser) | |
c6ecf39a DS |
5485 | hw->mac.ops.disable_tx_laser(hw); |
5486 | ||
9a799d71 AK |
5487 | ixgbe_clean_all_tx_rings(adapter); |
5488 | ixgbe_clean_all_rx_rings(adapter); | |
9a799d71 AK |
5489 | } |
5490 | ||
9a799d71 AK |
5491 | /** |
5492 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
5493 | * @netdev: network interface device structure | |
5494 | **/ | |
5495 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
5496 | { | |
5497 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5498 | ||
5499 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 5500 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
5501 | } |
5502 | ||
9a799d71 AK |
5503 | /** |
5504 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
5505 | * @adapter: board private structure to initialize | |
5506 | * | |
5507 | * ixgbe_sw_init initializes the Adapter private data structure. | |
5508 | * Fields are initialized based on PCI device information and | |
5509 | * OS network device settings (MTU size). | |
5510 | **/ | |
9f9a12f8 | 5511 | static int ixgbe_sw_init(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5512 | { |
5513 | struct ixgbe_hw *hw = &adapter->hw; | |
5514 | struct pci_dev *pdev = adapter->pdev; | |
d3cb9869 | 5515 | unsigned int rss, fdir; |
cb6d0f5e | 5516 | u32 fwsm; |
7a6b6f51 | 5517 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5518 | int j; |
5519 | struct tc_configuration *tc; | |
5520 | #endif | |
021230d4 | 5521 | |
c44ade9e JB |
5522 | /* PCI config space info */ |
5523 | ||
5524 | hw->vendor_id = pdev->vendor; | |
5525 | hw->device_id = pdev->device; | |
5526 | hw->revision_id = pdev->revision; | |
5527 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
5528 | hw->subsystem_device_id = pdev->subsystem_device; | |
5529 | ||
8fc3bb6d | 5530 | /* Set common capability flags and settings */ |
0f9b232b | 5531 | rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); |
c087663e | 5532 | adapter->ring_feature[RING_F_RSS].limit = rss; |
8fc3bb6d | 5533 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
8fc3bb6d ET |
5534 | adapter->max_q_vectors = MAX_Q_VECTORS_82599; |
5535 | adapter->atr_sample_rate = 20; | |
d3cb9869 AD |
5536 | fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); |
5537 | adapter->ring_feature[RING_F_FDIR].limit = fdir; | |
8fc3bb6d ET |
5538 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
5539 | #ifdef CONFIG_IXGBE_DCA | |
5540 | adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; | |
5541 | #endif | |
5542 | #ifdef IXGBE_FCOE | |
5543 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; | |
5544 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5545 | #ifdef CONFIG_IXGBE_DCB | |
5546 | /* Default traffic class to use for FCoE */ | |
5547 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; | |
5548 | #endif /* CONFIG_IXGBE_DCB */ | |
5549 | #endif /* IXGBE_FCOE */ | |
5550 | ||
b82b17d9 JF |
5551 | /* initialize static ixgbe jump table entries */ |
5552 | adapter->jump_tables[0] = ixgbe_ipv4_fields; | |
5553 | ||
5d7daa35 JK |
5554 | adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * |
5555 | hw->mac.num_rar_entries, | |
5556 | GFP_ATOMIC); | |
530fd82a AD |
5557 | if (!adapter->mac_table) |
5558 | return -ENOMEM; | |
5d7daa35 | 5559 | |
8fc3bb6d | 5560 | /* Set MAC specific capability flags and exceptions */ |
bd508178 AD |
5561 | switch (hw->mac.type) { |
5562 | case ixgbe_mac_82598EB: | |
8fc3bb6d | 5563 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; |
8fc3bb6d | 5564 | |
bf069c97 DS |
5565 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
5566 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
8fc3bb6d | 5567 | |
49c7ffbe | 5568 | adapter->max_q_vectors = MAX_Q_VECTORS_82598; |
8fc3bb6d ET |
5569 | adapter->ring_feature[RING_F_FDIR].limit = 0; |
5570 | adapter->atr_sample_rate = 0; | |
5571 | adapter->fdir_pballoc = 0; | |
5572 | #ifdef IXGBE_FCOE | |
5573 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
5574 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5575 | #ifdef CONFIG_IXGBE_DCB | |
5576 | adapter->fcoe.up = 0; | |
5577 | #endif /* IXGBE_DCB */ | |
5578 | #endif /* IXGBE_FCOE */ | |
5579 | break; | |
5580 | case ixgbe_mac_82599EB: | |
5581 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) | |
5582 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
bd508178 | 5583 | break; |
b93a2226 | 5584 | case ixgbe_mac_X540: |
9a900eca | 5585 | fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); |
cb6d0f5e JK |
5586 | if (fwsm & IXGBE_FWSM_TS_ENABLED) |
5587 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
bd508178 | 5588 | break; |
9a75a1ac DS |
5589 | case ixgbe_mac_X550EM_x: |
5590 | case ixgbe_mac_X550: | |
5591 | #ifdef CONFIG_IXGBE_DCA | |
5592 | adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; | |
67359c3c MR |
5593 | #endif |
5594 | #ifdef CONFIG_IXGBE_VXLAN | |
5595 | adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; | |
9a75a1ac DS |
5596 | #endif |
5597 | break; | |
bd508178 AD |
5598 | default: |
5599 | break; | |
f8212f97 | 5600 | } |
2f90b865 | 5601 | |
7c8ae65a AD |
5602 | #ifdef IXGBE_FCOE |
5603 | /* FCoE support exists, always init the FCoE lock */ | |
5604 | spin_lock_init(&adapter->fcoe.lock); | |
5605 | ||
5606 | #endif | |
1fc5f038 AD |
5607 | /* n-tuple support exists, always init our spinlock */ |
5608 | spin_lock_init(&adapter->fdir_perfect_lock); | |
5609 | ||
7a6b6f51 | 5610 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
5611 | switch (hw->mac.type) { |
5612 | case ixgbe_mac_X540: | |
9a75a1ac DS |
5613 | case ixgbe_mac_X550: |
5614 | case ixgbe_mac_X550EM_x: | |
4de2a022 JF |
5615 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; |
5616 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
5617 | break; | |
5618 | default: | |
5619 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
5620 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
5621 | break; | |
5622 | } | |
5623 | ||
2f90b865 AD |
5624 | /* Configure DCB traffic classes */ |
5625 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
5626 | tc = &adapter->dcb_cfg.tc_config[j]; | |
5627 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
5628 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
5629 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
5630 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
5631 | tc->dcb_pfc = pfc_disabled; | |
5632 | } | |
4de2a022 JF |
5633 | |
5634 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
5635 | tc = &adapter->dcb_cfg.tc_config[0]; | |
5636 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5637 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5638 | ||
2f90b865 AD |
5639 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
5640 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 5641 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 5642 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 5643 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
f525c6d2 JF |
5644 | memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, |
5645 | sizeof(adapter->temp_dcb_cfg)); | |
2f90b865 AD |
5646 | |
5647 | #endif | |
9a799d71 AK |
5648 | |
5649 | /* default flow control settings */ | |
cd7664f6 | 5650 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 5651 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
9da712d2 | 5652 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
5653 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
5654 | hw->fc.send_xon = true; | |
73d80953 | 5655 | hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); |
9a799d71 | 5656 | |
99d74487 | 5657 | #ifdef CONFIG_PCI_IOV |
170e8543 JK |
5658 | if (max_vfs > 0) |
5659 | e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); | |
5660 | ||
99d74487 | 5661 | /* assign number of SR-IOV VFs */ |
170e8543 | 5662 | if (hw->mac.type != ixgbe_mac_82598EB) { |
dcc23e3a | 5663 | if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { |
170e8543 JK |
5664 | adapter->num_vfs = 0; |
5665 | e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); | |
5666 | } else { | |
5667 | adapter->num_vfs = max_vfs; | |
5668 | } | |
5669 | } | |
5670 | #endif /* CONFIG_PCI_IOV */ | |
99d74487 | 5671 | |
30efa5a3 | 5672 | /* enable itr by default in dynamic mode */ |
f7554a2b | 5673 | adapter->rx_itr_setting = 1; |
f7554a2b | 5674 | adapter->tx_itr_setting = 1; |
30efa5a3 | 5675 | |
30efa5a3 JB |
5676 | /* set default ring sizes */ |
5677 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
5678 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
5679 | ||
bd198058 | 5680 | /* set default work limits */ |
59224555 | 5681 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 5682 | |
9a799d71 | 5683 | /* initialize eeprom parameters */ |
c44ade9e | 5684 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 5685 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
5686 | return -EIO; |
5687 | } | |
5688 | ||
2a47fa45 JF |
5689 | /* PF holds first pool slot */ |
5690 | set_bit(0, &adapter->fwd_bitmask); | |
9a799d71 AK |
5691 | set_bit(__IXGBE_DOWN, &adapter->state); |
5692 | ||
5693 | return 0; | |
5694 | } | |
5695 | ||
5696 | /** | |
5697 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 5698 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5699 | * |
5700 | * Return 0 on success, negative on failure | |
5701 | **/ | |
b6ec895e | 5702 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5703 | { |
b6ec895e | 5704 | struct device *dev = tx_ring->dev; |
de88eeeb | 5705 | int orig_node = dev_to_node(dev); |
ca8dfe25 | 5706 | int ring_node = -1; |
9a799d71 AK |
5707 | int size; |
5708 | ||
3a581073 | 5709 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
5710 | |
5711 | if (tx_ring->q_vector) | |
ca8dfe25 | 5712 | ring_node = tx_ring->q_vector->numa_node; |
de88eeeb | 5713 | |
ca8dfe25 | 5714 | tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); |
1a6c14a2 | 5715 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 5716 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
5717 | if (!tx_ring->tx_buffer_info) |
5718 | goto err; | |
9a799d71 | 5719 | |
827da44c JS |
5720 | u64_stats_init(&tx_ring->syncp); |
5721 | ||
9a799d71 | 5722 | /* round up to nearest 4K */ |
12207e49 | 5723 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 5724 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 5725 | |
ca8dfe25 | 5726 | set_dev_node(dev, ring_node); |
de88eeeb AD |
5727 | tx_ring->desc = dma_alloc_coherent(dev, |
5728 | tx_ring->size, | |
5729 | &tx_ring->dma, | |
5730 | GFP_KERNEL); | |
5731 | set_dev_node(dev, orig_node); | |
5732 | if (!tx_ring->desc) | |
5733 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
5734 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
5735 | if (!tx_ring->desc) |
5736 | goto err; | |
9a799d71 | 5737 | |
3a581073 JB |
5738 | tx_ring->next_to_use = 0; |
5739 | tx_ring->next_to_clean = 0; | |
9a799d71 | 5740 | return 0; |
e01c31a5 JB |
5741 | |
5742 | err: | |
5743 | vfree(tx_ring->tx_buffer_info); | |
5744 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 5745 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 5746 | return -ENOMEM; |
9a799d71 AK |
5747 | } |
5748 | ||
69888674 AD |
5749 | /** |
5750 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
5751 | * @adapter: board private structure | |
5752 | * | |
5753 | * If this function returns with an error, then it's possible one or | |
5754 | * more of the rings is populated (while the rest are not). It is the | |
5755 | * callers duty to clean those orphaned rings. | |
5756 | * | |
5757 | * Return 0 on success, negative on failure | |
5758 | **/ | |
5759 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
5760 | { | |
5761 | int i, err = 0; | |
5762 | ||
5763 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 5764 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
5765 | if (!err) |
5766 | continue; | |
de3d5b94 | 5767 | |
396e799c | 5768 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
de3d5b94 | 5769 | goto err_setup_tx; |
69888674 AD |
5770 | } |
5771 | ||
de3d5b94 AD |
5772 | return 0; |
5773 | err_setup_tx: | |
5774 | /* rewind the index freeing the rings as we go */ | |
5775 | while (i--) | |
5776 | ixgbe_free_tx_resources(adapter->tx_ring[i]); | |
69888674 AD |
5777 | return err; |
5778 | } | |
5779 | ||
9a799d71 AK |
5780 | /** |
5781 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 5782 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5783 | * |
5784 | * Returns 0 on success, negative on failure | |
5785 | **/ | |
b6ec895e | 5786 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5787 | { |
b6ec895e | 5788 | struct device *dev = rx_ring->dev; |
de88eeeb | 5789 | int orig_node = dev_to_node(dev); |
ca8dfe25 | 5790 | int ring_node = -1; |
021230d4 | 5791 | int size; |
9a799d71 | 5792 | |
3a581073 | 5793 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
5794 | |
5795 | if (rx_ring->q_vector) | |
ca8dfe25 | 5796 | ring_node = rx_ring->q_vector->numa_node; |
de88eeeb | 5797 | |
ca8dfe25 | 5798 | rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); |
1a6c14a2 | 5799 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 5800 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
5801 | if (!rx_ring->rx_buffer_info) |
5802 | goto err; | |
9a799d71 | 5803 | |
827da44c JS |
5804 | u64_stats_init(&rx_ring->syncp); |
5805 | ||
9a799d71 | 5806 | /* Round up to nearest 4K */ |
3a581073 JB |
5807 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5808 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5809 | |
ca8dfe25 | 5810 | set_dev_node(dev, ring_node); |
de88eeeb AD |
5811 | rx_ring->desc = dma_alloc_coherent(dev, |
5812 | rx_ring->size, | |
5813 | &rx_ring->dma, | |
5814 | GFP_KERNEL); | |
5815 | set_dev_node(dev, orig_node); | |
5816 | if (!rx_ring->desc) | |
5817 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
5818 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
5819 | if (!rx_ring->desc) |
5820 | goto err; | |
9a799d71 | 5821 | |
3a581073 JB |
5822 | rx_ring->next_to_clean = 0; |
5823 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
5824 | |
5825 | return 0; | |
b6ec895e AD |
5826 | err: |
5827 | vfree(rx_ring->rx_buffer_info); | |
5828 | rx_ring->rx_buffer_info = NULL; | |
5829 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 5830 | return -ENOMEM; |
9a799d71 AK |
5831 | } |
5832 | ||
69888674 AD |
5833 | /** |
5834 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5835 | * @adapter: board private structure | |
5836 | * | |
5837 | * If this function returns with an error, then it's possible one or | |
5838 | * more of the rings is populated (while the rest are not). It is the | |
5839 | * callers duty to clean those orphaned rings. | |
5840 | * | |
5841 | * Return 0 on success, negative on failure | |
5842 | **/ | |
69888674 AD |
5843 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
5844 | { | |
5845 | int i, err = 0; | |
5846 | ||
5847 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 5848 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
5849 | if (!err) |
5850 | continue; | |
de3d5b94 | 5851 | |
396e799c | 5852 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
de3d5b94 | 5853 | goto err_setup_rx; |
69888674 AD |
5854 | } |
5855 | ||
7c8ae65a AD |
5856 | #ifdef IXGBE_FCOE |
5857 | err = ixgbe_setup_fcoe_ddp_resources(adapter); | |
5858 | if (!err) | |
5859 | #endif | |
5860 | return 0; | |
de3d5b94 AD |
5861 | err_setup_rx: |
5862 | /* rewind the index freeing the rings as we go */ | |
5863 | while (i--) | |
5864 | ixgbe_free_rx_resources(adapter->rx_ring[i]); | |
69888674 AD |
5865 | return err; |
5866 | } | |
5867 | ||
9a799d71 AK |
5868 | /** |
5869 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
5870 | * @tx_ring: Tx descriptor ring for a specific queue |
5871 | * | |
5872 | * Free all transmit software resources | |
5873 | **/ | |
b6ec895e | 5874 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5875 | { |
b6ec895e | 5876 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
5877 | |
5878 | vfree(tx_ring->tx_buffer_info); | |
5879 | tx_ring->tx_buffer_info = NULL; | |
5880 | ||
b6ec895e AD |
5881 | /* if not set, then don't free */ |
5882 | if (!tx_ring->desc) | |
5883 | return; | |
5884 | ||
5885 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
5886 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
5887 | |
5888 | tx_ring->desc = NULL; | |
5889 | } | |
5890 | ||
5891 | /** | |
5892 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
5893 | * @adapter: board private structure | |
5894 | * | |
5895 | * Free all transmit software resources | |
5896 | **/ | |
5897 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
5898 | { | |
5899 | int i; | |
5900 | ||
5901 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5902 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 5903 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
5904 | } |
5905 | ||
5906 | /** | |
b4617240 | 5907 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
5908 | * @rx_ring: ring to clean the resources from |
5909 | * | |
5910 | * Free all receive software resources | |
5911 | **/ | |
b6ec895e | 5912 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5913 | { |
b6ec895e | 5914 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
5915 | |
5916 | vfree(rx_ring->rx_buffer_info); | |
5917 | rx_ring->rx_buffer_info = NULL; | |
5918 | ||
b6ec895e AD |
5919 | /* if not set, then don't free */ |
5920 | if (!rx_ring->desc) | |
5921 | return; | |
5922 | ||
5923 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
5924 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
5925 | |
5926 | rx_ring->desc = NULL; | |
5927 | } | |
5928 | ||
5929 | /** | |
5930 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5931 | * @adapter: board private structure | |
5932 | * | |
5933 | * Free all receive software resources | |
5934 | **/ | |
5935 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5936 | { | |
5937 | int i; | |
5938 | ||
7c8ae65a AD |
5939 | #ifdef IXGBE_FCOE |
5940 | ixgbe_free_fcoe_ddp_resources(adapter); | |
5941 | ||
5942 | #endif | |
9a799d71 | 5943 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 5944 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 5945 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
5946 | } |
5947 | ||
9a799d71 AK |
5948 | /** |
5949 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5950 | * @netdev: network interface device structure | |
5951 | * @new_mtu: new value for maximum frame size | |
5952 | * | |
5953 | * Returns 0 on success, negative on failure | |
5954 | **/ | |
5955 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5956 | { | |
5957 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5958 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
5959 | ||
42c783c5 | 5960 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
5961 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
5962 | return -EINVAL; | |
5963 | ||
5964 | /* | |
872844dd AD |
5965 | * For 82599EB we cannot allow legacy VFs to enable their receive |
5966 | * paths when MTU greater than 1500 is configured. So display a | |
5967 | * warning that legacy VFs will be disabled. | |
655309e9 AD |
5968 | */ |
5969 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
5970 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
c560451c | 5971 | (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) |
872844dd | 5972 | e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); |
9a799d71 | 5973 | |
396e799c | 5974 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 5975 | |
021230d4 | 5976 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5977 | netdev->mtu = new_mtu; |
5978 | ||
d4f80882 AV |
5979 | if (netif_running(netdev)) |
5980 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5981 | |
5982 | return 0; | |
5983 | } | |
5984 | ||
5985 | /** | |
5986 | * ixgbe_open - Called when a network interface is made active | |
5987 | * @netdev: network interface device structure | |
5988 | * | |
5989 | * Returns 0 on success, negative value on failure | |
5990 | * | |
5991 | * The open entry point is called when a network interface is made | |
5992 | * active by the system (IFF_UP). At this point all resources needed | |
5993 | * for transmit and receive operations are allocated, the interrupt | |
5994 | * handler is registered with the OS, the watchdog timer is started, | |
5995 | * and the stack is notified that the interface is ready. | |
5996 | **/ | |
5997 | static int ixgbe_open(struct net_device *netdev) | |
5998 | { | |
5999 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
961fac88 | 6000 | struct ixgbe_hw *hw = &adapter->hw; |
2a47fa45 | 6001 | int err, queues; |
4bebfaa5 AK |
6002 | |
6003 | /* disallow open during test */ | |
6004 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
6005 | return -EBUSY; | |
9a799d71 | 6006 | |
54386467 JB |
6007 | netif_carrier_off(netdev); |
6008 | ||
9a799d71 AK |
6009 | /* allocate transmit descriptors */ |
6010 | err = ixgbe_setup_all_tx_resources(adapter); | |
6011 | if (err) | |
6012 | goto err_setup_tx; | |
6013 | ||
9a799d71 AK |
6014 | /* allocate receive descriptors */ |
6015 | err = ixgbe_setup_all_rx_resources(adapter); | |
6016 | if (err) | |
6017 | goto err_setup_rx; | |
6018 | ||
6019 | ixgbe_configure(adapter); | |
6020 | ||
021230d4 | 6021 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
6022 | if (err) |
6023 | goto err_req_irq; | |
6024 | ||
ac802f5d | 6025 | /* Notify the stack of the actual queue counts. */ |
2a47fa45 JF |
6026 | if (adapter->num_rx_pools > 1) |
6027 | queues = adapter->num_rx_queues_per_pool; | |
6028 | else | |
6029 | queues = adapter->num_tx_queues; | |
6030 | ||
6031 | err = netif_set_real_num_tx_queues(netdev, queues); | |
ac802f5d AD |
6032 | if (err) |
6033 | goto err_set_queues; | |
6034 | ||
2a47fa45 JF |
6035 | if (adapter->num_rx_pools > 1 && |
6036 | adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) | |
6037 | queues = IXGBE_MAX_L2A_QUEUES; | |
6038 | else | |
6039 | queues = adapter->num_rx_queues; | |
6040 | err = netif_set_real_num_rx_queues(netdev, queues); | |
ac802f5d AD |
6041 | if (err) |
6042 | goto err_set_queues; | |
6043 | ||
1a71ab24 | 6044 | ixgbe_ptp_init(adapter); |
1a71ab24 | 6045 | |
c7ccde0f | 6046 | ixgbe_up_complete(adapter); |
9a799d71 | 6047 | |
67359c3c MR |
6048 | ixgbe_clear_vxlan_port(adapter); |
6049 | #ifdef CONFIG_IXGBE_VXLAN | |
3f207800 | 6050 | vxlan_get_rx_port(netdev); |
3f207800 | 6051 | #endif |
67359c3c | 6052 | |
9a799d71 AK |
6053 | return 0; |
6054 | ||
ac802f5d AD |
6055 | err_set_queues: |
6056 | ixgbe_free_irq(adapter); | |
9a799d71 | 6057 | err_req_irq: |
a20a1199 | 6058 | ixgbe_free_all_rx_resources(adapter); |
961fac88 DS |
6059 | if (hw->phy.ops.set_phy_power && !adapter->wol) |
6060 | hw->phy.ops.set_phy_power(&adapter->hw, false); | |
de3d5b94 | 6061 | err_setup_rx: |
a20a1199 | 6062 | ixgbe_free_all_tx_resources(adapter); |
de3d5b94 | 6063 | err_setup_tx: |
9a799d71 AK |
6064 | ixgbe_reset(adapter); |
6065 | ||
6066 | return err; | |
6067 | } | |
6068 | ||
a0cccce2 JK |
6069 | static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) |
6070 | { | |
6071 | ixgbe_ptp_suspend(adapter); | |
6072 | ||
6ac74394 DS |
6073 | if (adapter->hw.phy.ops.enter_lplu) { |
6074 | adapter->hw.phy.reset_disable = true; | |
6075 | ixgbe_down(adapter); | |
6076 | adapter->hw.phy.ops.enter_lplu(&adapter->hw); | |
6077 | adapter->hw.phy.reset_disable = false; | |
6078 | } else { | |
6079 | ixgbe_down(adapter); | |
6080 | } | |
6081 | ||
a0cccce2 JK |
6082 | ixgbe_free_irq(adapter); |
6083 | ||
6084 | ixgbe_free_all_tx_resources(adapter); | |
6085 | ixgbe_free_all_rx_resources(adapter); | |
6086 | } | |
6087 | ||
9a799d71 AK |
6088 | /** |
6089 | * ixgbe_close - Disables a network interface | |
6090 | * @netdev: network interface device structure | |
6091 | * | |
6092 | * Returns 0, this is not allowed to fail | |
6093 | * | |
6094 | * The close entry point is called when an interface is de-activated | |
6095 | * by the OS. The hardware is still under the drivers control, but | |
6096 | * needs to be disabled. A global MAC reset is issued to stop the | |
6097 | * hardware, and all transmit and receive resources are freed. | |
6098 | **/ | |
6099 | static int ixgbe_close(struct net_device *netdev) | |
6100 | { | |
6101 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 | 6102 | |
1a71ab24 | 6103 | ixgbe_ptp_stop(adapter); |
1a71ab24 | 6104 | |
a0cccce2 | 6105 | ixgbe_close_suspend(adapter); |
9a799d71 | 6106 | |
e4911d57 AD |
6107 | ixgbe_fdir_filter_exit(adapter); |
6108 | ||
5eba3699 | 6109 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
6110 | |
6111 | return 0; | |
6112 | } | |
6113 | ||
b3c8b4ba AD |
6114 | #ifdef CONFIG_PM |
6115 | static int ixgbe_resume(struct pci_dev *pdev) | |
6116 | { | |
c60fbb00 AD |
6117 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6118 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
6119 | u32 err; |
6120 | ||
0391bbe3 | 6121 | adapter->hw.hw_addr = adapter->io_addr; |
b3c8b4ba AD |
6122 | pci_set_power_state(pdev, PCI_D0); |
6123 | pci_restore_state(pdev); | |
656ab817 DS |
6124 | /* |
6125 | * pci_restore_state clears dev->state_saved so call | |
6126 | * pci_save_state to restore it. | |
6127 | */ | |
6128 | pci_save_state(pdev); | |
9ce77666 | 6129 | |
6130 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 6131 | if (err) { |
849c4542 | 6132 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
6133 | return err; |
6134 | } | |
4e857c58 | 6135 | smp_mb__before_atomic(); |
41c62843 | 6136 | clear_bit(__IXGBE_DISABLED, &adapter->state); |
b3c8b4ba AD |
6137 | pci_set_master(pdev); |
6138 | ||
dd4d8ca6 | 6139 | pci_wake_from_d3(pdev, false); |
b3c8b4ba | 6140 | |
b3c8b4ba AD |
6141 | ixgbe_reset(adapter); |
6142 | ||
495dce12 WJP |
6143 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6144 | ||
ac802f5d AD |
6145 | rtnl_lock(); |
6146 | err = ixgbe_init_interrupt_scheme(adapter); | |
6147 | if (!err && netif_running(netdev)) | |
c60fbb00 | 6148 | err = ixgbe_open(netdev); |
ac802f5d AD |
6149 | |
6150 | rtnl_unlock(); | |
6151 | ||
6152 | if (err) | |
6153 | return err; | |
b3c8b4ba AD |
6154 | |
6155 | netif_device_attach(netdev); | |
6156 | ||
6157 | return 0; | |
6158 | } | |
b3c8b4ba | 6159 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
6160 | |
6161 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 6162 | { |
c60fbb00 AD |
6163 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6164 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
6165 | struct ixgbe_hw *hw = &adapter->hw; |
6166 | u32 ctrl, fctrl; | |
6167 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
6168 | #ifdef CONFIG_PM |
6169 | int retval = 0; | |
6170 | #endif | |
6171 | ||
6172 | netif_device_detach(netdev); | |
6173 | ||
499ab5cc | 6174 | rtnl_lock(); |
a0cccce2 JK |
6175 | if (netif_running(netdev)) |
6176 | ixgbe_close_suspend(adapter); | |
499ab5cc | 6177 | rtnl_unlock(); |
b3c8b4ba | 6178 | |
5f5ae6fc AD |
6179 | ixgbe_clear_interrupt_scheme(adapter); |
6180 | ||
b3c8b4ba AD |
6181 | #ifdef CONFIG_PM |
6182 | retval = pci_save_state(pdev); | |
6183 | if (retval) | |
6184 | return retval; | |
4df10466 | 6185 | |
b3c8b4ba | 6186 | #endif |
f4f1040a JK |
6187 | if (hw->mac.ops.stop_link_on_d3) |
6188 | hw->mac.ops.stop_link_on_d3(hw); | |
6189 | ||
e8e26350 PW |
6190 | if (wufc) { |
6191 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 6192 | |
ec74a471 ET |
6193 | /* enable the optics for 82599 SFP+ fiber as we can WoL */ |
6194 | if (hw->mac.ops.enable_tx_laser) | |
c509e754 DS |
6195 | hw->mac.ops.enable_tx_laser(hw); |
6196 | ||
e8e26350 PW |
6197 | /* turn on all-multi mode if wake on multicast is enabled */ |
6198 | if (wufc & IXGBE_WUFC_MC) { | |
6199 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
6200 | fctrl |= IXGBE_FCTRL_MPE; | |
6201 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
6202 | } | |
6203 | ||
6204 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
6205 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
6206 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
6207 | ||
6208 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
6209 | } else { | |
6210 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
6211 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
6212 | } | |
6213 | ||
bd508178 AD |
6214 | switch (hw->mac.type) { |
6215 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 6216 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
6217 | break; |
6218 | case ixgbe_mac_82599EB: | |
b93a2226 | 6219 | case ixgbe_mac_X540: |
9a75a1ac DS |
6220 | case ixgbe_mac_X550: |
6221 | case ixgbe_mac_X550EM_x: | |
bd508178 AD |
6222 | pci_wake_from_d3(pdev, !!wufc); |
6223 | break; | |
6224 | default: | |
6225 | break; | |
6226 | } | |
b3c8b4ba | 6227 | |
9d8d05ae | 6228 | *enable_wake = !!wufc; |
961fac88 DS |
6229 | if (hw->phy.ops.set_phy_power && !*enable_wake) |
6230 | hw->phy.ops.set_phy_power(hw, false); | |
9d8d05ae | 6231 | |
b3c8b4ba AD |
6232 | ixgbe_release_hw_control(adapter); |
6233 | ||
41c62843 MR |
6234 | if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) |
6235 | pci_disable_device(pdev); | |
b3c8b4ba | 6236 | |
9d8d05ae RW |
6237 | return 0; |
6238 | } | |
6239 | ||
6240 | #ifdef CONFIG_PM | |
6241 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
6242 | { | |
6243 | int retval; | |
6244 | bool wake; | |
6245 | ||
6246 | retval = __ixgbe_shutdown(pdev, &wake); | |
6247 | if (retval) | |
6248 | return retval; | |
6249 | ||
6250 | if (wake) { | |
6251 | pci_prepare_to_sleep(pdev); | |
6252 | } else { | |
6253 | pci_wake_from_d3(pdev, false); | |
6254 | pci_set_power_state(pdev, PCI_D3hot); | |
6255 | } | |
b3c8b4ba AD |
6256 | |
6257 | return 0; | |
6258 | } | |
9d8d05ae | 6259 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
6260 | |
6261 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
6262 | { | |
9d8d05ae RW |
6263 | bool wake; |
6264 | ||
6265 | __ixgbe_shutdown(pdev, &wake); | |
6266 | ||
6267 | if (system_state == SYSTEM_POWER_OFF) { | |
6268 | pci_wake_from_d3(pdev, wake); | |
6269 | pci_set_power_state(pdev, PCI_D3hot); | |
6270 | } | |
b3c8b4ba AD |
6271 | } |
6272 | ||
9a799d71 AK |
6273 | /** |
6274 | * ixgbe_update_stats - Update the board statistics counters. | |
6275 | * @adapter: board private structure | |
6276 | **/ | |
6277 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
6278 | { | |
2d86f139 | 6279 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 6280 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 6281 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
6282 | u64 total_mpc = 0; |
6283 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
6284 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
6285 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 6286 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
9a799d71 | 6287 | |
d08935c2 DS |
6288 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
6289 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6290 | return; | |
6291 | ||
94b982b2 | 6292 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 6293 | u64 rsc_count = 0; |
94b982b2 | 6294 | u64 rsc_flush = 0; |
94b982b2 | 6295 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
6296 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
6297 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
6298 | } |
6299 | adapter->rsc_total_count = rsc_count; | |
6300 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
6301 | } |
6302 | ||
5b7da515 AD |
6303 | for (i = 0; i < adapter->num_rx_queues; i++) { |
6304 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
6305 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
6306 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
6307 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 6308 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
6309 | bytes += rx_ring->stats.bytes; |
6310 | packets += rx_ring->stats.packets; | |
6311 | } | |
6312 | adapter->non_eop_descs = non_eop_descs; | |
6313 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
6314 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 6315 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
6316 | netdev->stats.rx_bytes = bytes; |
6317 | netdev->stats.rx_packets = packets; | |
6318 | ||
6319 | bytes = 0; | |
6320 | packets = 0; | |
7ca3bc58 | 6321 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
6322 | for (i = 0; i < adapter->num_tx_queues; i++) { |
6323 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
6324 | restart_queue += tx_ring->tx_stats.restart_queue; | |
6325 | tx_busy += tx_ring->tx_stats.tx_busy; | |
6326 | bytes += tx_ring->stats.bytes; | |
6327 | packets += tx_ring->stats.packets; | |
6328 | } | |
eb985f09 | 6329 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
6330 | adapter->tx_busy = tx_busy; |
6331 | netdev->stats.tx_bytes = bytes; | |
6332 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 6333 | |
7ca647bd | 6334 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
6335 | |
6336 | /* 8 register reads */ | |
6f11eef7 AV |
6337 | for (i = 0; i < 8; i++) { |
6338 | /* for packet buffers not used, the register should read 0 */ | |
6339 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
6340 | missed_rx += mpc; | |
7ca647bd JP |
6341 | hwstats->mpc[i] += mpc; |
6342 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
6343 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
6344 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
6345 | switch (hw->mac.type) { |
6346 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
6347 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
6348 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
6349 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
6350 | hwstats->pxonrxc[i] += |
6351 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
6352 | break; |
6353 | case ixgbe_mac_82599EB: | |
b93a2226 | 6354 | case ixgbe_mac_X540: |
9a75a1ac DS |
6355 | case ixgbe_mac_X550: |
6356 | case ixgbe_mac_X550EM_x: | |
bd508178 AD |
6357 | hwstats->pxonrxc[i] += |
6358 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
6359 | break; |
6360 | default: | |
6361 | break; | |
e8e26350 | 6362 | } |
6f11eef7 | 6363 | } |
1a70db4b ET |
6364 | |
6365 | /*16 register reads */ | |
6366 | for (i = 0; i < 16; i++) { | |
6367 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
6368 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
6369 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
9a75a1ac DS |
6370 | (hw->mac.type == ixgbe_mac_X540) || |
6371 | (hw->mac.type == ixgbe_mac_X550) || | |
6372 | (hw->mac.type == ixgbe_mac_X550EM_x)) { | |
1a70db4b ET |
6373 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); |
6374 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
6375 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
6376 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
6377 | } | |
6378 | } | |
6379 | ||
7ca647bd | 6380 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 6381 | /* work around hardware counting issue */ |
7ca647bd | 6382 | hwstats->gprc -= missed_rx; |
6f11eef7 | 6383 | |
c84d324c JF |
6384 | ixgbe_update_xoff_received(adapter); |
6385 | ||
6f11eef7 | 6386 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
6387 | switch (hw->mac.type) { |
6388 | case ixgbe_mac_82598EB: | |
6389 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
6390 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
6391 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
6392 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
6393 | break; | |
b93a2226 | 6394 | case ixgbe_mac_X540: |
9a75a1ac DS |
6395 | case ixgbe_mac_X550: |
6396 | case ixgbe_mac_X550EM_x: | |
6397 | /* OS2BMC stats are X540 and later */ | |
58f6bcf9 ET |
6398 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); |
6399 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
6400 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
6401 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
6402 | case ixgbe_mac_82599EB: | |
a4d4f629 AD |
6403 | for (i = 0; i < 16; i++) |
6404 | adapter->hw_rx_no_dma_resources += | |
6405 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
7ca647bd | 6406 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 6407 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 6408 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 6409 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 6410 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 6411 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 6412 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
6413 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
6414 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 6415 | #ifdef IXGBE_FCOE |
7ca647bd JP |
6416 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
6417 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
6418 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
6419 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
6420 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
6421 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc | 6422 | /* Add up per cpu counters for total ddp aloc fail */ |
5a1ee270 AD |
6423 | if (adapter->fcoe.ddp_pool) { |
6424 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
6425 | struct ixgbe_fcoe_ddp_pool *ddp_pool; | |
6426 | unsigned int cpu; | |
6427 | u64 noddp = 0, noddp_ext_buff = 0; | |
7b859ebc | 6428 | for_each_possible_cpu(cpu) { |
5a1ee270 AD |
6429 | ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); |
6430 | noddp += ddp_pool->noddp; | |
6431 | noddp_ext_buff += ddp_pool->noddp_ext_buff; | |
7b859ebc | 6432 | } |
5a1ee270 AD |
6433 | hwstats->fcoe_noddp = noddp; |
6434 | hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; | |
7b859ebc | 6435 | } |
6d45522c | 6436 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
6437 | break; |
6438 | default: | |
6439 | break; | |
e8e26350 | 6440 | } |
9a799d71 | 6441 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
6442 | hwstats->bprc += bprc; |
6443 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 6444 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
6445 | hwstats->mprc -= bprc; |
6446 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
6447 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
6448 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
6449 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
6450 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
6451 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
6452 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
6453 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 6454 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 6455 | hwstats->lxontxc += lxon; |
6f11eef7 | 6456 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 6457 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
6458 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
6459 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
6460 | /* |
6461 | * 82598 errata - tx of flow control packets is included in tx counters | |
6462 | */ | |
6463 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
6464 | hwstats->gptc -= xon_off_tot; |
6465 | hwstats->mptc -= xon_off_tot; | |
6466 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
6467 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
6468 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
6469 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
6470 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
6471 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6472 | hwstats->ptc64 -= xon_off_tot; | |
6473 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
6474 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
6475 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
6476 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
6477 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
6478 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
6479 | |
6480 | /* Fill out the OS statistics structure */ | |
7ca647bd | 6481 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
6482 | |
6483 | /* Rx Errors */ | |
7ca647bd | 6484 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 6485 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
6486 | netdev->stats.rx_length_errors = hwstats->rlec; |
6487 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 6488 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
6489 | } |
6490 | ||
6491 | /** | |
d034acf1 | 6492 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
49ce9c2c | 6493 | * @adapter: pointer to the device adapter structure |
9a799d71 | 6494 | **/ |
d034acf1 | 6495 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 6496 | { |
cf8280ee | 6497 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 6498 | int i; |
cf8280ee | 6499 | |
d034acf1 AD |
6500 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
6501 | return; | |
6502 | ||
6503 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 6504 | |
d034acf1 | 6505 | /* if interface is down do nothing */ |
fe49f04a | 6506 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
6507 | return; |
6508 | ||
6509 | /* do nothing if we are not using signature filters */ | |
6510 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
6511 | return; | |
6512 | ||
6513 | adapter->fdir_overflow++; | |
6514 | ||
93c52dd0 AD |
6515 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
6516 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6517 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
e7cf745b | 6518 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
6519 | /* re-enable flow director interrupts */ |
6520 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
6521 | } else { |
6522 | e_err(probe, "failed to finish FDIR re-initialization, " | |
6523 | "ignored adding FDIR ATR filters\n"); | |
6524 | } | |
93c52dd0 AD |
6525 | } |
6526 | ||
6527 | /** | |
6528 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
49ce9c2c | 6529 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
6530 | * |
6531 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 6532 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 6533 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 6534 | * determine if a hang has occurred. |
93c52dd0 AD |
6535 | */ |
6536 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 6537 | { |
cf8280ee | 6538 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
6539 | u64 eics = 0; |
6540 | int i; | |
cf8280ee | 6541 | |
09f40aed | 6542 | /* If we're down, removing or resetting, just bail */ |
93c52dd0 | 6543 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 6544 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
93c52dd0 AD |
6545 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
6546 | return; | |
22d5a71b | 6547 | |
93c52dd0 AD |
6548 | /* Force detection of hung controller */ |
6549 | if (netif_carrier_ok(adapter->netdev)) { | |
6550 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6551 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
6552 | } | |
22d5a71b | 6553 | |
fe49f04a AD |
6554 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
6555 | /* | |
6556 | * for legacy and MSI interrupts don't set any bits | |
6557 | * that are enabled for EIAM, because this operation | |
6558 | * would set *both* EIMS and EICS for any bit in EIAM | |
6559 | */ | |
6560 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
6561 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
6562 | } else { |
6563 | /* get one bit for every active tx/rx interrupt vector */ | |
49c7ffbe | 6564 | for (i = 0; i < adapter->num_q_vectors; i++) { |
93c52dd0 | 6565 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; |
efe3d3c8 | 6566 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
6567 | eics |= ((u64)1 << i); |
6568 | } | |
cf8280ee | 6569 | } |
9a799d71 | 6570 | |
93c52dd0 | 6571 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a | 6572 | ixgbe_irq_rearm_queues(adapter, eics); |
cf8280ee JB |
6573 | } |
6574 | ||
e8e26350 | 6575 | /** |
93c52dd0 | 6576 | * ixgbe_watchdog_update_link - update the link status |
49ce9c2c BH |
6577 | * @adapter: pointer to the device adapter structure |
6578 | * @link_speed: pointer to a u32 to store the link_speed | |
e8e26350 | 6579 | **/ |
93c52dd0 | 6580 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 6581 | { |
e8e26350 | 6582 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
6583 | u32 link_speed = adapter->link_speed; |
6584 | bool link_up = adapter->link_up; | |
041441d0 | 6585 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; |
e8e26350 | 6586 | |
93c52dd0 AD |
6587 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
6588 | return; | |
6589 | ||
6590 | if (hw->mac.ops.check_link) { | |
6591 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 6592 | } else { |
93c52dd0 AD |
6593 | /* always assume link is up, if no check link function */ |
6594 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
6595 | link_up = true; | |
c4cf55e5 | 6596 | } |
041441d0 AD |
6597 | |
6598 | if (adapter->ixgbe_ieee_pfc) | |
6599 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
6600 | ||
3ebe8fde | 6601 | if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { |
041441d0 | 6602 | hw->mac.ops.fc_enable(hw); |
3ebe8fde AD |
6603 | ixgbe_set_rx_drop_en(adapter); |
6604 | } | |
93c52dd0 AD |
6605 | |
6606 | if (link_up || | |
6607 | time_after(jiffies, (adapter->link_check_timeout + | |
6608 | IXGBE_TRY_LINK_TIMEOUT))) { | |
6609 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
6610 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
6611 | IXGBE_WRITE_FLUSH(hw); | |
6612 | } | |
6613 | ||
6614 | adapter->link_up = link_up; | |
6615 | adapter->link_speed = link_speed; | |
e8e26350 PW |
6616 | } |
6617 | ||
107d3018 AD |
6618 | static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) |
6619 | { | |
6620 | #ifdef CONFIG_IXGBE_DCB | |
6621 | struct net_device *netdev = adapter->netdev; | |
6622 | struct dcb_app app = { | |
6623 | .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, | |
6624 | .protocol = 0, | |
6625 | }; | |
6626 | u8 up = 0; | |
6627 | ||
6628 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) | |
6629 | up = dcb_ieee_getapp_mask(netdev, &app); | |
6630 | ||
6631 | adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; | |
6632 | #endif | |
6633 | } | |
6634 | ||
e8e26350 | 6635 | /** |
93c52dd0 AD |
6636 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
6637 | * print link up message | |
49ce9c2c | 6638 | * @adapter: pointer to the device adapter structure |
e8e26350 | 6639 | **/ |
93c52dd0 | 6640 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 6641 | { |
93c52dd0 | 6642 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 6643 | struct ixgbe_hw *hw = &adapter->hw; |
cdc04dcc ET |
6644 | struct net_device *upper; |
6645 | struct list_head *iter; | |
93c52dd0 | 6646 | u32 link_speed = adapter->link_speed; |
454adb00 | 6647 | const char *speed_str; |
93c52dd0 | 6648 | bool flow_rx, flow_tx; |
e8e26350 | 6649 | |
93c52dd0 AD |
6650 | /* only continue if link was previously down */ |
6651 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 6652 | return; |
63d6e1d8 | 6653 | |
93c52dd0 | 6654 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 6655 | |
93c52dd0 AD |
6656 | switch (hw->mac.type) { |
6657 | case ixgbe_mac_82598EB: { | |
6658 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
6659 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
6660 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
6661 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
6662 | } | |
6663 | break; | |
6664 | case ixgbe_mac_X540: | |
9a75a1ac DS |
6665 | case ixgbe_mac_X550: |
6666 | case ixgbe_mac_X550EM_x: | |
93c52dd0 AD |
6667 | case ixgbe_mac_82599EB: { |
6668 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
6669 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
6670 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
6671 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
6672 | } | |
6673 | break; | |
6674 | default: | |
6675 | flow_tx = false; | |
6676 | flow_rx = false; | |
6677 | break; | |
e8e26350 | 6678 | } |
3a6a4eda | 6679 | |
6cb562d6 JK |
6680 | adapter->last_rx_ptp_check = jiffies; |
6681 | ||
8fecf67c | 6682 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 6683 | ixgbe_ptp_start_cyclecounter(adapter); |
3a6a4eda | 6684 | |
454adb00 MR |
6685 | switch (link_speed) { |
6686 | case IXGBE_LINK_SPEED_10GB_FULL: | |
6687 | speed_str = "10 Gbps"; | |
6688 | break; | |
6689 | case IXGBE_LINK_SPEED_2_5GB_FULL: | |
6690 | speed_str = "2.5 Gbps"; | |
6691 | break; | |
6692 | case IXGBE_LINK_SPEED_1GB_FULL: | |
6693 | speed_str = "1 Gbps"; | |
6694 | break; | |
6695 | case IXGBE_LINK_SPEED_100_FULL: | |
6696 | speed_str = "100 Mbps"; | |
6697 | break; | |
6698 | default: | |
6699 | speed_str = "unknown speed"; | |
6700 | break; | |
6701 | } | |
6702 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, | |
93c52dd0 AD |
6703 | ((flow_rx && flow_tx) ? "RX/TX" : |
6704 | (flow_rx ? "RX" : | |
6705 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 6706 | |
93c52dd0 | 6707 | netif_carrier_on(netdev); |
93c52dd0 | 6708 | ixgbe_check_vf_rate_limit(adapter); |
befa2af7 | 6709 | |
cdc04dcc ET |
6710 | /* enable transmits */ |
6711 | netif_tx_wake_all_queues(adapter->netdev); | |
6712 | ||
6713 | /* enable any upper devices */ | |
6714 | rtnl_lock(); | |
6715 | netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { | |
6716 | if (netif_is_macvlan(upper)) { | |
6717 | struct macvlan_dev *vlan = netdev_priv(upper); | |
6718 | ||
6719 | if (vlan->fwd_priv) | |
6720 | netif_tx_wake_all_queues(upper); | |
6721 | } | |
6722 | } | |
6723 | rtnl_unlock(); | |
6724 | ||
107d3018 AD |
6725 | /* update the default user priority for VFs */ |
6726 | ixgbe_update_default_up(adapter); | |
6727 | ||
befa2af7 AD |
6728 | /* ping all the active vfs to let them know link has changed */ |
6729 | ixgbe_ping_all_vfs(adapter); | |
e8e26350 PW |
6730 | } |
6731 | ||
c4cf55e5 | 6732 | /** |
93c52dd0 AD |
6733 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
6734 | * print link down message | |
49ce9c2c | 6735 | * @adapter: pointer to the adapter structure |
c4cf55e5 | 6736 | **/ |
581330ba | 6737 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 6738 | { |
cf8280ee | 6739 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 6740 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 6741 | |
93c52dd0 AD |
6742 | adapter->link_up = false; |
6743 | adapter->link_speed = 0; | |
cf8280ee | 6744 | |
93c52dd0 AD |
6745 | /* only continue if link was up previously */ |
6746 | if (!netif_carrier_ok(netdev)) | |
6747 | return; | |
264857b8 | 6748 | |
93c52dd0 AD |
6749 | /* poll for SFP+ cable when link is down */ |
6750 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
6751 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 6752 | |
8fecf67c | 6753 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 6754 | ixgbe_ptp_start_cyclecounter(adapter); |
3a6a4eda | 6755 | |
93c52dd0 AD |
6756 | e_info(drv, "NIC Link is Down\n"); |
6757 | netif_carrier_off(netdev); | |
befa2af7 AD |
6758 | |
6759 | /* ping all the active vfs to let them know link has changed */ | |
6760 | ixgbe_ping_all_vfs(adapter); | |
93c52dd0 | 6761 | } |
e8e26350 | 6762 | |
07923c17 ET |
6763 | static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) |
6764 | { | |
6765 | int i; | |
6766 | ||
6767 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6768 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
6769 | ||
6770 | if (tx_ring->next_to_use != tx_ring->next_to_clean) | |
6771 | return true; | |
6772 | } | |
6773 | ||
6774 | return false; | |
6775 | } | |
6776 | ||
6777 | static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) | |
6778 | { | |
6779 | struct ixgbe_hw *hw = &adapter->hw; | |
6780 | struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; | |
6781 | u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); | |
6782 | ||
6783 | int i, j; | |
6784 | ||
6785 | if (!adapter->num_vfs) | |
6786 | return false; | |
6787 | ||
9a75a1ac DS |
6788 | /* resetting the PF is only needed for MAC before X550 */ |
6789 | if (hw->mac.type >= ixgbe_mac_X550) | |
6790 | return false; | |
6791 | ||
07923c17 ET |
6792 | for (i = 0; i < adapter->num_vfs; i++) { |
6793 | for (j = 0; j < q_per_pool; j++) { | |
6794 | u32 h, t; | |
6795 | ||
6796 | h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); | |
6797 | t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); | |
6798 | ||
6799 | if (h != t) | |
6800 | return true; | |
6801 | } | |
6802 | } | |
6803 | ||
6804 | return false; | |
6805 | } | |
6806 | ||
93c52dd0 AD |
6807 | /** |
6808 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
49ce9c2c | 6809 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
6810 | **/ |
6811 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
6812 | { | |
93c52dd0 | 6813 | if (!netif_carrier_ok(adapter->netdev)) { |
07923c17 ET |
6814 | if (ixgbe_ring_tx_pending(adapter) || |
6815 | ixgbe_vf_tx_pending(adapter)) { | |
bc59fcda NS |
6816 | /* We've lost link, so the controller stops DMA, |
6817 | * but we've got queued Tx work that's never going | |
6818 | * to get done, so reset controller to flush Tx. | |
6819 | * (Do the reset outside of interrupt context). | |
6820 | */ | |
12ff3f3b | 6821 | e_warn(drv, "initiating reset to clear Tx work after link loss\n"); |
c83c6cbd | 6822 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 6823 | } |
c4cf55e5 | 6824 | } |
c4cf55e5 PWJ |
6825 | } |
6826 | ||
9079e416 ET |
6827 | #ifdef CONFIG_PCI_IOV |
6828 | static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, | |
6829 | struct pci_dev *vfdev) | |
6830 | { | |
6831 | if (!pci_wait_for_pending_transaction(vfdev)) | |
6832 | e_dev_warn("Issuing VFLR with pending transactions\n"); | |
6833 | ||
6834 | e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); | |
6835 | pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); | |
6836 | ||
6837 | msleep(100); | |
6838 | } | |
6839 | ||
6840 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
6841 | { | |
6842 | struct ixgbe_hw *hw = &adapter->hw; | |
6843 | struct pci_dev *pdev = adapter->pdev; | |
988d1307 | 6844 | unsigned int vf; |
9079e416 | 6845 | u32 gpc; |
9079e416 ET |
6846 | |
6847 | if (!(netif_carrier_ok(adapter->netdev))) | |
6848 | return; | |
6849 | ||
6850 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
6851 | if (gpc) /* If incrementing then no need for the check below */ | |
6852 | return; | |
6853 | /* Check to see if a bad DMA write target from an errant or | |
6854 | * malicious VF has caused a PCIe error. If so then we can | |
6855 | * issue a VFLR to the offending VF(s) and then resume without | |
6856 | * requesting a full slot reset. | |
6857 | */ | |
6858 | ||
6859 | if (!pdev) | |
6860 | return; | |
6861 | ||
9079e416 | 6862 | /* check status reg for all VFs owned by this PF */ |
988d1307 MR |
6863 | for (vf = 0; vf < adapter->num_vfs; ++vf) { |
6864 | struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; | |
6865 | u16 status_reg; | |
9079e416 | 6866 | |
988d1307 MR |
6867 | if (!vfdev) |
6868 | continue; | |
6869 | pci_read_config_word(vfdev, PCI_STATUS, &status_reg); | |
6870 | if (status_reg != IXGBE_FAILED_READ_CFG_WORD && | |
6871 | status_reg & PCI_STATUS_REC_MASTER_ABORT) | |
6872 | ixgbe_issue_vf_flr(adapter, vfdev); | |
9079e416 ET |
6873 | } |
6874 | } | |
6875 | ||
a985b6c3 GR |
6876 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
6877 | { | |
6878 | u32 ssvpc; | |
6879 | ||
0584d999 GR |
6880 | /* Do not perform spoof check for 82598 or if not in IOV mode */ |
6881 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
6882 | adapter->num_vfs == 0) | |
a985b6c3 GR |
6883 | return; |
6884 | ||
6885 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
6886 | ||
6887 | /* | |
6888 | * ssvpc register is cleared on read, if zero then no | |
6889 | * spoofed packets in the last interval. | |
6890 | */ | |
6891 | if (!ssvpc) | |
6892 | return; | |
6893 | ||
d6ea0754 | 6894 | e_warn(drv, "%u Spoofed packets detected\n", ssvpc); |
a985b6c3 | 6895 | } |
9079e416 ET |
6896 | #else |
6897 | static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) | |
6898 | { | |
6899 | } | |
6900 | ||
6901 | static void | |
6902 | ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) | |
6903 | { | |
6904 | } | |
6905 | #endif /* CONFIG_PCI_IOV */ | |
6906 | ||
a985b6c3 | 6907 | |
93c52dd0 AD |
6908 | /** |
6909 | * ixgbe_watchdog_subtask - check and bring link up | |
49ce9c2c | 6910 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
6911 | **/ |
6912 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
6913 | { | |
09f40aed | 6914 | /* if interface is down, removing or resetting, do nothing */ |
7edebf9a | 6915 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 6916 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
7edebf9a | 6917 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
93c52dd0 AD |
6918 | return; |
6919 | ||
6920 | ixgbe_watchdog_update_link(adapter); | |
6921 | ||
6922 | if (adapter->link_up) | |
6923 | ixgbe_watchdog_link_is_up(adapter); | |
6924 | else | |
6925 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 6926 | |
9079e416 | 6927 | ixgbe_check_for_bad_vf(adapter); |
a985b6c3 | 6928 | ixgbe_spoof_check(adapter); |
9a799d71 | 6929 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
6930 | |
6931 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 6932 | } |
10eec955 | 6933 | |
cf8280ee | 6934 | /** |
7086400d | 6935 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
49ce9c2c | 6936 | * @adapter: the ixgbe adapter structure |
cf8280ee | 6937 | **/ |
7086400d | 6938 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 6939 | { |
cf8280ee | 6940 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 6941 | s32 err; |
cf8280ee | 6942 | |
7086400d AD |
6943 | /* not searching for SFP so there is nothing to do here */ |
6944 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
6945 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
6946 | return; | |
10eec955 | 6947 | |
58e7cd24 MR |
6948 | if (adapter->sfp_poll_time && |
6949 | time_after(adapter->sfp_poll_time, jiffies)) | |
6950 | return; /* If not yet time to poll for SFP */ | |
6951 | ||
7086400d AD |
6952 | /* someone else is in init, wait until next service event */ |
6953 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
6954 | return; | |
cf8280ee | 6955 | |
58e7cd24 MR |
6956 | adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; |
6957 | ||
7086400d AD |
6958 | err = hw->phy.ops.identify_sfp(hw); |
6959 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
6960 | goto sfp_out; | |
264857b8 | 6961 | |
7086400d AD |
6962 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
6963 | /* If no cable is present, then we need to reset | |
6964 | * the next time we find a good cable. */ | |
6965 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 6966 | } |
9a799d71 | 6967 | |
7086400d AD |
6968 | /* exit on error */ |
6969 | if (err) | |
6970 | goto sfp_out; | |
e8e26350 | 6971 | |
7086400d AD |
6972 | /* exit if reset not needed */ |
6973 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
6974 | goto sfp_out; | |
9a799d71 | 6975 | |
7086400d | 6976 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 6977 | |
7086400d AD |
6978 | /* |
6979 | * A module may be identified correctly, but the EEPROM may not have | |
6980 | * support for that module. setup_sfp() will fail in that case, so | |
6981 | * we should not allow that module to load. | |
6982 | */ | |
6983 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6984 | err = hw->phy.ops.reset(hw); | |
6985 | else | |
6986 | err = hw->mac.ops.setup_sfp(hw); | |
6987 | ||
6988 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
6989 | goto sfp_out; | |
6990 | ||
6991 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
6992 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
6993 | ||
6994 | sfp_out: | |
6995 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
6996 | ||
6997 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
6998 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
6999 | e_dev_err("failed to initialize because an unsupported " | |
7000 | "SFP+ module type was detected.\n"); | |
7001 | e_dev_err("Reload the driver after installing a " | |
7002 | "supported module.\n"); | |
7003 | unregister_netdev(adapter->netdev); | |
bc59fcda | 7004 | } |
7086400d | 7005 | } |
bc59fcda | 7006 | |
7086400d AD |
7007 | /** |
7008 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
49ce9c2c | 7009 | * @adapter: the ixgbe adapter structure |
7086400d AD |
7010 | **/ |
7011 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
7012 | { | |
7013 | struct ixgbe_hw *hw = &adapter->hw; | |
3d292265 JH |
7014 | u32 speed; |
7015 | bool autoneg = false; | |
7086400d AD |
7016 | |
7017 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
7018 | return; | |
7019 | ||
7020 | /* someone else is in init, wait until next service event */ | |
7021 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
7022 | return; | |
7023 | ||
7024 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
7025 | ||
3d292265 | 7026 | speed = hw->phy.autoneg_advertised; |
ed33ff66 | 7027 | if ((!speed) && (hw->mac.ops.get_link_capabilities)) { |
3d292265 | 7028 | hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); |
ed33ff66 ET |
7029 | |
7030 | /* setup the highest link when no autoneg */ | |
7031 | if (!autoneg) { | |
7032 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
7033 | speed = IXGBE_LINK_SPEED_10GB_FULL; | |
7034 | } | |
7035 | } | |
7036 | ||
7086400d | 7037 | if (hw->mac.ops.setup_link) |
fd0326f2 | 7038 | hw->mac.ops.setup_link(hw, speed, true); |
7086400d AD |
7039 | |
7040 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
7041 | adapter->link_check_timeout = jiffies; | |
7042 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
7043 | } | |
7044 | ||
7045 | /** | |
7046 | * ixgbe_service_timer - Timer Call-back | |
7047 | * @data: pointer to adapter cast into an unsigned long | |
7048 | **/ | |
7049 | static void ixgbe_service_timer(unsigned long data) | |
7050 | { | |
7051 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
7052 | unsigned long next_event_offset; | |
7053 | ||
6bb78cfb AD |
7054 | /* poll faster when waiting for link */ |
7055 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
7056 | next_event_offset = HZ / 10; | |
7057 | else | |
7058 | next_event_offset = HZ * 2; | |
83c61fa9 | 7059 | |
7086400d AD |
7060 | /* Reset the timer */ |
7061 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
7062 | ||
9079e416 | 7063 | ixgbe_service_event_schedule(adapter); |
7086400d AD |
7064 | } |
7065 | ||
597f22d6 DS |
7066 | static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) |
7067 | { | |
7068 | struct ixgbe_hw *hw = &adapter->hw; | |
7069 | u32 status; | |
7070 | ||
7071 | if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) | |
7072 | return; | |
7073 | ||
7074 | adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; | |
7075 | ||
7076 | if (!hw->phy.ops.handle_lasi) | |
7077 | return; | |
7078 | ||
7079 | status = hw->phy.ops.handle_lasi(&adapter->hw); | |
7080 | if (status != IXGBE_ERR_OVERTEMP) | |
7081 | return; | |
7082 | ||
7083 | e_crit(drv, "%s\n", ixgbe_overheat_msg); | |
7084 | } | |
7085 | ||
c83c6cbd AD |
7086 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
7087 | { | |
7088 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
7089 | return; | |
7090 | ||
7091 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
7092 | ||
09f40aed | 7093 | /* If we're already down, removing or resetting, just bail */ |
c83c6cbd | 7094 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 7095 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
c83c6cbd AD |
7096 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
7097 | return; | |
7098 | ||
7099 | ixgbe_dump(adapter); | |
7100 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
7101 | adapter->tx_timeout_count++; | |
7102 | ||
8f4c5c9f | 7103 | rtnl_lock(); |
c83c6cbd | 7104 | ixgbe_reinit_locked(adapter); |
8f4c5c9f | 7105 | rtnl_unlock(); |
c83c6cbd AD |
7106 | } |
7107 | ||
7086400d AD |
7108 | /** |
7109 | * ixgbe_service_task - manages and runs subtasks | |
7110 | * @work: pointer to work_struct containing our data | |
7111 | **/ | |
7112 | static void ixgbe_service_task(struct work_struct *work) | |
7113 | { | |
7114 | struct ixgbe_adapter *adapter = container_of(work, | |
7115 | struct ixgbe_adapter, | |
7116 | service_task); | |
b0483c8f MR |
7117 | if (ixgbe_removed(adapter->hw.hw_addr)) { |
7118 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
7119 | rtnl_lock(); | |
7120 | ixgbe_down(adapter); | |
7121 | rtnl_unlock(); | |
7122 | } | |
7123 | ixgbe_service_event_complete(adapter); | |
7124 | return; | |
7125 | } | |
67359c3c MR |
7126 | #ifdef CONFIG_IXGBE_VXLAN |
7127 | if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) { | |
7128 | adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED; | |
7129 | vxlan_get_rx_port(adapter->netdev); | |
7130 | } | |
7131 | #endif /* CONFIG_IXGBE_VXLAN */ | |
c83c6cbd | 7132 | ixgbe_reset_subtask(adapter); |
597f22d6 | 7133 | ixgbe_phy_interrupt_subtask(adapter); |
7086400d AD |
7134 | ixgbe_sfp_detection_subtask(adapter); |
7135 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 7136 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 7137 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 7138 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 7139 | ixgbe_check_hang_subtask(adapter); |
891dc082 | 7140 | |
8fecf67c | 7141 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { |
891dc082 JK |
7142 | ixgbe_ptp_overflow_check(adapter); |
7143 | ixgbe_ptp_rx_hang(adapter); | |
7144 | } | |
7086400d AD |
7145 | |
7146 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
7147 | } |
7148 | ||
fd0db0ed AD |
7149 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
7150 | struct ixgbe_tx_buffer *first, | |
244e27ad | 7151 | u8 *hdr_len) |
897ab156 | 7152 | { |
fd0db0ed | 7153 | struct sk_buff *skb = first->skb; |
897ab156 AD |
7154 | u32 vlan_macip_lens, type_tucmd; |
7155 | u32 mss_l4len_idx, l4len; | |
2049e1f6 | 7156 | int err; |
9a799d71 | 7157 | |
8f4fbb9b AD |
7158 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
7159 | return 0; | |
7160 | ||
897ab156 AD |
7161 | if (!skb_is_gso(skb)) |
7162 | return 0; | |
9a799d71 | 7163 | |
2049e1f6 FR |
7164 | err = skb_cow_head(skb, 0); |
7165 | if (err < 0) | |
7166 | return err; | |
9a799d71 | 7167 | |
897ab156 AD |
7168 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
7169 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
7170 | ||
a1108ffd | 7171 | if (first->protocol == htons(ETH_P_IP)) { |
897ab156 AD |
7172 | struct iphdr *iph = ip_hdr(skb); |
7173 | iph->tot_len = 0; | |
7174 | iph->check = 0; | |
7175 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
7176 | iph->daddr, 0, | |
7177 | IPPROTO_TCP, | |
7178 | 0); | |
7179 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
244e27ad AD |
7180 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
7181 | IXGBE_TX_FLAGS_CSUM | | |
7182 | IXGBE_TX_FLAGS_IPV4; | |
897ab156 AD |
7183 | } else if (skb_is_gso_v6(skb)) { |
7184 | ipv6_hdr(skb)->payload_len = 0; | |
7185 | tcp_hdr(skb)->check = | |
7186 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
7187 | &ipv6_hdr(skb)->daddr, | |
7188 | 0, IPPROTO_TCP, 0); | |
244e27ad AD |
7189 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
7190 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
7191 | } |
7192 | ||
091a6246 | 7193 | /* compute header lengths */ |
897ab156 AD |
7194 | l4len = tcp_hdrlen(skb); |
7195 | *hdr_len = skb_transport_offset(skb) + l4len; | |
7196 | ||
091a6246 AD |
7197 | /* update gso size and bytecount with header size */ |
7198 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
7199 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
7200 | ||
c44f5f51 | 7201 | /* mss_l4len_id: use 0 as index for TSO */ |
897ab156 AD |
7202 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; |
7203 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
897ab156 AD |
7204 | |
7205 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
7206 | vlan_macip_lens = skb_network_header_len(skb); | |
7207 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 7208 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
7209 | |
7210 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 7211 | mss_l4len_idx); |
897ab156 AD |
7212 | |
7213 | return 1; | |
7214 | } | |
7215 | ||
244e27ad AD |
7216 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
7217 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 7218 | { |
fd0db0ed | 7219 | struct sk_buff *skb = first->skb; |
897ab156 AD |
7220 | u32 vlan_macip_lens = 0; |
7221 | u32 mss_l4len_idx = 0; | |
7222 | u32 type_tucmd = 0; | |
7ca647bd | 7223 | |
897ab156 | 7224 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
472148c3 AD |
7225 | if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
7226 | !(first->tx_flags & IXGBE_TX_FLAGS_CC)) | |
7227 | return; | |
f467bc06 MR |
7228 | vlan_macip_lens = skb_network_offset(skb) << |
7229 | IXGBE_ADVTXD_MACLEN_SHIFT; | |
897ab156 AD |
7230 | } else { |
7231 | u8 l4_hdr = 0; | |
f467bc06 MR |
7232 | union { |
7233 | struct iphdr *ipv4; | |
7234 | struct ipv6hdr *ipv6; | |
7235 | u8 *raw; | |
7236 | } network_hdr; | |
7237 | union { | |
7238 | struct tcphdr *tcphdr; | |
7239 | u8 *raw; | |
7240 | } transport_hdr; | |
36a92d71 | 7241 | __be16 frag_off; |
f467bc06 MR |
7242 | |
7243 | if (skb->encapsulation) { | |
7244 | network_hdr.raw = skb_inner_network_header(skb); | |
7245 | transport_hdr.raw = skb_inner_transport_header(skb); | |
7246 | vlan_macip_lens = skb_inner_network_offset(skb) << | |
7247 | IXGBE_ADVTXD_MACLEN_SHIFT; | |
7248 | } else { | |
7249 | network_hdr.raw = skb_network_header(skb); | |
7250 | transport_hdr.raw = skb_transport_header(skb); | |
7251 | vlan_macip_lens = skb_network_offset(skb) << | |
7252 | IXGBE_ADVTXD_MACLEN_SHIFT; | |
7253 | } | |
7254 | ||
7255 | /* use first 4 bits to determine IP version */ | |
7256 | switch (network_hdr.ipv4->version) { | |
7257 | case IPVERSION: | |
7258 | vlan_macip_lens |= transport_hdr.raw - network_hdr.raw; | |
897ab156 | 7259 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; |
f467bc06 | 7260 | l4_hdr = network_hdr.ipv4->protocol; |
7ca647bd | 7261 | break; |
f467bc06 MR |
7262 | case 6: |
7263 | vlan_macip_lens |= transport_hdr.raw - network_hdr.raw; | |
7264 | l4_hdr = network_hdr.ipv6->nexthdr; | |
36a92d71 MR |
7265 | if (likely((transport_hdr.raw - network_hdr.raw) == |
7266 | sizeof(struct ipv6hdr))) | |
7267 | break; | |
7268 | ipv6_skip_exthdr(skb, network_hdr.raw - skb->data + | |
7269 | sizeof(struct ipv6hdr), | |
7270 | &l4_hdr, &frag_off); | |
7271 | if (unlikely(frag_off)) | |
7272 | l4_hdr = NEXTHDR_FRAGMENT; | |
897ab156 AD |
7273 | break; |
7274 | default: | |
36a92d71 | 7275 | break; |
7ca647bd | 7276 | } |
897ab156 AD |
7277 | |
7278 | switch (l4_hdr) { | |
7ca647bd | 7279 | case IPPROTO_TCP: |
897ab156 | 7280 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
f467bc06 | 7281 | mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) << |
897ab156 | 7282 | IXGBE_ADVTXD_L4LEN_SHIFT; |
7ca647bd JP |
7283 | break; |
7284 | case IPPROTO_SCTP: | |
897ab156 AD |
7285 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
7286 | mss_l4len_idx = sizeof(struct sctphdr) << | |
7287 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7288 | break; | |
7289 | case IPPROTO_UDP: | |
7290 | mss_l4len_idx = sizeof(struct udphdr) << | |
7291 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7292 | break; | |
7293 | default: | |
7294 | if (unlikely(net_ratelimit())) { | |
7295 | dev_warn(tx_ring->dev, | |
36a92d71 MR |
7296 | "partial checksum, version=%d, l4 proto=%x\n", |
7297 | network_hdr.ipv4->version, l4_hdr); | |
897ab156 | 7298 | } |
36a92d71 MR |
7299 | skb_checksum_help(skb); |
7300 | goto no_csum; | |
7ca647bd | 7301 | } |
244e27ad AD |
7302 | |
7303 | /* update TX checksum flag */ | |
7304 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7ca647bd JP |
7305 | } |
7306 | ||
36a92d71 | 7307 | no_csum: |
244e27ad | 7308 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
244e27ad | 7309 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 7310 | |
897ab156 AD |
7311 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
7312 | type_tucmd, mss_l4len_idx); | |
9a799d71 AK |
7313 | } |
7314 | ||
472148c3 AD |
7315 | #define IXGBE_SET_FLAG(_input, _flag, _result) \ |
7316 | ((_flag <= _result) ? \ | |
7317 | ((u32)(_input & _flag) * (_result / _flag)) : \ | |
7318 | ((u32)(_input & _flag) / (_flag / _result))) | |
7319 | ||
7320 | static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) | |
9a799d71 | 7321 | { |
d3d00239 | 7322 | /* set type for advanced descriptor with frame checksum insertion */ |
472148c3 AD |
7323 | u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | |
7324 | IXGBE_ADVTXD_DCMD_DEXT | | |
7325 | IXGBE_ADVTXD_DCMD_IFCS; | |
9a799d71 | 7326 | |
d3d00239 | 7327 | /* set HW vlan bit if vlan is present */ |
472148c3 AD |
7328 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, |
7329 | IXGBE_ADVTXD_DCMD_VLE); | |
3a6a4eda | 7330 | |
d3d00239 | 7331 | /* set segmentation enable bits for TSO/FSO */ |
472148c3 AD |
7332 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, |
7333 | IXGBE_ADVTXD_DCMD_TSE); | |
7334 | ||
7335 | /* set timestamp bit if present */ | |
7336 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, | |
7337 | IXGBE_ADVTXD_MAC_TSTAMP); | |
eacd73f7 | 7338 | |
62748b7b | 7339 | /* insert frame checksum */ |
472148c3 | 7340 | cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); |
62748b7b | 7341 | |
d3d00239 AD |
7342 | return cmd_type; |
7343 | } | |
9a799d71 | 7344 | |
729739b7 AD |
7345 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
7346 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 7347 | { |
472148c3 | 7348 | u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; |
9a799d71 | 7349 | |
d3d00239 | 7350 | /* enable L4 checksum for TSO and TX checksum offload */ |
472148c3 AD |
7351 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7352 | IXGBE_TX_FLAGS_CSUM, | |
7353 | IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 7354 | |
93f5b3c1 | 7355 | /* enble IPv4 checksum for TSO */ |
472148c3 AD |
7356 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7357 | IXGBE_TX_FLAGS_IPV4, | |
7358 | IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 7359 | |
7f9643fd AD |
7360 | /* |
7361 | * Check Context must be set if Tx switch is enabled, which it | |
7362 | * always is for case where virtual functions are running | |
7363 | */ | |
472148c3 AD |
7364 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7365 | IXGBE_TX_FLAGS_CC, | |
7366 | IXGBE_ADVTXD_CC); | |
7f9643fd | 7367 | |
472148c3 | 7368 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
d3d00239 | 7369 | } |
44df32c5 | 7370 | |
2367a173 DB |
7371 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
7372 | { | |
7373 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
7374 | ||
7375 | /* Herbert's original patch had: | |
7376 | * smp_mb__after_netif_stop_queue(); | |
7377 | * but since that doesn't exist yet, just open code it. | |
7378 | */ | |
7379 | smp_mb(); | |
7380 | ||
7381 | /* We need to check again in a case another CPU has just | |
7382 | * made room available. | |
7383 | */ | |
7384 | if (likely(ixgbe_desc_unused(tx_ring) < size)) | |
7385 | return -EBUSY; | |
7386 | ||
7387 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
7388 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
7389 | ++tx_ring->tx_stats.restart_queue; | |
7390 | return 0; | |
7391 | } | |
7392 | ||
7393 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) | |
7394 | { | |
7395 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) | |
7396 | return 0; | |
7397 | ||
7398 | return __ixgbe_maybe_stop_tx(tx_ring, size); | |
7399 | } | |
7400 | ||
d3d00239 AD |
7401 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
7402 | IXGBE_TXD_CMD_RS) | |
7403 | ||
7404 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 7405 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
7406 | const u8 hdr_len) |
7407 | { | |
fd0db0ed | 7408 | struct sk_buff *skb = first->skb; |
729739b7 | 7409 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 7410 | union ixgbe_adv_tx_desc *tx_desc; |
ec718254 AD |
7411 | struct skb_frag_struct *frag; |
7412 | dma_addr_t dma; | |
7413 | unsigned int data_len, size; | |
244e27ad | 7414 | u32 tx_flags = first->tx_flags; |
472148c3 | 7415 | u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); |
d3d00239 | 7416 | u16 i = tx_ring->next_to_use; |
d3d00239 | 7417 | |
729739b7 AD |
7418 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
7419 | ||
ec718254 AD |
7420 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); |
7421 | ||
7422 | size = skb_headlen(skb); | |
7423 | data_len = skb->data_len; | |
729739b7 | 7424 | |
d3d00239 AD |
7425 | #ifdef IXGBE_FCOE |
7426 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 7427 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
7428 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
7429 | data_len = 0; | |
729739b7 AD |
7430 | } else { |
7431 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
7432 | } |
7433 | } | |
44df32c5 | 7434 | |
d3d00239 | 7435 | #endif |
729739b7 | 7436 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
8ad494b0 | 7437 | |
ec718254 | 7438 | tx_buffer = first; |
9a799d71 | 7439 | |
ec718254 AD |
7440 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { |
7441 | if (dma_mapping_error(tx_ring->dev, dma)) | |
7442 | goto dma_error; | |
7443 | ||
7444 | /* record length, and DMA address */ | |
7445 | dma_unmap_len_set(tx_buffer, len, size); | |
7446 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
7447 | ||
7448 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
e5a43549 | 7449 | |
729739b7 | 7450 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 | 7451 | tx_desc->read.cmd_type_len = |
472148c3 | 7452 | cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); |
e5a43549 | 7453 | |
d3d00239 | 7454 | i++; |
729739b7 | 7455 | tx_desc++; |
d3d00239 | 7456 | if (i == tx_ring->count) { |
e4f74028 | 7457 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
7458 | i = 0; |
7459 | } | |
ec718254 | 7460 | tx_desc->read.olinfo_status = 0; |
729739b7 AD |
7461 | |
7462 | dma += IXGBE_MAX_DATA_PER_TXD; | |
7463 | size -= IXGBE_MAX_DATA_PER_TXD; | |
7464 | ||
7465 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
d3d00239 | 7466 | } |
e5a43549 | 7467 | |
729739b7 AD |
7468 | if (likely(!data_len)) |
7469 | break; | |
9a799d71 | 7470 | |
472148c3 | 7471 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); |
9a799d71 | 7472 | |
729739b7 AD |
7473 | i++; |
7474 | tx_desc++; | |
7475 | if (i == tx_ring->count) { | |
7476 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
7477 | i = 0; | |
7478 | } | |
ec718254 | 7479 | tx_desc->read.olinfo_status = 0; |
9a799d71 | 7480 | |
d3d00239 | 7481 | #ifdef IXGBE_FCOE |
9e903e08 | 7482 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 7483 | #else |
9e903e08 | 7484 | size = skb_frag_size(frag); |
d3d00239 AD |
7485 | #endif |
7486 | data_len -= size; | |
9a799d71 | 7487 | |
729739b7 AD |
7488 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
7489 | DMA_TO_DEVICE); | |
9a799d71 | 7490 | |
729739b7 | 7491 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
729739b7 | 7492 | } |
9a799d71 | 7493 | |
729739b7 | 7494 | /* write last descriptor with RS and EOP bits */ |
472148c3 AD |
7495 | cmd_type |= size | IXGBE_TXD_CMD; |
7496 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); | |
eacd73f7 | 7497 | |
091a6246 | 7498 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 7499 | |
d3d00239 AD |
7500 | /* set the timestamp */ |
7501 | first->time_stamp = jiffies; | |
9a799d71 AK |
7502 | |
7503 | /* | |
729739b7 AD |
7504 | * Force memory writes to complete before letting h/w know there |
7505 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
7506 | * memory model archs, such as IA-64). | |
7507 | * | |
7508 | * We also need this memory barrier to make certain all of the | |
7509 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
7510 | */ |
7511 | wmb(); | |
7512 | ||
d3d00239 AD |
7513 | /* set next_to_watch value indicating a packet is present */ |
7514 | first->next_to_watch = tx_desc; | |
7515 | ||
729739b7 AD |
7516 | i++; |
7517 | if (i == tx_ring->count) | |
7518 | i = 0; | |
7519 | ||
7520 | tx_ring->next_to_use = i; | |
7521 | ||
2367a173 DB |
7522 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); |
7523 | ||
7524 | if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { | |
ad435ec6 AD |
7525 | writel(i, tx_ring->tail); |
7526 | ||
7527 | /* we need this if more than one processor can write to our tail | |
7528 | * at a time, it synchronizes IO on IA64/Altix systems | |
7529 | */ | |
7530 | mmiowb(); | |
9c938cdd | 7531 | } |
2367a173 | 7532 | |
d3d00239 AD |
7533 | return; |
7534 | dma_error: | |
729739b7 | 7535 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
7536 | |
7537 | /* clear dma mappings for failed tx_buffer_info map */ | |
7538 | for (;;) { | |
729739b7 AD |
7539 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
7540 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
7541 | if (tx_buffer == first) | |
d3d00239 AD |
7542 | break; |
7543 | if (i == 0) | |
7544 | i = tx_ring->count; | |
7545 | i--; | |
7546 | } | |
7547 | ||
d3d00239 | 7548 | tx_ring->next_to_use = i; |
9a799d71 AK |
7549 | } |
7550 | ||
fd0db0ed | 7551 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 7552 | struct ixgbe_tx_buffer *first) |
69830529 AD |
7553 | { |
7554 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
7555 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
7556 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
7557 | union { | |
7558 | unsigned char *network; | |
7559 | struct iphdr *ipv4; | |
7560 | struct ipv6hdr *ipv6; | |
7561 | } hdr; | |
ee9e0f0b | 7562 | struct tcphdr *th; |
67359c3c MR |
7563 | struct sk_buff *skb; |
7564 | #ifdef CONFIG_IXGBE_VXLAN | |
7565 | u8 encap = false; | |
7566 | #endif /* CONFIG_IXGBE_VXLAN */ | |
905e4a41 | 7567 | __be16 vlan_id; |
c4cf55e5 | 7568 | |
69830529 AD |
7569 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
7570 | if (!q_vector) | |
7571 | return; | |
7572 | ||
7573 | /* do nothing if sampling is disabled */ | |
7574 | if (!ring->atr_sample_rate) | |
d3ead241 | 7575 | return; |
c4cf55e5 | 7576 | |
69830529 | 7577 | ring->atr_count++; |
c4cf55e5 | 7578 | |
69830529 | 7579 | /* snag network header to get L4 type and address */ |
67359c3c MR |
7580 | skb = first->skb; |
7581 | hdr.network = skb_network_header(skb); | |
e19dcdeb MR |
7582 | if (!skb->encapsulation) { |
7583 | th = tcp_hdr(skb); | |
7584 | } else { | |
67359c3c MR |
7585 | #ifdef CONFIG_IXGBE_VXLAN |
7586 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
69830529 | 7587 | |
67359c3c MR |
7588 | if (!adapter->vxlan_port) |
7589 | return; | |
7590 | if (first->protocol != htons(ETH_P_IP) || | |
7591 | hdr.ipv4->version != IPVERSION || | |
7592 | hdr.ipv4->protocol != IPPROTO_UDP) { | |
7593 | return; | |
7594 | } | |
7595 | if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port) | |
7596 | return; | |
7597 | encap = true; | |
7598 | hdr.network = skb_inner_network_header(skb); | |
7599 | th = inner_tcp_hdr(skb); | |
7600 | #else | |
69830529 | 7601 | return; |
67359c3c | 7602 | #endif /* CONFIG_IXGBE_VXLAN */ |
e19dcdeb MR |
7603 | } |
7604 | ||
7605 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
7606 | switch (hdr.ipv4->version) { | |
7607 | case IPVERSION: | |
7608 | if (hdr.ipv4->protocol != IPPROTO_TCP) | |
67359c3c | 7609 | return; |
e19dcdeb MR |
7610 | break; |
7611 | case 6: | |
7612 | if (likely((unsigned char *)th - hdr.network == | |
7613 | sizeof(struct ipv6hdr))) { | |
7614 | if (hdr.ipv6->nexthdr != IPPROTO_TCP) | |
7615 | return; | |
7616 | } else { | |
7617 | __be16 frag_off; | |
7618 | u8 l4_hdr; | |
7619 | ||
7620 | ipv6_skip_exthdr(skb, hdr.network - skb->data + | |
7621 | sizeof(struct ipv6hdr), | |
7622 | &l4_hdr, &frag_off); | |
7623 | if (unlikely(frag_off)) | |
7624 | return; | |
7625 | if (l4_hdr != IPPROTO_TCP) | |
7626 | return; | |
7627 | } | |
7628 | break; | |
7629 | default: | |
7630 | return; | |
67359c3c | 7631 | } |
c4cf55e5 | 7632 | |
66f32a8b AD |
7633 | /* skip this packet since it is invalid or the socket is closing */ |
7634 | if (!th || th->fin) | |
69830529 AD |
7635 | return; |
7636 | ||
7637 | /* sample on all syn packets or once every atr sample count */ | |
7638 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
7639 | return; | |
7640 | ||
7641 | /* reset sample count */ | |
7642 | ring->atr_count = 0; | |
7643 | ||
244e27ad | 7644 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
7645 | |
7646 | /* | |
7647 | * src and dst are inverted, think how the receiver sees them | |
7648 | * | |
7649 | * The input is broken into two sections, a non-compressed section | |
7650 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
7651 | * is XORed together and stored in the compressed dword. | |
7652 | */ | |
7653 | input.formatted.vlan_id = vlan_id; | |
7654 | ||
7655 | /* | |
7656 | * since src port and flex bytes occupy the same word XOR them together | |
7657 | * and write the value to source port portion of compressed dword | |
7658 | */ | |
244e27ad | 7659 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
a1108ffd | 7660 | common.port.src ^= th->dest ^ htons(ETH_P_8021Q); |
69830529 | 7661 | else |
244e27ad | 7662 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
7663 | common.port.dst ^= th->source; |
7664 | ||
e19dcdeb MR |
7665 | switch (hdr.ipv4->version) { |
7666 | case IPVERSION: | |
69830529 AD |
7667 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
7668 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
e19dcdeb MR |
7669 | break; |
7670 | case 6: | |
69830529 AD |
7671 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; |
7672 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
7673 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
7674 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
7675 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
7676 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
7677 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
7678 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
7679 | hdr.ipv6->daddr.s6_addr32[3]; | |
e19dcdeb MR |
7680 | break; |
7681 | default: | |
7682 | break; | |
69830529 | 7683 | } |
c4cf55e5 | 7684 | |
67359c3c MR |
7685 | #ifdef CONFIG_IXGBE_VXLAN |
7686 | if (encap) | |
7687 | input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; | |
7688 | #endif /* CONFIG_IXGBE_VXLAN */ | |
7689 | ||
c4cf55e5 | 7690 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ |
69830529 AD |
7691 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
7692 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
7693 | } |
7694 | ||
f663dd9a | 7695 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 7696 | void *accel_priv, select_queue_fallback_t fallback) |
09a3b1f8 | 7697 | { |
f663dd9a JW |
7698 | struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; |
7699 | #ifdef IXGBE_FCOE | |
97488bd1 AD |
7700 | struct ixgbe_adapter *adapter; |
7701 | struct ixgbe_ring_feature *f; | |
7702 | int txq; | |
f663dd9a JW |
7703 | #endif |
7704 | ||
7705 | if (fwd_adapter) | |
7706 | return skb->queue_mapping + fwd_adapter->tx_base_queue; | |
7707 | ||
7708 | #ifdef IXGBE_FCOE | |
5e09a105 | 7709 | |
97488bd1 AD |
7710 | /* |
7711 | * only execute the code below if protocol is FCoE | |
7712 | * or FIP and we have FCoE enabled on the adapter | |
7713 | */ | |
7714 | switch (vlan_get_protocol(skb)) { | |
a1108ffd JP |
7715 | case htons(ETH_P_FCOE): |
7716 | case htons(ETH_P_FIP): | |
97488bd1 | 7717 | adapter = netdev_priv(dev); |
c087663e | 7718 | |
97488bd1 AD |
7719 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) |
7720 | break; | |
7721 | default: | |
99932d4f | 7722 | return fallback(dev, skb); |
97488bd1 | 7723 | } |
c087663e | 7724 | |
97488bd1 | 7725 | f = &adapter->ring_feature[RING_F_FCOE]; |
c087663e | 7726 | |
97488bd1 AD |
7727 | txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
7728 | smp_processor_id(); | |
56075a98 | 7729 | |
97488bd1 AD |
7730 | while (txq >= f->indices) |
7731 | txq -= f->indices; | |
c4cf55e5 | 7732 | |
97488bd1 | 7733 | return txq + f->offset; |
f663dd9a | 7734 | #else |
99932d4f | 7735 | return fallback(dev, skb); |
f663dd9a | 7736 | #endif |
09a3b1f8 SH |
7737 | } |
7738 | ||
fc77dc3c | 7739 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
7740 | struct ixgbe_adapter *adapter, |
7741 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 7742 | { |
d3d00239 | 7743 | struct ixgbe_tx_buffer *first; |
5f715823 | 7744 | int tso; |
d3d00239 | 7745 | u32 tx_flags = 0; |
a535c30e | 7746 | unsigned short f; |
a535c30e | 7747 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 7748 | __be16 protocol = skb->protocol; |
63544e9c | 7749 | u8 hdr_len = 0; |
5e09a105 | 7750 | |
a535c30e AD |
7751 | /* |
7752 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 7753 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
7754 | * + 2 desc gap to keep tail from touching head, |
7755 | * + 1 desc for context descriptor, | |
7756 | * otherwise try next time | |
7757 | */ | |
a535c30e AD |
7758 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) |
7759 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
7f66162b | 7760 | |
a535c30e AD |
7761 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { |
7762 | tx_ring->tx_stats.tx_busy++; | |
7763 | return NETDEV_TX_BUSY; | |
7764 | } | |
7765 | ||
fd0db0ed AD |
7766 | /* record the location of the first descriptor for this packet */ |
7767 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
7768 | first->skb = skb; | |
091a6246 AD |
7769 | first->bytecount = skb->len; |
7770 | first->gso_segs = 1; | |
fd0db0ed | 7771 | |
66f32a8b | 7772 | /* if we have a HW VLAN tag being added default to the HW one */ |
df8a39de JP |
7773 | if (skb_vlan_tag_present(skb)) { |
7774 | tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
7775 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; |
7776 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
a1108ffd | 7777 | } else if (protocol == htons(ETH_P_8021Q)) { |
66f32a8b AD |
7778 | struct vlan_hdr *vhdr, _vhdr; |
7779 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
7780 | if (!vhdr) | |
7781 | goto out_drop; | |
7782 | ||
9e0c5648 AD |
7783 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
7784 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
7785 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
7786 | } | |
0213668f | 7787 | protocol = vlan_get_protocol(skb); |
66f32a8b | 7788 | |
d5234933 MR |
7789 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
7790 | adapter->ptp_clock && | |
7791 | !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, | |
7792 | &adapter->state)) { | |
3a6a4eda JK |
7793 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
7794 | tx_flags |= IXGBE_TX_FLAGS_TSTAMP; | |
891dc082 JK |
7795 | |
7796 | /* schedule check for Tx timestamp */ | |
7797 | adapter->ptp_tx_skb = skb_get(skb); | |
7798 | adapter->ptp_tx_start = jiffies; | |
7799 | schedule_work(&adapter->ptp_tx_work); | |
3a6a4eda | 7800 | } |
3a6a4eda | 7801 | |
ff29a86e JK |
7802 | skb_tx_timestamp(skb); |
7803 | ||
9e0c5648 AD |
7804 | #ifdef CONFIG_PCI_IOV |
7805 | /* | |
7806 | * Use the l2switch_enable flag - would be false if the DMA | |
7807 | * Tx switch had been disabled. | |
7808 | */ | |
7809 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
472148c3 | 7810 | tx_flags |= IXGBE_TX_FLAGS_CC; |
9e0c5648 AD |
7811 | |
7812 | #endif | |
32701dc2 | 7813 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 7814 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
7815 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
7816 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 7817 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
7818 | tx_flags |= (skb->priority & 0x7) << |
7819 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
7820 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
7821 | struct vlan_ethhdr *vhdr; | |
2049e1f6 FR |
7822 | |
7823 | if (skb_cow_head(skb, 0)) | |
66f32a8b AD |
7824 | goto out_drop; |
7825 | vhdr = (struct vlan_ethhdr *)skb->data; | |
7826 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
7827 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
7828 | } else { | |
7829 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 7830 | } |
9a799d71 | 7831 | } |
eacd73f7 | 7832 | |
244e27ad AD |
7833 | /* record initial flags and protocol */ |
7834 | first->tx_flags = tx_flags; | |
7835 | first->protocol = protocol; | |
7836 | ||
eacd73f7 | 7837 | #ifdef IXGBE_FCOE |
66f32a8b | 7838 | /* setup tx offload for FCoE */ |
a1108ffd | 7839 | if ((protocol == htons(ETH_P_FCOE)) && |
a58915c7 | 7840 | (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { |
244e27ad | 7841 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
7842 | if (tso < 0) |
7843 | goto out_drop; | |
9a799d71 | 7844 | |
66f32a8b | 7845 | goto xmit_fcoe; |
eacd73f7 | 7846 | } |
9a799d71 | 7847 | |
66f32a8b | 7848 | #endif /* IXGBE_FCOE */ |
244e27ad | 7849 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 7850 | if (tso < 0) |
897ab156 | 7851 | goto out_drop; |
244e27ad AD |
7852 | else if (!tso) |
7853 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
7854 | |
7855 | /* add the ATR filter if ATR is on */ | |
7856 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 7857 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
7858 | |
7859 | #ifdef IXGBE_FCOE | |
7860 | xmit_fcoe: | |
7861 | #endif /* IXGBE_FCOE */ | |
244e27ad | 7862 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 | 7863 | |
9a799d71 | 7864 | return NETDEV_TX_OK; |
897ab156 AD |
7865 | |
7866 | out_drop: | |
fd0db0ed AD |
7867 | dev_kfree_skb_any(first->skb); |
7868 | first->skb = NULL; | |
7869 | ||
897ab156 | 7870 | return NETDEV_TX_OK; |
9a799d71 AK |
7871 | } |
7872 | ||
2a47fa45 JF |
7873 | static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, |
7874 | struct net_device *netdev, | |
7875 | struct ixgbe_ring *ring) | |
84418e3b AD |
7876 | { |
7877 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7878 | struct ixgbe_ring *tx_ring; | |
7879 | ||
a50c29dd AD |
7880 | /* |
7881 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
7882 | * in order to meet this minimum size requirement. | |
7883 | */ | |
a94d9e22 AD |
7884 | if (skb_put_padto(skb, 17)) |
7885 | return NETDEV_TX_OK; | |
a50c29dd | 7886 | |
2a47fa45 JF |
7887 | tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; |
7888 | ||
fc77dc3c | 7889 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
7890 | } |
7891 | ||
2a47fa45 JF |
7892 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
7893 | struct net_device *netdev) | |
7894 | { | |
7895 | return __ixgbe_xmit_frame(skb, netdev, NULL); | |
7896 | } | |
7897 | ||
9a799d71 AK |
7898 | /** |
7899 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
7900 | * @netdev: network interface device structure | |
7901 | * @p: pointer to an address structure | |
7902 | * | |
7903 | * Returns 0 on success, negative on failure | |
7904 | **/ | |
7905 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
7906 | { | |
7907 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 7908 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
7909 | struct sockaddr *addr = p; |
7910 | ||
7911 | if (!is_valid_ether_addr(addr->sa_data)) | |
7912 | return -EADDRNOTAVAIL; | |
7913 | ||
7914 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 7915 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 7916 | |
c9f53e63 AD |
7917 | ixgbe_mac_set_default_filter(adapter); |
7918 | ||
7919 | return 0; | |
9a799d71 AK |
7920 | } |
7921 | ||
6b73e10d BH |
7922 | static int |
7923 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
7924 | { | |
7925 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7926 | struct ixgbe_hw *hw = &adapter->hw; | |
7927 | u16 value; | |
7928 | int rc; | |
7929 | ||
7930 | if (prtad != hw->phy.mdio.prtad) | |
7931 | return -EINVAL; | |
7932 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
7933 | if (!rc) | |
7934 | rc = value; | |
7935 | return rc; | |
7936 | } | |
7937 | ||
7938 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
7939 | u16 addr, u16 value) | |
7940 | { | |
7941 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7942 | struct ixgbe_hw *hw = &adapter->hw; | |
7943 | ||
7944 | if (prtad != hw->phy.mdio.prtad) | |
7945 | return -EINVAL; | |
7946 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
7947 | } | |
7948 | ||
7949 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
7950 | { | |
7951 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7952 | ||
3a6a4eda | 7953 | switch (cmd) { |
3a6a4eda | 7954 | case SIOCSHWTSTAMP: |
93501d48 JK |
7955 | return ixgbe_ptp_set_ts_config(adapter, req); |
7956 | case SIOCGHWTSTAMP: | |
7957 | return ixgbe_ptp_get_ts_config(adapter, req); | |
3a6a4eda JK |
7958 | default: |
7959 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
7960 | } | |
6b73e10d BH |
7961 | } |
7962 | ||
0365e6e4 PW |
7963 | /** |
7964 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 7965 | * netdev->dev_addrs |
0365e6e4 PW |
7966 | * @netdev: network interface device structure |
7967 | * | |
7968 | * Returns non-zero on failure | |
7969 | **/ | |
7970 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
7971 | { | |
7972 | int err = 0; | |
7973 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7fa7c9dc | 7974 | struct ixgbe_hw *hw = &adapter->hw; |
0365e6e4 | 7975 | |
7fa7c9dc | 7976 | if (is_valid_ether_addr(hw->mac.san_addr)) { |
0365e6e4 | 7977 | rtnl_lock(); |
7fa7c9dc | 7978 | err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); |
0365e6e4 | 7979 | rtnl_unlock(); |
7fa7c9dc AD |
7980 | |
7981 | /* update SAN MAC vmdq pool selection */ | |
7982 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
0365e6e4 PW |
7983 | } |
7984 | return err; | |
7985 | } | |
7986 | ||
7987 | /** | |
7988 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 7989 | * netdev->dev_addrs |
0365e6e4 PW |
7990 | * @netdev: network interface device structure |
7991 | * | |
7992 | * Returns non-zero on failure | |
7993 | **/ | |
7994 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
7995 | { | |
7996 | int err = 0; | |
7997 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7998 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
7999 | ||
8000 | if (is_valid_ether_addr(mac->san_addr)) { | |
8001 | rtnl_lock(); | |
8002 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
8003 | rtnl_unlock(); | |
8004 | } | |
8005 | return err; | |
8006 | } | |
8007 | ||
9a799d71 AK |
8008 | #ifdef CONFIG_NET_POLL_CONTROLLER |
8009 | /* | |
8010 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
8011 | * without having to re-enable interrupts. It's not called while | |
8012 | * the interrupt routine is executing. | |
8013 | */ | |
8014 | static void ixgbe_netpoll(struct net_device *netdev) | |
8015 | { | |
8016 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 8017 | int i; |
9a799d71 | 8018 | |
1a647bd2 AD |
8019 | /* if interface is down do nothing */ |
8020 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
8021 | return; | |
8022 | ||
856f606e AD |
8023 | /* loop through and schedule all active queues */ |
8024 | for (i = 0; i < adapter->num_q_vectors; i++) | |
8025 | ixgbe_msix_clean_rings(0, adapter->q_vector[i]); | |
9a799d71 | 8026 | } |
9a799d71 | 8027 | |
581330ba | 8028 | #endif |
de1036b1 ED |
8029 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
8030 | struct rtnl_link_stats64 *stats) | |
8031 | { | |
8032 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8033 | int i; | |
8034 | ||
1a51502b | 8035 | rcu_read_lock(); |
de1036b1 | 8036 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 8037 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
8038 | u64 bytes, packets; |
8039 | unsigned int start; | |
8040 | ||
1a51502b ED |
8041 | if (ring) { |
8042 | do { | |
57a7744e | 8043 | start = u64_stats_fetch_begin_irq(&ring->syncp); |
1a51502b ED |
8044 | packets = ring->stats.packets; |
8045 | bytes = ring->stats.bytes; | |
57a7744e | 8046 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); |
1a51502b ED |
8047 | stats->rx_packets += packets; |
8048 | stats->rx_bytes += bytes; | |
8049 | } | |
de1036b1 | 8050 | } |
1ac9ad13 ED |
8051 | |
8052 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
8053 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
8054 | u64 bytes, packets; | |
8055 | unsigned int start; | |
8056 | ||
8057 | if (ring) { | |
8058 | do { | |
57a7744e | 8059 | start = u64_stats_fetch_begin_irq(&ring->syncp); |
1ac9ad13 ED |
8060 | packets = ring->stats.packets; |
8061 | bytes = ring->stats.bytes; | |
57a7744e | 8062 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); |
1ac9ad13 ED |
8063 | stats->tx_packets += packets; |
8064 | stats->tx_bytes += bytes; | |
8065 | } | |
8066 | } | |
1a51502b | 8067 | rcu_read_unlock(); |
de1036b1 ED |
8068 | /* following stats updated by ixgbe_watchdog_task() */ |
8069 | stats->multicast = netdev->stats.multicast; | |
8070 | stats->rx_errors = netdev->stats.rx_errors; | |
8071 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
8072 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
8073 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
8074 | return stats; | |
8075 | } | |
8076 | ||
8af3c33f | 8077 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c BH |
8078 | /** |
8079 | * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. | |
8080 | * @adapter: pointer to ixgbe_adapter | |
8b1c0b24 JF |
8081 | * @tc: number of traffic classes currently enabled |
8082 | * | |
8083 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
8084 | * 802.1Q priority maps to a packet buffer that exists. | |
8085 | */ | |
8086 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
8087 | { | |
8088 | struct ixgbe_hw *hw = &adapter->hw; | |
8089 | u32 reg, rsave; | |
8090 | int i; | |
8091 | ||
8092 | /* 82598 have a static priority to TC mapping that can not | |
8093 | * be changed so no validation is needed. | |
8094 | */ | |
8095 | if (hw->mac.type == ixgbe_mac_82598EB) | |
8096 | return; | |
8097 | ||
8098 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
8099 | rsave = reg; | |
8100 | ||
8101 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
8102 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
8103 | ||
8104 | /* If up2tc is out of bounds default to zero */ | |
8105 | if (up2tc > tc) | |
8106 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
8107 | } | |
8108 | ||
8109 | if (reg != rsave) | |
8110 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
8111 | ||
8112 | return; | |
8113 | } | |
8114 | ||
02debdc9 AD |
8115 | /** |
8116 | * ixgbe_set_prio_tc_map - Configure netdev prio tc map | |
8117 | * @adapter: Pointer to adapter struct | |
8118 | * | |
8119 | * Populate the netdev user priority to tc map | |
8120 | */ | |
8121 | static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) | |
8122 | { | |
8123 | struct net_device *dev = adapter->netdev; | |
8124 | struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; | |
8125 | struct ieee_ets *ets = adapter->ixgbe_ieee_ets; | |
8126 | u8 prio; | |
8127 | ||
8128 | for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { | |
8129 | u8 tc = 0; | |
8130 | ||
8131 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) | |
8132 | tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); | |
8133 | else if (ets) | |
8134 | tc = ets->prio_tc[prio]; | |
8135 | ||
8136 | netdev_set_prio_tc_map(dev, prio, tc); | |
8137 | } | |
8138 | } | |
8139 | ||
cca73c59 | 8140 | #endif /* CONFIG_IXGBE_DCB */ |
49ce9c2c BH |
8141 | /** |
8142 | * ixgbe_setup_tc - configure net_device for multiple traffic classes | |
8b1c0b24 JF |
8143 | * |
8144 | * @netdev: net device to configure | |
8145 | * @tc: number of traffic classes to enable | |
8146 | */ | |
8147 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
8148 | { | |
8b1c0b24 JF |
8149 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
8150 | struct ixgbe_hw *hw = &adapter->hw; | |
2a47fa45 | 8151 | bool pools; |
8b1c0b24 | 8152 | |
8b1c0b24 | 8153 | /* Hardware supports up to 8 traffic classes */ |
7e3f5c88 ET |
8154 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) |
8155 | return -EINVAL; | |
8156 | ||
8157 | if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) | |
8b1c0b24 JF |
8158 | return -EINVAL; |
8159 | ||
2a47fa45 JF |
8160 | pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); |
8161 | if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) | |
8162 | return -EBUSY; | |
8163 | ||
8b1c0b24 | 8164 | /* Hardware has to reinitialize queues and interrupts to |
52f33af8 | 8165 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
8166 | * hardware is not flexible enough to do this dynamically. |
8167 | */ | |
8168 | if (netif_running(dev)) | |
8169 | ixgbe_close(dev); | |
bf4d67d9 AD |
8170 | else |
8171 | ixgbe_reset(adapter); | |
8172 | ||
8b1c0b24 JF |
8173 | ixgbe_clear_interrupt_scheme(adapter); |
8174 | ||
cca73c59 | 8175 | #ifdef CONFIG_IXGBE_DCB |
e7589eab | 8176 | if (tc) { |
8b1c0b24 | 8177 | netdev_set_num_tc(dev, tc); |
02debdc9 AD |
8178 | ixgbe_set_prio_tc_map(adapter); |
8179 | ||
e7589eab | 8180 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
e7589eab | 8181 | |
943561d3 AD |
8182 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
8183 | adapter->last_lfc_mode = adapter->hw.fc.requested_mode; | |
e7589eab | 8184 | adapter->hw.fc.requested_mode = ixgbe_fc_none; |
943561d3 | 8185 | } |
e7589eab | 8186 | } else { |
8b1c0b24 | 8187 | netdev_reset_tc(dev); |
02debdc9 | 8188 | |
943561d3 AD |
8189 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
8190 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; | |
e7589eab JF |
8191 | |
8192 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
e7589eab JF |
8193 | |
8194 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
8195 | adapter->dcb_cfg.pfc_mode_enable = false; | |
8196 | } | |
8197 | ||
8b1c0b24 | 8198 | ixgbe_validate_rtr(adapter, tc); |
cca73c59 AD |
8199 | |
8200 | #endif /* CONFIG_IXGBE_DCB */ | |
8201 | ixgbe_init_interrupt_scheme(adapter); | |
8202 | ||
8b1c0b24 | 8203 | if (netif_running(dev)) |
cca73c59 | 8204 | return ixgbe_open(dev); |
8b1c0b24 JF |
8205 | |
8206 | return 0; | |
8207 | } | |
de1036b1 | 8208 | |
b82b17d9 JF |
8209 | static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, |
8210 | struct tc_cls_u32_offload *cls) | |
8211 | { | |
8212 | int err; | |
8213 | ||
8214 | spin_lock(&adapter->fdir_perfect_lock); | |
8215 | err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, cls->knode.handle); | |
8216 | spin_unlock(&adapter->fdir_perfect_lock); | |
8217 | return err; | |
8218 | } | |
8219 | ||
db956ae8 JF |
8220 | static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, |
8221 | __be16 protocol, | |
8222 | struct tc_cls_u32_offload *cls) | |
8223 | { | |
8224 | /* This ixgbe devices do not support hash tables at the moment | |
8225 | * so abort when given hash tables. | |
8226 | */ | |
8227 | if (cls->hnode.divisor > 0) | |
8228 | return -EINVAL; | |
8229 | ||
8230 | set_bit(TC_U32_USERHTID(cls->hnode.handle), &adapter->tables); | |
8231 | return 0; | |
8232 | } | |
8233 | ||
8234 | static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, | |
8235 | struct tc_cls_u32_offload *cls) | |
8236 | { | |
8237 | clear_bit(TC_U32_USERHTID(cls->hnode.handle), &adapter->tables); | |
8238 | return 0; | |
8239 | } | |
8240 | ||
b82b17d9 JF |
8241 | static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, |
8242 | __be16 protocol, | |
8243 | struct tc_cls_u32_offload *cls) | |
8244 | { | |
8245 | u32 loc = cls->knode.handle & 0xfffff; | |
8246 | struct ixgbe_hw *hw = &adapter->hw; | |
8247 | struct ixgbe_mat_field *field_ptr; | |
8248 | struct ixgbe_fdir_filter *input; | |
8249 | union ixgbe_atr_input mask; | |
8250 | #ifdef CONFIG_NET_CLS_ACT | |
8251 | const struct tc_action *a; | |
8252 | #endif | |
8253 | int i, err = 0; | |
8254 | u8 queue; | |
8255 | u32 handle; | |
8256 | ||
8257 | memset(&mask, 0, sizeof(union ixgbe_atr_input)); | |
8258 | handle = cls->knode.handle; | |
8259 | ||
8260 | /* At the moment cls_u32 jumps to transport layer and skips past | |
8261 | * L2 headers. The canonical method to match L2 frames is to use | |
8262 | * negative values. However this is error prone at best but really | |
8263 | * just broken because there is no way to "know" what sort of hdr | |
8264 | * is in front of the transport layer. Fix cls_u32 to support L2 | |
8265 | * headers when needed. | |
8266 | */ | |
8267 | if (protocol != htons(ETH_P_IP)) | |
8268 | return -EINVAL; | |
8269 | ||
8270 | if (cls->knode.link_handle || | |
8271 | cls->knode.link_handle >= IXGBE_MAX_LINK_HANDLE) { | |
8272 | struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; | |
8273 | u32 uhtid = TC_U32_USERHTID(cls->knode.link_handle); | |
8274 | ||
db956ae8 JF |
8275 | if (!test_bit(uhtid, &adapter->tables)) |
8276 | return -EINVAL; | |
8277 | ||
b82b17d9 JF |
8278 | for (i = 0; nexthdr[i].jump; i++) { |
8279 | if (nexthdr->o != cls->knode.sel->offoff || | |
8280 | nexthdr->s != cls->knode.sel->offshift || | |
8281 | nexthdr->m != cls->knode.sel->offmask || | |
8282 | /* do not support multiple key jumps its just mad */ | |
8283 | cls->knode.sel->nkeys > 1) | |
8284 | return -EINVAL; | |
8285 | ||
8286 | if (nexthdr->off != cls->knode.sel->keys[0].off || | |
8287 | nexthdr->val != cls->knode.sel->keys[0].val || | |
8288 | nexthdr->mask != cls->knode.sel->keys[0].mask) | |
8289 | return -EINVAL; | |
8290 | ||
8291 | if (uhtid >= IXGBE_MAX_LINK_HANDLE) | |
8292 | return -EINVAL; | |
8293 | ||
8294 | adapter->jump_tables[uhtid] = nexthdr->jump; | |
8295 | } | |
8296 | return 0; | |
8297 | } | |
8298 | ||
8299 | if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { | |
8300 | e_err(drv, "Location out of range\n"); | |
8301 | return -EINVAL; | |
8302 | } | |
8303 | ||
8304 | /* cls u32 is a graph starting at root node 0x800. The driver tracks | |
8305 | * links and also the fields used to advance the parser across each | |
8306 | * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map | |
8307 | * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h | |
8308 | * To add support for new nodes update ixgbe_model.h parse structures | |
8309 | * this function _should_ be generic try not to hardcode values here. | |
8310 | */ | |
8311 | if (TC_U32_USERHTID(handle) == 0x800) { | |
8312 | field_ptr = adapter->jump_tables[0]; | |
8313 | } else { | |
8314 | if (TC_U32_USERHTID(handle) >= ARRAY_SIZE(adapter->jump_tables)) | |
8315 | return -EINVAL; | |
8316 | ||
8317 | field_ptr = adapter->jump_tables[TC_U32_USERHTID(handle)]; | |
8318 | } | |
8319 | ||
8320 | if (!field_ptr) | |
8321 | return -EINVAL; | |
8322 | ||
8323 | input = kzalloc(sizeof(*input), GFP_KERNEL); | |
8324 | if (!input) | |
8325 | return -ENOMEM; | |
8326 | ||
8327 | for (i = 0; i < cls->knode.sel->nkeys; i++) { | |
8328 | int off = cls->knode.sel->keys[i].off; | |
8329 | __be32 val = cls->knode.sel->keys[i].val; | |
8330 | __be32 m = cls->knode.sel->keys[i].mask; | |
8331 | bool found_entry = false; | |
8332 | int j; | |
8333 | ||
8334 | for (j = 0; field_ptr[j].val; j++) { | |
8335 | if (field_ptr[j].off == off && | |
8336 | field_ptr[j].mask == m) { | |
8337 | field_ptr[j].val(input, &mask, val, m); | |
8338 | input->filter.formatted.flow_type |= | |
8339 | field_ptr[j].type; | |
8340 | found_entry = true; | |
8341 | break; | |
8342 | } | |
8343 | } | |
8344 | ||
8345 | if (!found_entry) | |
8346 | goto err_out; | |
8347 | } | |
8348 | ||
8349 | mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | | |
8350 | IXGBE_ATR_L4TYPE_MASK; | |
8351 | ||
8352 | if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) | |
8353 | mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; | |
8354 | ||
8355 | #ifdef CONFIG_NET_CLS_ACT | |
8356 | if (list_empty(&cls->knode.exts->actions)) | |
8357 | goto err_out; | |
8358 | ||
8359 | list_for_each_entry(a, &cls->knode.exts->actions, list) { | |
8360 | if (!is_tcf_gact_shot(a)) | |
8361 | goto err_out; | |
8362 | } | |
8363 | #endif | |
8364 | ||
8365 | input->action = IXGBE_FDIR_DROP_QUEUE; | |
8366 | queue = IXGBE_FDIR_DROP_QUEUE; | |
8367 | input->sw_idx = loc; | |
8368 | ||
8369 | spin_lock(&adapter->fdir_perfect_lock); | |
8370 | ||
8371 | if (hlist_empty(&adapter->fdir_filter_list)) { | |
8372 | memcpy(&adapter->fdir_mask, &mask, sizeof(mask)); | |
8373 | err = ixgbe_fdir_set_input_mask_82599(hw, &mask); | |
8374 | if (err) | |
8375 | goto err_out_w_lock; | |
8376 | } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) { | |
8377 | err = -EINVAL; | |
8378 | goto err_out_w_lock; | |
8379 | } | |
8380 | ||
8381 | ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask); | |
8382 | err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, | |
8383 | input->sw_idx, queue); | |
8384 | if (!err) | |
8385 | ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); | |
8386 | spin_unlock(&adapter->fdir_perfect_lock); | |
8387 | ||
8388 | return err; | |
8389 | err_out_w_lock: | |
8390 | spin_unlock(&adapter->fdir_perfect_lock); | |
8391 | err_out: | |
8392 | kfree(input); | |
8393 | return -EINVAL; | |
8394 | } | |
8395 | ||
16e5cc64 JF |
8396 | int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto, |
8397 | struct tc_to_netdev *tc) | |
e4c6734e | 8398 | { |
b82b17d9 JF |
8399 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
8400 | ||
8401 | if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) && | |
8402 | tc->type == TC_SETUP_CLSU32) { | |
b82b17d9 JF |
8403 | switch (tc->cls_u32->command) { |
8404 | case TC_CLSU32_NEW_KNODE: | |
8405 | case TC_CLSU32_REPLACE_KNODE: | |
8406 | return ixgbe_configure_clsu32(adapter, | |
8407 | proto, tc->cls_u32); | |
8408 | case TC_CLSU32_DELETE_KNODE: | |
8409 | return ixgbe_delete_clsu32(adapter, tc->cls_u32); | |
db956ae8 JF |
8410 | case TC_CLSU32_NEW_HNODE: |
8411 | case TC_CLSU32_REPLACE_HNODE: | |
8412 | return ixgbe_configure_clsu32_add_hnode(adapter, proto, | |
8413 | tc->cls_u32); | |
8414 | case TC_CLSU32_DELETE_HNODE: | |
8415 | return ixgbe_configure_clsu32_del_hnode(adapter, | |
8416 | tc->cls_u32); | |
b82b17d9 JF |
8417 | default: |
8418 | return -EINVAL; | |
8419 | } | |
8420 | } | |
8421 | ||
16e5cc64 | 8422 | if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO) |
e4c6734e JF |
8423 | return -EINVAL; |
8424 | ||
16e5cc64 | 8425 | return ixgbe_setup_tc(dev, tc->tc); |
e4c6734e JF |
8426 | } |
8427 | ||
da36b647 GR |
8428 | #ifdef CONFIG_PCI_IOV |
8429 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) | |
8430 | { | |
8431 | struct net_device *netdev = adapter->netdev; | |
8432 | ||
8433 | rtnl_lock(); | |
da36b647 | 8434 | ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); |
da36b647 GR |
8435 | rtnl_unlock(); |
8436 | } | |
8437 | ||
8438 | #endif | |
082757af DS |
8439 | void ixgbe_do_reset(struct net_device *netdev) |
8440 | { | |
8441 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8442 | ||
8443 | if (netif_running(netdev)) | |
8444 | ixgbe_reinit_locked(adapter); | |
8445 | else | |
8446 | ixgbe_reset(adapter); | |
8447 | } | |
8448 | ||
c8f44aff | 8449 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 8450 | netdev_features_t features) |
082757af DS |
8451 | { |
8452 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8453 | ||
082757af | 8454 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ |
567d2de2 AD |
8455 | if (!(features & NETIF_F_RXCSUM)) |
8456 | features &= ~NETIF_F_LRO; | |
082757af | 8457 | |
567d2de2 AD |
8458 | /* Turn off LRO if not RSC capable */ |
8459 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
8460 | features &= ~NETIF_F_LRO; | |
8e2813f5 | 8461 | |
567d2de2 | 8462 | return features; |
082757af DS |
8463 | } |
8464 | ||
c8f44aff | 8465 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 8466 | netdev_features_t features) |
082757af DS |
8467 | { |
8468 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 8469 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
8470 | bool need_reset = false; |
8471 | ||
082757af | 8472 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
8473 | if (!(features & NETIF_F_LRO)) { |
8474 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 8475 | need_reset = true; |
567d2de2 AD |
8476 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
8477 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
8478 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
8479 | if (adapter->rx_itr_setting == 1 || | |
8480 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
8481 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
8482 | need_reset = true; | |
8483 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
8484 | e_info(probe, "rx-usecs set too low, " | |
8485 | "disabling RSC\n"); | |
082757af DS |
8486 | } |
8487 | } | |
8488 | ||
8489 | /* | |
b82b17d9 JF |
8490 | * Check if Flow Director n-tuple support or hw_tc support was |
8491 | * enabled or disabled. If the state changed, we need to reset. | |
082757af | 8492 | */ |
b82b17d9 | 8493 | if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { |
567d2de2 | 8494 | /* turn off ATR, enable perfect filters and reset */ |
39cb681b AD |
8495 | if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) |
8496 | need_reset = true; | |
8497 | ||
567d2de2 AD |
8498 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
8499 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
b82b17d9 | 8500 | } else { |
39cb681b AD |
8501 | /* turn off perfect filters, enable ATR and reset */ |
8502 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
8503 | need_reset = true; | |
8504 | ||
8505 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
8506 | ||
8507 | /* We cannot enable ATR if SR-IOV is enabled */ | |
b82b17d9 JF |
8508 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || |
8509 | /* We cannot enable ATR if we have 2 or more tcs */ | |
8510 | (netdev_get_num_tc(netdev) > 1) || | |
8511 | /* We cannot enable ATR if RSS is disabled */ | |
8512 | (adapter->ring_feature[RING_F_RSS].limit <= 1) || | |
8513 | /* A sample rate of 0 indicates ATR disabled */ | |
8514 | (!adapter->atr_sample_rate)) | |
8515 | ; /* do nothing not supported */ | |
8516 | else /* otherwise supported and set the flag */ | |
8517 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
082757af DS |
8518 | } |
8519 | ||
f646968f | 8520 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
146d4cc9 JF |
8521 | ixgbe_vlan_strip_enable(adapter); |
8522 | else | |
8523 | ixgbe_vlan_strip_disable(adapter); | |
8524 | ||
3f2d1c0f BG |
8525 | if (changed & NETIF_F_RXALL) |
8526 | need_reset = true; | |
8527 | ||
567d2de2 | 8528 | netdev->features = features; |
67359c3c MR |
8529 | |
8530 | #ifdef CONFIG_IXGBE_VXLAN | |
8531 | if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { | |
8532 | if (features & NETIF_F_RXCSUM) | |
8533 | adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED; | |
8534 | else | |
8535 | ixgbe_clear_vxlan_port(adapter); | |
8536 | } | |
8537 | #endif /* CONFIG_IXGBE_VXLAN */ | |
8538 | ||
082757af DS |
8539 | if (need_reset) |
8540 | ixgbe_do_reset(netdev); | |
8541 | ||
8542 | return 0; | |
082757af DS |
8543 | } |
8544 | ||
67359c3c | 8545 | #ifdef CONFIG_IXGBE_VXLAN |
3f207800 DS |
8546 | /** |
8547 | * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up | |
8548 | * @dev: The port's netdev | |
8549 | * @sa_family: Socket Family that VXLAN is notifiying us about | |
8550 | * @port: New UDP port number that VXLAN started listening to | |
8551 | **/ | |
8552 | static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family, | |
8553 | __be16 port) | |
8554 | { | |
8555 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
8556 | struct ixgbe_hw *hw = &adapter->hw; | |
8557 | u16 new_port = ntohs(port); | |
8558 | ||
67359c3c MR |
8559 | if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) |
8560 | return; | |
8561 | ||
3f207800 DS |
8562 | if (sa_family == AF_INET6) |
8563 | return; | |
8564 | ||
67359c3c | 8565 | if (adapter->vxlan_port == new_port) |
3f207800 | 8566 | return; |
3f207800 DS |
8567 | |
8568 | if (adapter->vxlan_port) { | |
8569 | netdev_info(dev, | |
67359c3c | 8570 | "Hit Max num of VXLAN ports, not adding port %d\n", |
3f207800 DS |
8571 | new_port); |
8572 | return; | |
8573 | } | |
8574 | ||
8575 | adapter->vxlan_port = new_port; | |
8576 | IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port); | |
8577 | } | |
8578 | ||
8579 | /** | |
8580 | * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away | |
8581 | * @dev: The port's netdev | |
8582 | * @sa_family: Socket Family that VXLAN is notifying us about | |
8583 | * @port: UDP port number that VXLAN stopped listening to | |
8584 | **/ | |
8585 | static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family, | |
8586 | __be16 port) | |
8587 | { | |
8588 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
3f207800 DS |
8589 | u16 new_port = ntohs(port); |
8590 | ||
67359c3c MR |
8591 | if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) |
8592 | return; | |
8593 | ||
3f207800 DS |
8594 | if (sa_family == AF_INET6) |
8595 | return; | |
8596 | ||
8597 | if (adapter->vxlan_port != new_port) { | |
8598 | netdev_info(dev, "Port %d was not found, not deleting\n", | |
8599 | new_port); | |
8600 | return; | |
8601 | } | |
8602 | ||
67359c3c MR |
8603 | ixgbe_clear_vxlan_port(adapter); |
8604 | adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED; | |
3f207800 | 8605 | } |
67359c3c | 8606 | #endif /* CONFIG_IXGBE_VXLAN */ |
3f207800 | 8607 | |
edc7d573 | 8608 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
0f4b0add | 8609 | struct net_device *dev, |
f6f6424b | 8610 | const unsigned char *addr, u16 vid, |
0f4b0add JF |
8611 | u16 flags) |
8612 | { | |
bcfd3432 | 8613 | /* guarantee we can provide a unique filter for the unicast address */ |
46acc460 | 8614 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { |
2f9be166 AD |
8615 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
8616 | u16 pool = VMDQ_P(0); | |
8617 | ||
8618 | if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) | |
bcfd3432 | 8619 | return -ENOMEM; |
0f4b0add JF |
8620 | } |
8621 | ||
f6f6424b | 8622 | return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); |
0f4b0add JF |
8623 | } |
8624 | ||
219efe97 DS |
8625 | /** |
8626 | * ixgbe_configure_bridge_mode - set various bridge modes | |
8627 | * @adapter - the private structure | |
8628 | * @mode - requested bridge mode | |
8629 | * | |
8630 | * Configure some settings require for various bridge modes. | |
8631 | **/ | |
8632 | static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, | |
8633 | __u16 mode) | |
8634 | { | |
6d4c96ad DS |
8635 | struct ixgbe_hw *hw = &adapter->hw; |
8636 | unsigned int p, num_pools; | |
8637 | u32 vmdctl; | |
8638 | ||
219efe97 DS |
8639 | switch (mode) { |
8640 | case BRIDGE_MODE_VEPA: | |
6d4c96ad | 8641 | /* disable Tx loopback, rely on switch hairpin mode */ |
219efe97 | 8642 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); |
6d4c96ad DS |
8643 | |
8644 | /* must enable Rx switching replication to allow multicast | |
8645 | * packet reception on all VFs, and to enable source address | |
8646 | * pruning. | |
8647 | */ | |
8648 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); | |
8649 | vmdctl |= IXGBE_VT_CTL_REPLEN; | |
8650 | IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); | |
8651 | ||
8652 | /* enable Rx source address pruning. Note, this requires | |
8653 | * replication to be enabled or else it does nothing. | |
8654 | */ | |
8655 | num_pools = adapter->num_vfs + adapter->num_rx_pools; | |
8656 | for (p = 0; p < num_pools; p++) { | |
8657 | if (hw->mac.ops.set_source_address_pruning) | |
8658 | hw->mac.ops.set_source_address_pruning(hw, | |
8659 | true, | |
8660 | p); | |
8661 | } | |
219efe97 DS |
8662 | break; |
8663 | case BRIDGE_MODE_VEB: | |
6d4c96ad | 8664 | /* enable Tx loopback for internal VF/PF communication */ |
219efe97 DS |
8665 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, |
8666 | IXGBE_PFDTXGSWC_VT_LBEN); | |
6d4c96ad DS |
8667 | |
8668 | /* disable Rx switching replication unless we have SR-IOV | |
8669 | * virtual functions | |
8670 | */ | |
8671 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); | |
8672 | if (!adapter->num_vfs) | |
8673 | vmdctl &= ~IXGBE_VT_CTL_REPLEN; | |
8674 | IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); | |
8675 | ||
8676 | /* disable Rx source address pruning, since we don't expect to | |
8677 | * be receiving external loopback of our transmitted frames. | |
8678 | */ | |
8679 | num_pools = adapter->num_vfs + adapter->num_rx_pools; | |
8680 | for (p = 0; p < num_pools; p++) { | |
8681 | if (hw->mac.ops.set_source_address_pruning) | |
8682 | hw->mac.ops.set_source_address_pruning(hw, | |
8683 | false, | |
8684 | p); | |
8685 | } | |
219efe97 DS |
8686 | break; |
8687 | default: | |
8688 | return -EINVAL; | |
8689 | } | |
8690 | ||
8691 | adapter->bridge_mode = mode; | |
8692 | ||
8693 | e_info(drv, "enabling bridge mode: %s\n", | |
8694 | mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
8695 | ||
8696 | return 0; | |
8697 | } | |
8698 | ||
815cccbf | 8699 | static int ixgbe_ndo_bridge_setlink(struct net_device *dev, |
add511b3 | 8700 | struct nlmsghdr *nlh, u16 flags) |
815cccbf JF |
8701 | { |
8702 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
8703 | struct nlattr *attr, *br_spec; | |
8704 | int rem; | |
8705 | ||
8706 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
8707 | return -EOPNOTSUPP; | |
8708 | ||
8709 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
4ea85e83 TG |
8710 | if (!br_spec) |
8711 | return -EINVAL; | |
815cccbf JF |
8712 | |
8713 | nla_for_each_nested(attr, br_spec, rem) { | |
a1e869de | 8714 | int status; |
815cccbf | 8715 | __u16 mode; |
815cccbf JF |
8716 | |
8717 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
8718 | continue; | |
8719 | ||
b7c1a314 TG |
8720 | if (nla_len(attr) < sizeof(mode)) |
8721 | return -EINVAL; | |
8722 | ||
815cccbf | 8723 | mode = nla_get_u16(attr); |
219efe97 DS |
8724 | status = ixgbe_configure_bridge_mode(adapter, mode); |
8725 | if (status) | |
8726 | return status; | |
aa2bacb6 DS |
8727 | |
8728 | break; | |
815cccbf JF |
8729 | } |
8730 | ||
8731 | return 0; | |
8732 | } | |
8733 | ||
8734 | static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, | |
6cbdceeb | 8735 | struct net_device *dev, |
46c264da | 8736 | u32 filter_mask, int nlflags) |
815cccbf JF |
8737 | { |
8738 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
815cccbf JF |
8739 | |
8740 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
8741 | return 0; | |
8742 | ||
aa2bacb6 | 8743 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, |
7d4f8d87 SF |
8744 | adapter->bridge_mode, 0, 0, nlflags, |
8745 | filter_mask, NULL); | |
815cccbf JF |
8746 | } |
8747 | ||
2a47fa45 JF |
8748 | static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) |
8749 | { | |
8750 | struct ixgbe_fwd_adapter *fwd_adapter = NULL; | |
8751 | struct ixgbe_adapter *adapter = netdev_priv(pdev); | |
aac2f1bf | 8752 | int used_pools = adapter->num_vfs + adapter->num_rx_pools; |
51f3773b | 8753 | unsigned int limit; |
2a47fa45 JF |
8754 | int pool, err; |
8755 | ||
aac2f1bf JK |
8756 | /* Hardware has a limited number of available pools. Each VF, and the |
8757 | * PF require a pool. Check to ensure we don't attempt to use more | |
8758 | * then the available number of pools. | |
8759 | */ | |
8760 | if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) | |
8761 | return ERR_PTR(-EINVAL); | |
8762 | ||
219354d4 JF |
8763 | #ifdef CONFIG_RPS |
8764 | if (vdev->num_rx_queues != vdev->num_tx_queues) { | |
8765 | netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", | |
8766 | vdev->name); | |
8767 | return ERR_PTR(-EINVAL); | |
8768 | } | |
8769 | #endif | |
2a47fa45 | 8770 | /* Check for hardware restriction on number of rx/tx queues */ |
219354d4 | 8771 | if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || |
2a47fa45 JF |
8772 | vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { |
8773 | netdev_info(pdev, | |
8774 | "%s: Supports RX/TX Queue counts 1,2, and 4\n", | |
8775 | pdev->name); | |
8776 | return ERR_PTR(-EINVAL); | |
8777 | } | |
8778 | ||
8779 | if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && | |
8780 | adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || | |
8781 | (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) | |
8782 | return ERR_PTR(-EBUSY); | |
8783 | ||
bc52f951 | 8784 | fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); |
2a47fa45 JF |
8785 | if (!fwd_adapter) |
8786 | return ERR_PTR(-ENOMEM); | |
8787 | ||
8788 | pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); | |
8789 | adapter->num_rx_pools++; | |
8790 | set_bit(pool, &adapter->fwd_bitmask); | |
51f3773b | 8791 | limit = find_last_bit(&adapter->fwd_bitmask, 32); |
2a47fa45 JF |
8792 | |
8793 | /* Enable VMDq flag so device will be set in VM mode */ | |
8794 | adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; | |
51f3773b | 8795 | adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; |
219354d4 | 8796 | adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; |
2a47fa45 JF |
8797 | |
8798 | /* Force reinit of ring allocation with VMDQ enabled */ | |
8799 | err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); | |
8800 | if (err) | |
8801 | goto fwd_add_err; | |
8802 | fwd_adapter->pool = pool; | |
8803 | fwd_adapter->real_adapter = adapter; | |
8804 | err = ixgbe_fwd_ring_up(vdev, fwd_adapter); | |
8805 | if (err) | |
8806 | goto fwd_add_err; | |
8807 | netif_tx_start_all_queues(vdev); | |
8808 | return fwd_adapter; | |
8809 | fwd_add_err: | |
8810 | /* unwind counter and free adapter struct */ | |
8811 | netdev_info(pdev, | |
8812 | "%s: dfwd hardware acceleration failed\n", vdev->name); | |
8813 | clear_bit(pool, &adapter->fwd_bitmask); | |
8814 | adapter->num_rx_pools--; | |
8815 | kfree(fwd_adapter); | |
8816 | return ERR_PTR(err); | |
8817 | } | |
8818 | ||
8819 | static void ixgbe_fwd_del(struct net_device *pdev, void *priv) | |
8820 | { | |
8821 | struct ixgbe_fwd_adapter *fwd_adapter = priv; | |
8822 | struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; | |
51f3773b | 8823 | unsigned int limit; |
2a47fa45 JF |
8824 | |
8825 | clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); | |
8826 | adapter->num_rx_pools--; | |
8827 | ||
51f3773b JF |
8828 | limit = find_last_bit(&adapter->fwd_bitmask, 32); |
8829 | adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; | |
2a47fa45 JF |
8830 | ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); |
8831 | ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); | |
8832 | netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", | |
8833 | fwd_adapter->pool, adapter->num_rx_pools, | |
8834 | fwd_adapter->rx_base_queue, | |
8835 | fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, | |
8836 | adapter->fwd_bitmask); | |
8837 | kfree(fwd_adapter); | |
8838 | } | |
8839 | ||
f467bc06 MR |
8840 | #define IXGBE_MAX_TUNNEL_HDR_LEN 80 |
8841 | static netdev_features_t | |
8842 | ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, | |
8843 | netdev_features_t features) | |
8844 | { | |
8845 | if (!skb->encapsulation) | |
8846 | return features; | |
8847 | ||
8848 | if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) > | |
8849 | IXGBE_MAX_TUNNEL_HDR_LEN)) | |
a188222b | 8850 | return features & ~NETIF_F_CSUM_MASK; |
f467bc06 MR |
8851 | |
8852 | return features; | |
8853 | } | |
8854 | ||
0edc3527 | 8855 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 8856 | .ndo_open = ixgbe_open, |
0edc3527 | 8857 | .ndo_stop = ixgbe_close, |
00829823 | 8858 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 8859 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 8860 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
8861 | .ndo_validate_addr = eth_validate_addr, |
8862 | .ndo_set_mac_address = ixgbe_set_mac, | |
8863 | .ndo_change_mtu = ixgbe_change_mtu, | |
8864 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
8865 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
8866 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 8867 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
8868 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
8869 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
ed616689 | 8870 | .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, |
581330ba | 8871 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
e65ce0d3 | 8872 | .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, |
54011e4d | 8873 | .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, |
7f01648a | 8874 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 8875 | .ndo_get_stats64 = ixgbe_get_stats64, |
e4c6734e | 8876 | .ndo_setup_tc = __ixgbe_setup_tc, |
0edc3527 SH |
8877 | #ifdef CONFIG_NET_POLL_CONTROLLER |
8878 | .ndo_poll_controller = ixgbe_netpoll, | |
8879 | #endif | |
e0d1095a | 8880 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8b80cda5 | 8881 | .ndo_busy_poll = ixgbe_low_latency_recv, |
5a85e737 | 8882 | #endif |
332d4a7d YZ |
8883 | #ifdef IXGBE_FCOE |
8884 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 8885 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 8886 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
8887 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
8888 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 8889 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 8890 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 8891 | #endif /* IXGBE_FCOE */ |
082757af DS |
8892 | .ndo_set_features = ixgbe_set_features, |
8893 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add | 8894 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
815cccbf JF |
8895 | .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, |
8896 | .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, | |
2a47fa45 JF |
8897 | .ndo_dfwd_add_station = ixgbe_fwd_add, |
8898 | .ndo_dfwd_del_station = ixgbe_fwd_del, | |
67359c3c | 8899 | #ifdef CONFIG_IXGBE_VXLAN |
3f207800 DS |
8900 | .ndo_add_vxlan_port = ixgbe_add_vxlan_port, |
8901 | .ndo_del_vxlan_port = ixgbe_del_vxlan_port, | |
67359c3c | 8902 | #endif /* CONFIG_IXGBE_VXLAN */ |
f467bc06 | 8903 | .ndo_features_check = ixgbe_features_check, |
0edc3527 SH |
8904 | }; |
8905 | ||
e027d1ae JK |
8906 | /** |
8907 | * ixgbe_enumerate_functions - Get the number of ports this device has | |
8908 | * @adapter: adapter structure | |
8909 | * | |
8910 | * This function enumerates the phsyical functions co-located on a single slot, | |
8911 | * in order to determine how many ports a device has. This is most useful in | |
8912 | * determining the required GT/s of PCIe bandwidth necessary for optimal | |
8913 | * performance. | |
8914 | **/ | |
8915 | static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) | |
8916 | { | |
caafb95d | 8917 | struct pci_dev *entry, *pdev = adapter->pdev; |
e027d1ae JK |
8918 | int physfns = 0; |
8919 | ||
f1f96579 JK |
8920 | /* Some cards can not use the generic count PCIe functions method, |
8921 | * because they are behind a parent switch, so we hardcode these with | |
8922 | * the correct number of functions. | |
e027d1ae | 8923 | */ |
8818970d | 8924 | if (ixgbe_pcie_from_parent(&adapter->hw)) |
e027d1ae | 8925 | physfns = 4; |
8818970d JK |
8926 | |
8927 | list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { | |
8928 | /* don't count virtual functions */ | |
caafb95d JK |
8929 | if (entry->is_virtfn) |
8930 | continue; | |
8931 | ||
8932 | /* When the devices on the bus don't all match our device ID, | |
8933 | * we can't reliably determine the correct number of | |
8934 | * functions. This can occur if a function has been direct | |
8935 | * attached to a virtual machine using VT-d, for example. In | |
8936 | * this case, simply return -1 to indicate this. | |
8937 | */ | |
8938 | if ((entry->vendor != pdev->vendor) || | |
8939 | (entry->device != pdev->device)) | |
8940 | return -1; | |
8941 | ||
8942 | physfns++; | |
e027d1ae JK |
8943 | } |
8944 | ||
8945 | return physfns; | |
8946 | } | |
8947 | ||
8e2813f5 JK |
8948 | /** |
8949 | * ixgbe_wol_supported - Check whether device supports WoL | |
8950 | * @hw: hw specific details | |
8951 | * @device_id: the device ID | |
8952 | * @subdev_id: the subsystem device ID | |
8953 | * | |
8954 | * This function is used by probe and ethtool to determine | |
8955 | * which devices have WoL support | |
8956 | * | |
8957 | **/ | |
8958 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
8959 | u16 subdevice_id) | |
8960 | { | |
8961 | struct ixgbe_hw *hw = &adapter->hw; | |
8962 | u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
8963 | int is_wol_supported = 0; | |
8964 | ||
8965 | switch (device_id) { | |
8966 | case IXGBE_DEV_ID_82599_SFP: | |
8967 | /* Only these subdevices could supports WOL */ | |
8968 | switch (subdevice_id) { | |
87557440 | 8969 | case IXGBE_SUBDEV_ID_82599_SFP_WOL0: |
8e2813f5 JK |
8970 | case IXGBE_SUBDEV_ID_82599_560FLR: |
8971 | /* only support first port */ | |
8972 | if (hw->bus.func != 0) | |
8973 | break; | |
5700ff26 | 8974 | case IXGBE_SUBDEV_ID_82599_SP_560FLR: |
8e2813f5 | 8975 | case IXGBE_SUBDEV_ID_82599_SFP: |
b6dfd939 | 8976 | case IXGBE_SUBDEV_ID_82599_RNDC: |
f8a06c2c | 8977 | case IXGBE_SUBDEV_ID_82599_ECNA_DP: |
979fe5f7 | 8978 | case IXGBE_SUBDEV_ID_82599_LOM_SFP: |
8e2813f5 JK |
8979 | is_wol_supported = 1; |
8980 | break; | |
8981 | } | |
8982 | break; | |
5daebbb0 DS |
8983 | case IXGBE_DEV_ID_82599EN_SFP: |
8984 | /* Only this subdevice supports WOL */ | |
8985 | switch (subdevice_id) { | |
8986 | case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: | |
8987 | is_wol_supported = 1; | |
8988 | break; | |
8989 | } | |
8990 | break; | |
8e2813f5 JK |
8991 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
8992 | /* All except this subdevice support WOL */ | |
8993 | if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) | |
8994 | is_wol_supported = 1; | |
8995 | break; | |
8996 | case IXGBE_DEV_ID_82599_KX4: | |
8997 | is_wol_supported = 1; | |
8998 | break; | |
8999 | case IXGBE_DEV_ID_X540T: | |
df376f0d | 9000 | case IXGBE_DEV_ID_X540T1: |
df8c26fd DS |
9001 | case IXGBE_DEV_ID_X550T: |
9002 | case IXGBE_DEV_ID_X550EM_X_KX4: | |
9003 | case IXGBE_DEV_ID_X550EM_X_KR: | |
9004 | case IXGBE_DEV_ID_X550EM_X_10G_T: | |
8e2813f5 JK |
9005 | /* check eeprom to see if enabled wol */ |
9006 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
9007 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
9008 | (hw->bus.func == 0))) { | |
9009 | is_wol_supported = 1; | |
9010 | } | |
9011 | break; | |
9012 | } | |
9013 | ||
9014 | return is_wol_supported; | |
9015 | } | |
9016 | ||
c762dff2 MP |
9017 | /** |
9018 | * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM | |
9019 | * @adapter: Pointer to adapter struct | |
9020 | */ | |
9021 | static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter) | |
9022 | { | |
9023 | #ifdef CONFIG_OF | |
9024 | struct device_node *dp = pci_device_to_OF_node(adapter->pdev); | |
9025 | struct ixgbe_hw *hw = &adapter->hw; | |
9026 | const unsigned char *addr; | |
9027 | ||
9028 | addr = of_get_mac_address(dp); | |
9029 | if (addr) { | |
9030 | ether_addr_copy(hw->mac.perm_addr, addr); | |
9031 | return; | |
9032 | } | |
9033 | #endif /* CONFIG_OF */ | |
9034 | ||
9035 | #ifdef CONFIG_SPARC | |
9036 | ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr); | |
9037 | #endif /* CONFIG_SPARC */ | |
9038 | } | |
9039 | ||
9a799d71 AK |
9040 | /** |
9041 | * ixgbe_probe - Device Initialization Routine | |
9042 | * @pdev: PCI device information struct | |
9043 | * @ent: entry in ixgbe_pci_tbl | |
9044 | * | |
9045 | * Returns 0 on success, negative on failure | |
9046 | * | |
9047 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
9048 | * The OS initialization, configuring of the adapter private structure, | |
9049 | * and a hardware reset occur. | |
9050 | **/ | |
1dd06ae8 | 9051 | static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
9a799d71 AK |
9052 | { |
9053 | struct net_device *netdev; | |
9054 | struct ixgbe_adapter *adapter = NULL; | |
9055 | struct ixgbe_hw *hw; | |
9056 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
e027d1ae | 9057 | int i, err, pci_using_dac, expected_gts; |
d3cb9869 | 9058 | unsigned int indices = MAX_TX_QUEUES; |
289700db | 9059 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
b5b2ffc0 | 9060 | bool disable_dev = false; |
eacd73f7 YZ |
9061 | #ifdef IXGBE_FCOE |
9062 | u16 device_caps; | |
9063 | #endif | |
289700db | 9064 | u32 eec; |
9a799d71 | 9065 | |
bded64a7 AG |
9066 | /* Catch broken hardware that put the wrong VF device ID in |
9067 | * the PCIe SR-IOV capability. | |
9068 | */ | |
9069 | if (pdev->is_virtfn) { | |
9070 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
9071 | pci_name(pdev), pdev->vendor, pdev->device); | |
9072 | return -EINVAL; | |
9073 | } | |
9074 | ||
9ce77666 | 9075 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
9076 | if (err) |
9077 | return err; | |
9078 | ||
f5f2eda8 | 9079 | if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { |
9a799d71 AK |
9080 | pci_using_dac = 1; |
9081 | } else { | |
f5f2eda8 | 9082 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 9083 | if (err) { |
f5f2eda8 RK |
9084 | dev_err(&pdev->dev, |
9085 | "No usable DMA configuration, aborting\n"); | |
9086 | goto err_dma; | |
9a799d71 AK |
9087 | } |
9088 | pci_using_dac = 0; | |
9089 | } | |
9090 | ||
9ce77666 | 9091 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 9092 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 9093 | if (err) { |
b8bc0421 DC |
9094 | dev_err(&pdev->dev, |
9095 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
9096 | goto err_pci_reg; |
9097 | } | |
9098 | ||
19d5afd4 | 9099 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 9100 | |
9a799d71 | 9101 | pci_set_master(pdev); |
fb3b27bc | 9102 | pci_save_state(pdev); |
9a799d71 | 9103 | |
d3cb9869 | 9104 | if (ii->mac == ixgbe_mac_82598EB) { |
e901acd6 | 9105 | #ifdef CONFIG_IXGBE_DCB |
d3cb9869 AD |
9106 | /* 8 TC w/ 4 queues per TC */ |
9107 | indices = 4 * MAX_TRAFFIC_CLASS; | |
9108 | #else | |
9109 | indices = IXGBE_MAX_RSS_INDICES; | |
e901acd6 | 9110 | #endif |
d3cb9869 | 9111 | } |
e901acd6 | 9112 | |
c85a2618 | 9113 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
9114 | if (!netdev) { |
9115 | err = -ENOMEM; | |
9116 | goto err_alloc_etherdev; | |
9117 | } | |
9118 | ||
9a799d71 AK |
9119 | SET_NETDEV_DEV(netdev, &pdev->dev); |
9120 | ||
9a799d71 AK |
9121 | adapter = netdev_priv(netdev); |
9122 | ||
9123 | adapter->netdev = netdev; | |
9124 | adapter->pdev = pdev; | |
9125 | hw = &adapter->hw; | |
9126 | hw->back = adapter; | |
b3f4d599 | 9127 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 9128 | |
05857980 | 9129 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 9130 | pci_resource_len(pdev, 0)); |
2a1a091c | 9131 | adapter->io_addr = hw->hw_addr; |
9a799d71 AK |
9132 | if (!hw->hw_addr) { |
9133 | err = -EIO; | |
9134 | goto err_ioremap; | |
9135 | } | |
9136 | ||
0edc3527 | 9137 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 9138 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 9139 | netdev->watchdog_timeo = 5 * HZ; |
339de30f | 9140 | strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); |
9a799d71 | 9141 | |
9a799d71 AK |
9142 | /* Setup hw api */ |
9143 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 9144 | hw->mac.type = ii->mac; |
9a900eca | 9145 | hw->mvals = ii->mvals; |
9a799d71 | 9146 | |
c44ade9e JB |
9147 | /* EEPROM */ |
9148 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
9a900eca | 9149 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
58cf663f MR |
9150 | if (ixgbe_removed(hw->hw_addr)) { |
9151 | err = -EIO; | |
9152 | goto err_ioremap; | |
9153 | } | |
c44ade9e JB |
9154 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ |
9155 | if (!(eec & (1 << 8))) | |
9156 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
9157 | ||
9158 | /* PHY */ | |
9159 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 9160 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
9161 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
9162 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
9163 | hw->phy.mdio.mmds = 0; | |
9164 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
9165 | hw->phy.mdio.dev = netdev; | |
9166 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
9167 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 9168 | |
8ca783ab | 9169 | ii->get_invariants(hw); |
9a799d71 AK |
9170 | |
9171 | /* setup the private structure */ | |
9172 | err = ixgbe_sw_init(adapter); | |
9173 | if (err) | |
9174 | goto err_sw_init; | |
9175 | ||
e86bff0e | 9176 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
9177 | switch (adapter->hw.mac.type) { |
9178 | case ixgbe_mac_82599EB: | |
9179 | case ixgbe_mac_X540: | |
9a75a1ac DS |
9180 | case ixgbe_mac_X550: |
9181 | case ixgbe_mac_X550EM_x: | |
e86bff0e | 9182 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
9183 | break; |
9184 | default: | |
9185 | break; | |
9186 | } | |
e86bff0e | 9187 | |
bf069c97 DS |
9188 | /* |
9189 | * If there is a fan on this device and it has failed log the | |
9190 | * failure. | |
9191 | */ | |
9192 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
9193 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
9194 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 9195 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
9196 | } |
9197 | ||
8ef78adc PWJ |
9198 | if (allow_unsupported_sfp) |
9199 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
9200 | ||
c44ade9e | 9201 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 9202 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 9203 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 9204 | hw->phy.reset_if_overtemp = false; |
29a8dca1 | 9205 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
8ca783ab DS |
9206 | err = 0; |
9207 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
1b1bf31a DS |
9208 | e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); |
9209 | e_dev_err("Reload the driver after installing a supported module.\n"); | |
04f165ef PW |
9210 | goto err_sw_init; |
9211 | } else if (err) { | |
849c4542 | 9212 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
9213 | goto err_sw_init; |
9214 | } | |
9215 | ||
99d74487 | 9216 | #ifdef CONFIG_PCI_IOV |
60a1a680 GR |
9217 | /* SR-IOV not supported on the 82598 */ |
9218 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
9219 | goto skip_sriov; | |
9220 | /* Mailbox */ | |
9221 | ixgbe_init_mbx_params_pf(hw); | |
9222 | memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops)); | |
dcc23e3a | 9223 | pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); |
31ac910e | 9224 | ixgbe_enable_sriov(adapter); |
60a1a680 | 9225 | skip_sriov: |
1cdd1ec8 | 9226 | |
99d74487 | 9227 | #endif |
396e799c | 9228 | netdev->features = NETIF_F_SG | |
e8e9f696 | 9229 | NETIF_F_IP_CSUM | |
082757af | 9230 | NETIF_F_IPV6_CSUM | |
f646968f PM |
9231 | NETIF_F_HW_VLAN_CTAG_TX | |
9232 | NETIF_F_HW_VLAN_CTAG_RX | | |
082757af DS |
9233 | NETIF_F_TSO | |
9234 | NETIF_F_TSO6 | | |
082757af | 9235 | NETIF_F_RXHASH | |
8bf1264d | 9236 | NETIF_F_RXCSUM; |
9a799d71 | 9237 | |
8bf1264d | 9238 | netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD; |
ad31c402 | 9239 | |
58be7666 DS |
9240 | switch (adapter->hw.mac.type) { |
9241 | case ixgbe_mac_82599EB: | |
9242 | case ixgbe_mac_X540: | |
9a75a1ac DS |
9243 | case ixgbe_mac_X550: |
9244 | case ixgbe_mac_X550EM_x: | |
53692b1d TH |
9245 | netdev->features |= NETIF_F_SCTP_CRC; |
9246 | netdev->hw_features |= NETIF_F_SCTP_CRC | | |
b82b17d9 JF |
9247 | NETIF_F_NTUPLE | |
9248 | NETIF_F_HW_TC; | |
58be7666 DS |
9249 | break; |
9250 | default: | |
9251 | break; | |
9252 | } | |
45a5ead0 | 9253 | |
3f2d1c0f | 9254 | netdev->hw_features |= NETIF_F_RXALL; |
87031c0d | 9255 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
3f2d1c0f | 9256 | |
ad31c402 JK |
9257 | netdev->vlan_features |= NETIF_F_TSO; |
9258 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 9259 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 9260 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
9261 | netdev->vlan_features |= NETIF_F_SG; |
9262 | ||
fb8ad4a5 | 9263 | netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
f467bc06 | 9264 | |
01789349 | 9265 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 9266 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 9267 | |
67359c3c | 9268 | #ifdef CONFIG_IXGBE_VXLAN |
3f207800 DS |
9269 | switch (adapter->hw.mac.type) { |
9270 | case ixgbe_mac_X550: | |
9271 | case ixgbe_mac_X550EM_x: | |
fb8ad4a5 | 9272 | netdev->hw_enc_features |= NETIF_F_RXCSUM; |
3f207800 DS |
9273 | break; |
9274 | default: | |
9275 | break; | |
9276 | } | |
67359c3c | 9277 | #endif /* CONFIG_IXGBE_VXLAN */ |
3f207800 | 9278 | |
7a6b6f51 | 9279 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
9280 | netdev->dcbnl_ops = &dcbnl_ops; |
9281 | #endif | |
9282 | ||
eacd73f7 | 9283 | #ifdef IXGBE_FCOE |
0d551589 | 9284 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
d3cb9869 AD |
9285 | unsigned int fcoe_l; |
9286 | ||
eacd73f7 YZ |
9287 | if (hw->mac.ops.get_device_caps) { |
9288 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
9289 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
9290 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 | 9291 | } |
7c8ae65a | 9292 | |
d3cb9869 AD |
9293 | |
9294 | fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); | |
9295 | adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; | |
7c8ae65a | 9296 | |
a58915c7 AD |
9297 | netdev->features |= NETIF_F_FSO | |
9298 | NETIF_F_FCOE_CRC; | |
9299 | ||
7c8ae65a AD |
9300 | netdev->vlan_features |= NETIF_F_FSO | |
9301 | NETIF_F_FCOE_CRC | | |
9302 | NETIF_F_FCOE_MTU; | |
5e09d7f6 | 9303 | } |
eacd73f7 | 9304 | #endif /* IXGBE_FCOE */ |
7b872a55 | 9305 | if (pci_using_dac) { |
9a799d71 | 9306 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
9307 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
9308 | } | |
9a799d71 | 9309 | |
082757af DS |
9310 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
9311 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 9312 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
9313 | netdev->features |= NETIF_F_LRO; |
9314 | ||
9a799d71 | 9315 | /* make sure the EEPROM is good */ |
c44ade9e | 9316 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 9317 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 9318 | err = -EIO; |
35937c05 | 9319 | goto err_sw_init; |
9a799d71 AK |
9320 | } |
9321 | ||
c762dff2 MP |
9322 | ixgbe_get_platform_mac_addr(adapter); |
9323 | ||
9a799d71 | 9324 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); |
9a799d71 | 9325 | |
aaeb6cdf | 9326 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
849c4542 | 9327 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 9328 | err = -EIO; |
35937c05 | 9329 | goto err_sw_init; |
9a799d71 AK |
9330 | } |
9331 | ||
c9f53e63 | 9332 | ixgbe_mac_set_default_filter(adapter); |
5d7daa35 | 9333 | |
7086400d | 9334 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 9335 | (unsigned long) adapter); |
9a799d71 | 9336 | |
58cf663f MR |
9337 | if (ixgbe_removed(hw->hw_addr)) { |
9338 | err = -EIO; | |
9339 | goto err_sw_init; | |
9340 | } | |
7086400d | 9341 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
58cf663f | 9342 | set_bit(__IXGBE_SERVICE_INITED, &adapter->state); |
7086400d | 9343 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); |
9a799d71 | 9344 | |
021230d4 AV |
9345 | err = ixgbe_init_interrupt_scheme(adapter); |
9346 | if (err) | |
9347 | goto err_sw_init; | |
9a799d71 | 9348 | |
8e2813f5 | 9349 | /* WOL not supported for all devices */ |
c23f5b6b | 9350 | adapter->wol = 0; |
8e2813f5 | 9351 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); |
6b92b0ba | 9352 | hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, |
b8f83638 | 9353 | pdev->subsystem_device); |
6b92b0ba | 9354 | if (hw->wol_enabled) |
9417c464 | 9355 | adapter->wol = IXGBE_WUFC_MAG; |
c23f5b6b | 9356 | |
e8e26350 PW |
9357 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9358 | ||
15e5209f ET |
9359 | /* save off EEPROM version number */ |
9360 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
9361 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
9362 | ||
04f165ef | 9363 | /* pick up the PCI bus settings for reporting later */ |
e027d1ae | 9364 | if (ixgbe_pcie_from_parent(hw)) |
b8e82001 | 9365 | ixgbe_get_parent_bus_info(adapter); |
f9328bc6 DS |
9366 | else |
9367 | hw->mac.ops.get_bus_info(hw); | |
04f165ef | 9368 | |
e027d1ae JK |
9369 | /* calculate the expected PCIe bandwidth required for optimal |
9370 | * performance. Note that some older parts will never have enough | |
9371 | * bandwidth due to being older generation PCIe parts. We clamp these | |
9372 | * parts to ensure no warning is displayed if it can't be fixed. | |
9373 | */ | |
9374 | switch (hw->mac.type) { | |
9375 | case ixgbe_mac_82598EB: | |
9376 | expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); | |
9377 | break; | |
9378 | default: | |
9379 | expected_gts = ixgbe_enumerate_functions(adapter) * 10; | |
9380 | break; | |
0c254d86 | 9381 | } |
caafb95d JK |
9382 | |
9383 | /* don't check link if we failed to enumerate functions */ | |
9384 | if (expected_gts > 0) | |
9385 | ixgbe_check_minimum_link(adapter, expected_gts); | |
0c254d86 | 9386 | |
339de30f | 9387 | err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); |
6a2aae5a | 9388 | if (err) |
339de30f | 9389 | strlcpy(part_str, "Unknown", sizeof(part_str)); |
6a2aae5a JK |
9390 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
9391 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", | |
9392 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
e7cf745b | 9393 | part_str); |
6a2aae5a JK |
9394 | else |
9395 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", | |
9396 | hw->mac.type, hw->phy.type, part_str); | |
9397 | ||
9398 | e_dev_info("%pM\n", netdev->dev_addr); | |
9399 | ||
9a799d71 | 9400 | /* reset the hardware with the new settings */ |
794caeb2 | 9401 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
9402 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
9403 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
9404 | e_dev_warn("This device is a pre-production adapter/LOM. " |
9405 | "Please be aware there may be issues associated " | |
9406 | "with your hardware. If you are experiencing " | |
9407 | "problems please contact your Intel or hardware " | |
9408 | "representative who provided you with this " | |
9409 | "hardware.\n"); | |
794caeb2 | 9410 | } |
9a799d71 AK |
9411 | strcpy(netdev->name, "eth%d"); |
9412 | err = register_netdev(netdev); | |
9413 | if (err) | |
9414 | goto err_register; | |
9415 | ||
0fb6a55c ET |
9416 | pci_set_drvdata(pdev, adapter); |
9417 | ||
ec74a471 ET |
9418 | /* power down the optics for 82599 SFP+ fiber */ |
9419 | if (hw->mac.ops.disable_tx_laser) | |
93d3ce8f ET |
9420 | hw->mac.ops.disable_tx_laser(hw); |
9421 | ||
54386467 JB |
9422 | /* carrier off reporting is important to ethtool even BEFORE open */ |
9423 | netif_carrier_off(netdev); | |
9424 | ||
5dd2d332 | 9425 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 9426 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 9427 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
9428 | ixgbe_setup_dca(adapter); |
9429 | } | |
9430 | #endif | |
1cdd1ec8 | 9431 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 9432 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
9433 | for (i = 0; i < adapter->num_vfs; i++) |
9434 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
9435 | } | |
9436 | ||
2466dd9c JK |
9437 | /* firmware requires driver version to be 0xFFFFFFFF |
9438 | * since os does not support feature | |
9439 | */ | |
9612de92 | 9440 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
9441 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
9442 | 0xFF); | |
9612de92 | 9443 | |
0365e6e4 PW |
9444 | /* add san mac addr to netdev */ |
9445 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 9446 | |
ea81875a | 9447 | e_dev_info("%s\n", ixgbe_default_device_descr); |
3ca8bc6d | 9448 | |
1210982b | 9449 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d DS |
9450 | if (ixgbe_sysfs_init(adapter)) |
9451 | e_err(probe, "failed to allocate sysfs resources\n"); | |
1210982b | 9452 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 9453 | |
00949167 | 9454 | ixgbe_dbg_adapter_init(adapter); |
00949167 | 9455 | |
d1a35ee2 ET |
9456 | /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ |
9457 | if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) | |
0b2679d6 DS |
9458 | hw->mac.ops.setup_link(hw, |
9459 | IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, | |
9460 | true); | |
9461 | ||
9a799d71 AK |
9462 | return 0; |
9463 | ||
9464 | err_register: | |
5eba3699 | 9465 | ixgbe_release_hw_control(adapter); |
7a921c93 | 9466 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 9467 | err_sw_init: |
99d74487 | 9468 | ixgbe_disable_sriov(adapter); |
7086400d | 9469 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
2a1a091c | 9470 | iounmap(adapter->io_addr); |
5d7daa35 | 9471 | kfree(adapter->mac_table); |
9a799d71 | 9472 | err_ioremap: |
b5b2ffc0 | 9473 | disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); |
9a799d71 AK |
9474 | free_netdev(netdev); |
9475 | err_alloc_etherdev: | |
e8e9f696 JP |
9476 | pci_release_selected_regions(pdev, |
9477 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
9478 | err_pci_reg: |
9479 | err_dma: | |
b5b2ffc0 | 9480 | if (!adapter || disable_dev) |
41c62843 | 9481 | pci_disable_device(pdev); |
9a799d71 AK |
9482 | return err; |
9483 | } | |
9484 | ||
9485 | /** | |
9486 | * ixgbe_remove - Device Removal Routine | |
9487 | * @pdev: PCI device information struct | |
9488 | * | |
9489 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
9490 | * that it should release a PCI device. The could be caused by a | |
9491 | * Hot-Plug event, or because the driver is going to be removed from | |
9492 | * memory. | |
9493 | **/ | |
9f9a12f8 | 9494 | static void ixgbe_remove(struct pci_dev *pdev) |
9a799d71 | 9495 | { |
c60fbb00 | 9496 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
0fb6a55c | 9497 | struct net_device *netdev; |
b5b2ffc0 | 9498 | bool disable_dev; |
9a799d71 | 9499 | |
0fb6a55c ET |
9500 | /* if !adapter then we already cleaned up in probe */ |
9501 | if (!adapter) | |
9502 | return; | |
9503 | ||
9504 | netdev = adapter->netdev; | |
00949167 | 9505 | ixgbe_dbg_adapter_exit(adapter); |
00949167 | 9506 | |
09f40aed | 9507 | set_bit(__IXGBE_REMOVING, &adapter->state); |
7086400d | 9508 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 9509 | |
3a6a4eda | 9510 | |
5dd2d332 | 9511 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
9512 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
9513 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
9514 | dca_remove_requester(&pdev->dev); | |
9de7605e MR |
9515 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
9516 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
bd0362dd JC |
9517 | } |
9518 | ||
9519 | #endif | |
1210982b | 9520 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d | 9521 | ixgbe_sysfs_exit(adapter); |
1210982b | 9522 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 9523 | |
0365e6e4 PW |
9524 | /* remove the added san mac */ |
9525 | ixgbe_del_sanmac_netdev(netdev); | |
9526 | ||
da36b647 | 9527 | #ifdef CONFIG_PCI_IOV |
7837e286 | 9528 | ixgbe_disable_sriov(adapter); |
da36b647 | 9529 | #endif |
6b010e9b AW |
9530 | if (netdev->reg_state == NETREG_REGISTERED) |
9531 | unregister_netdev(netdev); | |
9532 | ||
7a921c93 | 9533 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 9534 | |
021230d4 | 9535 | ixgbe_release_hw_control(adapter); |
9a799d71 | 9536 | |
2b1588c3 AD |
9537 | #ifdef CONFIG_DCB |
9538 | kfree(adapter->ixgbe_ieee_pfc); | |
9539 | kfree(adapter->ixgbe_ieee_ets); | |
9540 | ||
9541 | #endif | |
2a1a091c | 9542 | iounmap(adapter->io_addr); |
9ce77666 | 9543 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 9544 | IORESOURCE_MEM)); |
9a799d71 | 9545 | |
849c4542 | 9546 | e_dev_info("complete\n"); |
021230d4 | 9547 | |
5d7daa35 | 9548 | kfree(adapter->mac_table); |
b5b2ffc0 | 9549 | disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); |
9a799d71 AK |
9550 | free_netdev(netdev); |
9551 | ||
19d5afd4 | 9552 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 9553 | |
b5b2ffc0 | 9554 | if (disable_dev) |
41c62843 | 9555 | pci_disable_device(pdev); |
9a799d71 AK |
9556 | } |
9557 | ||
9558 | /** | |
9559 | * ixgbe_io_error_detected - called when PCI error is detected | |
9560 | * @pdev: Pointer to PCI device | |
9561 | * @state: The current pci connection state | |
9562 | * | |
9563 | * This function is called after a PCI bus error affecting | |
9564 | * this device has been detected. | |
9565 | */ | |
9566 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 9567 | pci_channel_state_t state) |
9a799d71 | 9568 | { |
c60fbb00 AD |
9569 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
9570 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 9571 | |
83c61fa9 | 9572 | #ifdef CONFIG_PCI_IOV |
14438464 | 9573 | struct ixgbe_hw *hw = &adapter->hw; |
83c61fa9 GR |
9574 | struct pci_dev *bdev, *vfdev; |
9575 | u32 dw0, dw1, dw2, dw3; | |
9576 | int vf, pos; | |
9577 | u16 req_id, pf_func; | |
9578 | ||
9579 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
9580 | adapter->num_vfs == 0) | |
9581 | goto skip_bad_vf_detection; | |
9582 | ||
9583 | bdev = pdev->bus->self; | |
62f87c0e | 9584 | while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) |
83c61fa9 GR |
9585 | bdev = bdev->bus->self; |
9586 | ||
9587 | if (!bdev) | |
9588 | goto skip_bad_vf_detection; | |
9589 | ||
9590 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
9591 | if (!pos) | |
9592 | goto skip_bad_vf_detection; | |
9593 | ||
14438464 MR |
9594 | dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); |
9595 | dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); | |
9596 | dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); | |
9597 | dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); | |
9598 | if (ixgbe_removed(hw->hw_addr)) | |
9599 | goto skip_bad_vf_detection; | |
83c61fa9 GR |
9600 | |
9601 | req_id = dw1 >> 16; | |
9602 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
9603 | if (!(req_id & 0x0080)) | |
9604 | goto skip_bad_vf_detection; | |
9605 | ||
9606 | pf_func = req_id & 0x01; | |
9607 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
9608 | unsigned int device_id; | |
9609 | ||
9610 | vf = (req_id & 0x7F) >> 1; | |
9611 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
9612 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
9613 | "%8.8x\tdw3: %8.8x\n", | |
9614 | dw0, dw1, dw2, dw3); | |
9615 | switch (adapter->hw.mac.type) { | |
9616 | case ixgbe_mac_82599EB: | |
9617 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
9618 | break; | |
9619 | case ixgbe_mac_X540: | |
9620 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
9621 | break; | |
9a75a1ac DS |
9622 | case ixgbe_mac_X550: |
9623 | device_id = IXGBE_DEV_ID_X550_VF; | |
9624 | break; | |
9625 | case ixgbe_mac_X550EM_x: | |
9626 | device_id = IXGBE_DEV_ID_X550EM_X_VF; | |
9627 | break; | |
83c61fa9 GR |
9628 | default: |
9629 | device_id = 0; | |
9630 | break; | |
9631 | } | |
9632 | ||
9633 | /* Find the pci device of the offending VF */ | |
36e90319 | 9634 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); |
83c61fa9 GR |
9635 | while (vfdev) { |
9636 | if (vfdev->devfn == (req_id & 0xFF)) | |
9637 | break; | |
36e90319 | 9638 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
83c61fa9 GR |
9639 | device_id, vfdev); |
9640 | } | |
9641 | /* | |
9642 | * There's a slim chance the VF could have been hot plugged, | |
9643 | * so if it is no longer present we don't need to issue the | |
9644 | * VFLR. Just clean up the AER in that case. | |
9645 | */ | |
9646 | if (vfdev) { | |
9079e416 | 9647 | ixgbe_issue_vf_flr(adapter, vfdev); |
b4fafbe9 GR |
9648 | /* Free device reference count */ |
9649 | pci_dev_put(vfdev); | |
83c61fa9 GR |
9650 | } |
9651 | ||
9652 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
9653 | } | |
9654 | ||
9655 | /* | |
9656 | * Even though the error may have occurred on the other port | |
9657 | * we still need to increment the vf error reference count for | |
9658 | * both ports because the I/O resume function will be called | |
9659 | * for both of them. | |
9660 | */ | |
9661 | adapter->vferr_refcount++; | |
9662 | ||
9663 | return PCI_ERS_RESULT_RECOVERED; | |
9664 | ||
9665 | skip_bad_vf_detection: | |
9666 | #endif /* CONFIG_PCI_IOV */ | |
58cf663f MR |
9667 | if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) |
9668 | return PCI_ERS_RESULT_DISCONNECT; | |
9669 | ||
41c62843 | 9670 | rtnl_lock(); |
9a799d71 AK |
9671 | netif_device_detach(netdev); |
9672 | ||
41c62843 MR |
9673 | if (state == pci_channel_io_perm_failure) { |
9674 | rtnl_unlock(); | |
3044b8d1 | 9675 | return PCI_ERS_RESULT_DISCONNECT; |
41c62843 | 9676 | } |
3044b8d1 | 9677 | |
9a799d71 AK |
9678 | if (netif_running(netdev)) |
9679 | ixgbe_down(adapter); | |
41c62843 MR |
9680 | |
9681 | if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) | |
9682 | pci_disable_device(pdev); | |
9683 | rtnl_unlock(); | |
9a799d71 | 9684 | |
b4617240 | 9685 | /* Request a slot reset. */ |
9a799d71 AK |
9686 | return PCI_ERS_RESULT_NEED_RESET; |
9687 | } | |
9688 | ||
9689 | /** | |
9690 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
9691 | * @pdev: Pointer to PCI device | |
9692 | * | |
9693 | * Restart the card from scratch, as if from a cold-boot. | |
9694 | */ | |
9695 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
9696 | { | |
c60fbb00 | 9697 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
9698 | pci_ers_result_t result; |
9699 | int err; | |
9a799d71 | 9700 | |
9ce77666 | 9701 | if (pci_enable_device_mem(pdev)) { |
396e799c | 9702 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
9703 | result = PCI_ERS_RESULT_DISCONNECT; |
9704 | } else { | |
4e857c58 | 9705 | smp_mb__before_atomic(); |
41c62843 | 9706 | clear_bit(__IXGBE_DISABLED, &adapter->state); |
0391bbe3 | 9707 | adapter->hw.hw_addr = adapter->io_addr; |
6fabd715 PWJ |
9708 | pci_set_master(pdev); |
9709 | pci_restore_state(pdev); | |
c0e1f68b | 9710 | pci_save_state(pdev); |
9a799d71 | 9711 | |
dd4d8ca6 | 9712 | pci_wake_from_d3(pdev, false); |
9a799d71 | 9713 | |
6fabd715 | 9714 | ixgbe_reset(adapter); |
88512539 | 9715 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
9716 | result = PCI_ERS_RESULT_RECOVERED; |
9717 | } | |
9718 | ||
9719 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
9720 | if (err) { | |
849c4542 ET |
9721 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
9722 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
9723 | /* non-fatal, continue */ |
9724 | } | |
9a799d71 | 9725 | |
6fabd715 | 9726 | return result; |
9a799d71 AK |
9727 | } |
9728 | ||
9729 | /** | |
9730 | * ixgbe_io_resume - called when traffic can start flowing again. | |
9731 | * @pdev: Pointer to PCI device | |
9732 | * | |
9733 | * This callback is called when the error recovery driver tells us that | |
9734 | * its OK to resume normal operation. | |
9735 | */ | |
9736 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
9737 | { | |
c60fbb00 AD |
9738 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
9739 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 9740 | |
83c61fa9 GR |
9741 | #ifdef CONFIG_PCI_IOV |
9742 | if (adapter->vferr_refcount) { | |
9743 | e_info(drv, "Resuming after VF err\n"); | |
9744 | adapter->vferr_refcount--; | |
9745 | return; | |
9746 | } | |
9747 | ||
9748 | #endif | |
c7ccde0f AD |
9749 | if (netif_running(netdev)) |
9750 | ixgbe_up(adapter); | |
9a799d71 AK |
9751 | |
9752 | netif_device_attach(netdev); | |
9a799d71 AK |
9753 | } |
9754 | ||
3646f0e5 | 9755 | static const struct pci_error_handlers ixgbe_err_handler = { |
9a799d71 AK |
9756 | .error_detected = ixgbe_io_error_detected, |
9757 | .slot_reset = ixgbe_io_slot_reset, | |
9758 | .resume = ixgbe_io_resume, | |
9759 | }; | |
9760 | ||
9761 | static struct pci_driver ixgbe_driver = { | |
9762 | .name = ixgbe_driver_name, | |
9763 | .id_table = ixgbe_pci_tbl, | |
9764 | .probe = ixgbe_probe, | |
9f9a12f8 | 9765 | .remove = ixgbe_remove, |
9a799d71 AK |
9766 | #ifdef CONFIG_PM |
9767 | .suspend = ixgbe_suspend, | |
9768 | .resume = ixgbe_resume, | |
9769 | #endif | |
9770 | .shutdown = ixgbe_shutdown, | |
da36b647 | 9771 | .sriov_configure = ixgbe_pci_sriov_configure, |
9a799d71 AK |
9772 | .err_handler = &ixgbe_err_handler |
9773 | }; | |
9774 | ||
9775 | /** | |
9776 | * ixgbe_init_module - Driver Registration Routine | |
9777 | * | |
9778 | * ixgbe_init_module is the first routine called when the driver is | |
9779 | * loaded. All it does is register with the PCI subsystem. | |
9780 | **/ | |
9781 | static int __init ixgbe_init_module(void) | |
9782 | { | |
9783 | int ret; | |
c7689578 | 9784 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 9785 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 9786 | |
780484d8 MR |
9787 | ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); |
9788 | if (!ixgbe_wq) { | |
9789 | pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); | |
9790 | return -ENOMEM; | |
9791 | } | |
9792 | ||
00949167 | 9793 | ixgbe_dbg_init(); |
00949167 | 9794 | |
f01fc1a8 JK |
9795 | ret = pci_register_driver(&ixgbe_driver); |
9796 | if (ret) { | |
f01fc1a8 | 9797 | ixgbe_dbg_exit(); |
f01fc1a8 JK |
9798 | return ret; |
9799 | } | |
9800 | ||
5dd2d332 | 9801 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 9802 | dca_register_notify(&dca_notifier); |
bd0362dd | 9803 | #endif |
5dd2d332 | 9804 | |
f01fc1a8 | 9805 | return 0; |
9a799d71 | 9806 | } |
b4617240 | 9807 | |
9a799d71 AK |
9808 | module_init(ixgbe_init_module); |
9809 | ||
9810 | /** | |
9811 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
9812 | * | |
9813 | * ixgbe_exit_module is called just before the driver is removed | |
9814 | * from memory. | |
9815 | **/ | |
9816 | static void __exit ixgbe_exit_module(void) | |
9817 | { | |
5dd2d332 | 9818 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
9819 | dca_unregister_notify(&dca_notifier); |
9820 | #endif | |
9a799d71 | 9821 | pci_unregister_driver(&ixgbe_driver); |
00949167 | 9822 | |
00949167 | 9823 | ixgbe_dbg_exit(); |
780484d8 MR |
9824 | if (ixgbe_wq) { |
9825 | destroy_workqueue(ixgbe_wq); | |
9826 | ixgbe_wq = NULL; | |
9827 | } | |
9a799d71 | 9828 | } |
bd0362dd | 9829 | |
5dd2d332 | 9830 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 9831 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 9832 | void *p) |
bd0362dd JC |
9833 | { |
9834 | int ret_val; | |
9835 | ||
9836 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 9837 | __ixgbe_notify_dca); |
bd0362dd JC |
9838 | |
9839 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
9840 | } | |
b453368d | 9841 | |
5dd2d332 | 9842 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 9843 | |
9a799d71 AK |
9844 | module_exit(ixgbe_exit_module); |
9845 | ||
9846 | /* ixgbe_main.c */ |