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e1000: add byte queue limits
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
7086400d
AD		 154static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155{
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159}
160
161static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162{
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
52f33af8 165 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168}
169
dcd79aeb
TI		 170struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173};
174
175static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205};
206
207
208/*
209 * ixgbe_regdump - register printout routine
210 */
211static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212{
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
c7689578 275 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 282 pr_err("%-15s", rname);
dcd79aeb 283 for (j = 0; j < 8; j++)
c7689578
JP		 284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
dcd79aeb
TI		 286 }
287
288}
289
290/*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293static void ixgbe_dump(struct ixgbe_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
729739b7 300 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 315 pr_info("Device Name state "
dcd79aeb 316 "trans_start last_rx\n");
c7689578
JP		 317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
dcd79aeb
TI		 322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 326 pr_info(" Register Name Value\n");
dcd79aeb
TI		 327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
c7689578
JP		 368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 377 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 378 u0 = (struct my_u0 *)tx_desc;
c7689578 379 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 380 " %04X %p %016llX %p", i,
dcd79aeb
TI		 381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
729739b7
AD		 383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
dcd79aeb
TI		 388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
c7689578 390 pr_cont(" NTC/U\n");
dcd79aeb 391 else if (i == tx_ring->next_to_use)
c7689578 392 pr_cont(" NTU\n");
dcd79aeb 393 else if (i == tx_ring->next_to_clean)
c7689578 394 pr_cont(" NTC\n");
dcd79aeb 395 else
c7689578 396 pr_cont("\n");
dcd79aeb
TI		 397
398 if (netif_msg_pktdata(adapter) &&
9c50c035 399 tx_buffer->skb)
dcd79aeb
TI		 400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035 402 tx_buffer->skb->data,
729739b7
AD		 403 dma_unmap_len(tx_buffer, len),
404 true);
dcd79aeb
TI		 405 }
406 }
407
408 /* Print RX Rings Summary */
409rx_ring_summary:
410 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 411 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 412 for (n = 0; n < adapter->num_rx_queues; n++) {
413 rx_ring = adapter->rx_ring[n];
c7689578
JP		 414 pr_info("%5d %5X %5X\n",
415 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 416 }
417
418 /* Print RX Rings */
419 if (!netif_msg_rx_status(adapter))
420 goto exit;
421
422 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
423
424 /* Advanced Receive Descriptor (Read) Format
425 * 63 1 0
426 * +-----------------------------------------------------+
427 * 0 | Packet Buffer Address [63:1] |A0/NSE|
428 * +----------------------------------------------+------+
429 * 8 | Header Buffer Address [63:1] | DD |
430 * +-----------------------------------------------------+
431 *
432 *
433 * Advanced Receive Descriptor (Write-Back) Format
434 *
435 * 63 48 47 32 31 30 21 20 16 15 4 3 0
436 * +------------------------------------------------------+
437 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
438 * | Checksum Ident | | | | Type | Type |
439 * +------------------------------------------------------+
440 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
441 * +------------------------------------------------------+
442 * 63 48 47 32 31 20 19 0
443 */
444 for (n = 0; n < adapter->num_rx_queues; n++) {
445 rx_ring = adapter->rx_ring[n];
c7689578
JP		 446 pr_info("------------------------------------\n");
447 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
448 pr_info("------------------------------------\n");
449 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 450 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
451 "<-- Adv Rx Read format\n");
c7689578 452 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 453 "[vl er S cks ln] ---------------- [bi->skb] "
454 "<-- Adv Rx Write-Back format\n");
455
456 for (i = 0; i < rx_ring->count; i++) {
457 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 458 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 459 u0 = (struct my_u0 *)rx_desc;
460 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
461 if (staterr & IXGBE_RXD_STAT_DD) {
462 /* Descriptor Done */
c7689578 463 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 464 "%016llX ---------------- %p", i,
465 le64_to_cpu(u0->a),
466 le64_to_cpu(u0->b),
467 rx_buffer_info->skb);
468 } else {
c7689578 469 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 470 "%016llX %016llX %p", i,
471 le64_to_cpu(u0->a),
472 le64_to_cpu(u0->b),
473 (u64)rx_buffer_info->dma,
474 rx_buffer_info->skb);
475
9c50c035
ET		 476 if (netif_msg_pktdata(adapter) &&
477 rx_buffer_info->dma) {
dcd79aeb
TI		 478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 480 page_address(rx_buffer_info->page) +
481 rx_buffer_info->page_offset,
f800326d 482 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
49ce9c2c 520/**
e8e26350
PW		 521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
729739b7
AD		 592void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
729739b7
AD		 595 if (tx_buffer->skb) {
596 dev_kfree_skb_any(tx_buffer->skb);
597 if (dma_unmap_len(tx_buffer, len))
d3d00239 598 dma_unmap_single(ring->dev,
729739b7
AD		 599 dma_unmap_addr(tx_buffer, dma),
600 dma_unmap_len(tx_buffer, len),
601 DMA_TO_DEVICE);
602 } else if (dma_unmap_len(tx_buffer, len)) {
603 dma_unmap_page(ring->dev,
604 dma_unmap_addr(tx_buffer, dma),
605 dma_unmap_len(tx_buffer, len),
606 DMA_TO_DEVICE);
e5a43549 607 }
729739b7
AD		 608 tx_buffer->next_to_watch = NULL;
609 tx_buffer->skb = NULL;
610 dma_unmap_len_set(tx_buffer, len, 0);
611 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 612}
613
943561d3 614static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 615{
616 struct ixgbe_hw *hw = &adapter->hw;
617 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 618 int i;
943561d3 619 u32 data;
c84d324c 620
943561d3
AD		 621 if ((hw->fc.current_mode != ixgbe_fc_full) &&
622 (hw->fc.current_mode != ixgbe_fc_rx_pause))
623 return;
c84d324c 624
943561d3
AD		 625 switch (hw->mac.type) {
626 case ixgbe_mac_82598EB:
627 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
628 break;
629 default:
630 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
631 }
632 hwstats->lxoffrxc += data;
c84d324c 633
943561d3
AD		 634 /* refill credits (no tx hang) if we received xoff */
635 if (!data)
c84d324c 636 return;
943561d3
AD		 637
638 for (i = 0; i < adapter->num_tx_queues; i++)
639 clear_bit(__IXGBE_HANG_CHECK_ARMED,
640 &adapter->tx_ring[i]->state);
641}
642
643static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
644{
645 struct ixgbe_hw *hw = &adapter->hw;
646 struct ixgbe_hw_stats *hwstats = &adapter->stats;
647 u32 xoff[8] = {0};
648 int i;
649 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
650
651 if (adapter->ixgbe_ieee_pfc)
652 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
653
654 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
655 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 656 return;
943561d3 657 }
c84d324c
JF		 658
659 /* update stats for each tc, only valid with PFC enabled */
660 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
661 switch (hw->mac.type) {
662 case ixgbe_mac_82598EB:
663 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 664 break;
c84d324c
JF		 665 default:
666 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 667 }
c84d324c
JF		 668 hwstats->pxoffrxc[i] += xoff[i];
669 }
670
671 /* disarm tx queues that have received xoff frames */
672 for (i = 0; i < adapter->num_tx_queues; i++) {
673 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 674 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 675
676 if (xoff[tc])
677 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 678 }
26f23d82
YZ		 679}
680
c84d324c 681static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 682{
7d7ce682 683 return ring->stats.packets;
c84d324c
JF		 684}
685
686static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
687{
688 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 689 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 690
c84d324c
JF		 691 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
692 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
693
694 if (head != tail)
695 return (head < tail) ?
696 tail - head : (tail + ring->count - head);
697
698 return 0;
699}
700
701static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
702{
703 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
704 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
705 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
706 bool ret = false;
707
7d637bcc 708 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 709
710 /*
711 * Check for a hung queue, but be thorough. This verifies
712 * that a transmit has been completed since the previous
713 * check AND there is at least one packet pending. The
714 * ARMED bit is set to indicate a potential hang. The
715 * bit is cleared if a pause frame is received to remove
716 * false hang detection due to PFC or 802.3x frames. By
717 * requiring this to fail twice we avoid races with
718 * pfc clearing the ARMED bit and conditions where we
719 * run the check_tx_hang logic with a transmit completion
720 * pending but without time to complete it yet.
721 */
722 if ((tx_done_old == tx_done) && tx_pending) {
723 /* make sure it is true for two checks in a row */
724 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
725 &tx_ring->state);
726 } else {
727 /* update completed stats and continue */
728 tx_ring->tx_stats.tx_done_old = tx_done;
729 /* reset the countdown */
730 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 731 }
732
c84d324c 733 return ret;
9a799d71
AK		 734}
735
c83c6cbd
AD		 736/**
737 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
738 * @adapter: driver private struct
739 **/
740static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
741{
742
743 /* Do the reset outside of interrupt context */
744 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
745 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
746 ixgbe_service_event_schedule(adapter);
747 }
748}
e01c31a5 749
9a799d71
AK		 750/**
751 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 752 * @q_vector: structure containing interrupt and ring information
e01c31a5 753 * @tx_ring: tx ring to clean
9a799d71 754 **/
fe49f04a 755static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 756 struct ixgbe_ring *tx_ring)
9a799d71 757{
fe49f04a 758 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 759 struct ixgbe_tx_buffer *tx_buffer;
760 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 761 unsigned int total_bytes = 0, total_packets = 0;
59224555 762 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 763 unsigned int i = tx_ring->next_to_clean;
764
765 if (test_bit(__IXGBE_DOWN, &adapter->state))
766 return true;
9a799d71 767
d3d00239 768 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 769 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 770 i -= tx_ring->count;
12207e49 771
729739b7 772 do {
d3d00239
AD		 773 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
774
775 /* if next_to_watch is not set then there is no work pending */
776 if (!eop_desc)
777 break;
778
7f83a9e6
AD		 779 /* prevent any other reads prior to eop_desc */
780 rmb();
781
d3d00239
AD		 782 /* if DD is not set pending work has not been completed */
783 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
784 break;
8ad494b0 785
d3d00239
AD		 786 /* clear next_to_watch to prevent false hangs */
787 tx_buffer->next_to_watch = NULL;
8ad494b0 788
091a6246
AD		 789 /* update the statistics for this packet */
790 total_bytes += tx_buffer->bytecount;
791 total_packets += tx_buffer->gso_segs;
792
3a6a4eda 793#ifdef CONFIG_IXGBE_PTP
0ede4a60
JK		 794 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
795 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
3a6a4eda 796#endif
0ede4a60 797
fd0db0ed
AD		 798 /* free the skb */
799 dev_kfree_skb_any(tx_buffer->skb);
800
729739b7
AD		 801 /* unmap skb header data */
802 dma_unmap_single(tx_ring->dev,
803 dma_unmap_addr(tx_buffer, dma),
804 dma_unmap_len(tx_buffer, len),
805 DMA_TO_DEVICE);
806
fd0db0ed
AD		 807 /* clear tx_buffer data */
808 tx_buffer->skb = NULL;
729739b7 809 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 810
729739b7
AD		 811 /* unmap remaining buffers */
812 while (tx_desc != eop_desc) {
d3d00239
AD		 813 tx_buffer++;
814 tx_desc++;
8ad494b0 815 i++;
729739b7
AD		 816 if (unlikely(!i)) {
817 i -= tx_ring->count;
d3d00239 818 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 819 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 820 }
e01c31a5 821
729739b7
AD		 822 /* unmap any remaining paged data */
823 if (dma_unmap_len(tx_buffer, len)) {
824 dma_unmap_page(tx_ring->dev,
825 dma_unmap_addr(tx_buffer, dma),
826 dma_unmap_len(tx_buffer, len),
827 DMA_TO_DEVICE);
828 dma_unmap_len_set(tx_buffer, len, 0);
829 }
830 }
831
832 /* move us one more past the eop_desc for start of next pkt */
833 tx_buffer++;
834 tx_desc++;
835 i++;
836 if (unlikely(!i)) {
837 i -= tx_ring->count;
838 tx_buffer = tx_ring->tx_buffer_info;
839 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
840 }
841
842 /* issue prefetch for next Tx descriptor */
843 prefetch(tx_desc);
12207e49 844
729739b7
AD		 845 /* update budget accounting */
846 budget--;
847 } while (likely(budget));
848
849 i += tx_ring->count;
9a799d71 850 tx_ring->next_to_clean = i;
d3d00239 851 u64_stats_update_begin(&tx_ring->syncp);
b953799e 852 tx_ring->stats.bytes += total_bytes;
bd198058 853 tx_ring->stats.packets += total_packets;
d3d00239 854 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 855 q_vector->tx.total_bytes += total_bytes;
856 q_vector->tx.total_packets += total_packets;
b953799e 857
c84d324c
JF		 858 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
859 /* schedule immediate reset if we believe we hung */
860 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 861 e_err(drv, "Detected Tx Unit Hang\n"
862 " Tx Queue <%d>\n"
863 " TDH, TDT <%x>, <%x>\n"
864 " next_to_use <%x>\n"
865 " next_to_clean <%x>\n"
866 "tx_buffer_info[next_to_clean]\n"
867 " time_stamp <%lx>\n"
868 " jiffies <%lx>\n",
869 tx_ring->queue_index,
870 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
871 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 872 tx_ring->next_to_use, i,
873 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 874
875 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
876
877 e_info(probe,
878 "tx hang %d detected on queue %d, resetting adapter\n",
879 adapter->tx_timeout_count + 1, tx_ring->queue_index);
880
b953799e 881 /* schedule immediate reset if we believe we hung */
c83c6cbd 882 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 883
884 /* the adapter is about to reset, no point in enabling stuff */
59224555 885 return true;
b953799e 886 }
9a799d71 887
b2d96e0a
AD		 888 netdev_tx_completed_queue(txring_txq(tx_ring),
889 total_packets, total_bytes);
890
e092be60 891#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 892 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 893 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 894 /* Make sure that anybody stopping the queue after this
895 * sees the new next_to_clean.
896 */
897 smp_mb();
729739b7
AD		 898 if (__netif_subqueue_stopped(tx_ring->netdev,
899 tx_ring->queue_index)
900 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
901 netif_wake_subqueue(tx_ring->netdev,
902 tx_ring->queue_index);
5b7da515 903 ++tx_ring->tx_stats.restart_queue;
30eba97a 904 }
e092be60 905 }
9a799d71 906
59224555 907 return !!budget;
9a799d71
AK		 908}
909
5dd2d332 910#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 911static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
912 struct ixgbe_ring *tx_ring,
33cf09c9 913 int cpu)
bd0362dd 914{
33cf09c9 915 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 916 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
917 u16 reg_offset;
33cf09c9 918
33cf09c9
AD		 919 switch (hw->mac.type) {
920 case ixgbe_mac_82598EB:
bdda1a61 921 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 922 break;
923 case ixgbe_mac_82599EB:
b93a2226 924 case ixgbe_mac_X540:
bdda1a61
AD		 925 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
926 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 927 break;
928 default:
bdda1a61
AD		 929 /* for unknown hardware do not write register */
930 return;
bd0362dd 931 }
bdda1a61
AD		 932
933 /*
934 * We can enable relaxed ordering for reads, but not writes when
935 * DCA is enabled. This is due to a known issue in some chipsets
936 * which will cause the DCA tag to be cleared.
937 */
938 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
939 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
940 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
941
942 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 943}
944
bdda1a61
AD		 945static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
946 struct ixgbe_ring *rx_ring,
33cf09c9 947 int cpu)
bd0362dd 948{
33cf09c9 949 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 950 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
951 u8 reg_idx = rx_ring->reg_idx;
952
33cf09c9
AD		 953
954 switch (hw->mac.type) {
33cf09c9 955 case ixgbe_mac_82599EB:
b93a2226 956 case ixgbe_mac_X540:
bdda1a61 957 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 958 break;
959 default:
960 break;
961 }
bdda1a61
AD		 962
963 /*
964 * We can enable relaxed ordering for reads, but not writes when
965 * DCA is enabled. This is due to a known issue in some chipsets
966 * which will cause the DCA tag to be cleared.
967 */
968 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
969 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
970 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
971
972 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 973}
974
975static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
976{
977 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 978 struct ixgbe_ring *ring;
bd0362dd 979 int cpu = get_cpu();
bd0362dd 980
33cf09c9
AD		 981 if (q_vector->cpu == cpu)
982 goto out_no_update;
983
a557928e 984 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 985 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 986
a557928e 987 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 988 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 989
990 q_vector->cpu = cpu;
991out_no_update:
bd0362dd
JC		 992 put_cpu();
993}
994
995static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
996{
997 int i;
998
999 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000 return;
1001
e35ec126
AD		 1002 /* always use CB2 mode, difference is masked in the CB driver */
1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
49c7ffbe 1005 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1006 adapter->q_vector[i]->cpu = -1;
1007 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1008 }
1009}
1010
1011static int __ixgbe_notify_dca(struct device *dev, void *data)
1012{
c60fbb00 1013 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1014 unsigned long event = *(unsigned long *)data;
1015
2a72c31e 1016 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1017 return 0;
1018
bd0362dd
JC		 1019 switch (event) {
1020 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1021 /* if we're already enabled, don't do it again */
1022 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1023 break;
652f093f 1024 if (dca_add_requester(dev) == 0) {
96b0e0f6 1025 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1026 ixgbe_setup_dca(adapter);
1027 break;
1028 }
1029 /* Fall Through since DCA is disabled. */
1030 case DCA_PROVIDER_REMOVE:
1031 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1032 dca_remove_requester(dev);
1033 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1035 }
1036 break;
1037 }
1038
652f093f 1039 return 0;
bd0362dd 1040}
67a74ee2 1041
bdda1a61 1042#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1043static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1044 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1045 struct sk_buff *skb)
1046{
8a0da21b
AD		 1047 if (ring->netdev->features & NETIF_F_RXHASH)
1048 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1049}
1050
f800326d 1051#ifdef IXGBE_FCOE
ff886dfc
AD		 1052/**
1053 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1054 * @ring: structure containing ring specific data
ff886dfc
AD		 1055 * @rx_desc: advanced rx descriptor
1056 *
1057 * Returns : true if it is FCoE pkt
1058 */
57efd44c 1059static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1060 union ixgbe_adv_rx_desc *rx_desc)
1061{
1062 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1063
57efd44c 1064 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1065 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1066 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1067 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1068}
1069
f800326d 1070#endif /* IXGBE_FCOE */
e59bd25d
AV		 1071/**
1072 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1073 * @ring: structure containing ring specific data
1074 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1075 * @skb: skb currently being received and modified
1076 **/
8a0da21b 1077static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1078 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1079 struct sk_buff *skb)
9a799d71 1080{
8a0da21b 1081 skb_checksum_none_assert(skb);
9a799d71 1082
712744be 1083 /* Rx csum disabled */
8a0da21b 1084 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1085 return;
e59bd25d
AV		 1086
1087 /* if IP and error */
f56e0cb1
AD		 1088 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1089 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1090 ring->rx_stats.csum_err++;
9a799d71
AK		 1091 return;
1092 }
e59bd25d 1093
f56e0cb1 1094 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1095 return;
1096
f56e0cb1 1097 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1098 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1099
1100 /*
1101 * 82599 errata, UDP frames with a 0 checksum can be marked as
1102 * checksum errors.
1103 */
8a0da21b
AD		 1104 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1105 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1106 return;
1107
8a0da21b 1108 ring->rx_stats.csum_err++;
e59bd25d
AV		 1109 return;
1110 }
1111
9a799d71 1112 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1113 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1114}
1115
84ea2591 1116static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1117{
f56e0cb1 1118 rx_ring->next_to_use = val;
f800326d
AD		 1119
1120 /* update next to alloc since we have filled the ring */
1121 rx_ring->next_to_alloc = val;
e8e26350
PW		 1122 /*
1123 * Force memory writes to complete before letting h/w
1124 * know there are new descriptors to fetch. (Only
1125 * applicable for weak-ordered memory model archs,
1126 * such as IA-64).
1127 */
1128 wmb();
84ea2591 1129 writel(val, rx_ring->tail);
e8e26350
PW		 1130}
1131
f990b79b
AD		 1132static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1133 struct ixgbe_rx_buffer *bi)
1134{
1135 struct page *page = bi->page;
f800326d 1136 dma_addr_t dma = bi->dma;
f990b79b 1137
f800326d
AD		 1138 /* since we are recycling buffers we should seldom need to alloc */
1139 if (likely(dma))
f990b79b
AD		 1140 return true;
1141
f800326d
AD		 1142 /* alloc new page for storage */
1143 if (likely(!page)) {
0614002b
MG		 1144 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1145 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1146 if (unlikely(!page)) {
1147 rx_ring->rx_stats.alloc_rx_page_failed++;
1148 return false;
1149 }
f800326d 1150 bi->page = page;
f990b79b
AD		 1151 }
1152
f800326d
AD		 1153 /* map page for use */
1154 dma = dma_map_page(rx_ring->dev, page, 0,
1155 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1156
1157 /*
1158 * if mapping failed free memory back to system since
1159 * there isn't much point in holding memory we can't use
1160 */
1161 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1162 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1163 bi->page = NULL;
f990b79b 1164
f990b79b
AD		 1165 rx_ring->rx_stats.alloc_rx_page_failed++;
1166 return false;
1167 }
1168
f800326d 1169 bi->dma = dma;
afaa9459 1170 bi->page_offset = 0;
f800326d 1171
f990b79b
AD		 1172 return true;
1173}
1174
9a799d71 1175/**
f990b79b 1176 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1177 * @rx_ring: ring to place buffers on
1178 * @cleaned_count: number of buffers to replace
9a799d71 1179 **/
fc77dc3c 1180void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1181{
9a799d71 1182 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1183 struct ixgbe_rx_buffer *bi;
d5f398ed 1184 u16 i = rx_ring->next_to_use;
9a799d71 1185
f800326d
AD		 1186 /* nothing to do */
1187 if (!cleaned_count)
fc77dc3c
AD		 1188 return;
1189
e4f74028 1190 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1191 bi = &rx_ring->rx_buffer_info[i];
1192 i -= rx_ring->count;
9a799d71 1193
f800326d
AD		 1194 do {
1195 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1196 break;
d5f398ed 1197
f800326d
AD		 1198 /*
1199 * Refresh the desc even if buffer_addrs didn't change
1200 * because each write-back erases this info.
1201 */
1202 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1203
f990b79b
AD		 1204 rx_desc++;
1205 bi++;
9a799d71 1206 i++;
f990b79b 1207 if (unlikely(!i)) {
e4f74028 1208 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1209 bi = rx_ring->rx_buffer_info;
1210 i -= rx_ring->count;
1211 }
1212
1213 /* clear the hdr_addr for the next_to_use descriptor */
1214 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1215
1216 cleaned_count--;
1217 } while (cleaned_count);
7c6e0a43 1218
f990b79b
AD		 1219 i += rx_ring->count;
1220
f56e0cb1 1221 if (rx_ring->next_to_use != i)
84ea2591 1222 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1223}
1224
1d2024f6
AD		 1225/**
1226 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1227 * @data: pointer to the start of the headers
1228 * @max_len: total length of section to find headers in
1229 *
1230 * This function is meant to determine the length of headers that will
1231 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1232 * motivation of doing this is to only perform one pull for IPv4 TCP
1233 * packets so that we can do basic things like calculating the gso_size
1234 * based on the average data per packet.
1235 **/
1236static unsigned int ixgbe_get_headlen(unsigned char *data,
1237 unsigned int max_len)
1238{
1239 union {
1240 unsigned char *network;
1241 /* l2 headers */
1242 struct ethhdr *eth;
1243 struct vlan_hdr *vlan;
1244 /* l3 headers */
1245 struct iphdr *ipv4;
1246 } hdr;
1247 __be16 protocol;
1248 u8 nexthdr = 0; /* default to not TCP */
1249 u8 hlen;
1250
1251 /* this should never happen, but better safe than sorry */
1252 if (max_len < ETH_HLEN)
1253 return max_len;
1254
1255 /* initialize network frame pointer */
1256 hdr.network = data;
1257
1258 /* set first protocol and move network header forward */
1259 protocol = hdr.eth->h_proto;
1260 hdr.network += ETH_HLEN;
1261
1262 /* handle any vlan tag if present */
1263 if (protocol == __constant_htons(ETH_P_8021Q)) {
1264 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1265 return max_len;
1266
1267 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1268 hdr.network += VLAN_HLEN;
1269 }
1270
1271 /* handle L3 protocols */
1272 if (protocol == __constant_htons(ETH_P_IP)) {
1273 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1274 return max_len;
1275
1276 /* access ihl as a u8 to avoid unaligned access on ia64 */
1277 hlen = (hdr.network[0] & 0x0F) << 2;
1278
1279 /* verify hlen meets minimum size requirements */
1280 if (hlen < sizeof(struct iphdr))
1281 return hdr.network - data;
1282
1283 /* record next protocol */
1284 nexthdr = hdr.ipv4->protocol;
1285 hdr.network += hlen;
f800326d 1286#ifdef IXGBE_FCOE
1d2024f6
AD		 1287 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1288 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1289 return max_len;
1290 hdr.network += FCOE_HEADER_LEN;
1291#endif
1292 } else {
1293 return hdr.network - data;
1294 }
1295
1296 /* finally sort out TCP */
1297 if (nexthdr == IPPROTO_TCP) {
1298 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1299 return max_len;
1300
1301 /* access doff as a u8 to avoid unaligned access on ia64 */
1302 hlen = (hdr.network[12] & 0xF0) >> 2;
1303
1304 /* verify hlen meets minimum size requirements */
1305 if (hlen < sizeof(struct tcphdr))
1306 return hdr.network - data;
1307
1308 hdr.network += hlen;
1309 }
1310
1311 /*
1312 * If everything has gone correctly hdr.network should be the
1313 * data section of the packet and will be the end of the header.
1314 * If not then it probably represents the end of the last recognized
1315 * header.
1316 */
1317 if ((hdr.network - data) < max_len)
1318 return hdr.network - data;
1319 else
1320 return max_len;
1321}
1322
1d2024f6
AD		 1323static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1324 struct sk_buff *skb)
1325{
f800326d 1326 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1327
1328 /* set gso_size to avoid messing up TCP MSS */
1329 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1330 IXGBE_CB(skb)->append_cnt);
1331}
1332
1333static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1334 struct sk_buff *skb)
1335{
1336 /* if append_cnt is 0 then frame is not RSC */
1337 if (!IXGBE_CB(skb)->append_cnt)
1338 return;
1339
1340 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1341 rx_ring->rx_stats.rsc_flush++;
1342
1343 ixgbe_set_rsc_gso_size(rx_ring, skb);
1344
1345 /* gso_size is computed using append_cnt so always clear it last */
1346 IXGBE_CB(skb)->append_cnt = 0;
1347}
1348
8a0da21b
AD		 1349/**
1350 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1351 * @rx_ring: rx descriptor ring packet is being transacted on
1352 * @rx_desc: pointer to the EOP Rx descriptor
1353 * @skb: pointer to current skb being populated
f8212f97 1354 *
8a0da21b
AD		 1355 * This function checks the ring, descriptor, and packet information in
1356 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1357 * other fields within the skb.
f8212f97 1358 **/
8a0da21b
AD		 1359static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1360 union ixgbe_adv_rx_desc *rx_desc,
1361 struct sk_buff *skb)
f8212f97 1362{
43e95f11
JF		 1363 struct net_device *dev = rx_ring->netdev;
1364
8a0da21b
AD		 1365 ixgbe_update_rsc_stats(rx_ring, skb);
1366
1367 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1368
8a0da21b
AD		 1369 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1370
3a6a4eda 1371#ifdef CONFIG_IXGBE_PTP
1d1a79b5 1372 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda
JK		 1373#endif
1374
43e95f11
JF		 1375 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1376 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1377 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1378 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1379 }
1380
8a0da21b 1381 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1382
43e95f11 1383 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1384}
1385
8a0da21b
AD		 1386static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1387 struct sk_buff *skb)
aa80175a 1388{
8a0da21b
AD		 1389 struct ixgbe_adapter *adapter = q_vector->adapter;
1390
1391 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1392 napi_gro_receive(&q_vector->napi, skb);
1393 else
1394 netif_rx(skb);
aa80175a 1395}
43634e82 1396
f800326d
AD		 1397/**
1398 * ixgbe_is_non_eop - process handling of non-EOP buffers
1399 * @rx_ring: Rx ring being processed
1400 * @rx_desc: Rx descriptor for current buffer
1401 * @skb: Current socket buffer containing buffer in progress
1402 *
1403 * This function updates next to clean. If the buffer is an EOP buffer
1404 * this function exits returning false, otherwise it will place the
1405 * sk_buff in the next buffer to be chained and return true indicating
1406 * that this is in fact a non-EOP buffer.
1407 **/
1408static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1409 union ixgbe_adv_rx_desc *rx_desc,
1410 struct sk_buff *skb)
1411{
1412 u32 ntc = rx_ring->next_to_clean + 1;
1413
1414 /* fetch, update, and store next to clean */
1415 ntc = (ntc < rx_ring->count) ? ntc : 0;
1416 rx_ring->next_to_clean = ntc;
1417
1418 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1419
5a02cbd1
AD		 1420 /* update RSC append count if present */
1421 if (ring_is_rsc_enabled(rx_ring)) {
1422 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1423 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1424
1425 if (unlikely(rsc_enabled)) {
1426 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1427
1428 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1429 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1430
5a02cbd1
AD		 1431 /* update ntc based on RSC value */
1432 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1433 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1434 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1435 }
f800326d
AD		 1436 }
1437
5a02cbd1
AD		 1438 /* if we are the last buffer then there is nothing else to do */
1439 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1440 return false;
1441
f800326d
AD		 1442 /* place skb in next buffer to be received */
1443 rx_ring->rx_buffer_info[ntc].skb = skb;
1444 rx_ring->rx_stats.non_eop_descs++;
1445
1446 return true;
1447}
1448
19861ce2
AD		 1449/**
1450 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1451 * @rx_ring: rx descriptor ring packet is being transacted on
1452 * @skb: pointer to current skb being adjusted
1453 *
1454 * This function is an ixgbe specific version of __pskb_pull_tail. The
1455 * main difference between this version and the original function is that
1456 * this function can make several assumptions about the state of things
1457 * that allow for significant optimizations versus the standard function.
1458 * As a result we can do things like drop a frag and maintain an accurate
1459 * truesize for the skb.
1460 */
1461static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1462 struct sk_buff *skb)
1463{
1464 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1465 unsigned char *va;
1466 unsigned int pull_len;
1467
1468 /*
1469 * it is valid to use page_address instead of kmap since we are
1470 * working with pages allocated out of the lomem pool per
1471 * alloc_page(GFP_ATOMIC)
1472 */
1473 va = skb_frag_address(frag);
1474
1475 /*
1476 * we need the header to contain the greater of either ETH_HLEN or
1477 * 60 bytes if the skb->len is less than 60 for skb_pad.
1478 */
cf3fe7ac 1479 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1480
1481 /* align pull length to size of long to optimize memcpy performance */
1482 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1483
1484 /* update all of the pointers */
1485 skb_frag_size_sub(frag, pull_len);
1486 frag->page_offset += pull_len;
1487 skb->data_len -= pull_len;
1488 skb->tail += pull_len;
19861ce2
AD		 1489}
1490
42073d91
AD		 1491/**
1492 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1493 * @rx_ring: rx descriptor ring packet is being transacted on
1494 * @skb: pointer to current skb being updated
1495 *
1496 * This function provides a basic DMA sync up for the first fragment of an
1497 * skb. The reason for doing this is that the first fragment cannot be
1498 * unmapped until we have reached the end of packet descriptor for a buffer
1499 * chain.
1500 */
1501static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1502 struct sk_buff *skb)
1503{
1504 /* if the page was released unmap it, else just sync our portion */
1505 if (unlikely(IXGBE_CB(skb)->page_released)) {
1506 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1507 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1508 IXGBE_CB(skb)->page_released = false;
1509 } else {
1510 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1511
1512 dma_sync_single_range_for_cpu(rx_ring->dev,
1513 IXGBE_CB(skb)->dma,
1514 frag->page_offset,
1515 ixgbe_rx_bufsz(rx_ring),
1516 DMA_FROM_DEVICE);
1517 }
1518 IXGBE_CB(skb)->dma = 0;
1519}
1520
f800326d
AD		 1521/**
1522 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1523 * @rx_ring: rx descriptor ring packet is being transacted on
1524 * @rx_desc: pointer to the EOP Rx descriptor
1525 * @skb: pointer to current skb being fixed
1526 *
1527 * Check for corrupted packet headers caused by senders on the local L2
1528 * embedded NIC switch not setting up their Tx Descriptors right. These
1529 * should be very rare.
1530 *
1531 * Also address the case where we are pulling data in on pages only
1532 * and as such no data is present in the skb header.
1533 *
1534 * In addition if skb is not at least 60 bytes we need to pad it so that
1535 * it is large enough to qualify as a valid Ethernet frame.
1536 *
1537 * Returns true if an error was encountered and skb was freed.
1538 **/
1539static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1540 union ixgbe_adv_rx_desc *rx_desc,
1541 struct sk_buff *skb)
1542{
f800326d 1543 struct net_device *netdev = rx_ring->netdev;
f800326d 1544
f800326d
AD		 1545 /* verify that the packet does not have any known errors */
1546 if (unlikely(ixgbe_test_staterr(rx_desc,
1547 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1548 !(netdev->features & NETIF_F_RXALL))) {
1549 dev_kfree_skb_any(skb);
1550 return true;
1551 }
1552
19861ce2 1553 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1554 if (skb_is_nonlinear(skb))
1555 ixgbe_pull_tail(rx_ring, skb);
f800326d 1556
57efd44c
AD		 1557#ifdef IXGBE_FCOE
1558 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1559 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1560 return false;
1561
1562#endif
f800326d
AD		 1563 /* if skb_pad returns an error the skb was freed */
1564 if (unlikely(skb->len < 60)) {
1565 int pad_len = 60 - skb->len;
1566
1567 if (skb_pad(skb, pad_len))
1568 return true;
1569 __skb_put(skb, pad_len);
1570 }
1571
1572 return false;
1573}
1574
f800326d
AD		 1575/**
1576 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1577 * @rx_ring: rx descriptor ring to store buffers on
1578 * @old_buff: donor buffer to have page reused
1579 *
0549ae20 1580 * Synchronizes page for reuse by the adapter
f800326d
AD		 1581 **/
1582static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1583 struct ixgbe_rx_buffer *old_buff)
1584{
1585 struct ixgbe_rx_buffer *new_buff;
1586 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1587
1588 new_buff = &rx_ring->rx_buffer_info[nta];
1589
1590 /* update, and store next to alloc */
1591 nta++;
1592 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1593
1594 /* transfer page from old buffer to new buffer */
1595 new_buff->page = old_buff->page;
1596 new_buff->dma = old_buff->dma;
0549ae20 1597 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1598
1599 /* sync the buffer for use by the device */
1600 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1601 new_buff->page_offset,
1602 ixgbe_rx_bufsz(rx_ring),
f800326d 1603 DMA_FROM_DEVICE);
f800326d
AD		 1604}
1605
1606/**
1607 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1608 * @rx_ring: rx descriptor ring to transact packets on
1609 * @rx_buffer: buffer containing page to add
1610 * @rx_desc: descriptor containing length of buffer written by hardware
1611 * @skb: sk_buff to place the data into
1612 *
0549ae20
AD		 1613 * This function will add the data contained in rx_buffer->page to the skb.
1614 * This is done either through a direct copy if the data in the buffer is
1615 * less than the skb header size, otherwise it will just attach the page as
1616 * a frag to the skb.
1617 *
1618 * The function will then update the page offset if necessary and return
1619 * true if the buffer can be reused by the adapter.
f800326d 1620 **/
0549ae20 1621static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1622 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1623 union ixgbe_adv_rx_desc *rx_desc,
1624 struct sk_buff *skb)
f800326d 1625{
0549ae20
AD		 1626 struct page *page = rx_buffer->page;
1627 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1628#if (PAGE_SIZE < 8192)
0549ae20 1629 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1630#else
1631 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1632 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1633 ixgbe_rx_bufsz(rx_ring);
1634#endif
0549ae20 1635
cf3fe7ac
AD		 1636 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1637 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1638
1639 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1640
1641 /* we can reuse buffer as-is, just make sure it is local */
1642 if (likely(page_to_nid(page) == numa_node_id()))
1643 return true;
1644
1645 /* this page cannot be reused so discard it */
1646 put_page(page);
1647 return false;
1648 }
1649
0549ae20
AD		 1650 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1651 rx_buffer->page_offset, size, truesize);
1652
09816fbe
AD		 1653 /* avoid re-using remote pages */
1654 if (unlikely(page_to_nid(page) != numa_node_id()))
1655 return false;
1656
1657#if (PAGE_SIZE < 8192)
1658 /* if we are only owner of page we can reuse it */
1659 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1660 return false;
1661
1662 /* flip page offset to other buffer */
1663 rx_buffer->page_offset ^= truesize;
1664
09816fbe
AD		 1665 /*
1666 * since we are the only owner of the page and we need to
1667 * increment it, just set the value to 2 in order to avoid
1668 * an unecessary locked operation
1669 */
1670 atomic_set(&page->_count, 2);
1671#else
1672 /* move offset up to the next cache line */
1673 rx_buffer->page_offset += truesize;
1674
1675 if (rx_buffer->page_offset > last_offset)
1676 return false;
1677
0549ae20
AD		 1678 /* bump ref count on page before it is given to the stack */
1679 get_page(page);
09816fbe 1680#endif
0549ae20
AD		 1681
1682 return true;
f800326d
AD		 1683}
1684
18806c9e
AD		 1685static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1686 union ixgbe_adv_rx_desc *rx_desc)
1687{
1688 struct ixgbe_rx_buffer *rx_buffer;
1689 struct sk_buff *skb;
1690 struct page *page;
1691
1692 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1693 page = rx_buffer->page;
1694 prefetchw(page);
1695
1696 skb = rx_buffer->skb;
1697
1698 if (likely(!skb)) {
1699 void *page_addr = page_address(page) +
1700 rx_buffer->page_offset;
1701
1702 /* prefetch first cache line of first page */
1703 prefetch(page_addr);
1704#if L1_CACHE_BYTES < 128
1705 prefetch(page_addr + L1_CACHE_BYTES);
1706#endif
1707
1708 /* allocate a skb to store the frags */
1709 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1710 IXGBE_RX_HDR_SIZE);
1711 if (unlikely(!skb)) {
1712 rx_ring->rx_stats.alloc_rx_buff_failed++;
1713 return NULL;
1714 }
1715
1716 /*
1717 * we will be copying header into skb->data in
1718 * pskb_may_pull so it is in our interest to prefetch
1719 * it now to avoid a possible cache miss
1720 */
1721 prefetchw(skb->data);
1722
1723 /*
1724 * Delay unmapping of the first packet. It carries the
1725 * header information, HW may still access the header
1726 * after the writeback. Only unmap it when EOP is
1727 * reached
1728 */
1729 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1730 goto dma_sync;
1731
1732 IXGBE_CB(skb)->dma = rx_buffer->dma;
1733 } else {
1734 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1735 ixgbe_dma_sync_frag(rx_ring, skb);
1736
1737dma_sync:
1738 /* we are reusing so sync this buffer for CPU use */
1739 dma_sync_single_range_for_cpu(rx_ring->dev,
1740 rx_buffer->dma,
1741 rx_buffer->page_offset,
1742 ixgbe_rx_bufsz(rx_ring),
1743 DMA_FROM_DEVICE);
1744 }
1745
1746 /* pull page into skb */
1747 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1748 /* hand second half of page back to the ring */
1749 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1750 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1751 /* the page has been released from the ring */
1752 IXGBE_CB(skb)->page_released = true;
1753 } else {
1754 /* we are not reusing the buffer so unmap it */
1755 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1756 ixgbe_rx_pg_size(rx_ring),
1757 DMA_FROM_DEVICE);
1758 }
1759
1760 /* clear contents of buffer_info */
1761 rx_buffer->skb = NULL;
1762 rx_buffer->dma = 0;
1763 rx_buffer->page = NULL;
1764
1765 return skb;
1766}
1767
f800326d
AD		 1768/**
1769 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1770 * @q_vector: structure containing interrupt and ring information
1771 * @rx_ring: rx descriptor ring to transact packets on
1772 * @budget: Total limit on number of packets to process
1773 *
1774 * This function provides a "bounce buffer" approach to Rx interrupt
1775 * processing. The advantage to this is that on systems that have
1776 * expensive overhead for IOMMU access this provides a means of avoiding
1777 * it by maintaining the mapping of the page to the syste.
1778 *
1779 * Returns true if all work is completed without reaching budget
1780 **/
4ff7fb12 1781static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1782 struct ixgbe_ring *rx_ring,
4ff7fb12 1783 int budget)
9a799d71 1784{
d2f4fbe2 1785 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1786#ifdef IXGBE_FCOE
f800326d 1787 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1788 int ddp_bytes = 0;
1789#endif /* IXGBE_FCOE */
f800326d 1790 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1791
f800326d 1792 do {
f800326d
AD		 1793 union ixgbe_adv_rx_desc *rx_desc;
1794 struct sk_buff *skb;
f800326d
AD		 1795
1796 /* return some buffers to hardware, one at a time is too slow */
1797 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1798 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1799 cleaned_count = 0;
1800 }
1801
18806c9e 1802 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 1803
1804 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1805 break;
9a799d71 1806
f800326d
AD		 1807 /*
1808 * This memory barrier is needed to keep us from reading
1809 * any other fields out of the rx_desc until we know the
1810 * RXD_STAT_DD bit is set
1811 */
1812 rmb();
9a799d71 1813
18806c9e
AD		 1814 /* retrieve a buffer from the ring */
1815 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 1816
18806c9e
AD		 1817 /* exit if we failed to retrieve a buffer */
1818 if (!skb)
1819 break;
4c1975d7 1820
9a799d71 1821 cleaned_count++;
f8212f97 1822
f800326d
AD		 1823 /* place incomplete frames back on ring for completion */
1824 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1825 continue;
c267fc16 1826
f800326d
AD		 1827 /* verify the packet layout is correct */
1828 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1829 continue;
9a799d71 1830
d2f4fbe2
AV		 1831 /* probably a little skewed due to removing CRC */
1832 total_rx_bytes += skb->len;
1833 total_rx_packets++;
1834
8a0da21b
AD		 1835 /* populate checksum, timestamp, VLAN, and protocol */
1836 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1837
332d4a7d
YZ		 1838#ifdef IXGBE_FCOE
1839 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1840 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1841 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1842 if (!ddp_bytes) {
1843 dev_kfree_skb_any(skb);
f800326d 1844 continue;
63d635b2 1845 }
3d8fd385 1846 }
f800326d 1847
332d4a7d 1848#endif /* IXGBE_FCOE */
8a0da21b 1849 ixgbe_rx_skb(q_vector, skb);
9a799d71 1850
f800326d 1851 /* update budget accounting */
4ff7fb12 1852 budget--;
f800326d 1853 } while (likely(budget));
9a799d71 1854
3d8fd385
YZ		 1855#ifdef IXGBE_FCOE
1856 /* include DDPed FCoE data */
1857 if (ddp_bytes > 0) {
1858 unsigned int mss;
1859
fc77dc3c 1860 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1861 sizeof(struct fc_frame_header) -
1862 sizeof(struct fcoe_crc_eof);
1863 if (mss > 512)
1864 mss &= ~511;
1865 total_rx_bytes += ddp_bytes;
1866 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1867 }
3d8fd385 1868
f800326d 1869#endif /* IXGBE_FCOE */
c267fc16
AD		 1870 u64_stats_update_begin(&rx_ring->syncp);
1871 rx_ring->stats.packets += total_rx_packets;
1872 rx_ring->stats.bytes += total_rx_bytes;
1873 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1874 q_vector->rx.total_packets += total_rx_packets;
1875 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1876
f800326d
AD		 1877 if (cleaned_count)
1878 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1879
4ff7fb12 1880 return !!budget;
9a799d71
AK		 1881}
1882
9a799d71
AK		 1883/**
1884 * ixgbe_configure_msix - Configure MSI-X hardware
1885 * @adapter: board private structure
1886 *
1887 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1888 * interrupts.
1889 **/
1890static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1891{
021230d4 1892 struct ixgbe_q_vector *q_vector;
49c7ffbe 1893 int v_idx;
021230d4 1894 u32 mask;
9a799d71 1895
8e34d1aa
AD		 1896 /* Populate MSIX to EITR Select */
1897 if (adapter->num_vfs > 32) {
1898 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1900 }
1901
4df10466
JB		 1902 /*
1903 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1904 * corresponding register.
1905 */
49c7ffbe 1906 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1907 struct ixgbe_ring *ring;
7a921c93 1908 q_vector = adapter->q_vector[v_idx];
021230d4 1909
a557928e 1910 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1911 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1912
a557928e 1913 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1914 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1915
d5bf4f67
ET		 1916 if (q_vector->tx.ring && !q_vector->rx.ring) {
1917 /* tx only vector */
1918 if (adapter->tx_itr_setting == 1)
1919 q_vector->itr = IXGBE_10K_ITR;
1920 else
1921 q_vector->itr = adapter->tx_itr_setting;
1922 } else {
1923 /* rx or rx/tx vector */
1924 if (adapter->rx_itr_setting == 1)
1925 q_vector->itr = IXGBE_20K_ITR;
1926 else
1927 q_vector->itr = adapter->rx_itr_setting;
1928 }
021230d4 1929
fe49f04a 1930 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1931 }
1932
bd508178
AD		 1933 switch (adapter->hw.mac.type) {
1934 case ixgbe_mac_82598EB:
e8e26350 1935 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1936 v_idx);
bd508178
AD		 1937 break;
1938 case ixgbe_mac_82599EB:
b93a2226 1939 case ixgbe_mac_X540:
e8e26350 1940 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1941 break;
bd508178
AD		 1942 default:
1943 break;
1944 }
021230d4
AV		 1945 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1946
41fb9248 1947 /* set up to autoclear timer, and the vectors */
021230d4 1948 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1949 mask &= ~(IXGBE_EIMS_OTHER |
1950 IXGBE_EIMS_MAILBOX |
1951 IXGBE_EIMS_LSC);
1952
021230d4 1953 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1954}
1955
f494e8fa
AV		 1956enum latency_range {
1957 lowest_latency = 0,
1958 low_latency = 1,
1959 bulk_latency = 2,
1960 latency_invalid = 255
1961};
1962
1963/**
1964 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1965 * @q_vector: structure containing interrupt and ring information
1966 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1967 *
1968 * Stores a new ITR value based on packets and byte
1969 * counts during the last interrupt. The advantage of per interrupt
1970 * computation is faster updates and more accurate ITR for the current
1971 * traffic pattern. Constants in this function were computed
1972 * based on theoretical maximum wire speed and thresholds were set based
1973 * on testing data as well as attempting to minimize response time
1974 * while increasing bulk throughput.
1975 * this functionality is controlled by the InterruptThrottleRate module
1976 * parameter (see ixgbe_param.c)
1977 **/
bd198058
AD		 1978static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1979 struct ixgbe_ring_container *ring_container)
f494e8fa 1980{
bd198058
AD		 1981 int bytes = ring_container->total_bytes;
1982 int packets = ring_container->total_packets;
1983 u32 timepassed_us;
621bd70e 1984 u64 bytes_perint;
bd198058 1985 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1986
1987 if (packets == 0)
bd198058 1988 return;
f494e8fa
AV		 1989
1990 /* simple throttlerate management
621bd70e
AD		 1991 * 0-10MB/s lowest (100000 ints/s)
1992 * 10-20MB/s low (20000 ints/s)
1993 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1994 */
1995 /* what was last interrupt timeslice? */
d5bf4f67 1996 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1997 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1998
1999 switch (itr_setting) {
2000 case lowest_latency:
621bd70e 2001 if (bytes_perint > 10)
bd198058 2002 itr_setting = low_latency;
f494e8fa
AV		 2003 break;
2004 case low_latency:
621bd70e 2005 if (bytes_perint > 20)
bd198058 2006 itr_setting = bulk_latency;
621bd70e 2007 else if (bytes_perint <= 10)
bd198058 2008 itr_setting = lowest_latency;
f494e8fa
AV		 2009 break;
2010 case bulk_latency:
621bd70e 2011 if (bytes_perint <= 20)
bd198058 2012 itr_setting = low_latency;
f494e8fa
AV		 2013 break;
2014 }
2015
bd198058
AD		 2016 /* clear work counters since we have the values we need */
2017 ring_container->total_bytes = 0;
2018 ring_container->total_packets = 0;
2019
2020 /* write updated itr to ring container */
2021 ring_container->itr = itr_setting;
f494e8fa
AV		 2022}
2023
509ee935
JB		 2024/**
2025 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2026 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2027 *
2028 * This function is made to be called by ethtool and by the driver
2029 * when it needs to update EITR registers at runtime. Hardware
2030 * specific quirks/differences are taken care of here.
2031 */
fe49f04a 2032void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2033{
fe49f04a 2034 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2035 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2036 int v_idx = q_vector->v_idx;
5d967eb7 2037 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2038
bd508178
AD		 2039 switch (adapter->hw.mac.type) {
2040 case ixgbe_mac_82598EB:
509ee935
JB		 2041 /* must write high and low 16 bits to reset counter */
2042 itr_reg |= (itr_reg << 16);
bd508178
AD		 2043 break;
2044 case ixgbe_mac_82599EB:
b93a2226 2045 case ixgbe_mac_X540:
509ee935
JB		 2046 /*
2047 * set the WDIS bit to not clear the timer bits and cause an
2048 * immediate assertion of the interrupt
2049 */
2050 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2051 break;
2052 default:
2053 break;
509ee935
JB		 2054 }
2055 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2056}
2057
bd198058 2058static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2059{
d5bf4f67 2060 u32 new_itr = q_vector->itr;
bd198058 2061 u8 current_itr;
f494e8fa 2062
bd198058
AD		 2063 ixgbe_update_itr(q_vector, &q_vector->tx);
2064 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2065
08c8833b 2066 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2067
2068 switch (current_itr) {
2069 /* counts and packets in update_itr are dependent on these numbers */
2070 case lowest_latency:
d5bf4f67 2071 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2072 break;
2073 case low_latency:
d5bf4f67 2074 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2075 break;
2076 case bulk_latency:
d5bf4f67 2077 new_itr = IXGBE_8K_ITR;
f494e8fa 2078 break;
bd198058
AD		 2079 default:
2080 break;
f494e8fa
AV		 2081 }
2082
d5bf4f67 2083 if (new_itr != q_vector->itr) {
fe49f04a 2084 /* do an exponential smoothing */
d5bf4f67
ET		 2085 new_itr = (10 * new_itr * q_vector->itr) /
2086 ((9 * new_itr) + q_vector->itr);
509ee935 2087
bd198058 2088 /* save the algorithm value here */
5d967eb7 2089 q_vector->itr = new_itr;
fe49f04a
AD		 2090
2091 ixgbe_write_eitr(q_vector);
f494e8fa 2092 }
f494e8fa
AV		 2093}
2094
119fc60a 2095/**
de88eeeb 2096 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2097 * @adapter: pointer to adapter
119fc60a 2098 **/
f0f9778d 2099static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2100{
119fc60a
MC		 2101 struct ixgbe_hw *hw = &adapter->hw;
2102 u32 eicr = adapter->interrupt_event;
2103
f0f9778d 2104 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2105 return;
2106
f0f9778d
AD		 2107 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2108 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2109 return;
2110
2111 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2112
7ca647bd 2113 switch (hw->device_id) {
f0f9778d
AD		 2114 case IXGBE_DEV_ID_82599_T3_LOM:
2115 /*
2116 * Since the warning interrupt is for both ports
2117 * we don't have to check if:
2118 * - This interrupt wasn't for our port.
2119 * - We may have missed the interrupt so always have to
2120 * check if we got a LSC
2121 */
2122 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2123 !(eicr & IXGBE_EICR_LSC))
2124 return;
2125
2126 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2127 u32 autoneg;
2128 bool link_up = false;
7ca647bd 2129
7ca647bd
JP		 2130 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2131
f0f9778d
AD		 2132 if (link_up)
2133 return;
2134 }
2135
2136 /* Check if this is not due to overtemp */
2137 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2138 return;
2139
2140 break;
7ca647bd
JP		 2141 default:
2142 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2143 return;
7ca647bd 2144 break;
119fc60a 2145 }
7ca647bd
JP		 2146 e_crit(drv,
2147 "Network adapter has been stopped because it has over heated. "
2148 "Restart the computer. If the problem persists, "
2149 "power off the system and replace the adapter\n");
f0f9778d
AD		 2150
2151 adapter->interrupt_event = 0;
119fc60a
MC		 2152}
2153
0befdb3e
JB		 2154static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2155{
2156 struct ixgbe_hw *hw = &adapter->hw;
2157
2158 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2159 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2160 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2161 /* write to clear the interrupt */
2162 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2163 }
2164}
cf8280ee 2165
4f51bf70
JK		 2166static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2167{
2168 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2169 return;
2170
2171 switch (adapter->hw.mac.type) {
2172 case ixgbe_mac_82599EB:
2173 /*
2174 * Need to check link state so complete overtemp check
2175 * on service task
2176 */
2177 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2178 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2179 adapter->interrupt_event = eicr;
2180 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2181 ixgbe_service_event_schedule(adapter);
2182 return;
2183 }
2184 return;
2185 case ixgbe_mac_X540:
2186 if (!(eicr & IXGBE_EICR_TS))
2187 return;
2188 break;
2189 default:
2190 return;
2191 }
2192
2193 e_crit(drv,
2194 "Network adapter has been stopped because it has over heated. "
2195 "Restart the computer. If the problem persists, "
2196 "power off the system and replace the adapter\n");
2197}
2198
e8e26350
PW		 2199static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2200{
2201 struct ixgbe_hw *hw = &adapter->hw;
2202
73c4b7cd
AD		 2203 if (eicr & IXGBE_EICR_GPI_SDP2) {
2204 /* Clear the interrupt */
2205 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2206 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2207 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2208 ixgbe_service_event_schedule(adapter);
2209 }
73c4b7cd
AD		 2210 }
2211
e8e26350
PW		 2212 if (eicr & IXGBE_EICR_GPI_SDP1) {
2213 /* Clear the interrupt */
2214 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2215 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2216 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2217 ixgbe_service_event_schedule(adapter);
2218 }
e8e26350
PW		 2219 }
2220}
2221
cf8280ee
JB		 2222static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2223{
2224 struct ixgbe_hw *hw = &adapter->hw;
2225
2226 adapter->lsc_int++;
2227 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2228 adapter->link_check_timeout = jiffies;
2229 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2230 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2231 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2232 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2233 }
2234}
2235
fe49f04a
AD		 2236static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2237 u64 qmask)
2238{
2239 u32 mask;
bd508178 2240 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2241
bd508178
AD		 2242 switch (hw->mac.type) {
2243 case ixgbe_mac_82598EB:
fe49f04a 2244 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2245 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2246 break;
2247 case ixgbe_mac_82599EB:
b93a2226 2248 case ixgbe_mac_X540:
fe49f04a 2249 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2250 if (mask)
2251 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2252 mask = (qmask >> 32);
bd508178
AD		 2253 if (mask)
2254 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2255 break;
2256 default:
2257 break;
fe49f04a
AD		 2258 }
2259 /* skip the flush */
2260}
2261
2262static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2263 u64 qmask)
fe49f04a
AD		 2264{
2265 u32 mask;
bd508178 2266 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2267
bd508178
AD		 2268 switch (hw->mac.type) {
2269 case ixgbe_mac_82598EB:
fe49f04a 2270 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2271 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2272 break;
2273 case ixgbe_mac_82599EB:
b93a2226 2274 case ixgbe_mac_X540:
fe49f04a 2275 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2276 if (mask)
2277 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2278 mask = (qmask >> 32);
bd508178
AD		 2279 if (mask)
2280 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2281 break;
2282 default:
2283 break;
fe49f04a
AD		 2284 }
2285 /* skip the flush */
2286}
2287
021230d4 2288/**
2c4af694
AD		 2289 * ixgbe_irq_enable - Enable default interrupt generation settings
2290 * @adapter: board private structure
021230d4 2291 **/
2c4af694
AD		 2292static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2293 bool flush)
9a799d71 2294{
2c4af694 2295 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2296
2c4af694
AD		 2297 /* don't reenable LSC while waiting for link */
2298 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2299 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2300
2c4af694 2301 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2302 switch (adapter->hw.mac.type) {
2303 case ixgbe_mac_82599EB:
2304 mask |= IXGBE_EIMS_GPI_SDP0;
2305 break;
2306 case ixgbe_mac_X540:
2307 mask |= IXGBE_EIMS_TS;
2308 break;
2309 default:
2310 break;
2311 }
2c4af694
AD		 2312 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2313 mask |= IXGBE_EIMS_GPI_SDP1;
2314 switch (adapter->hw.mac.type) {
2315 case ixgbe_mac_82599EB:
2c4af694
AD		 2316 mask |= IXGBE_EIMS_GPI_SDP1;
2317 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2318 case ixgbe_mac_X540:
2319 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2320 mask |= IXGBE_EIMS_MAILBOX;
2321 break;
2322 default:
2323 break;
9a799d71 2324 }
2c4af694
AD		 2325 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2326 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2327 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2328
2c4af694
AD		 2329 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2330 if (queues)
2331 ixgbe_irq_enable_queues(adapter, ~0);
2332 if (flush)
2333 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2334}
2335
2c4af694 2336static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2337{
a65151ba 2338 struct ixgbe_adapter *adapter = data;
9a799d71 2339 struct ixgbe_hw *hw = &adapter->hw;
54037505 2340 u32 eicr;
91281fd3 2341
54037505
DS		 2342 /*
2343 * Workaround for Silicon errata. Use clear-by-write instead
2344 * of clear-by-read. Reading with EICS will return the
2345 * interrupt causes without clearing, which later be done
2346 * with the write to EICR.
2347 */
2348 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2349 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2350
cf8280ee
JB		 2351 if (eicr & IXGBE_EICR_LSC)
2352 ixgbe_check_lsc(adapter);
f0848276 2353
1cdd1ec8
GR		 2354 if (eicr & IXGBE_EICR_MAILBOX)
2355 ixgbe_msg_task(adapter);
efe3d3c8 2356
bd508178
AD		 2357 switch (hw->mac.type) {
2358 case ixgbe_mac_82599EB:
b93a2226 2359 case ixgbe_mac_X540:
2c4af694
AD		 2360 if (eicr & IXGBE_EICR_ECC)
2361 e_info(link, "Received unrecoverable ECC Err, please "
2362 "reboot\n");
c4cf55e5
PWJ		 2363 /* Handle Flow Director Full threshold interrupt */
2364 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2365 int reinit_count = 0;
c4cf55e5 2366 int i;
c4cf55e5 2367 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2368 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2369 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2370 &ring->state))
2371 reinit_count++;
2372 }
2373 if (reinit_count) {
2374 /* no more flow director interrupts until after init */
2375 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2376 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2377 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2378 }
2379 }
f0f9778d 2380 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2381 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2382 break;
2383 default:
2384 break;
c4cf55e5 2385 }
f0848276 2386
bd508178 2387 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2388#ifdef CONFIG_IXGBE_PTP
2389 ixgbe_ptp_check_pps_event(adapter, eicr);
2390#endif
efe3d3c8 2391
7086400d 2392 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2393 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2394 ixgbe_irq_enable(adapter, false, false);
f0848276 2395
9a799d71 2396 return IRQ_HANDLED;
f0848276 2397}
91281fd3 2398
4ff7fb12 2399static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2400{
021230d4 2401 struct ixgbe_q_vector *q_vector = data;
91281fd3 2402
9b471446 2403 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2404
4ff7fb12
AD		 2405 if (q_vector->rx.ring || q_vector->tx.ring)
2406 napi_schedule(&q_vector->napi);
91281fd3 2407
9a799d71 2408 return IRQ_HANDLED;
91281fd3
AD		 2409}
2410
eb01b975
AD		 2411/**
2412 * ixgbe_poll - NAPI Rx polling callback
2413 * @napi: structure for representing this polling device
2414 * @budget: how many packets driver is allowed to clean
2415 *
2416 * This function is used for legacy and MSI, NAPI mode
2417 **/
8af3c33f 2418int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2419{
2420 struct ixgbe_q_vector *q_vector =
2421 container_of(napi, struct ixgbe_q_vector, napi);
2422 struct ixgbe_adapter *adapter = q_vector->adapter;
2423 struct ixgbe_ring *ring;
2424 int per_ring_budget;
2425 bool clean_complete = true;
2426
2427#ifdef CONFIG_IXGBE_DCA
2428 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2429 ixgbe_update_dca(q_vector);
2430#endif
2431
2432 ixgbe_for_each_ring(ring, q_vector->tx)
2433 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2434
2435 /* attempt to distribute budget to each queue fairly, but don't allow
2436 * the budget to go below 1 because we'll exit polling */
2437 if (q_vector->rx.count > 1)
2438 per_ring_budget = max(budget/q_vector->rx.count, 1);
2439 else
2440 per_ring_budget = budget;
2441
2442 ixgbe_for_each_ring(ring, q_vector->rx)
2443 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2444 per_ring_budget);
2445
2446 /* If all work not completed, return budget and keep polling */
2447 if (!clean_complete)
2448 return budget;
2449
2450 /* all work done, exit the polling mode */
2451 napi_complete(napi);
2452 if (adapter->rx_itr_setting & 1)
2453 ixgbe_set_itr(q_vector);
2454 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2455 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2456
2457 return 0;
2458}
2459
021230d4
AV		 2460/**
2461 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2462 * @adapter: board private structure
2463 *
2464 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2465 * interrupts from the kernel.
2466 **/
2467static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2468{
2469 struct net_device *netdev = adapter->netdev;
207867f5 2470 int vector, err;
e8e9f696 2471 int ri = 0, ti = 0;
021230d4 2472
49c7ffbe 2473 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2474 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2475 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2476
4ff7fb12 2477 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2478 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2479 "%s-%s-%d", netdev->name, "TxRx", ri++);
2480 ti++;
2481 } else if (q_vector->rx.ring) {
9fe93afd 2482 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2483 "%s-%s-%d", netdev->name, "rx", ri++);
2484 } else if (q_vector->tx.ring) {
9fe93afd 2485 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2486 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2487 } else {
2488 /* skip this unused q_vector */
2489 continue;
32aa77a4 2490 }
207867f5
AD		 2491 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2492 q_vector->name, q_vector);
9a799d71 2493 if (err) {
396e799c 2494 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2495 "Error: %d\n", err);
021230d4 2496 goto free_queue_irqs;
9a799d71 2497 }
207867f5
AD		 2498 /* If Flow Director is enabled, set interrupt affinity */
2499 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2500 /* assign the mask for this irq */
2501 irq_set_affinity_hint(entry->vector,
de88eeeb 2502 &q_vector->affinity_mask);
207867f5 2503 }
9a799d71
AK		 2504 }
2505
021230d4 2506 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2507 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2508 if (err) {
de88eeeb 2509 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2510 goto free_queue_irqs;
9a799d71
AK		 2511 }
2512
9a799d71
AK		 2513 return 0;
2514
021230d4 2515free_queue_irqs:
207867f5
AD		 2516 while (vector) {
2517 vector--;
2518 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2519 NULL);
2520 free_irq(adapter->msix_entries[vector].vector,
2521 adapter->q_vector[vector]);
2522 }
021230d4
AV		 2523 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2524 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2525 kfree(adapter->msix_entries);
2526 adapter->msix_entries = NULL;
9a799d71
AK		 2527 return err;
2528}
2529
2530/**
021230d4 2531 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2532 * @irq: interrupt number
2533 * @data: pointer to a network interface device structure
9a799d71
AK		 2534 **/
2535static irqreturn_t ixgbe_intr(int irq, void *data)
2536{
a65151ba 2537 struct ixgbe_adapter *adapter = data;
9a799d71 2538 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2539 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2540 u32 eicr;
2541
54037505 2542 /*
24ddd967 2543 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2544 * before the read of EICR.
2545 */
2546 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2547
021230d4 2548 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2549 * therefore no explicit interrupt disable is necessary */
021230d4 2550 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2551 if (!eicr) {
6af3b9eb
ET		 2552 /*
2553 * shared interrupt alert!
f47cf66e 2554 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2555 * have disabled interrupts due to EIAM
2556 * finish the workaround of silicon errata on 82598. Unmask
2557 * the interrupt that we masked before the EICR read.
2558 */
2559 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2560 ixgbe_irq_enable(adapter, true, true);
9a799d71 2561 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2562 }
9a799d71 2563
cf8280ee
JB		 2564 if (eicr & IXGBE_EICR_LSC)
2565 ixgbe_check_lsc(adapter);
021230d4 2566
bd508178
AD		 2567 switch (hw->mac.type) {
2568 case ixgbe_mac_82599EB:
e8e26350 2569 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2570 /* Fall through */
2571 case ixgbe_mac_X540:
2572 if (eicr & IXGBE_EICR_ECC)
2573 e_info(link, "Received unrecoverable ECC err, please "
2574 "reboot\n");
4f51bf70 2575 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2576 break;
2577 default:
2578 break;
2579 }
e8e26350 2580
0befdb3e 2581 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2582#ifdef CONFIG_IXGBE_PTP
2583 ixgbe_ptp_check_pps_event(adapter, eicr);
2584#endif
0befdb3e 2585
b9f6ed2b
AD		 2586 /* would disable interrupts here but EIAM disabled it */
2587 napi_schedule(&q_vector->napi);
9a799d71 2588
6af3b9eb
ET		 2589 /*
2590 * re-enable link(maybe) and non-queue interrupts, no flush.
2591 * ixgbe_poll will re-enable the queue interrupts
2592 */
6af3b9eb
ET		 2593 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2594 ixgbe_irq_enable(adapter, false, false);
2595
9a799d71
AK		 2596 return IRQ_HANDLED;
2597}
2598
2599/**
2600 * ixgbe_request_irq - initialize interrupts
2601 * @adapter: board private structure
2602 *
2603 * Attempts to configure interrupts using the best available
2604 * capabilities of the hardware and kernel.
2605 **/
021230d4 2606static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2607{
2608 struct net_device *netdev = adapter->netdev;
021230d4 2609 int err;
9a799d71 2610
4cc6df29 2611 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2612 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2613 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2614 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2615 netdev->name, adapter);
4cc6df29 2616 else
a0607fd3 2617 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2618 netdev->name, adapter);
9a799d71 2619
de88eeeb 2620 if (err)
396e799c 2621 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2622
9a799d71
AK		 2623 return err;
2624}
2625
2626static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2627{
49c7ffbe 2628 int vector;
9a799d71 2629
49c7ffbe
AD		 2630 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2631 free_irq(adapter->pdev->irq, adapter);
2632 return;
2633 }
4cc6df29 2634
49c7ffbe
AD		 2635 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2636 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2637 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2638
49c7ffbe
AD		 2639 /* free only the irqs that were actually requested */
2640 if (!q_vector->rx.ring && !q_vector->tx.ring)
2641 continue;
207867f5 2642
49c7ffbe
AD		 2643 /* clear the affinity_mask in the IRQ descriptor */
2644 irq_set_affinity_hint(entry->vector, NULL);
2645
2646 free_irq(entry->vector, q_vector);
9a799d71 2647 }
49c7ffbe
AD		 2648
2649 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2650}
2651
22d5a71b
JB		 2652/**
2653 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2654 * @adapter: board private structure
2655 **/
2656static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2657{
bd508178
AD		 2658 switch (adapter->hw.mac.type) {
2659 case ixgbe_mac_82598EB:
835462fc 2660 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2661 break;
2662 case ixgbe_mac_82599EB:
b93a2226 2663 case ixgbe_mac_X540:
835462fc
NS		 2664 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2665 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2666 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2667 break;
2668 default:
2669 break;
22d5a71b
JB		 2670 }
2671 IXGBE_WRITE_FLUSH(&adapter->hw);
2672 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2673 int vector;
2674
2675 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2676 synchronize_irq(adapter->msix_entries[vector].vector);
2677
2678 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2679 } else {
2680 synchronize_irq(adapter->pdev->irq);
2681 }
2682}
2683
9a799d71
AK		 2684/**
2685 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2686 *
2687 **/
2688static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2689{
d5bf4f67 2690 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2691
d5bf4f67
ET		 2692 /* rx/tx vector */
2693 if (adapter->rx_itr_setting == 1)
2694 q_vector->itr = IXGBE_20K_ITR;
2695 else
2696 q_vector->itr = adapter->rx_itr_setting;
2697
2698 ixgbe_write_eitr(q_vector);
9a799d71 2699
e8e26350
PW		 2700 ixgbe_set_ivar(adapter, 0, 0, 0);
2701 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2702
396e799c 2703 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2704}
2705
43e69bf0
AD		 2706/**
2707 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2708 * @adapter: board private structure
2709 * @ring: structure containing ring specific data
2710 *
2711 * Configure the Tx descriptor ring after a reset.
2712 **/
84418e3b
AD		 2713void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2714 struct ixgbe_ring *ring)
43e69bf0
AD		 2715{
2716 struct ixgbe_hw *hw = &adapter->hw;
2717 u64 tdba = ring->dma;
2f1860b8 2718 int wait_loop = 10;
b88c6de2 2719 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2720 u8 reg_idx = ring->reg_idx;
43e69bf0 2721
2f1860b8 2722 /* disable queue to avoid issues while updating state */
b88c6de2 2723 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2724 IXGBE_WRITE_FLUSH(hw);
2725
43e69bf0 2726 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2727 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2728 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2729 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2730 ring->count * sizeof(union ixgbe_adv_tx_desc));
2731 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2732 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2733 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2734
b88c6de2
AD		 2735 /*
2736 * set WTHRESH to encourage burst writeback, it should not be set
2737 * higher than 1 when ITR is 0 as it could cause false TX hangs
2738 *
2739 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2740 * to or less than the number of on chip descriptors, which is
2741 * currently 40.
2742 */
e954b374 2743 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2744 txdctl |= (1 << 16); /* WTHRESH = 1 */
2745 else
2746 txdctl |= (8 << 16); /* WTHRESH = 8 */
2747
e954b374
AD		 2748 /*
2749 * Setting PTHRESH to 32 both improves performance
2750 * and avoids a TX hang with DFP enabled
2751 */
b88c6de2
AD		 2752 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2753 32; /* PTHRESH = 32 */
2f1860b8
AD		 2754
2755 /* reinitialize flowdirector state */
39cb681b 2756 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2757 ring->atr_sample_rate = adapter->atr_sample_rate;
2758 ring->atr_count = 0;
2759 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2760 } else {
2761 ring->atr_sample_rate = 0;
2762 }
2f1860b8 2763
c84d324c
JF		 2764 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2765
2f1860b8 2766 /* enable queue */
2f1860b8
AD		 2767 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2768
2769 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2770 if (hw->mac.type == ixgbe_mac_82598EB &&
2771 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2772 return;
2773
2774 /* poll to verify queue is enabled */
2775 do {
032b4325 2776 usleep_range(1000, 2000);
2f1860b8
AD		 2777 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2778 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2779 if (!wait_loop)
2780 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2781}
2782
120ff942
AD		 2783static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2784{
2785 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2786 u32 rttdcs, mtqc;
8b1c0b24 2787 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2788
2789 if (hw->mac.type == ixgbe_mac_82598EB)
2790 return;
2791
2792 /* disable the arbiter while setting MTQC */
2793 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2794 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2795 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2796
2797 /* set transmit pool layout */
671c0adb
AD		 2798 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2799 mtqc = IXGBE_MTQC_VT_ENA;
2800 if (tcs > 4)
2801 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2802 else if (tcs > 1)
2803 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2804 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2805 mtqc |= IXGBE_MTQC_32VF;
2806 else
2807 mtqc |= IXGBE_MTQC_64VF;
2808 } else {
2809 if (tcs > 4)
2810 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2811 else if (tcs > 1)
2812 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2813 else
671c0adb
AD		 2814 mtqc = IXGBE_MTQC_64Q_1PB;
2815 }
120ff942 2816
671c0adb 2817 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2818
671c0adb
AD		 2819 /* Enable Security TX Buffer IFG for multiple pb */
2820 if (tcs) {
2821 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2822 sectx |= IXGBE_SECTX_DCB;
2823 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2824 }
2825
2826 /* re-enable the arbiter */
2827 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2828 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2829}
2830
9a799d71 2831/**
3a581073 2832 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2833 * @adapter: board private structure
2834 *
2835 * Configure the Tx unit of the MAC after a reset.
2836 **/
2837static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2838{
2f1860b8
AD		 2839 struct ixgbe_hw *hw = &adapter->hw;
2840 u32 dmatxctl;
43e69bf0 2841 u32 i;
9a799d71 2842
2f1860b8
AD		 2843 ixgbe_setup_mtqc(adapter);
2844
2845 if (hw->mac.type != ixgbe_mac_82598EB) {
2846 /* DMATXCTL.EN must be before Tx queues are enabled */
2847 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2848 dmatxctl |= IXGBE_DMATXCTL_TE;
2849 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2850 }
2851
9a799d71 2852 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2853 for (i = 0; i < adapter->num_tx_queues; i++)
2854 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2855}
2856
3ebe8fde
AD		 2857static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2858 struct ixgbe_ring *ring)
2859{
2860 struct ixgbe_hw *hw = &adapter->hw;
2861 u8 reg_idx = ring->reg_idx;
2862 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2863
2864 srrctl |= IXGBE_SRRCTL_DROP_EN;
2865
2866 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2867}
2868
2869static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2870 struct ixgbe_ring *ring)
2871{
2872 struct ixgbe_hw *hw = &adapter->hw;
2873 u8 reg_idx = ring->reg_idx;
2874 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2875
2876 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2877
2878 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2879}
2880
2881#ifdef CONFIG_IXGBE_DCB
2882void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2883#else
2884static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2885#endif
2886{
2887 int i;
2888 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2889
2890 if (adapter->ixgbe_ieee_pfc)
2891 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2892
2893 /*
2894 * We should set the drop enable bit if:
2895 * SR-IOV is enabled
2896 * or
2897 * Number of Rx queues > 1 and flow control is disabled
2898 *
2899 * This allows us to avoid head of line blocking for security
2900 * and performance reasons.
2901 */
2902 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2903 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2904 for (i = 0; i < adapter->num_rx_queues; i++)
2905 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2906 } else {
2907 for (i = 0; i < adapter->num_rx_queues; i++)
2908 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2909 }
2910}
2911
e8e26350 2912#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2913
a6616b42 2914static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2915 struct ixgbe_ring *rx_ring)
cc41ac7c 2916{
45e9baa5 2917 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2918 u32 srrctl;
bf29ee6c 2919 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2920
45e9baa5
AD		 2921 if (hw->mac.type == ixgbe_mac_82598EB) {
2922 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2923
45e9baa5
AD		 2924 /*
2925 * if VMDq is not active we must program one srrctl register
2926 * per RSS queue since we have enabled RDRXCTL.MVMEN
2927 */
2928 reg_idx &= mask;
2929 }
cc41ac7c 2930
45e9baa5
AD		 2931 /* configure header buffer length, needed for RSC */
2932 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2933
45e9baa5 2934 /* configure the packet buffer length */
f800326d 2935 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 2936
2937 /* configure descriptor type */
f800326d 2938 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2939
45e9baa5 2940 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2941}
9a799d71 2942
05abb126 2943static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2944{
05abb126
AD		 2945 struct ixgbe_hw *hw = &adapter->hw;
2946 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2947 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2948 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2949 u32 mrqc = 0, reta = 0;
2950 u32 rxcsum;
2951 int i, j;
671c0adb
AD		 2952 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2953
671c0adb
AD		 2954 /*
2955 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2956 * make full use of any rings they may have. We will use the
2957 * PSRTYPE register to control how many rings we use within the PF.
2958 */
2959 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
2960 rss_i = 2;
0cefafad 2961
05abb126
AD		 2962 /* Fill out hash function seeds */
2963 for (i = 0; i < 10; i++)
2964 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2965
2966 /* Fill out redirection table */
2967 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 2968 if (j == rss_i)
05abb126
AD		 2969 j = 0;
2970 /* reta = 4-byte sliding window of
2971 * 0x00..(indices-1)(indices-1)00..etc. */
2972 reta = (reta << 8) | (j * 0x11);
2973 if ((i & 3) == 3)
2974 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2975 }
0cefafad 2976
05abb126
AD		 2977 /* Disable indicating checksum in descriptor, enables RSS hash */
2978 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2979 rxcsum |= IXGBE_RXCSUM_PCSD;
2980 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2981
671c0adb 2982 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 2983 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 2984 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2985 } else {
671c0adb
AD		 2986 u8 tcs = netdev_get_num_tc(adapter->netdev);
2987
2988 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2989 if (tcs > 4)
2990 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
2991 else if (tcs > 1)
2992 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
2993 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2994 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 2995 else
671c0adb
AD		 2996 mrqc = IXGBE_MRQC_VMDQRSS64EN;
2997 } else {
2998 if (tcs > 4)
8b1c0b24 2999 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3000 else if (tcs > 1)
3001 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3002 else
3003 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3004 }
0cefafad
JB		 3005 }
3006
05abb126 3007 /* Perform hash on these packet types */
671c0adb
AD		 3008 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3009 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3010 IXGBE_MRQC_RSS_FIELD_IPV6 |
3011 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3012
ef6afc0c
AD		 3013 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3014 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3015 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3016 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3017
05abb126 3018 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3019}
3020
bb5a9ad2
NS		 3021/**
3022 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3023 * @adapter: address of board private structure
3024 * @index: index of ring to set
bb5a9ad2 3025 **/
082757af 3026static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3027 struct ixgbe_ring *ring)
bb5a9ad2 3028{
bb5a9ad2 3029 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3030 u32 rscctrl;
bf29ee6c 3031 u8 reg_idx = ring->reg_idx;
7367096a 3032
7d637bcc 3033 if (!ring_is_rsc_enabled(ring))
7367096a 3034 return;
bb5a9ad2 3035
7367096a 3036 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3037 rscctrl |= IXGBE_RSCCTL_RSCEN;
3038 /*
3039 * we must limit the number of descriptors so that the
3040 * total size of max desc * buf_len is not greater
642c680e 3041 * than 65536
bb5a9ad2 3042 */
f800326d 3043 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3044 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3045}
3046
9e10e045
AD		 3047#define IXGBE_MAX_RX_DESC_POLL 10
3048static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3049 struct ixgbe_ring *ring)
3050{
3051 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3052 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3053 u32 rxdctl;
bf29ee6c 3054 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3055
3056 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3057 if (hw->mac.type == ixgbe_mac_82598EB &&
3058 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3059 return;
3060
3061 do {
032b4325 3062 usleep_range(1000, 2000);
9e10e045
AD		 3063 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3064 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3065
3066 if (!wait_loop) {
3067 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3068 "the polling period\n", reg_idx);
3069 }
3070}
3071
2d39d576
YZ		 3072void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3073 struct ixgbe_ring *ring)
3074{
3075 struct ixgbe_hw *hw = &adapter->hw;
3076 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3077 u32 rxdctl;
3078 u8 reg_idx = ring->reg_idx;
3079
3080 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3081 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3082
3083 /* write value back with RXDCTL.ENABLE bit cleared */
3084 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3085
3086 if (hw->mac.type == ixgbe_mac_82598EB &&
3087 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3088 return;
3089
3090 /* the hardware may take up to 100us to really disable the rx queue */
3091 do {
3092 udelay(10);
3093 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3094 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3095
3096 if (!wait_loop) {
3097 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3098 "the polling period\n", reg_idx);
3099 }
3100}
3101
84418e3b
AD		 3102void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3103 struct ixgbe_ring *ring)
acd37177
AD		 3104{
3105 struct ixgbe_hw *hw = &adapter->hw;
3106 u64 rdba = ring->dma;
9e10e045 3107 u32 rxdctl;
bf29ee6c 3108 u8 reg_idx = ring->reg_idx;
acd37177 3109
9e10e045
AD		 3110 /* disable queue to avoid issues while updating state */
3111 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3112 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3113
acd37177
AD		 3114 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3115 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3116 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3117 ring->count * sizeof(union ixgbe_adv_rx_desc));
3118 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3119 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3120 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3121
3122 ixgbe_configure_srrctl(adapter, ring);
3123 ixgbe_configure_rscctl(adapter, ring);
3124
e9f98072
GR		 3125 /* If operating in IOV mode set RLPML for X540 */
3126 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3127 hw->mac.type == ixgbe_mac_X540) {
3128 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3129 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3130 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3131 }
3132
9e10e045
AD		 3133 if (hw->mac.type == ixgbe_mac_82598EB) {
3134 /*
3135 * enable cache line friendly hardware writes:
3136 * PTHRESH=32 descriptors (half the internal cache),
3137 * this also removes ugly rx_no_buffer_count increment
3138 * HTHRESH=4 descriptors (to minimize latency on fetch)
3139 * WTHRESH=8 burst writeback up to two cache lines
3140 */
3141 rxdctl &= ~0x3FFFFF;
3142 rxdctl |= 0x080420;
3143 }
3144
3145 /* enable receive descriptor ring */
3146 rxdctl |= IXGBE_RXDCTL_ENABLE;
3147 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3148
3149 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3150 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3151}
3152
48654521
AD		 3153static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3154{
3155 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3156 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3157 int p;
3158
3159 /* PSRTYPE must be initialized in non 82598 adapters */
3160 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3161 IXGBE_PSRTYPE_UDPHDR |
3162 IXGBE_PSRTYPE_IPV4HDR |
48654521 3163 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3164 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3165
3166 if (hw->mac.type == ixgbe_mac_82598EB)
3167 return;
3168
fbe7ca7f
AD		 3169 if (rss_i > 3)
3170 psrtype |= 2 << 29;
3171 else if (rss_i > 1)
3172 psrtype |= 1 << 29;
48654521
AD		 3173
3174 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3175 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3176 psrtype);
3177}
3178
f5b4a52e
AD		 3179static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3180{
3181 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3182 u32 reg_offset, vf_shift;
435b19f6 3183 u32 gcr_ext, vmdctl;
de4c7f65 3184 int i;
f5b4a52e
AD		 3185
3186 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3187 return;
3188
3189 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3190 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3191 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3192 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3193 vmdctl |= IXGBE_VT_CTL_REPLEN;
3194 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3195
1d9c0bfd
AD		 3196 vf_shift = VMDQ_P(0) % 32;
3197 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3198
3199 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3200 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3201 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3202 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3203 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3204 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3205
3206 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3207 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3208
3209 /*
3210 * Set up VF register offsets for selected VT Mode,
3211 * i.e. 32 or 64 VFs for SR-IOV
3212 */
73079ea0
AD		 3213 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3214 case IXGBE_82599_VMDQ_8Q_MASK:
3215 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3216 break;
3217 case IXGBE_82599_VMDQ_4Q_MASK:
3218 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3219 break;
3220 default:
3221 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3222 break;
3223 }
3224
f5b4a52e
AD		 3225 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3226
3227 /* enable Tx loopback for VF/PF communication */
3228 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
435b19f6 3229
a985b6c3 3230 /* Enable MAC Anti-Spoofing */
435b19f6 3231 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3232 adapter->num_vfs);
de4c7f65
GR		 3233 /* For VFs that have spoof checking turned off */
3234 for (i = 0; i < adapter->num_vfs; i++) {
3235 if (!adapter->vfinfo[i].spoofchk_enabled)
3236 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3237 }
f5b4a52e
AD		 3238}
3239
477de6ed 3240static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3241{
9a799d71
AK		 3242 struct ixgbe_hw *hw = &adapter->hw;
3243 struct net_device *netdev = adapter->netdev;
3244 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3245 struct ixgbe_ring *rx_ring;
3246 int i;
3247 u32 mhadd, hlreg0;
48654521 3248
63f39bd1 3249#ifdef IXGBE_FCOE
477de6ed
AD		 3250 /* adjust max frame to be able to do baby jumbo for FCoE */
3251 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3252 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3253 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3254
477de6ed
AD		 3255#endif /* IXGBE_FCOE */
3256 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3257 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3258 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3259 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3260
3261 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3262 }
3263
919e78a6
AD		 3264 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3265 max_frame += VLAN_HLEN;
3266
477de6ed
AD		 3267 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3268 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3269 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3270 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3271
0cefafad
JB		 3272 /*
3273 * Setup the HW Rx Head and Tail Descriptor Pointers and
3274 * the Base and Length of the Rx Descriptor Ring
3275 */
9a799d71 3276 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3277 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3278 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3279 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3280 else
7d637bcc 3281 clear_ring_rsc_enabled(rx_ring);
477de6ed 3282 }
477de6ed
AD		 3283}
3284
7367096a
AD		 3285static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3286{
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3289
3290 switch (hw->mac.type) {
3291 case ixgbe_mac_82598EB:
3292 /*
3293 * For VMDq support of different descriptor types or
3294 * buffer sizes through the use of multiple SRRCTL
3295 * registers, RDRXCTL.MVMEN must be set to 1
3296 *
3297 * also, the manual doesn't mention it clearly but DCA hints
3298 * will only use queue 0's tags unless this bit is set. Side
3299 * effects of setting this bit are only that SRRCTL must be
3300 * fully programmed [0..15]
3301 */
3302 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3303 break;
3304 case ixgbe_mac_82599EB:
b93a2226 3305 case ixgbe_mac_X540:
7367096a
AD		 3306 /* Disable RSC for ACK packets */
3307 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3308 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3309 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3310 /* hardware requires some bits to be set by default */
3311 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3312 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3313 break;
3314 default:
3315 /* We should do nothing since we don't know this hardware */
3316 return;
3317 }
3318
3319 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3320}
3321
477de6ed
AD		 3322/**
3323 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3324 * @adapter: board private structure
3325 *
3326 * Configure the Rx unit of the MAC after a reset.
3327 **/
3328static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3329{
3330 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3331 int i;
3332 u32 rxctrl;
477de6ed
AD		 3333
3334 /* disable receives while setting up the descriptors */
3335 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3336 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3337
3338 ixgbe_setup_psrtype(adapter);
7367096a 3339 ixgbe_setup_rdrxctl(adapter);
477de6ed 3340
9e10e045 3341 /* Program registers for the distribution of queues */
f5b4a52e 3342 ixgbe_setup_mrqc(adapter);
f5b4a52e 3343
477de6ed
AD		 3344 /* set_rx_buffer_len must be called before ring initialization */
3345 ixgbe_set_rx_buffer_len(adapter);
3346
3347 /*
3348 * Setup the HW Rx Head and Tail Descriptor Pointers and
3349 * the Base and Length of the Rx Descriptor Ring
3350 */
9e10e045
AD		 3351 for (i = 0; i < adapter->num_rx_queues; i++)
3352 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3353
9e10e045
AD		 3354 /* disable drop enable for 82598 parts */
3355 if (hw->mac.type == ixgbe_mac_82598EB)
3356 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3357
3358 /* enable all receives */
3359 rxctrl |= IXGBE_RXCTRL_RXEN;
3360 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3361}
3362
8e586137 3363static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3364{
3365 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3366 struct ixgbe_hw *hw = &adapter->hw;
3367
3368 /* add VID to filter table */
1d9c0bfd 3369 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3370 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3371
3372 return 0;
068c89b0
DS		 3373}
3374
8e586137 3375static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3376{
3377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3378 struct ixgbe_hw *hw = &adapter->hw;
3379
068c89b0 3380 /* remove VID from filter table */
1d9c0bfd 3381 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3382 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3383
3384 return 0;
068c89b0
DS		 3385}
3386
5f6c0181
JB		 3387/**
3388 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3389 * @adapter: driver data
3390 */
3391static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3392{
3393 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3394 u32 vlnctrl;
3395
3396 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3397 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3398 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3399}
3400
3401/**
3402 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3403 * @adapter: driver data
3404 */
3405static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3406{
3407 struct ixgbe_hw *hw = &adapter->hw;
3408 u32 vlnctrl;
3409
3410 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3411 vlnctrl |= IXGBE_VLNCTRL_VFE;
3412 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3413 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3414}
3415
3416/**
3417 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3418 * @adapter: driver data
3419 */
3420static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3421{
3422 struct ixgbe_hw *hw = &adapter->hw;
3423 u32 vlnctrl;
5f6c0181
JB		 3424 int i, j;
3425
3426 switch (hw->mac.type) {
3427 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3428 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3429 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3430 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3431 break;
3432 case ixgbe_mac_82599EB:
b93a2226 3433 case ixgbe_mac_X540:
5f6c0181
JB		 3434 for (i = 0; i < adapter->num_rx_queues; i++) {
3435 j = adapter->rx_ring[i]->reg_idx;
3436 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3437 vlnctrl &= ~IXGBE_RXDCTL_VME;
3438 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3439 }
3440 break;
3441 default:
3442 break;
3443 }
3444}
3445
3446/**
f62bbb5e 3447 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3448 * @adapter: driver data
3449 */
f62bbb5e 3450static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3451{
3452 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3453 u32 vlnctrl;
5f6c0181
JB		 3454 int i, j;
3455
3456 switch (hw->mac.type) {
3457 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3458 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3459 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3460 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3461 break;
3462 case ixgbe_mac_82599EB:
b93a2226 3463 case ixgbe_mac_X540:
5f6c0181
JB		 3464 for (i = 0; i < adapter->num_rx_queues; i++) {
3465 j = adapter->rx_ring[i]->reg_idx;
3466 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3467 vlnctrl |= IXGBE_RXDCTL_VME;
3468 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3469 }
3470 break;
3471 default:
3472 break;
3473 }
3474}
3475
9a799d71
AK		 3476static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3477{
f62bbb5e 3478 u16 vid;
9a799d71 3479
f62bbb5e
JG		 3480 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3481
3482 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3483 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3484}
3485
2850062a
AD		 3486/**
3487 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3488 * @netdev: network interface device structure
3489 *
3490 * Writes unicast address list to the RAR table.
3491 * Returns: -ENOMEM on failure/insufficient address space
3492 * 0 on no addresses written
3493 * X on writing X addresses to the RAR table
3494 **/
3495static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3496{
3497 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3498 struct ixgbe_hw *hw = &adapter->hw;
95447461 3499 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3500 int count = 0;
3501
95447461
JF		 3502 /* In SR-IOV mode significantly less RAR entries are available */
3503 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3504 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3505
2850062a
AD		 3506 /* return ENOMEM indicating insufficient memory for addresses */
3507 if (netdev_uc_count(netdev) > rar_entries)
3508 return -ENOMEM;
3509
95447461 3510 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3511 struct netdev_hw_addr *ha;
3512 /* return error if we do not support writing to RAR table */
3513 if (!hw->mac.ops.set_rar)
3514 return -ENOMEM;
3515
3516 netdev_for_each_uc_addr(ha, netdev) {
3517 if (!rar_entries)
3518 break;
3519 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3520 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3521 count++;
3522 }
3523 }
3524 /* write the addresses in reverse order to avoid write combining */
3525 for (; rar_entries > 0 ; rar_entries--)
3526 hw->mac.ops.clear_rar(hw, rar_entries);
3527
3528 return count;
3529}
3530
9a799d71 3531/**
2c5645cf 3532 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3533 * @netdev: network interface device structure
3534 *
2c5645cf
CL		 3535 * The set_rx_method entry point is called whenever the unicast/multicast
3536 * address list or the network interface flags are updated. This routine is
3537 * responsible for configuring the hardware for proper unicast, multicast and
3538 * promiscuous mode.
9a799d71 3539 **/
7f870475 3540void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3541{
3542 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3543 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3544 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3545 int count;
9a799d71
AK		 3546
3547 /* Check for Promiscuous and All Multicast modes */
3548
3549 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3550
f5dc442b 3551 /* set all bits that we expect to always be set */
3f2d1c0f 3552 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3553 fctrl |= IXGBE_FCTRL_BAM;
3554 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3555 fctrl |= IXGBE_FCTRL_PMCF;
3556
2850062a
AD		 3557 /* clear the bits we are changing the status of */
3558 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3559
9a799d71 3560 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3561 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3562 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3563 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3564 /* don't hardware filter vlans in promisc mode */
3565 ixgbe_vlan_filter_disable(adapter);
9a799d71 3566 } else {
746b9f02
PM		 3567 if (netdev->flags & IFF_ALLMULTI) {
3568 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3569 vmolr |= IXGBE_VMOLR_MPE;
3570 } else {
3571 /*
3572 * Write addresses to the MTA, if the attempt fails
25985edc 3573 * then we should just turn on promiscuous mode so
2850062a
AD		 3574 * that we can at least receive multicast traffic
3575 */
3576 hw->mac.ops.update_mc_addr_list(hw, netdev);
3577 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3578 }
5f6c0181 3579 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3580 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3581 }
3582
3583 /*
3584 * Write addresses to available RAR registers, if there is not
3585 * sufficient space to store all the addresses then enable
3586 * unicast promiscuous mode
3587 */
3588 count = ixgbe_write_uc_addr_list(netdev);
3589 if (count < 0) {
3590 fctrl |= IXGBE_FCTRL_UPE;
3591 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3592 }
3593
1d9c0bfd 3594 if (adapter->num_vfs)
1cdd1ec8 3595 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3596
3597 if (hw->mac.type != ixgbe_mac_82598EB) {
3598 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3599 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3600 IXGBE_VMOLR_ROPE);
1d9c0bfd 3601 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3602 }
3603
3f2d1c0f
BG		 3604 /* This is useful for sniffing bad packets. */
3605 if (adapter->netdev->features & NETIF_F_RXALL) {
3606 /* UPE and MPE will be handled by normal PROMISC logic
3607 * in e1000e_set_rx_mode */
3608 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3609 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3610 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3611
3612 fctrl &= ~(IXGBE_FCTRL_DPF);
3613 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3614 }
3615
2850062a 3616 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3617
3618 if (netdev->features & NETIF_F_HW_VLAN_RX)
3619 ixgbe_vlan_strip_enable(adapter);
3620 else
3621 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3622}
3623
021230d4
AV		 3624static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3625{
3626 int q_idx;
021230d4 3627
49c7ffbe
AD		 3628 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3629 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3630}
3631
3632static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3633{
3634 int q_idx;
021230d4 3635
49c7ffbe
AD		 3636 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3637 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3638}
3639
7a6b6f51 3640#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3641/**
2f90b865
AD		 3642 * ixgbe_configure_dcb - Configure DCB hardware
3643 * @adapter: ixgbe adapter struct
3644 *
3645 * This is called by the driver on open to configure the DCB hardware.
3646 * This is also called by the gennetlink interface when reconfiguring
3647 * the DCB state.
3648 */
3649static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3650{
3651 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3652 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3653
67ebd791
AD		 3654 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3655 if (hw->mac.type == ixgbe_mac_82598EB)
3656 netif_set_gso_max_size(adapter->netdev, 65536);
3657 return;
3658 }
3659
3660 if (hw->mac.type == ixgbe_mac_82598EB)
3661 netif_set_gso_max_size(adapter->netdev, 32768);
3662
2f90b865 3663 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3664
971060b1 3665#ifdef IXGBE_FCOE
b120818e
JF		 3666 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3667 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3668#endif
b120818e
JF		 3669
3670 /* reconfigure the hardware */
3671 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3672 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3673 DCB_TX_CONFIG);
3674 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3675 DCB_RX_CONFIG);
3676 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3677 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3678 ixgbe_dcb_hw_ets(&adapter->hw,
3679 adapter->ixgbe_ieee_ets,
3680 max_frame);
3681 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3682 adapter->ixgbe_ieee_pfc->pfc_en,
3683 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3684 }
8187cd48
JF		 3685
3686 /* Enable RSS Hash per TC */
3687 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3688 u32 msb = 0;
3689 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3690
d411a936
AD		 3691 while (rss_i) {
3692 msb++;
3693 rss_i >>= 1;
3694 }
8187cd48 3695
4ae63730
AD		 3696 /* write msb to all 8 TCs in one write */
3697 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3698 }
2f90b865 3699}
9da712d2
JF		 3700#endif
3701
3702/* Additional bittime to account for IXGBE framing */
3703#define IXGBE_ETH_FRAMING 20
3704
49ce9c2c 3705/**
9da712d2
JF		 3706 * ixgbe_hpbthresh - calculate high water mark for flow control
3707 *
3708 * @adapter: board private structure to calculate for
49ce9c2c 3709 * @pb: packet buffer to calculate
9da712d2
JF		 3710 */
3711static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3712{
3713 struct ixgbe_hw *hw = &adapter->hw;
3714 struct net_device *dev = adapter->netdev;
3715 int link, tc, kb, marker;
3716 u32 dv_id, rx_pba;
3717
3718 /* Calculate max LAN frame size */
3719 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3720
3721#ifdef IXGBE_FCOE
3722 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3723 if ((dev->features & NETIF_F_FCOE_MTU) &&
3724 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3725 (pb == ixgbe_fcoe_get_tc(adapter)))
3726 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3727
3728#endif
9da712d2
JF		 3729 /* Calculate delay value for device */
3730 switch (hw->mac.type) {
3731 case ixgbe_mac_X540:
3732 dv_id = IXGBE_DV_X540(link, tc);
3733 break;
3734 default:
3735 dv_id = IXGBE_DV(link, tc);
3736 break;
3737 }
3738
3739 /* Loopback switch introduces additional latency */
3740 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3741 dv_id += IXGBE_B2BT(tc);
3742
3743 /* Delay value is calculated in bit times convert to KB */
3744 kb = IXGBE_BT2KB(dv_id);
3745 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3746
3747 marker = rx_pba - kb;
3748
3749 /* It is possible that the packet buffer is not large enough
3750 * to provide required headroom. In this case throw an error
3751 * to user and a do the best we can.
3752 */
3753 if (marker < 0) {
3754 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3755 "headroom to support flow control."
3756 "Decrease MTU or number of traffic classes\n", pb);
3757 marker = tc + 1;
3758 }
3759
3760 return marker;
3761}
3762
49ce9c2c 3763/**
9da712d2
JF		 3764 * ixgbe_lpbthresh - calculate low water mark for for flow control
3765 *
3766 * @adapter: board private structure to calculate for
49ce9c2c 3767 * @pb: packet buffer to calculate
9da712d2
JF		 3768 */
3769static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3770{
3771 struct ixgbe_hw *hw = &adapter->hw;
3772 struct net_device *dev = adapter->netdev;
3773 int tc;
3774 u32 dv_id;
3775
3776 /* Calculate max LAN frame size */
3777 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3778
3779 /* Calculate delay value for device */
3780 switch (hw->mac.type) {
3781 case ixgbe_mac_X540:
3782 dv_id = IXGBE_LOW_DV_X540(tc);
3783 break;
3784 default:
3785 dv_id = IXGBE_LOW_DV(tc);
3786 break;
3787 }
3788
3789 /* Delay value is calculated in bit times convert to KB */
3790 return IXGBE_BT2KB(dv_id);
3791}
3792
3793/*
3794 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3795 */
3796static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3797{
3798 struct ixgbe_hw *hw = &adapter->hw;
3799 int num_tc = netdev_get_num_tc(adapter->netdev);
3800 int i;
3801
3802 if (!num_tc)
3803 num_tc = 1;
3804
3805 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3806
3807 for (i = 0; i < num_tc; i++) {
3808 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3809
3810 /* Low water marks must not be larger than high water marks */
3811 if (hw->fc.low_water > hw->fc.high_water[i])
3812 hw->fc.low_water = 0;
3813 }
3814}
3815
80605c65
JF		 3816static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3817{
80605c65 3818 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3819 int hdrm;
3820 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3821
3822 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3823 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3824 hdrm = 32 << adapter->fdir_pballoc;
3825 else
3826 hdrm = 0;
80605c65 3827
f7e1027f 3828 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3829 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3830}
3831
e4911d57
AD		 3832static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3833{
3834 struct ixgbe_hw *hw = &adapter->hw;
3835 struct hlist_node *node, *node2;
3836 struct ixgbe_fdir_filter *filter;
3837
3838 spin_lock(&adapter->fdir_perfect_lock);
3839
3840 if (!hlist_empty(&adapter->fdir_filter_list))
3841 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3842
3843 hlist_for_each_entry_safe(filter, node, node2,
3844 &adapter->fdir_filter_list, fdir_node) {
3845 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3846 &filter->filter,
3847 filter->sw_idx,
3848 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3849 IXGBE_FDIR_DROP_QUEUE :
3850 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3851 }
3852
3853 spin_unlock(&adapter->fdir_perfect_lock);
3854}
3855
9a799d71
AK		 3856static void ixgbe_configure(struct ixgbe_adapter *adapter)
3857{
d2f5e7f3
AS		 3858 struct ixgbe_hw *hw = &adapter->hw;
3859
80605c65 3860 ixgbe_configure_pb(adapter);
7a6b6f51 3861#ifdef CONFIG_IXGBE_DCB
67ebd791 3862 ixgbe_configure_dcb(adapter);
2f90b865 3863#endif
9a799d71 3864
4c1d7b4b 3865 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3866 ixgbe_restore_vlan(adapter);
3867
d2f5e7f3
AS		 3868 switch (hw->mac.type) {
3869 case ixgbe_mac_82599EB:
3870 case ixgbe_mac_X540:
3871 hw->mac.ops.disable_rx_buff(hw);
3872 break;
3873 default:
3874 break;
3875 }
3876
c4cf55e5 3877 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3878 ixgbe_init_fdir_signature_82599(&adapter->hw,
3879 adapter->fdir_pballoc);
e4911d57
AD		 3880 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3881 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3882 adapter->fdir_pballoc);
3883 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3884 }
4c1d7b4b 3885
d2f5e7f3
AS		 3886 switch (hw->mac.type) {
3887 case ixgbe_mac_82599EB:
3888 case ixgbe_mac_X540:
3889 hw->mac.ops.enable_rx_buff(hw);
3890 break;
3891 default:
3892 break;
3893 }
3894
933d41f1 3895 ixgbe_configure_virtualization(adapter);
c4cf55e5 3896
7c8ae65a
AD		 3897#ifdef IXGBE_FCOE
3898 /* configure FCoE L2 filters, redirection table, and Rx control */
3899 ixgbe_configure_fcoe(adapter);
3900
3901#endif /* IXGBE_FCOE */
9a799d71
AK		 3902 ixgbe_configure_tx(adapter);
3903 ixgbe_configure_rx(adapter);
9a799d71
AK		 3904}
3905
e8e26350
PW		 3906static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3907{
3908 switch (hw->phy.type) {
3909 case ixgbe_phy_sfp_avago:
3910 case ixgbe_phy_sfp_ftl:
3911 case ixgbe_phy_sfp_intel:
3912 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3913 case ixgbe_phy_sfp_passive_tyco:
3914 case ixgbe_phy_sfp_passive_unknown:
3915 case ixgbe_phy_sfp_active_unknown:
3916 case ixgbe_phy_sfp_ftl_active:
e8e26350 3917 return true;
8917b447
AD		 3918 case ixgbe_phy_nl:
3919 if (hw->mac.type == ixgbe_mac_82598EB)
3920 return true;
e8e26350
PW		 3921 default:
3922 return false;
3923 }
3924}
3925
0ecc061d 3926/**
e8e26350
PW		 3927 * ixgbe_sfp_link_config - set up SFP+ link
3928 * @adapter: pointer to private adapter struct
3929 **/
3930static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3931{
7086400d 3932 /*
52f33af8 3933 * We are assuming the worst case scenario here, and that
7086400d
AD		 3934 * is that an SFP was inserted/removed after the reset
3935 * but before SFP detection was enabled. As such the best
3936 * solution is to just start searching as soon as we start
3937 */
3938 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3939 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3940
7086400d 3941 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3942}
3943
3944/**
3945 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3946 * @hw: pointer to private hardware struct
3947 *
3948 * Returns 0 on success, negative on failure
3949 **/
e8e26350 3950static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3951{
3952 u32 autoneg;
8620a103 3953 bool negotiation, link_up = false;
0ecc061d
PWJ		 3954 u32 ret = IXGBE_ERR_LINK_SETUP;
3955
3956 if (hw->mac.ops.check_link)
3957 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3958
3959 if (ret)
3960 goto link_cfg_out;
3961
0b0c2b31
ET		 3962 autoneg = hw->phy.autoneg_advertised;
3963 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3964 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3965 &negotiation);
0ecc061d
PWJ		 3966 if (ret)
3967 goto link_cfg_out;
3968
8620a103
MC		 3969 if (hw->mac.ops.setup_link)
3970 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3971link_cfg_out:
3972 return ret;
3973}
3974
a34bcfff 3975static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3976{
9a799d71 3977 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3978 u32 gpie = 0;
9a799d71 3979
9b471446 3980 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3981 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3982 IXGBE_GPIE_OCD;
3983 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3984 /*
3985 * use EIAM to auto-mask when MSI-X interrupt is asserted
3986 * this saves a register write for every interrupt
3987 */
3988 switch (hw->mac.type) {
3989 case ixgbe_mac_82598EB:
3990 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3991 break;
9b471446 3992 case ixgbe_mac_82599EB:
b93a2226
DS		 3993 case ixgbe_mac_X540:
3994 default:
9b471446
JB		 3995 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3996 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3997 break;
3998 }
3999 } else {
021230d4
AV		 4000 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4001 * specifically only auto mask tx and rx interrupts */
4002 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4003 }
9a799d71 4004
a34bcfff
AD		 4005 /* XXX: to interrupt immediately for EICS writes, enable this */
4006 /* gpie |= IXGBE_GPIE_EIMEN; */
4007
4008 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4009 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4010
4011 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4012 case IXGBE_82599_VMDQ_8Q_MASK:
4013 gpie |= IXGBE_GPIE_VTMODE_16;
4014 break;
4015 case IXGBE_82599_VMDQ_4Q_MASK:
4016 gpie |= IXGBE_GPIE_VTMODE_32;
4017 break;
4018 default:
4019 gpie |= IXGBE_GPIE_VTMODE_64;
4020 break;
4021 }
119fc60a
MC		 4022 }
4023
5fdd31f9 4024 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4025 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4026 switch (adapter->hw.mac.type) {
4027 case ixgbe_mac_82599EB:
4028 gpie |= IXGBE_SDP0_GPIEN;
4029 break;
4030 case ixgbe_mac_X540:
4031 gpie |= IXGBE_EIMS_TS;
4032 break;
4033 default:
4034 break;
4035 }
4036 }
5fdd31f9 4037
a34bcfff
AD		 4038 /* Enable fan failure interrupt */
4039 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4040 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4041
2698b208 4042 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4043 gpie |= IXGBE_SDP1_GPIEN;
4044 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4045 }
a34bcfff
AD		 4046
4047 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4048}
4049
c7ccde0f 4050static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4051{
4052 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4053 int err;
a34bcfff
AD		 4054 u32 ctrl_ext;
4055
4056 ixgbe_get_hw_control(adapter);
4057 ixgbe_setup_gpie(adapter);
e8e26350 4058
9a799d71
AK		 4059 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4060 ixgbe_configure_msix(adapter);
4061 else
4062 ixgbe_configure_msi_and_legacy(adapter);
4063
c6ecf39a
DS		 4064 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4065 if (hw->mac.ops.enable_tx_laser &&
4066 ((hw->phy.multispeed_fiber) ||
9f911707 4067 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 4068 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 4069 hw->mac.ops.enable_tx_laser(hw);
4070
9a799d71 4071 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4072 ixgbe_napi_enable_all(adapter);
4073
73c4b7cd
AD		 4074 if (ixgbe_is_sfp(hw)) {
4075 ixgbe_sfp_link_config(adapter);
4076 } else {
4077 err = ixgbe_non_sfp_link_config(hw);
4078 if (err)
4079 e_err(probe, "link_config FAILED %d\n", err);
4080 }
4081
021230d4
AV		 4082 /* clear any pending interrupts, may auto mask */
4083 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4084 ixgbe_irq_enable(adapter, true, true);
9a799d71 4085
bf069c97
DS		 4086 /*
4087 * If this adapter has a fan, check to see if we had a failure
4088 * before we enabled the interrupt.
4089 */
4090 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4091 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4092 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4093 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4094 }
4095
1da100bb 4096 /* enable transmits */
477de6ed 4097 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4098
9a799d71
AK		 4099 /* bring the link up in the watchdog, this could race with our first
4100 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4101 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4102 adapter->link_check_timeout = jiffies;
7086400d 4103 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4104
4105 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4106 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4107 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4108 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4109}
4110
d4f80882
AV		 4111void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4112{
4113 WARN_ON(in_interrupt());
7086400d
AD		 4114 /* put off any impending NetWatchDogTimeout */
4115 adapter->netdev->trans_start = jiffies;
4116
d4f80882 4117 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4118 usleep_range(1000, 2000);
d4f80882 4119 ixgbe_down(adapter);
5809a1ae
GR		 4120 /*
4121 * If SR-IOV enabled then wait a bit before bringing the adapter
4122 * back up to give the VFs time to respond to the reset. The
4123 * two second wait is based upon the watchdog timer cycle in
4124 * the VF driver.
4125 */
4126 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4127 msleep(2000);
d4f80882
AV		 4128 ixgbe_up(adapter);
4129 clear_bit(__IXGBE_RESETTING, &adapter->state);
4130}
4131
c7ccde0f 4132void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4133{
4134 /* hardware has been reset, we need to reload some things */
4135 ixgbe_configure(adapter);
4136
c7ccde0f 4137 ixgbe_up_complete(adapter);
9a799d71
AK		 4138}
4139
4140void ixgbe_reset(struct ixgbe_adapter *adapter)
4141{
c44ade9e 4142 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4143 int err;
4144
7086400d
AD		 4145 /* lock SFP init bit to prevent race conditions with the watchdog */
4146 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4147 usleep_range(1000, 2000);
4148
4149 /* clear all SFP and link config related flags while holding SFP_INIT */
4150 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4151 IXGBE_FLAG2_SFP_NEEDS_RESET);
4152 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4153
8ca783ab 4154 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4155 switch (err) {
4156 case 0:
4157 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4158 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4159 break;
4160 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4161 e_dev_err("master disable timed out\n");
da4dd0f7 4162 break;
794caeb2
PWJ		 4163 case IXGBE_ERR_EEPROM_VERSION:
4164 /* We are running on a pre-production device, log a warning */
849c4542 4165 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4166 "Please be aware there may be issues associated with "
849c4542
ET		 4167 "your hardware. If you are experiencing problems "
4168 "please contact your Intel or hardware "
4169 "representative who provided you with this "
4170 "hardware.\n");
794caeb2 4171 break;
da4dd0f7 4172 default:
849c4542 4173 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4174 }
9a799d71 4175
7086400d
AD		 4176 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4177
9a799d71 4178 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4179 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4180
4181 /* update SAN MAC vmdq pool selection */
4182 if (hw->mac.san_mac_rar_index)
4183 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
9a799d71
AK		 4184}
4185
9a799d71
AK		 4186/**
4187 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4188 * @rx_ring: ring to free buffers from
4189 **/
b6ec895e 4190static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4191{
b6ec895e 4192 struct device *dev = rx_ring->dev;
9a799d71 4193 unsigned long size;
b6ec895e 4194 u16 i;
9a799d71 4195
84418e3b
AD		 4196 /* ring already cleared, nothing to do */
4197 if (!rx_ring->rx_buffer_info)
4198 return;
9a799d71 4199
84418e3b 4200 /* Free all the Rx ring sk_buffs */
9a799d71 4201 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4202 struct ixgbe_rx_buffer *rx_buffer;
4203
4204 rx_buffer = &rx_ring->rx_buffer_info[i];
4205 if (rx_buffer->skb) {
4206 struct sk_buff *skb = rx_buffer->skb;
4207 if (IXGBE_CB(skb)->page_released) {
4208 dma_unmap_page(dev,
4209 IXGBE_CB(skb)->dma,
4210 ixgbe_rx_bufsz(rx_ring),
4211 DMA_FROM_DEVICE);
4212 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4213 }
4214 dev_kfree_skb(skb);
9a799d71 4215 }
f800326d
AD		 4216 rx_buffer->skb = NULL;
4217 if (rx_buffer->dma)
4218 dma_unmap_page(dev, rx_buffer->dma,
4219 ixgbe_rx_pg_size(rx_ring),
4220 DMA_FROM_DEVICE);
4221 rx_buffer->dma = 0;
4222 if (rx_buffer->page)
dd411ec4
AD		 4223 __free_pages(rx_buffer->page,
4224 ixgbe_rx_pg_order(rx_ring));
f800326d 4225 rx_buffer->page = NULL;
9a799d71
AK		 4226 }
4227
4228 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4229 memset(rx_ring->rx_buffer_info, 0, size);
4230
4231 /* Zero out the descriptor ring */
4232 memset(rx_ring->desc, 0, rx_ring->size);
4233
f800326d 4234 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4235 rx_ring->next_to_clean = 0;
4236 rx_ring->next_to_use = 0;
9a799d71
AK		 4237}
4238
4239/**
4240 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4241 * @tx_ring: ring to be cleaned
4242 **/
b6ec895e 4243static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4244{
4245 struct ixgbe_tx_buffer *tx_buffer_info;
4246 unsigned long size;
b6ec895e 4247 u16 i;
9a799d71 4248
84418e3b
AD		 4249 /* ring already cleared, nothing to do */
4250 if (!tx_ring->tx_buffer_info)
4251 return;
9a799d71 4252
84418e3b 4253 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4254 for (i = 0; i < tx_ring->count; i++) {
4255 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4256 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4257 }
4258
dad8a3b3
JF		 4259 netdev_tx_reset_queue(txring_txq(tx_ring));
4260
9a799d71
AK		 4261 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4262 memset(tx_ring->tx_buffer_info, 0, size);
4263
4264 /* Zero out the descriptor ring */
4265 memset(tx_ring->desc, 0, tx_ring->size);
4266
4267 tx_ring->next_to_use = 0;
4268 tx_ring->next_to_clean = 0;
9a799d71
AK		 4269}
4270
4271/**
021230d4 4272 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4273 * @adapter: board private structure
4274 **/
021230d4 4275static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4276{
4277 int i;
4278
021230d4 4279 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4280 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4281}
4282
4283/**
021230d4 4284 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4285 * @adapter: board private structure
4286 **/
021230d4 4287static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4288{
4289 int i;
4290
021230d4 4291 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4292 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4293}
4294
e4911d57
AD		 4295static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4296{
4297 struct hlist_node *node, *node2;
4298 struct ixgbe_fdir_filter *filter;
4299
4300 spin_lock(&adapter->fdir_perfect_lock);
4301
4302 hlist_for_each_entry_safe(filter, node, node2,
4303 &adapter->fdir_filter_list, fdir_node) {
4304 hlist_del(&filter->fdir_node);
4305 kfree(filter);
4306 }
4307 adapter->fdir_filter_count = 0;
4308
4309 spin_unlock(&adapter->fdir_perfect_lock);
4310}
4311
9a799d71
AK		 4312void ixgbe_down(struct ixgbe_adapter *adapter)
4313{
4314 struct net_device *netdev = adapter->netdev;
7f821875 4315 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4316 u32 rxctrl;
bf29ee6c 4317 int i;
9a799d71
AK		 4318
4319 /* signal that we are down to the interrupt handler */
4320 set_bit(__IXGBE_DOWN, &adapter->state);
4321
4322 /* disable receives */
7f821875
JB		 4323 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4324 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4325
2d39d576
YZ		 4326 /* disable all enabled rx queues */
4327 for (i = 0; i < adapter->num_rx_queues; i++)
4328 /* this call also flushes the previous write */
4329 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4330
032b4325 4331 usleep_range(10000, 20000);
9a799d71 4332
7f821875
JB		 4333 netif_tx_stop_all_queues(netdev);
4334
7086400d 4335 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4336 netif_carrier_off(netdev);
4337 netif_tx_disable(netdev);
4338
4339 ixgbe_irq_disable(adapter);
4340
4341 ixgbe_napi_disable_all(adapter);
4342
d034acf1
AD		 4343 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4344 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4345 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4346
4347 del_timer_sync(&adapter->service_timer);
4348
34cecbbf 4349 if (adapter->num_vfs) {
8e34d1aa
AD		 4350 /* Clear EITR Select mapping */
4351 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4352
4353 /* Mark all the VFs as inactive */
4354 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4355 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4356
34cecbbf
AD		 4357 /* ping all the active vfs to let them know we are going down */
4358 ixgbe_ping_all_vfs(adapter);
4359
4360 /* Disable all VFTE/VFRE TX/RX */
4361 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4362 }
4363
7f821875
JB		 4364 /* disable transmits in the hardware now that interrupts are off */
4365 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4366 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4367 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4368 }
34cecbbf
AD		 4369
4370 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4371 switch (hw->mac.type) {
4372 case ixgbe_mac_82599EB:
b93a2226 4373 case ixgbe_mac_X540:
88512539 4374 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4375 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4376 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4377 break;
4378 default:
4379 break;
4380 }
7f821875 4381
6f4a0e45
PL		 4382 if (!pci_channel_offline(adapter->pdev))
4383 ixgbe_reset(adapter);
c6ecf39a
DS		 4384
4385 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4386 if (hw->mac.ops.disable_tx_laser &&
4387 ((hw->phy.multispeed_fiber) ||
9f911707 4388 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4389 (hw->mac.type == ixgbe_mac_82599EB))))
4390 hw->mac.ops.disable_tx_laser(hw);
4391
9a799d71
AK		 4392 ixgbe_clean_all_tx_rings(adapter);
4393 ixgbe_clean_all_rx_rings(adapter);
4394
5dd2d332 4395#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4396 /* since we reset the hardware DCA settings were cleared */
e35ec126 4397 ixgbe_setup_dca(adapter);
96b0e0f6 4398#endif
9a799d71
AK		 4399}
4400
9a799d71
AK		 4401/**
4402 * ixgbe_tx_timeout - Respond to a Tx Hang
4403 * @netdev: network interface device structure
4404 **/
4405static void ixgbe_tx_timeout(struct net_device *netdev)
4406{
4407 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4408
4409 /* Do the reset outside of interrupt context */
c83c6cbd 4410 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4411}
4412
9a799d71
AK		 4413/**
4414 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4415 * @adapter: board private structure to initialize
4416 *
4417 * ixgbe_sw_init initializes the Adapter private data structure.
4418 * Fields are initialized based on PCI device information and
4419 * OS network device settings (MTU size).
4420 **/
4421static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4422{
4423 struct ixgbe_hw *hw = &adapter->hw;
4424 struct pci_dev *pdev = adapter->pdev;
021230d4 4425 unsigned int rss;
7a6b6f51 4426#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4427 int j;
4428 struct tc_configuration *tc;
4429#endif
021230d4 4430
c44ade9e
JB		 4431 /* PCI config space info */
4432
4433 hw->vendor_id = pdev->vendor;
4434 hw->device_id = pdev->device;
4435 hw->revision_id = pdev->revision;
4436 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4437 hw->subsystem_device_id = pdev->subsystem_device;
4438
021230d4 4439 /* Set capability flags */
3ed69d7e 4440 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4441 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4442 switch (hw->mac.type) {
4443 case ixgbe_mac_82598EB:
bf069c97
DS		 4444 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4445 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4446 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4447 break;
b93a2226 4448 case ixgbe_mac_X540:
4f51bf70
JK		 4449 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4450 case ixgbe_mac_82599EB:
49c7ffbe 4451 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4452 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4453 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4454 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4455 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4456 /* Flow Director hash filters enabled */
45b9f509 4457 adapter->atr_sample_rate = 20;
c087663e 4458 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4459 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4460 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4461#ifdef IXGBE_FCOE
0d551589
YZ		 4462 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4463 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4464#ifdef CONFIG_IXGBE_DCB
6ee16520 4465 /* Default traffic class to use for FCoE */
56075a98 4466 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4467#endif
eacd73f7 4468#endif /* IXGBE_FCOE */
bd508178
AD		 4469 break;
4470 default:
4471 break;
f8212f97 4472 }
2f90b865 4473
7c8ae65a
AD		 4474#ifdef IXGBE_FCOE
4475 /* FCoE support exists, always init the FCoE lock */
4476 spin_lock_init(&adapter->fcoe.lock);
4477
4478#endif
1fc5f038
AD		 4479 /* n-tuple support exists, always init our spinlock */
4480 spin_lock_init(&adapter->fdir_perfect_lock);
4481
7a6b6f51 4482#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4483 switch (hw->mac.type) {
4484 case ixgbe_mac_X540:
4485 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4486 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4487 break;
4488 default:
4489 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4490 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4491 break;
4492 }
4493
2f90b865
AD		 4494 /* Configure DCB traffic classes */
4495 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4496 tc = &adapter->dcb_cfg.tc_config[j];
4497 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4498 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4499 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4500 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4501 tc->dcb_pfc = pfc_disabled;
4502 }
4de2a022
JF		 4503
4504 /* Initialize default user to priority mapping, UPx->TC0 */
4505 tc = &adapter->dcb_cfg.tc_config[0];
4506 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4507 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4508
2f90b865
AD		 4509 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4510 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4511 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4512 adapter->dcb_set_bitmap = 0x00;
3032309b 4513 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4514 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4515 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4516
4517#endif
9a799d71
AK		 4518
4519 /* default flow control settings */
cd7664f6 4520 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4521 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4522 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4523 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4524 hw->fc.send_xon = true;
71fd570b 4525 hw->fc.disable_fc_autoneg = false;
9a799d71 4526
99d74487
AD		 4527#ifdef CONFIG_PCI_IOV
4528 /* assign number of SR-IOV VFs */
4529 if (hw->mac.type != ixgbe_mac_82598EB)
4530 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4531
4532#endif
30efa5a3 4533 /* enable itr by default in dynamic mode */
f7554a2b 4534 adapter->rx_itr_setting = 1;
f7554a2b 4535 adapter->tx_itr_setting = 1;
30efa5a3 4536
30efa5a3
JB		 4537 /* set default ring sizes */
4538 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4539 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4540
bd198058 4541 /* set default work limits */
59224555 4542 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4543
9a799d71 4544 /* initialize eeprom parameters */
c44ade9e 4545 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4546 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4547 return -EIO;
4548 }
4549
9a799d71
AK		 4550 set_bit(__IXGBE_DOWN, &adapter->state);
4551
4552 return 0;
4553}
4554
4555/**
4556 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4557 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4558 *
4559 * Return 0 on success, negative on failure
4560 **/
b6ec895e 4561int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4562{
b6ec895e 4563 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4564 int orig_node = dev_to_node(dev);
4565 int numa_node = -1;
9a799d71
AK		 4566 int size;
4567
3a581073 4568 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4569
4570 if (tx_ring->q_vector)
4571 numa_node = tx_ring->q_vector->numa_node;
4572
4573 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4574 if (!tx_ring->tx_buffer_info)
89bf67f1 4575 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4576 if (!tx_ring->tx_buffer_info)
4577 goto err;
9a799d71
AK		 4578
4579 /* round up to nearest 4K */
12207e49 4580 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4581 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4582
de88eeeb
AD		 4583 set_dev_node(dev, numa_node);
4584 tx_ring->desc = dma_alloc_coherent(dev,
4585 tx_ring->size,
4586 &tx_ring->dma,
4587 GFP_KERNEL);
4588 set_dev_node(dev, orig_node);
4589 if (!tx_ring->desc)
4590 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4591 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4592 if (!tx_ring->desc)
4593 goto err;
9a799d71 4594
3a581073
JB		 4595 tx_ring->next_to_use = 0;
4596 tx_ring->next_to_clean = 0;
9a799d71 4597 return 0;
e01c31a5
JB		 4598
4599err:
4600 vfree(tx_ring->tx_buffer_info);
4601 tx_ring->tx_buffer_info = NULL;
b6ec895e 4602 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4603 return -ENOMEM;
9a799d71
AK		 4604}
4605
69888674
AD		 4606/**
4607 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4608 * @adapter: board private structure
4609 *
4610 * If this function returns with an error, then it's possible one or
4611 * more of the rings is populated (while the rest are not). It is the
4612 * callers duty to clean those orphaned rings.
4613 *
4614 * Return 0 on success, negative on failure
4615 **/
4616static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4617{
4618 int i, err = 0;
4619
4620 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4621 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4622 if (!err)
4623 continue;
de3d5b94 4624
396e799c 4625 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4626 goto err_setup_tx;
69888674
AD		 4627 }
4628
de3d5b94
AD		 4629 return 0;
4630err_setup_tx:
4631 /* rewind the index freeing the rings as we go */
4632 while (i--)
4633 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4634 return err;
4635}
4636
9a799d71
AK		 4637/**
4638 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4639 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4640 *
4641 * Returns 0 on success, negative on failure
4642 **/
b6ec895e 4643int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4644{
b6ec895e 4645 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4646 int orig_node = dev_to_node(dev);
4647 int numa_node = -1;
021230d4 4648 int size;
9a799d71 4649
3a581073 4650 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4651
4652 if (rx_ring->q_vector)
4653 numa_node = rx_ring->q_vector->numa_node;
4654
4655 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4656 if (!rx_ring->rx_buffer_info)
89bf67f1 4657 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4658 if (!rx_ring->rx_buffer_info)
4659 goto err;
9a799d71 4660
9a799d71 4661 /* Round up to nearest 4K */
3a581073
JB		 4662 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4663 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4664
de88eeeb
AD		 4665 set_dev_node(dev, numa_node);
4666 rx_ring->desc = dma_alloc_coherent(dev,
4667 rx_ring->size,
4668 &rx_ring->dma,
4669 GFP_KERNEL);
4670 set_dev_node(dev, orig_node);
4671 if (!rx_ring->desc)
4672 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4673 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4674 if (!rx_ring->desc)
4675 goto err;
9a799d71 4676
3a581073
JB		 4677 rx_ring->next_to_clean = 0;
4678 rx_ring->next_to_use = 0;
9a799d71
AK		 4679
4680 return 0;
b6ec895e
AD		 4681err:
4682 vfree(rx_ring->rx_buffer_info);
4683 rx_ring->rx_buffer_info = NULL;
4684 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4685 return -ENOMEM;
9a799d71
AK		 4686}
4687
69888674
AD		 4688/**
4689 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4690 * @adapter: board private structure
4691 *
4692 * If this function returns with an error, then it's possible one or
4693 * more of the rings is populated (while the rest are not). It is the
4694 * callers duty to clean those orphaned rings.
4695 *
4696 * Return 0 on success, negative on failure
4697 **/
69888674
AD		 4698static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4699{
4700 int i, err = 0;
4701
4702 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4703 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4704 if (!err)
4705 continue;
de3d5b94 4706
396e799c 4707 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4708 goto err_setup_rx;
69888674
AD		 4709 }
4710
7c8ae65a
AD		 4711#ifdef IXGBE_FCOE
4712 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4713 if (!err)
4714#endif
4715 return 0;
de3d5b94
AD		 4716err_setup_rx:
4717 /* rewind the index freeing the rings as we go */
4718 while (i--)
4719 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4720 return err;
4721}
4722
9a799d71
AK		 4723/**
4724 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4725 * @tx_ring: Tx descriptor ring for a specific queue
4726 *
4727 * Free all transmit software resources
4728 **/
b6ec895e 4729void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4730{
b6ec895e 4731 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4732
4733 vfree(tx_ring->tx_buffer_info);
4734 tx_ring->tx_buffer_info = NULL;
4735
b6ec895e
AD		 4736 /* if not set, then don't free */
4737 if (!tx_ring->desc)
4738 return;
4739
4740 dma_free_coherent(tx_ring->dev, tx_ring->size,
4741 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4742
4743 tx_ring->desc = NULL;
4744}
4745
4746/**
4747 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4748 * @adapter: board private structure
4749 *
4750 * Free all transmit software resources
4751 **/
4752static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4753{
4754 int i;
4755
4756 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4757 if (adapter->tx_ring[i]->desc)
b6ec895e 4758 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4759}
4760
4761/**
b4617240 4762 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4763 * @rx_ring: ring to clean the resources from
4764 *
4765 * Free all receive software resources
4766 **/
b6ec895e 4767void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4768{
b6ec895e 4769 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4770
4771 vfree(rx_ring->rx_buffer_info);
4772 rx_ring->rx_buffer_info = NULL;
4773
b6ec895e
AD		 4774 /* if not set, then don't free */
4775 if (!rx_ring->desc)
4776 return;
4777
4778 dma_free_coherent(rx_ring->dev, rx_ring->size,
4779 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4780
4781 rx_ring->desc = NULL;
4782}
4783
4784/**
4785 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4786 * @adapter: board private structure
4787 *
4788 * Free all receive software resources
4789 **/
4790static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4791{
4792 int i;
4793
7c8ae65a
AD		 4794#ifdef IXGBE_FCOE
4795 ixgbe_free_fcoe_ddp_resources(adapter);
4796
4797#endif
9a799d71 4798 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4799 if (adapter->rx_ring[i]->desc)
b6ec895e 4800 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4801}
4802
9a799d71
AK		 4803/**
4804 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4805 * @netdev: network interface device structure
4806 * @new_mtu: new value for maximum frame size
4807 *
4808 * Returns 0 on success, negative on failure
4809 **/
4810static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4811{
4812 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4813 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4814
42c783c5 4815 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4816 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4817 return -EINVAL;
4818
4819 /*
4820 * For 82599EB we cannot allow PF to change MTU greater than 1500
4821 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4822 * don't allocate and chain buffers correctly.
4823 */
4824 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4825 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4826 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 4827 return -EINVAL;
9a799d71 4828
396e799c 4829 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4830
021230d4 4831 /* must set new MTU before calling down or up */
9a799d71
AK		 4832 netdev->mtu = new_mtu;
4833
d4f80882
AV		 4834 if (netif_running(netdev))
4835 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4836
4837 return 0;
4838}
4839
4840/**
4841 * ixgbe_open - Called when a network interface is made active
4842 * @netdev: network interface device structure
4843 *
4844 * Returns 0 on success, negative value on failure
4845 *
4846 * The open entry point is called when a network interface is made
4847 * active by the system (IFF_UP). At this point all resources needed
4848 * for transmit and receive operations are allocated, the interrupt
4849 * handler is registered with the OS, the watchdog timer is started,
4850 * and the stack is notified that the interface is ready.
4851 **/
4852static int ixgbe_open(struct net_device *netdev)
4853{
4854 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4855 int err;
4bebfaa5
AK		 4856
4857 /* disallow open during test */
4858 if (test_bit(__IXGBE_TESTING, &adapter->state))
4859 return -EBUSY;
9a799d71 4860
54386467
JB		 4861 netif_carrier_off(netdev);
4862
9a799d71
AK		 4863 /* allocate transmit descriptors */
4864 err = ixgbe_setup_all_tx_resources(adapter);
4865 if (err)
4866 goto err_setup_tx;
4867
9a799d71
AK		 4868 /* allocate receive descriptors */
4869 err = ixgbe_setup_all_rx_resources(adapter);
4870 if (err)
4871 goto err_setup_rx;
4872
4873 ixgbe_configure(adapter);
4874
021230d4 4875 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4876 if (err)
4877 goto err_req_irq;
4878
ac802f5d
AD		 4879 /* Notify the stack of the actual queue counts. */
4880 err = netif_set_real_num_tx_queues(netdev,
4881 adapter->num_rx_pools > 1 ? 1 :
4882 adapter->num_tx_queues);
4883 if (err)
4884 goto err_set_queues;
4885
4886
4887 err = netif_set_real_num_rx_queues(netdev,
4888 adapter->num_rx_pools > 1 ? 1 :
4889 adapter->num_rx_queues);
4890 if (err)
4891 goto err_set_queues;
4892
c7ccde0f 4893 ixgbe_up_complete(adapter);
9a799d71
AK		 4894
4895 return 0;
4896
ac802f5d
AD		 4897err_set_queues:
4898 ixgbe_free_irq(adapter);
9a799d71 4899err_req_irq:
a20a1199 4900 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4901err_setup_rx:
a20a1199 4902 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4903err_setup_tx:
9a799d71
AK		 4904 ixgbe_reset(adapter);
4905
4906 return err;
4907}
4908
4909/**
4910 * ixgbe_close - Disables a network interface
4911 * @netdev: network interface device structure
4912 *
4913 * Returns 0, this is not allowed to fail
4914 *
4915 * The close entry point is called when an interface is de-activated
4916 * by the OS. The hardware is still under the drivers control, but
4917 * needs to be disabled. A global MAC reset is issued to stop the
4918 * hardware, and all transmit and receive resources are freed.
4919 **/
4920static int ixgbe_close(struct net_device *netdev)
4921{
4922 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4923
4924 ixgbe_down(adapter);
4925 ixgbe_free_irq(adapter);
4926
e4911d57
AD		 4927 ixgbe_fdir_filter_exit(adapter);
4928
9a799d71
AK		 4929 ixgbe_free_all_tx_resources(adapter);
4930 ixgbe_free_all_rx_resources(adapter);
4931
5eba3699 4932 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4933
4934 return 0;
4935}
4936
b3c8b4ba
AD		 4937#ifdef CONFIG_PM
4938static int ixgbe_resume(struct pci_dev *pdev)
4939{
c60fbb00
AD		 4940 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4941 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4942 u32 err;
4943
4944 pci_set_power_state(pdev, PCI_D0);
4945 pci_restore_state(pdev);
656ab817
DS		 4946 /*
4947 * pci_restore_state clears dev->state_saved so call
4948 * pci_save_state to restore it.
4949 */
4950 pci_save_state(pdev);
9ce77666 4951
4952 err = pci_enable_device_mem(pdev);
b3c8b4ba 4953 if (err) {
849c4542 4954 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4955 return err;
4956 }
4957 pci_set_master(pdev);
4958
dd4d8ca6 4959 pci_wake_from_d3(pdev, false);
b3c8b4ba 4960
b3c8b4ba
AD		 4961 ixgbe_reset(adapter);
4962
495dce12
WJP		 4963 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4964
ac802f5d
AD		 4965 rtnl_lock();
4966 err = ixgbe_init_interrupt_scheme(adapter);
4967 if (!err && netif_running(netdev))
c60fbb00 4968 err = ixgbe_open(netdev);
ac802f5d
AD		 4969
4970 rtnl_unlock();
4971
4972 if (err)
4973 return err;
b3c8b4ba
AD		 4974
4975 netif_device_attach(netdev);
4976
4977 return 0;
4978}
b3c8b4ba 4979#endif /* CONFIG_PM */
9d8d05ae
RW		 4980
4981static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 4982{
c60fbb00
AD		 4983 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4984 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 4985 struct ixgbe_hw *hw = &adapter->hw;
4986 u32 ctrl, fctrl;
4987 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4988#ifdef CONFIG_PM
4989 int retval = 0;
4990#endif
4991
4992 netif_device_detach(netdev);
4993
4994 if (netif_running(netdev)) {
ab6039a7 4995 rtnl_lock();
b3c8b4ba
AD		 4996 ixgbe_down(adapter);
4997 ixgbe_free_irq(adapter);
4998 ixgbe_free_all_tx_resources(adapter);
4999 ixgbe_free_all_rx_resources(adapter);
ab6039a7 5000 rtnl_unlock();
b3c8b4ba 5001 }
b3c8b4ba 5002
5f5ae6fc
AD		 5003 ixgbe_clear_interrupt_scheme(adapter);
5004
b3c8b4ba
AD		 5005#ifdef CONFIG_PM
5006 retval = pci_save_state(pdev);
5007 if (retval)
5008 return retval;
4df10466 5009
b3c8b4ba 5010#endif
e8e26350
PW		 5011 if (wufc) {
5012 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5013
c509e754
DS		 5014 /*
5015 * enable the optics for both mult-speed fiber and
5016 * 82599 SFP+ fiber as we can WoL.
5017 */
5018 if (hw->mac.ops.enable_tx_laser &&
5019 (hw->phy.multispeed_fiber ||
5020 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
5021 hw->mac.type == ixgbe_mac_82599EB)))
5022 hw->mac.ops.enable_tx_laser(hw);
5023
e8e26350
PW		 5024 /* turn on all-multi mode if wake on multicast is enabled */
5025 if (wufc & IXGBE_WUFC_MC) {
5026 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5027 fctrl |= IXGBE_FCTRL_MPE;
5028 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5029 }
5030
5031 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5032 ctrl |= IXGBE_CTRL_GIO_DIS;
5033 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5034
5035 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5036 } else {
5037 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5038 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5039 }
5040
bd508178
AD		 5041 switch (hw->mac.type) {
5042 case ixgbe_mac_82598EB:
dd4d8ca6 5043 pci_wake_from_d3(pdev, false);
bd508178
AD		 5044 break;
5045 case ixgbe_mac_82599EB:
b93a2226 5046 case ixgbe_mac_X540:
bd508178
AD		 5047 pci_wake_from_d3(pdev, !!wufc);
5048 break;
5049 default:
5050 break;
5051 }
b3c8b4ba 5052
9d8d05ae
RW		 5053 *enable_wake = !!wufc;
5054
b3c8b4ba
AD		 5055 ixgbe_release_hw_control(adapter);
5056
5057 pci_disable_device(pdev);
5058
9d8d05ae
RW		 5059 return 0;
5060}
5061
5062#ifdef CONFIG_PM
5063static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5064{
5065 int retval;
5066 bool wake;
5067
5068 retval = __ixgbe_shutdown(pdev, &wake);
5069 if (retval)
5070 return retval;
5071
5072 if (wake) {
5073 pci_prepare_to_sleep(pdev);
5074 } else {
5075 pci_wake_from_d3(pdev, false);
5076 pci_set_power_state(pdev, PCI_D3hot);
5077 }
b3c8b4ba
AD		 5078
5079 return 0;
5080}
9d8d05ae 5081#endif /* CONFIG_PM */
b3c8b4ba
AD		 5082
5083static void ixgbe_shutdown(struct pci_dev *pdev)
5084{
9d8d05ae
RW		 5085 bool wake;
5086
5087 __ixgbe_shutdown(pdev, &wake);
5088
5089 if (system_state == SYSTEM_POWER_OFF) {
5090 pci_wake_from_d3(pdev, wake);
5091 pci_set_power_state(pdev, PCI_D3hot);
5092 }
b3c8b4ba
AD		 5093}
5094
9a799d71
AK		 5095/**
5096 * ixgbe_update_stats - Update the board statistics counters.
5097 * @adapter: board private structure
5098 **/
5099void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5100{
2d86f139 5101 struct net_device *netdev = adapter->netdev;
9a799d71 5102 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5103 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5104 u64 total_mpc = 0;
5105 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5106 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5107 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5108 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5109
d08935c2
DS		 5110 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5111 test_bit(__IXGBE_RESETTING, &adapter->state))
5112 return;
5113
94b982b2 5114 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5115 u64 rsc_count = 0;
94b982b2 5116 u64 rsc_flush = 0;
94b982b2 5117 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5118 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5119 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5120 }
5121 adapter->rsc_total_count = rsc_count;
5122 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5123 }
5124
5b7da515
AD		 5125 for (i = 0; i < adapter->num_rx_queues; i++) {
5126 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5127 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5128 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5129 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5130 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5131 bytes += rx_ring->stats.bytes;
5132 packets += rx_ring->stats.packets;
5133 }
5134 adapter->non_eop_descs = non_eop_descs;
5135 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5136 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5137 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5138 netdev->stats.rx_bytes = bytes;
5139 netdev->stats.rx_packets = packets;
5140
5141 bytes = 0;
5142 packets = 0;
7ca3bc58 5143 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5144 for (i = 0; i < adapter->num_tx_queues; i++) {
5145 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5146 restart_queue += tx_ring->tx_stats.restart_queue;
5147 tx_busy += tx_ring->tx_stats.tx_busy;
5148 bytes += tx_ring->stats.bytes;
5149 packets += tx_ring->stats.packets;
5150 }
eb985f09 5151 adapter->restart_queue = restart_queue;
5b7da515
AD		 5152 adapter->tx_busy = tx_busy;
5153 netdev->stats.tx_bytes = bytes;
5154 netdev->stats.tx_packets = packets;
7ca3bc58 5155
7ca647bd 5156 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5157
5158 /* 8 register reads */
6f11eef7
AV		 5159 for (i = 0; i < 8; i++) {
5160 /* for packet buffers not used, the register should read 0 */
5161 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5162 missed_rx += mpc;
7ca647bd
JP		 5163 hwstats->mpc[i] += mpc;
5164 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5165 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5166 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5167 switch (hw->mac.type) {
5168 case ixgbe_mac_82598EB:
1a70db4b
ET		 5169 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5170 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5171 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5172 hwstats->pxonrxc[i] +=
5173 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5174 break;
5175 case ixgbe_mac_82599EB:
b93a2226 5176 case ixgbe_mac_X540:
bd508178
AD		 5177 hwstats->pxonrxc[i] +=
5178 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5179 break;
5180 default:
5181 break;
e8e26350 5182 }
6f11eef7 5183 }
1a70db4b
ET		 5184
5185 /*16 register reads */
5186 for (i = 0; i < 16; i++) {
5187 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5188 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5189 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5190 (hw->mac.type == ixgbe_mac_X540)) {
5191 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5192 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5193 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5194 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5195 }
5196 }
5197
7ca647bd 5198 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5199 /* work around hardware counting issue */
7ca647bd 5200 hwstats->gprc -= missed_rx;
6f11eef7 5201
c84d324c
JF		 5202 ixgbe_update_xoff_received(adapter);
5203
6f11eef7 5204 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5205 switch (hw->mac.type) {
5206 case ixgbe_mac_82598EB:
5207 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5208 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5209 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5210 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5211 break;
b93a2226 5212 case ixgbe_mac_X540:
58f6bcf9
ET		 5213 /* OS2BMC stats are X540 only*/
5214 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5215 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5216 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5217 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5218 case ixgbe_mac_82599EB:
a4d4f629
AD		 5219 for (i = 0; i < 16; i++)
5220 adapter->hw_rx_no_dma_resources +=
5221 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5222 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5223 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5224 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5225 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5226 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5227 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5228 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5229 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5230 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5231#ifdef IXGBE_FCOE
7ca647bd
JP		 5232 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5233 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5234 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5235 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5236 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5237 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5238 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5239 if (adapter->fcoe.ddp_pool) {
5240 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5241 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5242 unsigned int cpu;
5243 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5244 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5245 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5246 noddp += ddp_pool->noddp;
5247 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5248 }
5a1ee270
AD		 5249 hwstats->fcoe_noddp = noddp;
5250 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5251 }
6d45522c 5252#endif /* IXGBE_FCOE */
bd508178
AD		 5253 break;
5254 default:
5255 break;
e8e26350 5256 }
9a799d71 5257 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5258 hwstats->bprc += bprc;
5259 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5260 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5261 hwstats->mprc -= bprc;
5262 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5263 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5264 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5265 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5266 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5267 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5268 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5269 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5270 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5271 hwstats->lxontxc += lxon;
6f11eef7 5272 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5273 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5274 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5275 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5276 /*
5277 * 82598 errata - tx of flow control packets is included in tx counters
5278 */
5279 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5280 hwstats->gptc -= xon_off_tot;
5281 hwstats->mptc -= xon_off_tot;
5282 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5283 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5284 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5285 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5286 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5287 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5288 hwstats->ptc64 -= xon_off_tot;
5289 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5290 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5291 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5292 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5293 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5294 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5295
5296 /* Fill out the OS statistics structure */
7ca647bd 5297 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5298
5299 /* Rx Errors */
7ca647bd 5300 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5301 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5302 netdev->stats.rx_length_errors = hwstats->rlec;
5303 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5304 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5305}
5306
5307/**
d034acf1 5308 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5309 * @adapter: pointer to the device adapter structure
9a799d71 5310 **/
d034acf1 5311static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5312{
cf8280ee 5313 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5314 int i;
cf8280ee 5315
d034acf1
AD		 5316 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5317 return;
5318
5319 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5320
d034acf1 5321 /* if interface is down do nothing */
fe49f04a 5322 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5323 return;
5324
5325 /* do nothing if we are not using signature filters */
5326 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5327 return;
5328
5329 adapter->fdir_overflow++;
5330
93c52dd0
AD		 5331 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5332 for (i = 0; i < adapter->num_tx_queues; i++)
5333 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5334 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5335 /* re-enable flow director interrupts */
5336 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5337 } else {
5338 e_err(probe, "failed to finish FDIR re-initialization, "
5339 "ignored adding FDIR ATR filters\n");
5340 }
93c52dd0
AD		 5341}
5342
5343/**
5344 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5345 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5346 *
5347 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5348 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5349 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5350 * determine if a hang has occurred.
93c52dd0
AD		 5351 */
5352static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5353{
cf8280ee 5354 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5355 u64 eics = 0;
5356 int i;
cf8280ee 5357
93c52dd0
AD		 5358 /* If we're down or resetting, just bail */
5359 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5360 test_bit(__IXGBE_RESETTING, &adapter->state))
5361 return;
22d5a71b 5362
93c52dd0
AD		 5363 /* Force detection of hung controller */
5364 if (netif_carrier_ok(adapter->netdev)) {
5365 for (i = 0; i < adapter->num_tx_queues; i++)
5366 set_check_for_tx_hang(adapter->tx_ring[i]);
5367 }
22d5a71b 5368
fe49f04a
AD		 5369 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5370 /*
5371 * for legacy and MSI interrupts don't set any bits
5372 * that are enabled for EIAM, because this operation
5373 * would set *both* EIMS and EICS for any bit in EIAM
5374 */
5375 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5376 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5377 } else {
5378 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5379 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5380 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5381 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5382 eics |= ((u64)1 << i);
5383 }
cf8280ee 5384 }
9a799d71 5385
93c52dd0 5386 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5387 ixgbe_irq_rearm_queues(adapter, eics);
5388
cf8280ee
JB		 5389}
5390
e8e26350 5391/**
93c52dd0 5392 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5393 * @adapter: pointer to the device adapter structure
5394 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5395 **/
93c52dd0 5396static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5397{
e8e26350 5398 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5399 u32 link_speed = adapter->link_speed;
5400 bool link_up = adapter->link_up;
041441d0 5401 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5402
93c52dd0
AD		 5403 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5404 return;
5405
5406 if (hw->mac.ops.check_link) {
5407 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5408 } else {
93c52dd0
AD		 5409 /* always assume link is up, if no check link function */
5410 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5411 link_up = true;
c4cf55e5 5412 }
041441d0
AD		 5413
5414 if (adapter->ixgbe_ieee_pfc)
5415 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5416
3ebe8fde 5417 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5418 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5419 ixgbe_set_rx_drop_en(adapter);
5420 }
93c52dd0
AD		 5421
5422 if (link_up ||
5423 time_after(jiffies, (adapter->link_check_timeout +
5424 IXGBE_TRY_LINK_TIMEOUT))) {
5425 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5426 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5427 IXGBE_WRITE_FLUSH(hw);
5428 }
5429
5430 adapter->link_up = link_up;
5431 adapter->link_speed = link_speed;
e8e26350
PW		 5432}
5433
5434/**
93c52dd0
AD		 5435 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5436 * print link up message
49ce9c2c 5437 * @adapter: pointer to the device adapter structure
e8e26350 5438 **/
93c52dd0 5439static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5440{
93c52dd0 5441 struct net_device *netdev = adapter->netdev;
e8e26350 5442 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5443 u32 link_speed = adapter->link_speed;
5444 bool flow_rx, flow_tx;
e8e26350 5445
93c52dd0
AD		 5446 /* only continue if link was previously down */
5447 if (netif_carrier_ok(netdev))
a985b6c3 5448 return;
63d6e1d8 5449
93c52dd0 5450 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5451
93c52dd0
AD		 5452 switch (hw->mac.type) {
5453 case ixgbe_mac_82598EB: {
5454 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5455 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5456 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5457 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5458 }
5459 break;
5460 case ixgbe_mac_X540:
5461 case ixgbe_mac_82599EB: {
5462 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5463 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5464 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5465 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5466 }
5467 break;
5468 default:
5469 flow_tx = false;
5470 flow_rx = false;
5471 break;
e8e26350 5472 }
3a6a4eda
JK		 5473
5474#ifdef CONFIG_IXGBE_PTP
5475 ixgbe_ptp_start_cyclecounter(adapter);
5476#endif
5477
93c52dd0
AD		 5478 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5479 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5480 "10 Gbps" :
5481 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5482 "1 Gbps" :
5483 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5484 "100 Mbps" :
5485 "unknown speed"))),
5486 ((flow_rx && flow_tx) ? "RX/TX" :
5487 (flow_rx ? "RX" :
5488 (flow_tx ? "TX" : "None"))));
e8e26350 5489
93c52dd0 5490 netif_carrier_on(netdev);
93c52dd0 5491 ixgbe_check_vf_rate_limit(adapter);
befa2af7
AD		 5492
5493 /* ping all the active vfs to let them know link has changed */
5494 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5495}
5496
c4cf55e5 5497/**
93c52dd0
AD		 5498 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5499 * print link down message
49ce9c2c 5500 * @adapter: pointer to the adapter structure
c4cf55e5 5501 **/
581330ba 5502static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5503{
cf8280ee 5504 struct net_device *netdev = adapter->netdev;
c4cf55e5 5505 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5506
93c52dd0
AD		 5507 adapter->link_up = false;
5508 adapter->link_speed = 0;
cf8280ee 5509
93c52dd0
AD		 5510 /* only continue if link was up previously */
5511 if (!netif_carrier_ok(netdev))
5512 return;
264857b8 5513
93c52dd0
AD		 5514 /* poll for SFP+ cable when link is down */
5515 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5516 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5517
3a6a4eda
JK		 5518#ifdef CONFIG_IXGBE_PTP
5519 ixgbe_ptp_start_cyclecounter(adapter);
5520#endif
5521
93c52dd0
AD		 5522 e_info(drv, "NIC Link is Down\n");
5523 netif_carrier_off(netdev);
befa2af7
AD		 5524
5525 /* ping all the active vfs to let them know link has changed */
5526 ixgbe_ping_all_vfs(adapter);
93c52dd0 5527}
e8e26350 5528
93c52dd0
AD		 5529/**
5530 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5531 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5532 **/
5533static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5534{
c4cf55e5 5535 int i;
93c52dd0 5536 int some_tx_pending = 0;
c4cf55e5 5537
93c52dd0 5538 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5539 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5540 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5541 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5542 some_tx_pending = 1;
5543 break;
5544 }
5545 }
5546
5547 if (some_tx_pending) {
5548 /* We've lost link, so the controller stops DMA,
5549 * but we've got queued Tx work that's never going
5550 * to get done, so reset controller to flush Tx.
5551 * (Do the reset outside of interrupt context).
5552 */
c83c6cbd 5553 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5554 }
c4cf55e5 5555 }
c4cf55e5
PWJ		 5556}
5557
a985b6c3
GR		 5558static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5559{
5560 u32 ssvpc;
5561
5562 /* Do not perform spoof check for 82598 */
5563 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5564 return;
5565
5566 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5567
5568 /*
5569 * ssvpc register is cleared on read, if zero then no
5570 * spoofed packets in the last interval.
5571 */
5572 if (!ssvpc)
5573 return;
5574
5575 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5576}
5577
93c52dd0
AD		 5578/**
5579 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5580 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5581 **/
5582static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5583{
5584 /* if interface is down do nothing */
7edebf9a
ET		 5585 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5586 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5587 return;
5588
5589 ixgbe_watchdog_update_link(adapter);
5590
5591 if (adapter->link_up)
5592 ixgbe_watchdog_link_is_up(adapter);
5593 else
5594 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5595
a985b6c3 5596 ixgbe_spoof_check(adapter);
9a799d71 5597 ixgbe_update_stats(adapter);
93c52dd0
AD		 5598
5599 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5600}
10eec955 5601
cf8280ee 5602/**
7086400d 5603 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5604 * @adapter: the ixgbe adapter structure
cf8280ee 5605 **/
7086400d 5606static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5607{
cf8280ee 5608 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5609 s32 err;
cf8280ee 5610
7086400d
AD		 5611 /* not searching for SFP so there is nothing to do here */
5612 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5613 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5614 return;
10eec955 5615
7086400d
AD		 5616 /* someone else is in init, wait until next service event */
5617 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5618 return;
cf8280ee 5619
7086400d
AD		 5620 err = hw->phy.ops.identify_sfp(hw);
5621 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5622 goto sfp_out;
264857b8 5623
7086400d
AD		 5624 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5625 /* If no cable is present, then we need to reset
5626 * the next time we find a good cable. */
5627 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5628 }
9a799d71 5629
7086400d
AD		 5630 /* exit on error */
5631 if (err)
5632 goto sfp_out;
e8e26350 5633
7086400d
AD		 5634 /* exit if reset not needed */
5635 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5636 goto sfp_out;
9a799d71 5637
7086400d 5638 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5639
7086400d
AD		 5640 /*
5641 * A module may be identified correctly, but the EEPROM may not have
5642 * support for that module. setup_sfp() will fail in that case, so
5643 * we should not allow that module to load.
5644 */
5645 if (hw->mac.type == ixgbe_mac_82598EB)
5646 err = hw->phy.ops.reset(hw);
5647 else
5648 err = hw->mac.ops.setup_sfp(hw);
5649
5650 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5651 goto sfp_out;
5652
5653 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5654 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5655
5656sfp_out:
5657 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5658
5659 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5660 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5661 e_dev_err("failed to initialize because an unsupported "
5662 "SFP+ module type was detected.\n");
5663 e_dev_err("Reload the driver after installing a "
5664 "supported module.\n");
5665 unregister_netdev(adapter->netdev);
bc59fcda 5666 }
7086400d 5667}
bc59fcda 5668
7086400d
AD		 5669/**
5670 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5671 * @adapter: the ixgbe adapter structure
7086400d
AD		 5672 **/
5673static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5674{
5675 struct ixgbe_hw *hw = &adapter->hw;
5676 u32 autoneg;
5677 bool negotiation;
5678
5679 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5680 return;
5681
5682 /* someone else is in init, wait until next service event */
5683 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5684 return;
5685
5686 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5687
5688 autoneg = hw->phy.autoneg_advertised;
5689 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5690 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5691 if (hw->mac.ops.setup_link)
5692 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5693
5694 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5695 adapter->link_check_timeout = jiffies;
5696 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5697}
5698
83c61fa9
GR		 5699#ifdef CONFIG_PCI_IOV
5700static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5701{
5702 int vf;
5703 struct ixgbe_hw *hw = &adapter->hw;
5704 struct net_device *netdev = adapter->netdev;
5705 u32 gpc;
5706 u32 ciaa, ciad;
5707
5708 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5709 if (gpc) /* If incrementing then no need for the check below */
5710 return;
5711 /*
5712 * Check to see if a bad DMA write target from an errant or
5713 * malicious VF has caused a PCIe error. If so then we can
5714 * issue a VFLR to the offending VF(s) and then resume without
5715 * requesting a full slot reset.
5716 */
5717
5718 for (vf = 0; vf < adapter->num_vfs; vf++) {
5719 ciaa = (vf << 16) | 0x80000000;
5720 /* 32 bit read so align, we really want status at offset 6 */
5721 ciaa |= PCI_COMMAND;
5722 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5723 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5724 ciaa &= 0x7FFFFFFF;
5725 /* disable debug mode asap after reading data */
5726 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5727 /* Get the upper 16 bits which will be the PCI status reg */
5728 ciad >>= 16;
5729 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5730 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5731 /* Issue VFLR */
5732 ciaa = (vf << 16) | 0x80000000;
5733 ciaa |= 0xA8;
5734 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5735 ciad = 0x00008000; /* VFLR */
5736 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5737 ciaa &= 0x7FFFFFFF;
5738 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5739 }
5740 }
5741}
5742
5743#endif
7086400d
AD		 5744/**
5745 * ixgbe_service_timer - Timer Call-back
5746 * @data: pointer to adapter cast into an unsigned long
5747 **/
5748static void ixgbe_service_timer(unsigned long data)
5749{
5750 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5751 unsigned long next_event_offset;
83c61fa9 5752 bool ready = true;
7086400d 5753
6bb78cfb
AD		 5754 /* poll faster when waiting for link */
5755 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5756 next_event_offset = HZ / 10;
5757 else
5758 next_event_offset = HZ * 2;
83c61fa9 5759
6bb78cfb 5760#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5761 /*
5762 * don't bother with SR-IOV VF DMA hang check if there are
5763 * no VFs or the link is down
5764 */
5765 if (!adapter->num_vfs ||
6bb78cfb 5766 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5767 goto normal_timer_service;
83c61fa9
GR		 5768
5769 /* If we have VFs allocated then we must check for DMA hangs */
5770 ixgbe_check_for_bad_vf(adapter);
5771 next_event_offset = HZ / 50;
5772 adapter->timer_event_accumulator++;
5773
6bb78cfb 5774 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5775 adapter->timer_event_accumulator = 0;
7086400d 5776 else
6bb78cfb 5777 ready = false;
7086400d 5778
6bb78cfb 5779normal_timer_service:
83c61fa9 5780#endif
7086400d
AD		 5781 /* Reset the timer */
5782 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5783
83c61fa9
GR		 5784 if (ready)
5785 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5786}
5787
c83c6cbd
AD		 5788static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5789{
5790 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5791 return;
5792
5793 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5794
5795 /* If we're already down or resetting, just bail */
5796 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5797 test_bit(__IXGBE_RESETTING, &adapter->state))
5798 return;
5799
5800 ixgbe_dump(adapter);
5801 netdev_err(adapter->netdev, "Reset adapter\n");
5802 adapter->tx_timeout_count++;
5803
5804 ixgbe_reinit_locked(adapter);
5805}
5806
7086400d
AD		 5807/**
5808 * ixgbe_service_task - manages and runs subtasks
5809 * @work: pointer to work_struct containing our data
5810 **/
5811static void ixgbe_service_task(struct work_struct *work)
5812{
5813 struct ixgbe_adapter *adapter = container_of(work,
5814 struct ixgbe_adapter,
5815 service_task);
5816
c83c6cbd 5817 ixgbe_reset_subtask(adapter);
7086400d
AD		 5818 ixgbe_sfp_detection_subtask(adapter);
5819 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5820 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5821 ixgbe_watchdog_subtask(adapter);
d034acf1 5822 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5823 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5824#ifdef CONFIG_IXGBE_PTP
5825 ixgbe_ptp_overflow_check(adapter);
5826#endif
7086400d
AD		 5827
5828 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5829}
5830
fd0db0ed
AD		 5831static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5832 struct ixgbe_tx_buffer *first,
244e27ad 5833 u8 *hdr_len)
897ab156 5834{
fd0db0ed 5835 struct sk_buff *skb = first->skb;
897ab156
AD		 5836 u32 vlan_macip_lens, type_tucmd;
5837 u32 mss_l4len_idx, l4len;
9a799d71 5838
897ab156
AD		 5839 if (!skb_is_gso(skb))
5840 return 0;
9a799d71 5841
897ab156 5842 if (skb_header_cloned(skb)) {
244e27ad 5843 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5844 if (err)
5845 return err;
9a799d71 5846 }
9a799d71 5847
897ab156
AD		 5848 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5849 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5850
244e27ad 5851 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5852 struct iphdr *iph = ip_hdr(skb);
5853 iph->tot_len = 0;
5854 iph->check = 0;
5855 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5856 iph->daddr, 0,
5857 IPPROTO_TCP,
5858 0);
5859 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5860 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5861 IXGBE_TX_FLAGS_CSUM |
5862 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5863 } else if (skb_is_gso_v6(skb)) {
5864 ipv6_hdr(skb)->payload_len = 0;
5865 tcp_hdr(skb)->check =
5866 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5867 &ipv6_hdr(skb)->daddr,
5868 0, IPPROTO_TCP, 0);
244e27ad
AD		 5869 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5870 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5871 }
5872
091a6246 5873 /* compute header lengths */
897ab156
AD		 5874 l4len = tcp_hdrlen(skb);
5875 *hdr_len = skb_transport_offset(skb) + l4len;
5876
091a6246
AD		 5877 /* update gso size and bytecount with header size */
5878 first->gso_segs = skb_shinfo(skb)->gso_segs;
5879 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5880
897ab156
AD		 5881 /* mss_l4len_id: use 1 as index for TSO */
5882 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5883 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5884 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5885
5886 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5887 vlan_macip_lens = skb_network_header_len(skb);
5888 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5889 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5890
5891 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5892 mss_l4len_idx);
897ab156
AD		 5893
5894 return 1;
5895}
5896
244e27ad
AD		 5897static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5898 struct ixgbe_tx_buffer *first)
7ca647bd 5899{
fd0db0ed 5900 struct sk_buff *skb = first->skb;
897ab156
AD		 5901 u32 vlan_macip_lens = 0;
5902 u32 mss_l4len_idx = 0;
5903 u32 type_tucmd = 0;
7ca647bd 5904
897ab156 5905 if (skb->ip_summed != CHECKSUM_PARTIAL) {
62748b7b
AD		 5906 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN)) {
5907 if (unlikely(skb->no_fcs))
5908 first->tx_flags |= IXGBE_TX_FLAGS_NO_IFCS;
5909 if (!(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5910 return;
5911 }
897ab156
AD		 5912 } else {
5913 u8 l4_hdr = 0;
244e27ad 5914 switch (first->protocol) {
897ab156
AD		 5915 case __constant_htons(ETH_P_IP):
5916 vlan_macip_lens |= skb_network_header_len(skb);
5917 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5918 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5919 break;
897ab156
AD		 5920 case __constant_htons(ETH_P_IPV6):
5921 vlan_macip_lens |= skb_network_header_len(skb);
5922 l4_hdr = ipv6_hdr(skb)->nexthdr;
5923 break;
5924 default:
5925 if (unlikely(net_ratelimit())) {
5926 dev_warn(tx_ring->dev,
5927 "partial checksum but proto=%x!\n",
244e27ad 5928 first->protocol);
897ab156 5929 }
7ca647bd
JP		 5930 break;
5931 }
897ab156
AD		 5932
5933 switch (l4_hdr) {
7ca647bd 5934 case IPPROTO_TCP:
897ab156
AD		 5935 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5936 mss_l4len_idx = tcp_hdrlen(skb) <<
5937 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5938 break;
5939 case IPPROTO_SCTP:
897ab156
AD		 5940 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5941 mss_l4len_idx = sizeof(struct sctphdr) <<
5942 IXGBE_ADVTXD_L4LEN_SHIFT;
5943 break;
5944 case IPPROTO_UDP:
5945 mss_l4len_idx = sizeof(struct udphdr) <<
5946 IXGBE_ADVTXD_L4LEN_SHIFT;
5947 break;
5948 default:
5949 if (unlikely(net_ratelimit())) {
5950 dev_warn(tx_ring->dev,
5951 "partial checksum but l4 proto=%x!\n",
244e27ad 5952 l4_hdr);
897ab156 5953 }
7ca647bd
JP		 5954 break;
5955 }
244e27ad
AD		 5956
5957 /* update TX checksum flag */
5958 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 5959 }
5960
244e27ad 5961 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 5962 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5963 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 5964
897ab156
AD		 5965 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5966 type_tucmd, mss_l4len_idx);
9a799d71
AK		 5967}
5968
d3d00239 5969static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 5970{
d3d00239
AD		 5971 /* set type for advanced descriptor with frame checksum insertion */
5972 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
d3d00239 5973 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 5974
d3d00239 5975 /* set HW vlan bit if vlan is present */
66f32a8b 5976 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 5977 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 5978
3a6a4eda
JK		 5979#ifdef CONFIG_IXGBE_PTP
5980 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5981 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5982#endif
5983
d3d00239
AD		 5984 /* set segmentation enable bits for TSO/FSO */
5985#ifdef IXGBE_FCOE
93f5b3c1 5986 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 5987#else
5988 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5989#endif
5990 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 5991
62748b7b
AD		 5992 /* insert frame checksum */
5993 if (!(tx_flags & IXGBE_TX_FLAGS_NO_IFCS))
5994 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS);
5995
d3d00239
AD		 5996 return cmd_type;
5997}
9a799d71 5998
729739b7
AD		 5999static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6000 u32 tx_flags, unsigned int paylen)
d3d00239 6001{
93f5b3c1 6002 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 6003
d3d00239
AD		 6004 /* enable L4 checksum for TSO and TX checksum offload */
6005 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6006 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6007
93f5b3c1
AD		 6008 /* enble IPv4 checksum for TSO */
6009 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6010 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6011
93f5b3c1
AD		 6012 /* use index 1 context for TSO/FSO/FCOE */
6013#ifdef IXGBE_FCOE
6014 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
6015#else
6016 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 6017#endif
93f5b3c1
AD		 6018 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
6019
7f9643fd
AD		 6020 /*
6021 * Check Context must be set if Tx switch is enabled, which it
6022 * always is for case where virtual functions are running
6023 */
93f5b3c1
AD		 6024#ifdef IXGBE_FCOE
6025 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
6026#else
7f9643fd 6027 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 6028#endif
7f9643fd
AD		 6029 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6030
729739b7 6031 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 6032}
44df32c5 6033
d3d00239
AD		 6034#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6035 IXGBE_TXD_CMD_RS)
6036
6037static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6038 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6039 const u8 hdr_len)
6040{
729739b7 6041 dma_addr_t dma;
fd0db0ed 6042 struct sk_buff *skb = first->skb;
729739b7 6043 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6044 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6045 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6046 unsigned int data_len = skb->data_len;
6047 unsigned int size = skb_headlen(skb);
729739b7 6048 unsigned int paylen = skb->len - hdr_len;
244e27ad 6049 u32 tx_flags = first->tx_flags;
729739b7 6050 __le32 cmd_type;
d3d00239 6051 u16 i = tx_ring->next_to_use;
d3d00239 6052
729739b7
AD		 6053 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6054
6055 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6056 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6057
d3d00239
AD		 6058#ifdef IXGBE_FCOE
6059 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6060 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6061 size -= sizeof(struct fcoe_crc_eof) - data_len;
6062 data_len = 0;
729739b7
AD		 6063 } else {
6064 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6065 }
6066 }
44df32c5 6067
d3d00239 6068#endif
729739b7
AD		 6069 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6070 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6071 goto dma_error;
8ad494b0 6072
729739b7
AD		 6073 /* record length, and DMA address */
6074 dma_unmap_len_set(first, len, size);
6075 dma_unmap_addr_set(first, dma, dma);
9a799d71 6076
729739b7 6077 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6078
d3d00239 6079 for (;;) {
729739b7 6080 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6081 tx_desc->read.cmd_type_len =
6082 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6083
d3d00239 6084 i++;
729739b7 6085 tx_desc++;
d3d00239 6086 if (i == tx_ring->count) {
e4f74028 6087 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6088 i = 0;
6089 }
729739b7
AD		 6090
6091 dma += IXGBE_MAX_DATA_PER_TXD;
6092 size -= IXGBE_MAX_DATA_PER_TXD;
6093
6094 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6095 tx_desc->read.olinfo_status = 0;
d3d00239 6096 }
e5a43549 6097
729739b7
AD		 6098 if (likely(!data_len))
6099 break;
9a799d71 6100
d3d00239 6101 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6102
729739b7
AD		 6103 i++;
6104 tx_desc++;
6105 if (i == tx_ring->count) {
6106 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6107 i = 0;
6108 }
9a799d71 6109
d3d00239 6110#ifdef IXGBE_FCOE
9e903e08 6111 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6112#else
9e903e08 6113 size = skb_frag_size(frag);
d3d00239
AD		 6114#endif
6115 data_len -= size;
9a799d71 6116
729739b7
AD		 6117 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6118 DMA_TO_DEVICE);
6119 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6120 goto dma_error;
9a799d71 6121
729739b7
AD		 6122 tx_buffer = &tx_ring->tx_buffer_info[i];
6123 dma_unmap_len_set(tx_buffer, len, size);
6124 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6125
729739b7
AD		 6126 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6127 tx_desc->read.olinfo_status = 0;
9a799d71 6128
729739b7
AD		 6129 frag++;
6130 }
9a799d71 6131
729739b7
AD		 6132 /* write last descriptor with RS and EOP bits */
6133 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6134 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6135
091a6246 6136 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6137
d3d00239
AD		 6138 /* set the timestamp */
6139 first->time_stamp = jiffies;
9a799d71
AK		 6140
6141 /*
729739b7
AD		 6142 * Force memory writes to complete before letting h/w know there
6143 * are new descriptors to fetch. (Only applicable for weak-ordered
6144 * memory model archs, such as IA-64).
6145 *
6146 * We also need this memory barrier to make certain all of the
6147 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6148 */
6149 wmb();
6150
d3d00239
AD		 6151 /* set next_to_watch value indicating a packet is present */
6152 first->next_to_watch = tx_desc;
6153
729739b7
AD		 6154 i++;
6155 if (i == tx_ring->count)
6156 i = 0;
6157
6158 tx_ring->next_to_use = i;
6159
d3d00239 6160 /* notify HW of packet */
84ea2591 6161 writel(i, tx_ring->tail);
d3d00239
AD		 6162
6163 return;
6164dma_error:
729739b7 6165 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6166
6167 /* clear dma mappings for failed tx_buffer_info map */
6168 for (;;) {
729739b7
AD		 6169 tx_buffer = &tx_ring->tx_buffer_info[i];
6170 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6171 if (tx_buffer == first)
d3d00239
AD		 6172 break;
6173 if (i == 0)
6174 i = tx_ring->count;
6175 i--;
6176 }
6177
d3d00239 6178 tx_ring->next_to_use = i;
9a799d71
AK		 6179}
6180
fd0db0ed 6181static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6182 struct ixgbe_tx_buffer *first)
69830529
AD		 6183{
6184 struct ixgbe_q_vector *q_vector = ring->q_vector;
6185 union ixgbe_atr_hash_dword input = { .dword = 0 };
6186 union ixgbe_atr_hash_dword common = { .dword = 0 };
6187 union {
6188 unsigned char *network;
6189 struct iphdr *ipv4;
6190 struct ipv6hdr *ipv6;
6191 } hdr;
ee9e0f0b 6192 struct tcphdr *th;
905e4a41 6193 __be16 vlan_id;
c4cf55e5 6194
69830529
AD		 6195 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6196 if (!q_vector)
6197 return;
6198
6199 /* do nothing if sampling is disabled */
6200 if (!ring->atr_sample_rate)
d3ead241 6201 return;
c4cf55e5 6202
69830529 6203 ring->atr_count++;
c4cf55e5 6204
69830529 6205 /* snag network header to get L4 type and address */
fd0db0ed 6206 hdr.network = skb_network_header(first->skb);
69830529
AD		 6207
6208 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6209 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6210 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6211 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6212 hdr.ipv4->protocol != IPPROTO_TCP))
6213 return;
ee9e0f0b 6214
fd0db0ed 6215 th = tcp_hdr(first->skb);
c4cf55e5 6216
66f32a8b
AD		 6217 /* skip this packet since it is invalid or the socket is closing */
6218 if (!th || th->fin)
69830529
AD		 6219 return;
6220
6221 /* sample on all syn packets or once every atr sample count */
6222 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6223 return;
6224
6225 /* reset sample count */
6226 ring->atr_count = 0;
6227
244e27ad 6228 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6229
6230 /*
6231 * src and dst are inverted, think how the receiver sees them
6232 *
6233 * The input is broken into two sections, a non-compressed section
6234 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6235 * is XORed together and stored in the compressed dword.
6236 */
6237 input.formatted.vlan_id = vlan_id;
6238
6239 /*
6240 * since src port and flex bytes occupy the same word XOR them together
6241 * and write the value to source port portion of compressed dword
6242 */
244e27ad 6243 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6244 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6245 else
244e27ad 6246 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6247 common.port.dst ^= th->source;
6248
244e27ad 6249 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6250 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6251 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6252 } else {
6253 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6254 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6255 hdr.ipv6->saddr.s6_addr32[1] ^
6256 hdr.ipv6->saddr.s6_addr32[2] ^
6257 hdr.ipv6->saddr.s6_addr32[3] ^
6258 hdr.ipv6->daddr.s6_addr32[0] ^
6259 hdr.ipv6->daddr.s6_addr32[1] ^
6260 hdr.ipv6->daddr.s6_addr32[2] ^
6261 hdr.ipv6->daddr.s6_addr32[3];
6262 }
c4cf55e5
PWJ		 6263
6264 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6265 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6266 input, common, ring->queue_index);
c4cf55e5
PWJ		 6267}
6268
63544e9c 6269static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6270{
fc77dc3c 6271 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6272 /* Herbert's original patch had:
6273 * smp_mb__after_netif_stop_queue();
6274 * but since that doesn't exist yet, just open code it. */
6275 smp_mb();
6276
6277 /* We need to check again in a case another CPU has just
6278 * made room available. */
7d4987de 6279 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6280 return -EBUSY;
6281
6282 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6283 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6284 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6285 return 0;
6286}
6287
82d4e46e 6288static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6289{
7d4987de 6290 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6291 return 0;
fc77dc3c 6292 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6293}
6294
09a3b1f8
SH		 6295static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6296{
6297 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6298 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6299 smp_processor_id();
56075a98 6300#ifdef IXGBE_FCOE
6440752c 6301 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6302
e5b64635
JF		 6303 if (((protocol == htons(ETH_P_FCOE)) ||
6304 (protocol == htons(ETH_P_FIP))) &&
6305 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6306 struct ixgbe_ring_feature *f;
6307
6308 f = &adapter->ring_feature[RING_F_FCOE];
6309
6310 while (txq >= f->indices)
6311 txq -= f->indices;
e4b317e9 6312 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6313
e5b64635 6314 return txq;
56075a98
JF		 6315 }
6316#endif
6317
fdd3d631
KK		 6318 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6319 while (unlikely(txq >= dev->real_num_tx_queues))
6320 txq -= dev->real_num_tx_queues;
5f715823 6321 return txq;
fdd3d631 6322 }
c4cf55e5 6323
09a3b1f8
SH		 6324 return skb_tx_hash(dev, skb);
6325}
6326
fc77dc3c 6327netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6328 struct ixgbe_adapter *adapter,
6329 struct ixgbe_ring *tx_ring)
9a799d71 6330{
d3d00239 6331 struct ixgbe_tx_buffer *first;
5f715823 6332 int tso;
d3d00239 6333 u32 tx_flags = 0;
a535c30e
AD		 6334#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6335 unsigned short f;
6336#endif
a535c30e 6337 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6338 __be16 protocol = skb->protocol;
63544e9c 6339 u8 hdr_len = 0;
5e09a105 6340
a535c30e
AD		 6341 /*
6342 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6343 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6344 * + 2 desc gap to keep tail from touching head,
6345 * + 1 desc for context descriptor,
6346 * otherwise try next time
6347 */
6348#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6349 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6350 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6351#else
6352 count += skb_shinfo(skb)->nr_frags;
6353#endif
6354 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6355 tx_ring->tx_stats.tx_busy++;
6356 return NETDEV_TX_BUSY;
6357 }
6358
fd0db0ed
AD		 6359 /* record the location of the first descriptor for this packet */
6360 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6361 first->skb = skb;
091a6246
AD		 6362 first->bytecount = skb->len;
6363 first->gso_segs = 1;
fd0db0ed 6364
66f32a8b 6365 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6366 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6367 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6368 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6369 /* else if it is a SW VLAN check the next protocol and store the tag */
6370 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6371 struct vlan_hdr *vhdr, _vhdr;
6372 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6373 if (!vhdr)
6374 goto out_drop;
6375
6376 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6377 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6378 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6379 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6380 }
6381
aa7bd467
JK		 6382 skb_tx_timestamp(skb);
6383
3a6a4eda
JK		 6384#ifdef CONFIG_IXGBE_PTP
6385 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6386 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6387 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6388 }
6389#endif
6390
9e0c5648
AD		 6391#ifdef CONFIG_PCI_IOV
6392 /*
6393 * Use the l2switch_enable flag - would be false if the DMA
6394 * Tx switch had been disabled.
6395 */
6396 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6397 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6398
6399#endif
32701dc2 6400 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6401 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6402 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6403 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6404 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6405 tx_flags |= (skb->priority & 0x7) <<
6406 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6407 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6408 struct vlan_ethhdr *vhdr;
6409 if (skb_header_cloned(skb) &&
6410 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6411 goto out_drop;
6412 vhdr = (struct vlan_ethhdr *)skb->data;
6413 vhdr->h_vlan_TCI = htons(tx_flags >>
6414 IXGBE_TX_FLAGS_VLAN_SHIFT);
6415 } else {
6416 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6417 }
9a799d71 6418 }
eacd73f7 6419
244e27ad
AD		 6420 /* record initial flags and protocol */
6421 first->tx_flags = tx_flags;
6422 first->protocol = protocol;
6423
eacd73f7 6424#ifdef IXGBE_FCOE
66f32a8b
AD		 6425 /* setup tx offload for FCoE */
6426 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6427 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6428 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6429 if (tso < 0)
6430 goto out_drop;
9a799d71 6431
66f32a8b 6432 goto xmit_fcoe;
eacd73f7 6433 }
9a799d71 6434
66f32a8b 6435#endif /* IXGBE_FCOE */
244e27ad 6436 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6437 if (tso < 0)
897ab156 6438 goto out_drop;
244e27ad
AD		 6439 else if (!tso)
6440 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6441
6442 /* add the ATR filter if ATR is on */
6443 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6444 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6445
6446#ifdef IXGBE_FCOE
6447xmit_fcoe:
6448#endif /* IXGBE_FCOE */
244e27ad 6449 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6450
6451 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6452
6453 return NETDEV_TX_OK;
897ab156
AD		 6454
6455out_drop:
fd0db0ed
AD		 6456 dev_kfree_skb_any(first->skb);
6457 first->skb = NULL;
6458
897ab156 6459 return NETDEV_TX_OK;
9a799d71
AK		 6460}
6461
a50c29dd
AD		 6462static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6463 struct net_device *netdev)
84418e3b
AD		 6464{
6465 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6466 struct ixgbe_ring *tx_ring;
6467
a50c29dd
AD		 6468 /*
6469 * The minimum packet size for olinfo paylen is 17 so pad the skb
6470 * in order to meet this minimum size requirement.
6471 */
f73332fc
SH		 6472 if (unlikely(skb->len < 17)) {
6473 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6474 return NETDEV_TX_OK;
6475 skb->len = 17;
6476 }
6477
84418e3b 6478 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6479 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6480}
6481
9a799d71
AK		 6482/**
6483 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6484 * @netdev: network interface device structure
6485 * @p: pointer to an address structure
6486 *
6487 * Returns 0 on success, negative on failure
6488 **/
6489static int ixgbe_set_mac(struct net_device *netdev, void *p)
6490{
6491 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6492 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6493 struct sockaddr *addr = p;
6494
6495 if (!is_valid_ether_addr(addr->sa_data))
6496 return -EADDRNOTAVAIL;
6497
6498 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6499 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6500
1d9c0bfd 6501 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6502
6503 return 0;
6504}
6505
6b73e10d
BH		 6506static int
6507ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6508{
6509 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6510 struct ixgbe_hw *hw = &adapter->hw;
6511 u16 value;
6512 int rc;
6513
6514 if (prtad != hw->phy.mdio.prtad)
6515 return -EINVAL;
6516 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6517 if (!rc)
6518 rc = value;
6519 return rc;
6520}
6521
6522static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6523 u16 addr, u16 value)
6524{
6525 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6526 struct ixgbe_hw *hw = &adapter->hw;
6527
6528 if (prtad != hw->phy.mdio.prtad)
6529 return -EINVAL;
6530 return hw->phy.ops.write_reg(hw, addr, devad, value);
6531}
6532
6533static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6534{
6535 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6536
3a6a4eda
JK		 6537 switch (cmd) {
6538#ifdef CONFIG_IXGBE_PTP
6539 case SIOCSHWTSTAMP:
6540 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6541#endif
6542 default:
6543 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6544 }
6b73e10d
BH		 6545}
6546
0365e6e4
PW		 6547/**
6548 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6549 * netdev->dev_addrs
0365e6e4
PW		 6550 * @netdev: network interface device structure
6551 *
6552 * Returns non-zero on failure
6553 **/
6554static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6555{
6556 int err = 0;
6557 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6558 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6559
7fa7c9dc 6560 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6561 rtnl_lock();
7fa7c9dc 6562 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6563 rtnl_unlock();
7fa7c9dc
AD		 6564
6565 /* update SAN MAC vmdq pool selection */
6566 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6567 }
6568 return err;
6569}
6570
6571/**
6572 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6573 * netdev->dev_addrs
0365e6e4
PW		 6574 * @netdev: network interface device structure
6575 *
6576 * Returns non-zero on failure
6577 **/
6578static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6579{
6580 int err = 0;
6581 struct ixgbe_adapter *adapter = netdev_priv(dev);
6582 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6583
6584 if (is_valid_ether_addr(mac->san_addr)) {
6585 rtnl_lock();
6586 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6587 rtnl_unlock();
6588 }
6589 return err;
6590}
6591
9a799d71
AK		 6592#ifdef CONFIG_NET_POLL_CONTROLLER
6593/*
6594 * Polling 'interrupt' - used by things like netconsole to send skbs
6595 * without having to re-enable interrupts. It's not called while
6596 * the interrupt routine is executing.
6597 */
6598static void ixgbe_netpoll(struct net_device *netdev)
6599{
6600 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6601 int i;
9a799d71 6602
1a647bd2
AD		 6603 /* if interface is down do nothing */
6604 if (test_bit(__IXGBE_DOWN, &adapter->state))
6605 return;
6606
9a799d71 6607 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6608 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6609 for (i = 0; i < adapter->num_q_vectors; i++)
6610 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6611 } else {
6612 ixgbe_intr(adapter->pdev->irq, netdev);
6613 }
9a799d71 6614 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6615}
9a799d71 6616
581330ba 6617#endif
de1036b1
ED		 6618static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6619 struct rtnl_link_stats64 *stats)
6620{
6621 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6622 int i;
6623
1a51502b 6624 rcu_read_lock();
de1036b1 6625 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6626 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6627 u64 bytes, packets;
6628 unsigned int start;
6629
1a51502b
ED		 6630 if (ring) {
6631 do {
6632 start = u64_stats_fetch_begin_bh(&ring->syncp);
6633 packets = ring->stats.packets;
6634 bytes = ring->stats.bytes;
6635 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6636 stats->rx_packets += packets;
6637 stats->rx_bytes += bytes;
6638 }
de1036b1 6639 }
1ac9ad13
ED		 6640
6641 for (i = 0; i < adapter->num_tx_queues; i++) {
6642 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6643 u64 bytes, packets;
6644 unsigned int start;
6645
6646 if (ring) {
6647 do {
6648 start = u64_stats_fetch_begin_bh(&ring->syncp);
6649 packets = ring->stats.packets;
6650 bytes = ring->stats.bytes;
6651 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6652 stats->tx_packets += packets;
6653 stats->tx_bytes += bytes;
6654 }
6655 }
1a51502b 6656 rcu_read_unlock();
de1036b1
ED		 6657 /* following stats updated by ixgbe_watchdog_task() */
6658 stats->multicast = netdev->stats.multicast;
6659 stats->rx_errors = netdev->stats.rx_errors;
6660 stats->rx_length_errors = netdev->stats.rx_length_errors;
6661 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6662 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6663 return stats;
6664}
6665
8af3c33f 6666#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6667/**
6668 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6669 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6670 * @tc: number of traffic classes currently enabled
6671 *
6672 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6673 * 802.1Q priority maps to a packet buffer that exists.
6674 */
6675static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6676{
6677 struct ixgbe_hw *hw = &adapter->hw;
6678 u32 reg, rsave;
6679 int i;
6680
6681 /* 82598 have a static priority to TC mapping that can not
6682 * be changed so no validation is needed.
6683 */
6684 if (hw->mac.type == ixgbe_mac_82598EB)
6685 return;
6686
6687 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6688 rsave = reg;
6689
6690 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6691 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6692
6693 /* If up2tc is out of bounds default to zero */
6694 if (up2tc > tc)
6695 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6696 }
6697
6698 if (reg != rsave)
6699 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6700
6701 return;
6702}
6703
02debdc9
AD		 6704/**
6705 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6706 * @adapter: Pointer to adapter struct
6707 *
6708 * Populate the netdev user priority to tc map
6709 */
6710static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6711{
6712 struct net_device *dev = adapter->netdev;
6713 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6714 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6715 u8 prio;
6716
6717 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6718 u8 tc = 0;
6719
6720 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6721 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6722 else if (ets)
6723 tc = ets->prio_tc[prio];
6724
6725 netdev_set_prio_tc_map(dev, prio, tc);
6726 }
6727}
6728
49ce9c2c
BH		 6729/**
6730 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6731 *
6732 * @netdev: net device to configure
6733 * @tc: number of traffic classes to enable
6734 */
6735int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6736{
8b1c0b24
JF		 6737 struct ixgbe_adapter *adapter = netdev_priv(dev);
6738 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6739
8b1c0b24 6740 /* Hardware supports up to 8 traffic classes */
4de2a022 6741 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6742 (hw->mac.type == ixgbe_mac_82598EB &&
6743 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6744 return -EINVAL;
6745
6746 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6747 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6748 * hardware is not flexible enough to do this dynamically.
6749 */
6750 if (netif_running(dev))
6751 ixgbe_close(dev);
6752 ixgbe_clear_interrupt_scheme(adapter);
6753
e7589eab 6754 if (tc) {
8b1c0b24 6755 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6756 ixgbe_set_prio_tc_map(adapter);
6757
e7589eab 6758 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6759
943561d3
AD		 6760 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6761 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6762 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6763 }
e7589eab 6764 } else {
8b1c0b24 6765 netdev_reset_tc(dev);
02debdc9 6766
943561d3
AD		 6767 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6768 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6769
6770 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6771
6772 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6773 adapter->dcb_cfg.pfc_mode_enable = false;
6774 }
6775
8b1c0b24
JF		 6776 ixgbe_init_interrupt_scheme(adapter);
6777 ixgbe_validate_rtr(adapter, tc);
6778 if (netif_running(dev))
6779 ixgbe_open(dev);
6780
6781 return 0;
6782}
de1036b1 6783
8af3c33f 6784#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6785void ixgbe_do_reset(struct net_device *netdev)
6786{
6787 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6788
6789 if (netif_running(netdev))
6790 ixgbe_reinit_locked(adapter);
6791 else
6792 ixgbe_reset(adapter);
6793}
6794
c8f44aff 6795static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6796 netdev_features_t features)
082757af
DS		 6797{
6798 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6799
082757af 6800 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6801 if (!(features & NETIF_F_RXCSUM))
6802 features &= ~NETIF_F_LRO;
082757af 6803
567d2de2
AD		 6804 /* Turn off LRO if not RSC capable */
6805 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6806 features &= ~NETIF_F_LRO;
8e2813f5 6807
567d2de2 6808 return features;
082757af
DS		 6809}
6810
c8f44aff 6811static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6812 netdev_features_t features)
082757af
DS		 6813{
6814 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6815 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6816 bool need_reset = false;
6817
082757af 6818 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6819 if (!(features & NETIF_F_LRO)) {
6820 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6821 need_reset = true;
567d2de2
AD		 6822 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6823 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6824 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6825 if (adapter->rx_itr_setting == 1 ||
6826 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6827 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6828 need_reset = true;
6829 } else if ((changed ^ features) & NETIF_F_LRO) {
6830 e_info(probe, "rx-usecs set too low, "
6831 "disabling RSC\n");
082757af
DS		 6832 }
6833 }
6834
6835 /*
6836 * Check if Flow Director n-tuple support was enabled or disabled. If
6837 * the state changed, we need to reset.
6838 */
39cb681b
AD		 6839 switch (features & NETIF_F_NTUPLE) {
6840 case NETIF_F_NTUPLE:
567d2de2 6841 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6842 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6843 need_reset = true;
6844
567d2de2
AD		 6845 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6846 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6847 break;
6848 default:
6849 /* turn off perfect filters, enable ATR and reset */
6850 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6851 need_reset = true;
6852
6853 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6854
6855 /* We cannot enable ATR if SR-IOV is enabled */
6856 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6857 break;
6858
6859 /* We cannot enable ATR if we have 2 or more traffic classes */
6860 if (netdev_get_num_tc(netdev) > 1)
6861 break;
6862
6863 /* We cannot enable ATR if RSS is disabled */
6864 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6865 break;
6866
6867 /* A sample rate of 0 indicates ATR disabled */
6868 if (!adapter->atr_sample_rate)
6869 break;
6870
6871 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6872 break;
082757af
DS		 6873 }
6874
146d4cc9
JF		 6875 if (features & NETIF_F_HW_VLAN_RX)
6876 ixgbe_vlan_strip_enable(adapter);
6877 else
6878 ixgbe_vlan_strip_disable(adapter);
6879
3f2d1c0f
BG		 6880 if (changed & NETIF_F_RXALL)
6881 need_reset = true;
6882
567d2de2 6883 netdev->features = features;
082757af
DS		 6884 if (need_reset)
6885 ixgbe_do_reset(netdev);
6886
6887 return 0;
082757af
DS		 6888}
6889
0f4b0add
JF		 6890static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6891 struct net_device *dev,
6892 unsigned char *addr,
6893 u16 flags)
6894{
6895 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6896 int err;
6897
6898 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6899 return -EOPNOTSUPP;
0f4b0add
JF		 6900
6901 if (ndm->ndm_state & NUD_PERMANENT) {
6902 pr_info("%s: FDB only supports static addresses\n",
6903 ixgbe_driver_name);
6904 return -EINVAL;
6905 }
6906
95447461
JF		 6907 if (is_unicast_ether_addr(addr)) {
6908 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6909
6910 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6911 err = dev_uc_add_excl(dev, addr);
0f4b0add 6912 else
95447461
JF		 6913 err = -ENOMEM;
6914 } else if (is_multicast_ether_addr(addr)) {
6915 err = dev_mc_add_excl(dev, addr);
6916 } else {
6917 err = -EINVAL;
0f4b0add
JF		 6918 }
6919
6920 /* Only return duplicate errors if NLM_F_EXCL is set */
6921 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6922 err = 0;
6923
6924 return err;
6925}
6926
6927static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6928 struct net_device *dev,
6929 unsigned char *addr)
6930{
6931 struct ixgbe_adapter *adapter = netdev_priv(dev);
6932 int err = -EOPNOTSUPP;
6933
6934 if (ndm->ndm_state & NUD_PERMANENT) {
6935 pr_info("%s: FDB only supports static addresses\n",
6936 ixgbe_driver_name);
6937 return -EINVAL;
6938 }
6939
6940 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6941 if (is_unicast_ether_addr(addr))
6942 err = dev_uc_del(dev, addr);
6943 else if (is_multicast_ether_addr(addr))
6944 err = dev_mc_del(dev, addr);
6945 else
6946 err = -EINVAL;
6947 }
6948
6949 return err;
6950}
6951
6952static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6953 struct netlink_callback *cb,
6954 struct net_device *dev,
6955 int idx)
6956{
6957 struct ixgbe_adapter *adapter = netdev_priv(dev);
6958
6959 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6960 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6961
6962 return idx;
6963}
6964
0edc3527 6965static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6966 .ndo_open = ixgbe_open,
0edc3527 6967 .ndo_stop = ixgbe_close,
00829823 6968 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6969 .ndo_select_queue = ixgbe_select_queue,
581330ba 6970 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6971 .ndo_validate_addr = eth_validate_addr,
6972 .ndo_set_mac_address = ixgbe_set_mac,
6973 .ndo_change_mtu = ixgbe_change_mtu,
6974 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6975 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6976 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6977 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6978 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6979 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6980 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 6981 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 6982 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6983 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 6984#ifdef CONFIG_IXGBE_DCB
24095aa3 6985 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 6986#endif
0edc3527
SH		 6987#ifdef CONFIG_NET_POLL_CONTROLLER
6988 .ndo_poll_controller = ixgbe_netpoll,
6989#endif
332d4a7d
YZ		 6990#ifdef IXGBE_FCOE
6991 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 6992 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 6993 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6994 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6995 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6996 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 6997 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 6998#endif /* IXGBE_FCOE */
082757af
DS		 6999 .ndo_set_features = ixgbe_set_features,
7000 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 7001 .ndo_fdb_add = ixgbe_ndo_fdb_add,
7002 .ndo_fdb_del = ixgbe_ndo_fdb_del,
7003 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 7004};
7005
8e2813f5
JK		 7006/**
7007 * ixgbe_wol_supported - Check whether device supports WoL
7008 * @hw: hw specific details
7009 * @device_id: the device ID
7010 * @subdev_id: the subsystem device ID
7011 *
7012 * This function is used by probe and ethtool to determine
7013 * which devices have WoL support
7014 *
7015 **/
7016int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7017 u16 subdevice_id)
7018{
7019 struct ixgbe_hw *hw = &adapter->hw;
7020 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7021 int is_wol_supported = 0;
7022
7023 switch (device_id) {
7024 case IXGBE_DEV_ID_82599_SFP:
7025 /* Only these subdevices could supports WOL */
7026 switch (subdevice_id) {
7027 case IXGBE_SUBDEV_ID_82599_560FLR:
7028 /* only support first port */
7029 if (hw->bus.func != 0)
7030 break;
7031 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7032 case IXGBE_SUBDEV_ID_82599_RNDC:
8e2813f5
JK		 7033 is_wol_supported = 1;
7034 break;
7035 }
7036 break;
7037 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7038 /* All except this subdevice support WOL */
7039 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7040 is_wol_supported = 1;
7041 break;
7042 case IXGBE_DEV_ID_82599_KX4:
7043 is_wol_supported = 1;
7044 break;
7045 case IXGBE_DEV_ID_X540T:
7046 /* check eeprom to see if enabled wol */
7047 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7048 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7049 (hw->bus.func == 0))) {
7050 is_wol_supported = 1;
7051 }
7052 break;
7053 }
7054
7055 return is_wol_supported;
7056}
7057
9a799d71
AK		 7058/**
7059 * ixgbe_probe - Device Initialization Routine
7060 * @pdev: PCI device information struct
7061 * @ent: entry in ixgbe_pci_tbl
7062 *
7063 * Returns 0 on success, negative on failure
7064 *
7065 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7066 * The OS initialization, configuring of the adapter private structure,
7067 * and a hardware reset occur.
7068 **/
7069static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7070 const struct pci_device_id *ent)
9a799d71
AK		 7071{
7072 struct net_device *netdev;
7073 struct ixgbe_adapter *adapter = NULL;
7074 struct ixgbe_hw *hw;
7075 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7076 static int cards_found;
7077 int i, err, pci_using_dac;
289700db 7078 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7079 unsigned int indices = num_possible_cpus();
3f4a6f00 7080 unsigned int dcb_max = 0;
eacd73f7
YZ		 7081#ifdef IXGBE_FCOE
7082 u16 device_caps;
7083#endif
289700db 7084 u32 eec;
9a799d71 7085
bded64a7
AG		 7086 /* Catch broken hardware that put the wrong VF device ID in
7087 * the PCIe SR-IOV capability.
7088 */
7089 if (pdev->is_virtfn) {
7090 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7091 pci_name(pdev), pdev->vendor, pdev->device);
7092 return -EINVAL;
7093 }
7094
9ce77666 7095 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7096 if (err)
7097 return err;
7098
1b507730
NN		 7099 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7100 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7101 pci_using_dac = 1;
7102 } else {
1b507730 7103 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7104 if (err) {
1b507730
NN		 7105 err = dma_set_coherent_mask(&pdev->dev,
7106 DMA_BIT_MASK(32));
9a799d71 7107 if (err) {
b8bc0421
DC		 7108 dev_err(&pdev->dev,
7109 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7110 goto err_dma;
7111 }
7112 }
7113 pci_using_dac = 0;
7114 }
7115
9ce77666 7116 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7117 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7118 if (err) {
b8bc0421
DC		 7119 dev_err(&pdev->dev,
7120 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7121 goto err_pci_reg;
7122 }
7123
19d5afd4 7124 pci_enable_pcie_error_reporting(pdev);
6fabd715 7125
9a799d71 7126 pci_set_master(pdev);
fb3b27bc 7127 pci_save_state(pdev);
9a799d71 7128
e901acd6 7129#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7130 if (ii->mac == ixgbe_mac_82598EB)
7131 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7132 IXGBE_MAX_RSS_INDICES);
7133 else
7134 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7135 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7136#endif
7137
c85a2618
JF		 7138 if (ii->mac == ixgbe_mac_82598EB)
7139 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7140 else
7141 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7142
e901acd6 7143#ifdef IXGBE_FCOE
c85a2618
JF		 7144 indices += min_t(unsigned int, num_possible_cpus(),
7145 IXGBE_MAX_FCOE_INDICES);
7146#endif
3f4a6f00 7147 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7148 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7149 if (!netdev) {
7150 err = -ENOMEM;
7151 goto err_alloc_etherdev;
7152 }
7153
9a799d71
AK		 7154 SET_NETDEV_DEV(netdev, &pdev->dev);
7155
9a799d71 7156 adapter = netdev_priv(netdev);
c60fbb00 7157 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7158
7159 adapter->netdev = netdev;
7160 adapter->pdev = pdev;
7161 hw = &adapter->hw;
7162 hw->back = adapter;
b3f4d599 7163 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7164
05857980 7165 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7166 pci_resource_len(pdev, 0));
9a799d71
AK		 7167 if (!hw->hw_addr) {
7168 err = -EIO;
7169 goto err_ioremap;
7170 }
7171
0edc3527 7172 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7173 ixgbe_set_ethtool_ops(netdev);
9a799d71 7174 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7175 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7176
9a799d71
AK		 7177 adapter->bd_number = cards_found;
7178
9a799d71
AK		 7179 /* Setup hw api */
7180 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7181 hw->mac.type = ii->mac;
9a799d71 7182
c44ade9e
JB		 7183 /* EEPROM */
7184 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7185 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7186 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7187 if (!(eec & (1 << 8)))
7188 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7189
7190 /* PHY */
7191 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7192 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7193 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7194 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7195 hw->phy.mdio.mmds = 0;
7196 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7197 hw->phy.mdio.dev = netdev;
7198 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7199 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7200
8ca783ab 7201 ii->get_invariants(hw);
9a799d71
AK		 7202
7203 /* setup the private structure */
7204 err = ixgbe_sw_init(adapter);
7205 if (err)
7206 goto err_sw_init;
7207
e86bff0e 7208 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7209 switch (adapter->hw.mac.type) {
7210 case ixgbe_mac_82599EB:
7211 case ixgbe_mac_X540:
e86bff0e 7212 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7213 break;
7214 default:
7215 break;
7216 }
e86bff0e 7217
bf069c97
DS		 7218 /*
7219 * If there is a fan on this device and it has failed log the
7220 * failure.
7221 */
7222 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7223 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7224 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7225 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7226 }
7227
8ef78adc
PWJ		 7228 if (allow_unsupported_sfp)
7229 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7230
c44ade9e 7231 /* reset_hw fills in the perm_addr as well */
119fc60a 7232 hw->phy.reset_if_overtemp = true;
c44ade9e 7233 err = hw->mac.ops.reset_hw(hw);
119fc60a 7234 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7235 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7236 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7237 err = 0;
7238 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7239 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7240 "module type was detected.\n");
7241 e_dev_err("Reload the driver after installing a supported "
7242 "module.\n");
04f165ef
PW		 7243 goto err_sw_init;
7244 } else if (err) {
849c4542 7245 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7246 goto err_sw_init;
7247 }
7248
99d74487
AD		 7249#ifdef CONFIG_PCI_IOV
7250 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7251
99d74487 7252#endif
396e799c 7253 netdev->features = NETIF_F_SG |
e8e9f696 7254 NETIF_F_IP_CSUM |
082757af 7255 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7256 NETIF_F_HW_VLAN_TX |
7257 NETIF_F_HW_VLAN_RX |
082757af
DS		 7258 NETIF_F_HW_VLAN_FILTER |
7259 NETIF_F_TSO |
7260 NETIF_F_TSO6 |
082757af
DS		 7261 NETIF_F_RXHASH |
7262 NETIF_F_RXCSUM;
9a799d71 7263
082757af 7264 netdev->hw_features = netdev->features;
ad31c402 7265
58be7666
DS		 7266 switch (adapter->hw.mac.type) {
7267 case ixgbe_mac_82599EB:
7268 case ixgbe_mac_X540:
45a5ead0 7269 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7270 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7271 NETIF_F_NTUPLE;
58be7666
DS		 7272 break;
7273 default:
7274 break;
7275 }
45a5ead0 7276
3f2d1c0f
BG		 7277 netdev->hw_features |= NETIF_F_RXALL;
7278
ad31c402
JK		 7279 netdev->vlan_features |= NETIF_F_TSO;
7280 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7281 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7282 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7283 netdev->vlan_features |= NETIF_F_SG;
7284
01789349 7285 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7286 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7287
7a6b6f51 7288#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7289 netdev->dcbnl_ops = &dcbnl_ops;
7290#endif
7291
eacd73f7 7292#ifdef IXGBE_FCOE
0d551589 7293 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7294 if (hw->mac.ops.get_device_caps) {
7295 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7296 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7297 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7298 }
7c8ae65a
AD		 7299
7300 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7301
a58915c7
AD		 7302 netdev->features |= NETIF_F_FSO |
7303 NETIF_F_FCOE_CRC;
7304
7c8ae65a
AD		 7305 netdev->vlan_features |= NETIF_F_FSO |
7306 NETIF_F_FCOE_CRC |
7307 NETIF_F_FCOE_MTU;
5e09d7f6 7308 }
eacd73f7 7309#endif /* IXGBE_FCOE */
7b872a55 7310 if (pci_using_dac) {
9a799d71 7311 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7312 netdev->vlan_features |= NETIF_F_HIGHDMA;
7313 }
9a799d71 7314
082757af
DS		 7315 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7316 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7317 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7318 netdev->features |= NETIF_F_LRO;
7319
9a799d71 7320 /* make sure the EEPROM is good */
c44ade9e 7321 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7322 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7323 err = -EIO;
35937c05 7324 goto err_sw_init;
9a799d71
AK		 7325 }
7326
7327 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7328 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7329
c44ade9e 7330 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7331 e_dev_err("invalid MAC address\n");
9a799d71 7332 err = -EIO;
35937c05 7333 goto err_sw_init;
9a799d71
AK		 7334 }
7335
7086400d 7336 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7337 (unsigned long) adapter);
9a799d71 7338
7086400d
AD		 7339 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7340 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7341
021230d4
AV		 7342 err = ixgbe_init_interrupt_scheme(adapter);
7343 if (err)
7344 goto err_sw_init;
9a799d71 7345
8e2813f5 7346 /* WOL not supported for all devices */
c23f5b6b 7347 adapter->wol = 0;
8e2813f5
JK		 7348 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7349 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7350 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7351
e8e26350
PW		 7352 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7353
3a6a4eda
JK		 7354#ifdef CONFIG_IXGBE_PTP
7355 ixgbe_ptp_init(adapter);
7356#endif /* CONFIG_IXGBE_PTP*/
7357
15e5209f
ET		 7358 /* save off EEPROM version number */
7359 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7360 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7361
04f165ef
PW		 7362 /* pick up the PCI bus settings for reporting later */
7363 hw->mac.ops.get_bus_info(hw);
7364
9a799d71 7365 /* print bus type/speed/width info */
849c4542 7366 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7367 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7368 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7369 "Unknown"),
7370 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7371 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7372 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7373 "Unknown"),
7374 netdev->dev_addr);
289700db
DS		 7375
7376 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7377 if (err)
9fe93afd 7378 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7379 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7380 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7381 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7382 part_str);
e8e26350 7383 else
289700db
DS		 7384 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7385 hw->mac.type, hw->phy.type, part_str);
9a799d71 7386
e8e26350 7387 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7388 e_dev_warn("PCI-Express bandwidth available for this card is "
7389 "not sufficient for optimal performance.\n");
7390 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7391 "is required.\n");
0c254d86
AK		 7392 }
7393
9a799d71 7394 /* reset the hardware with the new settings */
794caeb2 7395 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7396 if (err == IXGBE_ERR_EEPROM_VERSION) {
7397 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7398 e_dev_warn("This device is a pre-production adapter/LOM. "
7399 "Please be aware there may be issues associated "
7400 "with your hardware. If you are experiencing "
7401 "problems please contact your Intel or hardware "
7402 "representative who provided you with this "
7403 "hardware.\n");
794caeb2 7404 }
9a799d71
AK		 7405 strcpy(netdev->name, "eth%d");
7406 err = register_netdev(netdev);
7407 if (err)
7408 goto err_register;
7409
93d3ce8f
ET		 7410 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7411 if (hw->mac.ops.disable_tx_laser &&
7412 ((hw->phy.multispeed_fiber) ||
7413 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7414 (hw->mac.type == ixgbe_mac_82599EB))))
7415 hw->mac.ops.disable_tx_laser(hw);
7416
54386467
JB		 7417 /* carrier off reporting is important to ethtool even BEFORE open */
7418 netif_carrier_off(netdev);
7419
5dd2d332 7420#ifdef CONFIG_IXGBE_DCA
652f093f 7421 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7422 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7423 ixgbe_setup_dca(adapter);
7424 }
7425#endif
1cdd1ec8 7426 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7427 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7428 for (i = 0; i < adapter->num_vfs; i++)
7429 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7430 }
7431
2466dd9c
JK		 7432 /* firmware requires driver version to be 0xFFFFFFFF
7433 * since os does not support feature
7434 */
9612de92 7435 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7436 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7437 0xFF);
9612de92 7438
0365e6e4
PW		 7439 /* add san mac addr to netdev */
7440 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7441
ea81875a 7442 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7443 cards_found++;
3ca8bc6d 7444
1210982b 7445#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7446 if (ixgbe_sysfs_init(adapter))
7447 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7448#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7449
9a799d71
AK		 7450 return 0;
7451
7452err_register:
5eba3699 7453 ixgbe_release_hw_control(adapter);
7a921c93 7454 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7455err_sw_init:
99d74487 7456 ixgbe_disable_sriov(adapter);
7086400d 7457 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7458 iounmap(hw->hw_addr);
7459err_ioremap:
7460 free_netdev(netdev);
7461err_alloc_etherdev:
e8e9f696
JP		 7462 pci_release_selected_regions(pdev,
7463 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7464err_pci_reg:
7465err_dma:
7466 pci_disable_device(pdev);
7467 return err;
7468}
7469
7470/**
7471 * ixgbe_remove - Device Removal Routine
7472 * @pdev: PCI device information struct
7473 *
7474 * ixgbe_remove is called by the PCI subsystem to alert the driver
7475 * that it should release a PCI device. The could be caused by a
7476 * Hot-Plug event, or because the driver is going to be removed from
7477 * memory.
7478 **/
7479static void __devexit ixgbe_remove(struct pci_dev *pdev)
7480{
c60fbb00
AD		 7481 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7482 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7483
7484 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7485 cancel_work_sync(&adapter->service_task);
9a799d71 7486
3a6a4eda
JK		 7487#ifdef CONFIG_IXGBE_PTP
7488 ixgbe_ptp_stop(adapter);
7489#endif
7490
5dd2d332 7491#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7492 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7493 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7494 dca_remove_requester(&pdev->dev);
7495 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7496 }
7497
7498#endif
1210982b 7499#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7500 ixgbe_sysfs_exit(adapter);
1210982b 7501#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7502
0365e6e4
PW		 7503 /* remove the added san mac */
7504 ixgbe_del_sanmac_netdev(netdev);
7505
c4900be0
DS		 7506 if (netdev->reg_state == NETREG_REGISTERED)
7507 unregister_netdev(netdev);
9a799d71 7508
9297127b 7509 ixgbe_disable_sriov(adapter);
1cdd1ec8 7510
7a921c93 7511 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7512
021230d4 7513 ixgbe_release_hw_control(adapter);
9a799d71 7514
2b1588c3
AD		 7515#ifdef CONFIG_DCB
7516 kfree(adapter->ixgbe_ieee_pfc);
7517 kfree(adapter->ixgbe_ieee_ets);
7518
7519#endif
9a799d71 7520 iounmap(adapter->hw.hw_addr);
9ce77666 7521 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7522 IORESOURCE_MEM));
9a799d71 7523
849c4542 7524 e_dev_info("complete\n");
021230d4 7525
9a799d71
AK		 7526 free_netdev(netdev);
7527
19d5afd4 7528 pci_disable_pcie_error_reporting(pdev);
6fabd715 7529
9a799d71
AK		 7530 pci_disable_device(pdev);
7531}
7532
7533/**
7534 * ixgbe_io_error_detected - called when PCI error is detected
7535 * @pdev: Pointer to PCI device
7536 * @state: The current pci connection state
7537 *
7538 * This function is called after a PCI bus error affecting
7539 * this device has been detected.
7540 */
7541static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7542 pci_channel_state_t state)
9a799d71 7543{
c60fbb00
AD		 7544 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7545 struct net_device *netdev = adapter->netdev;
9a799d71 7546
83c61fa9
GR		 7547#ifdef CONFIG_PCI_IOV
7548 struct pci_dev *bdev, *vfdev;
7549 u32 dw0, dw1, dw2, dw3;
7550 int vf, pos;
7551 u16 req_id, pf_func;
7552
7553 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7554 adapter->num_vfs == 0)
7555 goto skip_bad_vf_detection;
7556
7557 bdev = pdev->bus->self;
7558 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7559 bdev = bdev->bus->self;
7560
7561 if (!bdev)
7562 goto skip_bad_vf_detection;
7563
7564 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7565 if (!pos)
7566 goto skip_bad_vf_detection;
7567
7568 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7569 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7570 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7571 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7572
7573 req_id = dw1 >> 16;
7574 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7575 if (!(req_id & 0x0080))
7576 goto skip_bad_vf_detection;
7577
7578 pf_func = req_id & 0x01;
7579 if ((pf_func & 1) == (pdev->devfn & 1)) {
7580 unsigned int device_id;
7581
7582 vf = (req_id & 0x7F) >> 1;
7583 e_dev_err("VF %d has caused a PCIe error\n", vf);
7584 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7585 "%8.8x\tdw3: %8.8x\n",
7586 dw0, dw1, dw2, dw3);
7587 switch (adapter->hw.mac.type) {
7588 case ixgbe_mac_82599EB:
7589 device_id = IXGBE_82599_VF_DEVICE_ID;
7590 break;
7591 case ixgbe_mac_X540:
7592 device_id = IXGBE_X540_VF_DEVICE_ID;
7593 break;
7594 default:
7595 device_id = 0;
7596 break;
7597 }
7598
7599 /* Find the pci device of the offending VF */
36e90319 7600 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7601 while (vfdev) {
7602 if (vfdev->devfn == (req_id & 0xFF))
7603 break;
36e90319 7604 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7605 device_id, vfdev);
7606 }
7607 /*
7608 * There's a slim chance the VF could have been hot plugged,
7609 * so if it is no longer present we don't need to issue the
7610 * VFLR. Just clean up the AER in that case.
7611 */
7612 if (vfdev) {
7613 e_dev_err("Issuing VFLR to VF %d\n", vf);
7614 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7615 }
7616
7617 pci_cleanup_aer_uncorrect_error_status(pdev);
7618 }
7619
7620 /*
7621 * Even though the error may have occurred on the other port
7622 * we still need to increment the vf error reference count for
7623 * both ports because the I/O resume function will be called
7624 * for both of them.
7625 */
7626 adapter->vferr_refcount++;
7627
7628 return PCI_ERS_RESULT_RECOVERED;
7629
7630skip_bad_vf_detection:
7631#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7632 netif_device_detach(netdev);
7633
3044b8d1
BL		 7634 if (state == pci_channel_io_perm_failure)
7635 return PCI_ERS_RESULT_DISCONNECT;
7636
9a799d71
AK		 7637 if (netif_running(netdev))
7638 ixgbe_down(adapter);
7639 pci_disable_device(pdev);
7640
b4617240 7641 /* Request a slot reset. */
9a799d71
AK		 7642 return PCI_ERS_RESULT_NEED_RESET;
7643}
7644
7645/**
7646 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7647 * @pdev: Pointer to PCI device
7648 *
7649 * Restart the card from scratch, as if from a cold-boot.
7650 */
7651static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7652{
c60fbb00 7653 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7654 pci_ers_result_t result;
7655 int err;
9a799d71 7656
9ce77666 7657 if (pci_enable_device_mem(pdev)) {
396e799c 7658 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7659 result = PCI_ERS_RESULT_DISCONNECT;
7660 } else {
7661 pci_set_master(pdev);
7662 pci_restore_state(pdev);
c0e1f68b 7663 pci_save_state(pdev);
9a799d71 7664
dd4d8ca6 7665 pci_wake_from_d3(pdev, false);
9a799d71 7666
6fabd715 7667 ixgbe_reset(adapter);
88512539 7668 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7669 result = PCI_ERS_RESULT_RECOVERED;
7670 }
7671
7672 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7673 if (err) {
849c4542
ET		 7674 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7675 "failed 0x%0x\n", err);
6fabd715
PWJ		 7676 /* non-fatal, continue */
7677 }
9a799d71 7678
6fabd715 7679 return result;
9a799d71
AK		 7680}
7681
7682/**
7683 * ixgbe_io_resume - called when traffic can start flowing again.
7684 * @pdev: Pointer to PCI device
7685 *
7686 * This callback is called when the error recovery driver tells us that
7687 * its OK to resume normal operation.
7688 */
7689static void ixgbe_io_resume(struct pci_dev *pdev)
7690{
c60fbb00
AD		 7691 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7692 struct net_device *netdev = adapter->netdev;
9a799d71 7693
83c61fa9
GR		 7694#ifdef CONFIG_PCI_IOV
7695 if (adapter->vferr_refcount) {
7696 e_info(drv, "Resuming after VF err\n");
7697 adapter->vferr_refcount--;
7698 return;
7699 }
7700
7701#endif
c7ccde0f
AD		 7702 if (netif_running(netdev))
7703 ixgbe_up(adapter);
9a799d71
AK		 7704
7705 netif_device_attach(netdev);
9a799d71
AK		 7706}
7707
7708static struct pci_error_handlers ixgbe_err_handler = {
7709 .error_detected = ixgbe_io_error_detected,
7710 .slot_reset = ixgbe_io_slot_reset,
7711 .resume = ixgbe_io_resume,
7712};
7713
7714static struct pci_driver ixgbe_driver = {
7715 .name = ixgbe_driver_name,
7716 .id_table = ixgbe_pci_tbl,
7717 .probe = ixgbe_probe,
7718 .remove = __devexit_p(ixgbe_remove),
7719#ifdef CONFIG_PM
7720 .suspend = ixgbe_suspend,
7721 .resume = ixgbe_resume,
7722#endif
7723 .shutdown = ixgbe_shutdown,
7724 .err_handler = &ixgbe_err_handler
7725};
7726
7727/**
7728 * ixgbe_init_module - Driver Registration Routine
7729 *
7730 * ixgbe_init_module is the first routine called when the driver is
7731 * loaded. All it does is register with the PCI subsystem.
7732 **/
7733static int __init ixgbe_init_module(void)
7734{
7735 int ret;
c7689578 7736 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7737 pr_info("%s\n", ixgbe_copyright);
9a799d71 7738
5dd2d332 7739#ifdef CONFIG_IXGBE_DCA
bd0362dd 7740 dca_register_notify(&dca_notifier);
bd0362dd 7741#endif
5dd2d332 7742
9a799d71
AK		 7743 ret = pci_register_driver(&ixgbe_driver);
7744 return ret;
7745}
b4617240 7746
9a799d71
AK		 7747module_init(ixgbe_init_module);
7748
7749/**
7750 * ixgbe_exit_module - Driver Exit Cleanup Routine
7751 *
7752 * ixgbe_exit_module is called just before the driver is removed
7753 * from memory.
7754 **/
7755static void __exit ixgbe_exit_module(void)
7756{
5dd2d332 7757#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7758 dca_unregister_notify(&dca_notifier);
7759#endif
9a799d71 7760 pci_unregister_driver(&ixgbe_driver);
1a51502b 7761 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7762}
bd0362dd 7763
5dd2d332 7764#ifdef CONFIG_IXGBE_DCA
bd0362dd 7765static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7766 void *p)
bd0362dd
JC		 7767{
7768 int ret_val;
7769
7770 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7771 __ixgbe_notify_dca);
bd0362dd
JC		 7772
7773 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7774}
b453368d 7775
5dd2d332 7776#endif /* CONFIG_IXGBE_DCA */
849c4542 7777
9a799d71
AK		 7778module_exit(ixgbe_exit_module);
7779
7780/* ixgbe_main.c */
Linux kernel - Deliverables
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