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hyperv: Add hash value into RNDIS Per-packet info
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/ethtool.h>
01789349 46#include <linux/if.h>
9a799d71 47#include <linux/if_vlan.h>
2a47fa45 48#include <linux/if_macvlan.h>
815cccbf 49#include <linux/if_bridge.h>
70c71606 50#include <linux/prefetch.h>
eacd73f7 51#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 52
53#include "ixgbe.h"
54#include "ixgbe_common.h"
ee5f784a 55#include "ixgbe_dcb_82599.h"
1cdd1ec8 56#include "ixgbe_sriov.h"
9a799d71
AK		 57
58char ixgbe_driver_name[] = "ixgbe";
9c8eb720 59static const char ixgbe_driver_string[] =
e8e9f696 60 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 61#ifdef IXGBE_FCOE
ea81875a
NP		 62char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 64#else
65static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67#endif
f341c4e0 68#define DRV_VERSION "3.19.1-k"
9c8eb720 69const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 70static const char ixgbe_copyright[] =
0391bbe3 71 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 72
73static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 74 [board_82598] = &ixgbe_82598_info,
e8e26350 75 [board_82599] = &ixgbe_82599_info,
fe15e8e1 76 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 77};
78
79/* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 118 /* required last entry */
119 {0, }
120};
121MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
5dd2d332 123#ifdef CONFIG_IXGBE_DCA
bd0362dd 124static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 125 void *p);
bd0362dd
JC		 126static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130};
131#endif
132
1cdd1ec8
GR		 133#ifdef CONFIG_PCI_IOV
134static unsigned int max_vfs;
135module_param(max_vfs, uint, 0);
e8e9f696 136MODULE_PARM_DESC(max_vfs,
170e8543 137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 138#endif /* CONFIG_PCI_IOV */
139
8ef78adc
PWJ		 140static unsigned int allow_unsupported_sfp;
141module_param(allow_unsupported_sfp, uint, 0);
142MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
b3f4d599 145#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146static int debug = -1;
147module_param(debug, int, 0);
148MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
9a799d71
AK		 150MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
14438464
MR		 155static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
b8e82001
JK		 157static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159{
b8e82001
JK		 160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
c0798edf 171 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 172 return -1;
173
c0798edf 174 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
b8e82001
JK		 178 return 0;
179}
180
181static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182{
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202}
203
e027d1ae
JK		 204/**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214{
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 218 return true;
219 default:
220 return false;
221 }
222}
223
224static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226{
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
9f0a433c 255 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 273 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282}
283
7086400d
AD		 284static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285{
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290}
291
2a1a091c
MR		 292static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293{
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
58cf663f
MR		 300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 302}
303
f8e2472f 304static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 305{
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321}
322
f8e2472f
MR		 323/**
324 * ixgbe_read_reg - Read from device register
325 * @hw: hw specific details
326 * @reg: offset of register to read
327 *
328 * Returns : value read or IXGBE_FAILED_READ_REG if removed
329 *
330 * This function is used to read device registers. It checks for device
331 * removal by confirming any read that returns all ones by checking the
332 * status register value for all ones. This function avoids reading from
333 * the hardware if a removal was previously detected in which case it
334 * returns IXGBE_FAILED_READ_REG (all ones).
335 */
336u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337{
338 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 u32 value;
340
341 if (ixgbe_removed(reg_addr))
342 return IXGBE_FAILED_READ_REG;
343 value = readl(reg_addr + reg);
344 if (unlikely(value == IXGBE_FAILED_READ_REG))
345 ixgbe_check_remove(hw, reg);
346 return value;
347}
348
14438464
MR		 349static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350{
351 u16 value;
352
353 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 ixgbe_remove_adapter(hw);
356 return true;
357 }
358 return false;
359}
360
361u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362{
363 struct ixgbe_adapter *adapter = hw->back;
364 u16 value;
365
366 if (ixgbe_removed(hw->hw_addr))
367 return IXGBE_FAILED_READ_CFG_WORD;
368 pci_read_config_word(adapter->pdev, reg, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 ixgbe_check_cfg_remove(hw, adapter->pdev))
371 return IXGBE_FAILED_READ_CFG_WORD;
372 return value;
373}
374
375#ifdef CONFIG_PCI_IOV
376static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377{
378 struct ixgbe_adapter *adapter = hw->back;
379 u32 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_DWORD;
383 pci_read_config_dword(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_DWORD;
387 return value;
388}
389#endif /* CONFIG_PCI_IOV */
390
ed19231c
JK		 391void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392{
393 struct ixgbe_adapter *adapter = hw->back;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return;
397 pci_write_config_word(adapter->pdev, reg, value);
398}
399
7086400d
AD		 400static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401{
402 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403
52f33af8 404 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 405 smp_mb__before_clear_bit();
406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407}
408
dcd79aeb
TI		 409struct ixgbe_reg_info {
410 u32 ofs;
411 char *name;
412};
413
414static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415
416 /* General Registers */
417 {IXGBE_CTRL, "CTRL"},
418 {IXGBE_STATUS, "STATUS"},
419 {IXGBE_CTRL_EXT, "CTRL_EXT"},
420
421 /* Interrupt Registers */
422 {IXGBE_EICR, "EICR"},
423
424 /* RX Registers */
425 {IXGBE_SRRCTL(0), "SRRCTL"},
426 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 {IXGBE_RDLEN(0), "RDLEN"},
428 {IXGBE_RDH(0), "RDH"},
429 {IXGBE_RDT(0), "RDT"},
430 {IXGBE_RXDCTL(0), "RXDCTL"},
431 {IXGBE_RDBAL(0), "RDBAL"},
432 {IXGBE_RDBAH(0), "RDBAH"},
433
434 /* TX Registers */
435 {IXGBE_TDBAL(0), "TDBAL"},
436 {IXGBE_TDBAH(0), "TDBAH"},
437 {IXGBE_TDLEN(0), "TDLEN"},
438 {IXGBE_TDH(0), "TDH"},
439 {IXGBE_TDT(0), "TDT"},
440 {IXGBE_TXDCTL(0), "TXDCTL"},
441
442 /* List Terminator */
443 {}
444};
445
446
447/*
448 * ixgbe_regdump - register printout routine
449 */
450static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451{
452 int i = 0, j = 0;
453 char rname[16];
454 u32 regs[64];
455
456 switch (reginfo->ofs) {
457 case IXGBE_SRRCTL(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 break;
461 case IXGBE_DCA_RXCTRL(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 break;
465 case IXGBE_RDLEN(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 break;
469 case IXGBE_RDH(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 break;
473 case IXGBE_RDT(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 break;
477 case IXGBE_RXDCTL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 break;
481 case IXGBE_RDBAL(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 break;
485 case IXGBE_RDBAH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 break;
489 case IXGBE_TDBAL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 break;
493 case IXGBE_TDBAH(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 break;
497 case IXGBE_TDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 break;
501 case IXGBE_TDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 break;
505 case IXGBE_TDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 break;
509 case IXGBE_TXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 break;
513 default:
c7689578 514 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 515 IXGBE_READ_REG(hw, reginfo->ofs));
516 return;
517 }
518
519 for (i = 0; i < 8; i++) {
520 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 521 pr_err("%-15s", rname);
dcd79aeb 522 for (j = 0; j < 8; j++)
c7689578
JP		 523 pr_cont(" %08x", regs[i*8+j]);
524 pr_cont("\n");
dcd79aeb
TI		 525 }
526
527}
528
529/*
530 * ixgbe_dump - Print registers, tx-rings and rx-rings
531 */
532static void ixgbe_dump(struct ixgbe_adapter *adapter)
533{
534 struct net_device *netdev = adapter->netdev;
535 struct ixgbe_hw *hw = &adapter->hw;
536 struct ixgbe_reg_info *reginfo;
537 int n = 0;
538 struct ixgbe_ring *tx_ring;
729739b7 539 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 540 union ixgbe_adv_tx_desc *tx_desc;
541 struct my_u0 { u64 a; u64 b; } *u0;
542 struct ixgbe_ring *rx_ring;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *rx_buffer_info;
545 u32 staterr;
546 int i = 0;
547
548 if (!netif_msg_hw(adapter))
549 return;
550
551 /* Print netdevice Info */
552 if (netdev) {
553 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 554 pr_info("Device Name state "
dcd79aeb 555 "trans_start last_rx\n");
c7689578
JP		 556 pr_info("%-15s %016lX %016lX %016lX\n",
557 netdev->name,
558 netdev->state,
559 netdev->trans_start,
560 netdev->last_rx);
dcd79aeb
TI		 561 }
562
563 /* Print Registers */
564 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 565 pr_info(" Register Name Value\n");
dcd79aeb
TI		 566 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 reginfo->name; reginfo++) {
568 ixgbe_regdump(hw, reginfo);
569 }
570
571 /* Print TX Ring Summary */
572 if (!netdev || !netif_running(netdev))
573 goto exit;
574
575 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 576 pr_info(" %s %s %s %s\n",
577 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
578 "leng", "ntw", "timestamp");
dcd79aeb
TI		 579 for (n = 0; n < adapter->num_tx_queues; n++) {
580 tx_ring = adapter->tx_ring[n];
729739b7 581 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 582 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 583 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 584 (u64)dma_unmap_addr(tx_buffer, dma),
585 dma_unmap_len(tx_buffer, len),
586 tx_buffer->next_to_watch,
587 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 588 }
589
590 /* Print TX Rings */
591 if (!netif_msg_tx_done(adapter))
592 goto rx_ring_summary;
593
594 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595
596 /* Transmit Descriptor Formats
597 *
39ac868a 598 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 599 * +--------------------------------------------------------------+
600 * 0 | Buffer Address [63:0] |
601 * +--------------------------------------------------------------+
39ac868a 602 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 603 * +--------------------------------------------------------------+
604 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 605 *
606 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 * +--------------------------------------------------------------+
608 * 0 | RSV [63:0] |
609 * +--------------------------------------------------------------+
610 * 8 | RSV | STA | NXTSEQ |
611 * +--------------------------------------------------------------+
612 * 63 36 35 32 31 0
613 *
614 * 82599+ Advanced Transmit Descriptor
615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
618 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
621 *
622 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | RSV |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
dcd79aeb
TI		 629 */
630
631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
c7689578
JP		 633 pr_info("------------------------------------\n");
634 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 pr_info("------------------------------------\n");
8ad88e37
JH		 636 pr_info("%s%s %s %s %s %s\n",
637 "T [desc] [address 63:0 ] ",
638 "[PlPOIdStDDt Ln] [bi->dma ] ",
639 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 640
641 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 642 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 643 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 644 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 645 if (dma_unmap_len(tx_buffer, len) > 0) {
646 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
647 i,
648 le64_to_cpu(u0->a),
649 le64_to_cpu(u0->b),
650 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 651 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 652 tx_buffer->next_to_watch,
653 (u64)tx_buffer->time_stamp,
654 tx_buffer->skb);
655 if (i == tx_ring->next_to_use &&
656 i == tx_ring->next_to_clean)
657 pr_cont(" NTC/U\n");
658 else if (i == tx_ring->next_to_use)
659 pr_cont(" NTU\n");
660 else if (i == tx_ring->next_to_clean)
661 pr_cont(" NTC\n");
662 else
663 pr_cont("\n");
664
665 if (netif_msg_pktdata(adapter) &&
666 tx_buffer->skb)
667 print_hex_dump(KERN_INFO, "",
668 DUMP_PREFIX_ADDRESS, 16, 1,
669 tx_buffer->skb->data,
670 dma_unmap_len(tx_buffer, len),
671 true);
672 }
dcd79aeb
TI		 673 }
674 }
675
676 /* Print RX Rings Summary */
677rx_ring_summary:
678 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 679 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 680 for (n = 0; n < adapter->num_rx_queues; n++) {
681 rx_ring = adapter->rx_ring[n];
c7689578
JP		 682 pr_info("%5d %5X %5X\n",
683 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 684 }
685
686 /* Print RX Rings */
687 if (!netif_msg_rx_status(adapter))
688 goto exit;
689
690 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691
39ac868a
JH		 692 /* Receive Descriptor Formats
693 *
694 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 695 * 63 1 0
696 * +-----------------------------------------------------+
697 * 0 | Packet Buffer Address [63:1] |A0/NSE|
698 * +----------------------------------------------+------+
699 * 8 | Header Buffer Address [63:1] | DD |
700 * +-----------------------------------------------------+
701 *
702 *
39ac868a 703 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 704 *
705 * 63 48 47 32 31 30 21 20 16 15 4 3 0
706 * +------------------------------------------------------+
39ac868a
JH		 707 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
708 * | Packet | IP | | | | Type | Type |
709 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 710 * +------------------------------------------------------+
711 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 * +------------------------------------------------------+
713 * 63 48 47 32 31 20 19 0
39ac868a
JH		 714 *
715 * 82599+ Advanced Receive Descriptor (Read) Format
716 * 63 1 0
717 * +-----------------------------------------------------+
718 * 0 | Packet Buffer Address [63:1] |A0/NSE|
719 * +----------------------------------------------+------+
720 * 8 | Header Buffer Address [63:1] | DD |
721 * +-----------------------------------------------------+
722 *
723 *
724 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 *
726 * 63 48 47 32 31 30 21 20 17 16 4 3 0
727 * +------------------------------------------------------+
728 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
729 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
730 * |/ Flow Dir Flt ID | | | | | |
731 * +------------------------------------------------------+
732 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 * +------------------------------------------------------+
734 * 63 48 47 32 31 20 19 0
dcd79aeb 735 */
39ac868a 736
dcd79aeb
TI		 737 for (n = 0; n < adapter->num_rx_queues; n++) {
738 rx_ring = adapter->rx_ring[n];
c7689578
JP		 739 pr_info("------------------------------------\n");
740 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 pr_info("------------------------------------\n");
8ad88e37
JH		 742 pr_info("%s%s%s",
743 "R [desc] [ PktBuf A0] ",
744 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 745 "<-- Adv Rx Read format\n");
8ad88e37
JH		 746 pr_info("%s%s%s",
747 "RWB[desc] [PcsmIpSHl PtRs] ",
748 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 749 "<-- Adv Rx Write-Back format\n");
750
751 for (i = 0; i < rx_ring->count; i++) {
752 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 753 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 754 u0 = (struct my_u0 *)rx_desc;
755 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 if (staterr & IXGBE_RXD_STAT_DD) {
757 /* Descriptor Done */
c7689578 758 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 759 "%016llX ---------------- %p", i,
760 le64_to_cpu(u0->a),
761 le64_to_cpu(u0->b),
762 rx_buffer_info->skb);
763 } else {
c7689578 764 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 765 "%016llX %016llX %p", i,
766 le64_to_cpu(u0->a),
767 le64_to_cpu(u0->b),
768 (u64)rx_buffer_info->dma,
769 rx_buffer_info->skb);
770
9c50c035
ET		 771 if (netif_msg_pktdata(adapter) &&
772 rx_buffer_info->dma) {
dcd79aeb
TI		 773 print_hex_dump(KERN_INFO, "",
774 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 775 page_address(rx_buffer_info->page) +
776 rx_buffer_info->page_offset,
f800326d 777 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 778 }
779 }
780
781 if (i == rx_ring->next_to_use)
c7689578 782 pr_cont(" NTU\n");
dcd79aeb 783 else if (i == rx_ring->next_to_clean)
c7689578 784 pr_cont(" NTC\n");
dcd79aeb 785 else
c7689578 786 pr_cont("\n");
dcd79aeb
TI		 787
788 }
789 }
790
791exit:
792 return;
793}
794
5eba3699
AV		 795static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
796{
797 u32 ctrl_ext;
798
799 /* Let firmware take over control of h/w */
800 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
801 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 802 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 803}
804
805static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
806{
807 u32 ctrl_ext;
808
809 /* Let firmware know the driver has taken over */
810 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
811 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 812 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 813}
9a799d71 814
49ce9c2c 815/**
e8e26350
PW		 816 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
817 * @adapter: pointer to adapter struct
818 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
819 * @queue: queue to map the corresponding interrupt to
820 * @msix_vector: the vector to map to the corresponding queue
821 *
822 */
823static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 824 u8 queue, u8 msix_vector)
9a799d71
AK		 825{
826 u32 ivar, index;
e8e26350
PW		 827 struct ixgbe_hw *hw = &adapter->hw;
828 switch (hw->mac.type) {
829 case ixgbe_mac_82598EB:
830 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
831 if (direction == -1)
832 direction = 0;
833 index = (((direction * 64) + queue) >> 2) & 0x1F;
834 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
835 ivar &= ~(0xFF << (8 * (queue & 0x3)));
836 ivar |= (msix_vector << (8 * (queue & 0x3)));
837 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
838 break;
839 case ixgbe_mac_82599EB:
b93a2226 840 case ixgbe_mac_X540:
e8e26350
PW		 841 if (direction == -1) {
842 /* other causes */
843 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
844 index = ((queue & 1) * 8);
845 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
846 ivar &= ~(0xFF << index);
847 ivar |= (msix_vector << index);
848 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
849 break;
850 } else {
851 /* tx or rx causes */
852 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
853 index = ((16 * (queue & 1)) + (8 * direction));
854 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
855 ivar &= ~(0xFF << index);
856 ivar |= (msix_vector << index);
857 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
858 break;
859 }
860 default:
861 break;
862 }
9a799d71
AK		 863}
864
fe49f04a 865static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 866 u64 qmask)
fe49f04a
AD		 867{
868 u32 mask;
869
bd508178
AD		 870 switch (adapter->hw.mac.type) {
871 case ixgbe_mac_82598EB:
fe49f04a
AD		 872 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
873 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 874 break;
875 case ixgbe_mac_82599EB:
b93a2226 876 case ixgbe_mac_X540:
fe49f04a
AD		 877 mask = (qmask & 0xFFFFFFFF);
878 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
879 mask = (qmask >> 32);
880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 881 break;
882 default:
883 break;
fe49f04a
AD		 884 }
885}
886
729739b7
AD		 887void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
888 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 889{
729739b7
AD		 890 if (tx_buffer->skb) {
891 dev_kfree_skb_any(tx_buffer->skb);
892 if (dma_unmap_len(tx_buffer, len))
d3d00239 893 dma_unmap_single(ring->dev,
729739b7
AD		 894 dma_unmap_addr(tx_buffer, dma),
895 dma_unmap_len(tx_buffer, len),
896 DMA_TO_DEVICE);
897 } else if (dma_unmap_len(tx_buffer, len)) {
898 dma_unmap_page(ring->dev,
899 dma_unmap_addr(tx_buffer, dma),
900 dma_unmap_len(tx_buffer, len),
901 DMA_TO_DEVICE);
e5a43549 902 }
729739b7
AD		 903 tx_buffer->next_to_watch = NULL;
904 tx_buffer->skb = NULL;
905 dma_unmap_len_set(tx_buffer, len, 0);
906 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 907}
908
943561d3 909static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 910{
911 struct ixgbe_hw *hw = &adapter->hw;
912 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 913 int i;
943561d3 914 u32 data;
c84d324c 915
943561d3
AD		 916 if ((hw->fc.current_mode != ixgbe_fc_full) &&
917 (hw->fc.current_mode != ixgbe_fc_rx_pause))
918 return;
c84d324c 919
943561d3
AD		 920 switch (hw->mac.type) {
921 case ixgbe_mac_82598EB:
922 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
923 break;
924 default:
925 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
926 }
927 hwstats->lxoffrxc += data;
c84d324c 928
943561d3
AD		 929 /* refill credits (no tx hang) if we received xoff */
930 if (!data)
c84d324c 931 return;
943561d3
AD		 932
933 for (i = 0; i < adapter->num_tx_queues; i++)
934 clear_bit(__IXGBE_HANG_CHECK_ARMED,
935 &adapter->tx_ring[i]->state);
936}
937
938static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
939{
940 struct ixgbe_hw *hw = &adapter->hw;
941 struct ixgbe_hw_stats *hwstats = &adapter->stats;
942 u32 xoff[8] = {0};
2afaa00d 943 u8 tc;
943561d3
AD		 944 int i;
945 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
946
947 if (adapter->ixgbe_ieee_pfc)
948 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
949
950 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
951 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 952 return;
943561d3 953 }
c84d324c
JF		 954
955 /* update stats for each tc, only valid with PFC enabled */
956 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 957 u32 pxoffrxc;
958
c84d324c
JF		 959 switch (hw->mac.type) {
960 case ixgbe_mac_82598EB:
2afaa00d 961 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 962 break;
c84d324c 963 default:
2afaa00d 964 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 965 }
2afaa00d
PN		 966 hwstats->pxoffrxc[i] += pxoffrxc;
967 /* Get the TC for given UP */
968 tc = netdev_get_prio_tc_map(adapter->netdev, i);
969 xoff[tc] += pxoffrxc;
c84d324c
JF		 970 }
971
972 /* disarm tx queues that have received xoff frames */
973 for (i = 0; i < adapter->num_tx_queues; i++) {
974 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 975
2afaa00d 976 tc = tx_ring->dcb_tc;
c84d324c
JF		 977 if (xoff[tc])
978 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 979 }
26f23d82
YZ		 980}
981
c84d324c 982static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 983{
7d7ce682 984 return ring->stats.packets;
c84d324c
JF		 985}
986
987static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
988{
2a47fa45
JF		 989 struct ixgbe_adapter *adapter;
990 struct ixgbe_hw *hw;
991 u32 head, tail;
992
993 if (ring->l2_accel_priv)
994 adapter = ring->l2_accel_priv->real_adapter;
995 else
996 adapter = netdev_priv(ring->netdev);
e01c31a5 997
2a47fa45
JF		 998 hw = &adapter->hw;
999 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1000 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1001
1002 if (head != tail)
1003 return (head < tail) ?
1004 tail - head : (tail + ring->count - head);
1005
1006 return 0;
1007}
1008
1009static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1010{
1011 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1012 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1013 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1014 bool ret = false;
1015
7d637bcc 1016 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1017
1018 /*
1019 * Check for a hung queue, but be thorough. This verifies
1020 * that a transmit has been completed since the previous
1021 * check AND there is at least one packet pending. The
1022 * ARMED bit is set to indicate a potential hang. The
1023 * bit is cleared if a pause frame is received to remove
1024 * false hang detection due to PFC or 802.3x frames. By
1025 * requiring this to fail twice we avoid races with
1026 * pfc clearing the ARMED bit and conditions where we
1027 * run the check_tx_hang logic with a transmit completion
1028 * pending but without time to complete it yet.
1029 */
1030 if ((tx_done_old == tx_done) && tx_pending) {
1031 /* make sure it is true for two checks in a row */
1032 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1033 &tx_ring->state);
1034 } else {
1035 /* update completed stats and continue */
1036 tx_ring->tx_stats.tx_done_old = tx_done;
1037 /* reset the countdown */
1038 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 1039 }
1040
c84d324c 1041 return ret;
9a799d71
AK		 1042}
1043
c83c6cbd
AD		 1044/**
1045 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1046 * @adapter: driver private struct
1047 **/
1048static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1049{
1050
1051 /* Do the reset outside of interrupt context */
1052 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1053 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1054 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1055 ixgbe_service_event_schedule(adapter);
1056 }
1057}
e01c31a5 1058
9a799d71
AK		 1059/**
1060 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1061 * @q_vector: structure containing interrupt and ring information
e01c31a5 1062 * @tx_ring: tx ring to clean
9a799d71 1063 **/
fe49f04a 1064static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1065 struct ixgbe_ring *tx_ring)
9a799d71 1066{
fe49f04a 1067 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1068 struct ixgbe_tx_buffer *tx_buffer;
1069 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1070 unsigned int total_bytes = 0, total_packets = 0;
59224555 1071 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1072 unsigned int i = tx_ring->next_to_clean;
1073
1074 if (test_bit(__IXGBE_DOWN, &adapter->state))
1075 return true;
9a799d71 1076
d3d00239 1077 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1078 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1079 i -= tx_ring->count;
12207e49 1080
729739b7 1081 do {
d3d00239
AD		 1082 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1083
1084 /* if next_to_watch is not set then there is no work pending */
1085 if (!eop_desc)
1086 break;
1087
7f83a9e6 1088 /* prevent any other reads prior to eop_desc */
7e63bf49 1089 read_barrier_depends();
7f83a9e6 1090
d3d00239
AD		 1091 /* if DD is not set pending work has not been completed */
1092 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1093 break;
8ad494b0 1094
d3d00239
AD		 1095 /* clear next_to_watch to prevent false hangs */
1096 tx_buffer->next_to_watch = NULL;
8ad494b0 1097
091a6246
AD		 1098 /* update the statistics for this packet */
1099 total_bytes += tx_buffer->bytecount;
1100 total_packets += tx_buffer->gso_segs;
1101
fd0db0ed
AD		 1102 /* free the skb */
1103 dev_kfree_skb_any(tx_buffer->skb);
1104
729739b7
AD		 1105 /* unmap skb header data */
1106 dma_unmap_single(tx_ring->dev,
1107 dma_unmap_addr(tx_buffer, dma),
1108 dma_unmap_len(tx_buffer, len),
1109 DMA_TO_DEVICE);
1110
fd0db0ed
AD		 1111 /* clear tx_buffer data */
1112 tx_buffer->skb = NULL;
729739b7 1113 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1114
729739b7
AD		 1115 /* unmap remaining buffers */
1116 while (tx_desc != eop_desc) {
d3d00239
AD		 1117 tx_buffer++;
1118 tx_desc++;
8ad494b0 1119 i++;
729739b7
AD		 1120 if (unlikely(!i)) {
1121 i -= tx_ring->count;
d3d00239 1122 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1123 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1124 }
e01c31a5 1125
729739b7
AD		 1126 /* unmap any remaining paged data */
1127 if (dma_unmap_len(tx_buffer, len)) {
1128 dma_unmap_page(tx_ring->dev,
1129 dma_unmap_addr(tx_buffer, dma),
1130 dma_unmap_len(tx_buffer, len),
1131 DMA_TO_DEVICE);
1132 dma_unmap_len_set(tx_buffer, len, 0);
1133 }
1134 }
1135
1136 /* move us one more past the eop_desc for start of next pkt */
1137 tx_buffer++;
1138 tx_desc++;
1139 i++;
1140 if (unlikely(!i)) {
1141 i -= tx_ring->count;
1142 tx_buffer = tx_ring->tx_buffer_info;
1143 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1144 }
1145
1146 /* issue prefetch for next Tx descriptor */
1147 prefetch(tx_desc);
12207e49 1148
729739b7
AD		 1149 /* update budget accounting */
1150 budget--;
1151 } while (likely(budget));
1152
1153 i += tx_ring->count;
9a799d71 1154 tx_ring->next_to_clean = i;
d3d00239 1155 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1156 tx_ring->stats.bytes += total_bytes;
bd198058 1157 tx_ring->stats.packets += total_packets;
d3d00239 1158 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1159 q_vector->tx.total_bytes += total_bytes;
1160 q_vector->tx.total_packets += total_packets;
b953799e 1161
c84d324c
JF		 1162 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1163 /* schedule immediate reset if we believe we hung */
1164 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1165 e_err(drv, "Detected Tx Unit Hang\n"
1166 " Tx Queue <%d>\n"
1167 " TDH, TDT <%x>, <%x>\n"
1168 " next_to_use <%x>\n"
1169 " next_to_clean <%x>\n"
1170 "tx_buffer_info[next_to_clean]\n"
1171 " time_stamp <%lx>\n"
1172 " jiffies <%lx>\n",
1173 tx_ring->queue_index,
1174 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1175 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1176 tx_ring->next_to_use, i,
1177 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1178
1179 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1180
1181 e_info(probe,
1182 "tx hang %d detected on queue %d, resetting adapter\n",
1183 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1184
b953799e 1185 /* schedule immediate reset if we believe we hung */
c83c6cbd 1186 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1187
1188 /* the adapter is about to reset, no point in enabling stuff */
59224555 1189 return true;
b953799e 1190 }
9a799d71 1191
b2d96e0a
AD		 1192 netdev_tx_completed_queue(txring_txq(tx_ring),
1193 total_packets, total_bytes);
1194
e092be60 1195#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1196 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1197 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1198 /* Make sure that anybody stopping the queue after this
1199 * sees the new next_to_clean.
1200 */
1201 smp_mb();
729739b7
AD		 1202 if (__netif_subqueue_stopped(tx_ring->netdev,
1203 tx_ring->queue_index)
1204 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1205 netif_wake_subqueue(tx_ring->netdev,
1206 tx_ring->queue_index);
5b7da515 1207 ++tx_ring->tx_stats.restart_queue;
30eba97a 1208 }
e092be60 1209 }
9a799d71 1210
59224555 1211 return !!budget;
9a799d71
AK		 1212}
1213
5dd2d332 1214#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1215static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1216 struct ixgbe_ring *tx_ring,
33cf09c9 1217 int cpu)
bd0362dd 1218{
33cf09c9 1219 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1220 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1221 u16 reg_offset;
33cf09c9 1222
33cf09c9
AD		 1223 switch (hw->mac.type) {
1224 case ixgbe_mac_82598EB:
bdda1a61 1225 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1226 break;
1227 case ixgbe_mac_82599EB:
b93a2226 1228 case ixgbe_mac_X540:
bdda1a61
AD		 1229 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1230 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1231 break;
1232 default:
bdda1a61
AD		 1233 /* for unknown hardware do not write register */
1234 return;
bd0362dd 1235 }
bdda1a61
AD		 1236
1237 /*
1238 * We can enable relaxed ordering for reads, but not writes when
1239 * DCA is enabled. This is due to a known issue in some chipsets
1240 * which will cause the DCA tag to be cleared.
1241 */
1242 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1243 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1244 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1245
1246 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1247}
1248
bdda1a61
AD		 1249static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1250 struct ixgbe_ring *rx_ring,
33cf09c9 1251 int cpu)
bd0362dd 1252{
33cf09c9 1253 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1254 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1255 u8 reg_idx = rx_ring->reg_idx;
1256
33cf09c9
AD		 1257
1258 switch (hw->mac.type) {
33cf09c9 1259 case ixgbe_mac_82599EB:
b93a2226 1260 case ixgbe_mac_X540:
bdda1a61 1261 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1262 break;
1263 default:
1264 break;
1265 }
bdda1a61
AD		 1266
1267 /*
1268 * We can enable relaxed ordering for reads, but not writes when
1269 * DCA is enabled. This is due to a known issue in some chipsets
1270 * which will cause the DCA tag to be cleared.
1271 */
1272 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1273 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1274
1275 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1276}
1277
1278static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1279{
1280 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1281 struct ixgbe_ring *ring;
bd0362dd 1282 int cpu = get_cpu();
bd0362dd 1283
33cf09c9
AD		 1284 if (q_vector->cpu == cpu)
1285 goto out_no_update;
1286
a557928e 1287 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1288 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1289
a557928e 1290 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1291 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1292
1293 q_vector->cpu = cpu;
1294out_no_update:
bd0362dd
JC		 1295 put_cpu();
1296}
1297
1298static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1299{
1300 int i;
1301
1302 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1303 return;
1304
e35ec126
AD		 1305 /* always use CB2 mode, difference is masked in the CB driver */
1306 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1307
49c7ffbe 1308 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1309 adapter->q_vector[i]->cpu = -1;
1310 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1311 }
1312}
1313
1314static int __ixgbe_notify_dca(struct device *dev, void *data)
1315{
c60fbb00 1316 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1317 unsigned long event = *(unsigned long *)data;
1318
2a72c31e 1319 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1320 return 0;
1321
bd0362dd
JC		 1322 switch (event) {
1323 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1324 /* if we're already enabled, don't do it again */
1325 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1326 break;
652f093f 1327 if (dca_add_requester(dev) == 0) {
96b0e0f6 1328 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1329 ixgbe_setup_dca(adapter);
1330 break;
1331 }
1332 /* Fall Through since DCA is disabled. */
1333 case DCA_PROVIDER_REMOVE:
1334 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1335 dca_remove_requester(dev);
1336 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1338 }
1339 break;
1340 }
1341
652f093f 1342 return 0;
bd0362dd 1343}
67a74ee2 1344
bdda1a61 1345#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1346static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1347 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1348 struct sk_buff *skb)
1349{
8a0da21b 1350 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1351 skb_set_hash(skb,
1352 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1353 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1354}
1355
f800326d 1356#ifdef IXGBE_FCOE
ff886dfc
AD		 1357/**
1358 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1359 * @ring: structure containing ring specific data
ff886dfc
AD		 1360 * @rx_desc: advanced rx descriptor
1361 *
1362 * Returns : true if it is FCoE pkt
1363 */
57efd44c 1364static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1365 union ixgbe_adv_rx_desc *rx_desc)
1366{
1367 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1368
57efd44c 1369 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1370 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1371 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1372 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1373}
1374
f800326d 1375#endif /* IXGBE_FCOE */
e59bd25d
AV		 1376/**
1377 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1378 * @ring: structure containing ring specific data
1379 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1380 * @skb: skb currently being received and modified
1381 **/
8a0da21b 1382static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1383 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1384 struct sk_buff *skb)
9a799d71 1385{
8a0da21b 1386 skb_checksum_none_assert(skb);
9a799d71 1387
712744be 1388 /* Rx csum disabled */
8a0da21b 1389 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1390 return;
e59bd25d
AV		 1391
1392 /* if IP and error */
f56e0cb1
AD		 1393 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1394 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1395 ring->rx_stats.csum_err++;
9a799d71
AK		 1396 return;
1397 }
e59bd25d 1398
f56e0cb1 1399 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1400 return;
1401
f56e0cb1 1402 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1403 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1404
1405 /*
1406 * 82599 errata, UDP frames with a 0 checksum can be marked as
1407 * checksum errors.
1408 */
8a0da21b
AD		 1409 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1410 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1411 return;
1412
8a0da21b 1413 ring->rx_stats.csum_err++;
e59bd25d
AV		 1414 return;
1415 }
1416
9a799d71 1417 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1418 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1419}
1420
84ea2591 1421static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1422{
f56e0cb1 1423 rx_ring->next_to_use = val;
f800326d
AD		 1424
1425 /* update next to alloc since we have filled the ring */
1426 rx_ring->next_to_alloc = val;
e8e26350
PW		 1427 /*
1428 * Force memory writes to complete before letting h/w
1429 * know there are new descriptors to fetch. (Only
1430 * applicable for weak-ordered memory model archs,
1431 * such as IA-64).
1432 */
1433 wmb();
84227bcd 1434 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1435}
1436
f990b79b
AD		 1437static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1438 struct ixgbe_rx_buffer *bi)
1439{
1440 struct page *page = bi->page;
f800326d 1441 dma_addr_t dma = bi->dma;
f990b79b 1442
f800326d
AD		 1443 /* since we are recycling buffers we should seldom need to alloc */
1444 if (likely(dma))
f990b79b
AD		 1445 return true;
1446
f800326d
AD		 1447 /* alloc new page for storage */
1448 if (likely(!page)) {
0614002b
MG		 1449 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1450 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1451 if (unlikely(!page)) {
1452 rx_ring->rx_stats.alloc_rx_page_failed++;
1453 return false;
1454 }
f800326d 1455 bi->page = page;
f990b79b
AD		 1456 }
1457
f800326d
AD		 1458 /* map page for use */
1459 dma = dma_map_page(rx_ring->dev, page, 0,
1460 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1461
1462 /*
1463 * if mapping failed free memory back to system since
1464 * there isn't much point in holding memory we can't use
1465 */
1466 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1467 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1468 bi->page = NULL;
f990b79b 1469
f990b79b
AD		 1470 rx_ring->rx_stats.alloc_rx_page_failed++;
1471 return false;
1472 }
1473
f800326d 1474 bi->dma = dma;
afaa9459 1475 bi->page_offset = 0;
f800326d 1476
f990b79b
AD		 1477 return true;
1478}
1479
9a799d71 1480/**
f990b79b 1481 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1482 * @rx_ring: ring to place buffers on
1483 * @cleaned_count: number of buffers to replace
9a799d71 1484 **/
fc77dc3c 1485void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1486{
9a799d71 1487 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1488 struct ixgbe_rx_buffer *bi;
d5f398ed 1489 u16 i = rx_ring->next_to_use;
9a799d71 1490
f800326d
AD		 1491 /* nothing to do */
1492 if (!cleaned_count)
fc77dc3c
AD		 1493 return;
1494
e4f74028 1495 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1496 bi = &rx_ring->rx_buffer_info[i];
1497 i -= rx_ring->count;
9a799d71 1498
f800326d
AD		 1499 do {
1500 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1501 break;
d5f398ed 1502
f800326d
AD		 1503 /*
1504 * Refresh the desc even if buffer_addrs didn't change
1505 * because each write-back erases this info.
1506 */
1507 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1508
f990b79b
AD		 1509 rx_desc++;
1510 bi++;
9a799d71 1511 i++;
f990b79b 1512 if (unlikely(!i)) {
e4f74028 1513 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1514 bi = rx_ring->rx_buffer_info;
1515 i -= rx_ring->count;
1516 }
1517
1518 /* clear the hdr_addr for the next_to_use descriptor */
1519 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1520
1521 cleaned_count--;
1522 } while (cleaned_count);
7c6e0a43 1523
f990b79b
AD		 1524 i += rx_ring->count;
1525
f56e0cb1 1526 if (rx_ring->next_to_use != i)
84ea2591 1527 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1528}
1529
1d2024f6
AD		 1530/**
1531 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1532 * @data: pointer to the start of the headers
1533 * @max_len: total length of section to find headers in
1534 *
1535 * This function is meant to determine the length of headers that will
1536 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1537 * motivation of doing this is to only perform one pull for IPv4 TCP
1538 * packets so that we can do basic things like calculating the gso_size
1539 * based on the average data per packet.
1540 **/
1541static unsigned int ixgbe_get_headlen(unsigned char *data,
1542 unsigned int max_len)
1543{
1544 union {
1545 unsigned char *network;
1546 /* l2 headers */
1547 struct ethhdr *eth;
1548 struct vlan_hdr *vlan;
1549 /* l3 headers */
1550 struct iphdr *ipv4;
a048b40e 1551 struct ipv6hdr *ipv6;
1d2024f6
AD		 1552 } hdr;
1553 __be16 protocol;
1554 u8 nexthdr = 0; /* default to not TCP */
1555 u8 hlen;
1556
1557 /* this should never happen, but better safe than sorry */
1558 if (max_len < ETH_HLEN)
1559 return max_len;
1560
1561 /* initialize network frame pointer */
1562 hdr.network = data;
1563
1564 /* set first protocol and move network header forward */
1565 protocol = hdr.eth->h_proto;
1566 hdr.network += ETH_HLEN;
1567
1568 /* handle any vlan tag if present */
a1108ffd 1569 if (protocol == htons(ETH_P_8021Q)) {
1d2024f6
AD		 1570 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1571 return max_len;
1572
1573 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1574 hdr.network += VLAN_HLEN;
1575 }
1576
1577 /* handle L3 protocols */
a1108ffd 1578 if (protocol == htons(ETH_P_IP)) {
1d2024f6
AD		 1579 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1580 return max_len;
1581
1582 /* access ihl as a u8 to avoid unaligned access on ia64 */
1583 hlen = (hdr.network[0] & 0x0F) << 2;
1584
1585 /* verify hlen meets minimum size requirements */
1586 if (hlen < sizeof(struct iphdr))
1587 return hdr.network - data;
1588
ed83da12 1589 /* record next protocol if header is present */
20967f42 1590 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1591 nexthdr = hdr.ipv4->protocol;
a1108ffd 1592 } else if (protocol == htons(ETH_P_IPV6)) {
a048b40e
AD		 1593 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1594 return max_len;
1595
1596 /* record next protocol */
1597 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1598 hlen = sizeof(struct ipv6hdr);
f800326d 1599#ifdef IXGBE_FCOE
a1108ffd 1600 } else if (protocol == htons(ETH_P_FCOE)) {
1d2024f6
AD		 1601 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1602 return max_len;
ed83da12 1603 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1604#endif
1605 } else {
1606 return hdr.network - data;
1607 }
1608
ed83da12
AD		 1609 /* relocate pointer to start of L4 header */
1610 hdr.network += hlen;
1611
a048b40e 1612 /* finally sort out TCP/UDP */
1d2024f6
AD		 1613 if (nexthdr == IPPROTO_TCP) {
1614 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1615 return max_len;
1616
1617 /* access doff as a u8 to avoid unaligned access on ia64 */
1618 hlen = (hdr.network[12] & 0xF0) >> 2;
1619
1620 /* verify hlen meets minimum size requirements */
1621 if (hlen < sizeof(struct tcphdr))
1622 return hdr.network - data;
1623
1624 hdr.network += hlen;
a048b40e
AD		 1625 } else if (nexthdr == IPPROTO_UDP) {
1626 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1627 return max_len;
1628
1629 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1630 }
1631
1632 /*
1633 * If everything has gone correctly hdr.network should be the
1634 * data section of the packet and will be the end of the header.
1635 * If not then it probably represents the end of the last recognized
1636 * header.
1637 */
1638 if ((hdr.network - data) < max_len)
1639 return hdr.network - data;
1640 else
1641 return max_len;
1642}
1643
1d2024f6
AD		 1644static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1645 struct sk_buff *skb)
1646{
f800326d 1647 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1648
1649 /* set gso_size to avoid messing up TCP MSS */
1650 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1651 IXGBE_CB(skb)->append_cnt);
96be80ab 1652 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1653}
1654
1655static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1656 struct sk_buff *skb)
1657{
1658 /* if append_cnt is 0 then frame is not RSC */
1659 if (!IXGBE_CB(skb)->append_cnt)
1660 return;
1661
1662 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1663 rx_ring->rx_stats.rsc_flush++;
1664
1665 ixgbe_set_rsc_gso_size(rx_ring, skb);
1666
1667 /* gso_size is computed using append_cnt so always clear it last */
1668 IXGBE_CB(skb)->append_cnt = 0;
1669}
1670
8a0da21b
AD		 1671/**
1672 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1673 * @rx_ring: rx descriptor ring packet is being transacted on
1674 * @rx_desc: pointer to the EOP Rx descriptor
1675 * @skb: pointer to current skb being populated
f8212f97 1676 *
8a0da21b
AD		 1677 * This function checks the ring, descriptor, and packet information in
1678 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1679 * other fields within the skb.
f8212f97 1680 **/
8a0da21b
AD		 1681static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1682 union ixgbe_adv_rx_desc *rx_desc,
1683 struct sk_buff *skb)
f8212f97 1684{
43e95f11
JF		 1685 struct net_device *dev = rx_ring->netdev;
1686
8a0da21b
AD		 1687 ixgbe_update_rsc_stats(rx_ring, skb);
1688
1689 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1690
8a0da21b
AD		 1691 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1692
eda183c2
JK		 1693 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1694 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1695
f646968f 1696 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1697 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1698 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1699 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1700 }
1701
8a0da21b 1702 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1703
43e95f11 1704 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1705}
1706
8a0da21b
AD		 1707static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1708 struct sk_buff *skb)
aa80175a 1709{
8a0da21b
AD		 1710 struct ixgbe_adapter *adapter = q_vector->adapter;
1711
b4640030 1712 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1713 netif_receive_skb(skb);
1714 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1715 napi_gro_receive(&q_vector->napi, skb);
1716 else
1717 netif_rx(skb);
aa80175a 1718}
43634e82 1719
f800326d
AD		 1720/**
1721 * ixgbe_is_non_eop - process handling of non-EOP buffers
1722 * @rx_ring: Rx ring being processed
1723 * @rx_desc: Rx descriptor for current buffer
1724 * @skb: Current socket buffer containing buffer in progress
1725 *
1726 * This function updates next to clean. If the buffer is an EOP buffer
1727 * this function exits returning false, otherwise it will place the
1728 * sk_buff in the next buffer to be chained and return true indicating
1729 * that this is in fact a non-EOP buffer.
1730 **/
1731static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1732 union ixgbe_adv_rx_desc *rx_desc,
1733 struct sk_buff *skb)
1734{
1735 u32 ntc = rx_ring->next_to_clean + 1;
1736
1737 /* fetch, update, and store next to clean */
1738 ntc = (ntc < rx_ring->count) ? ntc : 0;
1739 rx_ring->next_to_clean = ntc;
1740
1741 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1742
5a02cbd1
AD		 1743 /* update RSC append count if present */
1744 if (ring_is_rsc_enabled(rx_ring)) {
1745 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1746 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1747
1748 if (unlikely(rsc_enabled)) {
1749 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1750
1751 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1752 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1753
5a02cbd1
AD		 1754 /* update ntc based on RSC value */
1755 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1756 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1757 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1758 }
f800326d
AD		 1759 }
1760
5a02cbd1
AD		 1761 /* if we are the last buffer then there is nothing else to do */
1762 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1763 return false;
1764
f800326d
AD		 1765 /* place skb in next buffer to be received */
1766 rx_ring->rx_buffer_info[ntc].skb = skb;
1767 rx_ring->rx_stats.non_eop_descs++;
1768
1769 return true;
1770}
1771
19861ce2
AD		 1772/**
1773 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1774 * @rx_ring: rx descriptor ring packet is being transacted on
1775 * @skb: pointer to current skb being adjusted
1776 *
1777 * This function is an ixgbe specific version of __pskb_pull_tail. The
1778 * main difference between this version and the original function is that
1779 * this function can make several assumptions about the state of things
1780 * that allow for significant optimizations versus the standard function.
1781 * As a result we can do things like drop a frag and maintain an accurate
1782 * truesize for the skb.
1783 */
1784static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1785 struct sk_buff *skb)
1786{
1787 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1788 unsigned char *va;
1789 unsigned int pull_len;
1790
1791 /*
1792 * it is valid to use page_address instead of kmap since we are
1793 * working with pages allocated out of the lomem pool per
1794 * alloc_page(GFP_ATOMIC)
1795 */
1796 va = skb_frag_address(frag);
1797
1798 /*
1799 * we need the header to contain the greater of either ETH_HLEN or
1800 * 60 bytes if the skb->len is less than 60 for skb_pad.
1801 */
cf3fe7ac 1802 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1803
1804 /* align pull length to size of long to optimize memcpy performance */
1805 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1806
1807 /* update all of the pointers */
1808 skb_frag_size_sub(frag, pull_len);
1809 frag->page_offset += pull_len;
1810 skb->data_len -= pull_len;
1811 skb->tail += pull_len;
19861ce2
AD		 1812}
1813
42073d91
AD		 1814/**
1815 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1816 * @rx_ring: rx descriptor ring packet is being transacted on
1817 * @skb: pointer to current skb being updated
1818 *
1819 * This function provides a basic DMA sync up for the first fragment of an
1820 * skb. The reason for doing this is that the first fragment cannot be
1821 * unmapped until we have reached the end of packet descriptor for a buffer
1822 * chain.
1823 */
1824static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1825 struct sk_buff *skb)
1826{
1827 /* if the page was released unmap it, else just sync our portion */
1828 if (unlikely(IXGBE_CB(skb)->page_released)) {
1829 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1830 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1831 IXGBE_CB(skb)->page_released = false;
1832 } else {
1833 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1834
1835 dma_sync_single_range_for_cpu(rx_ring->dev,
1836 IXGBE_CB(skb)->dma,
1837 frag->page_offset,
1838 ixgbe_rx_bufsz(rx_ring),
1839 DMA_FROM_DEVICE);
1840 }
1841 IXGBE_CB(skb)->dma = 0;
1842}
1843
f800326d
AD		 1844/**
1845 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1846 * @rx_ring: rx descriptor ring packet is being transacted on
1847 * @rx_desc: pointer to the EOP Rx descriptor
1848 * @skb: pointer to current skb being fixed
1849 *
1850 * Check for corrupted packet headers caused by senders on the local L2
1851 * embedded NIC switch not setting up their Tx Descriptors right. These
1852 * should be very rare.
1853 *
1854 * Also address the case where we are pulling data in on pages only
1855 * and as such no data is present in the skb header.
1856 *
1857 * In addition if skb is not at least 60 bytes we need to pad it so that
1858 * it is large enough to qualify as a valid Ethernet frame.
1859 *
1860 * Returns true if an error was encountered and skb was freed.
1861 **/
1862static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1863 union ixgbe_adv_rx_desc *rx_desc,
1864 struct sk_buff *skb)
1865{
f800326d 1866 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1867
1868 /* verify that the packet does not have any known errors */
1869 if (unlikely(ixgbe_test_staterr(rx_desc,
1870 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1871 !(netdev->features & NETIF_F_RXALL))) {
1872 dev_kfree_skb_any(skb);
1873 return true;
1874 }
1875
19861ce2 1876 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1877 if (skb_is_nonlinear(skb))
1878 ixgbe_pull_tail(rx_ring, skb);
f800326d 1879
57efd44c
AD		 1880#ifdef IXGBE_FCOE
1881 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1882 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1883 return false;
1884
1885#endif
f800326d
AD		 1886 /* if skb_pad returns an error the skb was freed */
1887 if (unlikely(skb->len < 60)) {
1888 int pad_len = 60 - skb->len;
1889
1890 if (skb_pad(skb, pad_len))
1891 return true;
1892 __skb_put(skb, pad_len);
1893 }
1894
1895 return false;
1896}
1897
f800326d
AD		 1898/**
1899 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1900 * @rx_ring: rx descriptor ring to store buffers on
1901 * @old_buff: donor buffer to have page reused
1902 *
0549ae20 1903 * Synchronizes page for reuse by the adapter
f800326d
AD		 1904 **/
1905static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1906 struct ixgbe_rx_buffer *old_buff)
1907{
1908 struct ixgbe_rx_buffer *new_buff;
1909 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1910
1911 new_buff = &rx_ring->rx_buffer_info[nta];
1912
1913 /* update, and store next to alloc */
1914 nta++;
1915 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1916
1917 /* transfer page from old buffer to new buffer */
1918 new_buff->page = old_buff->page;
1919 new_buff->dma = old_buff->dma;
0549ae20 1920 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1921
1922 /* sync the buffer for use by the device */
1923 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1924 new_buff->page_offset,
1925 ixgbe_rx_bufsz(rx_ring),
f800326d 1926 DMA_FROM_DEVICE);
f800326d
AD		 1927}
1928
1929/**
1930 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1931 * @rx_ring: rx descriptor ring to transact packets on
1932 * @rx_buffer: buffer containing page to add
1933 * @rx_desc: descriptor containing length of buffer written by hardware
1934 * @skb: sk_buff to place the data into
1935 *
0549ae20
AD		 1936 * This function will add the data contained in rx_buffer->page to the skb.
1937 * This is done either through a direct copy if the data in the buffer is
1938 * less than the skb header size, otherwise it will just attach the page as
1939 * a frag to the skb.
1940 *
1941 * The function will then update the page offset if necessary and return
1942 * true if the buffer can be reused by the adapter.
f800326d 1943 **/
0549ae20 1944static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1945 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1946 union ixgbe_adv_rx_desc *rx_desc,
1947 struct sk_buff *skb)
f800326d 1948{
0549ae20
AD		 1949 struct page *page = rx_buffer->page;
1950 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1951#if (PAGE_SIZE < 8192)
0549ae20 1952 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1953#else
1954 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1955 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1956 ixgbe_rx_bufsz(rx_ring);
1957#endif
0549ae20 1958
cf3fe7ac
AD		 1959 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1960 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1961
1962 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1963
1964 /* we can reuse buffer as-is, just make sure it is local */
1965 if (likely(page_to_nid(page) == numa_node_id()))
1966 return true;
1967
1968 /* this page cannot be reused so discard it */
1969 put_page(page);
1970 return false;
1971 }
1972
0549ae20
AD		 1973 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1974 rx_buffer->page_offset, size, truesize);
1975
09816fbe
AD		 1976 /* avoid re-using remote pages */
1977 if (unlikely(page_to_nid(page) != numa_node_id()))
1978 return false;
1979
1980#if (PAGE_SIZE < 8192)
1981 /* if we are only owner of page we can reuse it */
1982 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1983 return false;
1984
1985 /* flip page offset to other buffer */
1986 rx_buffer->page_offset ^= truesize;
1987
09816fbe
AD		 1988 /*
1989 * since we are the only owner of the page and we need to
1990 * increment it, just set the value to 2 in order to avoid
1991 * an unecessary locked operation
1992 */
1993 atomic_set(&page->_count, 2);
1994#else
1995 /* move offset up to the next cache line */
1996 rx_buffer->page_offset += truesize;
1997
1998 if (rx_buffer->page_offset > last_offset)
1999 return false;
2000
0549ae20
AD		 2001 /* bump ref count on page before it is given to the stack */
2002 get_page(page);
09816fbe 2003#endif
0549ae20
AD		 2004
2005 return true;
f800326d
AD		 2006}
2007
18806c9e
AD		 2008static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
2009 union ixgbe_adv_rx_desc *rx_desc)
2010{
2011 struct ixgbe_rx_buffer *rx_buffer;
2012 struct sk_buff *skb;
2013 struct page *page;
2014
2015 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2016 page = rx_buffer->page;
2017 prefetchw(page);
2018
2019 skb = rx_buffer->skb;
2020
2021 if (likely(!skb)) {
2022 void *page_addr = page_address(page) +
2023 rx_buffer->page_offset;
2024
2025 /* prefetch first cache line of first page */
2026 prefetch(page_addr);
2027#if L1_CACHE_BYTES < 128
2028 prefetch(page_addr + L1_CACHE_BYTES);
2029#endif
2030
2031 /* allocate a skb to store the frags */
2032 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
2033 IXGBE_RX_HDR_SIZE);
2034 if (unlikely(!skb)) {
2035 rx_ring->rx_stats.alloc_rx_buff_failed++;
2036 return NULL;
2037 }
2038
2039 /*
2040 * we will be copying header into skb->data in
2041 * pskb_may_pull so it is in our interest to prefetch
2042 * it now to avoid a possible cache miss
2043 */
2044 prefetchw(skb->data);
2045
2046 /*
2047 * Delay unmapping of the first packet. It carries the
2048 * header information, HW may still access the header
2049 * after the writeback. Only unmap it when EOP is
2050 * reached
2051 */
2052 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2053 goto dma_sync;
2054
2055 IXGBE_CB(skb)->dma = rx_buffer->dma;
2056 } else {
2057 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2058 ixgbe_dma_sync_frag(rx_ring, skb);
2059
2060dma_sync:
2061 /* we are reusing so sync this buffer for CPU use */
2062 dma_sync_single_range_for_cpu(rx_ring->dev,
2063 rx_buffer->dma,
2064 rx_buffer->page_offset,
2065 ixgbe_rx_bufsz(rx_ring),
2066 DMA_FROM_DEVICE);
2067 }
2068
2069 /* pull page into skb */
2070 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2071 /* hand second half of page back to the ring */
2072 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2073 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2074 /* the page has been released from the ring */
2075 IXGBE_CB(skb)->page_released = true;
2076 } else {
2077 /* we are not reusing the buffer so unmap it */
2078 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2079 ixgbe_rx_pg_size(rx_ring),
2080 DMA_FROM_DEVICE);
2081 }
2082
2083 /* clear contents of buffer_info */
2084 rx_buffer->skb = NULL;
2085 rx_buffer->dma = 0;
2086 rx_buffer->page = NULL;
2087
2088 return skb;
f800326d
AD		 2089}
2090
2091/**
2092 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2093 * @q_vector: structure containing interrupt and ring information
2094 * @rx_ring: rx descriptor ring to transact packets on
2095 * @budget: Total limit on number of packets to process
2096 *
2097 * This function provides a "bounce buffer" approach to Rx interrupt
2098 * processing. The advantage to this is that on systems that have
2099 * expensive overhead for IOMMU access this provides a means of avoiding
2100 * it by maintaining the mapping of the page to the syste.
2101 *
5a85e737 2102 * Returns amount of work completed
f800326d 2103 **/
5a85e737 2104static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2105 struct ixgbe_ring *rx_ring,
f4de00ed 2106 const int budget)
9a799d71 2107{
d2f4fbe2 2108 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2109#ifdef IXGBE_FCOE
f800326d 2110 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2111 int ddp_bytes;
2112 unsigned int mss = 0;
3d8fd385 2113#endif /* IXGBE_FCOE */
f800326d 2114 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2115
fdabfc8a 2116 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2117 union ixgbe_adv_rx_desc *rx_desc;
2118 struct sk_buff *skb;
f800326d
AD		 2119
2120 /* return some buffers to hardware, one at a time is too slow */
2121 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2122 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2123 cleaned_count = 0;
2124 }
2125
18806c9e 2126 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2127
2128 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2129 break;
9a799d71 2130
f800326d
AD		 2131 /*
2132 * This memory barrier is needed to keep us from reading
2133 * any other fields out of the rx_desc until we know the
2134 * RXD_STAT_DD bit is set
2135 */
2136 rmb();
9a799d71 2137
18806c9e
AD		 2138 /* retrieve a buffer from the ring */
2139 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2140
18806c9e
AD		 2141 /* exit if we failed to retrieve a buffer */
2142 if (!skb)
2143 break;
9a799d71 2144
9a799d71 2145 cleaned_count++;
f8212f97 2146
f800326d
AD		 2147 /* place incomplete frames back on ring for completion */
2148 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2149 continue;
c267fc16 2150
f800326d
AD		 2151 /* verify the packet layout is correct */
2152 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2153 continue;
9a799d71 2154
d2f4fbe2
AV		 2155 /* probably a little skewed due to removing CRC */
2156 total_rx_bytes += skb->len;
d2f4fbe2 2157
8a0da21b
AD		 2158 /* populate checksum, timestamp, VLAN, and protocol */
2159 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2160
332d4a7d
YZ		 2161#ifdef IXGBE_FCOE
2162 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2163 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2164 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2165 /* include DDPed FCoE data */
2166 if (ddp_bytes > 0) {
2167 if (!mss) {
2168 mss = rx_ring->netdev->mtu -
2169 sizeof(struct fcoe_hdr) -
2170 sizeof(struct fc_frame_header) -
2171 sizeof(struct fcoe_crc_eof);
2172 if (mss > 512)
2173 mss &= ~511;
2174 }
2175 total_rx_bytes += ddp_bytes;
2176 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2177 mss);
2178 }
63d635b2
AD		 2179 if (!ddp_bytes) {
2180 dev_kfree_skb_any(skb);
f800326d 2181 continue;
63d635b2 2182 }
3d8fd385 2183 }
f800326d 2184
332d4a7d 2185#endif /* IXGBE_FCOE */
8b80cda5 2186 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2187 ixgbe_rx_skb(q_vector, skb);
9a799d71 2188
f800326d 2189 /* update budget accounting */
f4de00ed 2190 total_rx_packets++;
fdabfc8a 2191 }
9a799d71 2192
c267fc16
AD		 2193 u64_stats_update_begin(&rx_ring->syncp);
2194 rx_ring->stats.packets += total_rx_packets;
2195 rx_ring->stats.bytes += total_rx_bytes;
2196 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2197 q_vector->rx.total_packets += total_rx_packets;
2198 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2199
f800326d
AD		 2200 if (cleaned_count)
2201 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2202
5a85e737 2203 return total_rx_packets;
9a799d71
AK		 2204}
2205
e0d1095a 2206#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2207/* must be called with local_bh_disable()d */
2208static int ixgbe_low_latency_recv(struct napi_struct *napi)
2209{
2210 struct ixgbe_q_vector *q_vector =
2211 container_of(napi, struct ixgbe_q_vector, napi);
2212 struct ixgbe_adapter *adapter = q_vector->adapter;
2213 struct ixgbe_ring *ring;
2214 int found = 0;
2215
2216 if (test_bit(__IXGBE_DOWN, &adapter->state))
2217 return LL_FLUSH_FAILED;
2218
2219 if (!ixgbe_qv_lock_poll(q_vector))
2220 return LL_FLUSH_BUSY;
2221
2222 ixgbe_for_each_ring(ring, q_vector->rx) {
2223 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2224#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2225 if (found)
2226 ring->stats.cleaned += found;
2227 else
2228 ring->stats.misses++;
2229#endif
5a85e737
ET		 2230 if (found)
2231 break;
2232 }
2233
2234 ixgbe_qv_unlock_poll(q_vector);
2235
2236 return found;
2237}
e0d1095a 2238#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2239
9a799d71
AK		 2240/**
2241 * ixgbe_configure_msix - Configure MSI-X hardware
2242 * @adapter: board private structure
2243 *
2244 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2245 * interrupts.
2246 **/
2247static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2248{
021230d4 2249 struct ixgbe_q_vector *q_vector;
49c7ffbe 2250 int v_idx;
021230d4 2251 u32 mask;
9a799d71 2252
8e34d1aa
AD		 2253 /* Populate MSIX to EITR Select */
2254 if (adapter->num_vfs > 32) {
2255 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2256 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2257 }
2258
4df10466
JB		 2259 /*
2260 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2261 * corresponding register.
2262 */
49c7ffbe 2263 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2264 struct ixgbe_ring *ring;
7a921c93 2265 q_vector = adapter->q_vector[v_idx];
021230d4 2266
a557928e 2267 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2268 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2269
a557928e 2270 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2271 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2272
fe49f04a 2273 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2274 }
2275
bd508178
AD		 2276 switch (adapter->hw.mac.type) {
2277 case ixgbe_mac_82598EB:
e8e26350 2278 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2279 v_idx);
bd508178
AD		 2280 break;
2281 case ixgbe_mac_82599EB:
b93a2226 2282 case ixgbe_mac_X540:
e8e26350 2283 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2284 break;
bd508178
AD		 2285 default:
2286 break;
2287 }
021230d4
AV		 2288 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2289
41fb9248 2290 /* set up to autoclear timer, and the vectors */
021230d4 2291 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2292 mask &= ~(IXGBE_EIMS_OTHER |
2293 IXGBE_EIMS_MAILBOX |
2294 IXGBE_EIMS_LSC);
2295
021230d4 2296 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2297}
2298
f494e8fa
AV		 2299enum latency_range {
2300 lowest_latency = 0,
2301 low_latency = 1,
2302 bulk_latency = 2,
2303 latency_invalid = 255
2304};
2305
2306/**
2307 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2308 * @q_vector: structure containing interrupt and ring information
2309 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2310 *
2311 * Stores a new ITR value based on packets and byte
2312 * counts during the last interrupt. The advantage of per interrupt
2313 * computation is faster updates and more accurate ITR for the current
2314 * traffic pattern. Constants in this function were computed
2315 * based on theoretical maximum wire speed and thresholds were set based
2316 * on testing data as well as attempting to minimize response time
2317 * while increasing bulk throughput.
2318 * this functionality is controlled by the InterruptThrottleRate module
2319 * parameter (see ixgbe_param.c)
2320 **/
bd198058
AD		 2321static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2322 struct ixgbe_ring_container *ring_container)
f494e8fa 2323{
bd198058
AD		 2324 int bytes = ring_container->total_bytes;
2325 int packets = ring_container->total_packets;
2326 u32 timepassed_us;
621bd70e 2327 u64 bytes_perint;
bd198058 2328 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2329
2330 if (packets == 0)
bd198058 2331 return;
f494e8fa
AV		 2332
2333 /* simple throttlerate management
621bd70e
AD		 2334 * 0-10MB/s lowest (100000 ints/s)
2335 * 10-20MB/s low (20000 ints/s)
2336 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2337 */
2338 /* what was last interrupt timeslice? */
d5bf4f67 2339 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2340 if (timepassed_us == 0)
2341 return;
2342
f494e8fa
AV		 2343 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2344
2345 switch (itr_setting) {
2346 case lowest_latency:
621bd70e 2347 if (bytes_perint > 10)
bd198058 2348 itr_setting = low_latency;
f494e8fa
AV		 2349 break;
2350 case low_latency:
621bd70e 2351 if (bytes_perint > 20)
bd198058 2352 itr_setting = bulk_latency;
621bd70e 2353 else if (bytes_perint <= 10)
bd198058 2354 itr_setting = lowest_latency;
f494e8fa
AV		 2355 break;
2356 case bulk_latency:
621bd70e 2357 if (bytes_perint <= 20)
bd198058 2358 itr_setting = low_latency;
f494e8fa
AV		 2359 break;
2360 }
2361
bd198058
AD		 2362 /* clear work counters since we have the values we need */
2363 ring_container->total_bytes = 0;
2364 ring_container->total_packets = 0;
2365
2366 /* write updated itr to ring container */
2367 ring_container->itr = itr_setting;
f494e8fa
AV		 2368}
2369
509ee935
JB		 2370/**
2371 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2372 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2373 *
2374 * This function is made to be called by ethtool and by the driver
2375 * when it needs to update EITR registers at runtime. Hardware
2376 * specific quirks/differences are taken care of here.
2377 */
fe49f04a 2378void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2379{
fe49f04a 2380 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2381 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2382 int v_idx = q_vector->v_idx;
5d967eb7 2383 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2384
bd508178
AD		 2385 switch (adapter->hw.mac.type) {
2386 case ixgbe_mac_82598EB:
509ee935
JB		 2387 /* must write high and low 16 bits to reset counter */
2388 itr_reg |= (itr_reg << 16);
bd508178
AD		 2389 break;
2390 case ixgbe_mac_82599EB:
b93a2226 2391 case ixgbe_mac_X540:
509ee935
JB		 2392 /*
2393 * set the WDIS bit to not clear the timer bits and cause an
2394 * immediate assertion of the interrupt
2395 */
2396 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2397 break;
2398 default:
2399 break;
509ee935
JB		 2400 }
2401 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2402}
2403
bd198058 2404static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2405{
d5bf4f67 2406 u32 new_itr = q_vector->itr;
bd198058 2407 u8 current_itr;
f494e8fa 2408
bd198058
AD		 2409 ixgbe_update_itr(q_vector, &q_vector->tx);
2410 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2411
08c8833b 2412 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2413
2414 switch (current_itr) {
2415 /* counts and packets in update_itr are dependent on these numbers */
2416 case lowest_latency:
d5bf4f67 2417 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2418 break;
2419 case low_latency:
d5bf4f67 2420 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2421 break;
2422 case bulk_latency:
d5bf4f67 2423 new_itr = IXGBE_8K_ITR;
f494e8fa 2424 break;
bd198058
AD		 2425 default:
2426 break;
f494e8fa
AV		 2427 }
2428
d5bf4f67 2429 if (new_itr != q_vector->itr) {
fe49f04a 2430 /* do an exponential smoothing */
d5bf4f67
ET		 2431 new_itr = (10 * new_itr * q_vector->itr) /
2432 ((9 * new_itr) + q_vector->itr);
509ee935 2433
bd198058 2434 /* save the algorithm value here */
5d967eb7 2435 q_vector->itr = new_itr;
fe49f04a
AD		 2436
2437 ixgbe_write_eitr(q_vector);
f494e8fa 2438 }
f494e8fa
AV		 2439}
2440
119fc60a 2441/**
de88eeeb 2442 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2443 * @adapter: pointer to adapter
119fc60a 2444 **/
f0f9778d 2445static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2446{
119fc60a
MC		 2447 struct ixgbe_hw *hw = &adapter->hw;
2448 u32 eicr = adapter->interrupt_event;
2449
f0f9778d 2450 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2451 return;
2452
f0f9778d
AD		 2453 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2454 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2455 return;
2456
2457 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2458
7ca647bd 2459 switch (hw->device_id) {
f0f9778d
AD		 2460 case IXGBE_DEV_ID_82599_T3_LOM:
2461 /*
2462 * Since the warning interrupt is for both ports
2463 * we don't have to check if:
2464 * - This interrupt wasn't for our port.
2465 * - We may have missed the interrupt so always have to
2466 * check if we got a LSC
2467 */
2468 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2469 !(eicr & IXGBE_EICR_LSC))
2470 return;
2471
2472 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2473 u32 speed;
f0f9778d 2474 bool link_up = false;
7ca647bd 2475
3d292265 2476 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2477
f0f9778d
AD		 2478 if (link_up)
2479 return;
2480 }
2481
2482 /* Check if this is not due to overtemp */
2483 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2484 return;
2485
2486 break;
7ca647bd
JP		 2487 default:
2488 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2489 return;
7ca647bd 2490 break;
119fc60a 2491 }
7ca647bd
JP		 2492 e_crit(drv,
2493 "Network adapter has been stopped because it has over heated. "
2494 "Restart the computer. If the problem persists, "
2495 "power off the system and replace the adapter\n");
f0f9778d
AD		 2496
2497 adapter->interrupt_event = 0;
119fc60a
MC		 2498}
2499
0befdb3e
JB		 2500static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2501{
2502 struct ixgbe_hw *hw = &adapter->hw;
2503
2504 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2505 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2506 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2507 /* write to clear the interrupt */
2508 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2509 }
2510}
cf8280ee 2511
4f51bf70
JK		 2512static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2513{
2514 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2515 return;
2516
2517 switch (adapter->hw.mac.type) {
2518 case ixgbe_mac_82599EB:
2519 /*
2520 * Need to check link state so complete overtemp check
2521 * on service task
2522 */
2523 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2524 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2525 adapter->interrupt_event = eicr;
2526 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2527 ixgbe_service_event_schedule(adapter);
2528 return;
2529 }
2530 return;
2531 case ixgbe_mac_X540:
2532 if (!(eicr & IXGBE_EICR_TS))
2533 return;
2534 break;
2535 default:
2536 return;
2537 }
2538
2539 e_crit(drv,
2540 "Network adapter has been stopped because it has over heated. "
2541 "Restart the computer. If the problem persists, "
2542 "power off the system and replace the adapter\n");
2543}
2544
e8e26350
PW		 2545static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2546{
2547 struct ixgbe_hw *hw = &adapter->hw;
2548
73c4b7cd
AD		 2549 if (eicr & IXGBE_EICR_GPI_SDP2) {
2550 /* Clear the interrupt */
2551 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2552 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2553 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2554 ixgbe_service_event_schedule(adapter);
2555 }
73c4b7cd
AD		 2556 }
2557
e8e26350
PW		 2558 if (eicr & IXGBE_EICR_GPI_SDP1) {
2559 /* Clear the interrupt */
2560 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2561 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2562 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2563 ixgbe_service_event_schedule(adapter);
2564 }
e8e26350
PW		 2565 }
2566}
2567
cf8280ee
JB		 2568static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2569{
2570 struct ixgbe_hw *hw = &adapter->hw;
2571
2572 adapter->lsc_int++;
2573 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2574 adapter->link_check_timeout = jiffies;
2575 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2576 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2577 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2578 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2579 }
2580}
2581
fe49f04a
AD		 2582static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2583 u64 qmask)
2584{
2585 u32 mask;
bd508178 2586 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2587
bd508178
AD		 2588 switch (hw->mac.type) {
2589 case ixgbe_mac_82598EB:
fe49f04a 2590 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2591 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2592 break;
2593 case ixgbe_mac_82599EB:
b93a2226 2594 case ixgbe_mac_X540:
fe49f04a 2595 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2596 if (mask)
2597 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2598 mask = (qmask >> 32);
bd508178
AD		 2599 if (mask)
2600 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2601 break;
2602 default:
2603 break;
fe49f04a
AD		 2604 }
2605 /* skip the flush */
2606}
2607
2608static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2609 u64 qmask)
fe49f04a
AD		 2610{
2611 u32 mask;
bd508178 2612 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2613
bd508178
AD		 2614 switch (hw->mac.type) {
2615 case ixgbe_mac_82598EB:
fe49f04a 2616 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2617 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2618 break;
2619 case ixgbe_mac_82599EB:
b93a2226 2620 case ixgbe_mac_X540:
fe49f04a 2621 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2622 if (mask)
2623 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2624 mask = (qmask >> 32);
bd508178
AD		 2625 if (mask)
2626 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2627 break;
2628 default:
2629 break;
fe49f04a
AD		 2630 }
2631 /* skip the flush */
2632}
2633
021230d4 2634/**
2c4af694
AD		 2635 * ixgbe_irq_enable - Enable default interrupt generation settings
2636 * @adapter: board private structure
021230d4 2637 **/
2c4af694
AD		 2638static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2639 bool flush)
9a799d71 2640{
2c4af694 2641 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2642
2c4af694
AD		 2643 /* don't reenable LSC while waiting for link */
2644 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2645 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2646
2c4af694 2647 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2648 switch (adapter->hw.mac.type) {
2649 case ixgbe_mac_82599EB:
2650 mask |= IXGBE_EIMS_GPI_SDP0;
2651 break;
2652 case ixgbe_mac_X540:
2653 mask |= IXGBE_EIMS_TS;
2654 break;
2655 default:
2656 break;
2657 }
2c4af694
AD		 2658 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2659 mask |= IXGBE_EIMS_GPI_SDP1;
2660 switch (adapter->hw.mac.type) {
2661 case ixgbe_mac_82599EB:
2c4af694
AD		 2662 mask |= IXGBE_EIMS_GPI_SDP1;
2663 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2664 case ixgbe_mac_X540:
2665 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2666 mask |= IXGBE_EIMS_MAILBOX;
2667 break;
2668 default:
2669 break;
9a799d71 2670 }
db0677fa 2671
db0677fa
JK		 2672 if (adapter->hw.mac.type == ixgbe_mac_X540)
2673 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2674
2c4af694
AD		 2675 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2676 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2677 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2678
2c4af694
AD		 2679 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2680 if (queues)
2681 ixgbe_irq_enable_queues(adapter, ~0);
2682 if (flush)
2683 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2684}
2685
2c4af694 2686static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2687{
a65151ba 2688 struct ixgbe_adapter *adapter = data;
9a799d71 2689 struct ixgbe_hw *hw = &adapter->hw;
54037505 2690 u32 eicr;
91281fd3 2691
54037505
DS		 2692 /*
2693 * Workaround for Silicon errata. Use clear-by-write instead
2694 * of clear-by-read. Reading with EICS will return the
2695 * interrupt causes without clearing, which later be done
2696 * with the write to EICR.
2697 */
2698 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2699
2700 /* The lower 16bits of the EICR register are for the queue interrupts
2701 * which should be masked here in order to not accidently clear them if
2702 * the bits are high when ixgbe_msix_other is called. There is a race
2703 * condition otherwise which results in possible performance loss
2704 * especially if the ixgbe_msix_other interrupt is triggering
2705 * consistently (as it would when PPS is turned on for the X540 device)
2706 */
2707 eicr &= 0xFFFF0000;
2708
54037505 2709 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2710
cf8280ee
JB		 2711 if (eicr & IXGBE_EICR_LSC)
2712 ixgbe_check_lsc(adapter);
f0848276 2713
1cdd1ec8
GR		 2714 if (eicr & IXGBE_EICR_MAILBOX)
2715 ixgbe_msg_task(adapter);
efe3d3c8 2716
bd508178
AD		 2717 switch (hw->mac.type) {
2718 case ixgbe_mac_82599EB:
b93a2226 2719 case ixgbe_mac_X540:
d773ce2d
DS		 2720 if (eicr & IXGBE_EICR_ECC) {
2721 e_info(link, "Received ECC Err, initiating reset\n");
2722 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2723 ixgbe_service_event_schedule(adapter);
2724 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2725 }
c4cf55e5
PWJ		 2726 /* Handle Flow Director Full threshold interrupt */
2727 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2728 int reinit_count = 0;
c4cf55e5 2729 int i;
c4cf55e5 2730 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2731 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2732 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2733 &ring->state))
2734 reinit_count++;
2735 }
2736 if (reinit_count) {
2737 /* no more flow director interrupts until after init */
2738 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2739 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2740 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2741 }
2742 }
f0f9778d 2743 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2744 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2745 break;
2746 default:
2747 break;
c4cf55e5 2748 }
f0848276 2749
bd508178 2750 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2751
db0677fa
JK		 2752 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2753 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2754
7086400d 2755 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2756 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2757 ixgbe_irq_enable(adapter, false, false);
f0848276 2758
9a799d71 2759 return IRQ_HANDLED;
f0848276 2760}
91281fd3 2761
4ff7fb12 2762static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2763{
021230d4 2764 struct ixgbe_q_vector *q_vector = data;
91281fd3 2765
9b471446 2766 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2767
4ff7fb12
AD		 2768 if (q_vector->rx.ring || q_vector->tx.ring)
2769 napi_schedule(&q_vector->napi);
91281fd3 2770
9a799d71 2771 return IRQ_HANDLED;
91281fd3
AD		 2772}
2773
eb01b975
AD		 2774/**
2775 * ixgbe_poll - NAPI Rx polling callback
2776 * @napi: structure for representing this polling device
2777 * @budget: how many packets driver is allowed to clean
2778 *
2779 * This function is used for legacy and MSI, NAPI mode
2780 **/
8af3c33f 2781int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2782{
2783 struct ixgbe_q_vector *q_vector =
2784 container_of(napi, struct ixgbe_q_vector, napi);
2785 struct ixgbe_adapter *adapter = q_vector->adapter;
2786 struct ixgbe_ring *ring;
2787 int per_ring_budget;
2788 bool clean_complete = true;
2789
2790#ifdef CONFIG_IXGBE_DCA
2791 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2792 ixgbe_update_dca(q_vector);
2793#endif
2794
2795 ixgbe_for_each_ring(ring, q_vector->tx)
2796 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2797
5a85e737
ET		 2798 if (!ixgbe_qv_lock_napi(q_vector))
2799 return budget;
2800
eb01b975
AD		 2801 /* attempt to distribute budget to each queue fairly, but don't allow
2802 * the budget to go below 1 because we'll exit polling */
2803 if (q_vector->rx.count > 1)
2804 per_ring_budget = max(budget/q_vector->rx.count, 1);
2805 else
2806 per_ring_budget = budget;
2807
2808 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2809 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2810 per_ring_budget) < per_ring_budget);
eb01b975 2811
5a85e737 2812 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2813 /* If all work not completed, return budget and keep polling */
2814 if (!clean_complete)
2815 return budget;
2816
2817 /* all work done, exit the polling mode */
2818 napi_complete(napi);
2819 if (adapter->rx_itr_setting & 1)
2820 ixgbe_set_itr(q_vector);
2821 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2822 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2823
2824 return 0;
2825}
2826
021230d4
AV		 2827/**
2828 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2829 * @adapter: board private structure
2830 *
2831 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2832 * interrupts from the kernel.
2833 **/
2834static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2835{
2836 struct net_device *netdev = adapter->netdev;
207867f5 2837 int vector, err;
e8e9f696 2838 int ri = 0, ti = 0;
021230d4 2839
49c7ffbe 2840 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2841 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2842 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2843
4ff7fb12 2844 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2845 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2846 "%s-%s-%d", netdev->name, "TxRx", ri++);
2847 ti++;
2848 } else if (q_vector->rx.ring) {
9fe93afd 2849 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2850 "%s-%s-%d", netdev->name, "rx", ri++);
2851 } else if (q_vector->tx.ring) {
9fe93afd 2852 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2853 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2854 } else {
2855 /* skip this unused q_vector */
2856 continue;
32aa77a4 2857 }
207867f5
AD		 2858 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2859 q_vector->name, q_vector);
9a799d71 2860 if (err) {
396e799c 2861 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2862 "Error: %d\n", err);
021230d4 2863 goto free_queue_irqs;
9a799d71 2864 }
207867f5
AD		 2865 /* If Flow Director is enabled, set interrupt affinity */
2866 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2867 /* assign the mask for this irq */
2868 irq_set_affinity_hint(entry->vector,
de88eeeb 2869 &q_vector->affinity_mask);
207867f5 2870 }
9a799d71
AK		 2871 }
2872
021230d4 2873 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2874 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2875 if (err) {
de88eeeb 2876 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2877 goto free_queue_irqs;
9a799d71
AK		 2878 }
2879
9a799d71
AK		 2880 return 0;
2881
021230d4 2882free_queue_irqs:
207867f5
AD		 2883 while (vector) {
2884 vector--;
2885 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2886 NULL);
2887 free_irq(adapter->msix_entries[vector].vector,
2888 adapter->q_vector[vector]);
2889 }
021230d4
AV		 2890 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2891 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2892 kfree(adapter->msix_entries);
2893 adapter->msix_entries = NULL;
9a799d71
AK		 2894 return err;
2895}
2896
2897/**
021230d4 2898 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2899 * @irq: interrupt number
2900 * @data: pointer to a network interface device structure
9a799d71
AK		 2901 **/
2902static irqreturn_t ixgbe_intr(int irq, void *data)
2903{
a65151ba 2904 struct ixgbe_adapter *adapter = data;
9a799d71 2905 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2906 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2907 u32 eicr;
2908
54037505 2909 /*
24ddd967 2910 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2911 * before the read of EICR.
2912 */
2913 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2914
021230d4 2915 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2916 * therefore no explicit interrupt disable is necessary */
021230d4 2917 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2918 if (!eicr) {
6af3b9eb
ET		 2919 /*
2920 * shared interrupt alert!
f47cf66e 2921 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2922 * have disabled interrupts due to EIAM
2923 * finish the workaround of silicon errata on 82598. Unmask
2924 * the interrupt that we masked before the EICR read.
2925 */
2926 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2927 ixgbe_irq_enable(adapter, true, true);
9a799d71 2928 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2929 }
9a799d71 2930
cf8280ee
JB		 2931 if (eicr & IXGBE_EICR_LSC)
2932 ixgbe_check_lsc(adapter);
021230d4 2933
bd508178
AD		 2934 switch (hw->mac.type) {
2935 case ixgbe_mac_82599EB:
e8e26350 2936 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2937 /* Fall through */
2938 case ixgbe_mac_X540:
d773ce2d
DS		 2939 if (eicr & IXGBE_EICR_ECC) {
2940 e_info(link, "Received ECC Err, initiating reset\n");
2941 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2942 ixgbe_service_event_schedule(adapter);
2943 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2944 }
4f51bf70 2945 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2946 break;
2947 default:
2948 break;
2949 }
e8e26350 2950
0befdb3e 2951 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2952 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2953 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2954
b9f6ed2b
AD		 2955 /* would disable interrupts here but EIAM disabled it */
2956 napi_schedule(&q_vector->napi);
9a799d71 2957
6af3b9eb
ET		 2958 /*
2959 * re-enable link(maybe) and non-queue interrupts, no flush.
2960 * ixgbe_poll will re-enable the queue interrupts
2961 */
6af3b9eb
ET		 2962 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2963 ixgbe_irq_enable(adapter, false, false);
2964
9a799d71
AK		 2965 return IRQ_HANDLED;
2966}
2967
2968/**
2969 * ixgbe_request_irq - initialize interrupts
2970 * @adapter: board private structure
2971 *
2972 * Attempts to configure interrupts using the best available
2973 * capabilities of the hardware and kernel.
2974 **/
021230d4 2975static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2976{
2977 struct net_device *netdev = adapter->netdev;
021230d4 2978 int err;
9a799d71 2979
4cc6df29 2980 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2981 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2982 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2983 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2984 netdev->name, adapter);
4cc6df29 2985 else
a0607fd3 2986 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2987 netdev->name, adapter);
9a799d71 2988
de88eeeb 2989 if (err)
396e799c 2990 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2991
9a799d71
AK		 2992 return err;
2993}
2994
2995static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2996{
49c7ffbe 2997 int vector;
9a799d71 2998
49c7ffbe
AD		 2999 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3000 free_irq(adapter->pdev->irq, adapter);
3001 return;
3002 }
4cc6df29 3003
49c7ffbe
AD		 3004 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3005 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3006 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3007
49c7ffbe
AD		 3008 /* free only the irqs that were actually requested */
3009 if (!q_vector->rx.ring && !q_vector->tx.ring)
3010 continue;
207867f5 3011
49c7ffbe
AD		 3012 /* clear the affinity_mask in the IRQ descriptor */
3013 irq_set_affinity_hint(entry->vector, NULL);
3014
3015 free_irq(entry->vector, q_vector);
9a799d71 3016 }
49c7ffbe
AD		 3017
3018 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3019}
3020
22d5a71b
JB		 3021/**
3022 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3023 * @adapter: board private structure
3024 **/
3025static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3026{
bd508178
AD		 3027 switch (adapter->hw.mac.type) {
3028 case ixgbe_mac_82598EB:
835462fc 3029 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3030 break;
3031 case ixgbe_mac_82599EB:
b93a2226 3032 case ixgbe_mac_X540:
835462fc
NS		 3033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3036 break;
3037 default:
3038 break;
22d5a71b
JB		 3039 }
3040 IXGBE_WRITE_FLUSH(&adapter->hw);
3041 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3042 int vector;
3043
3044 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3045 synchronize_irq(adapter->msix_entries[vector].vector);
3046
3047 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3048 } else {
3049 synchronize_irq(adapter->pdev->irq);
3050 }
3051}
3052
9a799d71
AK		 3053/**
3054 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3055 *
3056 **/
3057static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3058{
d5bf4f67 3059 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3060
d5bf4f67 3061 ixgbe_write_eitr(q_vector);
9a799d71 3062
e8e26350
PW		 3063 ixgbe_set_ivar(adapter, 0, 0, 0);
3064 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3065
396e799c 3066 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3067}
3068
43e69bf0
AD		 3069/**
3070 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3071 * @adapter: board private structure
3072 * @ring: structure containing ring specific data
3073 *
3074 * Configure the Tx descriptor ring after a reset.
3075 **/
84418e3b
AD		 3076void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3077 struct ixgbe_ring *ring)
43e69bf0
AD		 3078{
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u64 tdba = ring->dma;
2f1860b8 3081 int wait_loop = 10;
b88c6de2 3082 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3083 u8 reg_idx = ring->reg_idx;
43e69bf0 3084
2f1860b8 3085 /* disable queue to avoid issues while updating state */
b88c6de2 3086 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3087 IXGBE_WRITE_FLUSH(hw);
3088
43e69bf0 3089 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3090 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3091 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3092 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3093 ring->count * sizeof(union ixgbe_adv_tx_desc));
3094 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3095 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3096 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3097
b88c6de2
AD		 3098 /*
3099 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3100 * higher than 1 when:
3101 * - ITR is 0 as it could cause false TX hangs
3102 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3103 *
3104 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3105 * to or less than the number of on chip descriptors, which is
3106 * currently 40.
3107 */
67da097e
ET		 3108#if IS_ENABLED(CONFIG_BQL)
3109 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3110#else
e954b374 3111 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 3112#endif
b88c6de2
AD		 3113 txdctl |= (1 << 16); /* WTHRESH = 1 */
3114 else
3115 txdctl |= (8 << 16); /* WTHRESH = 8 */
3116
e954b374
AD		 3117 /*
3118 * Setting PTHRESH to 32 both improves performance
3119 * and avoids a TX hang with DFP enabled
3120 */
b88c6de2
AD		 3121 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3122 32; /* PTHRESH = 32 */
2f1860b8
AD		 3123
3124 /* reinitialize flowdirector state */
39cb681b 3125 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3126 ring->atr_sample_rate = adapter->atr_sample_rate;
3127 ring->atr_count = 0;
3128 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3129 } else {
3130 ring->atr_sample_rate = 0;
3131 }
2f1860b8 3132
fd786b7b
AD		 3133 /* initialize XPS */
3134 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3135 struct ixgbe_q_vector *q_vector = ring->q_vector;
3136
3137 if (q_vector)
2a47fa45 3138 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3139 &q_vector->affinity_mask,
3140 ring->queue_index);
3141 }
3142
c84d324c
JF		 3143 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3144
2f1860b8 3145 /* enable queue */
2f1860b8
AD		 3146 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3147
3148 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3149 if (hw->mac.type == ixgbe_mac_82598EB &&
3150 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3151 return;
3152
3153 /* poll to verify queue is enabled */
3154 do {
032b4325 3155 usleep_range(1000, 2000);
2f1860b8
AD		 3156 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3157 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3158 if (!wait_loop)
3159 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3160}
3161
120ff942
AD		 3162static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3163{
3164 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3165 u32 rttdcs, mtqc;
8b1c0b24 3166 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3167
3168 if (hw->mac.type == ixgbe_mac_82598EB)
3169 return;
3170
3171 /* disable the arbiter while setting MTQC */
3172 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3173 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3174 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3175
3176 /* set transmit pool layout */
671c0adb
AD		 3177 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3178 mtqc = IXGBE_MTQC_VT_ENA;
3179 if (tcs > 4)
3180 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3181 else if (tcs > 1)
3182 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3183 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3184 mtqc |= IXGBE_MTQC_32VF;
3185 else
3186 mtqc |= IXGBE_MTQC_64VF;
3187 } else {
3188 if (tcs > 4)
3189 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3190 else if (tcs > 1)
3191 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3192 else
671c0adb
AD		 3193 mtqc = IXGBE_MTQC_64Q_1PB;
3194 }
120ff942 3195
671c0adb 3196 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3197
671c0adb
AD		 3198 /* Enable Security TX Buffer IFG for multiple pb */
3199 if (tcs) {
3200 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3201 sectx |= IXGBE_SECTX_DCB;
3202 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3203 }
3204
3205 /* re-enable the arbiter */
3206 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3207 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3208}
3209
9a799d71 3210/**
3a581073 3211 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3212 * @adapter: board private structure
3213 *
3214 * Configure the Tx unit of the MAC after a reset.
3215 **/
3216static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3217{
2f1860b8
AD		 3218 struct ixgbe_hw *hw = &adapter->hw;
3219 u32 dmatxctl;
43e69bf0 3220 u32 i;
9a799d71 3221
2f1860b8
AD		 3222 ixgbe_setup_mtqc(adapter);
3223
3224 if (hw->mac.type != ixgbe_mac_82598EB) {
3225 /* DMATXCTL.EN must be before Tx queues are enabled */
3226 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3227 dmatxctl |= IXGBE_DMATXCTL_TE;
3228 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3229 }
3230
9a799d71 3231 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3232 for (i = 0; i < adapter->num_tx_queues; i++)
3233 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3234}
3235
3ebe8fde
AD		 3236static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3237 struct ixgbe_ring *ring)
3238{
3239 struct ixgbe_hw *hw = &adapter->hw;
3240 u8 reg_idx = ring->reg_idx;
3241 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3242
3243 srrctl |= IXGBE_SRRCTL_DROP_EN;
3244
3245 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3246}
3247
3248static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3249 struct ixgbe_ring *ring)
3250{
3251 struct ixgbe_hw *hw = &adapter->hw;
3252 u8 reg_idx = ring->reg_idx;
3253 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3254
3255 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3256
3257 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3258}
3259
3260#ifdef CONFIG_IXGBE_DCB
3261void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3262#else
3263static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3264#endif
3265{
3266 int i;
3267 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3268
3269 if (adapter->ixgbe_ieee_pfc)
3270 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3271
3272 /*
3273 * We should set the drop enable bit if:
3274 * SR-IOV is enabled
3275 * or
3276 * Number of Rx queues > 1 and flow control is disabled
3277 *
3278 * This allows us to avoid head of line blocking for security
3279 * and performance reasons.
3280 */
3281 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3282 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3283 for (i = 0; i < adapter->num_rx_queues; i++)
3284 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3285 } else {
3286 for (i = 0; i < adapter->num_rx_queues; i++)
3287 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3288 }
3289}
3290
e8e26350 3291#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3292
a6616b42 3293static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3294 struct ixgbe_ring *rx_ring)
cc41ac7c 3295{
45e9baa5 3296 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3297 u32 srrctl;
bf29ee6c 3298 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3299
45e9baa5
AD		 3300 if (hw->mac.type == ixgbe_mac_82598EB) {
3301 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3302
45e9baa5
AD		 3303 /*
3304 * if VMDq is not active we must program one srrctl register
3305 * per RSS queue since we have enabled RDRXCTL.MVMEN
3306 */
3307 reg_idx &= mask;
3308 }
cc41ac7c 3309
45e9baa5
AD		 3310 /* configure header buffer length, needed for RSC */
3311 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3312
45e9baa5 3313 /* configure the packet buffer length */
f800326d 3314 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3315
3316 /* configure descriptor type */
f800326d 3317 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3318
45e9baa5 3319 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3320}
9a799d71 3321
05abb126 3322static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3323{
05abb126
AD		 3324 struct ixgbe_hw *hw = &adapter->hw;
3325 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3326 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3327 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3328 u32 mrqc = 0, reta = 0;
3329 u32 rxcsum;
3330 int i, j;
671c0adb
AD		 3331 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3332
671c0adb
AD		 3333 /*
3334 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3335 * make full use of any rings they may have. We will use the
3336 * PSRTYPE register to control how many rings we use within the PF.
3337 */
3338 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3339 rss_i = 2;
0cefafad 3340
05abb126
AD		 3341 /* Fill out hash function seeds */
3342 for (i = 0; i < 10; i++)
3343 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3344
3345 /* Fill out redirection table */
3346 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3347 if (j == rss_i)
05abb126
AD		 3348 j = 0;
3349 /* reta = 4-byte sliding window of
3350 * 0x00..(indices-1)(indices-1)00..etc. */
3351 reta = (reta << 8) | (j * 0x11);
3352 if ((i & 3) == 3)
3353 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3354 }
0cefafad 3355
05abb126
AD		 3356 /* Disable indicating checksum in descriptor, enables RSS hash */
3357 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3358 rxcsum |= IXGBE_RXCSUM_PCSD;
3359 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3360
671c0adb 3361 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3362 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3363 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3364 } else {
671c0adb
AD		 3365 u8 tcs = netdev_get_num_tc(adapter->netdev);
3366
3367 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3368 if (tcs > 4)
3369 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3370 else if (tcs > 1)
3371 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3372 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3373 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3374 else
671c0adb
AD		 3375 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3376 } else {
3377 if (tcs > 4)
8b1c0b24 3378 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3379 else if (tcs > 1)
3380 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3381 else
3382 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3383 }
0cefafad
JB		 3384 }
3385
05abb126 3386 /* Perform hash on these packet types */
671c0adb
AD		 3387 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3388 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3389 IXGBE_MRQC_RSS_FIELD_IPV6 |
3390 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3391
ef6afc0c
AD		 3392 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3393 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3394 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3395 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3396
05abb126 3397 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3398}
3399
bb5a9ad2
NS		 3400/**
3401 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3402 * @adapter: address of board private structure
3403 * @index: index of ring to set
bb5a9ad2 3404 **/
082757af 3405static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3406 struct ixgbe_ring *ring)
bb5a9ad2 3407{
bb5a9ad2 3408 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3409 u32 rscctrl;
bf29ee6c 3410 u8 reg_idx = ring->reg_idx;
7367096a 3411
7d637bcc 3412 if (!ring_is_rsc_enabled(ring))
7367096a 3413 return;
bb5a9ad2 3414
7367096a 3415 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3416 rscctrl |= IXGBE_RSCCTL_RSCEN;
3417 /*
3418 * we must limit the number of descriptors so that the
3419 * total size of max desc * buf_len is not greater
642c680e 3420 * than 65536
bb5a9ad2 3421 */
f800326d 3422 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3423 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3424}
3425
9e10e045
AD		 3426#define IXGBE_MAX_RX_DESC_POLL 10
3427static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3428 struct ixgbe_ring *ring)
3429{
3430 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3431 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3432 u32 rxdctl;
bf29ee6c 3433 u8 reg_idx = ring->reg_idx;
9e10e045 3434
b0483c8f
MR		 3435 if (ixgbe_removed(hw->hw_addr))
3436 return;
9e10e045
AD		 3437 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3438 if (hw->mac.type == ixgbe_mac_82598EB &&
3439 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3440 return;
3441
3442 do {
032b4325 3443 usleep_range(1000, 2000);
9e10e045
AD		 3444 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3445 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3446
3447 if (!wait_loop) {
3448 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3449 "the polling period\n", reg_idx);
3450 }
3451}
3452
2d39d576
YZ		 3453void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3454 struct ixgbe_ring *ring)
3455{
3456 struct ixgbe_hw *hw = &adapter->hw;
3457 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3458 u32 rxdctl;
3459 u8 reg_idx = ring->reg_idx;
3460
b0483c8f
MR		 3461 if (ixgbe_removed(hw->hw_addr))
3462 return;
2d39d576
YZ		 3463 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3464 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3465
3466 /* write value back with RXDCTL.ENABLE bit cleared */
3467 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3468
3469 if (hw->mac.type == ixgbe_mac_82598EB &&
3470 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3471 return;
3472
3473 /* the hardware may take up to 100us to really disable the rx queue */
3474 do {
3475 udelay(10);
3476 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3477 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3478
3479 if (!wait_loop) {
3480 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3481 "the polling period\n", reg_idx);
3482 }
3483}
3484
84418e3b
AD		 3485void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3486 struct ixgbe_ring *ring)
acd37177
AD		 3487{
3488 struct ixgbe_hw *hw = &adapter->hw;
3489 u64 rdba = ring->dma;
9e10e045 3490 u32 rxdctl;
bf29ee6c 3491 u8 reg_idx = ring->reg_idx;
acd37177 3492
9e10e045
AD		 3493 /* disable queue to avoid issues while updating state */
3494 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3495 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3496
acd37177
AD		 3497 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3498 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3499 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3500 ring->count * sizeof(union ixgbe_adv_rx_desc));
3501 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3502 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3503 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3504
3505 ixgbe_configure_srrctl(adapter, ring);
3506 ixgbe_configure_rscctl(adapter, ring);
3507
3508 if (hw->mac.type == ixgbe_mac_82598EB) {
3509 /*
3510 * enable cache line friendly hardware writes:
3511 * PTHRESH=32 descriptors (half the internal cache),
3512 * this also removes ugly rx_no_buffer_count increment
3513 * HTHRESH=4 descriptors (to minimize latency on fetch)
3514 * WTHRESH=8 burst writeback up to two cache lines
3515 */
3516 rxdctl &= ~0x3FFFFF;
3517 rxdctl |= 0x080420;
3518 }
3519
3520 /* enable receive descriptor ring */
3521 rxdctl |= IXGBE_RXDCTL_ENABLE;
3522 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3523
3524 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3525 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3526}
3527
48654521
AD		 3528static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3529{
3530 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3531 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3532 u16 pool;
48654521
AD		 3533
3534 /* PSRTYPE must be initialized in non 82598 adapters */
3535 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3536 IXGBE_PSRTYPE_UDPHDR |
3537 IXGBE_PSRTYPE_IPV4HDR |
48654521 3538 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3539 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3540
3541 if (hw->mac.type == ixgbe_mac_82598EB)
3542 return;
3543
fbe7ca7f
AD		 3544 if (rss_i > 3)
3545 psrtype |= 2 << 29;
3546 else if (rss_i > 1)
3547 psrtype |= 1 << 29;
48654521 3548
2a47fa45
JF		 3549 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3550 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3551}
3552
f5b4a52e
AD		 3553static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3554{
3555 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3556 u32 reg_offset, vf_shift;
435b19f6 3557 u32 gcr_ext, vmdctl;
de4c7f65 3558 int i;
f5b4a52e
AD		 3559
3560 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3561 return;
3562
3563 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3564 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3565 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3566 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3567 vmdctl |= IXGBE_VT_CTL_REPLEN;
3568 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3569
1d9c0bfd
AD		 3570 vf_shift = VMDQ_P(0) % 32;
3571 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3572
3573 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3574 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3575 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3576 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3577 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3578 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3579 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3580
3581 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3582 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3583
3584 /*
3585 * Set up VF register offsets for selected VT Mode,
3586 * i.e. 32 or 64 VFs for SR-IOV
3587 */
73079ea0
AD		 3588 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3589 case IXGBE_82599_VMDQ_8Q_MASK:
3590 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3591 break;
3592 case IXGBE_82599_VMDQ_4Q_MASK:
3593 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3594 break;
3595 default:
3596 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3597 break;
3598 }
3599
f5b4a52e
AD		 3600 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3601
435b19f6 3602
a985b6c3 3603 /* Enable MAC Anti-Spoofing */
435b19f6 3604 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3605 adapter->num_vfs);
de4c7f65
GR		 3606 /* For VFs that have spoof checking turned off */
3607 for (i = 0; i < adapter->num_vfs; i++) {
3608 if (!adapter->vfinfo[i].spoofchk_enabled)
3609 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3610 }
f5b4a52e
AD		 3611}
3612
477de6ed 3613static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3614{
9a799d71
AK		 3615 struct ixgbe_hw *hw = &adapter->hw;
3616 struct net_device *netdev = adapter->netdev;
3617 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3618 struct ixgbe_ring *rx_ring;
3619 int i;
3620 u32 mhadd, hlreg0;
48654521 3621
63f39bd1 3622#ifdef IXGBE_FCOE
477de6ed
AD		 3623 /* adjust max frame to be able to do baby jumbo for FCoE */
3624 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3625 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3626 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3627
477de6ed 3628#endif /* IXGBE_FCOE */
872844dd
AD		 3629
3630 /* adjust max frame to be at least the size of a standard frame */
3631 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3632 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3633
477de6ed
AD		 3634 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3635 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3636 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3637 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3638
3639 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3640 }
3641
3642 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3643 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3644 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3645 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3646
0cefafad
JB		 3647 /*
3648 * Setup the HW Rx Head and Tail Descriptor Pointers and
3649 * the Base and Length of the Rx Descriptor Ring
3650 */
9a799d71 3651 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3652 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3653 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3654 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3655 else
7d637bcc 3656 clear_ring_rsc_enabled(rx_ring);
477de6ed 3657 }
477de6ed
AD		 3658}
3659
7367096a
AD		 3660static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3661{
3662 struct ixgbe_hw *hw = &adapter->hw;
3663 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3664
3665 switch (hw->mac.type) {
3666 case ixgbe_mac_82598EB:
3667 /*
3668 * For VMDq support of different descriptor types or
3669 * buffer sizes through the use of multiple SRRCTL
3670 * registers, RDRXCTL.MVMEN must be set to 1
3671 *
3672 * also, the manual doesn't mention it clearly but DCA hints
3673 * will only use queue 0's tags unless this bit is set. Side
3674 * effects of setting this bit are only that SRRCTL must be
3675 * fully programmed [0..15]
3676 */
3677 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3678 break;
3679 case ixgbe_mac_82599EB:
b93a2226 3680 case ixgbe_mac_X540:
7367096a
AD		 3681 /* Disable RSC for ACK packets */
3682 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3683 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3684 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3685 /* hardware requires some bits to be set by default */
3686 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3687 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3688 break;
3689 default:
3690 /* We should do nothing since we don't know this hardware */
3691 return;
3692 }
3693
3694 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3695}
3696
477de6ed
AD		 3697/**
3698 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3699 * @adapter: board private structure
3700 *
3701 * Configure the Rx unit of the MAC after a reset.
3702 **/
3703static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3704{
3705 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3706 int i;
6dcc28b9 3707 u32 rxctrl, rfctl;
477de6ed
AD		 3708
3709 /* disable receives while setting up the descriptors */
3710 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3711 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3712
3713 ixgbe_setup_psrtype(adapter);
7367096a 3714 ixgbe_setup_rdrxctl(adapter);
477de6ed 3715
6dcc28b9
JK		 3716 /* RSC Setup */
3717 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3718 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3719 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3720 rfctl |= IXGBE_RFCTL_RSC_DIS;
3721 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3722
9e10e045 3723 /* Program registers for the distribution of queues */
f5b4a52e 3724 ixgbe_setup_mrqc(adapter);
f5b4a52e 3725
477de6ed
AD		 3726 /* set_rx_buffer_len must be called before ring initialization */
3727 ixgbe_set_rx_buffer_len(adapter);
3728
3729 /*
3730 * Setup the HW Rx Head and Tail Descriptor Pointers and
3731 * the Base and Length of the Rx Descriptor Ring
3732 */
9e10e045
AD		 3733 for (i = 0; i < adapter->num_rx_queues; i++)
3734 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3735
9e10e045
AD		 3736 /* disable drop enable for 82598 parts */
3737 if (hw->mac.type == ixgbe_mac_82598EB)
3738 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3739
3740 /* enable all receives */
3741 rxctrl |= IXGBE_RXCTRL_RXEN;
3742 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3743}
3744
80d5c368
PM		 3745static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3746 __be16 proto, u16 vid)
068c89b0
DS		 3747{
3748 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3749 struct ixgbe_hw *hw = &adapter->hw;
3750
3751 /* add VID to filter table */
1d9c0bfd 3752 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3753 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3754
3755 return 0;
068c89b0
DS		 3756}
3757
80d5c368
PM		 3758static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3759 __be16 proto, u16 vid)
068c89b0
DS		 3760{
3761 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3762 struct ixgbe_hw *hw = &adapter->hw;
3763
068c89b0 3764 /* remove VID from filter table */
1d9c0bfd 3765 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3766 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3767
3768 return 0;
068c89b0
DS		 3769}
3770
f62bbb5e
JG		 3771/**
3772 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3773 * @adapter: driver data
3774 */
3775static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3776{
3777 struct ixgbe_hw *hw = &adapter->hw;
3778 u32 vlnctrl;
5f6c0181
JB		 3779 int i, j;
3780
3781 switch (hw->mac.type) {
3782 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3783 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3784 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3785 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3786 break;
3787 case ixgbe_mac_82599EB:
b93a2226 3788 case ixgbe_mac_X540:
5f6c0181 3789 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3790 struct ixgbe_ring *ring = adapter->rx_ring[i];
3791
3792 if (ring->l2_accel_priv)
3793 continue;
3794 j = ring->reg_idx;
5f6c0181
JB		 3795 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3796 vlnctrl &= ~IXGBE_RXDCTL_VME;
3797 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3798 }
3799 break;
3800 default:
3801 break;
3802 }
3803}
3804
3805/**
f62bbb5e 3806 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3807 * @adapter: driver data
3808 */
f62bbb5e 3809static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3810{
3811 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3812 u32 vlnctrl;
5f6c0181
JB		 3813 int i, j;
3814
3815 switch (hw->mac.type) {
3816 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3817 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3818 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3819 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3820 break;
3821 case ixgbe_mac_82599EB:
b93a2226 3822 case ixgbe_mac_X540:
5f6c0181 3823 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3824 struct ixgbe_ring *ring = adapter->rx_ring[i];
3825
3826 if (ring->l2_accel_priv)
3827 continue;
3828 j = ring->reg_idx;
5f6c0181
JB		 3829 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3830 vlnctrl |= IXGBE_RXDCTL_VME;
3831 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3832 }
3833 break;
3834 default:
3835 break;
3836 }
3837}
3838
9a799d71
AK		 3839static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3840{
f62bbb5e 3841 u16 vid;
9a799d71 3842
80d5c368 3843 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3844
3845 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3846 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3847}
3848
b335e75b
JK		 3849/**
3850 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3851 * @netdev: network interface device structure
3852 *
3853 * Writes multicast address list to the MTA hash table.
3854 * Returns: -ENOMEM on failure
3855 * 0 on no addresses written
3856 * X on writing X addresses to MTA
3857 **/
3858static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3859{
3860 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3861 struct ixgbe_hw *hw = &adapter->hw;
3862
3863 if (!netif_running(netdev))
3864 return 0;
3865
3866 if (hw->mac.ops.update_mc_addr_list)
3867 hw->mac.ops.update_mc_addr_list(hw, netdev);
3868 else
3869 return -ENOMEM;
3870
3871#ifdef CONFIG_PCI_IOV
5d7daa35 3872 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 3873#endif
3874
3875 return netdev_mc_count(netdev);
3876}
3877
5d7daa35
JK		 3878#ifdef CONFIG_PCI_IOV
3879void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
3880{
3881 struct ixgbe_hw *hw = &adapter->hw;
3882 int i;
3883 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3884 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3885 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
3886 adapter->mac_table[i].queue,
3887 IXGBE_RAH_AV);
3888 else
3889 hw->mac.ops.clear_rar(hw, i);
3890
3891 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
3892 }
3893}
3894#endif
3895
3896static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
3897{
3898 struct ixgbe_hw *hw = &adapter->hw;
3899 int i;
3900 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3901 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
3902 if (adapter->mac_table[i].state &
3903 IXGBE_MAC_STATE_IN_USE)
3904 hw->mac.ops.set_rar(hw, i,
3905 adapter->mac_table[i].addr,
3906 adapter->mac_table[i].queue,
3907 IXGBE_RAH_AV);
3908 else
3909 hw->mac.ops.clear_rar(hw, i);
3910
3911 adapter->mac_table[i].state &=
3912 ~(IXGBE_MAC_STATE_MODIFIED);
3913 }
3914 }
3915}
3916
3917static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
3918{
3919 int i;
3920 struct ixgbe_hw *hw = &adapter->hw;
3921
3922 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3923 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3924 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3925 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3926 adapter->mac_table[i].queue = 0;
3927 }
3928 ixgbe_sync_mac_table(adapter);
3929}
3930
3931static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
3932{
3933 struct ixgbe_hw *hw = &adapter->hw;
3934 int i, count = 0;
3935
3936 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3937 if (adapter->mac_table[i].state == 0)
3938 count++;
3939 }
3940 return count;
3941}
3942
3943/* this function destroys the first RAR entry */
3944static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
3945 u8 *addr)
3946{
3947 struct ixgbe_hw *hw = &adapter->hw;
3948
3949 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
3950 adapter->mac_table[0].queue = VMDQ_P(0);
3951 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
3952 IXGBE_MAC_STATE_IN_USE);
3953 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
3954 adapter->mac_table[0].queue,
3955 IXGBE_RAH_AV);
3956}
3957
3958int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3959{
3960 struct ixgbe_hw *hw = &adapter->hw;
3961 int i;
3962
3963 if (is_zero_ether_addr(addr))
3964 return -EINVAL;
3965
3966 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3967 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
3968 continue;
3969 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
3970 IXGBE_MAC_STATE_IN_USE);
3971 ether_addr_copy(adapter->mac_table[i].addr, addr);
3972 adapter->mac_table[i].queue = queue;
3973 ixgbe_sync_mac_table(adapter);
3974 return i;
3975 }
3976 return -ENOMEM;
3977}
3978
3979int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
3980{
3981 /* search table for addr, if found, set to 0 and sync */
3982 int i;
3983 struct ixgbe_hw *hw = &adapter->hw;
3984
3985 if (is_zero_ether_addr(addr))
3986 return -EINVAL;
3987
3988 for (i = 0; i < hw->mac.num_rar_entries; i++) {
3989 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
3990 adapter->mac_table[i].queue == queue) {
3991 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
3992 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
3993 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
3994 adapter->mac_table[i].queue = 0;
3995 ixgbe_sync_mac_table(adapter);
3996 return 0;
3997 }
3998 }
3999 return -ENOMEM;
4000}
2850062a
AD		 4001/**
4002 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4003 * @netdev: network interface device structure
4004 *
4005 * Writes unicast address list to the RAR table.
4006 * Returns: -ENOMEM on failure/insufficient address space
4007 * 0 on no addresses written
4008 * X on writing X addresses to the RAR table
4009 **/
5d7daa35 4010static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4011{
4012 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4013 int count = 0;
4014
4015 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4016 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4017 return -ENOMEM;
4018
95447461 4019 if (!netdev_uc_empty(netdev)) {
2850062a 4020 struct netdev_hw_addr *ha;
2850062a 4021 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4022 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4023 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4024 count++;
4025 }
4026 }
2850062a
AD		 4027 return count;
4028}
4029
9a799d71 4030/**
2c5645cf 4031 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4032 * @netdev: network interface device structure
4033 *
2c5645cf
CL		 4034 * The set_rx_method entry point is called whenever the unicast/multicast
4035 * address list or the network interface flags are updated. This routine is
4036 * responsible for configuring the hardware for proper unicast, multicast and
4037 * promiscuous mode.
9a799d71 4038 **/
7f870475 4039void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4040{
4041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4042 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4043 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4044 u32 vlnctrl;
2850062a 4045 int count;
9a799d71
AK		 4046
4047 /* Check for Promiscuous and All Multicast modes */
9a799d71 4048 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4049 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4050
f5dc442b 4051 /* set all bits that we expect to always be set */
3f2d1c0f 4052 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4053 fctrl |= IXGBE_FCTRL_BAM;
4054 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4055 fctrl |= IXGBE_FCTRL_PMCF;
4056
2850062a
AD		 4057 /* clear the bits we are changing the status of */
4058 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4059 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4060 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4061 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4062 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4063 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4064 /* Only disable hardware filter vlans in promiscuous mode
4065 * if SR-IOV and VMDQ are disabled - otherwise ensure
4066 * that hardware VLAN filters remain enabled.
4067 */
4068 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4069 IXGBE_FLAG_SRIOV_ENABLED)))
a9b8943e 4070 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4071 } else {
746b9f02
PM		 4072 if (netdev->flags & IFF_ALLMULTI) {
4073 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4074 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4075 }
a9b8943e 4076 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4077 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4078 }
4079
4080 /*
4081 * Write addresses to available RAR registers, if there is not
4082 * sufficient space to store all the addresses then enable
4083 * unicast promiscuous mode
4084 */
5d7daa35 4085 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4086 if (count < 0) {
4087 fctrl |= IXGBE_FCTRL_UPE;
4088 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4089 }
4090
cf78959c
ET		 4091 /* Write addresses to the MTA, if the attempt fails
4092 * then we should just turn on promiscuous mode so
4093 * that we can at least receive multicast traffic
4094 */
b335e75b
JK		 4095 count = ixgbe_write_mc_addr_list(netdev);
4096 if (count < 0) {
4097 fctrl |= IXGBE_FCTRL_MPE;
4098 vmolr |= IXGBE_VMOLR_MPE;
4099 } else if (count) {
4100 vmolr |= IXGBE_VMOLR_ROMPE;
4101 }
1d9c0bfd
AD		 4102
4103 if (hw->mac.type != ixgbe_mac_82598EB) {
4104 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4105 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4106 IXGBE_VMOLR_ROPE);
1d9c0bfd 4107 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4108 }
4109
3f2d1c0f
BG		 4110 /* This is useful for sniffing bad packets. */
4111 if (adapter->netdev->features & NETIF_F_RXALL) {
4112 /* UPE and MPE will be handled by normal PROMISC logic
4113 * in e1000e_set_rx_mode */
4114 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4115 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4116 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4117
4118 fctrl &= ~(IXGBE_FCTRL_DPF);
4119 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4120 }
4121
a9b8943e 4122 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4123 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4124
f646968f 4125 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4126 ixgbe_vlan_strip_enable(adapter);
4127 else
4128 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4129}
4130
021230d4
AV		 4131static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4132{
4133 int q_idx;
021230d4 4134
5a85e737
ET		 4135 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4136 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4137 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4138 }
021230d4
AV		 4139}
4140
4141static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4142{
4143 int q_idx;
021230d4 4144
5a85e737 4145 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4146 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4147 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4148 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4149 usleep_range(1000, 20000);
5a85e737
ET		 4150 }
4151 }
021230d4
AV		 4152}
4153
7a6b6f51 4154#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4155/**
2f90b865
AD		 4156 * ixgbe_configure_dcb - Configure DCB hardware
4157 * @adapter: ixgbe adapter struct
4158 *
4159 * This is called by the driver on open to configure the DCB hardware.
4160 * This is also called by the gennetlink interface when reconfiguring
4161 * the DCB state.
4162 */
4163static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4164{
4165 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4166 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4167
67ebd791
AD		 4168 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4169 if (hw->mac.type == ixgbe_mac_82598EB)
4170 netif_set_gso_max_size(adapter->netdev, 65536);
4171 return;
4172 }
4173
4174 if (hw->mac.type == ixgbe_mac_82598EB)
4175 netif_set_gso_max_size(adapter->netdev, 32768);
4176
971060b1 4177#ifdef IXGBE_FCOE
b120818e
JF		 4178 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4179 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4180#endif
b120818e
JF		 4181
4182 /* reconfigure the hardware */
4183 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4184 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4185 DCB_TX_CONFIG);
4186 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4187 DCB_RX_CONFIG);
4188 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4189 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4190 ixgbe_dcb_hw_ets(&adapter->hw,
4191 adapter->ixgbe_ieee_ets,
4192 max_frame);
4193 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4194 adapter->ixgbe_ieee_pfc->pfc_en,
4195 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4196 }
8187cd48
JF		 4197
4198 /* Enable RSS Hash per TC */
4199 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4200 u32 msb = 0;
4201 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4202
d411a936
AD		 4203 while (rss_i) {
4204 msb++;
4205 rss_i >>= 1;
4206 }
8187cd48 4207
4ae63730
AD		 4208 /* write msb to all 8 TCs in one write */
4209 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4210 }
2f90b865 4211}
9da712d2
JF		 4212#endif
4213
4214/* Additional bittime to account for IXGBE framing */
4215#define IXGBE_ETH_FRAMING 20
4216
49ce9c2c 4217/**
9da712d2
JF		 4218 * ixgbe_hpbthresh - calculate high water mark for flow control
4219 *
4220 * @adapter: board private structure to calculate for
49ce9c2c 4221 * @pb: packet buffer to calculate
9da712d2
JF		 4222 */
4223static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4224{
4225 struct ixgbe_hw *hw = &adapter->hw;
4226 struct net_device *dev = adapter->netdev;
4227 int link, tc, kb, marker;
4228 u32 dv_id, rx_pba;
4229
4230 /* Calculate max LAN frame size */
4231 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4232
4233#ifdef IXGBE_FCOE
4234 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4235 if ((dev->features & NETIF_F_FCOE_MTU) &&
4236 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4237 (pb == ixgbe_fcoe_get_tc(adapter)))
4238 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4239#endif
e5776620 4240
9da712d2
JF		 4241 /* Calculate delay value for device */
4242 switch (hw->mac.type) {
4243 case ixgbe_mac_X540:
4244 dv_id = IXGBE_DV_X540(link, tc);
4245 break;
4246 default:
4247 dv_id = IXGBE_DV(link, tc);
4248 break;
4249 }
4250
4251 /* Loopback switch introduces additional latency */
4252 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4253 dv_id += IXGBE_B2BT(tc);
4254
4255 /* Delay value is calculated in bit times convert to KB */
4256 kb = IXGBE_BT2KB(dv_id);
4257 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4258
4259 marker = rx_pba - kb;
4260
4261 /* It is possible that the packet buffer is not large enough
4262 * to provide required headroom. In this case throw an error
4263 * to user and a do the best we can.
4264 */
4265 if (marker < 0) {
4266 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4267 "headroom to support flow control."
4268 "Decrease MTU or number of traffic classes\n", pb);
4269 marker = tc + 1;
4270 }
4271
4272 return marker;
4273}
4274
49ce9c2c 4275/**
9da712d2
JF		 4276 * ixgbe_lpbthresh - calculate low water mark for for flow control
4277 *
4278 * @adapter: board private structure to calculate for
49ce9c2c 4279 * @pb: packet buffer to calculate
9da712d2 4280 */
e5776620 4281static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4282{
4283 struct ixgbe_hw *hw = &adapter->hw;
4284 struct net_device *dev = adapter->netdev;
4285 int tc;
4286 u32 dv_id;
4287
4288 /* Calculate max LAN frame size */
4289 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4290
e5776620
JK		 4291#ifdef IXGBE_FCOE
4292 /* FCoE traffic class uses FCOE jumbo frames */
4293 if ((dev->features & NETIF_F_FCOE_MTU) &&
4294 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4295 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4296 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4297#endif
4298
9da712d2
JF		 4299 /* Calculate delay value for device */
4300 switch (hw->mac.type) {
4301 case ixgbe_mac_X540:
4302 dv_id = IXGBE_LOW_DV_X540(tc);
4303 break;
4304 default:
4305 dv_id = IXGBE_LOW_DV(tc);
4306 break;
4307 }
4308
4309 /* Delay value is calculated in bit times convert to KB */
4310 return IXGBE_BT2KB(dv_id);
4311}
4312
4313/*
4314 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4315 */
4316static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4317{
4318 struct ixgbe_hw *hw = &adapter->hw;
4319 int num_tc = netdev_get_num_tc(adapter->netdev);
4320 int i;
4321
4322 if (!num_tc)
4323 num_tc = 1;
4324
9da712d2
JF		 4325 for (i = 0; i < num_tc; i++) {
4326 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4327 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4328
4329 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4330 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4331 hw->fc.low_water[i] = 0;
9da712d2 4332 }
e5776620
JK		 4333
4334 for (; i < MAX_TRAFFIC_CLASS; i++)
4335 hw->fc.high_water[i] = 0;
9da712d2
JF		 4336}
4337
80605c65
JF		 4338static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4339{
80605c65 4340 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4341 int hdrm;
4342 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4343
4344 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4345 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4346 hdrm = 32 << adapter->fdir_pballoc;
4347 else
4348 hdrm = 0;
80605c65 4349
f7e1027f 4350 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4351 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4352}
4353
e4911d57
AD		 4354static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4355{
4356 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4357 struct hlist_node *node2;
e4911d57
AD		 4358 struct ixgbe_fdir_filter *filter;
4359
4360 spin_lock(&adapter->fdir_perfect_lock);
4361
4362 if (!hlist_empty(&adapter->fdir_filter_list))
4363 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4364
b67bfe0d 4365 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4366 &adapter->fdir_filter_list, fdir_node) {
4367 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4368 &filter->filter,
4369 filter->sw_idx,
4370 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4371 IXGBE_FDIR_DROP_QUEUE :
4372 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4373 }
4374
4375 spin_unlock(&adapter->fdir_perfect_lock);
4376}
4377
2a47fa45
JF		 4378static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4379 struct ixgbe_adapter *adapter)
4380{
4381 struct ixgbe_hw *hw = &adapter->hw;
4382 u32 vmolr;
4383
4384 /* No unicast promiscuous support for VMDQ devices. */
4385 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4386 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4387
4388 /* clear the affected bit */
4389 vmolr &= ~IXGBE_VMOLR_MPE;
4390
4391 if (dev->flags & IFF_ALLMULTI) {
4392 vmolr |= IXGBE_VMOLR_MPE;
4393 } else {
4394 vmolr |= IXGBE_VMOLR_ROMPE;
4395 hw->mac.ops.update_mc_addr_list(hw, dev);
4396 }
5d7daa35 4397 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4398 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4399}
4400
2a47fa45
JF		 4401static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4402{
4403 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4404 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4405 struct ixgbe_hw *hw = &adapter->hw;
4406 u16 pool = vadapter->pool;
4407 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4408 IXGBE_PSRTYPE_UDPHDR |
4409 IXGBE_PSRTYPE_IPV4HDR |
4410 IXGBE_PSRTYPE_L2HDR |
4411 IXGBE_PSRTYPE_IPV6HDR;
4412
4413 if (hw->mac.type == ixgbe_mac_82598EB)
4414 return;
4415
4416 if (rss_i > 3)
4417 psrtype |= 2 << 29;
4418 else if (rss_i > 1)
4419 psrtype |= 1 << 29;
4420
4421 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4422}
4423
4424/**
4425 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4426 * @rx_ring: ring to free buffers from
4427 **/
4428static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4429{
4430 struct device *dev = rx_ring->dev;
4431 unsigned long size;
4432 u16 i;
4433
4434 /* ring already cleared, nothing to do */
4435 if (!rx_ring->rx_buffer_info)
4436 return;
4437
4438 /* Free all the Rx ring sk_buffs */
4439 for (i = 0; i < rx_ring->count; i++) {
4440 struct ixgbe_rx_buffer *rx_buffer;
4441
4442 rx_buffer = &rx_ring->rx_buffer_info[i];
4443 if (rx_buffer->skb) {
4444 struct sk_buff *skb = rx_buffer->skb;
4445 if (IXGBE_CB(skb)->page_released) {
4446 dma_unmap_page(dev,
4447 IXGBE_CB(skb)->dma,
4448 ixgbe_rx_bufsz(rx_ring),
4449 DMA_FROM_DEVICE);
4450 IXGBE_CB(skb)->page_released = false;
4451 }
4452 dev_kfree_skb(skb);
4453 }
4454 rx_buffer->skb = NULL;
4455 if (rx_buffer->dma)
4456 dma_unmap_page(dev, rx_buffer->dma,
4457 ixgbe_rx_pg_size(rx_ring),
4458 DMA_FROM_DEVICE);
4459 rx_buffer->dma = 0;
4460 if (rx_buffer->page)
4461 __free_pages(rx_buffer->page,
4462 ixgbe_rx_pg_order(rx_ring));
4463 rx_buffer->page = NULL;
4464 }
4465
4466 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4467 memset(rx_ring->rx_buffer_info, 0, size);
4468
4469 /* Zero out the descriptor ring */
4470 memset(rx_ring->desc, 0, rx_ring->size);
4471
4472 rx_ring->next_to_alloc = 0;
4473 rx_ring->next_to_clean = 0;
4474 rx_ring->next_to_use = 0;
4475}
4476
4477static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4478 struct ixgbe_ring *rx_ring)
4479{
4480 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4481 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4482
4483 /* shutdown specific queue receive and wait for dma to settle */
4484 ixgbe_disable_rx_queue(adapter, rx_ring);
4485 usleep_range(10000, 20000);
4486 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4487 ixgbe_clean_rx_ring(rx_ring);
4488 rx_ring->l2_accel_priv = NULL;
4489}
4490
ae72c8d0
JF		 4491static int ixgbe_fwd_ring_down(struct net_device *vdev,
4492 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4493{
4494 struct ixgbe_adapter *adapter = accel->real_adapter;
4495 unsigned int rxbase = accel->rx_base_queue;
4496 unsigned int txbase = accel->tx_base_queue;
4497 int i;
4498
4499 netif_tx_stop_all_queues(vdev);
4500
4501 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4502 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4503 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4504 }
4505
4506 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4507 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4508 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4509 }
4510
4511
4512 return 0;
4513}
4514
4515static int ixgbe_fwd_ring_up(struct net_device *vdev,
4516 struct ixgbe_fwd_adapter *accel)
4517{
4518 struct ixgbe_adapter *adapter = accel->real_adapter;
4519 unsigned int rxbase, txbase, queues;
4520 int i, baseq, err = 0;
4521
4522 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4523 return 0;
4524
4525 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4526 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4527 accel->pool, adapter->num_rx_pools,
4528 baseq, baseq + adapter->num_rx_queues_per_pool,
4529 adapter->fwd_bitmask);
4530
4531 accel->netdev = vdev;
4532 accel->rx_base_queue = rxbase = baseq;
4533 accel->tx_base_queue = txbase = baseq;
4534
4535 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4536 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4537
4538 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4539 adapter->rx_ring[rxbase + i]->netdev = vdev;
4540 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4541 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4542 }
4543
4544 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4545 adapter->tx_ring[txbase + i]->netdev = vdev;
4546 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4547 }
4548
4549 queues = min_t(unsigned int,
4550 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4551 err = netif_set_real_num_tx_queues(vdev, queues);
4552 if (err)
4553 goto fwd_queue_err;
4554
2a47fa45
JF		 4555 err = netif_set_real_num_rx_queues(vdev, queues);
4556 if (err)
4557 goto fwd_queue_err;
4558
4559 if (is_valid_ether_addr(vdev->dev_addr))
4560 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4561
4562 ixgbe_fwd_psrtype(accel);
4563 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4564 return err;
4565fwd_queue_err:
4566 ixgbe_fwd_ring_down(vdev, accel);
4567 return err;
4568}
4569
4570static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4571{
4572 struct net_device *upper;
4573 struct list_head *iter;
4574 int err;
4575
4576 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4577 if (netif_is_macvlan(upper)) {
4578 struct macvlan_dev *dfwd = netdev_priv(upper);
4579 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4580
4581 if (dfwd->fwd_priv) {
4582 err = ixgbe_fwd_ring_up(upper, vadapter);
4583 if (err)
4584 continue;
4585 }
4586 }
4587 }
4588}
4589
9a799d71
AK		 4590static void ixgbe_configure(struct ixgbe_adapter *adapter)
4591{
d2f5e7f3
AS		 4592 struct ixgbe_hw *hw = &adapter->hw;
4593
80605c65 4594 ixgbe_configure_pb(adapter);
7a6b6f51 4595#ifdef CONFIG_IXGBE_DCB
67ebd791 4596 ixgbe_configure_dcb(adapter);
2f90b865 4597#endif
b35d4d42
AD		 4598 /*
4599 * We must restore virtualization before VLANs or else
4600 * the VLVF registers will not be populated
4601 */
4602 ixgbe_configure_virtualization(adapter);
9a799d71 4603
4c1d7b4b 4604 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4605 ixgbe_restore_vlan(adapter);
4606
d2f5e7f3
AS		 4607 switch (hw->mac.type) {
4608 case ixgbe_mac_82599EB:
4609 case ixgbe_mac_X540:
4610 hw->mac.ops.disable_rx_buff(hw);
4611 break;
4612 default:
4613 break;
4614 }
4615
c4cf55e5 4616 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4617 ixgbe_init_fdir_signature_82599(&adapter->hw,
4618 adapter->fdir_pballoc);
e4911d57
AD		 4619 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4620 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4621 adapter->fdir_pballoc);
4622 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4623 }
4c1d7b4b 4624
d2f5e7f3
AS		 4625 switch (hw->mac.type) {
4626 case ixgbe_mac_82599EB:
4627 case ixgbe_mac_X540:
4628 hw->mac.ops.enable_rx_buff(hw);
4629 break;
4630 default:
4631 break;
4632 }
4633
7c8ae65a
AD		 4634#ifdef IXGBE_FCOE
4635 /* configure FCoE L2 filters, redirection table, and Rx control */
4636 ixgbe_configure_fcoe(adapter);
4637
4638#endif /* IXGBE_FCOE */
9a799d71
AK		 4639 ixgbe_configure_tx(adapter);
4640 ixgbe_configure_rx(adapter);
2a47fa45 4641 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4642}
4643
e8e26350
PW		 4644static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4645{
4646 switch (hw->phy.type) {
4647 case ixgbe_phy_sfp_avago:
4648 case ixgbe_phy_sfp_ftl:
4649 case ixgbe_phy_sfp_intel:
4650 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4651 case ixgbe_phy_sfp_passive_tyco:
4652 case ixgbe_phy_sfp_passive_unknown:
4653 case ixgbe_phy_sfp_active_unknown:
4654 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4655 case ixgbe_phy_qsfp_passive_unknown:
4656 case ixgbe_phy_qsfp_active_unknown:
4657 case ixgbe_phy_qsfp_intel:
4658 case ixgbe_phy_qsfp_unknown:
e8e26350 4659 return true;
8917b447
AD		 4660 case ixgbe_phy_nl:
4661 if (hw->mac.type == ixgbe_mac_82598EB)
4662 return true;
e8e26350
PW		 4663 default:
4664 return false;
4665 }
4666}
4667
0ecc061d 4668/**
e8e26350
PW		 4669 * ixgbe_sfp_link_config - set up SFP+ link
4670 * @adapter: pointer to private adapter struct
4671 **/
4672static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4673{
7086400d 4674 /*
52f33af8 4675 * We are assuming the worst case scenario here, and that
7086400d
AD		 4676 * is that an SFP was inserted/removed after the reset
4677 * but before SFP detection was enabled. As such the best
4678 * solution is to just start searching as soon as we start
4679 */
4680 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4681 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4682
7086400d 4683 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4684}
4685
4686/**
4687 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4688 * @hw: pointer to private hardware struct
4689 *
4690 * Returns 0 on success, negative on failure
4691 **/
e8e26350 4692static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4693{
3d292265
JH		 4694 u32 speed;
4695 bool autoneg, link_up = false;
0ecc061d
PWJ		 4696 u32 ret = IXGBE_ERR_LINK_SETUP;
4697
4698 if (hw->mac.ops.check_link)
3d292265 4699 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4700
4701 if (ret)
4702 goto link_cfg_out;
4703
3d292265
JH		 4704 speed = hw->phy.autoneg_advertised;
4705 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4706 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4707 &autoneg);
0ecc061d
PWJ		 4708 if (ret)
4709 goto link_cfg_out;
4710
8620a103 4711 if (hw->mac.ops.setup_link)
fd0326f2 4712 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4713link_cfg_out:
4714 return ret;
4715}
4716
a34bcfff 4717static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4718{
9a799d71 4719 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4720 u32 gpie = 0;
9a799d71 4721
9b471446 4722 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4723 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4724 IXGBE_GPIE_OCD;
4725 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4726 /*
4727 * use EIAM to auto-mask when MSI-X interrupt is asserted
4728 * this saves a register write for every interrupt
4729 */
4730 switch (hw->mac.type) {
4731 case ixgbe_mac_82598EB:
4732 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4733 break;
9b471446 4734 case ixgbe_mac_82599EB:
b93a2226
DS		 4735 case ixgbe_mac_X540:
4736 default:
9b471446
JB		 4737 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4738 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4739 break;
4740 }
4741 } else {
021230d4
AV		 4742 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4743 * specifically only auto mask tx and rx interrupts */
4744 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4745 }
9a799d71 4746
a34bcfff
AD		 4747 /* XXX: to interrupt immediately for EICS writes, enable this */
4748 /* gpie |= IXGBE_GPIE_EIMEN; */
4749
4750 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4751 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4752
4753 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4754 case IXGBE_82599_VMDQ_8Q_MASK:
4755 gpie |= IXGBE_GPIE_VTMODE_16;
4756 break;
4757 case IXGBE_82599_VMDQ_4Q_MASK:
4758 gpie |= IXGBE_GPIE_VTMODE_32;
4759 break;
4760 default:
4761 gpie |= IXGBE_GPIE_VTMODE_64;
4762 break;
4763 }
119fc60a
MC		 4764 }
4765
5fdd31f9 4766 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4767 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4768 switch (adapter->hw.mac.type) {
4769 case ixgbe_mac_82599EB:
4770 gpie |= IXGBE_SDP0_GPIEN;
4771 break;
4772 case ixgbe_mac_X540:
4773 gpie |= IXGBE_EIMS_TS;
4774 break;
4775 default:
4776 break;
4777 }
4778 }
5fdd31f9 4779
a34bcfff
AD		 4780 /* Enable fan failure interrupt */
4781 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4782 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4783
2698b208 4784 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4785 gpie |= IXGBE_SDP1_GPIEN;
4786 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4787 }
a34bcfff
AD		 4788
4789 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4790}
4791
c7ccde0f 4792static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4793{
4794 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4795 int err;
a34bcfff
AD		 4796 u32 ctrl_ext;
4797
4798 ixgbe_get_hw_control(adapter);
4799 ixgbe_setup_gpie(adapter);
e8e26350 4800
9a799d71
AK		 4801 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4802 ixgbe_configure_msix(adapter);
4803 else
4804 ixgbe_configure_msi_and_legacy(adapter);
4805
ec74a471
ET		 4806 /* enable the optics for 82599 SFP+ fiber */
4807 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4808 hw->mac.ops.enable_tx_laser(hw);
4809
c3049c8f 4810 smp_mb__before_clear_bit();
9a799d71 4811 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4812 ixgbe_napi_enable_all(adapter);
4813
73c4b7cd
AD		 4814 if (ixgbe_is_sfp(hw)) {
4815 ixgbe_sfp_link_config(adapter);
4816 } else {
4817 err = ixgbe_non_sfp_link_config(hw);
4818 if (err)
4819 e_err(probe, "link_config FAILED %d\n", err);
4820 }
4821
021230d4
AV		 4822 /* clear any pending interrupts, may auto mask */
4823 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4824 ixgbe_irq_enable(adapter, true, true);
9a799d71 4825
bf069c97
DS		 4826 /*
4827 * If this adapter has a fan, check to see if we had a failure
4828 * before we enabled the interrupt.
4829 */
4830 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4831 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4832 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4833 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4834 }
4835
9a799d71
AK		 4836 /* bring the link up in the watchdog, this could race with our first
4837 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4838 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4839 adapter->link_check_timeout = jiffies;
7086400d 4840 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4841
4842 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4843 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4844 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4845 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4846}
4847
d4f80882
AV		 4848void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4849{
4850 WARN_ON(in_interrupt());
7086400d
AD		 4851 /* put off any impending NetWatchDogTimeout */
4852 adapter->netdev->trans_start = jiffies;
4853
d4f80882 4854 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4855 usleep_range(1000, 2000);
d4f80882 4856 ixgbe_down(adapter);
5809a1ae
GR		 4857 /*
4858 * If SR-IOV enabled then wait a bit before bringing the adapter
4859 * back up to give the VFs time to respond to the reset. The
4860 * two second wait is based upon the watchdog timer cycle in
4861 * the VF driver.
4862 */
4863 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4864 msleep(2000);
d4f80882
AV		 4865 ixgbe_up(adapter);
4866 clear_bit(__IXGBE_RESETTING, &adapter->state);
4867}
4868
c7ccde0f 4869void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4870{
4871 /* hardware has been reset, we need to reload some things */
4872 ixgbe_configure(adapter);
4873
c7ccde0f 4874 ixgbe_up_complete(adapter);
9a799d71
AK		 4875}
4876
4877void ixgbe_reset(struct ixgbe_adapter *adapter)
4878{
c44ade9e 4879 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 4880 struct net_device *netdev = adapter->netdev;
8ca783ab 4881 int err;
5d7daa35 4882 u8 old_addr[ETH_ALEN];
8ca783ab 4883
b0483c8f
MR		 4884 if (ixgbe_removed(hw->hw_addr))
4885 return;
7086400d
AD		 4886 /* lock SFP init bit to prevent race conditions with the watchdog */
4887 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4888 usleep_range(1000, 2000);
4889
4890 /* clear all SFP and link config related flags while holding SFP_INIT */
4891 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4892 IXGBE_FLAG2_SFP_NEEDS_RESET);
4893 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4894
8ca783ab 4895 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4896 switch (err) {
4897 case 0:
4898 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4899 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4900 break;
4901 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4902 e_dev_err("master disable timed out\n");
da4dd0f7 4903 break;
794caeb2
PWJ		 4904 case IXGBE_ERR_EEPROM_VERSION:
4905 /* We are running on a pre-production device, log a warning */
849c4542 4906 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4907 "Please be aware there may be issues associated with "
849c4542
ET		 4908 "your hardware. If you are experiencing problems "
4909 "please contact your Intel or hardware "
4910 "representative who provided you with this "
4911 "hardware.\n");
794caeb2 4912 break;
da4dd0f7 4913 default:
849c4542 4914 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4915 }
9a799d71 4916
7086400d 4917 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 4918 /* do not flush user set addresses */
4919 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
4920 ixgbe_flush_sw_mac_table(adapter);
4921 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 4922
4923 /* update SAN MAC vmdq pool selection */
4924 if (hw->mac.san_mac_rar_index)
4925 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4926
8fecf67c 4927 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4928 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4929}
4930
9a799d71
AK		 4931/**
4932 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4933 * @tx_ring: ring to be cleaned
4934 **/
b6ec895e 4935static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4936{
4937 struct ixgbe_tx_buffer *tx_buffer_info;
4938 unsigned long size;
b6ec895e 4939 u16 i;
9a799d71 4940
84418e3b
AD		 4941 /* ring already cleared, nothing to do */
4942 if (!tx_ring->tx_buffer_info)
4943 return;
9a799d71 4944
84418e3b 4945 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4946 for (i = 0; i < tx_ring->count; i++) {
4947 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4948 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4949 }
4950
dad8a3b3
JF		 4951 netdev_tx_reset_queue(txring_txq(tx_ring));
4952
9a799d71
AK		 4953 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4954 memset(tx_ring->tx_buffer_info, 0, size);
4955
4956 /* Zero out the descriptor ring */
4957 memset(tx_ring->desc, 0, tx_ring->size);
4958
4959 tx_ring->next_to_use = 0;
4960 tx_ring->next_to_clean = 0;
9a799d71
AK		 4961}
4962
4963/**
021230d4 4964 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4965 * @adapter: board private structure
4966 **/
021230d4 4967static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4968{
4969 int i;
4970
021230d4 4971 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4972 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4973}
4974
4975/**
021230d4 4976 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4977 * @adapter: board private structure
4978 **/
021230d4 4979static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4980{
4981 int i;
4982
021230d4 4983 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4984 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4985}
4986
e4911d57
AD		 4987static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4988{
b67bfe0d 4989 struct hlist_node *node2;
e4911d57
AD		 4990 struct ixgbe_fdir_filter *filter;
4991
4992 spin_lock(&adapter->fdir_perfect_lock);
4993
b67bfe0d 4994 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4995 &adapter->fdir_filter_list, fdir_node) {
4996 hlist_del(&filter->fdir_node);
4997 kfree(filter);
4998 }
4999 adapter->fdir_filter_count = 0;
5000
5001 spin_unlock(&adapter->fdir_perfect_lock);
5002}
5003
9a799d71
AK		 5004void ixgbe_down(struct ixgbe_adapter *adapter)
5005{
5006 struct net_device *netdev = adapter->netdev;
7f821875 5007 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5008 struct net_device *upper;
5009 struct list_head *iter;
9a799d71 5010 u32 rxctrl;
bf29ee6c 5011 int i;
9a799d71
AK		 5012
5013 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5014 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5015 return; /* do nothing if already down */
9a799d71
AK		 5016
5017 /* disable receives */
7f821875
JB		 5018 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
5019 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 5020
2d39d576
YZ		 5021 /* disable all enabled rx queues */
5022 for (i = 0; i < adapter->num_rx_queues; i++)
5023 /* this call also flushes the previous write */
5024 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5025
032b4325 5026 usleep_range(10000, 20000);
9a799d71 5027
7f821875
JB		 5028 netif_tx_stop_all_queues(netdev);
5029
7086400d 5030 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5031 netif_carrier_off(netdev);
5032 netif_tx_disable(netdev);
5033
2a47fa45
JF		 5034 /* disable any upper devices */
5035 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5036 if (netif_is_macvlan(upper)) {
5037 struct macvlan_dev *vlan = netdev_priv(upper);
5038
5039 if (vlan->fwd_priv) {
5040 netif_tx_stop_all_queues(upper);
5041 netif_carrier_off(upper);
5042 netif_tx_disable(upper);
5043 }
5044 }
5045 }
5046
c0dfb90e
JF		 5047 ixgbe_irq_disable(adapter);
5048
5049 ixgbe_napi_disable_all(adapter);
5050
d034acf1
AD		 5051 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5052 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5053 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5054
5055 del_timer_sync(&adapter->service_timer);
5056
34cecbbf 5057 if (adapter->num_vfs) {
8e34d1aa
AD		 5058 /* Clear EITR Select mapping */
5059 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5060
5061 /* Mark all the VFs as inactive */
5062 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5063 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5064
34cecbbf
AD		 5065 /* ping all the active vfs to let them know we are going down */
5066 ixgbe_ping_all_vfs(adapter);
5067
5068 /* Disable all VFTE/VFRE TX/RX */
5069 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5070 }
5071
7f821875
JB		 5072 /* disable transmits in the hardware now that interrupts are off */
5073 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5074 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5075 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5076 }
34cecbbf
AD		 5077
5078 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 5079 switch (hw->mac.type) {
5080 case ixgbe_mac_82599EB:
b93a2226 5081 case ixgbe_mac_X540:
88512539 5082 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5083 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5084 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5085 break;
5086 default:
5087 break;
5088 }
7f821875 5089
6f4a0e45
PL		 5090 if (!pci_channel_offline(adapter->pdev))
5091 ixgbe_reset(adapter);
c6ecf39a 5092
ec74a471
ET		 5093 /* power down the optics for 82599 SFP+ fiber */
5094 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5095 hw->mac.ops.disable_tx_laser(hw);
5096
9a799d71
AK		 5097 ixgbe_clean_all_tx_rings(adapter);
5098 ixgbe_clean_all_rx_rings(adapter);
5099
5dd2d332 5100#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5101 /* since we reset the hardware DCA settings were cleared */
e35ec126 5102 ixgbe_setup_dca(adapter);
96b0e0f6 5103#endif
9a799d71
AK		 5104}
5105
9a799d71
AK		 5106/**
5107 * ixgbe_tx_timeout - Respond to a Tx Hang
5108 * @netdev: network interface device structure
5109 **/
5110static void ixgbe_tx_timeout(struct net_device *netdev)
5111{
5112 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5113
5114 /* Do the reset outside of interrupt context */
c83c6cbd 5115 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5116}
5117
9a799d71
AK		 5118/**
5119 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5120 * @adapter: board private structure to initialize
5121 *
5122 * ixgbe_sw_init initializes the Adapter private data structure.
5123 * Fields are initialized based on PCI device information and
5124 * OS network device settings (MTU size).
5125 **/
9f9a12f8 5126static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5127{
5128 struct ixgbe_hw *hw = &adapter->hw;
5129 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5130 unsigned int rss, fdir;
cb6d0f5e 5131 u32 fwsm;
7a6b6f51 5132#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5133 int j;
5134 struct tc_configuration *tc;
5135#endif
021230d4 5136
c44ade9e
JB		 5137 /* PCI config space info */
5138
5139 hw->vendor_id = pdev->vendor;
5140 hw->device_id = pdev->device;
5141 hw->revision_id = pdev->revision;
5142 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5143 hw->subsystem_device_id = pdev->subsystem_device;
5144
8fc3bb6d 5145 /* Set common capability flags and settings */
3ed69d7e 5146 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5147 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5148 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5149 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5150 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5151 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5152 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5153 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5154 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5155#ifdef CONFIG_IXGBE_DCA
5156 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5157#endif
5158#ifdef IXGBE_FCOE
5159 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5160 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5161#ifdef CONFIG_IXGBE_DCB
5162 /* Default traffic class to use for FCoE */
5163 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5164#endif /* CONFIG_IXGBE_DCB */
5165#endif /* IXGBE_FCOE */
5166
5d7daa35
JK		 5167 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5168 hw->mac.num_rar_entries,
5169 GFP_ATOMIC);
5170
8fc3bb6d 5171 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5172 switch (hw->mac.type) {
5173 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5174 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5175 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5176
bf069c97
DS		 5177 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5178 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5179
49c7ffbe 5180 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5181 adapter->ring_feature[RING_F_FDIR].limit = 0;
5182 adapter->atr_sample_rate = 0;
5183 adapter->fdir_pballoc = 0;
5184#ifdef IXGBE_FCOE
5185 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5186 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5187#ifdef CONFIG_IXGBE_DCB
5188 adapter->fcoe.up = 0;
5189#endif /* IXGBE_DCB */
5190#endif /* IXGBE_FCOE */
5191 break;
5192 case ixgbe_mac_82599EB:
5193 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5194 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5195 break;
b93a2226 5196 case ixgbe_mac_X540:
cb6d0f5e
JK		 5197 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5198 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5199 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 5200 break;
5201 default:
5202 break;
f8212f97 5203 }
2f90b865 5204
7c8ae65a
AD		 5205#ifdef IXGBE_FCOE
5206 /* FCoE support exists, always init the FCoE lock */
5207 spin_lock_init(&adapter->fcoe.lock);
5208
5209#endif
1fc5f038
AD		 5210 /* n-tuple support exists, always init our spinlock */
5211 spin_lock_init(&adapter->fdir_perfect_lock);
5212
7a6b6f51 5213#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5214 switch (hw->mac.type) {
5215 case ixgbe_mac_X540:
5216 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5217 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5218 break;
5219 default:
5220 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5221 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5222 break;
5223 }
5224
2f90b865
AD		 5225 /* Configure DCB traffic classes */
5226 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5227 tc = &adapter->dcb_cfg.tc_config[j];
5228 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5229 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5230 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5231 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5232 tc->dcb_pfc = pfc_disabled;
5233 }
4de2a022
JF		 5234
5235 /* Initialize default user to priority mapping, UPx->TC0 */
5236 tc = &adapter->dcb_cfg.tc_config[0];
5237 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5238 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5239
2f90b865
AD		 5240 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5241 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5242 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5243 adapter->dcb_set_bitmap = 0x00;
3032309b 5244 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5245 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5246 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5247
5248#endif
9a799d71
AK		 5249
5250 /* default flow control settings */
cd7664f6 5251 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5252 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5253 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5254 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5255 hw->fc.send_xon = true;
73d80953 5256 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5257
99d74487 5258#ifdef CONFIG_PCI_IOV
170e8543
JK		 5259 if (max_vfs > 0)
5260 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5261
99d74487 5262 /* assign number of SR-IOV VFs */
170e8543 5263 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5264 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5265 adapter->num_vfs = 0;
5266 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5267 } else {
5268 adapter->num_vfs = max_vfs;
5269 }
5270 }
5271#endif /* CONFIG_PCI_IOV */
99d74487 5272
30efa5a3 5273 /* enable itr by default in dynamic mode */
f7554a2b 5274 adapter->rx_itr_setting = 1;
f7554a2b 5275 adapter->tx_itr_setting = 1;
30efa5a3 5276
30efa5a3
JB		 5277 /* set default ring sizes */
5278 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5279 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5280
bd198058 5281 /* set default work limits */
59224555 5282 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5283
9a799d71 5284 /* initialize eeprom parameters */
c44ade9e 5285 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5286 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5287 return -EIO;
5288 }
5289
2a47fa45
JF		 5290 /* PF holds first pool slot */
5291 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5292 set_bit(__IXGBE_DOWN, &adapter->state);
5293
5294 return 0;
5295}
5296
5297/**
5298 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5299 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5300 *
5301 * Return 0 on success, negative on failure
5302 **/
b6ec895e 5303int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5304{
b6ec895e 5305 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5306 int orig_node = dev_to_node(dev);
5307 int numa_node = -1;
9a799d71
AK		 5308 int size;
5309
3a581073 5310 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5311
5312 if (tx_ring->q_vector)
5313 numa_node = tx_ring->q_vector->numa_node;
5314
5315 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5316 if (!tx_ring->tx_buffer_info)
89bf67f1 5317 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5318 if (!tx_ring->tx_buffer_info)
5319 goto err;
9a799d71 5320
827da44c
JS		 5321 u64_stats_init(&tx_ring->syncp);
5322
9a799d71 5323 /* round up to nearest 4K */
12207e49 5324 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5325 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5326
de88eeeb
AD		 5327 set_dev_node(dev, numa_node);
5328 tx_ring->desc = dma_alloc_coherent(dev,
5329 tx_ring->size,
5330 &tx_ring->dma,
5331 GFP_KERNEL);
5332 set_dev_node(dev, orig_node);
5333 if (!tx_ring->desc)
5334 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5335 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5336 if (!tx_ring->desc)
5337 goto err;
9a799d71 5338
3a581073
JB		 5339 tx_ring->next_to_use = 0;
5340 tx_ring->next_to_clean = 0;
9a799d71 5341 return 0;
e01c31a5
JB		 5342
5343err:
5344 vfree(tx_ring->tx_buffer_info);
5345 tx_ring->tx_buffer_info = NULL;
b6ec895e 5346 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5347 return -ENOMEM;
9a799d71
AK		 5348}
5349
69888674
AD		 5350/**
5351 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5352 * @adapter: board private structure
5353 *
5354 * If this function returns with an error, then it's possible one or
5355 * more of the rings is populated (while the rest are not). It is the
5356 * callers duty to clean those orphaned rings.
5357 *
5358 * Return 0 on success, negative on failure
5359 **/
5360static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5361{
5362 int i, err = 0;
5363
5364 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5365 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5366 if (!err)
5367 continue;
de3d5b94 5368
396e799c 5369 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5370 goto err_setup_tx;
69888674
AD		 5371 }
5372
de3d5b94
AD		 5373 return 0;
5374err_setup_tx:
5375 /* rewind the index freeing the rings as we go */
5376 while (i--)
5377 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5378 return err;
5379}
5380
9a799d71
AK		 5381/**
5382 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5383 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5384 *
5385 * Returns 0 on success, negative on failure
5386 **/
b6ec895e 5387int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5388{
b6ec895e 5389 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5390 int orig_node = dev_to_node(dev);
5391 int numa_node = -1;
021230d4 5392 int size;
9a799d71 5393
3a581073 5394 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5395
5396 if (rx_ring->q_vector)
5397 numa_node = rx_ring->q_vector->numa_node;
5398
5399 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5400 if (!rx_ring->rx_buffer_info)
89bf67f1 5401 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5402 if (!rx_ring->rx_buffer_info)
5403 goto err;
9a799d71 5404
827da44c
JS		 5405 u64_stats_init(&rx_ring->syncp);
5406
9a799d71 5407 /* Round up to nearest 4K */
3a581073
JB		 5408 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5409 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5410
de88eeeb
AD		 5411 set_dev_node(dev, numa_node);
5412 rx_ring->desc = dma_alloc_coherent(dev,
5413 rx_ring->size,
5414 &rx_ring->dma,
5415 GFP_KERNEL);
5416 set_dev_node(dev, orig_node);
5417 if (!rx_ring->desc)
5418 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5419 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5420 if (!rx_ring->desc)
5421 goto err;
9a799d71 5422
3a581073
JB		 5423 rx_ring->next_to_clean = 0;
5424 rx_ring->next_to_use = 0;
9a799d71
AK		 5425
5426 return 0;
b6ec895e
AD		 5427err:
5428 vfree(rx_ring->rx_buffer_info);
5429 rx_ring->rx_buffer_info = NULL;
5430 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5431 return -ENOMEM;
9a799d71
AK		 5432}
5433
69888674
AD		 5434/**
5435 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5436 * @adapter: board private structure
5437 *
5438 * If this function returns with an error, then it's possible one or
5439 * more of the rings is populated (while the rest are not). It is the
5440 * callers duty to clean those orphaned rings.
5441 *
5442 * Return 0 on success, negative on failure
5443 **/
69888674
AD		 5444static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5445{
5446 int i, err = 0;
5447
5448 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5449 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5450 if (!err)
5451 continue;
de3d5b94 5452
396e799c 5453 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5454 goto err_setup_rx;
69888674
AD		 5455 }
5456
7c8ae65a
AD		 5457#ifdef IXGBE_FCOE
5458 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5459 if (!err)
5460#endif
5461 return 0;
de3d5b94
AD		 5462err_setup_rx:
5463 /* rewind the index freeing the rings as we go */
5464 while (i--)
5465 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5466 return err;
5467}
5468
9a799d71
AK		 5469/**
5470 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5471 * @tx_ring: Tx descriptor ring for a specific queue
5472 *
5473 * Free all transmit software resources
5474 **/
b6ec895e 5475void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5476{
b6ec895e 5477 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5478
5479 vfree(tx_ring->tx_buffer_info);
5480 tx_ring->tx_buffer_info = NULL;
5481
b6ec895e
AD		 5482 /* if not set, then don't free */
5483 if (!tx_ring->desc)
5484 return;
5485
5486 dma_free_coherent(tx_ring->dev, tx_ring->size,
5487 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5488
5489 tx_ring->desc = NULL;
5490}
5491
5492/**
5493 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5494 * @adapter: board private structure
5495 *
5496 * Free all transmit software resources
5497 **/
5498static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5499{
5500 int i;
5501
5502 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5503 if (adapter->tx_ring[i]->desc)
b6ec895e 5504 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5505}
5506
5507/**
b4617240 5508 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5509 * @rx_ring: ring to clean the resources from
5510 *
5511 * Free all receive software resources
5512 **/
b6ec895e 5513void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5514{
b6ec895e 5515 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5516
5517 vfree(rx_ring->rx_buffer_info);
5518 rx_ring->rx_buffer_info = NULL;
5519
b6ec895e
AD		 5520 /* if not set, then don't free */
5521 if (!rx_ring->desc)
5522 return;
5523
5524 dma_free_coherent(rx_ring->dev, rx_ring->size,
5525 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5526
5527 rx_ring->desc = NULL;
5528}
5529
5530/**
5531 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5532 * @adapter: board private structure
5533 *
5534 * Free all receive software resources
5535 **/
5536static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5537{
5538 int i;
5539
7c8ae65a
AD		 5540#ifdef IXGBE_FCOE
5541 ixgbe_free_fcoe_ddp_resources(adapter);
5542
5543#endif
9a799d71 5544 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5545 if (adapter->rx_ring[i]->desc)
b6ec895e 5546 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5547}
5548
9a799d71
AK		 5549/**
5550 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5551 * @netdev: network interface device structure
5552 * @new_mtu: new value for maximum frame size
5553 *
5554 * Returns 0 on success, negative on failure
5555 **/
5556static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5557{
5558 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5559 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5560
42c783c5 5561 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5562 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5563 return -EINVAL;
5564
5565 /*
872844dd
AD		 5566 * For 82599EB we cannot allow legacy VFs to enable their receive
5567 * paths when MTU greater than 1500 is configured. So display a
5568 * warning that legacy VFs will be disabled.
655309e9
AD		 5569 */
5570 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5571 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5572 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5573 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5574
396e799c 5575 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5576
021230d4 5577 /* must set new MTU before calling down or up */
9a799d71
AK		 5578 netdev->mtu = new_mtu;
5579
d4f80882
AV		 5580 if (netif_running(netdev))
5581 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5582
5583 return 0;
5584}
5585
5586/**
5587 * ixgbe_open - Called when a network interface is made active
5588 * @netdev: network interface device structure
5589 *
5590 * Returns 0 on success, negative value on failure
5591 *
5592 * The open entry point is called when a network interface is made
5593 * active by the system (IFF_UP). At this point all resources needed
5594 * for transmit and receive operations are allocated, the interrupt
5595 * handler is registered with the OS, the watchdog timer is started,
5596 * and the stack is notified that the interface is ready.
5597 **/
5598static int ixgbe_open(struct net_device *netdev)
5599{
5600 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5601 int err, queues;
4bebfaa5
AK		 5602
5603 /* disallow open during test */
5604 if (test_bit(__IXGBE_TESTING, &adapter->state))
5605 return -EBUSY;
9a799d71 5606
54386467
JB		 5607 netif_carrier_off(netdev);
5608
9a799d71
AK		 5609 /* allocate transmit descriptors */
5610 err = ixgbe_setup_all_tx_resources(adapter);
5611 if (err)
5612 goto err_setup_tx;
5613
9a799d71
AK		 5614 /* allocate receive descriptors */
5615 err = ixgbe_setup_all_rx_resources(adapter);
5616 if (err)
5617 goto err_setup_rx;
5618
5619 ixgbe_configure(adapter);
5620
021230d4 5621 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5622 if (err)
5623 goto err_req_irq;
5624
ac802f5d 5625 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5626 if (adapter->num_rx_pools > 1)
5627 queues = adapter->num_rx_queues_per_pool;
5628 else
5629 queues = adapter->num_tx_queues;
5630
5631 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5632 if (err)
5633 goto err_set_queues;
5634
2a47fa45
JF		 5635 if (adapter->num_rx_pools > 1 &&
5636 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5637 queues = IXGBE_MAX_L2A_QUEUES;
5638 else
5639 queues = adapter->num_rx_queues;
5640 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5641 if (err)
5642 goto err_set_queues;
5643
1a71ab24 5644 ixgbe_ptp_init(adapter);
1a71ab24 5645
c7ccde0f 5646 ixgbe_up_complete(adapter);
9a799d71
AK		 5647
5648 return 0;
5649
ac802f5d
AD		 5650err_set_queues:
5651 ixgbe_free_irq(adapter);
9a799d71 5652err_req_irq:
a20a1199 5653 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5654err_setup_rx:
a20a1199 5655 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5656err_setup_tx:
9a799d71
AK		 5657 ixgbe_reset(adapter);
5658
5659 return err;
5660}
5661
5662/**
5663 * ixgbe_close - Disables a network interface
5664 * @netdev: network interface device structure
5665 *
5666 * Returns 0, this is not allowed to fail
5667 *
5668 * The close entry point is called when an interface is de-activated
5669 * by the OS. The hardware is still under the drivers control, but
5670 * needs to be disabled. A global MAC reset is issued to stop the
5671 * hardware, and all transmit and receive resources are freed.
5672 **/
5673static int ixgbe_close(struct net_device *netdev)
5674{
5675 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5676
1a71ab24 5677 ixgbe_ptp_stop(adapter);
1a71ab24 5678
9a799d71
AK		 5679 ixgbe_down(adapter);
5680 ixgbe_free_irq(adapter);
5681
e4911d57
AD		 5682 ixgbe_fdir_filter_exit(adapter);
5683
9a799d71
AK		 5684 ixgbe_free_all_tx_resources(adapter);
5685 ixgbe_free_all_rx_resources(adapter);
5686
5eba3699 5687 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5688
5689 return 0;
5690}
5691
b3c8b4ba
AD		 5692#ifdef CONFIG_PM
5693static int ixgbe_resume(struct pci_dev *pdev)
5694{
c60fbb00
AD		 5695 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5696 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5697 u32 err;
5698
0391bbe3 5699 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5700 pci_set_power_state(pdev, PCI_D0);
5701 pci_restore_state(pdev);
656ab817
DS		 5702 /*
5703 * pci_restore_state clears dev->state_saved so call
5704 * pci_save_state to restore it.
5705 */
5706 pci_save_state(pdev);
9ce77666 5707
5708 err = pci_enable_device_mem(pdev);
b3c8b4ba 5709 if (err) {
849c4542 5710 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5711 return err;
5712 }
41c62843
MR		 5713 smp_mb__before_clear_bit();
5714 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5715 pci_set_master(pdev);
5716
dd4d8ca6 5717 pci_wake_from_d3(pdev, false);
b3c8b4ba 5718
b3c8b4ba
AD		 5719 ixgbe_reset(adapter);
5720
495dce12
WJP		 5721 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5722
ac802f5d
AD		 5723 rtnl_lock();
5724 err = ixgbe_init_interrupt_scheme(adapter);
5725 if (!err && netif_running(netdev))
c60fbb00 5726 err = ixgbe_open(netdev);
ac802f5d
AD		 5727
5728 rtnl_unlock();
5729
5730 if (err)
5731 return err;
b3c8b4ba
AD		 5732
5733 netif_device_attach(netdev);
5734
5735 return 0;
5736}
b3c8b4ba 5737#endif /* CONFIG_PM */
9d8d05ae
RW		 5738
5739static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5740{
c60fbb00
AD		 5741 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5742 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5743 struct ixgbe_hw *hw = &adapter->hw;
5744 u32 ctrl, fctrl;
5745 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5746#ifdef CONFIG_PM
5747 int retval = 0;
5748#endif
5749
5750 netif_device_detach(netdev);
5751
499ab5cc 5752 rtnl_lock();
b3c8b4ba
AD		 5753 if (netif_running(netdev)) {
5754 ixgbe_down(adapter);
5755 ixgbe_free_irq(adapter);
5756 ixgbe_free_all_tx_resources(adapter);
5757 ixgbe_free_all_rx_resources(adapter);
5758 }
499ab5cc 5759 rtnl_unlock();
b3c8b4ba 5760
5f5ae6fc
AD		 5761 ixgbe_clear_interrupt_scheme(adapter);
5762
b3c8b4ba
AD		 5763#ifdef CONFIG_PM
5764 retval = pci_save_state(pdev);
5765 if (retval)
5766 return retval;
4df10466 5767
b3c8b4ba 5768#endif
f4f1040a
JK		 5769 if (hw->mac.ops.stop_link_on_d3)
5770 hw->mac.ops.stop_link_on_d3(hw);
5771
e8e26350
PW		 5772 if (wufc) {
5773 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5774
ec74a471
ET		 5775 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5776 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5777 hw->mac.ops.enable_tx_laser(hw);
5778
e8e26350
PW		 5779 /* turn on all-multi mode if wake on multicast is enabled */
5780 if (wufc & IXGBE_WUFC_MC) {
5781 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5782 fctrl |= IXGBE_FCTRL_MPE;
5783 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5784 }
5785
5786 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5787 ctrl |= IXGBE_CTRL_GIO_DIS;
5788 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5789
5790 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5791 } else {
5792 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5793 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5794 }
5795
bd508178
AD		 5796 switch (hw->mac.type) {
5797 case ixgbe_mac_82598EB:
dd4d8ca6 5798 pci_wake_from_d3(pdev, false);
bd508178
AD		 5799 break;
5800 case ixgbe_mac_82599EB:
b93a2226 5801 case ixgbe_mac_X540:
bd508178
AD		 5802 pci_wake_from_d3(pdev, !!wufc);
5803 break;
5804 default:
5805 break;
5806 }
b3c8b4ba 5807
9d8d05ae
RW		 5808 *enable_wake = !!wufc;
5809
b3c8b4ba
AD		 5810 ixgbe_release_hw_control(adapter);
5811
41c62843
MR		 5812 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5813 pci_disable_device(pdev);
b3c8b4ba 5814
9d8d05ae
RW		 5815 return 0;
5816}
5817
5818#ifdef CONFIG_PM
5819static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5820{
5821 int retval;
5822 bool wake;
5823
5824 retval = __ixgbe_shutdown(pdev, &wake);
5825 if (retval)
5826 return retval;
5827
5828 if (wake) {
5829 pci_prepare_to_sleep(pdev);
5830 } else {
5831 pci_wake_from_d3(pdev, false);
5832 pci_set_power_state(pdev, PCI_D3hot);
5833 }
b3c8b4ba
AD		 5834
5835 return 0;
5836}
9d8d05ae 5837#endif /* CONFIG_PM */
b3c8b4ba
AD		 5838
5839static void ixgbe_shutdown(struct pci_dev *pdev)
5840{
9d8d05ae
RW		 5841 bool wake;
5842
5843 __ixgbe_shutdown(pdev, &wake);
5844
5845 if (system_state == SYSTEM_POWER_OFF) {
5846 pci_wake_from_d3(pdev, wake);
5847 pci_set_power_state(pdev, PCI_D3hot);
5848 }
b3c8b4ba
AD		 5849}
5850
9a799d71
AK		 5851/**
5852 * ixgbe_update_stats - Update the board statistics counters.
5853 * @adapter: board private structure
5854 **/
5855void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5856{
2d86f139 5857 struct net_device *netdev = adapter->netdev;
9a799d71 5858 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5859 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5860 u64 total_mpc = 0;
5861 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5862 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5863 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5864 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5865
d08935c2
DS		 5866 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5867 test_bit(__IXGBE_RESETTING, &adapter->state))
5868 return;
5869
94b982b2 5870 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5871 u64 rsc_count = 0;
94b982b2 5872 u64 rsc_flush = 0;
94b982b2 5873 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5874 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5875 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5876 }
5877 adapter->rsc_total_count = rsc_count;
5878 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5879 }
5880
5b7da515
AD		 5881 for (i = 0; i < adapter->num_rx_queues; i++) {
5882 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5883 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5884 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5885 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5886 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5887 bytes += rx_ring->stats.bytes;
5888 packets += rx_ring->stats.packets;
5889 }
5890 adapter->non_eop_descs = non_eop_descs;
5891 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5892 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5893 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5894 netdev->stats.rx_bytes = bytes;
5895 netdev->stats.rx_packets = packets;
5896
5897 bytes = 0;
5898 packets = 0;
7ca3bc58 5899 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5900 for (i = 0; i < adapter->num_tx_queues; i++) {
5901 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5902 restart_queue += tx_ring->tx_stats.restart_queue;
5903 tx_busy += tx_ring->tx_stats.tx_busy;
5904 bytes += tx_ring->stats.bytes;
5905 packets += tx_ring->stats.packets;
5906 }
eb985f09 5907 adapter->restart_queue = restart_queue;
5b7da515
AD		 5908 adapter->tx_busy = tx_busy;
5909 netdev->stats.tx_bytes = bytes;
5910 netdev->stats.tx_packets = packets;
7ca3bc58 5911
7ca647bd 5912 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5913
5914 /* 8 register reads */
6f11eef7
AV		 5915 for (i = 0; i < 8; i++) {
5916 /* for packet buffers not used, the register should read 0 */
5917 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5918 missed_rx += mpc;
7ca647bd
JP		 5919 hwstats->mpc[i] += mpc;
5920 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5921 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5922 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5923 switch (hw->mac.type) {
5924 case ixgbe_mac_82598EB:
1a70db4b
ET		 5925 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5926 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5927 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5928 hwstats->pxonrxc[i] +=
5929 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5930 break;
5931 case ixgbe_mac_82599EB:
b93a2226 5932 case ixgbe_mac_X540:
bd508178
AD		 5933 hwstats->pxonrxc[i] +=
5934 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5935 break;
5936 default:
5937 break;
e8e26350 5938 }
6f11eef7 5939 }
1a70db4b
ET		 5940
5941 /*16 register reads */
5942 for (i = 0; i < 16; i++) {
5943 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5944 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5945 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5946 (hw->mac.type == ixgbe_mac_X540)) {
5947 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5948 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5949 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5950 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5951 }
5952 }
5953
7ca647bd 5954 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5955 /* work around hardware counting issue */
7ca647bd 5956 hwstats->gprc -= missed_rx;
6f11eef7 5957
c84d324c
JF		 5958 ixgbe_update_xoff_received(adapter);
5959
6f11eef7 5960 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5961 switch (hw->mac.type) {
5962 case ixgbe_mac_82598EB:
5963 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5964 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5965 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5966 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5967 break;
b93a2226 5968 case ixgbe_mac_X540:
58f6bcf9
ET		 5969 /* OS2BMC stats are X540 only*/
5970 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5971 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5972 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5973 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5974 case ixgbe_mac_82599EB:
a4d4f629
AD		 5975 for (i = 0; i < 16; i++)
5976 adapter->hw_rx_no_dma_resources +=
5977 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5978 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5979 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5980 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5981 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5982 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5983 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5984 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5985 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5986 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5987#ifdef IXGBE_FCOE
7ca647bd
JP		 5988 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5989 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5990 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5991 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5992 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5993 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5994 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5995 if (adapter->fcoe.ddp_pool) {
5996 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5997 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5998 unsigned int cpu;
5999 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6000 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6001 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6002 noddp += ddp_pool->noddp;
6003 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6004 }
5a1ee270
AD		 6005 hwstats->fcoe_noddp = noddp;
6006 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6007 }
6d45522c 6008#endif /* IXGBE_FCOE */
bd508178
AD		 6009 break;
6010 default:
6011 break;
e8e26350 6012 }
9a799d71 6013 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6014 hwstats->bprc += bprc;
6015 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6016 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6017 hwstats->mprc -= bprc;
6018 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6019 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6020 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6021 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6022 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6023 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6024 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6025 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6026 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6027 hwstats->lxontxc += lxon;
6f11eef7 6028 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6029 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6030 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6031 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6032 /*
6033 * 82598 errata - tx of flow control packets is included in tx counters
6034 */
6035 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6036 hwstats->gptc -= xon_off_tot;
6037 hwstats->mptc -= xon_off_tot;
6038 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6039 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6040 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6041 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6042 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6043 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6044 hwstats->ptc64 -= xon_off_tot;
6045 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6046 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6047 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6048 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6049 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6050 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6051
6052 /* Fill out the OS statistics structure */
7ca647bd 6053 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6054
6055 /* Rx Errors */
7ca647bd 6056 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6057 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6058 netdev->stats.rx_length_errors = hwstats->rlec;
6059 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6060 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6061}
6062
6063/**
d034acf1 6064 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6065 * @adapter: pointer to the device adapter structure
9a799d71 6066 **/
d034acf1 6067static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6068{
cf8280ee 6069 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6070 int i;
cf8280ee 6071
d034acf1
AD		 6072 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6073 return;
6074
6075 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6076
d034acf1 6077 /* if interface is down do nothing */
fe49f04a 6078 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6079 return;
6080
6081 /* do nothing if we are not using signature filters */
6082 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6083 return;
6084
6085 adapter->fdir_overflow++;
6086
93c52dd0
AD		 6087 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6088 for (i = 0; i < adapter->num_tx_queues; i++)
6089 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 6090 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6091 /* re-enable flow director interrupts */
6092 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6093 } else {
6094 e_err(probe, "failed to finish FDIR re-initialization, "
6095 "ignored adding FDIR ATR filters\n");
6096 }
93c52dd0
AD		 6097}
6098
6099/**
6100 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6101 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6102 *
6103 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6104 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6105 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6106 * determine if a hang has occurred.
93c52dd0
AD		 6107 */
6108static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6109{
cf8280ee 6110 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6111 u64 eics = 0;
6112 int i;
cf8280ee 6113
09f40aed 6114 /* If we're down, removing or resetting, just bail */
93c52dd0 6115 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6116 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6117 test_bit(__IXGBE_RESETTING, &adapter->state))
6118 return;
22d5a71b 6119
93c52dd0
AD		 6120 /* Force detection of hung controller */
6121 if (netif_carrier_ok(adapter->netdev)) {
6122 for (i = 0; i < adapter->num_tx_queues; i++)
6123 set_check_for_tx_hang(adapter->tx_ring[i]);
6124 }
22d5a71b 6125
fe49f04a
AD		 6126 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6127 /*
6128 * for legacy and MSI interrupts don't set any bits
6129 * that are enabled for EIAM, because this operation
6130 * would set *both* EIMS and EICS for any bit in EIAM
6131 */
6132 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6133 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6134 } else {
6135 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6136 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6137 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6138 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6139 eics |= ((u64)1 << i);
6140 }
cf8280ee 6141 }
9a799d71 6142
93c52dd0 6143 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6144 ixgbe_irq_rearm_queues(adapter, eics);
6145
cf8280ee
JB		 6146}
6147
e8e26350 6148/**
93c52dd0 6149 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6150 * @adapter: pointer to the device adapter structure
6151 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6152 **/
93c52dd0 6153static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6154{
e8e26350 6155 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6156 u32 link_speed = adapter->link_speed;
6157 bool link_up = adapter->link_up;
041441d0 6158 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6159
93c52dd0
AD		 6160 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6161 return;
6162
6163 if (hw->mac.ops.check_link) {
6164 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6165 } else {
93c52dd0
AD		 6166 /* always assume link is up, if no check link function */
6167 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6168 link_up = true;
c4cf55e5 6169 }
041441d0
AD		 6170
6171 if (adapter->ixgbe_ieee_pfc)
6172 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6173
3ebe8fde 6174 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6175 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6176 ixgbe_set_rx_drop_en(adapter);
6177 }
93c52dd0
AD		 6178
6179 if (link_up ||
6180 time_after(jiffies, (adapter->link_check_timeout +
6181 IXGBE_TRY_LINK_TIMEOUT))) {
6182 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6183 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6184 IXGBE_WRITE_FLUSH(hw);
6185 }
6186
6187 adapter->link_up = link_up;
6188 adapter->link_speed = link_speed;
e8e26350
PW		 6189}
6190
107d3018
AD		 6191static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6192{
6193#ifdef CONFIG_IXGBE_DCB
6194 struct net_device *netdev = adapter->netdev;
6195 struct dcb_app app = {
6196 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6197 .protocol = 0,
6198 };
6199 u8 up = 0;
6200
6201 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6202 up = dcb_ieee_getapp_mask(netdev, &app);
6203
6204 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6205#endif
6206}
6207
e8e26350 6208/**
93c52dd0
AD		 6209 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6210 * print link up message
49ce9c2c 6211 * @adapter: pointer to the device adapter structure
e8e26350 6212 **/
93c52dd0 6213static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6214{
93c52dd0 6215 struct net_device *netdev = adapter->netdev;
e8e26350 6216 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6217 struct net_device *upper;
6218 struct list_head *iter;
93c52dd0
AD		 6219 u32 link_speed = adapter->link_speed;
6220 bool flow_rx, flow_tx;
e8e26350 6221
93c52dd0
AD		 6222 /* only continue if link was previously down */
6223 if (netif_carrier_ok(netdev))
a985b6c3 6224 return;
63d6e1d8 6225
93c52dd0 6226 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6227
93c52dd0
AD		 6228 switch (hw->mac.type) {
6229 case ixgbe_mac_82598EB: {
6230 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6231 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6232 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6233 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6234 }
6235 break;
6236 case ixgbe_mac_X540:
6237 case ixgbe_mac_82599EB: {
6238 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6239 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6240 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6241 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6242 }
6243 break;
6244 default:
6245 flow_tx = false;
6246 flow_rx = false;
6247 break;
e8e26350 6248 }
3a6a4eda 6249
6cb562d6
JK		 6250 adapter->last_rx_ptp_check = jiffies;
6251
8fecf67c 6252 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6253 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6254
93c52dd0
AD		 6255 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6256 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6257 "10 Gbps" :
6258 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6259 "1 Gbps" :
6260 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6261 "100 Mbps" :
6262 "unknown speed"))),
6263 ((flow_rx && flow_tx) ? "RX/TX" :
6264 (flow_rx ? "RX" :
6265 (flow_tx ? "TX" : "None"))));
e8e26350 6266
93c52dd0 6267 netif_carrier_on(netdev);
93c52dd0 6268 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6269
cdc04dcc
ET		 6270 /* enable transmits */
6271 netif_tx_wake_all_queues(adapter->netdev);
6272
6273 /* enable any upper devices */
6274 rtnl_lock();
6275 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6276 if (netif_is_macvlan(upper)) {
6277 struct macvlan_dev *vlan = netdev_priv(upper);
6278
6279 if (vlan->fwd_priv)
6280 netif_tx_wake_all_queues(upper);
6281 }
6282 }
6283 rtnl_unlock();
6284
107d3018
AD		 6285 /* update the default user priority for VFs */
6286 ixgbe_update_default_up(adapter);
6287
befa2af7
AD		 6288 /* ping all the active vfs to let them know link has changed */
6289 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6290}
6291
c4cf55e5 6292/**
93c52dd0
AD		 6293 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6294 * print link down message
49ce9c2c 6295 * @adapter: pointer to the adapter structure
c4cf55e5 6296 **/
581330ba 6297static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6298{
cf8280ee 6299 struct net_device *netdev = adapter->netdev;
c4cf55e5 6300 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6301
93c52dd0
AD		 6302 adapter->link_up = false;
6303 adapter->link_speed = 0;
cf8280ee 6304
93c52dd0
AD		 6305 /* only continue if link was up previously */
6306 if (!netif_carrier_ok(netdev))
6307 return;
264857b8 6308
93c52dd0
AD		 6309 /* poll for SFP+ cable when link is down */
6310 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6311 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6312
8fecf67c 6313 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6314 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6315
93c52dd0
AD		 6316 e_info(drv, "NIC Link is Down\n");
6317 netif_carrier_off(netdev);
befa2af7
AD		 6318
6319 /* ping all the active vfs to let them know link has changed */
6320 ixgbe_ping_all_vfs(adapter);
93c52dd0 6321}
e8e26350 6322
93c52dd0
AD		 6323/**
6324 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6325 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6326 **/
6327static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6328{
c4cf55e5 6329 int i;
93c52dd0 6330 int some_tx_pending = 0;
c4cf55e5 6331
93c52dd0 6332 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6333 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6334 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6335 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6336 some_tx_pending = 1;
6337 break;
6338 }
6339 }
6340
6341 if (some_tx_pending) {
6342 /* We've lost link, so the controller stops DMA,
6343 * but we've got queued Tx work that's never going
6344 * to get done, so reset controller to flush Tx.
6345 * (Do the reset outside of interrupt context).
6346 */
12ff3f3b 6347 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6348 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6349 }
c4cf55e5 6350 }
c4cf55e5
PWJ		 6351}
6352
a985b6c3
GR		 6353static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6354{
6355 u32 ssvpc;
6356
0584d999
GR		 6357 /* Do not perform spoof check for 82598 or if not in IOV mode */
6358 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6359 adapter->num_vfs == 0)
a985b6c3
GR		 6360 return;
6361
6362 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6363
6364 /*
6365 * ssvpc register is cleared on read, if zero then no
6366 * spoofed packets in the last interval.
6367 */
6368 if (!ssvpc)
6369 return;
6370
d6ea0754 6371 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6372}
6373
93c52dd0
AD		 6374/**
6375 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6376 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6377 **/
6378static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6379{
09f40aed 6380 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6381 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6382 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6383 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6384 return;
6385
6386 ixgbe_watchdog_update_link(adapter);
6387
6388 if (adapter->link_up)
6389 ixgbe_watchdog_link_is_up(adapter);
6390 else
6391 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6392
a985b6c3 6393 ixgbe_spoof_check(adapter);
9a799d71 6394 ixgbe_update_stats(adapter);
93c52dd0
AD		 6395
6396 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6397}
10eec955 6398
cf8280ee 6399/**
7086400d 6400 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6401 * @adapter: the ixgbe adapter structure
cf8280ee 6402 **/
7086400d 6403static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6404{
cf8280ee 6405 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6406 s32 err;
cf8280ee 6407
7086400d
AD		 6408 /* not searching for SFP so there is nothing to do here */
6409 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6410 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6411 return;
10eec955 6412
7086400d
AD		 6413 /* someone else is in init, wait until next service event */
6414 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6415 return;
cf8280ee 6416
7086400d
AD		 6417 err = hw->phy.ops.identify_sfp(hw);
6418 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6419 goto sfp_out;
264857b8 6420
7086400d
AD		 6421 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6422 /* If no cable is present, then we need to reset
6423 * the next time we find a good cable. */
6424 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6425 }
9a799d71 6426
7086400d
AD		 6427 /* exit on error */
6428 if (err)
6429 goto sfp_out;
e8e26350 6430
7086400d
AD		 6431 /* exit if reset not needed */
6432 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6433 goto sfp_out;
9a799d71 6434
7086400d 6435 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6436
7086400d
AD		 6437 /*
6438 * A module may be identified correctly, but the EEPROM may not have
6439 * support for that module. setup_sfp() will fail in that case, so
6440 * we should not allow that module to load.
6441 */
6442 if (hw->mac.type == ixgbe_mac_82598EB)
6443 err = hw->phy.ops.reset(hw);
6444 else
6445 err = hw->mac.ops.setup_sfp(hw);
6446
6447 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6448 goto sfp_out;
6449
6450 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6451 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6452
6453sfp_out:
6454 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6455
6456 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6457 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6458 e_dev_err("failed to initialize because an unsupported "
6459 "SFP+ module type was detected.\n");
6460 e_dev_err("Reload the driver after installing a "
6461 "supported module.\n");
6462 unregister_netdev(adapter->netdev);
bc59fcda 6463 }
7086400d 6464}
bc59fcda 6465
7086400d
AD		 6466/**
6467 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6468 * @adapter: the ixgbe adapter structure
7086400d
AD		 6469 **/
6470static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6471{
6472 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6473 u32 speed;
6474 bool autoneg = false;
7086400d
AD		 6475
6476 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6477 return;
6478
6479 /* someone else is in init, wait until next service event */
6480 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6481 return;
6482
6483 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6484
3d292265 6485 speed = hw->phy.autoneg_advertised;
ed33ff66 6486 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6487 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6488
6489 /* setup the highest link when no autoneg */
6490 if (!autoneg) {
6491 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6492 speed = IXGBE_LINK_SPEED_10GB_FULL;
6493 }
6494 }
6495
7086400d 6496 if (hw->mac.ops.setup_link)
fd0326f2 6497 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6498
6499 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6500 adapter->link_check_timeout = jiffies;
6501 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6502}
6503
83c61fa9
GR		 6504#ifdef CONFIG_PCI_IOV
6505static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6506{
6507 int vf;
6508 struct ixgbe_hw *hw = &adapter->hw;
6509 struct net_device *netdev = adapter->netdev;
6510 u32 gpc;
6511 u32 ciaa, ciad;
6512
6513 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6514 if (gpc) /* If incrementing then no need for the check below */
6515 return;
6516 /*
6517 * Check to see if a bad DMA write target from an errant or
6518 * malicious VF has caused a PCIe error. If so then we can
6519 * issue a VFLR to the offending VF(s) and then resume without
6520 * requesting a full slot reset.
6521 */
6522
6523 for (vf = 0; vf < adapter->num_vfs; vf++) {
6524 ciaa = (vf << 16) | 0x80000000;
6525 /* 32 bit read so align, we really want status at offset 6 */
6526 ciaa |= PCI_COMMAND;
6527 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6528 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6529 ciaa &= 0x7FFFFFFF;
6530 /* disable debug mode asap after reading data */
6531 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6532 /* Get the upper 16 bits which will be the PCI status reg */
6533 ciad >>= 16;
6534 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6535 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6536 /* Issue VFLR */
6537 ciaa = (vf << 16) | 0x80000000;
6538 ciaa |= 0xA8;
6539 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6540 ciad = 0x00008000; /* VFLR */
6541 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6542 ciaa &= 0x7FFFFFFF;
6543 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6544 }
6545 }
6546}
6547
6548#endif
7086400d
AD		 6549/**
6550 * ixgbe_service_timer - Timer Call-back
6551 * @data: pointer to adapter cast into an unsigned long
6552 **/
6553static void ixgbe_service_timer(unsigned long data)
6554{
6555 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6556 unsigned long next_event_offset;
83c61fa9 6557 bool ready = true;
7086400d 6558
6bb78cfb
AD		 6559 /* poll faster when waiting for link */
6560 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6561 next_event_offset = HZ / 10;
6562 else
6563 next_event_offset = HZ * 2;
83c61fa9 6564
6bb78cfb 6565#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6566 /*
6567 * don't bother with SR-IOV VF DMA hang check if there are
6568 * no VFs or the link is down
6569 */
6570 if (!adapter->num_vfs ||
6bb78cfb 6571 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6572 goto normal_timer_service;
83c61fa9
GR		 6573
6574 /* If we have VFs allocated then we must check for DMA hangs */
6575 ixgbe_check_for_bad_vf(adapter);
6576 next_event_offset = HZ / 50;
6577 adapter->timer_event_accumulator++;
6578
6bb78cfb 6579 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6580 adapter->timer_event_accumulator = 0;
7086400d 6581 else
6bb78cfb 6582 ready = false;
7086400d 6583
6bb78cfb 6584normal_timer_service:
83c61fa9 6585#endif
7086400d
AD		 6586 /* Reset the timer */
6587 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6588
83c61fa9
GR		 6589 if (ready)
6590 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6591}
6592
c83c6cbd
AD		 6593static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6594{
6595 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6596 return;
6597
6598 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6599
09f40aed 6600 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6601 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6602 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6603 test_bit(__IXGBE_RESETTING, &adapter->state))
6604 return;
6605
6606 ixgbe_dump(adapter);
6607 netdev_err(adapter->netdev, "Reset adapter\n");
6608 adapter->tx_timeout_count++;
6609
8f4c5c9f 6610 rtnl_lock();
c83c6cbd 6611 ixgbe_reinit_locked(adapter);
8f4c5c9f 6612 rtnl_unlock();
c83c6cbd
AD		 6613}
6614
7086400d
AD		 6615/**
6616 * ixgbe_service_task - manages and runs subtasks
6617 * @work: pointer to work_struct containing our data
6618 **/
6619static void ixgbe_service_task(struct work_struct *work)
6620{
6621 struct ixgbe_adapter *adapter = container_of(work,
6622 struct ixgbe_adapter,
6623 service_task);
b0483c8f
MR		 6624 if (ixgbe_removed(adapter->hw.hw_addr)) {
6625 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6626 rtnl_lock();
6627 ixgbe_down(adapter);
6628 rtnl_unlock();
6629 }
6630 ixgbe_service_event_complete(adapter);
6631 return;
6632 }
c83c6cbd 6633 ixgbe_reset_subtask(adapter);
7086400d
AD		 6634 ixgbe_sfp_detection_subtask(adapter);
6635 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6636 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6637 ixgbe_watchdog_subtask(adapter);
d034acf1 6638 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6639 ixgbe_check_hang_subtask(adapter);
891dc082 6640
8fecf67c 6641 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6642 ixgbe_ptp_overflow_check(adapter);
6643 ixgbe_ptp_rx_hang(adapter);
6644 }
7086400d
AD		 6645
6646 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6647}
6648
fd0db0ed
AD		 6649static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6650 struct ixgbe_tx_buffer *first,
244e27ad 6651 u8 *hdr_len)
897ab156 6652{
fd0db0ed 6653 struct sk_buff *skb = first->skb;
897ab156
AD		 6654 u32 vlan_macip_lens, type_tucmd;
6655 u32 mss_l4len_idx, l4len;
2049e1f6 6656 int err;
9a799d71 6657
8f4fbb9b
AD		 6658 if (skb->ip_summed != CHECKSUM_PARTIAL)
6659 return 0;
6660
897ab156
AD		 6661 if (!skb_is_gso(skb))
6662 return 0;
9a799d71 6663
2049e1f6
FR		 6664 err = skb_cow_head(skb, 0);
6665 if (err < 0)
6666 return err;
9a799d71 6667
897ab156
AD		 6668 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6669 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6670
a1108ffd 6671 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6672 struct iphdr *iph = ip_hdr(skb);
6673 iph->tot_len = 0;
6674 iph->check = 0;
6675 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6676 iph->daddr, 0,
6677 IPPROTO_TCP,
6678 0);
6679 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6680 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6681 IXGBE_TX_FLAGS_CSUM |
6682 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6683 } else if (skb_is_gso_v6(skb)) {
6684 ipv6_hdr(skb)->payload_len = 0;
6685 tcp_hdr(skb)->check =
6686 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6687 &ipv6_hdr(skb)->daddr,
6688 0, IPPROTO_TCP, 0);
244e27ad
AD		 6689 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6690 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6691 }
6692
091a6246 6693 /* compute header lengths */
897ab156
AD		 6694 l4len = tcp_hdrlen(skb);
6695 *hdr_len = skb_transport_offset(skb) + l4len;
6696
091a6246
AD		 6697 /* update gso size and bytecount with header size */
6698 first->gso_segs = skb_shinfo(skb)->gso_segs;
6699 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6700
c44f5f51 6701 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6702 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6703 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6704
6705 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6706 vlan_macip_lens = skb_network_header_len(skb);
6707 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6708 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6709
6710 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6711 mss_l4len_idx);
897ab156
AD		 6712
6713 return 1;
6714}
6715
244e27ad
AD		 6716static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6717 struct ixgbe_tx_buffer *first)
7ca647bd 6718{
fd0db0ed 6719 struct sk_buff *skb = first->skb;
897ab156
AD		 6720 u32 vlan_macip_lens = 0;
6721 u32 mss_l4len_idx = 0;
6722 u32 type_tucmd = 0;
7ca647bd 6723
897ab156 6724 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6725 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6726 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6727 return;
897ab156
AD		 6728 } else {
6729 u8 l4_hdr = 0;
244e27ad 6730 switch (first->protocol) {
a1108ffd 6731 case htons(ETH_P_IP):
897ab156
AD		 6732 vlan_macip_lens |= skb_network_header_len(skb);
6733 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6734 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6735 break;
a1108ffd 6736 case htons(ETH_P_IPV6):
897ab156
AD		 6737 vlan_macip_lens |= skb_network_header_len(skb);
6738 l4_hdr = ipv6_hdr(skb)->nexthdr;
6739 break;
6740 default:
6741 if (unlikely(net_ratelimit())) {
6742 dev_warn(tx_ring->dev,
6743 "partial checksum but proto=%x!\n",
244e27ad 6744 first->protocol);
897ab156 6745 }
7ca647bd
JP		 6746 break;
6747 }
897ab156
AD		 6748
6749 switch (l4_hdr) {
7ca647bd 6750 case IPPROTO_TCP:
897ab156
AD		 6751 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6752 mss_l4len_idx = tcp_hdrlen(skb) <<
6753 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6754 break;
6755 case IPPROTO_SCTP:
897ab156
AD		 6756 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6757 mss_l4len_idx = sizeof(struct sctphdr) <<
6758 IXGBE_ADVTXD_L4LEN_SHIFT;
6759 break;
6760 case IPPROTO_UDP:
6761 mss_l4len_idx = sizeof(struct udphdr) <<
6762 IXGBE_ADVTXD_L4LEN_SHIFT;
6763 break;
6764 default:
6765 if (unlikely(net_ratelimit())) {
6766 dev_warn(tx_ring->dev,
6767 "partial checksum but l4 proto=%x!\n",
244e27ad 6768 l4_hdr);
897ab156 6769 }
7ca647bd
JP		 6770 break;
6771 }
244e27ad
AD		 6772
6773 /* update TX checksum flag */
6774 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6775 }
6776
244e27ad 6777 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6778 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6779 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6780
897ab156
AD		 6781 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6782 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6783}
6784
472148c3
AD		 6785#define IXGBE_SET_FLAG(_input, _flag, _result) \
6786 ((_flag <= _result) ? \
6787 ((u32)(_input & _flag) * (_result / _flag)) : \
6788 ((u32)(_input & _flag) / (_flag / _result)))
6789
6790static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6791{
d3d00239 6792 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6793 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6794 IXGBE_ADVTXD_DCMD_DEXT |
6795 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6796
d3d00239 6797 /* set HW vlan bit if vlan is present */
472148c3
AD		 6798 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6799 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6800
d3d00239 6801 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6802 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6803 IXGBE_ADVTXD_DCMD_TSE);
6804
6805 /* set timestamp bit if present */
6806 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6807 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6808
62748b7b 6809 /* insert frame checksum */
472148c3 6810 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6811
d3d00239
AD		 6812 return cmd_type;
6813}
9a799d71 6814
729739b7
AD		 6815static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6816 u32 tx_flags, unsigned int paylen)
d3d00239 6817{
472148c3 6818 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6819
d3d00239 6820 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6821 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6822 IXGBE_TX_FLAGS_CSUM,
6823 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6824
93f5b3c1 6825 /* enble IPv4 checksum for TSO */
472148c3
AD		 6826 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6827 IXGBE_TX_FLAGS_IPV4,
6828 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6829
7f9643fd
AD		 6830 /*
6831 * Check Context must be set if Tx switch is enabled, which it
6832 * always is for case where virtual functions are running
6833 */
472148c3
AD		 6834 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6835 IXGBE_TX_FLAGS_CC,
6836 IXGBE_ADVTXD_CC);
7f9643fd 6837
472148c3 6838 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6839}
44df32c5 6840
d3d00239
AD		 6841#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6842 IXGBE_TXD_CMD_RS)
6843
6844static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6845 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6846 const u8 hdr_len)
6847{
fd0db0ed 6848 struct sk_buff *skb = first->skb;
729739b7 6849 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6850 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6851 struct skb_frag_struct *frag;
6852 dma_addr_t dma;
6853 unsigned int data_len, size;
244e27ad 6854 u32 tx_flags = first->tx_flags;
472148c3 6855 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6856 u16 i = tx_ring->next_to_use;
d3d00239 6857
729739b7
AD		 6858 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6859
ec718254
AD		 6860 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6861
6862 size = skb_headlen(skb);
6863 data_len = skb->data_len;
729739b7 6864
d3d00239
AD		 6865#ifdef IXGBE_FCOE
6866 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6867 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6868 size -= sizeof(struct fcoe_crc_eof) - data_len;
6869 data_len = 0;
729739b7
AD		 6870 } else {
6871 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6872 }
6873 }
44df32c5 6874
d3d00239 6875#endif
729739b7 6876 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6877
ec718254 6878 tx_buffer = first;
9a799d71 6879
ec718254
AD		 6880 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6881 if (dma_mapping_error(tx_ring->dev, dma))
6882 goto dma_error;
6883
6884 /* record length, and DMA address */
6885 dma_unmap_len_set(tx_buffer, len, size);
6886 dma_unmap_addr_set(tx_buffer, dma, dma);
6887
6888 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6889
729739b7 6890 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6891 tx_desc->read.cmd_type_len =
472148c3 6892 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6893
d3d00239 6894 i++;
729739b7 6895 tx_desc++;
d3d00239 6896 if (i == tx_ring->count) {
e4f74028 6897 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6898 i = 0;
6899 }
ec718254 6900 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6901
6902 dma += IXGBE_MAX_DATA_PER_TXD;
6903 size -= IXGBE_MAX_DATA_PER_TXD;
6904
6905 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6906 }
e5a43549 6907
729739b7
AD		 6908 if (likely(!data_len))
6909 break;
9a799d71 6910
472148c3 6911 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6912
729739b7
AD		 6913 i++;
6914 tx_desc++;
6915 if (i == tx_ring->count) {
6916 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6917 i = 0;
6918 }
ec718254 6919 tx_desc->read.olinfo_status = 0;
9a799d71 6920
d3d00239 6921#ifdef IXGBE_FCOE
9e903e08 6922 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6923#else
9e903e08 6924 size = skb_frag_size(frag);
d3d00239
AD		 6925#endif
6926 data_len -= size;
9a799d71 6927
729739b7
AD		 6928 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6929 DMA_TO_DEVICE);
9a799d71 6930
729739b7 6931 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6932 }
9a799d71 6933
729739b7 6934 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6935 cmd_type |= size | IXGBE_TXD_CMD;
6936 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6937
091a6246 6938 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6939
d3d00239
AD		 6940 /* set the timestamp */
6941 first->time_stamp = jiffies;
9a799d71
AK		 6942
6943 /*
729739b7
AD		 6944 * Force memory writes to complete before letting h/w know there
6945 * are new descriptors to fetch. (Only applicable for weak-ordered
6946 * memory model archs, such as IA-64).
6947 *
6948 * We also need this memory barrier to make certain all of the
6949 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6950 */
6951 wmb();
6952
d3d00239
AD		 6953 /* set next_to_watch value indicating a packet is present */
6954 first->next_to_watch = tx_desc;
6955
729739b7
AD		 6956 i++;
6957 if (i == tx_ring->count)
6958 i = 0;
6959
6960 tx_ring->next_to_use = i;
6961
d3d00239 6962 /* notify HW of packet */
84227bcd 6963 ixgbe_write_tail(tx_ring, i);
d3d00239
AD		 6964
6965 return;
6966dma_error:
729739b7 6967 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6968
6969 /* clear dma mappings for failed tx_buffer_info map */
6970 for (;;) {
729739b7
AD		 6971 tx_buffer = &tx_ring->tx_buffer_info[i];
6972 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6973 if (tx_buffer == first)
d3d00239
AD		 6974 break;
6975 if (i == 0)
6976 i = tx_ring->count;
6977 i--;
6978 }
6979
d3d00239 6980 tx_ring->next_to_use = i;
9a799d71
AK		 6981}
6982
fd0db0ed 6983static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6984 struct ixgbe_tx_buffer *first)
69830529
AD		 6985{
6986 struct ixgbe_q_vector *q_vector = ring->q_vector;
6987 union ixgbe_atr_hash_dword input = { .dword = 0 };
6988 union ixgbe_atr_hash_dword common = { .dword = 0 };
6989 union {
6990 unsigned char *network;
6991 struct iphdr *ipv4;
6992 struct ipv6hdr *ipv6;
6993 } hdr;
ee9e0f0b 6994 struct tcphdr *th;
905e4a41 6995 __be16 vlan_id;
c4cf55e5 6996
69830529
AD		 6997 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6998 if (!q_vector)
6999 return;
7000
7001 /* do nothing if sampling is disabled */
7002 if (!ring->atr_sample_rate)
d3ead241 7003 return;
c4cf55e5 7004
69830529 7005 ring->atr_count++;
c4cf55e5 7006
69830529 7007 /* snag network header to get L4 type and address */
fd0db0ed 7008 hdr.network = skb_network_header(first->skb);
69830529
AD		 7009
7010 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 7011 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 7012 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 7013 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 7014 hdr.ipv4->protocol != IPPROTO_TCP))
7015 return;
ee9e0f0b 7016
fd0db0ed 7017 th = tcp_hdr(first->skb);
c4cf55e5 7018
66f32a8b
AD		 7019 /* skip this packet since it is invalid or the socket is closing */
7020 if (!th || th->fin)
69830529
AD		 7021 return;
7022
7023 /* sample on all syn packets or once every atr sample count */
7024 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7025 return;
7026
7027 /* reset sample count */
7028 ring->atr_count = 0;
7029
244e27ad 7030 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7031
7032 /*
7033 * src and dst are inverted, think how the receiver sees them
7034 *
7035 * The input is broken into two sections, a non-compressed section
7036 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7037 * is XORed together and stored in the compressed dword.
7038 */
7039 input.formatted.vlan_id = vlan_id;
7040
7041 /*
7042 * since src port and flex bytes occupy the same word XOR them together
7043 * and write the value to source port portion of compressed dword
7044 */
244e27ad 7045 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7046 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7047 else
244e27ad 7048 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7049 common.port.dst ^= th->source;
7050
a1108ffd 7051 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7052 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7053 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7054 } else {
7055 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7056 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7057 hdr.ipv6->saddr.s6_addr32[1] ^
7058 hdr.ipv6->saddr.s6_addr32[2] ^
7059 hdr.ipv6->saddr.s6_addr32[3] ^
7060 hdr.ipv6->daddr.s6_addr32[0] ^
7061 hdr.ipv6->daddr.s6_addr32[1] ^
7062 hdr.ipv6->daddr.s6_addr32[2] ^
7063 hdr.ipv6->daddr.s6_addr32[3];
7064 }
c4cf55e5
PWJ		 7065
7066 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7067 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7068 input, common, ring->queue_index);
c4cf55e5
PWJ		 7069}
7070
63544e9c 7071static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 7072{
fc77dc3c 7073 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 7074 /* Herbert's original patch had:
7075 * smp_mb__after_netif_stop_queue();
7076 * but since that doesn't exist yet, just open code it. */
7077 smp_mb();
7078
7079 /* We need to check again in a case another CPU has just
7080 * made room available. */
7d4987de 7081 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 7082 return -EBUSY;
7083
7084 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 7085 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 7086 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 7087 return 0;
7088}
7089
82d4e46e 7090static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 7091{
7d4987de 7092 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 7093 return 0;
fc77dc3c 7094 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 7095}
7096
f663dd9a 7097static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7098 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7099{
f663dd9a
JW		 7100 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7101#ifdef IXGBE_FCOE
97488bd1
AD		 7102 struct ixgbe_adapter *adapter;
7103 struct ixgbe_ring_feature *f;
7104 int txq;
f663dd9a
JW		 7105#endif
7106
7107 if (fwd_adapter)
7108 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7109
7110#ifdef IXGBE_FCOE
5e09a105 7111
97488bd1
AD		 7112 /*
7113 * only execute the code below if protocol is FCoE
7114 * or FIP and we have FCoE enabled on the adapter
7115 */
7116 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7117 case htons(ETH_P_FCOE):
7118 case htons(ETH_P_FIP):
97488bd1 7119 adapter = netdev_priv(dev);
c087663e 7120
97488bd1
AD		 7121 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7122 break;
7123 default:
99932d4f 7124 return fallback(dev, skb);
97488bd1 7125 }
c087663e 7126
97488bd1 7127 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7128
97488bd1
AD		 7129 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7130 smp_processor_id();
56075a98 7131
97488bd1
AD		 7132 while (txq >= f->indices)
7133 txq -= f->indices;
c4cf55e5 7134
97488bd1 7135 return txq + f->offset;
f663dd9a 7136#else
99932d4f 7137 return fallback(dev, skb);
f663dd9a 7138#endif
09a3b1f8
SH		 7139}
7140
fc77dc3c 7141netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7142 struct ixgbe_adapter *adapter,
7143 struct ixgbe_ring *tx_ring)
9a799d71 7144{
d3d00239 7145 struct ixgbe_tx_buffer *first;
5f715823 7146 int tso;
d3d00239 7147 u32 tx_flags = 0;
a535c30e 7148 unsigned short f;
a535c30e 7149 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7150 __be16 protocol = skb->protocol;
63544e9c 7151 u8 hdr_len = 0;
5e09a105 7152
a535c30e
AD		 7153 /*
7154 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7155 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7156 * + 2 desc gap to keep tail from touching head,
7157 * + 1 desc for context descriptor,
7158 * otherwise try next time
7159 */
a535c30e
AD		 7160 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7161 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7162
a535c30e
AD		 7163 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7164 tx_ring->tx_stats.tx_busy++;
7165 return NETDEV_TX_BUSY;
7166 }
7167
fd0db0ed
AD		 7168 /* record the location of the first descriptor for this packet */
7169 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7170 first->skb = skb;
091a6246
AD		 7171 first->bytecount = skb->len;
7172 first->gso_segs = 1;
fd0db0ed 7173
66f32a8b 7174 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7175 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7176 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7177 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7178 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7179 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7180 struct vlan_hdr *vhdr, _vhdr;
7181 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7182 if (!vhdr)
7183 goto out_drop;
7184
7185 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7186 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7187 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7188 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7189 }
7190
151b260c
JK		 7191 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
7192 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7193 &adapter->state))) {
3a6a4eda
JK		 7194 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7195 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7196
7197 /* schedule check for Tx timestamp */
7198 adapter->ptp_tx_skb = skb_get(skb);
7199 adapter->ptp_tx_start = jiffies;
7200 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7201 }
3a6a4eda 7202
ff29a86e
JK		 7203 skb_tx_timestamp(skb);
7204
9e0c5648
AD		 7205#ifdef CONFIG_PCI_IOV
7206 /*
7207 * Use the l2switch_enable flag - would be false if the DMA
7208 * Tx switch had been disabled.
7209 */
7210 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7211 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7212
7213#endif
32701dc2 7214 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7215 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7216 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7217 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7218 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7219 tx_flags |= (skb->priority & 0x7) <<
7220 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7221 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7222 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7223
7224 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7225 goto out_drop;
7226 vhdr = (struct vlan_ethhdr *)skb->data;
7227 vhdr->h_vlan_TCI = htons(tx_flags >>
7228 IXGBE_TX_FLAGS_VLAN_SHIFT);
7229 } else {
7230 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7231 }
9a799d71 7232 }
eacd73f7 7233
244e27ad
AD		 7234 /* record initial flags and protocol */
7235 first->tx_flags = tx_flags;
7236 first->protocol = protocol;
7237
eacd73f7 7238#ifdef IXGBE_FCOE
66f32a8b 7239 /* setup tx offload for FCoE */
a1108ffd 7240 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7241 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7242 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7243 if (tso < 0)
7244 goto out_drop;
9a799d71 7245
66f32a8b 7246 goto xmit_fcoe;
eacd73f7 7247 }
9a799d71 7248
66f32a8b 7249#endif /* IXGBE_FCOE */
244e27ad 7250 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7251 if (tso < 0)
897ab156 7252 goto out_drop;
244e27ad
AD		 7253 else if (!tso)
7254 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7255
7256 /* add the ATR filter if ATR is on */
7257 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7258 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7259
7260#ifdef IXGBE_FCOE
7261xmit_fcoe:
7262#endif /* IXGBE_FCOE */
244e27ad 7263 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 7264
7265 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7266
7267 return NETDEV_TX_OK;
897ab156
AD		 7268
7269out_drop:
fd0db0ed
AD		 7270 dev_kfree_skb_any(first->skb);
7271 first->skb = NULL;
7272
897ab156 7273 return NETDEV_TX_OK;
9a799d71
AK		 7274}
7275
2a47fa45
JF		 7276static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7277 struct net_device *netdev,
7278 struct ixgbe_ring *ring)
84418e3b
AD		 7279{
7280 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7281 struct ixgbe_ring *tx_ring;
7282
a50c29dd
AD		 7283 /*
7284 * The minimum packet size for olinfo paylen is 17 so pad the skb
7285 * in order to meet this minimum size requirement.
7286 */
f73332fc
SH		 7287 if (unlikely(skb->len < 17)) {
7288 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7289 return NETDEV_TX_OK;
7290 skb->len = 17;
71a49f77 7291 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7292 }
7293
2a47fa45
JF		 7294 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7295
fc77dc3c 7296 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7297}
7298
2a47fa45
JF		 7299static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7300 struct net_device *netdev)
7301{
7302 return __ixgbe_xmit_frame(skb, netdev, NULL);
7303}
7304
9a799d71
AK		 7305/**
7306 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7307 * @netdev: network interface device structure
7308 * @p: pointer to an address structure
7309 *
7310 * Returns 0 on success, negative on failure
7311 **/
7312static int ixgbe_set_mac(struct net_device *netdev, void *p)
7313{
7314 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7315 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7316 struct sockaddr *addr = p;
5d7daa35 7317 int ret;
9a799d71
AK		 7318
7319 if (!is_valid_ether_addr(addr->sa_data))
7320 return -EADDRNOTAVAIL;
7321
5d7daa35 7322 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7323 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7324 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7325
5d7daa35
JK		 7326 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7327 return ret > 0 ? 0 : ret;
9a799d71
AK		 7328}
7329
6b73e10d
BH		 7330static int
7331ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7332{
7333 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7334 struct ixgbe_hw *hw = &adapter->hw;
7335 u16 value;
7336 int rc;
7337
7338 if (prtad != hw->phy.mdio.prtad)
7339 return -EINVAL;
7340 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7341 if (!rc)
7342 rc = value;
7343 return rc;
7344}
7345
7346static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7347 u16 addr, u16 value)
7348{
7349 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7350 struct ixgbe_hw *hw = &adapter->hw;
7351
7352 if (prtad != hw->phy.mdio.prtad)
7353 return -EINVAL;
7354 return hw->phy.ops.write_reg(hw, addr, devad, value);
7355}
7356
7357static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7358{
7359 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7360
3a6a4eda 7361 switch (cmd) {
3a6a4eda 7362 case SIOCSHWTSTAMP:
93501d48
JK		 7363 return ixgbe_ptp_set_ts_config(adapter, req);
7364 case SIOCGHWTSTAMP:
7365 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7366 default:
7367 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7368 }
6b73e10d
BH		 7369}
7370
0365e6e4
PW		 7371/**
7372 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7373 * netdev->dev_addrs
0365e6e4
PW		 7374 * @netdev: network interface device structure
7375 *
7376 * Returns non-zero on failure
7377 **/
7378static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7379{
7380 int err = 0;
7381 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7382 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7383
7fa7c9dc 7384 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7385 rtnl_lock();
7fa7c9dc 7386 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7387 rtnl_unlock();
7fa7c9dc
AD		 7388
7389 /* update SAN MAC vmdq pool selection */
7390 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7391 }
7392 return err;
7393}
7394
7395/**
7396 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7397 * netdev->dev_addrs
0365e6e4
PW		 7398 * @netdev: network interface device structure
7399 *
7400 * Returns non-zero on failure
7401 **/
7402static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7403{
7404 int err = 0;
7405 struct ixgbe_adapter *adapter = netdev_priv(dev);
7406 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7407
7408 if (is_valid_ether_addr(mac->san_addr)) {
7409 rtnl_lock();
7410 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7411 rtnl_unlock();
7412 }
7413 return err;
7414}
7415
9a799d71
AK		 7416#ifdef CONFIG_NET_POLL_CONTROLLER
7417/*
7418 * Polling 'interrupt' - used by things like netconsole to send skbs
7419 * without having to re-enable interrupts. It's not called while
7420 * the interrupt routine is executing.
7421 */
7422static void ixgbe_netpoll(struct net_device *netdev)
7423{
7424 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7425 int i;
9a799d71 7426
1a647bd2
AD		 7427 /* if interface is down do nothing */
7428 if (test_bit(__IXGBE_DOWN, &adapter->state))
7429 return;
7430
9a799d71 7431 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7432 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7433 for (i = 0; i < adapter->num_q_vectors; i++)
7434 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7435 } else {
7436 ixgbe_intr(adapter->pdev->irq, netdev);
7437 }
9a799d71 7438 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7439}
9a799d71 7440
581330ba 7441#endif
de1036b1
ED		 7442static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7443 struct rtnl_link_stats64 *stats)
7444{
7445 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7446 int i;
7447
1a51502b 7448 rcu_read_lock();
de1036b1 7449 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7450 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7451 u64 bytes, packets;
7452 unsigned int start;
7453
1a51502b
ED		 7454 if (ring) {
7455 do {
57a7744e 7456 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7457 packets = ring->stats.packets;
7458 bytes = ring->stats.bytes;
57a7744e 7459 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7460 stats->rx_packets += packets;
7461 stats->rx_bytes += bytes;
7462 }
de1036b1 7463 }
1ac9ad13
ED		 7464
7465 for (i = 0; i < adapter->num_tx_queues; i++) {
7466 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7467 u64 bytes, packets;
7468 unsigned int start;
7469
7470 if (ring) {
7471 do {
57a7744e 7472 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7473 packets = ring->stats.packets;
7474 bytes = ring->stats.bytes;
57a7744e 7475 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7476 stats->tx_packets += packets;
7477 stats->tx_bytes += bytes;
7478 }
7479 }
1a51502b 7480 rcu_read_unlock();
de1036b1
ED		 7481 /* following stats updated by ixgbe_watchdog_task() */
7482 stats->multicast = netdev->stats.multicast;
7483 stats->rx_errors = netdev->stats.rx_errors;
7484 stats->rx_length_errors = netdev->stats.rx_length_errors;
7485 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7486 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7487 return stats;
7488}
7489
8af3c33f 7490#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7491/**
7492 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7493 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7494 * @tc: number of traffic classes currently enabled
7495 *
7496 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7497 * 802.1Q priority maps to a packet buffer that exists.
7498 */
7499static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7500{
7501 struct ixgbe_hw *hw = &adapter->hw;
7502 u32 reg, rsave;
7503 int i;
7504
7505 /* 82598 have a static priority to TC mapping that can not
7506 * be changed so no validation is needed.
7507 */
7508 if (hw->mac.type == ixgbe_mac_82598EB)
7509 return;
7510
7511 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7512 rsave = reg;
7513
7514 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7515 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7516
7517 /* If up2tc is out of bounds default to zero */
7518 if (up2tc > tc)
7519 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7520 }
7521
7522 if (reg != rsave)
7523 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7524
7525 return;
7526}
7527
02debdc9
AD		 7528/**
7529 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7530 * @adapter: Pointer to adapter struct
7531 *
7532 * Populate the netdev user priority to tc map
7533 */
7534static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7535{
7536 struct net_device *dev = adapter->netdev;
7537 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7538 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7539 u8 prio;
7540
7541 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7542 u8 tc = 0;
7543
7544 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7545 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7546 else if (ets)
7547 tc = ets->prio_tc[prio];
7548
7549 netdev_set_prio_tc_map(dev, prio, tc);
7550 }
7551}
7552
cca73c59 7553#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7554/**
7555 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7556 *
7557 * @netdev: net device to configure
7558 * @tc: number of traffic classes to enable
7559 */
7560int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7561{
8b1c0b24
JF		 7562 struct ixgbe_adapter *adapter = netdev_priv(dev);
7563 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7564 bool pools;
8b1c0b24 7565
8b1c0b24 7566 /* Hardware supports up to 8 traffic classes */
4de2a022 7567 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7568 (hw->mac.type == ixgbe_mac_82598EB &&
7569 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7570 return -EINVAL;
7571
2a47fa45
JF		 7572 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7573 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7574 return -EBUSY;
7575
8b1c0b24 7576 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7577 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7578 * hardware is not flexible enough to do this dynamically.
7579 */
7580 if (netif_running(dev))
7581 ixgbe_close(dev);
7582 ixgbe_clear_interrupt_scheme(adapter);
7583
cca73c59 7584#ifdef CONFIG_IXGBE_DCB
e7589eab 7585 if (tc) {
8b1c0b24 7586 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7587 ixgbe_set_prio_tc_map(adapter);
7588
e7589eab 7589 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7590
943561d3
AD		 7591 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7592 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7593 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7594 }
e7589eab 7595 } else {
8b1c0b24 7596 netdev_reset_tc(dev);
02debdc9 7597
943561d3
AD		 7598 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7599 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7600
7601 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7602
7603 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7604 adapter->dcb_cfg.pfc_mode_enable = false;
7605 }
7606
8b1c0b24 7607 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7608
7609#endif /* CONFIG_IXGBE_DCB */
7610 ixgbe_init_interrupt_scheme(adapter);
7611
8b1c0b24 7612 if (netif_running(dev))
cca73c59 7613 return ixgbe_open(dev);
8b1c0b24
JF		 7614
7615 return 0;
7616}
de1036b1 7617
da36b647
GR		 7618#ifdef CONFIG_PCI_IOV
7619void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7620{
7621 struct net_device *netdev = adapter->netdev;
7622
7623 rtnl_lock();
da36b647 7624 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7625 rtnl_unlock();
7626}
7627
7628#endif
082757af
DS		 7629void ixgbe_do_reset(struct net_device *netdev)
7630{
7631 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7632
7633 if (netif_running(netdev))
7634 ixgbe_reinit_locked(adapter);
7635 else
7636 ixgbe_reset(adapter);
7637}
7638
c8f44aff 7639static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7640 netdev_features_t features)
082757af
DS		 7641{
7642 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7643
082757af 7644 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7645 if (!(features & NETIF_F_RXCSUM))
7646 features &= ~NETIF_F_LRO;
082757af 7647
567d2de2
AD		 7648 /* Turn off LRO if not RSC capable */
7649 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7650 features &= ~NETIF_F_LRO;
8e2813f5 7651
567d2de2 7652 return features;
082757af
DS		 7653}
7654
c8f44aff 7655static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7656 netdev_features_t features)
082757af
DS		 7657{
7658 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7659 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7660 bool need_reset = false;
7661
082757af 7662 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7663 if (!(features & NETIF_F_LRO)) {
7664 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7665 need_reset = true;
567d2de2
AD		 7666 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7667 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7668 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7669 if (adapter->rx_itr_setting == 1 ||
7670 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7671 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7672 need_reset = true;
7673 } else if ((changed ^ features) & NETIF_F_LRO) {
7674 e_info(probe, "rx-usecs set too low, "
7675 "disabling RSC\n");
082757af
DS		 7676 }
7677 }
7678
7679 /*
7680 * Check if Flow Director n-tuple support was enabled or disabled. If
7681 * the state changed, we need to reset.
7682 */
39cb681b
AD		 7683 switch (features & NETIF_F_NTUPLE) {
7684 case NETIF_F_NTUPLE:
567d2de2 7685 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7686 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7687 need_reset = true;
7688
567d2de2
AD		 7689 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7690 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7691 break;
7692 default:
7693 /* turn off perfect filters, enable ATR and reset */
7694 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7695 need_reset = true;
7696
7697 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7698
7699 /* We cannot enable ATR if SR-IOV is enabled */
7700 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7701 break;
7702
7703 /* We cannot enable ATR if we have 2 or more traffic classes */
7704 if (netdev_get_num_tc(netdev) > 1)
7705 break;
7706
7707 /* We cannot enable ATR if RSS is disabled */
7708 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7709 break;
7710
7711 /* A sample rate of 0 indicates ATR disabled */
7712 if (!adapter->atr_sample_rate)
7713 break;
7714
7715 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7716 break;
082757af
DS		 7717 }
7718
f646968f 7719 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7720 ixgbe_vlan_strip_enable(adapter);
7721 else
7722 ixgbe_vlan_strip_disable(adapter);
7723
3f2d1c0f
BG		 7724 if (changed & NETIF_F_RXALL)
7725 need_reset = true;
7726
567d2de2 7727 netdev->features = features;
082757af
DS		 7728 if (need_reset)
7729 ixgbe_do_reset(netdev);
7730
7731 return 0;
082757af
DS		 7732}
7733
edc7d573 7734static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7735 struct net_device *dev,
6b6e2725 7736 const unsigned char *addr,
0f4b0add
JF		 7737 u16 flags)
7738{
7739 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7740 int err;
7741
7742 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7743 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7744
b1ac1ef7
JF		 7745 /* Hardware does not support aging addresses so if a
7746 * ndm_state is given only allow permanent addresses
7747 */
7748 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7749 pr_info("%s: FDB only supports static addresses\n",
7750 ixgbe_driver_name);
7751 return -EINVAL;
7752 }
7753
46acc460 7754 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7755 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7756
7757 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7758 err = dev_uc_add_excl(dev, addr);
0f4b0add 7759 else
95447461
JF		 7760 err = -ENOMEM;
7761 } else if (is_multicast_ether_addr(addr)) {
7762 err = dev_mc_add_excl(dev, addr);
7763 } else {
7764 err = -EINVAL;
0f4b0add
JF		 7765 }
7766
7767 /* Only return duplicate errors if NLM_F_EXCL is set */
7768 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7769 err = 0;
7770
7771 return err;
7772}
7773
815cccbf
JF		 7774static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7775 struct nlmsghdr *nlh)
7776{
7777 struct ixgbe_adapter *adapter = netdev_priv(dev);
7778 struct nlattr *attr, *br_spec;
7779 int rem;
7780
7781 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7782 return -EOPNOTSUPP;
7783
7784 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7785
7786 nla_for_each_nested(attr, br_spec, rem) {
7787 __u16 mode;
7788 u32 reg = 0;
7789
7790 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7791 continue;
7792
7793 mode = nla_get_u16(attr);
9b735984 7794 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7795 reg = 0;
9b735984
GR		 7796 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7797 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7798 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7799 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7800 } else
815cccbf
JF		 7801 return -EINVAL;
7802
7803 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7804
7805 e_info(drv, "enabling bridge mode: %s\n",
7806 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7807 }
7808
7809 return 0;
7810}
7811
7812static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7813 struct net_device *dev,
7814 u32 filter_mask)
815cccbf
JF		 7815{
7816 struct ixgbe_adapter *adapter = netdev_priv(dev);
7817 u16 mode;
7818
7819 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7820 return 0;
7821
9b735984 7822 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7823 mode = BRIDGE_MODE_VEB;
7824 else
7825 mode = BRIDGE_MODE_VEPA;
7826
7827 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7828}
7829
2a47fa45
JF		 7830static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7831{
7832 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7833 struct ixgbe_adapter *adapter = netdev_priv(pdev);
51f3773b 7834 unsigned int limit;
2a47fa45
JF		 7835 int pool, err;
7836
219354d4
JF		 7837#ifdef CONFIG_RPS
7838 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7839 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7840 vdev->name);
7841 return ERR_PTR(-EINVAL);
7842 }
7843#endif
2a47fa45 7844 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7845 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7846 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7847 netdev_info(pdev,
7848 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7849 pdev->name);
7850 return ERR_PTR(-EINVAL);
7851 }
7852
7853 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7854 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7855 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7856 return ERR_PTR(-EBUSY);
7857
7858 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7859 if (!fwd_adapter)
7860 return ERR_PTR(-ENOMEM);
7861
7862 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7863 adapter->num_rx_pools++;
7864 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7865 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7866
7867 /* Enable VMDq flag so device will be set in VM mode */
7868 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7869 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7870 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7871
7872 /* Force reinit of ring allocation with VMDQ enabled */
7873 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7874 if (err)
7875 goto fwd_add_err;
7876 fwd_adapter->pool = pool;
7877 fwd_adapter->real_adapter = adapter;
7878 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7879 if (err)
7880 goto fwd_add_err;
7881 netif_tx_start_all_queues(vdev);
7882 return fwd_adapter;
7883fwd_add_err:
7884 /* unwind counter and free adapter struct */
7885 netdev_info(pdev,
7886 "%s: dfwd hardware acceleration failed\n", vdev->name);
7887 clear_bit(pool, &adapter->fwd_bitmask);
7888 adapter->num_rx_pools--;
7889 kfree(fwd_adapter);
7890 return ERR_PTR(err);
7891}
7892
7893static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7894{
7895 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7896 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7897 unsigned int limit;
2a47fa45
JF		 7898
7899 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7900 adapter->num_rx_pools--;
7901
51f3773b
JF		 7902 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7903 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7904 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7905 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7906 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7907 fwd_adapter->pool, adapter->num_rx_pools,
7908 fwd_adapter->rx_base_queue,
7909 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7910 adapter->fwd_bitmask);
7911 kfree(fwd_adapter);
7912}
7913
0edc3527 7914static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7915 .ndo_open = ixgbe_open,
0edc3527 7916 .ndo_stop = ixgbe_close,
00829823 7917 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7918 .ndo_select_queue = ixgbe_select_queue,
581330ba 7919 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7920 .ndo_validate_addr = eth_validate_addr,
7921 .ndo_set_mac_address = ixgbe_set_mac,
7922 .ndo_change_mtu = ixgbe_change_mtu,
7923 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7924 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7925 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7926 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7927 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7928 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7929 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7930 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7931 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7932 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7933#ifdef CONFIG_IXGBE_DCB
24095aa3 7934 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7935#endif
0edc3527
SH		 7936#ifdef CONFIG_NET_POLL_CONTROLLER
7937 .ndo_poll_controller = ixgbe_netpoll,
7938#endif
e0d1095a 7939#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7940 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7941#endif
332d4a7d
YZ		 7942#ifdef IXGBE_FCOE
7943 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7944 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7945 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7946 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7947 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7948 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7949 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7950#endif /* IXGBE_FCOE */
082757af
DS		 7951 .ndo_set_features = ixgbe_set_features,
7952 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7953 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7954 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7955 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7956 .ndo_dfwd_add_station = ixgbe_fwd_add,
7957 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7958};
7959
e027d1ae
JK		 7960/**
7961 * ixgbe_enumerate_functions - Get the number of ports this device has
7962 * @adapter: adapter structure
7963 *
7964 * This function enumerates the phsyical functions co-located on a single slot,
7965 * in order to determine how many ports a device has. This is most useful in
7966 * determining the required GT/s of PCIe bandwidth necessary for optimal
7967 * performance.
7968 **/
7969static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7970{
e027d1ae
JK		 7971 struct list_head *entry;
7972 int physfns = 0;
7973
f1f96579
JK		 7974 /* Some cards can not use the generic count PCIe functions method,
7975 * because they are behind a parent switch, so we hardcode these with
7976 * the correct number of functions.
e027d1ae 7977 */
f1f96579 7978 if (ixgbe_pcie_from_parent(&adapter->hw)) {
e027d1ae 7979 physfns = 4;
f1f96579 7980 } else {
e027d1ae
JK		 7981 list_for_each(entry, &adapter->pdev->bus_list) {
7982 struct pci_dev *pdev =
7983 list_entry(entry, struct pci_dev, bus_list);
7984 /* don't count virtual functions */
7985 if (!pdev->is_virtfn)
7986 physfns++;
7987 }
7988 }
7989
7990 return physfns;
7991}
7992
8e2813f5
JK		 7993/**
7994 * ixgbe_wol_supported - Check whether device supports WoL
7995 * @hw: hw specific details
7996 * @device_id: the device ID
7997 * @subdev_id: the subsystem device ID
7998 *
7999 * This function is used by probe and ethtool to determine
8000 * which devices have WoL support
8001 *
8002 **/
8003int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8004 u16 subdevice_id)
8005{
8006 struct ixgbe_hw *hw = &adapter->hw;
8007 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8008 int is_wol_supported = 0;
8009
8010 switch (device_id) {
8011 case IXGBE_DEV_ID_82599_SFP:
8012 /* Only these subdevices could supports WOL */
8013 switch (subdevice_id) {
87557440 8014 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8015 case IXGBE_SUBDEV_ID_82599_560FLR:
8016 /* only support first port */
8017 if (hw->bus.func != 0)
8018 break;
5700ff26 8019 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8020 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8021 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8022 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8023 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8024 is_wol_supported = 1;
8025 break;
8026 }
8027 break;
5daebbb0
DS		 8028 case IXGBE_DEV_ID_82599EN_SFP:
8029 /* Only this subdevice supports WOL */
8030 switch (subdevice_id) {
8031 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8032 is_wol_supported = 1;
8033 break;
8034 }
8035 break;
8e2813f5
JK		 8036 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8037 /* All except this subdevice support WOL */
8038 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8039 is_wol_supported = 1;
8040 break;
8041 case IXGBE_DEV_ID_82599_KX4:
8042 is_wol_supported = 1;
8043 break;
8044 case IXGBE_DEV_ID_X540T:
df376f0d 8045 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 8046 /* check eeprom to see if enabled wol */
8047 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8048 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8049 (hw->bus.func == 0))) {
8050 is_wol_supported = 1;
8051 }
8052 break;
8053 }
8054
8055 return is_wol_supported;
8056}
8057
9a799d71
AK		 8058/**
8059 * ixgbe_probe - Device Initialization Routine
8060 * @pdev: PCI device information struct
8061 * @ent: entry in ixgbe_pci_tbl
8062 *
8063 * Returns 0 on success, negative on failure
8064 *
8065 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8066 * The OS initialization, configuring of the adapter private structure,
8067 * and a hardware reset occur.
8068 **/
1dd06ae8 8069static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8070{
8071 struct net_device *netdev;
8072 struct ixgbe_adapter *adapter = NULL;
8073 struct ixgbe_hw *hw;
8074 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 8075 static int cards_found;
e027d1ae 8076 int i, err, pci_using_dac, expected_gts;
d3cb9869 8077 unsigned int indices = MAX_TX_QUEUES;
289700db 8078 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 8079#ifdef IXGBE_FCOE
8080 u16 device_caps;
8081#endif
289700db 8082 u32 eec;
9a799d71 8083
bded64a7
AG		 8084 /* Catch broken hardware that put the wrong VF device ID in
8085 * the PCIe SR-IOV capability.
8086 */
8087 if (pdev->is_virtfn) {
8088 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8089 pci_name(pdev), pdev->vendor, pdev->device);
8090 return -EINVAL;
8091 }
8092
9ce77666 8093 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8094 if (err)
8095 return err;
8096
f5f2eda8 8097 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8098 pci_using_dac = 1;
8099 } else {
f5f2eda8 8100 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8101 if (err) {
f5f2eda8
RK		 8102 dev_err(&pdev->dev,
8103 "No usable DMA configuration, aborting\n");
8104 goto err_dma;
9a799d71
AK		 8105 }
8106 pci_using_dac = 0;
8107 }
8108
9ce77666 8109 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8110 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8111 if (err) {
b8bc0421
DC		 8112 dev_err(&pdev->dev,
8113 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8114 goto err_pci_reg;
8115 }
8116
19d5afd4 8117 pci_enable_pcie_error_reporting(pdev);
6fabd715 8118
9a799d71 8119 pci_set_master(pdev);
fb3b27bc 8120 pci_save_state(pdev);
9a799d71 8121
d3cb9869 8122 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8123#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8124 /* 8 TC w/ 4 queues per TC */
8125 indices = 4 * MAX_TRAFFIC_CLASS;
8126#else
8127 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8128#endif
d3cb9869 8129 }
e901acd6 8130
c85a2618 8131 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8132 if (!netdev) {
8133 err = -ENOMEM;
8134 goto err_alloc_etherdev;
8135 }
8136
9a799d71
AK		 8137 SET_NETDEV_DEV(netdev, &pdev->dev);
8138
9a799d71 8139 adapter = netdev_priv(netdev);
c60fbb00 8140 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 8141
8142 adapter->netdev = netdev;
8143 adapter->pdev = pdev;
8144 hw = &adapter->hw;
8145 hw->back = adapter;
b3f4d599 8146 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8147
05857980 8148 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8149 pci_resource_len(pdev, 0));
2a1a091c 8150 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8151 if (!hw->hw_addr) {
8152 err = -EIO;
8153 goto err_ioremap;
8154 }
8155
0edc3527 8156 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8157 ixgbe_set_ethtool_ops(netdev);
9a799d71 8158 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 8159 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 8160
9a799d71
AK		 8161 adapter->bd_number = cards_found;
8162
9a799d71
AK		 8163 /* Setup hw api */
8164 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8165 hw->mac.type = ii->mac;
9a799d71 8166
c44ade9e
JB		 8167 /* EEPROM */
8168 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8169 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
58cf663f
MR		 8170 if (ixgbe_removed(hw->hw_addr)) {
8171 err = -EIO;
8172 goto err_ioremap;
8173 }
c44ade9e
JB		 8174 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8175 if (!(eec & (1 << 8)))
8176 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8177
8178 /* PHY */
8179 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8180 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8181 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8182 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8183 hw->phy.mdio.mmds = 0;
8184 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8185 hw->phy.mdio.dev = netdev;
8186 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8187 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8188
8ca783ab 8189 ii->get_invariants(hw);
9a799d71
AK		 8190
8191 /* setup the private structure */
8192 err = ixgbe_sw_init(adapter);
8193 if (err)
8194 goto err_sw_init;
8195
e86bff0e 8196 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8197 switch (adapter->hw.mac.type) {
8198 case ixgbe_mac_82599EB:
8199 case ixgbe_mac_X540:
e86bff0e 8200 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8201 break;
8202 default:
8203 break;
8204 }
e86bff0e 8205
bf069c97
DS		 8206 /*
8207 * If there is a fan on this device and it has failed log the
8208 * failure.
8209 */
8210 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8211 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8212 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8213 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8214 }
8215
8ef78adc
PWJ		 8216 if (allow_unsupported_sfp)
8217 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8218
c44ade9e 8219 /* reset_hw fills in the perm_addr as well */
119fc60a 8220 hw->phy.reset_if_overtemp = true;
c44ade9e 8221 err = hw->mac.ops.reset_hw(hw);
119fc60a 8222 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8223 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8224 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8225 err = 0;
8226 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8227 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8228 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8229 goto err_sw_init;
8230 } else if (err) {
849c4542 8231 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8232 goto err_sw_init;
8233 }
8234
99d74487 8235#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8236 /* SR-IOV not supported on the 82598 */
8237 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8238 goto skip_sriov;
8239 /* Mailbox */
8240 ixgbe_init_mbx_params_pf(hw);
8241 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8242 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8243 ixgbe_enable_sriov(adapter);
60a1a680 8244skip_sriov:
1cdd1ec8 8245
99d74487 8246#endif
396e799c 8247 netdev->features = NETIF_F_SG |
e8e9f696 8248 NETIF_F_IP_CSUM |
082757af 8249 NETIF_F_IPV6_CSUM |
f646968f
PM		 8250 NETIF_F_HW_VLAN_CTAG_TX |
8251 NETIF_F_HW_VLAN_CTAG_RX |
8252 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8253 NETIF_F_TSO |
8254 NETIF_F_TSO6 |
082757af 8255 NETIF_F_RXHASH |
8bf1264d 8256 NETIF_F_RXCSUM;
9a799d71 8257
8bf1264d 8258 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8259
58be7666
DS		 8260 switch (adapter->hw.mac.type) {
8261 case ixgbe_mac_82599EB:
8262 case ixgbe_mac_X540:
45a5ead0 8263 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8264 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8265 NETIF_F_NTUPLE;
58be7666
DS		 8266 break;
8267 default:
8268 break;
8269 }
45a5ead0 8270
3f2d1c0f
BG		 8271 netdev->hw_features |= NETIF_F_RXALL;
8272
ad31c402
JK		 8273 netdev->vlan_features |= NETIF_F_TSO;
8274 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8275 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8276 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8277 netdev->vlan_features |= NETIF_F_SG;
8278
01789349 8279 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8280 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8281
7a6b6f51 8282#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8283 netdev->dcbnl_ops = &dcbnl_ops;
8284#endif
8285
eacd73f7 8286#ifdef IXGBE_FCOE
0d551589 8287 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8288 unsigned int fcoe_l;
8289
eacd73f7
YZ		 8290 if (hw->mac.ops.get_device_caps) {
8291 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8292 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8293 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8294 }
7c8ae65a 8295
d3cb9869
AD		 8296
8297 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8298 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8299
a58915c7
AD		 8300 netdev->features |= NETIF_F_FSO |
8301 NETIF_F_FCOE_CRC;
8302
7c8ae65a
AD		 8303 netdev->vlan_features |= NETIF_F_FSO |
8304 NETIF_F_FCOE_CRC |
8305 NETIF_F_FCOE_MTU;
5e09d7f6 8306 }
eacd73f7 8307#endif /* IXGBE_FCOE */
7b872a55 8308 if (pci_using_dac) {
9a799d71 8309 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8310 netdev->vlan_features |= NETIF_F_HIGHDMA;
8311 }
9a799d71 8312
082757af
DS		 8313 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8314 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8315 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8316 netdev->features |= NETIF_F_LRO;
8317
9a799d71 8318 /* make sure the EEPROM is good */
c44ade9e 8319 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8320 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8321 err = -EIO;
35937c05 8322 goto err_sw_init;
9a799d71
AK		 8323 }
8324
8325 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8326
aaeb6cdf 8327 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8328 e_dev_err("invalid MAC address\n");
9a799d71 8329 err = -EIO;
35937c05 8330 goto err_sw_init;
9a799d71
AK		 8331 }
8332
5d7daa35
JK		 8333 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8334
7086400d 8335 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8336 (unsigned long) adapter);
9a799d71 8337
58cf663f
MR		 8338 if (ixgbe_removed(hw->hw_addr)) {
8339 err = -EIO;
8340 goto err_sw_init;
8341 }
7086400d 8342 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8343 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8344 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8345
021230d4
AV		 8346 err = ixgbe_init_interrupt_scheme(adapter);
8347 if (err)
8348 goto err_sw_init;
9a799d71 8349
8e2813f5 8350 /* WOL not supported for all devices */
c23f5b6b 8351 adapter->wol = 0;
8e2813f5 8352 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8353 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8354 pdev->subsystem_device);
6b92b0ba 8355 if (hw->wol_enabled)
9417c464 8356 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8357
e8e26350
PW		 8358 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8359
15e5209f
ET		 8360 /* save off EEPROM version number */
8361 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8362 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8363
04f165ef
PW		 8364 /* pick up the PCI bus settings for reporting later */
8365 hw->mac.ops.get_bus_info(hw);
e027d1ae 8366 if (ixgbe_pcie_from_parent(hw))
b8e82001 8367 ixgbe_get_parent_bus_info(adapter);
04f165ef 8368
e027d1ae
JK		 8369 /* calculate the expected PCIe bandwidth required for optimal
8370 * performance. Note that some older parts will never have enough
8371 * bandwidth due to being older generation PCIe parts. We clamp these
8372 * parts to ensure no warning is displayed if it can't be fixed.
8373 */
8374 switch (hw->mac.type) {
8375 case ixgbe_mac_82598EB:
8376 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8377 break;
8378 default:
8379 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8380 break;
0c254d86 8381 }
e027d1ae 8382 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8383
6a2aae5a
JK		 8384 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8385 if (err)
8386 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8387 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8388 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8389 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8390 part_str);
8391 else
8392 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8393 hw->mac.type, hw->phy.type, part_str);
8394
8395 e_dev_info("%pM\n", netdev->dev_addr);
8396
9a799d71 8397 /* reset the hardware with the new settings */
794caeb2 8398 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8399 if (err == IXGBE_ERR_EEPROM_VERSION) {
8400 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8401 e_dev_warn("This device is a pre-production adapter/LOM. "
8402 "Please be aware there may be issues associated "
8403 "with your hardware. If you are experiencing "
8404 "problems please contact your Intel or hardware "
8405 "representative who provided you with this "
8406 "hardware.\n");
794caeb2 8407 }
9a799d71
AK		 8408 strcpy(netdev->name, "eth%d");
8409 err = register_netdev(netdev);
8410 if (err)
8411 goto err_register;
8412
ec74a471
ET		 8413 /* power down the optics for 82599 SFP+ fiber */
8414 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8415 hw->mac.ops.disable_tx_laser(hw);
8416
54386467
JB		 8417 /* carrier off reporting is important to ethtool even BEFORE open */
8418 netif_carrier_off(netdev);
8419
5dd2d332 8420#ifdef CONFIG_IXGBE_DCA
652f093f 8421 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8422 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8423 ixgbe_setup_dca(adapter);
8424 }
8425#endif
1cdd1ec8 8426 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8427 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8428 for (i = 0; i < adapter->num_vfs; i++)
8429 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8430 }
8431
2466dd9c
JK		 8432 /* firmware requires driver version to be 0xFFFFFFFF
8433 * since os does not support feature
8434 */
9612de92 8435 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8436 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8437 0xFF);
9612de92 8438
0365e6e4
PW		 8439 /* add san mac addr to netdev */
8440 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8441
ea81875a 8442 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8443 cards_found++;
3ca8bc6d 8444
1210982b 8445#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8446 if (ixgbe_sysfs_init(adapter))
8447 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8448#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8449
00949167 8450 ixgbe_dbg_adapter_init(adapter);
00949167 8451
0b2679d6 8452 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7155d051 8453 if (ixgbe_mng_enabled(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8454 hw->mac.ops.setup_link(hw,
8455 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8456 true);
8457
9a799d71
AK		 8458 return 0;
8459
8460err_register:
5eba3699 8461 ixgbe_release_hw_control(adapter);
7a921c93 8462 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8463err_sw_init:
99d74487 8464 ixgbe_disable_sriov(adapter);
7086400d 8465 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8466 iounmap(adapter->io_addr);
5d7daa35 8467 kfree(adapter->mac_table);
9a799d71
AK		 8468err_ioremap:
8469 free_netdev(netdev);
8470err_alloc_etherdev:
e8e9f696
JP		 8471 pci_release_selected_regions(pdev,
8472 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8473err_pci_reg:
8474err_dma:
41c62843
MR		 8475 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8476 pci_disable_device(pdev);
9a799d71
AK		 8477 return err;
8478}
8479
8480/**
8481 * ixgbe_remove - Device Removal Routine
8482 * @pdev: PCI device information struct
8483 *
8484 * ixgbe_remove is called by the PCI subsystem to alert the driver
8485 * that it should release a PCI device. The could be caused by a
8486 * Hot-Plug event, or because the driver is going to be removed from
8487 * memory.
8488 **/
9f9a12f8 8489static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8490{
c60fbb00
AD		 8491 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8492 struct net_device *netdev = adapter->netdev;
9a799d71 8493
00949167 8494 ixgbe_dbg_adapter_exit(adapter);
00949167 8495
09f40aed 8496 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8497 cancel_work_sync(&adapter->service_task);
9a799d71 8498
3a6a4eda 8499
5dd2d332 8500#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8501 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8502 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8503 dca_remove_requester(&pdev->dev);
8504 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8505 }
8506
8507#endif
1210982b 8508#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8509 ixgbe_sysfs_exit(adapter);
1210982b 8510#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8511
0365e6e4
PW		 8512 /* remove the added san mac */
8513 ixgbe_del_sanmac_netdev(netdev);
8514
c4900be0
DS		 8515 if (netdev->reg_state == NETREG_REGISTERED)
8516 unregister_netdev(netdev);
9a799d71 8517
da36b647
GR		 8518#ifdef CONFIG_PCI_IOV
8519 /*
8520 * Only disable SR-IOV on unload if the user specified the now
8521 * deprecated max_vfs module parameter.
8522 */
8523 if (max_vfs)
8524 ixgbe_disable_sriov(adapter);
8525#endif
7a921c93 8526 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8527
021230d4 8528 ixgbe_release_hw_control(adapter);
9a799d71 8529
2b1588c3
AD		 8530#ifdef CONFIG_DCB
8531 kfree(adapter->ixgbe_ieee_pfc);
8532 kfree(adapter->ixgbe_ieee_ets);
8533
8534#endif
2a1a091c 8535 iounmap(adapter->io_addr);
9ce77666 8536 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8537 IORESOURCE_MEM));
9a799d71 8538
849c4542 8539 e_dev_info("complete\n");
021230d4 8540
5d7daa35 8541 kfree(adapter->mac_table);
9a799d71
AK		 8542 free_netdev(netdev);
8543
19d5afd4 8544 pci_disable_pcie_error_reporting(pdev);
6fabd715 8545
41c62843
MR		 8546 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8547 pci_disable_device(pdev);
9a799d71
AK		 8548}
8549
8550/**
8551 * ixgbe_io_error_detected - called when PCI error is detected
8552 * @pdev: Pointer to PCI device
8553 * @state: The current pci connection state
8554 *
8555 * This function is called after a PCI bus error affecting
8556 * this device has been detected.
8557 */
8558static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8559 pci_channel_state_t state)
9a799d71 8560{
c60fbb00
AD		 8561 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8562 struct net_device *netdev = adapter->netdev;
9a799d71 8563
83c61fa9 8564#ifdef CONFIG_PCI_IOV
14438464 8565 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8566 struct pci_dev *bdev, *vfdev;
8567 u32 dw0, dw1, dw2, dw3;
8568 int vf, pos;
8569 u16 req_id, pf_func;
8570
8571 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8572 adapter->num_vfs == 0)
8573 goto skip_bad_vf_detection;
8574
8575 bdev = pdev->bus->self;
62f87c0e 8576 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8577 bdev = bdev->bus->self;
8578
8579 if (!bdev)
8580 goto skip_bad_vf_detection;
8581
8582 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8583 if (!pos)
8584 goto skip_bad_vf_detection;
8585
14438464
MR		 8586 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8587 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8588 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8589 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8590 if (ixgbe_removed(hw->hw_addr))
8591 goto skip_bad_vf_detection;
83c61fa9
GR		 8592
8593 req_id = dw1 >> 16;
8594 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8595 if (!(req_id & 0x0080))
8596 goto skip_bad_vf_detection;
8597
8598 pf_func = req_id & 0x01;
8599 if ((pf_func & 1) == (pdev->devfn & 1)) {
8600 unsigned int device_id;
8601
8602 vf = (req_id & 0x7F) >> 1;
8603 e_dev_err("VF %d has caused a PCIe error\n", vf);
8604 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8605 "%8.8x\tdw3: %8.8x\n",
8606 dw0, dw1, dw2, dw3);
8607 switch (adapter->hw.mac.type) {
8608 case ixgbe_mac_82599EB:
8609 device_id = IXGBE_82599_VF_DEVICE_ID;
8610 break;
8611 case ixgbe_mac_X540:
8612 device_id = IXGBE_X540_VF_DEVICE_ID;
8613 break;
8614 default:
8615 device_id = 0;
8616 break;
8617 }
8618
8619 /* Find the pci device of the offending VF */
36e90319 8620 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8621 while (vfdev) {
8622 if (vfdev->devfn == (req_id & 0xFF))
8623 break;
36e90319 8624 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8625 device_id, vfdev);
8626 }
8627 /*
8628 * There's a slim chance the VF could have been hot plugged,
8629 * so if it is no longer present we don't need to issue the
8630 * VFLR. Just clean up the AER in that case.
8631 */
8632 if (vfdev) {
8633 e_dev_err("Issuing VFLR to VF %d\n", vf);
8634 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8635 /* Free device reference count */
8636 pci_dev_put(vfdev);
83c61fa9
GR		 8637 }
8638
8639 pci_cleanup_aer_uncorrect_error_status(pdev);
8640 }
8641
8642 /*
8643 * Even though the error may have occurred on the other port
8644 * we still need to increment the vf error reference count for
8645 * both ports because the I/O resume function will be called
8646 * for both of them.
8647 */
8648 adapter->vferr_refcount++;
8649
8650 return PCI_ERS_RESULT_RECOVERED;
8651
8652skip_bad_vf_detection:
8653#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 8654 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8655 return PCI_ERS_RESULT_DISCONNECT;
8656
41c62843 8657 rtnl_lock();
9a799d71
AK		 8658 netif_device_detach(netdev);
8659
41c62843
MR		 8660 if (state == pci_channel_io_perm_failure) {
8661 rtnl_unlock();
3044b8d1 8662 return PCI_ERS_RESULT_DISCONNECT;
41c62843 8663 }
3044b8d1 8664
9a799d71
AK		 8665 if (netif_running(netdev))
8666 ixgbe_down(adapter);
41c62843
MR		 8667
8668 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8669 pci_disable_device(pdev);
8670 rtnl_unlock();
9a799d71 8671
b4617240 8672 /* Request a slot reset. */
9a799d71
AK		 8673 return PCI_ERS_RESULT_NEED_RESET;
8674}
8675
8676/**
8677 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8678 * @pdev: Pointer to PCI device
8679 *
8680 * Restart the card from scratch, as if from a cold-boot.
8681 */
8682static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8683{
c60fbb00 8684 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8685 pci_ers_result_t result;
8686 int err;
9a799d71 8687
9ce77666 8688 if (pci_enable_device_mem(pdev)) {
396e799c 8689 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8690 result = PCI_ERS_RESULT_DISCONNECT;
8691 } else {
41c62843
MR		 8692 smp_mb__before_clear_bit();
8693 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 8694 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8695 pci_set_master(pdev);
8696 pci_restore_state(pdev);
c0e1f68b 8697 pci_save_state(pdev);
9a799d71 8698
dd4d8ca6 8699 pci_wake_from_d3(pdev, false);
9a799d71 8700
6fabd715 8701 ixgbe_reset(adapter);
88512539 8702 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8703 result = PCI_ERS_RESULT_RECOVERED;
8704 }
8705
8706 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8707 if (err) {
849c4542
ET		 8708 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8709 "failed 0x%0x\n", err);
6fabd715
PWJ		 8710 /* non-fatal, continue */
8711 }
9a799d71 8712
6fabd715 8713 return result;
9a799d71
AK		 8714}
8715
8716/**
8717 * ixgbe_io_resume - called when traffic can start flowing again.
8718 * @pdev: Pointer to PCI device
8719 *
8720 * This callback is called when the error recovery driver tells us that
8721 * its OK to resume normal operation.
8722 */
8723static void ixgbe_io_resume(struct pci_dev *pdev)
8724{
c60fbb00
AD		 8725 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8726 struct net_device *netdev = adapter->netdev;
9a799d71 8727
83c61fa9
GR		 8728#ifdef CONFIG_PCI_IOV
8729 if (adapter->vferr_refcount) {
8730 e_info(drv, "Resuming after VF err\n");
8731 adapter->vferr_refcount--;
8732 return;
8733 }
8734
8735#endif
c7ccde0f
AD		 8736 if (netif_running(netdev))
8737 ixgbe_up(adapter);
9a799d71
AK		 8738
8739 netif_device_attach(netdev);
9a799d71
AK		 8740}
8741
3646f0e5 8742static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8743 .error_detected = ixgbe_io_error_detected,
8744 .slot_reset = ixgbe_io_slot_reset,
8745 .resume = ixgbe_io_resume,
8746};
8747
8748static struct pci_driver ixgbe_driver = {
8749 .name = ixgbe_driver_name,
8750 .id_table = ixgbe_pci_tbl,
8751 .probe = ixgbe_probe,
9f9a12f8 8752 .remove = ixgbe_remove,
9a799d71
AK		 8753#ifdef CONFIG_PM
8754 .suspend = ixgbe_suspend,
8755 .resume = ixgbe_resume,
8756#endif
8757 .shutdown = ixgbe_shutdown,
da36b647 8758 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8759 .err_handler = &ixgbe_err_handler
8760};
8761
8762/**
8763 * ixgbe_init_module - Driver Registration Routine
8764 *
8765 * ixgbe_init_module is the first routine called when the driver is
8766 * loaded. All it does is register with the PCI subsystem.
8767 **/
8768static int __init ixgbe_init_module(void)
8769{
8770 int ret;
c7689578 8771 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8772 pr_info("%s\n", ixgbe_copyright);
9a799d71 8773
00949167 8774 ixgbe_dbg_init();
00949167 8775
f01fc1a8
JK		 8776 ret = pci_register_driver(&ixgbe_driver);
8777 if (ret) {
f01fc1a8 8778 ixgbe_dbg_exit();
f01fc1a8
JK		 8779 return ret;
8780 }
8781
5dd2d332 8782#ifdef CONFIG_IXGBE_DCA
bd0362dd 8783 dca_register_notify(&dca_notifier);
bd0362dd 8784#endif
5dd2d332 8785
f01fc1a8 8786 return 0;
9a799d71 8787}
b4617240 8788
9a799d71
AK		 8789module_init(ixgbe_init_module);
8790
8791/**
8792 * ixgbe_exit_module - Driver Exit Cleanup Routine
8793 *
8794 * ixgbe_exit_module is called just before the driver is removed
8795 * from memory.
8796 **/
8797static void __exit ixgbe_exit_module(void)
8798{
5dd2d332 8799#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8800 dca_unregister_notify(&dca_notifier);
8801#endif
9a799d71 8802 pci_unregister_driver(&ixgbe_driver);
00949167 8803
00949167 8804 ixgbe_dbg_exit();
00949167 8805
1a51502b 8806 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8807}
bd0362dd 8808
5dd2d332 8809#ifdef CONFIG_IXGBE_DCA
bd0362dd 8810static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8811 void *p)
bd0362dd
JC		 8812{
8813 int ret_val;
8814
8815 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8816 __ixgbe_notify_dca);
bd0362dd
JC		 8817
8818 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8819}
b453368d 8820
5dd2d332 8821#endif /* CONFIG_IXGBE_DCA */
849c4542 8822
9a799d71
AK		 8823module_exit(ixgbe_exit_module);
8824
8825/* ixgbe_main.c */
Linux kernel - Deliverables
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