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ixgbe: Support RX-ALL feature flag.
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
ea81875a
NP		 58char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
75e3d3c6 60#define MAJ 3
19d478bb
DS		 61#define MIN 6
62#define BUILD 7
75e3d3c6 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 64 __stringify(BUILD) "-k"
9c8eb720 65const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 66static const char ixgbe_copyright[] =
94971820 67 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 68
69static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 70 [board_82598] = &ixgbe_82598_info,
e8e26350 71 [board_82599] = &ixgbe_82599_info,
fe15e8e1 72 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 73};
74
75/* ixgbe_pci_tbl - PCI Device ID Table
76 *
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
79 *
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
82 */
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
1cdd1ec8
GR		 127#ifdef CONFIG_PCI_IOV
128static unsigned int max_vfs;
129module_param(max_vfs, uint, 0);
e8e9f696
JP		 130MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 132#endif /* CONFIG_PCI_IOV */
133
8ef78adc
PWJ		 134static unsigned int allow_unsupported_sfp;
135module_param(allow_unsupported_sfp, uint, 0);
136MODULE_PARM_DESC(allow_unsupported_sfp,
137 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
138
9a799d71
AK		 139MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_VERSION);
143
144#define DEFAULT_DEBUG_LEVEL_SHIFT 3
145
7086400d
AD		 146static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
147{
148 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
149 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
150 schedule_work(&adapter->service_task);
151}
152
153static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
154{
155 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
156
52f33af8 157 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 158 smp_mb__before_clear_bit();
159 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
160}
161
dcd79aeb
TI		 162struct ixgbe_reg_info {
163 u32 ofs;
164 char *name;
165};
166
167static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
168
169 /* General Registers */
170 {IXGBE_CTRL, "CTRL"},
171 {IXGBE_STATUS, "STATUS"},
172 {IXGBE_CTRL_EXT, "CTRL_EXT"},
173
174 /* Interrupt Registers */
175 {IXGBE_EICR, "EICR"},
176
177 /* RX Registers */
178 {IXGBE_SRRCTL(0), "SRRCTL"},
179 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
180 {IXGBE_RDLEN(0), "RDLEN"},
181 {IXGBE_RDH(0), "RDH"},
182 {IXGBE_RDT(0), "RDT"},
183 {IXGBE_RXDCTL(0), "RXDCTL"},
184 {IXGBE_RDBAL(0), "RDBAL"},
185 {IXGBE_RDBAH(0), "RDBAH"},
186
187 /* TX Registers */
188 {IXGBE_TDBAL(0), "TDBAL"},
189 {IXGBE_TDBAH(0), "TDBAH"},
190 {IXGBE_TDLEN(0), "TDLEN"},
191 {IXGBE_TDH(0), "TDH"},
192 {IXGBE_TDT(0), "TDT"},
193 {IXGBE_TXDCTL(0), "TXDCTL"},
194
195 /* List Terminator */
196 {}
197};
198
199
200/*
201 * ixgbe_regdump - register printout routine
202 */
203static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
204{
205 int i = 0, j = 0;
206 char rname[16];
207 u32 regs[64];
208
209 switch (reginfo->ofs) {
210 case IXGBE_SRRCTL(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
213 break;
214 case IXGBE_DCA_RXCTRL(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
217 break;
218 case IXGBE_RDLEN(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
221 break;
222 case IXGBE_RDH(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
225 break;
226 case IXGBE_RDT(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
229 break;
230 case IXGBE_RXDCTL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
233 break;
234 case IXGBE_RDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
237 break;
238 case IXGBE_RDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
241 break;
242 case IXGBE_TDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
245 break;
246 case IXGBE_TDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
249 break;
250 case IXGBE_TDLEN(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
253 break;
254 case IXGBE_TDH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
257 break;
258 case IXGBE_TDT(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
261 break;
262 case IXGBE_TXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
265 break;
266 default:
c7689578 267 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 268 IXGBE_READ_REG(hw, reginfo->ofs));
269 return;
270 }
271
272 for (i = 0; i < 8; i++) {
273 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 274 pr_err("%-15s", rname);
dcd79aeb 275 for (j = 0; j < 8; j++)
c7689578
JP		 276 pr_cont(" %08x", regs[i*8+j]);
277 pr_cont("\n");
dcd79aeb
TI		 278 }
279
280}
281
282/*
283 * ixgbe_dump - Print registers, tx-rings and rx-rings
284 */
285static void ixgbe_dump(struct ixgbe_adapter *adapter)
286{
287 struct net_device *netdev = adapter->netdev;
288 struct ixgbe_hw *hw = &adapter->hw;
289 struct ixgbe_reg_info *reginfo;
290 int n = 0;
291 struct ixgbe_ring *tx_ring;
292 struct ixgbe_tx_buffer *tx_buffer_info;
293 union ixgbe_adv_tx_desc *tx_desc;
294 struct my_u0 { u64 a; u64 b; } *u0;
295 struct ixgbe_ring *rx_ring;
296 union ixgbe_adv_rx_desc *rx_desc;
297 struct ixgbe_rx_buffer *rx_buffer_info;
298 u32 staterr;
299 int i = 0;
300
301 if (!netif_msg_hw(adapter))
302 return;
303
304 /* Print netdevice Info */
305 if (netdev) {
306 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 307 pr_info("Device Name state "
dcd79aeb 308 "trans_start last_rx\n");
c7689578
JP		 309 pr_info("%-15s %016lX %016lX %016lX\n",
310 netdev->name,
311 netdev->state,
312 netdev->trans_start,
313 netdev->last_rx);
dcd79aeb
TI		 314 }
315
316 /* Print Registers */
317 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 318 pr_info(" Register Name Value\n");
dcd79aeb
TI		 319 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
320 reginfo->name; reginfo++) {
321 ixgbe_regdump(hw, reginfo);
322 }
323
324 /* Print TX Ring Summary */
325 if (!netdev || !netif_running(netdev))
326 goto exit;
327
328 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 329 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 330 for (n = 0; n < adapter->num_tx_queues; n++) {
331 tx_ring = adapter->tx_ring[n];
332 tx_buffer_info =
333 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 334 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 335 n, tx_ring->next_to_use, tx_ring->next_to_clean,
336 (u64)tx_buffer_info->dma,
337 tx_buffer_info->length,
338 tx_buffer_info->next_to_watch,
339 (u64)tx_buffer_info->time_stamp);
340 }
341
342 /* Print TX Rings */
343 if (!netif_msg_tx_done(adapter))
344 goto rx_ring_summary;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
347
348 /* Transmit Descriptor Formats
349 *
350 * Advanced Transmit Descriptor
351 * +--------------------------------------------------------------+
352 * 0 | Buffer Address [63:0] |
353 * +--------------------------------------------------------------+
354 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
355 * +--------------------------------------------------------------+
356 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
357 */
358
359 for (n = 0; n < adapter->num_tx_queues; n++) {
360 tx_ring = adapter->tx_ring[n];
c7689578
JP		 361 pr_info("------------------------------------\n");
362 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
363 pr_info("------------------------------------\n");
364 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 365 "[PlPOIdStDDt Ln] [bi->dma ] "
366 "leng ntw timestamp bi->skb\n");
367
368 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 369 tx_desc = IXGBE_TX_DESC(tx_ring, i);
dcd79aeb
TI		 370 tx_buffer_info = &tx_ring->tx_buffer_info[i];
371 u0 = (struct my_u0 *)tx_desc;
c7689578 372 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 373 " %04X %p %016llX %p", i,
dcd79aeb
TI		 374 le64_to_cpu(u0->a),
375 le64_to_cpu(u0->b),
376 (u64)tx_buffer_info->dma,
377 tx_buffer_info->length,
378 tx_buffer_info->next_to_watch,
379 (u64)tx_buffer_info->time_stamp,
380 tx_buffer_info->skb);
381 if (i == tx_ring->next_to_use &&
382 i == tx_ring->next_to_clean)
c7689578 383 pr_cont(" NTC/U\n");
dcd79aeb 384 else if (i == tx_ring->next_to_use)
c7689578 385 pr_cont(" NTU\n");
dcd79aeb 386 else if (i == tx_ring->next_to_clean)
c7689578 387 pr_cont(" NTC\n");
dcd79aeb 388 else
c7689578 389 pr_cont("\n");
dcd79aeb
TI		 390
391 if (netif_msg_pktdata(adapter) &&
392 tx_buffer_info->dma != 0)
393 print_hex_dump(KERN_INFO, "",
394 DUMP_PREFIX_ADDRESS, 16, 1,
395 phys_to_virt(tx_buffer_info->dma),
396 tx_buffer_info->length, true);
397 }
398 }
399
400 /* Print RX Rings Summary */
401rx_ring_summary:
402 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 403 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 404 for (n = 0; n < adapter->num_rx_queues; n++) {
405 rx_ring = adapter->rx_ring[n];
c7689578
JP		 406 pr_info("%5d %5X %5X\n",
407 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 408 }
409
410 /* Print RX Rings */
411 if (!netif_msg_rx_status(adapter))
412 goto exit;
413
414 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
415
416 /* Advanced Receive Descriptor (Read) Format
417 * 63 1 0
418 * +-----------------------------------------------------+
419 * 0 | Packet Buffer Address [63:1] |A0/NSE|
420 * +----------------------------------------------+------+
421 * 8 | Header Buffer Address [63:1] | DD |
422 * +-----------------------------------------------------+
423 *
424 *
425 * Advanced Receive Descriptor (Write-Back) Format
426 *
427 * 63 48 47 32 31 30 21 20 16 15 4 3 0
428 * +------------------------------------------------------+
429 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
430 * | Checksum Ident | | | | Type | Type |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
435 */
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 442 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
443 "<-- Adv Rx Read format\n");
c7689578 444 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 445 "[vl er S cks ln] ---------------- [bi->skb] "
446 "<-- Adv Rx Write-Back format\n");
447
448 for (i = 0; i < rx_ring->count; i++) {
449 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 450 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 451 u0 = (struct my_u0 *)rx_desc;
452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
453 if (staterr & IXGBE_RXD_STAT_DD) {
454 /* Descriptor Done */
c7689578 455 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 456 "%016llX ---------------- %p", i,
457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
459 rx_buffer_info->skb);
460 } else {
c7689578 461 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 462 "%016llX %016llX %p", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)rx_buffer_info->dma,
466 rx_buffer_info->skb);
467
468 if (netif_msg_pktdata(adapter)) {
469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(rx_buffer_info->dma),
472 rx_ring->rx_buf_len, true);
473
474 if (rx_ring->rx_buf_len
919e78a6 475 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 476 print_hex_dump(KERN_INFO, "",
477 DUMP_PREFIX_ADDRESS, 16, 1,
478 phys_to_virt(
479 rx_buffer_info->page_dma +
480 rx_buffer_info->page_offset
481 ),
482 PAGE_SIZE/2, true);
483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
e8e26350
PW		 520/*
521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
d3d00239
AD		 592static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
d3d00239
AD		 595 if (tx_buffer->dma) {
596 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
597 dma_unmap_page(ring->dev,
598 tx_buffer->dma,
599 tx_buffer->length,
600 DMA_TO_DEVICE);
e5a43549 601 else
d3d00239
AD		 602 dma_unmap_single(ring->dev,
603 tx_buffer->dma,
604 tx_buffer->length,
605 DMA_TO_DEVICE);
e5a43549 606 }
d3d00239
AD		 607 tx_buffer->dma = 0;
608}
609
610void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
611 struct ixgbe_tx_buffer *tx_buffer_info)
612{
613 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
614 if (tx_buffer_info->skb)
9a799d71 615 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 616 tx_buffer_info->skb = NULL;
9a799d71
AK		 617 /* tx_buffer_info must be completely set up in the transmit path */
618}
619
c84d324c
JF		 620static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
621{
622 struct ixgbe_hw *hw = &adapter->hw;
623 struct ixgbe_hw_stats *hwstats = &adapter->stats;
624 u32 data = 0;
625 u32 xoff[8] = {0};
626 int i;
627
628 if ((hw->fc.current_mode == ixgbe_fc_full) ||
629 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
630 switch (hw->mac.type) {
631 case ixgbe_mac_82598EB:
632 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 633 break;
634 default:
c84d324c
JF		 635 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
636 }
637 hwstats->lxoffrxc += data;
638
639 /* refill credits (no tx hang) if we received xoff */
640 if (!data)
641 return;
642
643 for (i = 0; i < adapter->num_tx_queues; i++)
644 clear_bit(__IXGBE_HANG_CHECK_ARMED,
645 &adapter->tx_ring[i]->state);
646 return;
647 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
648 return;
649
650 /* update stats for each tc, only valid with PFC enabled */
651 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
652 switch (hw->mac.type) {
653 case ixgbe_mac_82598EB:
654 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 655 break;
c84d324c
JF		 656 default:
657 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 658 }
c84d324c
JF		 659 hwstats->pxoffrxc[i] += xoff[i];
660 }
661
662 /* disarm tx queues that have received xoff frames */
663 for (i = 0; i < adapter->num_tx_queues; i++) {
664 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 665 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 666
667 if (xoff[tc])
668 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 669 }
26f23d82
YZ		 670}
671
c84d324c 672static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 673{
c84d324c
JF		 674 return ring->tx_stats.completed;
675}
676
677static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
678{
679 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 680 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 681
c84d324c
JF		 682 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
683 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
684
685 if (head != tail)
686 return (head < tail) ?
687 tail - head : (tail + ring->count - head);
688
689 return 0;
690}
691
692static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
693{
694 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
695 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
696 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
697 bool ret = false;
698
7d637bcc 699 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 700
701 /*
702 * Check for a hung queue, but be thorough. This verifies
703 * that a transmit has been completed since the previous
704 * check AND there is at least one packet pending. The
705 * ARMED bit is set to indicate a potential hang. The
706 * bit is cleared if a pause frame is received to remove
707 * false hang detection due to PFC or 802.3x frames. By
708 * requiring this to fail twice we avoid races with
709 * pfc clearing the ARMED bit and conditions where we
710 * run the check_tx_hang logic with a transmit completion
711 * pending but without time to complete it yet.
712 */
713 if ((tx_done_old == tx_done) && tx_pending) {
714 /* make sure it is true for two checks in a row */
715 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
716 &tx_ring->state);
717 } else {
718 /* update completed stats and continue */
719 tx_ring->tx_stats.tx_done_old = tx_done;
720 /* reset the countdown */
721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 722 }
723
c84d324c 724 return ret;
9a799d71
AK		 725}
726
c83c6cbd
AD		 727/**
728 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
729 * @adapter: driver private struct
730 **/
731static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
732{
733
734 /* Do the reset outside of interrupt context */
735 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
736 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
737 ixgbe_service_event_schedule(adapter);
738 }
739}
e01c31a5 740
9a799d71
AK		 741/**
742 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 743 * @q_vector: structure containing interrupt and ring information
e01c31a5 744 * @tx_ring: tx ring to clean
9a799d71 745 **/
fe49f04a 746static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 747 struct ixgbe_ring *tx_ring)
9a799d71 748{
fe49f04a 749 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 750 struct ixgbe_tx_buffer *tx_buffer;
751 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 752 unsigned int total_bytes = 0, total_packets = 0;
59224555 753 unsigned int budget = q_vector->tx.work_limit;
d3d00239 754 u16 i = tx_ring->next_to_clean;
9a799d71 755
d3d00239 756 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 757 tx_desc = IXGBE_TX_DESC(tx_ring, i);
12207e49 758
30065e63 759 for (; budget; budget--) {
d3d00239
AD		 760 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
761
762 /* if next_to_watch is not set then there is no work pending */
763 if (!eop_desc)
764 break;
765
7f83a9e6
AD		 766 /* prevent any other reads prior to eop_desc */
767 rmb();
768
d3d00239
AD		 769 /* if DD is not set pending work has not been completed */
770 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
771 break;
8ad494b0 772
d3d00239
AD		 773 /* count the packet as being completed */
774 tx_ring->tx_stats.completed++;
775
776 /* clear next_to_watch to prevent false hangs */
777 tx_buffer->next_to_watch = NULL;
8ad494b0 778
d3d00239
AD		 779 do {
780 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
d3d00239
AD		 781 if (likely(tx_desc == eop_desc)) {
782 eop_desc = NULL;
783 dev_kfree_skb_any(tx_buffer->skb);
784 tx_buffer->skb = NULL;
785
786 total_bytes += tx_buffer->bytecount;
787 total_packets += tx_buffer->gso_segs;
788 }
9a799d71 789
d3d00239
AD		 790 tx_buffer++;
791 tx_desc++;
8ad494b0 792 i++;
d3d00239 793 if (unlikely(i == tx_ring->count)) {
8ad494b0 794 i = 0;
e01c31a5 795
d3d00239 796 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 797 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 798 }
e01c31a5 799
d3d00239 800 } while (eop_desc);
12207e49
PWJ		 801 }
802
9a799d71 803 tx_ring->next_to_clean = i;
d3d00239 804 u64_stats_update_begin(&tx_ring->syncp);
b953799e 805 tx_ring->stats.bytes += total_bytes;
bd198058 806 tx_ring->stats.packets += total_packets;
d3d00239 807 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 808 q_vector->tx.total_bytes += total_bytes;
809 q_vector->tx.total_packets += total_packets;
b953799e 810
c84d324c
JF		 811 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
812 /* schedule immediate reset if we believe we hung */
813 struct ixgbe_hw *hw = &adapter->hw;
e4f74028 814 tx_desc = IXGBE_TX_DESC(tx_ring, i);
c84d324c
JF		 815 e_err(drv, "Detected Tx Unit Hang\n"
816 " Tx Queue <%d>\n"
817 " TDH, TDT <%x>, <%x>\n"
818 " next_to_use <%x>\n"
819 " next_to_clean <%x>\n"
820 "tx_buffer_info[next_to_clean]\n"
821 " time_stamp <%lx>\n"
822 " jiffies <%lx>\n",
823 tx_ring->queue_index,
824 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
825 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 826 tx_ring->next_to_use, i,
827 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 828
829 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
830
831 e_info(probe,
832 "tx hang %d detected on queue %d, resetting adapter\n",
833 adapter->tx_timeout_count + 1, tx_ring->queue_index);
834
b953799e 835 /* schedule immediate reset if we believe we hung */
c83c6cbd 836 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 837
838 /* the adapter is about to reset, no point in enabling stuff */
59224555 839 return true;
b953799e 840 }
9a799d71 841
b2d96e0a
AD		 842 netdev_tx_completed_queue(txring_txq(tx_ring),
843 total_packets, total_bytes);
844
e092be60 845#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 846 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 847 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 848 /* Make sure that anybody stopping the queue after this
849 * sees the new next_to_clean.
850 */
851 smp_mb();
fc77dc3c 852 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 853 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 854 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 855 ++tx_ring->tx_stats.restart_queue;
30eba97a 856 }
e092be60 857 }
9a799d71 858
59224555 859 return !!budget;
9a799d71
AK		 860}
861
5dd2d332 862#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 863static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
864 struct ixgbe_ring *tx_ring,
33cf09c9 865 int cpu)
bd0362dd 866{
33cf09c9 867 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 868 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
869 u16 reg_offset;
33cf09c9 870
33cf09c9
AD		 871 switch (hw->mac.type) {
872 case ixgbe_mac_82598EB:
bdda1a61 873 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 874 break;
875 case ixgbe_mac_82599EB:
b93a2226 876 case ixgbe_mac_X540:
bdda1a61
AD		 877 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
878 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 879 break;
880 default:
bdda1a61
AD		 881 /* for unknown hardware do not write register */
882 return;
bd0362dd 883 }
bdda1a61
AD		 884
885 /*
886 * We can enable relaxed ordering for reads, but not writes when
887 * DCA is enabled. This is due to a known issue in some chipsets
888 * which will cause the DCA tag to be cleared.
889 */
890 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
891 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
892 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
893
894 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 895}
896
bdda1a61
AD		 897static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
898 struct ixgbe_ring *rx_ring,
33cf09c9 899 int cpu)
bd0362dd 900{
33cf09c9 901 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 902 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
903 u8 reg_idx = rx_ring->reg_idx;
904
33cf09c9
AD		 905
906 switch (hw->mac.type) {
33cf09c9 907 case ixgbe_mac_82599EB:
b93a2226 908 case ixgbe_mac_X540:
bdda1a61 909 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 910 break;
911 default:
912 break;
913 }
bdda1a61
AD		 914
915 /*
916 * We can enable relaxed ordering for reads, but not writes when
917 * DCA is enabled. This is due to a known issue in some chipsets
918 * which will cause the DCA tag to be cleared.
919 */
920 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
921 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
922 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
923
924 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 925}
926
927static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
928{
929 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 930 struct ixgbe_ring *ring;
bd0362dd 931 int cpu = get_cpu();
bd0362dd 932
33cf09c9
AD		 933 if (q_vector->cpu == cpu)
934 goto out_no_update;
935
a557928e 936 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 937 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 938
a557928e 939 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 940 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 941
942 q_vector->cpu = cpu;
943out_no_update:
bd0362dd
JC		 944 put_cpu();
945}
946
947static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
948{
33cf09c9 949 int num_q_vectors;
bd0362dd
JC		 950 int i;
951
952 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
953 return;
954
e35ec126
AD		 955 /* always use CB2 mode, difference is masked in the CB driver */
956 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
957
33cf09c9
AD		 958 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
959 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
960 else
961 num_q_vectors = 1;
962
963 for (i = 0; i < num_q_vectors; i++) {
964 adapter->q_vector[i]->cpu = -1;
965 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 966 }
967}
968
969static int __ixgbe_notify_dca(struct device *dev, void *data)
970{
c60fbb00 971 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 972 unsigned long event = *(unsigned long *)data;
973
2a72c31e 974 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 975 return 0;
976
bd0362dd
JC		 977 switch (event) {
978 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 979 /* if we're already enabled, don't do it again */
980 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
981 break;
652f093f 982 if (dca_add_requester(dev) == 0) {
96b0e0f6 983 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 984 ixgbe_setup_dca(adapter);
985 break;
986 }
987 /* Fall Through since DCA is disabled. */
988 case DCA_PROVIDER_REMOVE:
989 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
990 dca_remove_requester(dev);
991 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
993 }
994 break;
995 }
996
652f093f 997 return 0;
bd0362dd 998}
67a74ee2 999
bdda1a61 1000#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1001static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1002 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1003 struct sk_buff *skb)
1004{
8a0da21b
AD		 1005 if (ring->netdev->features & NETIF_F_RXHASH)
1006 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1007}
1008
ff886dfc
AD		 1009/**
1010 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1011 * @adapter: address of board private structure
1012 * @rx_desc: advanced rx descriptor
1013 *
1014 * Returns : true if it is FCoE pkt
1015 */
1016static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1017 union ixgbe_adv_rx_desc *rx_desc)
1018{
1019 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1020
1021 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1022 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1023 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1024 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1025}
1026
e59bd25d
AV		 1027/**
1028 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1029 * @ring: structure containing ring specific data
1030 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1031 * @skb: skb currently being received and modified
1032 **/
8a0da21b 1033static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1034 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1035 struct sk_buff *skb)
9a799d71 1036{
8a0da21b 1037 skb_checksum_none_assert(skb);
9a799d71 1038
712744be 1039 /* Rx csum disabled */
8a0da21b 1040 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1041 return;
e59bd25d
AV		 1042
1043 /* if IP and error */
f56e0cb1
AD		 1044 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1045 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1046 ring->rx_stats.csum_err++;
9a799d71
AK		 1047 return;
1048 }
e59bd25d 1049
f56e0cb1 1050 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1051 return;
1052
f56e0cb1 1053 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1054 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1055
1056 /*
1057 * 82599 errata, UDP frames with a 0 checksum can be marked as
1058 * checksum errors.
1059 */
8a0da21b
AD		 1060 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1061 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1062 return;
1063
8a0da21b 1064 ring->rx_stats.csum_err++;
e59bd25d
AV		 1065 return;
1066 }
1067
9a799d71 1068 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1069 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1070}
1071
84ea2591 1072static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1073{
f56e0cb1 1074 rx_ring->next_to_use = val;
e8e26350
PW		 1075 /*
1076 * Force memory writes to complete before letting h/w
1077 * know there are new descriptors to fetch. (Only
1078 * applicable for weak-ordered memory model archs,
1079 * such as IA-64).
1080 */
1081 wmb();
84ea2591 1082 writel(val, rx_ring->tail);
e8e26350
PW		 1083}
1084
f990b79b
AD		 1085static bool ixgbe_alloc_mapped_skb(struct ixgbe_ring *rx_ring,
1086 struct ixgbe_rx_buffer *bi)
1087{
1088 struct sk_buff *skb = bi->skb;
1089 dma_addr_t dma = bi->dma;
1090
1091 if (dma)
1092 return true;
1093
1094 if (likely(!skb)) {
1095 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1096 rx_ring->rx_buf_len);
1097 bi->skb = skb;
1098 if (!skb) {
1099 rx_ring->rx_stats.alloc_rx_buff_failed++;
1100 return false;
1101 }
f990b79b
AD		 1102 }
1103
1104 dma = dma_map_single(rx_ring->dev, skb->data,
1105 rx_ring->rx_buf_len, DMA_FROM_DEVICE);
1106
1107 if (dma_mapping_error(rx_ring->dev, dma)) {
1108 rx_ring->rx_stats.alloc_rx_buff_failed++;
1109 return false;
1110 }
1111
1112 bi->dma = dma;
1113 return true;
1114}
1115
1116static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1117 struct ixgbe_rx_buffer *bi)
1118{
1119 struct page *page = bi->page;
1120 dma_addr_t page_dma = bi->page_dma;
1121 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
1122
1123 if (page_dma)
1124 return true;
1125
1126 if (!page) {
1127 page = alloc_page(GFP_ATOMIC | __GFP_COLD);
1128 bi->page = page;
1129 if (unlikely(!page)) {
1130 rx_ring->rx_stats.alloc_rx_page_failed++;
1131 return false;
1132 }
1133 }
1134
1135 page_dma = dma_map_page(rx_ring->dev, page,
1136 page_offset, PAGE_SIZE / 2,
1137 DMA_FROM_DEVICE);
1138
1139 if (dma_mapping_error(rx_ring->dev, page_dma)) {
1140 rx_ring->rx_stats.alloc_rx_page_failed++;
1141 return false;
1142 }
1143
1144 bi->page_dma = page_dma;
1145 bi->page_offset = page_offset;
1146 return true;
1147}
1148
9a799d71 1149/**
f990b79b 1150 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1151 * @rx_ring: ring to place buffers on
1152 * @cleaned_count: number of buffers to replace
9a799d71 1153 **/
fc77dc3c 1154void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1155{
9a799d71 1156 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1157 struct ixgbe_rx_buffer *bi;
d5f398ed 1158 u16 i = rx_ring->next_to_use;
9a799d71 1159
f990b79b
AD		 1160 /* nothing to do or no valid netdev defined */
1161 if (!cleaned_count || !rx_ring->netdev)
fc77dc3c
AD		 1162 return;
1163
e4f74028 1164 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1165 bi = &rx_ring->rx_buffer_info[i];
1166 i -= rx_ring->count;
9a799d71 1167
f990b79b
AD		 1168 while (cleaned_count--) {
1169 if (!ixgbe_alloc_mapped_skb(rx_ring, bi))
1170 break;
d5f398ed 1171
f990b79b
AD		 1172 /* Refresh the desc even if buffer_addrs didn't change
1173 * because each write-back erases this info. */
7d637bcc 1174 if (ring_is_ps_enabled(rx_ring)) {
f990b79b 1175 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
d5f398ed 1176
f990b79b
AD		 1177 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1178 break;
d5f398ed 1179
3a581073 1180 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
9a799d71 1181 } else {
3a581073 1182 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1183 }
1184
f990b79b
AD		 1185 rx_desc++;
1186 bi++;
9a799d71 1187 i++;
f990b79b 1188 if (unlikely(!i)) {
e4f74028 1189 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1190 bi = rx_ring->rx_buffer_info;
1191 i -= rx_ring->count;
1192 }
1193
1194 /* clear the hdr_addr for the next_to_use descriptor */
1195 rx_desc->read.hdr_addr = 0;
9a799d71 1196 }
7c6e0a43 1197
f990b79b
AD		 1198 i += rx_ring->count;
1199
f56e0cb1 1200 if (rx_ring->next_to_use != i)
84ea2591 1201 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1202}
1203
c267fc16 1204static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1205{
c267fc16
AD		 1206 /* HW will not DMA in data larger than the given buffer, even if it
1207 * parses the (NFS, of course) header to be larger. In that case, it
1208 * fills the header buffer and spills the rest into the page.
1209 */
1210 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1211 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1212 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1213 if (hlen > IXGBE_RX_HDR_SIZE)
1214 hlen = IXGBE_RX_HDR_SIZE;
1215 return hlen;
7c6e0a43
JB		 1216}
1217
f8212f97 1218/**
4c1975d7
AD		 1219 * ixgbe_merge_active_tail - merge active tail into lro skb
1220 * @tail: pointer to active tail in frag_list
f8212f97 1221 *
4c1975d7
AD		 1222 * This function merges the length and data of an active tail into the
1223 * skb containing the frag_list. It resets the tail's pointer to the head,
1224 * but it leaves the heads pointer to tail intact.
f8212f97 1225 **/
4c1975d7 1226static inline struct sk_buff *ixgbe_merge_active_tail(struct sk_buff *tail)
f8212f97 1227{
4c1975d7 1228 struct sk_buff *head = IXGBE_CB(tail)->head;
f8212f97 1229
4c1975d7
AD		 1230 if (!head)
1231 return tail;
1232
1233 head->len += tail->len;
1234 head->data_len += tail->len;
1235 head->truesize += tail->len;
1236
1237 IXGBE_CB(tail)->head = NULL;
1238
1239 return head;
1240}
1241
1242/**
1243 * ixgbe_add_active_tail - adds an active tail into the skb frag_list
1244 * @head: pointer to the start of the skb
1245 * @tail: pointer to active tail to add to frag_list
1246 *
1247 * This function adds an active tail to the end of the frag list. This tail
1248 * will still be receiving data so we cannot yet ad it's stats to the main
1249 * skb. That is done via ixgbe_merge_active_tail.
1250 **/
1251static inline void ixgbe_add_active_tail(struct sk_buff *head,
1252 struct sk_buff *tail)
1253{
1254 struct sk_buff *old_tail = IXGBE_CB(head)->tail;
1255
1256 if (old_tail) {
1257 ixgbe_merge_active_tail(old_tail);
1258 old_tail->next = tail;
1259 } else {
1260 skb_shinfo(head)->frag_list = tail;
f8212f97
AD		 1261 }
1262
4c1975d7
AD		 1263 IXGBE_CB(tail)->head = head;
1264 IXGBE_CB(head)->tail = tail;
1265}
1266
1267/**
1268 * ixgbe_close_active_frag_list - cleanup pointers on a frag_list skb
1269 * @head: pointer to head of an active frag list
1270 *
1271 * This function will clear the frag_tail_tracker pointer on an active
1272 * frag_list and returns true if the pointer was actually set
1273 **/
1274static inline bool ixgbe_close_active_frag_list(struct sk_buff *head)
1275{
1276 struct sk_buff *tail = IXGBE_CB(head)->tail;
1277
1278 if (!tail)
1279 return false;
1280
1281 ixgbe_merge_active_tail(tail);
1282
1283 IXGBE_CB(head)->tail = NULL;
aa80175a 1284
4c1975d7 1285 return true;
f8212f97
AD		 1286}
1287
1d2024f6
AD		 1288/**
1289 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1290 * @data: pointer to the start of the headers
1291 * @max_len: total length of section to find headers in
1292 *
1293 * This function is meant to determine the length of headers that will
1294 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1295 * motivation of doing this is to only perform one pull for IPv4 TCP
1296 * packets so that we can do basic things like calculating the gso_size
1297 * based on the average data per packet.
1298 **/
1299static unsigned int ixgbe_get_headlen(unsigned char *data,
1300 unsigned int max_len)
1301{
1302 union {
1303 unsigned char *network;
1304 /* l2 headers */
1305 struct ethhdr *eth;
1306 struct vlan_hdr *vlan;
1307 /* l3 headers */
1308 struct iphdr *ipv4;
1309 } hdr;
1310 __be16 protocol;
1311 u8 nexthdr = 0; /* default to not TCP */
1312 u8 hlen;
1313
1314 /* this should never happen, but better safe than sorry */
1315 if (max_len < ETH_HLEN)
1316 return max_len;
1317
1318 /* initialize network frame pointer */
1319 hdr.network = data;
1320
1321 /* set first protocol and move network header forward */
1322 protocol = hdr.eth->h_proto;
1323 hdr.network += ETH_HLEN;
1324
1325 /* handle any vlan tag if present */
1326 if (protocol == __constant_htons(ETH_P_8021Q)) {
1327 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1328 return max_len;
1329
1330 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1331 hdr.network += VLAN_HLEN;
1332 }
1333
1334 /* handle L3 protocols */
1335 if (protocol == __constant_htons(ETH_P_IP)) {
1336 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1337 return max_len;
1338
1339 /* access ihl as a u8 to avoid unaligned access on ia64 */
1340 hlen = (hdr.network[0] & 0x0F) << 2;
1341
1342 /* verify hlen meets minimum size requirements */
1343 if (hlen < sizeof(struct iphdr))
1344 return hdr.network - data;
1345
1346 /* record next protocol */
1347 nexthdr = hdr.ipv4->protocol;
1348 hdr.network += hlen;
1349#ifdef CONFIG_FCOE
1350 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1351 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1352 return max_len;
1353 hdr.network += FCOE_HEADER_LEN;
1354#endif
1355 } else {
1356 return hdr.network - data;
1357 }
1358
1359 /* finally sort out TCP */
1360 if (nexthdr == IPPROTO_TCP) {
1361 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1362 return max_len;
1363
1364 /* access doff as a u8 to avoid unaligned access on ia64 */
1365 hlen = (hdr.network[12] & 0xF0) >> 2;
1366
1367 /* verify hlen meets minimum size requirements */
1368 if (hlen < sizeof(struct tcphdr))
1369 return hdr.network - data;
1370
1371 hdr.network += hlen;
1372 }
1373
1374 /*
1375 * If everything has gone correctly hdr.network should be the
1376 * data section of the packet and will be the end of the header.
1377 * If not then it probably represents the end of the last recognized
1378 * header.
1379 */
1380 if ((hdr.network - data) < max_len)
1381 return hdr.network - data;
1382 else
1383 return max_len;
1384}
1385
4c1975d7
AD		 1386static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1387 union ixgbe_adv_rx_desc *rx_desc,
1388 struct sk_buff *skb)
aa80175a 1389{
4c1975d7
AD		 1390 __le32 rsc_enabled;
1391 u32 rsc_cnt;
1392
1393 if (!ring_is_rsc_enabled(rx_ring))
1394 return;
1395
1396 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1397 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1398
1399 /* If this is an RSC frame rsc_cnt should be non-zero */
1400 if (!rsc_enabled)
1401 return;
1402
1403 rsc_cnt = le32_to_cpu(rsc_enabled);
1404 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1405
1406 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1407}
43634e82 1408
1d2024f6
AD		 1409static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1410 struct sk_buff *skb)
1411{
1412 u16 hdr_len = ixgbe_get_headlen(skb->data, skb_headlen(skb));
1413
1414 /* set gso_size to avoid messing up TCP MSS */
1415 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1416 IXGBE_CB(skb)->append_cnt);
1417}
1418
1419static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1420 struct sk_buff *skb)
1421{
1422 /* if append_cnt is 0 then frame is not RSC */
1423 if (!IXGBE_CB(skb)->append_cnt)
1424 return;
1425
1426 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1427 rx_ring->rx_stats.rsc_flush++;
1428
1429 ixgbe_set_rsc_gso_size(rx_ring, skb);
1430
1431 /* gso_size is computed using append_cnt so always clear it last */
1432 IXGBE_CB(skb)->append_cnt = 0;
1433}
1434
8a0da21b
AD		 1435/**
1436 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1437 * @rx_ring: rx descriptor ring packet is being transacted on
1438 * @rx_desc: pointer to the EOP Rx descriptor
1439 * @skb: pointer to current skb being populated
f8212f97 1440 *
8a0da21b
AD		 1441 * This function checks the ring, descriptor, and packet information in
1442 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1443 * other fields within the skb.
f8212f97 1444 **/
8a0da21b
AD		 1445static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1446 union ixgbe_adv_rx_desc *rx_desc,
1447 struct sk_buff *skb)
f8212f97 1448{
8a0da21b
AD		 1449 ixgbe_update_rsc_stats(rx_ring, skb);
1450
1451 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1452
8a0da21b
AD		 1453 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1454
1455 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1456 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1457 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1458 }
1459
8a0da21b 1460 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1461
8a0da21b 1462 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
f8212f97
AD		 1463}
1464
8a0da21b
AD		 1465static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1466 struct sk_buff *skb)
aa80175a 1467{
8a0da21b
AD		 1468 struct ixgbe_adapter *adapter = q_vector->adapter;
1469
1470 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1471 napi_gro_receive(&q_vector->napi, skb);
1472 else
1473 netif_rx(skb);
aa80175a 1474}
43634e82 1475
4ff7fb12 1476static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1477 struct ixgbe_ring *rx_ring,
4ff7fb12 1478 int budget)
9a799d71 1479{
9a799d71 1480 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
4c1975d7 1481 struct ixgbe_rx_buffer *rx_buffer_info;
9a799d71 1482 struct sk_buff *skb;
d2f4fbe2 1483 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1484 const int current_node = numa_node_id();
8a0da21b 1485 struct ixgbe_adapter *adapter = q_vector->adapter;
3f2d1c0f 1486#ifdef IXGBE_FCOE
3d8fd385
YZ		 1487 int ddp_bytes = 0;
1488#endif /* IXGBE_FCOE */
c267fc16
AD		 1489 u16 i;
1490 u16 cleaned_count = 0;
9a799d71
AK		 1491
1492 i = rx_ring->next_to_clean;
e4f74028 1493 rx_desc = IXGBE_RX_DESC(rx_ring, i);
9a799d71 1494
f56e0cb1 1495 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
7c6e0a43 1496 u32 upper_len = 0;
9a799d71 1497
3c945e5b 1498 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1499
c267fc16
AD		 1500 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1501
9a799d71 1502 skb = rx_buffer_info->skb;
9a799d71 1503 rx_buffer_info->skb = NULL;
c267fc16 1504 prefetch(skb->data);
9a799d71 1505
b811ce91
JB		 1506 /* linear means we are building an skb from multiple pages */
1507 if (!skb_is_nonlinear(skb)) {
c267fc16 1508 u16 hlen;
c267fc16
AD		 1509 if (ring_is_ps_enabled(rx_ring)) {
1510 hlen = ixgbe_get_hlen(rx_desc);
1511 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1512 } else {
1513 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1514 }
1515
1516 skb_put(skb, hlen);
4c1975d7
AD		 1517
1518 /*
1519 * Delay unmapping of the first packet. It carries the
1520 * header information, HW may still access the header
1521 * after writeback. Only unmap it when EOP is reached
1522 */
1523 if (!IXGBE_CB(skb)->head) {
1524 IXGBE_CB(skb)->delay_unmap = true;
1525 IXGBE_CB(skb)->dma = rx_buffer_info->dma;
1526 } else {
1527 skb = ixgbe_merge_active_tail(skb);
1528 dma_unmap_single(rx_ring->dev,
1529 rx_buffer_info->dma,
1530 rx_ring->rx_buf_len,
1531 DMA_FROM_DEVICE);
1532 }
1533 rx_buffer_info->dma = 0;
c267fc16
AD		 1534 } else {
1535 /* assume packet split since header is unmapped */
1536 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1537 }
1538
1539 if (upper_len) {
b6ec895e
AD		 1540 dma_unmap_page(rx_ring->dev,
1541 rx_buffer_info->page_dma,
1542 PAGE_SIZE / 2,
1543 DMA_FROM_DEVICE);
9a799d71
AK		 1544 rx_buffer_info->page_dma = 0;
1545 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1546 rx_buffer_info->page,
1547 rx_buffer_info->page_offset,
1548 upper_len);
762f4c57 1549
c267fc16
AD		 1550 if ((page_count(rx_buffer_info->page) == 1) &&
1551 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1552 get_page(rx_buffer_info->page);
c267fc16
AD		 1553 else
1554 rx_buffer_info->page = NULL;
9a799d71
AK		 1555
1556 skb->len += upper_len;
1557 skb->data_len += upper_len;
98130646 1558 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1559 }
1560
4c1975d7
AD		 1561 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1562
9a799d71
AK		 1563 i++;
1564 if (i == rx_ring->count)
1565 i = 0;
9a799d71 1566
e4f74028 1567 next_rxd = IXGBE_RX_DESC(rx_ring, i);
9a799d71 1568 prefetch(next_rxd);
9a799d71 1569 cleaned_count++;
f8212f97 1570
f56e0cb1 1571 if ((!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) {
4c1975d7
AD		 1572 struct ixgbe_rx_buffer *next_buffer;
1573 u32 nextp;
1574
1575 if (IXGBE_CB(skb)->append_cnt) {
f56e0cb1
AD		 1576 nextp = le32_to_cpu(
1577 rx_desc->wb.upper.status_error);
4c1975d7
AD		 1578 nextp >>= IXGBE_RXDADV_NEXTP_SHIFT;
1579 } else {
1580 nextp = i;
1581 }
1582
f8212f97 1583 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97 1584
7d637bcc 1585 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1586 rx_buffer_info->skb = next_buffer->skb;
1587 rx_buffer_info->dma = next_buffer->dma;
1588 next_buffer->skb = skb;
1589 next_buffer->dma = 0;
1590 } else {
4c1975d7
AD		 1591 struct sk_buff *next_skb = next_buffer->skb;
1592 ixgbe_add_active_tail(skb, next_skb);
1593 IXGBE_CB(next_skb)->head = skb;
f8212f97 1594 }
5b7da515 1595 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1596 goto next_desc;
1597 }
1598
4c1975d7
AD		 1599 dma_unmap_single(rx_ring->dev,
1600 IXGBE_CB(skb)->dma,
1601 rx_ring->rx_buf_len,
1602 DMA_FROM_DEVICE);
1603 IXGBE_CB(skb)->dma = 0;
1604 IXGBE_CB(skb)->delay_unmap = false;
c267fc16 1605
4c1975d7
AD		 1606 if (ixgbe_close_active_frag_list(skb) &&
1607 !IXGBE_CB(skb)->append_cnt) {
aa80175a 1608 /* if we got here without RSC the packet is invalid */
4c1975d7
AD		 1609 dev_kfree_skb_any(skb);
1610 goto next_desc;
c267fc16
AD		 1611 }
1612
1613 /* ERR_MASK will only have valid bits if EOP set */
f56e0cb1 1614 if (unlikely(ixgbe_test_staterr(rx_desc,
3f2d1c0f
BG		 1615 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1616 !(adapter->netdev->features & NETIF_F_RXALL))) {
ff886dfc 1617 dev_kfree_skb_any(skb);
9a799d71
AK		 1618 goto next_desc;
1619 }
1620
d2f4fbe2
AV		 1621 /* probably a little skewed due to removing CRC */
1622 total_rx_bytes += skb->len;
1623 total_rx_packets++;
1624
8a0da21b
AD		 1625 /* populate checksum, timestamp, VLAN, and protocol */
1626 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1627
332d4a7d
YZ		 1628#ifdef IXGBE_FCOE
1629 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc 1630 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
f56e0cb1 1631 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1632 if (!ddp_bytes) {
1633 dev_kfree_skb_any(skb);
332d4a7d 1634 goto next_desc;
63d635b2 1635 }
3d8fd385 1636 }
332d4a7d 1637#endif /* IXGBE_FCOE */
8a0da21b 1638 ixgbe_rx_skb(q_vector, skb);
9a799d71 1639
4ff7fb12 1640 budget--;
9a799d71 1641next_desc:
4ff7fb12 1642 if (!budget)
c267fc16
AD		 1643 break;
1644
9a799d71
AK		 1645 /* return some buffers to hardware, one at a time is too slow */
1646 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1647 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1648 cleaned_count = 0;
1649 }
1650
1651 /* use prefetched values */
1652 rx_desc = next_rxd;
177db6ff
MC		 1653 }
1654
9a799d71 1655 rx_ring->next_to_clean = i;
7d4987de 1656 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1657
1658 if (cleaned_count)
fc77dc3c 1659 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1660
3d8fd385
YZ		 1661#ifdef IXGBE_FCOE
1662 /* include DDPed FCoE data */
1663 if (ddp_bytes > 0) {
1664 unsigned int mss;
1665
fc77dc3c 1666 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1667 sizeof(struct fc_frame_header) -
1668 sizeof(struct fcoe_crc_eof);
1669 if (mss > 512)
1670 mss &= ~511;
1671 total_rx_bytes += ddp_bytes;
1672 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1673 }
1674#endif /* IXGBE_FCOE */
1675
c267fc16
AD		 1676 u64_stats_update_begin(&rx_ring->syncp);
1677 rx_ring->stats.packets += total_rx_packets;
1678 rx_ring->stats.bytes += total_rx_bytes;
1679 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1680 q_vector->rx.total_packets += total_rx_packets;
1681 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1682
1683 return !!budget;
9a799d71
AK		 1684}
1685
9a799d71
AK		 1686/**
1687 * ixgbe_configure_msix - Configure MSI-X hardware
1688 * @adapter: board private structure
1689 *
1690 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1691 * interrupts.
1692 **/
1693static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1694{
021230d4 1695 struct ixgbe_q_vector *q_vector;
efe3d3c8 1696 int q_vectors, v_idx;
021230d4 1697 u32 mask;
9a799d71 1698
021230d4 1699 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1700
8e34d1aa
AD		 1701 /* Populate MSIX to EITR Select */
1702 if (adapter->num_vfs > 32) {
1703 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1704 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1705 }
1706
4df10466
JB		 1707 /*
1708 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1709 * corresponding register.
1710 */
1711 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1712 struct ixgbe_ring *ring;
7a921c93 1713 q_vector = adapter->q_vector[v_idx];
021230d4 1714
a557928e 1715 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1716 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1717
a557928e 1718 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1719 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1720
d5bf4f67
ET		 1721 if (q_vector->tx.ring && !q_vector->rx.ring) {
1722 /* tx only vector */
1723 if (adapter->tx_itr_setting == 1)
1724 q_vector->itr = IXGBE_10K_ITR;
1725 else
1726 q_vector->itr = adapter->tx_itr_setting;
1727 } else {
1728 /* rx or rx/tx vector */
1729 if (adapter->rx_itr_setting == 1)
1730 q_vector->itr = IXGBE_20K_ITR;
1731 else
1732 q_vector->itr = adapter->rx_itr_setting;
1733 }
021230d4 1734
fe49f04a 1735 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1736 }
1737
bd508178
AD		 1738 switch (adapter->hw.mac.type) {
1739 case ixgbe_mac_82598EB:
e8e26350 1740 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1741 v_idx);
bd508178
AD		 1742 break;
1743 case ixgbe_mac_82599EB:
b93a2226 1744 case ixgbe_mac_X540:
e8e26350 1745 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1746 break;
bd508178
AD		 1747 default:
1748 break;
1749 }
021230d4
AV		 1750 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1751
41fb9248 1752 /* set up to autoclear timer, and the vectors */
021230d4 1753 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1754 mask &= ~(IXGBE_EIMS_OTHER |
1755 IXGBE_EIMS_MAILBOX |
1756 IXGBE_EIMS_LSC);
1757
021230d4 1758 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1759}
1760
f494e8fa
AV		 1761enum latency_range {
1762 lowest_latency = 0,
1763 low_latency = 1,
1764 bulk_latency = 2,
1765 latency_invalid = 255
1766};
1767
1768/**
1769 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1770 * @q_vector: structure containing interrupt and ring information
1771 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1772 *
1773 * Stores a new ITR value based on packets and byte
1774 * counts during the last interrupt. The advantage of per interrupt
1775 * computation is faster updates and more accurate ITR for the current
1776 * traffic pattern. Constants in this function were computed
1777 * based on theoretical maximum wire speed and thresholds were set based
1778 * on testing data as well as attempting to minimize response time
1779 * while increasing bulk throughput.
1780 * this functionality is controlled by the InterruptThrottleRate module
1781 * parameter (see ixgbe_param.c)
1782 **/
bd198058
AD		 1783static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1784 struct ixgbe_ring_container *ring_container)
f494e8fa 1785{
bd198058
AD		 1786 int bytes = ring_container->total_bytes;
1787 int packets = ring_container->total_packets;
1788 u32 timepassed_us;
621bd70e 1789 u64 bytes_perint;
bd198058 1790 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1791
1792 if (packets == 0)
bd198058 1793 return;
f494e8fa
AV		 1794
1795 /* simple throttlerate management
621bd70e
AD		 1796 * 0-10MB/s lowest (100000 ints/s)
1797 * 10-20MB/s low (20000 ints/s)
1798 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1799 */
1800 /* what was last interrupt timeslice? */
d5bf4f67 1801 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1802 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1803
1804 switch (itr_setting) {
1805 case lowest_latency:
621bd70e 1806 if (bytes_perint > 10)
bd198058 1807 itr_setting = low_latency;
f494e8fa
AV		 1808 break;
1809 case low_latency:
621bd70e 1810 if (bytes_perint > 20)
bd198058 1811 itr_setting = bulk_latency;
621bd70e 1812 else if (bytes_perint <= 10)
bd198058 1813 itr_setting = lowest_latency;
f494e8fa
AV		 1814 break;
1815 case bulk_latency:
621bd70e 1816 if (bytes_perint <= 20)
bd198058 1817 itr_setting = low_latency;
f494e8fa
AV		 1818 break;
1819 }
1820
bd198058
AD		 1821 /* clear work counters since we have the values we need */
1822 ring_container->total_bytes = 0;
1823 ring_container->total_packets = 0;
1824
1825 /* write updated itr to ring container */
1826 ring_container->itr = itr_setting;
f494e8fa
AV		 1827}
1828
509ee935
JB		 1829/**
1830 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1831 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1832 *
1833 * This function is made to be called by ethtool and by the driver
1834 * when it needs to update EITR registers at runtime. Hardware
1835 * specific quirks/differences are taken care of here.
1836 */
fe49f04a 1837void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1838{
fe49f04a 1839 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1840 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1841 int v_idx = q_vector->v_idx;
5d967eb7 1842 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 1843
bd508178
AD		 1844 switch (adapter->hw.mac.type) {
1845 case ixgbe_mac_82598EB:
509ee935
JB		 1846 /* must write high and low 16 bits to reset counter */
1847 itr_reg |= (itr_reg << 16);
bd508178
AD		 1848 break;
1849 case ixgbe_mac_82599EB:
b93a2226 1850 case ixgbe_mac_X540:
509ee935
JB		 1851 /*
1852 * set the WDIS bit to not clear the timer bits and cause an
1853 * immediate assertion of the interrupt
1854 */
1855 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1856 break;
1857 default:
1858 break;
509ee935
JB		 1859 }
1860 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1861}
1862
bd198058 1863static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1864{
d5bf4f67 1865 u32 new_itr = q_vector->itr;
bd198058 1866 u8 current_itr;
f494e8fa 1867
bd198058
AD		 1868 ixgbe_update_itr(q_vector, &q_vector->tx);
1869 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1870
08c8833b 1871 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1872
1873 switch (current_itr) {
1874 /* counts and packets in update_itr are dependent on these numbers */
1875 case lowest_latency:
d5bf4f67 1876 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1877 break;
1878 case low_latency:
d5bf4f67 1879 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1880 break;
1881 case bulk_latency:
d5bf4f67 1882 new_itr = IXGBE_8K_ITR;
f494e8fa 1883 break;
bd198058
AD		 1884 default:
1885 break;
f494e8fa
AV		 1886 }
1887
d5bf4f67 1888 if (new_itr != q_vector->itr) {
fe49f04a 1889 /* do an exponential smoothing */
d5bf4f67
ET		 1890 new_itr = (10 * new_itr * q_vector->itr) /
1891 ((9 * new_itr) + q_vector->itr);
509ee935 1892
bd198058 1893 /* save the algorithm value here */
5d967eb7 1894 q_vector->itr = new_itr;
fe49f04a
AD		 1895
1896 ixgbe_write_eitr(q_vector);
f494e8fa 1897 }
f494e8fa
AV		 1898}
1899
119fc60a 1900/**
de88eeeb 1901 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 1902 * @adapter: pointer to adapter
119fc60a 1903 **/
f0f9778d 1904static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1905{
119fc60a
MC		 1906 struct ixgbe_hw *hw = &adapter->hw;
1907 u32 eicr = adapter->interrupt_event;
1908
f0f9778d 1909 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1910 return;
1911
f0f9778d
AD		 1912 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1913 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1914 return;
1915
1916 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1917
7ca647bd 1918 switch (hw->device_id) {
f0f9778d
AD		 1919 case IXGBE_DEV_ID_82599_T3_LOM:
1920 /*
1921 * Since the warning interrupt is for both ports
1922 * we don't have to check if:
1923 * - This interrupt wasn't for our port.
1924 * - We may have missed the interrupt so always have to
1925 * check if we got a LSC
1926 */
1927 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1928 !(eicr & IXGBE_EICR_LSC))
1929 return;
1930
1931 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1932 u32 autoneg;
1933 bool link_up = false;
7ca647bd 1934
7ca647bd
JP		 1935 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1936
f0f9778d
AD		 1937 if (link_up)
1938 return;
1939 }
1940
1941 /* Check if this is not due to overtemp */
1942 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1943 return;
1944
1945 break;
7ca647bd
JP		 1946 default:
1947 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1948 return;
7ca647bd 1949 break;
119fc60a 1950 }
7ca647bd
JP		 1951 e_crit(drv,
1952 "Network adapter has been stopped because it has over heated. "
1953 "Restart the computer. If the problem persists, "
1954 "power off the system and replace the adapter\n");
f0f9778d
AD		 1955
1956 adapter->interrupt_event = 0;
119fc60a
MC		 1957}
1958
0befdb3e
JB		 1959static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1960{
1961 struct ixgbe_hw *hw = &adapter->hw;
1962
1963 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1964 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1965 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1966 /* write to clear the interrupt */
1967 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1968 }
1969}
cf8280ee 1970
4f51bf70
JK		 1971static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1972{
1973 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1974 return;
1975
1976 switch (adapter->hw.mac.type) {
1977 case ixgbe_mac_82599EB:
1978 /*
1979 * Need to check link state so complete overtemp check
1980 * on service task
1981 */
1982 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1983 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1984 adapter->interrupt_event = eicr;
1985 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1986 ixgbe_service_event_schedule(adapter);
1987 return;
1988 }
1989 return;
1990 case ixgbe_mac_X540:
1991 if (!(eicr & IXGBE_EICR_TS))
1992 return;
1993 break;
1994 default:
1995 return;
1996 }
1997
1998 e_crit(drv,
1999 "Network adapter has been stopped because it has over heated. "
2000 "Restart the computer. If the problem persists, "
2001 "power off the system and replace the adapter\n");
2002}
2003
e8e26350
PW		 2004static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2005{
2006 struct ixgbe_hw *hw = &adapter->hw;
2007
73c4b7cd
AD		 2008 if (eicr & IXGBE_EICR_GPI_SDP2) {
2009 /* Clear the interrupt */
2010 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2011 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2012 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2013 ixgbe_service_event_schedule(adapter);
2014 }
73c4b7cd
AD		 2015 }
2016
e8e26350
PW		 2017 if (eicr & IXGBE_EICR_GPI_SDP1) {
2018 /* Clear the interrupt */
2019 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2020 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2021 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2022 ixgbe_service_event_schedule(adapter);
2023 }
e8e26350
PW		 2024 }
2025}
2026
cf8280ee
JB		 2027static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2028{
2029 struct ixgbe_hw *hw = &adapter->hw;
2030
2031 adapter->lsc_int++;
2032 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2033 adapter->link_check_timeout = jiffies;
2034 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2035 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2036 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2037 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2038 }
2039}
2040
fe49f04a
AD		 2041static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2042 u64 qmask)
2043{
2044 u32 mask;
bd508178 2045 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2046
bd508178
AD		 2047 switch (hw->mac.type) {
2048 case ixgbe_mac_82598EB:
fe49f04a 2049 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2050 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2051 break;
2052 case ixgbe_mac_82599EB:
b93a2226 2053 case ixgbe_mac_X540:
fe49f04a 2054 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2055 if (mask)
2056 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2057 mask = (qmask >> 32);
bd508178
AD		 2058 if (mask)
2059 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2060 break;
2061 default:
2062 break;
fe49f04a
AD		 2063 }
2064 /* skip the flush */
2065}
2066
2067static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2068 u64 qmask)
fe49f04a
AD		 2069{
2070 u32 mask;
bd508178 2071 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2072
bd508178
AD		 2073 switch (hw->mac.type) {
2074 case ixgbe_mac_82598EB:
fe49f04a 2075 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2076 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2077 break;
2078 case ixgbe_mac_82599EB:
b93a2226 2079 case ixgbe_mac_X540:
fe49f04a 2080 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2081 if (mask)
2082 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2083 mask = (qmask >> 32);
bd508178
AD		 2084 if (mask)
2085 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2086 break;
2087 default:
2088 break;
fe49f04a
AD		 2089 }
2090 /* skip the flush */
2091}
2092
021230d4 2093/**
2c4af694
AD		 2094 * ixgbe_irq_enable - Enable default interrupt generation settings
2095 * @adapter: board private structure
021230d4 2096 **/
2c4af694
AD		 2097static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2098 bool flush)
9a799d71 2099{
2c4af694 2100 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2101
2c4af694
AD		 2102 /* don't reenable LSC while waiting for link */
2103 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2104 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2105
2c4af694 2106 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2107 switch (adapter->hw.mac.type) {
2108 case ixgbe_mac_82599EB:
2109 mask |= IXGBE_EIMS_GPI_SDP0;
2110 break;
2111 case ixgbe_mac_X540:
2112 mask |= IXGBE_EIMS_TS;
2113 break;
2114 default:
2115 break;
2116 }
2c4af694
AD		 2117 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2118 mask |= IXGBE_EIMS_GPI_SDP1;
2119 switch (adapter->hw.mac.type) {
2120 case ixgbe_mac_82599EB:
2c4af694
AD		 2121 mask |= IXGBE_EIMS_GPI_SDP1;
2122 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2123 case ixgbe_mac_X540:
2124 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2125 mask |= IXGBE_EIMS_MAILBOX;
2126 break;
2127 default:
2128 break;
9a799d71 2129 }
2c4af694
AD		 2130 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2131 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2132 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2133
2c4af694
AD		 2134 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2135 if (queues)
2136 ixgbe_irq_enable_queues(adapter, ~0);
2137 if (flush)
2138 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2139}
2140
2c4af694 2141static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2142{
a65151ba 2143 struct ixgbe_adapter *adapter = data;
9a799d71 2144 struct ixgbe_hw *hw = &adapter->hw;
54037505 2145 u32 eicr;
91281fd3 2146
54037505
DS		 2147 /*
2148 * Workaround for Silicon errata. Use clear-by-write instead
2149 * of clear-by-read. Reading with EICS will return the
2150 * interrupt causes without clearing, which later be done
2151 * with the write to EICR.
2152 */
2153 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2154 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2155
cf8280ee
JB		 2156 if (eicr & IXGBE_EICR_LSC)
2157 ixgbe_check_lsc(adapter);
f0848276 2158
1cdd1ec8
GR		 2159 if (eicr & IXGBE_EICR_MAILBOX)
2160 ixgbe_msg_task(adapter);
efe3d3c8 2161
bd508178
AD		 2162 switch (hw->mac.type) {
2163 case ixgbe_mac_82599EB:
b93a2226 2164 case ixgbe_mac_X540:
2c4af694
AD		 2165 if (eicr & IXGBE_EICR_ECC)
2166 e_info(link, "Received unrecoverable ECC Err, please "
2167 "reboot\n");
c4cf55e5
PWJ		 2168 /* Handle Flow Director Full threshold interrupt */
2169 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2170 int reinit_count = 0;
c4cf55e5 2171 int i;
c4cf55e5 2172 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2173 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2174 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2175 &ring->state))
2176 reinit_count++;
2177 }
2178 if (reinit_count) {
2179 /* no more flow director interrupts until after init */
2180 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2181 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2182 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2183 }
2184 }
f0f9778d 2185 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2186 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2187 break;
2188 default:
2189 break;
c4cf55e5 2190 }
f0848276 2191
bd508178 2192 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 2193
7086400d 2194 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2195 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2196 ixgbe_irq_enable(adapter, false, false);
f0848276 2197
9a799d71 2198 return IRQ_HANDLED;
f0848276 2199}
91281fd3 2200
4ff7fb12 2201static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2202{
021230d4 2203 struct ixgbe_q_vector *q_vector = data;
91281fd3 2204
9b471446 2205 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2206
4ff7fb12
AD		 2207 if (q_vector->rx.ring || q_vector->tx.ring)
2208 napi_schedule(&q_vector->napi);
91281fd3 2209
9a799d71 2210 return IRQ_HANDLED;
91281fd3
AD		 2211}
2212
021230d4
AV		 2213/**
2214 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2215 * @adapter: board private structure
2216 *
2217 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2218 * interrupts from the kernel.
2219 **/
2220static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2221{
2222 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2223 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2224 int vector, err;
e8e9f696 2225 int ri = 0, ti = 0;
021230d4 2226
021230d4 2227 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2228 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2229 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2230
4ff7fb12 2231 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2232 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2233 "%s-%s-%d", netdev->name, "TxRx", ri++);
2234 ti++;
2235 } else if (q_vector->rx.ring) {
9fe93afd 2236 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2237 "%s-%s-%d", netdev->name, "rx", ri++);
2238 } else if (q_vector->tx.ring) {
9fe93afd 2239 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2240 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2241 } else {
2242 /* skip this unused q_vector */
2243 continue;
32aa77a4 2244 }
207867f5
AD		 2245 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2246 q_vector->name, q_vector);
9a799d71 2247 if (err) {
396e799c 2248 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2249 "Error: %d\n", err);
021230d4 2250 goto free_queue_irqs;
9a799d71 2251 }
207867f5
AD		 2252 /* If Flow Director is enabled, set interrupt affinity */
2253 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2254 /* assign the mask for this irq */
2255 irq_set_affinity_hint(entry->vector,
de88eeeb 2256 &q_vector->affinity_mask);
207867f5 2257 }
9a799d71
AK		 2258 }
2259
021230d4 2260 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2261 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2262 if (err) {
de88eeeb 2263 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2264 goto free_queue_irqs;
9a799d71
AK		 2265 }
2266
9a799d71
AK		 2267 return 0;
2268
021230d4 2269free_queue_irqs:
207867f5
AD		 2270 while (vector) {
2271 vector--;
2272 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2273 NULL);
2274 free_irq(adapter->msix_entries[vector].vector,
2275 adapter->q_vector[vector]);
2276 }
021230d4
AV		 2277 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2278 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2279 kfree(adapter->msix_entries);
2280 adapter->msix_entries = NULL;
9a799d71
AK		 2281 return err;
2282}
2283
2284/**
021230d4 2285 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2286 * @irq: interrupt number
2287 * @data: pointer to a network interface device structure
9a799d71
AK		 2288 **/
2289static irqreturn_t ixgbe_intr(int irq, void *data)
2290{
a65151ba 2291 struct ixgbe_adapter *adapter = data;
9a799d71 2292 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2293 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2294 u32 eicr;
2295
54037505 2296 /*
24ddd967 2297 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2298 * before the read of EICR.
2299 */
2300 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2301
021230d4 2302 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2303 * therefore no explicit interrupt disable is necessary */
021230d4 2304 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2305 if (!eicr) {
6af3b9eb
ET		 2306 /*
2307 * shared interrupt alert!
f47cf66e 2308 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2309 * have disabled interrupts due to EIAM
2310 * finish the workaround of silicon errata on 82598. Unmask
2311 * the interrupt that we masked before the EICR read.
2312 */
2313 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2314 ixgbe_irq_enable(adapter, true, true);
9a799d71 2315 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2316 }
9a799d71 2317
cf8280ee
JB		 2318 if (eicr & IXGBE_EICR_LSC)
2319 ixgbe_check_lsc(adapter);
021230d4 2320
bd508178
AD		 2321 switch (hw->mac.type) {
2322 case ixgbe_mac_82599EB:
e8e26350 2323 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2324 /* Fall through */
2325 case ixgbe_mac_X540:
2326 if (eicr & IXGBE_EICR_ECC)
2327 e_info(link, "Received unrecoverable ECC err, please "
2328 "reboot\n");
4f51bf70 2329 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2330 break;
2331 default:
2332 break;
2333 }
e8e26350 2334
0befdb3e
JB		 2335 ixgbe_check_fan_failure(adapter, eicr);
2336
b9f6ed2b
AD		 2337 /* would disable interrupts here but EIAM disabled it */
2338 napi_schedule(&q_vector->napi);
9a799d71 2339
6af3b9eb
ET		 2340 /*
2341 * re-enable link(maybe) and non-queue interrupts, no flush.
2342 * ixgbe_poll will re-enable the queue interrupts
2343 */
6af3b9eb
ET		 2344 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2345 ixgbe_irq_enable(adapter, false, false);
2346
9a799d71
AK		 2347 return IRQ_HANDLED;
2348}
2349
2350/**
2351 * ixgbe_request_irq - initialize interrupts
2352 * @adapter: board private structure
2353 *
2354 * Attempts to configure interrupts using the best available
2355 * capabilities of the hardware and kernel.
2356 **/
021230d4 2357static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2358{
2359 struct net_device *netdev = adapter->netdev;
021230d4 2360 int err;
9a799d71 2361
4cc6df29 2362 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2363 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2364 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2365 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2366 netdev->name, adapter);
4cc6df29 2367 else
a0607fd3 2368 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2369 netdev->name, adapter);
9a799d71 2370
de88eeeb 2371 if (err)
396e799c 2372 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2373
9a799d71
AK		 2374 return err;
2375}
2376
2377static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2378{
9a799d71 2379 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2380 int i, q_vectors;
9a799d71 2381
021230d4 2382 q_vectors = adapter->num_msix_vectors;
021230d4 2383 i = q_vectors - 1;
a65151ba 2384 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2385 i--;
4cc6df29 2386
021230d4 2387 for (; i >= 0; i--) {
894ff7cf 2388 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2389 if (!adapter->q_vector[i]->rx.ring &&
2390 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2391 continue;
2392
207867f5
AD		 2393 /* clear the affinity_mask in the IRQ descriptor */
2394 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2395 NULL);
2396
021230d4 2397 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2398 adapter->q_vector[i]);
021230d4 2399 }
021230d4 2400 } else {
a65151ba 2401 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2402 }
2403}
2404
22d5a71b
JB		 2405/**
2406 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2407 * @adapter: board private structure
2408 **/
2409static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2410{
bd508178
AD		 2411 switch (adapter->hw.mac.type) {
2412 case ixgbe_mac_82598EB:
835462fc 2413 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2414 break;
2415 case ixgbe_mac_82599EB:
b93a2226 2416 case ixgbe_mac_X540:
835462fc
NS		 2417 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2418 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2419 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2420 break;
2421 default:
2422 break;
22d5a71b
JB		 2423 }
2424 IXGBE_WRITE_FLUSH(&adapter->hw);
2425 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2426 int i;
2427 for (i = 0; i < adapter->num_msix_vectors; i++)
2428 synchronize_irq(adapter->msix_entries[i].vector);
2429 } else {
2430 synchronize_irq(adapter->pdev->irq);
2431 }
2432}
2433
9a799d71
AK		 2434/**
2435 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2436 *
2437 **/
2438static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2439{
d5bf4f67 2440 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2441
d5bf4f67
ET		 2442 /* rx/tx vector */
2443 if (adapter->rx_itr_setting == 1)
2444 q_vector->itr = IXGBE_20K_ITR;
2445 else
2446 q_vector->itr = adapter->rx_itr_setting;
2447
2448 ixgbe_write_eitr(q_vector);
9a799d71 2449
e8e26350
PW		 2450 ixgbe_set_ivar(adapter, 0, 0, 0);
2451 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2452
396e799c 2453 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2454}
2455
43e69bf0
AD		 2456/**
2457 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2458 * @adapter: board private structure
2459 * @ring: structure containing ring specific data
2460 *
2461 * Configure the Tx descriptor ring after a reset.
2462 **/
84418e3b
AD		 2463void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2464 struct ixgbe_ring *ring)
43e69bf0
AD		 2465{
2466 struct ixgbe_hw *hw = &adapter->hw;
2467 u64 tdba = ring->dma;
2f1860b8 2468 int wait_loop = 10;
b88c6de2 2469 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2470 u8 reg_idx = ring->reg_idx;
43e69bf0 2471
2f1860b8 2472 /* disable queue to avoid issues while updating state */
b88c6de2 2473 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2474 IXGBE_WRITE_FLUSH(hw);
2475
43e69bf0 2476 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2477 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2478 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2479 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2480 ring->count * sizeof(union ixgbe_adv_tx_desc));
2481 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2482 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2483 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2484
b88c6de2
AD		 2485 /*
2486 * set WTHRESH to encourage burst writeback, it should not be set
2487 * higher than 1 when ITR is 0 as it could cause false TX hangs
2488 *
2489 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2490 * to or less than the number of on chip descriptors, which is
2491 * currently 40.
2492 */
e954b374 2493 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2494 txdctl |= (1 << 16); /* WTHRESH = 1 */
2495 else
2496 txdctl |= (8 << 16); /* WTHRESH = 8 */
2497
e954b374
AD		 2498 /*
2499 * Setting PTHRESH to 32 both improves performance
2500 * and avoids a TX hang with DFP enabled
2501 */
b88c6de2
AD		 2502 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2503 32; /* PTHRESH = 32 */
2f1860b8
AD		 2504
2505 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2506 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2507 adapter->atr_sample_rate) {
2508 ring->atr_sample_rate = adapter->atr_sample_rate;
2509 ring->atr_count = 0;
2510 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2511 } else {
2512 ring->atr_sample_rate = 0;
2513 }
2f1860b8 2514
c84d324c
JF		 2515 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2516
2f1860b8 2517 /* enable queue */
2f1860b8
AD		 2518 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2519
b2d96e0a
AD		 2520 netdev_tx_reset_queue(txring_txq(ring));
2521
2f1860b8
AD		 2522 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2523 if (hw->mac.type == ixgbe_mac_82598EB &&
2524 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2525 return;
2526
2527 /* poll to verify queue is enabled */
2528 do {
032b4325 2529 usleep_range(1000, 2000);
2f1860b8
AD		 2530 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2531 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2532 if (!wait_loop)
2533 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2534}
2535
120ff942
AD		 2536static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2537{
2538 struct ixgbe_hw *hw = &adapter->hw;
2539 u32 rttdcs;
72a32f1f 2540 u32 reg;
8b1c0b24 2541 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2542
2543 if (hw->mac.type == ixgbe_mac_82598EB)
2544 return;
2545
2546 /* disable the arbiter while setting MTQC */
2547 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2548 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2549 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2550
2551 /* set transmit pool layout */
8b1c0b24 2552 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2553 case (IXGBE_FLAG_SRIOV_ENABLED):
2554 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2555 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2556 break;
8b1c0b24
JF		 2557 default:
2558 if (!tcs)
2559 reg = IXGBE_MTQC_64Q_1PB;
2560 else if (tcs <= 4)
2561 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2562 else
2563 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2564
8b1c0b24 2565 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2566
8b1c0b24
JF		 2567 /* Enable Security TX Buffer IFG for multiple pb */
2568 if (tcs) {
2569 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2570 reg |= IXGBE_SECTX_DCB;
2571 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2572 }
120ff942
AD		 2573 break;
2574 }
2575
2576 /* re-enable the arbiter */
2577 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2578 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2579}
2580
9a799d71 2581/**
3a581073 2582 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2583 * @adapter: board private structure
2584 *
2585 * Configure the Tx unit of the MAC after a reset.
2586 **/
2587static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2588{
2f1860b8
AD		 2589 struct ixgbe_hw *hw = &adapter->hw;
2590 u32 dmatxctl;
43e69bf0 2591 u32 i;
9a799d71 2592
2f1860b8
AD		 2593 ixgbe_setup_mtqc(adapter);
2594
2595 if (hw->mac.type != ixgbe_mac_82598EB) {
2596 /* DMATXCTL.EN must be before Tx queues are enabled */
2597 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2598 dmatxctl |= IXGBE_DMATXCTL_TE;
2599 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2600 }
2601
9a799d71 2602 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2603 for (i = 0; i < adapter->num_tx_queues; i++)
2604 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2605}
2606
e8e26350 2607#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2608
a6616b42 2609static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2610 struct ixgbe_ring *rx_ring)
cc41ac7c 2611{
cc41ac7c 2612 u32 srrctl;
bf29ee6c 2613 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2614
bd508178
AD		 2615 switch (adapter->hw.mac.type) {
2616 case ixgbe_mac_82598EB: {
2617 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2618 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2619 reg_idx = reg_idx & mask;
cc41ac7c 2620 }
bd508178
AD		 2621 break;
2622 case ixgbe_mac_82599EB:
b93a2226 2623 case ixgbe_mac_X540:
bd508178
AD		 2624 default:
2625 break;
2626 }
2627
bf29ee6c 2628 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2629
2630 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2631 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2632 if (adapter->num_vfs)
2633 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2634
afafd5b0
AD		 2635 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2636 IXGBE_SRRCTL_BSIZEHDR_MASK;
2637
7d637bcc 2638 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2639#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2640 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2641#else
2642 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2643#endif
cc41ac7c 2644 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2645 } else {
afafd5b0
AD		 2646 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2647 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2648 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2649 }
e8e26350 2650
bf29ee6c 2651 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2652}
9a799d71 2653
05abb126 2654static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2655{
05abb126
AD		 2656 struct ixgbe_hw *hw = &adapter->hw;
2657 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2658 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2659 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2660 u32 mrqc = 0, reta = 0;
2661 u32 rxcsum;
2662 int i, j;
8b1c0b24 2663 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2664 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2665
2666 if (tcs)
2667 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2668
05abb126
AD		 2669 /* Fill out hash function seeds */
2670 for (i = 0; i < 10; i++)
2671 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2672
2673 /* Fill out redirection table */
2674 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2675 if (j == maxq)
05abb126
AD		 2676 j = 0;
2677 /* reta = 4-byte sliding window of
2678 * 0x00..(indices-1)(indices-1)00..etc. */
2679 reta = (reta << 8) | (j * 0x11);
2680 if ((i & 3) == 3)
2681 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2682 }
0cefafad 2683
05abb126
AD		 2684 /* Disable indicating checksum in descriptor, enables RSS hash */
2685 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2686 rxcsum |= IXGBE_RXCSUM_PCSD;
2687 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2688
8b1c0b24
JF		 2689 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2690 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2691 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2692 } else {
2693 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2694 | IXGBE_FLAG_SRIOV_ENABLED);
2695
2696 switch (mask) {
2697 case (IXGBE_FLAG_RSS_ENABLED):
2698 if (!tcs)
2699 mrqc = IXGBE_MRQC_RSSEN;
2700 else if (tcs <= 4)
2701 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2702 else
2703 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2704 break;
2705 case (IXGBE_FLAG_SRIOV_ENABLED):
2706 mrqc = IXGBE_MRQC_VMDQEN;
2707 break;
2708 default:
2709 break;
2710 }
0cefafad
JB		 2711 }
2712
05abb126
AD		 2713 /* Perform hash on these packet types */
2714 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2715 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2716 | IXGBE_MRQC_RSS_FIELD_IPV6
2717 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2718
2719 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2720}
2721
bb5a9ad2
NS		 2722/**
2723 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2724 * @adapter: address of board private structure
2725 * @index: index of ring to set
bb5a9ad2 2726 **/
082757af 2727static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2728 struct ixgbe_ring *ring)
bb5a9ad2 2729{
bb5a9ad2 2730 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2731 u32 rscctrl;
edd2ea55 2732 int rx_buf_len;
bf29ee6c 2733 u8 reg_idx = ring->reg_idx;
7367096a 2734
7d637bcc 2735 if (!ring_is_rsc_enabled(ring))
7367096a 2736 return;
bb5a9ad2 2737
7367096a
AD		 2738 rx_buf_len = ring->rx_buf_len;
2739 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2740 rscctrl |= IXGBE_RSCCTL_RSCEN;
2741 /*
2742 * we must limit the number of descriptors so that the
2743 * total size of max desc * buf_len is not greater
642c680e 2744 * than 65536
bb5a9ad2 2745 */
7d637bcc 2746 if (ring_is_ps_enabled(ring)) {
642c680e 2747#if (PAGE_SIZE < 8192)
bb5a9ad2 2748 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
642c680e 2749#elif (PAGE_SIZE < 16384)
bb5a9ad2 2750 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
642c680e 2751#elif (PAGE_SIZE < 32768)
bb5a9ad2
NS		 2752 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2753#else
2754 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2755#endif
2756 } else {
642c680e 2757 if (rx_buf_len <= IXGBE_RXBUFFER_4K)
bb5a9ad2 2758 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
642c680e 2759 else if (rx_buf_len <= IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2760 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2761 else
2762 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2763 }
7367096a 2764 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2765}
2766
9e10e045
AD		 2767/**
2768 * ixgbe_set_uta - Set unicast filter table address
2769 * @adapter: board private structure
2770 *
2771 * The unicast table address is a register array of 32-bit registers.
2772 * The table is meant to be used in a way similar to how the MTA is used
2773 * however due to certain limitations in the hardware it is necessary to
2774 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2775 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2776 **/
2777static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2778{
2779 struct ixgbe_hw *hw = &adapter->hw;
2780 int i;
2781
2782 /* The UTA table only exists on 82599 hardware and newer */
2783 if (hw->mac.type < ixgbe_mac_82599EB)
2784 return;
2785
2786 /* we only need to do this if VMDq is enabled */
2787 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2788 return;
2789
2790 for (i = 0; i < 128; i++)
2791 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2792}
2793
2794#define IXGBE_MAX_RX_DESC_POLL 10
2795static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2796 struct ixgbe_ring *ring)
2797{
2798 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2799 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2800 u32 rxdctl;
bf29ee6c 2801 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2802
2803 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2804 if (hw->mac.type == ixgbe_mac_82598EB &&
2805 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2806 return;
2807
2808 do {
032b4325 2809 usleep_range(1000, 2000);
9e10e045
AD		 2810 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2811 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2812
2813 if (!wait_loop) {
2814 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2815 "the polling period\n", reg_idx);
2816 }
2817}
2818
2d39d576
YZ		 2819void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2820 struct ixgbe_ring *ring)
2821{
2822 struct ixgbe_hw *hw = &adapter->hw;
2823 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2824 u32 rxdctl;
2825 u8 reg_idx = ring->reg_idx;
2826
2827 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2828 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2829
2830 /* write value back with RXDCTL.ENABLE bit cleared */
2831 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2832
2833 if (hw->mac.type == ixgbe_mac_82598EB &&
2834 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2835 return;
2836
2837 /* the hardware may take up to 100us to really disable the rx queue */
2838 do {
2839 udelay(10);
2840 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2841 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2842
2843 if (!wait_loop) {
2844 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2845 "the polling period\n", reg_idx);
2846 }
2847}
2848
84418e3b
AD		 2849void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2850 struct ixgbe_ring *ring)
acd37177
AD		 2851{
2852 struct ixgbe_hw *hw = &adapter->hw;
2853 u64 rdba = ring->dma;
9e10e045 2854 u32 rxdctl;
bf29ee6c 2855 u8 reg_idx = ring->reg_idx;
acd37177 2856
9e10e045
AD		 2857 /* disable queue to avoid issues while updating state */
2858 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2859 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2860
acd37177
AD		 2861 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2862 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2863 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2864 ring->count * sizeof(union ixgbe_adv_rx_desc));
2865 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2866 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2867 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2868
2869 ixgbe_configure_srrctl(adapter, ring);
2870 ixgbe_configure_rscctl(adapter, ring);
2871
e9f98072
GR		 2872 /* If operating in IOV mode set RLPML for X540 */
2873 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2874 hw->mac.type == ixgbe_mac_X540) {
2875 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2876 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2877 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2878 }
2879
9e10e045
AD		 2880 if (hw->mac.type == ixgbe_mac_82598EB) {
2881 /*
2882 * enable cache line friendly hardware writes:
2883 * PTHRESH=32 descriptors (half the internal cache),
2884 * this also removes ugly rx_no_buffer_count increment
2885 * HTHRESH=4 descriptors (to minimize latency on fetch)
2886 * WTHRESH=8 burst writeback up to two cache lines
2887 */
2888 rxdctl &= ~0x3FFFFF;
2889 rxdctl |= 0x080420;
2890 }
2891
2892 /* enable receive descriptor ring */
2893 rxdctl |= IXGBE_RXDCTL_ENABLE;
2894 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2895
2896 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2897 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2898}
2899
48654521
AD		 2900static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2901{
2902 struct ixgbe_hw *hw = &adapter->hw;
2903 int p;
2904
2905 /* PSRTYPE must be initialized in non 82598 adapters */
2906 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2907 IXGBE_PSRTYPE_UDPHDR |
2908 IXGBE_PSRTYPE_IPV4HDR |
48654521 2909 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2910 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2911
2912 if (hw->mac.type == ixgbe_mac_82598EB)
2913 return;
2914
2915 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2916 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2917
2918 for (p = 0; p < adapter->num_rx_pools; p++)
2919 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2920 psrtype);
2921}
2922
f5b4a52e
AD		 2923static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2924{
2925 struct ixgbe_hw *hw = &adapter->hw;
2926 u32 gcr_ext;
2927 u32 vt_reg_bits;
2928 u32 reg_offset, vf_shift;
2929 u32 vmdctl;
de4c7f65 2930 int i;
f5b4a52e
AD		 2931
2932 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2933 return;
2934
2935 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2936 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2937 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2938 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2939
2940 vf_shift = adapter->num_vfs % 32;
4cd6923d 2941 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 2942
2943 /* Enable only the PF's pool for Tx/Rx */
2944 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2945 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2946 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2947 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2948 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2949
2950 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2951 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2952
2953 /*
2954 * Set up VF register offsets for selected VT Mode,
2955 * i.e. 32 or 64 VFs for SR-IOV
2956 */
2957 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2958 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2959 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2960 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2961
2962 /* enable Tx loopback for VF/PF communication */
2963 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2964 /* Enable MAC Anti-Spoofing */
a1cbb15c 2965 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 2966 (adapter->num_vfs != 0),
a985b6c3 2967 adapter->num_vfs);
de4c7f65
GR		 2968 /* For VFs that have spoof checking turned off */
2969 for (i = 0; i < adapter->num_vfs; i++) {
2970 if (!adapter->vfinfo[i].spoofchk_enabled)
2971 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2972 }
f5b4a52e
AD		 2973}
2974
477de6ed 2975static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2976{
9a799d71
AK		 2977 struct ixgbe_hw *hw = &adapter->hw;
2978 struct net_device *netdev = adapter->netdev;
2979 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2980 int rx_buf_len;
477de6ed
AD		 2981 struct ixgbe_ring *rx_ring;
2982 int i;
2983 u32 mhadd, hlreg0;
48654521 2984
9a799d71 2985 /* Decide whether to use packet split mode or not */
a124339a
DS		 2986 /* On by default */
2987 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2988
1cdd1ec8 2989 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2990 if (adapter->num_vfs)
2991 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2992
2993 /* Disable packet split due to 82599 erratum #45 */
2994 if (hw->mac.type == ixgbe_mac_82599EB)
2995 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2996
63f39bd1 2997#ifdef IXGBE_FCOE
477de6ed
AD		 2998 /* adjust max frame to be able to do baby jumbo for FCoE */
2999 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3000 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3001 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3002
477de6ed
AD		 3003#endif /* IXGBE_FCOE */
3004 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3005 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3006 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3007 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3008
3009 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3010 }
3011
919e78a6
AD		 3012 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3013 max_frame += VLAN_HLEN;
3014
3015 /* Set the RX buffer length according to the mode */
3016 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3017 rx_buf_len = IXGBE_RX_HDR_SIZE;
3018 } else {
3019 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3020 (netdev->mtu <= ETH_DATA_LEN))
3021 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3022 /*
3023 * Make best use of allocation by using all but 1K of a
3024 * power of 2 allocation that will be used for skb->head.
3025 */
3026 else if (max_frame <= IXGBE_RXBUFFER_3K)
3027 rx_buf_len = IXGBE_RXBUFFER_3K;
3028 else if (max_frame <= IXGBE_RXBUFFER_7K)
3029 rx_buf_len = IXGBE_RXBUFFER_7K;
3030 else if (max_frame <= IXGBE_RXBUFFER_15K)
3031 rx_buf_len = IXGBE_RXBUFFER_15K;
3032 else
3033 rx_buf_len = IXGBE_MAX_RXBUFFER;
3034 }
3035
477de6ed
AD		 3036 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3037 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3038 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3039 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3040
0cefafad
JB		 3041 /*
3042 * Setup the HW Rx Head and Tail Descriptor Pointers and
3043 * the Base and Length of the Rx Descriptor Ring
3044 */
9a799d71 3045 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3046 rx_ring = adapter->rx_ring[i];
a6616b42 3047 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3048
6e455b89 3049 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3050 set_ring_ps_enabled(rx_ring);
3051 else
3052 clear_ring_ps_enabled(rx_ring);
3053
3054 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3055 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3056 else
7d637bcc 3057 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3058
63f39bd1 3059#ifdef IXGBE_FCOE
e8e9f696 3060 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3061 struct ixgbe_ring_feature *f;
3062 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3063 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3064 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3065 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3066 rx_ring->rx_buf_len =
e8e9f696 3067 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3068 } else if (!ring_is_rsc_enabled(rx_ring) &&
3069 !ring_is_ps_enabled(rx_ring)) {
3070 rx_ring->rx_buf_len =
3071 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3072 }
63f39bd1 3073 }
63f39bd1 3074#endif /* IXGBE_FCOE */
477de6ed 3075 }
477de6ed
AD		 3076}
3077
7367096a
AD		 3078static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3079{
3080 struct ixgbe_hw *hw = &adapter->hw;
3081 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3082
3083 switch (hw->mac.type) {
3084 case ixgbe_mac_82598EB:
3085 /*
3086 * For VMDq support of different descriptor types or
3087 * buffer sizes through the use of multiple SRRCTL
3088 * registers, RDRXCTL.MVMEN must be set to 1
3089 *
3090 * also, the manual doesn't mention it clearly but DCA hints
3091 * will only use queue 0's tags unless this bit is set. Side
3092 * effects of setting this bit are only that SRRCTL must be
3093 * fully programmed [0..15]
3094 */
3095 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3096 break;
3097 case ixgbe_mac_82599EB:
b93a2226 3098 case ixgbe_mac_X540:
7367096a
AD		 3099 /* Disable RSC for ACK packets */
3100 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3101 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3102 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3103 /* hardware requires some bits to be set by default */
3104 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3105 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3106 break;
3107 default:
3108 /* We should do nothing since we don't know this hardware */
3109 return;
3110 }
3111
3112 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3113}
3114
477de6ed
AD		 3115/**
3116 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3117 * @adapter: board private structure
3118 *
3119 * Configure the Rx unit of the MAC after a reset.
3120 **/
3121static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3122{
3123 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3124 int i;
3125 u32 rxctrl;
477de6ed
AD		 3126
3127 /* disable receives while setting up the descriptors */
3128 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3129 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3130
3131 ixgbe_setup_psrtype(adapter);
7367096a 3132 ixgbe_setup_rdrxctl(adapter);
477de6ed 3133
9e10e045 3134 /* Program registers for the distribution of queues */
f5b4a52e 3135 ixgbe_setup_mrqc(adapter);
f5b4a52e 3136
9e10e045
AD		 3137 ixgbe_set_uta(adapter);
3138
477de6ed
AD		 3139 /* set_rx_buffer_len must be called before ring initialization */
3140 ixgbe_set_rx_buffer_len(adapter);
3141
3142 /*
3143 * Setup the HW Rx Head and Tail Descriptor Pointers and
3144 * the Base and Length of the Rx Descriptor Ring
3145 */
9e10e045
AD		 3146 for (i = 0; i < adapter->num_rx_queues; i++)
3147 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3148
9e10e045
AD		 3149 /* disable drop enable for 82598 parts */
3150 if (hw->mac.type == ixgbe_mac_82598EB)
3151 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3152
3153 /* enable all receives */
3154 rxctrl |= IXGBE_RXCTRL_RXEN;
3155 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3156}
3157
8e586137 3158static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3159{
3160 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3161 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3162 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3163
3164 /* add VID to filter table */
1ada1b1b 3165 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3166 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3167
3168 return 0;
068c89b0
DS		 3169}
3170
8e586137 3171static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3172{
3173 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3174 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3175 int pool_ndx = adapter->num_vfs;
068c89b0 3176
068c89b0 3177 /* remove VID from filter table */
1ada1b1b 3178 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3179 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3180
3181 return 0;
068c89b0
DS		 3182}
3183
5f6c0181
JB		 3184/**
3185 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3186 * @adapter: driver data
3187 */
3188static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3189{
3190 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3191 u32 vlnctrl;
3192
3193 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3194 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3195 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3196}
3197
3198/**
3199 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3200 * @adapter: driver data
3201 */
3202static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3203{
3204 struct ixgbe_hw *hw = &adapter->hw;
3205 u32 vlnctrl;
3206
3207 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3208 vlnctrl |= IXGBE_VLNCTRL_VFE;
3209 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3210 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3211}
3212
3213/**
3214 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3215 * @adapter: driver data
3216 */
3217static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3218{
3219 struct ixgbe_hw *hw = &adapter->hw;
3220 u32 vlnctrl;
5f6c0181
JB		 3221 int i, j;
3222
3223 switch (hw->mac.type) {
3224 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3225 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3226 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3227 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3228 break;
3229 case ixgbe_mac_82599EB:
b93a2226 3230 case ixgbe_mac_X540:
5f6c0181
JB		 3231 for (i = 0; i < adapter->num_rx_queues; i++) {
3232 j = adapter->rx_ring[i]->reg_idx;
3233 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3234 vlnctrl &= ~IXGBE_RXDCTL_VME;
3235 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3236 }
3237 break;
3238 default:
3239 break;
3240 }
3241}
3242
3243/**
f62bbb5e 3244 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3245 * @adapter: driver data
3246 */
f62bbb5e 3247static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3248{
3249 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3250 u32 vlnctrl;
5f6c0181
JB		 3251 int i, j;
3252
3253 switch (hw->mac.type) {
3254 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3255 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3256 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3257 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3258 break;
3259 case ixgbe_mac_82599EB:
b93a2226 3260 case ixgbe_mac_X540:
5f6c0181
JB		 3261 for (i = 0; i < adapter->num_rx_queues; i++) {
3262 j = adapter->rx_ring[i]->reg_idx;
3263 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3264 vlnctrl |= IXGBE_RXDCTL_VME;
3265 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3266 }
3267 break;
3268 default:
3269 break;
3270 }
3271}
3272
9a799d71
AK		 3273static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3274{
f62bbb5e 3275 u16 vid;
9a799d71 3276
f62bbb5e
JG		 3277 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3278
3279 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3280 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3281}
3282
2850062a
AD		 3283/**
3284 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3285 * @netdev: network interface device structure
3286 *
3287 * Writes unicast address list to the RAR table.
3288 * Returns: -ENOMEM on failure/insufficient address space
3289 * 0 on no addresses written
3290 * X on writing X addresses to the RAR table
3291 **/
3292static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3293{
3294 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3295 struct ixgbe_hw *hw = &adapter->hw;
3296 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3297 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3298 int count = 0;
3299
3300 /* return ENOMEM indicating insufficient memory for addresses */
3301 if (netdev_uc_count(netdev) > rar_entries)
3302 return -ENOMEM;
3303
3304 if (!netdev_uc_empty(netdev) && rar_entries) {
3305 struct netdev_hw_addr *ha;
3306 /* return error if we do not support writing to RAR table */
3307 if (!hw->mac.ops.set_rar)
3308 return -ENOMEM;
3309
3310 netdev_for_each_uc_addr(ha, netdev) {
3311 if (!rar_entries)
3312 break;
3313 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3314 vfn, IXGBE_RAH_AV);
3315 count++;
3316 }
3317 }
3318 /* write the addresses in reverse order to avoid write combining */
3319 for (; rar_entries > 0 ; rar_entries--)
3320 hw->mac.ops.clear_rar(hw, rar_entries);
3321
3322 return count;
3323}
3324
9a799d71 3325/**
2c5645cf 3326 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3327 * @netdev: network interface device structure
3328 *
2c5645cf
CL		 3329 * The set_rx_method entry point is called whenever the unicast/multicast
3330 * address list or the network interface flags are updated. This routine is
3331 * responsible for configuring the hardware for proper unicast, multicast and
3332 * promiscuous mode.
9a799d71 3333 **/
7f870475 3334void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3335{
3336 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3337 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3338 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3339 int count;
9a799d71
AK		 3340
3341 /* Check for Promiscuous and All Multicast modes */
3342
3343 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3344
f5dc442b 3345 /* set all bits that we expect to always be set */
3f2d1c0f 3346 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3347 fctrl |= IXGBE_FCTRL_BAM;
3348 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3349 fctrl |= IXGBE_FCTRL_PMCF;
3350
2850062a
AD		 3351 /* clear the bits we are changing the status of */
3352 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3353
9a799d71 3354 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3355 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3356 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3357 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3358 /* don't hardware filter vlans in promisc mode */
3359 ixgbe_vlan_filter_disable(adapter);
9a799d71 3360 } else {
746b9f02
PM		 3361 if (netdev->flags & IFF_ALLMULTI) {
3362 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3363 vmolr |= IXGBE_VMOLR_MPE;
3364 } else {
3365 /*
3366 * Write addresses to the MTA, if the attempt fails
25985edc 3367 * then we should just turn on promiscuous mode so
2850062a
AD		 3368 * that we can at least receive multicast traffic
3369 */
3370 hw->mac.ops.update_mc_addr_list(hw, netdev);
3371 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3372 }
5f6c0181 3373 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3374 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3375 /*
3376 * Write addresses to available RAR registers, if there is not
3377 * sufficient space to store all the addresses then enable
25985edc 3378 * unicast promiscuous mode
2850062a
AD		 3379 */
3380 count = ixgbe_write_uc_addr_list(netdev);
3381 if (count < 0) {
3382 fctrl |= IXGBE_FCTRL_UPE;
3383 vmolr |= IXGBE_VMOLR_ROPE;
3384 }
9a799d71
AK		 3385 }
3386
2850062a 3387 if (adapter->num_vfs) {
1cdd1ec8 3388 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3389 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3390 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3391 IXGBE_VMOLR_ROPE);
3392 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3393 }
3394
3f2d1c0f
BG		 3395 /* This is useful for sniffing bad packets. */
3396 if (adapter->netdev->features & NETIF_F_RXALL) {
3397 /* UPE and MPE will be handled by normal PROMISC logic
3398 * in e1000e_set_rx_mode */
3399 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3400 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3401 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3402
3403 fctrl &= ~(IXGBE_FCTRL_DPF);
3404 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3405 }
3406
2850062a 3407 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3408
3409 if (netdev->features & NETIF_F_HW_VLAN_RX)
3410 ixgbe_vlan_strip_enable(adapter);
3411 else
3412 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3413}
3414
021230d4
AV		 3415static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3416{
3417 int q_idx;
3418 struct ixgbe_q_vector *q_vector;
3419 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3420
3421 /* legacy and MSI only use one vector */
3422 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3423 q_vectors = 1;
3424
3425 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3426 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3427 napi_enable(&q_vector->napi);
021230d4
AV		 3428 }
3429}
3430
3431static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3432{
3433 int q_idx;
3434 struct ixgbe_q_vector *q_vector;
3435 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3436
3437 /* legacy and MSI only use one vector */
3438 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3439 q_vectors = 1;
3440
3441 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3442 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3443 napi_disable(&q_vector->napi);
3444 }
3445}
3446
7a6b6f51 3447#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3448/*
3449 * ixgbe_configure_dcb - Configure DCB hardware
3450 * @adapter: ixgbe adapter struct
3451 *
3452 * This is called by the driver on open to configure the DCB hardware.
3453 * This is also called by the gennetlink interface when reconfiguring
3454 * the DCB state.
3455 */
3456static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3457{
3458 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3459 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3460
67ebd791
AD		 3461 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3462 if (hw->mac.type == ixgbe_mac_82598EB)
3463 netif_set_gso_max_size(adapter->netdev, 65536);
3464 return;
3465 }
3466
3467 if (hw->mac.type == ixgbe_mac_82598EB)
3468 netif_set_gso_max_size(adapter->netdev, 32768);
3469
2f90b865 3470
2f90b865 3471 /* Enable VLAN tag insert/strip */
f62bbb5e 3472 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3473
2f90b865 3474 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3475
971060b1 3476#ifdef IXGBE_FCOE
b120818e
JF		 3477 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3478 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3479#endif
b120818e
JF		 3480
3481 /* reconfigure the hardware */
3482 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3483 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3484 DCB_TX_CONFIG);
3485 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3486 DCB_RX_CONFIG);
3487 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3488 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3489 ixgbe_dcb_hw_ets(&adapter->hw,
3490 adapter->ixgbe_ieee_ets,
3491 max_frame);
3492 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3493 adapter->ixgbe_ieee_pfc->pfc_en,
3494 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3495 }
8187cd48
JF		 3496
3497 /* Enable RSS Hash per TC */
3498 if (hw->mac.type != ixgbe_mac_82598EB) {
3499 int i;
3500 u32 reg = 0;
3501
3502 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3503 u8 msb = 0;
3504 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3505
3506 while (cnt >>= 1)
3507 msb++;
3508
3509 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3510 }
3511 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3512 }
2f90b865 3513}
9da712d2
JF		 3514#endif
3515
3516/* Additional bittime to account for IXGBE framing */
3517#define IXGBE_ETH_FRAMING 20
3518
3519/*
3520 * ixgbe_hpbthresh - calculate high water mark for flow control
3521 *
3522 * @adapter: board private structure to calculate for
3523 * @pb - packet buffer to calculate
3524 */
3525static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3526{
3527 struct ixgbe_hw *hw = &adapter->hw;
3528 struct net_device *dev = adapter->netdev;
3529 int link, tc, kb, marker;
3530 u32 dv_id, rx_pba;
3531
3532 /* Calculate max LAN frame size */
3533 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3534
3535#ifdef IXGBE_FCOE
3536 /* FCoE traffic class uses FCOE jumbo frames */
3537 if (dev->features & NETIF_F_FCOE_MTU) {
3538 int fcoe_pb = 0;
2f90b865 3539
9da712d2
JF		 3540#ifdef CONFIG_IXGBE_DCB
3541 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3542
3543#endif
3544 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3545 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3546 }
2f90b865 3547#endif
80605c65 3548
9da712d2
JF		 3549 /* Calculate delay value for device */
3550 switch (hw->mac.type) {
3551 case ixgbe_mac_X540:
3552 dv_id = IXGBE_DV_X540(link, tc);
3553 break;
3554 default:
3555 dv_id = IXGBE_DV(link, tc);
3556 break;
3557 }
3558
3559 /* Loopback switch introduces additional latency */
3560 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3561 dv_id += IXGBE_B2BT(tc);
3562
3563 /* Delay value is calculated in bit times convert to KB */
3564 kb = IXGBE_BT2KB(dv_id);
3565 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3566
3567 marker = rx_pba - kb;
3568
3569 /* It is possible that the packet buffer is not large enough
3570 * to provide required headroom. In this case throw an error
3571 * to user and a do the best we can.
3572 */
3573 if (marker < 0) {
3574 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3575 "headroom to support flow control."
3576 "Decrease MTU or number of traffic classes\n", pb);
3577 marker = tc + 1;
3578 }
3579
3580 return marker;
3581}
3582
3583/*
3584 * ixgbe_lpbthresh - calculate low water mark for for flow control
3585 *
3586 * @adapter: board private structure to calculate for
3587 * @pb - packet buffer to calculate
3588 */
3589static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3590{
3591 struct ixgbe_hw *hw = &adapter->hw;
3592 struct net_device *dev = adapter->netdev;
3593 int tc;
3594 u32 dv_id;
3595
3596 /* Calculate max LAN frame size */
3597 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3598
3599 /* Calculate delay value for device */
3600 switch (hw->mac.type) {
3601 case ixgbe_mac_X540:
3602 dv_id = IXGBE_LOW_DV_X540(tc);
3603 break;
3604 default:
3605 dv_id = IXGBE_LOW_DV(tc);
3606 break;
3607 }
3608
3609 /* Delay value is calculated in bit times convert to KB */
3610 return IXGBE_BT2KB(dv_id);
3611}
3612
3613/*
3614 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3615 */
3616static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3617{
3618 struct ixgbe_hw *hw = &adapter->hw;
3619 int num_tc = netdev_get_num_tc(adapter->netdev);
3620 int i;
3621
3622 if (!num_tc)
3623 num_tc = 1;
3624
3625 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3626
3627 for (i = 0; i < num_tc; i++) {
3628 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3629
3630 /* Low water marks must not be larger than high water marks */
3631 if (hw->fc.low_water > hw->fc.high_water[i])
3632 hw->fc.low_water = 0;
3633 }
3634}
3635
80605c65
JF		 3636static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3637{
80605c65 3638 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3639 int hdrm;
3640 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3641
3642 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3643 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3644 hdrm = 32 << adapter->fdir_pballoc;
3645 else
3646 hdrm = 0;
80605c65 3647
f7e1027f 3648 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3649 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3650}
3651
e4911d57
AD		 3652static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3653{
3654 struct ixgbe_hw *hw = &adapter->hw;
3655 struct hlist_node *node, *node2;
3656 struct ixgbe_fdir_filter *filter;
3657
3658 spin_lock(&adapter->fdir_perfect_lock);
3659
3660 if (!hlist_empty(&adapter->fdir_filter_list))
3661 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3662
3663 hlist_for_each_entry_safe(filter, node, node2,
3664 &adapter->fdir_filter_list, fdir_node) {
3665 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3666 &filter->filter,
3667 filter->sw_idx,
3668 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3669 IXGBE_FDIR_DROP_QUEUE :
3670 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3671 }
3672
3673 spin_unlock(&adapter->fdir_perfect_lock);
3674}
3675
9a799d71
AK		 3676static void ixgbe_configure(struct ixgbe_adapter *adapter)
3677{
d2f5e7f3
AS		 3678 struct ixgbe_hw *hw = &adapter->hw;
3679
80605c65 3680 ixgbe_configure_pb(adapter);
7a6b6f51 3681#ifdef CONFIG_IXGBE_DCB
67ebd791 3682 ixgbe_configure_dcb(adapter);
2f90b865 3683#endif
9a799d71 3684
4c1d7b4b 3685 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3686 ixgbe_restore_vlan(adapter);
3687
eacd73f7
YZ		 3688#ifdef IXGBE_FCOE
3689 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3690 ixgbe_configure_fcoe(adapter);
3691
3692#endif /* IXGBE_FCOE */
d2f5e7f3
AS		 3693
3694 switch (hw->mac.type) {
3695 case ixgbe_mac_82599EB:
3696 case ixgbe_mac_X540:
3697 hw->mac.ops.disable_rx_buff(hw);
3698 break;
3699 default:
3700 break;
3701 }
3702
c4cf55e5 3703 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3704 ixgbe_init_fdir_signature_82599(&adapter->hw,
3705 adapter->fdir_pballoc);
e4911d57
AD		 3706 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3707 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3708 adapter->fdir_pballoc);
3709 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3710 }
4c1d7b4b 3711
d2f5e7f3
AS		 3712 switch (hw->mac.type) {
3713 case ixgbe_mac_82599EB:
3714 case ixgbe_mac_X540:
3715 hw->mac.ops.enable_rx_buff(hw);
3716 break;
3717 default:
3718 break;
3719 }
3720
933d41f1 3721 ixgbe_configure_virtualization(adapter);
c4cf55e5 3722
9a799d71
AK		 3723 ixgbe_configure_tx(adapter);
3724 ixgbe_configure_rx(adapter);
9a799d71
AK		 3725}
3726
e8e26350
PW		 3727static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3728{
3729 switch (hw->phy.type) {
3730 case ixgbe_phy_sfp_avago:
3731 case ixgbe_phy_sfp_ftl:
3732 case ixgbe_phy_sfp_intel:
3733 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3734 case ixgbe_phy_sfp_passive_tyco:
3735 case ixgbe_phy_sfp_passive_unknown:
3736 case ixgbe_phy_sfp_active_unknown:
3737 case ixgbe_phy_sfp_ftl_active:
e8e26350 3738 return true;
8917b447
AD		 3739 case ixgbe_phy_nl:
3740 if (hw->mac.type == ixgbe_mac_82598EB)
3741 return true;
e8e26350
PW		 3742 default:
3743 return false;
3744 }
3745}
3746
0ecc061d 3747/**
e8e26350
PW		 3748 * ixgbe_sfp_link_config - set up SFP+ link
3749 * @adapter: pointer to private adapter struct
3750 **/
3751static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3752{
7086400d 3753 /*
52f33af8 3754 * We are assuming the worst case scenario here, and that
7086400d
AD		 3755 * is that an SFP was inserted/removed after the reset
3756 * but before SFP detection was enabled. As such the best
3757 * solution is to just start searching as soon as we start
3758 */
3759 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3760 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3761
7086400d 3762 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3763}
3764
3765/**
3766 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3767 * @hw: pointer to private hardware struct
3768 *
3769 * Returns 0 on success, negative on failure
3770 **/
e8e26350 3771static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3772{
3773 u32 autoneg;
8620a103 3774 bool negotiation, link_up = false;
0ecc061d
PWJ		 3775 u32 ret = IXGBE_ERR_LINK_SETUP;
3776
3777 if (hw->mac.ops.check_link)
3778 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3779
3780 if (ret)
3781 goto link_cfg_out;
3782
0b0c2b31
ET		 3783 autoneg = hw->phy.autoneg_advertised;
3784 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3785 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3786 &negotiation);
0ecc061d
PWJ		 3787 if (ret)
3788 goto link_cfg_out;
3789
8620a103
MC		 3790 if (hw->mac.ops.setup_link)
3791 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3792link_cfg_out:
3793 return ret;
3794}
3795
a34bcfff 3796static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3797{
9a799d71 3798 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3799 u32 gpie = 0;
9a799d71 3800
9b471446 3801 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3802 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3803 IXGBE_GPIE_OCD;
3804 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3805 /*
3806 * use EIAM to auto-mask when MSI-X interrupt is asserted
3807 * this saves a register write for every interrupt
3808 */
3809 switch (hw->mac.type) {
3810 case ixgbe_mac_82598EB:
3811 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3812 break;
9b471446 3813 case ixgbe_mac_82599EB:
b93a2226
DS		 3814 case ixgbe_mac_X540:
3815 default:
9b471446
JB		 3816 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3817 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3818 break;
3819 }
3820 } else {
021230d4
AV		 3821 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3822 * specifically only auto mask tx and rx interrupts */
3823 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3824 }
9a799d71 3825
a34bcfff
AD		 3826 /* XXX: to interrupt immediately for EICS writes, enable this */
3827 /* gpie |= IXGBE_GPIE_EIMEN; */
3828
3829 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3830 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3831 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3832 }
3833
5fdd31f9 3834 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3835 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3836 switch (adapter->hw.mac.type) {
3837 case ixgbe_mac_82599EB:
3838 gpie |= IXGBE_SDP0_GPIEN;
3839 break;
3840 case ixgbe_mac_X540:
3841 gpie |= IXGBE_EIMS_TS;
3842 break;
3843 default:
3844 break;
3845 }
3846 }
5fdd31f9 3847
a34bcfff
AD		 3848 /* Enable fan failure interrupt */
3849 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3850 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3851
2698b208 3852 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3853 gpie |= IXGBE_SDP1_GPIEN;
3854 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3855 }
a34bcfff
AD		 3856
3857 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3858}
3859
c7ccde0f 3860static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3861{
3862 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3863 int err;
a34bcfff
AD		 3864 u32 ctrl_ext;
3865
3866 ixgbe_get_hw_control(adapter);
3867 ixgbe_setup_gpie(adapter);
e8e26350 3868
9a799d71
AK		 3869 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3870 ixgbe_configure_msix(adapter);
3871 else
3872 ixgbe_configure_msi_and_legacy(adapter);
3873
c6ecf39a
DS		 3874 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3875 if (hw->mac.ops.enable_tx_laser &&
3876 ((hw->phy.multispeed_fiber) ||
9f911707 3877 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3878 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3879 hw->mac.ops.enable_tx_laser(hw);
3880
9a799d71 3881 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3882 ixgbe_napi_enable_all(adapter);
3883
73c4b7cd
AD		 3884 if (ixgbe_is_sfp(hw)) {
3885 ixgbe_sfp_link_config(adapter);
3886 } else {
3887 err = ixgbe_non_sfp_link_config(hw);
3888 if (err)
3889 e_err(probe, "link_config FAILED %d\n", err);
3890 }
3891
021230d4
AV		 3892 /* clear any pending interrupts, may auto mask */
3893 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3894 ixgbe_irq_enable(adapter, true, true);
9a799d71 3895
bf069c97
DS		 3896 /*
3897 * If this adapter has a fan, check to see if we had a failure
3898 * before we enabled the interrupt.
3899 */
3900 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3901 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3902 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3903 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3904 }
3905
1da100bb 3906 /* enable transmits */
477de6ed 3907 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3908
9a799d71
AK		 3909 /* bring the link up in the watchdog, this could race with our first
3910 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3911 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3912 adapter->link_check_timeout = jiffies;
7086400d 3913 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3914
3915 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3916 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3917 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3918 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3919}
3920
d4f80882
AV		 3921void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3922{
3923 WARN_ON(in_interrupt());
7086400d
AD		 3924 /* put off any impending NetWatchDogTimeout */
3925 adapter->netdev->trans_start = jiffies;
3926
d4f80882 3927 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3928 usleep_range(1000, 2000);
d4f80882 3929 ixgbe_down(adapter);
5809a1ae
GR		 3930 /*
3931 * If SR-IOV enabled then wait a bit before bringing the adapter
3932 * back up to give the VFs time to respond to the reset. The
3933 * two second wait is based upon the watchdog timer cycle in
3934 * the VF driver.
3935 */
3936 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3937 msleep(2000);
d4f80882
AV		 3938 ixgbe_up(adapter);
3939 clear_bit(__IXGBE_RESETTING, &adapter->state);
3940}
3941
c7ccde0f 3942void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3943{
3944 /* hardware has been reset, we need to reload some things */
3945 ixgbe_configure(adapter);
3946
c7ccde0f 3947 ixgbe_up_complete(adapter);
9a799d71
AK		 3948}
3949
3950void ixgbe_reset(struct ixgbe_adapter *adapter)
3951{
c44ade9e 3952 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3953 int err;
3954
7086400d
AD		 3955 /* lock SFP init bit to prevent race conditions with the watchdog */
3956 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3957 usleep_range(1000, 2000);
3958
3959 /* clear all SFP and link config related flags while holding SFP_INIT */
3960 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3961 IXGBE_FLAG2_SFP_NEEDS_RESET);
3962 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3963
8ca783ab 3964 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3965 switch (err) {
3966 case 0:
3967 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3968 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3969 break;
3970 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3971 e_dev_err("master disable timed out\n");
da4dd0f7 3972 break;
794caeb2
PWJ		 3973 case IXGBE_ERR_EEPROM_VERSION:
3974 /* We are running on a pre-production device, log a warning */
849c4542 3975 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 3976 "Please be aware there may be issues associated with "
849c4542
ET		 3977 "your hardware. If you are experiencing problems "
3978 "please contact your Intel or hardware "
3979 "representative who provided you with this "
3980 "hardware.\n");
794caeb2 3981 break;
da4dd0f7 3982 default:
849c4542 3983 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3984 }
9a799d71 3985
7086400d
AD		 3986 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3987
9a799d71 3988 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3989 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3990 IXGBE_RAH_AV);
9a799d71
AK		 3991}
3992
9a799d71
AK		 3993/**
3994 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3995 * @rx_ring: ring to free buffers from
3996 **/
b6ec895e 3997static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3998{
b6ec895e 3999 struct device *dev = rx_ring->dev;
9a799d71 4000 unsigned long size;
b6ec895e 4001 u16 i;
9a799d71 4002
84418e3b
AD		 4003 /* ring already cleared, nothing to do */
4004 if (!rx_ring->rx_buffer_info)
4005 return;
9a799d71 4006
84418e3b 4007 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4008 for (i = 0; i < rx_ring->count; i++) {
4009 struct ixgbe_rx_buffer *rx_buffer_info;
4010
4011 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4012 if (rx_buffer_info->dma) {
b6ec895e 4013 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4014 rx_ring->rx_buf_len,
1b507730 4015 DMA_FROM_DEVICE);
9a799d71
AK		 4016 rx_buffer_info->dma = 0;
4017 }
4018 if (rx_buffer_info->skb) {
f8212f97 4019 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4020 rx_buffer_info->skb = NULL;
4c1975d7
AD		 4021 /* We need to clean up RSC frag lists */
4022 skb = ixgbe_merge_active_tail(skb);
4023 ixgbe_close_active_frag_list(skb);
4024 if (IXGBE_CB(skb)->delay_unmap) {
4025 dma_unmap_single(dev,
4026 IXGBE_CB(skb)->dma,
4027 rx_ring->rx_buf_len,
4028 DMA_FROM_DEVICE);
4029 IXGBE_CB(skb)->dma = 0;
4030 IXGBE_CB(skb)->delay_unmap = false;
4031 }
4032 dev_kfree_skb(skb);
9a799d71
AK		 4033 }
4034 if (!rx_buffer_info->page)
4035 continue;
4f57ca6e 4036 if (rx_buffer_info->page_dma) {
b6ec895e 4037 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4038 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4039 rx_buffer_info->page_dma = 0;
4040 }
9a799d71
AK		 4041 put_page(rx_buffer_info->page);
4042 rx_buffer_info->page = NULL;
762f4c57 4043 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4044 }
4045
4046 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4047 memset(rx_ring->rx_buffer_info, 0, size);
4048
4049 /* Zero out the descriptor ring */
4050 memset(rx_ring->desc, 0, rx_ring->size);
4051
4052 rx_ring->next_to_clean = 0;
4053 rx_ring->next_to_use = 0;
9a799d71
AK		 4054}
4055
4056/**
4057 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4058 * @tx_ring: ring to be cleaned
4059 **/
b6ec895e 4060static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4061{
4062 struct ixgbe_tx_buffer *tx_buffer_info;
4063 unsigned long size;
b6ec895e 4064 u16 i;
9a799d71 4065
84418e3b
AD		 4066 /* ring already cleared, nothing to do */
4067 if (!tx_ring->tx_buffer_info)
4068 return;
9a799d71 4069
84418e3b 4070 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4071 for (i = 0; i < tx_ring->count; i++) {
4072 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4073 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4074 }
4075
4076 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4077 memset(tx_ring->tx_buffer_info, 0, size);
4078
4079 /* Zero out the descriptor ring */
4080 memset(tx_ring->desc, 0, tx_ring->size);
4081
4082 tx_ring->next_to_use = 0;
4083 tx_ring->next_to_clean = 0;
9a799d71
AK		 4084}
4085
4086/**
021230d4 4087 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4088 * @adapter: board private structure
4089 **/
021230d4 4090static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4091{
4092 int i;
4093
021230d4 4094 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4095 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4096}
4097
4098/**
021230d4 4099 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4100 * @adapter: board private structure
4101 **/
021230d4 4102static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4103{
4104 int i;
4105
021230d4 4106 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4107 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4108}
4109
e4911d57
AD		 4110static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4111{
4112 struct hlist_node *node, *node2;
4113 struct ixgbe_fdir_filter *filter;
4114
4115 spin_lock(&adapter->fdir_perfect_lock);
4116
4117 hlist_for_each_entry_safe(filter, node, node2,
4118 &adapter->fdir_filter_list, fdir_node) {
4119 hlist_del(&filter->fdir_node);
4120 kfree(filter);
4121 }
4122 adapter->fdir_filter_count = 0;
4123
4124 spin_unlock(&adapter->fdir_perfect_lock);
4125}
4126
9a799d71
AK		 4127void ixgbe_down(struct ixgbe_adapter *adapter)
4128{
4129 struct net_device *netdev = adapter->netdev;
7f821875 4130 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4131 u32 rxctrl;
bf29ee6c 4132 int i;
9a799d71
AK		 4133
4134 /* signal that we are down to the interrupt handler */
4135 set_bit(__IXGBE_DOWN, &adapter->state);
4136
4137 /* disable receives */
7f821875
JB		 4138 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4139 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4140
2d39d576
YZ		 4141 /* disable all enabled rx queues */
4142 for (i = 0; i < adapter->num_rx_queues; i++)
4143 /* this call also flushes the previous write */
4144 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4145
032b4325 4146 usleep_range(10000, 20000);
9a799d71 4147
7f821875
JB		 4148 netif_tx_stop_all_queues(netdev);
4149
7086400d 4150 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4151 netif_carrier_off(netdev);
4152 netif_tx_disable(netdev);
4153
4154 ixgbe_irq_disable(adapter);
4155
4156 ixgbe_napi_disable_all(adapter);
4157
d034acf1
AD		 4158 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4159 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4160 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4161
4162 del_timer_sync(&adapter->service_timer);
4163
34cecbbf 4164 if (adapter->num_vfs) {
8e34d1aa
AD		 4165 /* Clear EITR Select mapping */
4166 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4167
4168 /* Mark all the VFs as inactive */
4169 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4170 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4171
34cecbbf
AD		 4172 /* ping all the active vfs to let them know we are going down */
4173 ixgbe_ping_all_vfs(adapter);
4174
4175 /* Disable all VFTE/VFRE TX/RX */
4176 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4177 }
4178
7f821875
JB		 4179 /* disable transmits in the hardware now that interrupts are off */
4180 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4181 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4182 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4183 }
34cecbbf
AD		 4184
4185 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4186 switch (hw->mac.type) {
4187 case ixgbe_mac_82599EB:
b93a2226 4188 case ixgbe_mac_X540:
88512539 4189 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4190 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4191 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4192 break;
4193 default:
4194 break;
4195 }
7f821875 4196
6f4a0e45
PL		 4197 if (!pci_channel_offline(adapter->pdev))
4198 ixgbe_reset(adapter);
c6ecf39a
DS		 4199
4200 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4201 if (hw->mac.ops.disable_tx_laser &&
4202 ((hw->phy.multispeed_fiber) ||
9f911707 4203 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4204 (hw->mac.type == ixgbe_mac_82599EB))))
4205 hw->mac.ops.disable_tx_laser(hw);
4206
9a799d71
AK		 4207 ixgbe_clean_all_tx_rings(adapter);
4208 ixgbe_clean_all_rx_rings(adapter);
4209
5dd2d332 4210#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4211 /* since we reset the hardware DCA settings were cleared */
e35ec126 4212 ixgbe_setup_dca(adapter);
96b0e0f6 4213#endif
9a799d71
AK		 4214}
4215
9a799d71 4216/**
021230d4
AV		 4217 * ixgbe_poll - NAPI Rx polling callback
4218 * @napi: structure for representing this polling device
4219 * @budget: how many packets driver is allowed to clean
4220 *
4221 * This function is used for legacy and MSI, NAPI mode
9a799d71 4222 **/
021230d4 4223static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4224{
9a1a69ad 4225 struct ixgbe_q_vector *q_vector =
e8e9f696 4226 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4227 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4228 struct ixgbe_ring *ring;
4229 int per_ring_budget;
4230 bool clean_complete = true;
9a799d71 4231
5dd2d332 4232#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4233 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4234 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4235#endif
4236
a557928e 4237 ixgbe_for_each_ring(ring, q_vector->tx)
4ff7fb12 4238 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4239
4ff7fb12
AD		 4240 /* attempt to distribute budget to each queue fairly, but don't allow
4241 * the budget to go below 1 because we'll exit polling */
4242 if (q_vector->rx.count > 1)
4243 per_ring_budget = max(budget/q_vector->rx.count, 1);
4244 else
4245 per_ring_budget = budget;
d2c7ddd6 4246
a557928e 4247 ixgbe_for_each_ring(ring, q_vector->rx)
4ff7fb12
AD		 4248 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4249 per_ring_budget);
4250
4251 /* If all work not completed, return budget and keep polling */
4252 if (!clean_complete)
4253 return budget;
4254
4255 /* all work done, exit the polling mode */
4256 napi_complete(napi);
4257 if (adapter->rx_itr_setting & 1)
4258 ixgbe_set_itr(q_vector);
4259 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4260 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4261
4262 return 0;
9a799d71
AK		 4263}
4264
4265/**
4266 * ixgbe_tx_timeout - Respond to a Tx Hang
4267 * @netdev: network interface device structure
4268 **/
4269static void ixgbe_tx_timeout(struct net_device *netdev)
4270{
4271 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4272
4273 /* Do the reset outside of interrupt context */
c83c6cbd 4274 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4275}
4276
4df10466
JB		 4277/**
4278 * ixgbe_set_rss_queues: Allocate queues for RSS
4279 * @adapter: board private structure to initialize
4280 *
4281 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4282 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4283 *
4284 **/
bc97114d
PWJ		 4285static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4286{
4287 bool ret = false;
0cefafad 4288 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4289
4290 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4291 f->mask = 0xF;
4292 adapter->num_rx_queues = f->indices;
4293 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4294 ret = true;
4295 } else {
bc97114d 4296 ret = false;
b9804972
JB		 4297 }
4298
bc97114d
PWJ		 4299 return ret;
4300}
4301
c4cf55e5
PWJ		 4302/**
4303 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4304 * @adapter: board private structure to initialize
4305 *
4306 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4307 * to the original CPU that initiated the Tx session. This runs in addition
4308 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4309 * Rx load across CPUs using RSS.
4310 *
4311 **/
e8e9f696 4312static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4313{
4314 bool ret = false;
4315 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4316
4317 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4318 f_fdir->mask = 0;
4319
24ddd967
AD		 4320 /*
4321 * Use RSS in addition to Flow Director to ensure the best
4322 * distribution of flows across cores, even when an FDIR flow
4323 * isn't matched.
4324 */
03ecf91a
AD		 4325 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4326 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4327 adapter->num_tx_queues = f_fdir->indices;
4328 adapter->num_rx_queues = f_fdir->indices;
4329 ret = true;
4330 } else {
4331 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4332 }
4333 return ret;
4334}
4335
0331a832
YZ		 4336#ifdef IXGBE_FCOE
4337/**
4338 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4339 * @adapter: board private structure to initialize
4340 *
4341 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4342 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4343 * rx queues out of the max number of rx queues, instead, it is used as the
4344 * index of the first rx queue used by FCoE.
4345 *
4346 **/
4347static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4348{
0331a832
YZ		 4349 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4350
e5b64635
JF		 4351 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4352 return false;
4353
3ed69d7e 4354 f->indices = min_t(int, num_online_cpus(), f->indices);
e5b64635 4355
e901acd6
JF		 4356 adapter->num_rx_queues = 1;
4357 adapter->num_tx_queues = 1;
e5b64635 4358
e901acd6
JF		 4359 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4360 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4361 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4362 ixgbe_set_fdir_queues(adapter);
4363 else
4364 ixgbe_set_rss_queues(adapter);
e5b64635 4365 }
03ecf91a 4366
e901acd6
JF		 4367 /* adding FCoE rx rings to the end */
4368 f->mask = adapter->num_rx_queues;
4369 adapter->num_rx_queues += f->indices;
4370 adapter->num_tx_queues += f->indices;
0331a832 4371
e5b64635
JF		 4372 return true;
4373}
4374#endif /* IXGBE_FCOE */
4375
e901acd6
JF		 4376/* Artificial max queue cap per traffic class in DCB mode */
4377#define DCB_QUEUE_CAP 8
4378
e5b64635
JF		 4379#ifdef CONFIG_IXGBE_DCB
4380static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4381{
e901acd6
JF		 4382 int per_tc_q, q, i, offset = 0;
4383 struct net_device *dev = adapter->netdev;
4384 int tcs = netdev_get_num_tc(dev);
e5b64635 4385
e901acd6
JF		 4386 if (!tcs)
4387 return false;
e5b64635 4388
e901acd6 4389 /* Map queue offset and counts onto allocated tx queues */
3ed69d7e
JB		 4390 per_tc_q = min_t(unsigned int, dev->num_tx_queues / tcs, DCB_QUEUE_CAP);
4391 q = min_t(int, num_online_cpus(), per_tc_q);
8b1c0b24 4392
8b1c0b24 4393 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4394 netdev_set_tc_queue(dev, i, q, offset);
4395 offset += q;
0331a832
YZ		 4396 }
4397
e901acd6
JF		 4398 adapter->num_tx_queues = q * tcs;
4399 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4400
4401#ifdef IXGBE_FCOE
e901acd6
JF		 4402 /* FCoE enabled queues require special configuration indexed
4403 * by feature specific indices and mask. Here we map FCoE
4404 * indices onto the DCB queue pairs allowing FCoE to own
4405 * configuration later.
e5b64635 4406 */
e901acd6 4407 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
cdf485be 4408 u8 prio_tc[MAX_USER_PRIORITY] = {0};
e901acd6
JF		 4409 int tc;
4410 struct ixgbe_ring_feature *f =
4411 &adapter->ring_feature[RING_F_FCOE];
4412
cdf485be
JF		 4413 ixgbe_dcb_unpack_map(&adapter->dcb_cfg, DCB_TX_CONFIG, prio_tc);
4414 tc = prio_tc[adapter->fcoe.up];
e901acd6
JF		 4415 f->indices = dev->tc_to_txq[tc].count;
4416 f->mask = dev->tc_to_txq[tc].offset;
4417 }
e5b64635
JF		 4418#endif
4419
e901acd6 4420 return true;
0331a832 4421}
e5b64635 4422#endif
0331a832 4423
1cdd1ec8
GR		 4424/**
4425 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4426 * @adapter: board private structure to initialize
4427 *
4428 * IOV doesn't actually use anything, so just NAK the
4429 * request for now and let the other queue routines
4430 * figure out what to do.
4431 */
4432static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4433{
4434 return false;
4435}
4436
4df10466 4437/*
25985edc 4438 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4439 * @adapter: board private structure to initialize
4440 *
4441 * This is the top level queue allocation routine. The order here is very
4442 * important, starting with the "most" number of features turned on at once,
4443 * and ending with the smallest set of features. This way large combinations
4444 * can be allocated if they're turned on, and smaller combinations are the
4445 * fallthrough conditions.
4446 *
4447 **/
847f53ff 4448static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4449{
1cdd1ec8
GR		 4450 /* Start with base case */
4451 adapter->num_rx_queues = 1;
4452 adapter->num_tx_queues = 1;
4453 adapter->num_rx_pools = adapter->num_rx_queues;
4454 adapter->num_rx_queues_per_pool = 1;
4455
4456 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4457 goto done;
1cdd1ec8 4458
bc97114d
PWJ		 4459#ifdef CONFIG_IXGBE_DCB
4460 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4461 goto done;
bc97114d
PWJ		 4462
4463#endif
e5b64635
JF		 4464#ifdef IXGBE_FCOE
4465 if (ixgbe_set_fcoe_queues(adapter))
4466 goto done;
4467
4468#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4469 if (ixgbe_set_fdir_queues(adapter))
4470 goto done;
4471
bc97114d 4472 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4473 goto done;
4474
4475 /* fallback to base case */
4476 adapter->num_rx_queues = 1;
4477 adapter->num_tx_queues = 1;
4478
4479done:
9d837ea2
YZ		 4480 if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) ||
4481 (adapter->netdev->reg_state == NETREG_UNREGISTERING))
4482 return 0;
4483
847f53ff 4484 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4485 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4486 return netif_set_real_num_rx_queues(adapter->netdev,
4487 adapter->num_rx_queues);
b9804972
JB		 4488}
4489
021230d4 4490static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4491 int vectors)
021230d4
AV		 4492{
4493 int err, vector_threshold;
4494
8f15486d
AD		 4495 /* We'll want at least 2 (vector_threshold):
4496 * 1) TxQ[0] + RxQ[0] handler
4497 * 2) Other (Link Status Change, etc.)
021230d4
AV		 4498 */
4499 vector_threshold = MIN_MSIX_COUNT;
4500
24ddd967
AD		 4501 /*
4502 * The more we get, the more we will assign to Tx/Rx Cleanup
021230d4
AV		 4503 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4504 * Right now, we simply care about how many we'll get; we'll
4505 * set them up later while requesting irq's.
4506 */
4507 while (vectors >= vector_threshold) {
4508 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4509 vectors);
021230d4
AV		 4510 if (!err) /* Success in acquiring all requested vectors. */
4511 break;
4512 else if (err < 0)
4513 vectors = 0; /* Nasty failure, quit now */
4514 else /* err == number of vectors we should try again with */
4515 vectors = err;
4516 }
4517
4518 if (vectors < vector_threshold) {
4519 /* Can't allocate enough MSI-X interrupts? Oh well.
4520 * This just means we'll go with either a single MSI
4521 * vector or fall back to legacy interrupts.
4522 */
849c4542
ET		 4523 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4524 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4525 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4526 kfree(adapter->msix_entries);
4527 adapter->msix_entries = NULL;
021230d4
AV		 4528 } else {
4529 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4530 /*
4531 * Adjust for only the vectors we'll use, which is minimum
4532 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4533 * vectors we were allocated.
4534 */
4535 adapter->num_msix_vectors = min(vectors,
e8e9f696 4536 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4537 }
4538}
4539
021230d4 4540/**
bc97114d 4541 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4542 * @adapter: board private structure to initialize
4543 *
bc97114d
PWJ		 4544 * Cache the descriptor ring offsets for RSS to the assigned rings.
4545 *
021230d4 4546 **/
bc97114d 4547static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4548{
bc97114d 4549 int i;
bc97114d 4550
9d6b758f
AD		 4551 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4552 return false;
bc97114d 4553
9d6b758f
AD		 4554 for (i = 0; i < adapter->num_rx_queues; i++)
4555 adapter->rx_ring[i]->reg_idx = i;
4556 for (i = 0; i < adapter->num_tx_queues; i++)
4557 adapter->tx_ring[i]->reg_idx = i;
4558
4559 return true;
bc97114d
PWJ		 4560}
4561
4562#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4563
4564/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4565static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4566 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4567{
4568 struct net_device *dev = adapter->netdev;
4569 struct ixgbe_hw *hw = &adapter->hw;
4570 u8 num_tcs = netdev_get_num_tc(dev);
4571
4572 *tx = 0;
4573 *rx = 0;
4574
4575 switch (hw->mac.type) {
4576 case ixgbe_mac_82598EB:
aba70d5e
JF		 4577 *tx = tc << 2;
4578 *rx = tc << 3;
e5b64635
JF		 4579 break;
4580 case ixgbe_mac_82599EB:
4581 case ixgbe_mac_X540:
4fa2e0e1 4582 if (num_tcs > 4) {
e5b64635
JF		 4583 if (tc < 3) {
4584 *tx = tc << 5;
4585 *rx = tc << 4;
4586 } else if (tc < 5) {
4587 *tx = ((tc + 2) << 4);
4588 *rx = tc << 4;
4589 } else if (tc < num_tcs) {
4590 *tx = ((tc + 8) << 3);
4591 *rx = tc << 4;
4592 }
4fa2e0e1 4593 } else {
e5b64635
JF		 4594 *rx = tc << 5;
4595 switch (tc) {
4596 case 0:
4597 *tx = 0;
4598 break;
4599 case 1:
4600 *tx = 64;
4601 break;
4602 case 2:
4603 *tx = 96;
4604 break;
4605 case 3:
4606 *tx = 112;
4607 break;
4608 default:
4609 break;
4610 }
4611 }
4612 break;
4613 default:
4614 break;
4615 }
4616}
4617
bc97114d
PWJ		 4618/**
4619 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4620 * @adapter: board private structure to initialize
4621 *
4622 * Cache the descriptor ring offsets for DCB to the assigned rings.
4623 *
4624 **/
4625static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4626{
e5b64635
JF		 4627 struct net_device *dev = adapter->netdev;
4628 int i, j, k;
4629 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4630
8b1c0b24 4631 if (!num_tcs)
bd508178 4632 return false;
f92ef202 4633
e5b64635
JF		 4634 for (i = 0, k = 0; i < num_tcs; i++) {
4635 unsigned int tx_s, rx_s;
4636 u16 count = dev->tc_to_txq[i].count;
4637
4638 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4639 for (j = 0; j < count; j++, k++) {
4640 adapter->tx_ring[k]->reg_idx = tx_s + j;
4641 adapter->rx_ring[k]->reg_idx = rx_s + j;
4642 adapter->tx_ring[k]->dcb_tc = i;
4643 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4644 }
021230d4 4645 }
e5b64635
JF		 4646
4647 return true;
bc97114d
PWJ		 4648}
4649#endif
4650
c4cf55e5
PWJ		 4651/**
4652 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4653 * @adapter: board private structure to initialize
4654 *
4655 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4656 *
4657 **/
e8e9f696 4658static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4659{
4660 int i;
4661 bool ret = false;
4662
03ecf91a
AD		 4663 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4664 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4665 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4666 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4667 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4668 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4669 ret = true;
4670 }
4671
4672 return ret;
4673}
4674
0331a832
YZ		 4675#ifdef IXGBE_FCOE
4676/**
4677 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4678 * @adapter: board private structure to initialize
4679 *
4680 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4681 *
4682 */
4683static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4684{
0331a832 4685 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4686 int i;
4687 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4688
4689 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4690 return false;
0331a832 4691
bf29ee6c 4692 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4693 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4694 ixgbe_cache_ring_fdir(adapter);
4695 else
4696 ixgbe_cache_ring_rss(adapter);
8faa2a78 4697
bf29ee6c
AD		 4698 fcoe_rx_i = f->mask;
4699 fcoe_tx_i = f->mask;
0331a832 4700 }
bf29ee6c
AD		 4701 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4702 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4703 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4704 }
4705 return true;
0331a832
YZ		 4706}
4707
4708#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4709/**
4710 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4711 * @adapter: board private structure to initialize
4712 *
4713 * SR-IOV doesn't use any descriptor rings but changes the default if
4714 * no other mapping is used.
4715 *
4716 */
4717static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4718{
4a0b9ca0
PW		 4719 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4720 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4721 if (adapter->num_vfs)
4722 return true;
4723 else
4724 return false;
4725}
4726
bc97114d
PWJ		 4727/**
4728 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4729 * @adapter: board private structure to initialize
4730 *
4731 * Once we know the feature-set enabled for the device, we'll cache
4732 * the register offset the descriptor ring is assigned to.
4733 *
4734 * Note, the order the various feature calls is important. It must start with
4735 * the "most" features enabled at the same time, then trickle down to the
4736 * least amount of features turned on at once.
4737 **/
4738static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4739{
4740 /* start with default case */
4a0b9ca0
PW		 4741 adapter->rx_ring[0]->reg_idx = 0;
4742 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4743
1cdd1ec8
GR		 4744 if (ixgbe_cache_ring_sriov(adapter))
4745 return;
4746
e5b64635
JF		 4747#ifdef CONFIG_IXGBE_DCB
4748 if (ixgbe_cache_ring_dcb(adapter))
4749 return;
4750#endif
4751
0331a832
YZ		 4752#ifdef IXGBE_FCOE
4753 if (ixgbe_cache_ring_fcoe(adapter))
4754 return;
0331a832 4755#endif /* IXGBE_FCOE */
bc97114d 4756
c4cf55e5
PWJ		 4757 if (ixgbe_cache_ring_fdir(adapter))
4758 return;
4759
bc97114d
PWJ		 4760 if (ixgbe_cache_ring_rss(adapter))
4761 return;
021230d4
AV		 4762}
4763
021230d4
AV		 4764/**
4765 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4766 * @adapter: board private structure to initialize
4767 *
4768 * Attempt to configure the interrupts using the best available
4769 * capabilities of the hardware and the kernel.
4770 **/
feea6a57 4771static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4772{
8be0e467 4773 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4774 int err = 0;
4775 int vector, v_budget;
4776
4777 /*
4778 * It's easy to be greedy for MSI-X vectors, but it really
4779 * doesn't do us much good if we have a lot more vectors
4780 * than CPU's. So let's be conservative and only ask for
342bde1b 4781 * (roughly) the same number of vectors as there are CPU's.
8f15486d 4782 * The default is to use pairs of vectors.
021230d4 4783 */
8f15486d
AD		 4784 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues);
4785 v_budget = min_t(int, v_budget, num_online_cpus());
4786 v_budget += NON_Q_VECTORS;
021230d4
AV		 4787
4788 /*
4789 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4790 * hw.mac->max_msix_vectors vectors. With features
4791 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4792 * descriptor queues supported by our device. Thus, we cap it off in
4793 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4794 */
de88eeeb 4795 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors);
021230d4
AV		 4796
4797 /* A failure in MSI-X entry allocation isn't fatal, but it does
4798 * mean we disable MSI-X capabilities of the adapter. */
4799 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4800 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4801 if (adapter->msix_entries) {
4802 for (vector = 0; vector < v_budget; vector++)
4803 adapter->msix_entries[vector].entry = vector;
021230d4 4804
7a921c93 4805 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4806
7a921c93
AD		 4807 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4808 goto out;
4809 }
26d27844 4810
7a921c93
AD		 4811 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4812 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4813 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4814 e_err(probe,
03ecf91a 4815 "ATR is not supported while multiple "
45b9f509
AD		 4816 "queues are disabled. Disabling Flow Director\n");
4817 }
c4cf55e5 4818 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4819 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4820 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4821 ixgbe_disable_sriov(adapter);
4822
847f53ff
BH		 4823 err = ixgbe_set_num_queues(adapter);
4824 if (err)
4825 return err;
021230d4 4826
021230d4
AV		 4827 err = pci_enable_msi(adapter->pdev);
4828 if (!err) {
4829 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4830 } else {
849c4542
ET		 4831 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4832 "Unable to allocate MSI interrupt, "
4833 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4834 /* reset err */
4835 err = 0;
4836 }
4837
4838out:
021230d4
AV		 4839 return err;
4840}
4841
de88eeeb
AD		 4842static void ixgbe_add_ring(struct ixgbe_ring *ring,
4843 struct ixgbe_ring_container *head)
4844{
4845 ring->next = head->ring;
4846 head->ring = ring;
4847 head->count++;
4848}
4849
4850/**
4851 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
4852 * @adapter: board private structure to initialize
4853 * @v_idx: index of vector in adapter struct
4854 *
4855 * We allocate one q_vector. If allocation fails we return -ENOMEM.
4856 **/
4857static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, int v_idx,
4858 int txr_count, int txr_idx,
4859 int rxr_count, int rxr_idx)
4860{
4861 struct ixgbe_q_vector *q_vector;
4862 struct ixgbe_ring *ring;
4863 int node = -1;
4864 int cpu = -1;
4865 int ring_count, size;
4866
4867 ring_count = txr_count + rxr_count;
4868 size = sizeof(struct ixgbe_q_vector) +
4869 (sizeof(struct ixgbe_ring) * ring_count);
4870
4871 /* customize cpu for Flow Director mapping */
4872 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4873 if (cpu_online(v_idx)) {
4874 cpu = v_idx;
4875 node = cpu_to_node(cpu);
4876 }
4877 }
4878
4879 /* allocate q_vector and rings */
4880 q_vector = kzalloc_node(size, GFP_KERNEL, node);
4881 if (!q_vector)
4882 q_vector = kzalloc(size, GFP_KERNEL);
4883 if (!q_vector)
4884 return -ENOMEM;
4885
4886 /* setup affinity mask and node */
4887 if (cpu != -1)
4888 cpumask_set_cpu(cpu, &q_vector->affinity_mask);
4889 else
4890 cpumask_copy(&q_vector->affinity_mask, cpu_online_mask);
4891 q_vector->numa_node = node;
4892
4893 /* initialize NAPI */
4894 netif_napi_add(adapter->netdev, &q_vector->napi,
4895 ixgbe_poll, 64);
4896
4897 /* tie q_vector and adapter together */
4898 adapter->q_vector[v_idx] = q_vector;
4899 q_vector->adapter = adapter;
4900 q_vector->v_idx = v_idx;
4901
4902 /* initialize work limits */
4903 q_vector->tx.work_limit = adapter->tx_work_limit;
4904
4905 /* initialize pointer to rings */
4906 ring = q_vector->ring;
4907
4908 while (txr_count) {
4909 /* assign generic ring traits */
4910 ring->dev = &adapter->pdev->dev;
4911 ring->netdev = adapter->netdev;
4912
4913 /* configure backlink on ring */
4914 ring->q_vector = q_vector;
4915
4916 /* update q_vector Tx values */
4917 ixgbe_add_ring(ring, &q_vector->tx);
4918
4919 /* apply Tx specific ring traits */
4920 ring->count = adapter->tx_ring_count;
4921 ring->queue_index = txr_idx;
4922
4923 /* assign ring to adapter */
4924 adapter->tx_ring[txr_idx] = ring;
4925
4926 /* update count and index */
4927 txr_count--;
4928 txr_idx++;
4929
4930 /* push pointer to next ring */
4931 ring++;
4932 }
4933
4934 while (rxr_count) {
4935 /* assign generic ring traits */
4936 ring->dev = &adapter->pdev->dev;
4937 ring->netdev = adapter->netdev;
4938
4939 /* configure backlink on ring */
4940 ring->q_vector = q_vector;
4941
4942 /* update q_vector Rx values */
4943 ixgbe_add_ring(ring, &q_vector->rx);
4944
4945 /*
4946 * 82599 errata, UDP frames with a 0 checksum
4947 * can be marked as checksum errors.
4948 */
4949 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4950 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
4951
4952 /* apply Rx specific ring traits */
4953 ring->count = adapter->rx_ring_count;
4954 ring->queue_index = rxr_idx;
4955
4956 /* assign ring to adapter */
4957 adapter->rx_ring[rxr_idx] = ring;
4958
4959 /* update count and index */
4960 rxr_count--;
4961 rxr_idx++;
4962
4963 /* push pointer to next ring */
4964 ring++;
4965 }
4966
4967 return 0;
4968}
4969
4970/**
4971 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
4972 * @adapter: board private structure to initialize
4973 * @v_idx: Index of vector to be freed
4974 *
4975 * This function frees the memory allocated to the q_vector. In addition if
4976 * NAPI is enabled it will delete any references to the NAPI struct prior
4977 * to freeing the q_vector.
4978 **/
4979static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx)
4980{
4981 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4982 struct ixgbe_ring *ring;
4983
a557928e 4984 ixgbe_for_each_ring(ring, q_vector->tx)
de88eeeb
AD		 4985 adapter->tx_ring[ring->queue_index] = NULL;
4986
a557928e 4987 ixgbe_for_each_ring(ring, q_vector->rx)
de88eeeb
AD		 4988 adapter->rx_ring[ring->queue_index] = NULL;
4989
4990 adapter->q_vector[v_idx] = NULL;
4991 netif_napi_del(&q_vector->napi);
4992
4993 /*
4994 * ixgbe_get_stats64() might access the rings on this vector,
4995 * we must wait a grace period before freeing it.
4996 */
4997 kfree_rcu(q_vector, rcu);
4998}
4999
7a921c93
AD		 5000/**
5001 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
5002 * @adapter: board private structure to initialize
5003 *
5004 * We allocate one q_vector per queue interrupt. If allocation fails we
5005 * return -ENOMEM.
5006 **/
5007static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
5008{
de88eeeb
AD		 5009 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5010 int rxr_remaining = adapter->num_rx_queues;
5011 int txr_remaining = adapter->num_tx_queues;
5012 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
5013 int err;
7a921c93 5014
de88eeeb
AD		 5015 /* only one q_vector if MSI-X is disabled. */
5016 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
5017 q_vectors = 1;
7a921c93 5018
de88eeeb
AD		 5019 if (q_vectors >= (rxr_remaining + txr_remaining)) {
5020 for (; rxr_remaining; v_idx++, q_vectors--) {
5021 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors);
5022 err = ixgbe_alloc_q_vector(adapter, v_idx,
5023 0, 0, rqpv, rxr_idx);
4ff7fb12 5024
de88eeeb
AD		 5025 if (err)
5026 goto err_out;
5027
5028 /* update counts and index */
5029 rxr_remaining -= rqpv;
5030 rxr_idx += rqpv;
5031 }
5032 }
4ff7fb12 5033
de88eeeb
AD		 5034 for (; q_vectors; v_idx++, q_vectors--) {
5035 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors);
5036 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors);
5037 err = ixgbe_alloc_q_vector(adapter, v_idx,
5038 tqpv, txr_idx,
5039 rqpv, rxr_idx);
5040
5041 if (err)
207867f5 5042 goto err_out;
de88eeeb
AD		 5043
5044 /* update counts and index */
5045 rxr_remaining -= rqpv;
5046 rxr_idx += rqpv;
5047 txr_remaining -= tqpv;
5048 txr_idx += tqpv;
7a921c93
AD		 5049 }
5050
5051 return 0;
5052
5053err_out:
4ff7fb12
AD		 5054 while (v_idx) {
5055 v_idx--;
de88eeeb 5056 ixgbe_free_q_vector(adapter, v_idx);
7a921c93 5057 }
de88eeeb 5058
7a921c93
AD		 5059 return -ENOMEM;
5060}
5061
5062/**
5063 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5064 * @adapter: board private structure to initialize
5065 *
5066 * This function frees the memory allocated to the q_vectors. In addition if
5067 * NAPI is enabled it will delete any references to the NAPI struct prior
5068 * to freeing the q_vector.
5069 **/
5070static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5071{
de88eeeb 5072 int v_idx, q_vectors;
7a921c93 5073
91281fd3 5074 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
de88eeeb 5075 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5076 else
de88eeeb 5077 q_vectors = 1;
7a921c93 5078
de88eeeb
AD		 5079 for (v_idx = 0; v_idx < q_vectors; v_idx++)
5080 ixgbe_free_q_vector(adapter, v_idx);
7a921c93
AD		 5081}
5082
7b25cdba 5083static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5084{
5085 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5086 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5087 pci_disable_msix(adapter->pdev);
5088 kfree(adapter->msix_entries);
5089 adapter->msix_entries = NULL;
5090 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5091 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5092 pci_disable_msi(adapter->pdev);
5093 }
021230d4
AV		 5094}
5095
5096/**
5097 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5098 * @adapter: board private structure to initialize
5099 *
5100 * We determine which interrupt scheme to use based on...
5101 * - Kernel support (MSI, MSI-X)
5102 * - which can be user-defined (via MODULE_PARAM)
5103 * - Hardware queue count (num_*_queues)
5104 * - defined by miscellaneous hardware support/features (RSS, etc.)
5105 **/
2f90b865 5106int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5107{
5108 int err;
5109
5110 /* Number of supported queues */
847f53ff
BH		 5111 err = ixgbe_set_num_queues(adapter);
5112 if (err)
5113 return err;
021230d4 5114
021230d4
AV		 5115 err = ixgbe_set_interrupt_capability(adapter);
5116 if (err) {
849c4542 5117 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5118 goto err_set_interrupt;
9a799d71
AK		 5119 }
5120
7a921c93
AD		 5121 err = ixgbe_alloc_q_vectors(adapter);
5122 if (err) {
849c4542 5123 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5124 goto err_alloc_q_vectors;
5125 }
5126
de88eeeb 5127 ixgbe_cache_ring_register(adapter);
7a921c93 5128
849c4542 5129 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5130 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5131 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5132
5133 set_bit(__IXGBE_DOWN, &adapter->state);
5134
9a799d71 5135 return 0;
021230d4 5136
7a921c93
AD		 5137err_alloc_q_vectors:
5138 ixgbe_reset_interrupt_capability(adapter);
021230d4 5139err_set_interrupt:
7a921c93
AD		 5140 return err;
5141}
5142
5143/**
5144 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5145 * @adapter: board private structure to clear interrupt scheme on
5146 *
5147 * We go through and clear interrupt specific resources and reset the structure
5148 * to pre-load conditions
5149 **/
5150void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5151{
b8eb3a10
DS		 5152 adapter->num_tx_queues = 0;
5153 adapter->num_rx_queues = 0;
5154
7a921c93
AD		 5155 ixgbe_free_q_vectors(adapter);
5156 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5157}
5158
5159/**
5160 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5161 * @adapter: board private structure to initialize
5162 *
5163 * ixgbe_sw_init initializes the Adapter private data structure.
5164 * Fields are initialized based on PCI device information and
5165 * OS network device settings (MTU size).
5166 **/
5167static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5168{
5169 struct ixgbe_hw *hw = &adapter->hw;
5170 struct pci_dev *pdev = adapter->pdev;
021230d4 5171 unsigned int rss;
7a6b6f51 5172#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5173 int j;
5174 struct tc_configuration *tc;
5175#endif
021230d4 5176
c44ade9e
JB		 5177 /* PCI config space info */
5178
5179 hw->vendor_id = pdev->vendor;
5180 hw->device_id = pdev->device;
5181 hw->revision_id = pdev->revision;
5182 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5183 hw->subsystem_device_id = pdev->subsystem_device;
5184
021230d4 5185 /* Set capability flags */
3ed69d7e 5186 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
021230d4
AV		 5187 adapter->ring_feature[RING_F_RSS].indices = rss;
5188 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5189 switch (hw->mac.type) {
5190 case ixgbe_mac_82598EB:
bf069c97
DS		 5191 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5192 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5193 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 5194 break;
b93a2226 5195 case ixgbe_mac_X540:
4f51bf70
JK		 5196 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5197 case ixgbe_mac_82599EB:
e8e26350 5198 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5199 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5200 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5201 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5202 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5203 /* Flow Director hash filters enabled */
5204 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5205 adapter->atr_sample_rate = 20;
c4cf55e5 5206 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5207 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5208 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5209#ifdef IXGBE_FCOE
0d551589
YZ		 5210 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5211 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5212 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5213#ifdef CONFIG_IXGBE_DCB
6ee16520 5214 /* Default traffic class to use for FCoE */
56075a98 5215 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5216#endif
eacd73f7 5217#endif /* IXGBE_FCOE */
bd508178
AD		 5218 break;
5219 default:
5220 break;
f8212f97 5221 }
2f90b865 5222
1fc5f038
AD		 5223 /* n-tuple support exists, always init our spinlock */
5224 spin_lock_init(&adapter->fdir_perfect_lock);
5225
7a6b6f51 5226#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5227 switch (hw->mac.type) {
5228 case ixgbe_mac_X540:
5229 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5230 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5231 break;
5232 default:
5233 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5234 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5235 break;
5236 }
5237
2f90b865
AD		 5238 /* Configure DCB traffic classes */
5239 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5240 tc = &adapter->dcb_cfg.tc_config[j];
5241 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5242 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5243 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5244 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5245 tc->dcb_pfc = pfc_disabled;
5246 }
4de2a022
JF		 5247
5248 /* Initialize default user to priority mapping, UPx->TC0 */
5249 tc = &adapter->dcb_cfg.tc_config[0];
5250 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5251 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5252
2f90b865
AD		 5253 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5254 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5255 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5256 adapter->dcb_set_bitmap = 0x00;
3032309b 5257 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5258 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5259 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5260
5261#endif
9a799d71
AK		 5262
5263 /* default flow control settings */
cd7664f6 5264 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5265 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5266#ifdef CONFIG_DCB
5267 adapter->last_lfc_mode = hw->fc.current_mode;
5268#endif
9da712d2 5269 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5270 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5271 hw->fc.send_xon = true;
71fd570b 5272 hw->fc.disable_fc_autoneg = false;
9a799d71 5273
30efa5a3 5274 /* enable itr by default in dynamic mode */
f7554a2b 5275 adapter->rx_itr_setting = 1;
f7554a2b 5276 adapter->tx_itr_setting = 1;
30efa5a3 5277
30efa5a3
JB		 5278 /* set default ring sizes */
5279 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5280 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5281
bd198058 5282 /* set default work limits */
59224555 5283 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5284
9a799d71 5285 /* initialize eeprom parameters */
c44ade9e 5286 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5287 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5288 return -EIO;
5289 }
5290
9a799d71
AK		 5291 set_bit(__IXGBE_DOWN, &adapter->state);
5292
5293 return 0;
5294}
5295
5296/**
5297 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5298 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5299 *
5300 * Return 0 on success, negative on failure
5301 **/
b6ec895e 5302int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5303{
b6ec895e 5304 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5305 int orig_node = dev_to_node(dev);
5306 int numa_node = -1;
9a799d71
AK		 5307 int size;
5308
3a581073 5309 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5310
5311 if (tx_ring->q_vector)
5312 numa_node = tx_ring->q_vector->numa_node;
5313
5314 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5315 if (!tx_ring->tx_buffer_info)
89bf67f1 5316 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5317 if (!tx_ring->tx_buffer_info)
5318 goto err;
9a799d71
AK		 5319
5320 /* round up to nearest 4K */
12207e49 5321 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5322 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5323
de88eeeb
AD		 5324 set_dev_node(dev, numa_node);
5325 tx_ring->desc = dma_alloc_coherent(dev,
5326 tx_ring->size,
5327 &tx_ring->dma,
5328 GFP_KERNEL);
5329 set_dev_node(dev, orig_node);
5330 if (!tx_ring->desc)
5331 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5332 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5333 if (!tx_ring->desc)
5334 goto err;
9a799d71 5335
3a581073
JB		 5336 tx_ring->next_to_use = 0;
5337 tx_ring->next_to_clean = 0;
9a799d71 5338 return 0;
e01c31a5
JB		 5339
5340err:
5341 vfree(tx_ring->tx_buffer_info);
5342 tx_ring->tx_buffer_info = NULL;
b6ec895e 5343 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5344 return -ENOMEM;
9a799d71
AK		 5345}
5346
69888674
AD		 5347/**
5348 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5349 * @adapter: board private structure
5350 *
5351 * If this function returns with an error, then it's possible one or
5352 * more of the rings is populated (while the rest are not). It is the
5353 * callers duty to clean those orphaned rings.
5354 *
5355 * Return 0 on success, negative on failure
5356 **/
5357static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5358{
5359 int i, err = 0;
5360
5361 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5362 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5363 if (!err)
5364 continue;
396e799c 5365 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5366 break;
5367 }
5368
5369 return err;
5370}
5371
9a799d71
AK		 5372/**
5373 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5374 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5375 *
5376 * Returns 0 on success, negative on failure
5377 **/
b6ec895e 5378int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5379{
b6ec895e 5380 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5381 int orig_node = dev_to_node(dev);
5382 int numa_node = -1;
021230d4 5383 int size;
9a799d71 5384
3a581073 5385 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5386
5387 if (rx_ring->q_vector)
5388 numa_node = rx_ring->q_vector->numa_node;
5389
5390 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5391 if (!rx_ring->rx_buffer_info)
89bf67f1 5392 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5393 if (!rx_ring->rx_buffer_info)
5394 goto err;
9a799d71 5395
9a799d71 5396 /* Round up to nearest 4K */
3a581073
JB		 5397 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5398 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5399
de88eeeb
AD		 5400 set_dev_node(dev, numa_node);
5401 rx_ring->desc = dma_alloc_coherent(dev,
5402 rx_ring->size,
5403 &rx_ring->dma,
5404 GFP_KERNEL);
5405 set_dev_node(dev, orig_node);
5406 if (!rx_ring->desc)
5407 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5408 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5409 if (!rx_ring->desc)
5410 goto err;
9a799d71 5411
3a581073
JB		 5412 rx_ring->next_to_clean = 0;
5413 rx_ring->next_to_use = 0;
9a799d71
AK		 5414
5415 return 0;
b6ec895e
AD		 5416err:
5417 vfree(rx_ring->rx_buffer_info);
5418 rx_ring->rx_buffer_info = NULL;
5419 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5420 return -ENOMEM;
9a799d71
AK		 5421}
5422
69888674
AD		 5423/**
5424 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5425 * @adapter: board private structure
5426 *
5427 * If this function returns with an error, then it's possible one or
5428 * more of the rings is populated (while the rest are not). It is the
5429 * callers duty to clean those orphaned rings.
5430 *
5431 * Return 0 on success, negative on failure
5432 **/
69888674
AD		 5433static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5434{
5435 int i, err = 0;
5436
5437 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5438 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5439 if (!err)
5440 continue;
396e799c 5441 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5442 break;
5443 }
5444
5445 return err;
5446}
5447
9a799d71
AK		 5448/**
5449 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5450 * @tx_ring: Tx descriptor ring for a specific queue
5451 *
5452 * Free all transmit software resources
5453 **/
b6ec895e 5454void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5455{
b6ec895e 5456 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5457
5458 vfree(tx_ring->tx_buffer_info);
5459 tx_ring->tx_buffer_info = NULL;
5460
b6ec895e
AD		 5461 /* if not set, then don't free */
5462 if (!tx_ring->desc)
5463 return;
5464
5465 dma_free_coherent(tx_ring->dev, tx_ring->size,
5466 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5467
5468 tx_ring->desc = NULL;
5469}
5470
5471/**
5472 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5473 * @adapter: board private structure
5474 *
5475 * Free all transmit software resources
5476 **/
5477static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5478{
5479 int i;
5480
5481 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5482 if (adapter->tx_ring[i]->desc)
b6ec895e 5483 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5484}
5485
5486/**
b4617240 5487 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5488 * @rx_ring: ring to clean the resources from
5489 *
5490 * Free all receive software resources
5491 **/
b6ec895e 5492void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5493{
b6ec895e 5494 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5495
5496 vfree(rx_ring->rx_buffer_info);
5497 rx_ring->rx_buffer_info = NULL;
5498
b6ec895e
AD		 5499 /* if not set, then don't free */
5500 if (!rx_ring->desc)
5501 return;
5502
5503 dma_free_coherent(rx_ring->dev, rx_ring->size,
5504 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5505
5506 rx_ring->desc = NULL;
5507}
5508
5509/**
5510 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5511 * @adapter: board private structure
5512 *
5513 * Free all receive software resources
5514 **/
5515static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5516{
5517 int i;
5518
5519 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5520 if (adapter->rx_ring[i]->desc)
b6ec895e 5521 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5522}
5523
9a799d71
AK		 5524/**
5525 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5526 * @netdev: network interface device structure
5527 * @new_mtu: new value for maximum frame size
5528 *
5529 * Returns 0 on success, negative on failure
5530 **/
5531static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5532{
5533 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5534 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5535 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5536
42c783c5 5537 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5538 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5539 hw->mac.type != ixgbe_mac_X540) {
5540 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5541 return -EINVAL;
5542 } else {
5543 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5544 return -EINVAL;
5545 }
9a799d71 5546
396e799c 5547 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5548 /* must set new MTU before calling down or up */
9a799d71
AK		 5549 netdev->mtu = new_mtu;
5550
d4f80882
AV		 5551 if (netif_running(netdev))
5552 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5553
5554 return 0;
5555}
5556
5557/**
5558 * ixgbe_open - Called when a network interface is made active
5559 * @netdev: network interface device structure
5560 *
5561 * Returns 0 on success, negative value on failure
5562 *
5563 * The open entry point is called when a network interface is made
5564 * active by the system (IFF_UP). At this point all resources needed
5565 * for transmit and receive operations are allocated, the interrupt
5566 * handler is registered with the OS, the watchdog timer is started,
5567 * and the stack is notified that the interface is ready.
5568 **/
5569static int ixgbe_open(struct net_device *netdev)
5570{
5571 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5572 int err;
4bebfaa5
AK		 5573
5574 /* disallow open during test */
5575 if (test_bit(__IXGBE_TESTING, &adapter->state))
5576 return -EBUSY;
9a799d71 5577
54386467
JB		 5578 netif_carrier_off(netdev);
5579
9a799d71
AK		 5580 /* allocate transmit descriptors */
5581 err = ixgbe_setup_all_tx_resources(adapter);
5582 if (err)
5583 goto err_setup_tx;
5584
9a799d71
AK		 5585 /* allocate receive descriptors */
5586 err = ixgbe_setup_all_rx_resources(adapter);
5587 if (err)
5588 goto err_setup_rx;
5589
5590 ixgbe_configure(adapter);
5591
021230d4 5592 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5593 if (err)
5594 goto err_req_irq;
5595
c7ccde0f 5596 ixgbe_up_complete(adapter);
9a799d71
AK		 5597
5598 return 0;
5599
9a799d71 5600err_req_irq:
9a799d71 5601err_setup_rx:
a20a1199 5602 ixgbe_free_all_rx_resources(adapter);
9a799d71 5603err_setup_tx:
a20a1199 5604 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5605 ixgbe_reset(adapter);
5606
5607 return err;
5608}
5609
5610/**
5611 * ixgbe_close - Disables a network interface
5612 * @netdev: network interface device structure
5613 *
5614 * Returns 0, this is not allowed to fail
5615 *
5616 * The close entry point is called when an interface is de-activated
5617 * by the OS. The hardware is still under the drivers control, but
5618 * needs to be disabled. A global MAC reset is issued to stop the
5619 * hardware, and all transmit and receive resources are freed.
5620 **/
5621static int ixgbe_close(struct net_device *netdev)
5622{
5623 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5624
5625 ixgbe_down(adapter);
5626 ixgbe_free_irq(adapter);
5627
e4911d57
AD		 5628 ixgbe_fdir_filter_exit(adapter);
5629
9a799d71
AK		 5630 ixgbe_free_all_tx_resources(adapter);
5631 ixgbe_free_all_rx_resources(adapter);
5632
5eba3699 5633 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5634
5635 return 0;
5636}
5637
b3c8b4ba
AD		 5638#ifdef CONFIG_PM
5639static int ixgbe_resume(struct pci_dev *pdev)
5640{
c60fbb00
AD		 5641 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5642 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5643 u32 err;
5644
5645 pci_set_power_state(pdev, PCI_D0);
5646 pci_restore_state(pdev);
656ab817
DS		 5647 /*
5648 * pci_restore_state clears dev->state_saved so call
5649 * pci_save_state to restore it.
5650 */
5651 pci_save_state(pdev);
9ce77666 5652
5653 err = pci_enable_device_mem(pdev);
b3c8b4ba 5654 if (err) {
849c4542 5655 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5656 return err;
5657 }
5658 pci_set_master(pdev);
5659
dd4d8ca6 5660 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5661
5662 err = ixgbe_init_interrupt_scheme(adapter);
5663 if (err) {
849c4542 5664 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5665 return err;
5666 }
5667
b3c8b4ba
AD		 5668 ixgbe_reset(adapter);
5669
495dce12
WJP		 5670 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5671
b3c8b4ba 5672 if (netif_running(netdev)) {
c60fbb00 5673 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5674 if (err)
5675 return err;
5676 }
5677
5678 netif_device_attach(netdev);
5679
5680 return 0;
5681}
b3c8b4ba 5682#endif /* CONFIG_PM */
9d8d05ae
RW		 5683
5684static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5685{
c60fbb00
AD		 5686 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5687 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5688 struct ixgbe_hw *hw = &adapter->hw;
5689 u32 ctrl, fctrl;
5690 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5691#ifdef CONFIG_PM
5692 int retval = 0;
5693#endif
5694
5695 netif_device_detach(netdev);
5696
5697 if (netif_running(netdev)) {
5698 ixgbe_down(adapter);
5699 ixgbe_free_irq(adapter);
5700 ixgbe_free_all_tx_resources(adapter);
5701 ixgbe_free_all_rx_resources(adapter);
5702 }
b3c8b4ba 5703
5f5ae6fc 5704 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5705#ifdef CONFIG_DCB
5706 kfree(adapter->ixgbe_ieee_pfc);
5707 kfree(adapter->ixgbe_ieee_ets);
5708#endif
5f5ae6fc 5709
b3c8b4ba
AD		 5710#ifdef CONFIG_PM
5711 retval = pci_save_state(pdev);
5712 if (retval)
5713 return retval;
4df10466 5714
b3c8b4ba 5715#endif
e8e26350
PW		 5716 if (wufc) {
5717 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5718
e8e26350
PW		 5719 /* turn on all-multi mode if wake on multicast is enabled */
5720 if (wufc & IXGBE_WUFC_MC) {
5721 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5722 fctrl |= IXGBE_FCTRL_MPE;
5723 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5724 }
5725
5726 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5727 ctrl |= IXGBE_CTRL_GIO_DIS;
5728 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5729
5730 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5731 } else {
5732 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5733 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5734 }
5735
bd508178
AD		 5736 switch (hw->mac.type) {
5737 case ixgbe_mac_82598EB:
dd4d8ca6 5738 pci_wake_from_d3(pdev, false);
bd508178
AD		 5739 break;
5740 case ixgbe_mac_82599EB:
b93a2226 5741 case ixgbe_mac_X540:
bd508178
AD		 5742 pci_wake_from_d3(pdev, !!wufc);
5743 break;
5744 default:
5745 break;
5746 }
b3c8b4ba 5747
9d8d05ae
RW		 5748 *enable_wake = !!wufc;
5749
b3c8b4ba
AD		 5750 ixgbe_release_hw_control(adapter);
5751
5752 pci_disable_device(pdev);
5753
9d8d05ae
RW		 5754 return 0;
5755}
5756
5757#ifdef CONFIG_PM
5758static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5759{
5760 int retval;
5761 bool wake;
5762
5763 retval = __ixgbe_shutdown(pdev, &wake);
5764 if (retval)
5765 return retval;
5766
5767 if (wake) {
5768 pci_prepare_to_sleep(pdev);
5769 } else {
5770 pci_wake_from_d3(pdev, false);
5771 pci_set_power_state(pdev, PCI_D3hot);
5772 }
b3c8b4ba
AD		 5773
5774 return 0;
5775}
9d8d05ae 5776#endif /* CONFIG_PM */
b3c8b4ba
AD		 5777
5778static void ixgbe_shutdown(struct pci_dev *pdev)
5779{
9d8d05ae
RW		 5780 bool wake;
5781
5782 __ixgbe_shutdown(pdev, &wake);
5783
5784 if (system_state == SYSTEM_POWER_OFF) {
5785 pci_wake_from_d3(pdev, wake);
5786 pci_set_power_state(pdev, PCI_D3hot);
5787 }
b3c8b4ba
AD		 5788}
5789
9a799d71
AK		 5790/**
5791 * ixgbe_update_stats - Update the board statistics counters.
5792 * @adapter: board private structure
5793 **/
5794void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5795{
2d86f139 5796 struct net_device *netdev = adapter->netdev;
9a799d71 5797 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5798 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5799 u64 total_mpc = 0;
5800 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5801 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5802 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5803 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7b859ebc
AH		 5804#ifdef IXGBE_FCOE
5805 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5806 unsigned int cpu;
5807 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5808#endif /* IXGBE_FCOE */
9a799d71 5809
d08935c2
DS		 5810 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5811 test_bit(__IXGBE_RESETTING, &adapter->state))
5812 return;
5813
94b982b2 5814 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5815 u64 rsc_count = 0;
94b982b2 5816 u64 rsc_flush = 0;
d51019a4
PW		 5817 for (i = 0; i < 16; i++)
5818 adapter->hw_rx_no_dma_resources +=
7ca647bd 5819 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5820 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5821 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5822 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5823 }
5824 adapter->rsc_total_count = rsc_count;
5825 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5826 }
5827
5b7da515
AD		 5828 for (i = 0; i < adapter->num_rx_queues; i++) {
5829 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5830 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5831 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5832 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5833 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5834 bytes += rx_ring->stats.bytes;
5835 packets += rx_ring->stats.packets;
5836 }
5837 adapter->non_eop_descs = non_eop_descs;
5838 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5839 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5840 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5841 netdev->stats.rx_bytes = bytes;
5842 netdev->stats.rx_packets = packets;
5843
5844 bytes = 0;
5845 packets = 0;
7ca3bc58 5846 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5847 for (i = 0; i < adapter->num_tx_queues; i++) {
5848 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5849 restart_queue += tx_ring->tx_stats.restart_queue;
5850 tx_busy += tx_ring->tx_stats.tx_busy;
5851 bytes += tx_ring->stats.bytes;
5852 packets += tx_ring->stats.packets;
5853 }
eb985f09 5854 adapter->restart_queue = restart_queue;
5b7da515
AD		 5855 adapter->tx_busy = tx_busy;
5856 netdev->stats.tx_bytes = bytes;
5857 netdev->stats.tx_packets = packets;
7ca3bc58 5858
7ca647bd 5859 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5860
5861 /* 8 register reads */
6f11eef7
AV		 5862 for (i = 0; i < 8; i++) {
5863 /* for packet buffers not used, the register should read 0 */
5864 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5865 missed_rx += mpc;
7ca647bd
JP		 5866 hwstats->mpc[i] += mpc;
5867 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5868 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5869 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5870 switch (hw->mac.type) {
5871 case ixgbe_mac_82598EB:
1a70db4b
ET		 5872 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5873 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5874 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5875 hwstats->pxonrxc[i] +=
5876 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5877 break;
5878 case ixgbe_mac_82599EB:
b93a2226 5879 case ixgbe_mac_X540:
bd508178
AD		 5880 hwstats->pxonrxc[i] +=
5881 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5882 break;
5883 default:
5884 break;
e8e26350 5885 }
6f11eef7 5886 }
1a70db4b
ET		 5887
5888 /*16 register reads */
5889 for (i = 0; i < 16; i++) {
5890 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5891 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5892 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5893 (hw->mac.type == ixgbe_mac_X540)) {
5894 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5895 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5896 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5897 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5898 }
5899 }
5900
7ca647bd 5901 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5902 /* work around hardware counting issue */
7ca647bd 5903 hwstats->gprc -= missed_rx;
6f11eef7 5904
c84d324c
JF		 5905 ixgbe_update_xoff_received(adapter);
5906
6f11eef7 5907 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5908 switch (hw->mac.type) {
5909 case ixgbe_mac_82598EB:
5910 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5911 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5912 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5913 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5914 break;
b93a2226 5915 case ixgbe_mac_X540:
58f6bcf9
ET		 5916 /* OS2BMC stats are X540 only*/
5917 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5918 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5919 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5920 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5921 case ixgbe_mac_82599EB:
7ca647bd 5922 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5923 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5924 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5925 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5926 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5927 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5928 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5929 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5930 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5931#ifdef IXGBE_FCOE
7ca647bd
JP		 5932 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5933 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5934 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5935 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5936 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5937 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5938 /* Add up per cpu counters for total ddp aloc fail */
5939 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5940 for_each_possible_cpu(cpu) {
5941 fcoe_noddp_counts_sum +=
5942 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5943 fcoe_noddp_ext_buff_counts_sum +=
5944 *per_cpu_ptr(fcoe->
5945 pcpu_noddp_ext_buff, cpu);
5946 }
5947 }
5948 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5949 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5950#endif /* IXGBE_FCOE */
bd508178
AD		 5951 break;
5952 default:
5953 break;
e8e26350 5954 }
9a799d71 5955 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5956 hwstats->bprc += bprc;
5957 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5958 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5959 hwstats->mprc -= bprc;
5960 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5961 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5962 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5963 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5964 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5965 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5966 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5967 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5968 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5969 hwstats->lxontxc += lxon;
6f11eef7 5970 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5971 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5972 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5973 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5974 /*
5975 * 82598 errata - tx of flow control packets is included in tx counters
5976 */
5977 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5978 hwstats->gptc -= xon_off_tot;
5979 hwstats->mptc -= xon_off_tot;
5980 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5981 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5982 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5983 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5984 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5985 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5986 hwstats->ptc64 -= xon_off_tot;
5987 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5988 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5989 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5990 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5991 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5992 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5993
5994 /* Fill out the OS statistics structure */
7ca647bd 5995 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5996
5997 /* Rx Errors */
7ca647bd 5998 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5999 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6000 netdev->stats.rx_length_errors = hwstats->rlec;
6001 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6002 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6003}
6004
6005/**
d034acf1
AD		 6006 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6007 * @adapter - pointer to the device adapter structure
9a799d71 6008 **/
d034acf1 6009static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6010{
cf8280ee 6011 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6012 int i;
cf8280ee 6013
d034acf1
AD		 6014 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6015 return;
6016
6017 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6018
d034acf1 6019 /* if interface is down do nothing */
fe49f04a 6020 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6021 return;
6022
6023 /* do nothing if we are not using signature filters */
6024 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6025 return;
6026
6027 adapter->fdir_overflow++;
6028
93c52dd0
AD		 6029 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6030 for (i = 0; i < adapter->num_tx_queues; i++)
6031 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 6032 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6033 /* re-enable flow director interrupts */
6034 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6035 } else {
6036 e_err(probe, "failed to finish FDIR re-initialization, "
6037 "ignored adding FDIR ATR filters\n");
6038 }
93c52dd0
AD		 6039}
6040
6041/**
6042 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6043 * @adapter - pointer to the device adapter structure
6044 *
6045 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6046 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6047 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6048 * determine if a hang has occurred.
93c52dd0
AD		 6049 */
6050static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6051{
cf8280ee 6052 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6053 u64 eics = 0;
6054 int i;
cf8280ee 6055
93c52dd0
AD		 6056 /* If we're down or resetting, just bail */
6057 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6058 test_bit(__IXGBE_RESETTING, &adapter->state))
6059 return;
22d5a71b 6060
93c52dd0
AD		 6061 /* Force detection of hung controller */
6062 if (netif_carrier_ok(adapter->netdev)) {
6063 for (i = 0; i < adapter->num_tx_queues; i++)
6064 set_check_for_tx_hang(adapter->tx_ring[i]);
6065 }
22d5a71b 6066
fe49f04a
AD		 6067 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6068 /*
6069 * for legacy and MSI interrupts don't set any bits
6070 * that are enabled for EIAM, because this operation
6071 * would set *both* EIMS and EICS for any bit in EIAM
6072 */
6073 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6074 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6075 } else {
6076 /* get one bit for every active tx/rx interrupt vector */
6077 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6078 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6079 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6080 eics |= ((u64)1 << i);
6081 }
cf8280ee 6082 }
9a799d71 6083
93c52dd0 6084 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6085 ixgbe_irq_rearm_queues(adapter, eics);
6086
cf8280ee
JB		 6087}
6088
e8e26350 6089/**
93c52dd0
AD		 6090 * ixgbe_watchdog_update_link - update the link status
6091 * @adapter - pointer to the device adapter structure
6092 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 6093 **/
93c52dd0 6094static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6095{
e8e26350 6096 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6097 u32 link_speed = adapter->link_speed;
6098 bool link_up = adapter->link_up;
c4cf55e5 6099 int i;
e8e26350 6100
93c52dd0
AD		 6101 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6102 return;
6103
6104 if (hw->mac.ops.check_link) {
6105 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6106 } else {
93c52dd0
AD		 6107 /* always assume link is up, if no check link function */
6108 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6109 link_up = true;
c4cf55e5 6110 }
93c52dd0
AD		 6111 if (link_up) {
6112 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6113 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6114 hw->mac.ops.fc_enable(hw, i);
6115 } else {
6116 hw->mac.ops.fc_enable(hw, 0);
6117 }
6118 }
6119
6120 if (link_up ||
6121 time_after(jiffies, (adapter->link_check_timeout +
6122 IXGBE_TRY_LINK_TIMEOUT))) {
6123 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6124 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6125 IXGBE_WRITE_FLUSH(hw);
6126 }
6127
6128 adapter->link_up = link_up;
6129 adapter->link_speed = link_speed;
e8e26350
PW		 6130}
6131
6132/**
93c52dd0
AD		 6133 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6134 * print link up message
6135 * @adapter - pointer to the device adapter structure
e8e26350 6136 **/
93c52dd0 6137static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6138{
93c52dd0 6139 struct net_device *netdev = adapter->netdev;
e8e26350 6140 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6141 u32 link_speed = adapter->link_speed;
6142 bool flow_rx, flow_tx;
e8e26350 6143
93c52dd0
AD		 6144 /* only continue if link was previously down */
6145 if (netif_carrier_ok(netdev))
a985b6c3 6146 return;
63d6e1d8 6147
93c52dd0 6148 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6149
93c52dd0
AD		 6150 switch (hw->mac.type) {
6151 case ixgbe_mac_82598EB: {
6152 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6153 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6154 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6155 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6156 }
6157 break;
6158 case ixgbe_mac_X540:
6159 case ixgbe_mac_82599EB: {
6160 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6161 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6162 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6163 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6164 }
6165 break;
6166 default:
6167 flow_tx = false;
6168 flow_rx = false;
6169 break;
e8e26350 6170 }
93c52dd0
AD		 6171 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6172 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6173 "10 Gbps" :
6174 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6175 "1 Gbps" :
6176 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6177 "100 Mbps" :
6178 "unknown speed"))),
6179 ((flow_rx && flow_tx) ? "RX/TX" :
6180 (flow_rx ? "RX" :
6181 (flow_tx ? "TX" : "None"))));
e8e26350 6182
93c52dd0 6183 netif_carrier_on(netdev);
93c52dd0 6184 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 6185}
6186
c4cf55e5 6187/**
93c52dd0
AD		 6188 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6189 * print link down message
6190 * @adapter - pointer to the adapter structure
c4cf55e5 6191 **/
93c52dd0 6192static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6193{
cf8280ee 6194 struct net_device *netdev = adapter->netdev;
c4cf55e5 6195 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6196
93c52dd0
AD		 6197 adapter->link_up = false;
6198 adapter->link_speed = 0;
cf8280ee 6199
93c52dd0
AD		 6200 /* only continue if link was up previously */
6201 if (!netif_carrier_ok(netdev))
6202 return;
264857b8 6203
93c52dd0
AD		 6204 /* poll for SFP+ cable when link is down */
6205 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6206 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6207
93c52dd0
AD		 6208 e_info(drv, "NIC Link is Down\n");
6209 netif_carrier_off(netdev);
6210}
e8e26350 6211
93c52dd0
AD		 6212/**
6213 * ixgbe_watchdog_flush_tx - flush queues on link down
6214 * @adapter - pointer to the device adapter structure
6215 **/
6216static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6217{
c4cf55e5 6218 int i;
93c52dd0 6219 int some_tx_pending = 0;
c4cf55e5 6220
93c52dd0 6221 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6222 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6223 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6224 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6225 some_tx_pending = 1;
6226 break;
6227 }
6228 }
6229
6230 if (some_tx_pending) {
6231 /* We've lost link, so the controller stops DMA,
6232 * but we've got queued Tx work that's never going
6233 * to get done, so reset controller to flush Tx.
6234 * (Do the reset outside of interrupt context).
6235 */
c83c6cbd 6236 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6237 }
c4cf55e5 6238 }
c4cf55e5
PWJ		 6239}
6240
a985b6c3
GR		 6241static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6242{
6243 u32 ssvpc;
6244
6245 /* Do not perform spoof check for 82598 */
6246 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6247 return;
6248
6249 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6250
6251 /*
6252 * ssvpc register is cleared on read, if zero then no
6253 * spoofed packets in the last interval.
6254 */
6255 if (!ssvpc)
6256 return;
6257
6258 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6259}
6260
93c52dd0
AD		 6261/**
6262 * ixgbe_watchdog_subtask - check and bring link up
6263 * @adapter - pointer to the device adapter structure
6264 **/
6265static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6266{
6267 /* if interface is down do nothing */
7edebf9a
ET		 6268 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6269 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6270 return;
6271
6272 ixgbe_watchdog_update_link(adapter);
6273
6274 if (adapter->link_up)
6275 ixgbe_watchdog_link_is_up(adapter);
6276 else
6277 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6278
a985b6c3 6279 ixgbe_spoof_check(adapter);
9a799d71 6280 ixgbe_update_stats(adapter);
93c52dd0
AD		 6281
6282 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6283}
10eec955 6284
cf8280ee 6285/**
7086400d
AD		 6286 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6287 * @adapter - the ixgbe adapter structure
cf8280ee 6288 **/
7086400d 6289static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6290{
cf8280ee 6291 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6292 s32 err;
cf8280ee 6293
7086400d
AD		 6294 /* not searching for SFP so there is nothing to do here */
6295 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6296 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6297 return;
10eec955 6298
7086400d
AD		 6299 /* someone else is in init, wait until next service event */
6300 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6301 return;
cf8280ee 6302
7086400d
AD		 6303 err = hw->phy.ops.identify_sfp(hw);
6304 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6305 goto sfp_out;
264857b8 6306
7086400d
AD		 6307 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6308 /* If no cable is present, then we need to reset
6309 * the next time we find a good cable. */
6310 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6311 }
9a799d71 6312
7086400d
AD		 6313 /* exit on error */
6314 if (err)
6315 goto sfp_out;
e8e26350 6316
7086400d
AD		 6317 /* exit if reset not needed */
6318 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6319 goto sfp_out;
9a799d71 6320
7086400d 6321 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6322
7086400d
AD		 6323 /*
6324 * A module may be identified correctly, but the EEPROM may not have
6325 * support for that module. setup_sfp() will fail in that case, so
6326 * we should not allow that module to load.
6327 */
6328 if (hw->mac.type == ixgbe_mac_82598EB)
6329 err = hw->phy.ops.reset(hw);
6330 else
6331 err = hw->mac.ops.setup_sfp(hw);
6332
6333 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6334 goto sfp_out;
6335
6336 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6337 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6338
6339sfp_out:
6340 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6341
6342 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6343 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6344 e_dev_err("failed to initialize because an unsupported "
6345 "SFP+ module type was detected.\n");
6346 e_dev_err("Reload the driver after installing a "
6347 "supported module.\n");
6348 unregister_netdev(adapter->netdev);
bc59fcda 6349 }
7086400d 6350}
bc59fcda 6351
7086400d
AD		 6352/**
6353 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6354 * @adapter - the ixgbe adapter structure
6355 **/
6356static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6357{
6358 struct ixgbe_hw *hw = &adapter->hw;
6359 u32 autoneg;
6360 bool negotiation;
6361
6362 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6363 return;
6364
6365 /* someone else is in init, wait until next service event */
6366 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6367 return;
6368
6369 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6370
6371 autoneg = hw->phy.autoneg_advertised;
6372 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6373 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6374 if (hw->mac.ops.setup_link)
6375 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6376
6377 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6378 adapter->link_check_timeout = jiffies;
6379 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6380}
6381
83c61fa9
GR		 6382#ifdef CONFIG_PCI_IOV
6383static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6384{
6385 int vf;
6386 struct ixgbe_hw *hw = &adapter->hw;
6387 struct net_device *netdev = adapter->netdev;
6388 u32 gpc;
6389 u32 ciaa, ciad;
6390
6391 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6392 if (gpc) /* If incrementing then no need for the check below */
6393 return;
6394 /*
6395 * Check to see if a bad DMA write target from an errant or
6396 * malicious VF has caused a PCIe error. If so then we can
6397 * issue a VFLR to the offending VF(s) and then resume without
6398 * requesting a full slot reset.
6399 */
6400
6401 for (vf = 0; vf < adapter->num_vfs; vf++) {
6402 ciaa = (vf << 16) | 0x80000000;
6403 /* 32 bit read so align, we really want status at offset 6 */
6404 ciaa |= PCI_COMMAND;
6405 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6406 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6407 ciaa &= 0x7FFFFFFF;
6408 /* disable debug mode asap after reading data */
6409 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6410 /* Get the upper 16 bits which will be the PCI status reg */
6411 ciad >>= 16;
6412 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6413 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6414 /* Issue VFLR */
6415 ciaa = (vf << 16) | 0x80000000;
6416 ciaa |= 0xA8;
6417 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6418 ciad = 0x00008000; /* VFLR */
6419 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6420 ciaa &= 0x7FFFFFFF;
6421 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6422 }
6423 }
6424}
6425
6426#endif
7086400d
AD		 6427/**
6428 * ixgbe_service_timer - Timer Call-back
6429 * @data: pointer to adapter cast into an unsigned long
6430 **/
6431static void ixgbe_service_timer(unsigned long data)
6432{
6433 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6434 unsigned long next_event_offset;
83c61fa9 6435 bool ready = true;
7086400d 6436
83c61fa9
GR		 6437#ifdef CONFIG_PCI_IOV
6438 ready = false;
6439
6440 /*
6441 * don't bother with SR-IOV VF DMA hang check if there are
6442 * no VFs or the link is down
6443 */
6444 if (!adapter->num_vfs ||
6445 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6446 ready = true;
6447 goto normal_timer_service;
6448 }
6449
6450 /* If we have VFs allocated then we must check for DMA hangs */
6451 ixgbe_check_for_bad_vf(adapter);
6452 next_event_offset = HZ / 50;
6453 adapter->timer_event_accumulator++;
6454
6455 if (adapter->timer_event_accumulator >= 100) {
6456 ready = true;
6457 adapter->timer_event_accumulator = 0;
6458 }
6459
6460 goto schedule_event;
6461
6462normal_timer_service:
6463#endif
7086400d
AD		 6464 /* poll faster when waiting for link */
6465 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6466 next_event_offset = HZ / 10;
6467 else
6468 next_event_offset = HZ * 2;
6469
83c61fa9
GR		 6470#ifdef CONFIG_PCI_IOV
6471schedule_event:
6472#endif
7086400d
AD		 6473 /* Reset the timer */
6474 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6475
83c61fa9
GR		 6476 if (ready)
6477 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6478}
6479
c83c6cbd
AD		 6480static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6481{
6482 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6483 return;
6484
6485 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6486
6487 /* If we're already down or resetting, just bail */
6488 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6489 test_bit(__IXGBE_RESETTING, &adapter->state))
6490 return;
6491
6492 ixgbe_dump(adapter);
6493 netdev_err(adapter->netdev, "Reset adapter\n");
6494 adapter->tx_timeout_count++;
6495
6496 ixgbe_reinit_locked(adapter);
6497}
6498
7086400d
AD		 6499/**
6500 * ixgbe_service_task - manages and runs subtasks
6501 * @work: pointer to work_struct containing our data
6502 **/
6503static void ixgbe_service_task(struct work_struct *work)
6504{
6505 struct ixgbe_adapter *adapter = container_of(work,
6506 struct ixgbe_adapter,
6507 service_task);
6508
c83c6cbd 6509 ixgbe_reset_subtask(adapter);
7086400d
AD		 6510 ixgbe_sfp_detection_subtask(adapter);
6511 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6512 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6513 ixgbe_watchdog_subtask(adapter);
d034acf1 6514 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6515 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6516
6517 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6518}
6519
897ab156
AD		 6520void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6521 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6522{
6523 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6524 u16 i = tx_ring->next_to_use;
9a799d71 6525
e4f74028 6526 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
9a799d71 6527
897ab156
AD		 6528 i++;
6529 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6530
897ab156
AD		 6531 /* set bits to identify this as an advanced context descriptor */
6532 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6533
897ab156
AD		 6534 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6535 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6536 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6537 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6538}
9a799d71 6539
897ab156
AD		 6540static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6541 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6542{
6543 int err;
6544 u32 vlan_macip_lens, type_tucmd;
6545 u32 mss_l4len_idx, l4len;
9a799d71 6546
897ab156
AD		 6547 if (!skb_is_gso(skb))
6548 return 0;
9a799d71 6549
897ab156
AD		 6550 if (skb_header_cloned(skb)) {
6551 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6552 if (err)
6553 return err;
9a799d71 6554 }
9a799d71 6555
897ab156
AD		 6556 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6557 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6558
6559 if (protocol == __constant_htons(ETH_P_IP)) {
6560 struct iphdr *iph = ip_hdr(skb);
6561 iph->tot_len = 0;
6562 iph->check = 0;
6563 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6564 iph->daddr, 0,
6565 IPPROTO_TCP,
6566 0);
6567 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6568 } else if (skb_is_gso_v6(skb)) {
6569 ipv6_hdr(skb)->payload_len = 0;
6570 tcp_hdr(skb)->check =
6571 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6572 &ipv6_hdr(skb)->daddr,
6573 0, IPPROTO_TCP, 0);
6574 }
6575
6576 l4len = tcp_hdrlen(skb);
6577 *hdr_len = skb_transport_offset(skb) + l4len;
6578
6579 /* mss_l4len_id: use 1 as index for TSO */
6580 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6581 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6582 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6583
6584 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6585 vlan_macip_lens = skb_network_header_len(skb);
6586 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6587 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6588
6589 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6590 mss_l4len_idx);
6591
6592 return 1;
6593}
6594
6595static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6596 struct sk_buff *skb, u32 tx_flags,
6597 __be16 protocol)
7ca647bd 6598{
897ab156
AD		 6599 u32 vlan_macip_lens = 0;
6600 u32 mss_l4len_idx = 0;
6601 u32 type_tucmd = 0;
7ca647bd 6602
897ab156 6603 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6604 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6605 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6606 return false;
6607 } else {
6608 u8 l4_hdr = 0;
6609 switch (protocol) {
6610 case __constant_htons(ETH_P_IP):
6611 vlan_macip_lens |= skb_network_header_len(skb);
6612 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6613 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6614 break;
897ab156
AD		 6615 case __constant_htons(ETH_P_IPV6):
6616 vlan_macip_lens |= skb_network_header_len(skb);
6617 l4_hdr = ipv6_hdr(skb)->nexthdr;
6618 break;
6619 default:
6620 if (unlikely(net_ratelimit())) {
6621 dev_warn(tx_ring->dev,
6622 "partial checksum but proto=%x!\n",
6623 skb->protocol);
6624 }
7ca647bd
JP		 6625 break;
6626 }
897ab156
AD		 6627
6628 switch (l4_hdr) {
7ca647bd 6629 case IPPROTO_TCP:
897ab156
AD		 6630 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6631 mss_l4len_idx = tcp_hdrlen(skb) <<
6632 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6633 break;
6634 case IPPROTO_SCTP:
897ab156
AD		 6635 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6636 mss_l4len_idx = sizeof(struct sctphdr) <<
6637 IXGBE_ADVTXD_L4LEN_SHIFT;
6638 break;
6639 case IPPROTO_UDP:
6640 mss_l4len_idx = sizeof(struct udphdr) <<
6641 IXGBE_ADVTXD_L4LEN_SHIFT;
6642 break;
6643 default:
6644 if (unlikely(net_ratelimit())) {
6645 dev_warn(tx_ring->dev,
6646 "partial checksum but l4 proto=%x!\n",
6647 skb->protocol);
6648 }
7ca647bd
JP		 6649 break;
6650 }
7ca647bd
JP		 6651 }
6652
897ab156
AD		 6653 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6654 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6655
897ab156
AD		 6656 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6657 type_tucmd, mss_l4len_idx);
9a799d71 6658
897ab156 6659 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6660}
6661
d3d00239 6662static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6663{
d3d00239
AD		 6664 /* set type for advanced descriptor with frame checksum insertion */
6665 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6666 IXGBE_ADVTXD_DCMD_IFCS |
6667 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6668
d3d00239 6669 /* set HW vlan bit if vlan is present */
66f32a8b 6670 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6671 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6672
d3d00239
AD		 6673 /* set segmentation enable bits for TSO/FSO */
6674#ifdef IXGBE_FCOE
6675 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6676#else
6677 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6678#endif
6679 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6680
d3d00239
AD		 6681 return cmd_type;
6682}
9a799d71 6683
d3d00239
AD		 6684static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6685{
6686 __le32 olinfo_status =
6687 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6688
d3d00239
AD		 6689 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6690 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6691 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6692 /* enble IPv4 checksum for TSO */
6693 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6694 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6695 }
6696
d3d00239
AD		 6697 /* enable L4 checksum for TSO and TX checksum offload */
6698 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6699 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6700
d3d00239
AD		 6701#ifdef IXGBE_FCOE
6702 /* use index 1 context for FCOE/FSO */
6703 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6704 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6705 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6706
d3d00239 6707#endif
7f9643fd
AD		 6708 /*
6709 * Check Context must be set if Tx switch is enabled, which it
6710 * always is for case where virtual functions are running
6711 */
6712 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6713 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6714
d3d00239
AD		 6715 return olinfo_status;
6716}
44df32c5 6717
d3d00239
AD		 6718#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6719 IXGBE_TXD_CMD_RS)
6720
6721static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6722 struct sk_buff *skb,
6723 struct ixgbe_tx_buffer *first,
6724 u32 tx_flags,
6725 const u8 hdr_len)
6726{
6727 struct device *dev = tx_ring->dev;
6728 struct ixgbe_tx_buffer *tx_buffer_info;
6729 union ixgbe_adv_tx_desc *tx_desc;
6730 dma_addr_t dma;
6731 __le32 cmd_type, olinfo_status;
6732 struct skb_frag_struct *frag;
6733 unsigned int f = 0;
6734 unsigned int data_len = skb->data_len;
6735 unsigned int size = skb_headlen(skb);
6736 u32 offset = 0;
6737 u32 paylen = skb->len - hdr_len;
6738 u16 i = tx_ring->next_to_use;
6739 u16 gso_segs;
6740
6741#ifdef IXGBE_FCOE
6742 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6743 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6744 data_len -= sizeof(struct fcoe_crc_eof);
6745 } else {
6746 size -= sizeof(struct fcoe_crc_eof) - data_len;
6747 data_len = 0;
9a799d71
AK		 6748 }
6749 }
44df32c5 6750
d3d00239
AD		 6751#endif
6752 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6753 if (dma_mapping_error(dev, dma))
6754 goto dma_error;
8ad494b0 6755
d3d00239
AD		 6756 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6757 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6758
e4f74028 6759 tx_desc = IXGBE_TX_DESC(tx_ring, i);
e5a43549 6760
d3d00239
AD		 6761 for (;;) {
6762 while (size > IXGBE_MAX_DATA_PER_TXD) {
6763 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6764 tx_desc->read.cmd_type_len =
6765 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6766 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6767
d3d00239
AD		 6768 offset += IXGBE_MAX_DATA_PER_TXD;
6769 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6770
d3d00239
AD		 6771 tx_desc++;
6772 i++;
6773 if (i == tx_ring->count) {
e4f74028 6774 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6775 i = 0;
6776 }
6777 }
e5a43549 6778
e5a43549 6779 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6780 tx_buffer_info->length = offset + size;
6781 tx_buffer_info->tx_flags = tx_flags;
6782 tx_buffer_info->dma = dma;
9a799d71 6783
d3d00239 6784 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
f43f313e
BG		 6785 if (unlikely(skb->no_fcs))
6786 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239
AD		 6787 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6788 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6789
d3d00239
AD		 6790 if (!data_len)
6791 break;
9a799d71 6792
d3d00239
AD		 6793 frag = &skb_shinfo(skb)->frags[f];
6794#ifdef IXGBE_FCOE
9e903e08 6795 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6796#else
9e903e08 6797 size = skb_frag_size(frag);
d3d00239
AD		 6798#endif
6799 data_len -= size;
6800 f++;
9a799d71 6801
d3d00239
AD		 6802 offset = 0;
6803 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6804
877749bf 6805 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6806 if (dma_mapping_error(dev, dma))
6807 goto dma_error;
9a799d71 6808
d3d00239
AD		 6809 tx_desc++;
6810 i++;
6811 if (i == tx_ring->count) {
e4f74028 6812 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6813 i = 0;
6814 }
6815 }
9a799d71 6816
d3d00239 6817 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6818
d3d00239
AD		 6819 i++;
6820 if (i == tx_ring->count)
6821 i = 0;
9a799d71 6822
d3d00239 6823 tx_ring->next_to_use = i;
eacd73f7 6824
d3d00239
AD		 6825 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6826 gso_segs = skb_shinfo(skb)->gso_segs;
6827#ifdef IXGBE_FCOE
6828 /* adjust for FCoE Sequence Offload */
6829 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6830 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6831 skb_shinfo(skb)->gso_size);
6832#endif /* IXGBE_FCOE */
6833 else
6834 gso_segs = 1;
9a799d71 6835
d3d00239
AD		 6836 /* multiply data chunks by size of headers */
6837 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6838 tx_buffer_info->gso_segs = gso_segs;
6839 tx_buffer_info->skb = skb;
9a799d71 6840
b2d96e0a
AD		 6841 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer_info->bytecount);
6842
d3d00239
AD		 6843 /* set the timestamp */
6844 first->time_stamp = jiffies;
9a799d71
AK		 6845
6846 /*
6847 * Force memory writes to complete before letting h/w
6848 * know there are new descriptors to fetch. (Only
6849 * applicable for weak-ordered memory model archs,
6850 * such as IA-64).
6851 */
6852 wmb();
6853
d3d00239
AD		 6854 /* set next_to_watch value indicating a packet is present */
6855 first->next_to_watch = tx_desc;
6856
6857 /* notify HW of packet */
84ea2591 6858 writel(i, tx_ring->tail);
d3d00239
AD		 6859
6860 return;
6861dma_error:
6862 dev_err(dev, "TX DMA map failed\n");
6863
6864 /* clear dma mappings for failed tx_buffer_info map */
6865 for (;;) {
6866 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6867 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6868 if (tx_buffer_info == first)
6869 break;
6870 if (i == 0)
6871 i = tx_ring->count;
6872 i--;
6873 }
6874
6875 dev_kfree_skb_any(skb);
6876
6877 tx_ring->next_to_use = i;
9a799d71
AK		 6878}
6879
69830529
AD		 6880static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6881 u32 tx_flags, __be16 protocol)
6882{
6883 struct ixgbe_q_vector *q_vector = ring->q_vector;
6884 union ixgbe_atr_hash_dword input = { .dword = 0 };
6885 union ixgbe_atr_hash_dword common = { .dword = 0 };
6886 union {
6887 unsigned char *network;
6888 struct iphdr *ipv4;
6889 struct ipv6hdr *ipv6;
6890 } hdr;
ee9e0f0b 6891 struct tcphdr *th;
905e4a41 6892 __be16 vlan_id;
c4cf55e5 6893
69830529
AD		 6894 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6895 if (!q_vector)
6896 return;
6897
6898 /* do nothing if sampling is disabled */
6899 if (!ring->atr_sample_rate)
d3ead241 6900 return;
c4cf55e5 6901
69830529 6902 ring->atr_count++;
c4cf55e5 6903
69830529
AD		 6904 /* snag network header to get L4 type and address */
6905 hdr.network = skb_network_header(skb);
6906
6907 /* Currently only IPv4/IPv6 with TCP is supported */
6908 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6909 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6910 (protocol != __constant_htons(ETH_P_IP) ||
6911 hdr.ipv4->protocol != IPPROTO_TCP))
6912 return;
ee9e0f0b
AD		 6913
6914 th = tcp_hdr(skb);
c4cf55e5 6915
66f32a8b
AD		 6916 /* skip this packet since it is invalid or the socket is closing */
6917 if (!th || th->fin)
69830529
AD		 6918 return;
6919
6920 /* sample on all syn packets or once every atr sample count */
6921 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6922 return;
6923
6924 /* reset sample count */
6925 ring->atr_count = 0;
6926
6927 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6928
6929 /*
6930 * src and dst are inverted, think how the receiver sees them
6931 *
6932 * The input is broken into two sections, a non-compressed section
6933 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6934 * is XORed together and stored in the compressed dword.
6935 */
6936 input.formatted.vlan_id = vlan_id;
6937
6938 /*
6939 * since src port and flex bytes occupy the same word XOR them together
6940 * and write the value to source port portion of compressed dword
6941 */
66f32a8b 6942 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6943 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6944 else
6945 common.port.src ^= th->dest ^ protocol;
6946 common.port.dst ^= th->source;
6947
6948 if (protocol == __constant_htons(ETH_P_IP)) {
6949 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6950 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6951 } else {
6952 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6953 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6954 hdr.ipv6->saddr.s6_addr32[1] ^
6955 hdr.ipv6->saddr.s6_addr32[2] ^
6956 hdr.ipv6->saddr.s6_addr32[3] ^
6957 hdr.ipv6->daddr.s6_addr32[0] ^
6958 hdr.ipv6->daddr.s6_addr32[1] ^
6959 hdr.ipv6->daddr.s6_addr32[2] ^
6960 hdr.ipv6->daddr.s6_addr32[3];
6961 }
c4cf55e5
PWJ		 6962
6963 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6964 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6965 input, common, ring->queue_index);
c4cf55e5
PWJ		 6966}
6967
63544e9c 6968static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6969{
fc77dc3c 6970 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6971 /* Herbert's original patch had:
6972 * smp_mb__after_netif_stop_queue();
6973 * but since that doesn't exist yet, just open code it. */
6974 smp_mb();
6975
6976 /* We need to check again in a case another CPU has just
6977 * made room available. */
7d4987de 6978 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6979 return -EBUSY;
6980
6981 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6982 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6983 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6984 return 0;
6985}
6986
82d4e46e 6987static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6988{
7d4987de 6989 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6990 return 0;
fc77dc3c 6991 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6992}
6993
09a3b1f8
SH		 6994static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6995{
6996 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6997 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6998 smp_processor_id();
56075a98 6999#ifdef IXGBE_FCOE
6440752c 7000 __be16 protocol = vlan_get_protocol(skb);
5e09a105 7001
e5b64635
JF		 7002 if (((protocol == htons(ETH_P_FCOE)) ||
7003 (protocol == htons(ETH_P_FIP))) &&
7004 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
7005 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
7006 txq += adapter->ring_feature[RING_F_FCOE].mask;
7007 return txq;
56075a98
JF		 7008 }
7009#endif
7010
fdd3d631
KK		 7011 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
7012 while (unlikely(txq >= dev->real_num_tx_queues))
7013 txq -= dev->real_num_tx_queues;
5f715823 7014 return txq;
fdd3d631 7015 }
c4cf55e5 7016
09a3b1f8
SH		 7017 return skb_tx_hash(dev, skb);
7018}
7019
fc77dc3c 7020netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7021 struct ixgbe_adapter *adapter,
7022 struct ixgbe_ring *tx_ring)
9a799d71 7023{
d3d00239 7024 struct ixgbe_tx_buffer *first;
5f715823 7025 int tso;
d3d00239 7026 u32 tx_flags = 0;
a535c30e
AD		 7027#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7028 unsigned short f;
7029#endif
a535c30e 7030 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7031 __be16 protocol = skb->protocol;
63544e9c 7032 u8 hdr_len = 0;
5e09a105 7033
a535c30e
AD		 7034 /*
7035 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7036 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7037 * + 2 desc gap to keep tail from touching head,
7038 * + 1 desc for context descriptor,
7039 * otherwise try next time
7040 */
7041#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7042 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7043 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7044#else
7045 count += skb_shinfo(skb)->nr_frags;
7046#endif
7047 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7048 tx_ring->tx_stats.tx_busy++;
7049 return NETDEV_TX_BUSY;
7050 }
7051
66f32a8b 7052 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7053 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7054 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7055 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7056 /* else if it is a SW VLAN check the next protocol and store the tag */
7057 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7058 struct vlan_hdr *vhdr, _vhdr;
7059 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7060 if (!vhdr)
7061 goto out_drop;
7062
7063 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7064 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7065 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7066 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7067 }
7068
9e0c5648
AD		 7069#ifdef CONFIG_PCI_IOV
7070 /*
7071 * Use the l2switch_enable flag - would be false if the DMA
7072 * Tx switch had been disabled.
7073 */
7074 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7075 tx_flags |= IXGBE_TX_FLAGS_TXSW;
7076
7077#endif
32701dc2 7078 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7079 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7080 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7081 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7082 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7083 tx_flags |= (skb->priority & 0x7) <<
7084 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7085 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7086 struct vlan_ethhdr *vhdr;
7087 if (skb_header_cloned(skb) &&
7088 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7089 goto out_drop;
7090 vhdr = (struct vlan_ethhdr *)skb->data;
7091 vhdr->h_vlan_TCI = htons(tx_flags >>
7092 IXGBE_TX_FLAGS_VLAN_SHIFT);
7093 } else {
7094 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7095 }
9a799d71 7096 }
eacd73f7 7097
a535c30e 7098 /* record the location of the first descriptor for this packet */
d3d00239 7099 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 7100
eacd73f7 7101#ifdef IXGBE_FCOE
66f32a8b
AD		 7102 /* setup tx offload for FCoE */
7103 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
7104 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 7105 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
7106 if (tso < 0)
7107 goto out_drop;
7108 else if (tso)
66f32a8b
AD		 7109 tx_flags |= IXGBE_TX_FLAGS_FSO |
7110 IXGBE_TX_FLAGS_FCOE;
7111 else
7112 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 7113
66f32a8b 7114 goto xmit_fcoe;
eacd73f7 7115 }
9a799d71 7116
66f32a8b
AD		 7117#endif /* IXGBE_FCOE */
7118 /* setup IPv4/IPv6 offloads */
7119 if (protocol == __constant_htons(ETH_P_IP))
7120 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 7121
66f32a8b
AD		 7122 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
7123 if (tso < 0)
897ab156 7124 goto out_drop;
66f32a8b
AD		 7125 else if (tso)
7126 tx_flags |= IXGBE_TX_FLAGS_TSO;
7127 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
7128 tx_flags |= IXGBE_TX_FLAGS_CSUM;
7129
7130 /* add the ATR filter if ATR is on */
7131 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7132 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7133
7134#ifdef IXGBE_FCOE
7135xmit_fcoe:
7136#endif /* IXGBE_FCOE */
d3d00239
AD		 7137 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
7138
7139 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7140
7141 return NETDEV_TX_OK;
897ab156
AD		 7142
7143out_drop:
7144 dev_kfree_skb_any(skb);
7145 return NETDEV_TX_OK;
9a799d71
AK		 7146}
7147
84418e3b
AD		 7148static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7149{
7150 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7151 struct ixgbe_ring *tx_ring;
7152
7153 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 7154 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7155}
7156
9a799d71
AK		 7157/**
7158 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7159 * @netdev: network interface device structure
7160 * @p: pointer to an address structure
7161 *
7162 * Returns 0 on success, negative on failure
7163 **/
7164static int ixgbe_set_mac(struct net_device *netdev, void *p)
7165{
7166 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7167 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7168 struct sockaddr *addr = p;
7169
7170 if (!is_valid_ether_addr(addr->sa_data))
7171 return -EADDRNOTAVAIL;
7172
7173 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7174 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7175
1cdd1ec8
GR		 7176 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7177 IXGBE_RAH_AV);
9a799d71
AK		 7178
7179 return 0;
7180}
7181
6b73e10d
BH		 7182static int
7183ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7184{
7185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7186 struct ixgbe_hw *hw = &adapter->hw;
7187 u16 value;
7188 int rc;
7189
7190 if (prtad != hw->phy.mdio.prtad)
7191 return -EINVAL;
7192 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7193 if (!rc)
7194 rc = value;
7195 return rc;
7196}
7197
7198static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7199 u16 addr, u16 value)
7200{
7201 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7202 struct ixgbe_hw *hw = &adapter->hw;
7203
7204 if (prtad != hw->phy.mdio.prtad)
7205 return -EINVAL;
7206 return hw->phy.ops.write_reg(hw, addr, devad, value);
7207}
7208
7209static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7210{
7211 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7212
7213 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7214}
7215
0365e6e4
PW		 7216/**
7217 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7218 * netdev->dev_addrs
0365e6e4
PW		 7219 * @netdev: network interface device structure
7220 *
7221 * Returns non-zero on failure
7222 **/
7223static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7224{
7225 int err = 0;
7226 struct ixgbe_adapter *adapter = netdev_priv(dev);
7227 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7228
7229 if (is_valid_ether_addr(mac->san_addr)) {
7230 rtnl_lock();
7231 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7232 rtnl_unlock();
7233 }
7234 return err;
7235}
7236
7237/**
7238 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7239 * netdev->dev_addrs
0365e6e4
PW		 7240 * @netdev: network interface device structure
7241 *
7242 * Returns non-zero on failure
7243 **/
7244static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7245{
7246 int err = 0;
7247 struct ixgbe_adapter *adapter = netdev_priv(dev);
7248 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7249
7250 if (is_valid_ether_addr(mac->san_addr)) {
7251 rtnl_lock();
7252 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7253 rtnl_unlock();
7254 }
7255 return err;
7256}
7257
9a799d71
AK		 7258#ifdef CONFIG_NET_POLL_CONTROLLER
7259/*
7260 * Polling 'interrupt' - used by things like netconsole to send skbs
7261 * without having to re-enable interrupts. It's not called while
7262 * the interrupt routine is executing.
7263 */
7264static void ixgbe_netpoll(struct net_device *netdev)
7265{
7266 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7267 int i;
9a799d71 7268
1a647bd2
AD		 7269 /* if interface is down do nothing */
7270 if (test_bit(__IXGBE_DOWN, &adapter->state))
7271 return;
7272
9a799d71 7273 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7274 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7275 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7276 for (i = 0; i < num_q_vectors; i++) {
7277 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7278 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7279 }
7280 } else {
7281 ixgbe_intr(adapter->pdev->irq, netdev);
7282 }
9a799d71 7283 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7284}
7285#endif
7286
de1036b1
ED		 7287static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7288 struct rtnl_link_stats64 *stats)
7289{
7290 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7291 int i;
7292
1a51502b 7293 rcu_read_lock();
de1036b1 7294 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7295 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7296 u64 bytes, packets;
7297 unsigned int start;
7298
1a51502b
ED		 7299 if (ring) {
7300 do {
7301 start = u64_stats_fetch_begin_bh(&ring->syncp);
7302 packets = ring->stats.packets;
7303 bytes = ring->stats.bytes;
7304 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7305 stats->rx_packets += packets;
7306 stats->rx_bytes += bytes;
7307 }
de1036b1 7308 }
1ac9ad13
ED		 7309
7310 for (i = 0; i < adapter->num_tx_queues; i++) {
7311 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7312 u64 bytes, packets;
7313 unsigned int start;
7314
7315 if (ring) {
7316 do {
7317 start = u64_stats_fetch_begin_bh(&ring->syncp);
7318 packets = ring->stats.packets;
7319 bytes = ring->stats.bytes;
7320 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7321 stats->tx_packets += packets;
7322 stats->tx_bytes += bytes;
7323 }
7324 }
1a51502b 7325 rcu_read_unlock();
de1036b1
ED		 7326 /* following stats updated by ixgbe_watchdog_task() */
7327 stats->multicast = netdev->stats.multicast;
7328 stats->rx_errors = netdev->stats.rx_errors;
7329 stats->rx_length_errors = netdev->stats.rx_length_errors;
7330 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7331 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7332 return stats;
7333}
7334
8b1c0b24
JF		 7335/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7336 * #adapter: pointer to ixgbe_adapter
7337 * @tc: number of traffic classes currently enabled
7338 *
7339 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7340 * 802.1Q priority maps to a packet buffer that exists.
7341 */
7342static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7343{
7344 struct ixgbe_hw *hw = &adapter->hw;
7345 u32 reg, rsave;
7346 int i;
7347
7348 /* 82598 have a static priority to TC mapping that can not
7349 * be changed so no validation is needed.
7350 */
7351 if (hw->mac.type == ixgbe_mac_82598EB)
7352 return;
7353
7354 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7355 rsave = reg;
7356
7357 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7358 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7359
7360 /* If up2tc is out of bounds default to zero */
7361 if (up2tc > tc)
7362 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7363 }
7364
7365 if (reg != rsave)
7366 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7367
7368 return;
7369}
7370
7371
7372/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7373 * classes.
7374 *
7375 * @netdev: net device to configure
7376 * @tc: number of traffic classes to enable
7377 */
7378int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7379{
8b1c0b24
JF		 7380 struct ixgbe_adapter *adapter = netdev_priv(dev);
7381 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7382
e7589eab
JF		 7383 /* Multiple traffic classes requires multiple queues */
7384 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7385 e_err(drv, "Enable failed, needs MSI-X\n");
7386 return -EINVAL;
7387 }
8b1c0b24
JF		 7388
7389 /* Hardware supports up to 8 traffic classes */
4de2a022 7390 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7391 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7392 return -EINVAL;
7393
7394 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7395 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7396 * hardware is not flexible enough to do this dynamically.
7397 */
7398 if (netif_running(dev))
7399 ixgbe_close(dev);
7400 ixgbe_clear_interrupt_scheme(adapter);
7401
e7589eab 7402 if (tc) {
8b1c0b24 7403 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7404 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7405
7406 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7407 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7408
7409 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7410 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7411 } else {
8b1c0b24
JF		 7412 netdev_reset_tc(dev);
7413
e7589eab
JF		 7414 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7415
7416 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7417 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7418
7419 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7420 adapter->dcb_cfg.pfc_mode_enable = false;
7421 }
7422
8b1c0b24
JF		 7423 ixgbe_init_interrupt_scheme(adapter);
7424 ixgbe_validate_rtr(adapter, tc);
7425 if (netif_running(dev))
7426 ixgbe_open(dev);
7427
7428 return 0;
7429}
de1036b1 7430
082757af
DS		 7431void ixgbe_do_reset(struct net_device *netdev)
7432{
7433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7434
7435 if (netif_running(netdev))
7436 ixgbe_reinit_locked(adapter);
7437 else
7438 ixgbe_reset(adapter);
7439}
7440
c8f44aff
MM		 7441static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7442 netdev_features_t data)
082757af
DS		 7443{
7444 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7445
7446#ifdef CONFIG_DCB
7447 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7448 data &= ~NETIF_F_HW_VLAN_RX;
7449#endif
7450
7451 /* return error if RXHASH is being enabled when RSS is not supported */
7452 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7453 data &= ~NETIF_F_RXHASH;
7454
7455 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7456 if (!(data & NETIF_F_RXCSUM))
7457 data &= ~NETIF_F_LRO;
7458
7459 /* Turn off LRO if not RSC capable or invalid ITR settings */
7460 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7461 data &= ~NETIF_F_LRO;
7462 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7463 (adapter->rx_itr_setting != 1 &&
7464 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7465 data &= ~NETIF_F_LRO;
7466 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7467 }
7468
7469 return data;
7470}
7471
c8f44aff
MM		 7472static int ixgbe_set_features(struct net_device *netdev,
7473 netdev_features_t data)
082757af
DS		 7474{
7475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3f2d1c0f 7476 netdev_features_t changed = netdev->features ^ data;
082757af
DS		 7477 bool need_reset = false;
7478
082757af
DS		 7479 /* Make sure RSC matches LRO, reset if change */
7480 if (!!(data & NETIF_F_LRO) !=
7481 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7482 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7483 switch (adapter->hw.mac.type) {
7484 case ixgbe_mac_X540:
7485 case ixgbe_mac_82599EB:
7486 need_reset = true;
7487 break;
7488 default:
7489 break;
7490 }
7491 }
7492
7493 /*
7494 * Check if Flow Director n-tuple support was enabled or disabled. If
7495 * the state changed, we need to reset.
7496 */
7497 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7498 /* turn off ATR, enable perfect filters and reset */
7499 if (data & NETIF_F_NTUPLE) {
7500 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7501 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7502 need_reset = true;
7503 }
7504 } else if (!(data & NETIF_F_NTUPLE)) {
7505 /* turn off Flow Director, set ATR and reset */
7506 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7507 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7508 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7509 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7510 need_reset = true;
7511 }
7512
3f2d1c0f
BG		 7513 if (changed & NETIF_F_RXALL)
7514 need_reset = true;
7515
7516 netdev->features = data;
082757af
DS		 7517 if (need_reset)
7518 ixgbe_do_reset(netdev);
7519
7520 return 0;
7521
7522}
7523
0edc3527 7524static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7525 .ndo_open = ixgbe_open,
0edc3527 7526 .ndo_stop = ixgbe_close,
00829823 7527 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7528 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7529 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7530 .ndo_validate_addr = eth_validate_addr,
7531 .ndo_set_mac_address = ixgbe_set_mac,
7532 .ndo_change_mtu = ixgbe_change_mtu,
7533 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7534 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7535 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7536 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7537 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7538 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7539 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7540 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7541 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7542 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7543 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7544#ifdef CONFIG_NET_POLL_CONTROLLER
7545 .ndo_poll_controller = ixgbe_netpoll,
7546#endif
332d4a7d
YZ		 7547#ifdef IXGBE_FCOE
7548 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7549 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7550 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7551 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7552 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7553 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7554 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7555#endif /* IXGBE_FCOE */
082757af
DS		 7556 .ndo_set_features = ixgbe_set_features,
7557 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7558};
7559
1cdd1ec8
GR		 7560static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7561 const struct ixgbe_info *ii)
7562{
7563#ifdef CONFIG_PCI_IOV
7564 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7565
c6bda30a 7566 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7567 return;
7568
7569 /* The 82599 supports up to 64 VFs per physical function
7570 * but this implementation limits allocation to 63 so that
7571 * basic networking resources are still available to the
7572 * physical function
7573 */
7574 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7575 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7576#endif /* CONFIG_PCI_IOV */
7577}
7578
9a799d71
AK		 7579/**
7580 * ixgbe_probe - Device Initialization Routine
7581 * @pdev: PCI device information struct
7582 * @ent: entry in ixgbe_pci_tbl
7583 *
7584 * Returns 0 on success, negative on failure
7585 *
7586 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7587 * The OS initialization, configuring of the adapter private structure,
7588 * and a hardware reset occur.
7589 **/
7590static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7591 const struct pci_device_id *ent)
9a799d71
AK		 7592{
7593 struct net_device *netdev;
7594 struct ixgbe_adapter *adapter = NULL;
7595 struct ixgbe_hw *hw;
7596 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7597 static int cards_found;
7598 int i, err, pci_using_dac;
289700db 7599 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7600 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7601#ifdef IXGBE_FCOE
7602 u16 device_caps;
7603#endif
289700db 7604 u32 eec;
c23f5b6b 7605 u16 wol_cap;
9a799d71 7606
bded64a7
AG		 7607 /* Catch broken hardware that put the wrong VF device ID in
7608 * the PCIe SR-IOV capability.
7609 */
7610 if (pdev->is_virtfn) {
7611 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7612 pci_name(pdev), pdev->vendor, pdev->device);
7613 return -EINVAL;
7614 }
7615
9ce77666 7616 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7617 if (err)
7618 return err;
7619
1b507730
NN		 7620 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7621 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7622 pci_using_dac = 1;
7623 } else {
1b507730 7624 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7625 if (err) {
1b507730
NN		 7626 err = dma_set_coherent_mask(&pdev->dev,
7627 DMA_BIT_MASK(32));
9a799d71 7628 if (err) {
b8bc0421
DC		 7629 dev_err(&pdev->dev,
7630 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7631 goto err_dma;
7632 }
7633 }
7634 pci_using_dac = 0;
7635 }
7636
9ce77666 7637 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7638 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7639 if (err) {
b8bc0421
DC		 7640 dev_err(&pdev->dev,
7641 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7642 goto err_pci_reg;
7643 }
7644
19d5afd4 7645 pci_enable_pcie_error_reporting(pdev);
6fabd715 7646
9a799d71 7647 pci_set_master(pdev);
fb3b27bc 7648 pci_save_state(pdev);
9a799d71 7649
e901acd6
JF		 7650#ifdef CONFIG_IXGBE_DCB
7651 indices *= MAX_TRAFFIC_CLASS;
7652#endif
7653
c85a2618
JF		 7654 if (ii->mac == ixgbe_mac_82598EB)
7655 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7656 else
7657 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7658
e901acd6 7659#ifdef IXGBE_FCOE
c85a2618
JF		 7660 indices += min_t(unsigned int, num_possible_cpus(),
7661 IXGBE_MAX_FCOE_INDICES);
7662#endif
c85a2618 7663 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7664 if (!netdev) {
7665 err = -ENOMEM;
7666 goto err_alloc_etherdev;
7667 }
7668
9a799d71
AK		 7669 SET_NETDEV_DEV(netdev, &pdev->dev);
7670
9a799d71 7671 adapter = netdev_priv(netdev);
c60fbb00 7672 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7673
7674 adapter->netdev = netdev;
7675 adapter->pdev = pdev;
7676 hw = &adapter->hw;
7677 hw->back = adapter;
7678 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7679
05857980 7680 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7681 pci_resource_len(pdev, 0));
9a799d71
AK		 7682 if (!hw->hw_addr) {
7683 err = -EIO;
7684 goto err_ioremap;
7685 }
7686
7687 for (i = 1; i <= 5; i++) {
7688 if (pci_resource_len(pdev, i) == 0)
7689 continue;
7690 }
7691
0edc3527 7692 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7693 ixgbe_set_ethtool_ops(netdev);
9a799d71 7694 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7695 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7696
9a799d71
AK		 7697 adapter->bd_number = cards_found;
7698
9a799d71
AK		 7699 /* Setup hw api */
7700 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7701 hw->mac.type = ii->mac;
9a799d71 7702
c44ade9e
JB		 7703 /* EEPROM */
7704 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7705 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7706 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7707 if (!(eec & (1 << 8)))
7708 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7709
7710 /* PHY */
7711 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7712 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7713 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7714 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7715 hw->phy.mdio.mmds = 0;
7716 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7717 hw->phy.mdio.dev = netdev;
7718 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7719 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7720
8ca783ab 7721 ii->get_invariants(hw);
9a799d71
AK		 7722
7723 /* setup the private structure */
7724 err = ixgbe_sw_init(adapter);
7725 if (err)
7726 goto err_sw_init;
7727
e86bff0e 7728 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7729 switch (adapter->hw.mac.type) {
7730 case ixgbe_mac_82599EB:
7731 case ixgbe_mac_X540:
e86bff0e 7732 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7733 break;
7734 default:
7735 break;
7736 }
e86bff0e 7737
bf069c97
DS		 7738 /*
7739 * If there is a fan on this device and it has failed log the
7740 * failure.
7741 */
7742 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7743 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7744 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7745 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7746 }
7747
8ef78adc
PWJ		 7748 if (allow_unsupported_sfp)
7749 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7750
c44ade9e 7751 /* reset_hw fills in the perm_addr as well */
119fc60a 7752 hw->phy.reset_if_overtemp = true;
c44ade9e 7753 err = hw->mac.ops.reset_hw(hw);
119fc60a 7754 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7755 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7756 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7757 err = 0;
7758 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7759 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7760 "module type was detected.\n");
7761 e_dev_err("Reload the driver after installing a supported "
7762 "module.\n");
04f165ef
PW		 7763 goto err_sw_init;
7764 } else if (err) {
849c4542 7765 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7766 goto err_sw_init;
7767 }
7768
1cdd1ec8
GR		 7769 ixgbe_probe_vf(adapter, ii);
7770
396e799c 7771 netdev->features = NETIF_F_SG |
e8e9f696 7772 NETIF_F_IP_CSUM |
082757af 7773 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7774 NETIF_F_HW_VLAN_TX |
7775 NETIF_F_HW_VLAN_RX |
082757af
DS		 7776 NETIF_F_HW_VLAN_FILTER |
7777 NETIF_F_TSO |
7778 NETIF_F_TSO6 |
082757af
DS		 7779 NETIF_F_RXHASH |
7780 NETIF_F_RXCSUM;
9a799d71 7781
082757af 7782 netdev->hw_features = netdev->features;
ad31c402 7783
58be7666
DS		 7784 switch (adapter->hw.mac.type) {
7785 case ixgbe_mac_82599EB:
7786 case ixgbe_mac_X540:
45a5ead0 7787 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7788 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7789 NETIF_F_NTUPLE;
58be7666
DS		 7790 break;
7791 default:
7792 break;
7793 }
45a5ead0 7794
3f2d1c0f
BG		 7795 netdev->hw_features |= NETIF_F_RXALL;
7796
ad31c402
JK		 7797 netdev->vlan_features |= NETIF_F_TSO;
7798 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7799 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7800 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7801 netdev->vlan_features |= NETIF_F_SG;
7802
01789349 7803 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7804 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7805
1cdd1ec8
GR		 7806 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7807 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7808 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7809
7a6b6f51 7810#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7811 netdev->dcbnl_ops = &dcbnl_ops;
7812#endif
7813
eacd73f7 7814#ifdef IXGBE_FCOE
0d551589 7815 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7816 if (hw->mac.ops.get_device_caps) {
7817 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7818 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7819 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7820 }
7821 }
5e09d7f6
YZ		 7822 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7823 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7824 netdev->vlan_features |= NETIF_F_FSO;
7825 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7826 }
eacd73f7 7827#endif /* IXGBE_FCOE */
7b872a55 7828 if (pci_using_dac) {
9a799d71 7829 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7830 netdev->vlan_features |= NETIF_F_HIGHDMA;
7831 }
9a799d71 7832
082757af
DS		 7833 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7834 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7835 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7836 netdev->features |= NETIF_F_LRO;
7837
9a799d71 7838 /* make sure the EEPROM is good */
c44ade9e 7839 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7840 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7841 err = -EIO;
7842 goto err_eeprom;
7843 }
7844
7845 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7846 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7847
c44ade9e 7848 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7849 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7850 err = -EIO;
7851 goto err_eeprom;
7852 }
7853
7086400d
AD		 7854 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7855 (unsigned long) adapter);
9a799d71 7856
7086400d
AD		 7857 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7858 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7859
021230d4
AV		 7860 err = ixgbe_init_interrupt_scheme(adapter);
7861 if (err)
7862 goto err_sw_init;
9a799d71 7863
082757af
DS		 7864 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7865 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7866 netdev->features &= ~NETIF_F_RXHASH;
082757af 7867 }
67a74ee2 7868
c23f5b6b
ET		 7869 /* WOL not supported for all but the following */
7870 adapter->wol = 0;
e8e26350 7871 switch (pdev->device) {
0b077fea 7872 case IXGBE_DEV_ID_82599_SFP:
0e22d043
DS		 7873 /* Only these subdevice supports WOL */
7874 switch (pdev->subsystem_device) {
7875 case IXGBE_SUBDEV_ID_82599_560FLR:
7876 /* only support first port */
7877 if (hw->bus.func != 0)
7878 break;
7879 case IXGBE_SUBDEV_ID_82599_SFP:
9417c464 7880 adapter->wol = IXGBE_WUFC_MAG;
0e22d043
DS		 7881 break;
7882 }
0b077fea 7883 break;
50d6c681
AD		 7884 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7885 /* All except this subdevice support WOL */
0b077fea 7886 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7887 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7888 break;
e8e26350 7889 case IXGBE_DEV_ID_82599_KX4:
9417c464 7890 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7891 break;
c23f5b6b
ET		 7892 case IXGBE_DEV_ID_X540T:
7893 /* Check eeprom to see if it is enabled */
7894 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7895 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7896
7897 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7898 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7899 (hw->bus.func == 0)))
7900 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7901 break;
7902 }
e8e26350
PW		 7903 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7904
15e5209f
ET		 7905 /* save off EEPROM version number */
7906 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7907 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7908
04f165ef
PW		 7909 /* pick up the PCI bus settings for reporting later */
7910 hw->mac.ops.get_bus_info(hw);
7911
9a799d71 7912 /* print bus type/speed/width info */
849c4542 7913 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7914 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7915 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7916 "Unknown"),
7917 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7918 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7919 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7920 "Unknown"),
7921 netdev->dev_addr);
289700db
DS		 7922
7923 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7924 if (err)
9fe93afd 7925 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7926 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7927 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7928 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7929 part_str);
e8e26350 7930 else
289700db
DS		 7931 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7932 hw->mac.type, hw->phy.type, part_str);
9a799d71 7933
e8e26350 7934 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7935 e_dev_warn("PCI-Express bandwidth available for this card is "
7936 "not sufficient for optimal performance.\n");
7937 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7938 "is required.\n");
0c254d86
AK		 7939 }
7940
9a799d71 7941 /* reset the hardware with the new settings */
794caeb2 7942 err = hw->mac.ops.start_hw(hw);
c44ade9e 7943
794caeb2
PWJ		 7944 if (err == IXGBE_ERR_EEPROM_VERSION) {
7945 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7946 e_dev_warn("This device is a pre-production adapter/LOM. "
7947 "Please be aware there may be issues associated "
7948 "with your hardware. If you are experiencing "
7949 "problems please contact your Intel or hardware "
7950 "representative who provided you with this "
7951 "hardware.\n");
794caeb2 7952 }
9a799d71
AK		 7953 strcpy(netdev->name, "eth%d");
7954 err = register_netdev(netdev);
7955 if (err)
7956 goto err_register;
7957
93d3ce8f
ET		 7958 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7959 if (hw->mac.ops.disable_tx_laser &&
7960 ((hw->phy.multispeed_fiber) ||
7961 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7962 (hw->mac.type == ixgbe_mac_82599EB))))
7963 hw->mac.ops.disable_tx_laser(hw);
7964
54386467
JB		 7965 /* carrier off reporting is important to ethtool even BEFORE open */
7966 netif_carrier_off(netdev);
7967
5dd2d332 7968#ifdef CONFIG_IXGBE_DCA
652f093f 7969 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7970 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7971 ixgbe_setup_dca(adapter);
7972 }
7973#endif
1cdd1ec8 7974 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7975 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7976 for (i = 0; i < adapter->num_vfs; i++)
7977 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7978 }
7979
2466dd9c
JK		 7980 /* firmware requires driver version to be 0xFFFFFFFF
7981 * since os does not support feature
7982 */
9612de92 7983 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7984 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7985 0xFF);
9612de92 7986
0365e6e4
PW		 7987 /* add san mac addr to netdev */
7988 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7989
ea81875a 7990 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71
AK		 7991 cards_found++;
7992 return 0;
7993
7994err_register:
5eba3699 7995 ixgbe_release_hw_control(adapter);
7a921c93 7996 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7997err_sw_init:
7998err_eeprom:
1cdd1ec8
GR		 7999 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8000 ixgbe_disable_sriov(adapter);
7086400d 8001 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 8002 iounmap(hw->hw_addr);
8003err_ioremap:
8004 free_netdev(netdev);
8005err_alloc_etherdev:
e8e9f696
JP		 8006 pci_release_selected_regions(pdev,
8007 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8008err_pci_reg:
8009err_dma:
8010 pci_disable_device(pdev);
8011 return err;
8012}
8013
8014/**
8015 * ixgbe_remove - Device Removal Routine
8016 * @pdev: PCI device information struct
8017 *
8018 * ixgbe_remove is called by the PCI subsystem to alert the driver
8019 * that it should release a PCI device. The could be caused by a
8020 * Hot-Plug event, or because the driver is going to be removed from
8021 * memory.
8022 **/
8023static void __devexit ixgbe_remove(struct pci_dev *pdev)
8024{
c60fbb00
AD		 8025 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8026 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 8027
8028 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 8029 cancel_work_sync(&adapter->service_task);
9a799d71 8030
5dd2d332 8031#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8032 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8033 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8034 dca_remove_requester(&pdev->dev);
8035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8036 }
8037
8038#endif
332d4a7d
YZ		 8039#ifdef IXGBE_FCOE
8040 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
8041 ixgbe_cleanup_fcoe(adapter);
8042
8043#endif /* IXGBE_FCOE */
0365e6e4
PW		 8044
8045 /* remove the added san mac */
8046 ixgbe_del_sanmac_netdev(netdev);
8047
c4900be0
DS		 8048 if (netdev->reg_state == NETREG_REGISTERED)
8049 unregister_netdev(netdev);
9a799d71 8050
c6bda30a
GR		 8051 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8052 if (!(ixgbe_check_vf_assignment(adapter)))
8053 ixgbe_disable_sriov(adapter);
8054 else
8055 e_dev_warn("Unloading driver while VFs are assigned "
8056 "- VFs will not be deallocated\n");
8057 }
1cdd1ec8 8058
7a921c93 8059 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8060
021230d4 8061 ixgbe_release_hw_control(adapter);
9a799d71
AK		 8062
8063 iounmap(adapter->hw.hw_addr);
9ce77666 8064 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8065 IORESOURCE_MEM));
9a799d71 8066
849c4542 8067 e_dev_info("complete\n");
021230d4 8068
9a799d71
AK		 8069 free_netdev(netdev);
8070
19d5afd4 8071 pci_disable_pcie_error_reporting(pdev);
6fabd715 8072
9a799d71
AK		 8073 pci_disable_device(pdev);
8074}
8075
8076/**
8077 * ixgbe_io_error_detected - called when PCI error is detected
8078 * @pdev: Pointer to PCI device
8079 * @state: The current pci connection state
8080 *
8081 * This function is called after a PCI bus error affecting
8082 * this device has been detected.
8083 */
8084static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8085 pci_channel_state_t state)
9a799d71 8086{
c60fbb00
AD		 8087 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8088 struct net_device *netdev = adapter->netdev;
9a799d71 8089
83c61fa9
GR		 8090#ifdef CONFIG_PCI_IOV
8091 struct pci_dev *bdev, *vfdev;
8092 u32 dw0, dw1, dw2, dw3;
8093 int vf, pos;
8094 u16 req_id, pf_func;
8095
8096 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8097 adapter->num_vfs == 0)
8098 goto skip_bad_vf_detection;
8099
8100 bdev = pdev->bus->self;
8101 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
8102 bdev = bdev->bus->self;
8103
8104 if (!bdev)
8105 goto skip_bad_vf_detection;
8106
8107 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8108 if (!pos)
8109 goto skip_bad_vf_detection;
8110
8111 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8112 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8113 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8114 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8115
8116 req_id = dw1 >> 16;
8117 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8118 if (!(req_id & 0x0080))
8119 goto skip_bad_vf_detection;
8120
8121 pf_func = req_id & 0x01;
8122 if ((pf_func & 1) == (pdev->devfn & 1)) {
8123 unsigned int device_id;
8124
8125 vf = (req_id & 0x7F) >> 1;
8126 e_dev_err("VF %d has caused a PCIe error\n", vf);
8127 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8128 "%8.8x\tdw3: %8.8x\n",
8129 dw0, dw1, dw2, dw3);
8130 switch (adapter->hw.mac.type) {
8131 case ixgbe_mac_82599EB:
8132 device_id = IXGBE_82599_VF_DEVICE_ID;
8133 break;
8134 case ixgbe_mac_X540:
8135 device_id = IXGBE_X540_VF_DEVICE_ID;
8136 break;
8137 default:
8138 device_id = 0;
8139 break;
8140 }
8141
8142 /* Find the pci device of the offending VF */
8143 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
8144 while (vfdev) {
8145 if (vfdev->devfn == (req_id & 0xFF))
8146 break;
8147 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
8148 device_id, vfdev);
8149 }
8150 /*
8151 * There's a slim chance the VF could have been hot plugged,
8152 * so if it is no longer present we don't need to issue the
8153 * VFLR. Just clean up the AER in that case.
8154 */
8155 if (vfdev) {
8156 e_dev_err("Issuing VFLR to VF %d\n", vf);
8157 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8158 }
8159
8160 pci_cleanup_aer_uncorrect_error_status(pdev);
8161 }
8162
8163 /*
8164 * Even though the error may have occurred on the other port
8165 * we still need to increment the vf error reference count for
8166 * both ports because the I/O resume function will be called
8167 * for both of them.
8168 */
8169 adapter->vferr_refcount++;
8170
8171 return PCI_ERS_RESULT_RECOVERED;
8172
8173skip_bad_vf_detection:
8174#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8175 netif_device_detach(netdev);
8176
3044b8d1
BL		 8177 if (state == pci_channel_io_perm_failure)
8178 return PCI_ERS_RESULT_DISCONNECT;
8179
9a799d71
AK		 8180 if (netif_running(netdev))
8181 ixgbe_down(adapter);
8182 pci_disable_device(pdev);
8183
b4617240 8184 /* Request a slot reset. */
9a799d71
AK		 8185 return PCI_ERS_RESULT_NEED_RESET;
8186}
8187
8188/**
8189 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8190 * @pdev: Pointer to PCI device
8191 *
8192 * Restart the card from scratch, as if from a cold-boot.
8193 */
8194static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8195{
c60fbb00 8196 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8197 pci_ers_result_t result;
8198 int err;
9a799d71 8199
9ce77666 8200 if (pci_enable_device_mem(pdev)) {
396e799c 8201 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8202 result = PCI_ERS_RESULT_DISCONNECT;
8203 } else {
8204 pci_set_master(pdev);
8205 pci_restore_state(pdev);
c0e1f68b 8206 pci_save_state(pdev);
9a799d71 8207
dd4d8ca6 8208 pci_wake_from_d3(pdev, false);
9a799d71 8209
6fabd715 8210 ixgbe_reset(adapter);
88512539 8211 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8212 result = PCI_ERS_RESULT_RECOVERED;
8213 }
8214
8215 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8216 if (err) {
849c4542
ET		 8217 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8218 "failed 0x%0x\n", err);
6fabd715
PWJ		 8219 /* non-fatal, continue */
8220 }
9a799d71 8221
6fabd715 8222 return result;
9a799d71
AK		 8223}
8224
8225/**
8226 * ixgbe_io_resume - called when traffic can start flowing again.
8227 * @pdev: Pointer to PCI device
8228 *
8229 * This callback is called when the error recovery driver tells us that
8230 * its OK to resume normal operation.
8231 */
8232static void ixgbe_io_resume(struct pci_dev *pdev)
8233{
c60fbb00
AD		 8234 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8235 struct net_device *netdev = adapter->netdev;
9a799d71 8236
83c61fa9
GR		 8237#ifdef CONFIG_PCI_IOV
8238 if (adapter->vferr_refcount) {
8239 e_info(drv, "Resuming after VF err\n");
8240 adapter->vferr_refcount--;
8241 return;
8242 }
8243
8244#endif
c7ccde0f
AD		 8245 if (netif_running(netdev))
8246 ixgbe_up(adapter);
9a799d71
AK		 8247
8248 netif_device_attach(netdev);
9a799d71
AK		 8249}
8250
8251static struct pci_error_handlers ixgbe_err_handler = {
8252 .error_detected = ixgbe_io_error_detected,
8253 .slot_reset = ixgbe_io_slot_reset,
8254 .resume = ixgbe_io_resume,
8255};
8256
8257static struct pci_driver ixgbe_driver = {
8258 .name = ixgbe_driver_name,
8259 .id_table = ixgbe_pci_tbl,
8260 .probe = ixgbe_probe,
8261 .remove = __devexit_p(ixgbe_remove),
8262#ifdef CONFIG_PM
8263 .suspend = ixgbe_suspend,
8264 .resume = ixgbe_resume,
8265#endif
8266 .shutdown = ixgbe_shutdown,
8267 .err_handler = &ixgbe_err_handler
8268};
8269
8270/**
8271 * ixgbe_init_module - Driver Registration Routine
8272 *
8273 * ixgbe_init_module is the first routine called when the driver is
8274 * loaded. All it does is register with the PCI subsystem.
8275 **/
8276static int __init ixgbe_init_module(void)
8277{
8278 int ret;
c7689578 8279 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8280 pr_info("%s\n", ixgbe_copyright);
9a799d71 8281
5dd2d332 8282#ifdef CONFIG_IXGBE_DCA
bd0362dd 8283 dca_register_notify(&dca_notifier);
bd0362dd 8284#endif
5dd2d332 8285
9a799d71
AK		 8286 ret = pci_register_driver(&ixgbe_driver);
8287 return ret;
8288}
b4617240 8289
9a799d71
AK		 8290module_init(ixgbe_init_module);
8291
8292/**
8293 * ixgbe_exit_module - Driver Exit Cleanup Routine
8294 *
8295 * ixgbe_exit_module is called just before the driver is removed
8296 * from memory.
8297 **/
8298static void __exit ixgbe_exit_module(void)
8299{
5dd2d332 8300#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8301 dca_unregister_notify(&dca_notifier);
8302#endif
9a799d71 8303 pci_unregister_driver(&ixgbe_driver);
1a51502b 8304 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8305}
bd0362dd 8306
5dd2d332 8307#ifdef CONFIG_IXGBE_DCA
bd0362dd 8308static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8309 void *p)
bd0362dd
JC		 8310{
8311 int ret_val;
8312
8313 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8314 __ixgbe_notify_dca);
bd0362dd
JC		 8315
8316 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8317}
b453368d 8318
5dd2d332 8319#endif /* CONFIG_IXGBE_DCA */
849c4542 8320
9a799d71
AK		 8321module_exit(ixgbe_exit_module);
8322
8323/* ixgbe_main.c */
Linux kernel - Deliverables
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