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ixgbe: Minor refactor of RSC
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
ea81875a
NP		 58char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
75e3d3c6 60#define MAJ 3
19d478bb
DS		 61#define MIN 6
62#define BUILD 7
75e3d3c6 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 64 __stringify(BUILD) "-k"
9c8eb720 65const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 66static const char ixgbe_copyright[] =
94971820 67 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 68
69static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 70 [board_82598] = &ixgbe_82598_info,
e8e26350 71 [board_82599] = &ixgbe_82599_info,
fe15e8e1 72 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 73};
74
75/* ixgbe_pci_tbl - PCI Device ID Table
76 *
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
79 *
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
82 */
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
1cdd1ec8
GR		 127#ifdef CONFIG_PCI_IOV
128static unsigned int max_vfs;
129module_param(max_vfs, uint, 0);
e8e9f696
JP		 130MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 132#endif /* CONFIG_PCI_IOV */
133
8ef78adc
PWJ		 134static unsigned int allow_unsupported_sfp;
135module_param(allow_unsupported_sfp, uint, 0);
136MODULE_PARM_DESC(allow_unsupported_sfp,
137 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
138
9a799d71
AK		 139MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_VERSION);
143
144#define DEFAULT_DEBUG_LEVEL_SHIFT 3
145
7086400d
AD		 146static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
147{
148 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
149 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
150 schedule_work(&adapter->service_task);
151}
152
153static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
154{
155 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
156
52f33af8 157 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 158 smp_mb__before_clear_bit();
159 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
160}
161
dcd79aeb
TI		 162struct ixgbe_reg_info {
163 u32 ofs;
164 char *name;
165};
166
167static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
168
169 /* General Registers */
170 {IXGBE_CTRL, "CTRL"},
171 {IXGBE_STATUS, "STATUS"},
172 {IXGBE_CTRL_EXT, "CTRL_EXT"},
173
174 /* Interrupt Registers */
175 {IXGBE_EICR, "EICR"},
176
177 /* RX Registers */
178 {IXGBE_SRRCTL(0), "SRRCTL"},
179 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
180 {IXGBE_RDLEN(0), "RDLEN"},
181 {IXGBE_RDH(0), "RDH"},
182 {IXGBE_RDT(0), "RDT"},
183 {IXGBE_RXDCTL(0), "RXDCTL"},
184 {IXGBE_RDBAL(0), "RDBAL"},
185 {IXGBE_RDBAH(0), "RDBAH"},
186
187 /* TX Registers */
188 {IXGBE_TDBAL(0), "TDBAL"},
189 {IXGBE_TDBAH(0), "TDBAH"},
190 {IXGBE_TDLEN(0), "TDLEN"},
191 {IXGBE_TDH(0), "TDH"},
192 {IXGBE_TDT(0), "TDT"},
193 {IXGBE_TXDCTL(0), "TXDCTL"},
194
195 /* List Terminator */
196 {}
197};
198
199
200/*
201 * ixgbe_regdump - register printout routine
202 */
203static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
204{
205 int i = 0, j = 0;
206 char rname[16];
207 u32 regs[64];
208
209 switch (reginfo->ofs) {
210 case IXGBE_SRRCTL(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
213 break;
214 case IXGBE_DCA_RXCTRL(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
217 break;
218 case IXGBE_RDLEN(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
221 break;
222 case IXGBE_RDH(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
225 break;
226 case IXGBE_RDT(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
229 break;
230 case IXGBE_RXDCTL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
233 break;
234 case IXGBE_RDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
237 break;
238 case IXGBE_RDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
241 break;
242 case IXGBE_TDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
245 break;
246 case IXGBE_TDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
249 break;
250 case IXGBE_TDLEN(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
253 break;
254 case IXGBE_TDH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
257 break;
258 case IXGBE_TDT(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
261 break;
262 case IXGBE_TXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
265 break;
266 default:
c7689578 267 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 268 IXGBE_READ_REG(hw, reginfo->ofs));
269 return;
270 }
271
272 for (i = 0; i < 8; i++) {
273 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 274 pr_err("%-15s", rname);
dcd79aeb 275 for (j = 0; j < 8; j++)
c7689578
JP		 276 pr_cont(" %08x", regs[i*8+j]);
277 pr_cont("\n");
dcd79aeb
TI		 278 }
279
280}
281
282/*
283 * ixgbe_dump - Print registers, tx-rings and rx-rings
284 */
285static void ixgbe_dump(struct ixgbe_adapter *adapter)
286{
287 struct net_device *netdev = adapter->netdev;
288 struct ixgbe_hw *hw = &adapter->hw;
289 struct ixgbe_reg_info *reginfo;
290 int n = 0;
291 struct ixgbe_ring *tx_ring;
292 struct ixgbe_tx_buffer *tx_buffer_info;
293 union ixgbe_adv_tx_desc *tx_desc;
294 struct my_u0 { u64 a; u64 b; } *u0;
295 struct ixgbe_ring *rx_ring;
296 union ixgbe_adv_rx_desc *rx_desc;
297 struct ixgbe_rx_buffer *rx_buffer_info;
298 u32 staterr;
299 int i = 0;
300
301 if (!netif_msg_hw(adapter))
302 return;
303
304 /* Print netdevice Info */
305 if (netdev) {
306 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 307 pr_info("Device Name state "
dcd79aeb 308 "trans_start last_rx\n");
c7689578
JP		 309 pr_info("%-15s %016lX %016lX %016lX\n",
310 netdev->name,
311 netdev->state,
312 netdev->trans_start,
313 netdev->last_rx);
dcd79aeb
TI		 314 }
315
316 /* Print Registers */
317 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 318 pr_info(" Register Name Value\n");
dcd79aeb
TI		 319 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
320 reginfo->name; reginfo++) {
321 ixgbe_regdump(hw, reginfo);
322 }
323
324 /* Print TX Ring Summary */
325 if (!netdev || !netif_running(netdev))
326 goto exit;
327
328 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 329 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 330 for (n = 0; n < adapter->num_tx_queues; n++) {
331 tx_ring = adapter->tx_ring[n];
332 tx_buffer_info =
333 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 334 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 335 n, tx_ring->next_to_use, tx_ring->next_to_clean,
336 (u64)tx_buffer_info->dma,
337 tx_buffer_info->length,
338 tx_buffer_info->next_to_watch,
339 (u64)tx_buffer_info->time_stamp);
340 }
341
342 /* Print TX Rings */
343 if (!netif_msg_tx_done(adapter))
344 goto rx_ring_summary;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
347
348 /* Transmit Descriptor Formats
349 *
350 * Advanced Transmit Descriptor
351 * +--------------------------------------------------------------+
352 * 0 | Buffer Address [63:0] |
353 * +--------------------------------------------------------------+
354 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
355 * +--------------------------------------------------------------+
356 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
357 */
358
359 for (n = 0; n < adapter->num_tx_queues; n++) {
360 tx_ring = adapter->tx_ring[n];
c7689578
JP		 361 pr_info("------------------------------------\n");
362 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
363 pr_info("------------------------------------\n");
364 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 365 "[PlPOIdStDDt Ln] [bi->dma ] "
366 "leng ntw timestamp bi->skb\n");
367
368 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 369 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 370 tx_buffer_info = &tx_ring->tx_buffer_info[i];
371 u0 = (struct my_u0 *)tx_desc;
c7689578 372 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 373 " %04X %p %016llX %p", i,
dcd79aeb
TI		 374 le64_to_cpu(u0->a),
375 le64_to_cpu(u0->b),
376 (u64)tx_buffer_info->dma,
377 tx_buffer_info->length,
378 tx_buffer_info->next_to_watch,
379 (u64)tx_buffer_info->time_stamp,
380 tx_buffer_info->skb);
381 if (i == tx_ring->next_to_use &&
382 i == tx_ring->next_to_clean)
c7689578 383 pr_cont(" NTC/U\n");
dcd79aeb 384 else if (i == tx_ring->next_to_use)
c7689578 385 pr_cont(" NTU\n");
dcd79aeb 386 else if (i == tx_ring->next_to_clean)
c7689578 387 pr_cont(" NTC\n");
dcd79aeb 388 else
c7689578 389 pr_cont("\n");
dcd79aeb
TI		 390
391 if (netif_msg_pktdata(adapter) &&
392 tx_buffer_info->dma != 0)
393 print_hex_dump(KERN_INFO, "",
394 DUMP_PREFIX_ADDRESS, 16, 1,
395 phys_to_virt(tx_buffer_info->dma),
396 tx_buffer_info->length, true);
397 }
398 }
399
400 /* Print RX Rings Summary */
401rx_ring_summary:
402 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 403 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 404 for (n = 0; n < adapter->num_rx_queues; n++) {
405 rx_ring = adapter->rx_ring[n];
c7689578
JP		 406 pr_info("%5d %5X %5X\n",
407 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 408 }
409
410 /* Print RX Rings */
411 if (!netif_msg_rx_status(adapter))
412 goto exit;
413
414 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
415
416 /* Advanced Receive Descriptor (Read) Format
417 * 63 1 0
418 * +-----------------------------------------------------+
419 * 0 | Packet Buffer Address [63:1] |A0/NSE|
420 * +----------------------------------------------+------+
421 * 8 | Header Buffer Address [63:1] | DD |
422 * +-----------------------------------------------------+
423 *
424 *
425 * Advanced Receive Descriptor (Write-Back) Format
426 *
427 * 63 48 47 32 31 30 21 20 16 15 4 3 0
428 * +------------------------------------------------------+
429 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
430 * | Checksum Ident | | | | Type | Type |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
435 */
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 442 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
443 "<-- Adv Rx Read format\n");
c7689578 444 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 445 "[vl er S cks ln] ---------------- [bi->skb] "
446 "<-- Adv Rx Write-Back format\n");
447
448 for (i = 0; i < rx_ring->count; i++) {
449 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 450 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 451 u0 = (struct my_u0 *)rx_desc;
452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
453 if (staterr & IXGBE_RXD_STAT_DD) {
454 /* Descriptor Done */
c7689578 455 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 456 "%016llX ---------------- %p", i,
457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
459 rx_buffer_info->skb);
460 } else {
c7689578 461 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 462 "%016llX %016llX %p", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)rx_buffer_info->dma,
466 rx_buffer_info->skb);
467
468 if (netif_msg_pktdata(adapter)) {
469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(rx_buffer_info->dma),
472 rx_ring->rx_buf_len, true);
473
474 if (rx_ring->rx_buf_len
919e78a6 475 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 476 print_hex_dump(KERN_INFO, "",
477 DUMP_PREFIX_ADDRESS, 16, 1,
478 phys_to_virt(
479 rx_buffer_info->page_dma +
480 rx_buffer_info->page_offset
481 ),
482 PAGE_SIZE/2, true);
483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
e8e26350
PW		 520/*
521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
d3d00239
AD		 592static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
d3d00239
AD		 595 if (tx_buffer->dma) {
596 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
597 dma_unmap_page(ring->dev,
598 tx_buffer->dma,
599 tx_buffer->length,
600 DMA_TO_DEVICE);
e5a43549 601 else
d3d00239
AD		 602 dma_unmap_single(ring->dev,
603 tx_buffer->dma,
604 tx_buffer->length,
605 DMA_TO_DEVICE);
e5a43549 606 }
d3d00239
AD		 607 tx_buffer->dma = 0;
608}
609
610void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
611 struct ixgbe_tx_buffer *tx_buffer_info)
612{
613 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
614 if (tx_buffer_info->skb)
9a799d71 615 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 616 tx_buffer_info->skb = NULL;
9a799d71
AK		 617 /* tx_buffer_info must be completely set up in the transmit path */
618}
619
c84d324c
JF		 620static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
621{
622 struct ixgbe_hw *hw = &adapter->hw;
623 struct ixgbe_hw_stats *hwstats = &adapter->stats;
624 u32 data = 0;
625 u32 xoff[8] = {0};
626 int i;
627
628 if ((hw->fc.current_mode == ixgbe_fc_full) ||
629 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
630 switch (hw->mac.type) {
631 case ixgbe_mac_82598EB:
632 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 633 break;
634 default:
c84d324c
JF		 635 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
636 }
637 hwstats->lxoffrxc += data;
638
639 /* refill credits (no tx hang) if we received xoff */
640 if (!data)
641 return;
642
643 for (i = 0; i < adapter->num_tx_queues; i++)
644 clear_bit(__IXGBE_HANG_CHECK_ARMED,
645 &adapter->tx_ring[i]->state);
646 return;
647 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
648 return;
649
650 /* update stats for each tc, only valid with PFC enabled */
651 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
652 switch (hw->mac.type) {
653 case ixgbe_mac_82598EB:
654 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 655 break;
c84d324c
JF		 656 default:
657 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 658 }
c84d324c
JF		 659 hwstats->pxoffrxc[i] += xoff[i];
660 }
661
662 /* disarm tx queues that have received xoff frames */
663 for (i = 0; i < adapter->num_tx_queues; i++) {
664 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 665 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 666
667 if (xoff[tc])
668 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 669 }
26f23d82
YZ		 670}
671
c84d324c 672static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 673{
c84d324c
JF		 674 return ring->tx_stats.completed;
675}
676
677static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
678{
679 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 680 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 681
c84d324c
JF		 682 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
683 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
684
685 if (head != tail)
686 return (head < tail) ?
687 tail - head : (tail + ring->count - head);
688
689 return 0;
690}
691
692static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
693{
694 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
695 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
696 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
697 bool ret = false;
698
7d637bcc 699 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 700
701 /*
702 * Check for a hung queue, but be thorough. This verifies
703 * that a transmit has been completed since the previous
704 * check AND there is at least one packet pending. The
705 * ARMED bit is set to indicate a potential hang. The
706 * bit is cleared if a pause frame is received to remove
707 * false hang detection due to PFC or 802.3x frames. By
708 * requiring this to fail twice we avoid races with
709 * pfc clearing the ARMED bit and conditions where we
710 * run the check_tx_hang logic with a transmit completion
711 * pending but without time to complete it yet.
712 */
713 if ((tx_done_old == tx_done) && tx_pending) {
714 /* make sure it is true for two checks in a row */
715 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
716 &tx_ring->state);
717 } else {
718 /* update completed stats and continue */
719 tx_ring->tx_stats.tx_done_old = tx_done;
720 /* reset the countdown */
721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 722 }
723
c84d324c 724 return ret;
9a799d71
AK		 725}
726
c83c6cbd
AD		 727/**
728 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
729 * @adapter: driver private struct
730 **/
731static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
732{
733
734 /* Do the reset outside of interrupt context */
735 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
736 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
737 ixgbe_service_event_schedule(adapter);
738 }
739}
e01c31a5 740
9a799d71
AK		 741/**
742 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 743 * @q_vector: structure containing interrupt and ring information
e01c31a5 744 * @tx_ring: tx ring to clean
9a799d71 745 **/
fe49f04a 746static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 747 struct ixgbe_ring *tx_ring)
9a799d71 748{
fe49f04a 749 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 750 struct ixgbe_tx_buffer *tx_buffer;
751 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 752 unsigned int total_bytes = 0, total_packets = 0;
59224555 753 unsigned int budget = q_vector->tx.work_limit;
d3d00239 754 u16 i = tx_ring->next_to_clean;
9a799d71 755
d3d00239
AD		 756 tx_buffer = &tx_ring->tx_buffer_info[i];
757 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 758
30065e63 759 for (; budget; budget--) {
d3d00239
AD		 760 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
761
762 /* if next_to_watch is not set then there is no work pending */
763 if (!eop_desc)
764 break;
765
766 /* if DD is not set pending work has not been completed */
767 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
768 break;
8ad494b0 769
d3d00239
AD		 770 /* count the packet as being completed */
771 tx_ring->tx_stats.completed++;
772
773 /* clear next_to_watch to prevent false hangs */
774 tx_buffer->next_to_watch = NULL;
8ad494b0 775
d3d00239
AD		 776 /* prevent any other reads prior to eop_desc being verified */
777 rmb();
778
779 do {
780 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 781 tx_desc->wb.status = 0;
d3d00239
AD		 782 if (likely(tx_desc == eop_desc)) {
783 eop_desc = NULL;
784 dev_kfree_skb_any(tx_buffer->skb);
785 tx_buffer->skb = NULL;
786
787 total_bytes += tx_buffer->bytecount;
788 total_packets += tx_buffer->gso_segs;
789 }
9a799d71 790
d3d00239
AD		 791 tx_buffer++;
792 tx_desc++;
8ad494b0 793 i++;
d3d00239 794 if (unlikely(i == tx_ring->count)) {
8ad494b0 795 i = 0;
e01c31a5 796
d3d00239
AD		 797 tx_buffer = tx_ring->tx_buffer_info;
798 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 799 }
e01c31a5 800
d3d00239 801 } while (eop_desc);
12207e49
PWJ		 802 }
803
9a799d71 804 tx_ring->next_to_clean = i;
d3d00239 805 u64_stats_update_begin(&tx_ring->syncp);
b953799e 806 tx_ring->stats.bytes += total_bytes;
bd198058 807 tx_ring->stats.packets += total_packets;
d3d00239 808 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 809 q_vector->tx.total_bytes += total_bytes;
810 q_vector->tx.total_packets += total_packets;
b953799e 811
c84d324c
JF		 812 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
813 /* schedule immediate reset if we believe we hung */
814 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 815 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 816 e_err(drv, "Detected Tx Unit Hang\n"
817 " Tx Queue <%d>\n"
818 " TDH, TDT <%x>, <%x>\n"
819 " next_to_use <%x>\n"
820 " next_to_clean <%x>\n"
821 "tx_buffer_info[next_to_clean]\n"
822 " time_stamp <%lx>\n"
823 " jiffies <%lx>\n",
824 tx_ring->queue_index,
825 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
826 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 827 tx_ring->next_to_use, i,
828 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 829
830 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
831
832 e_info(probe,
833 "tx hang %d detected on queue %d, resetting adapter\n",
834 adapter->tx_timeout_count + 1, tx_ring->queue_index);
835
b953799e 836 /* schedule immediate reset if we believe we hung */
c83c6cbd 837 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 838
839 /* the adapter is about to reset, no point in enabling stuff */
59224555 840 return true;
b953799e 841 }
9a799d71 842
e092be60 843#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 844 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 845 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 846 /* Make sure that anybody stopping the queue after this
847 * sees the new next_to_clean.
848 */
849 smp_mb();
fc77dc3c 850 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 851 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 852 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 853 ++tx_ring->tx_stats.restart_queue;
30eba97a 854 }
e092be60 855 }
9a799d71 856
59224555 857 return !!budget;
9a799d71
AK		 858}
859
5dd2d332 860#ifdef CONFIG_IXGBE_DCA
bd0362dd 861static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 862 struct ixgbe_ring *rx_ring,
863 int cpu)
bd0362dd 864{
33cf09c9 865 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 866 u32 rxctrl;
33cf09c9
AD		 867 u8 reg_idx = rx_ring->reg_idx;
868
869 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
870 switch (hw->mac.type) {
871 case ixgbe_mac_82598EB:
872 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 873 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 874 break;
875 case ixgbe_mac_82599EB:
b93a2226 876 case ixgbe_mac_X540:
33cf09c9 877 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 878 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 879 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
880 break;
881 default:
882 break;
bd0362dd 883 }
33cf09c9
AD		 884 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
885 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
886 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 887 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 888}
889
890static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 891 struct ixgbe_ring *tx_ring,
892 int cpu)
bd0362dd 893{
33cf09c9 894 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 895 u32 txctrl;
33cf09c9
AD		 896 u8 reg_idx = tx_ring->reg_idx;
897
898 switch (hw->mac.type) {
899 case ixgbe_mac_82598EB:
900 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
901 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 902 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 903 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
905 break;
906 case ixgbe_mac_82599EB:
b93a2226 907 case ixgbe_mac_X540:
33cf09c9
AD		 908 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
909 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 910 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 911 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
912 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 913 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
914 break;
915 default:
916 break;
917 }
918}
919
920static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
921{
922 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 923 struct ixgbe_ring *ring;
bd0362dd 924 int cpu = get_cpu();
bd0362dd 925
33cf09c9
AD		 926 if (q_vector->cpu == cpu)
927 goto out_no_update;
928
efe3d3c8
AD		 929 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
930 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 931
efe3d3c8
AD		 932 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
933 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 934
935 q_vector->cpu = cpu;
936out_no_update:
bd0362dd
JC		 937 put_cpu();
938}
939
940static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
941{
33cf09c9 942 int num_q_vectors;
bd0362dd
JC		 943 int i;
944
945 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
946 return;
947
e35ec126
AD		 948 /* always use CB2 mode, difference is masked in the CB driver */
949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
950
33cf09c9
AD		 951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
952 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
953 else
954 num_q_vectors = 1;
955
956 for (i = 0; i < num_q_vectors; i++) {
957 adapter->q_vector[i]->cpu = -1;
958 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 959 }
960}
961
962static int __ixgbe_notify_dca(struct device *dev, void *data)
963{
c60fbb00 964 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 965 unsigned long event = *(unsigned long *)data;
966
2a72c31e 967 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 968 return 0;
969
bd0362dd
JC		 970 switch (event) {
971 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 972 /* if we're already enabled, don't do it again */
973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
974 break;
652f093f 975 if (dca_add_requester(dev) == 0) {
96b0e0f6 976 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 977 ixgbe_setup_dca(adapter);
978 break;
979 }
980 /* Fall Through since DCA is disabled. */
981 case DCA_PROVIDER_REMOVE:
982 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
983 dca_remove_requester(dev);
984 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
985 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
986 }
987 break;
988 }
989
652f093f 990 return 0;
bd0362dd 991}
5dd2d332 992#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 993
994static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
995 struct sk_buff *skb)
996{
997 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
998}
999
ff886dfc
AD		 1000/**
1001 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1002 * @adapter: address of board private structure
1003 * @rx_desc: advanced rx descriptor
1004 *
1005 * Returns : true if it is FCoE pkt
1006 */
1007static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1008 union ixgbe_adv_rx_desc *rx_desc)
1009{
1010 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1011
1012 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1013 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1014 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1015 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1016}
1017
9a799d71
AK		 1018/**
1019 * ixgbe_receive_skb - Send a completed packet up the stack
1020 * @adapter: board private structure
1021 * @skb: packet to send up
177db6ff
MC		 1022 * @status: hardware indication of status of receive
1023 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1024 * @rx_desc: rx descriptor
9a799d71 1025 **/
78b6f4ce 1026static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1027 struct sk_buff *skb, u8 status,
1028 struct ixgbe_ring *ring,
1029 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1030{
78b6f4ce
HX		 1031 struct ixgbe_adapter *adapter = q_vector->adapter;
1032 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1033 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1034 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1035
f62bbb5e
JG		 1036 if (is_vlan && (tag & VLAN_VID_MASK))
1037 __vlan_hwaccel_put_tag(skb, tag);
1038
1039 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1040 napi_gro_receive(napi, skb);
1041 else
1042 netif_rx(skb);
9a799d71
AK		 1043}
1044
e59bd25d
AV		 1045/**
1046 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1047 * @adapter: address of board private structure
1048 * @status_err: hardware indication of status of receive
1049 * @skb: skb currently being received and modified
ff886dfc 1050 * @status_err: status error value of last descriptor in packet
e59bd25d 1051 **/
9a799d71 1052static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1053 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1054 struct sk_buff *skb,
1055 u32 status_err)
9a799d71 1056{
ff886dfc 1057 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1058
712744be
JB		 1059 /* Rx csum disabled */
1060 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1061 return;
e59bd25d
AV		 1062
1063 /* if IP and error */
1064 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1065 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1066 adapter->hw_csum_rx_error++;
1067 return;
1068 }
e59bd25d
AV		 1069
1070 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1071 return;
1072
1073 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1074 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1075
1076 /*
1077 * 82599 errata, UDP frames with a 0 checksum can be marked as
1078 * checksum errors.
1079 */
1080 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1081 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1082 return;
1083
e59bd25d
AV		 1084 adapter->hw_csum_rx_error++;
1085 return;
1086 }
1087
9a799d71 1088 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1089 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1090}
1091
84ea2591 1092static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1093{
1094 /*
1095 * Force memory writes to complete before letting h/w
1096 * know there are new descriptors to fetch. (Only
1097 * applicable for weak-ordered memory model archs,
1098 * such as IA-64).
1099 */
1100 wmb();
84ea2591 1101 writel(val, rx_ring->tail);
e8e26350
PW		 1102}
1103
9a799d71
AK		 1104/**
1105 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1106 * @rx_ring: ring to place buffers on
1107 * @cleaned_count: number of buffers to replace
9a799d71 1108 **/
fc77dc3c 1109void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1110{
9a799d71 1111 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1112 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1113 struct sk_buff *skb;
1114 u16 i = rx_ring->next_to_use;
9a799d71 1115
fc77dc3c
AD		 1116 /* do nothing if no valid netdev defined */
1117 if (!rx_ring->netdev)
1118 return;
1119
9a799d71 1120 while (cleaned_count--) {
31f05a2d 1121 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1122 bi = &rx_ring->rx_buffer_info[i];
1123 skb = bi->skb;
9a799d71 1124
d5f398ed 1125 if (!skb) {
fc77dc3c 1126 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1127 rx_ring->rx_buf_len);
9a799d71 1128 if (!skb) {
5b7da515 1129 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1130 goto no_buffers;
1131 }
d716a7d8
AD		 1132 /* initialize queue mapping */
1133 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1134 bi->skb = skb;
d716a7d8 1135 }
9a799d71 1136
d716a7d8 1137 if (!bi->dma) {
b6ec895e 1138 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1139 skb->data,
e8e9f696 1140 rx_ring->rx_buf_len,
1b507730 1141 DMA_FROM_DEVICE);
b6ec895e 1142 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1143 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1144 bi->dma = 0;
1145 goto no_buffers;
1146 }
9a799d71 1147 }
d5f398ed 1148
7d637bcc 1149 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1150 if (!bi->page) {
1f2149c1 1151 bi->page = alloc_page(GFP_ATOMIC | __GFP_COLD);
d5f398ed 1152 if (!bi->page) {
5b7da515 1153 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1154 goto no_buffers;
1155 }
1156 }
1157
1158 if (!bi->page_dma) {
1159 /* use a half page if we're re-using */
1160 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1161 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1162 bi->page,
1163 bi->page_offset,
1164 PAGE_SIZE / 2,
1165 DMA_FROM_DEVICE);
b6ec895e 1166 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1167 bi->page_dma)) {
5b7da515 1168 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1169 bi->page_dma = 0;
1170 goto no_buffers;
1171 }
1172 }
1173
1174 /* Refresh the desc even if buffer_addrs didn't change
1175 * because each write-back erases this info. */
3a581073
JB		 1176 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1177 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1178 } else {
3a581073 1179 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1180 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1181 }
1182
1183 i++;
1184 if (i == rx_ring->count)
1185 i = 0;
9a799d71 1186 }
7c6e0a43 1187
9a799d71
AK		 1188no_buffers:
1189 if (rx_ring->next_to_use != i) {
1190 rx_ring->next_to_use = i;
84ea2591 1191 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1192 }
1193}
1194
c267fc16 1195static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1196{
c267fc16
AD		 1197 /* HW will not DMA in data larger than the given buffer, even if it
1198 * parses the (NFS, of course) header to be larger. In that case, it
1199 * fills the header buffer and spills the rest into the page.
1200 */
1201 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1202 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1203 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1204 if (hlen > IXGBE_RX_HDR_SIZE)
1205 hlen = IXGBE_RX_HDR_SIZE;
1206 return hlen;
7c6e0a43
JB		 1207}
1208
f8212f97 1209/**
4c1975d7
AD		 1210 * ixgbe_merge_active_tail - merge active tail into lro skb
1211 * @tail: pointer to active tail in frag_list
f8212f97 1212 *
4c1975d7
AD		 1213 * This function merges the length and data of an active tail into the
1214 * skb containing the frag_list. It resets the tail's pointer to the head,
1215 * but it leaves the heads pointer to tail intact.
f8212f97 1216 **/
4c1975d7 1217static inline struct sk_buff *ixgbe_merge_active_tail(struct sk_buff *tail)
f8212f97 1218{
4c1975d7 1219 struct sk_buff *head = IXGBE_CB(tail)->head;
f8212f97 1220
4c1975d7
AD		 1221 if (!head)
1222 return tail;
1223
1224 head->len += tail->len;
1225 head->data_len += tail->len;
1226 head->truesize += tail->len;
1227
1228 IXGBE_CB(tail)->head = NULL;
1229
1230 return head;
1231}
1232
1233/**
1234 * ixgbe_add_active_tail - adds an active tail into the skb frag_list
1235 * @head: pointer to the start of the skb
1236 * @tail: pointer to active tail to add to frag_list
1237 *
1238 * This function adds an active tail to the end of the frag list. This tail
1239 * will still be receiving data so we cannot yet ad it's stats to the main
1240 * skb. That is done via ixgbe_merge_active_tail.
1241 **/
1242static inline void ixgbe_add_active_tail(struct sk_buff *head,
1243 struct sk_buff *tail)
1244{
1245 struct sk_buff *old_tail = IXGBE_CB(head)->tail;
1246
1247 if (old_tail) {
1248 ixgbe_merge_active_tail(old_tail);
1249 old_tail->next = tail;
1250 } else {
1251 skb_shinfo(head)->frag_list = tail;
f8212f97
AD		 1252 }
1253
4c1975d7
AD		 1254 IXGBE_CB(tail)->head = head;
1255 IXGBE_CB(head)->tail = tail;
1256}
1257
1258/**
1259 * ixgbe_close_active_frag_list - cleanup pointers on a frag_list skb
1260 * @head: pointer to head of an active frag list
1261 *
1262 * This function will clear the frag_tail_tracker pointer on an active
1263 * frag_list and returns true if the pointer was actually set
1264 **/
1265static inline bool ixgbe_close_active_frag_list(struct sk_buff *head)
1266{
1267 struct sk_buff *tail = IXGBE_CB(head)->tail;
1268
1269 if (!tail)
1270 return false;
1271
1272 ixgbe_merge_active_tail(tail);
1273
1274 IXGBE_CB(head)->tail = NULL;
aa80175a 1275
4c1975d7 1276 return true;
f8212f97
AD		 1277}
1278
4c1975d7
AD		 1279static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1280 union ixgbe_adv_rx_desc *rx_desc,
1281 struct sk_buff *skb)
aa80175a 1282{
4c1975d7
AD		 1283 __le32 rsc_enabled;
1284 u32 rsc_cnt;
1285
1286 if (!ring_is_rsc_enabled(rx_ring))
1287 return;
1288
1289 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1290 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1291
1292 /* If this is an RSC frame rsc_cnt should be non-zero */
1293 if (!rsc_enabled)
1294 return;
1295
1296 rsc_cnt = le32_to_cpu(rsc_enabled);
1297 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1298
1299 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1300}
43634e82 1301
4ff7fb12 1302static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1303 struct ixgbe_ring *rx_ring,
4ff7fb12 1304 int budget)
9a799d71 1305{
78b6f4ce 1306 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71 1307 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
4c1975d7 1308 struct ixgbe_rx_buffer *rx_buffer_info;
9a799d71 1309 struct sk_buff *skb;
d2f4fbe2 1310 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1311 const int current_node = numa_node_id();
3d8fd385
YZ		 1312#ifdef IXGBE_FCOE
1313 int ddp_bytes = 0;
1314#endif /* IXGBE_FCOE */
c267fc16
AD		 1315 u32 staterr;
1316 u16 i;
1317 u16 cleaned_count = 0;
9a799d71
AK		 1318
1319 i = rx_ring->next_to_clean;
31f05a2d 1320 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1321 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1322
1323 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1324 u32 upper_len = 0;
9a799d71 1325
3c945e5b 1326 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1327
c267fc16
AD		 1328 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1329
9a799d71 1330 skb = rx_buffer_info->skb;
9a799d71 1331 rx_buffer_info->skb = NULL;
c267fc16 1332 prefetch(skb->data);
9a799d71 1333
b811ce91
JB		 1334 /* linear means we are building an skb from multiple pages */
1335 if (!skb_is_nonlinear(skb)) {
c267fc16 1336 u16 hlen;
c267fc16
AD		 1337 if (ring_is_ps_enabled(rx_ring)) {
1338 hlen = ixgbe_get_hlen(rx_desc);
1339 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1340 } else {
1341 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1342 }
1343
1344 skb_put(skb, hlen);
4c1975d7
AD		 1345
1346 /*
1347 * Delay unmapping of the first packet. It carries the
1348 * header information, HW may still access the header
1349 * after writeback. Only unmap it when EOP is reached
1350 */
1351 if (!IXGBE_CB(skb)->head) {
1352 IXGBE_CB(skb)->delay_unmap = true;
1353 IXGBE_CB(skb)->dma = rx_buffer_info->dma;
1354 } else {
1355 skb = ixgbe_merge_active_tail(skb);
1356 dma_unmap_single(rx_ring->dev,
1357 rx_buffer_info->dma,
1358 rx_ring->rx_buf_len,
1359 DMA_FROM_DEVICE);
1360 }
1361 rx_buffer_info->dma = 0;
c267fc16
AD		 1362 } else {
1363 /* assume packet split since header is unmapped */
1364 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1365 }
1366
1367 if (upper_len) {
b6ec895e
AD		 1368 dma_unmap_page(rx_ring->dev,
1369 rx_buffer_info->page_dma,
1370 PAGE_SIZE / 2,
1371 DMA_FROM_DEVICE);
9a799d71
AK		 1372 rx_buffer_info->page_dma = 0;
1373 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1374 rx_buffer_info->page,
1375 rx_buffer_info->page_offset,
1376 upper_len);
762f4c57 1377
c267fc16
AD		 1378 if ((page_count(rx_buffer_info->page) == 1) &&
1379 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1380 get_page(rx_buffer_info->page);
c267fc16
AD		 1381 else
1382 rx_buffer_info->page = NULL;
9a799d71
AK		 1383
1384 skb->len += upper_len;
1385 skb->data_len += upper_len;
98130646 1386 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1387 }
1388
4c1975d7
AD		 1389 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1390
9a799d71
AK		 1391 i++;
1392 if (i == rx_ring->count)
1393 i = 0;
9a799d71 1394
31f05a2d 1395 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1396 prefetch(next_rxd);
9a799d71 1397 cleaned_count++;
f8212f97 1398
4c1975d7
AD		 1399 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1400 struct ixgbe_rx_buffer *next_buffer;
1401 u32 nextp;
1402
1403 if (IXGBE_CB(skb)->append_cnt) {
1404 nextp = staterr & IXGBE_RXDADV_NEXTP_MASK;
1405 nextp >>= IXGBE_RXDADV_NEXTP_SHIFT;
1406 } else {
1407 nextp = i;
1408 }
1409
f8212f97 1410 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97 1411
7d637bcc 1412 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1413 rx_buffer_info->skb = next_buffer->skb;
1414 rx_buffer_info->dma = next_buffer->dma;
1415 next_buffer->skb = skb;
1416 next_buffer->dma = 0;
1417 } else {
4c1975d7
AD		 1418 struct sk_buff *next_skb = next_buffer->skb;
1419 ixgbe_add_active_tail(skb, next_skb);
1420 IXGBE_CB(next_skb)->head = skb;
f8212f97 1421 }
5b7da515 1422 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1423 goto next_desc;
1424 }
1425
4c1975d7
AD		 1426 dma_unmap_single(rx_ring->dev,
1427 IXGBE_CB(skb)->dma,
1428 rx_ring->rx_buf_len,
1429 DMA_FROM_DEVICE);
1430 IXGBE_CB(skb)->dma = 0;
1431 IXGBE_CB(skb)->delay_unmap = false;
1432
1433 if (ixgbe_close_active_frag_list(skb) &&
1434 !IXGBE_CB(skb)->append_cnt) {
aa80175a 1435 /* if we got here without RSC the packet is invalid */
4c1975d7
AD		 1436 dev_kfree_skb_any(skb);
1437 goto next_desc;
aa80175a 1438 }
c267fc16 1439
4c1975d7
AD		 1440 if (IXGBE_CB(skb)->append_cnt) {
1441 rx_ring->rx_stats.rsc_count +=
1442 IXGBE_CB(skb)->append_cnt;
c267fc16
AD		 1443 rx_ring->rx_stats.rsc_flush++;
1444 }
1445
1446 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1447 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1448 dev_kfree_skb_any(skb);
9a799d71
AK		 1449 goto next_desc;
1450 }
1451
ff886dfc 1452 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1453 if (adapter->netdev->features & NETIF_F_RXHASH)
1454 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1455
1456 /* probably a little skewed due to removing CRC */
1457 total_rx_bytes += skb->len;
1458 total_rx_packets++;
1459
fc77dc3c 1460 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1461#ifdef IXGBE_FCOE
1462 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1463 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1464 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1465 staterr);
63d635b2
AD		 1466 if (!ddp_bytes) {
1467 dev_kfree_skb_any(skb);
332d4a7d 1468 goto next_desc;
63d635b2 1469 }
3d8fd385 1470 }
332d4a7d 1471#endif /* IXGBE_FCOE */
fdaff1ce 1472 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1473
4ff7fb12 1474 budget--;
9a799d71
AK		 1475next_desc:
1476 rx_desc->wb.upper.status_error = 0;
1477
4ff7fb12 1478 if (!budget)
c267fc16
AD		 1479 break;
1480
9a799d71
AK		 1481 /* return some buffers to hardware, one at a time is too slow */
1482 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1483 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1484 cleaned_count = 0;
1485 }
1486
1487 /* use prefetched values */
1488 rx_desc = next_rxd;
9a799d71 1489 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1490 }
1491
9a799d71 1492 rx_ring->next_to_clean = i;
7d4987de 1493 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1494
1495 if (cleaned_count)
fc77dc3c 1496 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1497
3d8fd385
YZ		 1498#ifdef IXGBE_FCOE
1499 /* include DDPed FCoE data */
1500 if (ddp_bytes > 0) {
1501 unsigned int mss;
1502
fc77dc3c 1503 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1504 sizeof(struct fc_frame_header) -
1505 sizeof(struct fcoe_crc_eof);
1506 if (mss > 512)
1507 mss &= ~511;
1508 total_rx_bytes += ddp_bytes;
1509 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1510 }
1511#endif /* IXGBE_FCOE */
1512
c267fc16
AD		 1513 u64_stats_update_begin(&rx_ring->syncp);
1514 rx_ring->stats.packets += total_rx_packets;
1515 rx_ring->stats.bytes += total_rx_bytes;
1516 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1517 q_vector->rx.total_packets += total_rx_packets;
1518 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1519
1520 return !!budget;
9a799d71
AK		 1521}
1522
9a799d71
AK		 1523/**
1524 * ixgbe_configure_msix - Configure MSI-X hardware
1525 * @adapter: board private structure
1526 *
1527 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1528 * interrupts.
1529 **/
1530static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1531{
021230d4 1532 struct ixgbe_q_vector *q_vector;
efe3d3c8 1533 int q_vectors, v_idx;
021230d4 1534 u32 mask;
9a799d71 1535
021230d4 1536 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1537
8e34d1aa
AD		 1538 /* Populate MSIX to EITR Select */
1539 if (adapter->num_vfs > 32) {
1540 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1542 }
1543
4df10466
JB		 1544 /*
1545 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1546 * corresponding register.
1547 */
1548 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1549 struct ixgbe_ring *ring;
7a921c93 1550 q_vector = adapter->q_vector[v_idx];
021230d4 1551
efe3d3c8
AD		 1552 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1553 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1554
1555 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1556 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1557
d5bf4f67
ET		 1558 if (q_vector->tx.ring && !q_vector->rx.ring) {
1559 /* tx only vector */
1560 if (adapter->tx_itr_setting == 1)
1561 q_vector->itr = IXGBE_10K_ITR;
1562 else
1563 q_vector->itr = adapter->tx_itr_setting;
1564 } else {
1565 /* rx or rx/tx vector */
1566 if (adapter->rx_itr_setting == 1)
1567 q_vector->itr = IXGBE_20K_ITR;
1568 else
1569 q_vector->itr = adapter->rx_itr_setting;
1570 }
021230d4 1571
fe49f04a 1572 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1573 }
1574
bd508178
AD		 1575 switch (adapter->hw.mac.type) {
1576 case ixgbe_mac_82598EB:
e8e26350 1577 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1578 v_idx);
bd508178
AD		 1579 break;
1580 case ixgbe_mac_82599EB:
b93a2226 1581 case ixgbe_mac_X540:
e8e26350 1582 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1583 break;
bd508178
AD		 1584 default:
1585 break;
1586 }
021230d4
AV		 1587 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1588
41fb9248 1589 /* set up to autoclear timer, and the vectors */
021230d4 1590 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1591 mask &= ~(IXGBE_EIMS_OTHER |
1592 IXGBE_EIMS_MAILBOX |
1593 IXGBE_EIMS_LSC);
1594
021230d4 1595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1596}
1597
f494e8fa
AV		 1598enum latency_range {
1599 lowest_latency = 0,
1600 low_latency = 1,
1601 bulk_latency = 2,
1602 latency_invalid = 255
1603};
1604
1605/**
1606 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1607 * @q_vector: structure containing interrupt and ring information
1608 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1609 *
1610 * Stores a new ITR value based on packets and byte
1611 * counts during the last interrupt. The advantage of per interrupt
1612 * computation is faster updates and more accurate ITR for the current
1613 * traffic pattern. Constants in this function were computed
1614 * based on theoretical maximum wire speed and thresholds were set based
1615 * on testing data as well as attempting to minimize response time
1616 * while increasing bulk throughput.
1617 * this functionality is controlled by the InterruptThrottleRate module
1618 * parameter (see ixgbe_param.c)
1619 **/
bd198058
AD		 1620static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1621 struct ixgbe_ring_container *ring_container)
f494e8fa 1622{
f494e8fa 1623 u64 bytes_perint;
bd198058
AD		 1624 struct ixgbe_adapter *adapter = q_vector->adapter;
1625 int bytes = ring_container->total_bytes;
1626 int packets = ring_container->total_packets;
1627 u32 timepassed_us;
1628 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1629
1630 if (packets == 0)
bd198058 1631 return;
f494e8fa
AV		 1632
1633 /* simple throttlerate management
1634 * 0-20MB/s lowest (100000 ints/s)
1635 * 20-100MB/s low (20000 ints/s)
1636 * 100-1249MB/s bulk (8000 ints/s)
1637 */
1638 /* what was last interrupt timeslice? */
d5bf4f67 1639 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1640 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1641
1642 switch (itr_setting) {
1643 case lowest_latency:
1644 if (bytes_perint > adapter->eitr_low)
bd198058 1645 itr_setting = low_latency;
f494e8fa
AV		 1646 break;
1647 case low_latency:
1648 if (bytes_perint > adapter->eitr_high)
bd198058 1649 itr_setting = bulk_latency;
f494e8fa 1650 else if (bytes_perint <= adapter->eitr_low)
bd198058 1651 itr_setting = lowest_latency;
f494e8fa
AV		 1652 break;
1653 case bulk_latency:
1654 if (bytes_perint <= adapter->eitr_high)
bd198058 1655 itr_setting = low_latency;
f494e8fa
AV		 1656 break;
1657 }
1658
bd198058
AD		 1659 /* clear work counters since we have the values we need */
1660 ring_container->total_bytes = 0;
1661 ring_container->total_packets = 0;
1662
1663 /* write updated itr to ring container */
1664 ring_container->itr = itr_setting;
f494e8fa
AV		 1665}
1666
509ee935
JB		 1667/**
1668 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1669 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1670 *
1671 * This function is made to be called by ethtool and by the driver
1672 * when it needs to update EITR registers at runtime. Hardware
1673 * specific quirks/differences are taken care of here.
1674 */
fe49f04a 1675void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1676{
fe49f04a 1677 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1678 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1679 int v_idx = q_vector->v_idx;
d5bf4f67 1680 u32 itr_reg = q_vector->itr;
fe49f04a 1681
bd508178
AD		 1682 switch (adapter->hw.mac.type) {
1683 case ixgbe_mac_82598EB:
509ee935
JB		 1684 /* must write high and low 16 bits to reset counter */
1685 itr_reg |= (itr_reg << 16);
bd508178
AD		 1686 break;
1687 case ixgbe_mac_82599EB:
b93a2226 1688 case ixgbe_mac_X540:
509ee935
JB		 1689 /*
1690 * set the WDIS bit to not clear the timer bits and cause an
1691 * immediate assertion of the interrupt
1692 */
1693 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1694 break;
1695 default:
1696 break;
509ee935
JB		 1697 }
1698 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1699}
1700
bd198058 1701static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1702{
d5bf4f67 1703 u32 new_itr = q_vector->itr;
bd198058 1704 u8 current_itr;
f494e8fa 1705
bd198058
AD		 1706 ixgbe_update_itr(q_vector, &q_vector->tx);
1707 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1708
08c8833b 1709 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1710
1711 switch (current_itr) {
1712 /* counts and packets in update_itr are dependent on these numbers */
1713 case lowest_latency:
d5bf4f67 1714 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1715 break;
1716 case low_latency:
d5bf4f67 1717 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1718 break;
1719 case bulk_latency:
d5bf4f67 1720 new_itr = IXGBE_8K_ITR;
f494e8fa 1721 break;
bd198058
AD		 1722 default:
1723 break;
f494e8fa
AV		 1724 }
1725
d5bf4f67 1726 if (new_itr != q_vector->itr) {
fe49f04a 1727 /* do an exponential smoothing */
d5bf4f67
ET		 1728 new_itr = (10 * new_itr * q_vector->itr) /
1729 ((9 * new_itr) + q_vector->itr);
509ee935 1730
bd198058 1731 /* save the algorithm value here */
d5bf4f67 1732 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1733
1734 ixgbe_write_eitr(q_vector);
f494e8fa 1735 }
f494e8fa
AV		 1736}
1737
119fc60a 1738/**
f0f9778d
AD		 1739 * ixgbe_check_overtemp_subtask - check for over tempurature
1740 * @adapter: pointer to adapter
119fc60a 1741 **/
f0f9778d 1742static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1743{
119fc60a
MC		 1744 struct ixgbe_hw *hw = &adapter->hw;
1745 u32 eicr = adapter->interrupt_event;
1746
f0f9778d 1747 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1748 return;
1749
f0f9778d
AD		 1750 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1751 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1752 return;
1753
1754 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1755
7ca647bd 1756 switch (hw->device_id) {
f0f9778d
AD		 1757 case IXGBE_DEV_ID_82599_T3_LOM:
1758 /*
1759 * Since the warning interrupt is for both ports
1760 * we don't have to check if:
1761 * - This interrupt wasn't for our port.
1762 * - We may have missed the interrupt so always have to
1763 * check if we got a LSC
1764 */
1765 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1766 !(eicr & IXGBE_EICR_LSC))
1767 return;
1768
1769 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1770 u32 autoneg;
1771 bool link_up = false;
7ca647bd 1772
7ca647bd
JP		 1773 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1774
f0f9778d
AD		 1775 if (link_up)
1776 return;
1777 }
1778
1779 /* Check if this is not due to overtemp */
1780 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1781 return;
1782
1783 break;
7ca647bd
JP		 1784 default:
1785 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1786 return;
7ca647bd 1787 break;
119fc60a 1788 }
7ca647bd
JP		 1789 e_crit(drv,
1790 "Network adapter has been stopped because it has over heated. "
1791 "Restart the computer. If the problem persists, "
1792 "power off the system and replace the adapter\n");
f0f9778d
AD		 1793
1794 adapter->interrupt_event = 0;
119fc60a
MC		 1795}
1796
0befdb3e
JB		 1797static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1798{
1799 struct ixgbe_hw *hw = &adapter->hw;
1800
1801 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1802 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1803 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1804 /* write to clear the interrupt */
1805 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1806 }
1807}
cf8280ee 1808
4f51bf70
JK		 1809static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1810{
1811 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1812 return;
1813
1814 switch (adapter->hw.mac.type) {
1815 case ixgbe_mac_82599EB:
1816 /*
1817 * Need to check link state so complete overtemp check
1818 * on service task
1819 */
1820 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1821 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1822 adapter->interrupt_event = eicr;
1823 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1824 ixgbe_service_event_schedule(adapter);
1825 return;
1826 }
1827 return;
1828 case ixgbe_mac_X540:
1829 if (!(eicr & IXGBE_EICR_TS))
1830 return;
1831 break;
1832 default:
1833 return;
1834 }
1835
1836 e_crit(drv,
1837 "Network adapter has been stopped because it has over heated. "
1838 "Restart the computer. If the problem persists, "
1839 "power off the system and replace the adapter\n");
1840}
1841
e8e26350
PW		 1842static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1843{
1844 struct ixgbe_hw *hw = &adapter->hw;
1845
73c4b7cd
AD		 1846 if (eicr & IXGBE_EICR_GPI_SDP2) {
1847 /* Clear the interrupt */
1848 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1849 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1850 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1851 ixgbe_service_event_schedule(adapter);
1852 }
73c4b7cd
AD		 1853 }
1854
e8e26350
PW		 1855 if (eicr & IXGBE_EICR_GPI_SDP1) {
1856 /* Clear the interrupt */
1857 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1858 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1859 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1860 ixgbe_service_event_schedule(adapter);
1861 }
e8e26350
PW		 1862 }
1863}
1864
cf8280ee
JB		 1865static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1866{
1867 struct ixgbe_hw *hw = &adapter->hw;
1868
1869 adapter->lsc_int++;
1870 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1871 adapter->link_check_timeout = jiffies;
1872 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1873 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1874 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1875 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1876 }
1877}
1878
fe49f04a
AD		 1879static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1880 u64 qmask)
1881{
1882 u32 mask;
bd508178 1883 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1884
bd508178
AD		 1885 switch (hw->mac.type) {
1886 case ixgbe_mac_82598EB:
fe49f04a 1887 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1888 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1889 break;
1890 case ixgbe_mac_82599EB:
b93a2226 1891 case ixgbe_mac_X540:
fe49f04a 1892 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1893 if (mask)
1894 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1895 mask = (qmask >> 32);
bd508178
AD		 1896 if (mask)
1897 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1898 break;
1899 default:
1900 break;
fe49f04a
AD		 1901 }
1902 /* skip the flush */
1903}
1904
1905static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1906 u64 qmask)
fe49f04a
AD		 1907{
1908 u32 mask;
bd508178 1909 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1910
bd508178
AD		 1911 switch (hw->mac.type) {
1912 case ixgbe_mac_82598EB:
fe49f04a 1913 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1914 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1915 break;
1916 case ixgbe_mac_82599EB:
b93a2226 1917 case ixgbe_mac_X540:
fe49f04a 1918 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1919 if (mask)
1920 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1921 mask = (qmask >> 32);
bd508178
AD		 1922 if (mask)
1923 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1924 break;
1925 default:
1926 break;
fe49f04a
AD		 1927 }
1928 /* skip the flush */
1929}
1930
021230d4 1931/**
2c4af694
AD		 1932 * ixgbe_irq_enable - Enable default interrupt generation settings
1933 * @adapter: board private structure
021230d4 1934 **/
2c4af694
AD		 1935static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1936 bool flush)
9a799d71 1937{
2c4af694 1938 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 1939
2c4af694
AD		 1940 /* don't reenable LSC while waiting for link */
1941 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1942 mask &= ~IXGBE_EIMS_LSC;
9a799d71 1943
2c4af694 1944 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 1945 switch (adapter->hw.mac.type) {
1946 case ixgbe_mac_82599EB:
1947 mask |= IXGBE_EIMS_GPI_SDP0;
1948 break;
1949 case ixgbe_mac_X540:
1950 mask |= IXGBE_EIMS_TS;
1951 break;
1952 default:
1953 break;
1954 }
2c4af694
AD		 1955 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1956 mask |= IXGBE_EIMS_GPI_SDP1;
1957 switch (adapter->hw.mac.type) {
1958 case ixgbe_mac_82599EB:
2c4af694
AD		 1959 mask |= IXGBE_EIMS_GPI_SDP1;
1960 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 1961 case ixgbe_mac_X540:
1962 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 1963 mask |= IXGBE_EIMS_MAILBOX;
1964 break;
1965 default:
1966 break;
9a799d71 1967 }
2c4af694
AD		 1968 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1969 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1970 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 1971
2c4af694
AD		 1972 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1973 if (queues)
1974 ixgbe_irq_enable_queues(adapter, ~0);
1975 if (flush)
1976 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1977}
1978
2c4af694 1979static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 1980{
a65151ba 1981 struct ixgbe_adapter *adapter = data;
9a799d71 1982 struct ixgbe_hw *hw = &adapter->hw;
54037505 1983 u32 eicr;
91281fd3 1984
54037505
DS		 1985 /*
1986 * Workaround for Silicon errata. Use clear-by-write instead
1987 * of clear-by-read. Reading with EICS will return the
1988 * interrupt causes without clearing, which later be done
1989 * with the write to EICR.
1990 */
1991 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1992 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 1993
cf8280ee
JB		 1994 if (eicr & IXGBE_EICR_LSC)
1995 ixgbe_check_lsc(adapter);
f0848276 1996
1cdd1ec8
GR		 1997 if (eicr & IXGBE_EICR_MAILBOX)
1998 ixgbe_msg_task(adapter);
efe3d3c8 1999
bd508178
AD		 2000 switch (hw->mac.type) {
2001 case ixgbe_mac_82599EB:
b93a2226 2002 case ixgbe_mac_X540:
2c4af694
AD		 2003 if (eicr & IXGBE_EICR_ECC)
2004 e_info(link, "Received unrecoverable ECC Err, please "
2005 "reboot\n");
c4cf55e5
PWJ		 2006 /* Handle Flow Director Full threshold interrupt */
2007 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2008 int reinit_count = 0;
c4cf55e5 2009 int i;
c4cf55e5 2010 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2011 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2012 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2013 &ring->state))
2014 reinit_count++;
2015 }
2016 if (reinit_count) {
2017 /* no more flow director interrupts until after init */
2018 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2019 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2020 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2021 }
2022 }
f0f9778d 2023 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2024 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2025 break;
2026 default:
2027 break;
c4cf55e5 2028 }
f0848276 2029
bd508178 2030 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 2031
7086400d 2032 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2033 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2034 ixgbe_irq_enable(adapter, false, false);
f0848276 2035
9a799d71 2036 return IRQ_HANDLED;
f0848276 2037}
91281fd3 2038
4ff7fb12 2039static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2040{
021230d4 2041 struct ixgbe_q_vector *q_vector = data;
91281fd3 2042
9b471446 2043 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2044
4ff7fb12
AD		 2045 if (q_vector->rx.ring || q_vector->tx.ring)
2046 napi_schedule(&q_vector->napi);
91281fd3 2047
9a799d71 2048 return IRQ_HANDLED;
91281fd3
AD		 2049}
2050
021230d4 2051static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2052 int r_idx)
021230d4 2053{
7a921c93 2054 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2055 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2056
2274543f 2057 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2058 rx_ring->next = q_vector->rx.ring;
2059 q_vector->rx.ring = rx_ring;
2060 q_vector->rx.count++;
021230d4
AV		 2061}
2062
2063static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2064 int t_idx)
021230d4 2065{
7a921c93 2066 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2067 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2068
2274543f 2069 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2070 tx_ring->next = q_vector->tx.ring;
2071 q_vector->tx.ring = tx_ring;
2072 q_vector->tx.count++;
bd198058 2073 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2074}
2075
9a799d71 2076/**
021230d4
AV		 2077 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2078 * @adapter: board private structure to initialize
9a799d71 2079 *
021230d4
AV		 2080 * This function maps descriptor rings to the queue-specific vectors
2081 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2082 * one vector per ring/queue, but on a constrained vector budget, we
2083 * group the rings as "efficiently" as possible. You would add new
2084 * mapping configurations in here.
9a799d71 2085 **/
4cc6df29 2086static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2087{
4cc6df29
AD		 2088 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2089 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2090 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2091 int v_start = 0;
021230d4 2092
4cc6df29 2093 /* only one q_vector if MSI-X is disabled. */
021230d4 2094 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2095 q_vectors = 1;
d0759ebb 2096
021230d4 2097 /*
4cc6df29
AD		 2098 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2099 * group them so there are multiple queues per vector.
2100 *
2101 * Re-adjusting *qpv takes care of the remainder.
021230d4 2102 */
4cc6df29
AD		 2103 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2104 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2105 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2106 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2107 }
9a799d71 2108
021230d4 2109 /*
4cc6df29
AD		 2110 * If there are not enough q_vectors for each ring to have it's own
2111 * vector then we must pair up Rx/Tx on a each vector
021230d4 2112 */
4cc6df29
AD		 2113 if ((v_start + txr_remaining) > q_vectors)
2114 v_start = 0;
2115
2116 for (; v_start < q_vectors && txr_remaining; v_start++) {
2117 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2118 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2119 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2120 }
021230d4
AV		 2121}
2122
2123/**
2124 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2125 * @adapter: board private structure
2126 *
2127 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2128 * interrupts from the kernel.
2129 **/
2130static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2131{
2132 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2133 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2134 int vector, err;
e8e9f696 2135 int ri = 0, ti = 0;
021230d4 2136
021230d4 2137 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2138 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2139 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2140
4ff7fb12 2141 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2142 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2143 "%s-%s-%d", netdev->name, "TxRx", ri++);
2144 ti++;
2145 } else if (q_vector->rx.ring) {
9fe93afd 2146 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2147 "%s-%s-%d", netdev->name, "rx", ri++);
2148 } else if (q_vector->tx.ring) {
9fe93afd 2149 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2150 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2151 } else {
2152 /* skip this unused q_vector */
2153 continue;
32aa77a4 2154 }
207867f5
AD		 2155 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2156 q_vector->name, q_vector);
9a799d71 2157 if (err) {
396e799c 2158 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2159 "Error: %d\n", err);
021230d4 2160 goto free_queue_irqs;
9a799d71 2161 }
207867f5
AD		 2162 /* If Flow Director is enabled, set interrupt affinity */
2163 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2164 /* assign the mask for this irq */
2165 irq_set_affinity_hint(entry->vector,
2166 q_vector->affinity_mask);
2167 }
9a799d71
AK		 2168 }
2169
021230d4 2170 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2171 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2172 if (err) {
396e799c 2173 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2174 goto free_queue_irqs;
9a799d71
AK		 2175 }
2176
9a799d71
AK		 2177 return 0;
2178
021230d4 2179free_queue_irqs:
207867f5
AD		 2180 while (vector) {
2181 vector--;
2182 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2183 NULL);
2184 free_irq(adapter->msix_entries[vector].vector,
2185 adapter->q_vector[vector]);
2186 }
021230d4
AV		 2187 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2188 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2189 kfree(adapter->msix_entries);
2190 adapter->msix_entries = NULL;
9a799d71
AK		 2191 return err;
2192}
2193
2194/**
021230d4 2195 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2196 * @irq: interrupt number
2197 * @data: pointer to a network interface device structure
9a799d71
AK		 2198 **/
2199static irqreturn_t ixgbe_intr(int irq, void *data)
2200{
a65151ba 2201 struct ixgbe_adapter *adapter = data;
9a799d71 2202 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2203 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2204 u32 eicr;
2205
54037505 2206 /*
6af3b9eb 2207 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2208 * before the read of EICR.
2209 */
2210 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2211
021230d4 2212 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2213 * therefore no explicit interrupt disable is necessary */
021230d4 2214 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2215 if (!eicr) {
6af3b9eb
ET		 2216 /*
2217 * shared interrupt alert!
f47cf66e 2218 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2219 * have disabled interrupts due to EIAM
2220 * finish the workaround of silicon errata on 82598. Unmask
2221 * the interrupt that we masked before the EICR read.
2222 */
2223 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2224 ixgbe_irq_enable(adapter, true, true);
9a799d71 2225 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2226 }
9a799d71 2227
cf8280ee
JB		 2228 if (eicr & IXGBE_EICR_LSC)
2229 ixgbe_check_lsc(adapter);
021230d4 2230
bd508178
AD		 2231 switch (hw->mac.type) {
2232 case ixgbe_mac_82599EB:
e8e26350 2233 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2234 /* Fall through */
2235 case ixgbe_mac_X540:
2236 if (eicr & IXGBE_EICR_ECC)
2237 e_info(link, "Received unrecoverable ECC err, please "
2238 "reboot\n");
4f51bf70 2239 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2240 break;
2241 default:
2242 break;
2243 }
e8e26350 2244
0befdb3e
JB		 2245 ixgbe_check_fan_failure(adapter, eicr);
2246
7a921c93 2247 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2248 /* would disable interrupts here but EIAM disabled it */
7a921c93 2249 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2250 }
2251
6af3b9eb
ET		 2252 /*
2253 * re-enable link(maybe) and non-queue interrupts, no flush.
2254 * ixgbe_poll will re-enable the queue interrupts
2255 */
2256
2257 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2258 ixgbe_irq_enable(adapter, false, false);
2259
9a799d71
AK		 2260 return IRQ_HANDLED;
2261}
2262
021230d4
AV		 2263static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2264{
efe3d3c8
AD		 2265 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2266 int i;
2267
2268 /* legacy and MSI only use one vector */
2269 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2270 q_vectors = 1;
2271
2272 for (i = 0; i < adapter->num_rx_queues; i++) {
2273 adapter->rx_ring[i]->q_vector = NULL;
2274 adapter->rx_ring[i]->next = NULL;
2275 }
2276 for (i = 0; i < adapter->num_tx_queues; i++) {
2277 adapter->tx_ring[i]->q_vector = NULL;
2278 adapter->tx_ring[i]->next = NULL;
2279 }
021230d4
AV		 2280
2281 for (i = 0; i < q_vectors; i++) {
7a921c93 2282 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2283 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2284 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2285 }
2286}
2287
9a799d71
AK		 2288/**
2289 * ixgbe_request_irq - initialize interrupts
2290 * @adapter: board private structure
2291 *
2292 * Attempts to configure interrupts using the best available
2293 * capabilities of the hardware and kernel.
2294 **/
021230d4 2295static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2296{
2297 struct net_device *netdev = adapter->netdev;
021230d4 2298 int err;
9a799d71 2299
4cc6df29
AD		 2300 /* map all of the rings to the q_vectors */
2301 ixgbe_map_rings_to_vectors(adapter);
2302
2303 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2304 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2305 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2306 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2307 netdev->name, adapter);
4cc6df29 2308 else
a0607fd3 2309 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2310 netdev->name, adapter);
9a799d71 2311
4cc6df29 2312 if (err) {
396e799c 2313 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2314
4cc6df29
AD		 2315 /* place q_vectors and rings back into a known good state */
2316 ixgbe_reset_q_vectors(adapter);
2317 }
2318
9a799d71
AK		 2319 return err;
2320}
2321
2322static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2323{
9a799d71 2324 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2325 int i, q_vectors;
9a799d71 2326
021230d4 2327 q_vectors = adapter->num_msix_vectors;
021230d4 2328 i = q_vectors - 1;
a65151ba 2329 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2330 i--;
4cc6df29 2331
021230d4 2332 for (; i >= 0; i--) {
894ff7cf 2333 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2334 if (!adapter->q_vector[i]->rx.ring &&
2335 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2336 continue;
2337
207867f5
AD		 2338 /* clear the affinity_mask in the IRQ descriptor */
2339 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2340 NULL);
2341
021230d4 2342 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2343 adapter->q_vector[i]);
021230d4 2344 }
021230d4 2345 } else {
a65151ba 2346 free_irq(adapter->pdev->irq, adapter);
9a799d71 2347 }
207867f5
AD		 2348
2349 /* clear q_vector state information */
2350 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2351}
2352
22d5a71b
JB		 2353/**
2354 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2355 * @adapter: board private structure
2356 **/
2357static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2358{
bd508178
AD		 2359 switch (adapter->hw.mac.type) {
2360 case ixgbe_mac_82598EB:
835462fc 2361 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2362 break;
2363 case ixgbe_mac_82599EB:
b93a2226 2364 case ixgbe_mac_X540:
835462fc
NS		 2365 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2366 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2368 break;
2369 default:
2370 break;
22d5a71b
JB		 2371 }
2372 IXGBE_WRITE_FLUSH(&adapter->hw);
2373 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2374 int i;
2375 for (i = 0; i < adapter->num_msix_vectors; i++)
2376 synchronize_irq(adapter->msix_entries[i].vector);
2377 } else {
2378 synchronize_irq(adapter->pdev->irq);
2379 }
2380}
2381
9a799d71
AK		 2382/**
2383 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2384 *
2385 **/
2386static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2387{
d5bf4f67 2388 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2389
d5bf4f67
ET		 2390 /* rx/tx vector */
2391 if (adapter->rx_itr_setting == 1)
2392 q_vector->itr = IXGBE_20K_ITR;
2393 else
2394 q_vector->itr = adapter->rx_itr_setting;
2395
2396 ixgbe_write_eitr(q_vector);
9a799d71 2397
e8e26350
PW		 2398 ixgbe_set_ivar(adapter, 0, 0, 0);
2399 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2400
396e799c 2401 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2402}
2403
43e69bf0
AD		 2404/**
2405 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2406 * @adapter: board private structure
2407 * @ring: structure containing ring specific data
2408 *
2409 * Configure the Tx descriptor ring after a reset.
2410 **/
84418e3b
AD		 2411void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2412 struct ixgbe_ring *ring)
43e69bf0
AD		 2413{
2414 struct ixgbe_hw *hw = &adapter->hw;
2415 u64 tdba = ring->dma;
2f1860b8 2416 int wait_loop = 10;
b88c6de2 2417 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2418 u8 reg_idx = ring->reg_idx;
43e69bf0 2419
2f1860b8 2420 /* disable queue to avoid issues while updating state */
b88c6de2 2421 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2422 IXGBE_WRITE_FLUSH(hw);
2423
43e69bf0 2424 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2425 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2426 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2427 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2428 ring->count * sizeof(union ixgbe_adv_tx_desc));
2429 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2430 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2431 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2432
b88c6de2
AD		 2433 /*
2434 * set WTHRESH to encourage burst writeback, it should not be set
2435 * higher than 1 when ITR is 0 as it could cause false TX hangs
2436 *
2437 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2438 * to or less than the number of on chip descriptors, which is
2439 * currently 40.
2440 */
2441 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2442 txdctl |= (1 << 16); /* WTHRESH = 1 */
2443 else
2444 txdctl |= (8 << 16); /* WTHRESH = 8 */
2445
2446 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2447 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2448 32; /* PTHRESH = 32 */
2f1860b8
AD		 2449
2450 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2451 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2452 adapter->atr_sample_rate) {
2453 ring->atr_sample_rate = adapter->atr_sample_rate;
2454 ring->atr_count = 0;
2455 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2456 } else {
2457 ring->atr_sample_rate = 0;
2458 }
2f1860b8 2459
c84d324c
JF		 2460 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2461
2f1860b8 2462 /* enable queue */
2f1860b8
AD		 2463 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2464
2465 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2466 if (hw->mac.type == ixgbe_mac_82598EB &&
2467 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2468 return;
2469
2470 /* poll to verify queue is enabled */
2471 do {
032b4325 2472 usleep_range(1000, 2000);
2f1860b8
AD		 2473 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2474 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2475 if (!wait_loop)
2476 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2477}
2478
120ff942
AD		 2479static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2480{
2481 struct ixgbe_hw *hw = &adapter->hw;
2482 u32 rttdcs;
72a32f1f 2483 u32 reg;
8b1c0b24 2484 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2485
2486 if (hw->mac.type == ixgbe_mac_82598EB)
2487 return;
2488
2489 /* disable the arbiter while setting MTQC */
2490 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2491 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2492 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2493
2494 /* set transmit pool layout */
8b1c0b24 2495 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2496 case (IXGBE_FLAG_SRIOV_ENABLED):
2497 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2498 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2499 break;
8b1c0b24
JF		 2500 default:
2501 if (!tcs)
2502 reg = IXGBE_MTQC_64Q_1PB;
2503 else if (tcs <= 4)
2504 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2505 else
2506 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2507
8b1c0b24 2508 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2509
8b1c0b24
JF		 2510 /* Enable Security TX Buffer IFG for multiple pb */
2511 if (tcs) {
2512 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2513 reg |= IXGBE_SECTX_DCB;
2514 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2515 }
120ff942
AD		 2516 break;
2517 }
2518
2519 /* re-enable the arbiter */
2520 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2521 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2522}
2523
9a799d71 2524/**
3a581073 2525 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2526 * @adapter: board private structure
2527 *
2528 * Configure the Tx unit of the MAC after a reset.
2529 **/
2530static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2531{
2f1860b8
AD		 2532 struct ixgbe_hw *hw = &adapter->hw;
2533 u32 dmatxctl;
43e69bf0 2534 u32 i;
9a799d71 2535
2f1860b8
AD		 2536 ixgbe_setup_mtqc(adapter);
2537
2538 if (hw->mac.type != ixgbe_mac_82598EB) {
2539 /* DMATXCTL.EN must be before Tx queues are enabled */
2540 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2541 dmatxctl |= IXGBE_DMATXCTL_TE;
2542 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2543 }
2544
9a799d71 2545 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2546 for (i = 0; i < adapter->num_tx_queues; i++)
2547 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2548}
2549
e8e26350 2550#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2551
a6616b42 2552static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2553 struct ixgbe_ring *rx_ring)
cc41ac7c 2554{
cc41ac7c 2555 u32 srrctl;
bf29ee6c 2556 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2557
bd508178
AD		 2558 switch (adapter->hw.mac.type) {
2559 case ixgbe_mac_82598EB: {
2560 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2561 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2562 reg_idx = reg_idx & mask;
cc41ac7c 2563 }
bd508178
AD		 2564 break;
2565 case ixgbe_mac_82599EB:
b93a2226 2566 case ixgbe_mac_X540:
bd508178
AD		 2567 default:
2568 break;
2569 }
2570
bf29ee6c 2571 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2572
2573 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2574 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2575 if (adapter->num_vfs)
2576 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2577
afafd5b0
AD		 2578 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2579 IXGBE_SRRCTL_BSIZEHDR_MASK;
2580
7d637bcc 2581 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2582#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2583 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2584#else
2585 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2586#endif
cc41ac7c 2587 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2588 } else {
afafd5b0
AD		 2589 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2590 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2591 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2592 }
e8e26350 2593
bf29ee6c 2594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2595}
9a799d71 2596
05abb126 2597static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2598{
05abb126
AD		 2599 struct ixgbe_hw *hw = &adapter->hw;
2600 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2601 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2602 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2603 u32 mrqc = 0, reta = 0;
2604 u32 rxcsum;
2605 int i, j;
8b1c0b24 2606 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2607 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2608
2609 if (tcs)
2610 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2611
05abb126
AD		 2612 /* Fill out hash function seeds */
2613 for (i = 0; i < 10; i++)
2614 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2615
2616 /* Fill out redirection table */
2617 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2618 if (j == maxq)
05abb126
AD		 2619 j = 0;
2620 /* reta = 4-byte sliding window of
2621 * 0x00..(indices-1)(indices-1)00..etc. */
2622 reta = (reta << 8) | (j * 0x11);
2623 if ((i & 3) == 3)
2624 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2625 }
0cefafad 2626
05abb126
AD		 2627 /* Disable indicating checksum in descriptor, enables RSS hash */
2628 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2629 rxcsum |= IXGBE_RXCSUM_PCSD;
2630 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2631
8b1c0b24
JF		 2632 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2633 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2634 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2635 } else {
2636 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2637 | IXGBE_FLAG_SRIOV_ENABLED);
2638
2639 switch (mask) {
2640 case (IXGBE_FLAG_RSS_ENABLED):
2641 if (!tcs)
2642 mrqc = IXGBE_MRQC_RSSEN;
2643 else if (tcs <= 4)
2644 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2645 else
2646 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2647 break;
2648 case (IXGBE_FLAG_SRIOV_ENABLED):
2649 mrqc = IXGBE_MRQC_VMDQEN;
2650 break;
2651 default:
2652 break;
2653 }
0cefafad
JB		 2654 }
2655
05abb126
AD		 2656 /* Perform hash on these packet types */
2657 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2658 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2659 | IXGBE_MRQC_RSS_FIELD_IPV6
2660 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2661
2662 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2663}
2664
bb5a9ad2
NS		 2665/**
2666 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2667 * @adapter: address of board private structure
2668 * @index: index of ring to set
bb5a9ad2 2669 **/
082757af 2670static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2671 struct ixgbe_ring *ring)
bb5a9ad2 2672{
bb5a9ad2 2673 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2674 u32 rscctrl;
edd2ea55 2675 int rx_buf_len;
bf29ee6c 2676 u8 reg_idx = ring->reg_idx;
7367096a 2677
7d637bcc 2678 if (!ring_is_rsc_enabled(ring))
7367096a 2679 return;
bb5a9ad2 2680
7367096a
AD		 2681 rx_buf_len = ring->rx_buf_len;
2682 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2683 rscctrl |= IXGBE_RSCCTL_RSCEN;
2684 /*
2685 * we must limit the number of descriptors so that the
2686 * total size of max desc * buf_len is not greater
2687 * than 65535
2688 */
7d637bcc 2689 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2690#if (MAX_SKB_FRAGS > 16)
2691 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2692#elif (MAX_SKB_FRAGS > 8)
2693 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2694#elif (MAX_SKB_FRAGS > 4)
2695 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2696#else
2697 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2698#endif
2699 } else {
919e78a6 2700 if (rx_buf_len < IXGBE_RXBUFFER_4K)
bb5a9ad2 2701 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
919e78a6 2702 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2703 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2704 else
2705 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2706 }
7367096a 2707 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2708}
2709
9e10e045
AD		 2710/**
2711 * ixgbe_set_uta - Set unicast filter table address
2712 * @adapter: board private structure
2713 *
2714 * The unicast table address is a register array of 32-bit registers.
2715 * The table is meant to be used in a way similar to how the MTA is used
2716 * however due to certain limitations in the hardware it is necessary to
2717 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2718 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2719 **/
2720static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2721{
2722 struct ixgbe_hw *hw = &adapter->hw;
2723 int i;
2724
2725 /* The UTA table only exists on 82599 hardware and newer */
2726 if (hw->mac.type < ixgbe_mac_82599EB)
2727 return;
2728
2729 /* we only need to do this if VMDq is enabled */
2730 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2731 return;
2732
2733 for (i = 0; i < 128; i++)
2734 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2735}
2736
2737#define IXGBE_MAX_RX_DESC_POLL 10
2738static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2739 struct ixgbe_ring *ring)
2740{
2741 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2742 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2743 u32 rxdctl;
bf29ee6c 2744 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2745
2746 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2747 if (hw->mac.type == ixgbe_mac_82598EB &&
2748 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2749 return;
2750
2751 do {
032b4325 2752 usleep_range(1000, 2000);
9e10e045
AD		 2753 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2754 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2755
2756 if (!wait_loop) {
2757 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2758 "the polling period\n", reg_idx);
2759 }
2760}
2761
2d39d576
YZ		 2762void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2763 struct ixgbe_ring *ring)
2764{
2765 struct ixgbe_hw *hw = &adapter->hw;
2766 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2767 u32 rxdctl;
2768 u8 reg_idx = ring->reg_idx;
2769
2770 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2771 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2772
2773 /* write value back with RXDCTL.ENABLE bit cleared */
2774 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2775
2776 if (hw->mac.type == ixgbe_mac_82598EB &&
2777 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2778 return;
2779
2780 /* the hardware may take up to 100us to really disable the rx queue */
2781 do {
2782 udelay(10);
2783 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2784 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2785
2786 if (!wait_loop) {
2787 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2788 "the polling period\n", reg_idx);
2789 }
2790}
2791
84418e3b
AD		 2792void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2793 struct ixgbe_ring *ring)
acd37177
AD		 2794{
2795 struct ixgbe_hw *hw = &adapter->hw;
2796 u64 rdba = ring->dma;
9e10e045 2797 u32 rxdctl;
bf29ee6c 2798 u8 reg_idx = ring->reg_idx;
acd37177 2799
9e10e045
AD		 2800 /* disable queue to avoid issues while updating state */
2801 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2802 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2803
acd37177
AD		 2804 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2805 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2806 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2807 ring->count * sizeof(union ixgbe_adv_rx_desc));
2808 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2809 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2810 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2811
2812 ixgbe_configure_srrctl(adapter, ring);
2813 ixgbe_configure_rscctl(adapter, ring);
2814
e9f98072
GR		 2815 /* If operating in IOV mode set RLPML for X540 */
2816 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2817 hw->mac.type == ixgbe_mac_X540) {
2818 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2819 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2820 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2821 }
2822
9e10e045
AD		 2823 if (hw->mac.type == ixgbe_mac_82598EB) {
2824 /*
2825 * enable cache line friendly hardware writes:
2826 * PTHRESH=32 descriptors (half the internal cache),
2827 * this also removes ugly rx_no_buffer_count increment
2828 * HTHRESH=4 descriptors (to minimize latency on fetch)
2829 * WTHRESH=8 burst writeback up to two cache lines
2830 */
2831 rxdctl &= ~0x3FFFFF;
2832 rxdctl |= 0x080420;
2833 }
2834
2835 /* enable receive descriptor ring */
2836 rxdctl |= IXGBE_RXDCTL_ENABLE;
2837 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2838
2839 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2840 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2841}
2842
48654521
AD		 2843static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2844{
2845 struct ixgbe_hw *hw = &adapter->hw;
2846 int p;
2847
2848 /* PSRTYPE must be initialized in non 82598 adapters */
2849 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2850 IXGBE_PSRTYPE_UDPHDR |
2851 IXGBE_PSRTYPE_IPV4HDR |
48654521 2852 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2853 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2854
2855 if (hw->mac.type == ixgbe_mac_82598EB)
2856 return;
2857
2858 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2859 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2860
2861 for (p = 0; p < adapter->num_rx_pools; p++)
2862 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2863 psrtype);
2864}
2865
f5b4a52e
AD		 2866static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2867{
2868 struct ixgbe_hw *hw = &adapter->hw;
2869 u32 gcr_ext;
2870 u32 vt_reg_bits;
2871 u32 reg_offset, vf_shift;
2872 u32 vmdctl;
de4c7f65 2873 int i;
f5b4a52e
AD		 2874
2875 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2876 return;
2877
2878 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2879 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2880 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2881 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2882
2883 vf_shift = adapter->num_vfs % 32;
2884 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2885
2886 /* Enable only the PF's pool for Tx/Rx */
2887 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2888 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2889 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2890 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2891 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2892
2893 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2894 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2895
2896 /*
2897 * Set up VF register offsets for selected VT Mode,
2898 * i.e. 32 or 64 VFs for SR-IOV
2899 */
2900 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2901 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2902 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2903 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2904
2905 /* enable Tx loopback for VF/PF communication */
2906 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2907 /* Enable MAC Anti-Spoofing */
a1cbb15c 2908 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 2909 (adapter->num_vfs != 0),
a985b6c3 2910 adapter->num_vfs);
de4c7f65
GR		 2911 /* For VFs that have spoof checking turned off */
2912 for (i = 0; i < adapter->num_vfs; i++) {
2913 if (!adapter->vfinfo[i].spoofchk_enabled)
2914 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2915 }
f5b4a52e
AD		 2916}
2917
477de6ed 2918static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2919{
9a799d71
AK		 2920 struct ixgbe_hw *hw = &adapter->hw;
2921 struct net_device *netdev = adapter->netdev;
2922 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2923 int rx_buf_len;
477de6ed
AD		 2924 struct ixgbe_ring *rx_ring;
2925 int i;
2926 u32 mhadd, hlreg0;
48654521 2927
9a799d71 2928 /* Decide whether to use packet split mode or not */
a124339a
DS		 2929 /* On by default */
2930 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2931
1cdd1ec8 2932 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2933 if (adapter->num_vfs)
2934 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2935
2936 /* Disable packet split due to 82599 erratum #45 */
2937 if (hw->mac.type == ixgbe_mac_82599EB)
2938 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2939
63f39bd1 2940#ifdef IXGBE_FCOE
477de6ed
AD		 2941 /* adjust max frame to be able to do baby jumbo for FCoE */
2942 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2943 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2944 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2945
477de6ed
AD		 2946#endif /* IXGBE_FCOE */
2947 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2948 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2949 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2950 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2951
2952 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2953 }
2954
919e78a6
AD		 2955 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2956 max_frame += VLAN_HLEN;
2957
2958 /* Set the RX buffer length according to the mode */
2959 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2960 rx_buf_len = IXGBE_RX_HDR_SIZE;
2961 } else {
2962 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2963 (netdev->mtu <= ETH_DATA_LEN))
2964 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2965 /*
2966 * Make best use of allocation by using all but 1K of a
2967 * power of 2 allocation that will be used for skb->head.
2968 */
2969 else if (max_frame <= IXGBE_RXBUFFER_3K)
2970 rx_buf_len = IXGBE_RXBUFFER_3K;
2971 else if (max_frame <= IXGBE_RXBUFFER_7K)
2972 rx_buf_len = IXGBE_RXBUFFER_7K;
2973 else if (max_frame <= IXGBE_RXBUFFER_15K)
2974 rx_buf_len = IXGBE_RXBUFFER_15K;
2975 else
2976 rx_buf_len = IXGBE_MAX_RXBUFFER;
2977 }
2978
477de6ed
AD		 2979 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2980 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2981 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2982 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2983
0cefafad
JB		 2984 /*
2985 * Setup the HW Rx Head and Tail Descriptor Pointers and
2986 * the Base and Length of the Rx Descriptor Ring
2987 */
9a799d71 2988 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2989 rx_ring = adapter->rx_ring[i];
a6616b42 2990 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2991
6e455b89 2992 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2993 set_ring_ps_enabled(rx_ring);
2994 else
2995 clear_ring_ps_enabled(rx_ring);
2996
2997 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2998 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2999 else
7d637bcc 3000 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3001
63f39bd1 3002#ifdef IXGBE_FCOE
e8e9f696 3003 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3004 struct ixgbe_ring_feature *f;
3005 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3006 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3007 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3008 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3009 rx_ring->rx_buf_len =
e8e9f696 3010 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3011 } else if (!ring_is_rsc_enabled(rx_ring) &&
3012 !ring_is_ps_enabled(rx_ring)) {
3013 rx_ring->rx_buf_len =
3014 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3015 }
63f39bd1 3016 }
63f39bd1 3017#endif /* IXGBE_FCOE */
477de6ed 3018 }
477de6ed
AD		 3019}
3020
7367096a
AD		 3021static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3022{
3023 struct ixgbe_hw *hw = &adapter->hw;
3024 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3025
3026 switch (hw->mac.type) {
3027 case ixgbe_mac_82598EB:
3028 /*
3029 * For VMDq support of different descriptor types or
3030 * buffer sizes through the use of multiple SRRCTL
3031 * registers, RDRXCTL.MVMEN must be set to 1
3032 *
3033 * also, the manual doesn't mention it clearly but DCA hints
3034 * will only use queue 0's tags unless this bit is set. Side
3035 * effects of setting this bit are only that SRRCTL must be
3036 * fully programmed [0..15]
3037 */
3038 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3039 break;
3040 case ixgbe_mac_82599EB:
b93a2226 3041 case ixgbe_mac_X540:
7367096a
AD		 3042 /* Disable RSC for ACK packets */
3043 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3044 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3045 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3046 /* hardware requires some bits to be set by default */
3047 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3048 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3049 break;
3050 default:
3051 /* We should do nothing since we don't know this hardware */
3052 return;
3053 }
3054
3055 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3056}
3057
477de6ed
AD		 3058/**
3059 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3060 * @adapter: board private structure
3061 *
3062 * Configure the Rx unit of the MAC after a reset.
3063 **/
3064static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3065{
3066 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3067 int i;
3068 u32 rxctrl;
477de6ed
AD		 3069
3070 /* disable receives while setting up the descriptors */
3071 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3072 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3073
3074 ixgbe_setup_psrtype(adapter);
7367096a 3075 ixgbe_setup_rdrxctl(adapter);
477de6ed 3076
9e10e045 3077 /* Program registers for the distribution of queues */
f5b4a52e 3078 ixgbe_setup_mrqc(adapter);
f5b4a52e 3079
9e10e045
AD		 3080 ixgbe_set_uta(adapter);
3081
477de6ed
AD		 3082 /* set_rx_buffer_len must be called before ring initialization */
3083 ixgbe_set_rx_buffer_len(adapter);
3084
3085 /*
3086 * Setup the HW Rx Head and Tail Descriptor Pointers and
3087 * the Base and Length of the Rx Descriptor Ring
3088 */
9e10e045
AD		 3089 for (i = 0; i < adapter->num_rx_queues; i++)
3090 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3091
9e10e045
AD		 3092 /* disable drop enable for 82598 parts */
3093 if (hw->mac.type == ixgbe_mac_82598EB)
3094 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3095
3096 /* enable all receives */
3097 rxctrl |= IXGBE_RXCTRL_RXEN;
3098 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3099}
3100
8e586137 3101static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3102{
3103 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3104 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3105 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3106
3107 /* add VID to filter table */
1ada1b1b 3108 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3109 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3110
3111 return 0;
068c89b0
DS		 3112}
3113
8e586137 3114static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3115{
3116 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3117 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3118 int pool_ndx = adapter->num_vfs;
068c89b0 3119
068c89b0 3120 /* remove VID from filter table */
1ada1b1b 3121 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3122 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3123
3124 return 0;
068c89b0
DS		 3125}
3126
5f6c0181
JB		 3127/**
3128 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3129 * @adapter: driver data
3130 */
3131static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3132{
3133 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3134 u32 vlnctrl;
3135
3136 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3137 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3138 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3139}
3140
3141/**
3142 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3143 * @adapter: driver data
3144 */
3145static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3146{
3147 struct ixgbe_hw *hw = &adapter->hw;
3148 u32 vlnctrl;
3149
3150 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3151 vlnctrl |= IXGBE_VLNCTRL_VFE;
3152 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3153 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3154}
3155
3156/**
3157 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3158 * @adapter: driver data
3159 */
3160static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3161{
3162 struct ixgbe_hw *hw = &adapter->hw;
3163 u32 vlnctrl;
5f6c0181
JB		 3164 int i, j;
3165
3166 switch (hw->mac.type) {
3167 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3168 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3169 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3170 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3171 break;
3172 case ixgbe_mac_82599EB:
b93a2226 3173 case ixgbe_mac_X540:
5f6c0181
JB		 3174 for (i = 0; i < adapter->num_rx_queues; i++) {
3175 j = adapter->rx_ring[i]->reg_idx;
3176 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3177 vlnctrl &= ~IXGBE_RXDCTL_VME;
3178 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3179 }
3180 break;
3181 default:
3182 break;
3183 }
3184}
3185
3186/**
f62bbb5e 3187 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3188 * @adapter: driver data
3189 */
f62bbb5e 3190static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3191{
3192 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3193 u32 vlnctrl;
5f6c0181
JB		 3194 int i, j;
3195
3196 switch (hw->mac.type) {
3197 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3198 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3199 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3200 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3201 break;
3202 case ixgbe_mac_82599EB:
b93a2226 3203 case ixgbe_mac_X540:
5f6c0181
JB		 3204 for (i = 0; i < adapter->num_rx_queues; i++) {
3205 j = adapter->rx_ring[i]->reg_idx;
3206 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3207 vlnctrl |= IXGBE_RXDCTL_VME;
3208 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3209 }
3210 break;
3211 default:
3212 break;
3213 }
3214}
3215
9a799d71
AK		 3216static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3217{
f62bbb5e 3218 u16 vid;
9a799d71 3219
f62bbb5e
JG		 3220 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3221
3222 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3223 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3224}
3225
2850062a
AD		 3226/**
3227 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3228 * @netdev: network interface device structure
3229 *
3230 * Writes unicast address list to the RAR table.
3231 * Returns: -ENOMEM on failure/insufficient address space
3232 * 0 on no addresses written
3233 * X on writing X addresses to the RAR table
3234 **/
3235static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3236{
3237 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3238 struct ixgbe_hw *hw = &adapter->hw;
3239 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3240 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3241 int count = 0;
3242
3243 /* return ENOMEM indicating insufficient memory for addresses */
3244 if (netdev_uc_count(netdev) > rar_entries)
3245 return -ENOMEM;
3246
3247 if (!netdev_uc_empty(netdev) && rar_entries) {
3248 struct netdev_hw_addr *ha;
3249 /* return error if we do not support writing to RAR table */
3250 if (!hw->mac.ops.set_rar)
3251 return -ENOMEM;
3252
3253 netdev_for_each_uc_addr(ha, netdev) {
3254 if (!rar_entries)
3255 break;
3256 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3257 vfn, IXGBE_RAH_AV);
3258 count++;
3259 }
3260 }
3261 /* write the addresses in reverse order to avoid write combining */
3262 for (; rar_entries > 0 ; rar_entries--)
3263 hw->mac.ops.clear_rar(hw, rar_entries);
3264
3265 return count;
3266}
3267
9a799d71 3268/**
2c5645cf 3269 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3270 * @netdev: network interface device structure
3271 *
2c5645cf
CL		 3272 * The set_rx_method entry point is called whenever the unicast/multicast
3273 * address list or the network interface flags are updated. This routine is
3274 * responsible for configuring the hardware for proper unicast, multicast and
3275 * promiscuous mode.
9a799d71 3276 **/
7f870475 3277void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3278{
3279 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3280 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3281 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3282 int count;
9a799d71
AK		 3283
3284 /* Check for Promiscuous and All Multicast modes */
3285
3286 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3287
f5dc442b
AD		 3288 /* set all bits that we expect to always be set */
3289 fctrl |= IXGBE_FCTRL_BAM;
3290 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3291 fctrl |= IXGBE_FCTRL_PMCF;
3292
2850062a
AD		 3293 /* clear the bits we are changing the status of */
3294 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3295
9a799d71 3296 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3297 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3298 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3299 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3300 /* don't hardware filter vlans in promisc mode */
3301 ixgbe_vlan_filter_disable(adapter);
9a799d71 3302 } else {
746b9f02
PM		 3303 if (netdev->flags & IFF_ALLMULTI) {
3304 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3305 vmolr |= IXGBE_VMOLR_MPE;
3306 } else {
3307 /*
3308 * Write addresses to the MTA, if the attempt fails
25985edc 3309 * then we should just turn on promiscuous mode so
2850062a
AD		 3310 * that we can at least receive multicast traffic
3311 */
3312 hw->mac.ops.update_mc_addr_list(hw, netdev);
3313 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3314 }
5f6c0181 3315 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3316 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3317 /*
3318 * Write addresses to available RAR registers, if there is not
3319 * sufficient space to store all the addresses then enable
25985edc 3320 * unicast promiscuous mode
2850062a
AD		 3321 */
3322 count = ixgbe_write_uc_addr_list(netdev);
3323 if (count < 0) {
3324 fctrl |= IXGBE_FCTRL_UPE;
3325 vmolr |= IXGBE_VMOLR_ROPE;
3326 }
9a799d71
AK		 3327 }
3328
2850062a 3329 if (adapter->num_vfs) {
1cdd1ec8 3330 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3331 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3332 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3333 IXGBE_VMOLR_ROPE);
3334 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3335 }
3336
3337 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3338
3339 if (netdev->features & NETIF_F_HW_VLAN_RX)
3340 ixgbe_vlan_strip_enable(adapter);
3341 else
3342 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3343}
3344
021230d4
AV		 3345static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3346{
3347 int q_idx;
3348 struct ixgbe_q_vector *q_vector;
3349 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3350
3351 /* legacy and MSI only use one vector */
3352 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3353 q_vectors = 1;
3354
3355 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3356 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3357 napi_enable(&q_vector->napi);
021230d4
AV		 3358 }
3359}
3360
3361static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3362{
3363 int q_idx;
3364 struct ixgbe_q_vector *q_vector;
3365 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3366
3367 /* legacy and MSI only use one vector */
3368 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3369 q_vectors = 1;
3370
3371 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3372 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3373 napi_disable(&q_vector->napi);
3374 }
3375}
3376
7a6b6f51 3377#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3378/*
3379 * ixgbe_configure_dcb - Configure DCB hardware
3380 * @adapter: ixgbe adapter struct
3381 *
3382 * This is called by the driver on open to configure the DCB hardware.
3383 * This is also called by the gennetlink interface when reconfiguring
3384 * the DCB state.
3385 */
3386static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3387{
3388 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3389 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3390
67ebd791
AD		 3391 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3392 if (hw->mac.type == ixgbe_mac_82598EB)
3393 netif_set_gso_max_size(adapter->netdev, 65536);
3394 return;
3395 }
3396
3397 if (hw->mac.type == ixgbe_mac_82598EB)
3398 netif_set_gso_max_size(adapter->netdev, 32768);
3399
2f90b865 3400
2f90b865 3401 /* Enable VLAN tag insert/strip */
f62bbb5e 3402 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3403
2f90b865 3404 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3405
971060b1 3406#ifdef IXGBE_FCOE
b120818e
JF		 3407 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3408 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3409#endif
b120818e
JF		 3410
3411 /* reconfigure the hardware */
3412 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3413 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3414 DCB_TX_CONFIG);
3415 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3416 DCB_RX_CONFIG);
3417 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3418 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3419 ixgbe_dcb_hw_ets(&adapter->hw,
3420 adapter->ixgbe_ieee_ets,
3421 max_frame);
3422 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3423 adapter->ixgbe_ieee_pfc->pfc_en,
3424 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3425 }
8187cd48
JF		 3426
3427 /* Enable RSS Hash per TC */
3428 if (hw->mac.type != ixgbe_mac_82598EB) {
3429 int i;
3430 u32 reg = 0;
3431
3432 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3433 u8 msb = 0;
3434 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3435
3436 while (cnt >>= 1)
3437 msb++;
3438
3439 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3440 }
3441 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3442 }
2f90b865 3443}
9da712d2
JF		 3444#endif
3445
3446/* Additional bittime to account for IXGBE framing */
3447#define IXGBE_ETH_FRAMING 20
3448
3449/*
3450 * ixgbe_hpbthresh - calculate high water mark for flow control
3451 *
3452 * @adapter: board private structure to calculate for
3453 * @pb - packet buffer to calculate
3454 */
3455static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3456{
3457 struct ixgbe_hw *hw = &adapter->hw;
3458 struct net_device *dev = adapter->netdev;
3459 int link, tc, kb, marker;
3460 u32 dv_id, rx_pba;
3461
3462 /* Calculate max LAN frame size */
3463 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3464
3465#ifdef IXGBE_FCOE
3466 /* FCoE traffic class uses FCOE jumbo frames */
3467 if (dev->features & NETIF_F_FCOE_MTU) {
3468 int fcoe_pb = 0;
2f90b865 3469
9da712d2
JF		 3470#ifdef CONFIG_IXGBE_DCB
3471 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3472
3473#endif
3474 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3475 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3476 }
2f90b865 3477#endif
80605c65 3478
9da712d2
JF		 3479 /* Calculate delay value for device */
3480 switch (hw->mac.type) {
3481 case ixgbe_mac_X540:
3482 dv_id = IXGBE_DV_X540(link, tc);
3483 break;
3484 default:
3485 dv_id = IXGBE_DV(link, tc);
3486 break;
3487 }
3488
3489 /* Loopback switch introduces additional latency */
3490 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3491 dv_id += IXGBE_B2BT(tc);
3492
3493 /* Delay value is calculated in bit times convert to KB */
3494 kb = IXGBE_BT2KB(dv_id);
3495 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3496
3497 marker = rx_pba - kb;
3498
3499 /* It is possible that the packet buffer is not large enough
3500 * to provide required headroom. In this case throw an error
3501 * to user and a do the best we can.
3502 */
3503 if (marker < 0) {
3504 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3505 "headroom to support flow control."
3506 "Decrease MTU or number of traffic classes\n", pb);
3507 marker = tc + 1;
3508 }
3509
3510 return marker;
3511}
3512
3513/*
3514 * ixgbe_lpbthresh - calculate low water mark for for flow control
3515 *
3516 * @adapter: board private structure to calculate for
3517 * @pb - packet buffer to calculate
3518 */
3519static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3520{
3521 struct ixgbe_hw *hw = &adapter->hw;
3522 struct net_device *dev = adapter->netdev;
3523 int tc;
3524 u32 dv_id;
3525
3526 /* Calculate max LAN frame size */
3527 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3528
3529 /* Calculate delay value for device */
3530 switch (hw->mac.type) {
3531 case ixgbe_mac_X540:
3532 dv_id = IXGBE_LOW_DV_X540(tc);
3533 break;
3534 default:
3535 dv_id = IXGBE_LOW_DV(tc);
3536 break;
3537 }
3538
3539 /* Delay value is calculated in bit times convert to KB */
3540 return IXGBE_BT2KB(dv_id);
3541}
3542
3543/*
3544 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3545 */
3546static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3547{
3548 struct ixgbe_hw *hw = &adapter->hw;
3549 int num_tc = netdev_get_num_tc(adapter->netdev);
3550 int i;
3551
3552 if (!num_tc)
3553 num_tc = 1;
3554
3555 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3556
3557 for (i = 0; i < num_tc; i++) {
3558 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3559
3560 /* Low water marks must not be larger than high water marks */
3561 if (hw->fc.low_water > hw->fc.high_water[i])
3562 hw->fc.low_water = 0;
3563 }
3564}
3565
80605c65
JF		 3566static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3567{
80605c65 3568 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3569 int hdrm;
3570 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3571
3572 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3573 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3574 hdrm = 32 << adapter->fdir_pballoc;
3575 else
3576 hdrm = 0;
80605c65 3577
f7e1027f 3578 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3579 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3580}
3581
e4911d57
AD		 3582static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3583{
3584 struct ixgbe_hw *hw = &adapter->hw;
3585 struct hlist_node *node, *node2;
3586 struct ixgbe_fdir_filter *filter;
3587
3588 spin_lock(&adapter->fdir_perfect_lock);
3589
3590 if (!hlist_empty(&adapter->fdir_filter_list))
3591 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3592
3593 hlist_for_each_entry_safe(filter, node, node2,
3594 &adapter->fdir_filter_list, fdir_node) {
3595 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3596 &filter->filter,
3597 filter->sw_idx,
3598 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3599 IXGBE_FDIR_DROP_QUEUE :
3600 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3601 }
3602
3603 spin_unlock(&adapter->fdir_perfect_lock);
3604}
3605
9a799d71
AK		 3606static void ixgbe_configure(struct ixgbe_adapter *adapter)
3607{
80605c65 3608 ixgbe_configure_pb(adapter);
7a6b6f51 3609#ifdef CONFIG_IXGBE_DCB
67ebd791 3610 ixgbe_configure_dcb(adapter);
2f90b865 3611#endif
9a799d71 3612
4c1d7b4b 3613 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3614 ixgbe_restore_vlan(adapter);
3615
eacd73f7
YZ		 3616#ifdef IXGBE_FCOE
3617 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3618 ixgbe_configure_fcoe(adapter);
3619
3620#endif /* IXGBE_FCOE */
c4cf55e5 3621 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3622 ixgbe_init_fdir_signature_82599(&adapter->hw,
3623 adapter->fdir_pballoc);
e4911d57
AD		 3624 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3625 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3626 adapter->fdir_pballoc);
3627 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3628 }
4c1d7b4b 3629
933d41f1 3630 ixgbe_configure_virtualization(adapter);
c4cf55e5 3631
9a799d71
AK		 3632 ixgbe_configure_tx(adapter);
3633 ixgbe_configure_rx(adapter);
9a799d71
AK		 3634}
3635
e8e26350
PW		 3636static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3637{
3638 switch (hw->phy.type) {
3639 case ixgbe_phy_sfp_avago:
3640 case ixgbe_phy_sfp_ftl:
3641 case ixgbe_phy_sfp_intel:
3642 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3643 case ixgbe_phy_sfp_passive_tyco:
3644 case ixgbe_phy_sfp_passive_unknown:
3645 case ixgbe_phy_sfp_active_unknown:
3646 case ixgbe_phy_sfp_ftl_active:
e8e26350 3647 return true;
8917b447
AD		 3648 case ixgbe_phy_nl:
3649 if (hw->mac.type == ixgbe_mac_82598EB)
3650 return true;
e8e26350
PW		 3651 default:
3652 return false;
3653 }
3654}
3655
0ecc061d 3656/**
e8e26350
PW		 3657 * ixgbe_sfp_link_config - set up SFP+ link
3658 * @adapter: pointer to private adapter struct
3659 **/
3660static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3661{
7086400d 3662 /*
52f33af8 3663 * We are assuming the worst case scenario here, and that
7086400d
AD		 3664 * is that an SFP was inserted/removed after the reset
3665 * but before SFP detection was enabled. As such the best
3666 * solution is to just start searching as soon as we start
3667 */
3668 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3669 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3670
7086400d 3671 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3672}
3673
3674/**
3675 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3676 * @hw: pointer to private hardware struct
3677 *
3678 * Returns 0 on success, negative on failure
3679 **/
e8e26350 3680static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3681{
3682 u32 autoneg;
8620a103 3683 bool negotiation, link_up = false;
0ecc061d
PWJ		 3684 u32 ret = IXGBE_ERR_LINK_SETUP;
3685
3686 if (hw->mac.ops.check_link)
3687 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3688
3689 if (ret)
3690 goto link_cfg_out;
3691
0b0c2b31
ET		 3692 autoneg = hw->phy.autoneg_advertised;
3693 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3694 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3695 &negotiation);
0ecc061d
PWJ		 3696 if (ret)
3697 goto link_cfg_out;
3698
8620a103
MC		 3699 if (hw->mac.ops.setup_link)
3700 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3701link_cfg_out:
3702 return ret;
3703}
3704
a34bcfff 3705static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3706{
9a799d71 3707 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3708 u32 gpie = 0;
9a799d71 3709
9b471446 3710 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3711 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3712 IXGBE_GPIE_OCD;
3713 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3714 /*
3715 * use EIAM to auto-mask when MSI-X interrupt is asserted
3716 * this saves a register write for every interrupt
3717 */
3718 switch (hw->mac.type) {
3719 case ixgbe_mac_82598EB:
3720 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3721 break;
9b471446 3722 case ixgbe_mac_82599EB:
b93a2226
DS		 3723 case ixgbe_mac_X540:
3724 default:
9b471446
JB		 3725 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3726 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3727 break;
3728 }
3729 } else {
021230d4
AV		 3730 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3731 * specifically only auto mask tx and rx interrupts */
3732 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3733 }
9a799d71 3734
a34bcfff
AD		 3735 /* XXX: to interrupt immediately for EICS writes, enable this */
3736 /* gpie |= IXGBE_GPIE_EIMEN; */
3737
3738 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3739 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3740 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3741 }
3742
5fdd31f9 3743 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3744 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3745 switch (adapter->hw.mac.type) {
3746 case ixgbe_mac_82599EB:
3747 gpie |= IXGBE_SDP0_GPIEN;
3748 break;
3749 case ixgbe_mac_X540:
3750 gpie |= IXGBE_EIMS_TS;
3751 break;
3752 default:
3753 break;
3754 }
3755 }
5fdd31f9 3756
a34bcfff
AD		 3757 /* Enable fan failure interrupt */
3758 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3759 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3760
2698b208 3761 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3762 gpie |= IXGBE_SDP1_GPIEN;
3763 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3764 }
a34bcfff
AD		 3765
3766 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3767}
3768
c7ccde0f 3769static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3770{
3771 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3772 int err;
a34bcfff
AD		 3773 u32 ctrl_ext;
3774
3775 ixgbe_get_hw_control(adapter);
3776 ixgbe_setup_gpie(adapter);
e8e26350 3777
9a799d71
AK		 3778 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3779 ixgbe_configure_msix(adapter);
3780 else
3781 ixgbe_configure_msi_and_legacy(adapter);
3782
c6ecf39a
DS		 3783 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3784 if (hw->mac.ops.enable_tx_laser &&
3785 ((hw->phy.multispeed_fiber) ||
9f911707 3786 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3787 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3788 hw->mac.ops.enable_tx_laser(hw);
3789
9a799d71 3790 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3791 ixgbe_napi_enable_all(adapter);
3792
73c4b7cd
AD		 3793 if (ixgbe_is_sfp(hw)) {
3794 ixgbe_sfp_link_config(adapter);
3795 } else {
3796 err = ixgbe_non_sfp_link_config(hw);
3797 if (err)
3798 e_err(probe, "link_config FAILED %d\n", err);
3799 }
3800
021230d4
AV		 3801 /* clear any pending interrupts, may auto mask */
3802 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3803 ixgbe_irq_enable(adapter, true, true);
9a799d71 3804
bf069c97
DS		 3805 /*
3806 * If this adapter has a fan, check to see if we had a failure
3807 * before we enabled the interrupt.
3808 */
3809 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3810 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3811 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3812 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3813 }
3814
1da100bb 3815 /* enable transmits */
477de6ed 3816 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3817
9a799d71
AK		 3818 /* bring the link up in the watchdog, this could race with our first
3819 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3820 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3821 adapter->link_check_timeout = jiffies;
7086400d 3822 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3823
3824 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3825 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3826 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3827 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3828}
3829
d4f80882
AV		 3830void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3831{
3832 WARN_ON(in_interrupt());
7086400d
AD		 3833 /* put off any impending NetWatchDogTimeout */
3834 adapter->netdev->trans_start = jiffies;
3835
d4f80882 3836 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3837 usleep_range(1000, 2000);
d4f80882 3838 ixgbe_down(adapter);
5809a1ae
GR		 3839 /*
3840 * If SR-IOV enabled then wait a bit before bringing the adapter
3841 * back up to give the VFs time to respond to the reset. The
3842 * two second wait is based upon the watchdog timer cycle in
3843 * the VF driver.
3844 */
3845 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3846 msleep(2000);
d4f80882
AV		 3847 ixgbe_up(adapter);
3848 clear_bit(__IXGBE_RESETTING, &adapter->state);
3849}
3850
c7ccde0f 3851void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3852{
3853 /* hardware has been reset, we need to reload some things */
3854 ixgbe_configure(adapter);
3855
c7ccde0f 3856 ixgbe_up_complete(adapter);
9a799d71
AK		 3857}
3858
3859void ixgbe_reset(struct ixgbe_adapter *adapter)
3860{
c44ade9e 3861 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3862 int err;
3863
7086400d
AD		 3864 /* lock SFP init bit to prevent race conditions with the watchdog */
3865 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3866 usleep_range(1000, 2000);
3867
3868 /* clear all SFP and link config related flags while holding SFP_INIT */
3869 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3870 IXGBE_FLAG2_SFP_NEEDS_RESET);
3871 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3872
8ca783ab 3873 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3874 switch (err) {
3875 case 0:
3876 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3877 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3878 break;
3879 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3880 e_dev_err("master disable timed out\n");
da4dd0f7 3881 break;
794caeb2
PWJ		 3882 case IXGBE_ERR_EEPROM_VERSION:
3883 /* We are running on a pre-production device, log a warning */
849c4542 3884 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 3885 "Please be aware there may be issues associated with "
849c4542
ET		 3886 "your hardware. If you are experiencing problems "
3887 "please contact your Intel or hardware "
3888 "representative who provided you with this "
3889 "hardware.\n");
794caeb2 3890 break;
da4dd0f7 3891 default:
849c4542 3892 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3893 }
9a799d71 3894
7086400d
AD		 3895 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3896
9a799d71 3897 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3898 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3899 IXGBE_RAH_AV);
9a799d71
AK		 3900}
3901
9a799d71
AK		 3902/**
3903 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3904 * @rx_ring: ring to free buffers from
3905 **/
b6ec895e 3906static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3907{
b6ec895e 3908 struct device *dev = rx_ring->dev;
9a799d71 3909 unsigned long size;
b6ec895e 3910 u16 i;
9a799d71 3911
84418e3b
AD		 3912 /* ring already cleared, nothing to do */
3913 if (!rx_ring->rx_buffer_info)
3914 return;
9a799d71 3915
84418e3b 3916 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3917 for (i = 0; i < rx_ring->count; i++) {
3918 struct ixgbe_rx_buffer *rx_buffer_info;
3919
3920 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3921 if (rx_buffer_info->dma) {
b6ec895e 3922 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3923 rx_ring->rx_buf_len,
1b507730 3924 DMA_FROM_DEVICE);
9a799d71
AK		 3925 rx_buffer_info->dma = 0;
3926 }
3927 if (rx_buffer_info->skb) {
f8212f97 3928 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3929 rx_buffer_info->skb = NULL;
4c1975d7
AD		 3930 /* We need to clean up RSC frag lists */
3931 skb = ixgbe_merge_active_tail(skb);
3932 ixgbe_close_active_frag_list(skb);
3933 if (IXGBE_CB(skb)->delay_unmap) {
3934 dma_unmap_single(dev,
3935 IXGBE_CB(skb)->dma,
3936 rx_ring->rx_buf_len,
3937 DMA_FROM_DEVICE);
3938 IXGBE_CB(skb)->dma = 0;
3939 IXGBE_CB(skb)->delay_unmap = false;
3940 }
3941 dev_kfree_skb(skb);
9a799d71
AK		 3942 }
3943 if (!rx_buffer_info->page)
3944 continue;
4f57ca6e 3945 if (rx_buffer_info->page_dma) {
b6ec895e 3946 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3947 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3948 rx_buffer_info->page_dma = 0;
3949 }
9a799d71
AK		 3950 put_page(rx_buffer_info->page);
3951 rx_buffer_info->page = NULL;
762f4c57 3952 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3953 }
3954
3955 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3956 memset(rx_ring->rx_buffer_info, 0, size);
3957
3958 /* Zero out the descriptor ring */
3959 memset(rx_ring->desc, 0, rx_ring->size);
3960
3961 rx_ring->next_to_clean = 0;
3962 rx_ring->next_to_use = 0;
9a799d71
AK		 3963}
3964
3965/**
3966 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3967 * @tx_ring: ring to be cleaned
3968 **/
b6ec895e 3969static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3970{
3971 struct ixgbe_tx_buffer *tx_buffer_info;
3972 unsigned long size;
b6ec895e 3973 u16 i;
9a799d71 3974
84418e3b
AD		 3975 /* ring already cleared, nothing to do */
3976 if (!tx_ring->tx_buffer_info)
3977 return;
9a799d71 3978
84418e3b 3979 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3980 for (i = 0; i < tx_ring->count; i++) {
3981 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3982 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3983 }
3984
3985 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3986 memset(tx_ring->tx_buffer_info, 0, size);
3987
3988 /* Zero out the descriptor ring */
3989 memset(tx_ring->desc, 0, tx_ring->size);
3990
3991 tx_ring->next_to_use = 0;
3992 tx_ring->next_to_clean = 0;
9a799d71
AK		 3993}
3994
3995/**
021230d4 3996 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3997 * @adapter: board private structure
3998 **/
021230d4 3999static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4000{
4001 int i;
4002
021230d4 4003 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4004 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4005}
4006
4007/**
021230d4 4008 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4009 * @adapter: board private structure
4010 **/
021230d4 4011static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4012{
4013 int i;
4014
021230d4 4015 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4016 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4017}
4018
e4911d57
AD		 4019static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4020{
4021 struct hlist_node *node, *node2;
4022 struct ixgbe_fdir_filter *filter;
4023
4024 spin_lock(&adapter->fdir_perfect_lock);
4025
4026 hlist_for_each_entry_safe(filter, node, node2,
4027 &adapter->fdir_filter_list, fdir_node) {
4028 hlist_del(&filter->fdir_node);
4029 kfree(filter);
4030 }
4031 adapter->fdir_filter_count = 0;
4032
4033 spin_unlock(&adapter->fdir_perfect_lock);
4034}
4035
9a799d71
AK		 4036void ixgbe_down(struct ixgbe_adapter *adapter)
4037{
4038 struct net_device *netdev = adapter->netdev;
7f821875 4039 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4040 u32 rxctrl;
bf29ee6c 4041 int i;
9a799d71
AK		 4042
4043 /* signal that we are down to the interrupt handler */
4044 set_bit(__IXGBE_DOWN, &adapter->state);
4045
4046 /* disable receives */
7f821875
JB		 4047 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4048 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4049
2d39d576
YZ		 4050 /* disable all enabled rx queues */
4051 for (i = 0; i < adapter->num_rx_queues; i++)
4052 /* this call also flushes the previous write */
4053 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4054
032b4325 4055 usleep_range(10000, 20000);
9a799d71 4056
7f821875
JB		 4057 netif_tx_stop_all_queues(netdev);
4058
7086400d 4059 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4060 netif_carrier_off(netdev);
4061 netif_tx_disable(netdev);
4062
4063 ixgbe_irq_disable(adapter);
4064
4065 ixgbe_napi_disable_all(adapter);
4066
d034acf1
AD		 4067 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4068 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4069 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4070
4071 del_timer_sync(&adapter->service_timer);
4072
34cecbbf 4073 if (adapter->num_vfs) {
8e34d1aa
AD		 4074 /* Clear EITR Select mapping */
4075 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4076
4077 /* Mark all the VFs as inactive */
4078 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4079 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4080
34cecbbf
AD		 4081 /* ping all the active vfs to let them know we are going down */
4082 ixgbe_ping_all_vfs(adapter);
4083
4084 /* Disable all VFTE/VFRE TX/RX */
4085 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4086 }
4087
7f821875
JB		 4088 /* disable transmits in the hardware now that interrupts are off */
4089 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4090 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4091 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4092 }
34cecbbf
AD		 4093
4094 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4095 switch (hw->mac.type) {
4096 case ixgbe_mac_82599EB:
b93a2226 4097 case ixgbe_mac_X540:
88512539 4098 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4099 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4100 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4101 break;
4102 default:
4103 break;
4104 }
7f821875 4105
6f4a0e45
PL		 4106 if (!pci_channel_offline(adapter->pdev))
4107 ixgbe_reset(adapter);
c6ecf39a
DS		 4108
4109 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4110 if (hw->mac.ops.disable_tx_laser &&
4111 ((hw->phy.multispeed_fiber) ||
9f911707 4112 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4113 (hw->mac.type == ixgbe_mac_82599EB))))
4114 hw->mac.ops.disable_tx_laser(hw);
4115
9a799d71
AK		 4116 ixgbe_clean_all_tx_rings(adapter);
4117 ixgbe_clean_all_rx_rings(adapter);
4118
5dd2d332 4119#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4120 /* since we reset the hardware DCA settings were cleared */
e35ec126 4121 ixgbe_setup_dca(adapter);
96b0e0f6 4122#endif
9a799d71
AK		 4123}
4124
9a799d71 4125/**
021230d4
AV		 4126 * ixgbe_poll - NAPI Rx polling callback
4127 * @napi: structure for representing this polling device
4128 * @budget: how many packets driver is allowed to clean
4129 *
4130 * This function is used for legacy and MSI, NAPI mode
9a799d71 4131 **/
021230d4 4132static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4133{
9a1a69ad 4134 struct ixgbe_q_vector *q_vector =
e8e9f696 4135 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4136 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4137 struct ixgbe_ring *ring;
4138 int per_ring_budget;
4139 bool clean_complete = true;
9a799d71 4140
5dd2d332 4141#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4142 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4143 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4144#endif
4145
4ff7fb12
AD		 4146 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4147 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4148
4ff7fb12
AD		 4149 /* attempt to distribute budget to each queue fairly, but don't allow
4150 * the budget to go below 1 because we'll exit polling */
4151 if (q_vector->rx.count > 1)
4152 per_ring_budget = max(budget/q_vector->rx.count, 1);
4153 else
4154 per_ring_budget = budget;
d2c7ddd6 4155
4ff7fb12
AD		 4156 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4157 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4158 per_ring_budget);
4159
4160 /* If all work not completed, return budget and keep polling */
4161 if (!clean_complete)
4162 return budget;
4163
4164 /* all work done, exit the polling mode */
4165 napi_complete(napi);
4166 if (adapter->rx_itr_setting & 1)
4167 ixgbe_set_itr(q_vector);
4168 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4169 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4170
4171 return 0;
9a799d71
AK		 4172}
4173
4174/**
4175 * ixgbe_tx_timeout - Respond to a Tx Hang
4176 * @netdev: network interface device structure
4177 **/
4178static void ixgbe_tx_timeout(struct net_device *netdev)
4179{
4180 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4181
4182 /* Do the reset outside of interrupt context */
c83c6cbd 4183 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4184}
4185
4df10466
JB		 4186/**
4187 * ixgbe_set_rss_queues: Allocate queues for RSS
4188 * @adapter: board private structure to initialize
4189 *
4190 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4191 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4192 *
4193 **/
bc97114d
PWJ		 4194static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4195{
4196 bool ret = false;
0cefafad 4197 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4198
4199 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4200 f->mask = 0xF;
4201 adapter->num_rx_queues = f->indices;
4202 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4203 ret = true;
4204 } else {
bc97114d 4205 ret = false;
b9804972
JB		 4206 }
4207
bc97114d
PWJ		 4208 return ret;
4209}
4210
c4cf55e5
PWJ		 4211/**
4212 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4213 * @adapter: board private structure to initialize
4214 *
4215 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4216 * to the original CPU that initiated the Tx session. This runs in addition
4217 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4218 * Rx load across CPUs using RSS.
4219 *
4220 **/
e8e9f696 4221static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4222{
4223 bool ret = false;
4224 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4225
4226 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4227 f_fdir->mask = 0;
4228
4229 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4230 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4231 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4232 adapter->num_tx_queues = f_fdir->indices;
4233 adapter->num_rx_queues = f_fdir->indices;
4234 ret = true;
4235 } else {
4236 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4237 }
4238 return ret;
4239}
4240
0331a832
YZ		 4241#ifdef IXGBE_FCOE
4242/**
4243 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4244 * @adapter: board private structure to initialize
4245 *
4246 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4247 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4248 * rx queues out of the max number of rx queues, instead, it is used as the
4249 * index of the first rx queue used by FCoE.
4250 *
4251 **/
4252static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4253{
0331a832
YZ		 4254 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4255
e5b64635
JF		 4256 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4257 return false;
4258
e901acd6 4259 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4260
e901acd6
JF		 4261 adapter->num_rx_queues = 1;
4262 adapter->num_tx_queues = 1;
e5b64635 4263
e901acd6
JF		 4264 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4265 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4266 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4267 ixgbe_set_fdir_queues(adapter);
4268 else
4269 ixgbe_set_rss_queues(adapter);
e5b64635 4270 }
03ecf91a 4271
e901acd6
JF		 4272 /* adding FCoE rx rings to the end */
4273 f->mask = adapter->num_rx_queues;
4274 adapter->num_rx_queues += f->indices;
4275 adapter->num_tx_queues += f->indices;
0331a832 4276
e5b64635
JF		 4277 return true;
4278}
4279#endif /* IXGBE_FCOE */
4280
e901acd6
JF		 4281/* Artificial max queue cap per traffic class in DCB mode */
4282#define DCB_QUEUE_CAP 8
4283
e5b64635
JF		 4284#ifdef CONFIG_IXGBE_DCB
4285static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4286{
e901acd6
JF		 4287 int per_tc_q, q, i, offset = 0;
4288 struct net_device *dev = adapter->netdev;
4289 int tcs = netdev_get_num_tc(dev);
e5b64635 4290
e901acd6
JF		 4291 if (!tcs)
4292 return false;
e5b64635 4293
e901acd6
JF		 4294 /* Map queue offset and counts onto allocated tx queues */
4295 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4296 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4297
8b1c0b24 4298 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4299 netdev_set_tc_queue(dev, i, q, offset);
4300 offset += q;
0331a832
YZ		 4301 }
4302
e901acd6
JF		 4303 adapter->num_tx_queues = q * tcs;
4304 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4305
4306#ifdef IXGBE_FCOE
e901acd6
JF		 4307 /* FCoE enabled queues require special configuration indexed
4308 * by feature specific indices and mask. Here we map FCoE
4309 * indices onto the DCB queue pairs allowing FCoE to own
4310 * configuration later.
e5b64635 4311 */
e901acd6
JF		 4312 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4313 int tc;
4314 struct ixgbe_ring_feature *f =
4315 &adapter->ring_feature[RING_F_FCOE];
4316
4317 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4318 f->indices = dev->tc_to_txq[tc].count;
4319 f->mask = dev->tc_to_txq[tc].offset;
4320 }
e5b64635
JF		 4321#endif
4322
e901acd6 4323 return true;
0331a832 4324}
e5b64635 4325#endif
0331a832 4326
1cdd1ec8
GR		 4327/**
4328 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4329 * @adapter: board private structure to initialize
4330 *
4331 * IOV doesn't actually use anything, so just NAK the
4332 * request for now and let the other queue routines
4333 * figure out what to do.
4334 */
4335static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4336{
4337 return false;
4338}
4339
4df10466 4340/*
25985edc 4341 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4342 * @adapter: board private structure to initialize
4343 *
4344 * This is the top level queue allocation routine. The order here is very
4345 * important, starting with the "most" number of features turned on at once,
4346 * and ending with the smallest set of features. This way large combinations
4347 * can be allocated if they're turned on, and smaller combinations are the
4348 * fallthrough conditions.
4349 *
4350 **/
847f53ff 4351static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4352{
1cdd1ec8
GR		 4353 /* Start with base case */
4354 adapter->num_rx_queues = 1;
4355 adapter->num_tx_queues = 1;
4356 adapter->num_rx_pools = adapter->num_rx_queues;
4357 adapter->num_rx_queues_per_pool = 1;
4358
4359 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4360 goto done;
1cdd1ec8 4361
bc97114d
PWJ		 4362#ifdef CONFIG_IXGBE_DCB
4363 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4364 goto done;
bc97114d
PWJ		 4365
4366#endif
e5b64635
JF		 4367#ifdef IXGBE_FCOE
4368 if (ixgbe_set_fcoe_queues(adapter))
4369 goto done;
4370
4371#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4372 if (ixgbe_set_fdir_queues(adapter))
4373 goto done;
4374
bc97114d 4375 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4376 goto done;
4377
4378 /* fallback to base case */
4379 adapter->num_rx_queues = 1;
4380 adapter->num_tx_queues = 1;
4381
4382done:
847f53ff 4383 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4384 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4385 return netif_set_real_num_rx_queues(adapter->netdev,
4386 adapter->num_rx_queues);
b9804972
JB		 4387}
4388
021230d4 4389static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4390 int vectors)
021230d4
AV		 4391{
4392 int err, vector_threshold;
4393
4394 /* We'll want at least 3 (vector_threshold):
4395 * 1) TxQ[0] Cleanup
4396 * 2) RxQ[0] Cleanup
4397 * 3) Other (Link Status Change, etc.)
4398 * 4) TCP Timer (optional)
4399 */
4400 vector_threshold = MIN_MSIX_COUNT;
4401
4402 /* The more we get, the more we will assign to Tx/Rx Cleanup
4403 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4404 * Right now, we simply care about how many we'll get; we'll
4405 * set them up later while requesting irq's.
4406 */
4407 while (vectors >= vector_threshold) {
4408 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4409 vectors);
021230d4
AV		 4410 if (!err) /* Success in acquiring all requested vectors. */
4411 break;
4412 else if (err < 0)
4413 vectors = 0; /* Nasty failure, quit now */
4414 else /* err == number of vectors we should try again with */
4415 vectors = err;
4416 }
4417
4418 if (vectors < vector_threshold) {
4419 /* Can't allocate enough MSI-X interrupts? Oh well.
4420 * This just means we'll go with either a single MSI
4421 * vector or fall back to legacy interrupts.
4422 */
849c4542
ET		 4423 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4424 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4425 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4426 kfree(adapter->msix_entries);
4427 adapter->msix_entries = NULL;
021230d4
AV		 4428 } else {
4429 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4430 /*
4431 * Adjust for only the vectors we'll use, which is minimum
4432 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4433 * vectors we were allocated.
4434 */
4435 adapter->num_msix_vectors = min(vectors,
e8e9f696 4436 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4437 }
4438}
4439
021230d4 4440/**
bc97114d 4441 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4442 * @adapter: board private structure to initialize
4443 *
bc97114d
PWJ		 4444 * Cache the descriptor ring offsets for RSS to the assigned rings.
4445 *
021230d4 4446 **/
bc97114d 4447static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4448{
bc97114d 4449 int i;
bc97114d 4450
9d6b758f
AD		 4451 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4452 return false;
bc97114d 4453
9d6b758f
AD		 4454 for (i = 0; i < adapter->num_rx_queues; i++)
4455 adapter->rx_ring[i]->reg_idx = i;
4456 for (i = 0; i < adapter->num_tx_queues; i++)
4457 adapter->tx_ring[i]->reg_idx = i;
4458
4459 return true;
bc97114d
PWJ		 4460}
4461
4462#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4463
4464/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4465static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4466 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4467{
4468 struct net_device *dev = adapter->netdev;
4469 struct ixgbe_hw *hw = &adapter->hw;
4470 u8 num_tcs = netdev_get_num_tc(dev);
4471
4472 *tx = 0;
4473 *rx = 0;
4474
4475 switch (hw->mac.type) {
4476 case ixgbe_mac_82598EB:
aba70d5e
JF		 4477 *tx = tc << 2;
4478 *rx = tc << 3;
e5b64635
JF		 4479 break;
4480 case ixgbe_mac_82599EB:
4481 case ixgbe_mac_X540:
4fa2e0e1 4482 if (num_tcs > 4) {
e5b64635
JF		 4483 if (tc < 3) {
4484 *tx = tc << 5;
4485 *rx = tc << 4;
4486 } else if (tc < 5) {
4487 *tx = ((tc + 2) << 4);
4488 *rx = tc << 4;
4489 } else if (tc < num_tcs) {
4490 *tx = ((tc + 8) << 3);
4491 *rx = tc << 4;
4492 }
4fa2e0e1 4493 } else {
e5b64635
JF		 4494 *rx = tc << 5;
4495 switch (tc) {
4496 case 0:
4497 *tx = 0;
4498 break;
4499 case 1:
4500 *tx = 64;
4501 break;
4502 case 2:
4503 *tx = 96;
4504 break;
4505 case 3:
4506 *tx = 112;
4507 break;
4508 default:
4509 break;
4510 }
4511 }
4512 break;
4513 default:
4514 break;
4515 }
4516}
4517
bc97114d
PWJ		 4518/**
4519 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4520 * @adapter: board private structure to initialize
4521 *
4522 * Cache the descriptor ring offsets for DCB to the assigned rings.
4523 *
4524 **/
4525static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4526{
e5b64635
JF		 4527 struct net_device *dev = adapter->netdev;
4528 int i, j, k;
4529 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4530
8b1c0b24 4531 if (!num_tcs)
bd508178 4532 return false;
f92ef202 4533
e5b64635
JF		 4534 for (i = 0, k = 0; i < num_tcs; i++) {
4535 unsigned int tx_s, rx_s;
4536 u16 count = dev->tc_to_txq[i].count;
4537
4538 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4539 for (j = 0; j < count; j++, k++) {
4540 adapter->tx_ring[k]->reg_idx = tx_s + j;
4541 adapter->rx_ring[k]->reg_idx = rx_s + j;
4542 adapter->tx_ring[k]->dcb_tc = i;
4543 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4544 }
021230d4 4545 }
e5b64635
JF		 4546
4547 return true;
bc97114d
PWJ		 4548}
4549#endif
4550
c4cf55e5
PWJ		 4551/**
4552 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4553 * @adapter: board private structure to initialize
4554 *
4555 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4556 *
4557 **/
e8e9f696 4558static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4559{
4560 int i;
4561 bool ret = false;
4562
03ecf91a
AD		 4563 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4564 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4565 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4566 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4567 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4568 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4569 ret = true;
4570 }
4571
4572 return ret;
4573}
4574
0331a832
YZ		 4575#ifdef IXGBE_FCOE
4576/**
4577 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4578 * @adapter: board private structure to initialize
4579 *
4580 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4581 *
4582 */
4583static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4584{
0331a832 4585 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4586 int i;
4587 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4588
4589 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4590 return false;
0331a832 4591
bf29ee6c 4592 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4593 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4594 ixgbe_cache_ring_fdir(adapter);
4595 else
4596 ixgbe_cache_ring_rss(adapter);
8faa2a78 4597
bf29ee6c
AD		 4598 fcoe_rx_i = f->mask;
4599 fcoe_tx_i = f->mask;
0331a832 4600 }
bf29ee6c
AD		 4601 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4602 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4603 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4604 }
4605 return true;
0331a832
YZ		 4606}
4607
4608#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4609/**
4610 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4611 * @adapter: board private structure to initialize
4612 *
4613 * SR-IOV doesn't use any descriptor rings but changes the default if
4614 * no other mapping is used.
4615 *
4616 */
4617static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4618{
4a0b9ca0
PW		 4619 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4620 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4621 if (adapter->num_vfs)
4622 return true;
4623 else
4624 return false;
4625}
4626
bc97114d
PWJ		 4627/**
4628 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4629 * @adapter: board private structure to initialize
4630 *
4631 * Once we know the feature-set enabled for the device, we'll cache
4632 * the register offset the descriptor ring is assigned to.
4633 *
4634 * Note, the order the various feature calls is important. It must start with
4635 * the "most" features enabled at the same time, then trickle down to the
4636 * least amount of features turned on at once.
4637 **/
4638static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4639{
4640 /* start with default case */
4a0b9ca0
PW		 4641 adapter->rx_ring[0]->reg_idx = 0;
4642 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4643
1cdd1ec8
GR		 4644 if (ixgbe_cache_ring_sriov(adapter))
4645 return;
4646
e5b64635
JF		 4647#ifdef CONFIG_IXGBE_DCB
4648 if (ixgbe_cache_ring_dcb(adapter))
4649 return;
4650#endif
4651
0331a832
YZ		 4652#ifdef IXGBE_FCOE
4653 if (ixgbe_cache_ring_fcoe(adapter))
4654 return;
0331a832 4655#endif /* IXGBE_FCOE */
bc97114d 4656
c4cf55e5
PWJ		 4657 if (ixgbe_cache_ring_fdir(adapter))
4658 return;
4659
bc97114d
PWJ		 4660 if (ixgbe_cache_ring_rss(adapter))
4661 return;
021230d4
AV		 4662}
4663
9a799d71
AK		 4664/**
4665 * ixgbe_alloc_queues - Allocate memory for all rings
4666 * @adapter: board private structure to initialize
4667 *
4668 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4669 * number of queues at compile-time. The polling_netdev array is
4670 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4671 **/
2f90b865 4672static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4673{
e2ddeba9 4674 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4675
e2ddeba9
ED		 4676 if (nid < 0 || !node_online(nid))
4677 nid = first_online_node;
4678
4679 for (; tx < adapter->num_tx_queues; tx++) {
4680 struct ixgbe_ring *ring;
4681
4682 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4683 if (!ring)
e2ddeba9 4684 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4685 if (!ring)
e2ddeba9 4686 goto err_allocation;
4a0b9ca0 4687 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4688 ring->queue_index = tx;
4689 ring->numa_node = nid;
b6ec895e 4690 ring->dev = &adapter->pdev->dev;
fc77dc3c 4691 ring->netdev = adapter->netdev;
4a0b9ca0 4692
e2ddeba9 4693 adapter->tx_ring[tx] = ring;
021230d4 4694 }
b9804972 4695
e2ddeba9
ED		 4696 for (; rx < adapter->num_rx_queues; rx++) {
4697 struct ixgbe_ring *ring;
4a0b9ca0 4698
e2ddeba9 4699 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4700 if (!ring)
e2ddeba9 4701 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4702 if (!ring)
e2ddeba9
ED		 4703 goto err_allocation;
4704 ring->count = adapter->rx_ring_count;
4705 ring->queue_index = rx;
4706 ring->numa_node = nid;
b6ec895e 4707 ring->dev = &adapter->pdev->dev;
fc77dc3c 4708 ring->netdev = adapter->netdev;
4a0b9ca0 4709
e2ddeba9 4710 adapter->rx_ring[rx] = ring;
021230d4
AV		 4711 }
4712
4713 ixgbe_cache_ring_register(adapter);
4714
4715 return 0;
4716
e2ddeba9
ED		 4717err_allocation:
4718 while (tx)
4719 kfree(adapter->tx_ring[--tx]);
4720
4721 while (rx)
4722 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4723 return -ENOMEM;
4724}
4725
4726/**
4727 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4728 * @adapter: board private structure to initialize
4729 *
4730 * Attempt to configure the interrupts using the best available
4731 * capabilities of the hardware and the kernel.
4732 **/
feea6a57 4733static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4734{
8be0e467 4735 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4736 int err = 0;
4737 int vector, v_budget;
4738
4739 /*
4740 * It's easy to be greedy for MSI-X vectors, but it really
4741 * doesn't do us much good if we have a lot more vectors
4742 * than CPU's. So let's be conservative and only ask for
342bde1b 4743 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4744 */
4745 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4746 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4747
4748 /*
4749 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4750 * hw.mac->max_msix_vectors vectors. With features
4751 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4752 * descriptor queues supported by our device. Thus, we cap it off in
4753 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4754 */
8be0e467 4755 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4756
4757 /* A failure in MSI-X entry allocation isn't fatal, but it does
4758 * mean we disable MSI-X capabilities of the adapter. */
4759 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4760 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4761 if (adapter->msix_entries) {
4762 for (vector = 0; vector < v_budget; vector++)
4763 adapter->msix_entries[vector].entry = vector;
021230d4 4764
7a921c93 4765 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4766
7a921c93
AD		 4767 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4768 goto out;
4769 }
26d27844 4770
7a921c93
AD		 4771 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4772 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4773 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4774 e_err(probe,
03ecf91a 4775 "ATR is not supported while multiple "
45b9f509
AD		 4776 "queues are disabled. Disabling Flow Director\n");
4777 }
c4cf55e5 4778 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4779 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4780 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4781 ixgbe_disable_sriov(adapter);
4782
847f53ff
BH		 4783 err = ixgbe_set_num_queues(adapter);
4784 if (err)
4785 return err;
021230d4 4786
021230d4
AV		 4787 err = pci_enable_msi(adapter->pdev);
4788 if (!err) {
4789 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4790 } else {
849c4542
ET		 4791 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4792 "Unable to allocate MSI interrupt, "
4793 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4794 /* reset err */
4795 err = 0;
4796 }
4797
4798out:
021230d4
AV		 4799 return err;
4800}
4801
7a921c93
AD		 4802/**
4803 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4804 * @adapter: board private structure to initialize
4805 *
4806 * We allocate one q_vector per queue interrupt. If allocation fails we
4807 * return -ENOMEM.
4808 **/
4809static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4810{
4ff7fb12 4811 int v_idx, num_q_vectors;
7a921c93 4812 struct ixgbe_q_vector *q_vector;
7a921c93 4813
4ff7fb12 4814 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4815 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4816 else
7a921c93 4817 num_q_vectors = 1;
7a921c93 4818
4ff7fb12 4819 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4820 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4821 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4822 if (!q_vector)
4823 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4824 GFP_KERNEL);
7a921c93
AD		 4825 if (!q_vector)
4826 goto err_out;
4ff7fb12 4827
7a921c93 4828 q_vector->adapter = adapter;
4ff7fb12
AD		 4829 q_vector->v_idx = v_idx;
4830
207867f5
AD		 4831 /* Allocate the affinity_hint cpumask, configure the mask */
4832 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4833 goto err_out;
4834 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 4835 netif_napi_add(adapter->netdev, &q_vector->napi,
4836 ixgbe_poll, 64);
4837 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4838 }
4839
4840 return 0;
4841
4842err_out:
4ff7fb12
AD		 4843 while (v_idx) {
4844 v_idx--;
4845 q_vector = adapter->q_vector[v_idx];
7a921c93 4846 netif_napi_del(&q_vector->napi);
207867f5 4847 free_cpumask_var(q_vector->affinity_mask);
7a921c93 4848 kfree(q_vector);
4ff7fb12 4849 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 4850 }
4851 return -ENOMEM;
4852}
4853
4854/**
4855 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4856 * @adapter: board private structure to initialize
4857 *
4858 * This function frees the memory allocated to the q_vectors. In addition if
4859 * NAPI is enabled it will delete any references to the NAPI struct prior
4860 * to freeing the q_vector.
4861 **/
4862static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4863{
207867f5 4864 int v_idx, num_q_vectors;
7a921c93 4865
91281fd3 4866 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4867 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4868 else
7a921c93 4869 num_q_vectors = 1;
7a921c93 4870
207867f5
AD		 4871 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4872 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4873 adapter->q_vector[v_idx] = NULL;
91281fd3 4874 netif_napi_del(&q_vector->napi);
207867f5 4875 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 4876 kfree(q_vector);
4877 }
4878}
4879
7b25cdba 4880static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4881{
4882 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4883 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4884 pci_disable_msix(adapter->pdev);
4885 kfree(adapter->msix_entries);
4886 adapter->msix_entries = NULL;
4887 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4888 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4889 pci_disable_msi(adapter->pdev);
4890 }
021230d4
AV		 4891}
4892
4893/**
4894 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4895 * @adapter: board private structure to initialize
4896 *
4897 * We determine which interrupt scheme to use based on...
4898 * - Kernel support (MSI, MSI-X)
4899 * - which can be user-defined (via MODULE_PARAM)
4900 * - Hardware queue count (num_*_queues)
4901 * - defined by miscellaneous hardware support/features (RSS, etc.)
4902 **/
2f90b865 4903int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4904{
4905 int err;
4906
4907 /* Number of supported queues */
847f53ff
BH		 4908 err = ixgbe_set_num_queues(adapter);
4909 if (err)
4910 return err;
021230d4 4911
021230d4
AV		 4912 err = ixgbe_set_interrupt_capability(adapter);
4913 if (err) {
849c4542 4914 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4915 goto err_set_interrupt;
9a799d71
AK		 4916 }
4917
7a921c93
AD		 4918 err = ixgbe_alloc_q_vectors(adapter);
4919 if (err) {
849c4542 4920 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4921 goto err_alloc_q_vectors;
4922 }
4923
4924 err = ixgbe_alloc_queues(adapter);
4925 if (err) {
849c4542 4926 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4927 goto err_alloc_queues;
4928 }
4929
849c4542 4930 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4931 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4932 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4933
4934 set_bit(__IXGBE_DOWN, &adapter->state);
4935
9a799d71 4936 return 0;
021230d4 4937
7a921c93
AD		 4938err_alloc_queues:
4939 ixgbe_free_q_vectors(adapter);
4940err_alloc_q_vectors:
4941 ixgbe_reset_interrupt_capability(adapter);
021230d4 4942err_set_interrupt:
7a921c93
AD		 4943 return err;
4944}
4945
4946/**
4947 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4948 * @adapter: board private structure to clear interrupt scheme on
4949 *
4950 * We go through and clear interrupt specific resources and reset the structure
4951 * to pre-load conditions
4952 **/
4953void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4954{
4a0b9ca0
PW		 4955 int i;
4956
4957 for (i = 0; i < adapter->num_tx_queues; i++) {
4958 kfree(adapter->tx_ring[i]);
4959 adapter->tx_ring[i] = NULL;
4960 }
4961 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4962 struct ixgbe_ring *ring = adapter->rx_ring[i];
4963
4964 /* ixgbe_get_stats64() might access this ring, we must wait
4965 * a grace period before freeing it.
4966 */
bcec8b65 4967 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4968 adapter->rx_ring[i] = NULL;
4969 }
7a921c93 4970
b8eb3a10
DS		 4971 adapter->num_tx_queues = 0;
4972 adapter->num_rx_queues = 0;
4973
7a921c93
AD		 4974 ixgbe_free_q_vectors(adapter);
4975 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4976}
4977
4978/**
4979 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4980 * @adapter: board private structure to initialize
4981 *
4982 * ixgbe_sw_init initializes the Adapter private data structure.
4983 * Fields are initialized based on PCI device information and
4984 * OS network device settings (MTU size).
4985 **/
4986static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4987{
4988 struct ixgbe_hw *hw = &adapter->hw;
4989 struct pci_dev *pdev = adapter->pdev;
021230d4 4990 unsigned int rss;
7a6b6f51 4991#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4992 int j;
4993 struct tc_configuration *tc;
4994#endif
021230d4 4995
c44ade9e
JB		 4996 /* PCI config space info */
4997
4998 hw->vendor_id = pdev->vendor;
4999 hw->device_id = pdev->device;
5000 hw->revision_id = pdev->revision;
5001 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5002 hw->subsystem_device_id = pdev->subsystem_device;
5003
021230d4
AV		 5004 /* Set capability flags */
5005 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5006 adapter->ring_feature[RING_F_RSS].indices = rss;
5007 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5008 switch (hw->mac.type) {
5009 case ixgbe_mac_82598EB:
bf069c97
DS		 5010 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5011 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5012 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 5013 break;
b93a2226 5014 case ixgbe_mac_X540:
4f51bf70
JK		 5015 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5016 case ixgbe_mac_82599EB:
e8e26350 5017 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5018 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5019 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5020 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5021 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5022 /* Flow Director hash filters enabled */
5023 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5024 adapter->atr_sample_rate = 20;
c4cf55e5 5025 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5026 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5027 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5028#ifdef IXGBE_FCOE
0d551589
YZ		 5029 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5030 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5031 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5032#ifdef CONFIG_IXGBE_DCB
6ee16520 5033 /* Default traffic class to use for FCoE */
56075a98 5034 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5035#endif
eacd73f7 5036#endif /* IXGBE_FCOE */
bd508178
AD		 5037 break;
5038 default:
5039 break;
f8212f97 5040 }
2f90b865 5041
1fc5f038
AD		 5042 /* n-tuple support exists, always init our spinlock */
5043 spin_lock_init(&adapter->fdir_perfect_lock);
5044
7a6b6f51 5045#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5046 switch (hw->mac.type) {
5047 case ixgbe_mac_X540:
5048 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5049 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5050 break;
5051 default:
5052 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5053 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5054 break;
5055 }
5056
2f90b865
AD		 5057 /* Configure DCB traffic classes */
5058 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5059 tc = &adapter->dcb_cfg.tc_config[j];
5060 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5061 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5062 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5063 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5064 tc->dcb_pfc = pfc_disabled;
5065 }
4de2a022
JF		 5066
5067 /* Initialize default user to priority mapping, UPx->TC0 */
5068 tc = &adapter->dcb_cfg.tc_config[0];
5069 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5070 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5071
2f90b865
AD		 5072 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5073 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5074 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5075 adapter->dcb_set_bitmap = 0x00;
3032309b 5076 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5077 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5078 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5079
5080#endif
9a799d71
AK		 5081
5082 /* default flow control settings */
cd7664f6 5083 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5084 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5085#ifdef CONFIG_DCB
5086 adapter->last_lfc_mode = hw->fc.current_mode;
5087#endif
9da712d2 5088 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5089 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5090 hw->fc.send_xon = true;
71fd570b 5091 hw->fc.disable_fc_autoneg = false;
9a799d71 5092
30efa5a3 5093 /* enable itr by default in dynamic mode */
f7554a2b 5094 adapter->rx_itr_setting = 1;
f7554a2b 5095 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5096
5097 /* set defaults for eitr in MegaBytes */
5098 adapter->eitr_low = 10;
5099 adapter->eitr_high = 20;
5100
5101 /* set default ring sizes */
5102 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5103 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5104
bd198058 5105 /* set default work limits */
59224555 5106 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5107
9a799d71 5108 /* initialize eeprom parameters */
c44ade9e 5109 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5110 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5111 return -EIO;
5112 }
5113
021230d4 5114 /* enable rx csum by default */
9a799d71
AK		 5115 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5116
1a6c14a2
JB		 5117 /* get assigned NUMA node */
5118 adapter->node = dev_to_node(&pdev->dev);
5119
9a799d71
AK		 5120 set_bit(__IXGBE_DOWN, &adapter->state);
5121
5122 return 0;
5123}
5124
5125/**
5126 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5127 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5128 *
5129 * Return 0 on success, negative on failure
5130 **/
b6ec895e 5131int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5132{
b6ec895e 5133 struct device *dev = tx_ring->dev;
9a799d71
AK		 5134 int size;
5135
3a581073 5136 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5137 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5138 if (!tx_ring->tx_buffer_info)
89bf67f1 5139 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5140 if (!tx_ring->tx_buffer_info)
5141 goto err;
9a799d71
AK		 5142
5143 /* round up to nearest 4K */
12207e49 5144 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5145 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5146
b6ec895e 5147 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5148 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5149 if (!tx_ring->desc)
5150 goto err;
9a799d71 5151
3a581073
JB		 5152 tx_ring->next_to_use = 0;
5153 tx_ring->next_to_clean = 0;
9a799d71 5154 return 0;
e01c31a5
JB		 5155
5156err:
5157 vfree(tx_ring->tx_buffer_info);
5158 tx_ring->tx_buffer_info = NULL;
b6ec895e 5159 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5160 return -ENOMEM;
9a799d71
AK		 5161}
5162
69888674
AD		 5163/**
5164 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5165 * @adapter: board private structure
5166 *
5167 * If this function returns with an error, then it's possible one or
5168 * more of the rings is populated (while the rest are not). It is the
5169 * callers duty to clean those orphaned rings.
5170 *
5171 * Return 0 on success, negative on failure
5172 **/
5173static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5174{
5175 int i, err = 0;
5176
5177 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5178 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5179 if (!err)
5180 continue;
396e799c 5181 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5182 break;
5183 }
5184
5185 return err;
5186}
5187
9a799d71
AK		 5188/**
5189 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5190 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5191 *
5192 * Returns 0 on success, negative on failure
5193 **/
b6ec895e 5194int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5195{
b6ec895e 5196 struct device *dev = rx_ring->dev;
021230d4 5197 int size;
9a799d71 5198
3a581073 5199 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5200 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5201 if (!rx_ring->rx_buffer_info)
89bf67f1 5202 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5203 if (!rx_ring->rx_buffer_info)
5204 goto err;
9a799d71 5205
9a799d71 5206 /* Round up to nearest 4K */
3a581073
JB		 5207 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5208 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5209
b6ec895e 5210 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5211 &rx_ring->dma, GFP_KERNEL);
9a799d71 5212
b6ec895e
AD		 5213 if (!rx_ring->desc)
5214 goto err;
9a799d71 5215
3a581073
JB		 5216 rx_ring->next_to_clean = 0;
5217 rx_ring->next_to_use = 0;
9a799d71
AK		 5218
5219 return 0;
b6ec895e
AD		 5220err:
5221 vfree(rx_ring->rx_buffer_info);
5222 rx_ring->rx_buffer_info = NULL;
5223 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5224 return -ENOMEM;
9a799d71
AK		 5225}
5226
69888674
AD		 5227/**
5228 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5229 * @adapter: board private structure
5230 *
5231 * If this function returns with an error, then it's possible one or
5232 * more of the rings is populated (while the rest are not). It is the
5233 * callers duty to clean those orphaned rings.
5234 *
5235 * Return 0 on success, negative on failure
5236 **/
69888674
AD		 5237static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5238{
5239 int i, err = 0;
5240
5241 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5242 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5243 if (!err)
5244 continue;
396e799c 5245 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5246 break;
5247 }
5248
5249 return err;
5250}
5251
9a799d71
AK		 5252/**
5253 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5254 * @tx_ring: Tx descriptor ring for a specific queue
5255 *
5256 * Free all transmit software resources
5257 **/
b6ec895e 5258void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5259{
b6ec895e 5260 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5261
5262 vfree(tx_ring->tx_buffer_info);
5263 tx_ring->tx_buffer_info = NULL;
5264
b6ec895e
AD		 5265 /* if not set, then don't free */
5266 if (!tx_ring->desc)
5267 return;
5268
5269 dma_free_coherent(tx_ring->dev, tx_ring->size,
5270 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5271
5272 tx_ring->desc = NULL;
5273}
5274
5275/**
5276 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5277 * @adapter: board private structure
5278 *
5279 * Free all transmit software resources
5280 **/
5281static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5282{
5283 int i;
5284
5285 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5286 if (adapter->tx_ring[i]->desc)
b6ec895e 5287 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5288}
5289
5290/**
b4617240 5291 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5292 * @rx_ring: ring to clean the resources from
5293 *
5294 * Free all receive software resources
5295 **/
b6ec895e 5296void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5297{
b6ec895e 5298 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5299
5300 vfree(rx_ring->rx_buffer_info);
5301 rx_ring->rx_buffer_info = NULL;
5302
b6ec895e
AD		 5303 /* if not set, then don't free */
5304 if (!rx_ring->desc)
5305 return;
5306
5307 dma_free_coherent(rx_ring->dev, rx_ring->size,
5308 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5309
5310 rx_ring->desc = NULL;
5311}
5312
5313/**
5314 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5315 * @adapter: board private structure
5316 *
5317 * Free all receive software resources
5318 **/
5319static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5320{
5321 int i;
5322
5323 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5324 if (adapter->rx_ring[i]->desc)
b6ec895e 5325 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5326}
5327
9a799d71
AK		 5328/**
5329 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5330 * @netdev: network interface device structure
5331 * @new_mtu: new value for maximum frame size
5332 *
5333 * Returns 0 on success, negative on failure
5334 **/
5335static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5336{
5337 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5338 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5339 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5340
42c783c5 5341 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5342 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5343 hw->mac.type != ixgbe_mac_X540) {
5344 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5345 return -EINVAL;
5346 } else {
5347 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5348 return -EINVAL;
5349 }
9a799d71 5350
396e799c 5351 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5352 /* must set new MTU before calling down or up */
9a799d71
AK		 5353 netdev->mtu = new_mtu;
5354
d4f80882
AV		 5355 if (netif_running(netdev))
5356 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5357
5358 return 0;
5359}
5360
5361/**
5362 * ixgbe_open - Called when a network interface is made active
5363 * @netdev: network interface device structure
5364 *
5365 * Returns 0 on success, negative value on failure
5366 *
5367 * The open entry point is called when a network interface is made
5368 * active by the system (IFF_UP). At this point all resources needed
5369 * for transmit and receive operations are allocated, the interrupt
5370 * handler is registered with the OS, the watchdog timer is started,
5371 * and the stack is notified that the interface is ready.
5372 **/
5373static int ixgbe_open(struct net_device *netdev)
5374{
5375 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5376 int err;
4bebfaa5
AK		 5377
5378 /* disallow open during test */
5379 if (test_bit(__IXGBE_TESTING, &adapter->state))
5380 return -EBUSY;
9a799d71 5381
54386467
JB		 5382 netif_carrier_off(netdev);
5383
9a799d71
AK		 5384 /* allocate transmit descriptors */
5385 err = ixgbe_setup_all_tx_resources(adapter);
5386 if (err)
5387 goto err_setup_tx;
5388
9a799d71
AK		 5389 /* allocate receive descriptors */
5390 err = ixgbe_setup_all_rx_resources(adapter);
5391 if (err)
5392 goto err_setup_rx;
5393
5394 ixgbe_configure(adapter);
5395
021230d4 5396 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5397 if (err)
5398 goto err_req_irq;
5399
c7ccde0f 5400 ixgbe_up_complete(adapter);
9a799d71
AK		 5401
5402 return 0;
5403
9a799d71 5404err_req_irq:
9a799d71 5405err_setup_rx:
a20a1199 5406 ixgbe_free_all_rx_resources(adapter);
9a799d71 5407err_setup_tx:
a20a1199 5408 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5409 ixgbe_reset(adapter);
5410
5411 return err;
5412}
5413
5414/**
5415 * ixgbe_close - Disables a network interface
5416 * @netdev: network interface device structure
5417 *
5418 * Returns 0, this is not allowed to fail
5419 *
5420 * The close entry point is called when an interface is de-activated
5421 * by the OS. The hardware is still under the drivers control, but
5422 * needs to be disabled. A global MAC reset is issued to stop the
5423 * hardware, and all transmit and receive resources are freed.
5424 **/
5425static int ixgbe_close(struct net_device *netdev)
5426{
5427 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5428
5429 ixgbe_down(adapter);
5430 ixgbe_free_irq(adapter);
5431
e4911d57
AD		 5432 ixgbe_fdir_filter_exit(adapter);
5433
9a799d71
AK		 5434 ixgbe_free_all_tx_resources(adapter);
5435 ixgbe_free_all_rx_resources(adapter);
5436
5eba3699 5437 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5438
5439 return 0;
5440}
5441
b3c8b4ba
AD		 5442#ifdef CONFIG_PM
5443static int ixgbe_resume(struct pci_dev *pdev)
5444{
c60fbb00
AD		 5445 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5446 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5447 u32 err;
5448
5449 pci_set_power_state(pdev, PCI_D0);
5450 pci_restore_state(pdev);
656ab817
DS		 5451 /*
5452 * pci_restore_state clears dev->state_saved so call
5453 * pci_save_state to restore it.
5454 */
5455 pci_save_state(pdev);
9ce77666 5456
5457 err = pci_enable_device_mem(pdev);
b3c8b4ba 5458 if (err) {
849c4542 5459 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5460 return err;
5461 }
5462 pci_set_master(pdev);
5463
dd4d8ca6 5464 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5465
5466 err = ixgbe_init_interrupt_scheme(adapter);
5467 if (err) {
849c4542 5468 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5469 return err;
5470 }
5471
b3c8b4ba
AD		 5472 ixgbe_reset(adapter);
5473
495dce12
WJP		 5474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5475
b3c8b4ba 5476 if (netif_running(netdev)) {
c60fbb00 5477 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5478 if (err)
5479 return err;
5480 }
5481
5482 netif_device_attach(netdev);
5483
5484 return 0;
5485}
b3c8b4ba 5486#endif /* CONFIG_PM */
9d8d05ae
RW		 5487
5488static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5489{
c60fbb00
AD		 5490 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5491 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5492 struct ixgbe_hw *hw = &adapter->hw;
5493 u32 ctrl, fctrl;
5494 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5495#ifdef CONFIG_PM
5496 int retval = 0;
5497#endif
5498
5499 netif_device_detach(netdev);
5500
5501 if (netif_running(netdev)) {
5502 ixgbe_down(adapter);
5503 ixgbe_free_irq(adapter);
5504 ixgbe_free_all_tx_resources(adapter);
5505 ixgbe_free_all_rx_resources(adapter);
5506 }
b3c8b4ba 5507
5f5ae6fc 5508 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5509#ifdef CONFIG_DCB
5510 kfree(adapter->ixgbe_ieee_pfc);
5511 kfree(adapter->ixgbe_ieee_ets);
5512#endif
5f5ae6fc 5513
b3c8b4ba
AD		 5514#ifdef CONFIG_PM
5515 retval = pci_save_state(pdev);
5516 if (retval)
5517 return retval;
4df10466 5518
b3c8b4ba 5519#endif
e8e26350
PW		 5520 if (wufc) {
5521 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5522
e8e26350
PW		 5523 /* turn on all-multi mode if wake on multicast is enabled */
5524 if (wufc & IXGBE_WUFC_MC) {
5525 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5526 fctrl |= IXGBE_FCTRL_MPE;
5527 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5528 }
5529
5530 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5531 ctrl |= IXGBE_CTRL_GIO_DIS;
5532 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5533
5534 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5535 } else {
5536 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5537 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5538 }
5539
bd508178
AD		 5540 switch (hw->mac.type) {
5541 case ixgbe_mac_82598EB:
dd4d8ca6 5542 pci_wake_from_d3(pdev, false);
bd508178
AD		 5543 break;
5544 case ixgbe_mac_82599EB:
b93a2226 5545 case ixgbe_mac_X540:
bd508178
AD		 5546 pci_wake_from_d3(pdev, !!wufc);
5547 break;
5548 default:
5549 break;
5550 }
b3c8b4ba 5551
9d8d05ae
RW		 5552 *enable_wake = !!wufc;
5553
b3c8b4ba
AD		 5554 ixgbe_release_hw_control(adapter);
5555
5556 pci_disable_device(pdev);
5557
9d8d05ae
RW		 5558 return 0;
5559}
5560
5561#ifdef CONFIG_PM
5562static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5563{
5564 int retval;
5565 bool wake;
5566
5567 retval = __ixgbe_shutdown(pdev, &wake);
5568 if (retval)
5569 return retval;
5570
5571 if (wake) {
5572 pci_prepare_to_sleep(pdev);
5573 } else {
5574 pci_wake_from_d3(pdev, false);
5575 pci_set_power_state(pdev, PCI_D3hot);
5576 }
b3c8b4ba
AD		 5577
5578 return 0;
5579}
9d8d05ae 5580#endif /* CONFIG_PM */
b3c8b4ba
AD		 5581
5582static void ixgbe_shutdown(struct pci_dev *pdev)
5583{
9d8d05ae
RW		 5584 bool wake;
5585
5586 __ixgbe_shutdown(pdev, &wake);
5587
5588 if (system_state == SYSTEM_POWER_OFF) {
5589 pci_wake_from_d3(pdev, wake);
5590 pci_set_power_state(pdev, PCI_D3hot);
5591 }
b3c8b4ba
AD		 5592}
5593
9a799d71
AK		 5594/**
5595 * ixgbe_update_stats - Update the board statistics counters.
5596 * @adapter: board private structure
5597 **/
5598void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5599{
2d86f139 5600 struct net_device *netdev = adapter->netdev;
9a799d71 5601 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5602 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5603 u64 total_mpc = 0;
5604 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5605 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5606 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5607 u64 bytes = 0, packets = 0;
7b859ebc
AH		 5608#ifdef IXGBE_FCOE
5609 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5610 unsigned int cpu;
5611 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5612#endif /* IXGBE_FCOE */
9a799d71 5613
d08935c2
DS		 5614 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5615 test_bit(__IXGBE_RESETTING, &adapter->state))
5616 return;
5617
94b982b2 5618 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5619 u64 rsc_count = 0;
94b982b2 5620 u64 rsc_flush = 0;
d51019a4
PW		 5621 for (i = 0; i < 16; i++)
5622 adapter->hw_rx_no_dma_resources +=
7ca647bd 5623 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5624 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5625 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5626 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5627 }
5628 adapter->rsc_total_count = rsc_count;
5629 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5630 }
5631
5b7da515
AD		 5632 for (i = 0; i < adapter->num_rx_queues; i++) {
5633 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5634 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5635 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5636 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5637 bytes += rx_ring->stats.bytes;
5638 packets += rx_ring->stats.packets;
5639 }
5640 adapter->non_eop_descs = non_eop_descs;
5641 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5642 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5643 netdev->stats.rx_bytes = bytes;
5644 netdev->stats.rx_packets = packets;
5645
5646 bytes = 0;
5647 packets = 0;
7ca3bc58 5648 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5649 for (i = 0; i < adapter->num_tx_queues; i++) {
5650 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5651 restart_queue += tx_ring->tx_stats.restart_queue;
5652 tx_busy += tx_ring->tx_stats.tx_busy;
5653 bytes += tx_ring->stats.bytes;
5654 packets += tx_ring->stats.packets;
5655 }
eb985f09 5656 adapter->restart_queue = restart_queue;
5b7da515
AD		 5657 adapter->tx_busy = tx_busy;
5658 netdev->stats.tx_bytes = bytes;
5659 netdev->stats.tx_packets = packets;
7ca3bc58 5660
7ca647bd 5661 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5662
5663 /* 8 register reads */
6f11eef7
AV		 5664 for (i = 0; i < 8; i++) {
5665 /* for packet buffers not used, the register should read 0 */
5666 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5667 missed_rx += mpc;
7ca647bd
JP		 5668 hwstats->mpc[i] += mpc;
5669 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5670 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5671 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5672 switch (hw->mac.type) {
5673 case ixgbe_mac_82598EB:
1a70db4b
ET		 5674 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5675 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5676 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5677 hwstats->pxonrxc[i] +=
5678 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5679 break;
5680 case ixgbe_mac_82599EB:
b93a2226 5681 case ixgbe_mac_X540:
bd508178
AD		 5682 hwstats->pxonrxc[i] +=
5683 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5684 break;
5685 default:
5686 break;
e8e26350 5687 }
6f11eef7 5688 }
1a70db4b
ET		 5689
5690 /*16 register reads */
5691 for (i = 0; i < 16; i++) {
5692 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5693 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5694 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5695 (hw->mac.type == ixgbe_mac_X540)) {
5696 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5697 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5698 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5699 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5700 }
5701 }
5702
7ca647bd 5703 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5704 /* work around hardware counting issue */
7ca647bd 5705 hwstats->gprc -= missed_rx;
6f11eef7 5706
c84d324c
JF		 5707 ixgbe_update_xoff_received(adapter);
5708
6f11eef7 5709 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5710 switch (hw->mac.type) {
5711 case ixgbe_mac_82598EB:
5712 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5713 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5714 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5715 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5716 break;
b93a2226 5717 case ixgbe_mac_X540:
58f6bcf9
ET		 5718 /* OS2BMC stats are X540 only*/
5719 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5720 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5721 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5722 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5723 case ixgbe_mac_82599EB:
7ca647bd 5724 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5725 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5726 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5727 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5728 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5729 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5730 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5731 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5732 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5733#ifdef IXGBE_FCOE
7ca647bd
JP		 5734 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5735 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5736 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5737 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5738 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5739 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5740 /* Add up per cpu counters for total ddp aloc fail */
5741 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5742 for_each_possible_cpu(cpu) {
5743 fcoe_noddp_counts_sum +=
5744 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5745 fcoe_noddp_ext_buff_counts_sum +=
5746 *per_cpu_ptr(fcoe->
5747 pcpu_noddp_ext_buff, cpu);
5748 }
5749 }
5750 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5751 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5752#endif /* IXGBE_FCOE */
bd508178
AD		 5753 break;
5754 default:
5755 break;
e8e26350 5756 }
9a799d71 5757 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5758 hwstats->bprc += bprc;
5759 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5760 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5761 hwstats->mprc -= bprc;
5762 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5763 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5764 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5765 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5766 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5767 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5768 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5769 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5770 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5771 hwstats->lxontxc += lxon;
6f11eef7 5772 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5773 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5774 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5775 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5776 /*
5777 * 82598 errata - tx of flow control packets is included in tx counters
5778 */
5779 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5780 hwstats->gptc -= xon_off_tot;
5781 hwstats->mptc -= xon_off_tot;
5782 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5783 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5784 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5785 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5786 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5787 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5788 hwstats->ptc64 -= xon_off_tot;
5789 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5790 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5791 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5792 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5793 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5794 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5795
5796 /* Fill out the OS statistics structure */
7ca647bd 5797 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5798
5799 /* Rx Errors */
7ca647bd 5800 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5801 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5802 netdev->stats.rx_length_errors = hwstats->rlec;
5803 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5804 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5805}
5806
5807/**
d034acf1
AD		 5808 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5809 * @adapter - pointer to the device adapter structure
9a799d71 5810 **/
d034acf1 5811static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5812{
cf8280ee 5813 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5814 int i;
cf8280ee 5815
d034acf1
AD		 5816 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5817 return;
5818
5819 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5820
d034acf1 5821 /* if interface is down do nothing */
fe49f04a 5822 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5823 return;
5824
5825 /* do nothing if we are not using signature filters */
5826 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5827 return;
5828
5829 adapter->fdir_overflow++;
5830
93c52dd0
AD		 5831 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5832 for (i = 0; i < adapter->num_tx_queues; i++)
5833 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5834 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5835 /* re-enable flow director interrupts */
5836 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5837 } else {
5838 e_err(probe, "failed to finish FDIR re-initialization, "
5839 "ignored adding FDIR ATR filters\n");
5840 }
93c52dd0
AD		 5841}
5842
5843/**
5844 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5845 * @adapter - pointer to the device adapter structure
5846 *
5847 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5848 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5849 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5850 * determine if a hang has occurred.
93c52dd0
AD		 5851 */
5852static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5853{
cf8280ee 5854 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5855 u64 eics = 0;
5856 int i;
cf8280ee 5857
93c52dd0
AD		 5858 /* If we're down or resetting, just bail */
5859 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5860 test_bit(__IXGBE_RESETTING, &adapter->state))
5861 return;
22d5a71b 5862
93c52dd0
AD		 5863 /* Force detection of hung controller */
5864 if (netif_carrier_ok(adapter->netdev)) {
5865 for (i = 0; i < adapter->num_tx_queues; i++)
5866 set_check_for_tx_hang(adapter->tx_ring[i]);
5867 }
22d5a71b 5868
fe49f04a
AD		 5869 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5870 /*
5871 * for legacy and MSI interrupts don't set any bits
5872 * that are enabled for EIAM, because this operation
5873 * would set *both* EIMS and EICS for any bit in EIAM
5874 */
5875 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5876 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5877 } else {
5878 /* get one bit for every active tx/rx interrupt vector */
5879 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5880 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5881 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5882 eics |= ((u64)1 << i);
5883 }
cf8280ee 5884 }
9a799d71 5885
93c52dd0 5886 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5887 ixgbe_irq_rearm_queues(adapter, eics);
5888
cf8280ee
JB		 5889}
5890
e8e26350 5891/**
93c52dd0
AD		 5892 * ixgbe_watchdog_update_link - update the link status
5893 * @adapter - pointer to the device adapter structure
5894 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5895 **/
93c52dd0 5896static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5897{
e8e26350 5898 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5899 u32 link_speed = adapter->link_speed;
5900 bool link_up = adapter->link_up;
c4cf55e5 5901 int i;
e8e26350 5902
93c52dd0
AD		 5903 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5904 return;
5905
5906 if (hw->mac.ops.check_link) {
5907 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5908 } else {
93c52dd0
AD		 5909 /* always assume link is up, if no check link function */
5910 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5911 link_up = true;
c4cf55e5 5912 }
93c52dd0
AD		 5913 if (link_up) {
5914 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5915 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5916 hw->mac.ops.fc_enable(hw, i);
5917 } else {
5918 hw->mac.ops.fc_enable(hw, 0);
5919 }
5920 }
5921
5922 if (link_up ||
5923 time_after(jiffies, (adapter->link_check_timeout +
5924 IXGBE_TRY_LINK_TIMEOUT))) {
5925 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5926 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5927 IXGBE_WRITE_FLUSH(hw);
5928 }
5929
5930 adapter->link_up = link_up;
5931 adapter->link_speed = link_speed;
e8e26350
PW		 5932}
5933
5934/**
93c52dd0
AD		 5935 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5936 * print link up message
5937 * @adapter - pointer to the device adapter structure
e8e26350 5938 **/
93c52dd0 5939static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5940{
93c52dd0 5941 struct net_device *netdev = adapter->netdev;
e8e26350 5942 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5943 u32 link_speed = adapter->link_speed;
5944 bool flow_rx, flow_tx;
e8e26350 5945
93c52dd0
AD		 5946 /* only continue if link was previously down */
5947 if (netif_carrier_ok(netdev))
a985b6c3 5948 return;
63d6e1d8 5949
93c52dd0 5950 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5951
93c52dd0
AD		 5952 switch (hw->mac.type) {
5953 case ixgbe_mac_82598EB: {
5954 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5955 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5956 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5957 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5958 }
5959 break;
5960 case ixgbe_mac_X540:
5961 case ixgbe_mac_82599EB: {
5962 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5963 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5964 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5965 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5966 }
5967 break;
5968 default:
5969 flow_tx = false;
5970 flow_rx = false;
5971 break;
e8e26350 5972 }
93c52dd0
AD		 5973 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5974 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5975 "10 Gbps" :
5976 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5977 "1 Gbps" :
5978 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5979 "100 Mbps" :
5980 "unknown speed"))),
5981 ((flow_rx && flow_tx) ? "RX/TX" :
5982 (flow_rx ? "RX" :
5983 (flow_tx ? "TX" : "None"))));
e8e26350 5984
93c52dd0 5985 netif_carrier_on(netdev);
93c52dd0 5986 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5987}
5988
c4cf55e5 5989/**
93c52dd0
AD		 5990 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5991 * print link down message
5992 * @adapter - pointer to the adapter structure
c4cf55e5 5993 **/
93c52dd0 5994static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5995{
cf8280ee 5996 struct net_device *netdev = adapter->netdev;
c4cf55e5 5997 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5998
93c52dd0
AD		 5999 adapter->link_up = false;
6000 adapter->link_speed = 0;
cf8280ee 6001
93c52dd0
AD		 6002 /* only continue if link was up previously */
6003 if (!netif_carrier_ok(netdev))
6004 return;
264857b8 6005
93c52dd0
AD		 6006 /* poll for SFP+ cable when link is down */
6007 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6008 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6009
93c52dd0
AD		 6010 e_info(drv, "NIC Link is Down\n");
6011 netif_carrier_off(netdev);
6012}
e8e26350 6013
93c52dd0
AD		 6014/**
6015 * ixgbe_watchdog_flush_tx - flush queues on link down
6016 * @adapter - pointer to the device adapter structure
6017 **/
6018static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6019{
c4cf55e5 6020 int i;
93c52dd0 6021 int some_tx_pending = 0;
c4cf55e5 6022
93c52dd0 6023 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6024 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6025 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6026 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6027 some_tx_pending = 1;
6028 break;
6029 }
6030 }
6031
6032 if (some_tx_pending) {
6033 /* We've lost link, so the controller stops DMA,
6034 * but we've got queued Tx work that's never going
6035 * to get done, so reset controller to flush Tx.
6036 * (Do the reset outside of interrupt context).
6037 */
c83c6cbd 6038 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6039 }
c4cf55e5 6040 }
c4cf55e5
PWJ		 6041}
6042
a985b6c3
GR		 6043static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6044{
6045 u32 ssvpc;
6046
6047 /* Do not perform spoof check for 82598 */
6048 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6049 return;
6050
6051 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6052
6053 /*
6054 * ssvpc register is cleared on read, if zero then no
6055 * spoofed packets in the last interval.
6056 */
6057 if (!ssvpc)
6058 return;
6059
6060 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6061}
6062
93c52dd0
AD		 6063/**
6064 * ixgbe_watchdog_subtask - check and bring link up
6065 * @adapter - pointer to the device adapter structure
6066 **/
6067static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6068{
6069 /* if interface is down do nothing */
7edebf9a
ET		 6070 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6071 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6072 return;
6073
6074 ixgbe_watchdog_update_link(adapter);
6075
6076 if (adapter->link_up)
6077 ixgbe_watchdog_link_is_up(adapter);
6078 else
6079 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6080
a985b6c3 6081 ixgbe_spoof_check(adapter);
9a799d71 6082 ixgbe_update_stats(adapter);
93c52dd0
AD		 6083
6084 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6085}
10eec955 6086
cf8280ee 6087/**
7086400d
AD		 6088 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6089 * @adapter - the ixgbe adapter structure
cf8280ee 6090 **/
7086400d 6091static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6092{
cf8280ee 6093 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6094 s32 err;
cf8280ee 6095
7086400d
AD		 6096 /* not searching for SFP so there is nothing to do here */
6097 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6098 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6099 return;
10eec955 6100
7086400d
AD		 6101 /* someone else is in init, wait until next service event */
6102 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6103 return;
cf8280ee 6104
7086400d
AD		 6105 err = hw->phy.ops.identify_sfp(hw);
6106 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6107 goto sfp_out;
264857b8 6108
7086400d
AD		 6109 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6110 /* If no cable is present, then we need to reset
6111 * the next time we find a good cable. */
6112 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6113 }
9a799d71 6114
7086400d
AD		 6115 /* exit on error */
6116 if (err)
6117 goto sfp_out;
e8e26350 6118
7086400d
AD		 6119 /* exit if reset not needed */
6120 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6121 goto sfp_out;
9a799d71 6122
7086400d 6123 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6124
7086400d
AD		 6125 /*
6126 * A module may be identified correctly, but the EEPROM may not have
6127 * support for that module. setup_sfp() will fail in that case, so
6128 * we should not allow that module to load.
6129 */
6130 if (hw->mac.type == ixgbe_mac_82598EB)
6131 err = hw->phy.ops.reset(hw);
6132 else
6133 err = hw->mac.ops.setup_sfp(hw);
6134
6135 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6136 goto sfp_out;
6137
6138 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6139 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6140
6141sfp_out:
6142 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6143
6144 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6145 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6146 e_dev_err("failed to initialize because an unsupported "
6147 "SFP+ module type was detected.\n");
6148 e_dev_err("Reload the driver after installing a "
6149 "supported module.\n");
6150 unregister_netdev(adapter->netdev);
bc59fcda 6151 }
7086400d 6152}
bc59fcda 6153
7086400d
AD		 6154/**
6155 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6156 * @adapter - the ixgbe adapter structure
6157 **/
6158static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6159{
6160 struct ixgbe_hw *hw = &adapter->hw;
6161 u32 autoneg;
6162 bool negotiation;
6163
6164 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6165 return;
6166
6167 /* someone else is in init, wait until next service event */
6168 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6169 return;
6170
6171 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6172
6173 autoneg = hw->phy.autoneg_advertised;
6174 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6175 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6176 if (hw->mac.ops.setup_link)
6177 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6178
6179 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6180 adapter->link_check_timeout = jiffies;
6181 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6182}
6183
83c61fa9
GR		 6184#ifdef CONFIG_PCI_IOV
6185static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6186{
6187 int vf;
6188 struct ixgbe_hw *hw = &adapter->hw;
6189 struct net_device *netdev = adapter->netdev;
6190 u32 gpc;
6191 u32 ciaa, ciad;
6192
6193 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6194 if (gpc) /* If incrementing then no need for the check below */
6195 return;
6196 /*
6197 * Check to see if a bad DMA write target from an errant or
6198 * malicious VF has caused a PCIe error. If so then we can
6199 * issue a VFLR to the offending VF(s) and then resume without
6200 * requesting a full slot reset.
6201 */
6202
6203 for (vf = 0; vf < adapter->num_vfs; vf++) {
6204 ciaa = (vf << 16) | 0x80000000;
6205 /* 32 bit read so align, we really want status at offset 6 */
6206 ciaa |= PCI_COMMAND;
6207 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6208 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6209 ciaa &= 0x7FFFFFFF;
6210 /* disable debug mode asap after reading data */
6211 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6212 /* Get the upper 16 bits which will be the PCI status reg */
6213 ciad >>= 16;
6214 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6215 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6216 /* Issue VFLR */
6217 ciaa = (vf << 16) | 0x80000000;
6218 ciaa |= 0xA8;
6219 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6220 ciad = 0x00008000; /* VFLR */
6221 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6222 ciaa &= 0x7FFFFFFF;
6223 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6224 }
6225 }
6226}
6227
6228#endif
7086400d
AD		 6229/**
6230 * ixgbe_service_timer - Timer Call-back
6231 * @data: pointer to adapter cast into an unsigned long
6232 **/
6233static void ixgbe_service_timer(unsigned long data)
6234{
6235 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6236 unsigned long next_event_offset;
83c61fa9 6237 bool ready = true;
7086400d 6238
83c61fa9
GR		 6239#ifdef CONFIG_PCI_IOV
6240 ready = false;
6241
6242 /*
6243 * don't bother with SR-IOV VF DMA hang check if there are
6244 * no VFs or the link is down
6245 */
6246 if (!adapter->num_vfs ||
6247 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6248 ready = true;
6249 goto normal_timer_service;
6250 }
6251
6252 /* If we have VFs allocated then we must check for DMA hangs */
6253 ixgbe_check_for_bad_vf(adapter);
6254 next_event_offset = HZ / 50;
6255 adapter->timer_event_accumulator++;
6256
6257 if (adapter->timer_event_accumulator >= 100) {
6258 ready = true;
6259 adapter->timer_event_accumulator = 0;
6260 }
6261
6262 goto schedule_event;
6263
6264normal_timer_service:
6265#endif
7086400d
AD		 6266 /* poll faster when waiting for link */
6267 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6268 next_event_offset = HZ / 10;
6269 else
6270 next_event_offset = HZ * 2;
6271
83c61fa9
GR		 6272#ifdef CONFIG_PCI_IOV
6273schedule_event:
6274#endif
7086400d
AD		 6275 /* Reset the timer */
6276 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6277
83c61fa9
GR		 6278 if (ready)
6279 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6280}
6281
c83c6cbd
AD		 6282static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6283{
6284 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6285 return;
6286
6287 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6288
6289 /* If we're already down or resetting, just bail */
6290 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6291 test_bit(__IXGBE_RESETTING, &adapter->state))
6292 return;
6293
6294 ixgbe_dump(adapter);
6295 netdev_err(adapter->netdev, "Reset adapter\n");
6296 adapter->tx_timeout_count++;
6297
6298 ixgbe_reinit_locked(adapter);
6299}
6300
7086400d
AD		 6301/**
6302 * ixgbe_service_task - manages and runs subtasks
6303 * @work: pointer to work_struct containing our data
6304 **/
6305static void ixgbe_service_task(struct work_struct *work)
6306{
6307 struct ixgbe_adapter *adapter = container_of(work,
6308 struct ixgbe_adapter,
6309 service_task);
6310
c83c6cbd 6311 ixgbe_reset_subtask(adapter);
7086400d
AD		 6312 ixgbe_sfp_detection_subtask(adapter);
6313 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6314 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6315 ixgbe_watchdog_subtask(adapter);
d034acf1 6316 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6317 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6318
6319 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6320}
6321
897ab156
AD		 6322void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6323 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6324{
6325 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6326 u16 i = tx_ring->next_to_use;
9a799d71 6327
897ab156 6328 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6329
897ab156
AD		 6330 i++;
6331 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6332
897ab156
AD		 6333 /* set bits to identify this as an advanced context descriptor */
6334 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6335
897ab156
AD		 6336 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6337 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6338 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6339 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6340}
9a799d71 6341
897ab156
AD		 6342static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6343 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6344{
6345 int err;
6346 u32 vlan_macip_lens, type_tucmd;
6347 u32 mss_l4len_idx, l4len;
9a799d71 6348
897ab156
AD		 6349 if (!skb_is_gso(skb))
6350 return 0;
9a799d71 6351
897ab156
AD		 6352 if (skb_header_cloned(skb)) {
6353 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6354 if (err)
6355 return err;
9a799d71 6356 }
9a799d71 6357
897ab156
AD		 6358 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6359 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6360
6361 if (protocol == __constant_htons(ETH_P_IP)) {
6362 struct iphdr *iph = ip_hdr(skb);
6363 iph->tot_len = 0;
6364 iph->check = 0;
6365 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6366 iph->daddr, 0,
6367 IPPROTO_TCP,
6368 0);
6369 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6370 } else if (skb_is_gso_v6(skb)) {
6371 ipv6_hdr(skb)->payload_len = 0;
6372 tcp_hdr(skb)->check =
6373 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6374 &ipv6_hdr(skb)->daddr,
6375 0, IPPROTO_TCP, 0);
6376 }
6377
6378 l4len = tcp_hdrlen(skb);
6379 *hdr_len = skb_transport_offset(skb) + l4len;
6380
6381 /* mss_l4len_id: use 1 as index for TSO */
6382 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6383 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6384 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6385
6386 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6387 vlan_macip_lens = skb_network_header_len(skb);
6388 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6389 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6390
6391 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6392 mss_l4len_idx);
6393
6394 return 1;
6395}
6396
6397static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6398 struct sk_buff *skb, u32 tx_flags,
6399 __be16 protocol)
7ca647bd 6400{
897ab156
AD		 6401 u32 vlan_macip_lens = 0;
6402 u32 mss_l4len_idx = 0;
6403 u32 type_tucmd = 0;
7ca647bd 6404
897ab156 6405 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6406 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6407 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6408 return false;
6409 } else {
6410 u8 l4_hdr = 0;
6411 switch (protocol) {
6412 case __constant_htons(ETH_P_IP):
6413 vlan_macip_lens |= skb_network_header_len(skb);
6414 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6415 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6416 break;
897ab156
AD		 6417 case __constant_htons(ETH_P_IPV6):
6418 vlan_macip_lens |= skb_network_header_len(skb);
6419 l4_hdr = ipv6_hdr(skb)->nexthdr;
6420 break;
6421 default:
6422 if (unlikely(net_ratelimit())) {
6423 dev_warn(tx_ring->dev,
6424 "partial checksum but proto=%x!\n",
6425 skb->protocol);
6426 }
7ca647bd
JP		 6427 break;
6428 }
897ab156
AD		 6429
6430 switch (l4_hdr) {
7ca647bd 6431 case IPPROTO_TCP:
897ab156
AD		 6432 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6433 mss_l4len_idx = tcp_hdrlen(skb) <<
6434 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6435 break;
6436 case IPPROTO_SCTP:
897ab156
AD		 6437 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6438 mss_l4len_idx = sizeof(struct sctphdr) <<
6439 IXGBE_ADVTXD_L4LEN_SHIFT;
6440 break;
6441 case IPPROTO_UDP:
6442 mss_l4len_idx = sizeof(struct udphdr) <<
6443 IXGBE_ADVTXD_L4LEN_SHIFT;
6444 break;
6445 default:
6446 if (unlikely(net_ratelimit())) {
6447 dev_warn(tx_ring->dev,
6448 "partial checksum but l4 proto=%x!\n",
6449 skb->protocol);
6450 }
7ca647bd
JP		 6451 break;
6452 }
7ca647bd
JP		 6453 }
6454
897ab156
AD		 6455 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6456 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6457
897ab156
AD		 6458 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6459 type_tucmd, mss_l4len_idx);
9a799d71 6460
897ab156 6461 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6462}
6463
d3d00239 6464static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6465{
d3d00239
AD		 6466 /* set type for advanced descriptor with frame checksum insertion */
6467 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6468 IXGBE_ADVTXD_DCMD_IFCS |
6469 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6470
d3d00239 6471 /* set HW vlan bit if vlan is present */
66f32a8b 6472 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6473 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6474
d3d00239
AD		 6475 /* set segmentation enable bits for TSO/FSO */
6476#ifdef IXGBE_FCOE
6477 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6478#else
6479 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6480#endif
6481 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6482
d3d00239
AD		 6483 return cmd_type;
6484}
9a799d71 6485
d3d00239
AD		 6486static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6487{
6488 __le32 olinfo_status =
6489 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6490
d3d00239
AD		 6491 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6492 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6493 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6494 /* enble IPv4 checksum for TSO */
6495 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6496 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6497 }
6498
d3d00239
AD		 6499 /* enable L4 checksum for TSO and TX checksum offload */
6500 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6501 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6502
d3d00239
AD		 6503#ifdef IXGBE_FCOE
6504 /* use index 1 context for FCOE/FSO */
6505 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6506 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6507 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6508
d3d00239 6509#endif
7f9643fd
AD		 6510 /*
6511 * Check Context must be set if Tx switch is enabled, which it
6512 * always is for case where virtual functions are running
6513 */
6514 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6515 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6516
d3d00239
AD		 6517 return olinfo_status;
6518}
44df32c5 6519
d3d00239
AD		 6520#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6521 IXGBE_TXD_CMD_RS)
6522
6523static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6524 struct sk_buff *skb,
6525 struct ixgbe_tx_buffer *first,
6526 u32 tx_flags,
6527 const u8 hdr_len)
6528{
6529 struct device *dev = tx_ring->dev;
6530 struct ixgbe_tx_buffer *tx_buffer_info;
6531 union ixgbe_adv_tx_desc *tx_desc;
6532 dma_addr_t dma;
6533 __le32 cmd_type, olinfo_status;
6534 struct skb_frag_struct *frag;
6535 unsigned int f = 0;
6536 unsigned int data_len = skb->data_len;
6537 unsigned int size = skb_headlen(skb);
6538 u32 offset = 0;
6539 u32 paylen = skb->len - hdr_len;
6540 u16 i = tx_ring->next_to_use;
6541 u16 gso_segs;
6542
6543#ifdef IXGBE_FCOE
6544 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6545 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6546 data_len -= sizeof(struct fcoe_crc_eof);
6547 } else {
6548 size -= sizeof(struct fcoe_crc_eof) - data_len;
6549 data_len = 0;
9a799d71
AK		 6550 }
6551 }
44df32c5 6552
d3d00239
AD		 6553#endif
6554 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6555 if (dma_mapping_error(dev, dma))
6556 goto dma_error;
8ad494b0 6557
d3d00239
AD		 6558 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6559 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6560
d3d00239 6561 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6562
d3d00239
AD		 6563 for (;;) {
6564 while (size > IXGBE_MAX_DATA_PER_TXD) {
6565 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6566 tx_desc->read.cmd_type_len =
6567 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6568 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6569
d3d00239
AD		 6570 offset += IXGBE_MAX_DATA_PER_TXD;
6571 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6572
d3d00239
AD		 6573 tx_desc++;
6574 i++;
6575 if (i == tx_ring->count) {
6576 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6577 i = 0;
6578 }
6579 }
e5a43549 6580
e5a43549 6581 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6582 tx_buffer_info->length = offset + size;
6583 tx_buffer_info->tx_flags = tx_flags;
6584 tx_buffer_info->dma = dma;
9a799d71 6585
d3d00239
AD		 6586 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6587 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6588 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6589
d3d00239
AD		 6590 if (!data_len)
6591 break;
9a799d71 6592
d3d00239
AD		 6593 frag = &skb_shinfo(skb)->frags[f];
6594#ifdef IXGBE_FCOE
9e903e08 6595 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6596#else
9e903e08 6597 size = skb_frag_size(frag);
d3d00239
AD		 6598#endif
6599 data_len -= size;
6600 f++;
9a799d71 6601
d3d00239
AD		 6602 offset = 0;
6603 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6604
877749bf 6605 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6606 if (dma_mapping_error(dev, dma))
6607 goto dma_error;
9a799d71 6608
d3d00239
AD		 6609 tx_desc++;
6610 i++;
6611 if (i == tx_ring->count) {
6612 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6613 i = 0;
6614 }
6615 }
9a799d71 6616
d3d00239 6617 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6618
d3d00239
AD		 6619 i++;
6620 if (i == tx_ring->count)
6621 i = 0;
9a799d71 6622
d3d00239 6623 tx_ring->next_to_use = i;
eacd73f7 6624
d3d00239
AD		 6625 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6626 gso_segs = skb_shinfo(skb)->gso_segs;
6627#ifdef IXGBE_FCOE
6628 /* adjust for FCoE Sequence Offload */
6629 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6630 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6631 skb_shinfo(skb)->gso_size);
6632#endif /* IXGBE_FCOE */
6633 else
6634 gso_segs = 1;
9a799d71 6635
d3d00239
AD		 6636 /* multiply data chunks by size of headers */
6637 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6638 tx_buffer_info->gso_segs = gso_segs;
6639 tx_buffer_info->skb = skb;
9a799d71 6640
d3d00239
AD		 6641 /* set the timestamp */
6642 first->time_stamp = jiffies;
9a799d71
AK		 6643
6644 /*
6645 * Force memory writes to complete before letting h/w
6646 * know there are new descriptors to fetch. (Only
6647 * applicable for weak-ordered memory model archs,
6648 * such as IA-64).
6649 */
6650 wmb();
6651
d3d00239
AD		 6652 /* set next_to_watch value indicating a packet is present */
6653 first->next_to_watch = tx_desc;
6654
6655 /* notify HW of packet */
84ea2591 6656 writel(i, tx_ring->tail);
d3d00239
AD		 6657
6658 return;
6659dma_error:
6660 dev_err(dev, "TX DMA map failed\n");
6661
6662 /* clear dma mappings for failed tx_buffer_info map */
6663 for (;;) {
6664 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6665 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6666 if (tx_buffer_info == first)
6667 break;
6668 if (i == 0)
6669 i = tx_ring->count;
6670 i--;
6671 }
6672
6673 dev_kfree_skb_any(skb);
6674
6675 tx_ring->next_to_use = i;
9a799d71
AK		 6676}
6677
69830529
AD		 6678static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6679 u32 tx_flags, __be16 protocol)
6680{
6681 struct ixgbe_q_vector *q_vector = ring->q_vector;
6682 union ixgbe_atr_hash_dword input = { .dword = 0 };
6683 union ixgbe_atr_hash_dword common = { .dword = 0 };
6684 union {
6685 unsigned char *network;
6686 struct iphdr *ipv4;
6687 struct ipv6hdr *ipv6;
6688 } hdr;
ee9e0f0b 6689 struct tcphdr *th;
905e4a41 6690 __be16 vlan_id;
c4cf55e5 6691
69830529
AD		 6692 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6693 if (!q_vector)
6694 return;
6695
6696 /* do nothing if sampling is disabled */
6697 if (!ring->atr_sample_rate)
d3ead241 6698 return;
c4cf55e5 6699
69830529 6700 ring->atr_count++;
c4cf55e5 6701
69830529
AD		 6702 /* snag network header to get L4 type and address */
6703 hdr.network = skb_network_header(skb);
6704
6705 /* Currently only IPv4/IPv6 with TCP is supported */
6706 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6707 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6708 (protocol != __constant_htons(ETH_P_IP) ||
6709 hdr.ipv4->protocol != IPPROTO_TCP))
6710 return;
ee9e0f0b
AD		 6711
6712 th = tcp_hdr(skb);
c4cf55e5 6713
66f32a8b
AD		 6714 /* skip this packet since it is invalid or the socket is closing */
6715 if (!th || th->fin)
69830529
AD		 6716 return;
6717
6718 /* sample on all syn packets or once every atr sample count */
6719 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6720 return;
6721
6722 /* reset sample count */
6723 ring->atr_count = 0;
6724
6725 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6726
6727 /*
6728 * src and dst are inverted, think how the receiver sees them
6729 *
6730 * The input is broken into two sections, a non-compressed section
6731 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6732 * is XORed together and stored in the compressed dword.
6733 */
6734 input.formatted.vlan_id = vlan_id;
6735
6736 /*
6737 * since src port and flex bytes occupy the same word XOR them together
6738 * and write the value to source port portion of compressed dword
6739 */
66f32a8b 6740 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6741 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6742 else
6743 common.port.src ^= th->dest ^ protocol;
6744 common.port.dst ^= th->source;
6745
6746 if (protocol == __constant_htons(ETH_P_IP)) {
6747 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6748 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6749 } else {
6750 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6751 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6752 hdr.ipv6->saddr.s6_addr32[1] ^
6753 hdr.ipv6->saddr.s6_addr32[2] ^
6754 hdr.ipv6->saddr.s6_addr32[3] ^
6755 hdr.ipv6->daddr.s6_addr32[0] ^
6756 hdr.ipv6->daddr.s6_addr32[1] ^
6757 hdr.ipv6->daddr.s6_addr32[2] ^
6758 hdr.ipv6->daddr.s6_addr32[3];
6759 }
c4cf55e5
PWJ		 6760
6761 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6762 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6763 input, common, ring->queue_index);
c4cf55e5
PWJ		 6764}
6765
63544e9c 6766static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6767{
fc77dc3c 6768 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6769 /* Herbert's original patch had:
6770 * smp_mb__after_netif_stop_queue();
6771 * but since that doesn't exist yet, just open code it. */
6772 smp_mb();
6773
6774 /* We need to check again in a case another CPU has just
6775 * made room available. */
7d4987de 6776 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6777 return -EBUSY;
6778
6779 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6780 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6781 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6782 return 0;
6783}
6784
82d4e46e 6785static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6786{
7d4987de 6787 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6788 return 0;
fc77dc3c 6789 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6790}
6791
09a3b1f8
SH		 6792static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6793{
6794 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6795 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6796 smp_processor_id();
56075a98 6797#ifdef IXGBE_FCOE
6440752c 6798 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6799
e5b64635
JF		 6800 if (((protocol == htons(ETH_P_FCOE)) ||
6801 (protocol == htons(ETH_P_FIP))) &&
6802 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6803 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6804 txq += adapter->ring_feature[RING_F_FCOE].mask;
6805 return txq;
56075a98
JF		 6806 }
6807#endif
6808
fdd3d631
KK		 6809 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6810 while (unlikely(txq >= dev->real_num_tx_queues))
6811 txq -= dev->real_num_tx_queues;
5f715823 6812 return txq;
fdd3d631 6813 }
c4cf55e5 6814
09a3b1f8
SH		 6815 return skb_tx_hash(dev, skb);
6816}
6817
fc77dc3c 6818netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6819 struct ixgbe_adapter *adapter,
6820 struct ixgbe_ring *tx_ring)
9a799d71 6821{
d3d00239 6822 struct ixgbe_tx_buffer *first;
5f715823 6823 int tso;
d3d00239 6824 u32 tx_flags = 0;
a535c30e
AD		 6825#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6826 unsigned short f;
6827#endif
a535c30e 6828 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6829 __be16 protocol = skb->protocol;
63544e9c 6830 u8 hdr_len = 0;
5e09a105 6831
a535c30e
AD		 6832 /*
6833 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6834 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6835 * + 2 desc gap to keep tail from touching head,
6836 * + 1 desc for context descriptor,
6837 * otherwise try next time
6838 */
6839#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6840 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6841 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6842#else
6843 count += skb_shinfo(skb)->nr_frags;
6844#endif
6845 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6846 tx_ring->tx_stats.tx_busy++;
6847 return NETDEV_TX_BUSY;
6848 }
6849
7f9643fd
AD		 6850#ifdef CONFIG_PCI_IOV
6851 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6852 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6853
6854#endif
66f32a8b 6855 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6856 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6857 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6858 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6859 /* else if it is a SW VLAN check the next protocol and store the tag */
6860 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6861 struct vlan_hdr *vhdr, _vhdr;
6862 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6863 if (!vhdr)
6864 goto out_drop;
6865
6866 protocol = vhdr->h_vlan_encapsulated_proto;
6867 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6868 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6869 }
6870
32701dc2 6871 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6872 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6873 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6874 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6875 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6876 tx_flags |= (skb->priority & 0x7) <<
6877 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6878 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6879 struct vlan_ethhdr *vhdr;
6880 if (skb_header_cloned(skb) &&
6881 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6882 goto out_drop;
6883 vhdr = (struct vlan_ethhdr *)skb->data;
6884 vhdr->h_vlan_TCI = htons(tx_flags >>
6885 IXGBE_TX_FLAGS_VLAN_SHIFT);
6886 } else {
6887 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6888 }
9a799d71 6889 }
eacd73f7 6890
a535c30e 6891 /* record the location of the first descriptor for this packet */
d3d00239 6892 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6893
eacd73f7 6894#ifdef IXGBE_FCOE
66f32a8b
AD		 6895 /* setup tx offload for FCoE */
6896 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6897 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6898 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6899 if (tso < 0)
6900 goto out_drop;
6901 else if (tso)
66f32a8b
AD		 6902 tx_flags |= IXGBE_TX_FLAGS_FSO |
6903 IXGBE_TX_FLAGS_FCOE;
6904 else
6905 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6906
66f32a8b 6907 goto xmit_fcoe;
eacd73f7 6908 }
9a799d71 6909
66f32a8b
AD		 6910#endif /* IXGBE_FCOE */
6911 /* setup IPv4/IPv6 offloads */
6912 if (protocol == __constant_htons(ETH_P_IP))
6913 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6914
66f32a8b
AD		 6915 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6916 if (tso < 0)
897ab156 6917 goto out_drop;
66f32a8b
AD		 6918 else if (tso)
6919 tx_flags |= IXGBE_TX_FLAGS_TSO;
6920 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6921 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6922
6923 /* add the ATR filter if ATR is on */
6924 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6925 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6926
6927#ifdef IXGBE_FCOE
6928xmit_fcoe:
6929#endif /* IXGBE_FCOE */
d3d00239
AD		 6930 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6931
6932 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6933
6934 return NETDEV_TX_OK;
897ab156
AD		 6935
6936out_drop:
6937 dev_kfree_skb_any(skb);
6938 return NETDEV_TX_OK;
9a799d71
AK		 6939}
6940
84418e3b
AD		 6941static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6942{
6943 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6944 struct ixgbe_ring *tx_ring;
6945
6946 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6947 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6948}
6949
9a799d71
AK		 6950/**
6951 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6952 * @netdev: network interface device structure
6953 * @p: pointer to an address structure
6954 *
6955 * Returns 0 on success, negative on failure
6956 **/
6957static int ixgbe_set_mac(struct net_device *netdev, void *p)
6958{
6959 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6960 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6961 struct sockaddr *addr = p;
6962
6963 if (!is_valid_ether_addr(addr->sa_data))
6964 return -EADDRNOTAVAIL;
6965
6966 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6967 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6968
1cdd1ec8
GR		 6969 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6970 IXGBE_RAH_AV);
9a799d71
AK		 6971
6972 return 0;
6973}
6974
6b73e10d
BH		 6975static int
6976ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6977{
6978 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6979 struct ixgbe_hw *hw = &adapter->hw;
6980 u16 value;
6981 int rc;
6982
6983 if (prtad != hw->phy.mdio.prtad)
6984 return -EINVAL;
6985 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6986 if (!rc)
6987 rc = value;
6988 return rc;
6989}
6990
6991static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6992 u16 addr, u16 value)
6993{
6994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6995 struct ixgbe_hw *hw = &adapter->hw;
6996
6997 if (prtad != hw->phy.mdio.prtad)
6998 return -EINVAL;
6999 return hw->phy.ops.write_reg(hw, addr, devad, value);
7000}
7001
7002static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7003{
7004 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7005
7006 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7007}
7008
0365e6e4
PW		 7009/**
7010 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7011 * netdev->dev_addrs
0365e6e4
PW		 7012 * @netdev: network interface device structure
7013 *
7014 * Returns non-zero on failure
7015 **/
7016static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7017{
7018 int err = 0;
7019 struct ixgbe_adapter *adapter = netdev_priv(dev);
7020 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7021
7022 if (is_valid_ether_addr(mac->san_addr)) {
7023 rtnl_lock();
7024 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7025 rtnl_unlock();
7026 }
7027 return err;
7028}
7029
7030/**
7031 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7032 * netdev->dev_addrs
0365e6e4
PW		 7033 * @netdev: network interface device structure
7034 *
7035 * Returns non-zero on failure
7036 **/
7037static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7038{
7039 int err = 0;
7040 struct ixgbe_adapter *adapter = netdev_priv(dev);
7041 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7042
7043 if (is_valid_ether_addr(mac->san_addr)) {
7044 rtnl_lock();
7045 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7046 rtnl_unlock();
7047 }
7048 return err;
7049}
7050
9a799d71
AK		 7051#ifdef CONFIG_NET_POLL_CONTROLLER
7052/*
7053 * Polling 'interrupt' - used by things like netconsole to send skbs
7054 * without having to re-enable interrupts. It's not called while
7055 * the interrupt routine is executing.
7056 */
7057static void ixgbe_netpoll(struct net_device *netdev)
7058{
7059 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7060 int i;
9a799d71 7061
1a647bd2
AD		 7062 /* if interface is down do nothing */
7063 if (test_bit(__IXGBE_DOWN, &adapter->state))
7064 return;
7065
9a799d71 7066 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7067 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7068 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7069 for (i = 0; i < num_q_vectors; i++) {
7070 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7071 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7072 }
7073 } else {
7074 ixgbe_intr(adapter->pdev->irq, netdev);
7075 }
9a799d71 7076 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7077}
7078#endif
7079
de1036b1
ED		 7080static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7081 struct rtnl_link_stats64 *stats)
7082{
7083 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7084 int i;
7085
1a51502b 7086 rcu_read_lock();
de1036b1 7087 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7088 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7089 u64 bytes, packets;
7090 unsigned int start;
7091
1a51502b
ED		 7092 if (ring) {
7093 do {
7094 start = u64_stats_fetch_begin_bh(&ring->syncp);
7095 packets = ring->stats.packets;
7096 bytes = ring->stats.bytes;
7097 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7098 stats->rx_packets += packets;
7099 stats->rx_bytes += bytes;
7100 }
de1036b1 7101 }
1ac9ad13
ED		 7102
7103 for (i = 0; i < adapter->num_tx_queues; i++) {
7104 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7105 u64 bytes, packets;
7106 unsigned int start;
7107
7108 if (ring) {
7109 do {
7110 start = u64_stats_fetch_begin_bh(&ring->syncp);
7111 packets = ring->stats.packets;
7112 bytes = ring->stats.bytes;
7113 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7114 stats->tx_packets += packets;
7115 stats->tx_bytes += bytes;
7116 }
7117 }
1a51502b 7118 rcu_read_unlock();
de1036b1
ED		 7119 /* following stats updated by ixgbe_watchdog_task() */
7120 stats->multicast = netdev->stats.multicast;
7121 stats->rx_errors = netdev->stats.rx_errors;
7122 stats->rx_length_errors = netdev->stats.rx_length_errors;
7123 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7124 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7125 return stats;
7126}
7127
8b1c0b24
JF		 7128/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7129 * #adapter: pointer to ixgbe_adapter
7130 * @tc: number of traffic classes currently enabled
7131 *
7132 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7133 * 802.1Q priority maps to a packet buffer that exists.
7134 */
7135static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7136{
7137 struct ixgbe_hw *hw = &adapter->hw;
7138 u32 reg, rsave;
7139 int i;
7140
7141 /* 82598 have a static priority to TC mapping that can not
7142 * be changed so no validation is needed.
7143 */
7144 if (hw->mac.type == ixgbe_mac_82598EB)
7145 return;
7146
7147 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7148 rsave = reg;
7149
7150 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7151 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7152
7153 /* If up2tc is out of bounds default to zero */
7154 if (up2tc > tc)
7155 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7156 }
7157
7158 if (reg != rsave)
7159 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7160
7161 return;
7162}
7163
7164
7165/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7166 * classes.
7167 *
7168 * @netdev: net device to configure
7169 * @tc: number of traffic classes to enable
7170 */
7171int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7172{
8b1c0b24
JF		 7173 struct ixgbe_adapter *adapter = netdev_priv(dev);
7174 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7175
e7589eab
JF		 7176 /* Multiple traffic classes requires multiple queues */
7177 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7178 e_err(drv, "Enable failed, needs MSI-X\n");
7179 return -EINVAL;
7180 }
8b1c0b24
JF		 7181
7182 /* Hardware supports up to 8 traffic classes */
4de2a022 7183 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7184 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7185 return -EINVAL;
7186
7187 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7188 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7189 * hardware is not flexible enough to do this dynamically.
7190 */
7191 if (netif_running(dev))
7192 ixgbe_close(dev);
7193 ixgbe_clear_interrupt_scheme(adapter);
7194
e7589eab 7195 if (tc) {
8b1c0b24 7196 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7197 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7198
7199 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7200 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7201
7202 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7203 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7204 } else {
8b1c0b24
JF		 7205 netdev_reset_tc(dev);
7206
e7589eab
JF		 7207 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7208
7209 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7210 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7211
7212 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7213 adapter->dcb_cfg.pfc_mode_enable = false;
7214 }
7215
8b1c0b24
JF		 7216 ixgbe_init_interrupt_scheme(adapter);
7217 ixgbe_validate_rtr(adapter, tc);
7218 if (netif_running(dev))
7219 ixgbe_open(dev);
7220
7221 return 0;
7222}
de1036b1 7223
082757af
DS		 7224void ixgbe_do_reset(struct net_device *netdev)
7225{
7226 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7227
7228 if (netif_running(netdev))
7229 ixgbe_reinit_locked(adapter);
7230 else
7231 ixgbe_reset(adapter);
7232}
7233
c8f44aff
MM		 7234static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7235 netdev_features_t data)
082757af
DS		 7236{
7237 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7238
7239#ifdef CONFIG_DCB
7240 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7241 data &= ~NETIF_F_HW_VLAN_RX;
7242#endif
7243
7244 /* return error if RXHASH is being enabled when RSS is not supported */
7245 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7246 data &= ~NETIF_F_RXHASH;
7247
7248 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7249 if (!(data & NETIF_F_RXCSUM))
7250 data &= ~NETIF_F_LRO;
7251
7252 /* Turn off LRO if not RSC capable or invalid ITR settings */
7253 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7254 data &= ~NETIF_F_LRO;
7255 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7256 (adapter->rx_itr_setting != 1 &&
7257 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7258 data &= ~NETIF_F_LRO;
7259 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7260 }
7261
7262 return data;
7263}
7264
c8f44aff
MM		 7265static int ixgbe_set_features(struct net_device *netdev,
7266 netdev_features_t data)
082757af
DS		 7267{
7268 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7269 bool need_reset = false;
7270
7271 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7272 if (!(data & NETIF_F_RXCSUM))
7273 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7274 else
7275 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7276
7277 /* Make sure RSC matches LRO, reset if change */
7278 if (!!(data & NETIF_F_LRO) !=
7279 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7280 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7281 switch (adapter->hw.mac.type) {
7282 case ixgbe_mac_X540:
7283 case ixgbe_mac_82599EB:
7284 need_reset = true;
7285 break;
7286 default:
7287 break;
7288 }
7289 }
7290
7291 /*
7292 * Check if Flow Director n-tuple support was enabled or disabled. If
7293 * the state changed, we need to reset.
7294 */
7295 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7296 /* turn off ATR, enable perfect filters and reset */
7297 if (data & NETIF_F_NTUPLE) {
7298 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7299 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7300 need_reset = true;
7301 }
7302 } else if (!(data & NETIF_F_NTUPLE)) {
7303 /* turn off Flow Director, set ATR and reset */
7304 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7305 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7306 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7307 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7308 need_reset = true;
7309 }
7310
7311 if (need_reset)
7312 ixgbe_do_reset(netdev);
7313
7314 return 0;
7315
7316}
7317
0edc3527 7318static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7319 .ndo_open = ixgbe_open,
0edc3527 7320 .ndo_stop = ixgbe_close,
00829823 7321 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7322 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7323 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7324 .ndo_validate_addr = eth_validate_addr,
7325 .ndo_set_mac_address = ixgbe_set_mac,
7326 .ndo_change_mtu = ixgbe_change_mtu,
7327 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7328 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7329 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7330 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7331 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7332 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7333 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7334 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7335 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7336 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7337 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7338#ifdef CONFIG_NET_POLL_CONTROLLER
7339 .ndo_poll_controller = ixgbe_netpoll,
7340#endif
332d4a7d
YZ		 7341#ifdef IXGBE_FCOE
7342 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7343 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7344 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7345 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7346 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7347 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7348 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7349#endif /* IXGBE_FCOE */
082757af
DS		 7350 .ndo_set_features = ixgbe_set_features,
7351 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7352};
7353
1cdd1ec8
GR		 7354static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7355 const struct ixgbe_info *ii)
7356{
7357#ifdef CONFIG_PCI_IOV
7358 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7359
c6bda30a 7360 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7361 return;
7362
7363 /* The 82599 supports up to 64 VFs per physical function
7364 * but this implementation limits allocation to 63 so that
7365 * basic networking resources are still available to the
7366 * physical function
7367 */
7368 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7369 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7370#endif /* CONFIG_PCI_IOV */
7371}
7372
9a799d71
AK		 7373/**
7374 * ixgbe_probe - Device Initialization Routine
7375 * @pdev: PCI device information struct
7376 * @ent: entry in ixgbe_pci_tbl
7377 *
7378 * Returns 0 on success, negative on failure
7379 *
7380 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7381 * The OS initialization, configuring of the adapter private structure,
7382 * and a hardware reset occur.
7383 **/
7384static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7385 const struct pci_device_id *ent)
9a799d71
AK		 7386{
7387 struct net_device *netdev;
7388 struct ixgbe_adapter *adapter = NULL;
7389 struct ixgbe_hw *hw;
7390 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7391 static int cards_found;
7392 int i, err, pci_using_dac;
289700db 7393 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7394 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7395#ifdef IXGBE_FCOE
7396 u16 device_caps;
7397#endif
289700db 7398 u32 eec;
c23f5b6b 7399 u16 wol_cap;
9a799d71 7400
bded64a7
AG		 7401 /* Catch broken hardware that put the wrong VF device ID in
7402 * the PCIe SR-IOV capability.
7403 */
7404 if (pdev->is_virtfn) {
7405 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7406 pci_name(pdev), pdev->vendor, pdev->device);
7407 return -EINVAL;
7408 }
7409
9ce77666 7410 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7411 if (err)
7412 return err;
7413
1b507730
NN		 7414 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7415 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7416 pci_using_dac = 1;
7417 } else {
1b507730 7418 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7419 if (err) {
1b507730
NN		 7420 err = dma_set_coherent_mask(&pdev->dev,
7421 DMA_BIT_MASK(32));
9a799d71 7422 if (err) {
b8bc0421
DC		 7423 dev_err(&pdev->dev,
7424 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7425 goto err_dma;
7426 }
7427 }
7428 pci_using_dac = 0;
7429 }
7430
9ce77666 7431 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7432 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7433 if (err) {
b8bc0421
DC		 7434 dev_err(&pdev->dev,
7435 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7436 goto err_pci_reg;
7437 }
7438
19d5afd4 7439 pci_enable_pcie_error_reporting(pdev);
6fabd715 7440
9a799d71 7441 pci_set_master(pdev);
fb3b27bc 7442 pci_save_state(pdev);
9a799d71 7443
e901acd6
JF		 7444#ifdef CONFIG_IXGBE_DCB
7445 indices *= MAX_TRAFFIC_CLASS;
7446#endif
7447
c85a2618
JF		 7448 if (ii->mac == ixgbe_mac_82598EB)
7449 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7450 else
7451 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7452
e901acd6 7453#ifdef IXGBE_FCOE
c85a2618
JF		 7454 indices += min_t(unsigned int, num_possible_cpus(),
7455 IXGBE_MAX_FCOE_INDICES);
7456#endif
c85a2618 7457 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7458 if (!netdev) {
7459 err = -ENOMEM;
7460 goto err_alloc_etherdev;
7461 }
7462
9a799d71
AK		 7463 SET_NETDEV_DEV(netdev, &pdev->dev);
7464
9a799d71 7465 adapter = netdev_priv(netdev);
c60fbb00 7466 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7467
7468 adapter->netdev = netdev;
7469 adapter->pdev = pdev;
7470 hw = &adapter->hw;
7471 hw->back = adapter;
7472 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7473
05857980 7474 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7475 pci_resource_len(pdev, 0));
9a799d71
AK		 7476 if (!hw->hw_addr) {
7477 err = -EIO;
7478 goto err_ioremap;
7479 }
7480
7481 for (i = 1; i <= 5; i++) {
7482 if (pci_resource_len(pdev, i) == 0)
7483 continue;
7484 }
7485
0edc3527 7486 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7487 ixgbe_set_ethtool_ops(netdev);
9a799d71 7488 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7489 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7490
9a799d71
AK		 7491 adapter->bd_number = cards_found;
7492
9a799d71
AK		 7493 /* Setup hw api */
7494 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7495 hw->mac.type = ii->mac;
9a799d71 7496
c44ade9e
JB		 7497 /* EEPROM */
7498 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7499 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7500 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7501 if (!(eec & (1 << 8)))
7502 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7503
7504 /* PHY */
7505 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7506 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7507 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7508 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7509 hw->phy.mdio.mmds = 0;
7510 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7511 hw->phy.mdio.dev = netdev;
7512 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7513 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7514
8ca783ab 7515 ii->get_invariants(hw);
9a799d71
AK		 7516
7517 /* setup the private structure */
7518 err = ixgbe_sw_init(adapter);
7519 if (err)
7520 goto err_sw_init;
7521
e86bff0e 7522 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7523 switch (adapter->hw.mac.type) {
7524 case ixgbe_mac_82599EB:
7525 case ixgbe_mac_X540:
e86bff0e 7526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7527 break;
7528 default:
7529 break;
7530 }
e86bff0e 7531
bf069c97
DS		 7532 /*
7533 * If there is a fan on this device and it has failed log the
7534 * failure.
7535 */
7536 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7537 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7538 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7539 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7540 }
7541
8ef78adc
PWJ		 7542 if (allow_unsupported_sfp)
7543 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7544
c44ade9e 7545 /* reset_hw fills in the perm_addr as well */
119fc60a 7546 hw->phy.reset_if_overtemp = true;
c44ade9e 7547 err = hw->mac.ops.reset_hw(hw);
119fc60a 7548 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7549 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7550 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7551 err = 0;
7552 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7553 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7554 "module type was detected.\n");
7555 e_dev_err("Reload the driver after installing a supported "
7556 "module.\n");
04f165ef
PW		 7557 goto err_sw_init;
7558 } else if (err) {
849c4542 7559 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7560 goto err_sw_init;
7561 }
7562
1cdd1ec8
GR		 7563 ixgbe_probe_vf(adapter, ii);
7564
396e799c 7565 netdev->features = NETIF_F_SG |
e8e9f696 7566 NETIF_F_IP_CSUM |
082757af 7567 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7568 NETIF_F_HW_VLAN_TX |
7569 NETIF_F_HW_VLAN_RX |
082757af
DS		 7570 NETIF_F_HW_VLAN_FILTER |
7571 NETIF_F_TSO |
7572 NETIF_F_TSO6 |
082757af
DS		 7573 NETIF_F_RXHASH |
7574 NETIF_F_RXCSUM;
9a799d71 7575
082757af 7576 netdev->hw_features = netdev->features;
ad31c402 7577
58be7666
DS		 7578 switch (adapter->hw.mac.type) {
7579 case ixgbe_mac_82599EB:
7580 case ixgbe_mac_X540:
45a5ead0 7581 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7582 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7583 NETIF_F_NTUPLE;
58be7666
DS		 7584 break;
7585 default:
7586 break;
7587 }
45a5ead0 7588
ad31c402
JK		 7589 netdev->vlan_features |= NETIF_F_TSO;
7590 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7591 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7592 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7593 netdev->vlan_features |= NETIF_F_SG;
7594
01789349
JP		 7595 netdev->priv_flags |= IFF_UNICAST_FLT;
7596
1cdd1ec8
GR		 7597 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7598 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7599 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7600
7a6b6f51 7601#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7602 netdev->dcbnl_ops = &dcbnl_ops;
7603#endif
7604
eacd73f7 7605#ifdef IXGBE_FCOE
0d551589 7606 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7607 if (hw->mac.ops.get_device_caps) {
7608 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7609 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7610 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7611 }
7612 }
5e09d7f6
YZ		 7613 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7614 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7615 netdev->vlan_features |= NETIF_F_FSO;
7616 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7617 }
eacd73f7 7618#endif /* IXGBE_FCOE */
7b872a55 7619 if (pci_using_dac) {
9a799d71 7620 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7621 netdev->vlan_features |= NETIF_F_HIGHDMA;
7622 }
9a799d71 7623
082757af
DS		 7624 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7625 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7626 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7627 netdev->features |= NETIF_F_LRO;
7628
9a799d71 7629 /* make sure the EEPROM is good */
c44ade9e 7630 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7631 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7632 err = -EIO;
7633 goto err_eeprom;
7634 }
7635
7636 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7637 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7638
c44ade9e 7639 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7640 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7641 err = -EIO;
7642 goto err_eeprom;
7643 }
7644
7086400d
AD		 7645 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7646 (unsigned long) adapter);
9a799d71 7647
7086400d
AD		 7648 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7649 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7650
021230d4
AV		 7651 err = ixgbe_init_interrupt_scheme(adapter);
7652 if (err)
7653 goto err_sw_init;
9a799d71 7654
082757af
DS		 7655 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7656 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7657 netdev->features &= ~NETIF_F_RXHASH;
082757af 7658 }
67a74ee2 7659
c23f5b6b
ET		 7660 /* WOL not supported for all but the following */
7661 adapter->wol = 0;
e8e26350 7662 switch (pdev->device) {
0b077fea 7663 case IXGBE_DEV_ID_82599_SFP:
0e22d043
DS		 7664 /* Only these subdevice supports WOL */
7665 switch (pdev->subsystem_device) {
7666 case IXGBE_SUBDEV_ID_82599_560FLR:
7667 /* only support first port */
7668 if (hw->bus.func != 0)
7669 break;
7670 case IXGBE_SUBDEV_ID_82599_SFP:
9417c464 7671 adapter->wol = IXGBE_WUFC_MAG;
0e22d043
DS		 7672 break;
7673 }
0b077fea 7674 break;
50d6c681
AD		 7675 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7676 /* All except this subdevice support WOL */
0b077fea 7677 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7678 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7679 break;
e8e26350 7680 case IXGBE_DEV_ID_82599_KX4:
9417c464 7681 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7682 break;
c23f5b6b
ET		 7683 case IXGBE_DEV_ID_X540T:
7684 /* Check eeprom to see if it is enabled */
7685 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7686 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7687
7688 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7689 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7690 (hw->bus.func == 0)))
7691 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7692 break;
7693 }
e8e26350
PW		 7694 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7695
15e5209f
ET		 7696 /* save off EEPROM version number */
7697 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7698 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7699
04f165ef
PW		 7700 /* pick up the PCI bus settings for reporting later */
7701 hw->mac.ops.get_bus_info(hw);
7702
9a799d71 7703 /* print bus type/speed/width info */
849c4542 7704 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7705 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7706 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7707 "Unknown"),
7708 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7709 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7710 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7711 "Unknown"),
7712 netdev->dev_addr);
289700db
DS		 7713
7714 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7715 if (err)
9fe93afd 7716 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7717 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7718 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7719 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7720 part_str);
e8e26350 7721 else
289700db
DS		 7722 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7723 hw->mac.type, hw->phy.type, part_str);
9a799d71 7724
e8e26350 7725 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7726 e_dev_warn("PCI-Express bandwidth available for this card is "
7727 "not sufficient for optimal performance.\n");
7728 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7729 "is required.\n");
0c254d86
AK		 7730 }
7731
9a799d71 7732 /* reset the hardware with the new settings */
794caeb2 7733 err = hw->mac.ops.start_hw(hw);
c44ade9e 7734
794caeb2
PWJ		 7735 if (err == IXGBE_ERR_EEPROM_VERSION) {
7736 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7737 e_dev_warn("This device is a pre-production adapter/LOM. "
7738 "Please be aware there may be issues associated "
7739 "with your hardware. If you are experiencing "
7740 "problems please contact your Intel or hardware "
7741 "representative who provided you with this "
7742 "hardware.\n");
794caeb2 7743 }
9a799d71
AK		 7744 strcpy(netdev->name, "eth%d");
7745 err = register_netdev(netdev);
7746 if (err)
7747 goto err_register;
7748
93d3ce8f
ET		 7749 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7750 if (hw->mac.ops.disable_tx_laser &&
7751 ((hw->phy.multispeed_fiber) ||
7752 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7753 (hw->mac.type == ixgbe_mac_82599EB))))
7754 hw->mac.ops.disable_tx_laser(hw);
7755
54386467
JB		 7756 /* carrier off reporting is important to ethtool even BEFORE open */
7757 netif_carrier_off(netdev);
7758
5dd2d332 7759#ifdef CONFIG_IXGBE_DCA
652f093f 7760 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7761 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7762 ixgbe_setup_dca(adapter);
7763 }
7764#endif
1cdd1ec8 7765 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7766 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7767 for (i = 0; i < adapter->num_vfs; i++)
7768 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7769 }
7770
2466dd9c
JK		 7771 /* firmware requires driver version to be 0xFFFFFFFF
7772 * since os does not support feature
7773 */
9612de92 7774 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7775 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7776 0xFF);
9612de92 7777
0365e6e4
PW		 7778 /* add san mac addr to netdev */
7779 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7780
ea81875a 7781 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71
AK		 7782 cards_found++;
7783 return 0;
7784
7785err_register:
5eba3699 7786 ixgbe_release_hw_control(adapter);
7a921c93 7787 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7788err_sw_init:
7789err_eeprom:
1cdd1ec8
GR		 7790 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7791 ixgbe_disable_sriov(adapter);
7086400d 7792 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7793 iounmap(hw->hw_addr);
7794err_ioremap:
7795 free_netdev(netdev);
7796err_alloc_etherdev:
e8e9f696
JP		 7797 pci_release_selected_regions(pdev,
7798 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7799err_pci_reg:
7800err_dma:
7801 pci_disable_device(pdev);
7802 return err;
7803}
7804
7805/**
7806 * ixgbe_remove - Device Removal Routine
7807 * @pdev: PCI device information struct
7808 *
7809 * ixgbe_remove is called by the PCI subsystem to alert the driver
7810 * that it should release a PCI device. The could be caused by a
7811 * Hot-Plug event, or because the driver is going to be removed from
7812 * memory.
7813 **/
7814static void __devexit ixgbe_remove(struct pci_dev *pdev)
7815{
c60fbb00
AD		 7816 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7817 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7818
7819 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7820 cancel_work_sync(&adapter->service_task);
9a799d71 7821
5dd2d332 7822#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7823 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7824 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7825 dca_remove_requester(&pdev->dev);
7826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7827 }
7828
7829#endif
332d4a7d
YZ		 7830#ifdef IXGBE_FCOE
7831 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7832 ixgbe_cleanup_fcoe(adapter);
7833
7834#endif /* IXGBE_FCOE */
0365e6e4
PW		 7835
7836 /* remove the added san mac */
7837 ixgbe_del_sanmac_netdev(netdev);
7838
c4900be0
DS		 7839 if (netdev->reg_state == NETREG_REGISTERED)
7840 unregister_netdev(netdev);
9a799d71 7841
c6bda30a
GR		 7842 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7843 if (!(ixgbe_check_vf_assignment(adapter)))
7844 ixgbe_disable_sriov(adapter);
7845 else
7846 e_dev_warn("Unloading driver while VFs are assigned "
7847 "- VFs will not be deallocated\n");
7848 }
1cdd1ec8 7849
7a921c93 7850 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7851
021230d4 7852 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7853
7854 iounmap(adapter->hw.hw_addr);
9ce77666 7855 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7856 IORESOURCE_MEM));
9a799d71 7857
849c4542 7858 e_dev_info("complete\n");
021230d4 7859
9a799d71
AK		 7860 free_netdev(netdev);
7861
19d5afd4 7862 pci_disable_pcie_error_reporting(pdev);
6fabd715 7863
9a799d71
AK		 7864 pci_disable_device(pdev);
7865}
7866
7867/**
7868 * ixgbe_io_error_detected - called when PCI error is detected
7869 * @pdev: Pointer to PCI device
7870 * @state: The current pci connection state
7871 *
7872 * This function is called after a PCI bus error affecting
7873 * this device has been detected.
7874 */
7875static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7876 pci_channel_state_t state)
9a799d71 7877{
c60fbb00
AD		 7878 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7879 struct net_device *netdev = adapter->netdev;
9a799d71 7880
83c61fa9
GR		 7881#ifdef CONFIG_PCI_IOV
7882 struct pci_dev *bdev, *vfdev;
7883 u32 dw0, dw1, dw2, dw3;
7884 int vf, pos;
7885 u16 req_id, pf_func;
7886
7887 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7888 adapter->num_vfs == 0)
7889 goto skip_bad_vf_detection;
7890
7891 bdev = pdev->bus->self;
7892 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7893 bdev = bdev->bus->self;
7894
7895 if (!bdev)
7896 goto skip_bad_vf_detection;
7897
7898 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7899 if (!pos)
7900 goto skip_bad_vf_detection;
7901
7902 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7903 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7904 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7905 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7906
7907 req_id = dw1 >> 16;
7908 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7909 if (!(req_id & 0x0080))
7910 goto skip_bad_vf_detection;
7911
7912 pf_func = req_id & 0x01;
7913 if ((pf_func & 1) == (pdev->devfn & 1)) {
7914 unsigned int device_id;
7915
7916 vf = (req_id & 0x7F) >> 1;
7917 e_dev_err("VF %d has caused a PCIe error\n", vf);
7918 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7919 "%8.8x\tdw3: %8.8x\n",
7920 dw0, dw1, dw2, dw3);
7921 switch (adapter->hw.mac.type) {
7922 case ixgbe_mac_82599EB:
7923 device_id = IXGBE_82599_VF_DEVICE_ID;
7924 break;
7925 case ixgbe_mac_X540:
7926 device_id = IXGBE_X540_VF_DEVICE_ID;
7927 break;
7928 default:
7929 device_id = 0;
7930 break;
7931 }
7932
7933 /* Find the pci device of the offending VF */
7934 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7935 while (vfdev) {
7936 if (vfdev->devfn == (req_id & 0xFF))
7937 break;
7938 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7939 device_id, vfdev);
7940 }
7941 /*
7942 * There's a slim chance the VF could have been hot plugged,
7943 * so if it is no longer present we don't need to issue the
7944 * VFLR. Just clean up the AER in that case.
7945 */
7946 if (vfdev) {
7947 e_dev_err("Issuing VFLR to VF %d\n", vf);
7948 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7949 }
7950
7951 pci_cleanup_aer_uncorrect_error_status(pdev);
7952 }
7953
7954 /*
7955 * Even though the error may have occurred on the other port
7956 * we still need to increment the vf error reference count for
7957 * both ports because the I/O resume function will be called
7958 * for both of them.
7959 */
7960 adapter->vferr_refcount++;
7961
7962 return PCI_ERS_RESULT_RECOVERED;
7963
7964skip_bad_vf_detection:
7965#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7966 netif_device_detach(netdev);
7967
3044b8d1
BL		 7968 if (state == pci_channel_io_perm_failure)
7969 return PCI_ERS_RESULT_DISCONNECT;
7970
9a799d71
AK		 7971 if (netif_running(netdev))
7972 ixgbe_down(adapter);
7973 pci_disable_device(pdev);
7974
b4617240 7975 /* Request a slot reset. */
9a799d71
AK		 7976 return PCI_ERS_RESULT_NEED_RESET;
7977}
7978
7979/**
7980 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7981 * @pdev: Pointer to PCI device
7982 *
7983 * Restart the card from scratch, as if from a cold-boot.
7984 */
7985static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7986{
c60fbb00 7987 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7988 pci_ers_result_t result;
7989 int err;
9a799d71 7990
9ce77666 7991 if (pci_enable_device_mem(pdev)) {
396e799c 7992 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7993 result = PCI_ERS_RESULT_DISCONNECT;
7994 } else {
7995 pci_set_master(pdev);
7996 pci_restore_state(pdev);
c0e1f68b 7997 pci_save_state(pdev);
9a799d71 7998
dd4d8ca6 7999 pci_wake_from_d3(pdev, false);
9a799d71 8000
6fabd715 8001 ixgbe_reset(adapter);
88512539 8002 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8003 result = PCI_ERS_RESULT_RECOVERED;
8004 }
8005
8006 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8007 if (err) {
849c4542
ET		 8008 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8009 "failed 0x%0x\n", err);
6fabd715
PWJ		 8010 /* non-fatal, continue */
8011 }
9a799d71 8012
6fabd715 8013 return result;
9a799d71
AK		 8014}
8015
8016/**
8017 * ixgbe_io_resume - called when traffic can start flowing again.
8018 * @pdev: Pointer to PCI device
8019 *
8020 * This callback is called when the error recovery driver tells us that
8021 * its OK to resume normal operation.
8022 */
8023static void ixgbe_io_resume(struct pci_dev *pdev)
8024{
c60fbb00
AD		 8025 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8026 struct net_device *netdev = adapter->netdev;
9a799d71 8027
83c61fa9
GR		 8028#ifdef CONFIG_PCI_IOV
8029 if (adapter->vferr_refcount) {
8030 e_info(drv, "Resuming after VF err\n");
8031 adapter->vferr_refcount--;
8032 return;
8033 }
8034
8035#endif
c7ccde0f
AD		 8036 if (netif_running(netdev))
8037 ixgbe_up(adapter);
9a799d71
AK		 8038
8039 netif_device_attach(netdev);
9a799d71
AK		 8040}
8041
8042static struct pci_error_handlers ixgbe_err_handler = {
8043 .error_detected = ixgbe_io_error_detected,
8044 .slot_reset = ixgbe_io_slot_reset,
8045 .resume = ixgbe_io_resume,
8046};
8047
8048static struct pci_driver ixgbe_driver = {
8049 .name = ixgbe_driver_name,
8050 .id_table = ixgbe_pci_tbl,
8051 .probe = ixgbe_probe,
8052 .remove = __devexit_p(ixgbe_remove),
8053#ifdef CONFIG_PM
8054 .suspend = ixgbe_suspend,
8055 .resume = ixgbe_resume,
8056#endif
8057 .shutdown = ixgbe_shutdown,
8058 .err_handler = &ixgbe_err_handler
8059};
8060
8061/**
8062 * ixgbe_init_module - Driver Registration Routine
8063 *
8064 * ixgbe_init_module is the first routine called when the driver is
8065 * loaded. All it does is register with the PCI subsystem.
8066 **/
8067static int __init ixgbe_init_module(void)
8068{
8069 int ret;
c7689578 8070 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8071 pr_info("%s\n", ixgbe_copyright);
9a799d71 8072
5dd2d332 8073#ifdef CONFIG_IXGBE_DCA
bd0362dd 8074 dca_register_notify(&dca_notifier);
bd0362dd 8075#endif
5dd2d332 8076
9a799d71
AK		 8077 ret = pci_register_driver(&ixgbe_driver);
8078 return ret;
8079}
b4617240 8080
9a799d71
AK		 8081module_init(ixgbe_init_module);
8082
8083/**
8084 * ixgbe_exit_module - Driver Exit Cleanup Routine
8085 *
8086 * ixgbe_exit_module is called just before the driver is removed
8087 * from memory.
8088 **/
8089static void __exit ixgbe_exit_module(void)
8090{
5dd2d332 8091#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8092 dca_unregister_notify(&dca_notifier);
8093#endif
9a799d71 8094 pci_unregister_driver(&ixgbe_driver);
1a51502b 8095 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8096}
bd0362dd 8097
5dd2d332 8098#ifdef CONFIG_IXGBE_DCA
bd0362dd 8099static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8100 void *p)
bd0362dd
JC		 8101{
8102 int ret_val;
8103
8104 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8105 __ixgbe_notify_dca);
bd0362dd
JC		 8106
8107 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8108}
b453368d 8109
5dd2d332 8110#endif /* CONFIG_IXGBE_DCA */
849c4542 8111
9a799d71
AK		 8112module_exit(ixgbe_exit_module);
8113
8114/* ixgbe_main.c */
Linux kernel - Deliverables
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