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drivers: replace dev->trans_start accesses with dev_trans_start
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
37689010 4 Copyright(c) 1999 - 2016 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
b82b17d9
JF		 54#include <net/pkt_cls.h>
55#include <net/tc_act/tc_gact.h>
9a799d71
AK		 56
57#include "ixgbe.h"
58#include "ixgbe_common.h"
ee5f784a 59#include "ixgbe_dcb_82599.h"
1cdd1ec8 60#include "ixgbe_sriov.h"
b82b17d9 61#include "ixgbe_model.h"
9a799d71
AK		 62
63char ixgbe_driver_name[] = "ixgbe";
9c8eb720 64static const char ixgbe_driver_string[] =
e8e9f696 65 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 66#ifdef IXGBE_FCOE
ea81875a
NP		 67char ixgbe_default_device_descr[] =
68 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 69#else
70static char ixgbe_default_device_descr[] =
71 "Intel(R) 10 Gigabit Network Connection";
72#endif
10ef00fe 73#define DRV_VERSION "4.4.0-k"
9c8eb720 74const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 75static const char ixgbe_copyright[] =
49425dfc 76 "Copyright (c) 1999-2016 Intel Corporation.";
9a799d71 77
f44e751b
DS		 78static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
79
9a799d71 80static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 81 [board_82598] = &ixgbe_82598_info,
82 [board_82599] = &ixgbe_82599_info,
83 [board_X540] = &ixgbe_X540_info,
84 [board_X550] = &ixgbe_X550_info,
85 [board_X550EM_x] = &ixgbe_X550EM_x_info,
49425dfc 86 [board_x550em_a] = &ixgbe_x550em_a_info,
9a799d71
AK		 87};
88
89/* ixgbe_pci_tbl - PCI Device ID Table
90 *
91 * Wildcard entries (PCI_ANY_ID) should come last
92 * Last entry must be all 0s
93 *
94 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
95 * Class, Class Mask, private data (not used) }
96 */
9baa3c34 97static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
a711ad89 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
6a14ee0c
DS		 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
f572b2c4
MR		 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
49425dfc 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
200157c2
MR		 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
2d40cd17 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
9a799d71
AK		 140 /* required last entry */
141 {0, }
142};
143MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
144
5dd2d332 145#ifdef CONFIG_IXGBE_DCA
bd0362dd 146static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 147 void *p);
bd0362dd
JC		 148static struct notifier_block dca_notifier = {
149 .notifier_call = ixgbe_notify_dca,
150 .next = NULL,
151 .priority = 0
152};
153#endif
154
1cdd1ec8
GR		 155#ifdef CONFIG_PCI_IOV
156static unsigned int max_vfs;
157module_param(max_vfs, uint, 0);
e8e9f696 158MODULE_PARM_DESC(max_vfs,
170e8543 159 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 160#endif /* CONFIG_PCI_IOV */
161
8ef78adc
PWJ		 162static unsigned int allow_unsupported_sfp;
163module_param(allow_unsupported_sfp, uint, 0);
164MODULE_PARM_DESC(allow_unsupported_sfp,
165 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
166
b3f4d599 167#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
168static int debug = -1;
169module_param(debug, int, 0);
170MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
171
9a799d71
AK		 172MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
173MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
174MODULE_LICENSE("GPL");
175MODULE_VERSION(DRV_VERSION);
176
780484d8
MR		 177static struct workqueue_struct *ixgbe_wq;
178
14438464
MR		 179static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
180
b8e82001
JK		 181static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
182 u32 reg, u16 *value)
183{
b8e82001
JK		 184 struct pci_dev *parent_dev;
185 struct pci_bus *parent_bus;
186
187 parent_bus = adapter->pdev->bus->parent;
188 if (!parent_bus)
189 return -1;
190
191 parent_dev = parent_bus->self;
192 if (!parent_dev)
193 return -1;
194
c0798edf 195 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 196 return -1;
197
c0798edf 198 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 199 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
200 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
201 return -1;
b8e82001
JK		 202 return 0;
203}
204
205static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
206{
207 struct ixgbe_hw *hw = &adapter->hw;
208 u16 link_status = 0;
209 int err;
210
211 hw->bus.type = ixgbe_bus_type_pci_express;
212
213 /* Get the negotiated link width and speed from PCI config space of the
214 * parent, as this device is behind a switch
215 */
216 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
217
218 /* assume caller will handle error case */
219 if (err)
220 return err;
221
222 hw->bus.width = ixgbe_convert_bus_width(link_status);
223 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
224
225 return 0;
226}
227
e027d1ae
JK		 228/**
229 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
230 * @hw: hw specific details
231 *
232 * This function is used by probe to determine whether a device's PCI-Express
233 * bandwidth details should be gathered from the parent bus instead of from the
234 * device. Used to ensure that various locations all have the correct device ID
235 * checks.
236 */
237static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
238{
239 switch (hw->device_id) {
240 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 241 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 242 return true;
243 default:
244 return false;
245 }
246}
247
248static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
249 int expected_gts)
250{
f9328bc6 251 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 252 int max_gts = 0;
253 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
254 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
255 struct pci_dev *pdev;
256
f9328bc6
DS		 257 /* Some devices are not connected over PCIe and thus do not negotiate
258 * speed. These devices do not have valid bus info, and thus any report
259 * we generate may not be correct.
260 */
261 if (hw->bus.type == ixgbe_bus_type_internal)
262 return;
263
56d1392f 264 /* determine whether to use the parent device */
e027d1ae
JK		 265 if (ixgbe_pcie_from_parent(&adapter->hw))
266 pdev = adapter->pdev->bus->parent->self;
267 else
268 pdev = adapter->pdev;
269
270 if (pcie_get_minimum_link(pdev, &speed, &width) ||
271 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
272 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
273 return;
274 }
275
276 switch (speed) {
277 case PCIE_SPEED_2_5GT:
278 /* 8b/10b encoding reduces max throughput by 20% */
279 max_gts = 2 * width;
280 break;
281 case PCIE_SPEED_5_0GT:
282 /* 8b/10b encoding reduces max throughput by 20% */
283 max_gts = 4 * width;
284 break;
285 case PCIE_SPEED_8_0GT:
9f0a433c 286 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 287 max_gts = 8 * width;
288 break;
289 default:
290 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
291 return;
292 }
293
294 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
295 max_gts);
296 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
297 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
298 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
299 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
300 "Unknown"),
301 width,
302 (speed == PCIE_SPEED_2_5GT ? "20%" :
303 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 304 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 305 "Unknown"));
306
307 if (max_gts < expected_gts) {
308 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
309 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
310 expected_gts);
311 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
312 }
313}
314
7086400d
AD		 315static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
316{
317 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 318 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 319 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 320 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 321}
322
2a1a091c
MR		 323static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
324{
325 struct ixgbe_adapter *adapter = hw->back;
326
327 if (!hw->hw_addr)
328 return;
329 hw->hw_addr = NULL;
330 e_dev_err("Adapter removed\n");
58cf663f
MR		 331 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
332 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 333}
334
f8e2472f 335static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 336{
337 u32 value;
338
339 /* The following check not only optimizes a bit by not
340 * performing a read on the status register when the
341 * register just read was a status register read that
342 * returned IXGBE_FAILED_READ_REG. It also blocks any
343 * potential recursion.
344 */
345 if (reg == IXGBE_STATUS) {
346 ixgbe_remove_adapter(hw);
347 return;
348 }
349 value = ixgbe_read_reg(hw, IXGBE_STATUS);
350 if (value == IXGBE_FAILED_READ_REG)
351 ixgbe_remove_adapter(hw);
352}
353
f8e2472f
MR		 354/**
355 * ixgbe_read_reg - Read from device register
356 * @hw: hw specific details
357 * @reg: offset of register to read
358 *
359 * Returns : value read or IXGBE_FAILED_READ_REG if removed
360 *
361 * This function is used to read device registers. It checks for device
362 * removal by confirming any read that returns all ones by checking the
363 * status register value for all ones. This function avoids reading from
364 * the hardware if a removal was previously detected in which case it
365 * returns IXGBE_FAILED_READ_REG (all ones).
366 */
367u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
368{
369 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
370 u32 value;
371
372 if (ixgbe_removed(reg_addr))
373 return IXGBE_FAILED_READ_REG;
2f2219be
MR		 374 if (unlikely(hw->phy.nw_mng_if_sel &
375 IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) {
376 struct ixgbe_adapter *adapter;
377 int i;
378
379 for (i = 0; i < 200; ++i) {
380 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
381 if (likely(!value))
382 goto writes_completed;
383 if (value == IXGBE_FAILED_READ_REG) {
384 ixgbe_remove_adapter(hw);
385 return IXGBE_FAILED_READ_REG;
386 }
387 udelay(5);
388 }
389
390 adapter = hw->back;
391 e_warn(hw, "register writes incomplete %08x\n", value);
392 }
393
394writes_completed:
f8e2472f
MR		 395 value = readl(reg_addr + reg);
396 if (unlikely(value == IXGBE_FAILED_READ_REG))
397 ixgbe_check_remove(hw, reg);
398 return value;
399}
400
14438464
MR		 401static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
402{
403 u16 value;
404
405 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
406 if (value == IXGBE_FAILED_READ_CFG_WORD) {
407 ixgbe_remove_adapter(hw);
408 return true;
409 }
410 return false;
411}
412
413u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
414{
415 struct ixgbe_adapter *adapter = hw->back;
416 u16 value;
417
418 if (ixgbe_removed(hw->hw_addr))
419 return IXGBE_FAILED_READ_CFG_WORD;
420 pci_read_config_word(adapter->pdev, reg, &value);
421 if (value == IXGBE_FAILED_READ_CFG_WORD &&
422 ixgbe_check_cfg_remove(hw, adapter->pdev))
423 return IXGBE_FAILED_READ_CFG_WORD;
424 return value;
425}
426
427#ifdef CONFIG_PCI_IOV
428static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
429{
430 struct ixgbe_adapter *adapter = hw->back;
431 u32 value;
432
433 if (ixgbe_removed(hw->hw_addr))
434 return IXGBE_FAILED_READ_CFG_DWORD;
435 pci_read_config_dword(adapter->pdev, reg, &value);
436 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
437 ixgbe_check_cfg_remove(hw, adapter->pdev))
438 return IXGBE_FAILED_READ_CFG_DWORD;
439 return value;
440}
441#endif /* CONFIG_PCI_IOV */
442
ed19231c
JK		 443void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
444{
445 struct ixgbe_adapter *adapter = hw->back;
446
447 if (ixgbe_removed(hw->hw_addr))
448 return;
449 pci_write_config_word(adapter->pdev, reg, value);
450}
451
7086400d
AD		 452static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
453{
454 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
455
52f33af8 456 /* flush memory to make sure state is correct before next watchdog */
4e857c58 457 smp_mb__before_atomic();
7086400d
AD		 458 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
459}
460
dcd79aeb
TI		 461struct ixgbe_reg_info {
462 u32 ofs;
463 char *name;
464};
465
466static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
467
468 /* General Registers */
469 {IXGBE_CTRL, "CTRL"},
470 {IXGBE_STATUS, "STATUS"},
471 {IXGBE_CTRL_EXT, "CTRL_EXT"},
472
473 /* Interrupt Registers */
474 {IXGBE_EICR, "EICR"},
475
476 /* RX Registers */
477 {IXGBE_SRRCTL(0), "SRRCTL"},
478 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
479 {IXGBE_RDLEN(0), "RDLEN"},
480 {IXGBE_RDH(0), "RDH"},
481 {IXGBE_RDT(0), "RDT"},
482 {IXGBE_RXDCTL(0), "RXDCTL"},
483 {IXGBE_RDBAL(0), "RDBAL"},
484 {IXGBE_RDBAH(0), "RDBAH"},
485
486 /* TX Registers */
487 {IXGBE_TDBAL(0), "TDBAL"},
488 {IXGBE_TDBAH(0), "TDBAH"},
489 {IXGBE_TDLEN(0), "TDLEN"},
490 {IXGBE_TDH(0), "TDH"},
491 {IXGBE_TDT(0), "TDT"},
492 {IXGBE_TXDCTL(0), "TXDCTL"},
493
494 /* List Terminator */
ca8dfe25 495 { .name = NULL }
dcd79aeb
TI		 496};
497
498
499/*
500 * ixgbe_regdump - register printout routine
501 */
502static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
503{
504 int i = 0, j = 0;
505 char rname[16];
506 u32 regs[64];
507
508 switch (reginfo->ofs) {
509 case IXGBE_SRRCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
512 break;
513 case IXGBE_DCA_RXCTRL(0):
514 for (i = 0; i < 64; i++)
515 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
516 break;
517 case IXGBE_RDLEN(0):
518 for (i = 0; i < 64; i++)
519 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
520 break;
521 case IXGBE_RDH(0):
522 for (i = 0; i < 64; i++)
523 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
524 break;
525 case IXGBE_RDT(0):
526 for (i = 0; i < 64; i++)
527 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
528 break;
529 case IXGBE_RXDCTL(0):
530 for (i = 0; i < 64; i++)
531 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
532 break;
533 case IXGBE_RDBAL(0):
534 for (i = 0; i < 64; i++)
535 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
536 break;
537 case IXGBE_RDBAH(0):
538 for (i = 0; i < 64; i++)
539 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
540 break;
541 case IXGBE_TDBAL(0):
542 for (i = 0; i < 64; i++)
543 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
544 break;
545 case IXGBE_TDBAH(0):
546 for (i = 0; i < 64; i++)
547 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
548 break;
549 case IXGBE_TDLEN(0):
550 for (i = 0; i < 64; i++)
551 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
552 break;
553 case IXGBE_TDH(0):
554 for (i = 0; i < 64; i++)
555 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
556 break;
557 case IXGBE_TDT(0):
558 for (i = 0; i < 64; i++)
559 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
560 break;
561 case IXGBE_TXDCTL(0):
562 for (i = 0; i < 64; i++)
563 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
564 break;
565 default:
c7689578 566 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 567 IXGBE_READ_REG(hw, reginfo->ofs));
568 return;
569 }
570
571 for (i = 0; i < 8; i++) {
572 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 573 pr_err("%-15s", rname);
dcd79aeb 574 for (j = 0; j < 8; j++)
c7689578
JP		 575 pr_cont(" %08x", regs[i*8+j]);
576 pr_cont("\n");
dcd79aeb
TI		 577 }
578
579}
580
581/*
582 * ixgbe_dump - Print registers, tx-rings and rx-rings
583 */
584static void ixgbe_dump(struct ixgbe_adapter *adapter)
585{
586 struct net_device *netdev = adapter->netdev;
587 struct ixgbe_hw *hw = &adapter->hw;
588 struct ixgbe_reg_info *reginfo;
589 int n = 0;
590 struct ixgbe_ring *tx_ring;
729739b7 591 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 592 union ixgbe_adv_tx_desc *tx_desc;
593 struct my_u0 { u64 a; u64 b; } *u0;
594 struct ixgbe_ring *rx_ring;
595 union ixgbe_adv_rx_desc *rx_desc;
596 struct ixgbe_rx_buffer *rx_buffer_info;
597 u32 staterr;
598 int i = 0;
599
600 if (!netif_msg_hw(adapter))
601 return;
602
603 /* Print netdevice Info */
604 if (netdev) {
605 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 606 pr_info("Device Name state "
dcd79aeb 607 "trans_start last_rx\n");
c7689578
JP		 608 pr_info("%-15s %016lX %016lX %016lX\n",
609 netdev->name,
610 netdev->state,
4d0e9657 611 dev_trans_start(netdev),
c7689578 612 netdev->last_rx);
dcd79aeb
TI		 613 }
614
615 /* Print Registers */
616 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 617 pr_info(" Register Name Value\n");
dcd79aeb
TI		 618 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
619 reginfo->name; reginfo++) {
620 ixgbe_regdump(hw, reginfo);
621 }
622
623 /* Print TX Ring Summary */
624 if (!netdev || !netif_running(netdev))
e90dd264 625 return;
dcd79aeb
TI		 626
627 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 628 pr_info(" %s %s %s %s\n",
629 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
630 "leng", "ntw", "timestamp");
dcd79aeb
TI		 631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
729739b7 633 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 634 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 635 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 636 (u64)dma_unmap_addr(tx_buffer, dma),
637 dma_unmap_len(tx_buffer, len),
638 tx_buffer->next_to_watch,
639 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 640 }
641
642 /* Print TX Rings */
643 if (!netif_msg_tx_done(adapter))
644 goto rx_ring_summary;
645
646 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
647
648 /* Transmit Descriptor Formats
649 *
39ac868a 650 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 651 * +--------------------------------------------------------------+
652 * 0 | Buffer Address [63:0] |
653 * +--------------------------------------------------------------+
39ac868a 654 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 655 * +--------------------------------------------------------------+
656 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 657 *
658 * 82598 Advanced Transmit Descriptor (Write-Back Format)
659 * +--------------------------------------------------------------+
660 * 0 | RSV [63:0] |
661 * +--------------------------------------------------------------+
662 * 8 | RSV | STA | NXTSEQ |
663 * +--------------------------------------------------------------+
664 * 63 36 35 32 31 0
665 *
666 * 82599+ Advanced Transmit Descriptor
667 * +--------------------------------------------------------------+
668 * 0 | Buffer Address [63:0] |
669 * +--------------------------------------------------------------+
670 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
671 * +--------------------------------------------------------------+
672 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
673 *
674 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
675 * +--------------------------------------------------------------+
676 * 0 | RSV [63:0] |
677 * +--------------------------------------------------------------+
678 * 8 | RSV | STA | RSV |
679 * +--------------------------------------------------------------+
680 * 63 36 35 32 31 0
dcd79aeb
TI		 681 */
682
683 for (n = 0; n < adapter->num_tx_queues; n++) {
684 tx_ring = adapter->tx_ring[n];
c7689578
JP		 685 pr_info("------------------------------------\n");
686 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
687 pr_info("------------------------------------\n");
8ad88e37
JH		 688 pr_info("%s%s %s %s %s %s\n",
689 "T [desc] [address 63:0 ] ",
690 "[PlPOIdStDDt Ln] [bi->dma ] ",
691 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 692
693 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 694 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 695 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 696 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 697 if (dma_unmap_len(tx_buffer, len) > 0) {
698 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
699 i,
700 le64_to_cpu(u0->a),
701 le64_to_cpu(u0->b),
702 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 703 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 704 tx_buffer->next_to_watch,
705 (u64)tx_buffer->time_stamp,
706 tx_buffer->skb);
707 if (i == tx_ring->next_to_use &&
708 i == tx_ring->next_to_clean)
709 pr_cont(" NTC/U\n");
710 else if (i == tx_ring->next_to_use)
711 pr_cont(" NTU\n");
712 else if (i == tx_ring->next_to_clean)
713 pr_cont(" NTC\n");
714 else
715 pr_cont("\n");
716
717 if (netif_msg_pktdata(adapter) &&
718 tx_buffer->skb)
719 print_hex_dump(KERN_INFO, "",
720 DUMP_PREFIX_ADDRESS, 16, 1,
721 tx_buffer->skb->data,
722 dma_unmap_len(tx_buffer, len),
723 true);
724 }
dcd79aeb
TI		 725 }
726 }
727
728 /* Print RX Rings Summary */
729rx_ring_summary:
730 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 731 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 732 for (n = 0; n < adapter->num_rx_queues; n++) {
733 rx_ring = adapter->rx_ring[n];
c7689578
JP		 734 pr_info("%5d %5X %5X\n",
735 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 736 }
737
738 /* Print RX Rings */
739 if (!netif_msg_rx_status(adapter))
e90dd264 740 return;
dcd79aeb
TI		 741
742 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
743
39ac868a
JH		 744 /* Receive Descriptor Formats
745 *
746 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 747 * 63 1 0
748 * +-----------------------------------------------------+
749 * 0 | Packet Buffer Address [63:1] |A0/NSE|
750 * +----------------------------------------------+------+
751 * 8 | Header Buffer Address [63:1] | DD |
752 * +-----------------------------------------------------+
753 *
754 *
39ac868a 755 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 756 *
757 * 63 48 47 32 31 30 21 20 16 15 4 3 0
758 * +------------------------------------------------------+
39ac868a
JH		 759 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
760 * | Packet | IP | | | | Type | Type |
761 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 762 * +------------------------------------------------------+
763 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
764 * +------------------------------------------------------+
765 * 63 48 47 32 31 20 19 0
39ac868a
JH		 766 *
767 * 82599+ Advanced Receive Descriptor (Read) Format
768 * 63 1 0
769 * +-----------------------------------------------------+
770 * 0 | Packet Buffer Address [63:1] |A0/NSE|
771 * +----------------------------------------------+------+
772 * 8 | Header Buffer Address [63:1] | DD |
773 * +-----------------------------------------------------+
774 *
775 *
776 * 82599+ Advanced Receive Descriptor (Write-Back) Format
777 *
778 * 63 48 47 32 31 30 21 20 17 16 4 3 0
779 * +------------------------------------------------------+
780 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
781 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
782 * |/ Flow Dir Flt ID | | | | | |
783 * +------------------------------------------------------+
784 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
785 * +------------------------------------------------------+
786 * 63 48 47 32 31 20 19 0
dcd79aeb 787 */
39ac868a 788
dcd79aeb
TI		 789 for (n = 0; n < adapter->num_rx_queues; n++) {
790 rx_ring = adapter->rx_ring[n];
c7689578
JP		 791 pr_info("------------------------------------\n");
792 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
793 pr_info("------------------------------------\n");
8ad88e37
JH		 794 pr_info("%s%s%s",
795 "R [desc] [ PktBuf A0] ",
796 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 797 "<-- Adv Rx Read format\n");
8ad88e37
JH		 798 pr_info("%s%s%s",
799 "RWB[desc] [PcsmIpSHl PtRs] ",
800 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 801 "<-- Adv Rx Write-Back format\n");
802
803 for (i = 0; i < rx_ring->count; i++) {
804 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 805 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 806 u0 = (struct my_u0 *)rx_desc;
807 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
808 if (staterr & IXGBE_RXD_STAT_DD) {
809 /* Descriptor Done */
c7689578 810 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 811 "%016llX ---------------- %p", i,
812 le64_to_cpu(u0->a),
813 le64_to_cpu(u0->b),
814 rx_buffer_info->skb);
815 } else {
c7689578 816 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 817 "%016llX %016llX %p", i,
818 le64_to_cpu(u0->a),
819 le64_to_cpu(u0->b),
820 (u64)rx_buffer_info->dma,
821 rx_buffer_info->skb);
822
9c50c035
ET		 823 if (netif_msg_pktdata(adapter) &&
824 rx_buffer_info->dma) {
dcd79aeb
TI		 825 print_hex_dump(KERN_INFO, "",
826 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 827 page_address(rx_buffer_info->page) +
828 rx_buffer_info->page_offset,
f800326d 829 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 830 }
831 }
832
833 if (i == rx_ring->next_to_use)
c7689578 834 pr_cont(" NTU\n");
dcd79aeb 835 else if (i == rx_ring->next_to_clean)
c7689578 836 pr_cont(" NTC\n");
dcd79aeb 837 else
c7689578 838 pr_cont("\n");
dcd79aeb
TI		 839
840 }
841 }
dcd79aeb
TI		 842}
843
5eba3699
AV		 844static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
845{
846 u32 ctrl_ext;
847
848 /* Let firmware take over control of h/w */
849 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
850 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 851 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 852}
853
854static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
855{
856 u32 ctrl_ext;
857
858 /* Let firmware know the driver has taken over */
859 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
860 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 861 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 862}
9a799d71 863
49ce9c2c 864/**
e8e26350
PW		 865 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
866 * @adapter: pointer to adapter struct
867 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
868 * @queue: queue to map the corresponding interrupt to
869 * @msix_vector: the vector to map to the corresponding queue
870 *
871 */
872static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 873 u8 queue, u8 msix_vector)
9a799d71
AK		 874{
875 u32 ivar, index;
e8e26350
PW		 876 struct ixgbe_hw *hw = &adapter->hw;
877 switch (hw->mac.type) {
878 case ixgbe_mac_82598EB:
879 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
880 if (direction == -1)
881 direction = 0;
882 index = (((direction * 64) + queue) >> 2) & 0x1F;
883 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
884 ivar &= ~(0xFF << (8 * (queue & 0x3)));
885 ivar |= (msix_vector << (8 * (queue & 0x3)));
886 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
887 break;
888 case ixgbe_mac_82599EB:
b93a2226 889 case ixgbe_mac_X540:
9a75a1ac
DS		 890 case ixgbe_mac_X550:
891 case ixgbe_mac_X550EM_x:
49425dfc 892 case ixgbe_mac_x550em_a:
e8e26350
PW		 893 if (direction == -1) {
894 /* other causes */
895 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
896 index = ((queue & 1) * 8);
897 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
898 ivar &= ~(0xFF << index);
899 ivar |= (msix_vector << index);
900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
901 break;
902 } else {
903 /* tx or rx causes */
904 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
905 index = ((16 * (queue & 1)) + (8 * direction));
906 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
907 ivar &= ~(0xFF << index);
908 ivar |= (msix_vector << index);
909 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
910 break;
911 }
912 default:
913 break;
914 }
9a799d71
AK		 915}
916
fe49f04a 917static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 918 u64 qmask)
fe49f04a
AD		 919{
920 u32 mask;
921
bd508178
AD		 922 switch (adapter->hw.mac.type) {
923 case ixgbe_mac_82598EB:
fe49f04a
AD		 924 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
925 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 926 break;
927 case ixgbe_mac_82599EB:
b93a2226 928 case ixgbe_mac_X540:
9a75a1ac
DS		 929 case ixgbe_mac_X550:
930 case ixgbe_mac_X550EM_x:
49425dfc 931 case ixgbe_mac_x550em_a:
fe49f04a
AD		 932 mask = (qmask & 0xFFFFFFFF);
933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
934 mask = (qmask >> 32);
935 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 936 break;
937 default:
938 break;
fe49f04a
AD		 939 }
940}
941
729739b7
AD		 942void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
943 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 944{
729739b7
AD		 945 if (tx_buffer->skb) {
946 dev_kfree_skb_any(tx_buffer->skb);
947 if (dma_unmap_len(tx_buffer, len))
d3d00239 948 dma_unmap_single(ring->dev,
729739b7
AD		 949 dma_unmap_addr(tx_buffer, dma),
950 dma_unmap_len(tx_buffer, len),
951 DMA_TO_DEVICE);
952 } else if (dma_unmap_len(tx_buffer, len)) {
953 dma_unmap_page(ring->dev,
954 dma_unmap_addr(tx_buffer, dma),
955 dma_unmap_len(tx_buffer, len),
956 DMA_TO_DEVICE);
e5a43549 957 }
729739b7
AD		 958 tx_buffer->next_to_watch = NULL;
959 tx_buffer->skb = NULL;
960 dma_unmap_len_set(tx_buffer, len, 0);
961 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 962}
963
943561d3 964static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 965{
966 struct ixgbe_hw *hw = &adapter->hw;
967 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 968 int i;
943561d3 969 u32 data;
c84d324c 970
943561d3
AD		 971 if ((hw->fc.current_mode != ixgbe_fc_full) &&
972 (hw->fc.current_mode != ixgbe_fc_rx_pause))
973 return;
c84d324c 974
943561d3
AD		 975 switch (hw->mac.type) {
976 case ixgbe_mac_82598EB:
977 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
978 break;
979 default:
980 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
981 }
982 hwstats->lxoffrxc += data;
c84d324c 983
943561d3
AD		 984 /* refill credits (no tx hang) if we received xoff */
985 if (!data)
c84d324c 986 return;
943561d3
AD		 987
988 for (i = 0; i < adapter->num_tx_queues; i++)
989 clear_bit(__IXGBE_HANG_CHECK_ARMED,
990 &adapter->tx_ring[i]->state);
991}
992
993static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
994{
995 struct ixgbe_hw *hw = &adapter->hw;
996 struct ixgbe_hw_stats *hwstats = &adapter->stats;
997 u32 xoff[8] = {0};
2afaa00d 998 u8 tc;
943561d3
AD		 999 int i;
1000 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
1001
1002 if (adapter->ixgbe_ieee_pfc)
1003 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
1004
1005 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
1006 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 1007 return;
943561d3 1008 }
c84d324c
JF		 1009
1010 /* update stats for each tc, only valid with PFC enabled */
1011 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 1012 u32 pxoffrxc;
1013
c84d324c
JF		 1014 switch (hw->mac.type) {
1015 case ixgbe_mac_82598EB:
2afaa00d 1016 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 1017 break;
c84d324c 1018 default:
2afaa00d 1019 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 1020 }
2afaa00d
PN		 1021 hwstats->pxoffrxc[i] += pxoffrxc;
1022 /* Get the TC for given UP */
1023 tc = netdev_get_prio_tc_map(adapter->netdev, i);
1024 xoff[tc] += pxoffrxc;
c84d324c
JF		 1025 }
1026
1027 /* disarm tx queues that have received xoff frames */
1028 for (i = 0; i < adapter->num_tx_queues; i++) {
1029 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1030
2afaa00d 1031 tc = tx_ring->dcb_tc;
c84d324c
JF		 1032 if (xoff[tc])
1033 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1034 }
26f23d82
YZ		 1035}
1036
c84d324c 1037static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1038{
7d7ce682 1039 return ring->stats.packets;
c84d324c
JF		 1040}
1041
1042static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1043{
2a47fa45
JF		 1044 struct ixgbe_adapter *adapter;
1045 struct ixgbe_hw *hw;
1046 u32 head, tail;
1047
1048 if (ring->l2_accel_priv)
1049 adapter = ring->l2_accel_priv->real_adapter;
1050 else
1051 adapter = netdev_priv(ring->netdev);
e01c31a5 1052
2a47fa45
JF		 1053 hw = &adapter->hw;
1054 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1055 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1056
1057 if (head != tail)
1058 return (head < tail) ?
1059 tail - head : (tail + ring->count - head);
1060
1061 return 0;
1062}
1063
1064static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1065{
1066 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1067 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1068 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1069
7d637bcc 1070 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1071
1072 /*
1073 * Check for a hung queue, but be thorough. This verifies
1074 * that a transmit has been completed since the previous
1075 * check AND there is at least one packet pending. The
1076 * ARMED bit is set to indicate a potential hang. The
1077 * bit is cleared if a pause frame is received to remove
1078 * false hang detection due to PFC or 802.3x frames. By
1079 * requiring this to fail twice we avoid races with
1080 * pfc clearing the ARMED bit and conditions where we
1081 * run the check_tx_hang logic with a transmit completion
1082 * pending but without time to complete it yet.
1083 */
e90dd264 1084 if (tx_done_old == tx_done && tx_pending)
c84d324c 1085 /* make sure it is true for two checks in a row */
e90dd264
MR		 1086 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1087 &tx_ring->state);
1088 /* update completed stats and continue */
1089 tx_ring->tx_stats.tx_done_old = tx_done;
1090 /* reset the countdown */
1091 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1092
e90dd264 1093 return false;
9a799d71
AK		 1094}
1095
c83c6cbd
AD		 1096/**
1097 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1098 * @adapter: driver private struct
1099 **/
1100static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1101{
1102
1103 /* Do the reset outside of interrupt context */
1104 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1105 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1106 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1107 ixgbe_service_event_schedule(adapter);
1108 }
1109}
e01c31a5 1110
c04f90e5
RP		 1111/**
1112 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1113 **/
1114static int ixgbe_tx_maxrate(struct net_device *netdev,
1115 int queue_index, u32 maxrate)
1116{
1117 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1118 struct ixgbe_hw *hw = &adapter->hw;
1119 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1120
1121 if (!maxrate)
1122 return 0;
1123
1124 /* Calculate the rate factor values to set */
1125 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1126 bcnrc_val /= maxrate;
1127
1128 /* clear everything but the rate factor */
1129 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1130 IXGBE_RTTBCNRC_RF_DEC_MASK;
1131
1132 /* enable the rate scheduler */
1133 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1134
1135 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1136 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1137
1138 return 0;
1139}
1140
9a799d71
AK		 1141/**
1142 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1143 * @q_vector: structure containing interrupt and ring information
e01c31a5 1144 * @tx_ring: tx ring to clean
8220bbc1 1145 * @napi_budget: Used to determine if we are in netpoll
9a799d71 1146 **/
fe49f04a 1147static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
a3a8749d 1148 struct ixgbe_ring *tx_ring, int napi_budget)
9a799d71 1149{
fe49f04a 1150 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1151 struct ixgbe_tx_buffer *tx_buffer;
1152 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1153 unsigned int total_bytes = 0, total_packets = 0;
59224555 1154 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1155 unsigned int i = tx_ring->next_to_clean;
1156
1157 if (test_bit(__IXGBE_DOWN, &adapter->state))
1158 return true;
9a799d71 1159
d3d00239 1160 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1161 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1162 i -= tx_ring->count;
12207e49 1163
729739b7 1164 do {
d3d00239
AD		 1165 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1166
1167 /* if next_to_watch is not set then there is no work pending */
1168 if (!eop_desc)
1169 break;
1170
7f83a9e6 1171 /* prevent any other reads prior to eop_desc */
7e63bf49 1172 read_barrier_depends();
7f83a9e6 1173
d3d00239
AD		 1174 /* if DD is not set pending work has not been completed */
1175 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1176 break;
8ad494b0 1177
d3d00239
AD		 1178 /* clear next_to_watch to prevent false hangs */
1179 tx_buffer->next_to_watch = NULL;
8ad494b0 1180
091a6246
AD		 1181 /* update the statistics for this packet */
1182 total_bytes += tx_buffer->bytecount;
1183 total_packets += tx_buffer->gso_segs;
1184
fd0db0ed 1185 /* free the skb */
a3a8749d 1186 napi_consume_skb(tx_buffer->skb, napi_budget);
fd0db0ed 1187
729739b7
AD		 1188 /* unmap skb header data */
1189 dma_unmap_single(tx_ring->dev,
1190 dma_unmap_addr(tx_buffer, dma),
1191 dma_unmap_len(tx_buffer, len),
1192 DMA_TO_DEVICE);
1193
fd0db0ed
AD		 1194 /* clear tx_buffer data */
1195 tx_buffer->skb = NULL;
729739b7 1196 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1197
729739b7
AD		 1198 /* unmap remaining buffers */
1199 while (tx_desc != eop_desc) {
d3d00239
AD		 1200 tx_buffer++;
1201 tx_desc++;
8ad494b0 1202 i++;
729739b7
AD		 1203 if (unlikely(!i)) {
1204 i -= tx_ring->count;
d3d00239 1205 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1206 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1207 }
e01c31a5 1208
729739b7
AD		 1209 /* unmap any remaining paged data */
1210 if (dma_unmap_len(tx_buffer, len)) {
1211 dma_unmap_page(tx_ring->dev,
1212 dma_unmap_addr(tx_buffer, dma),
1213 dma_unmap_len(tx_buffer, len),
1214 DMA_TO_DEVICE);
1215 dma_unmap_len_set(tx_buffer, len, 0);
1216 }
1217 }
1218
1219 /* move us one more past the eop_desc for start of next pkt */
1220 tx_buffer++;
1221 tx_desc++;
1222 i++;
1223 if (unlikely(!i)) {
1224 i -= tx_ring->count;
1225 tx_buffer = tx_ring->tx_buffer_info;
1226 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1227 }
1228
1229 /* issue prefetch for next Tx descriptor */
1230 prefetch(tx_desc);
12207e49 1231
729739b7
AD		 1232 /* update budget accounting */
1233 budget--;
1234 } while (likely(budget));
1235
1236 i += tx_ring->count;
9a799d71 1237 tx_ring->next_to_clean = i;
d3d00239 1238 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1239 tx_ring->stats.bytes += total_bytes;
bd198058 1240 tx_ring->stats.packets += total_packets;
d3d00239 1241 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1242 q_vector->tx.total_bytes += total_bytes;
1243 q_vector->tx.total_packets += total_packets;
b953799e 1244
c84d324c
JF		 1245 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1246 /* schedule immediate reset if we believe we hung */
1247 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1248 e_err(drv, "Detected Tx Unit Hang\n"
1249 " Tx Queue <%d>\n"
1250 " TDH, TDT <%x>, <%x>\n"
1251 " next_to_use <%x>\n"
1252 " next_to_clean <%x>\n"
1253 "tx_buffer_info[next_to_clean]\n"
1254 " time_stamp <%lx>\n"
1255 " jiffies <%lx>\n",
1256 tx_ring->queue_index,
1257 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1258 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1259 tx_ring->next_to_use, i,
1260 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1261
1262 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1263
1264 e_info(probe,
1265 "tx hang %d detected on queue %d, resetting adapter\n",
1266 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1267
b953799e 1268 /* schedule immediate reset if we believe we hung */
c83c6cbd 1269 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1270
1271 /* the adapter is about to reset, no point in enabling stuff */
59224555 1272 return true;
b953799e 1273 }
9a799d71 1274
b2d96e0a
AD		 1275 netdev_tx_completed_queue(txring_txq(tx_ring),
1276 total_packets, total_bytes);
1277
e092be60 1278#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1279 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1280 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1281 /* Make sure that anybody stopping the queue after this
1282 * sees the new next_to_clean.
1283 */
1284 smp_mb();
729739b7
AD		 1285 if (__netif_subqueue_stopped(tx_ring->netdev,
1286 tx_ring->queue_index)
1287 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1288 netif_wake_subqueue(tx_ring->netdev,
1289 tx_ring->queue_index);
5b7da515 1290 ++tx_ring->tx_stats.restart_queue;
30eba97a 1291 }
e092be60 1292 }
9a799d71 1293
59224555 1294 return !!budget;
9a799d71
AK		 1295}
1296
5dd2d332 1297#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1298static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1299 struct ixgbe_ring *tx_ring,
33cf09c9 1300 int cpu)
bd0362dd 1301{
33cf09c9 1302 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1303 u32 txctrl = 0;
bdda1a61 1304 u16 reg_offset;
33cf09c9 1305
9de7605e
MR		 1306 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1307 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1308
33cf09c9
AD		 1309 switch (hw->mac.type) {
1310 case ixgbe_mac_82598EB:
bdda1a61 1311 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1312 break;
1313 case ixgbe_mac_82599EB:
b93a2226 1314 case ixgbe_mac_X540:
bdda1a61
AD		 1315 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1316 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1317 break;
1318 default:
bdda1a61
AD		 1319 /* for unknown hardware do not write register */
1320 return;
bd0362dd 1321 }
bdda1a61
AD		 1322
1323 /*
1324 * We can enable relaxed ordering for reads, but not writes when
1325 * DCA is enabled. This is due to a known issue in some chipsets
1326 * which will cause the DCA tag to be cleared.
1327 */
1328 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1329 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1330 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1331
1332 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1333}
1334
bdda1a61
AD		 1335static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1336 struct ixgbe_ring *rx_ring,
33cf09c9 1337 int cpu)
bd0362dd 1338{
33cf09c9 1339 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1340 u32 rxctrl = 0;
bdda1a61
AD		 1341 u8 reg_idx = rx_ring->reg_idx;
1342
9de7605e
MR		 1343 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1344 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1345
1346 switch (hw->mac.type) {
33cf09c9 1347 case ixgbe_mac_82599EB:
b93a2226 1348 case ixgbe_mac_X540:
bdda1a61 1349 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1350 break;
1351 default:
1352 break;
1353 }
bdda1a61
AD		 1354
1355 /*
1356 * We can enable relaxed ordering for reads, but not writes when
1357 * DCA is enabled. This is due to a known issue in some chipsets
1358 * which will cause the DCA tag to be cleared.
1359 */
1360 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1361 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1362 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1363
1364 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1365}
1366
1367static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1368{
1369 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1370 struct ixgbe_ring *ring;
bd0362dd 1371 int cpu = get_cpu();
bd0362dd 1372
33cf09c9
AD		 1373 if (q_vector->cpu == cpu)
1374 goto out_no_update;
1375
a557928e 1376 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1377 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1378
a557928e 1379 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1380 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1381
1382 q_vector->cpu = cpu;
1383out_no_update:
bd0362dd
JC		 1384 put_cpu();
1385}
1386
1387static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1388{
1389 int i;
1390
e35ec126 1391 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1392 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1394 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1395 else
1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1397 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1398
49c7ffbe 1399 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1400 adapter->q_vector[i]->cpu = -1;
1401 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1402 }
1403}
1404
1405static int __ixgbe_notify_dca(struct device *dev, void *data)
1406{
c60fbb00 1407 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1408 unsigned long event = *(unsigned long *)data;
1409
2a72c31e 1410 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1411 return 0;
1412
bd0362dd
JC		 1413 switch (event) {
1414 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1415 /* if we're already enabled, don't do it again */
1416 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1417 break;
652f093f 1418 if (dca_add_requester(dev) == 0) {
96b0e0f6 1419 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1421 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1422 break;
1423 }
1424 /* Fall Through since DCA is disabled. */
1425 case DCA_PROVIDER_REMOVE:
1426 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1427 dca_remove_requester(dev);
1428 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1429 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1430 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1431 }
1432 break;
1433 }
1434
652f093f 1435 return 0;
bd0362dd 1436}
67a74ee2 1437
bdda1a61 1438#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1439
1440#define IXGBE_RSS_L4_TYPES_MASK \
1441 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1442 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1443 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1444 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1445
8a0da21b
AD		 1446static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1447 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1448 struct sk_buff *skb)
1449{
7edda4b8
FD		 1450 u16 rss_type;
1451
1452 if (!(ring->netdev->features & NETIF_F_RXHASH))
1453 return;
1454
1455 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1456 IXGBE_RXDADV_RSSTYPE_MASK;
1457
1458 if (!rss_type)
1459 return;
1460
1461 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1462 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1463 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1464}
1465
f800326d 1466#ifdef IXGBE_FCOE
ff886dfc
AD		 1467/**
1468 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1469 * @ring: structure containing ring specific data
ff886dfc
AD		 1470 * @rx_desc: advanced rx descriptor
1471 *
1472 * Returns : true if it is FCoE pkt
1473 */
57efd44c 1474static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1475 union ixgbe_adv_rx_desc *rx_desc)
1476{
1477 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1478
57efd44c 1479 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1480 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1481 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1482 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1483}
1484
f800326d 1485#endif /* IXGBE_FCOE */
e59bd25d
AV		 1486/**
1487 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1488 * @ring: structure containing ring specific data
1489 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1490 * @skb: skb currently being received and modified
1491 **/
8a0da21b 1492static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1493 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1494 struct sk_buff *skb)
9a799d71 1495{
3f207800
DS		 1496 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1497 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1498 bool encap_pkt = false;
1499
8a0da21b 1500 skb_checksum_none_assert(skb);
9a799d71 1501
712744be 1502 /* Rx csum disabled */
8a0da21b 1503 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1504 return;
e59bd25d 1505
3f207800
DS		 1506 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1507 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1508 encap_pkt = true;
1509 skb->encapsulation = 1;
3f207800
DS		 1510 }
1511
e59bd25d 1512 /* if IP and error */
f56e0cb1
AD		 1513 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1514 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1515 ring->rx_stats.csum_err++;
9a799d71
AK		 1516 return;
1517 }
e59bd25d 1518
f56e0cb1 1519 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1520 return;
1521
f56e0cb1 1522 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1523 /*
1524 * 82599 errata, UDP frames with a 0 checksum can be marked as
1525 * checksum errors.
1526 */
8a0da21b
AD		 1527 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1528 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1529 return;
1530
8a0da21b 1531 ring->rx_stats.csum_err++;
e59bd25d
AV		 1532 return;
1533 }
1534
9a799d71 1535 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1536 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1537 if (encap_pkt) {
1538 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1539 return;
1540
1541 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
d469251b 1542 skb->ip_summed = CHECKSUM_NONE;
3f207800
DS		 1543 return;
1544 }
1545 /* If we checked the outer header let the stack know */
1546 skb->csum_level = 1;
1547 }
9a799d71
AK		 1548}
1549
f990b79b
AD		 1550static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1551 struct ixgbe_rx_buffer *bi)
1552{
1553 struct page *page = bi->page;
18cb652a 1554 dma_addr_t dma;
f990b79b 1555
f800326d 1556 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1557 if (likely(page))
f990b79b
AD		 1558 return true;
1559
f800326d 1560 /* alloc new page for storage */
18cb652a
AD		 1561 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1562 if (unlikely(!page)) {
1563 rx_ring->rx_stats.alloc_rx_page_failed++;
1564 return false;
f990b79b
AD		 1565 }
1566
f800326d
AD		 1567 /* map page for use */
1568 dma = dma_map_page(rx_ring->dev, page, 0,
1569 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1570
1571 /*
1572 * if mapping failed free memory back to system since
1573 * there isn't much point in holding memory we can't use
1574 */
1575 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1576 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1577
f990b79b
AD		 1578 rx_ring->rx_stats.alloc_rx_page_failed++;
1579 return false;
1580 }
1581
f800326d 1582 bi->dma = dma;
18cb652a 1583 bi->page = page;
afaa9459 1584 bi->page_offset = 0;
f800326d 1585
f990b79b
AD		 1586 return true;
1587}
1588
9a799d71 1589/**
f990b79b 1590 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1591 * @rx_ring: ring to place buffers on
1592 * @cleaned_count: number of buffers to replace
9a799d71 1593 **/
fc77dc3c 1594void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1595{
9a799d71 1596 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1597 struct ixgbe_rx_buffer *bi;
d5f398ed 1598 u16 i = rx_ring->next_to_use;
9a799d71 1599
f800326d
AD		 1600 /* nothing to do */
1601 if (!cleaned_count)
fc77dc3c
AD		 1602 return;
1603
e4f74028 1604 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1605 bi = &rx_ring->rx_buffer_info[i];
1606 i -= rx_ring->count;
9a799d71 1607
f800326d
AD		 1608 do {
1609 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1610 break;
d5f398ed 1611
f800326d
AD		 1612 /*
1613 * Refresh the desc even if buffer_addrs didn't change
1614 * because each write-back erases this info.
1615 */
1616 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1617
f990b79b
AD		 1618 rx_desc++;
1619 bi++;
9a799d71 1620 i++;
f990b79b 1621 if (unlikely(!i)) {
e4f74028 1622 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1623 bi = rx_ring->rx_buffer_info;
1624 i -= rx_ring->count;
1625 }
1626
18cb652a
AD		 1627 /* clear the status bits for the next_to_use descriptor */
1628 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1629
1630 cleaned_count--;
1631 } while (cleaned_count);
7c6e0a43 1632
f990b79b
AD		 1633 i += rx_ring->count;
1634
ad435ec6
AD		 1635 if (rx_ring->next_to_use != i) {
1636 rx_ring->next_to_use = i;
1637
1638 /* update next to alloc since we have filled the ring */
1639 rx_ring->next_to_alloc = i;
1640
1641 /* Force memory writes to complete before letting h/w
1642 * know there are new descriptors to fetch. (Only
1643 * applicable for weak-ordered memory model archs,
1644 * such as IA-64).
1645 */
1646 wmb();
1647 writel(i, rx_ring->tail);
1648 }
9a799d71
AK		 1649}
1650
1d2024f6
AD		 1651static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1652 struct sk_buff *skb)
1653{
f800326d 1654 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1655
1656 /* set gso_size to avoid messing up TCP MSS */
1657 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1658 IXGBE_CB(skb)->append_cnt);
96be80ab 1659 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1660}
1661
1662static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1663 struct sk_buff *skb)
1664{
1665 /* if append_cnt is 0 then frame is not RSC */
1666 if (!IXGBE_CB(skb)->append_cnt)
1667 return;
1668
1669 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1670 rx_ring->rx_stats.rsc_flush++;
1671
1672 ixgbe_set_rsc_gso_size(rx_ring, skb);
1673
1674 /* gso_size is computed using append_cnt so always clear it last */
1675 IXGBE_CB(skb)->append_cnt = 0;
1676}
1677
8a0da21b
AD		 1678/**
1679 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1680 * @rx_ring: rx descriptor ring packet is being transacted on
1681 * @rx_desc: pointer to the EOP Rx descriptor
1682 * @skb: pointer to current skb being populated
f8212f97 1683 *
8a0da21b
AD		 1684 * This function checks the ring, descriptor, and packet information in
1685 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1686 * other fields within the skb.
f8212f97 1687 **/
8a0da21b
AD		 1688static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1689 union ixgbe_adv_rx_desc *rx_desc,
1690 struct sk_buff *skb)
f8212f97 1691{
43e95f11 1692 struct net_device *dev = rx_ring->netdev;
a9763f3c 1693 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1694
8a0da21b
AD		 1695 ixgbe_update_rsc_stats(rx_ring, skb);
1696
1697 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1698
8a0da21b
AD		 1699 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1700
a9763f3c
MR		 1701 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1702 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1703
f646968f 1704 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1705 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1706 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1707 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1708 }
1709
8a0da21b 1710 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1711
43e95f11 1712 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1713}
1714
8a0da21b
AD		 1715static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1716 struct sk_buff *skb)
aa80175a 1717{
93f93a44 1718 skb_mark_napi_id(skb, &q_vector->napi);
b4640030 1719 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1720 netif_receive_skb(skb);
8a0da21b 1721 else
856f606e 1722 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1723}
43634e82 1724
f800326d
AD		 1725/**
1726 * ixgbe_is_non_eop - process handling of non-EOP buffers
1727 * @rx_ring: Rx ring being processed
1728 * @rx_desc: Rx descriptor for current buffer
1729 * @skb: Current socket buffer containing buffer in progress
1730 *
1731 * This function updates next to clean. If the buffer is an EOP buffer
1732 * this function exits returning false, otherwise it will place the
1733 * sk_buff in the next buffer to be chained and return true indicating
1734 * that this is in fact a non-EOP buffer.
1735 **/
1736static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1737 union ixgbe_adv_rx_desc *rx_desc,
1738 struct sk_buff *skb)
1739{
1740 u32 ntc = rx_ring->next_to_clean + 1;
1741
1742 /* fetch, update, and store next to clean */
1743 ntc = (ntc < rx_ring->count) ? ntc : 0;
1744 rx_ring->next_to_clean = ntc;
1745
1746 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1747
5a02cbd1
AD		 1748 /* update RSC append count if present */
1749 if (ring_is_rsc_enabled(rx_ring)) {
1750 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1751 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1752
1753 if (unlikely(rsc_enabled)) {
1754 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1755
1756 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1757 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1758
5a02cbd1
AD		 1759 /* update ntc based on RSC value */
1760 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1761 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1762 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1763 }
f800326d
AD		 1764 }
1765
5a02cbd1
AD		 1766 /* if we are the last buffer then there is nothing else to do */
1767 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1768 return false;
1769
f800326d
AD		 1770 /* place skb in next buffer to be received */
1771 rx_ring->rx_buffer_info[ntc].skb = skb;
1772 rx_ring->rx_stats.non_eop_descs++;
1773
1774 return true;
1775}
1776
19861ce2
AD		 1777/**
1778 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1779 * @rx_ring: rx descriptor ring packet is being transacted on
1780 * @skb: pointer to current skb being adjusted
1781 *
1782 * This function is an ixgbe specific version of __pskb_pull_tail. The
1783 * main difference between this version and the original function is that
1784 * this function can make several assumptions about the state of things
1785 * that allow for significant optimizations versus the standard function.
1786 * As a result we can do things like drop a frag and maintain an accurate
1787 * truesize for the skb.
1788 */
1789static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1790 struct sk_buff *skb)
1791{
1792 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1793 unsigned char *va;
1794 unsigned int pull_len;
1795
1796 /*
1797 * it is valid to use page_address instead of kmap since we are
1798 * working with pages allocated out of the lomem pool per
1799 * alloc_page(GFP_ATOMIC)
1800 */
1801 va = skb_frag_address(frag);
1802
1803 /*
1804 * we need the header to contain the greater of either ETH_HLEN or
1805 * 60 bytes if the skb->len is less than 60 for skb_pad.
1806 */
8496e338 1807 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1808
1809 /* align pull length to size of long to optimize memcpy performance */
1810 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1811
1812 /* update all of the pointers */
1813 skb_frag_size_sub(frag, pull_len);
1814 frag->page_offset += pull_len;
1815 skb->data_len -= pull_len;
1816 skb->tail += pull_len;
19861ce2
AD		 1817}
1818
42073d91
AD		 1819/**
1820 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1821 * @rx_ring: rx descriptor ring packet is being transacted on
1822 * @skb: pointer to current skb being updated
1823 *
1824 * This function provides a basic DMA sync up for the first fragment of an
1825 * skb. The reason for doing this is that the first fragment cannot be
1826 * unmapped until we have reached the end of packet descriptor for a buffer
1827 * chain.
1828 */
1829static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1830 struct sk_buff *skb)
1831{
1832 /* if the page was released unmap it, else just sync our portion */
1833 if (unlikely(IXGBE_CB(skb)->page_released)) {
1834 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1835 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1836 IXGBE_CB(skb)->page_released = false;
1837 } else {
1838 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1839
1840 dma_sync_single_range_for_cpu(rx_ring->dev,
1841 IXGBE_CB(skb)->dma,
1842 frag->page_offset,
1843 ixgbe_rx_bufsz(rx_ring),
1844 DMA_FROM_DEVICE);
1845 }
1846 IXGBE_CB(skb)->dma = 0;
1847}
1848
f800326d
AD		 1849/**
1850 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1851 * @rx_ring: rx descriptor ring packet is being transacted on
1852 * @rx_desc: pointer to the EOP Rx descriptor
1853 * @skb: pointer to current skb being fixed
1854 *
1855 * Check for corrupted packet headers caused by senders on the local L2
1856 * embedded NIC switch not setting up their Tx Descriptors right. These
1857 * should be very rare.
1858 *
1859 * Also address the case where we are pulling data in on pages only
1860 * and as such no data is present in the skb header.
1861 *
1862 * In addition if skb is not at least 60 bytes we need to pad it so that
1863 * it is large enough to qualify as a valid Ethernet frame.
1864 *
1865 * Returns true if an error was encountered and skb was freed.
1866 **/
1867static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1868 union ixgbe_adv_rx_desc *rx_desc,
1869 struct sk_buff *skb)
1870{
f800326d 1871 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1872
1873 /* verify that the packet does not have any known errors */
1874 if (unlikely(ixgbe_test_staterr(rx_desc,
1875 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1876 !(netdev->features & NETIF_F_RXALL))) {
1877 dev_kfree_skb_any(skb);
1878 return true;
1879 }
1880
19861ce2 1881 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1882 if (skb_is_nonlinear(skb))
1883 ixgbe_pull_tail(rx_ring, skb);
f800326d 1884
57efd44c
AD		 1885#ifdef IXGBE_FCOE
1886 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1887 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1888 return false;
1889
1890#endif
a94d9e22
AD		 1891 /* if eth_skb_pad returns an error the skb was freed */
1892 if (eth_skb_pad(skb))
1893 return true;
f800326d
AD		 1894
1895 return false;
1896}
1897
f800326d
AD		 1898/**
1899 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1900 * @rx_ring: rx descriptor ring to store buffers on
1901 * @old_buff: donor buffer to have page reused
1902 *
0549ae20 1903 * Synchronizes page for reuse by the adapter
f800326d
AD		 1904 **/
1905static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1906 struct ixgbe_rx_buffer *old_buff)
1907{
1908 struct ixgbe_rx_buffer *new_buff;
1909 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1910
1911 new_buff = &rx_ring->rx_buffer_info[nta];
1912
1913 /* update, and store next to alloc */
1914 nta++;
1915 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1916
1917 /* transfer page from old buffer to new buffer */
18cb652a 1918 *new_buff = *old_buff;
f800326d
AD		 1919
1920 /* sync the buffer for use by the device */
1921 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1922 new_buff->page_offset,
1923 ixgbe_rx_bufsz(rx_ring),
f800326d 1924 DMA_FROM_DEVICE);
f800326d
AD		 1925}
1926
18cb652a
AD		 1927static inline bool ixgbe_page_is_reserved(struct page *page)
1928{
2f064f34 1929 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1930}
1931
f800326d
AD		 1932/**
1933 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1934 * @rx_ring: rx descriptor ring to transact packets on
1935 * @rx_buffer: buffer containing page to add
1936 * @rx_desc: descriptor containing length of buffer written by hardware
1937 * @skb: sk_buff to place the data into
1938 *
0549ae20
AD		 1939 * This function will add the data contained in rx_buffer->page to the skb.
1940 * This is done either through a direct copy if the data in the buffer is
1941 * less than the skb header size, otherwise it will just attach the page as
1942 * a frag to the skb.
1943 *
1944 * The function will then update the page offset if necessary and return
1945 * true if the buffer can be reused by the adapter.
f800326d 1946 **/
0549ae20 1947static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1948 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1949 union ixgbe_adv_rx_desc *rx_desc,
1950 struct sk_buff *skb)
f800326d 1951{
0549ae20
AD		 1952 struct page *page = rx_buffer->page;
1953 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1954#if (PAGE_SIZE < 8192)
0549ae20 1955 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1956#else
1957 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1958 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1959 ixgbe_rx_bufsz(rx_ring);
1960#endif
0549ae20 1961
cf3fe7ac
AD		 1962 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1963 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1964
1965 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1966
18cb652a
AD		 1967 /* page is not reserved, we can reuse buffer as-is */
1968 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1969 return true;
1970
1971 /* this page cannot be reused so discard it */
18cb652a 1972 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1973 return false;
1974 }
1975
0549ae20
AD		 1976 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1977 rx_buffer->page_offset, size, truesize);
1978
09816fbe 1979 /* avoid re-using remote pages */
18cb652a 1980 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1981 return false;
1982
1983#if (PAGE_SIZE < 8192)
1984 /* if we are only owner of page we can reuse it */
1985 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1986 return false;
1987
1988 /* flip page offset to other buffer */
1989 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1990#else
1991 /* move offset up to the next cache line */
1992 rx_buffer->page_offset += truesize;
1993
1994 if (rx_buffer->page_offset > last_offset)
1995 return false;
09816fbe 1996#endif
0549ae20 1997
18cb652a
AD		 1998 /* Even if we own the page, we are not allowed to use atomic_set()
1999 * This would break get_page_unless_zero() users.
2000 */
fe896d18 2001 page_ref_inc(page);
18cb652a 2002
0549ae20 2003 return true;
f800326d
AD		 2004}
2005
18806c9e
AD		 2006static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
2007 union ixgbe_adv_rx_desc *rx_desc)
2008{
2009 struct ixgbe_rx_buffer *rx_buffer;
2010 struct sk_buff *skb;
2011 struct page *page;
2012
2013 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2014 page = rx_buffer->page;
2015 prefetchw(page);
2016
2017 skb = rx_buffer->skb;
2018
2019 if (likely(!skb)) {
2020 void *page_addr = page_address(page) +
2021 rx_buffer->page_offset;
2022
2023 /* prefetch first cache line of first page */
2024 prefetch(page_addr);
2025#if L1_CACHE_BYTES < 128
2026 prefetch(page_addr + L1_CACHE_BYTES);
2027#endif
2028
2029 /* allocate a skb to store the frags */
67fd893e
AD		 2030 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
2031 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 2032 if (unlikely(!skb)) {
2033 rx_ring->rx_stats.alloc_rx_buff_failed++;
2034 return NULL;
2035 }
2036
2037 /*
2038 * we will be copying header into skb->data in
2039 * pskb_may_pull so it is in our interest to prefetch
2040 * it now to avoid a possible cache miss
2041 */
2042 prefetchw(skb->data);
2043
2044 /*
2045 * Delay unmapping of the first packet. It carries the
2046 * header information, HW may still access the header
2047 * after the writeback. Only unmap it when EOP is
2048 * reached
2049 */
2050 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2051 goto dma_sync;
2052
2053 IXGBE_CB(skb)->dma = rx_buffer->dma;
2054 } else {
2055 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2056 ixgbe_dma_sync_frag(rx_ring, skb);
2057
2058dma_sync:
2059 /* we are reusing so sync this buffer for CPU use */
2060 dma_sync_single_range_for_cpu(rx_ring->dev,
2061 rx_buffer->dma,
2062 rx_buffer->page_offset,
2063 ixgbe_rx_bufsz(rx_ring),
2064 DMA_FROM_DEVICE);
18cb652a
AD		 2065
2066 rx_buffer->skb = NULL;
18806c9e
AD		 2067 }
2068
2069 /* pull page into skb */
2070 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2071 /* hand second half of page back to the ring */
2072 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2073 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2074 /* the page has been released from the ring */
2075 IXGBE_CB(skb)->page_released = true;
2076 } else {
2077 /* we are not reusing the buffer so unmap it */
2078 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2079 ixgbe_rx_pg_size(rx_ring),
2080 DMA_FROM_DEVICE);
2081 }
2082
2083 /* clear contents of buffer_info */
18806c9e
AD		 2084 rx_buffer->page = NULL;
2085
2086 return skb;
f800326d
AD		 2087}
2088
2089/**
2090 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2091 * @q_vector: structure containing interrupt and ring information
2092 * @rx_ring: rx descriptor ring to transact packets on
2093 * @budget: Total limit on number of packets to process
2094 *
2095 * This function provides a "bounce buffer" approach to Rx interrupt
2096 * processing. The advantage to this is that on systems that have
2097 * expensive overhead for IOMMU access this provides a means of avoiding
2098 * it by maintaining the mapping of the page to the syste.
2099 *
5a85e737 2100 * Returns amount of work completed
f800326d 2101 **/
5a85e737 2102static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2103 struct ixgbe_ring *rx_ring,
f4de00ed 2104 const int budget)
9a799d71 2105{
d2f4fbe2 2106 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2107#ifdef IXGBE_FCOE
f800326d 2108 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2109 int ddp_bytes;
2110 unsigned int mss = 0;
3d8fd385 2111#endif /* IXGBE_FCOE */
f800326d 2112 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2113
fdabfc8a 2114 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2115 union ixgbe_adv_rx_desc *rx_desc;
2116 struct sk_buff *skb;
f800326d
AD		 2117
2118 /* return some buffers to hardware, one at a time is too slow */
2119 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2120 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2121 cleaned_count = 0;
2122 }
2123
18806c9e 2124 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2125
124b74c1 2126 if (!rx_desc->wb.upper.status_error)
f800326d 2127 break;
9a799d71 2128
124b74c1 2129 /* This memory barrier is needed to keep us from reading
f800326d 2130 * any other fields out of the rx_desc until we know the
124b74c1 2131 * descriptor has been written back
f800326d 2132 */
124b74c1 2133 dma_rmb();
9a799d71 2134
18806c9e
AD		 2135 /* retrieve a buffer from the ring */
2136 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2137
18806c9e
AD		 2138 /* exit if we failed to retrieve a buffer */
2139 if (!skb)
2140 break;
9a799d71 2141
9a799d71 2142 cleaned_count++;
f8212f97 2143
f800326d
AD		 2144 /* place incomplete frames back on ring for completion */
2145 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2146 continue;
c267fc16 2147
f800326d
AD		 2148 /* verify the packet layout is correct */
2149 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2150 continue;
9a799d71 2151
d2f4fbe2
AV		 2152 /* probably a little skewed due to removing CRC */
2153 total_rx_bytes += skb->len;
d2f4fbe2 2154
8a0da21b
AD		 2155 /* populate checksum, timestamp, VLAN, and protocol */
2156 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2157
332d4a7d
YZ		 2158#ifdef IXGBE_FCOE
2159 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2160 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2161 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2162 /* include DDPed FCoE data */
2163 if (ddp_bytes > 0) {
2164 if (!mss) {
2165 mss = rx_ring->netdev->mtu -
2166 sizeof(struct fcoe_hdr) -
2167 sizeof(struct fc_frame_header) -
2168 sizeof(struct fcoe_crc_eof);
2169 if (mss > 512)
2170 mss &= ~511;
2171 }
2172 total_rx_bytes += ddp_bytes;
2173 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2174 mss);
2175 }
63d635b2
AD		 2176 if (!ddp_bytes) {
2177 dev_kfree_skb_any(skb);
f800326d 2178 continue;
63d635b2 2179 }
3d8fd385 2180 }
f800326d 2181
332d4a7d 2182#endif /* IXGBE_FCOE */
8a0da21b 2183 ixgbe_rx_skb(q_vector, skb);
9a799d71 2184
f800326d 2185 /* update budget accounting */
f4de00ed 2186 total_rx_packets++;
fdabfc8a 2187 }
9a799d71 2188
c267fc16
AD		 2189 u64_stats_update_begin(&rx_ring->syncp);
2190 rx_ring->stats.packets += total_rx_packets;
2191 rx_ring->stats.bytes += total_rx_bytes;
2192 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2193 q_vector->rx.total_packets += total_rx_packets;
2194 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2195
5a85e737 2196 return total_rx_packets;
9a799d71
AK		 2197}
2198
e0d1095a 2199#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2200/* must be called with local_bh_disable()d */
2201static int ixgbe_low_latency_recv(struct napi_struct *napi)
2202{
2203 struct ixgbe_q_vector *q_vector =
2204 container_of(napi, struct ixgbe_q_vector, napi);
2205 struct ixgbe_adapter *adapter = q_vector->adapter;
2206 struct ixgbe_ring *ring;
2207 int found = 0;
2208
2209 if (test_bit(__IXGBE_DOWN, &adapter->state))
2210 return LL_FLUSH_FAILED;
2211
2212 if (!ixgbe_qv_lock_poll(q_vector))
2213 return LL_FLUSH_BUSY;
2214
2215 ixgbe_for_each_ring(ring, q_vector->rx) {
2216 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2217#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2218 if (found)
2219 ring->stats.cleaned += found;
2220 else
2221 ring->stats.misses++;
2222#endif
5a85e737
ET		 2223 if (found)
2224 break;
2225 }
2226
2227 ixgbe_qv_unlock_poll(q_vector);
2228
2229 return found;
2230}
e0d1095a 2231#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2232
9a799d71
AK		 2233/**
2234 * ixgbe_configure_msix - Configure MSI-X hardware
2235 * @adapter: board private structure
2236 *
2237 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2238 * interrupts.
2239 **/
2240static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2241{
021230d4 2242 struct ixgbe_q_vector *q_vector;
49c7ffbe 2243 int v_idx;
021230d4 2244 u32 mask;
9a799d71 2245
8e34d1aa
AD		 2246 /* Populate MSIX to EITR Select */
2247 if (adapter->num_vfs > 32) {
b4f47a48 2248 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
8e34d1aa
AD		 2249 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2250 }
2251
4df10466
JB		 2252 /*
2253 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2254 * corresponding register.
2255 */
49c7ffbe 2256 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2257 struct ixgbe_ring *ring;
7a921c93 2258 q_vector = adapter->q_vector[v_idx];
021230d4 2259
a557928e 2260 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2261 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2262
a557928e 2263 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2264 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2265
fe49f04a 2266 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2267 }
2268
bd508178
AD		 2269 switch (adapter->hw.mac.type) {
2270 case ixgbe_mac_82598EB:
e8e26350 2271 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2272 v_idx);
bd508178
AD		 2273 break;
2274 case ixgbe_mac_82599EB:
b93a2226 2275 case ixgbe_mac_X540:
9a75a1ac
DS		 2276 case ixgbe_mac_X550:
2277 case ixgbe_mac_X550EM_x:
49425dfc 2278 case ixgbe_mac_x550em_a:
e8e26350 2279 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2280 break;
bd508178
AD		 2281 default:
2282 break;
2283 }
021230d4
AV		 2284 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2285
41fb9248 2286 /* set up to autoclear timer, and the vectors */
021230d4 2287 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2288 mask &= ~(IXGBE_EIMS_OTHER |
2289 IXGBE_EIMS_MAILBOX |
2290 IXGBE_EIMS_LSC);
2291
021230d4 2292 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2293}
2294
f494e8fa
AV		 2295enum latency_range {
2296 lowest_latency = 0,
2297 low_latency = 1,
2298 bulk_latency = 2,
2299 latency_invalid = 255
2300};
2301
2302/**
2303 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2304 * @q_vector: structure containing interrupt and ring information
2305 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2306 *
2307 * Stores a new ITR value based on packets and byte
2308 * counts during the last interrupt. The advantage of per interrupt
2309 * computation is faster updates and more accurate ITR for the current
2310 * traffic pattern. Constants in this function were computed
2311 * based on theoretical maximum wire speed and thresholds were set based
2312 * on testing data as well as attempting to minimize response time
2313 * while increasing bulk throughput.
2314 * this functionality is controlled by the InterruptThrottleRate module
2315 * parameter (see ixgbe_param.c)
2316 **/
bd198058
AD		 2317static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2318 struct ixgbe_ring_container *ring_container)
f494e8fa 2319{
bd198058
AD		 2320 int bytes = ring_container->total_bytes;
2321 int packets = ring_container->total_packets;
2322 u32 timepassed_us;
621bd70e 2323 u64 bytes_perint;
bd198058 2324 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2325
2326 if (packets == 0)
bd198058 2327 return;
f494e8fa
AV		 2328
2329 /* simple throttlerate management
621bd70e
AD		 2330 * 0-10MB/s lowest (100000 ints/s)
2331 * 10-20MB/s low (20000 ints/s)
8ac34f10 2332 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2333 */
2334 /* what was last interrupt timeslice? */
d5bf4f67 2335 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2336 if (timepassed_us == 0)
2337 return;
2338
f494e8fa
AV		 2339 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2340
2341 switch (itr_setting) {
2342 case lowest_latency:
621bd70e 2343 if (bytes_perint > 10)
bd198058 2344 itr_setting = low_latency;
f494e8fa
AV		 2345 break;
2346 case low_latency:
621bd70e 2347 if (bytes_perint > 20)
bd198058 2348 itr_setting = bulk_latency;
621bd70e 2349 else if (bytes_perint <= 10)
bd198058 2350 itr_setting = lowest_latency;
f494e8fa
AV		 2351 break;
2352 case bulk_latency:
621bd70e 2353 if (bytes_perint <= 20)
bd198058 2354 itr_setting = low_latency;
f494e8fa
AV		 2355 break;
2356 }
2357
bd198058
AD		 2358 /* clear work counters since we have the values we need */
2359 ring_container->total_bytes = 0;
2360 ring_container->total_packets = 0;
2361
2362 /* write updated itr to ring container */
2363 ring_container->itr = itr_setting;
f494e8fa
AV		 2364}
2365
509ee935
JB		 2366/**
2367 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2368 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2369 *
2370 * This function is made to be called by ethtool and by the driver
2371 * when it needs to update EITR registers at runtime. Hardware
2372 * specific quirks/differences are taken care of here.
2373 */
fe49f04a 2374void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2375{
fe49f04a 2376 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2377 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2378 int v_idx = q_vector->v_idx;
5d967eb7 2379 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2380
bd508178
AD		 2381 switch (adapter->hw.mac.type) {
2382 case ixgbe_mac_82598EB:
509ee935
JB		 2383 /* must write high and low 16 bits to reset counter */
2384 itr_reg |= (itr_reg << 16);
bd508178
AD		 2385 break;
2386 case ixgbe_mac_82599EB:
b93a2226 2387 case ixgbe_mac_X540:
9a75a1ac
DS		 2388 case ixgbe_mac_X550:
2389 case ixgbe_mac_X550EM_x:
49425dfc 2390 case ixgbe_mac_x550em_a:
509ee935
JB		 2391 /*
2392 * set the WDIS bit to not clear the timer bits and cause an
2393 * immediate assertion of the interrupt
2394 */
2395 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2396 break;
2397 default:
2398 break;
509ee935
JB		 2399 }
2400 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2401}
2402
bd198058 2403static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2404{
d5bf4f67 2405 u32 new_itr = q_vector->itr;
bd198058 2406 u8 current_itr;
f494e8fa 2407
bd198058
AD		 2408 ixgbe_update_itr(q_vector, &q_vector->tx);
2409 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2410
08c8833b 2411 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2412
2413 switch (current_itr) {
2414 /* counts and packets in update_itr are dependent on these numbers */
2415 case lowest_latency:
d5bf4f67 2416 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2417 break;
2418 case low_latency:
d5bf4f67 2419 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2420 break;
2421 case bulk_latency:
8ac34f10 2422 new_itr = IXGBE_12K_ITR;
f494e8fa 2423 break;
bd198058
AD		 2424 default:
2425 break;
f494e8fa
AV		 2426 }
2427
d5bf4f67 2428 if (new_itr != q_vector->itr) {
fe49f04a 2429 /* do an exponential smoothing */
d5bf4f67
ET		 2430 new_itr = (10 * new_itr * q_vector->itr) /
2431 ((9 * new_itr) + q_vector->itr);
509ee935 2432
bd198058 2433 /* save the algorithm value here */
5d967eb7 2434 q_vector->itr = new_itr;
fe49f04a
AD		 2435
2436 ixgbe_write_eitr(q_vector);
f494e8fa 2437 }
f494e8fa
AV		 2438}
2439
119fc60a 2440/**
de88eeeb 2441 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2442 * @adapter: pointer to adapter
119fc60a 2443 **/
f0f9778d 2444static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2445{
119fc60a
MC		 2446 struct ixgbe_hw *hw = &adapter->hw;
2447 u32 eicr = adapter->interrupt_event;
2448
f0f9778d 2449 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2450 return;
2451
f0f9778d
AD		 2452 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2453 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2454 return;
2455
2456 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2457
7ca647bd 2458 switch (hw->device_id) {
f0f9778d
AD		 2459 case IXGBE_DEV_ID_82599_T3_LOM:
2460 /*
2461 * Since the warning interrupt is for both ports
2462 * we don't have to check if:
2463 * - This interrupt wasn't for our port.
2464 * - We may have missed the interrupt so always have to
2465 * check if we got a LSC
2466 */
9a900eca 2467 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2468 !(eicr & IXGBE_EICR_LSC))
2469 return;
2470
2471 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2472 u32 speed;
f0f9778d 2473 bool link_up = false;
7ca647bd 2474
3d292265 2475 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2476
f0f9778d
AD		 2477 if (link_up)
2478 return;
2479 }
2480
2481 /* Check if this is not due to overtemp */
2482 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2483 return;
2484
2485 break;
7ca647bd 2486 default:
597f22d6
DS		 2487 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2488 return;
9a900eca 2489 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2490 return;
7ca647bd 2491 break;
119fc60a 2492 }
f44e751b 2493 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2494
2495 adapter->interrupt_event = 0;
119fc60a
MC		 2496}
2497
0befdb3e
JB		 2498static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2499{
2500 struct ixgbe_hw *hw = &adapter->hw;
2501
2502 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2503 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2504 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2505 /* write to clear the interrupt */
9a900eca 2506 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2507 }
2508}
cf8280ee 2509
4f51bf70
JK		 2510static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2511{
9a900eca
DS		 2512 struct ixgbe_hw *hw = &adapter->hw;
2513
4f51bf70
JK		 2514 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2515 return;
2516
2517 switch (adapter->hw.mac.type) {
2518 case ixgbe_mac_82599EB:
2519 /*
2520 * Need to check link state so complete overtemp check
2521 * on service task
2522 */
9a900eca
DS		 2523 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2524 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2525 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2526 adapter->interrupt_event = eicr;
2527 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2528 ixgbe_service_event_schedule(adapter);
2529 return;
2530 }
2531 return;
2532 case ixgbe_mac_X540:
2533 if (!(eicr & IXGBE_EICR_TS))
2534 return;
2535 break;
2536 default:
2537 return;
2538 }
2539
f44e751b 2540 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2541}
2542
45788d2a
DS		 2543static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2544{
2545 switch (hw->mac.type) {
2546 case ixgbe_mac_82598EB:
2547 if (hw->phy.type == ixgbe_phy_nl)
2548 return true;
2549 return false;
2550 case ixgbe_mac_82599EB:
2551 case ixgbe_mac_X550EM_x:
49425dfc 2552 case ixgbe_mac_x550em_a:
45788d2a
DS		 2553 switch (hw->mac.ops.get_media_type(hw)) {
2554 case ixgbe_media_type_fiber:
2555 case ixgbe_media_type_fiber_qsfp:
2556 return true;
2557 default:
2558 return false;
2559 }
2560 default:
2561 return false;
2562 }
2563}
2564
e8e26350
PW		 2565static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2566{
2567 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2568 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2569
4ccc650c
DS		 2570 if (!ixgbe_is_sfp(hw))
2571 return;
2572
2573 /* Later MAC's use different SDP */
2574 if (hw->mac.type >= ixgbe_mac_X540)
2575 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2576
2577 if (eicr & eicr_mask) {
73c4b7cd 2578 /* Clear the interrupt */
4ccc650c 2579 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2580 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2581 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2582 adapter->sfp_poll_time = 0;
7086400d
AD		 2583 ixgbe_service_event_schedule(adapter);
2584 }
73c4b7cd
AD		 2585 }
2586
4ccc650c
DS		 2587 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2588 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2589 /* Clear the interrupt */
9a900eca 2590 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2591 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2592 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2593 ixgbe_service_event_schedule(adapter);
2594 }
e8e26350
PW		 2595 }
2596}
2597
cf8280ee
JB		 2598static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2599{
2600 struct ixgbe_hw *hw = &adapter->hw;
2601
2602 adapter->lsc_int++;
2603 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2604 adapter->link_check_timeout = jiffies;
2605 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2606 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2607 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2608 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2609 }
2610}
2611
fe49f04a
AD		 2612static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2613 u64 qmask)
2614{
2615 u32 mask;
bd508178 2616 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2617
bd508178
AD		 2618 switch (hw->mac.type) {
2619 case ixgbe_mac_82598EB:
fe49f04a 2620 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2621 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2622 break;
2623 case ixgbe_mac_82599EB:
b93a2226 2624 case ixgbe_mac_X540:
9a75a1ac
DS		 2625 case ixgbe_mac_X550:
2626 case ixgbe_mac_X550EM_x:
49425dfc 2627 case ixgbe_mac_x550em_a:
fe49f04a 2628 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2629 if (mask)
2630 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2631 mask = (qmask >> 32);
bd508178
AD		 2632 if (mask)
2633 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2634 break;
2635 default:
2636 break;
fe49f04a
AD		 2637 }
2638 /* skip the flush */
2639}
2640
2641static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2642 u64 qmask)
fe49f04a
AD		 2643{
2644 u32 mask;
bd508178 2645 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2646
bd508178
AD		 2647 switch (hw->mac.type) {
2648 case ixgbe_mac_82598EB:
fe49f04a 2649 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2650 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2651 break;
2652 case ixgbe_mac_82599EB:
b93a2226 2653 case ixgbe_mac_X540:
9a75a1ac
DS		 2654 case ixgbe_mac_X550:
2655 case ixgbe_mac_X550EM_x:
49425dfc 2656 case ixgbe_mac_x550em_a:
fe49f04a 2657 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2658 if (mask)
2659 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2660 mask = (qmask >> 32);
bd508178
AD		 2661 if (mask)
2662 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2663 break;
2664 default:
2665 break;
fe49f04a
AD		 2666 }
2667 /* skip the flush */
2668}
2669
021230d4 2670/**
2c4af694
AD		 2671 * ixgbe_irq_enable - Enable default interrupt generation settings
2672 * @adapter: board private structure
021230d4 2673 **/
2c4af694
AD		 2674static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2675 bool flush)
9a799d71 2676{
9a900eca 2677 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2678 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2679
2c4af694
AD		 2680 /* don't reenable LSC while waiting for link */
2681 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2682 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2683
2c4af694 2684 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2685 switch (adapter->hw.mac.type) {
2686 case ixgbe_mac_82599EB:
9a900eca 2687 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2688 break;
2689 case ixgbe_mac_X540:
9a75a1ac
DS		 2690 case ixgbe_mac_X550:
2691 case ixgbe_mac_X550EM_x:
49425dfc 2692 case ixgbe_mac_x550em_a:
4f51bf70
JK		 2693 mask |= IXGBE_EIMS_TS;
2694 break;
2695 default:
2696 break;
2697 }
2c4af694 2698 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2699 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2700 switch (adapter->hw.mac.type) {
2701 case ixgbe_mac_82599EB:
9a900eca
DS		 2702 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2703 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2704 /* fall through */
858bc081 2705 case ixgbe_mac_X540:
9a75a1ac
DS		 2706 case ixgbe_mac_X550:
2707 case ixgbe_mac_X550EM_x:
49425dfc
MR		 2708 case ixgbe_mac_x550em_a:
2709 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
2d40cd17 2710 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
49425dfc 2711 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
cbd45ec7 2712 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2713 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2714 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2715 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2716 mask |= IXGBE_EIMS_MAILBOX;
2717 break;
2718 default:
2719 break;
9a799d71 2720 }
db0677fa 2721
2c4af694
AD		 2722 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2723 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2724 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2725
2c4af694
AD		 2726 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2727 if (queues)
2728 ixgbe_irq_enable_queues(adapter, ~0);
2729 if (flush)
2730 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2731}
2732
2c4af694 2733static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2734{
a65151ba 2735 struct ixgbe_adapter *adapter = data;
9a799d71 2736 struct ixgbe_hw *hw = &adapter->hw;
54037505 2737 u32 eicr;
91281fd3 2738
54037505
DS		 2739 /*
2740 * Workaround for Silicon errata. Use clear-by-write instead
2741 * of clear-by-read. Reading with EICS will return the
2742 * interrupt causes without clearing, which later be done
2743 * with the write to EICR.
2744 */
2745 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2746
2747 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2748 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2749 * the bits are high when ixgbe_msix_other is called. There is a race
2750 * condition otherwise which results in possible performance loss
2751 * especially if the ixgbe_msix_other interrupt is triggering
2752 * consistently (as it would when PPS is turned on for the X540 device)
2753 */
2754 eicr &= 0xFFFF0000;
2755
54037505 2756 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2757
cf8280ee
JB		 2758 if (eicr & IXGBE_EICR_LSC)
2759 ixgbe_check_lsc(adapter);
f0848276 2760
1cdd1ec8
GR		 2761 if (eicr & IXGBE_EICR_MAILBOX)
2762 ixgbe_msg_task(adapter);
efe3d3c8 2763
bd508178
AD		 2764 switch (hw->mac.type) {
2765 case ixgbe_mac_82599EB:
b93a2226 2766 case ixgbe_mac_X540:
9a75a1ac
DS		 2767 case ixgbe_mac_X550:
2768 case ixgbe_mac_X550EM_x:
49425dfc 2769 case ixgbe_mac_x550em_a:
597f22d6
DS		 2770 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2771 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2772 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2773 ixgbe_service_event_schedule(adapter);
2774 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2775 IXGBE_EICR_GPI_SDP0_X540);
2776 }
d773ce2d
DS		 2777 if (eicr & IXGBE_EICR_ECC) {
2778 e_info(link, "Received ECC Err, initiating reset\n");
2779 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2780 ixgbe_service_event_schedule(adapter);
2781 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2782 }
c4cf55e5
PWJ		 2783 /* Handle Flow Director Full threshold interrupt */
2784 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2785 int reinit_count = 0;
c4cf55e5 2786 int i;
c4cf55e5 2787 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2788 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2789 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2790 &ring->state))
2791 reinit_count++;
2792 }
2793 if (reinit_count) {
2794 /* no more flow director interrupts until after init */
2795 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2796 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2797 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2798 }
2799 }
f0f9778d 2800 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2801 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2802 break;
2803 default:
2804 break;
c4cf55e5 2805 }
f0848276 2806
bd508178 2807 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2808
db0677fa 2809 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2810 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 2811
7086400d 2812 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2813 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2814 ixgbe_irq_enable(adapter, false, false);
f0848276 2815
9a799d71 2816 return IRQ_HANDLED;
f0848276 2817}
91281fd3 2818
4ff7fb12 2819static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2820{
021230d4 2821 struct ixgbe_q_vector *q_vector = data;
91281fd3 2822
9b471446 2823 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2824
4ff7fb12 2825 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 2826 napi_schedule_irqoff(&q_vector->napi);
91281fd3 2827
9a799d71 2828 return IRQ_HANDLED;
91281fd3
AD		 2829}
2830
eb01b975
AD		 2831/**
2832 * ixgbe_poll - NAPI Rx polling callback
2833 * @napi: structure for representing this polling device
2834 * @budget: how many packets driver is allowed to clean
2835 *
2836 * This function is used for legacy and MSI, NAPI mode
2837 **/
8af3c33f 2838int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2839{
2840 struct ixgbe_q_vector *q_vector =
2841 container_of(napi, struct ixgbe_q_vector, napi);
2842 struct ixgbe_adapter *adapter = q_vector->adapter;
2843 struct ixgbe_ring *ring;
32b3e08f 2844 int per_ring_budget, work_done = 0;
eb01b975
AD		 2845 bool clean_complete = true;
2846
2847#ifdef CONFIG_IXGBE_DCA
2848 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2849 ixgbe_update_dca(q_vector);
2850#endif
2851
8220bbc1
AD		 2852 ixgbe_for_each_ring(ring, q_vector->tx) {
2853 if (!ixgbe_clean_tx_irq(q_vector, ring, budget))
2854 clean_complete = false;
2855 }
eb01b975 2856
5d6002b7
AD		 2857 /* Exit if we are called by netpoll or busy polling is active */
2858 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
5a85e737
ET		 2859 return budget;
2860
eb01b975
AD		 2861 /* attempt to distribute budget to each queue fairly, but don't allow
2862 * the budget to go below 1 because we'll exit polling */
2863 if (q_vector->rx.count > 1)
2864 per_ring_budget = max(budget/q_vector->rx.count, 1);
2865 else
2866 per_ring_budget = budget;
2867
32b3e08f
JB		 2868 ixgbe_for_each_ring(ring, q_vector->rx) {
2869 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2870 per_ring_budget);
2871
2872 work_done += cleaned;
8220bbc1
AD		 2873 if (cleaned >= per_ring_budget)
2874 clean_complete = false;
32b3e08f 2875 }
eb01b975 2876
5a85e737 2877 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2878 /* If all work not completed, return budget and keep polling */
2879 if (!clean_complete)
2880 return budget;
2881
2882 /* all work done, exit the polling mode */
32b3e08f 2883 napi_complete_done(napi, work_done);
eb01b975
AD		 2884 if (adapter->rx_itr_setting & 1)
2885 ixgbe_set_itr(q_vector);
2886 if (!test_bit(__IXGBE_DOWN, &adapter->state))
b4f47a48 2887 ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx));
eb01b975
AD		 2888
2889 return 0;
2890}
2891
021230d4
AV		 2892/**
2893 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2894 * @adapter: board private structure
2895 *
2896 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2897 * interrupts from the kernel.
2898 **/
2899static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2900{
2901 struct net_device *netdev = adapter->netdev;
207867f5 2902 int vector, err;
e8e9f696 2903 int ri = 0, ti = 0;
021230d4 2904
49c7ffbe 2905 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2906 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2907 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2908
4ff7fb12 2909 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2910 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2911 "%s-%s-%d", netdev->name, "TxRx", ri++);
2912 ti++;
2913 } else if (q_vector->rx.ring) {
9fe93afd 2914 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2915 "%s-%s-%d", netdev->name, "rx", ri++);
2916 } else if (q_vector->tx.ring) {
9fe93afd 2917 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2918 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2919 } else {
2920 /* skip this unused q_vector */
2921 continue;
32aa77a4 2922 }
207867f5
AD		 2923 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2924 q_vector->name, q_vector);
9a799d71 2925 if (err) {
396e799c 2926 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2927 "Error: %d\n", err);
021230d4 2928 goto free_queue_irqs;
9a799d71 2929 }
207867f5
AD		 2930 /* If Flow Director is enabled, set interrupt affinity */
2931 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2932 /* assign the mask for this irq */
2933 irq_set_affinity_hint(entry->vector,
de88eeeb 2934 &q_vector->affinity_mask);
207867f5 2935 }
9a799d71
AK		 2936 }
2937
021230d4 2938 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2939 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2940 if (err) {
de88eeeb 2941 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2942 goto free_queue_irqs;
9a799d71
AK		 2943 }
2944
9a799d71
AK		 2945 return 0;
2946
021230d4 2947free_queue_irqs:
207867f5
AD		 2948 while (vector) {
2949 vector--;
2950 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2951 NULL);
2952 free_irq(adapter->msix_entries[vector].vector,
2953 adapter->q_vector[vector]);
2954 }
021230d4
AV		 2955 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2956 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2957 kfree(adapter->msix_entries);
2958 adapter->msix_entries = NULL;
9a799d71
AK		 2959 return err;
2960}
2961
2962/**
021230d4 2963 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2964 * @irq: interrupt number
2965 * @data: pointer to a network interface device structure
9a799d71
AK		 2966 **/
2967static irqreturn_t ixgbe_intr(int irq, void *data)
2968{
a65151ba 2969 struct ixgbe_adapter *adapter = data;
9a799d71 2970 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2971 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2972 u32 eicr;
2973
54037505 2974 /*
24ddd967 2975 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2976 * before the read of EICR.
2977 */
2978 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2979
021230d4 2980 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2981 * therefore no explicit interrupt disable is necessary */
021230d4 2982 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2983 if (!eicr) {
6af3b9eb
ET		 2984 /*
2985 * shared interrupt alert!
f47cf66e 2986 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2987 * have disabled interrupts due to EIAM
2988 * finish the workaround of silicon errata on 82598. Unmask
2989 * the interrupt that we masked before the EICR read.
2990 */
2991 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2992 ixgbe_irq_enable(adapter, true, true);
9a799d71 2993 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2994 }
9a799d71 2995
cf8280ee
JB		 2996 if (eicr & IXGBE_EICR_LSC)
2997 ixgbe_check_lsc(adapter);
021230d4 2998
bd508178
AD		 2999 switch (hw->mac.type) {
3000 case ixgbe_mac_82599EB:
e8e26350 3001 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 3002 /* Fall through */
3003 case ixgbe_mac_X540:
9a75a1ac
DS		 3004 case ixgbe_mac_X550:
3005 case ixgbe_mac_X550EM_x:
49425dfc 3006 case ixgbe_mac_x550em_a:
d773ce2d
DS		 3007 if (eicr & IXGBE_EICR_ECC) {
3008 e_info(link, "Received ECC Err, initiating reset\n");
3009 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
3010 ixgbe_service_event_schedule(adapter);
3011 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3012 }
4f51bf70 3013 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 3014 break;
3015 default:
3016 break;
3017 }
e8e26350 3018
0befdb3e 3019 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 3020 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 3021 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 3022
b9f6ed2b 3023 /* would disable interrupts here but EIAM disabled it */
ef2662b2 3024 napi_schedule_irqoff(&q_vector->napi);
9a799d71 3025
6af3b9eb
ET		 3026 /*
3027 * re-enable link(maybe) and non-queue interrupts, no flush.
3028 * ixgbe_poll will re-enable the queue interrupts
3029 */
6af3b9eb
ET		 3030 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3031 ixgbe_irq_enable(adapter, false, false);
3032
9a799d71
AK		 3033 return IRQ_HANDLED;
3034}
3035
3036/**
3037 * ixgbe_request_irq - initialize interrupts
3038 * @adapter: board private structure
3039 *
3040 * Attempts to configure interrupts using the best available
3041 * capabilities of the hardware and kernel.
3042 **/
021230d4 3043static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 3044{
3045 struct net_device *netdev = adapter->netdev;
021230d4 3046 int err;
9a799d71 3047
4cc6df29 3048 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 3049 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 3050 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 3051 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 3052 netdev->name, adapter);
4cc6df29 3053 else
a0607fd3 3054 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 3055 netdev->name, adapter);
9a799d71 3056
de88eeeb 3057 if (err)
396e799c 3058 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 3059
9a799d71
AK		 3060 return err;
3061}
3062
3063static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3064{
49c7ffbe 3065 int vector;
9a799d71 3066
49c7ffbe
AD		 3067 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3068 free_irq(adapter->pdev->irq, adapter);
3069 return;
3070 }
4cc6df29 3071
49c7ffbe
AD		 3072 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3073 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3074 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3075
49c7ffbe
AD		 3076 /* free only the irqs that were actually requested */
3077 if (!q_vector->rx.ring && !q_vector->tx.ring)
3078 continue;
207867f5 3079
49c7ffbe
AD		 3080 /* clear the affinity_mask in the IRQ descriptor */
3081 irq_set_affinity_hint(entry->vector, NULL);
3082
3083 free_irq(entry->vector, q_vector);
9a799d71 3084 }
49c7ffbe
AD		 3085
3086 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3087}
3088
22d5a71b
JB		 3089/**
3090 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3091 * @adapter: board private structure
3092 **/
3093static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3094{
bd508178
AD		 3095 switch (adapter->hw.mac.type) {
3096 case ixgbe_mac_82598EB:
835462fc 3097 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3098 break;
3099 case ixgbe_mac_82599EB:
b93a2226 3100 case ixgbe_mac_X540:
9a75a1ac
DS		 3101 case ixgbe_mac_X550:
3102 case ixgbe_mac_X550EM_x:
49425dfc 3103 case ixgbe_mac_x550em_a:
835462fc
NS		 3104 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3105 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3107 break;
3108 default:
3109 break;
22d5a71b
JB		 3110 }
3111 IXGBE_WRITE_FLUSH(&adapter->hw);
3112 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3113 int vector;
3114
3115 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3116 synchronize_irq(adapter->msix_entries[vector].vector);
3117
3118 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3119 } else {
3120 synchronize_irq(adapter->pdev->irq);
3121 }
3122}
3123
9a799d71
AK		 3124/**
3125 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3126 *
3127 **/
3128static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3129{
d5bf4f67 3130 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3131
d5bf4f67 3132 ixgbe_write_eitr(q_vector);
9a799d71 3133
e8e26350
PW		 3134 ixgbe_set_ivar(adapter, 0, 0, 0);
3135 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3136
396e799c 3137 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3138}
3139
43e69bf0
AD		 3140/**
3141 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3142 * @adapter: board private structure
3143 * @ring: structure containing ring specific data
3144 *
3145 * Configure the Tx descriptor ring after a reset.
3146 **/
84418e3b
AD		 3147void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3148 struct ixgbe_ring *ring)
43e69bf0
AD		 3149{
3150 struct ixgbe_hw *hw = &adapter->hw;
3151 u64 tdba = ring->dma;
2f1860b8 3152 int wait_loop = 10;
b88c6de2 3153 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3154 u8 reg_idx = ring->reg_idx;
43e69bf0 3155
2f1860b8 3156 /* disable queue to avoid issues while updating state */
b88c6de2 3157 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3158 IXGBE_WRITE_FLUSH(hw);
3159
43e69bf0 3160 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3161 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3162 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3163 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3164 ring->count * sizeof(union ixgbe_adv_tx_desc));
3165 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3166 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3167 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3168
b88c6de2
AD		 3169 /*
3170 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3171 * higher than 1 when:
3172 * - ITR is 0 as it could cause false TX hangs
3173 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3174 *
3175 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3176 * to or less than the number of on chip descriptors, which is
3177 * currently 40.
3178 */
67da097e 3179 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b4f47a48 3180 txdctl |= 1u << 16; /* WTHRESH = 1 */
b88c6de2 3181 else
b4f47a48 3182 txdctl |= 8u << 16; /* WTHRESH = 8 */
b88c6de2 3183
e954b374
AD		 3184 /*
3185 * Setting PTHRESH to 32 both improves performance
3186 * and avoids a TX hang with DFP enabled
3187 */
b4f47a48 3188 txdctl |= (1u << 8) | /* HTHRESH = 1 */
b88c6de2 3189 32; /* PTHRESH = 32 */
2f1860b8
AD		 3190
3191 /* reinitialize flowdirector state */
39cb681b 3192 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3193 ring->atr_sample_rate = adapter->atr_sample_rate;
3194 ring->atr_count = 0;
3195 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3196 } else {
3197 ring->atr_sample_rate = 0;
3198 }
2f1860b8 3199
fd786b7b
AD		 3200 /* initialize XPS */
3201 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3202 struct ixgbe_q_vector *q_vector = ring->q_vector;
3203
3204 if (q_vector)
2a47fa45 3205 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3206 &q_vector->affinity_mask,
3207 ring->queue_index);
3208 }
3209
c84d324c
JF		 3210 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3211
2f1860b8 3212 /* enable queue */
2f1860b8
AD		 3213 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3214
3215 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3216 if (hw->mac.type == ixgbe_mac_82598EB &&
3217 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3218 return;
3219
3220 /* poll to verify queue is enabled */
3221 do {
032b4325 3222 usleep_range(1000, 2000);
2f1860b8
AD		 3223 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3224 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3225 if (!wait_loop)
3226 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3227}
3228
120ff942
AD		 3229static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3230{
3231 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3232 u32 rttdcs, mtqc;
8b1c0b24 3233 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3234
3235 if (hw->mac.type == ixgbe_mac_82598EB)
3236 return;
3237
3238 /* disable the arbiter while setting MTQC */
3239 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3240 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3241 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3242
3243 /* set transmit pool layout */
671c0adb
AD		 3244 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3245 mtqc = IXGBE_MTQC_VT_ENA;
3246 if (tcs > 4)
3247 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3248 else if (tcs > 1)
3249 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3250 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3251 mtqc |= IXGBE_MTQC_32VF;
3252 else
3253 mtqc |= IXGBE_MTQC_64VF;
3254 } else {
3255 if (tcs > 4)
3256 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3257 else if (tcs > 1)
3258 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3259 else
671c0adb
AD		 3260 mtqc = IXGBE_MTQC_64Q_1PB;
3261 }
120ff942 3262
671c0adb 3263 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3264
671c0adb
AD		 3265 /* Enable Security TX Buffer IFG for multiple pb */
3266 if (tcs) {
3267 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3268 sectx |= IXGBE_SECTX_DCB;
3269 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3270 }
3271
3272 /* re-enable the arbiter */
3273 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3274 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3275}
3276
9a799d71 3277/**
3a581073 3278 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3279 * @adapter: board private structure
3280 *
3281 * Configure the Tx unit of the MAC after a reset.
3282 **/
3283static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3284{
2f1860b8
AD		 3285 struct ixgbe_hw *hw = &adapter->hw;
3286 u32 dmatxctl;
43e69bf0 3287 u32 i;
9a799d71 3288
2f1860b8
AD		 3289 ixgbe_setup_mtqc(adapter);
3290
3291 if (hw->mac.type != ixgbe_mac_82598EB) {
3292 /* DMATXCTL.EN must be before Tx queues are enabled */
3293 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3294 dmatxctl |= IXGBE_DMATXCTL_TE;
3295 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3296 }
3297
9a799d71 3298 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3299 for (i = 0; i < adapter->num_tx_queues; i++)
3300 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3301}
3302
3ebe8fde
AD		 3303static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3304 struct ixgbe_ring *ring)
3305{
3306 struct ixgbe_hw *hw = &adapter->hw;
3307 u8 reg_idx = ring->reg_idx;
3308 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3309
3310 srrctl |= IXGBE_SRRCTL_DROP_EN;
3311
3312 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3313}
3314
3315static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3316 struct ixgbe_ring *ring)
3317{
3318 struct ixgbe_hw *hw = &adapter->hw;
3319 u8 reg_idx = ring->reg_idx;
3320 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3321
3322 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3323
3324 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3325}
3326
3327#ifdef CONFIG_IXGBE_DCB
3328void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3329#else
3330static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3331#endif
3332{
3333 int i;
3334 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3335
3336 if (adapter->ixgbe_ieee_pfc)
3337 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3338
3339 /*
3340 * We should set the drop enable bit if:
3341 * SR-IOV is enabled
3342 * or
3343 * Number of Rx queues > 1 and flow control is disabled
3344 *
3345 * This allows us to avoid head of line blocking for security
3346 * and performance reasons.
3347 */
3348 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3349 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3350 for (i = 0; i < adapter->num_rx_queues; i++)
3351 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3352 } else {
3353 for (i = 0; i < adapter->num_rx_queues; i++)
3354 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3355 }
3356}
3357
e8e26350 3358#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3359
a6616b42 3360static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3361 struct ixgbe_ring *rx_ring)
cc41ac7c 3362{
45e9baa5 3363 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3364 u32 srrctl;
bf29ee6c 3365 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3366
45e9baa5
AD		 3367 if (hw->mac.type == ixgbe_mac_82598EB) {
3368 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3369
45e9baa5
AD		 3370 /*
3371 * if VMDq is not active we must program one srrctl register
3372 * per RSS queue since we have enabled RDRXCTL.MVMEN
3373 */
3374 reg_idx &= mask;
3375 }
cc41ac7c 3376
45e9baa5
AD		 3377 /* configure header buffer length, needed for RSC */
3378 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3379
45e9baa5 3380 /* configure the packet buffer length */
f800326d 3381 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3382
3383 /* configure descriptor type */
f800326d 3384 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3385
45e9baa5 3386 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3387}
9a799d71 3388
dfaf891d 3389/**
a897a2ad 3390 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3391 * @adapter: device handle
3392 *
3393 * - 82598/82599/X540: 128
3394 * - X550(non-SRIOV mode): 512
3395 * - X550(SRIOV mode): 64
3396 */
7f276efb 3397u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3398{
3399 if (adapter->hw.mac.type < ixgbe_mac_X550)
3400 return 128;
3401 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3402 return 64;
3403 else
3404 return 512;
3405}
3406
3407/**
a897a2ad 3408 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3409 * @adapter: device handle
3410 *
3411 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3412 */
1c7cf078 3413void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3414{
dfaf891d 3415 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3416 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3417 u32 reta = 0;
dfaf891d
VZ		 3418 u32 indices_multi;
3419 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3420
0f9b232b 3421 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3422 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3423 * indices.
3424 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3425 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3426 */
3427 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3428 indices_multi = 0x11;
3429 else
3430 indices_multi = 0x1;
3431
dfaf891d
VZ		 3432 /* Write redirection table to HW */
3433 for (i = 0; i < reta_entries; i++) {
3434 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3435 if ((i & 3) == 3) {
3436 if (i < 128)
3437 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3438 else
3439 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3440 reta);
dfaf891d 3441 reta = 0;
0f9b232b
DS		 3442 }
3443 }
3444}
3445
dfaf891d 3446/**
a897a2ad 3447 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3448 * @adapter: device handle
3449 *
3450 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3451 */
3452static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3453{
dfaf891d 3454 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3455 struct ixgbe_hw *hw = &adapter->hw;
3456 u32 vfreta = 0;
dfaf891d
VZ		 3457 unsigned int pf_pool = adapter->num_vfs;
3458
3459 /* Write redirection table to HW */
3460 for (i = 0; i < reta_entries; i++) {
3461 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3462 if ((i & 3) == 3) {
3463 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3464 vfreta);
3465 vfreta = 0;
3466 }
3467 }
3468}
3469
3470static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3471{
3472 struct ixgbe_hw *hw = &adapter->hw;
3473 u32 i, j;
3474 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3475 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3476
3477 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3478 * make full use of any rings they may have. We will use the
3479 * PSRTYPE register to control how many rings we use within the PF.
3480 */
3481 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3482 rss_i = 2;
3483
3484 /* Fill out hash function seeds */
3485 for (i = 0; i < 10; i++)
3486 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3487
3488 /* Fill out redirection table */
3489 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3490
3491 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3492 if (j == rss_i)
3493 j = 0;
3494
3495 adapter->rss_indir_tbl[i] = j;
3496 }
3497
3498 ixgbe_store_reta(adapter);
3499}
3500
3501static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3502{
3503 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3504 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3505 unsigned int pf_pool = adapter->num_vfs;
3506 int i, j;
3507
3508 /* Fill out hash function seeds */
3509 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3510 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3511 adapter->rss_key[i]);
0f9b232b
DS		 3512
3513 /* Fill out the redirection table */
3514 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3515 if (j == rss_i)
05abb126 3516 j = 0;
dfaf891d
VZ		 3517
3518 adapter->rss_indir_tbl[i] = j;
05abb126 3519 }
dfaf891d
VZ		 3520
3521 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3522}
3523
3524static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3525{
3526 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3527 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3528 u32 rxcsum;
0cefafad 3529
05abb126
AD		 3530 /* Disable indicating checksum in descriptor, enables RSS hash */
3531 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3532 rxcsum |= IXGBE_RXCSUM_PCSD;
3533 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3534
671c0adb 3535 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3536 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3537 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3538 } else {
671c0adb
AD		 3539 u8 tcs = netdev_get_num_tc(adapter->netdev);
3540
3541 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3542 if (tcs > 4)
3543 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3544 else if (tcs > 1)
3545 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3546 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3547 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3548 else
671c0adb
AD		 3549 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3550 } else {
3551 if (tcs > 4)
8b1c0b24 3552 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3553 else if (tcs > 1)
3554 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3555 else
3556 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3557 }
0cefafad
JB		 3558 }
3559
05abb126 3560 /* Perform hash on these packet types */
d1b849b9
DS		 3561 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3562 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3563 IXGBE_MRQC_RSS_FIELD_IPV6 |
3564 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3565
ef6afc0c 3566 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3567 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3568 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3569 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3570
dfaf891d 3571 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3572 if ((hw->mac.type >= ixgbe_mac_X550) &&
3573 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3574 unsigned int pf_pool = adapter->num_vfs;
3575
3576 /* Enable VF RSS mode */
3577 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3578 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3579
3580 /* Setup RSS through the VF registers */
dfaf891d 3581 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3582 vfmrqc = IXGBE_MRQC_RSSEN;
3583 vfmrqc |= rss_field;
3584 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3585 } else {
dfaf891d 3586 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3587 mrqc |= rss_field;
3588 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3589 }
0cefafad
JB		 3590}
3591
bb5a9ad2
NS		 3592/**
3593 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3594 * @adapter: address of board private structure
3595 * @index: index of ring to set
bb5a9ad2 3596 **/
082757af 3597static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3598 struct ixgbe_ring *ring)
bb5a9ad2 3599{
bb5a9ad2 3600 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3601 u32 rscctrl;
bf29ee6c 3602 u8 reg_idx = ring->reg_idx;
7367096a 3603
7d637bcc 3604 if (!ring_is_rsc_enabled(ring))
7367096a 3605 return;
bb5a9ad2 3606
7367096a 3607 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3608 rscctrl |= IXGBE_RSCCTL_RSCEN;
3609 /*
3610 * we must limit the number of descriptors so that the
3611 * total size of max desc * buf_len is not greater
642c680e 3612 * than 65536
bb5a9ad2 3613 */
f800326d 3614 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3615 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3616}
3617
9e10e045
AD		 3618#define IXGBE_MAX_RX_DESC_POLL 10
3619static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3620 struct ixgbe_ring *ring)
3621{
3622 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3623 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3624 u32 rxdctl;
bf29ee6c 3625 u8 reg_idx = ring->reg_idx;
9e10e045 3626
b0483c8f
MR		 3627 if (ixgbe_removed(hw->hw_addr))
3628 return;
9e10e045
AD		 3629 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3630 if (hw->mac.type == ixgbe_mac_82598EB &&
3631 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3632 return;
3633
3634 do {
032b4325 3635 usleep_range(1000, 2000);
9e10e045
AD		 3636 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3637 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3638
3639 if (!wait_loop) {
3640 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3641 "the polling period\n", reg_idx);
3642 }
3643}
3644
2d39d576
YZ		 3645void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3646 struct ixgbe_ring *ring)
3647{
3648 struct ixgbe_hw *hw = &adapter->hw;
3649 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3650 u32 rxdctl;
3651 u8 reg_idx = ring->reg_idx;
3652
b0483c8f
MR		 3653 if (ixgbe_removed(hw->hw_addr))
3654 return;
2d39d576
YZ		 3655 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3656 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3657
3658 /* write value back with RXDCTL.ENABLE bit cleared */
3659 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3660
3661 if (hw->mac.type == ixgbe_mac_82598EB &&
3662 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3663 return;
3664
3665 /* the hardware may take up to 100us to really disable the rx queue */
3666 do {
3667 udelay(10);
3668 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3669 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3670
3671 if (!wait_loop) {
3672 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3673 "the polling period\n", reg_idx);
3674 }
3675}
3676
84418e3b
AD		 3677void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3678 struct ixgbe_ring *ring)
acd37177
AD		 3679{
3680 struct ixgbe_hw *hw = &adapter->hw;
3681 u64 rdba = ring->dma;
9e10e045 3682 u32 rxdctl;
bf29ee6c 3683 u8 reg_idx = ring->reg_idx;
acd37177 3684
9e10e045
AD		 3685 /* disable queue to avoid issues while updating state */
3686 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3687 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3688
acd37177
AD		 3689 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3690 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3691 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3692 ring->count * sizeof(union ixgbe_adv_rx_desc));
8b75451b
NP		 3693 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3694 IXGBE_WRITE_FLUSH(hw);
3695
acd37177
AD		 3696 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3697 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3698 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3699
3700 ixgbe_configure_srrctl(adapter, ring);
3701 ixgbe_configure_rscctl(adapter, ring);
3702
3703 if (hw->mac.type == ixgbe_mac_82598EB) {
3704 /*
3705 * enable cache line friendly hardware writes:
3706 * PTHRESH=32 descriptors (half the internal cache),
3707 * this also removes ugly rx_no_buffer_count increment
3708 * HTHRESH=4 descriptors (to minimize latency on fetch)
3709 * WTHRESH=8 burst writeback up to two cache lines
3710 */
3711 rxdctl &= ~0x3FFFFF;
3712 rxdctl |= 0x080420;
3713 }
3714
3715 /* enable receive descriptor ring */
3716 rxdctl |= IXGBE_RXDCTL_ENABLE;
3717 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3718
3719 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3720 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3721}
3722
48654521
AD		 3723static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3724{
3725 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3726 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3727 u16 pool;
48654521
AD		 3728
3729 /* PSRTYPE must be initialized in non 82598 adapters */
3730 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3731 IXGBE_PSRTYPE_UDPHDR |
3732 IXGBE_PSRTYPE_IPV4HDR |
48654521 3733 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3734 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3735
3736 if (hw->mac.type == ixgbe_mac_82598EB)
3737 return;
3738
fbe7ca7f 3739 if (rss_i > 3)
b4f47a48 3740 psrtype |= 2u << 29;
fbe7ca7f 3741 else if (rss_i > 1)
b4f47a48 3742 psrtype |= 1u << 29;
48654521 3743
2a47fa45
JF		 3744 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3745 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3746}
3747
f5b4a52e
AD		 3748static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3749{
3750 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3751 u32 reg_offset, vf_shift;
435b19f6 3752 u32 gcr_ext, vmdctl;
de4c7f65 3753 int i;
f5b4a52e
AD		 3754
3755 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3756 return;
3757
3758 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3759 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3760 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3761 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3762 vmdctl |= IXGBE_VT_CTL_REPLEN;
3763 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3764
1d9c0bfd
AD		 3765 vf_shift = VMDQ_P(0) % 32;
3766 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3767
3768 /* Enable only the PF's pool for Tx/Rx */
3e973dc4 3769 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(vf_shift, 31));
435b19f6 3770 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3e973dc4 3771 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(vf_shift, 31));
435b19f6 3772 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3773 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3774 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3775
3776 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3777 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 3778
16369564
AD		 3779 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3780 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3781
f5b4a52e
AD		 3782 /*
3783 * Set up VF register offsets for selected VT Mode,
3784 * i.e. 32 or 64 VFs for SR-IOV
3785 */
73079ea0
AD		 3786 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3787 case IXGBE_82599_VMDQ_8Q_MASK:
3788 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3789 break;
3790 case IXGBE_82599_VMDQ_4Q_MASK:
3791 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3792 break;
3793 default:
3794 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3795 break;
3796 }
3797
f5b4a52e
AD		 3798 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3799
de4c7f65 3800 for (i = 0; i < adapter->num_vfs; i++) {
77f192af
ET		 3801 /* configure spoof checking */
3802 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
3803 adapter->vfinfo[i].spoofchk_enabled);
e65ce0d3
VZ		 3804
3805 /* Enable/Disable RSS query feature */
3806 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3807 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3808 }
f5b4a52e
AD		 3809}
3810
477de6ed 3811static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3812{
9a799d71
AK		 3813 struct ixgbe_hw *hw = &adapter->hw;
3814 struct net_device *netdev = adapter->netdev;
3815 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3816 struct ixgbe_ring *rx_ring;
3817 int i;
3818 u32 mhadd, hlreg0;
48654521 3819
63f39bd1 3820#ifdef IXGBE_FCOE
477de6ed
AD		 3821 /* adjust max frame to be able to do baby jumbo for FCoE */
3822 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3823 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3824 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3825
477de6ed 3826#endif /* IXGBE_FCOE */
872844dd
AD		 3827
3828 /* adjust max frame to be at least the size of a standard frame */
3829 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3830 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3831
477de6ed
AD		 3832 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3833 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3834 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3835 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3836
3837 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3838 }
3839
3840 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3841 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3842 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3843 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3844
0cefafad
JB		 3845 /*
3846 * Setup the HW Rx Head and Tail Descriptor Pointers and
3847 * the Base and Length of the Rx Descriptor Ring
3848 */
9a799d71 3849 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3850 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3851 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3852 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3853 else
7d637bcc 3854 clear_ring_rsc_enabled(rx_ring);
477de6ed 3855 }
477de6ed
AD		 3856}
3857
7367096a
AD		 3858static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3859{
3860 struct ixgbe_hw *hw = &adapter->hw;
3861 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3862
3863 switch (hw->mac.type) {
3864 case ixgbe_mac_82598EB:
3865 /*
3866 * For VMDq support of different descriptor types or
3867 * buffer sizes through the use of multiple SRRCTL
3868 * registers, RDRXCTL.MVMEN must be set to 1
3869 *
3870 * also, the manual doesn't mention it clearly but DCA hints
3871 * will only use queue 0's tags unless this bit is set. Side
3872 * effects of setting this bit are only that SRRCTL must be
3873 * fully programmed [0..15]
3874 */
3875 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3876 break;
052a1a72
MR		 3877 case ixgbe_mac_X550:
3878 case ixgbe_mac_X550EM_x:
49425dfc 3879 case ixgbe_mac_x550em_a:
f961ddae
MR		 3880 if (adapter->num_vfs)
3881 rdrxctl |= IXGBE_RDRXCTL_PSP;
3882 /* fall through for older HW */
7367096a 3883 case ixgbe_mac_82599EB:
b93a2226 3884 case ixgbe_mac_X540:
7367096a
AD		 3885 /* Disable RSC for ACK packets */
3886 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3887 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3888 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3889 /* hardware requires some bits to be set by default */
3890 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3891 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3892 break;
3893 default:
3894 /* We should do nothing since we don't know this hardware */
3895 return;
3896 }
3897
3898 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3899}
3900
477de6ed
AD		 3901/**
3902 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3903 * @adapter: board private structure
3904 *
3905 * Configure the Rx unit of the MAC after a reset.
3906 **/
3907static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3908{
3909 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3910 int i;
6dcc28b9 3911 u32 rxctrl, rfctl;
477de6ed
AD		 3912
3913 /* disable receives while setting up the descriptors */
1f9ac57c 3914 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3915
3916 ixgbe_setup_psrtype(adapter);
7367096a 3917 ixgbe_setup_rdrxctl(adapter);
477de6ed 3918
6dcc28b9
JK		 3919 /* RSC Setup */
3920 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3921 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3922 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3923 rfctl |= IXGBE_RFCTL_RSC_DIS;
3924 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3925
9e10e045 3926 /* Program registers for the distribution of queues */
f5b4a52e 3927 ixgbe_setup_mrqc(adapter);
f5b4a52e 3928
477de6ed
AD		 3929 /* set_rx_buffer_len must be called before ring initialization */
3930 ixgbe_set_rx_buffer_len(adapter);
3931
3932 /*
3933 * Setup the HW Rx Head and Tail Descriptor Pointers and
3934 * the Base and Length of the Rx Descriptor Ring
3935 */
9e10e045
AD		 3936 for (i = 0; i < adapter->num_rx_queues; i++)
3937 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3938
1f9ac57c 3939 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3940 /* disable drop enable for 82598 parts */
3941 if (hw->mac.type == ixgbe_mac_82598EB)
3942 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3943
3944 /* enable all receives */
3945 rxctrl |= IXGBE_RXCTRL_RXEN;
3946 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3947}
3948
80d5c368
PM		 3949static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3950 __be16 proto, u16 vid)
068c89b0
DS		 3951{
3952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3953 struct ixgbe_hw *hw = &adapter->hw;
3954
3955 /* add VID to filter table */
18be4fce
AD		 3956 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3957 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
3958
f62bbb5e 3959 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3960
3961 return 0;
068c89b0
DS		 3962}
3963
e1d0a2af
AD		 3964static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3965{
3966 u32 vlvf;
3967 int idx;
3968
3969 /* short cut the special case */
3970 if (vlan == 0)
3971 return 0;
3972
3973 /* Search for the vlan id in the VLVF entries */
3974 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3975 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3976 if ((vlvf & VLAN_VID_MASK) == vlan)
3977 break;
3978 }
3979
3980 return idx;
3981}
3982
3983void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3984{
3985 struct ixgbe_hw *hw = &adapter->hw;
3986 u32 bits, word;
3987 int idx;
3988
3989 idx = ixgbe_find_vlvf_entry(hw, vid);
3990 if (!idx)
3991 return;
3992
3993 /* See if any other pools are set for this VLAN filter
3994 * entry other than the PF.
3995 */
3996 word = idx * 2 + (VMDQ_P(0) / 32);
b4f47a48 3997 bits = ~BIT(VMDQ_P(0) % 32);
e1d0a2af
AD		 3998 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
3999
4000 /* Disable the filter so this falls into the default pool. */
4001 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4002 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4003 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4004 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4005 }
4006}
4007
80d5c368
PM		 4008static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4009 __be16 proto, u16 vid)
068c89b0
DS		 4010{
4011 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4012 struct ixgbe_hw *hw = &adapter->hw;
4013
068c89b0 4014 /* remove VID from filter table */
18be4fce 4015 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
e1d0a2af
AD		 4016 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4017
f62bbb5e 4018 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 4019
4020 return 0;
068c89b0
DS		 4021}
4022
f62bbb5e
JG		 4023/**
4024 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4025 * @adapter: driver data
4026 */
4027static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4028{
4029 struct ixgbe_hw *hw = &adapter->hw;
4030 u32 vlnctrl;
5f6c0181
JB		 4031 int i, j;
4032
4033 switch (hw->mac.type) {
4034 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4035 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4036 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4037 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4038 break;
4039 case ixgbe_mac_82599EB:
b93a2226 4040 case ixgbe_mac_X540:
9a75a1ac
DS		 4041 case ixgbe_mac_X550:
4042 case ixgbe_mac_X550EM_x:
49425dfc 4043 case ixgbe_mac_x550em_a:
5f6c0181 4044 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4045 struct ixgbe_ring *ring = adapter->rx_ring[i];
4046
4047 if (ring->l2_accel_priv)
4048 continue;
4049 j = ring->reg_idx;
5f6c0181
JB		 4050 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4051 vlnctrl &= ~IXGBE_RXDCTL_VME;
4052 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4053 }
4054 break;
4055 default:
4056 break;
4057 }
4058}
4059
4060/**
f62bbb5e 4061 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4062 * @adapter: driver data
4063 */
f62bbb5e 4064static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4065{
4066 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4067 u32 vlnctrl;
5f6c0181
JB		 4068 int i, j;
4069
4070 switch (hw->mac.type) {
4071 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4072 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4073 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4074 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4075 break;
4076 case ixgbe_mac_82599EB:
b93a2226 4077 case ixgbe_mac_X540:
9a75a1ac
DS		 4078 case ixgbe_mac_X550:
4079 case ixgbe_mac_X550EM_x:
49425dfc 4080 case ixgbe_mac_x550em_a:
5f6c0181 4081 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4082 struct ixgbe_ring *ring = adapter->rx_ring[i];
4083
4084 if (ring->l2_accel_priv)
4085 continue;
4086 j = ring->reg_idx;
5f6c0181
JB		 4087 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4088 vlnctrl |= IXGBE_RXDCTL_VME;
4089 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4090 }
4091 break;
4092 default:
4093 break;
4094 }
4095}
4096
16369564
AD		 4097static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4098{
4099 struct ixgbe_hw *hw = &adapter->hw;
4100 u32 vlnctrl, i;
4101
4102 switch (hw->mac.type) {
4103 case ixgbe_mac_82599EB:
4104 case ixgbe_mac_X540:
4105 case ixgbe_mac_X550:
4106 case ixgbe_mac_X550EM_x:
49425dfc 4107 case ixgbe_mac_x550em_a:
16369564
AD		 4108 default:
4109 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4110 break;
4111 /* fall through */
4112 case ixgbe_mac_82598EB:
4113 /* legacy case, we can just disable VLAN filtering */
4114 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4115 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4116 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4117 return;
4118 }
4119
4120 /* We are already in VLAN promisc, nothing to do */
4121 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4122 return;
4123
4124 /* Set flag so we don't redo unnecessary work */
4125 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4126
4127 /* Add PF to all active pools */
4128 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4129 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4130 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4131
b4f47a48 4132 vlvfb |= BIT(VMDQ_P(0) % 32);
16369564
AD		 4133 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4134 }
4135
4136 /* Set all bits in the VLAN filter table array */
4137 for (i = hw->mac.vft_size; i--;)
4138 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4139}
4140
4141#define VFTA_BLOCK_SIZE 8
4142static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4143{
4144 struct ixgbe_hw *hw = &adapter->hw;
4145 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4146 u32 vid_start = vfta_offset * 32;
4147 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4148 u32 i, vid, word, bits;
4149
4150 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4151 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4152
4153 /* pull VLAN ID from VLVF */
4154 vid = vlvf & VLAN_VID_MASK;
4155
4156 /* only concern outselves with a certain range */
4157 if (vid < vid_start || vid >= vid_end)
4158 continue;
4159
4160 if (vlvf) {
4161 /* record VLAN ID in VFTA */
b4f47a48 4162 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
16369564
AD		 4163
4164 /* if PF is part of this then continue */
4165 if (test_bit(vid, adapter->active_vlans))
4166 continue;
4167 }
4168
4169 /* remove PF from the pool */
4170 word = i * 2 + VMDQ_P(0) / 32;
b4f47a48 4171 bits = ~BIT(VMDQ_P(0) % 32);
16369564
AD		 4172 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4173 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4174 }
4175
4176 /* extract values from active_vlans and write back to VFTA */
4177 for (i = VFTA_BLOCK_SIZE; i--;) {
4178 vid = (vfta_offset + i) * 32;
4179 word = vid / BITS_PER_LONG;
4180 bits = vid % BITS_PER_LONG;
4181
4182 vfta[i] |= adapter->active_vlans[word] >> bits;
4183
4184 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4185 }
4186}
4187
4188static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4189{
4190 struct ixgbe_hw *hw = &adapter->hw;
4191 u32 vlnctrl, i;
4192
4193 switch (hw->mac.type) {
4194 case ixgbe_mac_82599EB:
4195 case ixgbe_mac_X540:
4196 case ixgbe_mac_X550:
4197 case ixgbe_mac_X550EM_x:
49425dfc 4198 case ixgbe_mac_x550em_a:
16369564
AD		 4199 default:
4200 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4201 break;
4202 /* fall through */
4203 case ixgbe_mac_82598EB:
4204 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4205 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
4206 vlnctrl |= IXGBE_VLNCTRL_VFE;
4207 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4208 return;
4209 }
4210
4211 /* We are not in VLAN promisc, nothing to do */
4212 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4213 return;
4214
4215 /* Set flag so we don't redo unnecessary work */
4216 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4217
4218 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4219 ixgbe_scrub_vfta(adapter, i);
4220}
4221
9a799d71
AK		 4222static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4223{
06bb1c39 4224 u16 vid = 1;
9a799d71 4225
80d5c368 4226 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e 4227
06bb1c39 4228 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4229 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4230}
4231
b335e75b
JK		 4232/**
4233 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4234 * @netdev: network interface device structure
4235 *
4236 * Writes multicast address list to the MTA hash table.
4237 * Returns: -ENOMEM on failure
4238 * 0 on no addresses written
4239 * X on writing X addresses to MTA
4240 **/
4241static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4242{
4243 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4244 struct ixgbe_hw *hw = &adapter->hw;
4245
4246 if (!netif_running(netdev))
4247 return 0;
4248
4249 if (hw->mac.ops.update_mc_addr_list)
4250 hw->mac.ops.update_mc_addr_list(hw, netdev);
4251 else
4252 return -ENOMEM;
4253
4254#ifdef CONFIG_PCI_IOV
5d7daa35 4255 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4256#endif
4257
4258 return netdev_mc_count(netdev);
4259}
4260
5d7daa35
JK		 4261#ifdef CONFIG_PCI_IOV
4262void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4263{
c9f53e63 4264 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4265 struct ixgbe_hw *hw = &adapter->hw;
4266 int i;
c9f53e63
AD		 4267
4268 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4269 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4270
4271 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4272 hw->mac.ops.set_rar(hw, i,
4273 mac_table->addr,
4274 mac_table->pool,
5d7daa35
JK		 4275 IXGBE_RAH_AV);
4276 else
4277 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4278 }
4279}
5d7daa35 4280
c9f53e63 4281#endif
5d7daa35
JK		 4282static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4283{
c9f53e63 4284 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4285 struct ixgbe_hw *hw = &adapter->hw;
4286 int i;
5d7daa35 4287
c9f53e63
AD		 4288 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4289 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4290 continue;
4291
4292 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4293
4294 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4295 hw->mac.ops.set_rar(hw, i,
4296 mac_table->addr,
4297 mac_table->pool,
4298 IXGBE_RAH_AV);
4299 else
4300 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4301 }
4302}
4303
4304static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4305{
c9f53e63 4306 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4307 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4308 int i;
5d7daa35 4309
c9f53e63
AD		 4310 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4311 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4312 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4313 }
c9f53e63 4314
5d7daa35
JK		 4315 ixgbe_sync_mac_table(adapter);
4316}
4317
c9f53e63 4318static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4319{
c9f53e63 4320 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4321 struct ixgbe_hw *hw = &adapter->hw;
4322 int i, count = 0;
4323
c9f53e63
AD		 4324 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4325 /* do not count default RAR as available */
4326 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4327 continue;
4328
4329 /* only count unused and addresses that belong to us */
4330 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4331 if (mac_table->pool != pool)
4332 continue;
4333 }
4334
4335 count++;
5d7daa35 4336 }
c9f53e63 4337
5d7daa35
JK		 4338 return count;
4339}
4340
4341/* this function destroys the first RAR entry */
c9f53e63 4342static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4343{
c9f53e63 4344 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4345 struct ixgbe_hw *hw = &adapter->hw;
4346
c9f53e63
AD		 4347 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4348 mac_table->pool = VMDQ_P(0);
4349
4350 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4351
4352 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4353 IXGBE_RAH_AV);
4354}
4355
c9f53e63
AD		 4356int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4357 const u8 *addr, u16 pool)
5d7daa35 4358{
c9f53e63 4359 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4360 struct ixgbe_hw *hw = &adapter->hw;
4361 int i;
4362
4363 if (is_zero_ether_addr(addr))
4364 return -EINVAL;
4365
c9f53e63
AD		 4366 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4367 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4368 continue;
c9f53e63
AD		 4369
4370 ether_addr_copy(mac_table->addr, addr);
4371 mac_table->pool = pool;
4372
4373 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4374 IXGBE_MAC_STATE_IN_USE;
4375
5d7daa35 4376 ixgbe_sync_mac_table(adapter);
c9f53e63 4377
5d7daa35
JK		 4378 return i;
4379 }
c9f53e63 4380
5d7daa35
JK		 4381 return -ENOMEM;
4382}
4383
c9f53e63
AD		 4384int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4385 const u8 *addr, u16 pool)
5d7daa35 4386{
c9f53e63 4387 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4388 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4389 int i;
5d7daa35
JK		 4390
4391 if (is_zero_ether_addr(addr))
4392 return -EINVAL;
4393
c9f53e63
AD		 4394 /* search table for addr, if found clear IN_USE flag and sync */
4395 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4396 /* we can only delete an entry if it is in use */
4397 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4398 continue;
4399 /* we only care about entries that belong to the given pool */
4400 if (mac_table->pool != pool)
4401 continue;
4402 /* we only care about a specific MAC address */
4403 if (!ether_addr_equal(addr, mac_table->addr))
4404 continue;
4405
4406 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4407 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4408
4409 ixgbe_sync_mac_table(adapter);
4410
4411 return 0;
5d7daa35 4412 }
c9f53e63 4413
5d7daa35
JK		 4414 return -ENOMEM;
4415}
2850062a
AD		 4416/**
4417 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4418 * @netdev: network interface device structure
4419 *
4420 * Writes unicast address list to the RAR table.
4421 * Returns: -ENOMEM on failure/insufficient address space
4422 * 0 on no addresses written
4423 * X on writing X addresses to the RAR table
4424 **/
5d7daa35 4425static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4426{
4427 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4428 int count = 0;
4429
4430 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4431 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4432 return -ENOMEM;
4433
95447461 4434 if (!netdev_uc_empty(netdev)) {
2850062a 4435 struct netdev_hw_addr *ha;
2850062a 4436 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4437 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4438 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4439 count++;
4440 }
4441 }
2850062a
AD		 4442 return count;
4443}
4444
0f079d22
AD		 4445static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4446{
4447 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4448 int ret;
4449
4450 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4451
4452 return min_t(int, ret, 0);
4453}
4454
4455static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4456{
4457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4458
4459 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4460
4461 return 0;
4462}
4463
9a799d71 4464/**
2c5645cf 4465 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4466 * @netdev: network interface device structure
4467 *
2c5645cf
CL		 4468 * The set_rx_method entry point is called whenever the unicast/multicast
4469 * address list or the network interface flags are updated. This routine is
4470 * responsible for configuring the hardware for proper unicast, multicast and
4471 * promiscuous mode.
9a799d71 4472 **/
7f870475 4473void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4474{
4475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4476 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4477 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
0c5a6166 4478 netdev_features_t features = netdev->features;
2850062a 4479 int count;
9a799d71
AK		 4480
4481 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4482 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4483
f5dc442b 4484 /* set all bits that we expect to always be set */
3f2d1c0f 4485 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4486 fctrl |= IXGBE_FCTRL_BAM;
4487 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4488 fctrl |= IXGBE_FCTRL_PMCF;
4489
2850062a
AD		 4490 /* clear the bits we are changing the status of */
4491 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4492 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4493 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4494 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4495 vmolr |= IXGBE_VMOLR_MPE;
0c5a6166 4496 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
9a799d71 4497 } else {
746b9f02
PM		 4498 if (netdev->flags & IFF_ALLMULTI) {
4499 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4500 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4501 }
e433ea1f 4502 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4503 }
4504
4505 /*
4506 * Write addresses to available RAR registers, if there is not
4507 * sufficient space to store all the addresses then enable
4508 * unicast promiscuous mode
4509 */
0f079d22 4510 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4511 fctrl |= IXGBE_FCTRL_UPE;
4512 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4513 }
4514
cf78959c
ET		 4515 /* Write addresses to the MTA, if the attempt fails
4516 * then we should just turn on promiscuous mode so
4517 * that we can at least receive multicast traffic
4518 */
b335e75b
JK		 4519 count = ixgbe_write_mc_addr_list(netdev);
4520 if (count < 0) {
4521 fctrl |= IXGBE_FCTRL_MPE;
4522 vmolr |= IXGBE_VMOLR_MPE;
4523 } else if (count) {
4524 vmolr |= IXGBE_VMOLR_ROMPE;
4525 }
1d9c0bfd
AD		 4526
4527 if (hw->mac.type != ixgbe_mac_82598EB) {
4528 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4529 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4530 IXGBE_VMOLR_ROPE);
1d9c0bfd 4531 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4532 }
4533
3f2d1c0f 4534 /* This is useful for sniffing bad packets. */
0c5a6166 4535 if (features & NETIF_F_RXALL) {
3f2d1c0f
BG		 4536 /* UPE and MPE will be handled by normal PROMISC logic
4537 * in e1000e_set_rx_mode */
4538 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4539 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4540 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4541
4542 fctrl &= ~(IXGBE_FCTRL_DPF);
4543 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4544 }
4545
2850062a 4546 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4547
0c5a6166 4548 if (features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4549 ixgbe_vlan_strip_enable(adapter);
4550 else
4551 ixgbe_vlan_strip_disable(adapter);
0c5a6166
AD		 4552
4553 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
4554 ixgbe_vlan_promisc_disable(adapter);
4555 else
4556 ixgbe_vlan_promisc_enable(adapter);
9a799d71
AK		 4557}
4558
021230d4
AV		 4559static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4560{
4561 int q_idx;
021230d4 4562
5a85e737
ET		 4563 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4564 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4565 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4566 }
021230d4
AV		 4567}
4568
4569static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4570{
4571 int q_idx;
021230d4 4572
5a85e737 4573 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4574 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4575 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4576 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4577 usleep_range(1000, 20000);
5a85e737
ET		 4578 }
4579 }
021230d4
AV		 4580}
4581
67359c3c
MR		 4582static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4583{
4584 switch (adapter->hw.mac.type) {
4585 case ixgbe_mac_X550:
4586 case ixgbe_mac_X550EM_x:
49425dfc 4587 case ixgbe_mac_x550em_a:
67359c3c 4588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
67359c3c 4589 adapter->vxlan_port = 0;
67359c3c
MR		 4590 break;
4591 default:
4592 break;
4593 }
4594}
4595
7a6b6f51 4596#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4597/**
2f90b865
AD		 4598 * ixgbe_configure_dcb - Configure DCB hardware
4599 * @adapter: ixgbe adapter struct
4600 *
4601 * This is called by the driver on open to configure the DCB hardware.
4602 * This is also called by the gennetlink interface when reconfiguring
4603 * the DCB state.
4604 */
4605static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4606{
4607 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4608 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4609
67ebd791
AD		 4610 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4611 if (hw->mac.type == ixgbe_mac_82598EB)
4612 netif_set_gso_max_size(adapter->netdev, 65536);
4613 return;
4614 }
4615
4616 if (hw->mac.type == ixgbe_mac_82598EB)
4617 netif_set_gso_max_size(adapter->netdev, 32768);
4618
971060b1 4619#ifdef IXGBE_FCOE
b120818e
JF		 4620 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4621 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4622#endif
b120818e
JF		 4623
4624 /* reconfigure the hardware */
4625 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4626 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4627 DCB_TX_CONFIG);
4628 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4629 DCB_RX_CONFIG);
4630 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4631 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4632 ixgbe_dcb_hw_ets(&adapter->hw,
4633 adapter->ixgbe_ieee_ets,
4634 max_frame);
4635 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4636 adapter->ixgbe_ieee_pfc->pfc_en,
4637 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4638 }
8187cd48
JF		 4639
4640 /* Enable RSS Hash per TC */
4641 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4642 u32 msb = 0;
4643 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4644
d411a936
AD		 4645 while (rss_i) {
4646 msb++;
4647 rss_i >>= 1;
4648 }
8187cd48 4649
4ae63730
AD		 4650 /* write msb to all 8 TCs in one write */
4651 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4652 }
2f90b865 4653}
9da712d2
JF		 4654#endif
4655
4656/* Additional bittime to account for IXGBE framing */
4657#define IXGBE_ETH_FRAMING 20
4658
49ce9c2c 4659/**
9da712d2
JF		 4660 * ixgbe_hpbthresh - calculate high water mark for flow control
4661 *
4662 * @adapter: board private structure to calculate for
49ce9c2c 4663 * @pb: packet buffer to calculate
9da712d2
JF		 4664 */
4665static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4666{
4667 struct ixgbe_hw *hw = &adapter->hw;
4668 struct net_device *dev = adapter->netdev;
4669 int link, tc, kb, marker;
4670 u32 dv_id, rx_pba;
4671
4672 /* Calculate max LAN frame size */
4673 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4674
4675#ifdef IXGBE_FCOE
4676 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4677 if ((dev->features & NETIF_F_FCOE_MTU) &&
4678 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4679 (pb == ixgbe_fcoe_get_tc(adapter)))
4680 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4681#endif
e5776620 4682
9da712d2
JF		 4683 /* Calculate delay value for device */
4684 switch (hw->mac.type) {
4685 case ixgbe_mac_X540:
9a75a1ac
DS		 4686 case ixgbe_mac_X550:
4687 case ixgbe_mac_X550EM_x:
49425dfc 4688 case ixgbe_mac_x550em_a:
9da712d2
JF		 4689 dv_id = IXGBE_DV_X540(link, tc);
4690 break;
4691 default:
4692 dv_id = IXGBE_DV(link, tc);
4693 break;
4694 }
4695
4696 /* Loopback switch introduces additional latency */
4697 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4698 dv_id += IXGBE_B2BT(tc);
4699
4700 /* Delay value is calculated in bit times convert to KB */
4701 kb = IXGBE_BT2KB(dv_id);
4702 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4703
4704 marker = rx_pba - kb;
4705
4706 /* It is possible that the packet buffer is not large enough
4707 * to provide required headroom. In this case throw an error
4708 * to user and a do the best we can.
4709 */
4710 if (marker < 0) {
4711 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4712 "headroom to support flow control."
4713 "Decrease MTU or number of traffic classes\n", pb);
4714 marker = tc + 1;
4715 }
4716
4717 return marker;
4718}
4719
49ce9c2c 4720/**
9da712d2
JF		 4721 * ixgbe_lpbthresh - calculate low water mark for for flow control
4722 *
4723 * @adapter: board private structure to calculate for
49ce9c2c 4724 * @pb: packet buffer to calculate
9da712d2 4725 */
e5776620 4726static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4727{
4728 struct ixgbe_hw *hw = &adapter->hw;
4729 struct net_device *dev = adapter->netdev;
4730 int tc;
4731 u32 dv_id;
4732
4733 /* Calculate max LAN frame size */
4734 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4735
e5776620
JK		 4736#ifdef IXGBE_FCOE
4737 /* FCoE traffic class uses FCOE jumbo frames */
4738 if ((dev->features & NETIF_F_FCOE_MTU) &&
4739 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4740 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4741 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4742#endif
4743
9da712d2
JF		 4744 /* Calculate delay value for device */
4745 switch (hw->mac.type) {
4746 case ixgbe_mac_X540:
9a75a1ac
DS		 4747 case ixgbe_mac_X550:
4748 case ixgbe_mac_X550EM_x:
49425dfc 4749 case ixgbe_mac_x550em_a:
9da712d2
JF		 4750 dv_id = IXGBE_LOW_DV_X540(tc);
4751 break;
4752 default:
4753 dv_id = IXGBE_LOW_DV(tc);
4754 break;
4755 }
4756
4757 /* Delay value is calculated in bit times convert to KB */
4758 return IXGBE_BT2KB(dv_id);
4759}
4760
4761/*
4762 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4763 */
4764static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4765{
4766 struct ixgbe_hw *hw = &adapter->hw;
4767 int num_tc = netdev_get_num_tc(adapter->netdev);
4768 int i;
4769
4770 if (!num_tc)
4771 num_tc = 1;
4772
9da712d2
JF		 4773 for (i = 0; i < num_tc; i++) {
4774 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4775 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4776
4777 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4778 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4779 hw->fc.low_water[i] = 0;
9da712d2 4780 }
e5776620
JK		 4781
4782 for (; i < MAX_TRAFFIC_CLASS; i++)
4783 hw->fc.high_water[i] = 0;
9da712d2
JF		 4784}
4785
80605c65
JF		 4786static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4787{
80605c65 4788 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4789 int hdrm;
4790 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4791
4792 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4793 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4794 hdrm = 32 << adapter->fdir_pballoc;
4795 else
4796 hdrm = 0;
80605c65 4797
f7e1027f 4798 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4799 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4800}
4801
e4911d57
AD		 4802static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4803{
4804 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4805 struct hlist_node *node2;
e4911d57
AD		 4806 struct ixgbe_fdir_filter *filter;
4807
4808 spin_lock(&adapter->fdir_perfect_lock);
4809
4810 if (!hlist_empty(&adapter->fdir_filter_list))
4811 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4812
b67bfe0d 4813 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4814 &adapter->fdir_filter_list, fdir_node) {
4815 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4816 &filter->filter,
4817 filter->sw_idx,
4818 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4819 IXGBE_FDIR_DROP_QUEUE :
4820 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4821 }
4822
4823 spin_unlock(&adapter->fdir_perfect_lock);
4824}
4825
2a47fa45
JF		 4826static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4827 struct ixgbe_adapter *adapter)
4828{
4829 struct ixgbe_hw *hw = &adapter->hw;
4830 u32 vmolr;
4831
4832 /* No unicast promiscuous support for VMDQ devices. */
4833 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4834 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4835
4836 /* clear the affected bit */
4837 vmolr &= ~IXGBE_VMOLR_MPE;
4838
4839 if (dev->flags & IFF_ALLMULTI) {
4840 vmolr |= IXGBE_VMOLR_MPE;
4841 } else {
4842 vmolr |= IXGBE_VMOLR_ROMPE;
4843 hw->mac.ops.update_mc_addr_list(hw, dev);
4844 }
5d7daa35 4845 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4846 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4847}
4848
2a47fa45
JF		 4849static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4850{
4851 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4852 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4853 struct ixgbe_hw *hw = &adapter->hw;
4854 u16 pool = vadapter->pool;
4855 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4856 IXGBE_PSRTYPE_UDPHDR |
4857 IXGBE_PSRTYPE_IPV4HDR |
4858 IXGBE_PSRTYPE_L2HDR |
4859 IXGBE_PSRTYPE_IPV6HDR;
4860
4861 if (hw->mac.type == ixgbe_mac_82598EB)
4862 return;
4863
4864 if (rss_i > 3)
b4f47a48 4865 psrtype |= 2u << 29;
2a47fa45 4866 else if (rss_i > 1)
b4f47a48 4867 psrtype |= 1u << 29;
2a47fa45
JF		 4868
4869 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4870}
4871
4872/**
4873 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4874 * @rx_ring: ring to free buffers from
4875 **/
4876static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4877{
4878 struct device *dev = rx_ring->dev;
4879 unsigned long size;
4880 u16 i;
4881
4882 /* ring already cleared, nothing to do */
4883 if (!rx_ring->rx_buffer_info)
4884 return;
4885
4886 /* Free all the Rx ring sk_buffs */
4887 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4888 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4889
2a47fa45
JF		 4890 if (rx_buffer->skb) {
4891 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4892 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4893 dma_unmap_page(dev,
4894 IXGBE_CB(skb)->dma,
4895 ixgbe_rx_bufsz(rx_ring),
4896 DMA_FROM_DEVICE);
2a47fa45 4897 dev_kfree_skb(skb);
4d2fcfbc 4898 rx_buffer->skb = NULL;
2a47fa45 4899 }
18cb652a
AD		 4900
4901 if (!rx_buffer->page)
4902 continue;
4903
4904 dma_unmap_page(dev, rx_buffer->dma,
4905 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4906 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4907
2a47fa45
JF		 4908 rx_buffer->page = NULL;
4909 }
4910
4911 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4912 memset(rx_ring->rx_buffer_info, 0, size);
4913
4914 /* Zero out the descriptor ring */
4915 memset(rx_ring->desc, 0, rx_ring->size);
4916
4917 rx_ring->next_to_alloc = 0;
4918 rx_ring->next_to_clean = 0;
4919 rx_ring->next_to_use = 0;
4920}
4921
4922static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4923 struct ixgbe_ring *rx_ring)
4924{
4925 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4926 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4927
4928 /* shutdown specific queue receive and wait for dma to settle */
4929 ixgbe_disable_rx_queue(adapter, rx_ring);
4930 usleep_range(10000, 20000);
b4f47a48 4931 ixgbe_irq_disable_queues(adapter, BIT_ULL(index));
2a47fa45
JF		 4932 ixgbe_clean_rx_ring(rx_ring);
4933 rx_ring->l2_accel_priv = NULL;
4934}
4935
ae72c8d0
JF		 4936static int ixgbe_fwd_ring_down(struct net_device *vdev,
4937 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4938{
4939 struct ixgbe_adapter *adapter = accel->real_adapter;
4940 unsigned int rxbase = accel->rx_base_queue;
4941 unsigned int txbase = accel->tx_base_queue;
4942 int i;
4943
4944 netif_tx_stop_all_queues(vdev);
4945
4946 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4947 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4948 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4949 }
4950
4951 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4952 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4953 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4954 }
4955
4956
4957 return 0;
4958}
4959
4960static int ixgbe_fwd_ring_up(struct net_device *vdev,
4961 struct ixgbe_fwd_adapter *accel)
4962{
4963 struct ixgbe_adapter *adapter = accel->real_adapter;
4964 unsigned int rxbase, txbase, queues;
4965 int i, baseq, err = 0;
4966
4967 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4968 return 0;
4969
4970 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4971 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4972 accel->pool, adapter->num_rx_pools,
4973 baseq, baseq + adapter->num_rx_queues_per_pool,
4974 adapter->fwd_bitmask);
4975
4976 accel->netdev = vdev;
4977 accel->rx_base_queue = rxbase = baseq;
4978 accel->tx_base_queue = txbase = baseq;
4979
4980 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4981 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4982
4983 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4984 adapter->rx_ring[rxbase + i]->netdev = vdev;
4985 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4986 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4987 }
4988
4989 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4990 adapter->tx_ring[txbase + i]->netdev = vdev;
4991 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4992 }
4993
4994 queues = min_t(unsigned int,
4995 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4996 err = netif_set_real_num_tx_queues(vdev, queues);
4997 if (err)
4998 goto fwd_queue_err;
4999
2a47fa45
JF		 5000 err = netif_set_real_num_rx_queues(vdev, queues);
5001 if (err)
5002 goto fwd_queue_err;
5003
5004 if (is_valid_ether_addr(vdev->dev_addr))
5005 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
5006
5007 ixgbe_fwd_psrtype(accel);
5008 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
5009 return err;
5010fwd_queue_err:
5011 ixgbe_fwd_ring_down(vdev, accel);
5012 return err;
5013}
5014
5015static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5016{
5017 struct net_device *upper;
5018 struct list_head *iter;
5019 int err;
5020
5021 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5022 if (netif_is_macvlan(upper)) {
5023 struct macvlan_dev *dfwd = netdev_priv(upper);
5024 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
5025
5026 if (dfwd->fwd_priv) {
5027 err = ixgbe_fwd_ring_up(upper, vadapter);
5028 if (err)
5029 continue;
5030 }
5031 }
5032 }
5033}
5034
9a799d71
AK		 5035static void ixgbe_configure(struct ixgbe_adapter *adapter)
5036{
d2f5e7f3
AS		 5037 struct ixgbe_hw *hw = &adapter->hw;
5038
80605c65 5039 ixgbe_configure_pb(adapter);
7a6b6f51 5040#ifdef CONFIG_IXGBE_DCB
67ebd791 5041 ixgbe_configure_dcb(adapter);
2f90b865 5042#endif
b35d4d42
AD		 5043 /*
5044 * We must restore virtualization before VLANs or else
5045 * the VLVF registers will not be populated
5046 */
5047 ixgbe_configure_virtualization(adapter);
9a799d71 5048
4c1d7b4b 5049 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 5050 ixgbe_restore_vlan(adapter);
5051
d2f5e7f3
AS		 5052 switch (hw->mac.type) {
5053 case ixgbe_mac_82599EB:
5054 case ixgbe_mac_X540:
5055 hw->mac.ops.disable_rx_buff(hw);
5056 break;
5057 default:
5058 break;
5059 }
5060
c4cf55e5 5061 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5062 ixgbe_init_fdir_signature_82599(&adapter->hw,
5063 adapter->fdir_pballoc);
e4911d57
AD		 5064 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5065 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5066 adapter->fdir_pballoc);
5067 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5068 }
4c1d7b4b 5069
d2f5e7f3
AS		 5070 switch (hw->mac.type) {
5071 case ixgbe_mac_82599EB:
5072 case ixgbe_mac_X540:
5073 hw->mac.ops.enable_rx_buff(hw);
5074 break;
5075 default:
5076 break;
5077 }
5078
9de7605e
MR		 5079#ifdef CONFIG_IXGBE_DCA
5080 /* configure DCA */
5081 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5082 ixgbe_setup_dca(adapter);
5083#endif /* CONFIG_IXGBE_DCA */
5084
7c8ae65a
AD		 5085#ifdef IXGBE_FCOE
5086 /* configure FCoE L2 filters, redirection table, and Rx control */
5087 ixgbe_configure_fcoe(adapter);
5088
5089#endif /* IXGBE_FCOE */
9a799d71
AK		 5090 ixgbe_configure_tx(adapter);
5091 ixgbe_configure_rx(adapter);
2a47fa45 5092 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5093}
5094
0ecc061d 5095/**
e8e26350
PW		 5096 * ixgbe_sfp_link_config - set up SFP+ link
5097 * @adapter: pointer to private adapter struct
5098 **/
5099static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5100{
7086400d 5101 /*
52f33af8 5102 * We are assuming the worst case scenario here, and that
7086400d
AD		 5103 * is that an SFP was inserted/removed after the reset
5104 * but before SFP detection was enabled. As such the best
5105 * solution is to just start searching as soon as we start
5106 */
5107 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5108 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5109
7086400d 5110 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5111 adapter->sfp_poll_time = 0;
e8e26350
PW		 5112}
5113
5114/**
5115 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5116 * @hw: pointer to private hardware struct
5117 *
5118 * Returns 0 on success, negative on failure
5119 **/
e8e26350 5120static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5121{
3d292265
JH		 5122 u32 speed;
5123 bool autoneg, link_up = false;
a1e869de 5124 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5125
5126 if (hw->mac.ops.check_link)
3d292265 5127 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5128
5129 if (ret)
e90dd264 5130 return ret;
0ecc061d 5131
3d292265
JH		 5132 speed = hw->phy.autoneg_advertised;
5133 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5134 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5135 &autoneg);
0ecc061d 5136 if (ret)
e90dd264 5137 return ret;
0ecc061d 5138
8620a103 5139 if (hw->mac.ops.setup_link)
fd0326f2 5140 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5141
0ecc061d
PWJ		 5142 return ret;
5143}
5144
a34bcfff 5145static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5146{
9a799d71 5147 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5148 u32 gpie = 0;
9a799d71 5149
9b471446 5150 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5151 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5152 IXGBE_GPIE_OCD;
5153 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5154 /*
5155 * use EIAM to auto-mask when MSI-X interrupt is asserted
5156 * this saves a register write for every interrupt
5157 */
5158 switch (hw->mac.type) {
5159 case ixgbe_mac_82598EB:
5160 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5161 break;
9b471446 5162 case ixgbe_mac_82599EB:
b93a2226 5163 case ixgbe_mac_X540:
9a75a1ac
DS		 5164 case ixgbe_mac_X550:
5165 case ixgbe_mac_X550EM_x:
49425dfc 5166 case ixgbe_mac_x550em_a:
b93a2226 5167 default:
9b471446
JB		 5168 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5169 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5170 break;
5171 }
5172 } else {
021230d4
AV		 5173 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5174 * specifically only auto mask tx and rx interrupts */
5175 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5176 }
9a799d71 5177
a34bcfff
AD		 5178 /* XXX: to interrupt immediately for EICS writes, enable this */
5179 /* gpie |= IXGBE_GPIE_EIMEN; */
5180
5181 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5182 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5183
5184 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5185 case IXGBE_82599_VMDQ_8Q_MASK:
5186 gpie |= IXGBE_GPIE_VTMODE_16;
5187 break;
5188 case IXGBE_82599_VMDQ_4Q_MASK:
5189 gpie |= IXGBE_GPIE_VTMODE_32;
5190 break;
5191 default:
5192 gpie |= IXGBE_GPIE_VTMODE_64;
5193 break;
5194 }
119fc60a
MC		 5195 }
5196
5fdd31f9 5197 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5198 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5199 switch (adapter->hw.mac.type) {
5200 case ixgbe_mac_82599EB:
9a900eca 5201 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5202 break;
f3df98ec
DS		 5203 default:
5204 break;
5205 }
5206 }
5fdd31f9 5207
a34bcfff
AD		 5208 /* Enable fan failure interrupt */
5209 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5210 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5211
a023bbd0
DS		 5212 switch (hw->mac.type) {
5213 case ixgbe_mac_82599EB:
5214 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5215 break;
5216 case ixgbe_mac_X550EM_x:
49425dfc 5217 case ixgbe_mac_x550em_a:
a023bbd0
DS		 5218 gpie |= IXGBE_SDP0_GPIEN_X540;
5219 break;
5220 default:
5221 break;
2698b208 5222 }
a34bcfff
AD		 5223
5224 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5225}
5226
c7ccde0f 5227static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5228{
5229 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5230 int err;
a34bcfff
AD		 5231 u32 ctrl_ext;
5232
5233 ixgbe_get_hw_control(adapter);
5234 ixgbe_setup_gpie(adapter);
e8e26350 5235
9a799d71
AK		 5236 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5237 ixgbe_configure_msix(adapter);
5238 else
5239 ixgbe_configure_msi_and_legacy(adapter);
5240
ec74a471
ET		 5241 /* enable the optics for 82599 SFP+ fiber */
5242 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5243 hw->mac.ops.enable_tx_laser(hw);
5244
961fac88
DS		 5245 if (hw->phy.ops.set_phy_power)
5246 hw->phy.ops.set_phy_power(hw, true);
5247
4e857c58 5248 smp_mb__before_atomic();
9a799d71 5249 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5250 ixgbe_napi_enable_all(adapter);
5251
73c4b7cd
AD		 5252 if (ixgbe_is_sfp(hw)) {
5253 ixgbe_sfp_link_config(adapter);
5254 } else {
5255 err = ixgbe_non_sfp_link_config(hw);
5256 if (err)
5257 e_err(probe, "link_config FAILED %d\n", err);
5258 }
5259
021230d4
AV		 5260 /* clear any pending interrupts, may auto mask */
5261 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5262 ixgbe_irq_enable(adapter, true, true);
9a799d71 5263
bf069c97
DS		 5264 /*
5265 * If this adapter has a fan, check to see if we had a failure
5266 * before we enabled the interrupt.
5267 */
5268 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5269 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5270 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5271 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5272 }
5273
9a799d71
AK		 5274 /* bring the link up in the watchdog, this could race with our first
5275 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5276 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5277 adapter->link_check_timeout = jiffies;
7086400d 5278 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5279
5280 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5281 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5282 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5283 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5284}
5285
d4f80882
AV		 5286void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5287{
5288 WARN_ON(in_interrupt());
7086400d
AD		 5289 /* put off any impending NetWatchDogTimeout */
5290 adapter->netdev->trans_start = jiffies;
5291
d4f80882 5292 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5293 usleep_range(1000, 2000);
d4f80882 5294 ixgbe_down(adapter);
5809a1ae
GR		 5295 /*
5296 * If SR-IOV enabled then wait a bit before bringing the adapter
5297 * back up to give the VFs time to respond to the reset. The
5298 * two second wait is based upon the watchdog timer cycle in
5299 * the VF driver.
5300 */
5301 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5302 msleep(2000);
d4f80882
AV		 5303 ixgbe_up(adapter);
5304 clear_bit(__IXGBE_RESETTING, &adapter->state);
5305}
5306
c7ccde0f 5307void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5308{
5309 /* hardware has been reset, we need to reload some things */
5310 ixgbe_configure(adapter);
5311
c7ccde0f 5312 ixgbe_up_complete(adapter);
9a799d71
AK		 5313}
5314
5315void ixgbe_reset(struct ixgbe_adapter *adapter)
5316{
c44ade9e 5317 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5318 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5319 int err;
5320
b0483c8f
MR		 5321 if (ixgbe_removed(hw->hw_addr))
5322 return;
7086400d
AD		 5323 /* lock SFP init bit to prevent race conditions with the watchdog */
5324 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5325 usleep_range(1000, 2000);
5326
5327 /* clear all SFP and link config related flags while holding SFP_INIT */
5328 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5329 IXGBE_FLAG2_SFP_NEEDS_RESET);
5330 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5331
8ca783ab 5332 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5333 switch (err) {
5334 case 0:
5335 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5336 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5337 break;
5338 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5339 e_dev_err("master disable timed out\n");
da4dd0f7 5340 break;
794caeb2
PWJ		 5341 case IXGBE_ERR_EEPROM_VERSION:
5342 /* We are running on a pre-production device, log a warning */
849c4542 5343 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5344 "Please be aware there may be issues associated with "
849c4542
ET		 5345 "your hardware. If you are experiencing problems "
5346 "please contact your Intel or hardware "
5347 "representative who provided you with this "
5348 "hardware.\n");
794caeb2 5349 break;
da4dd0f7 5350 default:
849c4542 5351 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5352 }
9a799d71 5353
7086400d 5354 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5355
5356 /* flush entries out of MAC table */
5d7daa35 5357 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5358 __dev_uc_unsync(netdev, NULL);
5359
5360 /* do not flush user set addresses */
c9f53e63 5361 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5362
5363 /* update SAN MAC vmdq pool selection */
5364 if (hw->mac.san_mac_rar_index)
5365 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5366
8fecf67c 5367 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5368 ixgbe_ptp_reset(adapter);
961fac88
DS		 5369
5370 if (hw->phy.ops.set_phy_power) {
5371 if (!netif_running(adapter->netdev) && !adapter->wol)
5372 hw->phy.ops.set_phy_power(hw, false);
5373 else
5374 hw->phy.ops.set_phy_power(hw, true);
5375 }
9a799d71
AK		 5376}
5377
9a799d71
AK		 5378/**
5379 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5380 * @tx_ring: ring to be cleaned
5381 **/
b6ec895e 5382static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5383{
5384 struct ixgbe_tx_buffer *tx_buffer_info;
5385 unsigned long size;
b6ec895e 5386 u16 i;
9a799d71 5387
84418e3b
AD		 5388 /* ring already cleared, nothing to do */
5389 if (!tx_ring->tx_buffer_info)
5390 return;
9a799d71 5391
84418e3b 5392 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5393 for (i = 0; i < tx_ring->count; i++) {
5394 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5395 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5396 }
5397
dad8a3b3
JF		 5398 netdev_tx_reset_queue(txring_txq(tx_ring));
5399
9a799d71
AK		 5400 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5401 memset(tx_ring->tx_buffer_info, 0, size);
5402
5403 /* Zero out the descriptor ring */
5404 memset(tx_ring->desc, 0, tx_ring->size);
5405
5406 tx_ring->next_to_use = 0;
5407 tx_ring->next_to_clean = 0;
9a799d71
AK		 5408}
5409
5410/**
021230d4 5411 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5412 * @adapter: board private structure
5413 **/
021230d4 5414static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5415{
5416 int i;
5417
021230d4 5418 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5419 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5420}
5421
5422/**
021230d4 5423 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5424 * @adapter: board private structure
5425 **/
021230d4 5426static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5427{
5428 int i;
5429
021230d4 5430 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5431 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5432}
5433
e4911d57
AD		 5434static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5435{
b67bfe0d 5436 struct hlist_node *node2;
e4911d57
AD		 5437 struct ixgbe_fdir_filter *filter;
5438
5439 spin_lock(&adapter->fdir_perfect_lock);
5440
b67bfe0d 5441 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5442 &adapter->fdir_filter_list, fdir_node) {
5443 hlist_del(&filter->fdir_node);
5444 kfree(filter);
5445 }
5446 adapter->fdir_filter_count = 0;
5447
5448 spin_unlock(&adapter->fdir_perfect_lock);
5449}
5450
9a799d71
AK		 5451void ixgbe_down(struct ixgbe_adapter *adapter)
5452{
5453 struct net_device *netdev = adapter->netdev;
7f821875 5454 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5455 struct net_device *upper;
5456 struct list_head *iter;
bf29ee6c 5457 int i;
9a799d71
AK		 5458
5459 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5460 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5461 return; /* do nothing if already down */
9a799d71
AK		 5462
5463 /* disable receives */
1f9ac57c 5464 hw->mac.ops.disable_rx(hw);
9a799d71 5465
2d39d576
YZ		 5466 /* disable all enabled rx queues */
5467 for (i = 0; i < adapter->num_rx_queues; i++)
5468 /* this call also flushes the previous write */
5469 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5470
032b4325 5471 usleep_range(10000, 20000);
9a799d71 5472
7f821875
JB		 5473 netif_tx_stop_all_queues(netdev);
5474
7086400d 5475 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5476 netif_carrier_off(netdev);
5477 netif_tx_disable(netdev);
5478
2a47fa45
JF		 5479 /* disable any upper devices */
5480 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5481 if (netif_is_macvlan(upper)) {
5482 struct macvlan_dev *vlan = netdev_priv(upper);
5483
5484 if (vlan->fwd_priv) {
5485 netif_tx_stop_all_queues(upper);
5486 netif_carrier_off(upper);
5487 netif_tx_disable(upper);
5488 }
5489 }
5490 }
5491
c0dfb90e
JF		 5492 ixgbe_irq_disable(adapter);
5493
5494 ixgbe_napi_disable_all(adapter);
5495
d034acf1
AD		 5496 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5497 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5498 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5499
5500 del_timer_sync(&adapter->service_timer);
5501
34cecbbf 5502 if (adapter->num_vfs) {
8e34d1aa
AD		 5503 /* Clear EITR Select mapping */
5504 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5505
5506 /* Mark all the VFs as inactive */
5507 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5508 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5509
34cecbbf
AD		 5510 /* ping all the active vfs to let them know we are going down */
5511 ixgbe_ping_all_vfs(adapter);
5512
5513 /* Disable all VFTE/VFRE TX/RX */
5514 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5515 }
5516
7f821875
JB		 5517 /* disable transmits in the hardware now that interrupts are off */
5518 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5519 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5520 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5521 }
34cecbbf 5522
9a75a1ac 5523 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5524 switch (hw->mac.type) {
5525 case ixgbe_mac_82599EB:
b93a2226 5526 case ixgbe_mac_X540:
9a75a1ac
DS		 5527 case ixgbe_mac_X550:
5528 case ixgbe_mac_X550EM_x:
49425dfc 5529 case ixgbe_mac_x550em_a:
88512539 5530 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5531 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5532 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5533 break;
5534 default:
5535 break;
5536 }
7f821875 5537
6f4a0e45
PL		 5538 if (!pci_channel_offline(adapter->pdev))
5539 ixgbe_reset(adapter);
c6ecf39a 5540
ec74a471
ET		 5541 /* power down the optics for 82599 SFP+ fiber */
5542 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5543 hw->mac.ops.disable_tx_laser(hw);
5544
9a799d71
AK		 5545 ixgbe_clean_all_tx_rings(adapter);
5546 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5547}
5548
9a799d71
AK		 5549/**
5550 * ixgbe_tx_timeout - Respond to a Tx Hang
5551 * @netdev: network interface device structure
5552 **/
5553static void ixgbe_tx_timeout(struct net_device *netdev)
5554{
5555 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5556
5557 /* Do the reset outside of interrupt context */
c83c6cbd 5558 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5559}
5560
9a799d71
AK		 5561/**
5562 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5563 * @adapter: board private structure to initialize
5564 *
5565 * ixgbe_sw_init initializes the Adapter private data structure.
5566 * Fields are initialized based on PCI device information and
5567 * OS network device settings (MTU size).
5568 **/
9f9a12f8 5569static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5570{
5571 struct ixgbe_hw *hw = &adapter->hw;
5572 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5573 unsigned int rss, fdir;
cb6d0f5e 5574 u32 fwsm;
4319a797 5575 u16 device_caps;
7a6b6f51 5576#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5577 int j;
5578 struct tc_configuration *tc;
5579#endif
021230d4 5580
c44ade9e
JB		 5581 /* PCI config space info */
5582
5583 hw->vendor_id = pdev->vendor;
5584 hw->device_id = pdev->device;
5585 hw->revision_id = pdev->revision;
5586 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5587 hw->subsystem_device_id = pdev->subsystem_device;
5588
8fc3bb6d 5589 /* Set common capability flags and settings */
0f9b232b 5590 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5591 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5592 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5593 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5594 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5595 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5596 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5597 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5598#ifdef CONFIG_IXGBE_DCA
5599 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5600#endif
5601#ifdef IXGBE_FCOE
5602 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5603 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5604#ifdef CONFIG_IXGBE_DCB
5605 /* Default traffic class to use for FCoE */
5606 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5607#endif /* CONFIG_IXGBE_DCB */
5608#endif /* IXGBE_FCOE */
5609
b82b17d9
JF		 5610 /* initialize static ixgbe jump table entries */
5611 adapter->jump_tables[0] = ixgbe_ipv4_fields;
5612
5d7daa35
JK		 5613 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5614 hw->mac.num_rar_entries,
5615 GFP_ATOMIC);
530fd82a
AD		 5616 if (!adapter->mac_table)
5617 return -ENOMEM;
5d7daa35 5618
8fc3bb6d 5619 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5620 switch (hw->mac.type) {
5621 case ixgbe_mac_82598EB:
8fc3bb6d 5622 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5623
bf069c97
DS		 5624 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5625 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5626
49c7ffbe 5627 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5628 adapter->ring_feature[RING_F_FDIR].limit = 0;
5629 adapter->atr_sample_rate = 0;
5630 adapter->fdir_pballoc = 0;
5631#ifdef IXGBE_FCOE
5632 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5633 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5634#ifdef CONFIG_IXGBE_DCB
5635 adapter->fcoe.up = 0;
5636#endif /* IXGBE_DCB */
5637#endif /* IXGBE_FCOE */
5638 break;
5639 case ixgbe_mac_82599EB:
5640 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5641 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5642 break;
b93a2226 5643 case ixgbe_mac_X540:
9a900eca 5644 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5645 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5646 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5647 break;
9a75a1ac 5648 case ixgbe_mac_X550EM_x:
49425dfc 5649 case ixgbe_mac_x550em_a:
9a75a1ac
DS		 5650 case ixgbe_mac_X550:
5651#ifdef CONFIG_IXGBE_DCA
5652 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5653#endif
5654#ifdef CONFIG_IXGBE_VXLAN
5655 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5656#endif
5657 break;
bd508178
AD		 5658 default:
5659 break;
f8212f97 5660 }
2f90b865 5661
7c8ae65a
AD		 5662#ifdef IXGBE_FCOE
5663 /* FCoE support exists, always init the FCoE lock */
5664 spin_lock_init(&adapter->fcoe.lock);
5665
5666#endif
1fc5f038
AD		 5667 /* n-tuple support exists, always init our spinlock */
5668 spin_lock_init(&adapter->fdir_perfect_lock);
5669
7a6b6f51 5670#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5671 switch (hw->mac.type) {
5672 case ixgbe_mac_X540:
9a75a1ac
DS		 5673 case ixgbe_mac_X550:
5674 case ixgbe_mac_X550EM_x:
49425dfc 5675 case ixgbe_mac_x550em_a:
4de2a022
JF		 5676 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5677 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5678 break;
5679 default:
5680 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5681 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5682 break;
5683 }
5684
2f90b865
AD		 5685 /* Configure DCB traffic classes */
5686 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5687 tc = &adapter->dcb_cfg.tc_config[j];
5688 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5689 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5690 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5691 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5692 tc->dcb_pfc = pfc_disabled;
5693 }
4de2a022
JF		 5694
5695 /* Initialize default user to priority mapping, UPx->TC0 */
5696 tc = &adapter->dcb_cfg.tc_config[0];
5697 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5698 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5699
2f90b865
AD		 5700 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5701 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5702 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5703 adapter->dcb_set_bitmap = 0x00;
3032309b 5704 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5705 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5706 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5707
5708#endif
9a799d71
AK		 5709
5710 /* default flow control settings */
cd7664f6 5711 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5712 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5713 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5714 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5715 hw->fc.send_xon = true;
73d80953 5716 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5717
99d74487 5718#ifdef CONFIG_PCI_IOV
170e8543
JK		 5719 if (max_vfs > 0)
5720 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5721
99d74487 5722 /* assign number of SR-IOV VFs */
170e8543 5723 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5724 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5725 adapter->num_vfs = 0;
5726 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5727 } else {
5728 adapter->num_vfs = max_vfs;
5729 }
5730 }
5731#endif /* CONFIG_PCI_IOV */
99d74487 5732
30efa5a3 5733 /* enable itr by default in dynamic mode */
f7554a2b 5734 adapter->rx_itr_setting = 1;
f7554a2b 5735 adapter->tx_itr_setting = 1;
30efa5a3 5736
30efa5a3
JB		 5737 /* set default ring sizes */
5738 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5739 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5740
4319a797
DS		 5741 /* Cache bit indicating need for crosstalk fix */
5742 switch (hw->mac.type) {
5743 case ixgbe_mac_82599EB:
5744 case ixgbe_mac_X550EM_x:
5745 case ixgbe_mac_x550em_a:
5746 hw->mac.ops.get_device_caps(hw, &device_caps);
5747 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
5748 adapter->need_crosstalk_fix = false;
5749 else
5750 adapter->need_crosstalk_fix = true;
5751 break;
5752 default:
5753 adapter->need_crosstalk_fix = false;
5754 break;
5755 }
5756
bd198058 5757 /* set default work limits */
59224555 5758 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5759
9a799d71 5760 /* initialize eeprom parameters */
c44ade9e 5761 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5762 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5763 return -EIO;
5764 }
5765
2a47fa45
JF		 5766 /* PF holds first pool slot */
5767 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5768 set_bit(__IXGBE_DOWN, &adapter->state);
5769
5770 return 0;
5771}
5772
5773/**
5774 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5775 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5776 *
5777 * Return 0 on success, negative on failure
5778 **/
b6ec895e 5779int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5780{
b6ec895e 5781 struct device *dev = tx_ring->dev;
de88eeeb 5782 int orig_node = dev_to_node(dev);
ca8dfe25 5783 int ring_node = -1;
9a799d71
AK		 5784 int size;
5785
3a581073 5786 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5787
5788 if (tx_ring->q_vector)
ca8dfe25 5789 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5790
ca8dfe25 5791 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5792 if (!tx_ring->tx_buffer_info)
89bf67f1 5793 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5794 if (!tx_ring->tx_buffer_info)
5795 goto err;
9a799d71 5796
827da44c
JS		 5797 u64_stats_init(&tx_ring->syncp);
5798
9a799d71 5799 /* round up to nearest 4K */
12207e49 5800 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5801 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5802
ca8dfe25 5803 set_dev_node(dev, ring_node);
de88eeeb
AD		 5804 tx_ring->desc = dma_alloc_coherent(dev,
5805 tx_ring->size,
5806 &tx_ring->dma,
5807 GFP_KERNEL);
5808 set_dev_node(dev, orig_node);
5809 if (!tx_ring->desc)
5810 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5811 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5812 if (!tx_ring->desc)
5813 goto err;
9a799d71 5814
3a581073
JB		 5815 tx_ring->next_to_use = 0;
5816 tx_ring->next_to_clean = 0;
9a799d71 5817 return 0;
e01c31a5
JB		 5818
5819err:
5820 vfree(tx_ring->tx_buffer_info);
5821 tx_ring->tx_buffer_info = NULL;
b6ec895e 5822 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5823 return -ENOMEM;
9a799d71
AK		 5824}
5825
69888674
AD		 5826/**
5827 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5828 * @adapter: board private structure
5829 *
5830 * If this function returns with an error, then it's possible one or
5831 * more of the rings is populated (while the rest are not). It is the
5832 * callers duty to clean those orphaned rings.
5833 *
5834 * Return 0 on success, negative on failure
5835 **/
5836static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5837{
5838 int i, err = 0;
5839
5840 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5841 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5842 if (!err)
5843 continue;
de3d5b94 5844
396e799c 5845 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5846 goto err_setup_tx;
69888674
AD		 5847 }
5848
de3d5b94
AD		 5849 return 0;
5850err_setup_tx:
5851 /* rewind the index freeing the rings as we go */
5852 while (i--)
5853 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5854 return err;
5855}
5856
9a799d71
AK		 5857/**
5858 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5859 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5860 *
5861 * Returns 0 on success, negative on failure
5862 **/
b6ec895e 5863int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5864{
b6ec895e 5865 struct device *dev = rx_ring->dev;
de88eeeb 5866 int orig_node = dev_to_node(dev);
ca8dfe25 5867 int ring_node = -1;
021230d4 5868 int size;
9a799d71 5869
3a581073 5870 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5871
5872 if (rx_ring->q_vector)
ca8dfe25 5873 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5874
ca8dfe25 5875 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5876 if (!rx_ring->rx_buffer_info)
89bf67f1 5877 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5878 if (!rx_ring->rx_buffer_info)
5879 goto err;
9a799d71 5880
827da44c
JS		 5881 u64_stats_init(&rx_ring->syncp);
5882
9a799d71 5883 /* Round up to nearest 4K */
3a581073
JB		 5884 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5885 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5886
ca8dfe25 5887 set_dev_node(dev, ring_node);
de88eeeb
AD		 5888 rx_ring->desc = dma_alloc_coherent(dev,
5889 rx_ring->size,
5890 &rx_ring->dma,
5891 GFP_KERNEL);
5892 set_dev_node(dev, orig_node);
5893 if (!rx_ring->desc)
5894 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5895 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5896 if (!rx_ring->desc)
5897 goto err;
9a799d71 5898
3a581073
JB		 5899 rx_ring->next_to_clean = 0;
5900 rx_ring->next_to_use = 0;
9a799d71
AK		 5901
5902 return 0;
b6ec895e
AD		 5903err:
5904 vfree(rx_ring->rx_buffer_info);
5905 rx_ring->rx_buffer_info = NULL;
5906 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5907 return -ENOMEM;
9a799d71
AK		 5908}
5909
69888674
AD		 5910/**
5911 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5912 * @adapter: board private structure
5913 *
5914 * If this function returns with an error, then it's possible one or
5915 * more of the rings is populated (while the rest are not). It is the
5916 * callers duty to clean those orphaned rings.
5917 *
5918 * Return 0 on success, negative on failure
5919 **/
69888674
AD		 5920static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5921{
5922 int i, err = 0;
5923
5924 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5925 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5926 if (!err)
5927 continue;
de3d5b94 5928
396e799c 5929 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5930 goto err_setup_rx;
69888674
AD		 5931 }
5932
7c8ae65a
AD		 5933#ifdef IXGBE_FCOE
5934 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5935 if (!err)
5936#endif
5937 return 0;
de3d5b94
AD		 5938err_setup_rx:
5939 /* rewind the index freeing the rings as we go */
5940 while (i--)
5941 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5942 return err;
5943}
5944
9a799d71
AK		 5945/**
5946 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5947 * @tx_ring: Tx descriptor ring for a specific queue
5948 *
5949 * Free all transmit software resources
5950 **/
b6ec895e 5951void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5952{
b6ec895e 5953 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5954
5955 vfree(tx_ring->tx_buffer_info);
5956 tx_ring->tx_buffer_info = NULL;
5957
b6ec895e
AD		 5958 /* if not set, then don't free */
5959 if (!tx_ring->desc)
5960 return;
5961
5962 dma_free_coherent(tx_ring->dev, tx_ring->size,
5963 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5964
5965 tx_ring->desc = NULL;
5966}
5967
5968/**
5969 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5970 * @adapter: board private structure
5971 *
5972 * Free all transmit software resources
5973 **/
5974static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5975{
5976 int i;
5977
5978 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5979 if (adapter->tx_ring[i]->desc)
b6ec895e 5980 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5981}
5982
5983/**
b4617240 5984 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5985 * @rx_ring: ring to clean the resources from
5986 *
5987 * Free all receive software resources
5988 **/
b6ec895e 5989void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5990{
b6ec895e 5991 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5992
5993 vfree(rx_ring->rx_buffer_info);
5994 rx_ring->rx_buffer_info = NULL;
5995
b6ec895e
AD		 5996 /* if not set, then don't free */
5997 if (!rx_ring->desc)
5998 return;
5999
6000 dma_free_coherent(rx_ring->dev, rx_ring->size,
6001 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 6002
6003 rx_ring->desc = NULL;
6004}
6005
6006/**
6007 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6008 * @adapter: board private structure
6009 *
6010 * Free all receive software resources
6011 **/
6012static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6013{
6014 int i;
6015
7c8ae65a
AD		 6016#ifdef IXGBE_FCOE
6017 ixgbe_free_fcoe_ddp_resources(adapter);
6018
6019#endif
9a799d71 6020 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 6021 if (adapter->rx_ring[i]->desc)
b6ec895e 6022 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 6023}
6024
9a799d71
AK		 6025/**
6026 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6027 * @netdev: network interface device structure
6028 * @new_mtu: new value for maximum frame size
6029 *
6030 * Returns 0 on success, negative on failure
6031 **/
6032static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6033{
6034 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6035 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
6036
42c783c5 6037 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 6038 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
6039 return -EINVAL;
6040
6041 /*
872844dd
AD		 6042 * For 82599EB we cannot allow legacy VFs to enable their receive
6043 * paths when MTU greater than 1500 is configured. So display a
6044 * warning that legacy VFs will be disabled.
655309e9
AD		 6045 */
6046 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6047 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 6048 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 6049 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 6050
396e799c 6051 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 6052
021230d4 6053 /* must set new MTU before calling down or up */
9a799d71
AK		 6054 netdev->mtu = new_mtu;
6055
d4f80882
AV		 6056 if (netif_running(netdev))
6057 ixgbe_reinit_locked(adapter);
9a799d71
AK		 6058
6059 return 0;
6060}
6061
6062/**
6063 * ixgbe_open - Called when a network interface is made active
6064 * @netdev: network interface device structure
6065 *
6066 * Returns 0 on success, negative value on failure
6067 *
6068 * The open entry point is called when a network interface is made
6069 * active by the system (IFF_UP). At this point all resources needed
6070 * for transmit and receive operations are allocated, the interrupt
6071 * handler is registered with the OS, the watchdog timer is started,
6072 * and the stack is notified that the interface is ready.
6073 **/
6c211fe1 6074int ixgbe_open(struct net_device *netdev)
9a799d71
AK		 6075{
6076 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 6077 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 6078 int err, queues;
4bebfaa5
AK		 6079
6080 /* disallow open during test */
6081 if (test_bit(__IXGBE_TESTING, &adapter->state))
6082 return -EBUSY;
9a799d71 6083
54386467
JB		 6084 netif_carrier_off(netdev);
6085
9a799d71
AK		 6086 /* allocate transmit descriptors */
6087 err = ixgbe_setup_all_tx_resources(adapter);
6088 if (err)
6089 goto err_setup_tx;
6090
9a799d71
AK		 6091 /* allocate receive descriptors */
6092 err = ixgbe_setup_all_rx_resources(adapter);
6093 if (err)
6094 goto err_setup_rx;
6095
6096 ixgbe_configure(adapter);
6097
021230d4 6098 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6099 if (err)
6100 goto err_req_irq;
6101
ac802f5d 6102 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 6103 if (adapter->num_rx_pools > 1)
6104 queues = adapter->num_rx_queues_per_pool;
6105 else
6106 queues = adapter->num_tx_queues;
6107
6108 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6109 if (err)
6110 goto err_set_queues;
6111
2a47fa45
JF		 6112 if (adapter->num_rx_pools > 1 &&
6113 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6114 queues = IXGBE_MAX_L2A_QUEUES;
6115 else
6116 queues = adapter->num_rx_queues;
6117 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6118 if (err)
6119 goto err_set_queues;
6120
1a71ab24 6121 ixgbe_ptp_init(adapter);
1a71ab24 6122
c7ccde0f 6123 ixgbe_up_complete(adapter);
9a799d71 6124
67359c3c
MR		 6125 ixgbe_clear_vxlan_port(adapter);
6126#ifdef CONFIG_IXGBE_VXLAN
3f207800 6127 vxlan_get_rx_port(netdev);
3f207800 6128#endif
67359c3c 6129
9a799d71
AK		 6130 return 0;
6131
ac802f5d
AD		 6132err_set_queues:
6133 ixgbe_free_irq(adapter);
9a799d71 6134err_req_irq:
a20a1199 6135 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6136 if (hw->phy.ops.set_phy_power && !adapter->wol)
6137 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6138err_setup_rx:
a20a1199 6139 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6140err_setup_tx:
9a799d71
AK		 6141 ixgbe_reset(adapter);
6142
6143 return err;
6144}
6145
a0cccce2
JK		 6146static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6147{
6148 ixgbe_ptp_suspend(adapter);
6149
6ac74394
DS		 6150 if (adapter->hw.phy.ops.enter_lplu) {
6151 adapter->hw.phy.reset_disable = true;
6152 ixgbe_down(adapter);
6153 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6154 adapter->hw.phy.reset_disable = false;
6155 } else {
6156 ixgbe_down(adapter);
6157 }
6158
a0cccce2
JK		 6159 ixgbe_free_irq(adapter);
6160
6161 ixgbe_free_all_tx_resources(adapter);
6162 ixgbe_free_all_rx_resources(adapter);
6163}
6164
9a799d71
AK		 6165/**
6166 * ixgbe_close - Disables a network interface
6167 * @netdev: network interface device structure
6168 *
6169 * Returns 0, this is not allowed to fail
6170 *
6171 * The close entry point is called when an interface is de-activated
6172 * by the OS. The hardware is still under the drivers control, but
6173 * needs to be disabled. A global MAC reset is issued to stop the
6174 * hardware, and all transmit and receive resources are freed.
6175 **/
6c211fe1 6176int ixgbe_close(struct net_device *netdev)
9a799d71
AK		 6177{
6178 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6179
1a71ab24 6180 ixgbe_ptp_stop(adapter);
1a71ab24 6181
a0cccce2 6182 ixgbe_close_suspend(adapter);
9a799d71 6183
e4911d57
AD		 6184 ixgbe_fdir_filter_exit(adapter);
6185
5eba3699 6186 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6187
6188 return 0;
6189}
6190
b3c8b4ba
AD		 6191#ifdef CONFIG_PM
6192static int ixgbe_resume(struct pci_dev *pdev)
6193{
c60fbb00
AD		 6194 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6195 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6196 u32 err;
6197
0391bbe3 6198 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 6199 pci_set_power_state(pdev, PCI_D0);
6200 pci_restore_state(pdev);
656ab817
DS		 6201 /*
6202 * pci_restore_state clears dev->state_saved so call
6203 * pci_save_state to restore it.
6204 */
6205 pci_save_state(pdev);
9ce77666 6206
6207 err = pci_enable_device_mem(pdev);
b3c8b4ba 6208 if (err) {
849c4542 6209 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 6210 return err;
6211 }
4e857c58 6212 smp_mb__before_atomic();
41c62843 6213 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6214 pci_set_master(pdev);
6215
dd4d8ca6 6216 pci_wake_from_d3(pdev, false);
b3c8b4ba 6217
b3c8b4ba
AD		 6218 ixgbe_reset(adapter);
6219
495dce12
WJP		 6220 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6221
ac802f5d
AD		 6222 rtnl_lock();
6223 err = ixgbe_init_interrupt_scheme(adapter);
6224 if (!err && netif_running(netdev))
c60fbb00 6225 err = ixgbe_open(netdev);
ac802f5d
AD		 6226
6227 rtnl_unlock();
6228
6229 if (err)
6230 return err;
b3c8b4ba
AD		 6231
6232 netif_device_attach(netdev);
6233
6234 return 0;
6235}
b3c8b4ba 6236#endif /* CONFIG_PM */
9d8d05ae
RW		 6237
6238static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6239{
c60fbb00
AD		 6240 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6241 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 6242 struct ixgbe_hw *hw = &adapter->hw;
6243 u32 ctrl, fctrl;
6244 u32 wufc = adapter->wol;
b3c8b4ba
AD		 6245#ifdef CONFIG_PM
6246 int retval = 0;
6247#endif
6248
6249 netif_device_detach(netdev);
6250
499ab5cc 6251 rtnl_lock();
a0cccce2
JK		 6252 if (netif_running(netdev))
6253 ixgbe_close_suspend(adapter);
499ab5cc 6254 rtnl_unlock();
b3c8b4ba 6255
5f5ae6fc
AD		 6256 ixgbe_clear_interrupt_scheme(adapter);
6257
b3c8b4ba
AD		 6258#ifdef CONFIG_PM
6259 retval = pci_save_state(pdev);
6260 if (retval)
6261 return retval;
4df10466 6262
b3c8b4ba 6263#endif
f4f1040a
JK		 6264 if (hw->mac.ops.stop_link_on_d3)
6265 hw->mac.ops.stop_link_on_d3(hw);
6266
e8e26350
PW		 6267 if (wufc) {
6268 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6269
ec74a471
ET		 6270 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6271 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6272 hw->mac.ops.enable_tx_laser(hw);
6273
e8e26350
PW		 6274 /* turn on all-multi mode if wake on multicast is enabled */
6275 if (wufc & IXGBE_WUFC_MC) {
6276 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6277 fctrl |= IXGBE_FCTRL_MPE;
6278 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6279 }
6280
6281 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6282 ctrl |= IXGBE_CTRL_GIO_DIS;
6283 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6284
6285 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6286 } else {
6287 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6288 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6289 }
6290
bd508178
AD		 6291 switch (hw->mac.type) {
6292 case ixgbe_mac_82598EB:
dd4d8ca6 6293 pci_wake_from_d3(pdev, false);
bd508178
AD		 6294 break;
6295 case ixgbe_mac_82599EB:
b93a2226 6296 case ixgbe_mac_X540:
9a75a1ac
DS		 6297 case ixgbe_mac_X550:
6298 case ixgbe_mac_X550EM_x:
49425dfc 6299 case ixgbe_mac_x550em_a:
bd508178
AD		 6300 pci_wake_from_d3(pdev, !!wufc);
6301 break;
6302 default:
6303 break;
6304 }
b3c8b4ba 6305
9d8d05ae 6306 *enable_wake = !!wufc;
961fac88
DS		 6307 if (hw->phy.ops.set_phy_power && !*enable_wake)
6308 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6309
b3c8b4ba
AD		 6310 ixgbe_release_hw_control(adapter);
6311
41c62843
MR		 6312 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6313 pci_disable_device(pdev);
b3c8b4ba 6314
9d8d05ae
RW		 6315 return 0;
6316}
6317
6318#ifdef CONFIG_PM
6319static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6320{
6321 int retval;
6322 bool wake;
6323
6324 retval = __ixgbe_shutdown(pdev, &wake);
6325 if (retval)
6326 return retval;
6327
6328 if (wake) {
6329 pci_prepare_to_sleep(pdev);
6330 } else {
6331 pci_wake_from_d3(pdev, false);
6332 pci_set_power_state(pdev, PCI_D3hot);
6333 }
b3c8b4ba
AD		 6334
6335 return 0;
6336}
9d8d05ae 6337#endif /* CONFIG_PM */
b3c8b4ba
AD		 6338
6339static void ixgbe_shutdown(struct pci_dev *pdev)
6340{
9d8d05ae
RW		 6341 bool wake;
6342
6343 __ixgbe_shutdown(pdev, &wake);
6344
6345 if (system_state == SYSTEM_POWER_OFF) {
6346 pci_wake_from_d3(pdev, wake);
6347 pci_set_power_state(pdev, PCI_D3hot);
6348 }
b3c8b4ba
AD		 6349}
6350
9a799d71
AK		 6351/**
6352 * ixgbe_update_stats - Update the board statistics counters.
6353 * @adapter: board private structure
6354 **/
6355void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6356{
2d86f139 6357 struct net_device *netdev = adapter->netdev;
9a799d71 6358 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6359 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6360 u64 total_mpc = 0;
6361 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6362 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6363 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6364 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6365
d08935c2
DS		 6366 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6367 test_bit(__IXGBE_RESETTING, &adapter->state))
6368 return;
6369
94b982b2 6370 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6371 u64 rsc_count = 0;
94b982b2 6372 u64 rsc_flush = 0;
94b982b2 6373 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6374 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6375 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6376 }
6377 adapter->rsc_total_count = rsc_count;
6378 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6379 }
6380
5b7da515
AD		 6381 for (i = 0; i < adapter->num_rx_queues; i++) {
6382 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6383 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6384 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6385 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6386 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6387 bytes += rx_ring->stats.bytes;
6388 packets += rx_ring->stats.packets;
6389 }
6390 adapter->non_eop_descs = non_eop_descs;
6391 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6392 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6393 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6394 netdev->stats.rx_bytes = bytes;
6395 netdev->stats.rx_packets = packets;
6396
6397 bytes = 0;
6398 packets = 0;
7ca3bc58 6399 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6400 for (i = 0; i < adapter->num_tx_queues; i++) {
6401 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6402 restart_queue += tx_ring->tx_stats.restart_queue;
6403 tx_busy += tx_ring->tx_stats.tx_busy;
6404 bytes += tx_ring->stats.bytes;
6405 packets += tx_ring->stats.packets;
6406 }
eb985f09 6407 adapter->restart_queue = restart_queue;
5b7da515
AD		 6408 adapter->tx_busy = tx_busy;
6409 netdev->stats.tx_bytes = bytes;
6410 netdev->stats.tx_packets = packets;
7ca3bc58 6411
7ca647bd 6412 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6413
6414 /* 8 register reads */
6f11eef7
AV		 6415 for (i = 0; i < 8; i++) {
6416 /* for packet buffers not used, the register should read 0 */
6417 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6418 missed_rx += mpc;
7ca647bd
JP		 6419 hwstats->mpc[i] += mpc;
6420 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6421 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6422 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6423 switch (hw->mac.type) {
6424 case ixgbe_mac_82598EB:
1a70db4b
ET		 6425 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6426 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6427 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6428 hwstats->pxonrxc[i] +=
6429 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6430 break;
6431 case ixgbe_mac_82599EB:
b93a2226 6432 case ixgbe_mac_X540:
9a75a1ac
DS		 6433 case ixgbe_mac_X550:
6434 case ixgbe_mac_X550EM_x:
49425dfc 6435 case ixgbe_mac_x550em_a:
bd508178
AD		 6436 hwstats->pxonrxc[i] +=
6437 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6438 break;
6439 default:
6440 break;
e8e26350 6441 }
6f11eef7 6442 }
1a70db4b
ET		 6443
6444 /*16 register reads */
6445 for (i = 0; i < 16; i++) {
6446 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6447 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6448 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6449 (hw->mac.type == ixgbe_mac_X540) ||
6450 (hw->mac.type == ixgbe_mac_X550) ||
49425dfc
MR		 6451 (hw->mac.type == ixgbe_mac_X550EM_x) ||
6452 (hw->mac.type == ixgbe_mac_x550em_a)) {
1a70db4b
ET		 6453 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6454 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6455 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6456 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6457 }
6458 }
6459
7ca647bd 6460 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6461 /* work around hardware counting issue */
7ca647bd 6462 hwstats->gprc -= missed_rx;
6f11eef7 6463
c84d324c
JF		 6464 ixgbe_update_xoff_received(adapter);
6465
6f11eef7 6466 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6467 switch (hw->mac.type) {
6468 case ixgbe_mac_82598EB:
6469 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6470 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6471 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6472 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6473 break;
b93a2226 6474 case ixgbe_mac_X540:
9a75a1ac
DS		 6475 case ixgbe_mac_X550:
6476 case ixgbe_mac_X550EM_x:
49425dfc 6477 case ixgbe_mac_x550em_a:
9a75a1ac 6478 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6479 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6480 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6481 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6482 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6483 case ixgbe_mac_82599EB:
a4d4f629
AD		 6484 for (i = 0; i < 16; i++)
6485 adapter->hw_rx_no_dma_resources +=
6486 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6487 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6488 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6489 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6490 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6491 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6492 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6493 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6494 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6495 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6496#ifdef IXGBE_FCOE
7ca647bd
JP		 6497 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6498 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6499 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6500 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6501 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6502 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6503 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6504 if (adapter->fcoe.ddp_pool) {
6505 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6506 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6507 unsigned int cpu;
6508 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6509 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6510 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6511 noddp += ddp_pool->noddp;
6512 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6513 }
5a1ee270
AD		 6514 hwstats->fcoe_noddp = noddp;
6515 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6516 }
6d45522c 6517#endif /* IXGBE_FCOE */
bd508178
AD		 6518 break;
6519 default:
6520 break;
e8e26350 6521 }
9a799d71 6522 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6523 hwstats->bprc += bprc;
6524 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6525 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6526 hwstats->mprc -= bprc;
6527 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6528 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6529 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6530 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6531 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6532 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6533 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6534 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6535 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6536 hwstats->lxontxc += lxon;
6f11eef7 6537 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6538 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6539 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6540 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6541 /*
6542 * 82598 errata - tx of flow control packets is included in tx counters
6543 */
6544 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6545 hwstats->gptc -= xon_off_tot;
6546 hwstats->mptc -= xon_off_tot;
6547 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6548 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6549 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6550 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6551 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6552 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6553 hwstats->ptc64 -= xon_off_tot;
6554 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6555 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6556 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6557 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6558 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6559 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6560
6561 /* Fill out the OS statistics structure */
7ca647bd 6562 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6563
6564 /* Rx Errors */
7ca647bd 6565 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6566 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6567 netdev->stats.rx_length_errors = hwstats->rlec;
6568 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6569 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6570}
6571
6572/**
d034acf1 6573 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6574 * @adapter: pointer to the device adapter structure
9a799d71 6575 **/
d034acf1 6576static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6577{
cf8280ee 6578 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6579 int i;
cf8280ee 6580
d034acf1
AD		 6581 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6582 return;
6583
6584 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6585
d034acf1 6586 /* if interface is down do nothing */
fe49f04a 6587 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6588 return;
6589
6590 /* do nothing if we are not using signature filters */
6591 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6592 return;
6593
6594 adapter->fdir_overflow++;
6595
93c52dd0
AD		 6596 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6597 for (i = 0; i < adapter->num_tx_queues; i++)
6598 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6599 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6600 /* re-enable flow director interrupts */
6601 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6602 } else {
6603 e_err(probe, "failed to finish FDIR re-initialization, "
6604 "ignored adding FDIR ATR filters\n");
6605 }
93c52dd0
AD		 6606}
6607
6608/**
6609 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6610 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6611 *
6612 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6613 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6614 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6615 * determine if a hang has occurred.
93c52dd0
AD		 6616 */
6617static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6618{
cf8280ee 6619 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6620 u64 eics = 0;
6621 int i;
cf8280ee 6622
09f40aed 6623 /* If we're down, removing or resetting, just bail */
93c52dd0 6624 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6625 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6626 test_bit(__IXGBE_RESETTING, &adapter->state))
6627 return;
22d5a71b 6628
93c52dd0
AD		 6629 /* Force detection of hung controller */
6630 if (netif_carrier_ok(adapter->netdev)) {
6631 for (i = 0; i < adapter->num_tx_queues; i++)
6632 set_check_for_tx_hang(adapter->tx_ring[i]);
6633 }
22d5a71b 6634
fe49f04a
AD		 6635 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6636 /*
6637 * for legacy and MSI interrupts don't set any bits
6638 * that are enabled for EIAM, because this operation
6639 * would set *both* EIMS and EICS for any bit in EIAM
6640 */
6641 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6642 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6643 } else {
6644 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6645 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6646 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6647 if (qv->rx.ring || qv->tx.ring)
b4f47a48 6648 eics |= BIT_ULL(i);
93c52dd0 6649 }
cf8280ee 6650 }
9a799d71 6651
93c52dd0 6652 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6653 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6654}
6655
e8e26350 6656/**
93c52dd0 6657 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6658 * @adapter: pointer to the device adapter structure
6659 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6660 **/
93c52dd0 6661static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6662{
e8e26350 6663 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6664 u32 link_speed = adapter->link_speed;
6665 bool link_up = adapter->link_up;
041441d0 6666 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6667
93c52dd0
AD		 6668 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6669 return;
6670
6671 if (hw->mac.ops.check_link) {
6672 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6673 } else {
93c52dd0
AD		 6674 /* always assume link is up, if no check link function */
6675 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6676 link_up = true;
c4cf55e5 6677 }
041441d0 6678
4319a797
DS		 6679 /* If Crosstalk fix enabled do the sanity check of making sure
6680 * the SFP+ cage is empty.
6681 */
6682 if (adapter->need_crosstalk_fix) {
6683 u32 sfp_cage_full;
6684
6685 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
6686 IXGBE_ESDP_SDP2;
6687 if (ixgbe_is_sfp(hw) && link_up && !sfp_cage_full)
6688 link_up = false;
6689 }
6690
041441d0
AD		 6691 if (adapter->ixgbe_ieee_pfc)
6692 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6693
3ebe8fde 6694 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6695 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6696 ixgbe_set_rx_drop_en(adapter);
6697 }
93c52dd0
AD		 6698
6699 if (link_up ||
6700 time_after(jiffies, (adapter->link_check_timeout +
6701 IXGBE_TRY_LINK_TIMEOUT))) {
6702 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6703 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6704 IXGBE_WRITE_FLUSH(hw);
6705 }
6706
6707 adapter->link_up = link_up;
6708 adapter->link_speed = link_speed;
e8e26350
PW		 6709}
6710
107d3018
AD		 6711static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6712{
6713#ifdef CONFIG_IXGBE_DCB
6714 struct net_device *netdev = adapter->netdev;
6715 struct dcb_app app = {
6716 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6717 .protocol = 0,
6718 };
6719 u8 up = 0;
6720
6721 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6722 up = dcb_ieee_getapp_mask(netdev, &app);
6723
6724 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6725#endif
6726}
6727
e8e26350 6728/**
93c52dd0
AD		 6729 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6730 * print link up message
49ce9c2c 6731 * @adapter: pointer to the device adapter structure
e8e26350 6732 **/
93c52dd0 6733static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6734{
93c52dd0 6735 struct net_device *netdev = adapter->netdev;
e8e26350 6736 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6737 struct net_device *upper;
6738 struct list_head *iter;
93c52dd0 6739 u32 link_speed = adapter->link_speed;
454adb00 6740 const char *speed_str;
93c52dd0 6741 bool flow_rx, flow_tx;
e8e26350 6742
93c52dd0
AD		 6743 /* only continue if link was previously down */
6744 if (netif_carrier_ok(netdev))
a985b6c3 6745 return;
63d6e1d8 6746
93c52dd0 6747 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6748
93c52dd0
AD		 6749 switch (hw->mac.type) {
6750 case ixgbe_mac_82598EB: {
6751 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6752 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6753 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6754 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6755 }
6756 break;
6757 case ixgbe_mac_X540:
9a75a1ac
DS		 6758 case ixgbe_mac_X550:
6759 case ixgbe_mac_X550EM_x:
49425dfc 6760 case ixgbe_mac_x550em_a:
93c52dd0
AD		 6761 case ixgbe_mac_82599EB: {
6762 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6763 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6764 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6765 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6766 }
6767 break;
6768 default:
6769 flow_tx = false;
6770 flow_rx = false;
6771 break;
e8e26350 6772 }
3a6a4eda 6773
6cb562d6
JK		 6774 adapter->last_rx_ptp_check = jiffies;
6775
8fecf67c 6776 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6777 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6778
454adb00
MR		 6779 switch (link_speed) {
6780 case IXGBE_LINK_SPEED_10GB_FULL:
6781 speed_str = "10 Gbps";
6782 break;
6783 case IXGBE_LINK_SPEED_2_5GB_FULL:
6784 speed_str = "2.5 Gbps";
6785 break;
6786 case IXGBE_LINK_SPEED_1GB_FULL:
6787 speed_str = "1 Gbps";
6788 break;
6789 case IXGBE_LINK_SPEED_100_FULL:
6790 speed_str = "100 Mbps";
6791 break;
6792 default:
6793 speed_str = "unknown speed";
6794 break;
6795 }
6796 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6797 ((flow_rx && flow_tx) ? "RX/TX" :
6798 (flow_rx ? "RX" :
6799 (flow_tx ? "TX" : "None"))));
e8e26350 6800
93c52dd0 6801 netif_carrier_on(netdev);
93c52dd0 6802 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6803
cdc04dcc
ET		 6804 /* enable transmits */
6805 netif_tx_wake_all_queues(adapter->netdev);
6806
6807 /* enable any upper devices */
6808 rtnl_lock();
6809 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6810 if (netif_is_macvlan(upper)) {
6811 struct macvlan_dev *vlan = netdev_priv(upper);
6812
6813 if (vlan->fwd_priv)
6814 netif_tx_wake_all_queues(upper);
6815 }
6816 }
6817 rtnl_unlock();
6818
107d3018
AD		 6819 /* update the default user priority for VFs */
6820 ixgbe_update_default_up(adapter);
6821
befa2af7
AD		 6822 /* ping all the active vfs to let them know link has changed */
6823 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6824}
6825
c4cf55e5 6826/**
93c52dd0
AD		 6827 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6828 * print link down message
49ce9c2c 6829 * @adapter: pointer to the adapter structure
c4cf55e5 6830 **/
581330ba 6831static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6832{
cf8280ee 6833 struct net_device *netdev = adapter->netdev;
c4cf55e5 6834 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6835
93c52dd0
AD		 6836 adapter->link_up = false;
6837 adapter->link_speed = 0;
cf8280ee 6838
93c52dd0
AD		 6839 /* only continue if link was up previously */
6840 if (!netif_carrier_ok(netdev))
6841 return;
264857b8 6842
93c52dd0
AD		 6843 /* poll for SFP+ cable when link is down */
6844 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6845 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6846
8fecf67c 6847 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6848 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6849
93c52dd0
AD		 6850 e_info(drv, "NIC Link is Down\n");
6851 netif_carrier_off(netdev);
befa2af7
AD		 6852
6853 /* ping all the active vfs to let them know link has changed */
6854 ixgbe_ping_all_vfs(adapter);
93c52dd0 6855}
e8e26350 6856
07923c17
ET		 6857static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6858{
6859 int i;
6860
6861 for (i = 0; i < adapter->num_tx_queues; i++) {
6862 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6863
6864 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6865 return true;
6866 }
6867
6868 return false;
6869}
6870
6871static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6872{
6873 struct ixgbe_hw *hw = &adapter->hw;
6874 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6875 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6876
6877 int i, j;
6878
6879 if (!adapter->num_vfs)
6880 return false;
6881
9a75a1ac
DS		 6882 /* resetting the PF is only needed for MAC before X550 */
6883 if (hw->mac.type >= ixgbe_mac_X550)
6884 return false;
6885
07923c17
ET		 6886 for (i = 0; i < adapter->num_vfs; i++) {
6887 for (j = 0; j < q_per_pool; j++) {
6888 u32 h, t;
6889
6890 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6891 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6892
6893 if (h != t)
6894 return true;
6895 }
6896 }
6897
6898 return false;
6899}
6900
93c52dd0
AD		 6901/**
6902 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6903 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6904 **/
6905static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6906{
93c52dd0 6907 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6908 if (ixgbe_ring_tx_pending(adapter) ||
6909 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6910 /* We've lost link, so the controller stops DMA,
6911 * but we've got queued Tx work that's never going
6912 * to get done, so reset controller to flush Tx.
6913 * (Do the reset outside of interrupt context).
6914 */
12ff3f3b 6915 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6916 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6917 }
c4cf55e5 6918 }
c4cf55e5
PWJ		 6919}
6920
9079e416
ET		 6921#ifdef CONFIG_PCI_IOV
6922static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6923 struct pci_dev *vfdev)
6924{
6925 if (!pci_wait_for_pending_transaction(vfdev))
6926 e_dev_warn("Issuing VFLR with pending transactions\n");
6927
6928 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6929 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6930
6931 msleep(100);
6932}
6933
6934static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6935{
6936 struct ixgbe_hw *hw = &adapter->hw;
6937 struct pci_dev *pdev = adapter->pdev;
988d1307 6938 unsigned int vf;
9079e416 6939 u32 gpc;
9079e416
ET		 6940
6941 if (!(netif_carrier_ok(adapter->netdev)))
6942 return;
6943
6944 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6945 if (gpc) /* If incrementing then no need for the check below */
6946 return;
6947 /* Check to see if a bad DMA write target from an errant or
6948 * malicious VF has caused a PCIe error. If so then we can
6949 * issue a VFLR to the offending VF(s) and then resume without
6950 * requesting a full slot reset.
6951 */
6952
6953 if (!pdev)
6954 return;
6955
9079e416 6956 /* check status reg for all VFs owned by this PF */
988d1307
MR		 6957 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6958 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6959 u16 status_reg;
9079e416 6960
988d1307
MR		 6961 if (!vfdev)
6962 continue;
6963 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6964 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6965 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6966 ixgbe_issue_vf_flr(adapter, vfdev);
9079e416
ET		 6967 }
6968}
6969
a985b6c3
GR		 6970static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6971{
6972 u32 ssvpc;
6973
0584d999
GR		 6974 /* Do not perform spoof check for 82598 or if not in IOV mode */
6975 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6976 adapter->num_vfs == 0)
a985b6c3
GR		 6977 return;
6978
6979 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6980
6981 /*
6982 * ssvpc register is cleared on read, if zero then no
6983 * spoofed packets in the last interval.
6984 */
6985 if (!ssvpc)
6986 return;
6987
d6ea0754 6988 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6989}
9079e416
ET		 6990#else
6991static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6992{
6993}
6994
6995static void
6996ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6997{
6998}
6999#endif /* CONFIG_PCI_IOV */
7000
a985b6c3 7001
93c52dd0
AD		 7002/**
7003 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 7004 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 7005 **/
7006static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7007{
09f40aed 7008 /* if interface is down, removing or resetting, do nothing */
7edebf9a 7009 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7010 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 7011 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 7012 return;
7013
7014 ixgbe_watchdog_update_link(adapter);
7015
7016 if (adapter->link_up)
7017 ixgbe_watchdog_link_is_up(adapter);
7018 else
7019 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 7020
9079e416 7021 ixgbe_check_for_bad_vf(adapter);
a985b6c3 7022 ixgbe_spoof_check(adapter);
9a799d71 7023 ixgbe_update_stats(adapter);
93c52dd0
AD		 7024
7025 ixgbe_watchdog_flush_tx(adapter);
9a799d71 7026}
10eec955 7027
cf8280ee 7028/**
7086400d 7029 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 7030 * @adapter: the ixgbe adapter structure
cf8280ee 7031 **/
7086400d 7032static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 7033{
cf8280ee 7034 struct ixgbe_hw *hw = &adapter->hw;
7086400d 7035 s32 err;
cf8280ee 7036
4319a797
DS		 7037 /* If crosstalk fix enabled verify the SFP+ cage is full */
7038 if (adapter->need_crosstalk_fix) {
7039 u32 sfp_cage_full;
7040
7041 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
7042 IXGBE_ESDP_SDP2;
7043 if (!sfp_cage_full)
7044 return;
7045 }
7046
7086400d
AD		 7047 /* not searching for SFP so there is nothing to do here */
7048 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7049 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7050 return;
10eec955 7051
58e7cd24
MR		 7052 if (adapter->sfp_poll_time &&
7053 time_after(adapter->sfp_poll_time, jiffies))
7054 return; /* If not yet time to poll for SFP */
7055
7086400d
AD		 7056 /* someone else is in init, wait until next service event */
7057 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7058 return;
cf8280ee 7059
58e7cd24
MR		 7060 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7061
7086400d
AD		 7062 err = hw->phy.ops.identify_sfp(hw);
7063 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7064 goto sfp_out;
264857b8 7065
7086400d
AD		 7066 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
7067 /* If no cable is present, then we need to reset
7068 * the next time we find a good cable. */
7069 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 7070 }
9a799d71 7071
7086400d
AD		 7072 /* exit on error */
7073 if (err)
7074 goto sfp_out;
e8e26350 7075
7086400d
AD		 7076 /* exit if reset not needed */
7077 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7078 goto sfp_out;
9a799d71 7079
7086400d 7080 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 7081
7086400d
AD		 7082 /*
7083 * A module may be identified correctly, but the EEPROM may not have
7084 * support for that module. setup_sfp() will fail in that case, so
7085 * we should not allow that module to load.
7086 */
7087 if (hw->mac.type == ixgbe_mac_82598EB)
7088 err = hw->phy.ops.reset(hw);
7089 else
7090 err = hw->mac.ops.setup_sfp(hw);
7091
7092 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
7093 goto sfp_out;
7094
7095 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7096 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7097
7098sfp_out:
7099 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7100
7101 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
7102 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
7103 e_dev_err("failed to initialize because an unsupported "
7104 "SFP+ module type was detected.\n");
7105 e_dev_err("Reload the driver after installing a "
7106 "supported module.\n");
7107 unregister_netdev(adapter->netdev);
bc59fcda 7108 }
7086400d 7109}
bc59fcda 7110
7086400d
AD		 7111/**
7112 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7113 * @adapter: the ixgbe adapter structure
7086400d
AD		 7114 **/
7115static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7116{
7117 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 7118 u32 speed;
7119 bool autoneg = false;
7086400d
AD		 7120
7121 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7122 return;
7123
7124 /* someone else is in init, wait until next service event */
7125 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7126 return;
7127
7128 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7129
3d292265 7130 speed = hw->phy.autoneg_advertised;
ed33ff66 7131 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 7132 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 7133
7134 /* setup the highest link when no autoneg */
7135 if (!autoneg) {
7136 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7137 speed = IXGBE_LINK_SPEED_10GB_FULL;
7138 }
7139 }
7140
7086400d 7141 if (hw->mac.ops.setup_link)
fd0326f2 7142 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7143
7144 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7145 adapter->link_check_timeout = jiffies;
7146 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7147}
7148
7149/**
7150 * ixgbe_service_timer - Timer Call-back
7151 * @data: pointer to adapter cast into an unsigned long
7152 **/
7153static void ixgbe_service_timer(unsigned long data)
7154{
7155 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7156 unsigned long next_event_offset;
7157
6bb78cfb
AD		 7158 /* poll faster when waiting for link */
7159 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7160 next_event_offset = HZ / 10;
7161 else
7162 next_event_offset = HZ * 2;
83c61fa9 7163
7086400d
AD		 7164 /* Reset the timer */
7165 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7166
9079e416 7167 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7168}
7169
597f22d6
DS		 7170static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7171{
7172 struct ixgbe_hw *hw = &adapter->hw;
7173 u32 status;
7174
7175 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7176 return;
7177
7178 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7179
7180 if (!hw->phy.ops.handle_lasi)
7181 return;
7182
7183 status = hw->phy.ops.handle_lasi(&adapter->hw);
7184 if (status != IXGBE_ERR_OVERTEMP)
7185 return;
7186
7187 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7188}
7189
c83c6cbd
AD		 7190static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7191{
7192 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
7193 return;
7194
7195 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
7196
09f40aed 7197 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7198 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7199 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 7200 test_bit(__IXGBE_RESETTING, &adapter->state))
7201 return;
7202
7203 ixgbe_dump(adapter);
7204 netdev_err(adapter->netdev, "Reset adapter\n");
7205 adapter->tx_timeout_count++;
7206
8f4c5c9f 7207 rtnl_lock();
c83c6cbd 7208 ixgbe_reinit_locked(adapter);
8f4c5c9f 7209 rtnl_unlock();
c83c6cbd
AD		 7210}
7211
7086400d
AD		 7212/**
7213 * ixgbe_service_task - manages and runs subtasks
7214 * @work: pointer to work_struct containing our data
7215 **/
7216static void ixgbe_service_task(struct work_struct *work)
7217{
7218 struct ixgbe_adapter *adapter = container_of(work,
7219 struct ixgbe_adapter,
7220 service_task);
b0483c8f
MR		 7221 if (ixgbe_removed(adapter->hw.hw_addr)) {
7222 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7223 rtnl_lock();
7224 ixgbe_down(adapter);
7225 rtnl_unlock();
7226 }
7227 ixgbe_service_event_complete(adapter);
7228 return;
7229 }
67359c3c 7230#ifdef CONFIG_IXGBE_VXLAN
b1f99a78 7231 rtnl_lock();
67359c3c
MR		 7232 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
7233 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
7234 vxlan_get_rx_port(adapter->netdev);
7235 }
b1f99a78 7236 rtnl_unlock();
67359c3c 7237#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 7238 ixgbe_reset_subtask(adapter);
597f22d6 7239 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7240 ixgbe_sfp_detection_subtask(adapter);
7241 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7242 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7243 ixgbe_watchdog_subtask(adapter);
d034acf1 7244 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7245 ixgbe_check_hang_subtask(adapter);
891dc082 7246
8fecf67c 7247 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 7248 ixgbe_ptp_overflow_check(adapter);
7249 ixgbe_ptp_rx_hang(adapter);
7250 }
7086400d
AD		 7251
7252 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7253}
7254
fd0db0ed
AD		 7255static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7256 struct ixgbe_tx_buffer *first,
244e27ad 7257 u8 *hdr_len)
897ab156 7258{
b83e3010 7259 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
fd0db0ed 7260 struct sk_buff *skb = first->skb;
b83e3010
AD		 7261 union {
7262 struct iphdr *v4;
7263 struct ipv6hdr *v6;
7264 unsigned char *hdr;
7265 } ip;
7266 union {
7267 struct tcphdr *tcp;
7268 unsigned char *hdr;
7269 } l4;
7270 u32 paylen, l4_offset;
2049e1f6 7271 int err;
9a799d71 7272
8f4fbb9b
AD		 7273 if (skb->ip_summed != CHECKSUM_PARTIAL)
7274 return 0;
7275
897ab156
AD		 7276 if (!skb_is_gso(skb))
7277 return 0;
9a799d71 7278
2049e1f6
FR		 7279 err = skb_cow_head(skb, 0);
7280 if (err < 0)
7281 return err;
9a799d71 7282
b83e3010
AD		 7283 ip.hdr = skb_network_header(skb);
7284 l4.hdr = skb_checksum_start(skb);
7285
897ab156
AD		 7286 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7287 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7288
b83e3010
AD		 7289 /* initialize outer IP header fields */
7290 if (ip.v4->version == 4) {
7291 /* IP header will have to cancel out any data that
7292 * is not a part of the outer IP header
7293 */
7294 ip.v4->check = csum_fold(csum_add(lco_csum(skb),
7295 csum_unfold(l4.tcp->check)));
897ab156 7296 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
b83e3010
AD		 7297
7298 ip.v4->tot_len = 0;
244e27ad
AD		 7299 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7300 IXGBE_TX_FLAGS_CSUM |
7301 IXGBE_TX_FLAGS_IPV4;
b83e3010
AD		 7302 } else {
7303 ip.v6->payload_len = 0;
244e27ad
AD		 7304 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7305 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7306 }
7307
b83e3010
AD		 7308 /* determine offset of inner transport header */
7309 l4_offset = l4.hdr - skb->data;
7310
7311 /* compute length of segmentation header */
7312 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
7313
7314 /* remove payload length from inner checksum */
7315 paylen = skb->len - l4_offset;
7316 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
897ab156 7317
091a6246
AD		 7318 /* update gso size and bytecount with header size */
7319 first->gso_segs = skb_shinfo(skb)->gso_segs;
7320 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7321
c44f5f51 7322 /* mss_l4len_id: use 0 as index for TSO */
b83e3010 7323 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
897ab156 7324 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7325
7326 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
b83e3010
AD		 7327 vlan_macip_lens = l4.hdr - ip.hdr;
7328 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7329 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7330
7331 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7332 mss_l4len_idx);
897ab156
AD		 7333
7334 return 1;
7335}
7336
49763de0
AD		 7337static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb)
7338{
7339 unsigned int offset = 0;
7340
7341 ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
7342
7343 return offset == skb_checksum_start_offset(skb);
7344}
7345
244e27ad
AD		 7346static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7347 struct ixgbe_tx_buffer *first)
7ca647bd 7348{
fd0db0ed 7349 struct sk_buff *skb = first->skb;
897ab156 7350 u32 vlan_macip_lens = 0;
897ab156 7351 u32 type_tucmd = 0;
7ca647bd 7352
897ab156 7353 if (skb->ip_summed != CHECKSUM_PARTIAL) {
49763de0
AD		 7354csum_failed:
7355 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
7356 IXGBE_TX_FLAGS_CC)))
472148c3 7357 return;
49763de0
AD		 7358 goto no_csum;
7359 }
897ab156 7360
49763de0
AD		 7361 switch (skb->csum_offset) {
7362 case offsetof(struct tcphdr, check):
7363 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7364 /* fall through */
7365 case offsetof(struct udphdr, check):
7366 break;
7367 case offsetof(struct sctphdr, checksum):
7368 /* validate that this is actually an SCTP request */
7369 if (((first->protocol == htons(ETH_P_IP)) &&
7370 (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
7371 ((first->protocol == htons(ETH_P_IPV6)) &&
7372 ixgbe_ipv6_csum_is_sctp(skb))) {
7373 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
897ab156 7374 break;
7ca647bd 7375 }
49763de0
AD		 7376 /* fall through */
7377 default:
7378 skb_checksum_help(skb);
7379 goto csum_failed;
7ca647bd
JP		 7380 }
7381
49763de0
AD		 7382 /* update TX checksum flag */
7383 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7384 vlan_macip_lens = skb_checksum_start_offset(skb) -
7385 skb_network_offset(skb);
36a92d71 7386no_csum:
244e27ad 7387 /* vlan_macip_lens: MACLEN, VLAN tag */
49763de0 7388 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7389 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7390
49763de0 7391 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0);
9a799d71
AK		 7392}
7393
472148c3
AD		 7394#define IXGBE_SET_FLAG(_input, _flag, _result) \
7395 ((_flag <= _result) ? \
7396 ((u32)(_input & _flag) * (_result / _flag)) : \
7397 ((u32)(_input & _flag) / (_flag / _result)))
7398
7399static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7400{
d3d00239 7401 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7402 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7403 IXGBE_ADVTXD_DCMD_DEXT |
7404 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7405
d3d00239 7406 /* set HW vlan bit if vlan is present */
472148c3
AD		 7407 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7408 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7409
d3d00239 7410 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7411 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7412 IXGBE_ADVTXD_DCMD_TSE);
7413
7414 /* set timestamp bit if present */
7415 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7416 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7417
62748b7b 7418 /* insert frame checksum */
472148c3 7419 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7420
d3d00239
AD		 7421 return cmd_type;
7422}
9a799d71 7423
729739b7
AD		 7424static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7425 u32 tx_flags, unsigned int paylen)
d3d00239 7426{
472148c3 7427 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7428
d3d00239 7429 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7430 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7431 IXGBE_TX_FLAGS_CSUM,
7432 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7433
93f5b3c1 7434 /* enble IPv4 checksum for TSO */
472148c3
AD		 7435 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7436 IXGBE_TX_FLAGS_IPV4,
7437 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7438
7f9643fd
AD		 7439 /*
7440 * Check Context must be set if Tx switch is enabled, which it
7441 * always is for case where virtual functions are running
7442 */
472148c3
AD		 7443 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7444 IXGBE_TX_FLAGS_CC,
7445 IXGBE_ADVTXD_CC);
7f9643fd 7446
472148c3 7447 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7448}
44df32c5 7449
2367a173
DB		 7450static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7451{
7452 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7453
7454 /* Herbert's original patch had:
7455 * smp_mb__after_netif_stop_queue();
7456 * but since that doesn't exist yet, just open code it.
7457 */
7458 smp_mb();
7459
7460 /* We need to check again in a case another CPU has just
7461 * made room available.
7462 */
7463 if (likely(ixgbe_desc_unused(tx_ring) < size))
7464 return -EBUSY;
7465
7466 /* A reprieve! - use start_queue because it doesn't call schedule */
7467 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7468 ++tx_ring->tx_stats.restart_queue;
7469 return 0;
7470}
7471
7472static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7473{
7474 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7475 return 0;
7476
7477 return __ixgbe_maybe_stop_tx(tx_ring, size);
7478}
7479
d3d00239
AD		 7480#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7481 IXGBE_TXD_CMD_RS)
7482
7483static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7484 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7485 const u8 hdr_len)
7486{
fd0db0ed 7487 struct sk_buff *skb = first->skb;
729739b7 7488 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7489 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7490 struct skb_frag_struct *frag;
7491 dma_addr_t dma;
7492 unsigned int data_len, size;
244e27ad 7493 u32 tx_flags = first->tx_flags;
472148c3 7494 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7495 u16 i = tx_ring->next_to_use;
d3d00239 7496
729739b7
AD		 7497 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7498
ec718254
AD		 7499 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7500
7501 size = skb_headlen(skb);
7502 data_len = skb->data_len;
729739b7 7503
d3d00239
AD		 7504#ifdef IXGBE_FCOE
7505 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7506 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7507 size -= sizeof(struct fcoe_crc_eof) - data_len;
7508 data_len = 0;
729739b7
AD		 7509 } else {
7510 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7511 }
7512 }
44df32c5 7513
d3d00239 7514#endif
729739b7 7515 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7516
ec718254 7517 tx_buffer = first;
9a799d71 7518
ec718254
AD		 7519 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7520 if (dma_mapping_error(tx_ring->dev, dma))
7521 goto dma_error;
7522
7523 /* record length, and DMA address */
7524 dma_unmap_len_set(tx_buffer, len, size);
7525 dma_unmap_addr_set(tx_buffer, dma, dma);
7526
7527 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7528
729739b7 7529 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7530 tx_desc->read.cmd_type_len =
472148c3 7531 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7532
d3d00239 7533 i++;
729739b7 7534 tx_desc++;
d3d00239 7535 if (i == tx_ring->count) {
e4f74028 7536 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7537 i = 0;
7538 }
ec718254 7539 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7540
7541 dma += IXGBE_MAX_DATA_PER_TXD;
7542 size -= IXGBE_MAX_DATA_PER_TXD;
7543
7544 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7545 }
e5a43549 7546
729739b7
AD		 7547 if (likely(!data_len))
7548 break;
9a799d71 7549
472148c3 7550 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7551
729739b7
AD		 7552 i++;
7553 tx_desc++;
7554 if (i == tx_ring->count) {
7555 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7556 i = 0;
7557 }
ec718254 7558 tx_desc->read.olinfo_status = 0;
9a799d71 7559
d3d00239 7560#ifdef IXGBE_FCOE
9e903e08 7561 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7562#else
9e903e08 7563 size = skb_frag_size(frag);
d3d00239
AD		 7564#endif
7565 data_len -= size;
9a799d71 7566
729739b7
AD		 7567 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7568 DMA_TO_DEVICE);
9a799d71 7569
729739b7 7570 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7571 }
9a799d71 7572
729739b7 7573 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7574 cmd_type |= size | IXGBE_TXD_CMD;
7575 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7576
091a6246 7577 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7578
d3d00239
AD		 7579 /* set the timestamp */
7580 first->time_stamp = jiffies;
9a799d71
AK		 7581
7582 /*
729739b7
AD		 7583 * Force memory writes to complete before letting h/w know there
7584 * are new descriptors to fetch. (Only applicable for weak-ordered
7585 * memory model archs, such as IA-64).
7586 *
7587 * We also need this memory barrier to make certain all of the
7588 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7589 */
7590 wmb();
7591
d3d00239
AD		 7592 /* set next_to_watch value indicating a packet is present */
7593 first->next_to_watch = tx_desc;
7594
729739b7
AD		 7595 i++;
7596 if (i == tx_ring->count)
7597 i = 0;
7598
7599 tx_ring->next_to_use = i;
7600
2367a173
DB		 7601 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7602
7603 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7604 writel(i, tx_ring->tail);
7605
7606 /* we need this if more than one processor can write to our tail
7607 * at a time, it synchronizes IO on IA64/Altix systems
7608 */
7609 mmiowb();
9c938cdd 7610 }
2367a173 7611
d3d00239
AD		 7612 return;
7613dma_error:
729739b7 7614 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7615
7616 /* clear dma mappings for failed tx_buffer_info map */
7617 for (;;) {
729739b7
AD		 7618 tx_buffer = &tx_ring->tx_buffer_info[i];
7619 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7620 if (tx_buffer == first)
d3d00239
AD		 7621 break;
7622 if (i == 0)
7623 i = tx_ring->count;
7624 i--;
7625 }
7626
d3d00239 7627 tx_ring->next_to_use = i;
9a799d71
AK		 7628}
7629
fd0db0ed 7630static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7631 struct ixgbe_tx_buffer *first)
69830529
AD		 7632{
7633 struct ixgbe_q_vector *q_vector = ring->q_vector;
7634 union ixgbe_atr_hash_dword input = { .dword = 0 };
7635 union ixgbe_atr_hash_dword common = { .dword = 0 };
7636 union {
7637 unsigned char *network;
7638 struct iphdr *ipv4;
7639 struct ipv6hdr *ipv6;
7640 } hdr;
ee9e0f0b 7641 struct tcphdr *th;
e2873d43 7642 unsigned int hlen;
67359c3c 7643 struct sk_buff *skb;
905e4a41 7644 __be16 vlan_id;
e2873d43 7645 int l4_proto;
c4cf55e5 7646
69830529
AD		 7647 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7648 if (!q_vector)
7649 return;
7650
7651 /* do nothing if sampling is disabled */
7652 if (!ring->atr_sample_rate)
d3ead241 7653 return;
c4cf55e5 7654
69830529 7655 ring->atr_count++;
c4cf55e5 7656
e2873d43
AD		 7657 /* currently only IPv4/IPv6 with TCP is supported */
7658 if ((first->protocol != htons(ETH_P_IP)) &&
7659 (first->protocol != htons(ETH_P_IPV6)))
7660 return;
7661
69830529 7662 /* snag network header to get L4 type and address */
67359c3c
MR		 7663 skb = first->skb;
7664 hdr.network = skb_network_header(skb);
67359c3c 7665#ifdef CONFIG_IXGBE_VXLAN
9f12df90
AD		 7666 if (skb->encapsulation &&
7667 first->protocol == htons(ETH_P_IP) &&
7668 hdr.ipv4->protocol != IPPROTO_UDP) {
67359c3c 7669 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7670
9f12df90
AD		 7671 /* verify the port is recognized as VXLAN */
7672 if (adapter->vxlan_port &&
e2873d43 7673 udp_hdr(skb)->dest == adapter->vxlan_port)
9f12df90 7674 hdr.network = skb_inner_network_header(skb);
e19dcdeb 7675 }
9f12df90 7676#endif /* CONFIG_IXGBE_VXLAN */
e19dcdeb
MR		 7677
7678 /* Currently only IPv4/IPv6 with TCP is supported */
7679 switch (hdr.ipv4->version) {
7680 case IPVERSION:
e2873d43
AD		 7681 /* access ihl as u8 to avoid unaligned access on ia64 */
7682 hlen = (hdr.network[0] & 0x0F) << 2;
7683 l4_proto = hdr.ipv4->protocol;
e19dcdeb
MR		 7684 break;
7685 case 6:
e2873d43
AD		 7686 hlen = hdr.network - skb->data;
7687 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
7688 hlen -= hdr.network - skb->data;
e19dcdeb
MR		 7689 break;
7690 default:
7691 return;
67359c3c 7692 }
c4cf55e5 7693
e2873d43
AD		 7694 if (l4_proto != IPPROTO_TCP)
7695 return;
7696
7697 th = (struct tcphdr *)(hdr.network + hlen);
7698
7699 /* skip this packet since the socket is closing */
7700 if (th->fin)
69830529
AD		 7701 return;
7702
7703 /* sample on all syn packets or once every atr sample count */
7704 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7705 return;
7706
7707 /* reset sample count */
7708 ring->atr_count = 0;
7709
244e27ad 7710 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7711
7712 /*
7713 * src and dst are inverted, think how the receiver sees them
7714 *
7715 * The input is broken into two sections, a non-compressed section
7716 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7717 * is XORed together and stored in the compressed dword.
7718 */
7719 input.formatted.vlan_id = vlan_id;
7720
7721 /*
7722 * since src port and flex bytes occupy the same word XOR them together
7723 * and write the value to source port portion of compressed dword
7724 */
244e27ad 7725 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7726 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7727 else
244e27ad 7728 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7729 common.port.dst ^= th->source;
7730
e19dcdeb
MR		 7731 switch (hdr.ipv4->version) {
7732 case IPVERSION:
69830529
AD		 7733 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7734 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
e19dcdeb
MR		 7735 break;
7736 case 6:
69830529
AD		 7737 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7738 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7739 hdr.ipv6->saddr.s6_addr32[1] ^
7740 hdr.ipv6->saddr.s6_addr32[2] ^
7741 hdr.ipv6->saddr.s6_addr32[3] ^
7742 hdr.ipv6->daddr.s6_addr32[0] ^
7743 hdr.ipv6->daddr.s6_addr32[1] ^
7744 hdr.ipv6->daddr.s6_addr32[2] ^
7745 hdr.ipv6->daddr.s6_addr32[3];
e19dcdeb
MR		 7746 break;
7747 default:
7748 break;
69830529 7749 }
c4cf55e5 7750
9f12df90 7751 if (hdr.network != skb_network_header(skb))
67359c3c 7752 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
67359c3c 7753
c4cf55e5 7754 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7755 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7756 input, common, ring->queue_index);
c4cf55e5
PWJ		 7757}
7758
f663dd9a 7759static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7760 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7761{
f663dd9a
JW		 7762 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7763#ifdef IXGBE_FCOE
97488bd1
AD		 7764 struct ixgbe_adapter *adapter;
7765 struct ixgbe_ring_feature *f;
7766 int txq;
f663dd9a
JW		 7767#endif
7768
7769 if (fwd_adapter)
7770 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7771
7772#ifdef IXGBE_FCOE
5e09a105 7773
97488bd1
AD		 7774 /*
7775 * only execute the code below if protocol is FCoE
7776 * or FIP and we have FCoE enabled on the adapter
7777 */
7778 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7779 case htons(ETH_P_FCOE):
7780 case htons(ETH_P_FIP):
97488bd1 7781 adapter = netdev_priv(dev);
c087663e 7782
97488bd1
AD		 7783 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7784 break;
7785 default:
99932d4f 7786 return fallback(dev, skb);
97488bd1 7787 }
c087663e 7788
97488bd1 7789 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7790
97488bd1
AD		 7791 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7792 smp_processor_id();
56075a98 7793
97488bd1
AD		 7794 while (txq >= f->indices)
7795 txq -= f->indices;
c4cf55e5 7796
97488bd1 7797 return txq + f->offset;
f663dd9a 7798#else
99932d4f 7799 return fallback(dev, skb);
f663dd9a 7800#endif
09a3b1f8
SH		 7801}
7802
fc77dc3c 7803netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7804 struct ixgbe_adapter *adapter,
7805 struct ixgbe_ring *tx_ring)
9a799d71 7806{
d3d00239 7807 struct ixgbe_tx_buffer *first;
5f715823 7808 int tso;
d3d00239 7809 u32 tx_flags = 0;
a535c30e 7810 unsigned short f;
a535c30e 7811 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7812 __be16 protocol = skb->protocol;
63544e9c 7813 u8 hdr_len = 0;
5e09a105 7814
a535c30e
AD		 7815 /*
7816 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7817 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7818 * + 2 desc gap to keep tail from touching head,
7819 * + 1 desc for context descriptor,
7820 * otherwise try next time
7821 */
a535c30e
AD		 7822 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7823 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7824
a535c30e
AD		 7825 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7826 tx_ring->tx_stats.tx_busy++;
7827 return NETDEV_TX_BUSY;
7828 }
7829
fd0db0ed
AD		 7830 /* record the location of the first descriptor for this packet */
7831 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7832 first->skb = skb;
091a6246
AD		 7833 first->bytecount = skb->len;
7834 first->gso_segs = 1;
fd0db0ed 7835
66f32a8b 7836 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7837 if (skb_vlan_tag_present(skb)) {
7838 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7839 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7840 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7841 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7842 struct vlan_hdr *vhdr, _vhdr;
7843 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7844 if (!vhdr)
7845 goto out_drop;
7846
9e0c5648
AD		 7847 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7848 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7849 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7850 }
0213668f 7851 protocol = vlan_get_protocol(skb);
66f32a8b 7852
d5234933
MR		 7853 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7854 adapter->ptp_clock &&
7855 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7856 &adapter->state)) {
3a6a4eda
JK		 7857 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7858 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7859
7860 /* schedule check for Tx timestamp */
7861 adapter->ptp_tx_skb = skb_get(skb);
7862 adapter->ptp_tx_start = jiffies;
7863 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7864 }
3a6a4eda 7865
ff29a86e
JK		 7866 skb_tx_timestamp(skb);
7867
9e0c5648
AD		 7868#ifdef CONFIG_PCI_IOV
7869 /*
7870 * Use the l2switch_enable flag - would be false if the DMA
7871 * Tx switch had been disabled.
7872 */
7873 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7874 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7875
7876#endif
32701dc2 7877 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7878 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7879 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7880 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7881 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7882 tx_flags |= (skb->priority & 0x7) <<
7883 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7884 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7885 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7886
7887 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7888 goto out_drop;
7889 vhdr = (struct vlan_ethhdr *)skb->data;
7890 vhdr->h_vlan_TCI = htons(tx_flags >>
7891 IXGBE_TX_FLAGS_VLAN_SHIFT);
7892 } else {
7893 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7894 }
9a799d71 7895 }
eacd73f7 7896
244e27ad
AD		 7897 /* record initial flags and protocol */
7898 first->tx_flags = tx_flags;
7899 first->protocol = protocol;
7900
eacd73f7 7901#ifdef IXGBE_FCOE
66f32a8b 7902 /* setup tx offload for FCoE */
a1108ffd 7903 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7904 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7905 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7906 if (tso < 0)
7907 goto out_drop;
9a799d71 7908
66f32a8b 7909 goto xmit_fcoe;
eacd73f7 7910 }
9a799d71 7911
66f32a8b 7912#endif /* IXGBE_FCOE */
244e27ad 7913 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7914 if (tso < 0)
897ab156 7915 goto out_drop;
244e27ad
AD		 7916 else if (!tso)
7917 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7918
7919 /* add the ATR filter if ATR is on */
7920 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7921 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7922
7923#ifdef IXGBE_FCOE
7924xmit_fcoe:
7925#endif /* IXGBE_FCOE */
244e27ad 7926 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7927
9a799d71 7928 return NETDEV_TX_OK;
897ab156
AD		 7929
7930out_drop:
fd0db0ed
AD		 7931 dev_kfree_skb_any(first->skb);
7932 first->skb = NULL;
7933
897ab156 7934 return NETDEV_TX_OK;
9a799d71
AK		 7935}
7936
2a47fa45
JF		 7937static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7938 struct net_device *netdev,
7939 struct ixgbe_ring *ring)
84418e3b
AD		 7940{
7941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7942 struct ixgbe_ring *tx_ring;
7943
a50c29dd
AD		 7944 /*
7945 * The minimum packet size for olinfo paylen is 17 so pad the skb
7946 * in order to meet this minimum size requirement.
7947 */
a94d9e22
AD		 7948 if (skb_put_padto(skb, 17))
7949 return NETDEV_TX_OK;
a50c29dd 7950
2a47fa45
JF		 7951 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7952
fc77dc3c 7953 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7954}
7955
2a47fa45
JF		 7956static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7957 struct net_device *netdev)
7958{
7959 return __ixgbe_xmit_frame(skb, netdev, NULL);
7960}
7961
9a799d71
AK		 7962/**
7963 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7964 * @netdev: network interface device structure
7965 * @p: pointer to an address structure
7966 *
7967 * Returns 0 on success, negative on failure
7968 **/
7969static int ixgbe_set_mac(struct net_device *netdev, void *p)
7970{
7971 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7972 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7973 struct sockaddr *addr = p;
7974
7975 if (!is_valid_ether_addr(addr->sa_data))
7976 return -EADDRNOTAVAIL;
7977
7978 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7979 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7980
c9f53e63
AD		 7981 ixgbe_mac_set_default_filter(adapter);
7982
7983 return 0;
9a799d71
AK		 7984}
7985
6b73e10d
BH		 7986static int
7987ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7988{
7989 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7990 struct ixgbe_hw *hw = &adapter->hw;
7991 u16 value;
7992 int rc;
7993
7994 if (prtad != hw->phy.mdio.prtad)
7995 return -EINVAL;
7996 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7997 if (!rc)
7998 rc = value;
7999 return rc;
8000}
8001
8002static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8003 u16 addr, u16 value)
8004{
8005 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8006 struct ixgbe_hw *hw = &adapter->hw;
8007
8008 if (prtad != hw->phy.mdio.prtad)
8009 return -EINVAL;
8010 return hw->phy.ops.write_reg(hw, addr, devad, value);
8011}
8012
8013static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8014{
8015 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8016
3a6a4eda 8017 switch (cmd) {
3a6a4eda 8018 case SIOCSHWTSTAMP:
93501d48
JK		 8019 return ixgbe_ptp_set_ts_config(adapter, req);
8020 case SIOCGHWTSTAMP:
8021 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 8022 default:
8023 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
8024 }
6b73e10d
BH		 8025}
8026
0365e6e4
PW		 8027/**
8028 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 8029 * netdev->dev_addrs
0365e6e4
PW		 8030 * @netdev: network interface device structure
8031 *
8032 * Returns non-zero on failure
8033 **/
8034static int ixgbe_add_sanmac_netdev(struct net_device *dev)
8035{
8036 int err = 0;
8037 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 8038 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 8039
7fa7c9dc 8040 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 8041 rtnl_lock();
7fa7c9dc 8042 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 8043 rtnl_unlock();
7fa7c9dc
AD		 8044
8045 /* update SAN MAC vmdq pool selection */
8046 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 8047 }
8048 return err;
8049}
8050
8051/**
8052 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 8053 * netdev->dev_addrs
0365e6e4
PW		 8054 * @netdev: network interface device structure
8055 *
8056 * Returns non-zero on failure
8057 **/
8058static int ixgbe_del_sanmac_netdev(struct net_device *dev)
8059{
8060 int err = 0;
8061 struct ixgbe_adapter *adapter = netdev_priv(dev);
8062 struct ixgbe_mac_info *mac = &adapter->hw.mac;
8063
8064 if (is_valid_ether_addr(mac->san_addr)) {
8065 rtnl_lock();
8066 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
8067 rtnl_unlock();
8068 }
8069 return err;
8070}
8071
9a799d71
AK		 8072#ifdef CONFIG_NET_POLL_CONTROLLER
8073/*
8074 * Polling 'interrupt' - used by things like netconsole to send skbs
8075 * without having to re-enable interrupts. It's not called while
8076 * the interrupt routine is executing.
8077 */
8078static void ixgbe_netpoll(struct net_device *netdev)
8079{
8080 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 8081 int i;
9a799d71 8082
1a647bd2
AD		 8083 /* if interface is down do nothing */
8084 if (test_bit(__IXGBE_DOWN, &adapter->state))
8085 return;
8086
856f606e
AD		 8087 /* loop through and schedule all active queues */
8088 for (i = 0; i < adapter->num_q_vectors; i++)
8089 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 8090}
9a799d71 8091
581330ba 8092#endif
de1036b1
ED		 8093static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
8094 struct rtnl_link_stats64 *stats)
8095{
8096 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8097 int i;
8098
1a51502b 8099 rcu_read_lock();
de1036b1 8100 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 8101 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8102 u64 bytes, packets;
8103 unsigned int start;
8104
1a51502b
ED		 8105 if (ring) {
8106 do {
57a7744e 8107 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8108 packets = ring->stats.packets;
8109 bytes = ring->stats.bytes;
57a7744e 8110 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8111 stats->rx_packets += packets;
8112 stats->rx_bytes += bytes;
8113 }
de1036b1 8114 }
1ac9ad13
ED		 8115
8116 for (i = 0; i < adapter->num_tx_queues; i++) {
8117 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8118 u64 bytes, packets;
8119 unsigned int start;
8120
8121 if (ring) {
8122 do {
57a7744e 8123 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 8124 packets = ring->stats.packets;
8125 bytes = ring->stats.bytes;
57a7744e 8126 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 8127 stats->tx_packets += packets;
8128 stats->tx_bytes += bytes;
8129 }
8130 }
1a51502b 8131 rcu_read_unlock();
de1036b1
ED		 8132 /* following stats updated by ixgbe_watchdog_task() */
8133 stats->multicast = netdev->stats.multicast;
8134 stats->rx_errors = netdev->stats.rx_errors;
8135 stats->rx_length_errors = netdev->stats.rx_length_errors;
8136 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8137 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8138 return stats;
8139}
8140
8af3c33f 8141#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8142/**
8143 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8144 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8145 * @tc: number of traffic classes currently enabled
8146 *
8147 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8148 * 802.1Q priority maps to a packet buffer that exists.
8149 */
8150static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8151{
8152 struct ixgbe_hw *hw = &adapter->hw;
8153 u32 reg, rsave;
8154 int i;
8155
8156 /* 82598 have a static priority to TC mapping that can not
8157 * be changed so no validation is needed.
8158 */
8159 if (hw->mac.type == ixgbe_mac_82598EB)
8160 return;
8161
8162 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8163 rsave = reg;
8164
8165 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8166 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8167
8168 /* If up2tc is out of bounds default to zero */
8169 if (up2tc > tc)
8170 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8171 }
8172
8173 if (reg != rsave)
8174 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8175
8176 return;
8177}
8178
02debdc9
AD		 8179/**
8180 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8181 * @adapter: Pointer to adapter struct
8182 *
8183 * Populate the netdev user priority to tc map
8184 */
8185static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8186{
8187 struct net_device *dev = adapter->netdev;
8188 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8189 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8190 u8 prio;
8191
8192 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8193 u8 tc = 0;
8194
8195 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8196 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8197 else if (ets)
8198 tc = ets->prio_tc[prio];
8199
8200 netdev_set_prio_tc_map(dev, prio, tc);
8201 }
8202}
8203
cca73c59 8204#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 8205/**
8206 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 8207 *
8208 * @netdev: net device to configure
8209 * @tc: number of traffic classes to enable
8210 */
8211int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8212{
8b1c0b24
JF		 8213 struct ixgbe_adapter *adapter = netdev_priv(dev);
8214 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 8215 bool pools;
8b1c0b24 8216
8b1c0b24 8217 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 8218 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8219 return -EINVAL;
8220
8221 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 8222 return -EINVAL;
8223
2a47fa45
JF		 8224 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8225 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8226 return -EBUSY;
8227
8b1c0b24 8228 /* Hardware has to reinitialize queues and interrupts to
52f33af8 8229 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 8230 * hardware is not flexible enough to do this dynamically.
8231 */
8232 if (netif_running(dev))
8233 ixgbe_close(dev);
bf4d67d9
AD		 8234 else
8235 ixgbe_reset(adapter);
8236
8b1c0b24
JF		 8237 ixgbe_clear_interrupt_scheme(adapter);
8238
cca73c59 8239#ifdef CONFIG_IXGBE_DCB
e7589eab 8240 if (tc) {
8b1c0b24 8241 netdev_set_num_tc(dev, tc);
02debdc9
AD		 8242 ixgbe_set_prio_tc_map(adapter);
8243
e7589eab 8244 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 8245
943561d3
AD		 8246 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8247 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 8248 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 8249 }
e7589eab 8250 } else {
8b1c0b24 8251 netdev_reset_tc(dev);
02debdc9 8252
943561d3
AD		 8253 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8254 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 8255
8256 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 8257
8258 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8259 adapter->dcb_cfg.pfc_mode_enable = false;
8260 }
8261
8b1c0b24 8262 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 8263
8264#endif /* CONFIG_IXGBE_DCB */
8265 ixgbe_init_interrupt_scheme(adapter);
8266
8b1c0b24 8267 if (netif_running(dev))
cca73c59 8268 return ixgbe_open(dev);
8b1c0b24
JF		 8269
8270 return 0;
8271}
de1036b1 8272
b82b17d9
JF		 8273static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8274 struct tc_cls_u32_offload *cls)
8275{
176621c9
SS		 8276 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
8277 u32 loc;
b82b17d9
JF		 8278 int err;
8279
176621c9
SS		 8280 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
8281 return -EINVAL;
8282
8283 loc = cls->knode.handle & 0xfffff;
8284
b82b17d9 8285 spin_lock(&adapter->fdir_perfect_lock);
176621c9 8286 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
b82b17d9
JF		 8287 spin_unlock(&adapter->fdir_perfect_lock);
8288 return err;
8289}
8290
db956ae8
JF		 8291static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8292 __be16 protocol,
8293 struct tc_cls_u32_offload *cls)
8294{
176621c9
SS		 8295 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8296
8297 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8298 return -EINVAL;
8299
db956ae8
JF		 8300 /* This ixgbe devices do not support hash tables at the moment
8301 * so abort when given hash tables.
8302 */
8303 if (cls->hnode.divisor > 0)
8304 return -EINVAL;
8305
176621c9 8306 set_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8307 return 0;
8308}
8309
8310static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8311 struct tc_cls_u32_offload *cls)
8312{
176621c9
SS		 8313 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
8314
8315 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8316 return -EINVAL;
8317
8318 clear_bit(uhtid - 1, &adapter->tables);
db956ae8
JF		 8319 return 0;
8320}
8321
b82b17d9
JF		 8322static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
8323 __be16 protocol,
8324 struct tc_cls_u32_offload *cls)
8325{
8326 u32 loc = cls->knode.handle & 0xfffff;
8327 struct ixgbe_hw *hw = &adapter->hw;
8328 struct ixgbe_mat_field *field_ptr;
8329 struct ixgbe_fdir_filter *input;
8330 union ixgbe_atr_input mask;
8331#ifdef CONFIG_NET_CLS_ACT
8332 const struct tc_action *a;
8333#endif
8334 int i, err = 0;
8335 u8 queue;
176621c9 8336 u32 uhtid, link_uhtid;
b82b17d9
JF		 8337
8338 memset(&mask, 0, sizeof(union ixgbe_atr_input));
176621c9
SS		 8339 uhtid = TC_U32_USERHTID(cls->knode.handle);
8340 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
b82b17d9 8341
176621c9 8342 /* At the moment cls_u32 jumps to network layer and skips past
b82b17d9
JF		 8343 * L2 headers. The canonical method to match L2 frames is to use
8344 * negative values. However this is error prone at best but really
8345 * just broken because there is no way to "know" what sort of hdr
176621c9 8346 * is in front of the network layer. Fix cls_u32 to support L2
b82b17d9
JF		 8347 * headers when needed.
8348 */
8349 if (protocol != htons(ETH_P_IP))
8350 return -EINVAL;
8351
176621c9 8352 if (link_uhtid) {
b82b17d9 8353 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
b82b17d9 8354
176621c9
SS		 8355 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
8356 return -EINVAL;
8357
8358 if (!test_bit(link_uhtid - 1, &adapter->tables))
db956ae8
JF		 8359 return -EINVAL;
8360
b82b17d9 8361 for (i = 0; nexthdr[i].jump; i++) {
4ae78342
AN		 8362 if (nexthdr[i].o != cls->knode.sel->offoff ||
8363 nexthdr[i].s != cls->knode.sel->offshift ||
8364 nexthdr[i].m != cls->knode.sel->offmask ||
b82b17d9
JF		 8365 /* do not support multiple key jumps its just mad */
8366 cls->knode.sel->nkeys > 1)
8367 return -EINVAL;
8368
4ae78342
AN		 8369 if (nexthdr[i].off == cls->knode.sel->keys[0].off &&
8370 nexthdr[i].val == cls->knode.sel->keys[0].val &&
8371 nexthdr[i].mask == cls->knode.sel->keys[0].mask) {
8372 adapter->jump_tables[link_uhtid] =
8373 nexthdr[i].jump;
8374 break;
8375 }
b82b17d9
JF		 8376 }
8377 return 0;
8378 }
8379
8380 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
8381 e_err(drv, "Location out of range\n");
8382 return -EINVAL;
8383 }
8384
8385 /* cls u32 is a graph starting at root node 0x800. The driver tracks
8386 * links and also the fields used to advance the parser across each
8387 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
8388 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
8389 * To add support for new nodes update ixgbe_model.h parse structures
8390 * this function _should_ be generic try not to hardcode values here.
8391 */
176621c9 8392 if (uhtid == 0x800) {
b82b17d9
JF		 8393 field_ptr = adapter->jump_tables[0];
8394 } else {
176621c9 8395 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
b82b17d9
JF		 8396 return -EINVAL;
8397
176621c9 8398 field_ptr = adapter->jump_tables[uhtid];
b82b17d9
JF		 8399 }
8400
8401 if (!field_ptr)
8402 return -EINVAL;
8403
8404 input = kzalloc(sizeof(*input), GFP_KERNEL);
8405 if (!input)
8406 return -ENOMEM;
8407
8408 for (i = 0; i < cls->knode.sel->nkeys; i++) {
8409 int off = cls->knode.sel->keys[i].off;
8410 __be32 val = cls->knode.sel->keys[i].val;
8411 __be32 m = cls->knode.sel->keys[i].mask;
8412 bool found_entry = false;
8413 int j;
8414
8415 for (j = 0; field_ptr[j].val; j++) {
ebd83ad8 8416 if (field_ptr[j].off == off) {
b82b17d9
JF		 8417 field_ptr[j].val(input, &mask, val, m);
8418 input->filter.formatted.flow_type |=
8419 field_ptr[j].type;
8420 found_entry = true;
8421 break;
8422 }
8423 }
8424
8425 if (!found_entry)
8426 goto err_out;
8427 }
8428
8429 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
8430 IXGBE_ATR_L4TYPE_MASK;
8431
8432 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
8433 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
8434
8435#ifdef CONFIG_NET_CLS_ACT
8436 if (list_empty(&cls->knode.exts->actions))
8437 goto err_out;
8438
8439 list_for_each_entry(a, &cls->knode.exts->actions, list) {
8440 if (!is_tcf_gact_shot(a))
8441 goto err_out;
8442 }
8443#endif
8444
8445 input->action = IXGBE_FDIR_DROP_QUEUE;
8446 queue = IXGBE_FDIR_DROP_QUEUE;
8447 input->sw_idx = loc;
8448
8449 spin_lock(&adapter->fdir_perfect_lock);
8450
8451 if (hlist_empty(&adapter->fdir_filter_list)) {
8452 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
8453 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
8454 if (err)
8455 goto err_out_w_lock;
8456 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
8457 err = -EINVAL;
8458 goto err_out_w_lock;
8459 }
8460
8461 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
8462 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
8463 input->sw_idx, queue);
8464 if (!err)
8465 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
8466 spin_unlock(&adapter->fdir_perfect_lock);
8467
8468 return err;
8469err_out_w_lock:
8470 spin_unlock(&adapter->fdir_perfect_lock);
8471err_out:
8472 kfree(input);
8473 return -EINVAL;
8474}
8475
6e2a60b5
ET		 8476static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
8477 struct tc_to_netdev *tc)
e4c6734e 8478{
b82b17d9
JF		 8479 struct ixgbe_adapter *adapter = netdev_priv(dev);
8480
8481 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
8482 tc->type == TC_SETUP_CLSU32) {
b82b17d9
JF		 8483 switch (tc->cls_u32->command) {
8484 case TC_CLSU32_NEW_KNODE:
8485 case TC_CLSU32_REPLACE_KNODE:
8486 return ixgbe_configure_clsu32(adapter,
8487 proto, tc->cls_u32);
8488 case TC_CLSU32_DELETE_KNODE:
8489 return ixgbe_delete_clsu32(adapter, tc->cls_u32);
db956ae8
JF		 8490 case TC_CLSU32_NEW_HNODE:
8491 case TC_CLSU32_REPLACE_HNODE:
8492 return ixgbe_configure_clsu32_add_hnode(adapter, proto,
8493 tc->cls_u32);
8494 case TC_CLSU32_DELETE_HNODE:
8495 return ixgbe_configure_clsu32_del_hnode(adapter,
8496 tc->cls_u32);
b82b17d9
JF		 8497 default:
8498 return -EINVAL;
8499 }
8500 }
8501
5eb4dce3 8502 if (tc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 8503 return -EINVAL;
8504
16e5cc64 8505 return ixgbe_setup_tc(dev, tc->tc);
e4c6734e
JF		 8506}
8507
da36b647
GR		 8508#ifdef CONFIG_PCI_IOV
8509void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8510{
8511 struct net_device *netdev = adapter->netdev;
8512
8513 rtnl_lock();
da36b647 8514 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 8515 rtnl_unlock();
8516}
8517
8518#endif
082757af
DS		 8519void ixgbe_do_reset(struct net_device *netdev)
8520{
8521 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8522
8523 if (netif_running(netdev))
8524 ixgbe_reinit_locked(adapter);
8525 else
8526 ixgbe_reset(adapter);
8527}
8528
c8f44aff 8529static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 8530 netdev_features_t features)
082757af
DS		 8531{
8532 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8533
082757af 8534 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 8535 if (!(features & NETIF_F_RXCSUM))
8536 features &= ~NETIF_F_LRO;
082757af 8537
567d2de2
AD		 8538 /* Turn off LRO if not RSC capable */
8539 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8540 features &= ~NETIF_F_LRO;
8e2813f5 8541
567d2de2 8542 return features;
082757af
DS		 8543}
8544
c8f44aff 8545static int ixgbe_set_features(struct net_device *netdev,
567d2de2 8546 netdev_features_t features)
082757af
DS		 8547{
8548 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 8549 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 8550 bool need_reset = false;
8551
082757af 8552 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 8553 if (!(features & NETIF_F_LRO)) {
8554 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8555 need_reset = true;
567d2de2
AD		 8556 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8557 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8558 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8559 if (adapter->rx_itr_setting == 1 ||
8560 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8561 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8562 need_reset = true;
8563 } else if ((changed ^ features) & NETIF_F_LRO) {
8564 e_info(probe, "rx-usecs set too low, "
8565 "disabling RSC\n");
082757af
DS		 8566 }
8567 }
8568
8569 /*
b82b17d9
JF		 8570 * Check if Flow Director n-tuple support or hw_tc support was
8571 * enabled or disabled. If the state changed, we need to reset.
082757af 8572 */
b82b17d9 8573 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
567d2de2 8574 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8575 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8576 need_reset = true;
8577
567d2de2
AD		 8578 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8579 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
b82b17d9 8580 } else {
39cb681b
AD		 8581 /* turn off perfect filters, enable ATR and reset */
8582 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8583 need_reset = true;
8584
8585 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8586
8587 /* We cannot enable ATR if SR-IOV is enabled */
b82b17d9
JF		 8588 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
8589 /* We cannot enable ATR if we have 2 or more tcs */
8590 (netdev_get_num_tc(netdev) > 1) ||
8591 /* We cannot enable ATR if RSS is disabled */
8592 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
8593 /* A sample rate of 0 indicates ATR disabled */
8594 (!adapter->atr_sample_rate))
8595 ; /* do nothing not supported */
8596 else /* otherwise supported and set the flag */
8597 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 8598 }
8599
3f2d1c0f
BG		 8600 if (changed & NETIF_F_RXALL)
8601 need_reset = true;
8602
567d2de2 8603 netdev->features = features;
67359c3c
MR		 8604
8605#ifdef CONFIG_IXGBE_VXLAN
8606 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8607 if (features & NETIF_F_RXCSUM)
8608 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8609 else
8610 ixgbe_clear_vxlan_port(adapter);
8611 }
8612#endif /* CONFIG_IXGBE_VXLAN */
8613
082757af
DS		 8614 if (need_reset)
8615 ixgbe_do_reset(netdev);
0c5a6166
AD		 8616 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
8617 NETIF_F_HW_VLAN_CTAG_FILTER))
8618 ixgbe_set_rx_mode(netdev);
082757af
DS		 8619
8620 return 0;
082757af
DS		 8621}
8622
67359c3c 8623#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8624/**
8625 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8626 * @dev: The port's netdev
8627 * @sa_family: Socket Family that VXLAN is notifiying us about
8628 * @port: New UDP port number that VXLAN started listening to
8629 **/
8630static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8631 __be16 port)
8632{
8633 struct ixgbe_adapter *adapter = netdev_priv(dev);
8634 struct ixgbe_hw *hw = &adapter->hw;
3f207800 8635
67359c3c
MR		 8636 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8637 return;
8638
3f207800
DS		 8639 if (sa_family == AF_INET6)
8640 return;
8641
9f12df90 8642 if (adapter->vxlan_port == port)
3f207800 8643 return;
3f207800
DS		 8644
8645 if (adapter->vxlan_port) {
8646 netdev_info(dev,
67359c3c 8647 "Hit Max num of VXLAN ports, not adding port %d\n",
9f12df90 8648 ntohs(port));
3f207800
DS		 8649 return;
8650 }
8651
9f12df90
AD		 8652 adapter->vxlan_port = port;
8653 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, ntohs(port));
3f207800
DS		 8654}
8655
8656/**
8657 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8658 * @dev: The port's netdev
8659 * @sa_family: Socket Family that VXLAN is notifying us about
8660 * @port: UDP port number that VXLAN stopped listening to
8661 **/
8662static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8663 __be16 port)
8664{
8665 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800 8666
67359c3c
MR		 8667 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8668 return;
8669
3f207800
DS		 8670 if (sa_family == AF_INET6)
8671 return;
8672
9f12df90 8673 if (adapter->vxlan_port != port) {
3f207800 8674 netdev_info(dev, "Port %d was not found, not deleting\n",
9f12df90 8675 ntohs(port));
3f207800
DS		 8676 return;
8677 }
8678
67359c3c
MR		 8679 ixgbe_clear_vxlan_port(adapter);
8680 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8681}
67359c3c 8682#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8683
edc7d573 8684static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8685 struct net_device *dev,
f6f6424b 8686 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8687 u16 flags)
8688{
bcfd3432 8689 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8690 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 8691 struct ixgbe_adapter *adapter = netdev_priv(dev);
8692 u16 pool = VMDQ_P(0);
8693
8694 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 8695 return -ENOMEM;
0f4b0add
JF		 8696 }
8697
f6f6424b 8698 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8699}
8700
219efe97
DS		 8701/**
8702 * ixgbe_configure_bridge_mode - set various bridge modes
8703 * @adapter - the private structure
8704 * @mode - requested bridge mode
8705 *
8706 * Configure some settings require for various bridge modes.
8707 **/
8708static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8709 __u16 mode)
8710{
6d4c96ad
DS		 8711 struct ixgbe_hw *hw = &adapter->hw;
8712 unsigned int p, num_pools;
8713 u32 vmdctl;
8714
219efe97
DS		 8715 switch (mode) {
8716 case BRIDGE_MODE_VEPA:
6d4c96ad 8717 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8718 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8719
8720 /* must enable Rx switching replication to allow multicast
8721 * packet reception on all VFs, and to enable source address
8722 * pruning.
8723 */
8724 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8725 vmdctl |= IXGBE_VT_CTL_REPLEN;
8726 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8727
8728 /* enable Rx source address pruning. Note, this requires
8729 * replication to be enabled or else it does nothing.
8730 */
8731 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8732 for (p = 0; p < num_pools; p++) {
8733 if (hw->mac.ops.set_source_address_pruning)
8734 hw->mac.ops.set_source_address_pruning(hw,
8735 true,
8736 p);
8737 }
219efe97
DS		 8738 break;
8739 case BRIDGE_MODE_VEB:
6d4c96ad 8740 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8741 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8742 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8743
8744 /* disable Rx switching replication unless we have SR-IOV
8745 * virtual functions
8746 */
8747 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8748 if (!adapter->num_vfs)
8749 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8750 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8751
8752 /* disable Rx source address pruning, since we don't expect to
8753 * be receiving external loopback of our transmitted frames.
8754 */
8755 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8756 for (p = 0; p < num_pools; p++) {
8757 if (hw->mac.ops.set_source_address_pruning)
8758 hw->mac.ops.set_source_address_pruning(hw,
8759 false,
8760 p);
8761 }
219efe97
DS		 8762 break;
8763 default:
8764 return -EINVAL;
8765 }
8766
8767 adapter->bridge_mode = mode;
8768
8769 e_info(drv, "enabling bridge mode: %s\n",
8770 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8771
8772 return 0;
8773}
8774
815cccbf 8775static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8776 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8777{
8778 struct ixgbe_adapter *adapter = netdev_priv(dev);
8779 struct nlattr *attr, *br_spec;
8780 int rem;
8781
8782 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8783 return -EOPNOTSUPP;
8784
8785 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8786 if (!br_spec)
8787 return -EINVAL;
815cccbf
JF		 8788
8789 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8790 int status;
815cccbf 8791 __u16 mode;
815cccbf
JF		 8792
8793 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8794 continue;
8795
b7c1a314
TG		 8796 if (nla_len(attr) < sizeof(mode))
8797 return -EINVAL;
8798
815cccbf 8799 mode = nla_get_u16(attr);
219efe97
DS		 8800 status = ixgbe_configure_bridge_mode(adapter, mode);
8801 if (status)
8802 return status;
aa2bacb6
DS		 8803
8804 break;
815cccbf
JF		 8805 }
8806
8807 return 0;
8808}
8809
8810static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8811 struct net_device *dev,
46c264da 8812 u32 filter_mask, int nlflags)
815cccbf
JF		 8813{
8814 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8815
8816 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8817 return 0;
8818
aa2bacb6 8819 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8820 adapter->bridge_mode, 0, 0, nlflags,
8821 filter_mask, NULL);
815cccbf
JF		 8822}
8823
2a47fa45
JF		 8824static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8825{
8826 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8827 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8828 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8829 unsigned int limit;
2a47fa45
JF		 8830 int pool, err;
8831
aac2f1bf
JK		 8832 /* Hardware has a limited number of available pools. Each VF, and the
8833 * PF require a pool. Check to ensure we don't attempt to use more
8834 * then the available number of pools.
8835 */
8836 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8837 return ERR_PTR(-EINVAL);
8838
219354d4
JF		 8839#ifdef CONFIG_RPS
8840 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8841 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8842 vdev->name);
8843 return ERR_PTR(-EINVAL);
8844 }
8845#endif
2a47fa45 8846 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8847 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8848 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8849 netdev_info(pdev,
8850 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8851 pdev->name);
8852 return ERR_PTR(-EINVAL);
8853 }
8854
8855 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8856 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8857 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8858 return ERR_PTR(-EBUSY);
8859
bc52f951 8860 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8861 if (!fwd_adapter)
8862 return ERR_PTR(-ENOMEM);
8863
8864 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8865 adapter->num_rx_pools++;
8866 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8867 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8868
8869 /* Enable VMDq flag so device will be set in VM mode */
8870 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8871 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8872 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8873
8874 /* Force reinit of ring allocation with VMDQ enabled */
8875 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8876 if (err)
8877 goto fwd_add_err;
8878 fwd_adapter->pool = pool;
8879 fwd_adapter->real_adapter = adapter;
8880 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8881 if (err)
8882 goto fwd_add_err;
8883 netif_tx_start_all_queues(vdev);
8884 return fwd_adapter;
8885fwd_add_err:
8886 /* unwind counter and free adapter struct */
8887 netdev_info(pdev,
8888 "%s: dfwd hardware acceleration failed\n", vdev->name);
8889 clear_bit(pool, &adapter->fwd_bitmask);
8890 adapter->num_rx_pools--;
8891 kfree(fwd_adapter);
8892 return ERR_PTR(err);
8893}
8894
8895static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8896{
8897 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8898 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8899 unsigned int limit;
2a47fa45
JF		 8900
8901 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8902 adapter->num_rx_pools--;
8903
51f3773b
JF		 8904 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8905 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8906 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8907 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8908 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8909 fwd_adapter->pool, adapter->num_rx_pools,
8910 fwd_adapter->rx_base_queue,
8911 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8912 adapter->fwd_bitmask);
8913 kfree(fwd_adapter);
8914}
8915
b83e3010
AD		 8916#define IXGBE_MAX_MAC_HDR_LEN 127
8917#define IXGBE_MAX_NETWORK_HDR_LEN 511
8918
f467bc06
MR		 8919static netdev_features_t
8920ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8921 netdev_features_t features)
8922{
b83e3010
AD		 8923 unsigned int network_hdr_len, mac_hdr_len;
8924
8925 /* Make certain the headers can be described by a context descriptor */
8926 mac_hdr_len = skb_network_header(skb) - skb->data;
8927 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
8928 return features & ~(NETIF_F_HW_CSUM |
8929 NETIF_F_SCTP_CRC |
8930 NETIF_F_HW_VLAN_CTAG_TX |
8931 NETIF_F_TSO |
8932 NETIF_F_TSO6);
8933
8934 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
8935 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
8936 return features & ~(NETIF_F_HW_CSUM |
8937 NETIF_F_SCTP_CRC |
8938 NETIF_F_TSO |
8939 NETIF_F_TSO6);
8940
8941 /* We can only support IPV4 TSO in tunnels if we can mangle the
8942 * inner IP ID field, so strip TSO if MANGLEID is not supported.
8943 */
8944 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
8945 features &= ~NETIF_F_TSO;
f467bc06
MR		 8946
8947 return features;
8948}
8949
0edc3527 8950static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8951 .ndo_open = ixgbe_open,
0edc3527 8952 .ndo_stop = ixgbe_close,
00829823 8953 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8954 .ndo_select_queue = ixgbe_select_queue,
581330ba 8955 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8956 .ndo_validate_addr = eth_validate_addr,
8957 .ndo_set_mac_address = ixgbe_set_mac,
8958 .ndo_change_mtu = ixgbe_change_mtu,
8959 .ndo_tx_timeout = ixgbe_tx_timeout,
c04f90e5 8960 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
0edc3527
SH		 8961 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8962 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8963 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8964 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8965 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8966 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8967 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8968 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 8969 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 8970 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8971 .ndo_get_stats64 = ixgbe_get_stats64,
e4c6734e 8972 .ndo_setup_tc = __ixgbe_setup_tc,
0edc3527
SH		 8973#ifdef CONFIG_NET_POLL_CONTROLLER
8974 .ndo_poll_controller = ixgbe_netpoll,
8975#endif
e0d1095a 8976#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8977 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8978#endif
332d4a7d
YZ		 8979#ifdef IXGBE_FCOE
8980 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8981 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8982 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8983 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8984 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8985 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8986 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8987#endif /* IXGBE_FCOE */
082757af
DS		 8988 .ndo_set_features = ixgbe_set_features,
8989 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8990 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8991 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8992 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8993 .ndo_dfwd_add_station = ixgbe_fwd_add,
8994 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8995#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8996 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8997 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8998#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8999 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 9000};
9001
e027d1ae
JK		 9002/**
9003 * ixgbe_enumerate_functions - Get the number of ports this device has
9004 * @adapter: adapter structure
9005 *
9006 * This function enumerates the phsyical functions co-located on a single slot,
9007 * in order to determine how many ports a device has. This is most useful in
9008 * determining the required GT/s of PCIe bandwidth necessary for optimal
9009 * performance.
9010 **/
9011static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
9012{
caafb95d 9013 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 9014 int physfns = 0;
9015
f1f96579
JK		 9016 /* Some cards can not use the generic count PCIe functions method,
9017 * because they are behind a parent switch, so we hardcode these with
9018 * the correct number of functions.
e027d1ae 9019 */
8818970d 9020 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 9021 physfns = 4;
8818970d
JK		 9022
9023 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
9024 /* don't count virtual functions */
caafb95d
JK		 9025 if (entry->is_virtfn)
9026 continue;
9027
9028 /* When the devices on the bus don't all match our device ID,
9029 * we can't reliably determine the correct number of
9030 * functions. This can occur if a function has been direct
9031 * attached to a virtual machine using VT-d, for example. In
9032 * this case, simply return -1 to indicate this.
9033 */
9034 if ((entry->vendor != pdev->vendor) ||
9035 (entry->device != pdev->device))
9036 return -1;
9037
9038 physfns++;
e027d1ae
JK		 9039 }
9040
9041 return physfns;
9042}
9043
8e2813f5
JK		 9044/**
9045 * ixgbe_wol_supported - Check whether device supports WoL
9046 * @hw: hw specific details
9047 * @device_id: the device ID
9048 * @subdev_id: the subsystem device ID
9049 *
9050 * This function is used by probe and ethtool to determine
9051 * which devices have WoL support
9052 *
9053 **/
9054int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
9055 u16 subdevice_id)
9056{
9057 struct ixgbe_hw *hw = &adapter->hw;
9058 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
9059 int is_wol_supported = 0;
9060
9061 switch (device_id) {
9062 case IXGBE_DEV_ID_82599_SFP:
9063 /* Only these subdevices could supports WOL */
9064 switch (subdevice_id) {
87557440 9065 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 9066 case IXGBE_SUBDEV_ID_82599_560FLR:
9067 /* only support first port */
9068 if (hw->bus.func != 0)
9069 break;
5700ff26 9070 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 9071 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 9072 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 9073 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 9074 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 9075 is_wol_supported = 1;
9076 break;
9077 }
9078 break;
5daebbb0
DS		 9079 case IXGBE_DEV_ID_82599EN_SFP:
9080 /* Only this subdevice supports WOL */
9081 switch (subdevice_id) {
9082 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
9083 is_wol_supported = 1;
9084 break;
9085 }
9086 break;
8e2813f5
JK		 9087 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
9088 /* All except this subdevice support WOL */
9089 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9090 is_wol_supported = 1;
9091 break;
9092 case IXGBE_DEV_ID_82599_KX4:
9093 is_wol_supported = 1;
9094 break;
9095 case IXGBE_DEV_ID_X540T:
df376f0d 9096 case IXGBE_DEV_ID_X540T1:
df8c26fd 9097 case IXGBE_DEV_ID_X550T:
a711ad89 9098 case IXGBE_DEV_ID_X550T1:
df8c26fd
DS		 9099 case IXGBE_DEV_ID_X550EM_X_KX4:
9100 case IXGBE_DEV_ID_X550EM_X_KR:
9101 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 9102 /* check eeprom to see if enabled wol */
9103 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
9104 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
9105 (hw->bus.func == 0))) {
9106 is_wol_supported = 1;
9107 }
9108 break;
9109 }
9110
9111 return is_wol_supported;
9112}
9113
9a799d71
AK		 9114/**
9115 * ixgbe_probe - Device Initialization Routine
9116 * @pdev: PCI device information struct
9117 * @ent: entry in ixgbe_pci_tbl
9118 *
9119 * Returns 0 on success, negative on failure
9120 *
9121 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
9122 * The OS initialization, configuring of the adapter private structure,
9123 * and a hardware reset occur.
9124 **/
1dd06ae8 9125static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 9126{
9127 struct net_device *netdev;
9128 struct ixgbe_adapter *adapter = NULL;
9129 struct ixgbe_hw *hw;
9130 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 9131 int i, err, pci_using_dac, expected_gts;
d3cb9869 9132 unsigned int indices = MAX_TX_QUEUES;
289700db 9133 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 9134 bool disable_dev = false;
eacd73f7
YZ		 9135#ifdef IXGBE_FCOE
9136 u16 device_caps;
9137#endif
289700db 9138 u32 eec;
9a799d71 9139
bded64a7
AG		 9140 /* Catch broken hardware that put the wrong VF device ID in
9141 * the PCIe SR-IOV capability.
9142 */
9143 if (pdev->is_virtfn) {
9144 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
9145 pci_name(pdev), pdev->vendor, pdev->device);
9146 return -EINVAL;
9147 }
9148
9ce77666 9149 err = pci_enable_device_mem(pdev);
9a799d71
AK		 9150 if (err)
9151 return err;
9152
f5f2eda8 9153 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 9154 pci_using_dac = 1;
9155 } else {
f5f2eda8 9156 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 9157 if (err) {
f5f2eda8
RK		 9158 dev_err(&pdev->dev,
9159 "No usable DMA configuration, aborting\n");
9160 goto err_dma;
9a799d71
AK		 9161 }
9162 pci_using_dac = 0;
9163 }
9164
9ce77666 9165 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9166 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 9167 if (err) {
b8bc0421
DC		 9168 dev_err(&pdev->dev,
9169 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 9170 goto err_pci_reg;
9171 }
9172
19d5afd4 9173 pci_enable_pcie_error_reporting(pdev);
6fabd715 9174
9a799d71 9175 pci_set_master(pdev);
fb3b27bc 9176 pci_save_state(pdev);
9a799d71 9177
d3cb9869 9178 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 9179#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 9180 /* 8 TC w/ 4 queues per TC */
9181 indices = 4 * MAX_TRAFFIC_CLASS;
9182#else
9183 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 9184#endif
d3cb9869 9185 }
e901acd6 9186
c85a2618 9187 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 9188 if (!netdev) {
9189 err = -ENOMEM;
9190 goto err_alloc_etherdev;
9191 }
9192
9a799d71
AK		 9193 SET_NETDEV_DEV(netdev, &pdev->dev);
9194
9a799d71
AK		 9195 adapter = netdev_priv(netdev);
9196
9197 adapter->netdev = netdev;
9198 adapter->pdev = pdev;
9199 hw = &adapter->hw;
9200 hw->back = adapter;
b3f4d599 9201 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 9202
05857980 9203 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 9204 pci_resource_len(pdev, 0));
2a1a091c 9205 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 9206 if (!hw->hw_addr) {
9207 err = -EIO;
9208 goto err_ioremap;
9209 }
9210
0edc3527 9211 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 9212 ixgbe_set_ethtool_ops(netdev);
9a799d71 9213 netdev->watchdog_timeo = 5 * HZ;
339de30f 9214 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 9215
9a799d71 9216 /* Setup hw api */
37689010 9217 hw->mac.ops = *ii->mac_ops;
021230d4 9218 hw->mac.type = ii->mac;
9a900eca 9219 hw->mvals = ii->mvals;
9a799d71 9220
c44ade9e 9221 /* EEPROM */
37689010 9222 hw->eeprom.ops = *ii->eeprom_ops;
9a900eca 9223 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 9224 if (ixgbe_removed(hw->hw_addr)) {
9225 err = -EIO;
9226 goto err_ioremap;
9227 }
c44ade9e 9228 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
b4f47a48 9229 if (!(eec & BIT(8)))
c44ade9e
JB		 9230 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9231
9232 /* PHY */
37689010 9233 hw->phy.ops = *ii->phy_ops;
c4900be0 9234 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 9235 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
9236 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
9237 hw->phy.mdio.mmds = 0;
9238 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9239 hw->phy.mdio.dev = netdev;
9240 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
9241 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 9242
8ca783ab 9243 ii->get_invariants(hw);
9a799d71
AK		 9244
9245 /* setup the private structure */
9246 err = ixgbe_sw_init(adapter);
9247 if (err)
9248 goto err_sw_init;
9249
dbd15b8f
DS		 9250 /* Make sure the SWFW semaphore is in a valid state */
9251 if (hw->mac.ops.init_swfw_sync)
9252 hw->mac.ops.init_swfw_sync(hw);
9253
e86bff0e 9254 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 9255 switch (adapter->hw.mac.type) {
9256 case ixgbe_mac_82599EB:
9257 case ixgbe_mac_X540:
9a75a1ac
DS		 9258 case ixgbe_mac_X550:
9259 case ixgbe_mac_X550EM_x:
49425dfc 9260 case ixgbe_mac_x550em_a:
e86bff0e 9261 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 9262 break;
9263 default:
9264 break;
9265 }
e86bff0e 9266
bf069c97
DS		 9267 /*
9268 * If there is a fan on this device and it has failed log the
9269 * failure.
9270 */
9271 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
9272 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
9273 if (esdp & IXGBE_ESDP_SDP1)
396e799c 9274 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 9275 }
9276
8ef78adc
PWJ		 9277 if (allow_unsupported_sfp)
9278 hw->allow_unsupported_sfp = allow_unsupported_sfp;
9279
c44ade9e 9280 /* reset_hw fills in the perm_addr as well */
119fc60a 9281 hw->phy.reset_if_overtemp = true;
c44ade9e 9282 err = hw->mac.ops.reset_hw(hw);
119fc60a 9283 hw->phy.reset_if_overtemp = false;
29a8dca1 9284 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 9285 err = 0;
9286 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 9287 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
9288 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 9289 goto err_sw_init;
9290 } else if (err) {
849c4542 9291 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 9292 goto err_sw_init;
9293 }
9294
99d74487 9295#ifdef CONFIG_PCI_IOV
60a1a680
GR		 9296 /* SR-IOV not supported on the 82598 */
9297 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9298 goto skip_sriov;
9299 /* Mailbox */
9300 ixgbe_init_mbx_params_pf(hw);
37689010 9301 hw->mbx.ops = ii->mbx_ops;
dcc23e3a 9302 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 9303 ixgbe_enable_sriov(adapter);
60a1a680 9304skip_sriov:
1cdd1ec8 9305
99d74487 9306#endif
396e799c 9307 netdev->features = NETIF_F_SG |
082757af
DS		 9308 NETIF_F_TSO |
9309 NETIF_F_TSO6 |
082757af 9310 NETIF_F_RXHASH |
49763de0 9311 NETIF_F_RXCSUM |
b83e3010
AD		 9312 NETIF_F_HW_CSUM;
9313
9314#define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
9315 NETIF_F_GSO_GRE_CSUM | \
9316 NETIF_F_GSO_IPIP | \
9317 NETIF_F_GSO_SIT | \
9318 NETIF_F_GSO_UDP_TUNNEL | \
9319 NETIF_F_GSO_UDP_TUNNEL_CSUM)
9320
9321 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
9322 netdev->features |= NETIF_F_GSO_PARTIAL |
9323 IXGBE_GSO_PARTIAL_FEATURES;
ad31c402 9324
49763de0 9325 if (hw->mac.type >= ixgbe_mac_82599EB)
53692b1d 9326 netdev->features |= NETIF_F_SCTP_CRC;
49763de0
AD		 9327
9328 /* copy netdev features into list of user selectable features */
b83e3010
AD		 9329 netdev->hw_features |= netdev->features |
9330 NETIF_F_HW_VLAN_CTAG_RX |
9331 NETIF_F_HW_VLAN_CTAG_TX |
9332 NETIF_F_RXALL |
49763de0
AD		 9333 NETIF_F_HW_L2FW_DOFFLOAD;
9334
9335 if (hw->mac.type >= ixgbe_mac_82599EB)
9336 netdev->hw_features |= NETIF_F_NTUPLE |
b82b17d9 9337 NETIF_F_HW_TC;
45a5ead0 9338
b83e3010
AD		 9339 if (pci_using_dac)
9340 netdev->features |= NETIF_F_HIGHDMA;
9341
9342 /* set this bit last since it cannot be part of vlan_features */
9343 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
9344 NETIF_F_HW_VLAN_CTAG_RX |
9345 NETIF_F_HW_VLAN_CTAG_TX;
ad31c402 9346
b83e3010
AD		 9347 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
9348 netdev->hw_enc_features |= netdev->vlan_features;
49763de0 9349 netdev->mpls_features |= NETIF_F_HW_CSUM;
f467bc06 9350
01789349 9351 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 9352 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 9353
7a6b6f51 9354#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 9355 netdev->dcbnl_ops = &dcbnl_ops;
9356#endif
9357
eacd73f7 9358#ifdef IXGBE_FCOE
0d551589 9359 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 9360 unsigned int fcoe_l;
9361
eacd73f7
YZ		 9362 if (hw->mac.ops.get_device_caps) {
9363 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 9364 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9365 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 9366 }
7c8ae65a 9367
d3cb9869
AD		 9368
9369 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9370 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 9371
a58915c7
AD		 9372 netdev->features |= NETIF_F_FSO |
9373 NETIF_F_FCOE_CRC;
9374
7c8ae65a
AD		 9375 netdev->vlan_features |= NETIF_F_FSO |
9376 NETIF_F_FCOE_CRC |
9377 NETIF_F_FCOE_MTU;
5e09d7f6 9378 }
eacd73f7 9379#endif /* IXGBE_FCOE */
9a799d71 9380
082757af
DS		 9381 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9382 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 9383 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 9384 netdev->features |= NETIF_F_LRO;
9385
9a799d71 9386 /* make sure the EEPROM is good */
c44ade9e 9387 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 9388 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 9389 err = -EIO;
35937c05 9390 goto err_sw_init;
9a799d71
AK		 9391 }
9392
c7374b5a
SV		 9393 eth_platform_get_mac_address(&adapter->pdev->dev,
9394 adapter->hw.mac.perm_addr);
c762dff2 9395
9a799d71 9396 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 9397
aaeb6cdf 9398 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 9399 e_dev_err("invalid MAC address\n");
9a799d71 9400 err = -EIO;
35937c05 9401 goto err_sw_init;
9a799d71
AK		 9402 }
9403
56768045
TD		 9404 /* Set hw->mac.addr to permanent MAC address */
9405 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
c9f53e63 9406 ixgbe_mac_set_default_filter(adapter);
5d7daa35 9407
7086400d 9408 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 9409 (unsigned long) adapter);
9a799d71 9410
58cf663f
MR		 9411 if (ixgbe_removed(hw->hw_addr)) {
9412 err = -EIO;
9413 goto err_sw_init;
9414 }
7086400d 9415 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 9416 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 9417 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 9418
021230d4
AV		 9419 err = ixgbe_init_interrupt_scheme(adapter);
9420 if (err)
9421 goto err_sw_init;
9a799d71 9422
8e2813f5 9423 /* WOL not supported for all devices */
c23f5b6b 9424 adapter->wol = 0;
8e2813f5 9425 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 9426 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 9427 pdev->subsystem_device);
6b92b0ba 9428 if (hw->wol_enabled)
9417c464 9429 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 9430
e8e26350
PW		 9431 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9432
15e5209f
ET		 9433 /* save off EEPROM version number */
9434 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9435 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9436
04f165ef 9437 /* pick up the PCI bus settings for reporting later */
e027d1ae 9438 if (ixgbe_pcie_from_parent(hw))
b8e82001 9439 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 9440 else
9441 hw->mac.ops.get_bus_info(hw);
04f165ef 9442
e027d1ae
JK		 9443 /* calculate the expected PCIe bandwidth required for optimal
9444 * performance. Note that some older parts will never have enough
9445 * bandwidth due to being older generation PCIe parts. We clamp these
9446 * parts to ensure no warning is displayed if it can't be fixed.
9447 */
9448 switch (hw->mac.type) {
9449 case ixgbe_mac_82598EB:
9450 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9451 break;
9452 default:
9453 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9454 break;
0c254d86 9455 }
caafb95d
JK		 9456
9457 /* don't check link if we failed to enumerate functions */
9458 if (expected_gts > 0)
9459 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 9460
339de30f 9461 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 9462 if (err)
339de30f 9463 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 9464 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9465 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9466 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 9467 part_str);
6a2aae5a
JK		 9468 else
9469 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9470 hw->mac.type, hw->phy.type, part_str);
9471
9472 e_dev_info("%pM\n", netdev->dev_addr);
9473
9a799d71 9474 /* reset the hardware with the new settings */
794caeb2 9475 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 9476 if (err == IXGBE_ERR_EEPROM_VERSION) {
9477 /* We are running on a pre-production device, log a warning */
849c4542
ET		 9478 e_dev_warn("This device is a pre-production adapter/LOM. "
9479 "Please be aware there may be issues associated "
9480 "with your hardware. If you are experiencing "
9481 "problems please contact your Intel or hardware "
9482 "representative who provided you with this "
9483 "hardware.\n");
794caeb2 9484 }
9a799d71
AK		 9485 strcpy(netdev->name, "eth%d");
9486 err = register_netdev(netdev);
9487 if (err)
9488 goto err_register;
9489
0fb6a55c
ET		 9490 pci_set_drvdata(pdev, adapter);
9491
ec74a471
ET		 9492 /* power down the optics for 82599 SFP+ fiber */
9493 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 9494 hw->mac.ops.disable_tx_laser(hw);
9495
54386467
JB		 9496 /* carrier off reporting is important to ethtool even BEFORE open */
9497 netif_carrier_off(netdev);
9498
5dd2d332 9499#ifdef CONFIG_IXGBE_DCA
652f093f 9500 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 9501 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 9502 ixgbe_setup_dca(adapter);
9503 }
9504#endif
1cdd1ec8 9505 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 9506 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 9507 for (i = 0; i < adapter->num_vfs; i++)
9508 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9509 }
9510
2466dd9c
JK		 9511 /* firmware requires driver version to be 0xFFFFFFFF
9512 * since os does not support feature
9513 */
9612de92 9514 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 9515 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9516 0xFF);
9612de92 9517
0365e6e4
PW		 9518 /* add san mac addr to netdev */
9519 ixgbe_add_sanmac_netdev(netdev);
9a799d71 9520
ea81875a 9521 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 9522
1210982b 9523#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 9524 if (ixgbe_sysfs_init(adapter))
9525 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 9526#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9527
00949167 9528 ixgbe_dbg_adapter_init(adapter);
00949167 9529
d1a35ee2
ET		 9530 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9531 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 9532 hw->mac.ops.setup_link(hw,
9533 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9534 true);
9535
9a799d71
AK		 9536 return 0;
9537
9538err_register:
5eba3699 9539 ixgbe_release_hw_control(adapter);
7a921c93 9540 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 9541err_sw_init:
99d74487 9542 ixgbe_disable_sriov(adapter);
7086400d 9543 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 9544 iounmap(adapter->io_addr);
5d7daa35 9545 kfree(adapter->mac_table);
9a799d71 9546err_ioremap:
b5b2ffc0 9547 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9548 free_netdev(netdev);
9549err_alloc_etherdev:
e8e9f696
JP		 9550 pci_release_selected_regions(pdev,
9551 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 9552err_pci_reg:
9553err_dma:
b5b2ffc0 9554 if (!adapter || disable_dev)
41c62843 9555 pci_disable_device(pdev);
9a799d71
AK		 9556 return err;
9557}
9558
9559/**
9560 * ixgbe_remove - Device Removal Routine
9561 * @pdev: PCI device information struct
9562 *
9563 * ixgbe_remove is called by the PCI subsystem to alert the driver
9564 * that it should release a PCI device. The could be caused by a
9565 * Hot-Plug event, or because the driver is going to be removed from
9566 * memory.
9567 **/
9f9a12f8 9568static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9569{
c60fbb00 9570 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9571 struct net_device *netdev;
b5b2ffc0 9572 bool disable_dev;
9a799d71 9573
0fb6a55c
ET		 9574 /* if !adapter then we already cleaned up in probe */
9575 if (!adapter)
9576 return;
9577
9578 netdev = adapter->netdev;
00949167 9579 ixgbe_dbg_adapter_exit(adapter);
00949167 9580
09f40aed 9581 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9582 cancel_work_sync(&adapter->service_task);
9a799d71 9583
3a6a4eda 9584
5dd2d332 9585#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9586 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9587 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9588 dca_remove_requester(&pdev->dev);
9de7605e
MR		 9589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9590 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 9591 }
9592
9593#endif
1210982b 9594#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9595 ixgbe_sysfs_exit(adapter);
1210982b 9596#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9597
0365e6e4
PW		 9598 /* remove the added san mac */
9599 ixgbe_del_sanmac_netdev(netdev);
9600
da36b647 9601#ifdef CONFIG_PCI_IOV
7837e286 9602 ixgbe_disable_sriov(adapter);
da36b647 9603#endif
6b010e9b
AW		 9604 if (netdev->reg_state == NETREG_REGISTERED)
9605 unregister_netdev(netdev);
9606
7a921c93 9607 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9608
021230d4 9609 ixgbe_release_hw_control(adapter);
9a799d71 9610
2b1588c3
AD		 9611#ifdef CONFIG_DCB
9612 kfree(adapter->ixgbe_ieee_pfc);
9613 kfree(adapter->ixgbe_ieee_ets);
9614
9615#endif
2a1a091c 9616 iounmap(adapter->io_addr);
9ce77666 9617 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9618 IORESOURCE_MEM));
9a799d71 9619
849c4542 9620 e_dev_info("complete\n");
021230d4 9621
5d7daa35 9622 kfree(adapter->mac_table);
b5b2ffc0 9623 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9624 free_netdev(netdev);
9625
19d5afd4 9626 pci_disable_pcie_error_reporting(pdev);
6fabd715 9627
b5b2ffc0 9628 if (disable_dev)
41c62843 9629 pci_disable_device(pdev);
9a799d71
AK		 9630}
9631
9632/**
9633 * ixgbe_io_error_detected - called when PCI error is detected
9634 * @pdev: Pointer to PCI device
9635 * @state: The current pci connection state
9636 *
9637 * This function is called after a PCI bus error affecting
9638 * this device has been detected.
9639 */
9640static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9641 pci_channel_state_t state)
9a799d71 9642{
c60fbb00
AD		 9643 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9644 struct net_device *netdev = adapter->netdev;
9a799d71 9645
83c61fa9 9646#ifdef CONFIG_PCI_IOV
14438464 9647 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9648 struct pci_dev *bdev, *vfdev;
9649 u32 dw0, dw1, dw2, dw3;
9650 int vf, pos;
9651 u16 req_id, pf_func;
9652
9653 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9654 adapter->num_vfs == 0)
9655 goto skip_bad_vf_detection;
9656
9657 bdev = pdev->bus->self;
62f87c0e 9658 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9659 bdev = bdev->bus->self;
9660
9661 if (!bdev)
9662 goto skip_bad_vf_detection;
9663
9664 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9665 if (!pos)
9666 goto skip_bad_vf_detection;
9667
14438464
MR		 9668 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9669 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9670 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9671 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9672 if (ixgbe_removed(hw->hw_addr))
9673 goto skip_bad_vf_detection;
83c61fa9
GR		 9674
9675 req_id = dw1 >> 16;
9676 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9677 if (!(req_id & 0x0080))
9678 goto skip_bad_vf_detection;
9679
9680 pf_func = req_id & 0x01;
9681 if ((pf_func & 1) == (pdev->devfn & 1)) {
9682 unsigned int device_id;
9683
9684 vf = (req_id & 0x7F) >> 1;
9685 e_dev_err("VF %d has caused a PCIe error\n", vf);
9686 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9687 "%8.8x\tdw3: %8.8x\n",
9688 dw0, dw1, dw2, dw3);
9689 switch (adapter->hw.mac.type) {
9690 case ixgbe_mac_82599EB:
9691 device_id = IXGBE_82599_VF_DEVICE_ID;
9692 break;
9693 case ixgbe_mac_X540:
9694 device_id = IXGBE_X540_VF_DEVICE_ID;
9695 break;
9a75a1ac
DS		 9696 case ixgbe_mac_X550:
9697 device_id = IXGBE_DEV_ID_X550_VF;
9698 break;
9699 case ixgbe_mac_X550EM_x:
9700 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9701 break;
49425dfc
MR		 9702 case ixgbe_mac_x550em_a:
9703 device_id = IXGBE_DEV_ID_X550EM_A_VF;
9704 break;
83c61fa9
GR		 9705 default:
9706 device_id = 0;
9707 break;
9708 }
9709
9710 /* Find the pci device of the offending VF */
36e90319 9711 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9712 while (vfdev) {
9713 if (vfdev->devfn == (req_id & 0xFF))
9714 break;
36e90319 9715 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9716 device_id, vfdev);
9717 }
9718 /*
9719 * There's a slim chance the VF could have been hot plugged,
9720 * so if it is no longer present we don't need to issue the
9721 * VFLR. Just clean up the AER in that case.
9722 */
9723 if (vfdev) {
9079e416 9724 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9725 /* Free device reference count */
9726 pci_dev_put(vfdev);
83c61fa9
GR		 9727 }
9728
9729 pci_cleanup_aer_uncorrect_error_status(pdev);
9730 }
9731
9732 /*
9733 * Even though the error may have occurred on the other port
9734 * we still need to increment the vf error reference count for
9735 * both ports because the I/O resume function will be called
9736 * for both of them.
9737 */
9738 adapter->vferr_refcount++;
9739
9740 return PCI_ERS_RESULT_RECOVERED;
9741
9742skip_bad_vf_detection:
9743#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9744 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9745 return PCI_ERS_RESULT_DISCONNECT;
9746
41c62843 9747 rtnl_lock();
9a799d71
AK		 9748 netif_device_detach(netdev);
9749
41c62843
MR		 9750 if (state == pci_channel_io_perm_failure) {
9751 rtnl_unlock();
3044b8d1 9752 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9753 }
3044b8d1 9754
9a799d71
AK		 9755 if (netif_running(netdev))
9756 ixgbe_down(adapter);
41c62843
MR		 9757
9758 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9759 pci_disable_device(pdev);
9760 rtnl_unlock();
9a799d71 9761
b4617240 9762 /* Request a slot reset. */
9a799d71
AK		 9763 return PCI_ERS_RESULT_NEED_RESET;
9764}
9765
9766/**
9767 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9768 * @pdev: Pointer to PCI device
9769 *
9770 * Restart the card from scratch, as if from a cold-boot.
9771 */
9772static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9773{
c60fbb00 9774 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9775 pci_ers_result_t result;
9776 int err;
9a799d71 9777
9ce77666 9778 if (pci_enable_device_mem(pdev)) {
396e799c 9779 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9780 result = PCI_ERS_RESULT_DISCONNECT;
9781 } else {
4e857c58 9782 smp_mb__before_atomic();
41c62843 9783 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9784 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9785 pci_set_master(pdev);
9786 pci_restore_state(pdev);
c0e1f68b 9787 pci_save_state(pdev);
9a799d71 9788
dd4d8ca6 9789 pci_wake_from_d3(pdev, false);
9a799d71 9790
6fabd715 9791 ixgbe_reset(adapter);
88512539 9792 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9793 result = PCI_ERS_RESULT_RECOVERED;
9794 }
9795
9796 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9797 if (err) {
849c4542
ET		 9798 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9799 "failed 0x%0x\n", err);
6fabd715
PWJ		 9800 /* non-fatal, continue */
9801 }
9a799d71 9802
6fabd715 9803 return result;
9a799d71
AK		 9804}
9805
9806/**
9807 * ixgbe_io_resume - called when traffic can start flowing again.
9808 * @pdev: Pointer to PCI device
9809 *
9810 * This callback is called when the error recovery driver tells us that
9811 * its OK to resume normal operation.
9812 */
9813static void ixgbe_io_resume(struct pci_dev *pdev)
9814{
c60fbb00
AD		 9815 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9816 struct net_device *netdev = adapter->netdev;
9a799d71 9817
83c61fa9
GR		 9818#ifdef CONFIG_PCI_IOV
9819 if (adapter->vferr_refcount) {
9820 e_info(drv, "Resuming after VF err\n");
9821 adapter->vferr_refcount--;
9822 return;
9823 }
9824
9825#endif
c7ccde0f
AD		 9826 if (netif_running(netdev))
9827 ixgbe_up(adapter);
9a799d71
AK		 9828
9829 netif_device_attach(netdev);
9a799d71
AK		 9830}
9831
3646f0e5 9832static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9833 .error_detected = ixgbe_io_error_detected,
9834 .slot_reset = ixgbe_io_slot_reset,
9835 .resume = ixgbe_io_resume,
9836};
9837
9838static struct pci_driver ixgbe_driver = {
9839 .name = ixgbe_driver_name,
9840 .id_table = ixgbe_pci_tbl,
9841 .probe = ixgbe_probe,
9f9a12f8 9842 .remove = ixgbe_remove,
9a799d71
AK		 9843#ifdef CONFIG_PM
9844 .suspend = ixgbe_suspend,
9845 .resume = ixgbe_resume,
9846#endif
9847 .shutdown = ixgbe_shutdown,
da36b647 9848 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9849 .err_handler = &ixgbe_err_handler
9850};
9851
9852/**
9853 * ixgbe_init_module - Driver Registration Routine
9854 *
9855 * ixgbe_init_module is the first routine called when the driver is
9856 * loaded. All it does is register with the PCI subsystem.
9857 **/
9858static int __init ixgbe_init_module(void)
9859{
9860 int ret;
c7689578 9861 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9862 pr_info("%s\n", ixgbe_copyright);
9a799d71 9863
780484d8
MR		 9864 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9865 if (!ixgbe_wq) {
9866 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9867 return -ENOMEM;
9868 }
9869
00949167 9870 ixgbe_dbg_init();
00949167 9871
f01fc1a8
JK		 9872 ret = pci_register_driver(&ixgbe_driver);
9873 if (ret) {
f01fc1a8 9874 ixgbe_dbg_exit();
f01fc1a8
JK		 9875 return ret;
9876 }
9877
5dd2d332 9878#ifdef CONFIG_IXGBE_DCA
bd0362dd 9879 dca_register_notify(&dca_notifier);
bd0362dd 9880#endif
5dd2d332 9881
f01fc1a8 9882 return 0;
9a799d71 9883}
b4617240 9884
9a799d71
AK		 9885module_init(ixgbe_init_module);
9886
9887/**
9888 * ixgbe_exit_module - Driver Exit Cleanup Routine
9889 *
9890 * ixgbe_exit_module is called just before the driver is removed
9891 * from memory.
9892 **/
9893static void __exit ixgbe_exit_module(void)
9894{
5dd2d332 9895#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9896 dca_unregister_notify(&dca_notifier);
9897#endif
9a799d71 9898 pci_unregister_driver(&ixgbe_driver);
00949167 9899
00949167 9900 ixgbe_dbg_exit();
780484d8
MR		 9901 if (ixgbe_wq) {
9902 destroy_workqueue(ixgbe_wq);
9903 ixgbe_wq = NULL;
9904 }
9a799d71 9905}
bd0362dd 9906
5dd2d332 9907#ifdef CONFIG_IXGBE_DCA
bd0362dd 9908static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9909 void *p)
bd0362dd
JC		 9910{
9911 int ret_val;
9912
9913 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9914 __ixgbe_notify_dca);
bd0362dd
JC		 9915
9916 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9917}
b453368d 9918
5dd2d332 9919#endif /* CONFIG_IXGBE_DCA */
849c4542 9920
9a799d71
AK		 9921module_exit(ixgbe_exit_module);
9922
9923/* ixgbe_main.c */
Linux kernel - Deliverables
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