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v2 ixgbe: consolidate all MSI-X ring interrupts and poll routines into one
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 58#define MAJ 3
a38a104d 59#define MIN 4
c89c7112 60#define BUILD 8
75e3d3c6 61#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 62 __stringify(BUILD) "-k"
9c8eb720 63const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 64static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 66
67static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 68 [board_82598] = &ixgbe_82598_info,
e8e26350 69 [board_82599] = &ixgbe_82599_info,
fe15e8e1 70 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 71};
72
73/* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
a3aa1884 81static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
83 board_82598 },
9a799d71 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 85 board_82598 },
9a799d71 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 87 board_82598 },
0befdb3e
JB		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
89 board_82598 },
3845bec0
PWJ		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
91 board_82598 },
9a799d71 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 93 board_82598 },
8d792cd9
JB		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
95 board_82598 },
c4900be0
DS		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
97 board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
99 board_82598 },
b95f5fcb
JB		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
101 board_82598 },
c4900be0
DS		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
103 board_82598 },
2f21bdd3
DS		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
105 board_82598 },
e8e26350
PW		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
107 board_82599 },
1fcf03e6
PWJ		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
109 board_82599 },
74757d49
DS		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
111 board_82599 },
e8e26350
PW		 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
113 board_82599 },
38ad1c8e
DS		 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
115 board_82599 },
dbfec662
DS		 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
117 board_82599 },
8911184f
PWJ		 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
119 board_82599 },
dbffcb21
DS		 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
121 board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
123 board_82599 },
119fc60a
MC		 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
125 board_82599 },
312eb931
DS		 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
127 board_82599 },
b93a2226 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 129 board_X540 },
4c40ef02
ET		 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
131 board_82599 },
4f6290cf
DS		 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
133 board_82599 },
9a799d71
AK		 134
135 /* required last entry */
136 {0, }
137};
138MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
139
5dd2d332 140#ifdef CONFIG_IXGBE_DCA
bd0362dd 141static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 142 void *p);
bd0362dd
JC		 143static struct notifier_block dca_notifier = {
144 .notifier_call = ixgbe_notify_dca,
145 .next = NULL,
146 .priority = 0
147};
148#endif
149
1cdd1ec8
GR		 150#ifdef CONFIG_PCI_IOV
151static unsigned int max_vfs;
152module_param(max_vfs, uint, 0);
e8e9f696
JP		 153MODULE_PARM_DESC(max_vfs,
154 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 155#endif /* CONFIG_PCI_IOV */
156
9a799d71
AK		 157MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
158MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_VERSION);
161
162#define DEFAULT_DEBUG_LEVEL_SHIFT 3
163
1cdd1ec8
GR		 164static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
165{
166 struct ixgbe_hw *hw = &adapter->hw;
167 u32 gcr;
168 u32 gpie;
169 u32 vmdctl;
170
171#ifdef CONFIG_PCI_IOV
172 /* disable iov and allow time for transactions to clear */
173 pci_disable_sriov(adapter->pdev);
174#endif
175
176 /* turn off device IOV mode */
177 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
178 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
179 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
180 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
181 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
182 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
183
184 /* set default pool back to 0 */
185 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
186 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
187 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
945a5151 188 IXGBE_WRITE_FLUSH(hw);
1cdd1ec8
GR		 189
190 /* take a breather then clean up driver data */
191 msleep(100);
e8e9f696
JP		 192
193 kfree(adapter->vfinfo);
1cdd1ec8
GR		 194 adapter->vfinfo = NULL;
195
196 adapter->num_vfs = 0;
197 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
198}
199
7086400d
AD		 200static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
201{
202 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
203 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
204 schedule_work(&adapter->service_task);
205}
206
207static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
208{
209 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
210
211 /* flush memory to make sure state is correct before next watchog */
212 smp_mb__before_clear_bit();
213 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
214}
215
dcd79aeb
TI		 216struct ixgbe_reg_info {
217 u32 ofs;
218 char *name;
219};
220
221static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
222
223 /* General Registers */
224 {IXGBE_CTRL, "CTRL"},
225 {IXGBE_STATUS, "STATUS"},
226 {IXGBE_CTRL_EXT, "CTRL_EXT"},
227
228 /* Interrupt Registers */
229 {IXGBE_EICR, "EICR"},
230
231 /* RX Registers */
232 {IXGBE_SRRCTL(0), "SRRCTL"},
233 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
234 {IXGBE_RDLEN(0), "RDLEN"},
235 {IXGBE_RDH(0), "RDH"},
236 {IXGBE_RDT(0), "RDT"},
237 {IXGBE_RXDCTL(0), "RXDCTL"},
238 {IXGBE_RDBAL(0), "RDBAL"},
239 {IXGBE_RDBAH(0), "RDBAH"},
240
241 /* TX Registers */
242 {IXGBE_TDBAL(0), "TDBAL"},
243 {IXGBE_TDBAH(0), "TDBAH"},
244 {IXGBE_TDLEN(0), "TDLEN"},
245 {IXGBE_TDH(0), "TDH"},
246 {IXGBE_TDT(0), "TDT"},
247 {IXGBE_TXDCTL(0), "TXDCTL"},
248
249 /* List Terminator */
250 {}
251};
252
253
254/*
255 * ixgbe_regdump - register printout routine
256 */
257static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
258{
259 int i = 0, j = 0;
260 char rname[16];
261 u32 regs[64];
262
263 switch (reginfo->ofs) {
264 case IXGBE_SRRCTL(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
267 break;
268 case IXGBE_DCA_RXCTRL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
271 break;
272 case IXGBE_RDLEN(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
275 break;
276 case IXGBE_RDH(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
279 break;
280 case IXGBE_RDT(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
283 break;
284 case IXGBE_RXDCTL(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
287 break;
288 case IXGBE_RDBAL(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
291 break;
292 case IXGBE_RDBAH(0):
293 for (i = 0; i < 64; i++)
294 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
295 break;
296 case IXGBE_TDBAL(0):
297 for (i = 0; i < 64; i++)
298 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
299 break;
300 case IXGBE_TDBAH(0):
301 for (i = 0; i < 64; i++)
302 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
303 break;
304 case IXGBE_TDLEN(0):
305 for (i = 0; i < 64; i++)
306 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
307 break;
308 case IXGBE_TDH(0):
309 for (i = 0; i < 64; i++)
310 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
311 break;
312 case IXGBE_TDT(0):
313 for (i = 0; i < 64; i++)
314 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
315 break;
316 case IXGBE_TXDCTL(0):
317 for (i = 0; i < 64; i++)
318 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
319 break;
320 default:
c7689578 321 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 322 IXGBE_READ_REG(hw, reginfo->ofs));
323 return;
324 }
325
326 for (i = 0; i < 8; i++) {
327 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 328 pr_err("%-15s", rname);
dcd79aeb 329 for (j = 0; j < 8; j++)
c7689578
JP		 330 pr_cont(" %08x", regs[i*8+j]);
331 pr_cont("\n");
dcd79aeb
TI		 332 }
333
334}
335
336/*
337 * ixgbe_dump - Print registers, tx-rings and rx-rings
338 */
339static void ixgbe_dump(struct ixgbe_adapter *adapter)
340{
341 struct net_device *netdev = adapter->netdev;
342 struct ixgbe_hw *hw = &adapter->hw;
343 struct ixgbe_reg_info *reginfo;
344 int n = 0;
345 struct ixgbe_ring *tx_ring;
346 struct ixgbe_tx_buffer *tx_buffer_info;
347 union ixgbe_adv_tx_desc *tx_desc;
348 struct my_u0 { u64 a; u64 b; } *u0;
349 struct ixgbe_ring *rx_ring;
350 union ixgbe_adv_rx_desc *rx_desc;
351 struct ixgbe_rx_buffer *rx_buffer_info;
352 u32 staterr;
353 int i = 0;
354
355 if (!netif_msg_hw(adapter))
356 return;
357
358 /* Print netdevice Info */
359 if (netdev) {
360 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 361 pr_info("Device Name state "
dcd79aeb 362 "trans_start last_rx\n");
c7689578
JP		 363 pr_info("%-15s %016lX %016lX %016lX\n",
364 netdev->name,
365 netdev->state,
366 netdev->trans_start,
367 netdev->last_rx);
dcd79aeb
TI		 368 }
369
370 /* Print Registers */
371 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 372 pr_info(" Register Name Value\n");
dcd79aeb
TI		 373 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
374 reginfo->name; reginfo++) {
375 ixgbe_regdump(hw, reginfo);
376 }
377
378 /* Print TX Ring Summary */
379 if (!netdev || !netif_running(netdev))
380 goto exit;
381
382 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 383 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 tx_buffer_info =
387 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 388 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 389 n, tx_ring->next_to_use, tx_ring->next_to_clean,
390 (u64)tx_buffer_info->dma,
391 tx_buffer_info->length,
392 tx_buffer_info->next_to_watch,
393 (u64)tx_buffer_info->time_stamp);
394 }
395
396 /* Print TX Rings */
397 if (!netif_msg_tx_done(adapter))
398 goto rx_ring_summary;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
401
402 /* Transmit Descriptor Formats
403 *
404 * Advanced Transmit Descriptor
405 * +--------------------------------------------------------------+
406 * 0 | Buffer Address [63:0] |
407 * +--------------------------------------------------------------+
408 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
409 * +--------------------------------------------------------------+
410 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
411 */
412
413 for (n = 0; n < adapter->num_tx_queues; n++) {
414 tx_ring = adapter->tx_ring[n];
c7689578
JP		 415 pr_info("------------------------------------\n");
416 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
417 pr_info("------------------------------------\n");
418 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 419 "[PlPOIdStDDt Ln] [bi->dma ] "
420 "leng ntw timestamp bi->skb\n");
421
422 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 423 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 424 tx_buffer_info = &tx_ring->tx_buffer_info[i];
425 u0 = (struct my_u0 *)tx_desc;
c7689578 426 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 427 " %04X %p %016llX %p", i,
dcd79aeb
TI		 428 le64_to_cpu(u0->a),
429 le64_to_cpu(u0->b),
430 (u64)tx_buffer_info->dma,
431 tx_buffer_info->length,
432 tx_buffer_info->next_to_watch,
433 (u64)tx_buffer_info->time_stamp,
434 tx_buffer_info->skb);
435 if (i == tx_ring->next_to_use &&
436 i == tx_ring->next_to_clean)
c7689578 437 pr_cont(" NTC/U\n");
dcd79aeb 438 else if (i == tx_ring->next_to_use)
c7689578 439 pr_cont(" NTU\n");
dcd79aeb 440 else if (i == tx_ring->next_to_clean)
c7689578 441 pr_cont(" NTC\n");
dcd79aeb 442 else
c7689578 443 pr_cont("\n");
dcd79aeb
TI		 444
445 if (netif_msg_pktdata(adapter) &&
446 tx_buffer_info->dma != 0)
447 print_hex_dump(KERN_INFO, "",
448 DUMP_PREFIX_ADDRESS, 16, 1,
449 phys_to_virt(tx_buffer_info->dma),
450 tx_buffer_info->length, true);
451 }
452 }
453
454 /* Print RX Rings Summary */
455rx_ring_summary:
456 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 457 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 458 for (n = 0; n < adapter->num_rx_queues; n++) {
459 rx_ring = adapter->rx_ring[n];
c7689578
JP		 460 pr_info("%5d %5X %5X\n",
461 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 462 }
463
464 /* Print RX Rings */
465 if (!netif_msg_rx_status(adapter))
466 goto exit;
467
468 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
469
470 /* Advanced Receive Descriptor (Read) Format
471 * 63 1 0
472 * +-----------------------------------------------------+
473 * 0 | Packet Buffer Address [63:1] |A0/NSE|
474 * +----------------------------------------------+------+
475 * 8 | Header Buffer Address [63:1] | DD |
476 * +-----------------------------------------------------+
477 *
478 *
479 * Advanced Receive Descriptor (Write-Back) Format
480 *
481 * 63 48 47 32 31 30 21 20 16 15 4 3 0
482 * +------------------------------------------------------+
483 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
484 * | Checksum Ident | | | | Type | Type |
485 * +------------------------------------------------------+
486 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
487 * +------------------------------------------------------+
488 * 63 48 47 32 31 20 19 0
489 */
490 for (n = 0; n < adapter->num_rx_queues; n++) {
491 rx_ring = adapter->rx_ring[n];
c7689578
JP		 492 pr_info("------------------------------------\n");
493 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
494 pr_info("------------------------------------\n");
495 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 496 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
497 "<-- Adv Rx Read format\n");
c7689578 498 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 499 "[vl er S cks ln] ---------------- [bi->skb] "
500 "<-- Adv Rx Write-Back format\n");
501
502 for (i = 0; i < rx_ring->count; i++) {
503 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 504 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 505 u0 = (struct my_u0 *)rx_desc;
506 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
507 if (staterr & IXGBE_RXD_STAT_DD) {
508 /* Descriptor Done */
c7689578 509 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 510 "%016llX ---------------- %p", i,
511 le64_to_cpu(u0->a),
512 le64_to_cpu(u0->b),
513 rx_buffer_info->skb);
514 } else {
c7689578 515 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 516 "%016llX %016llX %p", i,
517 le64_to_cpu(u0->a),
518 le64_to_cpu(u0->b),
519 (u64)rx_buffer_info->dma,
520 rx_buffer_info->skb);
521
522 if (netif_msg_pktdata(adapter)) {
523 print_hex_dump(KERN_INFO, "",
524 DUMP_PREFIX_ADDRESS, 16, 1,
525 phys_to_virt(rx_buffer_info->dma),
526 rx_ring->rx_buf_len, true);
527
528 if (rx_ring->rx_buf_len
529 < IXGBE_RXBUFFER_2048)
530 print_hex_dump(KERN_INFO, "",
531 DUMP_PREFIX_ADDRESS, 16, 1,
532 phys_to_virt(
533 rx_buffer_info->page_dma +
534 rx_buffer_info->page_offset
535 ),
536 PAGE_SIZE/2, true);
537 }
538 }
539
540 if (i == rx_ring->next_to_use)
c7689578 541 pr_cont(" NTU\n");
dcd79aeb 542 else if (i == rx_ring->next_to_clean)
c7689578 543 pr_cont(" NTC\n");
dcd79aeb 544 else
c7689578 545 pr_cont("\n");
dcd79aeb
TI		 546
547 }
548 }
549
550exit:
551 return;
552}
553
5eba3699
AV		 554static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
555{
556 u32 ctrl_ext;
557
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 562}
563
564static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
565{
566 u32 ctrl_ext;
567
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 572}
9a799d71 573
e8e26350
PW		 574/*
575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
580 *
581 */
582static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 583 u8 queue, u8 msix_vector)
9a799d71
AK		 584{
585 u32 ivar, index;
e8e26350
PW		 586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
590 if (direction == -1)
591 direction = 0;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
597 break;
598 case ixgbe_mac_82599EB:
b93a2226 599 case ixgbe_mac_X540:
e8e26350
PW		 600 if (direction == -1) {
601 /* other causes */
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
608 break;
609 } else {
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
617 break;
618 }
619 default:
620 break;
621 }
9a799d71
AK		 622}
623
fe49f04a 624static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 625 u64 qmask)
fe49f04a
AD		 626{
627 u32 mask;
628
bd508178
AD		 629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
fe49f04a
AD		 631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 633 break;
634 case ixgbe_mac_82599EB:
b93a2226 635 case ixgbe_mac_X540:
fe49f04a
AD		 636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 640 break;
641 default:
642 break;
fe49f04a
AD		 643 }
644}
645
d3d00239
AD		 646static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
647 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 648{
d3d00239
AD		 649 if (tx_buffer->dma) {
650 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
651 dma_unmap_page(ring->dev,
652 tx_buffer->dma,
653 tx_buffer->length,
654 DMA_TO_DEVICE);
e5a43549 655 else
d3d00239
AD		 656 dma_unmap_single(ring->dev,
657 tx_buffer->dma,
658 tx_buffer->length,
659 DMA_TO_DEVICE);
e5a43549 660 }
d3d00239
AD		 661 tx_buffer->dma = 0;
662}
663
664void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
665 struct ixgbe_tx_buffer *tx_buffer_info)
666{
667 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
668 if (tx_buffer_info->skb)
9a799d71 669 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 670 tx_buffer_info->skb = NULL;
9a799d71
AK		 671 /* tx_buffer_info must be completely set up in the transmit path */
672}
673
c84d324c
JF		 674static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
675{
676 struct ixgbe_hw *hw = &adapter->hw;
677 struct ixgbe_hw_stats *hwstats = &adapter->stats;
678 u32 data = 0;
679 u32 xoff[8] = {0};
680 int i;
681
682 if ((hw->fc.current_mode == ixgbe_fc_full) ||
683 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
684 switch (hw->mac.type) {
685 case ixgbe_mac_82598EB:
686 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 687 break;
688 default:
c84d324c
JF		 689 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
690 }
691 hwstats->lxoffrxc += data;
692
693 /* refill credits (no tx hang) if we received xoff */
694 if (!data)
695 return;
696
697 for (i = 0; i < adapter->num_tx_queues; i++)
698 clear_bit(__IXGBE_HANG_CHECK_ARMED,
699 &adapter->tx_ring[i]->state);
700 return;
701 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
702 return;
703
704 /* update stats for each tc, only valid with PFC enabled */
705 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
706 switch (hw->mac.type) {
707 case ixgbe_mac_82598EB:
708 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 709 break;
c84d324c
JF		 710 default:
711 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 712 }
c84d324c
JF		 713 hwstats->pxoffrxc[i] += xoff[i];
714 }
715
716 /* disarm tx queues that have received xoff frames */
717 for (i = 0; i < adapter->num_tx_queues; i++) {
718 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 719 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 720
721 if (xoff[tc])
722 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 723 }
26f23d82
YZ		 724}
725
c84d324c 726static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 727{
c84d324c
JF		 728 return ring->tx_stats.completed;
729}
730
731static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
732{
733 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 734 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 735
c84d324c
JF		 736 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
737 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
738
739 if (head != tail)
740 return (head < tail) ?
741 tail - head : (tail + ring->count - head);
742
743 return 0;
744}
745
746static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
747{
748 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
749 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
750 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
751 bool ret = false;
752
7d637bcc 753 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 754
755 /*
756 * Check for a hung queue, but be thorough. This verifies
757 * that a transmit has been completed since the previous
758 * check AND there is at least one packet pending. The
759 * ARMED bit is set to indicate a potential hang. The
760 * bit is cleared if a pause frame is received to remove
761 * false hang detection due to PFC or 802.3x frames. By
762 * requiring this to fail twice we avoid races with
763 * pfc clearing the ARMED bit and conditions where we
764 * run the check_tx_hang logic with a transmit completion
765 * pending but without time to complete it yet.
766 */
767 if ((tx_done_old == tx_done) && tx_pending) {
768 /* make sure it is true for two checks in a row */
769 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
770 &tx_ring->state);
771 } else {
772 /* update completed stats and continue */
773 tx_ring->tx_stats.tx_done_old = tx_done;
774 /* reset the countdown */
775 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 776 }
777
c84d324c 778 return ret;
9a799d71
AK		 779}
780
c83c6cbd
AD		 781/**
782 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
783 * @adapter: driver private struct
784 **/
785static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
786{
787
788 /* Do the reset outside of interrupt context */
789 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
790 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
791 ixgbe_service_event_schedule(adapter);
792 }
793}
e01c31a5 794
9a799d71
AK		 795/**
796 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 797 * @q_vector: structure containing interrupt and ring information
e01c31a5 798 * @tx_ring: tx ring to clean
9a799d71 799 **/
fe49f04a 800static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 801 struct ixgbe_ring *tx_ring)
9a799d71 802{
fe49f04a 803 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 804 struct ixgbe_tx_buffer *tx_buffer;
805 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 806 unsigned int total_bytes = 0, total_packets = 0;
59224555 807 unsigned int budget = q_vector->tx.work_limit;
d3d00239 808 u16 i = tx_ring->next_to_clean;
9a799d71 809
d3d00239
AD		 810 tx_buffer = &tx_ring->tx_buffer_info[i];
811 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 812
30065e63 813 for (; budget; budget--) {
d3d00239
AD		 814 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
815
816 /* if next_to_watch is not set then there is no work pending */
817 if (!eop_desc)
818 break;
819
820 /* if DD is not set pending work has not been completed */
821 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
822 break;
8ad494b0 823
d3d00239
AD		 824 /* count the packet as being completed */
825 tx_ring->tx_stats.completed++;
826
827 /* clear next_to_watch to prevent false hangs */
828 tx_buffer->next_to_watch = NULL;
8ad494b0 829
d3d00239
AD		 830 /* prevent any other reads prior to eop_desc being verified */
831 rmb();
832
833 do {
834 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 835 tx_desc->wb.status = 0;
d3d00239
AD		 836 if (likely(tx_desc == eop_desc)) {
837 eop_desc = NULL;
838 dev_kfree_skb_any(tx_buffer->skb);
839 tx_buffer->skb = NULL;
840
841 total_bytes += tx_buffer->bytecount;
842 total_packets += tx_buffer->gso_segs;
843 }
9a799d71 844
d3d00239
AD		 845 tx_buffer++;
846 tx_desc++;
8ad494b0 847 i++;
d3d00239 848 if (unlikely(i == tx_ring->count)) {
8ad494b0 849 i = 0;
e01c31a5 850
d3d00239
AD		 851 tx_buffer = tx_ring->tx_buffer_info;
852 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 853 }
e01c31a5 854
d3d00239 855 } while (eop_desc);
12207e49
PWJ		 856 }
857
9a799d71 858 tx_ring->next_to_clean = i;
d3d00239 859 u64_stats_update_begin(&tx_ring->syncp);
b953799e 860 tx_ring->stats.bytes += total_bytes;
bd198058 861 tx_ring->stats.packets += total_packets;
d3d00239 862 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 863 q_vector->tx.total_bytes += total_bytes;
864 q_vector->tx.total_packets += total_packets;
b953799e 865
c84d324c
JF		 866 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
867 /* schedule immediate reset if we believe we hung */
868 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 869 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 870 e_err(drv, "Detected Tx Unit Hang\n"
871 " Tx Queue <%d>\n"
872 " TDH, TDT <%x>, <%x>\n"
873 " next_to_use <%x>\n"
874 " next_to_clean <%x>\n"
875 "tx_buffer_info[next_to_clean]\n"
876 " time_stamp <%lx>\n"
877 " jiffies <%lx>\n",
878 tx_ring->queue_index,
879 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
880 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 881 tx_ring->next_to_use, i,
882 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 883
884 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
885
886 e_info(probe,
887 "tx hang %d detected on queue %d, resetting adapter\n",
888 adapter->tx_timeout_count + 1, tx_ring->queue_index);
889
b953799e 890 /* schedule immediate reset if we believe we hung */
c83c6cbd 891 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 892
893 /* the adapter is about to reset, no point in enabling stuff */
59224555 894 return true;
b953799e 895 }
9a799d71 896
e092be60 897#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 898 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 899 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 900 /* Make sure that anybody stopping the queue after this
901 * sees the new next_to_clean.
902 */
903 smp_mb();
fc77dc3c 904 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 905 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 906 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 907 ++tx_ring->tx_stats.restart_queue;
30eba97a 908 }
e092be60 909 }
9a799d71 910
59224555 911 return !!budget;
9a799d71
AK		 912}
913
5dd2d332 914#ifdef CONFIG_IXGBE_DCA
bd0362dd 915static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 916 struct ixgbe_ring *rx_ring,
917 int cpu)
bd0362dd 918{
33cf09c9 919 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 920 u32 rxctrl;
33cf09c9
AD		 921 u8 reg_idx = rx_ring->reg_idx;
922
923 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
924 switch (hw->mac.type) {
925 case ixgbe_mac_82598EB:
926 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
927 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
928 break;
929 case ixgbe_mac_82599EB:
b93a2226 930 case ixgbe_mac_X540:
33cf09c9
AD		 931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
932 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
933 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
934 break;
935 default:
936 break;
bd0362dd 937 }
33cf09c9
AD		 938 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
939 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
940 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 941 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 942}
943
944static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 945 struct ixgbe_ring *tx_ring,
946 int cpu)
bd0362dd 947{
33cf09c9 948 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 949 u32 txctrl;
33cf09c9
AD		 950 u8 reg_idx = tx_ring->reg_idx;
951
952 switch (hw->mac.type) {
953 case ixgbe_mac_82598EB:
954 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
955 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
956 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
957 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 958 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
959 break;
960 case ixgbe_mac_82599EB:
b93a2226 961 case ixgbe_mac_X540:
33cf09c9
AD		 962 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
963 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
964 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
965 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
966 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 967 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
968 break;
969 default:
970 break;
971 }
972}
973
974static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
975{
976 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 977 struct ixgbe_ring *ring;
bd0362dd 978 int cpu = get_cpu();
bd0362dd 979
33cf09c9
AD		 980 if (q_vector->cpu == cpu)
981 goto out_no_update;
982
efe3d3c8
AD		 983 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
984 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 985
efe3d3c8
AD		 986 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
987 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 988
989 q_vector->cpu = cpu;
990out_no_update:
bd0362dd
JC		 991 put_cpu();
992}
993
994static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
995{
33cf09c9 996 int num_q_vectors;
bd0362dd
JC		 997 int i;
998
999 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000 return;
1001
e35ec126
AD		 1002 /* always use CB2 mode, difference is masked in the CB driver */
1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
33cf09c9
AD		 1005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1006 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1007 else
1008 num_q_vectors = 1;
1009
1010 for (i = 0; i < num_q_vectors; i++) {
1011 adapter->q_vector[i]->cpu = -1;
1012 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1013 }
1014}
1015
1016static int __ixgbe_notify_dca(struct device *dev, void *data)
1017{
c60fbb00 1018 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1019 unsigned long event = *(unsigned long *)data;
1020
2a72c31e 1021 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1022 return 0;
1023
bd0362dd
JC		 1024 switch (event) {
1025 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1026 /* if we're already enabled, don't do it again */
1027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1028 break;
652f093f 1029 if (dca_add_requester(dev) == 0) {
96b0e0f6 1030 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1031 ixgbe_setup_dca(adapter);
1032 break;
1033 }
1034 /* Fall Through since DCA is disabled. */
1035 case DCA_PROVIDER_REMOVE:
1036 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1037 dca_remove_requester(dev);
1038 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1039 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1040 }
1041 break;
1042 }
1043
652f093f 1044 return 0;
bd0362dd 1045}
5dd2d332 1046#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1047
1048static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1049 struct sk_buff *skb)
1050{
1051 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1052}
1053
ff886dfc
AD		 1054/**
1055 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1056 * @adapter: address of board private structure
1057 * @rx_desc: advanced rx descriptor
1058 *
1059 * Returns : true if it is FCoE pkt
1060 */
1061static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1062 union ixgbe_adv_rx_desc *rx_desc)
1063{
1064 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1065
1066 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1067 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1068 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1069 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1070}
1071
9a799d71
AK		 1072/**
1073 * ixgbe_receive_skb - Send a completed packet up the stack
1074 * @adapter: board private structure
1075 * @skb: packet to send up
177db6ff
MC		 1076 * @status: hardware indication of status of receive
1077 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1078 * @rx_desc: rx descriptor
9a799d71 1079 **/
78b6f4ce 1080static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1081 struct sk_buff *skb, u8 status,
1082 struct ixgbe_ring *ring,
1083 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1084{
78b6f4ce
HX		 1085 struct ixgbe_adapter *adapter = q_vector->adapter;
1086 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1087 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1088 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1089
f62bbb5e
JG		 1090 if (is_vlan && (tag & VLAN_VID_MASK))
1091 __vlan_hwaccel_put_tag(skb, tag);
1092
1093 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1094 napi_gro_receive(napi, skb);
1095 else
1096 netif_rx(skb);
9a799d71
AK		 1097}
1098
e59bd25d
AV		 1099/**
1100 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1101 * @adapter: address of board private structure
1102 * @status_err: hardware indication of status of receive
1103 * @skb: skb currently being received and modified
ff886dfc 1104 * @status_err: status error value of last descriptor in packet
e59bd25d 1105 **/
9a799d71 1106static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1107 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1108 struct sk_buff *skb,
1109 u32 status_err)
9a799d71 1110{
ff886dfc 1111 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1112
712744be
JB		 1113 /* Rx csum disabled */
1114 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1115 return;
e59bd25d
AV		 1116
1117 /* if IP and error */
1118 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1119 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1120 adapter->hw_csum_rx_error++;
1121 return;
1122 }
e59bd25d
AV		 1123
1124 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1125 return;
1126
1127 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1128 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1129
1130 /*
1131 * 82599 errata, UDP frames with a 0 checksum can be marked as
1132 * checksum errors.
1133 */
1134 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1135 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1136 return;
1137
e59bd25d
AV		 1138 adapter->hw_csum_rx_error++;
1139 return;
1140 }
1141
9a799d71 1142 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1143 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1144}
1145
84ea2591 1146static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1147{
1148 /*
1149 * Force memory writes to complete before letting h/w
1150 * know there are new descriptors to fetch. (Only
1151 * applicable for weak-ordered memory model archs,
1152 * such as IA-64).
1153 */
1154 wmb();
84ea2591 1155 writel(val, rx_ring->tail);
e8e26350
PW		 1156}
1157
9a799d71
AK		 1158/**
1159 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1160 * @rx_ring: ring to place buffers on
1161 * @cleaned_count: number of buffers to replace
9a799d71 1162 **/
fc77dc3c 1163void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1164{
9a799d71 1165 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1166 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1167 struct sk_buff *skb;
1168 u16 i = rx_ring->next_to_use;
9a799d71 1169
fc77dc3c
AD		 1170 /* do nothing if no valid netdev defined */
1171 if (!rx_ring->netdev)
1172 return;
1173
9a799d71 1174 while (cleaned_count--) {
31f05a2d 1175 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1176 bi = &rx_ring->rx_buffer_info[i];
1177 skb = bi->skb;
9a799d71 1178
d5f398ed 1179 if (!skb) {
fc77dc3c 1180 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1181 rx_ring->rx_buf_len);
9a799d71 1182 if (!skb) {
5b7da515 1183 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1184 goto no_buffers;
1185 }
d716a7d8
AD		 1186 /* initialize queue mapping */
1187 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1188 bi->skb = skb;
d716a7d8 1189 }
9a799d71 1190
d716a7d8 1191 if (!bi->dma) {
b6ec895e 1192 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1193 skb->data,
e8e9f696 1194 rx_ring->rx_buf_len,
1b507730 1195 DMA_FROM_DEVICE);
b6ec895e 1196 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1197 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1198 bi->dma = 0;
1199 goto no_buffers;
1200 }
9a799d71 1201 }
d5f398ed 1202
7d637bcc 1203 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1204 if (!bi->page) {
fc77dc3c 1205 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1206 if (!bi->page) {
5b7da515 1207 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1208 goto no_buffers;
1209 }
1210 }
1211
1212 if (!bi->page_dma) {
1213 /* use a half page if we're re-using */
1214 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1215 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1216 bi->page,
1217 bi->page_offset,
1218 PAGE_SIZE / 2,
1219 DMA_FROM_DEVICE);
b6ec895e 1220 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1221 bi->page_dma)) {
5b7da515 1222 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1223 bi->page_dma = 0;
1224 goto no_buffers;
1225 }
1226 }
1227
1228 /* Refresh the desc even if buffer_addrs didn't change
1229 * because each write-back erases this info. */
3a581073
JB		 1230 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1231 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1232 } else {
3a581073 1233 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1234 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1235 }
1236
1237 i++;
1238 if (i == rx_ring->count)
1239 i = 0;
9a799d71 1240 }
7c6e0a43 1241
9a799d71
AK		 1242no_buffers:
1243 if (rx_ring->next_to_use != i) {
1244 rx_ring->next_to_use = i;
84ea2591 1245 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1246 }
1247}
1248
c267fc16 1249static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1250{
c267fc16
AD		 1251 /* HW will not DMA in data larger than the given buffer, even if it
1252 * parses the (NFS, of course) header to be larger. In that case, it
1253 * fills the header buffer and spills the rest into the page.
1254 */
1255 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1256 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1257 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1258 if (hlen > IXGBE_RX_HDR_SIZE)
1259 hlen = IXGBE_RX_HDR_SIZE;
1260 return hlen;
7c6e0a43
JB		 1261}
1262
f8212f97
AD		 1263/**
1264 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1265 * @skb: pointer to the last skb in the rsc queue
1266 *
1267 * This function changes a queue full of hw rsc buffers into a completed
1268 * packet. It uses the ->prev pointers to find the first packet and then
1269 * turns it into the frag list owner.
1270 **/
aa80175a 1271static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1272{
1273 unsigned int frag_list_size = 0;
aa80175a 1274 unsigned int skb_cnt = 1;
f8212f97
AD		 1275
1276 while (skb->prev) {
1277 struct sk_buff *prev = skb->prev;
1278 frag_list_size += skb->len;
1279 skb->prev = NULL;
1280 skb = prev;
aa80175a 1281 skb_cnt++;
f8212f97
AD		 1282 }
1283
1284 skb_shinfo(skb)->frag_list = skb->next;
1285 skb->next = NULL;
1286 skb->len += frag_list_size;
1287 skb->data_len += frag_list_size;
1288 skb->truesize += frag_list_size;
aa80175a
AD		 1289 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1290
f8212f97
AD		 1291 return skb;
1292}
1293
aa80175a
AD		 1294static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1295{
1296 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1297 IXGBE_RXDADV_RSCCNT_MASK);
1298}
43634e82 1299
4ff7fb12 1300static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1301 struct ixgbe_ring *rx_ring,
4ff7fb12 1302 int budget)
9a799d71 1303{
78b6f4ce 1304 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1305 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1306 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1307 struct sk_buff *skb;
d2f4fbe2 1308 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1309 const int current_node = numa_node_id();
3d8fd385
YZ		 1310#ifdef IXGBE_FCOE
1311 int ddp_bytes = 0;
1312#endif /* IXGBE_FCOE */
c267fc16
AD		 1313 u32 staterr;
1314 u16 i;
1315 u16 cleaned_count = 0;
aa80175a 1316 bool pkt_is_rsc = false;
9a799d71
AK		 1317
1318 i = rx_ring->next_to_clean;
31f05a2d 1319 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1320 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1321
1322 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1323 u32 upper_len = 0;
9a799d71 1324
3c945e5b 1325 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1326
c267fc16
AD		 1327 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1328
9a799d71 1329 skb = rx_buffer_info->skb;
9a799d71 1330 rx_buffer_info->skb = NULL;
c267fc16 1331 prefetch(skb->data);
9a799d71 1332
c267fc16 1333 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1334 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1335
1336 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1337 if (rx_buffer_info->dma) {
c267fc16 1338 u16 hlen;
aa80175a 1339 if (pkt_is_rsc &&
c267fc16
AD		 1340 !(staterr & IXGBE_RXD_STAT_EOP) &&
1341 !skb->prev) {
43634e82
MC		 1342 /*
1343 * When HWRSC is enabled, delay unmapping
1344 * of the first packet. It carries the
1345 * header information, HW may still
1346 * access the header after the writeback.
1347 * Only unmap it when EOP is reached
1348 */
e8171aaa 1349 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1350 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1351 } else {
b6ec895e 1352 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1353 rx_buffer_info->dma,
1354 rx_ring->rx_buf_len,
1355 DMA_FROM_DEVICE);
e8171aaa 1356 }
4f57ca6e 1357 rx_buffer_info->dma = 0;
c267fc16
AD		 1358
1359 if (ring_is_ps_enabled(rx_ring)) {
1360 hlen = ixgbe_get_hlen(rx_desc);
1361 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1362 } else {
1363 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1364 }
1365
1366 skb_put(skb, hlen);
1367 } else {
1368 /* assume packet split since header is unmapped */
1369 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1370 }
1371
1372 if (upper_len) {
b6ec895e
AD		 1373 dma_unmap_page(rx_ring->dev,
1374 rx_buffer_info->page_dma,
1375 PAGE_SIZE / 2,
1376 DMA_FROM_DEVICE);
9a799d71
AK		 1377 rx_buffer_info->page_dma = 0;
1378 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1379 rx_buffer_info->page,
1380 rx_buffer_info->page_offset,
1381 upper_len);
762f4c57 1382
c267fc16
AD		 1383 if ((page_count(rx_buffer_info->page) == 1) &&
1384 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1385 get_page(rx_buffer_info->page);
c267fc16
AD		 1386 else
1387 rx_buffer_info->page = NULL;
9a799d71
AK		 1388
1389 skb->len += upper_len;
1390 skb->data_len += upper_len;
1391 skb->truesize += upper_len;
1392 }
1393
1394 i++;
1395 if (i == rx_ring->count)
1396 i = 0;
9a799d71 1397
31f05a2d 1398 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1399 prefetch(next_rxd);
9a799d71 1400 cleaned_count++;
f8212f97 1401
aa80175a 1402 if (pkt_is_rsc) {
f8212f97
AD		 1403 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1404 IXGBE_RXDADV_NEXTP_SHIFT;
1405 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1406 } else {
1407 next_buffer = &rx_ring->rx_buffer_info[i];
1408 }
1409
c267fc16 1410 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1411 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1412 rx_buffer_info->skb = next_buffer->skb;
1413 rx_buffer_info->dma = next_buffer->dma;
1414 next_buffer->skb = skb;
1415 next_buffer->dma = 0;
1416 } else {
1417 skb->next = next_buffer->skb;
1418 skb->next->prev = skb;
1419 }
5b7da515 1420 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1421 goto next_desc;
1422 }
1423
aa80175a
AD		 1424 if (skb->prev) {
1425 skb = ixgbe_transform_rsc_queue(skb);
1426 /* if we got here without RSC the packet is invalid */
1427 if (!pkt_is_rsc) {
1428 __pskb_trim(skb, 0);
1429 rx_buffer_info->skb = skb;
1430 goto next_desc;
1431 }
1432 }
c267fc16
AD		 1433
1434 if (ring_is_rsc_enabled(rx_ring)) {
1435 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1436 dma_unmap_single(rx_ring->dev,
1437 IXGBE_RSC_CB(skb)->dma,
1438 rx_ring->rx_buf_len,
1439 DMA_FROM_DEVICE);
1440 IXGBE_RSC_CB(skb)->dma = 0;
1441 IXGBE_RSC_CB(skb)->delay_unmap = false;
1442 }
aa80175a
AD		 1443 }
1444 if (pkt_is_rsc) {
c267fc16
AD		 1445 if (ring_is_ps_enabled(rx_ring))
1446 rx_ring->rx_stats.rsc_count +=
aa80175a 1447 skb_shinfo(skb)->nr_frags;
c267fc16 1448 else
aa80175a
AD		 1449 rx_ring->rx_stats.rsc_count +=
1450 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1451 rx_ring->rx_stats.rsc_flush++;
1452 }
1453
1454 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1455 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1456 dev_kfree_skb_any(skb);
9a799d71
AK		 1457 goto next_desc;
1458 }
1459
ff886dfc 1460 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1461 if (adapter->netdev->features & NETIF_F_RXHASH)
1462 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1463
1464 /* probably a little skewed due to removing CRC */
1465 total_rx_bytes += skb->len;
1466 total_rx_packets++;
1467
fc77dc3c 1468 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1469#ifdef IXGBE_FCOE
1470 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1471 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1472 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1473 staterr);
63d635b2
AD		 1474 if (!ddp_bytes) {
1475 dev_kfree_skb_any(skb);
332d4a7d 1476 goto next_desc;
63d635b2 1477 }
3d8fd385 1478 }
332d4a7d 1479#endif /* IXGBE_FCOE */
fdaff1ce 1480 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1481
4ff7fb12 1482 budget--;
9a799d71
AK		 1483next_desc:
1484 rx_desc->wb.upper.status_error = 0;
1485
4ff7fb12 1486 if (!budget)
c267fc16
AD		 1487 break;
1488
9a799d71
AK		 1489 /* return some buffers to hardware, one at a time is too slow */
1490 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1491 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1492 cleaned_count = 0;
1493 }
1494
1495 /* use prefetched values */
1496 rx_desc = next_rxd;
9a799d71 1497 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1498 }
1499
9a799d71 1500 rx_ring->next_to_clean = i;
7d4987de 1501 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1502
1503 if (cleaned_count)
fc77dc3c 1504 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1505
3d8fd385
YZ		 1506#ifdef IXGBE_FCOE
1507 /* include DDPed FCoE data */
1508 if (ddp_bytes > 0) {
1509 unsigned int mss;
1510
fc77dc3c 1511 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1512 sizeof(struct fc_frame_header) -
1513 sizeof(struct fcoe_crc_eof);
1514 if (mss > 512)
1515 mss &= ~511;
1516 total_rx_bytes += ddp_bytes;
1517 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1518 }
1519#endif /* IXGBE_FCOE */
1520
c267fc16
AD		 1521 u64_stats_update_begin(&rx_ring->syncp);
1522 rx_ring->stats.packets += total_rx_packets;
1523 rx_ring->stats.bytes += total_rx_bytes;
1524 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1525 q_vector->rx.total_packets += total_rx_packets;
1526 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1527
1528 return !!budget;
9a799d71
AK		 1529}
1530
9a799d71
AK		 1531/**
1532 * ixgbe_configure_msix - Configure MSI-X hardware
1533 * @adapter: board private structure
1534 *
1535 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1536 * interrupts.
1537 **/
1538static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1539{
021230d4 1540 struct ixgbe_q_vector *q_vector;
efe3d3c8 1541 int q_vectors, v_idx;
021230d4 1542 u32 mask;
9a799d71 1543
021230d4 1544 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1545
4df10466
JB		 1546 /*
1547 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1548 * corresponding register.
1549 */
1550 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1551 struct ixgbe_ring *ring;
7a921c93 1552 q_vector = adapter->q_vector[v_idx];
021230d4 1553
efe3d3c8
AD		 1554 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1555 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1556
1557 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1558 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1559
1560 if (q_vector->tx.ring && !q_vector->rx.ring)
f7554a2b
NS		 1561 /* tx only */
1562 q_vector->eitr = adapter->tx_eitr_param;
efe3d3c8 1563 else if (q_vector->rx.ring)
f7554a2b
NS		 1564 /* rx or mixed */
1565 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1566
fe49f04a 1567 ixgbe_write_eitr(q_vector);
03ecf91a
AD		 1568 /* If ATR is enabled, set interrupt affinity */
1569 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
b25ebfd2
PW		 1570 /*
1571 * Allocate the affinity_hint cpumask, assign the mask
1572 * for this vector, and set our affinity_hint for
1573 * this irq.
1574 */
1575 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1576 GFP_KERNEL))
1577 return;
1578 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1579 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1580 q_vector->affinity_mask);
1581 }
9a799d71
AK		 1582 }
1583
bd508178
AD		 1584 switch (adapter->hw.mac.type) {
1585 case ixgbe_mac_82598EB:
e8e26350 1586 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1587 v_idx);
bd508178
AD		 1588 break;
1589 case ixgbe_mac_82599EB:
b93a2226 1590 case ixgbe_mac_X540:
e8e26350 1591 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1592 break;
1593
1594 default:
1595 break;
1596 }
021230d4
AV		 1597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1598
41fb9248 1599 /* set up to autoclear timer, and the vectors */
021230d4 1600 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1601 if (adapter->num_vfs)
1602 mask &= ~(IXGBE_EIMS_OTHER |
1603 IXGBE_EIMS_MAILBOX |
1604 IXGBE_EIMS_LSC);
1605 else
1606 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1608}
1609
f494e8fa
AV		 1610enum latency_range {
1611 lowest_latency = 0,
1612 low_latency = 1,
1613 bulk_latency = 2,
1614 latency_invalid = 255
1615};
1616
1617/**
1618 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1619 * @q_vector: structure containing interrupt and ring information
1620 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1621 *
1622 * Stores a new ITR value based on packets and byte
1623 * counts during the last interrupt. The advantage of per interrupt
1624 * computation is faster updates and more accurate ITR for the current
1625 * traffic pattern. Constants in this function were computed
1626 * based on theoretical maximum wire speed and thresholds were set based
1627 * on testing data as well as attempting to minimize response time
1628 * while increasing bulk throughput.
1629 * this functionality is controlled by the InterruptThrottleRate module
1630 * parameter (see ixgbe_param.c)
1631 **/
bd198058
AD		 1632static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1633 struct ixgbe_ring_container *ring_container)
f494e8fa 1634{
f494e8fa 1635 u64 bytes_perint;
bd198058
AD		 1636 struct ixgbe_adapter *adapter = q_vector->adapter;
1637 int bytes = ring_container->total_bytes;
1638 int packets = ring_container->total_packets;
1639 u32 timepassed_us;
1640 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1641
1642 if (packets == 0)
bd198058 1643 return;
f494e8fa
AV		 1644
1645 /* simple throttlerate management
1646 * 0-20MB/s lowest (100000 ints/s)
1647 * 20-100MB/s low (20000 ints/s)
1648 * 100-1249MB/s bulk (8000 ints/s)
1649 */
1650 /* what was last interrupt timeslice? */
bd198058 1651 timepassed_us = 1000000/q_vector->eitr;
f494e8fa
AV		 1652 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1653
1654 switch (itr_setting) {
1655 case lowest_latency:
1656 if (bytes_perint > adapter->eitr_low)
bd198058 1657 itr_setting = low_latency;
f494e8fa
AV		 1658 break;
1659 case low_latency:
1660 if (bytes_perint > adapter->eitr_high)
bd198058 1661 itr_setting = bulk_latency;
f494e8fa 1662 else if (bytes_perint <= adapter->eitr_low)
bd198058 1663 itr_setting = lowest_latency;
f494e8fa
AV		 1664 break;
1665 case bulk_latency:
1666 if (bytes_perint <= adapter->eitr_high)
bd198058 1667 itr_setting = low_latency;
f494e8fa
AV		 1668 break;
1669 }
1670
bd198058
AD		 1671 /* clear work counters since we have the values we need */
1672 ring_container->total_bytes = 0;
1673 ring_container->total_packets = 0;
1674
1675 /* write updated itr to ring container */
1676 ring_container->itr = itr_setting;
f494e8fa
AV		 1677}
1678
509ee935
JB		 1679/**
1680 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1681 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1682 *
1683 * This function is made to be called by ethtool and by the driver
1684 * when it needs to update EITR registers at runtime. Hardware
1685 * specific quirks/differences are taken care of here.
1686 */
fe49f04a 1687void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1688{
fe49f04a 1689 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1690 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1691 int v_idx = q_vector->v_idx;
1692 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1693
bd508178
AD		 1694 switch (adapter->hw.mac.type) {
1695 case ixgbe_mac_82598EB:
509ee935
JB		 1696 /* must write high and low 16 bits to reset counter */
1697 itr_reg |= (itr_reg << 16);
bd508178
AD		 1698 break;
1699 case ixgbe_mac_82599EB:
b93a2226 1700 case ixgbe_mac_X540:
f8d1dcaf 1701 /*
b93a2226 1702 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1703 * max interrupt rate, but there is an errata where it can
1704 * not be zero with RSC
1705 */
1706 if (itr_reg == 8 &&
1707 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1708 itr_reg = 0;
1709
509ee935
JB		 1710 /*
1711 * set the WDIS bit to not clear the timer bits and cause an
1712 * immediate assertion of the interrupt
1713 */
1714 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1715 break;
1716 default:
1717 break;
509ee935
JB		 1718 }
1719 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1720}
1721
bd198058 1722static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1723{
bd198058
AD		 1724 u32 new_itr = q_vector->eitr;
1725 u8 current_itr;
f494e8fa 1726
bd198058
AD		 1727 ixgbe_update_itr(q_vector, &q_vector->tx);
1728 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1729
08c8833b 1730 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1731
1732 switch (current_itr) {
1733 /* counts and packets in update_itr are dependent on these numbers */
1734 case lowest_latency:
1735 new_itr = 100000;
1736 break;
1737 case low_latency:
1738 new_itr = 20000; /* aka hwitr = ~200 */
1739 break;
1740 case bulk_latency:
f494e8fa
AV		 1741 new_itr = 8000;
1742 break;
bd198058
AD		 1743 default:
1744 break;
f494e8fa
AV		 1745 }
1746
1747 if (new_itr != q_vector->eitr) {
fe49f04a 1748 /* do an exponential smoothing */
125601bf 1749 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 1750
bd198058 1751 /* save the algorithm value here */
509ee935 1752 q_vector->eitr = new_itr;
fe49f04a
AD		 1753
1754 ixgbe_write_eitr(q_vector);
f494e8fa 1755 }
f494e8fa
AV		 1756}
1757
119fc60a 1758/**
f0f9778d
AD		 1759 * ixgbe_check_overtemp_subtask - check for over tempurature
1760 * @adapter: pointer to adapter
119fc60a 1761 **/
f0f9778d 1762static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1763{
119fc60a
MC		 1764 struct ixgbe_hw *hw = &adapter->hw;
1765 u32 eicr = adapter->interrupt_event;
1766
f0f9778d 1767 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1768 return;
1769
f0f9778d
AD		 1770 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1771 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1772 return;
1773
1774 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1775
7ca647bd 1776 switch (hw->device_id) {
f0f9778d
AD		 1777 case IXGBE_DEV_ID_82599_T3_LOM:
1778 /*
1779 * Since the warning interrupt is for both ports
1780 * we don't have to check if:
1781 * - This interrupt wasn't for our port.
1782 * - We may have missed the interrupt so always have to
1783 * check if we got a LSC
1784 */
1785 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1786 !(eicr & IXGBE_EICR_LSC))
1787 return;
1788
1789 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1790 u32 autoneg;
1791 bool link_up = false;
7ca647bd 1792
7ca647bd
JP		 1793 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1794
f0f9778d
AD		 1795 if (link_up)
1796 return;
1797 }
1798
1799 /* Check if this is not due to overtemp */
1800 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1801 return;
1802
1803 break;
7ca647bd
JP		 1804 default:
1805 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1806 return;
7ca647bd 1807 break;
119fc60a 1808 }
7ca647bd
JP		 1809 e_crit(drv,
1810 "Network adapter has been stopped because it has over heated. "
1811 "Restart the computer. If the problem persists, "
1812 "power off the system and replace the adapter\n");
f0f9778d
AD		 1813
1814 adapter->interrupt_event = 0;
119fc60a
MC		 1815}
1816
0befdb3e
JB		 1817static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1818{
1819 struct ixgbe_hw *hw = &adapter->hw;
1820
1821 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1822 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1823 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1824 /* write to clear the interrupt */
1825 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1826 }
1827}
cf8280ee 1828
e8e26350
PW		 1829static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1830{
1831 struct ixgbe_hw *hw = &adapter->hw;
1832
73c4b7cd
AD		 1833 if (eicr & IXGBE_EICR_GPI_SDP2) {
1834 /* Clear the interrupt */
1835 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1836 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1837 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1838 ixgbe_service_event_schedule(adapter);
1839 }
73c4b7cd
AD		 1840 }
1841
e8e26350
PW		 1842 if (eicr & IXGBE_EICR_GPI_SDP1) {
1843 /* Clear the interrupt */
1844 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1845 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1846 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1847 ixgbe_service_event_schedule(adapter);
1848 }
e8e26350
PW		 1849 }
1850}
1851
cf8280ee
JB		 1852static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1853{
1854 struct ixgbe_hw *hw = &adapter->hw;
1855
1856 adapter->lsc_int++;
1857 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1858 adapter->link_check_timeout = jiffies;
1859 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1860 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1861 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1862 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1863 }
1864}
1865
9a799d71
AK		 1866static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1867{
a65151ba 1868 struct ixgbe_adapter *adapter = data;
9a799d71 1869 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1870 u32 eicr;
1871
1872 /*
1873 * Workaround for Silicon errata. Use clear-by-write instead
1874 * of clear-by-read. Reading with EICS will return the
1875 * interrupt causes without clearing, which later be done
1876 * with the write to EICR.
1877 */
1878 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1879 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1880
cf8280ee
JB		 1881 if (eicr & IXGBE_EICR_LSC)
1882 ixgbe_check_lsc(adapter);
d4f80882 1883
1cdd1ec8
GR		 1884 if (eicr & IXGBE_EICR_MAILBOX)
1885 ixgbe_msg_task(adapter);
1886
bd508178
AD		 1887 switch (hw->mac.type) {
1888 case ixgbe_mac_82599EB:
b93a2226 1889 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1890 /* Handle Flow Director Full threshold interrupt */
1891 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1892 int reinit_count = 0;
c4cf55e5 1893 int i;
c4cf55e5 1894 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1895 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1896 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1897 &ring->state))
1898 reinit_count++;
1899 }
1900 if (reinit_count) {
1901 /* no more flow director interrupts until after init */
1902 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1903 eicr &= ~IXGBE_EICR_FLOW_DIR;
1904 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1905 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1906 }
1907 }
f0f9778d
AD		 1908 ixgbe_check_sfp_event(adapter, eicr);
1909 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1910 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1911 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1912 adapter->interrupt_event = eicr;
1913 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1914 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1915 }
1916 }
bd508178
AD		 1917 break;
1918 default:
1919 break;
c4cf55e5 1920 }
bd508178
AD		 1921
1922 ixgbe_check_fan_failure(adapter, eicr);
1923
7086400d 1924 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1925 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 1926 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1927 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 1928
1929 return IRQ_HANDLED;
1930}
1931
fe49f04a
AD		 1932static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1933 u64 qmask)
1934{
1935 u32 mask;
bd508178 1936 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1937
bd508178
AD		 1938 switch (hw->mac.type) {
1939 case ixgbe_mac_82598EB:
fe49f04a 1940 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1941 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1942 break;
1943 case ixgbe_mac_82599EB:
b93a2226 1944 case ixgbe_mac_X540:
fe49f04a 1945 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1946 if (mask)
1947 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1948 mask = (qmask >> 32);
bd508178
AD		 1949 if (mask)
1950 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1951 break;
1952 default:
1953 break;
fe49f04a
AD		 1954 }
1955 /* skip the flush */
1956}
1957
1958static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1959 u64 qmask)
fe49f04a
AD		 1960{
1961 u32 mask;
bd508178 1962 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1963
bd508178
AD		 1964 switch (hw->mac.type) {
1965 case ixgbe_mac_82598EB:
fe49f04a 1966 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1967 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1968 break;
1969 case ixgbe_mac_82599EB:
b93a2226 1970 case ixgbe_mac_X540:
fe49f04a 1971 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1972 if (mask)
1973 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1974 mask = (qmask >> 32);
bd508178
AD		 1975 if (mask)
1976 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1977 break;
1978 default:
1979 break;
fe49f04a
AD		 1980 }
1981 /* skip the flush */
1982}
1983
4ff7fb12 1984static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
9a799d71 1985{
021230d4 1986 struct ixgbe_q_vector *q_vector = data;
30efa5a3 1987
9b471446 1988 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1989
4ff7fb12
AD		 1990 if (q_vector->rx.ring || q_vector->tx.ring)
1991 napi_schedule(&q_vector->napi);
9a799d71 1992
9a799d71
AK		 1993 return IRQ_HANDLED;
1994}
1995
021230d4 1996static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 1997 int r_idx)
021230d4 1998{
7a921c93 1999 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2000 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2001
2274543f 2002 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2003 rx_ring->next = q_vector->rx.ring;
2004 q_vector->rx.ring = rx_ring;
2005 q_vector->rx.count++;
021230d4
AV		 2006}
2007
2008static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2009 int t_idx)
021230d4 2010{
7a921c93 2011 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2012 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2013
2274543f 2014 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2015 tx_ring->next = q_vector->tx.ring;
2016 q_vector->tx.ring = tx_ring;
2017 q_vector->tx.count++;
bd198058 2018 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2019}
2020
9a799d71 2021/**
021230d4
AV		 2022 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2023 * @adapter: board private structure to initialize
9a799d71 2024 *
021230d4
AV		 2025 * This function maps descriptor rings to the queue-specific vectors
2026 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2027 * one vector per ring/queue, but on a constrained vector budget, we
2028 * group the rings as "efficiently" as possible. You would add new
2029 * mapping configurations in here.
9a799d71 2030 **/
d0759ebb 2031static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2032{
d0759ebb 2033 int q_vectors;
021230d4
AV		 2034 int v_start = 0;
2035 int rxr_idx = 0, txr_idx = 0;
2036 int rxr_remaining = adapter->num_rx_queues;
2037 int txr_remaining = adapter->num_tx_queues;
2038 int i, j;
2039 int rqpv, tqpv;
2040 int err = 0;
2041
2042 /* No mapping required if MSI-X is disabled. */
2043 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2044 goto out;
9a799d71 2045
d0759ebb
AD		 2046 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2047
021230d4
AV		 2048 /*
2049 * The ideal configuration...
2050 * We have enough vectors to map one per queue.
2051 */
d0759ebb 2052 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2053 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2054 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2055
021230d4
AV		 2056 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2057 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2058
9a799d71 2059 goto out;
021230d4 2060 }
9a799d71 2061
021230d4
AV		 2062 /*
2063 * If we don't have enough vectors for a 1-to-1
2064 * mapping, we'll have to group them so there are
2065 * multiple queues per vector.
2066 */
2067 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2068 for (i = v_start; i < q_vectors; i++) {
2069 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2070 for (j = 0; j < rqpv; j++) {
2071 map_vector_to_rxq(adapter, i, rxr_idx);
2072 rxr_idx++;
2073 rxr_remaining--;
2074 }
d0759ebb 2075 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2076 for (j = 0; j < tqpv; j++) {
2077 map_vector_to_txq(adapter, i, txr_idx);
2078 txr_idx++;
2079 txr_remaining--;
9a799d71 2080 }
9a799d71 2081 }
021230d4
AV		 2082out:
2083 return err;
2084}
2085
2086/**
2087 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2088 * @adapter: board private structure
2089 *
2090 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2091 * interrupts from the kernel.
2092 **/
2093static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2094{
2095 struct net_device *netdev = adapter->netdev;
021230d4 2096 int i, vector, q_vectors, err;
e8e9f696 2097 int ri = 0, ti = 0;
021230d4
AV		 2098
2099 /* Decrement for Other and TCP Timer vectors */
2100 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2101
d0759ebb 2102 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2103 if (err)
d0759ebb 2104 return err;
021230d4 2105
021230d4 2106 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2107 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
cb13fc20 2108
4ff7fb12 2109 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2110 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2111 "%s-%s-%d", netdev->name, "TxRx", ri++);
2112 ti++;
2113 } else if (q_vector->rx.ring) {
9fe93afd 2114 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2115 "%s-%s-%d", netdev->name, "rx", ri++);
2116 } else if (q_vector->tx.ring) {
9fe93afd 2117 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2118 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2119 } else {
2120 /* skip this unused q_vector */
2121 continue;
32aa77a4 2122 }
021230d4 2123 err = request_irq(adapter->msix_entries[vector].vector,
4ff7fb12 2124 &ixgbe_msix_clean_rings, 0, q_vector->name,
d0759ebb 2125 q_vector);
9a799d71 2126 if (err) {
396e799c 2127 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2128 "Error: %d\n", err);
021230d4 2129 goto free_queue_irqs;
9a799d71 2130 }
9a799d71
AK		 2131 }
2132
d0759ebb 2133 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2134 err = request_irq(adapter->msix_entries[vector].vector,
a65151ba 2135 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
9a799d71 2136 if (err) {
396e799c 2137 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2138 goto free_queue_irqs;
9a799d71
AK		 2139 }
2140
9a799d71
AK		 2141 return 0;
2142
021230d4
AV		 2143free_queue_irqs:
2144 for (i = vector - 1; i >= 0; i--)
2145 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2146 adapter->q_vector[i]);
021230d4
AV		 2147 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2148 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2149 kfree(adapter->msix_entries);
2150 adapter->msix_entries = NULL;
9a799d71
AK		 2151 return err;
2152}
2153
79aefa45
AD		 2154/**
2155 * ixgbe_irq_enable - Enable default interrupt generation settings
2156 * @adapter: board private structure
2157 **/
6af3b9eb
ET		 2158static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2159 bool flush)
79aefa45
AD		 2160{
2161 u32 mask;
835462fc
NS		 2162
2163 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2164 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2165 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2166 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2167 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2168 switch (adapter->hw.mac.type) {
2169 case ixgbe_mac_82599EB:
b93a2226 2170 case ixgbe_mac_X540:
2a41ff81 2171 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2172 mask |= IXGBE_EIMS_GPI_SDP1;
2173 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2174 if (adapter->num_vfs)
2175 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2176 break;
2177 default:
2178 break;
e8e26350 2179 }
03ecf91a 2180 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
c4cf55e5 2181 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2182
79aefa45 2183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2184 if (queues)
2185 ixgbe_irq_enable_queues(adapter, ~0);
2186 if (flush)
2187 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2188
2189 if (adapter->num_vfs > 32) {
2190 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2191 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2192 }
79aefa45 2193}
021230d4 2194
9a799d71 2195/**
021230d4 2196 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2197 * @irq: interrupt number
2198 * @data: pointer to a network interface device structure
9a799d71
AK		 2199 **/
2200static irqreturn_t ixgbe_intr(int irq, void *data)
2201{
a65151ba 2202 struct ixgbe_adapter *adapter = data;
9a799d71 2203 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2204 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2205 u32 eicr;
2206
54037505 2207 /*
6af3b9eb 2208 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2209 * before the read of EICR.
2210 */
2211 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2212
021230d4
AV		 2213 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2214 * therefore no explict interrupt disable is necessary */
2215 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2216 if (!eicr) {
6af3b9eb
ET		 2217 /*
2218 * shared interrupt alert!
f47cf66e 2219 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2220 * have disabled interrupts due to EIAM
2221 * finish the workaround of silicon errata on 82598. Unmask
2222 * the interrupt that we masked before the EICR read.
2223 */
2224 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2225 ixgbe_irq_enable(adapter, true, true);
9a799d71 2226 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2227 }
9a799d71 2228
cf8280ee
JB		 2229 if (eicr & IXGBE_EICR_LSC)
2230 ixgbe_check_lsc(adapter);
021230d4 2231
bd508178
AD		 2232 switch (hw->mac.type) {
2233 case ixgbe_mac_82599EB:
e8e26350 2234 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2235 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2236 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
f0f9778d
AD		 2237 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2238 adapter->interrupt_event = eicr;
2239 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2240 ixgbe_service_event_schedule(adapter);
2241 }
bd508178
AD		 2242 }
2243 break;
2244 default:
2245 break;
2246 }
e8e26350 2247
0befdb3e
JB		 2248 ixgbe_check_fan_failure(adapter, eicr);
2249
7a921c93 2250 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2251 /* would disable interrupts here but EIAM disabled it */
7a921c93 2252 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2253 }
2254
6af3b9eb
ET		 2255 /*
2256 * re-enable link(maybe) and non-queue interrupts, no flush.
2257 * ixgbe_poll will re-enable the queue interrupts
2258 */
2259
2260 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2261 ixgbe_irq_enable(adapter, false, false);
2262
9a799d71
AK		 2263 return IRQ_HANDLED;
2264}
2265
021230d4
AV		 2266static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2267{
efe3d3c8
AD		 2268 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2269 int i;
2270
2271 /* legacy and MSI only use one vector */
2272 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2273 q_vectors = 1;
2274
2275 for (i = 0; i < adapter->num_rx_queues; i++) {
2276 adapter->rx_ring[i]->q_vector = NULL;
2277 adapter->rx_ring[i]->next = NULL;
2278 }
2279 for (i = 0; i < adapter->num_tx_queues; i++) {
2280 adapter->tx_ring[i]->q_vector = NULL;
2281 adapter->tx_ring[i]->next = NULL;
2282 }
021230d4
AV		 2283
2284 for (i = 0; i < q_vectors; i++) {
7a921c93 2285 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2286 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2287 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2288 }
2289}
2290
9a799d71
AK		 2291/**
2292 * ixgbe_request_irq - initialize interrupts
2293 * @adapter: board private structure
2294 *
2295 * Attempts to configure interrupts using the best available
2296 * capabilities of the hardware and kernel.
2297 **/
021230d4 2298static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2299{
2300 struct net_device *netdev = adapter->netdev;
021230d4 2301 int err;
9a799d71 2302
021230d4
AV		 2303 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2304 err = ixgbe_request_msix_irqs(adapter);
2305 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2306 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2307 netdev->name, adapter);
021230d4 2308 } else {
a0607fd3 2309 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2310 netdev->name, adapter);
9a799d71
AK		 2311 }
2312
9a799d71 2313 if (err)
396e799c 2314 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2315
9a799d71
AK		 2316 return err;
2317}
2318
2319static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2320{
9a799d71 2321 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2322 int i, q_vectors;
9a799d71 2323
021230d4
AV		 2324 q_vectors = adapter->num_msix_vectors;
2325
2326 i = q_vectors - 1;
a65151ba 2327 free_irq(adapter->msix_entries[i].vector, adapter);
9a799d71 2328
021230d4
AV		 2329 i--;
2330 for (; i >= 0; i--) {
894ff7cf 2331 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2332 if (!adapter->q_vector[i]->rx.ring &&
2333 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2334 continue;
2335
021230d4 2336 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2337 adapter->q_vector[i]);
021230d4
AV		 2338 }
2339
2340 ixgbe_reset_q_vectors(adapter);
2341 } else {
a65151ba 2342 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2343 }
2344}
2345
22d5a71b
JB		 2346/**
2347 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2348 * @adapter: board private structure
2349 **/
2350static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2351{
bd508178
AD		 2352 switch (adapter->hw.mac.type) {
2353 case ixgbe_mac_82598EB:
835462fc 2354 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2355 break;
2356 case ixgbe_mac_82599EB:
b93a2226 2357 case ixgbe_mac_X540:
835462fc
NS		 2358 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2359 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2360 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2361 if (adapter->num_vfs > 32)
2362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2363 break;
2364 default:
2365 break;
22d5a71b
JB		 2366 }
2367 IXGBE_WRITE_FLUSH(&adapter->hw);
2368 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2369 int i;
2370 for (i = 0; i < adapter->num_msix_vectors; i++)
2371 synchronize_irq(adapter->msix_entries[i].vector);
2372 } else {
2373 synchronize_irq(adapter->pdev->irq);
2374 }
2375}
2376
9a799d71
AK		 2377/**
2378 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2379 *
2380 **/
2381static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2382{
9a799d71
AK		 2383 struct ixgbe_hw *hw = &adapter->hw;
2384
021230d4 2385 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2386 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2387
e8e26350
PW		 2388 ixgbe_set_ivar(adapter, 0, 0, 0);
2389 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2390
2391 map_vector_to_rxq(adapter, 0, 0);
2392 map_vector_to_txq(adapter, 0, 0);
2393
396e799c 2394 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2395}
2396
43e69bf0
AD		 2397/**
2398 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2399 * @adapter: board private structure
2400 * @ring: structure containing ring specific data
2401 *
2402 * Configure the Tx descriptor ring after a reset.
2403 **/
84418e3b
AD		 2404void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2405 struct ixgbe_ring *ring)
43e69bf0
AD		 2406{
2407 struct ixgbe_hw *hw = &adapter->hw;
2408 u64 tdba = ring->dma;
2f1860b8
AD		 2409 int wait_loop = 10;
2410 u32 txdctl;
bf29ee6c 2411 u8 reg_idx = ring->reg_idx;
43e69bf0 2412
2f1860b8
AD		 2413 /* disable queue to avoid issues while updating state */
2414 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2415 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2416 txdctl & ~IXGBE_TXDCTL_ENABLE);
2417 IXGBE_WRITE_FLUSH(hw);
2418
43e69bf0 2419 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2420 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2421 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2422 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2423 ring->count * sizeof(union ixgbe_adv_tx_desc));
2424 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2425 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2426 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2427
2f1860b8
AD		 2428 /* configure fetching thresholds */
2429 if (adapter->rx_itr_setting == 0) {
2430 /* cannot set wthresh when itr==0 */
2431 txdctl &= ~0x007F0000;
2432 } else {
2433 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2434 txdctl |= (8 << 16);
2435 }
2436 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2437 /* PThresh workaround for Tx hang with DFP enabled. */
2438 txdctl |= 32;
2439 }
2440
2441 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2442 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2443 adapter->atr_sample_rate) {
2444 ring->atr_sample_rate = adapter->atr_sample_rate;
2445 ring->atr_count = 0;
2446 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2447 } else {
2448 ring->atr_sample_rate = 0;
2449 }
2f1860b8 2450
c84d324c
JF		 2451 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2452
2f1860b8
AD		 2453 /* enable queue */
2454 txdctl |= IXGBE_TXDCTL_ENABLE;
2455 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2456
2457 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2458 if (hw->mac.type == ixgbe_mac_82598EB &&
2459 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2460 return;
2461
2462 /* poll to verify queue is enabled */
2463 do {
032b4325 2464 usleep_range(1000, 2000);
2f1860b8
AD		 2465 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2466 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2467 if (!wait_loop)
2468 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2469}
2470
120ff942
AD		 2471static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2472{
2473 struct ixgbe_hw *hw = &adapter->hw;
2474 u32 rttdcs;
72a32f1f 2475 u32 reg;
8b1c0b24 2476 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2477
2478 if (hw->mac.type == ixgbe_mac_82598EB)
2479 return;
2480
2481 /* disable the arbiter while setting MTQC */
2482 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2483 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2484 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2485
2486 /* set transmit pool layout */
8b1c0b24 2487 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2488 case (IXGBE_FLAG_SRIOV_ENABLED):
2489 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2490 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2491 break;
8b1c0b24
JF		 2492 default:
2493 if (!tcs)
2494 reg = IXGBE_MTQC_64Q_1PB;
2495 else if (tcs <= 4)
2496 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2497 else
2498 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2499
8b1c0b24 2500 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2501
8b1c0b24
JF		 2502 /* Enable Security TX Buffer IFG for multiple pb */
2503 if (tcs) {
2504 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2505 reg |= IXGBE_SECTX_DCB;
2506 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2507 }
120ff942
AD		 2508 break;
2509 }
2510
2511 /* re-enable the arbiter */
2512 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2513 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2514}
2515
9a799d71 2516/**
3a581073 2517 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2518 * @adapter: board private structure
2519 *
2520 * Configure the Tx unit of the MAC after a reset.
2521 **/
2522static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2523{
2f1860b8
AD		 2524 struct ixgbe_hw *hw = &adapter->hw;
2525 u32 dmatxctl;
43e69bf0 2526 u32 i;
9a799d71 2527
2f1860b8
AD		 2528 ixgbe_setup_mtqc(adapter);
2529
2530 if (hw->mac.type != ixgbe_mac_82598EB) {
2531 /* DMATXCTL.EN must be before Tx queues are enabled */
2532 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2533 dmatxctl |= IXGBE_DMATXCTL_TE;
2534 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2535 }
2536
9a799d71 2537 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2538 for (i = 0; i < adapter->num_tx_queues; i++)
2539 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2540}
2541
e8e26350 2542#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2543
a6616b42 2544static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2545 struct ixgbe_ring *rx_ring)
cc41ac7c 2546{
cc41ac7c 2547 u32 srrctl;
bf29ee6c 2548 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2549
bd508178
AD		 2550 switch (adapter->hw.mac.type) {
2551 case ixgbe_mac_82598EB: {
2552 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2553 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2554 reg_idx = reg_idx & mask;
cc41ac7c 2555 }
bd508178
AD		 2556 break;
2557 case ixgbe_mac_82599EB:
b93a2226 2558 case ixgbe_mac_X540:
bd508178
AD		 2559 default:
2560 break;
2561 }
2562
bf29ee6c 2563 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2564
2565 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2566 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2567 if (adapter->num_vfs)
2568 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2569
afafd5b0
AD		 2570 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2571 IXGBE_SRRCTL_BSIZEHDR_MASK;
2572
7d637bcc 2573 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2574#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2575 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2576#else
2577 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2578#endif
cc41ac7c 2579 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2580 } else {
afafd5b0
AD		 2581 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2582 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2583 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2584 }
e8e26350 2585
bf29ee6c 2586 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2587}
9a799d71 2588
05abb126 2589static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2590{
05abb126
AD		 2591 struct ixgbe_hw *hw = &adapter->hw;
2592 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2593 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2594 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2595 u32 mrqc = 0, reta = 0;
2596 u32 rxcsum;
2597 int i, j;
8b1c0b24 2598 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2599 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2600
2601 if (tcs)
2602 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2603
05abb126
AD		 2604 /* Fill out hash function seeds */
2605 for (i = 0; i < 10; i++)
2606 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2607
2608 /* Fill out redirection table */
2609 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2610 if (j == maxq)
05abb126
AD		 2611 j = 0;
2612 /* reta = 4-byte sliding window of
2613 * 0x00..(indices-1)(indices-1)00..etc. */
2614 reta = (reta << 8) | (j * 0x11);
2615 if ((i & 3) == 3)
2616 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2617 }
0cefafad 2618
05abb126
AD		 2619 /* Disable indicating checksum in descriptor, enables RSS hash */
2620 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2621 rxcsum |= IXGBE_RXCSUM_PCSD;
2622 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2623
8b1c0b24
JF		 2624 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2625 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2626 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2627 } else {
2628 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2629 | IXGBE_FLAG_SRIOV_ENABLED);
2630
2631 switch (mask) {
2632 case (IXGBE_FLAG_RSS_ENABLED):
2633 if (!tcs)
2634 mrqc = IXGBE_MRQC_RSSEN;
2635 else if (tcs <= 4)
2636 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2637 else
2638 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2639 break;
2640 case (IXGBE_FLAG_SRIOV_ENABLED):
2641 mrqc = IXGBE_MRQC_VMDQEN;
2642 break;
2643 default:
2644 break;
2645 }
0cefafad
JB		 2646 }
2647
05abb126
AD		 2648 /* Perform hash on these packet types */
2649 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2650 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2651 | IXGBE_MRQC_RSS_FIELD_IPV6
2652 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2653
2654 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2655}
2656
bb5a9ad2
NS		 2657/**
2658 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2659 * @adapter: address of board private structure
2660 * @index: index of ring to set
bb5a9ad2 2661 **/
082757af 2662static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2663 struct ixgbe_ring *ring)
bb5a9ad2 2664{
bb5a9ad2 2665 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2666 u32 rscctrl;
edd2ea55 2667 int rx_buf_len;
bf29ee6c 2668 u8 reg_idx = ring->reg_idx;
7367096a 2669
7d637bcc 2670 if (!ring_is_rsc_enabled(ring))
7367096a 2671 return;
bb5a9ad2 2672
7367096a
AD		 2673 rx_buf_len = ring->rx_buf_len;
2674 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2675 rscctrl |= IXGBE_RSCCTL_RSCEN;
2676 /*
2677 * we must limit the number of descriptors so that the
2678 * total size of max desc * buf_len is not greater
2679 * than 65535
2680 */
7d637bcc 2681 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2682#if (MAX_SKB_FRAGS > 16)
2683 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2684#elif (MAX_SKB_FRAGS > 8)
2685 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2686#elif (MAX_SKB_FRAGS > 4)
2687 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2688#else
2689 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2690#endif
2691 } else {
2692 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2693 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2694 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2695 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2696 else
2697 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2698 }
7367096a 2699 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2700}
2701
9e10e045
AD		 2702/**
2703 * ixgbe_set_uta - Set unicast filter table address
2704 * @adapter: board private structure
2705 *
2706 * The unicast table address is a register array of 32-bit registers.
2707 * The table is meant to be used in a way similar to how the MTA is used
2708 * however due to certain limitations in the hardware it is necessary to
2709 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2710 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2711 **/
2712static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2713{
2714 struct ixgbe_hw *hw = &adapter->hw;
2715 int i;
2716
2717 /* The UTA table only exists on 82599 hardware and newer */
2718 if (hw->mac.type < ixgbe_mac_82599EB)
2719 return;
2720
2721 /* we only need to do this if VMDq is enabled */
2722 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2723 return;
2724
2725 for (i = 0; i < 128; i++)
2726 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2727}
2728
2729#define IXGBE_MAX_RX_DESC_POLL 10
2730static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2731 struct ixgbe_ring *ring)
2732{
2733 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2734 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2735 u32 rxdctl;
bf29ee6c 2736 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2737
2738 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2739 if (hw->mac.type == ixgbe_mac_82598EB &&
2740 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2741 return;
2742
2743 do {
032b4325 2744 usleep_range(1000, 2000);
9e10e045
AD		 2745 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2746 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2747
2748 if (!wait_loop) {
2749 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2750 "the polling period\n", reg_idx);
2751 }
2752}
2753
2d39d576
YZ		 2754void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2755 struct ixgbe_ring *ring)
2756{
2757 struct ixgbe_hw *hw = &adapter->hw;
2758 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2759 u32 rxdctl;
2760 u8 reg_idx = ring->reg_idx;
2761
2762 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2763 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2764
2765 /* write value back with RXDCTL.ENABLE bit cleared */
2766 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2767
2768 if (hw->mac.type == ixgbe_mac_82598EB &&
2769 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2770 return;
2771
2772 /* the hardware may take up to 100us to really disable the rx queue */
2773 do {
2774 udelay(10);
2775 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2776 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2777
2778 if (!wait_loop) {
2779 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2780 "the polling period\n", reg_idx);
2781 }
2782}
2783
84418e3b
AD		 2784void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2785 struct ixgbe_ring *ring)
acd37177
AD		 2786{
2787 struct ixgbe_hw *hw = &adapter->hw;
2788 u64 rdba = ring->dma;
9e10e045 2789 u32 rxdctl;
bf29ee6c 2790 u8 reg_idx = ring->reg_idx;
acd37177 2791
9e10e045
AD		 2792 /* disable queue to avoid issues while updating state */
2793 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2794 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2795
acd37177
AD		 2796 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2797 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2798 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2799 ring->count * sizeof(union ixgbe_adv_rx_desc));
2800 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2801 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2802 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2803
2804 ixgbe_configure_srrctl(adapter, ring);
2805 ixgbe_configure_rscctl(adapter, ring);
2806
e9f98072
GR		 2807 /* If operating in IOV mode set RLPML for X540 */
2808 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2809 hw->mac.type == ixgbe_mac_X540) {
2810 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2811 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2812 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2813 }
2814
9e10e045
AD		 2815 if (hw->mac.type == ixgbe_mac_82598EB) {
2816 /*
2817 * enable cache line friendly hardware writes:
2818 * PTHRESH=32 descriptors (half the internal cache),
2819 * this also removes ugly rx_no_buffer_count increment
2820 * HTHRESH=4 descriptors (to minimize latency on fetch)
2821 * WTHRESH=8 burst writeback up to two cache lines
2822 */
2823 rxdctl &= ~0x3FFFFF;
2824 rxdctl |= 0x080420;
2825 }
2826
2827 /* enable receive descriptor ring */
2828 rxdctl |= IXGBE_RXDCTL_ENABLE;
2829 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2830
2831 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2832 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2833}
2834
48654521
AD		 2835static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2836{
2837 struct ixgbe_hw *hw = &adapter->hw;
2838 int p;
2839
2840 /* PSRTYPE must be initialized in non 82598 adapters */
2841 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2842 IXGBE_PSRTYPE_UDPHDR |
2843 IXGBE_PSRTYPE_IPV4HDR |
48654521 2844 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2845 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2846
2847 if (hw->mac.type == ixgbe_mac_82598EB)
2848 return;
2849
2850 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2851 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2852
2853 for (p = 0; p < adapter->num_rx_pools; p++)
2854 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2855 psrtype);
2856}
2857
f5b4a52e
AD		 2858static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2859{
2860 struct ixgbe_hw *hw = &adapter->hw;
2861 u32 gcr_ext;
2862 u32 vt_reg_bits;
2863 u32 reg_offset, vf_shift;
2864 u32 vmdctl;
2865
2866 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2867 return;
2868
2869 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2870 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2871 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2872 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2873
2874 vf_shift = adapter->num_vfs % 32;
2875 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2876
2877 /* Enable only the PF's pool for Tx/Rx */
2878 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2879 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2880 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2881 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2882 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2883
2884 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2885 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2886
2887 /*
2888 * Set up VF register offsets for selected VT Mode,
2889 * i.e. 32 or 64 VFs for SR-IOV
2890 */
2891 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2892 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2893 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2894 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2895
2896 /* enable Tx loopback for VF/PF communication */
2897 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2898 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 2899 hw->mac.ops.set_mac_anti_spoofing(hw,
2900 (adapter->antispoofing_enabled =
2901 (adapter->num_vfs != 0)),
a985b6c3 2902 adapter->num_vfs);
f5b4a52e
AD		 2903}
2904
477de6ed 2905static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2906{
9a799d71
AK		 2907 struct ixgbe_hw *hw = &adapter->hw;
2908 struct net_device *netdev = adapter->netdev;
2909 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2910 int rx_buf_len;
477de6ed
AD		 2911 struct ixgbe_ring *rx_ring;
2912 int i;
2913 u32 mhadd, hlreg0;
48654521 2914
9a799d71 2915 /* Decide whether to use packet split mode or not */
a124339a
DS		 2916 /* On by default */
2917 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2918
1cdd1ec8 2919 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2920 if (adapter->num_vfs)
2921 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2922
2923 /* Disable packet split due to 82599 erratum #45 */
2924 if (hw->mac.type == ixgbe_mac_82599EB)
2925 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 2926
2927 /* Set the RX buffer length according to the mode */
2928 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 2929 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 2930 } else {
0c19d6af 2931 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 2932 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 2933 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 2934 else
477de6ed 2935 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 2936 }
2937
63f39bd1 2938#ifdef IXGBE_FCOE
477de6ed
AD		 2939 /* adjust max frame to be able to do baby jumbo for FCoE */
2940 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2941 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2942 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2943
477de6ed
AD		 2944#endif /* IXGBE_FCOE */
2945 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2946 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2947 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2948 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2949
2950 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2951 }
2952
2953 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2954 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2955 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2956 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2957
0cefafad
JB		 2958 /*
2959 * Setup the HW Rx Head and Tail Descriptor Pointers and
2960 * the Base and Length of the Rx Descriptor Ring
2961 */
9a799d71 2962 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2963 rx_ring = adapter->rx_ring[i];
a6616b42 2964 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2965
6e455b89 2966 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2967 set_ring_ps_enabled(rx_ring);
2968 else
2969 clear_ring_ps_enabled(rx_ring);
2970
2971 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2972 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2973 else
7d637bcc 2974 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 2975
63f39bd1 2976#ifdef IXGBE_FCOE
e8e9f696 2977 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2978 struct ixgbe_ring_feature *f;
2979 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 2980 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 2981 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 2982 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2983 rx_ring->rx_buf_len =
e8e9f696 2984 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 2985 } else if (!ring_is_rsc_enabled(rx_ring) &&
2986 !ring_is_ps_enabled(rx_ring)) {
2987 rx_ring->rx_buf_len =
2988 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2989 }
63f39bd1 2990 }
63f39bd1 2991#endif /* IXGBE_FCOE */
477de6ed 2992 }
477de6ed
AD		 2993}
2994
7367096a
AD		 2995static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2996{
2997 struct ixgbe_hw *hw = &adapter->hw;
2998 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2999
3000 switch (hw->mac.type) {
3001 case ixgbe_mac_82598EB:
3002 /*
3003 * For VMDq support of different descriptor types or
3004 * buffer sizes through the use of multiple SRRCTL
3005 * registers, RDRXCTL.MVMEN must be set to 1
3006 *
3007 * also, the manual doesn't mention it clearly but DCA hints
3008 * will only use queue 0's tags unless this bit is set. Side
3009 * effects of setting this bit are only that SRRCTL must be
3010 * fully programmed [0..15]
3011 */
3012 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3013 break;
3014 case ixgbe_mac_82599EB:
b93a2226 3015 case ixgbe_mac_X540:
7367096a
AD		 3016 /* Disable RSC for ACK packets */
3017 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3018 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3019 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3020 /* hardware requires some bits to be set by default */
3021 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3022 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3023 break;
3024 default:
3025 /* We should do nothing since we don't know this hardware */
3026 return;
3027 }
3028
3029 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3030}
3031
477de6ed
AD		 3032/**
3033 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3034 * @adapter: board private structure
3035 *
3036 * Configure the Rx unit of the MAC after a reset.
3037 **/
3038static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3039{
3040 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3041 int i;
3042 u32 rxctrl;
477de6ed
AD		 3043
3044 /* disable receives while setting up the descriptors */
3045 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3046 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3047
3048 ixgbe_setup_psrtype(adapter);
7367096a 3049 ixgbe_setup_rdrxctl(adapter);
477de6ed 3050
9e10e045 3051 /* Program registers for the distribution of queues */
f5b4a52e 3052 ixgbe_setup_mrqc(adapter);
f5b4a52e 3053
9e10e045
AD		 3054 ixgbe_set_uta(adapter);
3055
477de6ed
AD		 3056 /* set_rx_buffer_len must be called before ring initialization */
3057 ixgbe_set_rx_buffer_len(adapter);
3058
3059 /*
3060 * Setup the HW Rx Head and Tail Descriptor Pointers and
3061 * the Base and Length of the Rx Descriptor Ring
3062 */
9e10e045
AD		 3063 for (i = 0; i < adapter->num_rx_queues; i++)
3064 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3065
9e10e045
AD		 3066 /* disable drop enable for 82598 parts */
3067 if (hw->mac.type == ixgbe_mac_82598EB)
3068 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3069
3070 /* enable all receives */
3071 rxctrl |= IXGBE_RXCTRL_RXEN;
3072 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3073}
3074
068c89b0
DS		 3075static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3076{
3077 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3078 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3079 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3080
3081 /* add VID to filter table */
1ada1b1b 3082 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3083 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3084}
3085
3086static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3087{
3088 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3089 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3090 int pool_ndx = adapter->num_vfs;
068c89b0 3091
068c89b0 3092 /* remove VID from filter table */
1ada1b1b 3093 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3094 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3095}
3096
5f6c0181
JB		 3097/**
3098 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3099 * @adapter: driver data
3100 */
3101static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3102{
3103 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3104 u32 vlnctrl;
3105
3106 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3107 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3108 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3109}
3110
3111/**
3112 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3113 * @adapter: driver data
3114 */
3115static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3116{
3117 struct ixgbe_hw *hw = &adapter->hw;
3118 u32 vlnctrl;
3119
3120 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3121 vlnctrl |= IXGBE_VLNCTRL_VFE;
3122 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3123 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3124}
3125
3126/**
3127 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3128 * @adapter: driver data
3129 */
3130static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3131{
3132 struct ixgbe_hw *hw = &adapter->hw;
3133 u32 vlnctrl;
5f6c0181
JB		 3134 int i, j;
3135
3136 switch (hw->mac.type) {
3137 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3138 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3139 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3140 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3141 break;
3142 case ixgbe_mac_82599EB:
b93a2226 3143 case ixgbe_mac_X540:
5f6c0181
JB		 3144 for (i = 0; i < adapter->num_rx_queues; i++) {
3145 j = adapter->rx_ring[i]->reg_idx;
3146 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3147 vlnctrl &= ~IXGBE_RXDCTL_VME;
3148 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3149 }
3150 break;
3151 default:
3152 break;
3153 }
3154}
3155
3156/**
f62bbb5e 3157 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3158 * @adapter: driver data
3159 */
f62bbb5e 3160static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3161{
3162 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3163 u32 vlnctrl;
5f6c0181
JB		 3164 int i, j;
3165
3166 switch (hw->mac.type) {
3167 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3168 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3169 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3170 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3171 break;
3172 case ixgbe_mac_82599EB:
b93a2226 3173 case ixgbe_mac_X540:
5f6c0181
JB		 3174 for (i = 0; i < adapter->num_rx_queues; i++) {
3175 j = adapter->rx_ring[i]->reg_idx;
3176 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3177 vlnctrl |= IXGBE_RXDCTL_VME;
3178 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3179 }
3180 break;
3181 default:
3182 break;
3183 }
3184}
3185
9a799d71
AK		 3186static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3187{
f62bbb5e 3188 u16 vid;
9a799d71 3189
f62bbb5e
JG		 3190 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3191
3192 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3193 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3194}
3195
2850062a
AD		 3196/**
3197 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3198 * @netdev: network interface device structure
3199 *
3200 * Writes unicast address list to the RAR table.
3201 * Returns: -ENOMEM on failure/insufficient address space
3202 * 0 on no addresses written
3203 * X on writing X addresses to the RAR table
3204 **/
3205static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3206{
3207 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3208 struct ixgbe_hw *hw = &adapter->hw;
3209 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3210 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3211 int count = 0;
3212
3213 /* return ENOMEM indicating insufficient memory for addresses */
3214 if (netdev_uc_count(netdev) > rar_entries)
3215 return -ENOMEM;
3216
3217 if (!netdev_uc_empty(netdev) && rar_entries) {
3218 struct netdev_hw_addr *ha;
3219 /* return error if we do not support writing to RAR table */
3220 if (!hw->mac.ops.set_rar)
3221 return -ENOMEM;
3222
3223 netdev_for_each_uc_addr(ha, netdev) {
3224 if (!rar_entries)
3225 break;
3226 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3227 vfn, IXGBE_RAH_AV);
3228 count++;
3229 }
3230 }
3231 /* write the addresses in reverse order to avoid write combining */
3232 for (; rar_entries > 0 ; rar_entries--)
3233 hw->mac.ops.clear_rar(hw, rar_entries);
3234
3235 return count;
3236}
3237
9a799d71 3238/**
2c5645cf 3239 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3240 * @netdev: network interface device structure
3241 *
2c5645cf
CL		 3242 * The set_rx_method entry point is called whenever the unicast/multicast
3243 * address list or the network interface flags are updated. This routine is
3244 * responsible for configuring the hardware for proper unicast, multicast and
3245 * promiscuous mode.
9a799d71 3246 **/
7f870475 3247void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3248{
3249 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3250 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3251 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3252 int count;
9a799d71
AK		 3253
3254 /* Check for Promiscuous and All Multicast modes */
3255
3256 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3257
f5dc442b
AD		 3258 /* set all bits that we expect to always be set */
3259 fctrl |= IXGBE_FCTRL_BAM;
3260 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3261 fctrl |= IXGBE_FCTRL_PMCF;
3262
2850062a
AD		 3263 /* clear the bits we are changing the status of */
3264 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3265
9a799d71 3266 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3267 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3268 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3269 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3270 /* don't hardware filter vlans in promisc mode */
3271 ixgbe_vlan_filter_disable(adapter);
9a799d71 3272 } else {
746b9f02
PM		 3273 if (netdev->flags & IFF_ALLMULTI) {
3274 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3275 vmolr |= IXGBE_VMOLR_MPE;
3276 } else {
3277 /*
3278 * Write addresses to the MTA, if the attempt fails
25985edc 3279 * then we should just turn on promiscuous mode so
2850062a
AD		 3280 * that we can at least receive multicast traffic
3281 */
3282 hw->mac.ops.update_mc_addr_list(hw, netdev);
3283 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3284 }
5f6c0181 3285 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3286 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3287 /*
3288 * Write addresses to available RAR registers, if there is not
3289 * sufficient space to store all the addresses then enable
25985edc 3290 * unicast promiscuous mode
2850062a
AD		 3291 */
3292 count = ixgbe_write_uc_addr_list(netdev);
3293 if (count < 0) {
3294 fctrl |= IXGBE_FCTRL_UPE;
3295 vmolr |= IXGBE_VMOLR_ROPE;
3296 }
9a799d71
AK		 3297 }
3298
2850062a 3299 if (adapter->num_vfs) {
1cdd1ec8 3300 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3301 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3302 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3303 IXGBE_VMOLR_ROPE);
3304 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3305 }
3306
3307 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3308
3309 if (netdev->features & NETIF_F_HW_VLAN_RX)
3310 ixgbe_vlan_strip_enable(adapter);
3311 else
3312 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3313}
3314
021230d4
AV		 3315static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3316{
3317 int q_idx;
3318 struct ixgbe_q_vector *q_vector;
3319 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3320
3321 /* legacy and MSI only use one vector */
3322 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3323 q_vectors = 1;
3324
3325 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3326 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3327 napi_enable(&q_vector->napi);
021230d4
AV		 3328 }
3329}
3330
3331static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3332{
3333 int q_idx;
3334 struct ixgbe_q_vector *q_vector;
3335 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3336
3337 /* legacy and MSI only use one vector */
3338 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3339 q_vectors = 1;
3340
3341 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3342 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3343 napi_disable(&q_vector->napi);
3344 }
3345}
3346
7a6b6f51 3347#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3348/*
3349 * ixgbe_configure_dcb - Configure DCB hardware
3350 * @adapter: ixgbe adapter struct
3351 *
3352 * This is called by the driver on open to configure the DCB hardware.
3353 * This is also called by the gennetlink interface when reconfiguring
3354 * the DCB state.
3355 */
3356static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3357{
3358 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3359 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3360
67ebd791
AD		 3361 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3362 if (hw->mac.type == ixgbe_mac_82598EB)
3363 netif_set_gso_max_size(adapter->netdev, 65536);
3364 return;
3365 }
3366
3367 if (hw->mac.type == ixgbe_mac_82598EB)
3368 netif_set_gso_max_size(adapter->netdev, 32768);
3369
2f90b865 3370
2f90b865 3371 /* Enable VLAN tag insert/strip */
f62bbb5e 3372 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3373
2f90b865 3374 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3375
3376 /* reconfigure the hardware */
6f70f6ac 3377 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
971060b1 3378#ifdef IXGBE_FCOE
c27931da
JF		 3379 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3380 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3381#endif
3382 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3383 DCB_TX_CONFIG);
3384 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3385 DCB_RX_CONFIG);
3386 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3387 } else {
3388 struct net_device *dev = adapter->netdev;
3389
3390 if (adapter->ixgbe_ieee_ets)
3391 dev->dcbnl_ops->ieee_setets(dev,
3392 adapter->ixgbe_ieee_ets);
3393 if (adapter->ixgbe_ieee_pfc)
3394 dev->dcbnl_ops->ieee_setpfc(dev,
3395 adapter->ixgbe_ieee_pfc);
3396 }
8187cd48
JF		 3397
3398 /* Enable RSS Hash per TC */
3399 if (hw->mac.type != ixgbe_mac_82598EB) {
3400 int i;
3401 u32 reg = 0;
3402
3403 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3404 u8 msb = 0;
3405 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3406
3407 while (cnt >>= 1)
3408 msb++;
3409
3410 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3411 }
3412 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3413 }
2f90b865
AD		 3414}
3415
3416#endif
80605c65
JF		 3417
3418static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3419{
3420 int hdrm = 0;
3421 int num_tc = netdev_get_num_tc(adapter->netdev);
3422 struct ixgbe_hw *hw = &adapter->hw;
3423
3424 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3425 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3426 hdrm = 64 << adapter->fdir_pballoc;
3427
3428 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3429}
3430
e4911d57
AD		 3431static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3432{
3433 struct ixgbe_hw *hw = &adapter->hw;
3434 struct hlist_node *node, *node2;
3435 struct ixgbe_fdir_filter *filter;
3436
3437 spin_lock(&adapter->fdir_perfect_lock);
3438
3439 if (!hlist_empty(&adapter->fdir_filter_list))
3440 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3441
3442 hlist_for_each_entry_safe(filter, node, node2,
3443 &adapter->fdir_filter_list, fdir_node) {
3444 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3445 &filter->filter,
3446 filter->sw_idx,
3447 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3448 IXGBE_FDIR_DROP_QUEUE :
3449 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3450 }
3451
3452 spin_unlock(&adapter->fdir_perfect_lock);
3453}
3454
9a799d71
AK		 3455static void ixgbe_configure(struct ixgbe_adapter *adapter)
3456{
3457 struct net_device *netdev = adapter->netdev;
c4cf55e5 3458 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3459 int i;
3460
80605c65 3461 ixgbe_configure_pb(adapter);
7a6b6f51 3462#ifdef CONFIG_IXGBE_DCB
67ebd791 3463 ixgbe_configure_dcb(adapter);
2f90b865 3464#endif
9a799d71 3465
f62bbb5e
JG		 3466 ixgbe_set_rx_mode(netdev);
3467 ixgbe_restore_vlan(adapter);
3468
eacd73f7
YZ		 3469#ifdef IXGBE_FCOE
3470 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3471 ixgbe_configure_fcoe(adapter);
3472
3473#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3474 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3475 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3476 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3477 adapter->atr_sample_rate;
c4cf55e5 3478 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
e4911d57
AD		 3479 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3480 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3481 adapter->fdir_pballoc);
3482 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3483 }
933d41f1 3484 ixgbe_configure_virtualization(adapter);
c4cf55e5 3485
9a799d71
AK		 3486 ixgbe_configure_tx(adapter);
3487 ixgbe_configure_rx(adapter);
9a799d71
AK		 3488}
3489
e8e26350
PW		 3490static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3491{
3492 switch (hw->phy.type) {
3493 case ixgbe_phy_sfp_avago:
3494 case ixgbe_phy_sfp_ftl:
3495 case ixgbe_phy_sfp_intel:
3496 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3497 case ixgbe_phy_sfp_passive_tyco:
3498 case ixgbe_phy_sfp_passive_unknown:
3499 case ixgbe_phy_sfp_active_unknown:
3500 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3501 return true;
3502 default:
3503 return false;
3504 }
3505}
3506
0ecc061d 3507/**
e8e26350
PW		 3508 * ixgbe_sfp_link_config - set up SFP+ link
3509 * @adapter: pointer to private adapter struct
3510 **/
3511static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3512{
7086400d
AD		 3513 /*
3514 * We are assuming the worst case scenerio here, and that
3515 * is that an SFP was inserted/removed after the reset
3516 * but before SFP detection was enabled. As such the best
3517 * solution is to just start searching as soon as we start
3518 */
3519 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3520 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3521
7086400d 3522 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3523}
3524
3525/**
3526 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3527 * @hw: pointer to private hardware struct
3528 *
3529 * Returns 0 on success, negative on failure
3530 **/
e8e26350 3531static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3532{
3533 u32 autoneg;
8620a103 3534 bool negotiation, link_up = false;
0ecc061d
PWJ		 3535 u32 ret = IXGBE_ERR_LINK_SETUP;
3536
3537 if (hw->mac.ops.check_link)
3538 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3539
3540 if (ret)
3541 goto link_cfg_out;
3542
0b0c2b31
ET		 3543 autoneg = hw->phy.autoneg_advertised;
3544 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3545 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3546 &negotiation);
0ecc061d
PWJ		 3547 if (ret)
3548 goto link_cfg_out;
3549
8620a103
MC		 3550 if (hw->mac.ops.setup_link)
3551 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3552link_cfg_out:
3553 return ret;
3554}
3555
a34bcfff 3556static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3557{
9a799d71 3558 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3559 u32 gpie = 0;
9a799d71 3560
9b471446 3561 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3562 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3563 IXGBE_GPIE_OCD;
3564 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3565 /*
3566 * use EIAM to auto-mask when MSI-X interrupt is asserted
3567 * this saves a register write for every interrupt
3568 */
3569 switch (hw->mac.type) {
3570 case ixgbe_mac_82598EB:
3571 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3572 break;
9b471446 3573 case ixgbe_mac_82599EB:
b93a2226
DS		 3574 case ixgbe_mac_X540:
3575 default:
9b471446
JB		 3576 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3577 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3578 break;
3579 }
3580 } else {
021230d4
AV		 3581 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3582 * specifically only auto mask tx and rx interrupts */
3583 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3584 }
9a799d71 3585
a34bcfff
AD		 3586 /* XXX: to interrupt immediately for EICS writes, enable this */
3587 /* gpie |= IXGBE_GPIE_EIMEN; */
3588
3589 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3590 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3591 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3592 }
3593
a34bcfff
AD		 3594 /* Enable fan failure interrupt */
3595 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3596 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3597
2698b208 3598 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3599 gpie |= IXGBE_SDP1_GPIEN;
3600 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3601 }
a34bcfff
AD		 3602
3603 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3604}
3605
3606static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3607{
3608 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3609 int err;
a34bcfff
AD		 3610 u32 ctrl_ext;
3611
3612 ixgbe_get_hw_control(adapter);
3613 ixgbe_setup_gpie(adapter);
e8e26350 3614
9a799d71
AK		 3615 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3616 ixgbe_configure_msix(adapter);
3617 else
3618 ixgbe_configure_msi_and_legacy(adapter);
3619
c6ecf39a
DS		 3620 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3621 if (hw->mac.ops.enable_tx_laser &&
3622 ((hw->phy.multispeed_fiber) ||
9f911707 3623 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3624 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3625 hw->mac.ops.enable_tx_laser(hw);
3626
9a799d71 3627 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3628 ixgbe_napi_enable_all(adapter);
3629
73c4b7cd
AD		 3630 if (ixgbe_is_sfp(hw)) {
3631 ixgbe_sfp_link_config(adapter);
3632 } else {
3633 err = ixgbe_non_sfp_link_config(hw);
3634 if (err)
3635 e_err(probe, "link_config FAILED %d\n", err);
3636 }
3637
021230d4
AV		 3638 /* clear any pending interrupts, may auto mask */
3639 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3640 ixgbe_irq_enable(adapter, true, true);
9a799d71 3641
bf069c97
DS		 3642 /*
3643 * If this adapter has a fan, check to see if we had a failure
3644 * before we enabled the interrupt.
3645 */
3646 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3647 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3648 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3649 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3650 }
3651
1da100bb 3652 /* enable transmits */
477de6ed 3653 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3654
9a799d71
AK		 3655 /* bring the link up in the watchdog, this could race with our first
3656 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3657 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3658 adapter->link_check_timeout = jiffies;
7086400d 3659 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3660
3661 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3662 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3663 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3664 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3665
9a799d71
AK		 3666 return 0;
3667}
3668
d4f80882
AV		 3669void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3670{
3671 WARN_ON(in_interrupt());
7086400d
AD		 3672 /* put off any impending NetWatchDogTimeout */
3673 adapter->netdev->trans_start = jiffies;
3674
d4f80882 3675 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3676 usleep_range(1000, 2000);
d4f80882 3677 ixgbe_down(adapter);
5809a1ae
GR		 3678 /*
3679 * If SR-IOV enabled then wait a bit before bringing the adapter
3680 * back up to give the VFs time to respond to the reset. The
3681 * two second wait is based upon the watchdog timer cycle in
3682 * the VF driver.
3683 */
3684 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3685 msleep(2000);
d4f80882
AV		 3686 ixgbe_up(adapter);
3687 clear_bit(__IXGBE_RESETTING, &adapter->state);
3688}
3689
9a799d71
AK		 3690int ixgbe_up(struct ixgbe_adapter *adapter)
3691{
3692 /* hardware has been reset, we need to reload some things */
3693 ixgbe_configure(adapter);
3694
3695 return ixgbe_up_complete(adapter);
3696}
3697
3698void ixgbe_reset(struct ixgbe_adapter *adapter)
3699{
c44ade9e 3700 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3701 int err;
3702
7086400d
AD		 3703 /* lock SFP init bit to prevent race conditions with the watchdog */
3704 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3705 usleep_range(1000, 2000);
3706
3707 /* clear all SFP and link config related flags while holding SFP_INIT */
3708 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3709 IXGBE_FLAG2_SFP_NEEDS_RESET);
3710 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3711
8ca783ab 3712 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3713 switch (err) {
3714 case 0:
3715 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3716 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3717 break;
3718 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3719 e_dev_err("master disable timed out\n");
da4dd0f7 3720 break;
794caeb2
PWJ		 3721 case IXGBE_ERR_EEPROM_VERSION:
3722 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3723 e_dev_warn("This device is a pre-production adapter/LOM. "
3724 "Please be aware there may be issuesassociated with "
3725 "your hardware. If you are experiencing problems "
3726 "please contact your Intel or hardware "
3727 "representative who provided you with this "
3728 "hardware.\n");
794caeb2 3729 break;
da4dd0f7 3730 default:
849c4542 3731 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3732 }
9a799d71 3733
7086400d
AD		 3734 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3735
9a799d71 3736 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3737 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3738 IXGBE_RAH_AV);
9a799d71
AK		 3739}
3740
9a799d71
AK		 3741/**
3742 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3743 * @rx_ring: ring to free buffers from
3744 **/
b6ec895e 3745static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3746{
b6ec895e 3747 struct device *dev = rx_ring->dev;
9a799d71 3748 unsigned long size;
b6ec895e 3749 u16 i;
9a799d71 3750
84418e3b
AD		 3751 /* ring already cleared, nothing to do */
3752 if (!rx_ring->rx_buffer_info)
3753 return;
9a799d71 3754
84418e3b 3755 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3756 for (i = 0; i < rx_ring->count; i++) {
3757 struct ixgbe_rx_buffer *rx_buffer_info;
3758
3759 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3760 if (rx_buffer_info->dma) {
b6ec895e 3761 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3762 rx_ring->rx_buf_len,
1b507730 3763 DMA_FROM_DEVICE);
9a799d71
AK		 3764 rx_buffer_info->dma = 0;
3765 }
3766 if (rx_buffer_info->skb) {
f8212f97 3767 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3768 rx_buffer_info->skb = NULL;
f8212f97
AD		 3769 do {
3770 struct sk_buff *this = skb;
e8171aaa 3771 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3772 dma_unmap_single(dev,
1b507730 3773 IXGBE_RSC_CB(this)->dma,
e8e9f696 3774 rx_ring->rx_buf_len,
1b507730 3775 DMA_FROM_DEVICE);
fd3686a8 3776 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3777 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3778 }
f8212f97
AD		 3779 skb = skb->prev;
3780 dev_kfree_skb(this);
3781 } while (skb);
9a799d71
AK		 3782 }
3783 if (!rx_buffer_info->page)
3784 continue;
4f57ca6e 3785 if (rx_buffer_info->page_dma) {
b6ec895e 3786 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3787 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3788 rx_buffer_info->page_dma = 0;
3789 }
9a799d71
AK		 3790 put_page(rx_buffer_info->page);
3791 rx_buffer_info->page = NULL;
762f4c57 3792 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3793 }
3794
3795 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3796 memset(rx_ring->rx_buffer_info, 0, size);
3797
3798 /* Zero out the descriptor ring */
3799 memset(rx_ring->desc, 0, rx_ring->size);
3800
3801 rx_ring->next_to_clean = 0;
3802 rx_ring->next_to_use = 0;
9a799d71
AK		 3803}
3804
3805/**
3806 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3807 * @tx_ring: ring to be cleaned
3808 **/
b6ec895e 3809static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3810{
3811 struct ixgbe_tx_buffer *tx_buffer_info;
3812 unsigned long size;
b6ec895e 3813 u16 i;
9a799d71 3814
84418e3b
AD		 3815 /* ring already cleared, nothing to do */
3816 if (!tx_ring->tx_buffer_info)
3817 return;
9a799d71 3818
84418e3b 3819 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3820 for (i = 0; i < tx_ring->count; i++) {
3821 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3822 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3823 }
3824
3825 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3826 memset(tx_ring->tx_buffer_info, 0, size);
3827
3828 /* Zero out the descriptor ring */
3829 memset(tx_ring->desc, 0, tx_ring->size);
3830
3831 tx_ring->next_to_use = 0;
3832 tx_ring->next_to_clean = 0;
9a799d71
AK		 3833}
3834
3835/**
021230d4 3836 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3837 * @adapter: board private structure
3838 **/
021230d4 3839static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3840{
3841 int i;
3842
021230d4 3843 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3844 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3845}
3846
3847/**
021230d4 3848 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3849 * @adapter: board private structure
3850 **/
021230d4 3851static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3852{
3853 int i;
3854
021230d4 3855 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3856 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3857}
3858
e4911d57
AD		 3859static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3860{
3861 struct hlist_node *node, *node2;
3862 struct ixgbe_fdir_filter *filter;
3863
3864 spin_lock(&adapter->fdir_perfect_lock);
3865
3866 hlist_for_each_entry_safe(filter, node, node2,
3867 &adapter->fdir_filter_list, fdir_node) {
3868 hlist_del(&filter->fdir_node);
3869 kfree(filter);
3870 }
3871 adapter->fdir_filter_count = 0;
3872
3873 spin_unlock(&adapter->fdir_perfect_lock);
3874}
3875
9a799d71
AK		 3876void ixgbe_down(struct ixgbe_adapter *adapter)
3877{
3878 struct net_device *netdev = adapter->netdev;
7f821875 3879 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3880 u32 rxctrl;
bf29ee6c 3881 int i;
b25ebfd2 3882 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 3883
3884 /* signal that we are down to the interrupt handler */
3885 set_bit(__IXGBE_DOWN, &adapter->state);
3886
3887 /* disable receives */
7f821875
JB		 3888 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3889 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3890
2d39d576
YZ		 3891 /* disable all enabled rx queues */
3892 for (i = 0; i < adapter->num_rx_queues; i++)
3893 /* this call also flushes the previous write */
3894 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3895
032b4325 3896 usleep_range(10000, 20000);
9a799d71 3897
7f821875
JB		 3898 netif_tx_stop_all_queues(netdev);
3899
7086400d 3900 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 3901 netif_carrier_off(netdev);
3902 netif_tx_disable(netdev);
3903
3904 ixgbe_irq_disable(adapter);
3905
3906 ixgbe_napi_disable_all(adapter);
3907
d034acf1
AD		 3908 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
3909 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 3910 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3911
3912 del_timer_sync(&adapter->service_timer);
3913
34cecbbf
AD		 3914 /* disable receive for all VFs and wait one second */
3915 if (adapter->num_vfs) {
3916 /* ping all the active vfs to let them know we are going down */
3917 ixgbe_ping_all_vfs(adapter);
3918
3919 /* Disable all VFTE/VFRE TX/RX */
3920 ixgbe_disable_tx_rx(adapter);
3921
3922 /* Mark all the VFs as inactive */
3923 for (i = 0 ; i < adapter->num_vfs; i++)
3924 adapter->vfinfo[i].clear_to_send = 0;
3925 }
3926
b25ebfd2
PW		 3927 /* Cleanup the affinity_hint CPU mask memory and callback */
3928 for (i = 0; i < num_q_vectors; i++) {
3929 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3930 /* clear the affinity_mask in the IRQ descriptor */
3931 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3932 /* release the CPU mask memory */
3933 free_cpumask_var(q_vector->affinity_mask);
3934 }
3935
7f821875
JB		 3936 /* disable transmits in the hardware now that interrupts are off */
3937 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 3938 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 3939 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 3940 }
34cecbbf
AD		 3941
3942 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 3943 switch (hw->mac.type) {
3944 case ixgbe_mac_82599EB:
b93a2226 3945 case ixgbe_mac_X540:
88512539 3946 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 3947 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3948 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 3949 break;
3950 default:
3951 break;
3952 }
7f821875 3953
6f4a0e45
PL		 3954 if (!pci_channel_offline(adapter->pdev))
3955 ixgbe_reset(adapter);
c6ecf39a
DS		 3956
3957 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
3958 if (hw->mac.ops.disable_tx_laser &&
3959 ((hw->phy.multispeed_fiber) ||
9f911707 3960 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 3961 (hw->mac.type == ixgbe_mac_82599EB))))
3962 hw->mac.ops.disable_tx_laser(hw);
3963
9a799d71
AK		 3964 ixgbe_clean_all_tx_rings(adapter);
3965 ixgbe_clean_all_rx_rings(adapter);
3966
5dd2d332 3967#ifdef CONFIG_IXGBE_DCA
96b0e0f6 3968 /* since we reset the hardware DCA settings were cleared */
e35ec126 3969 ixgbe_setup_dca(adapter);
96b0e0f6 3970#endif
9a799d71
AK		 3971}
3972
9a799d71 3973/**
021230d4
AV		 3974 * ixgbe_poll - NAPI Rx polling callback
3975 * @napi: structure for representing this polling device
3976 * @budget: how many packets driver is allowed to clean
3977 *
3978 * This function is used for legacy and MSI, NAPI mode
9a799d71 3979 **/
021230d4 3980static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 3981{
9a1a69ad 3982 struct ixgbe_q_vector *q_vector =
e8e9f696 3983 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 3984 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 3985 struct ixgbe_ring *ring;
3986 int per_ring_budget;
3987 bool clean_complete = true;
9a799d71 3988
5dd2d332 3989#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 3990 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3991 ixgbe_update_dca(q_vector);
bd0362dd
JC		 3992#endif
3993
4ff7fb12
AD		 3994 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
3995 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 3996
4ff7fb12
AD		 3997 /* attempt to distribute budget to each queue fairly, but don't allow
3998 * the budget to go below 1 because we'll exit polling */
3999 if (q_vector->rx.count > 1)
4000 per_ring_budget = max(budget/q_vector->rx.count, 1);
4001 else
4002 per_ring_budget = budget;
d2c7ddd6 4003
4ff7fb12
AD		 4004 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4005 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4006 per_ring_budget);
4007
4008 /* If all work not completed, return budget and keep polling */
4009 if (!clean_complete)
4010 return budget;
4011
4012 /* all work done, exit the polling mode */
4013 napi_complete(napi);
4014 if (adapter->rx_itr_setting & 1)
4015 ixgbe_set_itr(q_vector);
4016 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4017 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4018
4019 return 0;
9a799d71
AK		 4020}
4021
4022/**
4023 * ixgbe_tx_timeout - Respond to a Tx Hang
4024 * @netdev: network interface device structure
4025 **/
4026static void ixgbe_tx_timeout(struct net_device *netdev)
4027{
4028 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4029
4030 /* Do the reset outside of interrupt context */
c83c6cbd 4031 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4032}
4033
4df10466
JB		 4034/**
4035 * ixgbe_set_rss_queues: Allocate queues for RSS
4036 * @adapter: board private structure to initialize
4037 *
4038 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4039 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4040 *
4041 **/
bc97114d
PWJ		 4042static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4043{
4044 bool ret = false;
0cefafad 4045 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4046
4047 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4048 f->mask = 0xF;
4049 adapter->num_rx_queues = f->indices;
4050 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4051 ret = true;
4052 } else {
bc97114d 4053 ret = false;
b9804972
JB		 4054 }
4055
bc97114d
PWJ		 4056 return ret;
4057}
4058
c4cf55e5
PWJ		 4059/**
4060 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4061 * @adapter: board private structure to initialize
4062 *
4063 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4064 * to the original CPU that initiated the Tx session. This runs in addition
4065 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4066 * Rx load across CPUs using RSS.
4067 *
4068 **/
e8e9f696 4069static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4070{
4071 bool ret = false;
4072 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4073
4074 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4075 f_fdir->mask = 0;
4076
4077 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4078 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4079 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4080 adapter->num_tx_queues = f_fdir->indices;
4081 adapter->num_rx_queues = f_fdir->indices;
4082 ret = true;
4083 } else {
4084 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4085 }
4086 return ret;
4087}
4088
0331a832
YZ		 4089#ifdef IXGBE_FCOE
4090/**
4091 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4092 * @adapter: board private structure to initialize
4093 *
4094 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4095 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4096 * rx queues out of the max number of rx queues, instead, it is used as the
4097 * index of the first rx queue used by FCoE.
4098 *
4099 **/
4100static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4101{
0331a832
YZ		 4102 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4103
e5b64635
JF		 4104 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4105 return false;
4106
e901acd6 4107 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4108
e901acd6
JF		 4109 adapter->num_rx_queues = 1;
4110 adapter->num_tx_queues = 1;
e5b64635 4111
e901acd6
JF		 4112 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4113 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4114 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4115 ixgbe_set_fdir_queues(adapter);
4116 else
4117 ixgbe_set_rss_queues(adapter);
e5b64635 4118 }
03ecf91a 4119
e901acd6
JF		 4120 /* adding FCoE rx rings to the end */
4121 f->mask = adapter->num_rx_queues;
4122 adapter->num_rx_queues += f->indices;
4123 adapter->num_tx_queues += f->indices;
0331a832 4124
e5b64635
JF		 4125 return true;
4126}
4127#endif /* IXGBE_FCOE */
4128
e901acd6
JF		 4129/* Artificial max queue cap per traffic class in DCB mode */
4130#define DCB_QUEUE_CAP 8
4131
e5b64635
JF		 4132#ifdef CONFIG_IXGBE_DCB
4133static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4134{
e901acd6
JF		 4135 int per_tc_q, q, i, offset = 0;
4136 struct net_device *dev = adapter->netdev;
4137 int tcs = netdev_get_num_tc(dev);
e5b64635 4138
e901acd6
JF		 4139 if (!tcs)
4140 return false;
e5b64635 4141
e901acd6
JF		 4142 /* Map queue offset and counts onto allocated tx queues */
4143 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4144 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4145
8b1c0b24 4146 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4147 netdev_set_prio_tc_map(dev, i, i);
4148 netdev_set_tc_queue(dev, i, q, offset);
4149 offset += q;
0331a832
YZ		 4150 }
4151
e901acd6
JF		 4152 adapter->num_tx_queues = q * tcs;
4153 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4154
4155#ifdef IXGBE_FCOE
e901acd6
JF		 4156 /* FCoE enabled queues require special configuration indexed
4157 * by feature specific indices and mask. Here we map FCoE
4158 * indices onto the DCB queue pairs allowing FCoE to own
4159 * configuration later.
e5b64635 4160 */
e901acd6
JF		 4161 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4162 int tc;
4163 struct ixgbe_ring_feature *f =
4164 &adapter->ring_feature[RING_F_FCOE];
4165
4166 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4167 f->indices = dev->tc_to_txq[tc].count;
4168 f->mask = dev->tc_to_txq[tc].offset;
4169 }
e5b64635
JF		 4170#endif
4171
e901acd6 4172 return true;
0331a832 4173}
e5b64635 4174#endif
0331a832 4175
1cdd1ec8
GR		 4176/**
4177 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4178 * @adapter: board private structure to initialize
4179 *
4180 * IOV doesn't actually use anything, so just NAK the
4181 * request for now and let the other queue routines
4182 * figure out what to do.
4183 */
4184static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4185{
4186 return false;
4187}
4188
4df10466 4189/*
25985edc 4190 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4191 * @adapter: board private structure to initialize
4192 *
4193 * This is the top level queue allocation routine. The order here is very
4194 * important, starting with the "most" number of features turned on at once,
4195 * and ending with the smallest set of features. This way large combinations
4196 * can be allocated if they're turned on, and smaller combinations are the
4197 * fallthrough conditions.
4198 *
4199 **/
847f53ff 4200static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4201{
1cdd1ec8
GR		 4202 /* Start with base case */
4203 adapter->num_rx_queues = 1;
4204 adapter->num_tx_queues = 1;
4205 adapter->num_rx_pools = adapter->num_rx_queues;
4206 adapter->num_rx_queues_per_pool = 1;
4207
4208 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4209 goto done;
1cdd1ec8 4210
bc97114d
PWJ		 4211#ifdef CONFIG_IXGBE_DCB
4212 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4213 goto done;
bc97114d
PWJ		 4214
4215#endif
e5b64635
JF		 4216#ifdef IXGBE_FCOE
4217 if (ixgbe_set_fcoe_queues(adapter))
4218 goto done;
4219
4220#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4221 if (ixgbe_set_fdir_queues(adapter))
4222 goto done;
4223
bc97114d 4224 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4225 goto done;
4226
4227 /* fallback to base case */
4228 adapter->num_rx_queues = 1;
4229 adapter->num_tx_queues = 1;
4230
4231done:
847f53ff 4232 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4233 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4234 return netif_set_real_num_rx_queues(adapter->netdev,
4235 adapter->num_rx_queues);
b9804972
JB		 4236}
4237
021230d4 4238static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4239 int vectors)
021230d4
AV		 4240{
4241 int err, vector_threshold;
4242
4243 /* We'll want at least 3 (vector_threshold):
4244 * 1) TxQ[0] Cleanup
4245 * 2) RxQ[0] Cleanup
4246 * 3) Other (Link Status Change, etc.)
4247 * 4) TCP Timer (optional)
4248 */
4249 vector_threshold = MIN_MSIX_COUNT;
4250
4251 /* The more we get, the more we will assign to Tx/Rx Cleanup
4252 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4253 * Right now, we simply care about how many we'll get; we'll
4254 * set them up later while requesting irq's.
4255 */
4256 while (vectors >= vector_threshold) {
4257 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4258 vectors);
021230d4
AV		 4259 if (!err) /* Success in acquiring all requested vectors. */
4260 break;
4261 else if (err < 0)
4262 vectors = 0; /* Nasty failure, quit now */
4263 else /* err == number of vectors we should try again with */
4264 vectors = err;
4265 }
4266
4267 if (vectors < vector_threshold) {
4268 /* Can't allocate enough MSI-X interrupts? Oh well.
4269 * This just means we'll go with either a single MSI
4270 * vector or fall back to legacy interrupts.
4271 */
849c4542
ET		 4272 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4273 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4274 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4275 kfree(adapter->msix_entries);
4276 adapter->msix_entries = NULL;
021230d4
AV		 4277 } else {
4278 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4279 /*
4280 * Adjust for only the vectors we'll use, which is minimum
4281 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4282 * vectors we were allocated.
4283 */
4284 adapter->num_msix_vectors = min(vectors,
e8e9f696 4285 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4286 }
4287}
4288
021230d4 4289/**
bc97114d 4290 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4291 * @adapter: board private structure to initialize
4292 *
bc97114d
PWJ		 4293 * Cache the descriptor ring offsets for RSS to the assigned rings.
4294 *
021230d4 4295 **/
bc97114d 4296static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4297{
bc97114d 4298 int i;
bc97114d 4299
9d6b758f
AD		 4300 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4301 return false;
bc97114d 4302
9d6b758f
AD		 4303 for (i = 0; i < adapter->num_rx_queues; i++)
4304 adapter->rx_ring[i]->reg_idx = i;
4305 for (i = 0; i < adapter->num_tx_queues; i++)
4306 adapter->tx_ring[i]->reg_idx = i;
4307
4308 return true;
bc97114d
PWJ		 4309}
4310
4311#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4312
4313/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4314static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4315 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4316{
4317 struct net_device *dev = adapter->netdev;
4318 struct ixgbe_hw *hw = &adapter->hw;
4319 u8 num_tcs = netdev_get_num_tc(dev);
4320
4321 *tx = 0;
4322 *rx = 0;
4323
4324 switch (hw->mac.type) {
4325 case ixgbe_mac_82598EB:
aba70d5e
JF		 4326 *tx = tc << 2;
4327 *rx = tc << 3;
e5b64635
JF		 4328 break;
4329 case ixgbe_mac_82599EB:
4330 case ixgbe_mac_X540:
4fa2e0e1 4331 if (num_tcs > 4) {
e5b64635
JF		 4332 if (tc < 3) {
4333 *tx = tc << 5;
4334 *rx = tc << 4;
4335 } else if (tc < 5) {
4336 *tx = ((tc + 2) << 4);
4337 *rx = tc << 4;
4338 } else if (tc < num_tcs) {
4339 *tx = ((tc + 8) << 3);
4340 *rx = tc << 4;
4341 }
4fa2e0e1 4342 } else {
e5b64635
JF		 4343 *rx = tc << 5;
4344 switch (tc) {
4345 case 0:
4346 *tx = 0;
4347 break;
4348 case 1:
4349 *tx = 64;
4350 break;
4351 case 2:
4352 *tx = 96;
4353 break;
4354 case 3:
4355 *tx = 112;
4356 break;
4357 default:
4358 break;
4359 }
4360 }
4361 break;
4362 default:
4363 break;
4364 }
4365}
4366
bc97114d
PWJ		 4367/**
4368 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4369 * @adapter: board private structure to initialize
4370 *
4371 * Cache the descriptor ring offsets for DCB to the assigned rings.
4372 *
4373 **/
4374static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4375{
e5b64635
JF		 4376 struct net_device *dev = adapter->netdev;
4377 int i, j, k;
4378 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4379
8b1c0b24 4380 if (!num_tcs)
bd508178 4381 return false;
f92ef202 4382
e5b64635
JF		 4383 for (i = 0, k = 0; i < num_tcs; i++) {
4384 unsigned int tx_s, rx_s;
4385 u16 count = dev->tc_to_txq[i].count;
4386
4387 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4388 for (j = 0; j < count; j++, k++) {
4389 adapter->tx_ring[k]->reg_idx = tx_s + j;
4390 adapter->rx_ring[k]->reg_idx = rx_s + j;
4391 adapter->tx_ring[k]->dcb_tc = i;
4392 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4393 }
021230d4 4394 }
e5b64635
JF		 4395
4396 return true;
bc97114d
PWJ		 4397}
4398#endif
4399
c4cf55e5
PWJ		 4400/**
4401 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4402 * @adapter: board private structure to initialize
4403 *
4404 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4405 *
4406 **/
e8e9f696 4407static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4408{
4409 int i;
4410 bool ret = false;
4411
03ecf91a
AD		 4412 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4413 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4414 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4415 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4416 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4417 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4418 ret = true;
4419 }
4420
4421 return ret;
4422}
4423
0331a832
YZ		 4424#ifdef IXGBE_FCOE
4425/**
4426 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4427 * @adapter: board private structure to initialize
4428 *
4429 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4430 *
4431 */
4432static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4433{
0331a832 4434 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4435 int i;
4436 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4437
4438 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4439 return false;
0331a832 4440
bf29ee6c 4441 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4442 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4443 ixgbe_cache_ring_fdir(adapter);
4444 else
4445 ixgbe_cache_ring_rss(adapter);
8faa2a78 4446
bf29ee6c
AD		 4447 fcoe_rx_i = f->mask;
4448 fcoe_tx_i = f->mask;
0331a832 4449 }
bf29ee6c
AD		 4450 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4451 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4452 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4453 }
4454 return true;
0331a832
YZ		 4455}
4456
4457#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4458/**
4459 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4460 * @adapter: board private structure to initialize
4461 *
4462 * SR-IOV doesn't use any descriptor rings but changes the default if
4463 * no other mapping is used.
4464 *
4465 */
4466static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4467{
4a0b9ca0
PW		 4468 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4469 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4470 if (adapter->num_vfs)
4471 return true;
4472 else
4473 return false;
4474}
4475
bc97114d
PWJ		 4476/**
4477 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4478 * @adapter: board private structure to initialize
4479 *
4480 * Once we know the feature-set enabled for the device, we'll cache
4481 * the register offset the descriptor ring is assigned to.
4482 *
4483 * Note, the order the various feature calls is important. It must start with
4484 * the "most" features enabled at the same time, then trickle down to the
4485 * least amount of features turned on at once.
4486 **/
4487static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4488{
4489 /* start with default case */
4a0b9ca0
PW		 4490 adapter->rx_ring[0]->reg_idx = 0;
4491 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4492
1cdd1ec8
GR		 4493 if (ixgbe_cache_ring_sriov(adapter))
4494 return;
4495
e5b64635
JF		 4496#ifdef CONFIG_IXGBE_DCB
4497 if (ixgbe_cache_ring_dcb(adapter))
4498 return;
4499#endif
4500
0331a832
YZ		 4501#ifdef IXGBE_FCOE
4502 if (ixgbe_cache_ring_fcoe(adapter))
4503 return;
0331a832 4504#endif /* IXGBE_FCOE */
bc97114d 4505
c4cf55e5
PWJ		 4506 if (ixgbe_cache_ring_fdir(adapter))
4507 return;
4508
bc97114d
PWJ		 4509 if (ixgbe_cache_ring_rss(adapter))
4510 return;
021230d4
AV		 4511}
4512
9a799d71
AK		 4513/**
4514 * ixgbe_alloc_queues - Allocate memory for all rings
4515 * @adapter: board private structure to initialize
4516 *
4517 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4518 * number of queues at compile-time. The polling_netdev array is
4519 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4520 **/
2f90b865 4521static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4522{
e2ddeba9 4523 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4524
e2ddeba9
ED		 4525 if (nid < 0 || !node_online(nid))
4526 nid = first_online_node;
4527
4528 for (; tx < adapter->num_tx_queues; tx++) {
4529 struct ixgbe_ring *ring;
4530
4531 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4532 if (!ring)
e2ddeba9 4533 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4534 if (!ring)
e2ddeba9 4535 goto err_allocation;
4a0b9ca0 4536 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4537 ring->queue_index = tx;
4538 ring->numa_node = nid;
b6ec895e 4539 ring->dev = &adapter->pdev->dev;
fc77dc3c 4540 ring->netdev = adapter->netdev;
4a0b9ca0 4541
e2ddeba9 4542 adapter->tx_ring[tx] = ring;
021230d4 4543 }
b9804972 4544
e2ddeba9
ED		 4545 for (; rx < adapter->num_rx_queues; rx++) {
4546 struct ixgbe_ring *ring;
4a0b9ca0 4547
e2ddeba9 4548 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4549 if (!ring)
e2ddeba9 4550 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4551 if (!ring)
e2ddeba9
ED		 4552 goto err_allocation;
4553 ring->count = adapter->rx_ring_count;
4554 ring->queue_index = rx;
4555 ring->numa_node = nid;
b6ec895e 4556 ring->dev = &adapter->pdev->dev;
fc77dc3c 4557 ring->netdev = adapter->netdev;
4a0b9ca0 4558
e2ddeba9 4559 adapter->rx_ring[rx] = ring;
021230d4
AV		 4560 }
4561
4562 ixgbe_cache_ring_register(adapter);
4563
4564 return 0;
4565
e2ddeba9
ED		 4566err_allocation:
4567 while (tx)
4568 kfree(adapter->tx_ring[--tx]);
4569
4570 while (rx)
4571 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4572 return -ENOMEM;
4573}
4574
4575/**
4576 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4577 * @adapter: board private structure to initialize
4578 *
4579 * Attempt to configure the interrupts using the best available
4580 * capabilities of the hardware and the kernel.
4581 **/
feea6a57 4582static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4583{
8be0e467 4584 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4585 int err = 0;
4586 int vector, v_budget;
4587
4588 /*
4589 * It's easy to be greedy for MSI-X vectors, but it really
4590 * doesn't do us much good if we have a lot more vectors
4591 * than CPU's. So let's be conservative and only ask for
342bde1b 4592 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4593 */
4594 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4595 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4596
4597 /*
4598 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4599 * hw.mac->max_msix_vectors vectors. With features
4600 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4601 * descriptor queues supported by our device. Thus, we cap it off in
4602 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4603 */
8be0e467 4604 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4605
4606 /* A failure in MSI-X entry allocation isn't fatal, but it does
4607 * mean we disable MSI-X capabilities of the adapter. */
4608 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4609 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4610 if (adapter->msix_entries) {
4611 for (vector = 0; vector < v_budget; vector++)
4612 adapter->msix_entries[vector].entry = vector;
021230d4 4613
7a921c93 4614 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4615
7a921c93
AD		 4616 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4617 goto out;
4618 }
26d27844 4619
7a921c93
AD		 4620 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4621 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4622 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4623 e_err(probe,
03ecf91a 4624 "ATR is not supported while multiple "
45b9f509
AD		 4625 "queues are disabled. Disabling Flow Director\n");
4626 }
c4cf55e5 4627 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4628 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4629 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4630 ixgbe_disable_sriov(adapter);
4631
847f53ff
BH		 4632 err = ixgbe_set_num_queues(adapter);
4633 if (err)
4634 return err;
021230d4 4635
021230d4
AV		 4636 err = pci_enable_msi(adapter->pdev);
4637 if (!err) {
4638 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4639 } else {
849c4542
ET		 4640 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4641 "Unable to allocate MSI interrupt, "
4642 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4643 /* reset err */
4644 err = 0;
4645 }
4646
4647out:
021230d4
AV		 4648 return err;
4649}
4650
7a921c93
AD		 4651/**
4652 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4653 * @adapter: board private structure to initialize
4654 *
4655 * We allocate one q_vector per queue interrupt. If allocation fails we
4656 * return -ENOMEM.
4657 **/
4658static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4659{
4ff7fb12 4660 int v_idx, num_q_vectors;
7a921c93 4661 struct ixgbe_q_vector *q_vector;
7a921c93 4662
4ff7fb12 4663 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4664 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4665 else
7a921c93 4666 num_q_vectors = 1;
7a921c93 4667
4ff7fb12 4668 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4669 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4670 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4671 if (!q_vector)
4672 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4673 GFP_KERNEL);
7a921c93
AD		 4674 if (!q_vector)
4675 goto err_out;
4ff7fb12 4676
7a921c93 4677 q_vector->adapter = adapter;
4ff7fb12
AD		 4678 q_vector->v_idx = v_idx;
4679
08c8833b 4680 if (q_vector->tx.count && !q_vector->rx.count)
f7554a2b
NS		 4681 q_vector->eitr = adapter->tx_eitr_param;
4682 else
4683 q_vector->eitr = adapter->rx_eitr_param;
4ff7fb12
AD		 4684
4685 netif_napi_add(adapter->netdev, &q_vector->napi,
4686 ixgbe_poll, 64);
4687 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4688 }
4689
4690 return 0;
4691
4692err_out:
4ff7fb12
AD		 4693 while (v_idx) {
4694 v_idx--;
4695 q_vector = adapter->q_vector[v_idx];
7a921c93
AD		 4696 netif_napi_del(&q_vector->napi);
4697 kfree(q_vector);
4ff7fb12 4698 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 4699 }
4700 return -ENOMEM;
4701}
4702
4703/**
4704 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4705 * @adapter: board private structure to initialize
4706 *
4707 * This function frees the memory allocated to the q_vectors. In addition if
4708 * NAPI is enabled it will delete any references to the NAPI struct prior
4709 * to freeing the q_vector.
4710 **/
4711static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4712{
4713 int q_idx, num_q_vectors;
7a921c93 4714
91281fd3 4715 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4716 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4717 else
7a921c93 4718 num_q_vectors = 1;
7a921c93
AD		 4719
4720 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4721 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4722 adapter->q_vector[q_idx] = NULL;
91281fd3 4723 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4724 kfree(q_vector);
4725 }
4726}
4727
7b25cdba 4728static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4729{
4730 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4731 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4732 pci_disable_msix(adapter->pdev);
4733 kfree(adapter->msix_entries);
4734 adapter->msix_entries = NULL;
4735 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4736 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4737 pci_disable_msi(adapter->pdev);
4738 }
021230d4
AV		 4739}
4740
4741/**
4742 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4743 * @adapter: board private structure to initialize
4744 *
4745 * We determine which interrupt scheme to use based on...
4746 * - Kernel support (MSI, MSI-X)
4747 * - which can be user-defined (via MODULE_PARAM)
4748 * - Hardware queue count (num_*_queues)
4749 * - defined by miscellaneous hardware support/features (RSS, etc.)
4750 **/
2f90b865 4751int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4752{
4753 int err;
4754
4755 /* Number of supported queues */
847f53ff
BH		 4756 err = ixgbe_set_num_queues(adapter);
4757 if (err)
4758 return err;
021230d4 4759
021230d4
AV		 4760 err = ixgbe_set_interrupt_capability(adapter);
4761 if (err) {
849c4542 4762 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4763 goto err_set_interrupt;
9a799d71
AK		 4764 }
4765
7a921c93
AD		 4766 err = ixgbe_alloc_q_vectors(adapter);
4767 if (err) {
849c4542 4768 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4769 goto err_alloc_q_vectors;
4770 }
4771
4772 err = ixgbe_alloc_queues(adapter);
4773 if (err) {
849c4542 4774 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4775 goto err_alloc_queues;
4776 }
4777
849c4542 4778 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4779 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4780 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4781
4782 set_bit(__IXGBE_DOWN, &adapter->state);
4783
9a799d71 4784 return 0;
021230d4 4785
7a921c93
AD		 4786err_alloc_queues:
4787 ixgbe_free_q_vectors(adapter);
4788err_alloc_q_vectors:
4789 ixgbe_reset_interrupt_capability(adapter);
021230d4 4790err_set_interrupt:
7a921c93
AD		 4791 return err;
4792}
4793
4794/**
4795 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4796 * @adapter: board private structure to clear interrupt scheme on
4797 *
4798 * We go through and clear interrupt specific resources and reset the structure
4799 * to pre-load conditions
4800 **/
4801void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4802{
4a0b9ca0
PW		 4803 int i;
4804
4805 for (i = 0; i < adapter->num_tx_queues; i++) {
4806 kfree(adapter->tx_ring[i]);
4807 adapter->tx_ring[i] = NULL;
4808 }
4809 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4810 struct ixgbe_ring *ring = adapter->rx_ring[i];
4811
4812 /* ixgbe_get_stats64() might access this ring, we must wait
4813 * a grace period before freeing it.
4814 */
bcec8b65 4815 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4816 adapter->rx_ring[i] = NULL;
4817 }
7a921c93 4818
b8eb3a10
DS		 4819 adapter->num_tx_queues = 0;
4820 adapter->num_rx_queues = 0;
4821
7a921c93
AD		 4822 ixgbe_free_q_vectors(adapter);
4823 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4824}
4825
4826/**
4827 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4828 * @adapter: board private structure to initialize
4829 *
4830 * ixgbe_sw_init initializes the Adapter private data structure.
4831 * Fields are initialized based on PCI device information and
4832 * OS network device settings (MTU size).
4833 **/
4834static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4835{
4836 struct ixgbe_hw *hw = &adapter->hw;
4837 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4838 struct net_device *dev = adapter->netdev;
021230d4 4839 unsigned int rss;
7a6b6f51 4840#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4841 int j;
4842 struct tc_configuration *tc;
4843#endif
16b61beb 4844 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 4845
c44ade9e
JB		 4846 /* PCI config space info */
4847
4848 hw->vendor_id = pdev->vendor;
4849 hw->device_id = pdev->device;
4850 hw->revision_id = pdev->revision;
4851 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4852 hw->subsystem_device_id = pdev->subsystem_device;
4853
021230d4
AV		 4854 /* Set capability flags */
4855 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4856 adapter->ring_feature[RING_F_RSS].indices = rss;
4857 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4858 switch (hw->mac.type) {
4859 case ixgbe_mac_82598EB:
bf069c97
DS		 4860 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4861 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4862 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 4863 break;
4864 case ixgbe_mac_82599EB:
b93a2226 4865 case ixgbe_mac_X540:
e8e26350 4866 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4867 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4868 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4869 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4870 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4871 /* Flow Director hash filters enabled */
4872 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4873 adapter->atr_sample_rate = 20;
c4cf55e5 4874 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4875 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4876 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4877#ifdef IXGBE_FCOE
0d551589
YZ		 4878 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4879 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4880 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4881#ifdef CONFIG_IXGBE_DCB
6ee16520 4882 /* Default traffic class to use for FCoE */
56075a98 4883 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4884#endif
eacd73f7 4885#endif /* IXGBE_FCOE */
bd508178
AD		 4886 break;
4887 default:
4888 break;
f8212f97 4889 }
2f90b865 4890
1fc5f038
AD		 4891 /* n-tuple support exists, always init our spinlock */
4892 spin_lock_init(&adapter->fdir_perfect_lock);
4893
7a6b6f51 4894#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4895 /* Configure DCB traffic classes */
4896 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4897 tc = &adapter->dcb_cfg.tc_config[j];
4898 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4899 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4900 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4901 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4902 tc->dcb_pfc = pfc_disabled;
4903 }
4904 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4905 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4906 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4907 adapter->dcb_set_bitmap = 0x00;
3032309b 4908 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 4909 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 4910 MAX_TRAFFIC_CLASS);
2f90b865
AD		 4911
4912#endif
9a799d71
AK		 4913
4914 /* default flow control settings */
cd7664f6 4915 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4916 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 4917#ifdef CONFIG_DCB
4918 adapter->last_lfc_mode = hw->fc.current_mode;
4919#endif
16b61beb
JF		 4920 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4921 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 4922 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4923 hw->fc.send_xon = true;
71fd570b 4924 hw->fc.disable_fc_autoneg = false;
9a799d71 4925
30efa5a3 4926 /* enable itr by default in dynamic mode */
f7554a2b
NS		 4927 adapter->rx_itr_setting = 1;
4928 adapter->rx_eitr_param = 20000;
4929 adapter->tx_itr_setting = 1;
4930 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 4931
4932 /* set defaults for eitr in MegaBytes */
4933 adapter->eitr_low = 10;
4934 adapter->eitr_high = 20;
4935
4936 /* set default ring sizes */
4937 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4938 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4939
bd198058 4940 /* set default work limits */
59224555 4941 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4942
9a799d71 4943 /* initialize eeprom parameters */
c44ade9e 4944 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4945 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4946 return -EIO;
4947 }
4948
021230d4 4949 /* enable rx csum by default */
9a799d71
AK		 4950 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4951
1a6c14a2
JB		 4952 /* get assigned NUMA node */
4953 adapter->node = dev_to_node(&pdev->dev);
4954
9a799d71
AK		 4955 set_bit(__IXGBE_DOWN, &adapter->state);
4956
4957 return 0;
4958}
4959
4960/**
4961 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4962 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4963 *
4964 * Return 0 on success, negative on failure
4965 **/
b6ec895e 4966int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4967{
b6ec895e 4968 struct device *dev = tx_ring->dev;
9a799d71
AK		 4969 int size;
4970
3a581073 4971 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 4972 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 4973 if (!tx_ring->tx_buffer_info)
89bf67f1 4974 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4975 if (!tx_ring->tx_buffer_info)
4976 goto err;
9a799d71
AK		 4977
4978 /* round up to nearest 4K */
12207e49 4979 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4980 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4981
b6ec895e 4982 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 4983 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4984 if (!tx_ring->desc)
4985 goto err;
9a799d71 4986
3a581073
JB		 4987 tx_ring->next_to_use = 0;
4988 tx_ring->next_to_clean = 0;
9a799d71 4989 return 0;
e01c31a5
JB		 4990
4991err:
4992 vfree(tx_ring->tx_buffer_info);
4993 tx_ring->tx_buffer_info = NULL;
b6ec895e 4994 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4995 return -ENOMEM;
9a799d71
AK		 4996}
4997
69888674
AD		 4998/**
4999 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5000 * @adapter: board private structure
5001 *
5002 * If this function returns with an error, then it's possible one or
5003 * more of the rings is populated (while the rest are not). It is the
5004 * callers duty to clean those orphaned rings.
5005 *
5006 * Return 0 on success, negative on failure
5007 **/
5008static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5009{
5010 int i, err = 0;
5011
5012 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5013 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5014 if (!err)
5015 continue;
396e799c 5016 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5017 break;
5018 }
5019
5020 return err;
5021}
5022
9a799d71
AK		 5023/**
5024 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5025 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5026 *
5027 * Returns 0 on success, negative on failure
5028 **/
b6ec895e 5029int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5030{
b6ec895e 5031 struct device *dev = rx_ring->dev;
021230d4 5032 int size;
9a799d71 5033
3a581073 5034 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5035 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5036 if (!rx_ring->rx_buffer_info)
89bf67f1 5037 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5038 if (!rx_ring->rx_buffer_info)
5039 goto err;
9a799d71 5040
9a799d71 5041 /* Round up to nearest 4K */
3a581073
JB		 5042 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5043 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5044
b6ec895e 5045 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5046 &rx_ring->dma, GFP_KERNEL);
9a799d71 5047
b6ec895e
AD		 5048 if (!rx_ring->desc)
5049 goto err;
9a799d71 5050
3a581073
JB		 5051 rx_ring->next_to_clean = 0;
5052 rx_ring->next_to_use = 0;
9a799d71
AK		 5053
5054 return 0;
b6ec895e
AD		 5055err:
5056 vfree(rx_ring->rx_buffer_info);
5057 rx_ring->rx_buffer_info = NULL;
5058 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5059 return -ENOMEM;
9a799d71
AK		 5060}
5061
69888674
AD		 5062/**
5063 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5064 * @adapter: board private structure
5065 *
5066 * If this function returns with an error, then it's possible one or
5067 * more of the rings is populated (while the rest are not). It is the
5068 * callers duty to clean those orphaned rings.
5069 *
5070 * Return 0 on success, negative on failure
5071 **/
69888674
AD		 5072static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5073{
5074 int i, err = 0;
5075
5076 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5077 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5078 if (!err)
5079 continue;
396e799c 5080 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5081 break;
5082 }
5083
5084 return err;
5085}
5086
9a799d71
AK		 5087/**
5088 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5089 * @tx_ring: Tx descriptor ring for a specific queue
5090 *
5091 * Free all transmit software resources
5092 **/
b6ec895e 5093void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5094{
b6ec895e 5095 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5096
5097 vfree(tx_ring->tx_buffer_info);
5098 tx_ring->tx_buffer_info = NULL;
5099
b6ec895e
AD		 5100 /* if not set, then don't free */
5101 if (!tx_ring->desc)
5102 return;
5103
5104 dma_free_coherent(tx_ring->dev, tx_ring->size,
5105 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5106
5107 tx_ring->desc = NULL;
5108}
5109
5110/**
5111 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5112 * @adapter: board private structure
5113 *
5114 * Free all transmit software resources
5115 **/
5116static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5117{
5118 int i;
5119
5120 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5121 if (adapter->tx_ring[i]->desc)
b6ec895e 5122 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5123}
5124
5125/**
b4617240 5126 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5127 * @rx_ring: ring to clean the resources from
5128 *
5129 * Free all receive software resources
5130 **/
b6ec895e 5131void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5132{
b6ec895e 5133 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5134
5135 vfree(rx_ring->rx_buffer_info);
5136 rx_ring->rx_buffer_info = NULL;
5137
b6ec895e
AD		 5138 /* if not set, then don't free */
5139 if (!rx_ring->desc)
5140 return;
5141
5142 dma_free_coherent(rx_ring->dev, rx_ring->size,
5143 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5144
5145 rx_ring->desc = NULL;
5146}
5147
5148/**
5149 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5150 * @adapter: board private structure
5151 *
5152 * Free all receive software resources
5153 **/
5154static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5155{
5156 int i;
5157
5158 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5159 if (adapter->rx_ring[i]->desc)
b6ec895e 5160 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5161}
5162
9a799d71
AK		 5163/**
5164 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5165 * @netdev: network interface device structure
5166 * @new_mtu: new value for maximum frame size
5167 *
5168 * Returns 0 on success, negative on failure
5169 **/
5170static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5171{
5172 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5173 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5174 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5175
42c783c5 5176 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5177 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5178 hw->mac.type != ixgbe_mac_X540) {
5179 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5180 return -EINVAL;
5181 } else {
5182 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5183 return -EINVAL;
5184 }
9a799d71 5185
396e799c 5186 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5187 /* must set new MTU before calling down or up */
9a799d71
AK		 5188 netdev->mtu = new_mtu;
5189
16b61beb
JF		 5190 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5191 hw->fc.low_water = FC_LOW_WATER(max_frame);
5192
d4f80882
AV		 5193 if (netif_running(netdev))
5194 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5195
5196 return 0;
5197}
5198
5199/**
5200 * ixgbe_open - Called when a network interface is made active
5201 * @netdev: network interface device structure
5202 *
5203 * Returns 0 on success, negative value on failure
5204 *
5205 * The open entry point is called when a network interface is made
5206 * active by the system (IFF_UP). At this point all resources needed
5207 * for transmit and receive operations are allocated, the interrupt
5208 * handler is registered with the OS, the watchdog timer is started,
5209 * and the stack is notified that the interface is ready.
5210 **/
5211static int ixgbe_open(struct net_device *netdev)
5212{
5213 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5214 int err;
4bebfaa5
AK		 5215
5216 /* disallow open during test */
5217 if (test_bit(__IXGBE_TESTING, &adapter->state))
5218 return -EBUSY;
9a799d71 5219
54386467
JB		 5220 netif_carrier_off(netdev);
5221
9a799d71
AK		 5222 /* allocate transmit descriptors */
5223 err = ixgbe_setup_all_tx_resources(adapter);
5224 if (err)
5225 goto err_setup_tx;
5226
9a799d71
AK		 5227 /* allocate receive descriptors */
5228 err = ixgbe_setup_all_rx_resources(adapter);
5229 if (err)
5230 goto err_setup_rx;
5231
5232 ixgbe_configure(adapter);
5233
021230d4 5234 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5235 if (err)
5236 goto err_req_irq;
5237
9a799d71
AK		 5238 err = ixgbe_up_complete(adapter);
5239 if (err)
5240 goto err_up;
5241
d55b53ff
JK		 5242 netif_tx_start_all_queues(netdev);
5243
9a799d71
AK		 5244 return 0;
5245
5246err_up:
5eba3699 5247 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5248 ixgbe_free_irq(adapter);
5249err_req_irq:
9a799d71 5250err_setup_rx:
a20a1199 5251 ixgbe_free_all_rx_resources(adapter);
9a799d71 5252err_setup_tx:
a20a1199 5253 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5254 ixgbe_reset(adapter);
5255
5256 return err;
5257}
5258
5259/**
5260 * ixgbe_close - Disables a network interface
5261 * @netdev: network interface device structure
5262 *
5263 * Returns 0, this is not allowed to fail
5264 *
5265 * The close entry point is called when an interface is de-activated
5266 * by the OS. The hardware is still under the drivers control, but
5267 * needs to be disabled. A global MAC reset is issued to stop the
5268 * hardware, and all transmit and receive resources are freed.
5269 **/
5270static int ixgbe_close(struct net_device *netdev)
5271{
5272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5273
5274 ixgbe_down(adapter);
5275 ixgbe_free_irq(adapter);
5276
e4911d57
AD		 5277 ixgbe_fdir_filter_exit(adapter);
5278
9a799d71
AK		 5279 ixgbe_free_all_tx_resources(adapter);
5280 ixgbe_free_all_rx_resources(adapter);
5281
5eba3699 5282 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5283
5284 return 0;
5285}
5286
b3c8b4ba
AD		 5287#ifdef CONFIG_PM
5288static int ixgbe_resume(struct pci_dev *pdev)
5289{
c60fbb00
AD		 5290 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5291 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5292 u32 err;
5293
5294 pci_set_power_state(pdev, PCI_D0);
5295 pci_restore_state(pdev);
656ab817
DS		 5296 /*
5297 * pci_restore_state clears dev->state_saved so call
5298 * pci_save_state to restore it.
5299 */
5300 pci_save_state(pdev);
9ce77666 5301
5302 err = pci_enable_device_mem(pdev);
b3c8b4ba 5303 if (err) {
849c4542 5304 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5305 return err;
5306 }
5307 pci_set_master(pdev);
5308
dd4d8ca6 5309 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5310
5311 err = ixgbe_init_interrupt_scheme(adapter);
5312 if (err) {
849c4542 5313 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5314 return err;
5315 }
5316
b3c8b4ba
AD		 5317 ixgbe_reset(adapter);
5318
495dce12
WJP		 5319 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5320
b3c8b4ba 5321 if (netif_running(netdev)) {
c60fbb00 5322 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5323 if (err)
5324 return err;
5325 }
5326
5327 netif_device_attach(netdev);
5328
5329 return 0;
5330}
b3c8b4ba 5331#endif /* CONFIG_PM */
9d8d05ae
RW		 5332
5333static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5334{
c60fbb00
AD		 5335 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5336 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5337 struct ixgbe_hw *hw = &adapter->hw;
5338 u32 ctrl, fctrl;
5339 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5340#ifdef CONFIG_PM
5341 int retval = 0;
5342#endif
5343
5344 netif_device_detach(netdev);
5345
5346 if (netif_running(netdev)) {
5347 ixgbe_down(adapter);
5348 ixgbe_free_irq(adapter);
5349 ixgbe_free_all_tx_resources(adapter);
5350 ixgbe_free_all_rx_resources(adapter);
5351 }
b3c8b4ba 5352
5f5ae6fc 5353 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5354#ifdef CONFIG_DCB
5355 kfree(adapter->ixgbe_ieee_pfc);
5356 kfree(adapter->ixgbe_ieee_ets);
5357#endif
5f5ae6fc 5358
b3c8b4ba
AD		 5359#ifdef CONFIG_PM
5360 retval = pci_save_state(pdev);
5361 if (retval)
5362 return retval;
4df10466 5363
b3c8b4ba 5364#endif
e8e26350
PW		 5365 if (wufc) {
5366 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5367
e8e26350
PW		 5368 /* turn on all-multi mode if wake on multicast is enabled */
5369 if (wufc & IXGBE_WUFC_MC) {
5370 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5371 fctrl |= IXGBE_FCTRL_MPE;
5372 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5373 }
5374
5375 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5376 ctrl |= IXGBE_CTRL_GIO_DIS;
5377 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5378
5379 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5380 } else {
5381 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5382 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5383 }
5384
bd508178
AD		 5385 switch (hw->mac.type) {
5386 case ixgbe_mac_82598EB:
dd4d8ca6 5387 pci_wake_from_d3(pdev, false);
bd508178
AD		 5388 break;
5389 case ixgbe_mac_82599EB:
b93a2226 5390 case ixgbe_mac_X540:
bd508178
AD		 5391 pci_wake_from_d3(pdev, !!wufc);
5392 break;
5393 default:
5394 break;
5395 }
b3c8b4ba 5396
9d8d05ae
RW		 5397 *enable_wake = !!wufc;
5398
b3c8b4ba
AD		 5399 ixgbe_release_hw_control(adapter);
5400
5401 pci_disable_device(pdev);
5402
9d8d05ae
RW		 5403 return 0;
5404}
5405
5406#ifdef CONFIG_PM
5407static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5408{
5409 int retval;
5410 bool wake;
5411
5412 retval = __ixgbe_shutdown(pdev, &wake);
5413 if (retval)
5414 return retval;
5415
5416 if (wake) {
5417 pci_prepare_to_sleep(pdev);
5418 } else {
5419 pci_wake_from_d3(pdev, false);
5420 pci_set_power_state(pdev, PCI_D3hot);
5421 }
b3c8b4ba
AD		 5422
5423 return 0;
5424}
9d8d05ae 5425#endif /* CONFIG_PM */
b3c8b4ba
AD		 5426
5427static void ixgbe_shutdown(struct pci_dev *pdev)
5428{
9d8d05ae
RW		 5429 bool wake;
5430
5431 __ixgbe_shutdown(pdev, &wake);
5432
5433 if (system_state == SYSTEM_POWER_OFF) {
5434 pci_wake_from_d3(pdev, wake);
5435 pci_set_power_state(pdev, PCI_D3hot);
5436 }
b3c8b4ba
AD		 5437}
5438
9a799d71
AK		 5439/**
5440 * ixgbe_update_stats - Update the board statistics counters.
5441 * @adapter: board private structure
5442 **/
5443void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5444{
2d86f139 5445 struct net_device *netdev = adapter->netdev;
9a799d71 5446 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5447 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5448 u64 total_mpc = 0;
5449 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5450 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5451 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5452 u64 bytes = 0, packets = 0;
9a799d71 5453
d08935c2
DS		 5454 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5455 test_bit(__IXGBE_RESETTING, &adapter->state))
5456 return;
5457
94b982b2 5458 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5459 u64 rsc_count = 0;
94b982b2 5460 u64 rsc_flush = 0;
d51019a4
PW		 5461 for (i = 0; i < 16; i++)
5462 adapter->hw_rx_no_dma_resources +=
7ca647bd 5463 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5464 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5465 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5466 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5467 }
5468 adapter->rsc_total_count = rsc_count;
5469 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5470 }
5471
5b7da515
AD		 5472 for (i = 0; i < adapter->num_rx_queues; i++) {
5473 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5474 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5475 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5476 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5477 bytes += rx_ring->stats.bytes;
5478 packets += rx_ring->stats.packets;
5479 }
5480 adapter->non_eop_descs = non_eop_descs;
5481 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5482 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5483 netdev->stats.rx_bytes = bytes;
5484 netdev->stats.rx_packets = packets;
5485
5486 bytes = 0;
5487 packets = 0;
7ca3bc58 5488 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5489 for (i = 0; i < adapter->num_tx_queues; i++) {
5490 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5491 restart_queue += tx_ring->tx_stats.restart_queue;
5492 tx_busy += tx_ring->tx_stats.tx_busy;
5493 bytes += tx_ring->stats.bytes;
5494 packets += tx_ring->stats.packets;
5495 }
eb985f09 5496 adapter->restart_queue = restart_queue;
5b7da515
AD		 5497 adapter->tx_busy = tx_busy;
5498 netdev->stats.tx_bytes = bytes;
5499 netdev->stats.tx_packets = packets;
7ca3bc58 5500
7ca647bd 5501 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5502 for (i = 0; i < 8; i++) {
5503 /* for packet buffers not used, the register should read 0 */
5504 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5505 missed_rx += mpc;
7ca647bd
JP		 5506 hwstats->mpc[i] += mpc;
5507 total_mpc += hwstats->mpc[i];
e8e26350 5508 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5509 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5510 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5511 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5512 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5513 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5514 switch (hw->mac.type) {
5515 case ixgbe_mac_82598EB:
7ca647bd
JP		 5516 hwstats->pxonrxc[i] +=
5517 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5518 break;
5519 case ixgbe_mac_82599EB:
b93a2226 5520 case ixgbe_mac_X540:
bd508178
AD		 5521 hwstats->pxonrxc[i] +=
5522 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5523 break;
5524 default:
5525 break;
e8e26350 5526 }
7ca647bd
JP		 5527 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5528 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5529 }
7ca647bd 5530 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5531 /* work around hardware counting issue */
7ca647bd 5532 hwstats->gprc -= missed_rx;
6f11eef7 5533
c84d324c
JF		 5534 ixgbe_update_xoff_received(adapter);
5535
6f11eef7 5536 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5537 switch (hw->mac.type) {
5538 case ixgbe_mac_82598EB:
5539 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5540 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5541 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5542 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5543 break;
b93a2226 5544 case ixgbe_mac_X540:
58f6bcf9
ET		 5545 /* OS2BMC stats are X540 only*/
5546 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5547 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5548 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5549 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5550 case ixgbe_mac_82599EB:
7ca647bd 5551 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5552 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5553 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5554 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5555 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5556 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5557 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5558 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5559 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5560#ifdef IXGBE_FCOE
7ca647bd
JP		 5561 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5562 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5563 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5564 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5565 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5566 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5567#endif /* IXGBE_FCOE */
bd508178
AD		 5568 break;
5569 default:
5570 break;
e8e26350 5571 }
9a799d71 5572 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5573 hwstats->bprc += bprc;
5574 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5575 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5576 hwstats->mprc -= bprc;
5577 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5578 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5579 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5580 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5581 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5582 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5583 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5584 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5585 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5586 hwstats->lxontxc += lxon;
6f11eef7 5587 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5588 hwstats->lxofftxc += lxoff;
5589 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5590 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5591 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5592 /*
5593 * 82598 errata - tx of flow control packets is included in tx counters
5594 */
5595 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5596 hwstats->gptc -= xon_off_tot;
5597 hwstats->mptc -= xon_off_tot;
5598 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5599 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5600 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5601 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5602 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5603 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5604 hwstats->ptc64 -= xon_off_tot;
5605 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5606 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5607 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5608 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5609 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5610 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5611
5612 /* Fill out the OS statistics structure */
7ca647bd 5613 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5614
5615 /* Rx Errors */
7ca647bd 5616 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5617 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5618 netdev->stats.rx_length_errors = hwstats->rlec;
5619 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5620 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5621}
5622
5623/**
d034acf1
AD		 5624 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5625 * @adapter - pointer to the device adapter structure
9a799d71 5626 **/
d034acf1 5627static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5628{
cf8280ee 5629 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5630 int i;
cf8280ee 5631
d034acf1
AD		 5632 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5633 return;
5634
5635 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5636
d034acf1 5637 /* if interface is down do nothing */
fe49f04a 5638 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5639 return;
5640
5641 /* do nothing if we are not using signature filters */
5642 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5643 return;
5644
5645 adapter->fdir_overflow++;
5646
93c52dd0
AD		 5647 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5648 for (i = 0; i < adapter->num_tx_queues; i++)
5649 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5650 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5651 /* re-enable flow director interrupts */
5652 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5653 } else {
5654 e_err(probe, "failed to finish FDIR re-initialization, "
5655 "ignored adding FDIR ATR filters\n");
5656 }
93c52dd0
AD		 5657}
5658
5659/**
5660 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5661 * @adapter - pointer to the device adapter structure
5662 *
5663 * This function serves two purposes. First it strobes the interrupt lines
5664 * in order to make certain interrupts are occuring. Secondly it sets the
5665 * bits needed to check for TX hangs. As a result we should immediately
5666 * determine if a hang has occured.
5667 */
5668static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5669{
cf8280ee 5670 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5671 u64 eics = 0;
5672 int i;
cf8280ee 5673
93c52dd0
AD		 5674 /* If we're down or resetting, just bail */
5675 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5676 test_bit(__IXGBE_RESETTING, &adapter->state))
5677 return;
22d5a71b 5678
93c52dd0
AD		 5679 /* Force detection of hung controller */
5680 if (netif_carrier_ok(adapter->netdev)) {
5681 for (i = 0; i < adapter->num_tx_queues; i++)
5682 set_check_for_tx_hang(adapter->tx_ring[i]);
5683 }
22d5a71b 5684
fe49f04a
AD		 5685 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5686 /*
5687 * for legacy and MSI interrupts don't set any bits
5688 * that are enabled for EIAM, because this operation
5689 * would set *both* EIMS and EICS for any bit in EIAM
5690 */
5691 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5692 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5693 } else {
5694 /* get one bit for every active tx/rx interrupt vector */
5695 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5696 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5697 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5698 eics |= ((u64)1 << i);
5699 }
cf8280ee 5700 }
9a799d71 5701
93c52dd0 5702 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5703 ixgbe_irq_rearm_queues(adapter, eics);
5704
cf8280ee
JB		 5705}
5706
e8e26350 5707/**
93c52dd0
AD		 5708 * ixgbe_watchdog_update_link - update the link status
5709 * @adapter - pointer to the device adapter structure
5710 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5711 **/
93c52dd0 5712static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5713{
e8e26350 5714 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5715 u32 link_speed = adapter->link_speed;
5716 bool link_up = adapter->link_up;
c4cf55e5 5717 int i;
e8e26350 5718
93c52dd0
AD		 5719 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5720 return;
5721
5722 if (hw->mac.ops.check_link) {
5723 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5724 } else {
93c52dd0
AD		 5725 /* always assume link is up, if no check link function */
5726 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5727 link_up = true;
c4cf55e5 5728 }
93c52dd0
AD		 5729 if (link_up) {
5730 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5731 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5732 hw->mac.ops.fc_enable(hw, i);
5733 } else {
5734 hw->mac.ops.fc_enable(hw, 0);
5735 }
5736 }
5737
5738 if (link_up ||
5739 time_after(jiffies, (adapter->link_check_timeout +
5740 IXGBE_TRY_LINK_TIMEOUT))) {
5741 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5742 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5743 IXGBE_WRITE_FLUSH(hw);
5744 }
5745
5746 adapter->link_up = link_up;
5747 adapter->link_speed = link_speed;
e8e26350
PW		 5748}
5749
5750/**
93c52dd0
AD		 5751 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5752 * print link up message
5753 * @adapter - pointer to the device adapter structure
e8e26350 5754 **/
93c52dd0 5755static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5756{
93c52dd0 5757 struct net_device *netdev = adapter->netdev;
e8e26350 5758 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5759 u32 link_speed = adapter->link_speed;
5760 bool flow_rx, flow_tx;
e8e26350 5761
93c52dd0
AD		 5762 /* only continue if link was previously down */
5763 if (netif_carrier_ok(netdev))
a985b6c3 5764 return;
63d6e1d8 5765
93c52dd0 5766 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5767
93c52dd0
AD		 5768 switch (hw->mac.type) {
5769 case ixgbe_mac_82598EB: {
5770 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5771 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5772 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5773 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5774 }
5775 break;
5776 case ixgbe_mac_X540:
5777 case ixgbe_mac_82599EB: {
5778 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5779 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5780 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5781 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5782 }
5783 break;
5784 default:
5785 flow_tx = false;
5786 flow_rx = false;
5787 break;
e8e26350 5788 }
93c52dd0
AD		 5789 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5790 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5791 "10 Gbps" :
5792 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5793 "1 Gbps" :
5794 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5795 "100 Mbps" :
5796 "unknown speed"))),
5797 ((flow_rx && flow_tx) ? "RX/TX" :
5798 (flow_rx ? "RX" :
5799 (flow_tx ? "TX" : "None"))));
e8e26350 5800
93c52dd0 5801 netif_carrier_on(netdev);
93c52dd0 5802 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5803}
5804
c4cf55e5 5805/**
93c52dd0
AD		 5806 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5807 * print link down message
5808 * @adapter - pointer to the adapter structure
c4cf55e5 5809 **/
93c52dd0 5810static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5811{
cf8280ee 5812 struct net_device *netdev = adapter->netdev;
c4cf55e5 5813 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5814
93c52dd0
AD		 5815 adapter->link_up = false;
5816 adapter->link_speed = 0;
cf8280ee 5817
93c52dd0
AD		 5818 /* only continue if link was up previously */
5819 if (!netif_carrier_ok(netdev))
5820 return;
264857b8 5821
93c52dd0
AD		 5822 /* poll for SFP+ cable when link is down */
5823 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5824 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5825
93c52dd0
AD		 5826 e_info(drv, "NIC Link is Down\n");
5827 netif_carrier_off(netdev);
5828}
e8e26350 5829
93c52dd0
AD		 5830/**
5831 * ixgbe_watchdog_flush_tx - flush queues on link down
5832 * @adapter - pointer to the device adapter structure
5833 **/
5834static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5835{
c4cf55e5 5836 int i;
93c52dd0 5837 int some_tx_pending = 0;
c4cf55e5 5838
93c52dd0 5839 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5840 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5841 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5842 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5843 some_tx_pending = 1;
5844 break;
5845 }
5846 }
5847
5848 if (some_tx_pending) {
5849 /* We've lost link, so the controller stops DMA,
5850 * but we've got queued Tx work that's never going
5851 * to get done, so reset controller to flush Tx.
5852 * (Do the reset outside of interrupt context).
5853 */
c83c6cbd 5854 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5855 }
c4cf55e5 5856 }
c4cf55e5
PWJ		 5857}
5858
a985b6c3
GR		 5859static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5860{
5861 u32 ssvpc;
5862
5863 /* Do not perform spoof check for 82598 */
5864 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5865 return;
5866
5867 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5868
5869 /*
5870 * ssvpc register is cleared on read, if zero then no
5871 * spoofed packets in the last interval.
5872 */
5873 if (!ssvpc)
5874 return;
5875
5876 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5877}
5878
93c52dd0
AD		 5879/**
5880 * ixgbe_watchdog_subtask - check and bring link up
5881 * @adapter - pointer to the device adapter structure
5882 **/
5883static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5884{
5885 /* if interface is down do nothing */
5886 if (test_bit(__IXGBE_DOWN, &adapter->state))
5887 return;
5888
5889 ixgbe_watchdog_update_link(adapter);
5890
5891 if (adapter->link_up)
5892 ixgbe_watchdog_link_is_up(adapter);
5893 else
5894 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5895
a985b6c3 5896 ixgbe_spoof_check(adapter);
9a799d71 5897 ixgbe_update_stats(adapter);
93c52dd0
AD		 5898
5899 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5900}
10eec955 5901
cf8280ee 5902/**
7086400d
AD		 5903 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5904 * @adapter - the ixgbe adapter structure
cf8280ee 5905 **/
7086400d 5906static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5907{
cf8280ee 5908 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5909 s32 err;
cf8280ee 5910
7086400d
AD		 5911 /* not searching for SFP so there is nothing to do here */
5912 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5913 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5914 return;
10eec955 5915
7086400d
AD		 5916 /* someone else is in init, wait until next service event */
5917 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5918 return;
cf8280ee 5919
7086400d
AD		 5920 err = hw->phy.ops.identify_sfp(hw);
5921 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5922 goto sfp_out;
264857b8 5923
7086400d
AD		 5924 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5925 /* If no cable is present, then we need to reset
5926 * the next time we find a good cable. */
5927 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5928 }
9a799d71 5929
7086400d
AD		 5930 /* exit on error */
5931 if (err)
5932 goto sfp_out;
e8e26350 5933
7086400d
AD		 5934 /* exit if reset not needed */
5935 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5936 goto sfp_out;
9a799d71 5937
7086400d 5938 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5939
7086400d
AD		 5940 /*
5941 * A module may be identified correctly, but the EEPROM may not have
5942 * support for that module. setup_sfp() will fail in that case, so
5943 * we should not allow that module to load.
5944 */
5945 if (hw->mac.type == ixgbe_mac_82598EB)
5946 err = hw->phy.ops.reset(hw);
5947 else
5948 err = hw->mac.ops.setup_sfp(hw);
5949
5950 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5951 goto sfp_out;
5952
5953 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5954 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5955
5956sfp_out:
5957 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5958
5959 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5960 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5961 e_dev_err("failed to initialize because an unsupported "
5962 "SFP+ module type was detected.\n");
5963 e_dev_err("Reload the driver after installing a "
5964 "supported module.\n");
5965 unregister_netdev(adapter->netdev);
bc59fcda 5966 }
7086400d 5967}
bc59fcda 5968
7086400d
AD		 5969/**
5970 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5971 * @adapter - the ixgbe adapter structure
5972 **/
5973static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5974{
5975 struct ixgbe_hw *hw = &adapter->hw;
5976 u32 autoneg;
5977 bool negotiation;
5978
5979 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5980 return;
5981
5982 /* someone else is in init, wait until next service event */
5983 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5984 return;
5985
5986 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5987
5988 autoneg = hw->phy.autoneg_advertised;
5989 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5990 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5991 hw->mac.autotry_restart = false;
5992 if (hw->mac.ops.setup_link)
5993 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5994
5995 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5996 adapter->link_check_timeout = jiffies;
5997 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5998}
5999
6000/**
6001 * ixgbe_service_timer - Timer Call-back
6002 * @data: pointer to adapter cast into an unsigned long
6003 **/
6004static void ixgbe_service_timer(unsigned long data)
6005{
6006 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6007 unsigned long next_event_offset;
6008
6009 /* poll faster when waiting for link */
6010 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6011 next_event_offset = HZ / 10;
6012 else
6013 next_event_offset = HZ * 2;
6014
6015 /* Reset the timer */
6016 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6017
6018 ixgbe_service_event_schedule(adapter);
6019}
6020
c83c6cbd
AD		 6021static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6022{
6023 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6024 return;
6025
6026 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6027
6028 /* If we're already down or resetting, just bail */
6029 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6030 test_bit(__IXGBE_RESETTING, &adapter->state))
6031 return;
6032
6033 ixgbe_dump(adapter);
6034 netdev_err(adapter->netdev, "Reset adapter\n");
6035 adapter->tx_timeout_count++;
6036
6037 ixgbe_reinit_locked(adapter);
6038}
6039
7086400d
AD		 6040/**
6041 * ixgbe_service_task - manages and runs subtasks
6042 * @work: pointer to work_struct containing our data
6043 **/
6044static void ixgbe_service_task(struct work_struct *work)
6045{
6046 struct ixgbe_adapter *adapter = container_of(work,
6047 struct ixgbe_adapter,
6048 service_task);
6049
c83c6cbd 6050 ixgbe_reset_subtask(adapter);
7086400d
AD		 6051 ixgbe_sfp_detection_subtask(adapter);
6052 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6053 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6054 ixgbe_watchdog_subtask(adapter);
d034acf1 6055 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6056 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6057
6058 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6059}
6060
897ab156
AD		 6061void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6062 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6063{
6064 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6065 u16 i = tx_ring->next_to_use;
9a799d71 6066
897ab156 6067 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6068
897ab156
AD		 6069 i++;
6070 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6071
897ab156
AD		 6072 /* set bits to identify this as an advanced context descriptor */
6073 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6074
897ab156
AD		 6075 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6076 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6077 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6078 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6079}
9a799d71 6080
897ab156
AD		 6081static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6082 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6083{
6084 int err;
6085 u32 vlan_macip_lens, type_tucmd;
6086 u32 mss_l4len_idx, l4len;
9a799d71 6087
897ab156
AD		 6088 if (!skb_is_gso(skb))
6089 return 0;
9a799d71 6090
897ab156
AD		 6091 if (skb_header_cloned(skb)) {
6092 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6093 if (err)
6094 return err;
9a799d71 6095 }
9a799d71 6096
897ab156
AD		 6097 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6098 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6099
6100 if (protocol == __constant_htons(ETH_P_IP)) {
6101 struct iphdr *iph = ip_hdr(skb);
6102 iph->tot_len = 0;
6103 iph->check = 0;
6104 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6105 iph->daddr, 0,
6106 IPPROTO_TCP,
6107 0);
6108 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6109 } else if (skb_is_gso_v6(skb)) {
6110 ipv6_hdr(skb)->payload_len = 0;
6111 tcp_hdr(skb)->check =
6112 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6113 &ipv6_hdr(skb)->daddr,
6114 0, IPPROTO_TCP, 0);
6115 }
6116
6117 l4len = tcp_hdrlen(skb);
6118 *hdr_len = skb_transport_offset(skb) + l4len;
6119
6120 /* mss_l4len_id: use 1 as index for TSO */
6121 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6122 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6123 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6124
6125 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6126 vlan_macip_lens = skb_network_header_len(skb);
6127 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6128 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6129
6130 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6131 mss_l4len_idx);
6132
6133 return 1;
6134}
6135
6136static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6137 struct sk_buff *skb, u32 tx_flags,
6138 __be16 protocol)
7ca647bd 6139{
897ab156
AD		 6140 u32 vlan_macip_lens = 0;
6141 u32 mss_l4len_idx = 0;
6142 u32 type_tucmd = 0;
7ca647bd 6143
897ab156 6144 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6145 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6146 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6147 return false;
6148 } else {
6149 u8 l4_hdr = 0;
6150 switch (protocol) {
6151 case __constant_htons(ETH_P_IP):
6152 vlan_macip_lens |= skb_network_header_len(skb);
6153 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6154 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6155 break;
897ab156
AD		 6156 case __constant_htons(ETH_P_IPV6):
6157 vlan_macip_lens |= skb_network_header_len(skb);
6158 l4_hdr = ipv6_hdr(skb)->nexthdr;
6159 break;
6160 default:
6161 if (unlikely(net_ratelimit())) {
6162 dev_warn(tx_ring->dev,
6163 "partial checksum but proto=%x!\n",
6164 skb->protocol);
6165 }
7ca647bd
JP		 6166 break;
6167 }
897ab156
AD		 6168
6169 switch (l4_hdr) {
7ca647bd 6170 case IPPROTO_TCP:
897ab156
AD		 6171 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6172 mss_l4len_idx = tcp_hdrlen(skb) <<
6173 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6174 break;
6175 case IPPROTO_SCTP:
897ab156
AD		 6176 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6177 mss_l4len_idx = sizeof(struct sctphdr) <<
6178 IXGBE_ADVTXD_L4LEN_SHIFT;
6179 break;
6180 case IPPROTO_UDP:
6181 mss_l4len_idx = sizeof(struct udphdr) <<
6182 IXGBE_ADVTXD_L4LEN_SHIFT;
6183 break;
6184 default:
6185 if (unlikely(net_ratelimit())) {
6186 dev_warn(tx_ring->dev,
6187 "partial checksum but l4 proto=%x!\n",
6188 skb->protocol);
6189 }
7ca647bd
JP		 6190 break;
6191 }
7ca647bd
JP		 6192 }
6193
897ab156
AD		 6194 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6195 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6196
897ab156
AD		 6197 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6198 type_tucmd, mss_l4len_idx);
9a799d71 6199
897ab156 6200 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6201}
6202
d3d00239 6203static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6204{
d3d00239
AD		 6205 /* set type for advanced descriptor with frame checksum insertion */
6206 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6207 IXGBE_ADVTXD_DCMD_IFCS |
6208 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6209
d3d00239 6210 /* set HW vlan bit if vlan is present */
66f32a8b 6211 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6212 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6213
d3d00239
AD		 6214 /* set segmentation enable bits for TSO/FSO */
6215#ifdef IXGBE_FCOE
6216 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6217#else
6218 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6219#endif
6220 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6221
d3d00239
AD		 6222 return cmd_type;
6223}
9a799d71 6224
d3d00239
AD		 6225static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6226{
6227 __le32 olinfo_status =
6228 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6229
d3d00239
AD		 6230 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6231 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6232 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6233 /* enble IPv4 checksum for TSO */
6234 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6235 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6236 }
6237
d3d00239
AD		 6238 /* enable L4 checksum for TSO and TX checksum offload */
6239 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6240 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6241
d3d00239
AD		 6242#ifdef IXGBE_FCOE
6243 /* use index 1 context for FCOE/FSO */
6244 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6245 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6246 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6247
d3d00239 6248#endif
7f9643fd
AD		 6249 /*
6250 * Check Context must be set if Tx switch is enabled, which it
6251 * always is for case where virtual functions are running
6252 */
6253 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6254 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6255
d3d00239
AD		 6256 return olinfo_status;
6257}
44df32c5 6258
d3d00239
AD		 6259#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6260 IXGBE_TXD_CMD_RS)
6261
6262static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6263 struct sk_buff *skb,
6264 struct ixgbe_tx_buffer *first,
6265 u32 tx_flags,
6266 const u8 hdr_len)
6267{
6268 struct device *dev = tx_ring->dev;
6269 struct ixgbe_tx_buffer *tx_buffer_info;
6270 union ixgbe_adv_tx_desc *tx_desc;
6271 dma_addr_t dma;
6272 __le32 cmd_type, olinfo_status;
6273 struct skb_frag_struct *frag;
6274 unsigned int f = 0;
6275 unsigned int data_len = skb->data_len;
6276 unsigned int size = skb_headlen(skb);
6277 u32 offset = 0;
6278 u32 paylen = skb->len - hdr_len;
6279 u16 i = tx_ring->next_to_use;
6280 u16 gso_segs;
6281
6282#ifdef IXGBE_FCOE
6283 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6284 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6285 data_len -= sizeof(struct fcoe_crc_eof);
6286 } else {
6287 size -= sizeof(struct fcoe_crc_eof) - data_len;
6288 data_len = 0;
9a799d71
AK		 6289 }
6290 }
44df32c5 6291
d3d00239
AD		 6292#endif
6293 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6294 if (dma_mapping_error(dev, dma))
6295 goto dma_error;
8ad494b0 6296
d3d00239
AD		 6297 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6298 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6299
d3d00239 6300 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6301
d3d00239
AD		 6302 for (;;) {
6303 while (size > IXGBE_MAX_DATA_PER_TXD) {
6304 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6305 tx_desc->read.cmd_type_len =
6306 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6307 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6308
d3d00239
AD		 6309 offset += IXGBE_MAX_DATA_PER_TXD;
6310 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6311
d3d00239
AD		 6312 tx_desc++;
6313 i++;
6314 if (i == tx_ring->count) {
6315 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6316 i = 0;
6317 }
6318 }
e5a43549 6319
e5a43549 6320 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6321 tx_buffer_info->length = offset + size;
6322 tx_buffer_info->tx_flags = tx_flags;
6323 tx_buffer_info->dma = dma;
9a799d71 6324
d3d00239
AD		 6325 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6326 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6327 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6328
d3d00239
AD		 6329 if (!data_len)
6330 break;
9a799d71 6331
d3d00239
AD		 6332 frag = &skb_shinfo(skb)->frags[f];
6333#ifdef IXGBE_FCOE
6334 size = min_t(unsigned int, data_len, frag->size);
6335#else
6336 size = frag->size;
6337#endif
6338 data_len -= size;
6339 f++;
9a799d71 6340
d3d00239
AD		 6341 offset = 0;
6342 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6343
d3d00239
AD		 6344 dma = dma_map_page(dev, frag->page, frag->page_offset,
6345 size, DMA_TO_DEVICE);
6346 if (dma_mapping_error(dev, dma))
6347 goto dma_error;
9a799d71 6348
d3d00239
AD		 6349 tx_desc++;
6350 i++;
6351 if (i == tx_ring->count) {
6352 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6353 i = 0;
6354 }
6355 }
9a799d71 6356
d3d00239 6357 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6358
d3d00239
AD		 6359 i++;
6360 if (i == tx_ring->count)
6361 i = 0;
9a799d71 6362
d3d00239 6363 tx_ring->next_to_use = i;
eacd73f7 6364
d3d00239
AD		 6365 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6366 gso_segs = skb_shinfo(skb)->gso_segs;
6367#ifdef IXGBE_FCOE
6368 /* adjust for FCoE Sequence Offload */
6369 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6370 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6371 skb_shinfo(skb)->gso_size);
6372#endif /* IXGBE_FCOE */
6373 else
6374 gso_segs = 1;
9a799d71 6375
d3d00239
AD		 6376 /* multiply data chunks by size of headers */
6377 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6378 tx_buffer_info->gso_segs = gso_segs;
6379 tx_buffer_info->skb = skb;
9a799d71 6380
d3d00239
AD		 6381 /* set the timestamp */
6382 first->time_stamp = jiffies;
9a799d71
AK		 6383
6384 /*
6385 * Force memory writes to complete before letting h/w
6386 * know there are new descriptors to fetch. (Only
6387 * applicable for weak-ordered memory model archs,
6388 * such as IA-64).
6389 */
6390 wmb();
6391
d3d00239
AD		 6392 /* set next_to_watch value indicating a packet is present */
6393 first->next_to_watch = tx_desc;
6394
6395 /* notify HW of packet */
84ea2591 6396 writel(i, tx_ring->tail);
d3d00239
AD		 6397
6398 return;
6399dma_error:
6400 dev_err(dev, "TX DMA map failed\n");
6401
6402 /* clear dma mappings for failed tx_buffer_info map */
6403 for (;;) {
6404 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6405 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6406 if (tx_buffer_info == first)
6407 break;
6408 if (i == 0)
6409 i = tx_ring->count;
6410 i--;
6411 }
6412
6413 dev_kfree_skb_any(skb);
6414
6415 tx_ring->next_to_use = i;
9a799d71
AK		 6416}
6417
69830529
AD		 6418static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6419 u32 tx_flags, __be16 protocol)
6420{
6421 struct ixgbe_q_vector *q_vector = ring->q_vector;
6422 union ixgbe_atr_hash_dword input = { .dword = 0 };
6423 union ixgbe_atr_hash_dword common = { .dword = 0 };
6424 union {
6425 unsigned char *network;
6426 struct iphdr *ipv4;
6427 struct ipv6hdr *ipv6;
6428 } hdr;
ee9e0f0b 6429 struct tcphdr *th;
905e4a41 6430 __be16 vlan_id;
c4cf55e5 6431
69830529
AD		 6432 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6433 if (!q_vector)
6434 return;
6435
6436 /* do nothing if sampling is disabled */
6437 if (!ring->atr_sample_rate)
d3ead241 6438 return;
c4cf55e5 6439
69830529 6440 ring->atr_count++;
c4cf55e5 6441
69830529
AD		 6442 /* snag network header to get L4 type and address */
6443 hdr.network = skb_network_header(skb);
6444
6445 /* Currently only IPv4/IPv6 with TCP is supported */
6446 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6447 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6448 (protocol != __constant_htons(ETH_P_IP) ||
6449 hdr.ipv4->protocol != IPPROTO_TCP))
6450 return;
ee9e0f0b
AD		 6451
6452 th = tcp_hdr(skb);
c4cf55e5 6453
66f32a8b
AD		 6454 /* skip this packet since it is invalid or the socket is closing */
6455 if (!th || th->fin)
69830529
AD		 6456 return;
6457
6458 /* sample on all syn packets or once every atr sample count */
6459 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6460 return;
6461
6462 /* reset sample count */
6463 ring->atr_count = 0;
6464
6465 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6466
6467 /*
6468 * src and dst are inverted, think how the receiver sees them
6469 *
6470 * The input is broken into two sections, a non-compressed section
6471 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6472 * is XORed together and stored in the compressed dword.
6473 */
6474 input.formatted.vlan_id = vlan_id;
6475
6476 /*
6477 * since src port and flex bytes occupy the same word XOR them together
6478 * and write the value to source port portion of compressed dword
6479 */
66f32a8b 6480 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6481 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6482 else
6483 common.port.src ^= th->dest ^ protocol;
6484 common.port.dst ^= th->source;
6485
6486 if (protocol == __constant_htons(ETH_P_IP)) {
6487 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6488 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6489 } else {
6490 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6491 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6492 hdr.ipv6->saddr.s6_addr32[1] ^
6493 hdr.ipv6->saddr.s6_addr32[2] ^
6494 hdr.ipv6->saddr.s6_addr32[3] ^
6495 hdr.ipv6->daddr.s6_addr32[0] ^
6496 hdr.ipv6->daddr.s6_addr32[1] ^
6497 hdr.ipv6->daddr.s6_addr32[2] ^
6498 hdr.ipv6->daddr.s6_addr32[3];
6499 }
c4cf55e5
PWJ		 6500
6501 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6502 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6503 input, common, ring->queue_index);
c4cf55e5
PWJ		 6504}
6505
63544e9c 6506static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6507{
fc77dc3c 6508 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6509 /* Herbert's original patch had:
6510 * smp_mb__after_netif_stop_queue();
6511 * but since that doesn't exist yet, just open code it. */
6512 smp_mb();
6513
6514 /* We need to check again in a case another CPU has just
6515 * made room available. */
7d4987de 6516 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6517 return -EBUSY;
6518
6519 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6520 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6521 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6522 return 0;
6523}
6524
82d4e46e 6525static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6526{
7d4987de 6527 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6528 return 0;
fc77dc3c 6529 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6530}
6531
09a3b1f8
SH		 6532static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6533{
6534 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6535 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6536 smp_processor_id();
56075a98 6537#ifdef IXGBE_FCOE
6440752c 6538 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6539
e5b64635
JF		 6540 if (((protocol == htons(ETH_P_FCOE)) ||
6541 (protocol == htons(ETH_P_FIP))) &&
6542 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6543 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6544 txq += adapter->ring_feature[RING_F_FCOE].mask;
6545 return txq;
56075a98
JF		 6546 }
6547#endif
6548
fdd3d631
KK		 6549 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6550 while (unlikely(txq >= dev->real_num_tx_queues))
6551 txq -= dev->real_num_tx_queues;
5f715823 6552 return txq;
fdd3d631 6553 }
c4cf55e5 6554
09a3b1f8
SH		 6555 return skb_tx_hash(dev, skb);
6556}
6557
fc77dc3c 6558netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6559 struct ixgbe_adapter *adapter,
6560 struct ixgbe_ring *tx_ring)
9a799d71 6561{
d3d00239 6562 struct ixgbe_tx_buffer *first;
5f715823 6563 int tso;
d3d00239 6564 u32 tx_flags = 0;
a535c30e
AD		 6565#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6566 unsigned short f;
6567#endif
a535c30e 6568 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6569 __be16 protocol = skb->protocol;
63544e9c 6570 u8 hdr_len = 0;
5e09a105 6571
a535c30e
AD		 6572 /*
6573 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6574 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6575 * + 2 desc gap to keep tail from touching head,
6576 * + 1 desc for context descriptor,
6577 * otherwise try next time
6578 */
6579#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6580 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6581 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6582#else
6583 count += skb_shinfo(skb)->nr_frags;
6584#endif
6585 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6586 tx_ring->tx_stats.tx_busy++;
6587 return NETDEV_TX_BUSY;
6588 }
6589
7f9643fd
AD		 6590#ifdef CONFIG_PCI_IOV
6591 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6592 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6593
6594#endif
66f32a8b 6595 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6596 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6597 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6598 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6599 /* else if it is a SW VLAN check the next protocol and store the tag */
6600 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6601 struct vlan_hdr *vhdr, _vhdr;
6602 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6603 if (!vhdr)
6604 goto out_drop;
6605
6606 protocol = vhdr->h_vlan_encapsulated_proto;
6607 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6608 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6609 }
6610
6611 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6612 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6613 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b
AD		 6614 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6615 tx_flags |= tx_ring->dcb_tc <<
6616 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6617 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6618 struct vlan_ethhdr *vhdr;
6619 if (skb_header_cloned(skb) &&
6620 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6621 goto out_drop;
6622 vhdr = (struct vlan_ethhdr *)skb->data;
6623 vhdr->h_vlan_TCI = htons(tx_flags >>
6624 IXGBE_TX_FLAGS_VLAN_SHIFT);
6625 } else {
6626 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6627 }
9a799d71 6628 }
eacd73f7 6629
a535c30e 6630 /* record the location of the first descriptor for this packet */
d3d00239 6631 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6632
eacd73f7 6633#ifdef IXGBE_FCOE
66f32a8b
AD		 6634 /* setup tx offload for FCoE */
6635 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6636 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6637 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6638 if (tso < 0)
6639 goto out_drop;
6640 else if (tso)
66f32a8b
AD		 6641 tx_flags |= IXGBE_TX_FLAGS_FSO |
6642 IXGBE_TX_FLAGS_FCOE;
6643 else
6644 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6645
66f32a8b 6646 goto xmit_fcoe;
eacd73f7 6647 }
9a799d71 6648
66f32a8b
AD		 6649#endif /* IXGBE_FCOE */
6650 /* setup IPv4/IPv6 offloads */
6651 if (protocol == __constant_htons(ETH_P_IP))
6652 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6653
66f32a8b
AD		 6654 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6655 if (tso < 0)
897ab156 6656 goto out_drop;
66f32a8b
AD		 6657 else if (tso)
6658 tx_flags |= IXGBE_TX_FLAGS_TSO;
6659 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6660 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6661
6662 /* add the ATR filter if ATR is on */
6663 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6664 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6665
6666#ifdef IXGBE_FCOE
6667xmit_fcoe:
6668#endif /* IXGBE_FCOE */
d3d00239
AD		 6669 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6670
6671 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6672
6673 return NETDEV_TX_OK;
897ab156
AD		 6674
6675out_drop:
6676 dev_kfree_skb_any(skb);
6677 return NETDEV_TX_OK;
9a799d71
AK		 6678}
6679
84418e3b
AD		 6680static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6681{
6682 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6683 struct ixgbe_ring *tx_ring;
6684
6685 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6686 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6687}
6688
9a799d71
AK		 6689/**
6690 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6691 * @netdev: network interface device structure
6692 * @p: pointer to an address structure
6693 *
6694 * Returns 0 on success, negative on failure
6695 **/
6696static int ixgbe_set_mac(struct net_device *netdev, void *p)
6697{
6698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6699 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6700 struct sockaddr *addr = p;
6701
6702 if (!is_valid_ether_addr(addr->sa_data))
6703 return -EADDRNOTAVAIL;
6704
6705 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6706 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6707
1cdd1ec8
GR		 6708 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6709 IXGBE_RAH_AV);
9a799d71
AK		 6710
6711 return 0;
6712}
6713
6b73e10d
BH		 6714static int
6715ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6716{
6717 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6718 struct ixgbe_hw *hw = &adapter->hw;
6719 u16 value;
6720 int rc;
6721
6722 if (prtad != hw->phy.mdio.prtad)
6723 return -EINVAL;
6724 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6725 if (!rc)
6726 rc = value;
6727 return rc;
6728}
6729
6730static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6731 u16 addr, u16 value)
6732{
6733 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6734 struct ixgbe_hw *hw = &adapter->hw;
6735
6736 if (prtad != hw->phy.mdio.prtad)
6737 return -EINVAL;
6738 return hw->phy.ops.write_reg(hw, addr, devad, value);
6739}
6740
6741static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6742{
6743 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6744
6745 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6746}
6747
0365e6e4
PW		 6748/**
6749 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6750 * netdev->dev_addrs
0365e6e4
PW		 6751 * @netdev: network interface device structure
6752 *
6753 * Returns non-zero on failure
6754 **/
6755static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6756{
6757 int err = 0;
6758 struct ixgbe_adapter *adapter = netdev_priv(dev);
6759 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6760
6761 if (is_valid_ether_addr(mac->san_addr)) {
6762 rtnl_lock();
6763 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6764 rtnl_unlock();
6765 }
6766 return err;
6767}
6768
6769/**
6770 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6771 * netdev->dev_addrs
0365e6e4
PW		 6772 * @netdev: network interface device structure
6773 *
6774 * Returns non-zero on failure
6775 **/
6776static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6777{
6778 int err = 0;
6779 struct ixgbe_adapter *adapter = netdev_priv(dev);
6780 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6781
6782 if (is_valid_ether_addr(mac->san_addr)) {
6783 rtnl_lock();
6784 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6785 rtnl_unlock();
6786 }
6787 return err;
6788}
6789
9a799d71
AK		 6790#ifdef CONFIG_NET_POLL_CONTROLLER
6791/*
6792 * Polling 'interrupt' - used by things like netconsole to send skbs
6793 * without having to re-enable interrupts. It's not called while
6794 * the interrupt routine is executing.
6795 */
6796static void ixgbe_netpoll(struct net_device *netdev)
6797{
6798 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6799 int i;
9a799d71 6800
1a647bd2
AD		 6801 /* if interface is down do nothing */
6802 if (test_bit(__IXGBE_DOWN, &adapter->state))
6803 return;
6804
9a799d71 6805 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6806 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6807 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6808 for (i = 0; i < num_q_vectors; i++) {
6809 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 6810 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 6811 }
6812 } else {
6813 ixgbe_intr(adapter->pdev->irq, netdev);
6814 }
9a799d71 6815 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6816}
6817#endif
6818
de1036b1
ED		 6819static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6820 struct rtnl_link_stats64 *stats)
6821{
6822 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6823 int i;
6824
1a51502b 6825 rcu_read_lock();
de1036b1 6826 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6827 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6828 u64 bytes, packets;
6829 unsigned int start;
6830
1a51502b
ED		 6831 if (ring) {
6832 do {
6833 start = u64_stats_fetch_begin_bh(&ring->syncp);
6834 packets = ring->stats.packets;
6835 bytes = ring->stats.bytes;
6836 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6837 stats->rx_packets += packets;
6838 stats->rx_bytes += bytes;
6839 }
de1036b1 6840 }
1ac9ad13
ED		 6841
6842 for (i = 0; i < adapter->num_tx_queues; i++) {
6843 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6844 u64 bytes, packets;
6845 unsigned int start;
6846
6847 if (ring) {
6848 do {
6849 start = u64_stats_fetch_begin_bh(&ring->syncp);
6850 packets = ring->stats.packets;
6851 bytes = ring->stats.bytes;
6852 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6853 stats->tx_packets += packets;
6854 stats->tx_bytes += bytes;
6855 }
6856 }
1a51502b 6857 rcu_read_unlock();
de1036b1
ED		 6858 /* following stats updated by ixgbe_watchdog_task() */
6859 stats->multicast = netdev->stats.multicast;
6860 stats->rx_errors = netdev->stats.rx_errors;
6861 stats->rx_length_errors = netdev->stats.rx_length_errors;
6862 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6863 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6864 return stats;
6865}
6866
8b1c0b24
JF		 6867/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6868 * #adapter: pointer to ixgbe_adapter
6869 * @tc: number of traffic classes currently enabled
6870 *
6871 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6872 * 802.1Q priority maps to a packet buffer that exists.
6873 */
6874static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6875{
6876 struct ixgbe_hw *hw = &adapter->hw;
6877 u32 reg, rsave;
6878 int i;
6879
6880 /* 82598 have a static priority to TC mapping that can not
6881 * be changed so no validation is needed.
6882 */
6883 if (hw->mac.type == ixgbe_mac_82598EB)
6884 return;
6885
6886 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6887 rsave = reg;
6888
6889 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6890 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6891
6892 /* If up2tc is out of bounds default to zero */
6893 if (up2tc > tc)
6894 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6895 }
6896
6897 if (reg != rsave)
6898 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6899
6900 return;
6901}
6902
6903
6904/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6905 * classes.
6906 *
6907 * @netdev: net device to configure
6908 * @tc: number of traffic classes to enable
6909 */
6910int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6911{
8b1c0b24
JF		 6912 struct ixgbe_adapter *adapter = netdev_priv(dev);
6913 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6914
e7589eab
JF		 6915 /* Multiple traffic classes requires multiple queues */
6916 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6917 e_err(drv, "Enable failed, needs MSI-X\n");
6918 return -EINVAL;
6919 }
8b1c0b24
JF		 6920
6921 /* Hardware supports up to 8 traffic classes */
6922 if (tc > MAX_TRAFFIC_CLASS ||
6923 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
6924 return -EINVAL;
6925
6926 /* Hardware has to reinitialize queues and interrupts to
6927 * match packet buffer alignment. Unfortunantly, the
6928 * hardware is not flexible enough to do this dynamically.
6929 */
6930 if (netif_running(dev))
6931 ixgbe_close(dev);
6932 ixgbe_clear_interrupt_scheme(adapter);
6933
e7589eab 6934 if (tc) {
8b1c0b24 6935 netdev_set_num_tc(dev, tc);
e7589eab
JF		 6936 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6937
6938 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6939 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6940
6941 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6942 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6943 } else {
8b1c0b24
JF		 6944 netdev_reset_tc(dev);
6945
e7589eab
JF		 6946 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6947
6948 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6949 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6950
6951 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6952 adapter->dcb_cfg.pfc_mode_enable = false;
6953 }
6954
8b1c0b24
JF		 6955 ixgbe_init_interrupt_scheme(adapter);
6956 ixgbe_validate_rtr(adapter, tc);
6957 if (netif_running(dev))
6958 ixgbe_open(dev);
6959
6960 return 0;
6961}
de1036b1 6962
082757af
DS		 6963void ixgbe_do_reset(struct net_device *netdev)
6964{
6965 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6966
6967 if (netif_running(netdev))
6968 ixgbe_reinit_locked(adapter);
6969 else
6970 ixgbe_reset(adapter);
6971}
6972
6973static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
6974{
6975 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6976
6977#ifdef CONFIG_DCB
6978 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6979 data &= ~NETIF_F_HW_VLAN_RX;
6980#endif
6981
6982 /* return error if RXHASH is being enabled when RSS is not supported */
6983 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6984 data &= ~NETIF_F_RXHASH;
6985
6986 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6987 if (!(data & NETIF_F_RXCSUM))
6988 data &= ~NETIF_F_LRO;
6989
6990 /* Turn off LRO if not RSC capable or invalid ITR settings */
6991 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
6992 data &= ~NETIF_F_LRO;
6993 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
6994 (adapter->rx_itr_setting != 1 &&
6995 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
6996 data &= ~NETIF_F_LRO;
6997 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
6998 }
6999
7000 return data;
7001}
7002
7003static int ixgbe_set_features(struct net_device *netdev, u32 data)
7004{
7005 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7006 bool need_reset = false;
7007
7008 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7009 if (!(data & NETIF_F_RXCSUM))
7010 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7011 else
7012 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7013
7014 /* Make sure RSC matches LRO, reset if change */
7015 if (!!(data & NETIF_F_LRO) !=
7016 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7017 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7018 switch (adapter->hw.mac.type) {
7019 case ixgbe_mac_X540:
7020 case ixgbe_mac_82599EB:
7021 need_reset = true;
7022 break;
7023 default:
7024 break;
7025 }
7026 }
7027
7028 /*
7029 * Check if Flow Director n-tuple support was enabled or disabled. If
7030 * the state changed, we need to reset.
7031 */
7032 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7033 /* turn off ATR, enable perfect filters and reset */
7034 if (data & NETIF_F_NTUPLE) {
7035 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7036 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7037 need_reset = true;
7038 }
7039 } else if (!(data & NETIF_F_NTUPLE)) {
7040 /* turn off Flow Director, set ATR and reset */
7041 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7042 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7043 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7044 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7045 need_reset = true;
7046 }
7047
7048 if (need_reset)
7049 ixgbe_do_reset(netdev);
7050
7051 return 0;
7052
7053}
7054
0edc3527 7055static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7056 .ndo_open = ixgbe_open,
0edc3527 7057 .ndo_stop = ixgbe_close,
00829823 7058 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7059 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7060 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7061 .ndo_validate_addr = eth_validate_addr,
7062 .ndo_set_mac_address = ixgbe_set_mac,
7063 .ndo_change_mtu = ixgbe_change_mtu,
7064 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7065 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7066 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7067 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7068 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7069 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7070 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7071 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7072 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7073 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7074#ifdef CONFIG_NET_POLL_CONTROLLER
7075 .ndo_poll_controller = ixgbe_netpoll,
7076#endif
332d4a7d
YZ		 7077#ifdef IXGBE_FCOE
7078 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7079 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7080 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7081 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7082 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7083 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7084#endif /* IXGBE_FCOE */
082757af
DS		 7085 .ndo_set_features = ixgbe_set_features,
7086 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7087};
7088
1cdd1ec8
GR		 7089static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7090 const struct ixgbe_info *ii)
7091{
7092#ifdef CONFIG_PCI_IOV
7093 struct ixgbe_hw *hw = &adapter->hw;
7094 int err;
a1cbb15c
GR		 7095 int num_vf_macvlans, i;
7096 struct vf_macvlans *mv_list;
1cdd1ec8 7097
3377eba7 7098 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7099 return;
7100
7101 /* The 82599 supports up to 64 VFs per physical function
7102 * but this implementation limits allocation to 63 so that
7103 * basic networking resources are still available to the
7104 * physical function
7105 */
7106 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7107 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7108 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7109 if (err) {
396e799c 7110 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7111 goto err_novfs;
7112 }
a1cbb15c
GR		 7113
7114 num_vf_macvlans = hw->mac.num_rar_entries -
7115 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7116
7117 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7118 sizeof(struct vf_macvlans),
7119 GFP_KERNEL);
7120 if (mv_list) {
7121 /* Initialize list of VF macvlans */
7122 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7123 for (i = 0; i < num_vf_macvlans; i++) {
7124 mv_list->vf = -1;
7125 mv_list->free = true;
7126 mv_list->rar_entry = hw->mac.num_rar_entries -
7127 (i + adapter->num_vfs + 1);
7128 list_add(&mv_list->l, &adapter->vf_mvs.l);
7129 mv_list++;
7130 }
7131 }
7132
1cdd1ec8
GR		 7133 /* If call to enable VFs succeeded then allocate memory
7134 * for per VF control structures.
7135 */
7136 adapter->vfinfo =
7137 kcalloc(adapter->num_vfs,
7138 sizeof(struct vf_data_storage), GFP_KERNEL);
7139 if (adapter->vfinfo) {
7140 /* Now that we're sure SR-IOV is enabled
7141 * and memory allocated set up the mailbox parameters
7142 */
7143 ixgbe_init_mbx_params_pf(hw);
7144 memcpy(&hw->mbx.ops, ii->mbx_ops,
7145 sizeof(hw->mbx.ops));
7146
7147 /* Disable RSC when in SR-IOV mode */
7148 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7149 IXGBE_FLAG2_RSC_ENABLED);
7150 return;
7151 }
7152
7153 /* Oh oh */
396e799c
ET		 7154 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7155 "SRIOV disabled\n");
1cdd1ec8
GR		 7156 pci_disable_sriov(adapter->pdev);
7157
7158err_novfs:
7159 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7160 adapter->num_vfs = 0;
7161#endif /* CONFIG_PCI_IOV */
7162}
7163
9a799d71
AK		 7164/**
7165 * ixgbe_probe - Device Initialization Routine
7166 * @pdev: PCI device information struct
7167 * @ent: entry in ixgbe_pci_tbl
7168 *
7169 * Returns 0 on success, negative on failure
7170 *
7171 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7172 * The OS initialization, configuring of the adapter private structure,
7173 * and a hardware reset occur.
7174 **/
7175static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7176 const struct pci_device_id *ent)
9a799d71
AK		 7177{
7178 struct net_device *netdev;
7179 struct ixgbe_adapter *adapter = NULL;
7180 struct ixgbe_hw *hw;
7181 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7182 static int cards_found;
7183 int i, err, pci_using_dac;
289700db 7184 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7185 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7186#ifdef IXGBE_FCOE
7187 u16 device_caps;
7188#endif
289700db 7189 u32 eec;
9a799d71 7190
bded64a7
AG		 7191 /* Catch broken hardware that put the wrong VF device ID in
7192 * the PCIe SR-IOV capability.
7193 */
7194 if (pdev->is_virtfn) {
7195 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7196 pci_name(pdev), pdev->vendor, pdev->device);
7197 return -EINVAL;
7198 }
7199
9ce77666 7200 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7201 if (err)
7202 return err;
7203
1b507730
NN		 7204 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7205 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7206 pci_using_dac = 1;
7207 } else {
1b507730 7208 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7209 if (err) {
1b507730
NN		 7210 err = dma_set_coherent_mask(&pdev->dev,
7211 DMA_BIT_MASK(32));
9a799d71 7212 if (err) {
b8bc0421
DC		 7213 dev_err(&pdev->dev,
7214 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7215 goto err_dma;
7216 }
7217 }
7218 pci_using_dac = 0;
7219 }
7220
9ce77666 7221 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7222 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7223 if (err) {
b8bc0421
DC		 7224 dev_err(&pdev->dev,
7225 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7226 goto err_pci_reg;
7227 }
7228
19d5afd4 7229 pci_enable_pcie_error_reporting(pdev);
6fabd715 7230
9a799d71 7231 pci_set_master(pdev);
fb3b27bc 7232 pci_save_state(pdev);
9a799d71 7233
e901acd6
JF		 7234#ifdef CONFIG_IXGBE_DCB
7235 indices *= MAX_TRAFFIC_CLASS;
7236#endif
7237
c85a2618
JF		 7238 if (ii->mac == ixgbe_mac_82598EB)
7239 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7240 else
7241 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7242
e901acd6 7243#ifdef IXGBE_FCOE
c85a2618
JF		 7244 indices += min_t(unsigned int, num_possible_cpus(),
7245 IXGBE_MAX_FCOE_INDICES);
7246#endif
c85a2618 7247 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7248 if (!netdev) {
7249 err = -ENOMEM;
7250 goto err_alloc_etherdev;
7251 }
7252
9a799d71
AK		 7253 SET_NETDEV_DEV(netdev, &pdev->dev);
7254
9a799d71 7255 adapter = netdev_priv(netdev);
c60fbb00 7256 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7257
7258 adapter->netdev = netdev;
7259 adapter->pdev = pdev;
7260 hw = &adapter->hw;
7261 hw->back = adapter;
7262 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7263
05857980 7264 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7265 pci_resource_len(pdev, 0));
9a799d71
AK		 7266 if (!hw->hw_addr) {
7267 err = -EIO;
7268 goto err_ioremap;
7269 }
7270
7271 for (i = 1; i <= 5; i++) {
7272 if (pci_resource_len(pdev, i) == 0)
7273 continue;
7274 }
7275
0edc3527 7276 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7277 ixgbe_set_ethtool_ops(netdev);
9a799d71 7278 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7279 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7280
9a799d71
AK		 7281 adapter->bd_number = cards_found;
7282
9a799d71
AK		 7283 /* Setup hw api */
7284 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7285 hw->mac.type = ii->mac;
9a799d71 7286
c44ade9e
JB		 7287 /* EEPROM */
7288 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7289 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7290 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7291 if (!(eec & (1 << 8)))
7292 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7293
7294 /* PHY */
7295 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7296 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7297 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7298 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7299 hw->phy.mdio.mmds = 0;
7300 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7301 hw->phy.mdio.dev = netdev;
7302 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7303 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7304
8ca783ab 7305 ii->get_invariants(hw);
9a799d71
AK		 7306
7307 /* setup the private structure */
7308 err = ixgbe_sw_init(adapter);
7309 if (err)
7310 goto err_sw_init;
7311
e86bff0e 7312 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7313 switch (adapter->hw.mac.type) {
7314 case ixgbe_mac_82599EB:
7315 case ixgbe_mac_X540:
e86bff0e 7316 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7317 break;
7318 default:
7319 break;
7320 }
e86bff0e 7321
bf069c97
DS		 7322 /*
7323 * If there is a fan on this device and it has failed log the
7324 * failure.
7325 */
7326 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7327 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7328 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7329 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7330 }
7331
c44ade9e 7332 /* reset_hw fills in the perm_addr as well */
119fc60a 7333 hw->phy.reset_if_overtemp = true;
c44ade9e 7334 err = hw->mac.ops.reset_hw(hw);
119fc60a 7335 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7336 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7337 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7338 err = 0;
7339 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7340 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7341 "module type was detected.\n");
7342 e_dev_err("Reload the driver after installing a supported "
7343 "module.\n");
04f165ef
PW		 7344 goto err_sw_init;
7345 } else if (err) {
849c4542 7346 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7347 goto err_sw_init;
7348 }
7349
1cdd1ec8
GR		 7350 ixgbe_probe_vf(adapter, ii);
7351
396e799c 7352 netdev->features = NETIF_F_SG |
e8e9f696 7353 NETIF_F_IP_CSUM |
082757af 7354 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7355 NETIF_F_HW_VLAN_TX |
7356 NETIF_F_HW_VLAN_RX |
082757af
DS		 7357 NETIF_F_HW_VLAN_FILTER |
7358 NETIF_F_TSO |
7359 NETIF_F_TSO6 |
082757af
DS		 7360 NETIF_F_RXHASH |
7361 NETIF_F_RXCSUM;
9a799d71 7362
082757af 7363 netdev->hw_features = netdev->features;
ad31c402 7364
58be7666
DS		 7365 switch (adapter->hw.mac.type) {
7366 case ixgbe_mac_82599EB:
7367 case ixgbe_mac_X540:
45a5ead0 7368 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7369 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7370 NETIF_F_NTUPLE;
58be7666
DS		 7371 break;
7372 default:
7373 break;
7374 }
45a5ead0 7375
ad31c402
JK		 7376 netdev->vlan_features |= NETIF_F_TSO;
7377 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7378 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7379 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7380 netdev->vlan_features |= NETIF_F_SG;
7381
01789349
JP		 7382 netdev->priv_flags |= IFF_UNICAST_FLT;
7383
1cdd1ec8
GR		 7384 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7385 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7386 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7387
7a6b6f51 7388#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7389 netdev->dcbnl_ops = &dcbnl_ops;
7390#endif
7391
eacd73f7 7392#ifdef IXGBE_FCOE
0d551589 7393 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7394 if (hw->mac.ops.get_device_caps) {
7395 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7396 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7397 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7398 }
7399 }
5e09d7f6
YZ		 7400 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7401 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7402 netdev->vlan_features |= NETIF_F_FSO;
7403 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7404 }
eacd73f7 7405#endif /* IXGBE_FCOE */
7b872a55 7406 if (pci_using_dac) {
9a799d71 7407 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7408 netdev->vlan_features |= NETIF_F_HIGHDMA;
7409 }
9a799d71 7410
082757af
DS		 7411 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7412 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7413 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7414 netdev->features |= NETIF_F_LRO;
7415
9a799d71 7416 /* make sure the EEPROM is good */
c44ade9e 7417 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7418 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7419 err = -EIO;
7420 goto err_eeprom;
7421 }
7422
7423 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7424 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7425
c44ade9e 7426 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7427 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7428 err = -EIO;
7429 goto err_eeprom;
7430 }
7431
c6ecf39a
DS		 7432 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7433 if (hw->mac.ops.disable_tx_laser &&
7434 ((hw->phy.multispeed_fiber) ||
9f911707 7435 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7436 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7437 hw->mac.ops.disable_tx_laser(hw);
7438
7086400d
AD		 7439 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7440 (unsigned long) adapter);
9a799d71 7441
7086400d
AD		 7442 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7443 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7444
021230d4
AV		 7445 err = ixgbe_init_interrupt_scheme(adapter);
7446 if (err)
7447 goto err_sw_init;
9a799d71 7448
082757af
DS		 7449 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7450 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7451 netdev->features &= ~NETIF_F_RXHASH;
082757af 7452 }
67a74ee2 7453
e8e26350 7454 switch (pdev->device) {
0b077fea
DS		 7455 case IXGBE_DEV_ID_82599_SFP:
7456 /* Only this subdevice supports WOL */
7457 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
9417c464 7458 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7459 break;
50d6c681
AD		 7460 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7461 /* All except this subdevice support WOL */
0b077fea 7462 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7463 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7464 break;
e8e26350 7465 case IXGBE_DEV_ID_82599_KX4:
9417c464 7466 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7467 break;
7468 default:
7469 adapter->wol = 0;
7470 break;
7471 }
e8e26350
PW		 7472 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7473
04f165ef
PW		 7474 /* pick up the PCI bus settings for reporting later */
7475 hw->mac.ops.get_bus_info(hw);
7476
9a799d71 7477 /* print bus type/speed/width info */
849c4542 7478 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7479 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7480 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7481 "Unknown"),
7482 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7483 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7484 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7485 "Unknown"),
7486 netdev->dev_addr);
289700db
DS		 7487
7488 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7489 if (err)
9fe93afd 7490 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7491 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7492 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7493 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7494 part_str);
e8e26350 7495 else
289700db
DS		 7496 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7497 hw->mac.type, hw->phy.type, part_str);
9a799d71 7498
e8e26350 7499 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7500 e_dev_warn("PCI-Express bandwidth available for this card is "
7501 "not sufficient for optimal performance.\n");
7502 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7503 "is required.\n");
0c254d86
AK		 7504 }
7505
34b0368c
PWJ		 7506 /* save off EEPROM version number */
7507 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7508
9a799d71 7509 /* reset the hardware with the new settings */
794caeb2 7510 err = hw->mac.ops.start_hw(hw);
c44ade9e 7511
794caeb2
PWJ		 7512 if (err == IXGBE_ERR_EEPROM_VERSION) {
7513 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7514 e_dev_warn("This device is a pre-production adapter/LOM. "
7515 "Please be aware there may be issues associated "
7516 "with your hardware. If you are experiencing "
7517 "problems please contact your Intel or hardware "
7518 "representative who provided you with this "
7519 "hardware.\n");
794caeb2 7520 }
9a799d71
AK		 7521 strcpy(netdev->name, "eth%d");
7522 err = register_netdev(netdev);
7523 if (err)
7524 goto err_register;
7525
54386467
JB		 7526 /* carrier off reporting is important to ethtool even BEFORE open */
7527 netif_carrier_off(netdev);
7528
5dd2d332 7529#ifdef CONFIG_IXGBE_DCA
652f093f 7530 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7531 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7532 ixgbe_setup_dca(adapter);
7533 }
7534#endif
1cdd1ec8 7535 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7536 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7537 for (i = 0; i < adapter->num_vfs; i++)
7538 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7539 }
7540
9612de92
ET		 7541 /* Inform firmware of driver version */
7542 if (hw->mac.ops.set_fw_drv_ver)
a38a104d
DS		 7543 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7544 FW_CEM_UNUSED_VER);
9612de92 7545
0365e6e4
PW		 7546 /* add san mac addr to netdev */
7547 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7548
849c4542 7549 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7550 cards_found++;
7551 return 0;
7552
7553err_register:
5eba3699 7554 ixgbe_release_hw_control(adapter);
7a921c93 7555 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7556err_sw_init:
7557err_eeprom:
1cdd1ec8
GR		 7558 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7559 ixgbe_disable_sriov(adapter);
7086400d 7560 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7561 iounmap(hw->hw_addr);
7562err_ioremap:
7563 free_netdev(netdev);
7564err_alloc_etherdev:
e8e9f696
JP		 7565 pci_release_selected_regions(pdev,
7566 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7567err_pci_reg:
7568err_dma:
7569 pci_disable_device(pdev);
7570 return err;
7571}
7572
7573/**
7574 * ixgbe_remove - Device Removal Routine
7575 * @pdev: PCI device information struct
7576 *
7577 * ixgbe_remove is called by the PCI subsystem to alert the driver
7578 * that it should release a PCI device. The could be caused by a
7579 * Hot-Plug event, or because the driver is going to be removed from
7580 * memory.
7581 **/
7582static void __devexit ixgbe_remove(struct pci_dev *pdev)
7583{
c60fbb00
AD		 7584 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7585 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7586
7587 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7588 cancel_work_sync(&adapter->service_task);
9a799d71 7589
5dd2d332 7590#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7591 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7592 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7593 dca_remove_requester(&pdev->dev);
7594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7595 }
7596
7597#endif
332d4a7d
YZ		 7598#ifdef IXGBE_FCOE
7599 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7600 ixgbe_cleanup_fcoe(adapter);
7601
7602#endif /* IXGBE_FCOE */
0365e6e4
PW		 7603
7604 /* remove the added san mac */
7605 ixgbe_del_sanmac_netdev(netdev);
7606
c4900be0
DS		 7607 if (netdev->reg_state == NETREG_REGISTERED)
7608 unregister_netdev(netdev);
9a799d71 7609
1cdd1ec8
GR		 7610 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7611 ixgbe_disable_sriov(adapter);
7612
7a921c93 7613 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7614
021230d4 7615 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7616
7617 iounmap(adapter->hw.hw_addr);
9ce77666 7618 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7619 IORESOURCE_MEM));
9a799d71 7620
849c4542 7621 e_dev_info("complete\n");
021230d4 7622
9a799d71
AK		 7623 free_netdev(netdev);
7624
19d5afd4 7625 pci_disable_pcie_error_reporting(pdev);
6fabd715 7626
9a799d71
AK		 7627 pci_disable_device(pdev);
7628}
7629
7630/**
7631 * ixgbe_io_error_detected - called when PCI error is detected
7632 * @pdev: Pointer to PCI device
7633 * @state: The current pci connection state
7634 *
7635 * This function is called after a PCI bus error affecting
7636 * this device has been detected.
7637 */
7638static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7639 pci_channel_state_t state)
9a799d71 7640{
c60fbb00
AD		 7641 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7642 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7643
7644 netif_device_detach(netdev);
7645
3044b8d1
BL		 7646 if (state == pci_channel_io_perm_failure)
7647 return PCI_ERS_RESULT_DISCONNECT;
7648
9a799d71
AK		 7649 if (netif_running(netdev))
7650 ixgbe_down(adapter);
7651 pci_disable_device(pdev);
7652
b4617240 7653 /* Request a slot reset. */
9a799d71
AK		 7654 return PCI_ERS_RESULT_NEED_RESET;
7655}
7656
7657/**
7658 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7659 * @pdev: Pointer to PCI device
7660 *
7661 * Restart the card from scratch, as if from a cold-boot.
7662 */
7663static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7664{
c60fbb00 7665 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7666 pci_ers_result_t result;
7667 int err;
9a799d71 7668
9ce77666 7669 if (pci_enable_device_mem(pdev)) {
396e799c 7670 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7671 result = PCI_ERS_RESULT_DISCONNECT;
7672 } else {
7673 pci_set_master(pdev);
7674 pci_restore_state(pdev);
c0e1f68b 7675 pci_save_state(pdev);
9a799d71 7676
dd4d8ca6 7677 pci_wake_from_d3(pdev, false);
9a799d71 7678
6fabd715 7679 ixgbe_reset(adapter);
88512539 7680 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7681 result = PCI_ERS_RESULT_RECOVERED;
7682 }
7683
7684 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7685 if (err) {
849c4542
ET		 7686 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7687 "failed 0x%0x\n", err);
6fabd715
PWJ		 7688 /* non-fatal, continue */
7689 }
9a799d71 7690
6fabd715 7691 return result;
9a799d71
AK		 7692}
7693
7694/**
7695 * ixgbe_io_resume - called when traffic can start flowing again.
7696 * @pdev: Pointer to PCI device
7697 *
7698 * This callback is called when the error recovery driver tells us that
7699 * its OK to resume normal operation.
7700 */
7701static void ixgbe_io_resume(struct pci_dev *pdev)
7702{
c60fbb00
AD		 7703 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7704 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7705
7706 if (netif_running(netdev)) {
7707 if (ixgbe_up(adapter)) {
396e799c 7708 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7709 return;
7710 }
7711 }
7712
7713 netif_device_attach(netdev);
9a799d71
AK		 7714}
7715
7716static struct pci_error_handlers ixgbe_err_handler = {
7717 .error_detected = ixgbe_io_error_detected,
7718 .slot_reset = ixgbe_io_slot_reset,
7719 .resume = ixgbe_io_resume,
7720};
7721
7722static struct pci_driver ixgbe_driver = {
7723 .name = ixgbe_driver_name,
7724 .id_table = ixgbe_pci_tbl,
7725 .probe = ixgbe_probe,
7726 .remove = __devexit_p(ixgbe_remove),
7727#ifdef CONFIG_PM
7728 .suspend = ixgbe_suspend,
7729 .resume = ixgbe_resume,
7730#endif
7731 .shutdown = ixgbe_shutdown,
7732 .err_handler = &ixgbe_err_handler
7733};
7734
7735/**
7736 * ixgbe_init_module - Driver Registration Routine
7737 *
7738 * ixgbe_init_module is the first routine called when the driver is
7739 * loaded. All it does is register with the PCI subsystem.
7740 **/
7741static int __init ixgbe_init_module(void)
7742{
7743 int ret;
c7689578 7744 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7745 pr_info("%s\n", ixgbe_copyright);
9a799d71 7746
5dd2d332 7747#ifdef CONFIG_IXGBE_DCA
bd0362dd 7748 dca_register_notify(&dca_notifier);
bd0362dd 7749#endif
5dd2d332 7750
9a799d71
AK		 7751 ret = pci_register_driver(&ixgbe_driver);
7752 return ret;
7753}
b4617240 7754
9a799d71
AK		 7755module_init(ixgbe_init_module);
7756
7757/**
7758 * ixgbe_exit_module - Driver Exit Cleanup Routine
7759 *
7760 * ixgbe_exit_module is called just before the driver is removed
7761 * from memory.
7762 **/
7763static void __exit ixgbe_exit_module(void)
7764{
5dd2d332 7765#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7766 dca_unregister_notify(&dca_notifier);
7767#endif
9a799d71 7768 pci_unregister_driver(&ixgbe_driver);
1a51502b 7769 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7770}
bd0362dd 7771
5dd2d332 7772#ifdef CONFIG_IXGBE_DCA
bd0362dd 7773static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7774 void *p)
bd0362dd
JC		 7775{
7776 int ret_val;
7777
7778 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7779 __ixgbe_notify_dca);
bd0362dd
JC		 7780
7781 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7782}
b453368d 7783
5dd2d332 7784#endif /* CONFIG_IXGBE_DCA */
849c4542 7785
9a799d71
AK		 7786module_exit(ixgbe_exit_module);
7787
7788/* ixgbe_main.c */
Linux kernel - Deliverables
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