projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: Add skb_inner_transport_offset function
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
67359c3c 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
9a799d71
AK		 68
69char ixgbe_driver_name[] = "ixgbe";
9c8eb720 70static const char ixgbe_driver_string[] =
e8e9f696 71 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 72#ifdef IXGBE_FCOE
ea81875a
NP		 73char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 75#else
76static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78#endif
21dd5601 79#define DRV_VERSION "4.2.1-k"
9c8eb720 80const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 81static const char ixgbe_copyright[] =
67359c3c 82 "Copyright (c) 1999-2015 Intel Corporation.";
9a799d71 83
f44e751b
DS		 84static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
85
9a799d71 86static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 87 [board_82598] = &ixgbe_82598_info,
88 [board_82599] = &ixgbe_82599_info,
89 [board_X540] = &ixgbe_X540_info,
90 [board_X550] = &ixgbe_X550_info,
91 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 92};
93
94/* ixgbe_pci_tbl - PCI Device ID Table
95 *
96 * Wildcard entries (PCI_ANY_ID) should come last
97 * Last entry must be all 0s
98 *
99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
100 * Class, Class Mask, private data (not used) }
101 */
9baa3c34 102static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
9a799d71
AK		 138 /* required last entry */
139 {0, }
140};
141MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
142
5dd2d332 143#ifdef CONFIG_IXGBE_DCA
bd0362dd 144static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 145 void *p);
bd0362dd
JC		 146static struct notifier_block dca_notifier = {
147 .notifier_call = ixgbe_notify_dca,
148 .next = NULL,
149 .priority = 0
150};
151#endif
152
1cdd1ec8
GR		 153#ifdef CONFIG_PCI_IOV
154static unsigned int max_vfs;
155module_param(max_vfs, uint, 0);
e8e9f696 156MODULE_PARM_DESC(max_vfs,
170e8543 157 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 158#endif /* CONFIG_PCI_IOV */
159
8ef78adc
PWJ		 160static unsigned int allow_unsupported_sfp;
161module_param(allow_unsupported_sfp, uint, 0);
162MODULE_PARM_DESC(allow_unsupported_sfp,
163 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
164
b3f4d599 165#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
166static int debug = -1;
167module_param(debug, int, 0);
168MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
169
9a799d71
AK		 170MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
171MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
172MODULE_LICENSE("GPL");
173MODULE_VERSION(DRV_VERSION);
174
780484d8
MR		 175static struct workqueue_struct *ixgbe_wq;
176
14438464
MR		 177static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
178
b8e82001
JK		 179static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
180 u32 reg, u16 *value)
181{
b8e82001
JK		 182 struct pci_dev *parent_dev;
183 struct pci_bus *parent_bus;
184
185 parent_bus = adapter->pdev->bus->parent;
186 if (!parent_bus)
187 return -1;
188
189 parent_dev = parent_bus->self;
190 if (!parent_dev)
191 return -1;
192
c0798edf 193 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 194 return -1;
195
c0798edf 196 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 197 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
199 return -1;
b8e82001
JK		 200 return 0;
201}
202
203static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
204{
205 struct ixgbe_hw *hw = &adapter->hw;
206 u16 link_status = 0;
207 int err;
208
209 hw->bus.type = ixgbe_bus_type_pci_express;
210
211 /* Get the negotiated link width and speed from PCI config space of the
212 * parent, as this device is behind a switch
213 */
214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
215
216 /* assume caller will handle error case */
217 if (err)
218 return err;
219
220 hw->bus.width = ixgbe_convert_bus_width(link_status);
221 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
222
223 return 0;
224}
225
e027d1ae
JK		 226/**
227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
228 * @hw: hw specific details
229 *
230 * This function is used by probe to determine whether a device's PCI-Express
231 * bandwidth details should be gathered from the parent bus instead of from the
232 * device. Used to ensure that various locations all have the correct device ID
233 * checks.
234 */
235static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
236{
237 switch (hw->device_id) {
238 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 239 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 240 return true;
241 default:
242 return false;
243 }
244}
245
246static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
247 int expected_gts)
248{
f9328bc6 249 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 250 int max_gts = 0;
251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
253 struct pci_dev *pdev;
254
f9328bc6
DS		 255 /* Some devices are not connected over PCIe and thus do not negotiate
256 * speed. These devices do not have valid bus info, and thus any report
257 * we generate may not be correct.
258 */
259 if (hw->bus.type == ixgbe_bus_type_internal)
260 return;
261
56d1392f 262 /* determine whether to use the parent device */
e027d1ae
JK		 263 if (ixgbe_pcie_from_parent(&adapter->hw))
264 pdev = adapter->pdev->bus->parent->self;
265 else
266 pdev = adapter->pdev;
267
268 if (pcie_get_minimum_link(pdev, &speed, &width) ||
269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
270 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
271 return;
272 }
273
274 switch (speed) {
275 case PCIE_SPEED_2_5GT:
276 /* 8b/10b encoding reduces max throughput by 20% */
277 max_gts = 2 * width;
278 break;
279 case PCIE_SPEED_5_0GT:
280 /* 8b/10b encoding reduces max throughput by 20% */
281 max_gts = 4 * width;
282 break;
283 case PCIE_SPEED_8_0GT:
9f0a433c 284 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 285 max_gts = 8 * width;
286 break;
287 default:
288 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
289 return;
290 }
291
292 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
293 max_gts);
294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
298 "Unknown"),
299 width,
300 (speed == PCIE_SPEED_2_5GT ? "20%" :
301 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 302 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 303 "Unknown"));
304
305 if (max_gts < expected_gts) {
306 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
308 expected_gts);
309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
310 }
311}
312
7086400d
AD		 313static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
314{
315 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 316 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 318 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 319}
320
2a1a091c
MR		 321static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
322{
323 struct ixgbe_adapter *adapter = hw->back;
324
325 if (!hw->hw_addr)
326 return;
327 hw->hw_addr = NULL;
328 e_dev_err("Adapter removed\n");
58cf663f
MR		 329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
330 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 331}
332
f8e2472f 333static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 334{
335 u32 value;
336
337 /* The following check not only optimizes a bit by not
338 * performing a read on the status register when the
339 * register just read was a status register read that
340 * returned IXGBE_FAILED_READ_REG. It also blocks any
341 * potential recursion.
342 */
343 if (reg == IXGBE_STATUS) {
344 ixgbe_remove_adapter(hw);
345 return;
346 }
347 value = ixgbe_read_reg(hw, IXGBE_STATUS);
348 if (value == IXGBE_FAILED_READ_REG)
349 ixgbe_remove_adapter(hw);
350}
351
f8e2472f
MR		 352/**
353 * ixgbe_read_reg - Read from device register
354 * @hw: hw specific details
355 * @reg: offset of register to read
356 *
357 * Returns : value read or IXGBE_FAILED_READ_REG if removed
358 *
359 * This function is used to read device registers. It checks for device
360 * removal by confirming any read that returns all ones by checking the
361 * status register value for all ones. This function avoids reading from
362 * the hardware if a removal was previously detected in which case it
363 * returns IXGBE_FAILED_READ_REG (all ones).
364 */
365u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
366{
367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
368 u32 value;
369
370 if (ixgbe_removed(reg_addr))
371 return IXGBE_FAILED_READ_REG;
372 value = readl(reg_addr + reg);
373 if (unlikely(value == IXGBE_FAILED_READ_REG))
374 ixgbe_check_remove(hw, reg);
375 return value;
376}
377
14438464
MR		 378static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
379{
380 u16 value;
381
382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
383 if (value == IXGBE_FAILED_READ_CFG_WORD) {
384 ixgbe_remove_adapter(hw);
385 return true;
386 }
387 return false;
388}
389
390u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
391{
392 struct ixgbe_adapter *adapter = hw->back;
393 u16 value;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return IXGBE_FAILED_READ_CFG_WORD;
397 pci_read_config_word(adapter->pdev, reg, &value);
398 if (value == IXGBE_FAILED_READ_CFG_WORD &&
399 ixgbe_check_cfg_remove(hw, adapter->pdev))
400 return IXGBE_FAILED_READ_CFG_WORD;
401 return value;
402}
403
404#ifdef CONFIG_PCI_IOV
405static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
406{
407 struct ixgbe_adapter *adapter = hw->back;
408 u32 value;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return IXGBE_FAILED_READ_CFG_DWORD;
412 pci_read_config_dword(adapter->pdev, reg, &value);
413 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
414 ixgbe_check_cfg_remove(hw, adapter->pdev))
415 return IXGBE_FAILED_READ_CFG_DWORD;
416 return value;
417}
418#endif /* CONFIG_PCI_IOV */
419
ed19231c
JK		 420void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
421{
422 struct ixgbe_adapter *adapter = hw->back;
423
424 if (ixgbe_removed(hw->hw_addr))
425 return;
426 pci_write_config_word(adapter->pdev, reg, value);
427}
428
7086400d
AD		 429static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
430{
431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
432
52f33af8 433 /* flush memory to make sure state is correct before next watchdog */
4e857c58 434 smp_mb__before_atomic();
7086400d
AD		 435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
436}
437
dcd79aeb
TI		 438struct ixgbe_reg_info {
439 u32 ofs;
440 char *name;
441};
442
443static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
444
445 /* General Registers */
446 {IXGBE_CTRL, "CTRL"},
447 {IXGBE_STATUS, "STATUS"},
448 {IXGBE_CTRL_EXT, "CTRL_EXT"},
449
450 /* Interrupt Registers */
451 {IXGBE_EICR, "EICR"},
452
453 /* RX Registers */
454 {IXGBE_SRRCTL(0), "SRRCTL"},
455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
456 {IXGBE_RDLEN(0), "RDLEN"},
457 {IXGBE_RDH(0), "RDH"},
458 {IXGBE_RDT(0), "RDT"},
459 {IXGBE_RXDCTL(0), "RXDCTL"},
460 {IXGBE_RDBAL(0), "RDBAL"},
461 {IXGBE_RDBAH(0), "RDBAH"},
462
463 /* TX Registers */
464 {IXGBE_TDBAL(0), "TDBAL"},
465 {IXGBE_TDBAH(0), "TDBAH"},
466 {IXGBE_TDLEN(0), "TDLEN"},
467 {IXGBE_TDH(0), "TDH"},
468 {IXGBE_TDT(0), "TDT"},
469 {IXGBE_TXDCTL(0), "TXDCTL"},
470
471 /* List Terminator */
ca8dfe25 472 { .name = NULL }
dcd79aeb
TI		 473};
474
475
476/*
477 * ixgbe_regdump - register printout routine
478 */
479static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
480{
481 int i = 0, j = 0;
482 char rname[16];
483 u32 regs[64];
484
485 switch (reginfo->ofs) {
486 case IXGBE_SRRCTL(0):
487 for (i = 0; i < 64; i++)
488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
489 break;
490 case IXGBE_DCA_RXCTRL(0):
491 for (i = 0; i < 64; i++)
492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
493 break;
494 case IXGBE_RDLEN(0):
495 for (i = 0; i < 64; i++)
496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
497 break;
498 case IXGBE_RDH(0):
499 for (i = 0; i < 64; i++)
500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
501 break;
502 case IXGBE_RDT(0):
503 for (i = 0; i < 64; i++)
504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
505 break;
506 case IXGBE_RXDCTL(0):
507 for (i = 0; i < 64; i++)
508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
509 break;
510 case IXGBE_RDBAL(0):
511 for (i = 0; i < 64; i++)
512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
513 break;
514 case IXGBE_RDBAH(0):
515 for (i = 0; i < 64; i++)
516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
517 break;
518 case IXGBE_TDBAL(0):
519 for (i = 0; i < 64; i++)
520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
521 break;
522 case IXGBE_TDBAH(0):
523 for (i = 0; i < 64; i++)
524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
525 break;
526 case IXGBE_TDLEN(0):
527 for (i = 0; i < 64; i++)
528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
529 break;
530 case IXGBE_TDH(0):
531 for (i = 0; i < 64; i++)
532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
533 break;
534 case IXGBE_TDT(0):
535 for (i = 0; i < 64; i++)
536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
537 break;
538 case IXGBE_TXDCTL(0):
539 for (i = 0; i < 64; i++)
540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
541 break;
542 default:
c7689578 543 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 544 IXGBE_READ_REG(hw, reginfo->ofs));
545 return;
546 }
547
548 for (i = 0; i < 8; i++) {
549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 550 pr_err("%-15s", rname);
dcd79aeb 551 for (j = 0; j < 8; j++)
c7689578
JP		 552 pr_cont(" %08x", regs[i*8+j]);
553 pr_cont("\n");
dcd79aeb
TI		 554 }
555
556}
557
558/*
559 * ixgbe_dump - Print registers, tx-rings and rx-rings
560 */
561static void ixgbe_dump(struct ixgbe_adapter *adapter)
562{
563 struct net_device *netdev = adapter->netdev;
564 struct ixgbe_hw *hw = &adapter->hw;
565 struct ixgbe_reg_info *reginfo;
566 int n = 0;
567 struct ixgbe_ring *tx_ring;
729739b7 568 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 569 union ixgbe_adv_tx_desc *tx_desc;
570 struct my_u0 { u64 a; u64 b; } *u0;
571 struct ixgbe_ring *rx_ring;
572 union ixgbe_adv_rx_desc *rx_desc;
573 struct ixgbe_rx_buffer *rx_buffer_info;
574 u32 staterr;
575 int i = 0;
576
577 if (!netif_msg_hw(adapter))
578 return;
579
580 /* Print netdevice Info */
581 if (netdev) {
582 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 583 pr_info("Device Name state "
dcd79aeb 584 "trans_start last_rx\n");
c7689578
JP		 585 pr_info("%-15s %016lX %016lX %016lX\n",
586 netdev->name,
587 netdev->state,
588 netdev->trans_start,
589 netdev->last_rx);
dcd79aeb
TI		 590 }
591
592 /* Print Registers */
593 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 594 pr_info(" Register Name Value\n");
dcd79aeb
TI		 595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
596 reginfo->name; reginfo++) {
597 ixgbe_regdump(hw, reginfo);
598 }
599
600 /* Print TX Ring Summary */
601 if (!netdev || !netif_running(netdev))
e90dd264 602 return;
dcd79aeb
TI		 603
604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 605 pr_info(" %s %s %s %s\n",
606 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
607 "leng", "ntw", "timestamp");
dcd79aeb
TI		 608 for (n = 0; n < adapter->num_tx_queues; n++) {
609 tx_ring = adapter->tx_ring[n];
729739b7 610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 612 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 613 (u64)dma_unmap_addr(tx_buffer, dma),
614 dma_unmap_len(tx_buffer, len),
615 tx_buffer->next_to_watch,
616 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
39ac868a 627 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
39ac868a 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
dcd79aeb
TI		 658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 tx_ring = adapter->tx_ring[n];
c7689578
JP		 662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
664 pr_info("------------------------------------\n");
8ad88e37
JH		 665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 669
670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 671 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 672 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 673 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
676 i,
677 le64_to_cpu(u0->a),
678 le64_to_cpu(u0->b),
679 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 680 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 681 tx_buffer->next_to_watch,
682 (u64)tx_buffer->time_stamp,
683 tx_buffer->skb);
684 if (i == tx_ring->next_to_use &&
685 i == tx_ring->next_to_clean)
686 pr_cont(" NTC/U\n");
687 else if (i == tx_ring->next_to_use)
688 pr_cont(" NTU\n");
689 else if (i == tx_ring->next_to_clean)
690 pr_cont(" NTC\n");
691 else
692 pr_cont("\n");
693
694 if (netif_msg_pktdata(adapter) &&
695 tx_buffer->skb)
696 print_hex_dump(KERN_INFO, "",
697 DUMP_PREFIX_ADDRESS, 16, 1,
698 tx_buffer->skb->data,
699 dma_unmap_len(tx_buffer, len),
700 true);
701 }
dcd79aeb
TI		 702 }
703 }
704
705 /* Print RX Rings Summary */
706rx_ring_summary:
707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 708 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 709 for (n = 0; n < adapter->num_rx_queues; n++) {
710 rx_ring = adapter->rx_ring[n];
c7689578
JP		 711 pr_info("%5d %5X %5X\n",
712 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 713 }
714
715 /* Print RX Rings */
716 if (!netif_msg_rx_status(adapter))
e90dd264 717 return;
dcd79aeb
TI		 718
719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
720
39ac868a
JH		 721 /* Receive Descriptor Formats
722 *
723 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 724 * 63 1 0
725 * +-----------------------------------------------------+
726 * 0 | Packet Buffer Address [63:1] |A0/NSE|
727 * +----------------------------------------------+------+
728 * 8 | Header Buffer Address [63:1] | DD |
729 * +-----------------------------------------------------+
730 *
731 *
39ac868a 732 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 733 *
734 * 63 48 47 32 31 30 21 20 16 15 4 3 0
735 * +------------------------------------------------------+
39ac868a
JH		 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
737 * | Packet | IP | | | | Type | Type |
738 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 739 * +------------------------------------------------------+
740 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
741 * +------------------------------------------------------+
742 * 63 48 47 32 31 20 19 0
39ac868a
JH		 743 *
744 * 82599+ Advanced Receive Descriptor (Read) Format
745 * 63 1 0
746 * +-----------------------------------------------------+
747 * 0 | Packet Buffer Address [63:1] |A0/NSE|
748 * +----------------------------------------------+------+
749 * 8 | Header Buffer Address [63:1] | DD |
750 * +-----------------------------------------------------+
751 *
752 *
753 * 82599+ Advanced Receive Descriptor (Write-Back) Format
754 *
755 * 63 48 47 32 31 30 21 20 17 16 4 3 0
756 * +------------------------------------------------------+
757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
759 * |/ Flow Dir Flt ID | | | | | |
760 * +------------------------------------------------------+
761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
762 * +------------------------------------------------------+
763 * 63 48 47 32 31 20 19 0
dcd79aeb 764 */
39ac868a 765
dcd79aeb
TI		 766 for (n = 0; n < adapter->num_rx_queues; n++) {
767 rx_ring = adapter->rx_ring[n];
c7689578
JP		 768 pr_info("------------------------------------\n");
769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
770 pr_info("------------------------------------\n");
8ad88e37
JH		 771 pr_info("%s%s%s",
772 "R [desc] [ PktBuf A0] ",
773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 774 "<-- Adv Rx Read format\n");
8ad88e37
JH		 775 pr_info("%s%s%s",
776 "RWB[desc] [PcsmIpSHl PtRs] ",
777 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 778 "<-- Adv Rx Write-Back format\n");
779
780 for (i = 0; i < rx_ring->count; i++) {
781 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 782 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 783 u0 = (struct my_u0 *)rx_desc;
784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
785 if (staterr & IXGBE_RXD_STAT_DD) {
786 /* Descriptor Done */
c7689578 787 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 788 "%016llX ---------------- %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 rx_buffer_info->skb);
792 } else {
c7689578 793 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 794 "%016llX %016llX %p", i,
795 le64_to_cpu(u0->a),
796 le64_to_cpu(u0->b),
797 (u64)rx_buffer_info->dma,
798 rx_buffer_info->skb);
799
9c50c035
ET		 800 if (netif_msg_pktdata(adapter) &&
801 rx_buffer_info->dma) {
dcd79aeb
TI		 802 print_hex_dump(KERN_INFO, "",
803 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 804 page_address(rx_buffer_info->page) +
805 rx_buffer_info->page_offset,
f800326d 806 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 807 }
808 }
809
810 if (i == rx_ring->next_to_use)
c7689578 811 pr_cont(" NTU\n");
dcd79aeb 812 else if (i == rx_ring->next_to_clean)
c7689578 813 pr_cont(" NTC\n");
dcd79aeb 814 else
c7689578 815 pr_cont("\n");
dcd79aeb
TI		 816
817 }
818 }
dcd79aeb
TI		 819}
820
5eba3699
AV		 821static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
822{
823 u32 ctrl_ext;
824
825 /* Let firmware take over control of h/w */
826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 829}
830
831static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
832{
833 u32 ctrl_ext;
834
835 /* Let firmware know the driver has taken over */
836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 839}
9a799d71 840
49ce9c2c 841/**
e8e26350
PW		 842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
843 * @adapter: pointer to adapter struct
844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
845 * @queue: queue to map the corresponding interrupt to
846 * @msix_vector: the vector to map to the corresponding queue
847 *
848 */
849static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 850 u8 queue, u8 msix_vector)
9a799d71
AK		 851{
852 u32 ivar, index;
e8e26350
PW		 853 struct ixgbe_hw *hw = &adapter->hw;
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
857 if (direction == -1)
858 direction = 0;
859 index = (((direction * 64) + queue) >> 2) & 0x1F;
860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
861 ivar &= ~(0xFF << (8 * (queue & 0x3)));
862 ivar |= (msix_vector << (8 * (queue & 0x3)));
863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
864 break;
865 case ixgbe_mac_82599EB:
b93a2226 866 case ixgbe_mac_X540:
9a75a1ac
DS		 867 case ixgbe_mac_X550:
868 case ixgbe_mac_X550EM_x:
e8e26350
PW		 869 if (direction == -1) {
870 /* other causes */
871 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
872 index = ((queue & 1) * 8);
873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
874 ivar &= ~(0xFF << index);
875 ivar |= (msix_vector << index);
876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
877 break;
878 } else {
879 /* tx or rx causes */
880 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
881 index = ((16 * (queue & 1)) + (8 * direction));
882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
883 ivar &= ~(0xFF << index);
884 ivar |= (msix_vector << index);
885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
886 break;
887 }
888 default:
889 break;
890 }
9a799d71
AK		 891}
892
fe49f04a 893static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 894 u64 qmask)
fe49f04a
AD		 895{
896 u32 mask;
897
bd508178
AD		 898 switch (adapter->hw.mac.type) {
899 case ixgbe_mac_82598EB:
fe49f04a
AD		 900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 902 break;
903 case ixgbe_mac_82599EB:
b93a2226 904 case ixgbe_mac_X540:
9a75a1ac
DS		 905 case ixgbe_mac_X550:
906 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 907 mask = (qmask & 0xFFFFFFFF);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
909 mask = (qmask >> 32);
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 911 break;
912 default:
913 break;
fe49f04a
AD		 914 }
915}
916
729739b7
AD		 917void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
918 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 919{
729739b7
AD		 920 if (tx_buffer->skb) {
921 dev_kfree_skb_any(tx_buffer->skb);
922 if (dma_unmap_len(tx_buffer, len))
d3d00239 923 dma_unmap_single(ring->dev,
729739b7
AD		 924 dma_unmap_addr(tx_buffer, dma),
925 dma_unmap_len(tx_buffer, len),
926 DMA_TO_DEVICE);
927 } else if (dma_unmap_len(tx_buffer, len)) {
928 dma_unmap_page(ring->dev,
929 dma_unmap_addr(tx_buffer, dma),
930 dma_unmap_len(tx_buffer, len),
931 DMA_TO_DEVICE);
e5a43549 932 }
729739b7
AD		 933 tx_buffer->next_to_watch = NULL;
934 tx_buffer->skb = NULL;
935 dma_unmap_len_set(tx_buffer, len, 0);
936 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 937}
938
943561d3 939static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 940{
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 943 int i;
943561d3 944 u32 data;
c84d324c 945
943561d3
AD		 946 if ((hw->fc.current_mode != ixgbe_fc_full) &&
947 (hw->fc.current_mode != ixgbe_fc_rx_pause))
948 return;
c84d324c 949
943561d3
AD		 950 switch (hw->mac.type) {
951 case ixgbe_mac_82598EB:
952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
953 break;
954 default:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
956 }
957 hwstats->lxoffrxc += data;
c84d324c 958
943561d3
AD		 959 /* refill credits (no tx hang) if we received xoff */
960 if (!data)
c84d324c 961 return;
943561d3
AD		 962
963 for (i = 0; i < adapter->num_tx_queues; i++)
964 clear_bit(__IXGBE_HANG_CHECK_ARMED,
965 &adapter->tx_ring[i]->state);
966}
967
968static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
969{
970 struct ixgbe_hw *hw = &adapter->hw;
971 struct ixgbe_hw_stats *hwstats = &adapter->stats;
972 u32 xoff[8] = {0};
2afaa00d 973 u8 tc;
943561d3
AD		 974 int i;
975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
976
977 if (adapter->ixgbe_ieee_pfc)
978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
979
980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
981 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 982 return;
943561d3 983 }
c84d324c
JF		 984
985 /* update stats for each tc, only valid with PFC enabled */
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 987 u32 pxoffrxc;
988
c84d324c
JF		 989 switch (hw->mac.type) {
990 case ixgbe_mac_82598EB:
2afaa00d 991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 992 break;
c84d324c 993 default:
2afaa00d 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 995 }
2afaa00d
PN		 996 hwstats->pxoffrxc[i] += pxoffrxc;
997 /* Get the TC for given UP */
998 tc = netdev_get_prio_tc_map(adapter->netdev, i);
999 xoff[tc] += pxoffrxc;
c84d324c
JF		 1000 }
1001
1002 /* disarm tx queues that have received xoff frames */
1003 for (i = 0; i < adapter->num_tx_queues; i++) {
1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1005
2afaa00d 1006 tc = tx_ring->dcb_tc;
c84d324c
JF		 1007 if (xoff[tc])
1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1009 }
26f23d82
YZ		 1010}
1011
c84d324c 1012static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1013{
7d7ce682 1014 return ring->stats.packets;
c84d324c
JF		 1015}
1016
1017static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1018{
2a47fa45
JF		 1019 struct ixgbe_adapter *adapter;
1020 struct ixgbe_hw *hw;
1021 u32 head, tail;
1022
1023 if (ring->l2_accel_priv)
1024 adapter = ring->l2_accel_priv->real_adapter;
1025 else
1026 adapter = netdev_priv(ring->netdev);
e01c31a5 1027
2a47fa45
JF		 1028 hw = &adapter->hw;
1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1031
1032 if (head != tail)
1033 return (head < tail) ?
1034 tail - head : (tail + ring->count - head);
1035
1036 return 0;
1037}
1038
1039static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1040{
1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1044
7d637bcc 1045 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1046
1047 /*
1048 * Check for a hung queue, but be thorough. This verifies
1049 * that a transmit has been completed since the previous
1050 * check AND there is at least one packet pending. The
1051 * ARMED bit is set to indicate a potential hang. The
1052 * bit is cleared if a pause frame is received to remove
1053 * false hang detection due to PFC or 802.3x frames. By
1054 * requiring this to fail twice we avoid races with
1055 * pfc clearing the ARMED bit and conditions where we
1056 * run the check_tx_hang logic with a transmit completion
1057 * pending but without time to complete it yet.
1058 */
e90dd264 1059 if (tx_done_old == tx_done && tx_pending)
c84d324c 1060 /* make sure it is true for two checks in a row */
e90dd264
MR		 1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1062 &tx_ring->state);
1063 /* update completed stats and continue */
1064 tx_ring->tx_stats.tx_done_old = tx_done;
1065 /* reset the countdown */
1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1067
e90dd264 1068 return false;
9a799d71
AK		 1069}
1070
c83c6cbd
AD		 1071/**
1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1073 * @adapter: driver private struct
1074 **/
1075static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1076{
1077
1078 /* Do the reset outside of interrupt context */
1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1081 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1082 ixgbe_service_event_schedule(adapter);
1083 }
1084}
e01c31a5 1085
9a799d71
AK		 1086/**
1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1088 * @q_vector: structure containing interrupt and ring information
e01c31a5 1089 * @tx_ring: tx ring to clean
9a799d71 1090 **/
fe49f04a 1091static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1092 struct ixgbe_ring *tx_ring)
9a799d71 1093{
fe49f04a 1094 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1095 struct ixgbe_tx_buffer *tx_buffer;
1096 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1097 unsigned int total_bytes = 0, total_packets = 0;
59224555 1098 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1099 unsigned int i = tx_ring->next_to_clean;
1100
1101 if (test_bit(__IXGBE_DOWN, &adapter->state))
1102 return true;
9a799d71 1103
d3d00239 1104 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1105 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1106 i -= tx_ring->count;
12207e49 1107
729739b7 1108 do {
d3d00239
AD		 1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1110
1111 /* if next_to_watch is not set then there is no work pending */
1112 if (!eop_desc)
1113 break;
1114
7f83a9e6 1115 /* prevent any other reads prior to eop_desc */
7e63bf49 1116 read_barrier_depends();
7f83a9e6 1117
d3d00239
AD		 1118 /* if DD is not set pending work has not been completed */
1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1120 break;
8ad494b0 1121
d3d00239
AD		 1122 /* clear next_to_watch to prevent false hangs */
1123 tx_buffer->next_to_watch = NULL;
8ad494b0 1124
091a6246
AD		 1125 /* update the statistics for this packet */
1126 total_bytes += tx_buffer->bytecount;
1127 total_packets += tx_buffer->gso_segs;
1128
fd0db0ed 1129 /* free the skb */
fe1f2a97 1130 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1131
729739b7
AD		 1132 /* unmap skb header data */
1133 dma_unmap_single(tx_ring->dev,
1134 dma_unmap_addr(tx_buffer, dma),
1135 dma_unmap_len(tx_buffer, len),
1136 DMA_TO_DEVICE);
1137
fd0db0ed
AD		 1138 /* clear tx_buffer data */
1139 tx_buffer->skb = NULL;
729739b7 1140 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1141
729739b7
AD		 1142 /* unmap remaining buffers */
1143 while (tx_desc != eop_desc) {
d3d00239
AD		 1144 tx_buffer++;
1145 tx_desc++;
8ad494b0 1146 i++;
729739b7
AD		 1147 if (unlikely(!i)) {
1148 i -= tx_ring->count;
d3d00239 1149 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1151 }
e01c31a5 1152
729739b7
AD		 1153 /* unmap any remaining paged data */
1154 if (dma_unmap_len(tx_buffer, len)) {
1155 dma_unmap_page(tx_ring->dev,
1156 dma_unmap_addr(tx_buffer, dma),
1157 dma_unmap_len(tx_buffer, len),
1158 DMA_TO_DEVICE);
1159 dma_unmap_len_set(tx_buffer, len, 0);
1160 }
1161 }
1162
1163 /* move us one more past the eop_desc for start of next pkt */
1164 tx_buffer++;
1165 tx_desc++;
1166 i++;
1167 if (unlikely(!i)) {
1168 i -= tx_ring->count;
1169 tx_buffer = tx_ring->tx_buffer_info;
1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1171 }
1172
1173 /* issue prefetch for next Tx descriptor */
1174 prefetch(tx_desc);
12207e49 1175
729739b7
AD		 1176 /* update budget accounting */
1177 budget--;
1178 } while (likely(budget));
1179
1180 i += tx_ring->count;
9a799d71 1181 tx_ring->next_to_clean = i;
d3d00239 1182 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1183 tx_ring->stats.bytes += total_bytes;
bd198058 1184 tx_ring->stats.packets += total_packets;
d3d00239 1185 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1186 q_vector->tx.total_bytes += total_bytes;
1187 q_vector->tx.total_packets += total_packets;
b953799e 1188
c84d324c
JF		 1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1190 /* schedule immediate reset if we believe we hung */
1191 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1192 e_err(drv, "Detected Tx Unit Hang\n"
1193 " Tx Queue <%d>\n"
1194 " TDH, TDT <%x>, <%x>\n"
1195 " next_to_use <%x>\n"
1196 " next_to_clean <%x>\n"
1197 "tx_buffer_info[next_to_clean]\n"
1198 " time_stamp <%lx>\n"
1199 " jiffies <%lx>\n",
1200 tx_ring->queue_index,
1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1203 tx_ring->next_to_use, i,
1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1205
1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1207
1208 e_info(probe,
1209 "tx hang %d detected on queue %d, resetting adapter\n",
1210 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1211
b953799e 1212 /* schedule immediate reset if we believe we hung */
c83c6cbd 1213 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1214
1215 /* the adapter is about to reset, no point in enabling stuff */
59224555 1216 return true;
b953799e 1217 }
9a799d71 1218
b2d96e0a
AD		 1219 netdev_tx_completed_queue(txring_txq(tx_ring),
1220 total_packets, total_bytes);
1221
e092be60 1222#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1225 /* Make sure that anybody stopping the queue after this
1226 * sees the new next_to_clean.
1227 */
1228 smp_mb();
729739b7
AD		 1229 if (__netif_subqueue_stopped(tx_ring->netdev,
1230 tx_ring->queue_index)
1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1232 netif_wake_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
5b7da515 1234 ++tx_ring->tx_stats.restart_queue;
30eba97a 1235 }
e092be60 1236 }
9a799d71 1237
59224555 1238 return !!budget;
9a799d71
AK		 1239}
1240
5dd2d332 1241#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1242static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1243 struct ixgbe_ring *tx_ring,
33cf09c9 1244 int cpu)
bd0362dd 1245{
33cf09c9 1246 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1247 u32 txctrl = 0;
bdda1a61 1248 u16 reg_offset;
33cf09c9 1249
9de7605e
MR		 1250 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1251 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1252
33cf09c9
AD		 1253 switch (hw->mac.type) {
1254 case ixgbe_mac_82598EB:
bdda1a61 1255 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1256 break;
1257 case ixgbe_mac_82599EB:
b93a2226 1258 case ixgbe_mac_X540:
bdda1a61
AD		 1259 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1260 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1261 break;
1262 default:
bdda1a61
AD		 1263 /* for unknown hardware do not write register */
1264 return;
bd0362dd 1265 }
bdda1a61
AD		 1266
1267 /*
1268 * We can enable relaxed ordering for reads, but not writes when
1269 * DCA is enabled. This is due to a known issue in some chipsets
1270 * which will cause the DCA tag to be cleared.
1271 */
1272 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1273 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1274 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1275
1276 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1277}
1278
bdda1a61
AD		 1279static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1280 struct ixgbe_ring *rx_ring,
33cf09c9 1281 int cpu)
bd0362dd 1282{
33cf09c9 1283 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1284 u32 rxctrl = 0;
bdda1a61
AD		 1285 u8 reg_idx = rx_ring->reg_idx;
1286
9de7605e
MR		 1287 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1288 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1289
1290 switch (hw->mac.type) {
33cf09c9 1291 case ixgbe_mac_82599EB:
b93a2226 1292 case ixgbe_mac_X540:
bdda1a61 1293 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1294 break;
1295 default:
1296 break;
1297 }
bdda1a61
AD		 1298
1299 /*
1300 * We can enable relaxed ordering for reads, but not writes when
1301 * DCA is enabled. This is due to a known issue in some chipsets
1302 * which will cause the DCA tag to be cleared.
1303 */
1304 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1305 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1306 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1307
1308 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1309}
1310
1311static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1312{
1313 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1314 struct ixgbe_ring *ring;
bd0362dd 1315 int cpu = get_cpu();
bd0362dd 1316
33cf09c9
AD		 1317 if (q_vector->cpu == cpu)
1318 goto out_no_update;
1319
a557928e 1320 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1321 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1322
a557928e 1323 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1324 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1325
1326 q_vector->cpu = cpu;
1327out_no_update:
bd0362dd
JC		 1328 put_cpu();
1329}
1330
1331static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1332{
1333 int i;
1334
e35ec126 1335 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1336 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1338 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1339 else
1340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1341 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1342
49c7ffbe 1343 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1344 adapter->q_vector[i]->cpu = -1;
1345 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1346 }
1347}
1348
1349static int __ixgbe_notify_dca(struct device *dev, void *data)
1350{
c60fbb00 1351 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1352 unsigned long event = *(unsigned long *)data;
1353
2a72c31e 1354 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1355 return 0;
1356
bd0362dd
JC		 1357 switch (event) {
1358 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1359 /* if we're already enabled, don't do it again */
1360 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1361 break;
652f093f 1362 if (dca_add_requester(dev) == 0) {
96b0e0f6 1363 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1365 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1366 break;
1367 }
1368 /* Fall Through since DCA is disabled. */
1369 case DCA_PROVIDER_REMOVE:
1370 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1371 dca_remove_requester(dev);
1372 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1373 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1374 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1375 }
1376 break;
1377 }
1378
652f093f 1379 return 0;
bd0362dd 1380}
67a74ee2 1381
bdda1a61 1382#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1383
1384#define IXGBE_RSS_L4_TYPES_MASK \
1385 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1386 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1387 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1388 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1389
8a0da21b
AD		 1390static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1391 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1392 struct sk_buff *skb)
1393{
7edda4b8
FD		 1394 u16 rss_type;
1395
1396 if (!(ring->netdev->features & NETIF_F_RXHASH))
1397 return;
1398
1399 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1400 IXGBE_RXDADV_RSSTYPE_MASK;
1401
1402 if (!rss_type)
1403 return;
1404
1405 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1406 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1407 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1408}
1409
f800326d 1410#ifdef IXGBE_FCOE
ff886dfc
AD		 1411/**
1412 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1413 * @ring: structure containing ring specific data
ff886dfc
AD		 1414 * @rx_desc: advanced rx descriptor
1415 *
1416 * Returns : true if it is FCoE pkt
1417 */
57efd44c 1418static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1419 union ixgbe_adv_rx_desc *rx_desc)
1420{
1421 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1422
57efd44c 1423 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1424 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1425 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1426 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1427}
1428
f800326d 1429#endif /* IXGBE_FCOE */
e59bd25d
AV		 1430/**
1431 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1432 * @ring: structure containing ring specific data
1433 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1434 * @skb: skb currently being received and modified
1435 **/
8a0da21b 1436static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1437 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1438 struct sk_buff *skb)
9a799d71 1439{
3f207800
DS		 1440 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1441 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1442 bool encap_pkt = false;
1443
8a0da21b 1444 skb_checksum_none_assert(skb);
9a799d71 1445
712744be 1446 /* Rx csum disabled */
8a0da21b 1447 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1448 return;
e59bd25d 1449
3f207800
DS		 1450 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1451 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1452 encap_pkt = true;
1453 skb->encapsulation = 1;
3f207800
DS		 1454 }
1455
e59bd25d 1456 /* if IP and error */
f56e0cb1
AD		 1457 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1458 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1459 ring->rx_stats.csum_err++;
9a799d71
AK		 1460 return;
1461 }
e59bd25d 1462
f56e0cb1 1463 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1464 return;
1465
f56e0cb1 1466 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1467 /*
1468 * 82599 errata, UDP frames with a 0 checksum can be marked as
1469 * checksum errors.
1470 */
8a0da21b
AD		 1471 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1472 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1473 return;
1474
8a0da21b 1475 ring->rx_stats.csum_err++;
e59bd25d
AV		 1476 return;
1477 }
1478
9a799d71 1479 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1480 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1481 if (encap_pkt) {
1482 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1483 return;
1484
1485 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1486 ring->rx_stats.csum_err++;
1487 return;
1488 }
1489 /* If we checked the outer header let the stack know */
1490 skb->csum_level = 1;
1491 }
9a799d71
AK		 1492}
1493
f990b79b
AD		 1494static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1495 struct ixgbe_rx_buffer *bi)
1496{
1497 struct page *page = bi->page;
18cb652a 1498 dma_addr_t dma;
f990b79b 1499
f800326d 1500 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1501 if (likely(page))
f990b79b
AD		 1502 return true;
1503
f800326d 1504 /* alloc new page for storage */
18cb652a
AD		 1505 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1506 if (unlikely(!page)) {
1507 rx_ring->rx_stats.alloc_rx_page_failed++;
1508 return false;
f990b79b
AD		 1509 }
1510
f800326d
AD		 1511 /* map page for use */
1512 dma = dma_map_page(rx_ring->dev, page, 0,
1513 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1514
1515 /*
1516 * if mapping failed free memory back to system since
1517 * there isn't much point in holding memory we can't use
1518 */
1519 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1520 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1521
f990b79b
AD		 1522 rx_ring->rx_stats.alloc_rx_page_failed++;
1523 return false;
1524 }
1525
f800326d 1526 bi->dma = dma;
18cb652a 1527 bi->page = page;
afaa9459 1528 bi->page_offset = 0;
f800326d 1529
f990b79b
AD		 1530 return true;
1531}
1532
9a799d71 1533/**
f990b79b 1534 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1535 * @rx_ring: ring to place buffers on
1536 * @cleaned_count: number of buffers to replace
9a799d71 1537 **/
fc77dc3c 1538void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1539{
9a799d71 1540 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1541 struct ixgbe_rx_buffer *bi;
d5f398ed 1542 u16 i = rx_ring->next_to_use;
9a799d71 1543
f800326d
AD		 1544 /* nothing to do */
1545 if (!cleaned_count)
fc77dc3c
AD		 1546 return;
1547
e4f74028 1548 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1549 bi = &rx_ring->rx_buffer_info[i];
1550 i -= rx_ring->count;
9a799d71 1551
f800326d
AD		 1552 do {
1553 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1554 break;
d5f398ed 1555
f800326d
AD		 1556 /*
1557 * Refresh the desc even if buffer_addrs didn't change
1558 * because each write-back erases this info.
1559 */
1560 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1561
f990b79b
AD		 1562 rx_desc++;
1563 bi++;
9a799d71 1564 i++;
f990b79b 1565 if (unlikely(!i)) {
e4f74028 1566 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1567 bi = rx_ring->rx_buffer_info;
1568 i -= rx_ring->count;
1569 }
1570
18cb652a
AD		 1571 /* clear the status bits for the next_to_use descriptor */
1572 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1573
1574 cleaned_count--;
1575 } while (cleaned_count);
7c6e0a43 1576
f990b79b
AD		 1577 i += rx_ring->count;
1578
ad435ec6
AD		 1579 if (rx_ring->next_to_use != i) {
1580 rx_ring->next_to_use = i;
1581
1582 /* update next to alloc since we have filled the ring */
1583 rx_ring->next_to_alloc = i;
1584
1585 /* Force memory writes to complete before letting h/w
1586 * know there are new descriptors to fetch. (Only
1587 * applicable for weak-ordered memory model archs,
1588 * such as IA-64).
1589 */
1590 wmb();
1591 writel(i, rx_ring->tail);
1592 }
9a799d71
AK		 1593}
1594
1d2024f6
AD		 1595static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1596 struct sk_buff *skb)
1597{
f800326d 1598 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1599
1600 /* set gso_size to avoid messing up TCP MSS */
1601 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1602 IXGBE_CB(skb)->append_cnt);
96be80ab 1603 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1604}
1605
1606static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1607 struct sk_buff *skb)
1608{
1609 /* if append_cnt is 0 then frame is not RSC */
1610 if (!IXGBE_CB(skb)->append_cnt)
1611 return;
1612
1613 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1614 rx_ring->rx_stats.rsc_flush++;
1615
1616 ixgbe_set_rsc_gso_size(rx_ring, skb);
1617
1618 /* gso_size is computed using append_cnt so always clear it last */
1619 IXGBE_CB(skb)->append_cnt = 0;
1620}
1621
8a0da21b
AD		 1622/**
1623 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1624 * @rx_ring: rx descriptor ring packet is being transacted on
1625 * @rx_desc: pointer to the EOP Rx descriptor
1626 * @skb: pointer to current skb being populated
f8212f97 1627 *
8a0da21b
AD		 1628 * This function checks the ring, descriptor, and packet information in
1629 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1630 * other fields within the skb.
f8212f97 1631 **/
8a0da21b
AD		 1632static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1633 union ixgbe_adv_rx_desc *rx_desc,
1634 struct sk_buff *skb)
f8212f97 1635{
43e95f11 1636 struct net_device *dev = rx_ring->netdev;
a9763f3c 1637 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1638
8a0da21b
AD		 1639 ixgbe_update_rsc_stats(rx_ring, skb);
1640
1641 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1642
8a0da21b
AD		 1643 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1644
a9763f3c
MR		 1645 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1646 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1647
f646968f 1648 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1649 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1650 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1651 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1652 }
1653
8a0da21b 1654 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1655
43e95f11 1656 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1657}
1658
8a0da21b
AD		 1659static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1660 struct sk_buff *skb)
aa80175a 1661{
93f93a44 1662 skb_mark_napi_id(skb, &q_vector->napi);
b4640030 1663 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1664 netif_receive_skb(skb);
8a0da21b 1665 else
856f606e 1666 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1667}
43634e82 1668
f800326d
AD		 1669/**
1670 * ixgbe_is_non_eop - process handling of non-EOP buffers
1671 * @rx_ring: Rx ring being processed
1672 * @rx_desc: Rx descriptor for current buffer
1673 * @skb: Current socket buffer containing buffer in progress
1674 *
1675 * This function updates next to clean. If the buffer is an EOP buffer
1676 * this function exits returning false, otherwise it will place the
1677 * sk_buff in the next buffer to be chained and return true indicating
1678 * that this is in fact a non-EOP buffer.
1679 **/
1680static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1681 union ixgbe_adv_rx_desc *rx_desc,
1682 struct sk_buff *skb)
1683{
1684 u32 ntc = rx_ring->next_to_clean + 1;
1685
1686 /* fetch, update, and store next to clean */
1687 ntc = (ntc < rx_ring->count) ? ntc : 0;
1688 rx_ring->next_to_clean = ntc;
1689
1690 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1691
5a02cbd1
AD		 1692 /* update RSC append count if present */
1693 if (ring_is_rsc_enabled(rx_ring)) {
1694 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1695 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1696
1697 if (unlikely(rsc_enabled)) {
1698 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1699
1700 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1701 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1702
5a02cbd1
AD		 1703 /* update ntc based on RSC value */
1704 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1705 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1706 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1707 }
f800326d
AD		 1708 }
1709
5a02cbd1
AD		 1710 /* if we are the last buffer then there is nothing else to do */
1711 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1712 return false;
1713
f800326d
AD		 1714 /* place skb in next buffer to be received */
1715 rx_ring->rx_buffer_info[ntc].skb = skb;
1716 rx_ring->rx_stats.non_eop_descs++;
1717
1718 return true;
1719}
1720
19861ce2
AD		 1721/**
1722 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1723 * @rx_ring: rx descriptor ring packet is being transacted on
1724 * @skb: pointer to current skb being adjusted
1725 *
1726 * This function is an ixgbe specific version of __pskb_pull_tail. The
1727 * main difference between this version and the original function is that
1728 * this function can make several assumptions about the state of things
1729 * that allow for significant optimizations versus the standard function.
1730 * As a result we can do things like drop a frag and maintain an accurate
1731 * truesize for the skb.
1732 */
1733static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1734 struct sk_buff *skb)
1735{
1736 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1737 unsigned char *va;
1738 unsigned int pull_len;
1739
1740 /*
1741 * it is valid to use page_address instead of kmap since we are
1742 * working with pages allocated out of the lomem pool per
1743 * alloc_page(GFP_ATOMIC)
1744 */
1745 va = skb_frag_address(frag);
1746
1747 /*
1748 * we need the header to contain the greater of either ETH_HLEN or
1749 * 60 bytes if the skb->len is less than 60 for skb_pad.
1750 */
8496e338 1751 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1752
1753 /* align pull length to size of long to optimize memcpy performance */
1754 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1755
1756 /* update all of the pointers */
1757 skb_frag_size_sub(frag, pull_len);
1758 frag->page_offset += pull_len;
1759 skb->data_len -= pull_len;
1760 skb->tail += pull_len;
19861ce2
AD		 1761}
1762
42073d91
AD		 1763/**
1764 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1765 * @rx_ring: rx descriptor ring packet is being transacted on
1766 * @skb: pointer to current skb being updated
1767 *
1768 * This function provides a basic DMA sync up for the first fragment of an
1769 * skb. The reason for doing this is that the first fragment cannot be
1770 * unmapped until we have reached the end of packet descriptor for a buffer
1771 * chain.
1772 */
1773static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1774 struct sk_buff *skb)
1775{
1776 /* if the page was released unmap it, else just sync our portion */
1777 if (unlikely(IXGBE_CB(skb)->page_released)) {
1778 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1779 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1780 IXGBE_CB(skb)->page_released = false;
1781 } else {
1782 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1783
1784 dma_sync_single_range_for_cpu(rx_ring->dev,
1785 IXGBE_CB(skb)->dma,
1786 frag->page_offset,
1787 ixgbe_rx_bufsz(rx_ring),
1788 DMA_FROM_DEVICE);
1789 }
1790 IXGBE_CB(skb)->dma = 0;
1791}
1792
f800326d
AD		 1793/**
1794 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1795 * @rx_ring: rx descriptor ring packet is being transacted on
1796 * @rx_desc: pointer to the EOP Rx descriptor
1797 * @skb: pointer to current skb being fixed
1798 *
1799 * Check for corrupted packet headers caused by senders on the local L2
1800 * embedded NIC switch not setting up their Tx Descriptors right. These
1801 * should be very rare.
1802 *
1803 * Also address the case where we are pulling data in on pages only
1804 * and as such no data is present in the skb header.
1805 *
1806 * In addition if skb is not at least 60 bytes we need to pad it so that
1807 * it is large enough to qualify as a valid Ethernet frame.
1808 *
1809 * Returns true if an error was encountered and skb was freed.
1810 **/
1811static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1812 union ixgbe_adv_rx_desc *rx_desc,
1813 struct sk_buff *skb)
1814{
f800326d 1815 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1816
1817 /* verify that the packet does not have any known errors */
1818 if (unlikely(ixgbe_test_staterr(rx_desc,
1819 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1820 !(netdev->features & NETIF_F_RXALL))) {
1821 dev_kfree_skb_any(skb);
1822 return true;
1823 }
1824
19861ce2 1825 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1826 if (skb_is_nonlinear(skb))
1827 ixgbe_pull_tail(rx_ring, skb);
f800326d 1828
57efd44c
AD		 1829#ifdef IXGBE_FCOE
1830 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1831 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1832 return false;
1833
1834#endif
a94d9e22
AD		 1835 /* if eth_skb_pad returns an error the skb was freed */
1836 if (eth_skb_pad(skb))
1837 return true;
f800326d
AD		 1838
1839 return false;
1840}
1841
f800326d
AD		 1842/**
1843 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1844 * @rx_ring: rx descriptor ring to store buffers on
1845 * @old_buff: donor buffer to have page reused
1846 *
0549ae20 1847 * Synchronizes page for reuse by the adapter
f800326d
AD		 1848 **/
1849static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1850 struct ixgbe_rx_buffer *old_buff)
1851{
1852 struct ixgbe_rx_buffer *new_buff;
1853 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1854
1855 new_buff = &rx_ring->rx_buffer_info[nta];
1856
1857 /* update, and store next to alloc */
1858 nta++;
1859 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1860
1861 /* transfer page from old buffer to new buffer */
18cb652a 1862 *new_buff = *old_buff;
f800326d
AD		 1863
1864 /* sync the buffer for use by the device */
1865 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1866 new_buff->page_offset,
1867 ixgbe_rx_bufsz(rx_ring),
f800326d 1868 DMA_FROM_DEVICE);
f800326d
AD		 1869}
1870
18cb652a
AD		 1871static inline bool ixgbe_page_is_reserved(struct page *page)
1872{
2f064f34 1873 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1874}
1875
f800326d
AD		 1876/**
1877 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1878 * @rx_ring: rx descriptor ring to transact packets on
1879 * @rx_buffer: buffer containing page to add
1880 * @rx_desc: descriptor containing length of buffer written by hardware
1881 * @skb: sk_buff to place the data into
1882 *
0549ae20
AD		 1883 * This function will add the data contained in rx_buffer->page to the skb.
1884 * This is done either through a direct copy if the data in the buffer is
1885 * less than the skb header size, otherwise it will just attach the page as
1886 * a frag to the skb.
1887 *
1888 * The function will then update the page offset if necessary and return
1889 * true if the buffer can be reused by the adapter.
f800326d 1890 **/
0549ae20 1891static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1892 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1893 union ixgbe_adv_rx_desc *rx_desc,
1894 struct sk_buff *skb)
f800326d 1895{
0549ae20
AD		 1896 struct page *page = rx_buffer->page;
1897 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1898#if (PAGE_SIZE < 8192)
0549ae20 1899 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1900#else
1901 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1902 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1903 ixgbe_rx_bufsz(rx_ring);
1904#endif
0549ae20 1905
cf3fe7ac
AD		 1906 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1907 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1908
1909 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1910
18cb652a
AD		 1911 /* page is not reserved, we can reuse buffer as-is */
1912 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1913 return true;
1914
1915 /* this page cannot be reused so discard it */
18cb652a 1916 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1917 return false;
1918 }
1919
0549ae20
AD		 1920 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1921 rx_buffer->page_offset, size, truesize);
1922
09816fbe 1923 /* avoid re-using remote pages */
18cb652a 1924 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1925 return false;
1926
1927#if (PAGE_SIZE < 8192)
1928 /* if we are only owner of page we can reuse it */
1929 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1930 return false;
1931
1932 /* flip page offset to other buffer */
1933 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1934#else
1935 /* move offset up to the next cache line */
1936 rx_buffer->page_offset += truesize;
1937
1938 if (rx_buffer->page_offset > last_offset)
1939 return false;
09816fbe 1940#endif
0549ae20 1941
18cb652a
AD		 1942 /* Even if we own the page, we are not allowed to use atomic_set()
1943 * This would break get_page_unless_zero() users.
1944 */
1945 atomic_inc(&page->_count);
1946
0549ae20 1947 return true;
f800326d
AD		 1948}
1949
18806c9e
AD		 1950static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1951 union ixgbe_adv_rx_desc *rx_desc)
1952{
1953 struct ixgbe_rx_buffer *rx_buffer;
1954 struct sk_buff *skb;
1955 struct page *page;
1956
1957 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1958 page = rx_buffer->page;
1959 prefetchw(page);
1960
1961 skb = rx_buffer->skb;
1962
1963 if (likely(!skb)) {
1964 void *page_addr = page_address(page) +
1965 rx_buffer->page_offset;
1966
1967 /* prefetch first cache line of first page */
1968 prefetch(page_addr);
1969#if L1_CACHE_BYTES < 128
1970 prefetch(page_addr + L1_CACHE_BYTES);
1971#endif
1972
1973 /* allocate a skb to store the frags */
67fd893e
AD		 1974 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1975 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1976 if (unlikely(!skb)) {
1977 rx_ring->rx_stats.alloc_rx_buff_failed++;
1978 return NULL;
1979 }
1980
1981 /*
1982 * we will be copying header into skb->data in
1983 * pskb_may_pull so it is in our interest to prefetch
1984 * it now to avoid a possible cache miss
1985 */
1986 prefetchw(skb->data);
1987
1988 /*
1989 * Delay unmapping of the first packet. It carries the
1990 * header information, HW may still access the header
1991 * after the writeback. Only unmap it when EOP is
1992 * reached
1993 */
1994 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1995 goto dma_sync;
1996
1997 IXGBE_CB(skb)->dma = rx_buffer->dma;
1998 } else {
1999 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2000 ixgbe_dma_sync_frag(rx_ring, skb);
2001
2002dma_sync:
2003 /* we are reusing so sync this buffer for CPU use */
2004 dma_sync_single_range_for_cpu(rx_ring->dev,
2005 rx_buffer->dma,
2006 rx_buffer->page_offset,
2007 ixgbe_rx_bufsz(rx_ring),
2008 DMA_FROM_DEVICE);
18cb652a
AD		 2009
2010 rx_buffer->skb = NULL;
18806c9e
AD		 2011 }
2012
2013 /* pull page into skb */
2014 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2015 /* hand second half of page back to the ring */
2016 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2017 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2018 /* the page has been released from the ring */
2019 IXGBE_CB(skb)->page_released = true;
2020 } else {
2021 /* we are not reusing the buffer so unmap it */
2022 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2023 ixgbe_rx_pg_size(rx_ring),
2024 DMA_FROM_DEVICE);
2025 }
2026
2027 /* clear contents of buffer_info */
18806c9e
AD		 2028 rx_buffer->page = NULL;
2029
2030 return skb;
f800326d
AD		 2031}
2032
2033/**
2034 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2035 * @q_vector: structure containing interrupt and ring information
2036 * @rx_ring: rx descriptor ring to transact packets on
2037 * @budget: Total limit on number of packets to process
2038 *
2039 * This function provides a "bounce buffer" approach to Rx interrupt
2040 * processing. The advantage to this is that on systems that have
2041 * expensive overhead for IOMMU access this provides a means of avoiding
2042 * it by maintaining the mapping of the page to the syste.
2043 *
5a85e737 2044 * Returns amount of work completed
f800326d 2045 **/
5a85e737 2046static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2047 struct ixgbe_ring *rx_ring,
f4de00ed 2048 const int budget)
9a799d71 2049{
d2f4fbe2 2050 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2051#ifdef IXGBE_FCOE
f800326d 2052 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2053 int ddp_bytes;
2054 unsigned int mss = 0;
3d8fd385 2055#endif /* IXGBE_FCOE */
f800326d 2056 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2057
fdabfc8a 2058 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2059 union ixgbe_adv_rx_desc *rx_desc;
2060 struct sk_buff *skb;
f800326d
AD		 2061
2062 /* return some buffers to hardware, one at a time is too slow */
2063 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2064 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2065 cleaned_count = 0;
2066 }
2067
18806c9e 2068 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2069
124b74c1 2070 if (!rx_desc->wb.upper.status_error)
f800326d 2071 break;
9a799d71 2072
124b74c1 2073 /* This memory barrier is needed to keep us from reading
f800326d 2074 * any other fields out of the rx_desc until we know the
124b74c1 2075 * descriptor has been written back
f800326d 2076 */
124b74c1 2077 dma_rmb();
9a799d71 2078
18806c9e
AD		 2079 /* retrieve a buffer from the ring */
2080 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2081
18806c9e
AD		 2082 /* exit if we failed to retrieve a buffer */
2083 if (!skb)
2084 break;
9a799d71 2085
9a799d71 2086 cleaned_count++;
f8212f97 2087
f800326d
AD		 2088 /* place incomplete frames back on ring for completion */
2089 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2090 continue;
c267fc16 2091
f800326d
AD		 2092 /* verify the packet layout is correct */
2093 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2094 continue;
9a799d71 2095
d2f4fbe2
AV		 2096 /* probably a little skewed due to removing CRC */
2097 total_rx_bytes += skb->len;
d2f4fbe2 2098
8a0da21b
AD		 2099 /* populate checksum, timestamp, VLAN, and protocol */
2100 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2101
332d4a7d
YZ		 2102#ifdef IXGBE_FCOE
2103 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2104 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2105 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2106 /* include DDPed FCoE data */
2107 if (ddp_bytes > 0) {
2108 if (!mss) {
2109 mss = rx_ring->netdev->mtu -
2110 sizeof(struct fcoe_hdr) -
2111 sizeof(struct fc_frame_header) -
2112 sizeof(struct fcoe_crc_eof);
2113 if (mss > 512)
2114 mss &= ~511;
2115 }
2116 total_rx_bytes += ddp_bytes;
2117 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2118 mss);
2119 }
63d635b2
AD		 2120 if (!ddp_bytes) {
2121 dev_kfree_skb_any(skb);
f800326d 2122 continue;
63d635b2 2123 }
3d8fd385 2124 }
f800326d 2125
332d4a7d 2126#endif /* IXGBE_FCOE */
8a0da21b 2127 ixgbe_rx_skb(q_vector, skb);
9a799d71 2128
f800326d 2129 /* update budget accounting */
f4de00ed 2130 total_rx_packets++;
fdabfc8a 2131 }
9a799d71 2132
c267fc16
AD		 2133 u64_stats_update_begin(&rx_ring->syncp);
2134 rx_ring->stats.packets += total_rx_packets;
2135 rx_ring->stats.bytes += total_rx_bytes;
2136 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2137 q_vector->rx.total_packets += total_rx_packets;
2138 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2139
5a85e737 2140 return total_rx_packets;
9a799d71
AK		 2141}
2142
e0d1095a 2143#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2144/* must be called with local_bh_disable()d */
2145static int ixgbe_low_latency_recv(struct napi_struct *napi)
2146{
2147 struct ixgbe_q_vector *q_vector =
2148 container_of(napi, struct ixgbe_q_vector, napi);
2149 struct ixgbe_adapter *adapter = q_vector->adapter;
2150 struct ixgbe_ring *ring;
2151 int found = 0;
2152
2153 if (test_bit(__IXGBE_DOWN, &adapter->state))
2154 return LL_FLUSH_FAILED;
2155
2156 if (!ixgbe_qv_lock_poll(q_vector))
2157 return LL_FLUSH_BUSY;
2158
2159 ixgbe_for_each_ring(ring, q_vector->rx) {
2160 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2161#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2162 if (found)
2163 ring->stats.cleaned += found;
2164 else
2165 ring->stats.misses++;
2166#endif
5a85e737
ET		 2167 if (found)
2168 break;
2169 }
2170
2171 ixgbe_qv_unlock_poll(q_vector);
2172
2173 return found;
2174}
e0d1095a 2175#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2176
9a799d71
AK		 2177/**
2178 * ixgbe_configure_msix - Configure MSI-X hardware
2179 * @adapter: board private structure
2180 *
2181 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2182 * interrupts.
2183 **/
2184static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2185{
021230d4 2186 struct ixgbe_q_vector *q_vector;
49c7ffbe 2187 int v_idx;
021230d4 2188 u32 mask;
9a799d71 2189
8e34d1aa
AD		 2190 /* Populate MSIX to EITR Select */
2191 if (adapter->num_vfs > 32) {
2192 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2193 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2194 }
2195
4df10466
JB		 2196 /*
2197 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2198 * corresponding register.
2199 */
49c7ffbe 2200 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2201 struct ixgbe_ring *ring;
7a921c93 2202 q_vector = adapter->q_vector[v_idx];
021230d4 2203
a557928e 2204 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2205 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2206
a557928e 2207 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2208 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2209
fe49f04a 2210 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2211 }
2212
bd508178
AD		 2213 switch (adapter->hw.mac.type) {
2214 case ixgbe_mac_82598EB:
e8e26350 2215 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2216 v_idx);
bd508178
AD		 2217 break;
2218 case ixgbe_mac_82599EB:
b93a2226 2219 case ixgbe_mac_X540:
9a75a1ac
DS		 2220 case ixgbe_mac_X550:
2221 case ixgbe_mac_X550EM_x:
e8e26350 2222 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2223 break;
bd508178
AD		 2224 default:
2225 break;
2226 }
021230d4
AV		 2227 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2228
41fb9248 2229 /* set up to autoclear timer, and the vectors */
021230d4 2230 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2231 mask &= ~(IXGBE_EIMS_OTHER |
2232 IXGBE_EIMS_MAILBOX |
2233 IXGBE_EIMS_LSC);
2234
021230d4 2235 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2236}
2237
f494e8fa
AV		 2238enum latency_range {
2239 lowest_latency = 0,
2240 low_latency = 1,
2241 bulk_latency = 2,
2242 latency_invalid = 255
2243};
2244
2245/**
2246 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2247 * @q_vector: structure containing interrupt and ring information
2248 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2249 *
2250 * Stores a new ITR value based on packets and byte
2251 * counts during the last interrupt. The advantage of per interrupt
2252 * computation is faster updates and more accurate ITR for the current
2253 * traffic pattern. Constants in this function were computed
2254 * based on theoretical maximum wire speed and thresholds were set based
2255 * on testing data as well as attempting to minimize response time
2256 * while increasing bulk throughput.
2257 * this functionality is controlled by the InterruptThrottleRate module
2258 * parameter (see ixgbe_param.c)
2259 **/
bd198058
AD		 2260static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2261 struct ixgbe_ring_container *ring_container)
f494e8fa 2262{
bd198058
AD		 2263 int bytes = ring_container->total_bytes;
2264 int packets = ring_container->total_packets;
2265 u32 timepassed_us;
621bd70e 2266 u64 bytes_perint;
bd198058 2267 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2268
2269 if (packets == 0)
bd198058 2270 return;
f494e8fa
AV		 2271
2272 /* simple throttlerate management
621bd70e
AD		 2273 * 0-10MB/s lowest (100000 ints/s)
2274 * 10-20MB/s low (20000 ints/s)
8ac34f10 2275 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2276 */
2277 /* what was last interrupt timeslice? */
d5bf4f67 2278 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2279 if (timepassed_us == 0)
2280 return;
2281
f494e8fa
AV		 2282 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2283
2284 switch (itr_setting) {
2285 case lowest_latency:
621bd70e 2286 if (bytes_perint > 10)
bd198058 2287 itr_setting = low_latency;
f494e8fa
AV		 2288 break;
2289 case low_latency:
621bd70e 2290 if (bytes_perint > 20)
bd198058 2291 itr_setting = bulk_latency;
621bd70e 2292 else if (bytes_perint <= 10)
bd198058 2293 itr_setting = lowest_latency;
f494e8fa
AV		 2294 break;
2295 case bulk_latency:
621bd70e 2296 if (bytes_perint <= 20)
bd198058 2297 itr_setting = low_latency;
f494e8fa
AV		 2298 break;
2299 }
2300
bd198058
AD		 2301 /* clear work counters since we have the values we need */
2302 ring_container->total_bytes = 0;
2303 ring_container->total_packets = 0;
2304
2305 /* write updated itr to ring container */
2306 ring_container->itr = itr_setting;
f494e8fa
AV		 2307}
2308
509ee935
JB		 2309/**
2310 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2311 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2312 *
2313 * This function is made to be called by ethtool and by the driver
2314 * when it needs to update EITR registers at runtime. Hardware
2315 * specific quirks/differences are taken care of here.
2316 */
fe49f04a 2317void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2318{
fe49f04a 2319 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2320 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2321 int v_idx = q_vector->v_idx;
5d967eb7 2322 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2323
bd508178
AD		 2324 switch (adapter->hw.mac.type) {
2325 case ixgbe_mac_82598EB:
509ee935
JB		 2326 /* must write high and low 16 bits to reset counter */
2327 itr_reg |= (itr_reg << 16);
bd508178
AD		 2328 break;
2329 case ixgbe_mac_82599EB:
b93a2226 2330 case ixgbe_mac_X540:
9a75a1ac
DS		 2331 case ixgbe_mac_X550:
2332 case ixgbe_mac_X550EM_x:
509ee935
JB		 2333 /*
2334 * set the WDIS bit to not clear the timer bits and cause an
2335 * immediate assertion of the interrupt
2336 */
2337 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2338 break;
2339 default:
2340 break;
509ee935
JB		 2341 }
2342 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2343}
2344
bd198058 2345static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2346{
d5bf4f67 2347 u32 new_itr = q_vector->itr;
bd198058 2348 u8 current_itr;
f494e8fa 2349
bd198058
AD		 2350 ixgbe_update_itr(q_vector, &q_vector->tx);
2351 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2352
08c8833b 2353 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2354
2355 switch (current_itr) {
2356 /* counts and packets in update_itr are dependent on these numbers */
2357 case lowest_latency:
d5bf4f67 2358 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2359 break;
2360 case low_latency:
d5bf4f67 2361 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2362 break;
2363 case bulk_latency:
8ac34f10 2364 new_itr = IXGBE_12K_ITR;
f494e8fa 2365 break;
bd198058
AD		 2366 default:
2367 break;
f494e8fa
AV		 2368 }
2369
d5bf4f67 2370 if (new_itr != q_vector->itr) {
fe49f04a 2371 /* do an exponential smoothing */
d5bf4f67
ET		 2372 new_itr = (10 * new_itr * q_vector->itr) /
2373 ((9 * new_itr) + q_vector->itr);
509ee935 2374
bd198058 2375 /* save the algorithm value here */
5d967eb7 2376 q_vector->itr = new_itr;
fe49f04a
AD		 2377
2378 ixgbe_write_eitr(q_vector);
f494e8fa 2379 }
f494e8fa
AV		 2380}
2381
119fc60a 2382/**
de88eeeb 2383 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2384 * @adapter: pointer to adapter
119fc60a 2385 **/
f0f9778d 2386static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2387{
119fc60a
MC		 2388 struct ixgbe_hw *hw = &adapter->hw;
2389 u32 eicr = adapter->interrupt_event;
2390
f0f9778d 2391 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2392 return;
2393
f0f9778d
AD		 2394 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2395 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2396 return;
2397
2398 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2399
7ca647bd 2400 switch (hw->device_id) {
f0f9778d
AD		 2401 case IXGBE_DEV_ID_82599_T3_LOM:
2402 /*
2403 * Since the warning interrupt is for both ports
2404 * we don't have to check if:
2405 * - This interrupt wasn't for our port.
2406 * - We may have missed the interrupt so always have to
2407 * check if we got a LSC
2408 */
9a900eca 2409 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2410 !(eicr & IXGBE_EICR_LSC))
2411 return;
2412
2413 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2414 u32 speed;
f0f9778d 2415 bool link_up = false;
7ca647bd 2416
3d292265 2417 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2418
f0f9778d
AD		 2419 if (link_up)
2420 return;
2421 }
2422
2423 /* Check if this is not due to overtemp */
2424 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2425 return;
2426
2427 break;
7ca647bd 2428 default:
597f22d6
DS		 2429 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2430 return;
9a900eca 2431 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2432 return;
7ca647bd 2433 break;
119fc60a 2434 }
f44e751b 2435 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2436
2437 adapter->interrupt_event = 0;
119fc60a
MC		 2438}
2439
0befdb3e
JB		 2440static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2441{
2442 struct ixgbe_hw *hw = &adapter->hw;
2443
2444 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2445 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2446 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2447 /* write to clear the interrupt */
9a900eca 2448 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2449 }
2450}
cf8280ee 2451
4f51bf70
JK		 2452static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2453{
9a900eca
DS		 2454 struct ixgbe_hw *hw = &adapter->hw;
2455
4f51bf70
JK		 2456 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2457 return;
2458
2459 switch (adapter->hw.mac.type) {
2460 case ixgbe_mac_82599EB:
2461 /*
2462 * Need to check link state so complete overtemp check
2463 * on service task
2464 */
9a900eca
DS		 2465 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2466 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2467 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2468 adapter->interrupt_event = eicr;
2469 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2470 ixgbe_service_event_schedule(adapter);
2471 return;
2472 }
2473 return;
2474 case ixgbe_mac_X540:
2475 if (!(eicr & IXGBE_EICR_TS))
2476 return;
2477 break;
2478 default:
2479 return;
2480 }
2481
f44e751b 2482 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2483}
2484
45788d2a
DS		 2485static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2486{
2487 switch (hw->mac.type) {
2488 case ixgbe_mac_82598EB:
2489 if (hw->phy.type == ixgbe_phy_nl)
2490 return true;
2491 return false;
2492 case ixgbe_mac_82599EB:
2493 case ixgbe_mac_X550EM_x:
2494 switch (hw->mac.ops.get_media_type(hw)) {
2495 case ixgbe_media_type_fiber:
2496 case ixgbe_media_type_fiber_qsfp:
2497 return true;
2498 default:
2499 return false;
2500 }
2501 default:
2502 return false;
2503 }
2504}
2505
e8e26350
PW		 2506static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2507{
2508 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2509 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2510
4ccc650c
DS		 2511 if (!ixgbe_is_sfp(hw))
2512 return;
2513
2514 /* Later MAC's use different SDP */
2515 if (hw->mac.type >= ixgbe_mac_X540)
2516 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2517
2518 if (eicr & eicr_mask) {
73c4b7cd 2519 /* Clear the interrupt */
4ccc650c 2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2522 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2523 adapter->sfp_poll_time = 0;
7086400d
AD		 2524 ixgbe_service_event_schedule(adapter);
2525 }
73c4b7cd
AD		 2526 }
2527
4ccc650c
DS		 2528 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2529 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2530 /* Clear the interrupt */
9a900eca 2531 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2532 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2533 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2534 ixgbe_service_event_schedule(adapter);
2535 }
e8e26350
PW		 2536 }
2537}
2538
cf8280ee
JB		 2539static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2540{
2541 struct ixgbe_hw *hw = &adapter->hw;
2542
2543 adapter->lsc_int++;
2544 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2545 adapter->link_check_timeout = jiffies;
2546 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2547 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2548 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2549 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2550 }
2551}
2552
fe49f04a
AD		 2553static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2554 u64 qmask)
2555{
2556 u32 mask;
bd508178 2557 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2558
bd508178
AD		 2559 switch (hw->mac.type) {
2560 case ixgbe_mac_82598EB:
fe49f04a 2561 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2562 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2563 break;
2564 case ixgbe_mac_82599EB:
b93a2226 2565 case ixgbe_mac_X540:
9a75a1ac
DS		 2566 case ixgbe_mac_X550:
2567 case ixgbe_mac_X550EM_x:
fe49f04a 2568 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2569 if (mask)
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2571 mask = (qmask >> 32);
bd508178
AD		 2572 if (mask)
2573 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2574 break;
2575 default:
2576 break;
fe49f04a
AD		 2577 }
2578 /* skip the flush */
2579}
2580
2581static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2582 u64 qmask)
fe49f04a
AD		 2583{
2584 u32 mask;
bd508178 2585 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2586
bd508178
AD		 2587 switch (hw->mac.type) {
2588 case ixgbe_mac_82598EB:
fe49f04a 2589 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2590 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2591 break;
2592 case ixgbe_mac_82599EB:
b93a2226 2593 case ixgbe_mac_X540:
9a75a1ac
DS		 2594 case ixgbe_mac_X550:
2595 case ixgbe_mac_X550EM_x:
fe49f04a 2596 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2599 mask = (qmask >> 32);
bd508178
AD		 2600 if (mask)
2601 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2602 break;
2603 default:
2604 break;
fe49f04a
AD		 2605 }
2606 /* skip the flush */
2607}
2608
021230d4 2609/**
2c4af694
AD		 2610 * ixgbe_irq_enable - Enable default interrupt generation settings
2611 * @adapter: board private structure
021230d4 2612 **/
2c4af694
AD		 2613static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2614 bool flush)
9a799d71 2615{
9a900eca 2616 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2617 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2618
2c4af694
AD		 2619 /* don't reenable LSC while waiting for link */
2620 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2621 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2622
2c4af694 2623 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2624 switch (adapter->hw.mac.type) {
2625 case ixgbe_mac_82599EB:
9a900eca 2626 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2627 break;
2628 case ixgbe_mac_X540:
9a75a1ac
DS		 2629 case ixgbe_mac_X550:
2630 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2631 mask |= IXGBE_EIMS_TS;
2632 break;
2633 default:
2634 break;
2635 }
2c4af694 2636 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2637 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2638 switch (adapter->hw.mac.type) {
2639 case ixgbe_mac_82599EB:
9a900eca
DS		 2640 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2641 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2642 /* fall through */
858bc081 2643 case ixgbe_mac_X540:
9a75a1ac
DS		 2644 case ixgbe_mac_X550:
2645 case ixgbe_mac_X550EM_x:
cbd45ec7
MR		 2646 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2647 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2648 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2649 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2650 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2651 mask |= IXGBE_EIMS_MAILBOX;
2652 break;
2653 default:
2654 break;
9a799d71 2655 }
db0677fa 2656
2c4af694
AD		 2657 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2658 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2659 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2660
2c4af694
AD		 2661 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2662 if (queues)
2663 ixgbe_irq_enable_queues(adapter, ~0);
2664 if (flush)
2665 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2666}
2667
2c4af694 2668static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2669{
a65151ba 2670 struct ixgbe_adapter *adapter = data;
9a799d71 2671 struct ixgbe_hw *hw = &adapter->hw;
54037505 2672 u32 eicr;
91281fd3 2673
54037505
DS		 2674 /*
2675 * Workaround for Silicon errata. Use clear-by-write instead
2676 * of clear-by-read. Reading with EICS will return the
2677 * interrupt causes without clearing, which later be done
2678 * with the write to EICR.
2679 */
2680 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2681
2682 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2683 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2684 * the bits are high when ixgbe_msix_other is called. There is a race
2685 * condition otherwise which results in possible performance loss
2686 * especially if the ixgbe_msix_other interrupt is triggering
2687 * consistently (as it would when PPS is turned on for the X540 device)
2688 */
2689 eicr &= 0xFFFF0000;
2690
54037505 2691 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2692
cf8280ee
JB		 2693 if (eicr & IXGBE_EICR_LSC)
2694 ixgbe_check_lsc(adapter);
f0848276 2695
1cdd1ec8
GR		 2696 if (eicr & IXGBE_EICR_MAILBOX)
2697 ixgbe_msg_task(adapter);
efe3d3c8 2698
bd508178
AD		 2699 switch (hw->mac.type) {
2700 case ixgbe_mac_82599EB:
b93a2226 2701 case ixgbe_mac_X540:
9a75a1ac
DS		 2702 case ixgbe_mac_X550:
2703 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2704 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2705 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2706 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2707 ixgbe_service_event_schedule(adapter);
2708 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2709 IXGBE_EICR_GPI_SDP0_X540);
2710 }
d773ce2d
DS		 2711 if (eicr & IXGBE_EICR_ECC) {
2712 e_info(link, "Received ECC Err, initiating reset\n");
2713 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2714 ixgbe_service_event_schedule(adapter);
2715 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2716 }
c4cf55e5
PWJ		 2717 /* Handle Flow Director Full threshold interrupt */
2718 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2719 int reinit_count = 0;
c4cf55e5 2720 int i;
c4cf55e5 2721 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2722 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2723 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2724 &ring->state))
2725 reinit_count++;
2726 }
2727 if (reinit_count) {
2728 /* no more flow director interrupts until after init */
2729 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2730 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2731 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2732 }
2733 }
f0f9778d 2734 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2735 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2736 break;
2737 default:
2738 break;
c4cf55e5 2739 }
f0848276 2740
bd508178 2741 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2742
db0677fa 2743 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2744 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 2745
7086400d 2746 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2747 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2748 ixgbe_irq_enable(adapter, false, false);
f0848276 2749
9a799d71 2750 return IRQ_HANDLED;
f0848276 2751}
91281fd3 2752
4ff7fb12 2753static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2754{
021230d4 2755 struct ixgbe_q_vector *q_vector = data;
91281fd3 2756
9b471446 2757 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2758
4ff7fb12 2759 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 2760 napi_schedule_irqoff(&q_vector->napi);
91281fd3 2761
9a799d71 2762 return IRQ_HANDLED;
91281fd3
AD		 2763}
2764
eb01b975
AD		 2765/**
2766 * ixgbe_poll - NAPI Rx polling callback
2767 * @napi: structure for representing this polling device
2768 * @budget: how many packets driver is allowed to clean
2769 *
2770 * This function is used for legacy and MSI, NAPI mode
2771 **/
8af3c33f 2772int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2773{
2774 struct ixgbe_q_vector *q_vector =
2775 container_of(napi, struct ixgbe_q_vector, napi);
2776 struct ixgbe_adapter *adapter = q_vector->adapter;
2777 struct ixgbe_ring *ring;
32b3e08f 2778 int per_ring_budget, work_done = 0;
eb01b975
AD		 2779 bool clean_complete = true;
2780
2781#ifdef CONFIG_IXGBE_DCA
2782 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2783 ixgbe_update_dca(q_vector);
2784#endif
2785
2786 ixgbe_for_each_ring(ring, q_vector->tx)
2787 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2788
5d6002b7
AD		 2789 /* Exit if we are called by netpoll or busy polling is active */
2790 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
5a85e737
ET		 2791 return budget;
2792
eb01b975
AD		 2793 /* attempt to distribute budget to each queue fairly, but don't allow
2794 * the budget to go below 1 because we'll exit polling */
2795 if (q_vector->rx.count > 1)
2796 per_ring_budget = max(budget/q_vector->rx.count, 1);
2797 else
2798 per_ring_budget = budget;
2799
32b3e08f
JB		 2800 ixgbe_for_each_ring(ring, q_vector->rx) {
2801 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2802 per_ring_budget);
2803
2804 work_done += cleaned;
2805 clean_complete &= (cleaned < per_ring_budget);
2806 }
eb01b975 2807
5a85e737 2808 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2809 /* If all work not completed, return budget and keep polling */
2810 if (!clean_complete)
2811 return budget;
2812
2813 /* all work done, exit the polling mode */
32b3e08f 2814 napi_complete_done(napi, work_done);
eb01b975
AD		 2815 if (adapter->rx_itr_setting & 1)
2816 ixgbe_set_itr(q_vector);
2817 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2818 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2819
2820 return 0;
2821}
2822
021230d4
AV		 2823/**
2824 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2825 * @adapter: board private structure
2826 *
2827 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2828 * interrupts from the kernel.
2829 **/
2830static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2831{
2832 struct net_device *netdev = adapter->netdev;
207867f5 2833 int vector, err;
e8e9f696 2834 int ri = 0, ti = 0;
021230d4 2835
49c7ffbe 2836 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2837 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2838 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2839
4ff7fb12 2840 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2841 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2842 "%s-%s-%d", netdev->name, "TxRx", ri++);
2843 ti++;
2844 } else if (q_vector->rx.ring) {
9fe93afd 2845 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2846 "%s-%s-%d", netdev->name, "rx", ri++);
2847 } else if (q_vector->tx.ring) {
9fe93afd 2848 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2849 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2850 } else {
2851 /* skip this unused q_vector */
2852 continue;
32aa77a4 2853 }
207867f5
AD		 2854 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2855 q_vector->name, q_vector);
9a799d71 2856 if (err) {
396e799c 2857 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2858 "Error: %d\n", err);
021230d4 2859 goto free_queue_irqs;
9a799d71 2860 }
207867f5
AD		 2861 /* If Flow Director is enabled, set interrupt affinity */
2862 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2863 /* assign the mask for this irq */
2864 irq_set_affinity_hint(entry->vector,
de88eeeb 2865 &q_vector->affinity_mask);
207867f5 2866 }
9a799d71
AK		 2867 }
2868
021230d4 2869 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2870 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2871 if (err) {
de88eeeb 2872 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2873 goto free_queue_irqs;
9a799d71
AK		 2874 }
2875
9a799d71
AK		 2876 return 0;
2877
021230d4 2878free_queue_irqs:
207867f5
AD		 2879 while (vector) {
2880 vector--;
2881 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2882 NULL);
2883 free_irq(adapter->msix_entries[vector].vector,
2884 adapter->q_vector[vector]);
2885 }
021230d4
AV		 2886 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2887 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2888 kfree(adapter->msix_entries);
2889 adapter->msix_entries = NULL;
9a799d71
AK		 2890 return err;
2891}
2892
2893/**
021230d4 2894 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2895 * @irq: interrupt number
2896 * @data: pointer to a network interface device structure
9a799d71
AK		 2897 **/
2898static irqreturn_t ixgbe_intr(int irq, void *data)
2899{
a65151ba 2900 struct ixgbe_adapter *adapter = data;
9a799d71 2901 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2902 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2903 u32 eicr;
2904
54037505 2905 /*
24ddd967 2906 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2907 * before the read of EICR.
2908 */
2909 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2910
021230d4 2911 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2912 * therefore no explicit interrupt disable is necessary */
021230d4 2913 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2914 if (!eicr) {
6af3b9eb
ET		 2915 /*
2916 * shared interrupt alert!
f47cf66e 2917 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2918 * have disabled interrupts due to EIAM
2919 * finish the workaround of silicon errata on 82598. Unmask
2920 * the interrupt that we masked before the EICR read.
2921 */
2922 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2923 ixgbe_irq_enable(adapter, true, true);
9a799d71 2924 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2925 }
9a799d71 2926
cf8280ee
JB		 2927 if (eicr & IXGBE_EICR_LSC)
2928 ixgbe_check_lsc(adapter);
021230d4 2929
bd508178
AD		 2930 switch (hw->mac.type) {
2931 case ixgbe_mac_82599EB:
e8e26350 2932 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2933 /* Fall through */
2934 case ixgbe_mac_X540:
9a75a1ac
DS		 2935 case ixgbe_mac_X550:
2936 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2937 if (eicr & IXGBE_EICR_ECC) {
2938 e_info(link, "Received ECC Err, initiating reset\n");
2939 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2940 ixgbe_service_event_schedule(adapter);
2941 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2942 }
4f51bf70 2943 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2944 break;
2945 default:
2946 break;
2947 }
e8e26350 2948
0befdb3e 2949 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2950 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2951 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 2952
b9f6ed2b 2953 /* would disable interrupts here but EIAM disabled it */
ef2662b2 2954 napi_schedule_irqoff(&q_vector->napi);
9a799d71 2955
6af3b9eb
ET		 2956 /*
2957 * re-enable link(maybe) and non-queue interrupts, no flush.
2958 * ixgbe_poll will re-enable the queue interrupts
2959 */
6af3b9eb
ET		 2960 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2961 ixgbe_irq_enable(adapter, false, false);
2962
9a799d71
AK		 2963 return IRQ_HANDLED;
2964}
2965
2966/**
2967 * ixgbe_request_irq - initialize interrupts
2968 * @adapter: board private structure
2969 *
2970 * Attempts to configure interrupts using the best available
2971 * capabilities of the hardware and kernel.
2972 **/
021230d4 2973static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2974{
2975 struct net_device *netdev = adapter->netdev;
021230d4 2976 int err;
9a799d71 2977
4cc6df29 2978 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2979 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2980 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2981 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2982 netdev->name, adapter);
4cc6df29 2983 else
a0607fd3 2984 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2985 netdev->name, adapter);
9a799d71 2986
de88eeeb 2987 if (err)
396e799c 2988 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2989
9a799d71
AK		 2990 return err;
2991}
2992
2993static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2994{
49c7ffbe 2995 int vector;
9a799d71 2996
49c7ffbe
AD		 2997 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2998 free_irq(adapter->pdev->irq, adapter);
2999 return;
3000 }
4cc6df29 3001
49c7ffbe
AD		 3002 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3003 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3004 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3005
49c7ffbe
AD		 3006 /* free only the irqs that were actually requested */
3007 if (!q_vector->rx.ring && !q_vector->tx.ring)
3008 continue;
207867f5 3009
49c7ffbe
AD		 3010 /* clear the affinity_mask in the IRQ descriptor */
3011 irq_set_affinity_hint(entry->vector, NULL);
3012
3013 free_irq(entry->vector, q_vector);
9a799d71 3014 }
49c7ffbe
AD		 3015
3016 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3017}
3018
22d5a71b
JB		 3019/**
3020 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3021 * @adapter: board private structure
3022 **/
3023static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3024{
bd508178
AD		 3025 switch (adapter->hw.mac.type) {
3026 case ixgbe_mac_82598EB:
835462fc 3027 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3028 break;
3029 case ixgbe_mac_82599EB:
b93a2226 3030 case ixgbe_mac_X540:
9a75a1ac
DS		 3031 case ixgbe_mac_X550:
3032 case ixgbe_mac_X550EM_x:
835462fc
NS		 3033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3035 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3036 break;
3037 default:
3038 break;
22d5a71b
JB		 3039 }
3040 IXGBE_WRITE_FLUSH(&adapter->hw);
3041 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3042 int vector;
3043
3044 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3045 synchronize_irq(adapter->msix_entries[vector].vector);
3046
3047 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3048 } else {
3049 synchronize_irq(adapter->pdev->irq);
3050 }
3051}
3052
9a799d71
AK		 3053/**
3054 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3055 *
3056 **/
3057static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3058{
d5bf4f67 3059 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3060
d5bf4f67 3061 ixgbe_write_eitr(q_vector);
9a799d71 3062
e8e26350
PW		 3063 ixgbe_set_ivar(adapter, 0, 0, 0);
3064 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3065
396e799c 3066 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3067}
3068
43e69bf0
AD		 3069/**
3070 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3071 * @adapter: board private structure
3072 * @ring: structure containing ring specific data
3073 *
3074 * Configure the Tx descriptor ring after a reset.
3075 **/
84418e3b
AD		 3076void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3077 struct ixgbe_ring *ring)
43e69bf0
AD		 3078{
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u64 tdba = ring->dma;
2f1860b8 3081 int wait_loop = 10;
b88c6de2 3082 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3083 u8 reg_idx = ring->reg_idx;
43e69bf0 3084
2f1860b8 3085 /* disable queue to avoid issues while updating state */
b88c6de2 3086 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3087 IXGBE_WRITE_FLUSH(hw);
3088
43e69bf0 3089 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3090 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3091 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3092 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3093 ring->count * sizeof(union ixgbe_adv_tx_desc));
3094 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3095 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3096 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3097
b88c6de2
AD		 3098 /*
3099 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3100 * higher than 1 when:
3101 * - ITR is 0 as it could cause false TX hangs
3102 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3103 *
3104 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3105 * to or less than the number of on chip descriptors, which is
3106 * currently 40.
3107 */
67da097e 3108 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3109 txdctl |= (1 << 16); /* WTHRESH = 1 */
3110 else
3111 txdctl |= (8 << 16); /* WTHRESH = 8 */
3112
e954b374
AD		 3113 /*
3114 * Setting PTHRESH to 32 both improves performance
3115 * and avoids a TX hang with DFP enabled
3116 */
b88c6de2
AD		 3117 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3118 32; /* PTHRESH = 32 */
2f1860b8
AD		 3119
3120 /* reinitialize flowdirector state */
39cb681b 3121 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3122 ring->atr_sample_rate = adapter->atr_sample_rate;
3123 ring->atr_count = 0;
3124 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3125 } else {
3126 ring->atr_sample_rate = 0;
3127 }
2f1860b8 3128
fd786b7b
AD		 3129 /* initialize XPS */
3130 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3131 struct ixgbe_q_vector *q_vector = ring->q_vector;
3132
3133 if (q_vector)
2a47fa45 3134 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3135 &q_vector->affinity_mask,
3136 ring->queue_index);
3137 }
3138
c84d324c
JF		 3139 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3140
2f1860b8 3141 /* enable queue */
2f1860b8
AD		 3142 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3143
3144 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3145 if (hw->mac.type == ixgbe_mac_82598EB &&
3146 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3147 return;
3148
3149 /* poll to verify queue is enabled */
3150 do {
032b4325 3151 usleep_range(1000, 2000);
2f1860b8
AD		 3152 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3153 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3154 if (!wait_loop)
3155 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3156}
3157
120ff942
AD		 3158static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3159{
3160 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3161 u32 rttdcs, mtqc;
8b1c0b24 3162 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3163
3164 if (hw->mac.type == ixgbe_mac_82598EB)
3165 return;
3166
3167 /* disable the arbiter while setting MTQC */
3168 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3169 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3170 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3171
3172 /* set transmit pool layout */
671c0adb
AD		 3173 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3174 mtqc = IXGBE_MTQC_VT_ENA;
3175 if (tcs > 4)
3176 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3177 else if (tcs > 1)
3178 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3179 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3180 mtqc |= IXGBE_MTQC_32VF;
3181 else
3182 mtqc |= IXGBE_MTQC_64VF;
3183 } else {
3184 if (tcs > 4)
3185 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3186 else if (tcs > 1)
3187 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3188 else
671c0adb
AD		 3189 mtqc = IXGBE_MTQC_64Q_1PB;
3190 }
120ff942 3191
671c0adb 3192 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3193
671c0adb
AD		 3194 /* Enable Security TX Buffer IFG for multiple pb */
3195 if (tcs) {
3196 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3197 sectx |= IXGBE_SECTX_DCB;
3198 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3199 }
3200
3201 /* re-enable the arbiter */
3202 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3203 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3204}
3205
9a799d71 3206/**
3a581073 3207 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3208 * @adapter: board private structure
3209 *
3210 * Configure the Tx unit of the MAC after a reset.
3211 **/
3212static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3213{
2f1860b8
AD		 3214 struct ixgbe_hw *hw = &adapter->hw;
3215 u32 dmatxctl;
43e69bf0 3216 u32 i;
9a799d71 3217
2f1860b8
AD		 3218 ixgbe_setup_mtqc(adapter);
3219
3220 if (hw->mac.type != ixgbe_mac_82598EB) {
3221 /* DMATXCTL.EN must be before Tx queues are enabled */
3222 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3223 dmatxctl |= IXGBE_DMATXCTL_TE;
3224 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3225 }
3226
9a799d71 3227 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3228 for (i = 0; i < adapter->num_tx_queues; i++)
3229 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3230}
3231
3ebe8fde
AD		 3232static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3233 struct ixgbe_ring *ring)
3234{
3235 struct ixgbe_hw *hw = &adapter->hw;
3236 u8 reg_idx = ring->reg_idx;
3237 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3238
3239 srrctl |= IXGBE_SRRCTL_DROP_EN;
3240
3241 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3242}
3243
3244static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3245 struct ixgbe_ring *ring)
3246{
3247 struct ixgbe_hw *hw = &adapter->hw;
3248 u8 reg_idx = ring->reg_idx;
3249 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3250
3251 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3252
3253 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3254}
3255
3256#ifdef CONFIG_IXGBE_DCB
3257void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3258#else
3259static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3260#endif
3261{
3262 int i;
3263 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3264
3265 if (adapter->ixgbe_ieee_pfc)
3266 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3267
3268 /*
3269 * We should set the drop enable bit if:
3270 * SR-IOV is enabled
3271 * or
3272 * Number of Rx queues > 1 and flow control is disabled
3273 *
3274 * This allows us to avoid head of line blocking for security
3275 * and performance reasons.
3276 */
3277 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3278 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3279 for (i = 0; i < adapter->num_rx_queues; i++)
3280 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3281 } else {
3282 for (i = 0; i < adapter->num_rx_queues; i++)
3283 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3284 }
3285}
3286
e8e26350 3287#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3288
a6616b42 3289static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3290 struct ixgbe_ring *rx_ring)
cc41ac7c 3291{
45e9baa5 3292 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3293 u32 srrctl;
bf29ee6c 3294 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3295
45e9baa5
AD		 3296 if (hw->mac.type == ixgbe_mac_82598EB) {
3297 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3298
45e9baa5
AD		 3299 /*
3300 * if VMDq is not active we must program one srrctl register
3301 * per RSS queue since we have enabled RDRXCTL.MVMEN
3302 */
3303 reg_idx &= mask;
3304 }
cc41ac7c 3305
45e9baa5
AD		 3306 /* configure header buffer length, needed for RSC */
3307 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3308
45e9baa5 3309 /* configure the packet buffer length */
f800326d 3310 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3311
3312 /* configure descriptor type */
f800326d 3313 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3314
45e9baa5 3315 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3316}
9a799d71 3317
dfaf891d 3318/**
a897a2ad 3319 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3320 * @adapter: device handle
3321 *
3322 * - 82598/82599/X540: 128
3323 * - X550(non-SRIOV mode): 512
3324 * - X550(SRIOV mode): 64
3325 */
7f276efb 3326u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3327{
3328 if (adapter->hw.mac.type < ixgbe_mac_X550)
3329 return 128;
3330 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3331 return 64;
3332 else
3333 return 512;
3334}
3335
3336/**
a897a2ad 3337 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3338 * @adapter: device handle
3339 *
3340 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3341 */
1c7cf078 3342void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3343{
dfaf891d 3344 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3345 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3346 u32 reta = 0;
dfaf891d
VZ		 3347 u32 indices_multi;
3348 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3349
0f9b232b 3350 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3351 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3352 * indices.
3353 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3354 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3355 */
3356 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3357 indices_multi = 0x11;
3358 else
3359 indices_multi = 0x1;
3360
dfaf891d
VZ		 3361 /* Write redirection table to HW */
3362 for (i = 0; i < reta_entries; i++) {
3363 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3364 if ((i & 3) == 3) {
3365 if (i < 128)
3366 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3367 else
3368 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3369 reta);
dfaf891d 3370 reta = 0;
0f9b232b
DS		 3371 }
3372 }
3373}
3374
dfaf891d 3375/**
a897a2ad 3376 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3377 * @adapter: device handle
3378 *
3379 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3380 */
3381static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3382{
dfaf891d 3383 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3384 struct ixgbe_hw *hw = &adapter->hw;
3385 u32 vfreta = 0;
dfaf891d
VZ		 3386 unsigned int pf_pool = adapter->num_vfs;
3387
3388 /* Write redirection table to HW */
3389 for (i = 0; i < reta_entries; i++) {
3390 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3391 if ((i & 3) == 3) {
3392 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3393 vfreta);
3394 vfreta = 0;
3395 }
3396 }
3397}
3398
3399static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3400{
3401 struct ixgbe_hw *hw = &adapter->hw;
3402 u32 i, j;
3403 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3404 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3405
3406 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3407 * make full use of any rings they may have. We will use the
3408 * PSRTYPE register to control how many rings we use within the PF.
3409 */
3410 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3411 rss_i = 2;
3412
3413 /* Fill out hash function seeds */
3414 for (i = 0; i < 10; i++)
3415 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3416
3417 /* Fill out redirection table */
3418 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3419
3420 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3421 if (j == rss_i)
3422 j = 0;
3423
3424 adapter->rss_indir_tbl[i] = j;
3425 }
3426
3427 ixgbe_store_reta(adapter);
3428}
3429
3430static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3431{
3432 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3433 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3434 unsigned int pf_pool = adapter->num_vfs;
3435 int i, j;
3436
3437 /* Fill out hash function seeds */
3438 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3439 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3440 adapter->rss_key[i]);
0f9b232b
DS		 3441
3442 /* Fill out the redirection table */
3443 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3444 if (j == rss_i)
05abb126 3445 j = 0;
dfaf891d
VZ		 3446
3447 adapter->rss_indir_tbl[i] = j;
05abb126 3448 }
dfaf891d
VZ		 3449
3450 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3451}
3452
3453static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3454{
3455 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3456 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3457 u32 rxcsum;
0cefafad 3458
05abb126
AD		 3459 /* Disable indicating checksum in descriptor, enables RSS hash */
3460 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3461 rxcsum |= IXGBE_RXCSUM_PCSD;
3462 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3463
671c0adb 3464 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3465 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3466 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3467 } else {
671c0adb
AD		 3468 u8 tcs = netdev_get_num_tc(adapter->netdev);
3469
3470 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3471 if (tcs > 4)
3472 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3473 else if (tcs > 1)
3474 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3475 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3476 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3477 else
671c0adb
AD		 3478 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3479 } else {
3480 if (tcs > 4)
8b1c0b24 3481 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3482 else if (tcs > 1)
3483 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3484 else
3485 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3486 }
0cefafad
JB		 3487 }
3488
05abb126 3489 /* Perform hash on these packet types */
d1b849b9
DS		 3490 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3491 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3492 IXGBE_MRQC_RSS_FIELD_IPV6 |
3493 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3494
ef6afc0c 3495 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3496 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3497 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3498 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3499
dfaf891d 3500 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3501 if ((hw->mac.type >= ixgbe_mac_X550) &&
3502 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3503 unsigned int pf_pool = adapter->num_vfs;
3504
3505 /* Enable VF RSS mode */
3506 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3507 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3508
3509 /* Setup RSS through the VF registers */
dfaf891d 3510 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3511 vfmrqc = IXGBE_MRQC_RSSEN;
3512 vfmrqc |= rss_field;
3513 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3514 } else {
dfaf891d 3515 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3516 mrqc |= rss_field;
3517 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3518 }
0cefafad
JB		 3519}
3520
bb5a9ad2
NS		 3521/**
3522 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3523 * @adapter: address of board private structure
3524 * @index: index of ring to set
bb5a9ad2 3525 **/
082757af 3526static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3527 struct ixgbe_ring *ring)
bb5a9ad2 3528{
bb5a9ad2 3529 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3530 u32 rscctrl;
bf29ee6c 3531 u8 reg_idx = ring->reg_idx;
7367096a 3532
7d637bcc 3533 if (!ring_is_rsc_enabled(ring))
7367096a 3534 return;
bb5a9ad2 3535
7367096a 3536 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3537 rscctrl |= IXGBE_RSCCTL_RSCEN;
3538 /*
3539 * we must limit the number of descriptors so that the
3540 * total size of max desc * buf_len is not greater
642c680e 3541 * than 65536
bb5a9ad2 3542 */
f800326d 3543 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3544 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3545}
3546
9e10e045
AD		 3547#define IXGBE_MAX_RX_DESC_POLL 10
3548static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3549 struct ixgbe_ring *ring)
3550{
3551 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3552 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3553 u32 rxdctl;
bf29ee6c 3554 u8 reg_idx = ring->reg_idx;
9e10e045 3555
b0483c8f
MR		 3556 if (ixgbe_removed(hw->hw_addr))
3557 return;
9e10e045
AD		 3558 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3559 if (hw->mac.type == ixgbe_mac_82598EB &&
3560 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3561 return;
3562
3563 do {
032b4325 3564 usleep_range(1000, 2000);
9e10e045
AD		 3565 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3566 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3567
3568 if (!wait_loop) {
3569 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3570 "the polling period\n", reg_idx);
3571 }
3572}
3573
2d39d576
YZ		 3574void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3575 struct ixgbe_ring *ring)
3576{
3577 struct ixgbe_hw *hw = &adapter->hw;
3578 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3579 u32 rxdctl;
3580 u8 reg_idx = ring->reg_idx;
3581
b0483c8f
MR		 3582 if (ixgbe_removed(hw->hw_addr))
3583 return;
2d39d576
YZ		 3584 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3585 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3586
3587 /* write value back with RXDCTL.ENABLE bit cleared */
3588 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3589
3590 if (hw->mac.type == ixgbe_mac_82598EB &&
3591 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3592 return;
3593
3594 /* the hardware may take up to 100us to really disable the rx queue */
3595 do {
3596 udelay(10);
3597 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3598 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3599
3600 if (!wait_loop) {
3601 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3602 "the polling period\n", reg_idx);
3603 }
3604}
3605
84418e3b
AD		 3606void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3607 struct ixgbe_ring *ring)
acd37177
AD		 3608{
3609 struct ixgbe_hw *hw = &adapter->hw;
3610 u64 rdba = ring->dma;
9e10e045 3611 u32 rxdctl;
bf29ee6c 3612 u8 reg_idx = ring->reg_idx;
acd37177 3613
9e10e045
AD		 3614 /* disable queue to avoid issues while updating state */
3615 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3616 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3617
acd37177
AD		 3618 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3619 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3620 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3621 ring->count * sizeof(union ixgbe_adv_rx_desc));
3622 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3623 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3624 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3625
3626 ixgbe_configure_srrctl(adapter, ring);
3627 ixgbe_configure_rscctl(adapter, ring);
3628
3629 if (hw->mac.type == ixgbe_mac_82598EB) {
3630 /*
3631 * enable cache line friendly hardware writes:
3632 * PTHRESH=32 descriptors (half the internal cache),
3633 * this also removes ugly rx_no_buffer_count increment
3634 * HTHRESH=4 descriptors (to minimize latency on fetch)
3635 * WTHRESH=8 burst writeback up to two cache lines
3636 */
3637 rxdctl &= ~0x3FFFFF;
3638 rxdctl |= 0x080420;
3639 }
3640
3641 /* enable receive descriptor ring */
3642 rxdctl |= IXGBE_RXDCTL_ENABLE;
3643 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3644
3645 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3646 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3647}
3648
48654521
AD		 3649static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3650{
3651 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3652 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3653 u16 pool;
48654521
AD		 3654
3655 /* PSRTYPE must be initialized in non 82598 adapters */
3656 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3657 IXGBE_PSRTYPE_UDPHDR |
3658 IXGBE_PSRTYPE_IPV4HDR |
48654521 3659 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3660 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3661
3662 if (hw->mac.type == ixgbe_mac_82598EB)
3663 return;
3664
fbe7ca7f
AD		 3665 if (rss_i > 3)
3666 psrtype |= 2 << 29;
3667 else if (rss_i > 1)
3668 psrtype |= 1 << 29;
48654521 3669
2a47fa45
JF		 3670 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3671 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3672}
3673
f5b4a52e
AD		 3674static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3675{
3676 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3677 u32 reg_offset, vf_shift;
435b19f6 3678 u32 gcr_ext, vmdctl;
de4c7f65 3679 int i;
f5b4a52e
AD		 3680
3681 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3682 return;
3683
3684 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3685 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3686 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3687 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3688 vmdctl |= IXGBE_VT_CTL_REPLEN;
3689 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3690
1d9c0bfd
AD		 3691 vf_shift = VMDQ_P(0) % 32;
3692 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3693
3694 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3695 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3696 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3697 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3698 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3699 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3700 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3701
3702 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3703 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 3704
16369564
AD		 3705 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3706 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3707
f5b4a52e
AD		 3708 /*
3709 * Set up VF register offsets for selected VT Mode,
3710 * i.e. 32 or 64 VFs for SR-IOV
3711 */
73079ea0
AD		 3712 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3713 case IXGBE_82599_VMDQ_8Q_MASK:
3714 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3715 break;
3716 case IXGBE_82599_VMDQ_4Q_MASK:
3717 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3718 break;
3719 default:
3720 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3721 break;
3722 }
3723
f5b4a52e
AD		 3724 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3725
435b19f6 3726
a985b6c3 3727 /* Enable MAC Anti-Spoofing */
435b19f6 3728 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3729 adapter->num_vfs);
5b7f000f 3730
f079fa00 3731 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
5b7f000f
DS		 3732 * calling set_ethertype_anti_spoofing for each VF in loop below
3733 */
f079fa00 3734 if (hw->mac.ops.set_ethertype_anti_spoofing) {
5b7f000f 3735 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
f079fa00
ET		 3736 (IXGBE_ETQF_FILTER_EN |
3737 IXGBE_ETQF_TX_ANTISPOOF |
3738 IXGBE_ETH_P_LLDP));
3739
3740 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3741 (IXGBE_ETQF_FILTER_EN |
3742 IXGBE_ETQF_TX_ANTISPOOF |
3743 ETH_P_PAUSE));
3744 }
5b7f000f 3745
de4c7f65
GR		 3746 /* For VFs that have spoof checking turned off */
3747 for (i = 0; i < adapter->num_vfs; i++) {
3748 if (!adapter->vfinfo[i].spoofchk_enabled)
3749 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3750
3751 /* enable ethertype anti spoofing if hw supports it */
3752 if (hw->mac.ops.set_ethertype_anti_spoofing)
3753 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3754
3755 /* Enable/Disable RSS query feature */
3756 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3757 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3758 }
f5b4a52e
AD		 3759}
3760
477de6ed 3761static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3762{
9a799d71
AK		 3763 struct ixgbe_hw *hw = &adapter->hw;
3764 struct net_device *netdev = adapter->netdev;
3765 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3766 struct ixgbe_ring *rx_ring;
3767 int i;
3768 u32 mhadd, hlreg0;
48654521 3769
63f39bd1 3770#ifdef IXGBE_FCOE
477de6ed
AD		 3771 /* adjust max frame to be able to do baby jumbo for FCoE */
3772 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3773 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3774 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3775
477de6ed 3776#endif /* IXGBE_FCOE */
872844dd
AD		 3777
3778 /* adjust max frame to be at least the size of a standard frame */
3779 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3780 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3781
477de6ed
AD		 3782 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3783 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3784 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3785 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3786
3787 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3788 }
3789
3790 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3791 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3792 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3793 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3794
0cefafad
JB		 3795 /*
3796 * Setup the HW Rx Head and Tail Descriptor Pointers and
3797 * the Base and Length of the Rx Descriptor Ring
3798 */
9a799d71 3799 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3800 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3801 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3802 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3803 else
7d637bcc 3804 clear_ring_rsc_enabled(rx_ring);
477de6ed 3805 }
477de6ed
AD		 3806}
3807
7367096a
AD		 3808static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3809{
3810 struct ixgbe_hw *hw = &adapter->hw;
3811 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3812
3813 switch (hw->mac.type) {
3814 case ixgbe_mac_82598EB:
3815 /*
3816 * For VMDq support of different descriptor types or
3817 * buffer sizes through the use of multiple SRRCTL
3818 * registers, RDRXCTL.MVMEN must be set to 1
3819 *
3820 * also, the manual doesn't mention it clearly but DCA hints
3821 * will only use queue 0's tags unless this bit is set. Side
3822 * effects of setting this bit are only that SRRCTL must be
3823 * fully programmed [0..15]
3824 */
3825 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3826 break;
052a1a72
MR		 3827 case ixgbe_mac_X550:
3828 case ixgbe_mac_X550EM_x:
f961ddae
MR		 3829 if (adapter->num_vfs)
3830 rdrxctl |= IXGBE_RDRXCTL_PSP;
3831 /* fall through for older HW */
7367096a 3832 case ixgbe_mac_82599EB:
b93a2226 3833 case ixgbe_mac_X540:
7367096a
AD		 3834 /* Disable RSC for ACK packets */
3835 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3836 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3837 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3838 /* hardware requires some bits to be set by default */
3839 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3840 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3841 break;
3842 default:
3843 /* We should do nothing since we don't know this hardware */
3844 return;
3845 }
3846
3847 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3848}
3849
477de6ed
AD		 3850/**
3851 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3852 * @adapter: board private structure
3853 *
3854 * Configure the Rx unit of the MAC after a reset.
3855 **/
3856static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3857{
3858 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3859 int i;
6dcc28b9 3860 u32 rxctrl, rfctl;
477de6ed
AD		 3861
3862 /* disable receives while setting up the descriptors */
1f9ac57c 3863 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3864
3865 ixgbe_setup_psrtype(adapter);
7367096a 3866 ixgbe_setup_rdrxctl(adapter);
477de6ed 3867
6dcc28b9
JK		 3868 /* RSC Setup */
3869 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3870 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3871 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3872 rfctl |= IXGBE_RFCTL_RSC_DIS;
3873 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3874
9e10e045 3875 /* Program registers for the distribution of queues */
f5b4a52e 3876 ixgbe_setup_mrqc(adapter);
f5b4a52e 3877
477de6ed
AD		 3878 /* set_rx_buffer_len must be called before ring initialization */
3879 ixgbe_set_rx_buffer_len(adapter);
3880
3881 /*
3882 * Setup the HW Rx Head and Tail Descriptor Pointers and
3883 * the Base and Length of the Rx Descriptor Ring
3884 */
9e10e045
AD		 3885 for (i = 0; i < adapter->num_rx_queues; i++)
3886 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3887
1f9ac57c 3888 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3889 /* disable drop enable for 82598 parts */
3890 if (hw->mac.type == ixgbe_mac_82598EB)
3891 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3892
3893 /* enable all receives */
3894 rxctrl |= IXGBE_RXCTRL_RXEN;
3895 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3896}
3897
80d5c368
PM		 3898static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3899 __be16 proto, u16 vid)
068c89b0
DS		 3900{
3901 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3902 struct ixgbe_hw *hw = &adapter->hw;
3903
3904 /* add VID to filter table */
b6488b66 3905 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, true);
f62bbb5e 3906 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3907
3908 return 0;
068c89b0
DS		 3909}
3910
e1d0a2af
AD		 3911static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3912{
3913 u32 vlvf;
3914 int idx;
3915
3916 /* short cut the special case */
3917 if (vlan == 0)
3918 return 0;
3919
3920 /* Search for the vlan id in the VLVF entries */
3921 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3922 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3923 if ((vlvf & VLAN_VID_MASK) == vlan)
3924 break;
3925 }
3926
3927 return idx;
3928}
3929
3930void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3931{
3932 struct ixgbe_hw *hw = &adapter->hw;
3933 u32 bits, word;
3934 int idx;
3935
3936 idx = ixgbe_find_vlvf_entry(hw, vid);
3937 if (!idx)
3938 return;
3939
3940 /* See if any other pools are set for this VLAN filter
3941 * entry other than the PF.
3942 */
3943 word = idx * 2 + (VMDQ_P(0) / 32);
3944 bits = ~(1 << (VMDQ_P(0)) % 32);
3945 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
3946
3947 /* Disable the filter so this falls into the default pool. */
3948 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
3949 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3950 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
3951 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
3952 }
3953}
3954
80d5c368
PM		 3955static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3956 __be16 proto, u16 vid)
068c89b0
DS		 3957{
3958 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3959 struct ixgbe_hw *hw = &adapter->hw;
3960
068c89b0 3961 /* remove VID from filter table */
e1d0a2af
AD		 3962 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
3963 ixgbe_update_pf_promisc_vlvf(adapter, vid);
3964 else
3965 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
3966
f62bbb5e 3967 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3968
3969 return 0;
068c89b0
DS		 3970}
3971
f62bbb5e
JG		 3972/**
3973 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3974 * @adapter: driver data
3975 */
3976static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3977{
3978 struct ixgbe_hw *hw = &adapter->hw;
3979 u32 vlnctrl;
5f6c0181
JB		 3980 int i, j;
3981
3982 switch (hw->mac.type) {
3983 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3984 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3985 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3986 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3987 break;
3988 case ixgbe_mac_82599EB:
b93a2226 3989 case ixgbe_mac_X540:
9a75a1ac
DS		 3990 case ixgbe_mac_X550:
3991 case ixgbe_mac_X550EM_x:
5f6c0181 3992 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3993 struct ixgbe_ring *ring = adapter->rx_ring[i];
3994
3995 if (ring->l2_accel_priv)
3996 continue;
3997 j = ring->reg_idx;
5f6c0181
JB		 3998 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3999 vlnctrl &= ~IXGBE_RXDCTL_VME;
4000 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4001 }
4002 break;
4003 default:
4004 break;
4005 }
4006}
4007
4008/**
f62bbb5e 4009 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4010 * @adapter: driver data
4011 */
f62bbb5e 4012static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4013{
4014 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4015 u32 vlnctrl;
5f6c0181
JB		 4016 int i, j;
4017
4018 switch (hw->mac.type) {
4019 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4020 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4021 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4022 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4023 break;
4024 case ixgbe_mac_82599EB:
b93a2226 4025 case ixgbe_mac_X540:
9a75a1ac
DS		 4026 case ixgbe_mac_X550:
4027 case ixgbe_mac_X550EM_x:
5f6c0181 4028 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4029 struct ixgbe_ring *ring = adapter->rx_ring[i];
4030
4031 if (ring->l2_accel_priv)
4032 continue;
4033 j = ring->reg_idx;
5f6c0181
JB		 4034 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4035 vlnctrl |= IXGBE_RXDCTL_VME;
4036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4037 }
4038 break;
4039 default:
4040 break;
4041 }
4042}
4043
16369564
AD		 4044static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4045{
4046 struct ixgbe_hw *hw = &adapter->hw;
4047 u32 vlnctrl, i;
4048
4049 switch (hw->mac.type) {
4050 case ixgbe_mac_82599EB:
4051 case ixgbe_mac_X540:
4052 case ixgbe_mac_X550:
4053 case ixgbe_mac_X550EM_x:
4054 default:
4055 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4056 break;
4057 /* fall through */
4058 case ixgbe_mac_82598EB:
4059 /* legacy case, we can just disable VLAN filtering */
4060 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4061 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4062 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4063 return;
4064 }
4065
4066 /* We are already in VLAN promisc, nothing to do */
4067 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4068 return;
4069
4070 /* Set flag so we don't redo unnecessary work */
4071 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4072
4073 /* Add PF to all active pools */
4074 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4075 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4076 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4077
4078 vlvfb |= 1 << (VMDQ_P(0) % 32);
4079 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4080 }
4081
4082 /* Set all bits in the VLAN filter table array */
4083 for (i = hw->mac.vft_size; i--;)
4084 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4085}
4086
4087#define VFTA_BLOCK_SIZE 8
4088static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4089{
4090 struct ixgbe_hw *hw = &adapter->hw;
4091 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4092 u32 vid_start = vfta_offset * 32;
4093 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4094 u32 i, vid, word, bits;
4095
4096 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4097 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4098
4099 /* pull VLAN ID from VLVF */
4100 vid = vlvf & VLAN_VID_MASK;
4101
4102 /* only concern outselves with a certain range */
4103 if (vid < vid_start || vid >= vid_end)
4104 continue;
4105
4106 if (vlvf) {
4107 /* record VLAN ID in VFTA */
4108 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4109
4110 /* if PF is part of this then continue */
4111 if (test_bit(vid, adapter->active_vlans))
4112 continue;
4113 }
4114
4115 /* remove PF from the pool */
4116 word = i * 2 + VMDQ_P(0) / 32;
4117 bits = ~(1 << (VMDQ_P(0) % 32));
4118 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4119 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4120 }
4121
4122 /* extract values from active_vlans and write back to VFTA */
4123 for (i = VFTA_BLOCK_SIZE; i--;) {
4124 vid = (vfta_offset + i) * 32;
4125 word = vid / BITS_PER_LONG;
4126 bits = vid % BITS_PER_LONG;
4127
4128 vfta[i] |= adapter->active_vlans[word] >> bits;
4129
4130 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4131 }
4132}
4133
4134static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4135{
4136 struct ixgbe_hw *hw = &adapter->hw;
4137 u32 vlnctrl, i;
4138
4139 switch (hw->mac.type) {
4140 case ixgbe_mac_82599EB:
4141 case ixgbe_mac_X540:
4142 case ixgbe_mac_X550:
4143 case ixgbe_mac_X550EM_x:
4144 default:
4145 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4146 break;
4147 /* fall through */
4148 case ixgbe_mac_82598EB:
4149 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4150 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
4151 vlnctrl |= IXGBE_VLNCTRL_VFE;
4152 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4153 return;
4154 }
4155
4156 /* We are not in VLAN promisc, nothing to do */
4157 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4158 return;
4159
4160 /* Set flag so we don't redo unnecessary work */
4161 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4162
4163 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4164 ixgbe_scrub_vfta(adapter, i);
4165}
4166
9a799d71
AK		 4167static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4168{
f62bbb5e 4169 u16 vid;
9a799d71 4170
80d5c368 4171 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 4172
4173 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4174 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4175}
4176
b335e75b
JK		 4177/**
4178 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4179 * @netdev: network interface device structure
4180 *
4181 * Writes multicast address list to the MTA hash table.
4182 * Returns: -ENOMEM on failure
4183 * 0 on no addresses written
4184 * X on writing X addresses to MTA
4185 **/
4186static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4187{
4188 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4189 struct ixgbe_hw *hw = &adapter->hw;
4190
4191 if (!netif_running(netdev))
4192 return 0;
4193
4194 if (hw->mac.ops.update_mc_addr_list)
4195 hw->mac.ops.update_mc_addr_list(hw, netdev);
4196 else
4197 return -ENOMEM;
4198
4199#ifdef CONFIG_PCI_IOV
5d7daa35 4200 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4201#endif
4202
4203 return netdev_mc_count(netdev);
4204}
4205
5d7daa35
JK		 4206#ifdef CONFIG_PCI_IOV
4207void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4208{
c9f53e63 4209 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4210 struct ixgbe_hw *hw = &adapter->hw;
4211 int i;
c9f53e63
AD		 4212
4213 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4214 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4215
4216 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4217 hw->mac.ops.set_rar(hw, i,
4218 mac_table->addr,
4219 mac_table->pool,
5d7daa35
JK		 4220 IXGBE_RAH_AV);
4221 else
4222 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4223 }
4224}
5d7daa35 4225
c9f53e63 4226#endif
5d7daa35
JK		 4227static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4228{
c9f53e63 4229 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4230 struct ixgbe_hw *hw = &adapter->hw;
4231 int i;
5d7daa35 4232
c9f53e63
AD		 4233 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4234 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4235 continue;
4236
4237 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4238
4239 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4240 hw->mac.ops.set_rar(hw, i,
4241 mac_table->addr,
4242 mac_table->pool,
4243 IXGBE_RAH_AV);
4244 else
4245 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4246 }
4247}
4248
4249static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4250{
c9f53e63 4251 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4252 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4253 int i;
5d7daa35 4254
c9f53e63
AD		 4255 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4256 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4257 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4258 }
c9f53e63 4259
5d7daa35
JK		 4260 ixgbe_sync_mac_table(adapter);
4261}
4262
c9f53e63 4263static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4264{
c9f53e63 4265 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4266 struct ixgbe_hw *hw = &adapter->hw;
4267 int i, count = 0;
4268
c9f53e63
AD		 4269 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4270 /* do not count default RAR as available */
4271 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4272 continue;
4273
4274 /* only count unused and addresses that belong to us */
4275 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4276 if (mac_table->pool != pool)
4277 continue;
4278 }
4279
4280 count++;
5d7daa35 4281 }
c9f53e63 4282
5d7daa35
JK		 4283 return count;
4284}
4285
4286/* this function destroys the first RAR entry */
c9f53e63 4287static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4288{
c9f53e63 4289 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4290 struct ixgbe_hw *hw = &adapter->hw;
4291
c9f53e63
AD		 4292 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4293 mac_table->pool = VMDQ_P(0);
4294
4295 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4296
4297 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4298 IXGBE_RAH_AV);
4299}
4300
c9f53e63
AD		 4301int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4302 const u8 *addr, u16 pool)
5d7daa35 4303{
c9f53e63 4304 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4305 struct ixgbe_hw *hw = &adapter->hw;
4306 int i;
4307
4308 if (is_zero_ether_addr(addr))
4309 return -EINVAL;
4310
c9f53e63
AD		 4311 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4312 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4313 continue;
c9f53e63
AD		 4314
4315 ether_addr_copy(mac_table->addr, addr);
4316 mac_table->pool = pool;
4317
4318 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4319 IXGBE_MAC_STATE_IN_USE;
4320
5d7daa35 4321 ixgbe_sync_mac_table(adapter);
c9f53e63 4322
5d7daa35
JK		 4323 return i;
4324 }
c9f53e63 4325
5d7daa35
JK		 4326 return -ENOMEM;
4327}
4328
c9f53e63
AD		 4329int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4330 const u8 *addr, u16 pool)
5d7daa35 4331{
c9f53e63 4332 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4333 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4334 int i;
5d7daa35
JK		 4335
4336 if (is_zero_ether_addr(addr))
4337 return -EINVAL;
4338
c9f53e63
AD		 4339 /* search table for addr, if found clear IN_USE flag and sync */
4340 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4341 /* we can only delete an entry if it is in use */
4342 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4343 continue;
4344 /* we only care about entries that belong to the given pool */
4345 if (mac_table->pool != pool)
4346 continue;
4347 /* we only care about a specific MAC address */
4348 if (!ether_addr_equal(addr, mac_table->addr))
4349 continue;
4350
4351 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4352 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4353
4354 ixgbe_sync_mac_table(adapter);
4355
4356 return 0;
5d7daa35 4357 }
c9f53e63 4358
5d7daa35
JK		 4359 return -ENOMEM;
4360}
2850062a
AD		 4361/**
4362 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4363 * @netdev: network interface device structure
4364 *
4365 * Writes unicast address list to the RAR table.
4366 * Returns: -ENOMEM on failure/insufficient address space
4367 * 0 on no addresses written
4368 * X on writing X addresses to the RAR table
4369 **/
5d7daa35 4370static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4371{
4372 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4373 int count = 0;
4374
4375 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4376 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4377 return -ENOMEM;
4378
95447461 4379 if (!netdev_uc_empty(netdev)) {
2850062a 4380 struct netdev_hw_addr *ha;
2850062a 4381 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4382 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4383 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4384 count++;
4385 }
4386 }
2850062a
AD		 4387 return count;
4388}
4389
0f079d22
AD		 4390static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4391{
4392 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4393 int ret;
4394
4395 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4396
4397 return min_t(int, ret, 0);
4398}
4399
4400static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4401{
4402 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4403
4404 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4405
4406 return 0;
4407}
4408
9a799d71 4409/**
2c5645cf 4410 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4411 * @netdev: network interface device structure
4412 *
2c5645cf
CL		 4413 * The set_rx_method entry point is called whenever the unicast/multicast
4414 * address list or the network interface flags are updated. This routine is
4415 * responsible for configuring the hardware for proper unicast, multicast and
4416 * promiscuous mode.
9a799d71 4417 **/
7f870475 4418void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4419{
4420 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4421 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 4422 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4423 int count;
9a799d71
AK		 4424
4425 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4426 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4427
f5dc442b 4428 /* set all bits that we expect to always be set */
3f2d1c0f 4429 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4430 fctrl |= IXGBE_FCTRL_BAM;
4431 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4432 fctrl |= IXGBE_FCTRL_PMCF;
4433
2850062a
AD		 4434 /* clear the bits we are changing the status of */
4435 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4436 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4437 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4438 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4439 vmolr |= IXGBE_VMOLR_MPE;
16369564 4440 ixgbe_vlan_promisc_enable(adapter);
9a799d71 4441 } else {
746b9f02
PM		 4442 if (netdev->flags & IFF_ALLMULTI) {
4443 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4444 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4445 }
e433ea1f 4446 hw->addr_ctrl.user_set_promisc = false;
16369564 4447 ixgbe_vlan_promisc_disable(adapter);
9dcb373c
JF		 4448 }
4449
4450 /*
4451 * Write addresses to available RAR registers, if there is not
4452 * sufficient space to store all the addresses then enable
4453 * unicast promiscuous mode
4454 */
0f079d22 4455 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4456 fctrl |= IXGBE_FCTRL_UPE;
4457 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4458 }
4459
cf78959c
ET		 4460 /* Write addresses to the MTA, if the attempt fails
4461 * then we should just turn on promiscuous mode so
4462 * that we can at least receive multicast traffic
4463 */
b335e75b
JK		 4464 count = ixgbe_write_mc_addr_list(netdev);
4465 if (count < 0) {
4466 fctrl |= IXGBE_FCTRL_MPE;
4467 vmolr |= IXGBE_VMOLR_MPE;
4468 } else if (count) {
4469 vmolr |= IXGBE_VMOLR_ROMPE;
4470 }
1d9c0bfd
AD		 4471
4472 if (hw->mac.type != ixgbe_mac_82598EB) {
4473 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4474 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4475 IXGBE_VMOLR_ROPE);
1d9c0bfd 4476 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4477 }
4478
3f2d1c0f
BG		 4479 /* This is useful for sniffing bad packets. */
4480 if (adapter->netdev->features & NETIF_F_RXALL) {
4481 /* UPE and MPE will be handled by normal PROMISC logic
4482 * in e1000e_set_rx_mode */
4483 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4484 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4485 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4486
4487 fctrl &= ~(IXGBE_FCTRL_DPF);
4488 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4489 }
4490
2850062a 4491 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4492
f646968f 4493 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4494 ixgbe_vlan_strip_enable(adapter);
4495 else
4496 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4497}
4498
021230d4
AV		 4499static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4500{
4501 int q_idx;
021230d4 4502
5a85e737
ET		 4503 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4504 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4505 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4506 }
021230d4
AV		 4507}
4508
4509static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4510{
4511 int q_idx;
021230d4 4512
5a85e737 4513 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4514 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4515 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4516 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4517 usleep_range(1000, 20000);
5a85e737
ET		 4518 }
4519 }
021230d4
AV		 4520}
4521
67359c3c
MR		 4522static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4523{
4524 switch (adapter->hw.mac.type) {
4525 case ixgbe_mac_X550:
4526 case ixgbe_mac_X550EM_x:
4527 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4528#ifdef CONFIG_IXGBE_VXLAN
4529 adapter->vxlan_port = 0;
4530#endif
4531 break;
4532 default:
4533 break;
4534 }
4535}
4536
7a6b6f51 4537#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4538/**
2f90b865
AD		 4539 * ixgbe_configure_dcb - Configure DCB hardware
4540 * @adapter: ixgbe adapter struct
4541 *
4542 * This is called by the driver on open to configure the DCB hardware.
4543 * This is also called by the gennetlink interface when reconfiguring
4544 * the DCB state.
4545 */
4546static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4547{
4548 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4549 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4550
67ebd791
AD		 4551 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4552 if (hw->mac.type == ixgbe_mac_82598EB)
4553 netif_set_gso_max_size(adapter->netdev, 65536);
4554 return;
4555 }
4556
4557 if (hw->mac.type == ixgbe_mac_82598EB)
4558 netif_set_gso_max_size(adapter->netdev, 32768);
4559
971060b1 4560#ifdef IXGBE_FCOE
b120818e
JF		 4561 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4562 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4563#endif
b120818e
JF		 4564
4565 /* reconfigure the hardware */
4566 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4567 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4568 DCB_TX_CONFIG);
4569 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4570 DCB_RX_CONFIG);
4571 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4572 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4573 ixgbe_dcb_hw_ets(&adapter->hw,
4574 adapter->ixgbe_ieee_ets,
4575 max_frame);
4576 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4577 adapter->ixgbe_ieee_pfc->pfc_en,
4578 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4579 }
8187cd48
JF		 4580
4581 /* Enable RSS Hash per TC */
4582 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4583 u32 msb = 0;
4584 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4585
d411a936
AD		 4586 while (rss_i) {
4587 msb++;
4588 rss_i >>= 1;
4589 }
8187cd48 4590
4ae63730
AD		 4591 /* write msb to all 8 TCs in one write */
4592 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4593 }
2f90b865 4594}
9da712d2
JF		 4595#endif
4596
4597/* Additional bittime to account for IXGBE framing */
4598#define IXGBE_ETH_FRAMING 20
4599
49ce9c2c 4600/**
9da712d2
JF		 4601 * ixgbe_hpbthresh - calculate high water mark for flow control
4602 *
4603 * @adapter: board private structure to calculate for
49ce9c2c 4604 * @pb: packet buffer to calculate
9da712d2
JF		 4605 */
4606static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4607{
4608 struct ixgbe_hw *hw = &adapter->hw;
4609 struct net_device *dev = adapter->netdev;
4610 int link, tc, kb, marker;
4611 u32 dv_id, rx_pba;
4612
4613 /* Calculate max LAN frame size */
4614 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4615
4616#ifdef IXGBE_FCOE
4617 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4618 if ((dev->features & NETIF_F_FCOE_MTU) &&
4619 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4620 (pb == ixgbe_fcoe_get_tc(adapter)))
4621 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4622#endif
e5776620 4623
9da712d2
JF		 4624 /* Calculate delay value for device */
4625 switch (hw->mac.type) {
4626 case ixgbe_mac_X540:
9a75a1ac
DS		 4627 case ixgbe_mac_X550:
4628 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4629 dv_id = IXGBE_DV_X540(link, tc);
4630 break;
4631 default:
4632 dv_id = IXGBE_DV(link, tc);
4633 break;
4634 }
4635
4636 /* Loopback switch introduces additional latency */
4637 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4638 dv_id += IXGBE_B2BT(tc);
4639
4640 /* Delay value is calculated in bit times convert to KB */
4641 kb = IXGBE_BT2KB(dv_id);
4642 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4643
4644 marker = rx_pba - kb;
4645
4646 /* It is possible that the packet buffer is not large enough
4647 * to provide required headroom. In this case throw an error
4648 * to user and a do the best we can.
4649 */
4650 if (marker < 0) {
4651 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4652 "headroom to support flow control."
4653 "Decrease MTU or number of traffic classes\n", pb);
4654 marker = tc + 1;
4655 }
4656
4657 return marker;
4658}
4659
49ce9c2c 4660/**
9da712d2
JF		 4661 * ixgbe_lpbthresh - calculate low water mark for for flow control
4662 *
4663 * @adapter: board private structure to calculate for
49ce9c2c 4664 * @pb: packet buffer to calculate
9da712d2 4665 */
e5776620 4666static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4667{
4668 struct ixgbe_hw *hw = &adapter->hw;
4669 struct net_device *dev = adapter->netdev;
4670 int tc;
4671 u32 dv_id;
4672
4673 /* Calculate max LAN frame size */
4674 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4675
e5776620
JK		 4676#ifdef IXGBE_FCOE
4677 /* FCoE traffic class uses FCOE jumbo frames */
4678 if ((dev->features & NETIF_F_FCOE_MTU) &&
4679 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4680 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4681 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4682#endif
4683
9da712d2
JF		 4684 /* Calculate delay value for device */
4685 switch (hw->mac.type) {
4686 case ixgbe_mac_X540:
9a75a1ac
DS		 4687 case ixgbe_mac_X550:
4688 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4689 dv_id = IXGBE_LOW_DV_X540(tc);
4690 break;
4691 default:
4692 dv_id = IXGBE_LOW_DV(tc);
4693 break;
4694 }
4695
4696 /* Delay value is calculated in bit times convert to KB */
4697 return IXGBE_BT2KB(dv_id);
4698}
4699
4700/*
4701 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4702 */
4703static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4704{
4705 struct ixgbe_hw *hw = &adapter->hw;
4706 int num_tc = netdev_get_num_tc(adapter->netdev);
4707 int i;
4708
4709 if (!num_tc)
4710 num_tc = 1;
4711
9da712d2
JF		 4712 for (i = 0; i < num_tc; i++) {
4713 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4714 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4715
4716 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4717 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4718 hw->fc.low_water[i] = 0;
9da712d2 4719 }
e5776620
JK		 4720
4721 for (; i < MAX_TRAFFIC_CLASS; i++)
4722 hw->fc.high_water[i] = 0;
9da712d2
JF		 4723}
4724
80605c65
JF		 4725static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4726{
80605c65 4727 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4728 int hdrm;
4729 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4730
4731 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4732 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4733 hdrm = 32 << adapter->fdir_pballoc;
4734 else
4735 hdrm = 0;
80605c65 4736
f7e1027f 4737 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4738 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4739}
4740
e4911d57
AD		 4741static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4742{
4743 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4744 struct hlist_node *node2;
e4911d57
AD		 4745 struct ixgbe_fdir_filter *filter;
4746
4747 spin_lock(&adapter->fdir_perfect_lock);
4748
4749 if (!hlist_empty(&adapter->fdir_filter_list))
4750 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4751
b67bfe0d 4752 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4753 &adapter->fdir_filter_list, fdir_node) {
4754 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4755 &filter->filter,
4756 filter->sw_idx,
4757 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4758 IXGBE_FDIR_DROP_QUEUE :
4759 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4760 }
4761
4762 spin_unlock(&adapter->fdir_perfect_lock);
4763}
4764
2a47fa45
JF		 4765static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4766 struct ixgbe_adapter *adapter)
4767{
4768 struct ixgbe_hw *hw = &adapter->hw;
4769 u32 vmolr;
4770
4771 /* No unicast promiscuous support for VMDQ devices. */
4772 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4773 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4774
4775 /* clear the affected bit */
4776 vmolr &= ~IXGBE_VMOLR_MPE;
4777
4778 if (dev->flags & IFF_ALLMULTI) {
4779 vmolr |= IXGBE_VMOLR_MPE;
4780 } else {
4781 vmolr |= IXGBE_VMOLR_ROMPE;
4782 hw->mac.ops.update_mc_addr_list(hw, dev);
4783 }
5d7daa35 4784 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4785 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4786}
4787
2a47fa45
JF		 4788static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4789{
4790 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4791 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4792 struct ixgbe_hw *hw = &adapter->hw;
4793 u16 pool = vadapter->pool;
4794 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4795 IXGBE_PSRTYPE_UDPHDR |
4796 IXGBE_PSRTYPE_IPV4HDR |
4797 IXGBE_PSRTYPE_L2HDR |
4798 IXGBE_PSRTYPE_IPV6HDR;
4799
4800 if (hw->mac.type == ixgbe_mac_82598EB)
4801 return;
4802
4803 if (rss_i > 3)
4804 psrtype |= 2 << 29;
4805 else if (rss_i > 1)
4806 psrtype |= 1 << 29;
4807
4808 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4809}
4810
4811/**
4812 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4813 * @rx_ring: ring to free buffers from
4814 **/
4815static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4816{
4817 struct device *dev = rx_ring->dev;
4818 unsigned long size;
4819 u16 i;
4820
4821 /* ring already cleared, nothing to do */
4822 if (!rx_ring->rx_buffer_info)
4823 return;
4824
4825 /* Free all the Rx ring sk_buffs */
4826 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4827 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4828
2a47fa45
JF		 4829 if (rx_buffer->skb) {
4830 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4831 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4832 dma_unmap_page(dev,
4833 IXGBE_CB(skb)->dma,
4834 ixgbe_rx_bufsz(rx_ring),
4835 DMA_FROM_DEVICE);
2a47fa45 4836 dev_kfree_skb(skb);
4d2fcfbc 4837 rx_buffer->skb = NULL;
2a47fa45 4838 }
18cb652a
AD		 4839
4840 if (!rx_buffer->page)
4841 continue;
4842
4843 dma_unmap_page(dev, rx_buffer->dma,
4844 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4845 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4846
2a47fa45
JF		 4847 rx_buffer->page = NULL;
4848 }
4849
4850 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4851 memset(rx_ring->rx_buffer_info, 0, size);
4852
4853 /* Zero out the descriptor ring */
4854 memset(rx_ring->desc, 0, rx_ring->size);
4855
4856 rx_ring->next_to_alloc = 0;
4857 rx_ring->next_to_clean = 0;
4858 rx_ring->next_to_use = 0;
4859}
4860
4861static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4862 struct ixgbe_ring *rx_ring)
4863{
4864 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4865 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4866
4867 /* shutdown specific queue receive and wait for dma to settle */
4868 ixgbe_disable_rx_queue(adapter, rx_ring);
4869 usleep_range(10000, 20000);
4870 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4871 ixgbe_clean_rx_ring(rx_ring);
4872 rx_ring->l2_accel_priv = NULL;
4873}
4874
ae72c8d0
JF		 4875static int ixgbe_fwd_ring_down(struct net_device *vdev,
4876 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4877{
4878 struct ixgbe_adapter *adapter = accel->real_adapter;
4879 unsigned int rxbase = accel->rx_base_queue;
4880 unsigned int txbase = accel->tx_base_queue;
4881 int i;
4882
4883 netif_tx_stop_all_queues(vdev);
4884
4885 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4886 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4887 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4888 }
4889
4890 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4891 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4892 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4893 }
4894
4895
4896 return 0;
4897}
4898
4899static int ixgbe_fwd_ring_up(struct net_device *vdev,
4900 struct ixgbe_fwd_adapter *accel)
4901{
4902 struct ixgbe_adapter *adapter = accel->real_adapter;
4903 unsigned int rxbase, txbase, queues;
4904 int i, baseq, err = 0;
4905
4906 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4907 return 0;
4908
4909 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4910 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4911 accel->pool, adapter->num_rx_pools,
4912 baseq, baseq + adapter->num_rx_queues_per_pool,
4913 adapter->fwd_bitmask);
4914
4915 accel->netdev = vdev;
4916 accel->rx_base_queue = rxbase = baseq;
4917 accel->tx_base_queue = txbase = baseq;
4918
4919 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4920 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4921
4922 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4923 adapter->rx_ring[rxbase + i]->netdev = vdev;
4924 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4925 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4926 }
4927
4928 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4929 adapter->tx_ring[txbase + i]->netdev = vdev;
4930 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4931 }
4932
4933 queues = min_t(unsigned int,
4934 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4935 err = netif_set_real_num_tx_queues(vdev, queues);
4936 if (err)
4937 goto fwd_queue_err;
4938
2a47fa45
JF		 4939 err = netif_set_real_num_rx_queues(vdev, queues);
4940 if (err)
4941 goto fwd_queue_err;
4942
4943 if (is_valid_ether_addr(vdev->dev_addr))
4944 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4945
4946 ixgbe_fwd_psrtype(accel);
4947 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4948 return err;
4949fwd_queue_err:
4950 ixgbe_fwd_ring_down(vdev, accel);
4951 return err;
4952}
4953
4954static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4955{
4956 struct net_device *upper;
4957 struct list_head *iter;
4958 int err;
4959
4960 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4961 if (netif_is_macvlan(upper)) {
4962 struct macvlan_dev *dfwd = netdev_priv(upper);
4963 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4964
4965 if (dfwd->fwd_priv) {
4966 err = ixgbe_fwd_ring_up(upper, vadapter);
4967 if (err)
4968 continue;
4969 }
4970 }
4971 }
4972}
4973
9a799d71
AK		 4974static void ixgbe_configure(struct ixgbe_adapter *adapter)
4975{
d2f5e7f3
AS		 4976 struct ixgbe_hw *hw = &adapter->hw;
4977
80605c65 4978 ixgbe_configure_pb(adapter);
7a6b6f51 4979#ifdef CONFIG_IXGBE_DCB
67ebd791 4980 ixgbe_configure_dcb(adapter);
2f90b865 4981#endif
b35d4d42
AD		 4982 /*
4983 * We must restore virtualization before VLANs or else
4984 * the VLVF registers will not be populated
4985 */
4986 ixgbe_configure_virtualization(adapter);
9a799d71 4987
4c1d7b4b 4988 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4989 ixgbe_restore_vlan(adapter);
4990
d2f5e7f3
AS		 4991 switch (hw->mac.type) {
4992 case ixgbe_mac_82599EB:
4993 case ixgbe_mac_X540:
4994 hw->mac.ops.disable_rx_buff(hw);
4995 break;
4996 default:
4997 break;
4998 }
4999
c4cf55e5 5000 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5001 ixgbe_init_fdir_signature_82599(&adapter->hw,
5002 adapter->fdir_pballoc);
e4911d57
AD		 5003 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5004 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5005 adapter->fdir_pballoc);
5006 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5007 }
4c1d7b4b 5008
d2f5e7f3
AS		 5009 switch (hw->mac.type) {
5010 case ixgbe_mac_82599EB:
5011 case ixgbe_mac_X540:
5012 hw->mac.ops.enable_rx_buff(hw);
5013 break;
5014 default:
5015 break;
5016 }
5017
9de7605e
MR		 5018#ifdef CONFIG_IXGBE_DCA
5019 /* configure DCA */
5020 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5021 ixgbe_setup_dca(adapter);
5022#endif /* CONFIG_IXGBE_DCA */
5023
7c8ae65a
AD		 5024#ifdef IXGBE_FCOE
5025 /* configure FCoE L2 filters, redirection table, and Rx control */
5026 ixgbe_configure_fcoe(adapter);
5027
5028#endif /* IXGBE_FCOE */
9a799d71
AK		 5029 ixgbe_configure_tx(adapter);
5030 ixgbe_configure_rx(adapter);
2a47fa45 5031 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5032}
5033
0ecc061d 5034/**
e8e26350
PW		 5035 * ixgbe_sfp_link_config - set up SFP+ link
5036 * @adapter: pointer to private adapter struct
5037 **/
5038static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5039{
7086400d 5040 /*
52f33af8 5041 * We are assuming the worst case scenario here, and that
7086400d
AD		 5042 * is that an SFP was inserted/removed after the reset
5043 * but before SFP detection was enabled. As such the best
5044 * solution is to just start searching as soon as we start
5045 */
5046 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5047 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5048
7086400d 5049 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5050 adapter->sfp_poll_time = 0;
e8e26350
PW		 5051}
5052
5053/**
5054 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5055 * @hw: pointer to private hardware struct
5056 *
5057 * Returns 0 on success, negative on failure
5058 **/
e8e26350 5059static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5060{
3d292265
JH		 5061 u32 speed;
5062 bool autoneg, link_up = false;
a1e869de 5063 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5064
5065 if (hw->mac.ops.check_link)
3d292265 5066 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5067
5068 if (ret)
e90dd264 5069 return ret;
0ecc061d 5070
3d292265
JH		 5071 speed = hw->phy.autoneg_advertised;
5072 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5073 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5074 &autoneg);
0ecc061d 5075 if (ret)
e90dd264 5076 return ret;
0ecc061d 5077
8620a103 5078 if (hw->mac.ops.setup_link)
fd0326f2 5079 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5080
0ecc061d
PWJ		 5081 return ret;
5082}
5083
a34bcfff 5084static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5085{
9a799d71 5086 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5087 u32 gpie = 0;
9a799d71 5088
9b471446 5089 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5090 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5091 IXGBE_GPIE_OCD;
5092 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5093 /*
5094 * use EIAM to auto-mask when MSI-X interrupt is asserted
5095 * this saves a register write for every interrupt
5096 */
5097 switch (hw->mac.type) {
5098 case ixgbe_mac_82598EB:
5099 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5100 break;
9b471446 5101 case ixgbe_mac_82599EB:
b93a2226 5102 case ixgbe_mac_X540:
9a75a1ac
DS		 5103 case ixgbe_mac_X550:
5104 case ixgbe_mac_X550EM_x:
b93a2226 5105 default:
9b471446
JB		 5106 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5107 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5108 break;
5109 }
5110 } else {
021230d4
AV		 5111 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5112 * specifically only auto mask tx and rx interrupts */
5113 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5114 }
9a799d71 5115
a34bcfff
AD		 5116 /* XXX: to interrupt immediately for EICS writes, enable this */
5117 /* gpie |= IXGBE_GPIE_EIMEN; */
5118
5119 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5120 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5121
5122 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5123 case IXGBE_82599_VMDQ_8Q_MASK:
5124 gpie |= IXGBE_GPIE_VTMODE_16;
5125 break;
5126 case IXGBE_82599_VMDQ_4Q_MASK:
5127 gpie |= IXGBE_GPIE_VTMODE_32;
5128 break;
5129 default:
5130 gpie |= IXGBE_GPIE_VTMODE_64;
5131 break;
5132 }
119fc60a
MC		 5133 }
5134
5fdd31f9 5135 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5136 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5137 switch (adapter->hw.mac.type) {
5138 case ixgbe_mac_82599EB:
9a900eca 5139 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5140 break;
f3df98ec
DS		 5141 default:
5142 break;
5143 }
5144 }
5fdd31f9 5145
a34bcfff
AD		 5146 /* Enable fan failure interrupt */
5147 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5148 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5149
a023bbd0
DS		 5150 switch (hw->mac.type) {
5151 case ixgbe_mac_82599EB:
5152 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5153 break;
5154 case ixgbe_mac_X550EM_x:
5155 gpie |= IXGBE_SDP0_GPIEN_X540;
5156 break;
5157 default:
5158 break;
2698b208 5159 }
a34bcfff
AD		 5160
5161 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5162}
5163
c7ccde0f 5164static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5165{
5166 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5167 int err;
a34bcfff
AD		 5168 u32 ctrl_ext;
5169
5170 ixgbe_get_hw_control(adapter);
5171 ixgbe_setup_gpie(adapter);
e8e26350 5172
9a799d71
AK		 5173 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5174 ixgbe_configure_msix(adapter);
5175 else
5176 ixgbe_configure_msi_and_legacy(adapter);
5177
ec74a471
ET		 5178 /* enable the optics for 82599 SFP+ fiber */
5179 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5180 hw->mac.ops.enable_tx_laser(hw);
5181
961fac88
DS		 5182 if (hw->phy.ops.set_phy_power)
5183 hw->phy.ops.set_phy_power(hw, true);
5184
4e857c58 5185 smp_mb__before_atomic();
9a799d71 5186 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5187 ixgbe_napi_enable_all(adapter);
5188
73c4b7cd
AD		 5189 if (ixgbe_is_sfp(hw)) {
5190 ixgbe_sfp_link_config(adapter);
5191 } else {
5192 err = ixgbe_non_sfp_link_config(hw);
5193 if (err)
5194 e_err(probe, "link_config FAILED %d\n", err);
5195 }
5196
021230d4
AV		 5197 /* clear any pending interrupts, may auto mask */
5198 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5199 ixgbe_irq_enable(adapter, true, true);
9a799d71 5200
bf069c97
DS		 5201 /*
5202 * If this adapter has a fan, check to see if we had a failure
5203 * before we enabled the interrupt.
5204 */
5205 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5206 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5207 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5208 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5209 }
5210
9a799d71
AK		 5211 /* bring the link up in the watchdog, this could race with our first
5212 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5213 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5214 adapter->link_check_timeout = jiffies;
7086400d 5215 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5216
5217 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5218 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5219 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5220 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5221}
5222
d4f80882
AV		 5223void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5224{
5225 WARN_ON(in_interrupt());
7086400d
AD		 5226 /* put off any impending NetWatchDogTimeout */
5227 adapter->netdev->trans_start = jiffies;
5228
d4f80882 5229 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5230 usleep_range(1000, 2000);
d4f80882 5231 ixgbe_down(adapter);
5809a1ae
GR		 5232 /*
5233 * If SR-IOV enabled then wait a bit before bringing the adapter
5234 * back up to give the VFs time to respond to the reset. The
5235 * two second wait is based upon the watchdog timer cycle in
5236 * the VF driver.
5237 */
5238 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5239 msleep(2000);
d4f80882
AV		 5240 ixgbe_up(adapter);
5241 clear_bit(__IXGBE_RESETTING, &adapter->state);
5242}
5243
c7ccde0f 5244void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5245{
5246 /* hardware has been reset, we need to reload some things */
5247 ixgbe_configure(adapter);
5248
c7ccde0f 5249 ixgbe_up_complete(adapter);
9a799d71
AK		 5250}
5251
5252void ixgbe_reset(struct ixgbe_adapter *adapter)
5253{
c44ade9e 5254 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5255 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5256 int err;
5257
b0483c8f
MR		 5258 if (ixgbe_removed(hw->hw_addr))
5259 return;
7086400d
AD		 5260 /* lock SFP init bit to prevent race conditions with the watchdog */
5261 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5262 usleep_range(1000, 2000);
5263
5264 /* clear all SFP and link config related flags while holding SFP_INIT */
5265 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5266 IXGBE_FLAG2_SFP_NEEDS_RESET);
5267 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5268
8ca783ab 5269 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5270 switch (err) {
5271 case 0:
5272 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5273 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5274 break;
5275 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5276 e_dev_err("master disable timed out\n");
da4dd0f7 5277 break;
794caeb2
PWJ		 5278 case IXGBE_ERR_EEPROM_VERSION:
5279 /* We are running on a pre-production device, log a warning */
849c4542 5280 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5281 "Please be aware there may be issues associated with "
849c4542
ET		 5282 "your hardware. If you are experiencing problems "
5283 "please contact your Intel or hardware "
5284 "representative who provided you with this "
5285 "hardware.\n");
794caeb2 5286 break;
da4dd0f7 5287 default:
849c4542 5288 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5289 }
9a799d71 5290
7086400d 5291 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5292
5293 /* flush entries out of MAC table */
5d7daa35 5294 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5295 __dev_uc_unsync(netdev, NULL);
5296
5297 /* do not flush user set addresses */
c9f53e63 5298 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5299
5300 /* update SAN MAC vmdq pool selection */
5301 if (hw->mac.san_mac_rar_index)
5302 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5303
8fecf67c 5304 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5305 ixgbe_ptp_reset(adapter);
961fac88
DS		 5306
5307 if (hw->phy.ops.set_phy_power) {
5308 if (!netif_running(adapter->netdev) && !adapter->wol)
5309 hw->phy.ops.set_phy_power(hw, false);
5310 else
5311 hw->phy.ops.set_phy_power(hw, true);
5312 }
9a799d71
AK		 5313}
5314
9a799d71
AK		 5315/**
5316 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5317 * @tx_ring: ring to be cleaned
5318 **/
b6ec895e 5319static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5320{
5321 struct ixgbe_tx_buffer *tx_buffer_info;
5322 unsigned long size;
b6ec895e 5323 u16 i;
9a799d71 5324
84418e3b
AD		 5325 /* ring already cleared, nothing to do */
5326 if (!tx_ring->tx_buffer_info)
5327 return;
9a799d71 5328
84418e3b 5329 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5330 for (i = 0; i < tx_ring->count; i++) {
5331 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5332 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5333 }
5334
dad8a3b3
JF		 5335 netdev_tx_reset_queue(txring_txq(tx_ring));
5336
9a799d71
AK		 5337 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5338 memset(tx_ring->tx_buffer_info, 0, size);
5339
5340 /* Zero out the descriptor ring */
5341 memset(tx_ring->desc, 0, tx_ring->size);
5342
5343 tx_ring->next_to_use = 0;
5344 tx_ring->next_to_clean = 0;
9a799d71
AK		 5345}
5346
5347/**
021230d4 5348 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5349 * @adapter: board private structure
5350 **/
021230d4 5351static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5352{
5353 int i;
5354
021230d4 5355 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5356 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5357}
5358
5359/**
021230d4 5360 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5361 * @adapter: board private structure
5362 **/
021230d4 5363static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5364{
5365 int i;
5366
021230d4 5367 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5368 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5369}
5370
e4911d57
AD		 5371static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5372{
b67bfe0d 5373 struct hlist_node *node2;
e4911d57
AD		 5374 struct ixgbe_fdir_filter *filter;
5375
5376 spin_lock(&adapter->fdir_perfect_lock);
5377
b67bfe0d 5378 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5379 &adapter->fdir_filter_list, fdir_node) {
5380 hlist_del(&filter->fdir_node);
5381 kfree(filter);
5382 }
5383 adapter->fdir_filter_count = 0;
5384
5385 spin_unlock(&adapter->fdir_perfect_lock);
5386}
5387
9a799d71
AK		 5388void ixgbe_down(struct ixgbe_adapter *adapter)
5389{
5390 struct net_device *netdev = adapter->netdev;
7f821875 5391 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5392 struct net_device *upper;
5393 struct list_head *iter;
bf29ee6c 5394 int i;
9a799d71
AK		 5395
5396 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5397 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5398 return; /* do nothing if already down */
9a799d71
AK		 5399
5400 /* disable receives */
1f9ac57c 5401 hw->mac.ops.disable_rx(hw);
9a799d71 5402
2d39d576
YZ		 5403 /* disable all enabled rx queues */
5404 for (i = 0; i < adapter->num_rx_queues; i++)
5405 /* this call also flushes the previous write */
5406 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5407
032b4325 5408 usleep_range(10000, 20000);
9a799d71 5409
7f821875
JB		 5410 netif_tx_stop_all_queues(netdev);
5411
7086400d 5412 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5413 netif_carrier_off(netdev);
5414 netif_tx_disable(netdev);
5415
2a47fa45
JF		 5416 /* disable any upper devices */
5417 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5418 if (netif_is_macvlan(upper)) {
5419 struct macvlan_dev *vlan = netdev_priv(upper);
5420
5421 if (vlan->fwd_priv) {
5422 netif_tx_stop_all_queues(upper);
5423 netif_carrier_off(upper);
5424 netif_tx_disable(upper);
5425 }
5426 }
5427 }
5428
c0dfb90e
JF		 5429 ixgbe_irq_disable(adapter);
5430
5431 ixgbe_napi_disable_all(adapter);
5432
d034acf1
AD		 5433 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5434 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5435 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5436
5437 del_timer_sync(&adapter->service_timer);
5438
34cecbbf 5439 if (adapter->num_vfs) {
8e34d1aa
AD		 5440 /* Clear EITR Select mapping */
5441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5442
5443 /* Mark all the VFs as inactive */
5444 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5445 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5446
34cecbbf
AD		 5447 /* ping all the active vfs to let them know we are going down */
5448 ixgbe_ping_all_vfs(adapter);
5449
5450 /* Disable all VFTE/VFRE TX/RX */
5451 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5452 }
5453
7f821875
JB		 5454 /* disable transmits in the hardware now that interrupts are off */
5455 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5456 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5457 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5458 }
34cecbbf 5459
9a75a1ac 5460 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5461 switch (hw->mac.type) {
5462 case ixgbe_mac_82599EB:
b93a2226 5463 case ixgbe_mac_X540:
9a75a1ac
DS		 5464 case ixgbe_mac_X550:
5465 case ixgbe_mac_X550EM_x:
88512539 5466 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5467 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5468 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5469 break;
5470 default:
5471 break;
5472 }
7f821875 5473
6f4a0e45
PL		 5474 if (!pci_channel_offline(adapter->pdev))
5475 ixgbe_reset(adapter);
c6ecf39a 5476
ec74a471
ET		 5477 /* power down the optics for 82599 SFP+ fiber */
5478 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5479 hw->mac.ops.disable_tx_laser(hw);
5480
9a799d71
AK		 5481 ixgbe_clean_all_tx_rings(adapter);
5482 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5483}
5484
9a799d71
AK		 5485/**
5486 * ixgbe_tx_timeout - Respond to a Tx Hang
5487 * @netdev: network interface device structure
5488 **/
5489static void ixgbe_tx_timeout(struct net_device *netdev)
5490{
5491 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5492
5493 /* Do the reset outside of interrupt context */
c83c6cbd 5494 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5495}
5496
9a799d71
AK		 5497/**
5498 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5499 * @adapter: board private structure to initialize
5500 *
5501 * ixgbe_sw_init initializes the Adapter private data structure.
5502 * Fields are initialized based on PCI device information and
5503 * OS network device settings (MTU size).
5504 **/
9f9a12f8 5505static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5506{
5507 struct ixgbe_hw *hw = &adapter->hw;
5508 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5509 unsigned int rss, fdir;
cb6d0f5e 5510 u32 fwsm;
7a6b6f51 5511#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5512 int j;
5513 struct tc_configuration *tc;
5514#endif
021230d4 5515
c44ade9e
JB		 5516 /* PCI config space info */
5517
5518 hw->vendor_id = pdev->vendor;
5519 hw->device_id = pdev->device;
5520 hw->revision_id = pdev->revision;
5521 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5522 hw->subsystem_device_id = pdev->subsystem_device;
5523
8fc3bb6d 5524 /* Set common capability flags and settings */
0f9b232b 5525 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5526 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5527 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5528 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5529 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5530 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5531 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5532 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5533#ifdef CONFIG_IXGBE_DCA
5534 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5535#endif
5536#ifdef IXGBE_FCOE
5537 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5538 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5539#ifdef CONFIG_IXGBE_DCB
5540 /* Default traffic class to use for FCoE */
5541 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5542#endif /* CONFIG_IXGBE_DCB */
5543#endif /* IXGBE_FCOE */
5544
5d7daa35
JK		 5545 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5546 hw->mac.num_rar_entries,
5547 GFP_ATOMIC);
530fd82a
AD		 5548 if (!adapter->mac_table)
5549 return -ENOMEM;
5d7daa35 5550
8fc3bb6d 5551 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5552 switch (hw->mac.type) {
5553 case ixgbe_mac_82598EB:
8fc3bb6d 5554 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5555
bf069c97
DS		 5556 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5557 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5558
49c7ffbe 5559 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5560 adapter->ring_feature[RING_F_FDIR].limit = 0;
5561 adapter->atr_sample_rate = 0;
5562 adapter->fdir_pballoc = 0;
5563#ifdef IXGBE_FCOE
5564 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5565 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5566#ifdef CONFIG_IXGBE_DCB
5567 adapter->fcoe.up = 0;
5568#endif /* IXGBE_DCB */
5569#endif /* IXGBE_FCOE */
5570 break;
5571 case ixgbe_mac_82599EB:
5572 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5573 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5574 break;
b93a2226 5575 case ixgbe_mac_X540:
9a900eca 5576 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5577 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5578 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5579 break;
9a75a1ac
DS		 5580 case ixgbe_mac_X550EM_x:
5581 case ixgbe_mac_X550:
5582#ifdef CONFIG_IXGBE_DCA
5583 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5584#endif
5585#ifdef CONFIG_IXGBE_VXLAN
5586 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5587#endif
5588 break;
bd508178
AD		 5589 default:
5590 break;
f8212f97 5591 }
2f90b865 5592
7c8ae65a
AD		 5593#ifdef IXGBE_FCOE
5594 /* FCoE support exists, always init the FCoE lock */
5595 spin_lock_init(&adapter->fcoe.lock);
5596
5597#endif
1fc5f038
AD		 5598 /* n-tuple support exists, always init our spinlock */
5599 spin_lock_init(&adapter->fdir_perfect_lock);
5600
7a6b6f51 5601#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5602 switch (hw->mac.type) {
5603 case ixgbe_mac_X540:
9a75a1ac
DS		 5604 case ixgbe_mac_X550:
5605 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5606 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5607 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5608 break;
5609 default:
5610 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5611 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5612 break;
5613 }
5614
2f90b865
AD		 5615 /* Configure DCB traffic classes */
5616 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5617 tc = &adapter->dcb_cfg.tc_config[j];
5618 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5619 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5620 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5621 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5622 tc->dcb_pfc = pfc_disabled;
5623 }
4de2a022
JF		 5624
5625 /* Initialize default user to priority mapping, UPx->TC0 */
5626 tc = &adapter->dcb_cfg.tc_config[0];
5627 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5628 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5629
2f90b865
AD		 5630 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5631 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5632 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5633 adapter->dcb_set_bitmap = 0x00;
3032309b 5634 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5635 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5636 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5637
5638#endif
9a799d71
AK		 5639
5640 /* default flow control settings */
cd7664f6 5641 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5642 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5643 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5644 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5645 hw->fc.send_xon = true;
73d80953 5646 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5647
99d74487 5648#ifdef CONFIG_PCI_IOV
170e8543
JK		 5649 if (max_vfs > 0)
5650 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5651
99d74487 5652 /* assign number of SR-IOV VFs */
170e8543 5653 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5654 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5655 adapter->num_vfs = 0;
5656 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5657 } else {
5658 adapter->num_vfs = max_vfs;
5659 }
5660 }
5661#endif /* CONFIG_PCI_IOV */
99d74487 5662
30efa5a3 5663 /* enable itr by default in dynamic mode */
f7554a2b 5664 adapter->rx_itr_setting = 1;
f7554a2b 5665 adapter->tx_itr_setting = 1;
30efa5a3 5666
30efa5a3
JB		 5667 /* set default ring sizes */
5668 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5669 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5670
bd198058 5671 /* set default work limits */
59224555 5672 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5673
9a799d71 5674 /* initialize eeprom parameters */
c44ade9e 5675 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5676 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5677 return -EIO;
5678 }
5679
2a47fa45
JF		 5680 /* PF holds first pool slot */
5681 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5682 set_bit(__IXGBE_DOWN, &adapter->state);
5683
5684 return 0;
5685}
5686
5687/**
5688 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5689 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5690 *
5691 * Return 0 on success, negative on failure
5692 **/
b6ec895e 5693int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5694{
b6ec895e 5695 struct device *dev = tx_ring->dev;
de88eeeb 5696 int orig_node = dev_to_node(dev);
ca8dfe25 5697 int ring_node = -1;
9a799d71
AK		 5698 int size;
5699
3a581073 5700 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5701
5702 if (tx_ring->q_vector)
ca8dfe25 5703 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5704
ca8dfe25 5705 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5706 if (!tx_ring->tx_buffer_info)
89bf67f1 5707 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5708 if (!tx_ring->tx_buffer_info)
5709 goto err;
9a799d71 5710
827da44c
JS		 5711 u64_stats_init(&tx_ring->syncp);
5712
9a799d71 5713 /* round up to nearest 4K */
12207e49 5714 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5715 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5716
ca8dfe25 5717 set_dev_node(dev, ring_node);
de88eeeb
AD		 5718 tx_ring->desc = dma_alloc_coherent(dev,
5719 tx_ring->size,
5720 &tx_ring->dma,
5721 GFP_KERNEL);
5722 set_dev_node(dev, orig_node);
5723 if (!tx_ring->desc)
5724 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5725 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5726 if (!tx_ring->desc)
5727 goto err;
9a799d71 5728
3a581073
JB		 5729 tx_ring->next_to_use = 0;
5730 tx_ring->next_to_clean = 0;
9a799d71 5731 return 0;
e01c31a5
JB		 5732
5733err:
5734 vfree(tx_ring->tx_buffer_info);
5735 tx_ring->tx_buffer_info = NULL;
b6ec895e 5736 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5737 return -ENOMEM;
9a799d71
AK		 5738}
5739
69888674
AD		 5740/**
5741 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5742 * @adapter: board private structure
5743 *
5744 * If this function returns with an error, then it's possible one or
5745 * more of the rings is populated (while the rest are not). It is the
5746 * callers duty to clean those orphaned rings.
5747 *
5748 * Return 0 on success, negative on failure
5749 **/
5750static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5751{
5752 int i, err = 0;
5753
5754 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5755 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5756 if (!err)
5757 continue;
de3d5b94 5758
396e799c 5759 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5760 goto err_setup_tx;
69888674
AD		 5761 }
5762
de3d5b94
AD		 5763 return 0;
5764err_setup_tx:
5765 /* rewind the index freeing the rings as we go */
5766 while (i--)
5767 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5768 return err;
5769}
5770
9a799d71
AK		 5771/**
5772 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5773 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5774 *
5775 * Returns 0 on success, negative on failure
5776 **/
b6ec895e 5777int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5778{
b6ec895e 5779 struct device *dev = rx_ring->dev;
de88eeeb 5780 int orig_node = dev_to_node(dev);
ca8dfe25 5781 int ring_node = -1;
021230d4 5782 int size;
9a799d71 5783
3a581073 5784 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5785
5786 if (rx_ring->q_vector)
ca8dfe25 5787 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5788
ca8dfe25 5789 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5790 if (!rx_ring->rx_buffer_info)
89bf67f1 5791 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5792 if (!rx_ring->rx_buffer_info)
5793 goto err;
9a799d71 5794
827da44c
JS		 5795 u64_stats_init(&rx_ring->syncp);
5796
9a799d71 5797 /* Round up to nearest 4K */
3a581073
JB		 5798 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5799 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5800
ca8dfe25 5801 set_dev_node(dev, ring_node);
de88eeeb
AD		 5802 rx_ring->desc = dma_alloc_coherent(dev,
5803 rx_ring->size,
5804 &rx_ring->dma,
5805 GFP_KERNEL);
5806 set_dev_node(dev, orig_node);
5807 if (!rx_ring->desc)
5808 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5809 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5810 if (!rx_ring->desc)
5811 goto err;
9a799d71 5812
3a581073
JB		 5813 rx_ring->next_to_clean = 0;
5814 rx_ring->next_to_use = 0;
9a799d71
AK		 5815
5816 return 0;
b6ec895e
AD		 5817err:
5818 vfree(rx_ring->rx_buffer_info);
5819 rx_ring->rx_buffer_info = NULL;
5820 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5821 return -ENOMEM;
9a799d71
AK		 5822}
5823
69888674
AD		 5824/**
5825 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5826 * @adapter: board private structure
5827 *
5828 * If this function returns with an error, then it's possible one or
5829 * more of the rings is populated (while the rest are not). It is the
5830 * callers duty to clean those orphaned rings.
5831 *
5832 * Return 0 on success, negative on failure
5833 **/
69888674
AD		 5834static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5835{
5836 int i, err = 0;
5837
5838 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5839 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5840 if (!err)
5841 continue;
de3d5b94 5842
396e799c 5843 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5844 goto err_setup_rx;
69888674
AD		 5845 }
5846
7c8ae65a
AD		 5847#ifdef IXGBE_FCOE
5848 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5849 if (!err)
5850#endif
5851 return 0;
de3d5b94
AD		 5852err_setup_rx:
5853 /* rewind the index freeing the rings as we go */
5854 while (i--)
5855 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5856 return err;
5857}
5858
9a799d71
AK		 5859/**
5860 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5861 * @tx_ring: Tx descriptor ring for a specific queue
5862 *
5863 * Free all transmit software resources
5864 **/
b6ec895e 5865void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5866{
b6ec895e 5867 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5868
5869 vfree(tx_ring->tx_buffer_info);
5870 tx_ring->tx_buffer_info = NULL;
5871
b6ec895e
AD		 5872 /* if not set, then don't free */
5873 if (!tx_ring->desc)
5874 return;
5875
5876 dma_free_coherent(tx_ring->dev, tx_ring->size,
5877 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5878
5879 tx_ring->desc = NULL;
5880}
5881
5882/**
5883 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5884 * @adapter: board private structure
5885 *
5886 * Free all transmit software resources
5887 **/
5888static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5889{
5890 int i;
5891
5892 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5893 if (adapter->tx_ring[i]->desc)
b6ec895e 5894 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5895}
5896
5897/**
b4617240 5898 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5899 * @rx_ring: ring to clean the resources from
5900 *
5901 * Free all receive software resources
5902 **/
b6ec895e 5903void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5904{
b6ec895e 5905 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5906
5907 vfree(rx_ring->rx_buffer_info);
5908 rx_ring->rx_buffer_info = NULL;
5909
b6ec895e
AD		 5910 /* if not set, then don't free */
5911 if (!rx_ring->desc)
5912 return;
5913
5914 dma_free_coherent(rx_ring->dev, rx_ring->size,
5915 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5916
5917 rx_ring->desc = NULL;
5918}
5919
5920/**
5921 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5922 * @adapter: board private structure
5923 *
5924 * Free all receive software resources
5925 **/
5926static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5927{
5928 int i;
5929
7c8ae65a
AD		 5930#ifdef IXGBE_FCOE
5931 ixgbe_free_fcoe_ddp_resources(adapter);
5932
5933#endif
9a799d71 5934 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5935 if (adapter->rx_ring[i]->desc)
b6ec895e 5936 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5937}
5938
9a799d71
AK		 5939/**
5940 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5941 * @netdev: network interface device structure
5942 * @new_mtu: new value for maximum frame size
5943 *
5944 * Returns 0 on success, negative on failure
5945 **/
5946static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5947{
5948 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5949 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5950
42c783c5 5951 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5952 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5953 return -EINVAL;
5954
5955 /*
872844dd
AD		 5956 * For 82599EB we cannot allow legacy VFs to enable their receive
5957 * paths when MTU greater than 1500 is configured. So display a
5958 * warning that legacy VFs will be disabled.
655309e9
AD		 5959 */
5960 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5961 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5962 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5963 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5964
396e799c 5965 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5966
021230d4 5967 /* must set new MTU before calling down or up */
9a799d71
AK		 5968 netdev->mtu = new_mtu;
5969
d4f80882
AV		 5970 if (netif_running(netdev))
5971 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5972
5973 return 0;
5974}
5975
5976/**
5977 * ixgbe_open - Called when a network interface is made active
5978 * @netdev: network interface device structure
5979 *
5980 * Returns 0 on success, negative value on failure
5981 *
5982 * The open entry point is called when a network interface is made
5983 * active by the system (IFF_UP). At this point all resources needed
5984 * for transmit and receive operations are allocated, the interrupt
5985 * handler is registered with the OS, the watchdog timer is started,
5986 * and the stack is notified that the interface is ready.
5987 **/
5988static int ixgbe_open(struct net_device *netdev)
5989{
5990 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5991 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5992 int err, queues;
4bebfaa5
AK		 5993
5994 /* disallow open during test */
5995 if (test_bit(__IXGBE_TESTING, &adapter->state))
5996 return -EBUSY;
9a799d71 5997
54386467
JB		 5998 netif_carrier_off(netdev);
5999
9a799d71
AK		 6000 /* allocate transmit descriptors */
6001 err = ixgbe_setup_all_tx_resources(adapter);
6002 if (err)
6003 goto err_setup_tx;
6004
9a799d71
AK		 6005 /* allocate receive descriptors */
6006 err = ixgbe_setup_all_rx_resources(adapter);
6007 if (err)
6008 goto err_setup_rx;
6009
6010 ixgbe_configure(adapter);
6011
021230d4 6012 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6013 if (err)
6014 goto err_req_irq;
6015
ac802f5d 6016 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 6017 if (adapter->num_rx_pools > 1)
6018 queues = adapter->num_rx_queues_per_pool;
6019 else
6020 queues = adapter->num_tx_queues;
6021
6022 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6023 if (err)
6024 goto err_set_queues;
6025
2a47fa45
JF		 6026 if (adapter->num_rx_pools > 1 &&
6027 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6028 queues = IXGBE_MAX_L2A_QUEUES;
6029 else
6030 queues = adapter->num_rx_queues;
6031 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6032 if (err)
6033 goto err_set_queues;
6034
1a71ab24 6035 ixgbe_ptp_init(adapter);
1a71ab24 6036
c7ccde0f 6037 ixgbe_up_complete(adapter);
9a799d71 6038
67359c3c
MR		 6039 ixgbe_clear_vxlan_port(adapter);
6040#ifdef CONFIG_IXGBE_VXLAN
3f207800 6041 vxlan_get_rx_port(netdev);
3f207800 6042#endif
67359c3c 6043
9a799d71
AK		 6044 return 0;
6045
ac802f5d
AD		 6046err_set_queues:
6047 ixgbe_free_irq(adapter);
9a799d71 6048err_req_irq:
a20a1199 6049 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6050 if (hw->phy.ops.set_phy_power && !adapter->wol)
6051 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6052err_setup_rx:
a20a1199 6053 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6054err_setup_tx:
9a799d71
AK		 6055 ixgbe_reset(adapter);
6056
6057 return err;
6058}
6059
a0cccce2
JK		 6060static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6061{
6062 ixgbe_ptp_suspend(adapter);
6063
6ac74394
DS		 6064 if (adapter->hw.phy.ops.enter_lplu) {
6065 adapter->hw.phy.reset_disable = true;
6066 ixgbe_down(adapter);
6067 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6068 adapter->hw.phy.reset_disable = false;
6069 } else {
6070 ixgbe_down(adapter);
6071 }
6072
a0cccce2
JK		 6073 ixgbe_free_irq(adapter);
6074
6075 ixgbe_free_all_tx_resources(adapter);
6076 ixgbe_free_all_rx_resources(adapter);
6077}
6078
9a799d71
AK		 6079/**
6080 * ixgbe_close - Disables a network interface
6081 * @netdev: network interface device structure
6082 *
6083 * Returns 0, this is not allowed to fail
6084 *
6085 * The close entry point is called when an interface is de-activated
6086 * by the OS. The hardware is still under the drivers control, but
6087 * needs to be disabled. A global MAC reset is issued to stop the
6088 * hardware, and all transmit and receive resources are freed.
6089 **/
6090static int ixgbe_close(struct net_device *netdev)
6091{
6092 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6093
1a71ab24 6094 ixgbe_ptp_stop(adapter);
1a71ab24 6095
a0cccce2 6096 ixgbe_close_suspend(adapter);
9a799d71 6097
e4911d57
AD		 6098 ixgbe_fdir_filter_exit(adapter);
6099
5eba3699 6100 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6101
6102 return 0;
6103}
6104
b3c8b4ba
AD		 6105#ifdef CONFIG_PM
6106static int ixgbe_resume(struct pci_dev *pdev)
6107{
c60fbb00
AD		 6108 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6109 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6110 u32 err;
6111
0391bbe3 6112 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 6113 pci_set_power_state(pdev, PCI_D0);
6114 pci_restore_state(pdev);
656ab817
DS		 6115 /*
6116 * pci_restore_state clears dev->state_saved so call
6117 * pci_save_state to restore it.
6118 */
6119 pci_save_state(pdev);
9ce77666 6120
6121 err = pci_enable_device_mem(pdev);
b3c8b4ba 6122 if (err) {
849c4542 6123 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 6124 return err;
6125 }
4e857c58 6126 smp_mb__before_atomic();
41c62843 6127 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6128 pci_set_master(pdev);
6129
dd4d8ca6 6130 pci_wake_from_d3(pdev, false);
b3c8b4ba 6131
b3c8b4ba
AD		 6132 ixgbe_reset(adapter);
6133
495dce12
WJP		 6134 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6135
ac802f5d
AD		 6136 rtnl_lock();
6137 err = ixgbe_init_interrupt_scheme(adapter);
6138 if (!err && netif_running(netdev))
c60fbb00 6139 err = ixgbe_open(netdev);
ac802f5d
AD		 6140
6141 rtnl_unlock();
6142
6143 if (err)
6144 return err;
b3c8b4ba
AD		 6145
6146 netif_device_attach(netdev);
6147
6148 return 0;
6149}
b3c8b4ba 6150#endif /* CONFIG_PM */
9d8d05ae
RW		 6151
6152static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6153{
c60fbb00
AD		 6154 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6155 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 6156 struct ixgbe_hw *hw = &adapter->hw;
6157 u32 ctrl, fctrl;
6158 u32 wufc = adapter->wol;
b3c8b4ba
AD		 6159#ifdef CONFIG_PM
6160 int retval = 0;
6161#endif
6162
6163 netif_device_detach(netdev);
6164
499ab5cc 6165 rtnl_lock();
a0cccce2
JK		 6166 if (netif_running(netdev))
6167 ixgbe_close_suspend(adapter);
499ab5cc 6168 rtnl_unlock();
b3c8b4ba 6169
5f5ae6fc
AD		 6170 ixgbe_clear_interrupt_scheme(adapter);
6171
b3c8b4ba
AD		 6172#ifdef CONFIG_PM
6173 retval = pci_save_state(pdev);
6174 if (retval)
6175 return retval;
4df10466 6176
b3c8b4ba 6177#endif
f4f1040a
JK		 6178 if (hw->mac.ops.stop_link_on_d3)
6179 hw->mac.ops.stop_link_on_d3(hw);
6180
e8e26350
PW		 6181 if (wufc) {
6182 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6183
ec74a471
ET		 6184 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6185 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6186 hw->mac.ops.enable_tx_laser(hw);
6187
e8e26350
PW		 6188 /* turn on all-multi mode if wake on multicast is enabled */
6189 if (wufc & IXGBE_WUFC_MC) {
6190 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6191 fctrl |= IXGBE_FCTRL_MPE;
6192 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6193 }
6194
6195 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6196 ctrl |= IXGBE_CTRL_GIO_DIS;
6197 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6198
6199 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6200 } else {
6201 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6202 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6203 }
6204
bd508178
AD		 6205 switch (hw->mac.type) {
6206 case ixgbe_mac_82598EB:
dd4d8ca6 6207 pci_wake_from_d3(pdev, false);
bd508178
AD		 6208 break;
6209 case ixgbe_mac_82599EB:
b93a2226 6210 case ixgbe_mac_X540:
9a75a1ac
DS		 6211 case ixgbe_mac_X550:
6212 case ixgbe_mac_X550EM_x:
bd508178
AD		 6213 pci_wake_from_d3(pdev, !!wufc);
6214 break;
6215 default:
6216 break;
6217 }
b3c8b4ba 6218
9d8d05ae 6219 *enable_wake = !!wufc;
961fac88
DS		 6220 if (hw->phy.ops.set_phy_power && !*enable_wake)
6221 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6222
b3c8b4ba
AD		 6223 ixgbe_release_hw_control(adapter);
6224
41c62843
MR		 6225 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6226 pci_disable_device(pdev);
b3c8b4ba 6227
9d8d05ae
RW		 6228 return 0;
6229}
6230
6231#ifdef CONFIG_PM
6232static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6233{
6234 int retval;
6235 bool wake;
6236
6237 retval = __ixgbe_shutdown(pdev, &wake);
6238 if (retval)
6239 return retval;
6240
6241 if (wake) {
6242 pci_prepare_to_sleep(pdev);
6243 } else {
6244 pci_wake_from_d3(pdev, false);
6245 pci_set_power_state(pdev, PCI_D3hot);
6246 }
b3c8b4ba
AD		 6247
6248 return 0;
6249}
9d8d05ae 6250#endif /* CONFIG_PM */
b3c8b4ba
AD		 6251
6252static void ixgbe_shutdown(struct pci_dev *pdev)
6253{
9d8d05ae
RW		 6254 bool wake;
6255
6256 __ixgbe_shutdown(pdev, &wake);
6257
6258 if (system_state == SYSTEM_POWER_OFF) {
6259 pci_wake_from_d3(pdev, wake);
6260 pci_set_power_state(pdev, PCI_D3hot);
6261 }
b3c8b4ba
AD		 6262}
6263
9a799d71
AK		 6264/**
6265 * ixgbe_update_stats - Update the board statistics counters.
6266 * @adapter: board private structure
6267 **/
6268void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6269{
2d86f139 6270 struct net_device *netdev = adapter->netdev;
9a799d71 6271 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6272 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6273 u64 total_mpc = 0;
6274 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6275 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6276 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6277 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6278
d08935c2
DS		 6279 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6280 test_bit(__IXGBE_RESETTING, &adapter->state))
6281 return;
6282
94b982b2 6283 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6284 u64 rsc_count = 0;
94b982b2 6285 u64 rsc_flush = 0;
94b982b2 6286 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6287 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6288 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6289 }
6290 adapter->rsc_total_count = rsc_count;
6291 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6292 }
6293
5b7da515
AD		 6294 for (i = 0; i < adapter->num_rx_queues; i++) {
6295 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6296 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6297 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6298 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6299 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6300 bytes += rx_ring->stats.bytes;
6301 packets += rx_ring->stats.packets;
6302 }
6303 adapter->non_eop_descs = non_eop_descs;
6304 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6305 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6306 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6307 netdev->stats.rx_bytes = bytes;
6308 netdev->stats.rx_packets = packets;
6309
6310 bytes = 0;
6311 packets = 0;
7ca3bc58 6312 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6313 for (i = 0; i < adapter->num_tx_queues; i++) {
6314 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6315 restart_queue += tx_ring->tx_stats.restart_queue;
6316 tx_busy += tx_ring->tx_stats.tx_busy;
6317 bytes += tx_ring->stats.bytes;
6318 packets += tx_ring->stats.packets;
6319 }
eb985f09 6320 adapter->restart_queue = restart_queue;
5b7da515
AD		 6321 adapter->tx_busy = tx_busy;
6322 netdev->stats.tx_bytes = bytes;
6323 netdev->stats.tx_packets = packets;
7ca3bc58 6324
7ca647bd 6325 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6326
6327 /* 8 register reads */
6f11eef7
AV		 6328 for (i = 0; i < 8; i++) {
6329 /* for packet buffers not used, the register should read 0 */
6330 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6331 missed_rx += mpc;
7ca647bd
JP		 6332 hwstats->mpc[i] += mpc;
6333 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6334 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6335 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6336 switch (hw->mac.type) {
6337 case ixgbe_mac_82598EB:
1a70db4b
ET		 6338 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6339 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6340 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6341 hwstats->pxonrxc[i] +=
6342 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6343 break;
6344 case ixgbe_mac_82599EB:
b93a2226 6345 case ixgbe_mac_X540:
9a75a1ac
DS		 6346 case ixgbe_mac_X550:
6347 case ixgbe_mac_X550EM_x:
bd508178
AD		 6348 hwstats->pxonrxc[i] +=
6349 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6350 break;
6351 default:
6352 break;
e8e26350 6353 }
6f11eef7 6354 }
1a70db4b
ET		 6355
6356 /*16 register reads */
6357 for (i = 0; i < 16; i++) {
6358 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6359 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6360 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6361 (hw->mac.type == ixgbe_mac_X540) ||
6362 (hw->mac.type == ixgbe_mac_X550) ||
6363 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6364 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6365 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6366 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6367 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6368 }
6369 }
6370
7ca647bd 6371 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6372 /* work around hardware counting issue */
7ca647bd 6373 hwstats->gprc -= missed_rx;
6f11eef7 6374
c84d324c
JF		 6375 ixgbe_update_xoff_received(adapter);
6376
6f11eef7 6377 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6378 switch (hw->mac.type) {
6379 case ixgbe_mac_82598EB:
6380 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6381 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6382 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6383 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6384 break;
b93a2226 6385 case ixgbe_mac_X540:
9a75a1ac
DS		 6386 case ixgbe_mac_X550:
6387 case ixgbe_mac_X550EM_x:
6388 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6389 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6390 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6391 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6392 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6393 case ixgbe_mac_82599EB:
a4d4f629
AD		 6394 for (i = 0; i < 16; i++)
6395 adapter->hw_rx_no_dma_resources +=
6396 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6397 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6398 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6399 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6400 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6401 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6402 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6403 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6404 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6405 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6406#ifdef IXGBE_FCOE
7ca647bd
JP		 6407 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6408 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6409 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6410 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6411 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6412 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6413 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6414 if (adapter->fcoe.ddp_pool) {
6415 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6416 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6417 unsigned int cpu;
6418 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6419 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6420 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6421 noddp += ddp_pool->noddp;
6422 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6423 }
5a1ee270
AD		 6424 hwstats->fcoe_noddp = noddp;
6425 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6426 }
6d45522c 6427#endif /* IXGBE_FCOE */
bd508178
AD		 6428 break;
6429 default:
6430 break;
e8e26350 6431 }
9a799d71 6432 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6433 hwstats->bprc += bprc;
6434 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6435 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6436 hwstats->mprc -= bprc;
6437 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6438 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6439 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6440 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6441 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6442 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6443 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6444 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6445 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6446 hwstats->lxontxc += lxon;
6f11eef7 6447 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6448 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6449 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6450 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6451 /*
6452 * 82598 errata - tx of flow control packets is included in tx counters
6453 */
6454 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6455 hwstats->gptc -= xon_off_tot;
6456 hwstats->mptc -= xon_off_tot;
6457 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6458 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6459 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6460 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6461 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6462 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6463 hwstats->ptc64 -= xon_off_tot;
6464 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6465 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6466 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6467 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6468 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6469 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6470
6471 /* Fill out the OS statistics structure */
7ca647bd 6472 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6473
6474 /* Rx Errors */
7ca647bd 6475 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6476 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6477 netdev->stats.rx_length_errors = hwstats->rlec;
6478 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6479 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6480}
6481
6482/**
d034acf1 6483 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6484 * @adapter: pointer to the device adapter structure
9a799d71 6485 **/
d034acf1 6486static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6487{
cf8280ee 6488 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6489 int i;
cf8280ee 6490
d034acf1
AD		 6491 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6492 return;
6493
6494 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6495
d034acf1 6496 /* if interface is down do nothing */
fe49f04a 6497 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6498 return;
6499
6500 /* do nothing if we are not using signature filters */
6501 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6502 return;
6503
6504 adapter->fdir_overflow++;
6505
93c52dd0
AD		 6506 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6507 for (i = 0; i < adapter->num_tx_queues; i++)
6508 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6509 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6510 /* re-enable flow director interrupts */
6511 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6512 } else {
6513 e_err(probe, "failed to finish FDIR re-initialization, "
6514 "ignored adding FDIR ATR filters\n");
6515 }
93c52dd0
AD		 6516}
6517
6518/**
6519 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6520 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6521 *
6522 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6523 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6524 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6525 * determine if a hang has occurred.
93c52dd0
AD		 6526 */
6527static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6528{
cf8280ee 6529 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6530 u64 eics = 0;
6531 int i;
cf8280ee 6532
09f40aed 6533 /* If we're down, removing or resetting, just bail */
93c52dd0 6534 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6535 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6536 test_bit(__IXGBE_RESETTING, &adapter->state))
6537 return;
22d5a71b 6538
93c52dd0
AD		 6539 /* Force detection of hung controller */
6540 if (netif_carrier_ok(adapter->netdev)) {
6541 for (i = 0; i < adapter->num_tx_queues; i++)
6542 set_check_for_tx_hang(adapter->tx_ring[i]);
6543 }
22d5a71b 6544
fe49f04a
AD		 6545 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6546 /*
6547 * for legacy and MSI interrupts don't set any bits
6548 * that are enabled for EIAM, because this operation
6549 * would set *both* EIMS and EICS for any bit in EIAM
6550 */
6551 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6552 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6553 } else {
6554 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6555 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6556 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6557 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6558 eics |= ((u64)1 << i);
6559 }
cf8280ee 6560 }
9a799d71 6561
93c52dd0 6562 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6563 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6564}
6565
e8e26350 6566/**
93c52dd0 6567 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6568 * @adapter: pointer to the device adapter structure
6569 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6570 **/
93c52dd0 6571static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6572{
e8e26350 6573 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6574 u32 link_speed = adapter->link_speed;
6575 bool link_up = adapter->link_up;
041441d0 6576 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6577
93c52dd0
AD		 6578 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6579 return;
6580
6581 if (hw->mac.ops.check_link) {
6582 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6583 } else {
93c52dd0
AD		 6584 /* always assume link is up, if no check link function */
6585 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6586 link_up = true;
c4cf55e5 6587 }
041441d0
AD		 6588
6589 if (adapter->ixgbe_ieee_pfc)
6590 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6591
3ebe8fde 6592 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6593 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6594 ixgbe_set_rx_drop_en(adapter);
6595 }
93c52dd0
AD		 6596
6597 if (link_up ||
6598 time_after(jiffies, (adapter->link_check_timeout +
6599 IXGBE_TRY_LINK_TIMEOUT))) {
6600 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6601 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6602 IXGBE_WRITE_FLUSH(hw);
6603 }
6604
6605 adapter->link_up = link_up;
6606 adapter->link_speed = link_speed;
e8e26350
PW		 6607}
6608
107d3018
AD		 6609static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6610{
6611#ifdef CONFIG_IXGBE_DCB
6612 struct net_device *netdev = adapter->netdev;
6613 struct dcb_app app = {
6614 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6615 .protocol = 0,
6616 };
6617 u8 up = 0;
6618
6619 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6620 up = dcb_ieee_getapp_mask(netdev, &app);
6621
6622 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6623#endif
6624}
6625
e8e26350 6626/**
93c52dd0
AD		 6627 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6628 * print link up message
49ce9c2c 6629 * @adapter: pointer to the device adapter structure
e8e26350 6630 **/
93c52dd0 6631static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6632{
93c52dd0 6633 struct net_device *netdev = adapter->netdev;
e8e26350 6634 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6635 struct net_device *upper;
6636 struct list_head *iter;
93c52dd0 6637 u32 link_speed = adapter->link_speed;
454adb00 6638 const char *speed_str;
93c52dd0 6639 bool flow_rx, flow_tx;
e8e26350 6640
93c52dd0
AD		 6641 /* only continue if link was previously down */
6642 if (netif_carrier_ok(netdev))
a985b6c3 6643 return;
63d6e1d8 6644
93c52dd0 6645 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6646
93c52dd0
AD		 6647 switch (hw->mac.type) {
6648 case ixgbe_mac_82598EB: {
6649 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6650 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6651 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6652 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6653 }
6654 break;
6655 case ixgbe_mac_X540:
9a75a1ac
DS		 6656 case ixgbe_mac_X550:
6657 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6658 case ixgbe_mac_82599EB: {
6659 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6660 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6661 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6662 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6663 }
6664 break;
6665 default:
6666 flow_tx = false;
6667 flow_rx = false;
6668 break;
e8e26350 6669 }
3a6a4eda 6670
6cb562d6
JK		 6671 adapter->last_rx_ptp_check = jiffies;
6672
8fecf67c 6673 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6674 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6675
454adb00
MR		 6676 switch (link_speed) {
6677 case IXGBE_LINK_SPEED_10GB_FULL:
6678 speed_str = "10 Gbps";
6679 break;
6680 case IXGBE_LINK_SPEED_2_5GB_FULL:
6681 speed_str = "2.5 Gbps";
6682 break;
6683 case IXGBE_LINK_SPEED_1GB_FULL:
6684 speed_str = "1 Gbps";
6685 break;
6686 case IXGBE_LINK_SPEED_100_FULL:
6687 speed_str = "100 Mbps";
6688 break;
6689 default:
6690 speed_str = "unknown speed";
6691 break;
6692 }
6693 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6694 ((flow_rx && flow_tx) ? "RX/TX" :
6695 (flow_rx ? "RX" :
6696 (flow_tx ? "TX" : "None"))));
e8e26350 6697
93c52dd0 6698 netif_carrier_on(netdev);
93c52dd0 6699 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6700
cdc04dcc
ET		 6701 /* enable transmits */
6702 netif_tx_wake_all_queues(adapter->netdev);
6703
6704 /* enable any upper devices */
6705 rtnl_lock();
6706 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6707 if (netif_is_macvlan(upper)) {
6708 struct macvlan_dev *vlan = netdev_priv(upper);
6709
6710 if (vlan->fwd_priv)
6711 netif_tx_wake_all_queues(upper);
6712 }
6713 }
6714 rtnl_unlock();
6715
107d3018
AD		 6716 /* update the default user priority for VFs */
6717 ixgbe_update_default_up(adapter);
6718
befa2af7
AD		 6719 /* ping all the active vfs to let them know link has changed */
6720 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6721}
6722
c4cf55e5 6723/**
93c52dd0
AD		 6724 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6725 * print link down message
49ce9c2c 6726 * @adapter: pointer to the adapter structure
c4cf55e5 6727 **/
581330ba 6728static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6729{
cf8280ee 6730 struct net_device *netdev = adapter->netdev;
c4cf55e5 6731 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6732
93c52dd0
AD		 6733 adapter->link_up = false;
6734 adapter->link_speed = 0;
cf8280ee 6735
93c52dd0
AD		 6736 /* only continue if link was up previously */
6737 if (!netif_carrier_ok(netdev))
6738 return;
264857b8 6739
93c52dd0
AD		 6740 /* poll for SFP+ cable when link is down */
6741 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6742 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6743
8fecf67c 6744 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6745 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6746
93c52dd0
AD		 6747 e_info(drv, "NIC Link is Down\n");
6748 netif_carrier_off(netdev);
befa2af7
AD		 6749
6750 /* ping all the active vfs to let them know link has changed */
6751 ixgbe_ping_all_vfs(adapter);
93c52dd0 6752}
e8e26350 6753
07923c17
ET		 6754static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6755{
6756 int i;
6757
6758 for (i = 0; i < adapter->num_tx_queues; i++) {
6759 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6760
6761 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6762 return true;
6763 }
6764
6765 return false;
6766}
6767
6768static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6769{
6770 struct ixgbe_hw *hw = &adapter->hw;
6771 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6772 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6773
6774 int i, j;
6775
6776 if (!adapter->num_vfs)
6777 return false;
6778
9a75a1ac
DS		 6779 /* resetting the PF is only needed for MAC before X550 */
6780 if (hw->mac.type >= ixgbe_mac_X550)
6781 return false;
6782
07923c17
ET		 6783 for (i = 0; i < adapter->num_vfs; i++) {
6784 for (j = 0; j < q_per_pool; j++) {
6785 u32 h, t;
6786
6787 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6788 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6789
6790 if (h != t)
6791 return true;
6792 }
6793 }
6794
6795 return false;
6796}
6797
93c52dd0
AD		 6798/**
6799 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6800 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6801 **/
6802static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6803{
93c52dd0 6804 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6805 if (ixgbe_ring_tx_pending(adapter) ||
6806 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6807 /* We've lost link, so the controller stops DMA,
6808 * but we've got queued Tx work that's never going
6809 * to get done, so reset controller to flush Tx.
6810 * (Do the reset outside of interrupt context).
6811 */
12ff3f3b 6812 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6813 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6814 }
c4cf55e5 6815 }
c4cf55e5
PWJ		 6816}
6817
9079e416
ET		 6818#ifdef CONFIG_PCI_IOV
6819static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6820 struct pci_dev *vfdev)
6821{
6822 if (!pci_wait_for_pending_transaction(vfdev))
6823 e_dev_warn("Issuing VFLR with pending transactions\n");
6824
6825 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6826 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6827
6828 msleep(100);
6829}
6830
6831static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6832{
6833 struct ixgbe_hw *hw = &adapter->hw;
6834 struct pci_dev *pdev = adapter->pdev;
988d1307 6835 unsigned int vf;
9079e416 6836 u32 gpc;
9079e416
ET		 6837
6838 if (!(netif_carrier_ok(adapter->netdev)))
6839 return;
6840
6841 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6842 if (gpc) /* If incrementing then no need for the check below */
6843 return;
6844 /* Check to see if a bad DMA write target from an errant or
6845 * malicious VF has caused a PCIe error. If so then we can
6846 * issue a VFLR to the offending VF(s) and then resume without
6847 * requesting a full slot reset.
6848 */
6849
6850 if (!pdev)
6851 return;
6852
9079e416 6853 /* check status reg for all VFs owned by this PF */
988d1307
MR		 6854 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6855 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6856 u16 status_reg;
9079e416 6857
988d1307
MR		 6858 if (!vfdev)
6859 continue;
6860 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6861 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6862 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6863 ixgbe_issue_vf_flr(adapter, vfdev);
9079e416
ET		 6864 }
6865}
6866
a985b6c3
GR		 6867static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6868{
6869 u32 ssvpc;
6870
0584d999
GR		 6871 /* Do not perform spoof check for 82598 or if not in IOV mode */
6872 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6873 adapter->num_vfs == 0)
a985b6c3
GR		 6874 return;
6875
6876 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6877
6878 /*
6879 * ssvpc register is cleared on read, if zero then no
6880 * spoofed packets in the last interval.
6881 */
6882 if (!ssvpc)
6883 return;
6884
d6ea0754 6885 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6886}
9079e416
ET		 6887#else
6888static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6889{
6890}
6891
6892static void
6893ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6894{
6895}
6896#endif /* CONFIG_PCI_IOV */
6897
a985b6c3 6898
93c52dd0
AD		 6899/**
6900 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6901 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6902 **/
6903static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6904{
09f40aed 6905 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6906 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6907 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6908 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6909 return;
6910
6911 ixgbe_watchdog_update_link(adapter);
6912
6913 if (adapter->link_up)
6914 ixgbe_watchdog_link_is_up(adapter);
6915 else
6916 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6917
9079e416 6918 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6919 ixgbe_spoof_check(adapter);
9a799d71 6920 ixgbe_update_stats(adapter);
93c52dd0
AD		 6921
6922 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6923}
10eec955 6924
cf8280ee 6925/**
7086400d 6926 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6927 * @adapter: the ixgbe adapter structure
cf8280ee 6928 **/
7086400d 6929static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6930{
cf8280ee 6931 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6932 s32 err;
cf8280ee 6933
7086400d
AD		 6934 /* not searching for SFP so there is nothing to do here */
6935 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6936 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6937 return;
10eec955 6938
58e7cd24
MR		 6939 if (adapter->sfp_poll_time &&
6940 time_after(adapter->sfp_poll_time, jiffies))
6941 return; /* If not yet time to poll for SFP */
6942
7086400d
AD		 6943 /* someone else is in init, wait until next service event */
6944 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6945 return;
cf8280ee 6946
58e7cd24
MR		 6947 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6948
7086400d
AD		 6949 err = hw->phy.ops.identify_sfp(hw);
6950 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6951 goto sfp_out;
264857b8 6952
7086400d
AD		 6953 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6954 /* If no cable is present, then we need to reset
6955 * the next time we find a good cable. */
6956 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6957 }
9a799d71 6958
7086400d
AD		 6959 /* exit on error */
6960 if (err)
6961 goto sfp_out;
e8e26350 6962
7086400d
AD		 6963 /* exit if reset not needed */
6964 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6965 goto sfp_out;
9a799d71 6966
7086400d 6967 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6968
7086400d
AD		 6969 /*
6970 * A module may be identified correctly, but the EEPROM may not have
6971 * support for that module. setup_sfp() will fail in that case, so
6972 * we should not allow that module to load.
6973 */
6974 if (hw->mac.type == ixgbe_mac_82598EB)
6975 err = hw->phy.ops.reset(hw);
6976 else
6977 err = hw->mac.ops.setup_sfp(hw);
6978
6979 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6980 goto sfp_out;
6981
6982 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6983 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6984
6985sfp_out:
6986 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6987
6988 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6989 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6990 e_dev_err("failed to initialize because an unsupported "
6991 "SFP+ module type was detected.\n");
6992 e_dev_err("Reload the driver after installing a "
6993 "supported module.\n");
6994 unregister_netdev(adapter->netdev);
bc59fcda 6995 }
7086400d 6996}
bc59fcda 6997
7086400d
AD		 6998/**
6999 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7000 * @adapter: the ixgbe adapter structure
7086400d
AD		 7001 **/
7002static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7003{
7004 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 7005 u32 speed;
7006 bool autoneg = false;
7086400d
AD		 7007
7008 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7009 return;
7010
7011 /* someone else is in init, wait until next service event */
7012 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7013 return;
7014
7015 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7016
3d292265 7017 speed = hw->phy.autoneg_advertised;
ed33ff66 7018 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 7019 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 7020
7021 /* setup the highest link when no autoneg */
7022 if (!autoneg) {
7023 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7024 speed = IXGBE_LINK_SPEED_10GB_FULL;
7025 }
7026 }
7027
7086400d 7028 if (hw->mac.ops.setup_link)
fd0326f2 7029 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7030
7031 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7032 adapter->link_check_timeout = jiffies;
7033 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7034}
7035
7036/**
7037 * ixgbe_service_timer - Timer Call-back
7038 * @data: pointer to adapter cast into an unsigned long
7039 **/
7040static void ixgbe_service_timer(unsigned long data)
7041{
7042 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7043 unsigned long next_event_offset;
7044
6bb78cfb
AD		 7045 /* poll faster when waiting for link */
7046 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7047 next_event_offset = HZ / 10;
7048 else
7049 next_event_offset = HZ * 2;
83c61fa9 7050
7086400d
AD		 7051 /* Reset the timer */
7052 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7053
9079e416 7054 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7055}
7056
597f22d6
DS		 7057static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7058{
7059 struct ixgbe_hw *hw = &adapter->hw;
7060 u32 status;
7061
7062 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7063 return;
7064
7065 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7066
7067 if (!hw->phy.ops.handle_lasi)
7068 return;
7069
7070 status = hw->phy.ops.handle_lasi(&adapter->hw);
7071 if (status != IXGBE_ERR_OVERTEMP)
7072 return;
7073
7074 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7075}
7076
c83c6cbd
AD		 7077static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7078{
7079 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
7080 return;
7081
7082 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
7083
09f40aed 7084 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7085 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7086 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 7087 test_bit(__IXGBE_RESETTING, &adapter->state))
7088 return;
7089
7090 ixgbe_dump(adapter);
7091 netdev_err(adapter->netdev, "Reset adapter\n");
7092 adapter->tx_timeout_count++;
7093
8f4c5c9f 7094 rtnl_lock();
c83c6cbd 7095 ixgbe_reinit_locked(adapter);
8f4c5c9f 7096 rtnl_unlock();
c83c6cbd
AD		 7097}
7098
7086400d
AD		 7099/**
7100 * ixgbe_service_task - manages and runs subtasks
7101 * @work: pointer to work_struct containing our data
7102 **/
7103static void ixgbe_service_task(struct work_struct *work)
7104{
7105 struct ixgbe_adapter *adapter = container_of(work,
7106 struct ixgbe_adapter,
7107 service_task);
b0483c8f
MR		 7108 if (ixgbe_removed(adapter->hw.hw_addr)) {
7109 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7110 rtnl_lock();
7111 ixgbe_down(adapter);
7112 rtnl_unlock();
7113 }
7114 ixgbe_service_event_complete(adapter);
7115 return;
7116 }
67359c3c
MR		 7117#ifdef CONFIG_IXGBE_VXLAN
7118 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
7119 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
7120 vxlan_get_rx_port(adapter->netdev);
7121 }
7122#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 7123 ixgbe_reset_subtask(adapter);
597f22d6 7124 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7125 ixgbe_sfp_detection_subtask(adapter);
7126 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7127 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7128 ixgbe_watchdog_subtask(adapter);
d034acf1 7129 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7130 ixgbe_check_hang_subtask(adapter);
891dc082 7131
8fecf67c 7132 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 7133 ixgbe_ptp_overflow_check(adapter);
7134 ixgbe_ptp_rx_hang(adapter);
7135 }
7086400d
AD		 7136
7137 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7138}
7139
fd0db0ed
AD		 7140static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7141 struct ixgbe_tx_buffer *first,
244e27ad 7142 u8 *hdr_len)
897ab156 7143{
fd0db0ed 7144 struct sk_buff *skb = first->skb;
897ab156
AD		 7145 u32 vlan_macip_lens, type_tucmd;
7146 u32 mss_l4len_idx, l4len;
2049e1f6 7147 int err;
9a799d71 7148
8f4fbb9b
AD		 7149 if (skb->ip_summed != CHECKSUM_PARTIAL)
7150 return 0;
7151
897ab156
AD		 7152 if (!skb_is_gso(skb))
7153 return 0;
9a799d71 7154
2049e1f6
FR		 7155 err = skb_cow_head(skb, 0);
7156 if (err < 0)
7157 return err;
9a799d71 7158
897ab156
AD		 7159 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7160 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7161
a1108ffd 7162 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 7163 struct iphdr *iph = ip_hdr(skb);
7164 iph->tot_len = 0;
7165 iph->check = 0;
7166 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7167 iph->daddr, 0,
7168 IPPROTO_TCP,
7169 0);
7170 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 7171 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7172 IXGBE_TX_FLAGS_CSUM |
7173 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 7174 } else if (skb_is_gso_v6(skb)) {
7175 ipv6_hdr(skb)->payload_len = 0;
7176 tcp_hdr(skb)->check =
7177 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7178 &ipv6_hdr(skb)->daddr,
7179 0, IPPROTO_TCP, 0);
244e27ad
AD		 7180 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7181 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7182 }
7183
091a6246 7184 /* compute header lengths */
897ab156
AD		 7185 l4len = tcp_hdrlen(skb);
7186 *hdr_len = skb_transport_offset(skb) + l4len;
7187
091a6246
AD		 7188 /* update gso size and bytecount with header size */
7189 first->gso_segs = skb_shinfo(skb)->gso_segs;
7190 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7191
c44f5f51 7192 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 7193 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7194 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7195
7196 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7197 vlan_macip_lens = skb_network_header_len(skb);
7198 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7199 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7200
7201 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7202 mss_l4len_idx);
897ab156
AD		 7203
7204 return 1;
7205}
7206
244e27ad
AD		 7207static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7208 struct ixgbe_tx_buffer *first)
7ca647bd 7209{
fd0db0ed 7210 struct sk_buff *skb = first->skb;
897ab156
AD		 7211 u32 vlan_macip_lens = 0;
7212 u32 mss_l4len_idx = 0;
7213 u32 type_tucmd = 0;
7ca647bd 7214
897ab156 7215 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 7216 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7217 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7218 return;
f467bc06
MR		 7219 vlan_macip_lens = skb_network_offset(skb) <<
7220 IXGBE_ADVTXD_MACLEN_SHIFT;
897ab156
AD		 7221 } else {
7222 u8 l4_hdr = 0;
f467bc06
MR		 7223 union {
7224 struct iphdr *ipv4;
7225 struct ipv6hdr *ipv6;
7226 u8 *raw;
7227 } network_hdr;
7228 union {
7229 struct tcphdr *tcphdr;
7230 u8 *raw;
7231 } transport_hdr;
36a92d71 7232 __be16 frag_off;
f467bc06
MR		 7233
7234 if (skb->encapsulation) {
7235 network_hdr.raw = skb_inner_network_header(skb);
7236 transport_hdr.raw = skb_inner_transport_header(skb);
7237 vlan_macip_lens = skb_inner_network_offset(skb) <<
7238 IXGBE_ADVTXD_MACLEN_SHIFT;
7239 } else {
7240 network_hdr.raw = skb_network_header(skb);
7241 transport_hdr.raw = skb_transport_header(skb);
7242 vlan_macip_lens = skb_network_offset(skb) <<
7243 IXGBE_ADVTXD_MACLEN_SHIFT;
7244 }
7245
7246 /* use first 4 bits to determine IP version */
7247 switch (network_hdr.ipv4->version) {
7248 case IPVERSION:
7249 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
897ab156 7250 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
f467bc06 7251 l4_hdr = network_hdr.ipv4->protocol;
7ca647bd 7252 break;
f467bc06
MR		 7253 case 6:
7254 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7255 l4_hdr = network_hdr.ipv6->nexthdr;
36a92d71
MR		 7256 if (likely((transport_hdr.raw - network_hdr.raw) ==
7257 sizeof(struct ipv6hdr)))
7258 break;
7259 ipv6_skip_exthdr(skb, network_hdr.raw - skb->data +
7260 sizeof(struct ipv6hdr),
7261 &l4_hdr, &frag_off);
7262 if (unlikely(frag_off))
7263 l4_hdr = NEXTHDR_FRAGMENT;
897ab156
AD		 7264 break;
7265 default:
36a92d71 7266 break;
7ca647bd 7267 }
897ab156
AD		 7268
7269 switch (l4_hdr) {
7ca647bd 7270 case IPPROTO_TCP:
897ab156 7271 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
f467bc06 7272 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
897ab156 7273 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 7274 break;
7275 case IPPROTO_SCTP:
897ab156
AD		 7276 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7277 mss_l4len_idx = sizeof(struct sctphdr) <<
7278 IXGBE_ADVTXD_L4LEN_SHIFT;
7279 break;
7280 case IPPROTO_UDP:
7281 mss_l4len_idx = sizeof(struct udphdr) <<
7282 IXGBE_ADVTXD_L4LEN_SHIFT;
7283 break;
7284 default:
7285 if (unlikely(net_ratelimit())) {
7286 dev_warn(tx_ring->dev,
36a92d71
MR		 7287 "partial checksum, version=%d, l4 proto=%x\n",
7288 network_hdr.ipv4->version, l4_hdr);
897ab156 7289 }
36a92d71
MR		 7290 skb_checksum_help(skb);
7291 goto no_csum;
7ca647bd 7292 }
244e27ad
AD		 7293
7294 /* update TX checksum flag */
7295 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 7296 }
7297
36a92d71 7298no_csum:
244e27ad 7299 /* vlan_macip_lens: MACLEN, VLAN tag */
244e27ad 7300 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7301
897ab156
AD		 7302 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7303 type_tucmd, mss_l4len_idx);
9a799d71
AK		 7304}
7305
472148c3
AD		 7306#define IXGBE_SET_FLAG(_input, _flag, _result) \
7307 ((_flag <= _result) ? \
7308 ((u32)(_input & _flag) * (_result / _flag)) : \
7309 ((u32)(_input & _flag) / (_flag / _result)))
7310
7311static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7312{
d3d00239 7313 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7314 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7315 IXGBE_ADVTXD_DCMD_DEXT |
7316 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7317
d3d00239 7318 /* set HW vlan bit if vlan is present */
472148c3
AD		 7319 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7320 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7321
d3d00239 7322 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7323 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7324 IXGBE_ADVTXD_DCMD_TSE);
7325
7326 /* set timestamp bit if present */
7327 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7328 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7329
62748b7b 7330 /* insert frame checksum */
472148c3 7331 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7332
d3d00239
AD		 7333 return cmd_type;
7334}
9a799d71 7335
729739b7
AD		 7336static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7337 u32 tx_flags, unsigned int paylen)
d3d00239 7338{
472148c3 7339 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7340
d3d00239 7341 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7342 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7343 IXGBE_TX_FLAGS_CSUM,
7344 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7345
93f5b3c1 7346 /* enble IPv4 checksum for TSO */
472148c3
AD		 7347 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7348 IXGBE_TX_FLAGS_IPV4,
7349 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7350
7f9643fd
AD		 7351 /*
7352 * Check Context must be set if Tx switch is enabled, which it
7353 * always is for case where virtual functions are running
7354 */
472148c3
AD		 7355 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7356 IXGBE_TX_FLAGS_CC,
7357 IXGBE_ADVTXD_CC);
7f9643fd 7358
472148c3 7359 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7360}
44df32c5 7361
2367a173
DB		 7362static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7363{
7364 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7365
7366 /* Herbert's original patch had:
7367 * smp_mb__after_netif_stop_queue();
7368 * but since that doesn't exist yet, just open code it.
7369 */
7370 smp_mb();
7371
7372 /* We need to check again in a case another CPU has just
7373 * made room available.
7374 */
7375 if (likely(ixgbe_desc_unused(tx_ring) < size))
7376 return -EBUSY;
7377
7378 /* A reprieve! - use start_queue because it doesn't call schedule */
7379 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7380 ++tx_ring->tx_stats.restart_queue;
7381 return 0;
7382}
7383
7384static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7385{
7386 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7387 return 0;
7388
7389 return __ixgbe_maybe_stop_tx(tx_ring, size);
7390}
7391
d3d00239
AD		 7392#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7393 IXGBE_TXD_CMD_RS)
7394
7395static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7396 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7397 const u8 hdr_len)
7398{
fd0db0ed 7399 struct sk_buff *skb = first->skb;
729739b7 7400 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7401 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7402 struct skb_frag_struct *frag;
7403 dma_addr_t dma;
7404 unsigned int data_len, size;
244e27ad 7405 u32 tx_flags = first->tx_flags;
472148c3 7406 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7407 u16 i = tx_ring->next_to_use;
d3d00239 7408
729739b7
AD		 7409 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7410
ec718254
AD		 7411 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7412
7413 size = skb_headlen(skb);
7414 data_len = skb->data_len;
729739b7 7415
d3d00239
AD		 7416#ifdef IXGBE_FCOE
7417 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7418 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7419 size -= sizeof(struct fcoe_crc_eof) - data_len;
7420 data_len = 0;
729739b7
AD		 7421 } else {
7422 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7423 }
7424 }
44df32c5 7425
d3d00239 7426#endif
729739b7 7427 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7428
ec718254 7429 tx_buffer = first;
9a799d71 7430
ec718254
AD		 7431 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7432 if (dma_mapping_error(tx_ring->dev, dma))
7433 goto dma_error;
7434
7435 /* record length, and DMA address */
7436 dma_unmap_len_set(tx_buffer, len, size);
7437 dma_unmap_addr_set(tx_buffer, dma, dma);
7438
7439 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7440
729739b7 7441 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7442 tx_desc->read.cmd_type_len =
472148c3 7443 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7444
d3d00239 7445 i++;
729739b7 7446 tx_desc++;
d3d00239 7447 if (i == tx_ring->count) {
e4f74028 7448 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7449 i = 0;
7450 }
ec718254 7451 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7452
7453 dma += IXGBE_MAX_DATA_PER_TXD;
7454 size -= IXGBE_MAX_DATA_PER_TXD;
7455
7456 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7457 }
e5a43549 7458
729739b7
AD		 7459 if (likely(!data_len))
7460 break;
9a799d71 7461
472148c3 7462 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7463
729739b7
AD		 7464 i++;
7465 tx_desc++;
7466 if (i == tx_ring->count) {
7467 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7468 i = 0;
7469 }
ec718254 7470 tx_desc->read.olinfo_status = 0;
9a799d71 7471
d3d00239 7472#ifdef IXGBE_FCOE
9e903e08 7473 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7474#else
9e903e08 7475 size = skb_frag_size(frag);
d3d00239
AD		 7476#endif
7477 data_len -= size;
9a799d71 7478
729739b7
AD		 7479 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7480 DMA_TO_DEVICE);
9a799d71 7481
729739b7 7482 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7483 }
9a799d71 7484
729739b7 7485 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7486 cmd_type |= size | IXGBE_TXD_CMD;
7487 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7488
091a6246 7489 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7490
d3d00239
AD		 7491 /* set the timestamp */
7492 first->time_stamp = jiffies;
9a799d71
AK		 7493
7494 /*
729739b7
AD		 7495 * Force memory writes to complete before letting h/w know there
7496 * are new descriptors to fetch. (Only applicable for weak-ordered
7497 * memory model archs, such as IA-64).
7498 *
7499 * We also need this memory barrier to make certain all of the
7500 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7501 */
7502 wmb();
7503
d3d00239
AD		 7504 /* set next_to_watch value indicating a packet is present */
7505 first->next_to_watch = tx_desc;
7506
729739b7
AD		 7507 i++;
7508 if (i == tx_ring->count)
7509 i = 0;
7510
7511 tx_ring->next_to_use = i;
7512
2367a173
DB		 7513 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7514
7515 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7516 writel(i, tx_ring->tail);
7517
7518 /* we need this if more than one processor can write to our tail
7519 * at a time, it synchronizes IO on IA64/Altix systems
7520 */
7521 mmiowb();
9c938cdd 7522 }
2367a173 7523
d3d00239
AD		 7524 return;
7525dma_error:
729739b7 7526 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7527
7528 /* clear dma mappings for failed tx_buffer_info map */
7529 for (;;) {
729739b7
AD		 7530 tx_buffer = &tx_ring->tx_buffer_info[i];
7531 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7532 if (tx_buffer == first)
d3d00239
AD		 7533 break;
7534 if (i == 0)
7535 i = tx_ring->count;
7536 i--;
7537 }
7538
d3d00239 7539 tx_ring->next_to_use = i;
9a799d71
AK		 7540}
7541
fd0db0ed 7542static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7543 struct ixgbe_tx_buffer *first)
69830529
AD		 7544{
7545 struct ixgbe_q_vector *q_vector = ring->q_vector;
7546 union ixgbe_atr_hash_dword input = { .dword = 0 };
7547 union ixgbe_atr_hash_dword common = { .dword = 0 };
7548 union {
7549 unsigned char *network;
7550 struct iphdr *ipv4;
7551 struct ipv6hdr *ipv6;
7552 } hdr;
ee9e0f0b 7553 struct tcphdr *th;
67359c3c
MR		 7554 struct sk_buff *skb;
7555#ifdef CONFIG_IXGBE_VXLAN
7556 u8 encap = false;
7557#endif /* CONFIG_IXGBE_VXLAN */
905e4a41 7558 __be16 vlan_id;
c4cf55e5 7559
69830529
AD		 7560 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7561 if (!q_vector)
7562 return;
7563
7564 /* do nothing if sampling is disabled */
7565 if (!ring->atr_sample_rate)
d3ead241 7566 return;
c4cf55e5 7567
69830529 7568 ring->atr_count++;
c4cf55e5 7569
69830529 7570 /* snag network header to get L4 type and address */
67359c3c
MR		 7571 skb = first->skb;
7572 hdr.network = skb_network_header(skb);
7573 if (skb->encapsulation) {
7574#ifdef CONFIG_IXGBE_VXLAN
7575 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7576
67359c3c
MR		 7577 if (!adapter->vxlan_port)
7578 return;
7579 if (first->protocol != htons(ETH_P_IP) ||
7580 hdr.ipv4->version != IPVERSION ||
7581 hdr.ipv4->protocol != IPPROTO_UDP) {
7582 return;
7583 }
7584 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7585 return;
7586 encap = true;
7587 hdr.network = skb_inner_network_header(skb);
7588 th = inner_tcp_hdr(skb);
7589#else
69830529 7590 return;
67359c3c
MR		 7591#endif /* CONFIG_IXGBE_VXLAN */
7592 } else {
7593 /* Currently only IPv4/IPv6 with TCP is supported */
7594 if ((first->protocol != htons(ETH_P_IPV6) ||
7595 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7596 (first->protocol != htons(ETH_P_IP) ||
7597 hdr.ipv4->protocol != IPPROTO_TCP))
7598 return;
7599 th = tcp_hdr(skb);
7600 }
c4cf55e5 7601
66f32a8b
AD		 7602 /* skip this packet since it is invalid or the socket is closing */
7603 if (!th || th->fin)
69830529
AD		 7604 return;
7605
7606 /* sample on all syn packets or once every atr sample count */
7607 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7608 return;
7609
7610 /* reset sample count */
7611 ring->atr_count = 0;
7612
244e27ad 7613 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7614
7615 /*
7616 * src and dst are inverted, think how the receiver sees them
7617 *
7618 * The input is broken into two sections, a non-compressed section
7619 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7620 * is XORed together and stored in the compressed dword.
7621 */
7622 input.formatted.vlan_id = vlan_id;
7623
7624 /*
7625 * since src port and flex bytes occupy the same word XOR them together
7626 * and write the value to source port portion of compressed dword
7627 */
244e27ad 7628 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7629 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7630 else
244e27ad 7631 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7632 common.port.dst ^= th->source;
7633
a1108ffd 7634 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7635 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7636 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7637 } else {
7638 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7639 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7640 hdr.ipv6->saddr.s6_addr32[1] ^
7641 hdr.ipv6->saddr.s6_addr32[2] ^
7642 hdr.ipv6->saddr.s6_addr32[3] ^
7643 hdr.ipv6->daddr.s6_addr32[0] ^
7644 hdr.ipv6->daddr.s6_addr32[1] ^
7645 hdr.ipv6->daddr.s6_addr32[2] ^
7646 hdr.ipv6->daddr.s6_addr32[3];
7647 }
c4cf55e5 7648
67359c3c
MR		 7649#ifdef CONFIG_IXGBE_VXLAN
7650 if (encap)
7651 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7652#endif /* CONFIG_IXGBE_VXLAN */
7653
c4cf55e5 7654 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7655 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7656 input, common, ring->queue_index);
c4cf55e5
PWJ		 7657}
7658
f663dd9a 7659static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7660 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7661{
f663dd9a
JW		 7662 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7663#ifdef IXGBE_FCOE
97488bd1
AD		 7664 struct ixgbe_adapter *adapter;
7665 struct ixgbe_ring_feature *f;
7666 int txq;
f663dd9a
JW		 7667#endif
7668
7669 if (fwd_adapter)
7670 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7671
7672#ifdef IXGBE_FCOE
5e09a105 7673
97488bd1
AD		 7674 /*
7675 * only execute the code below if protocol is FCoE
7676 * or FIP and we have FCoE enabled on the adapter
7677 */
7678 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7679 case htons(ETH_P_FCOE):
7680 case htons(ETH_P_FIP):
97488bd1 7681 adapter = netdev_priv(dev);
c087663e 7682
97488bd1
AD		 7683 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7684 break;
7685 default:
99932d4f 7686 return fallback(dev, skb);
97488bd1 7687 }
c087663e 7688
97488bd1 7689 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7690
97488bd1
AD		 7691 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7692 smp_processor_id();
56075a98 7693
97488bd1
AD		 7694 while (txq >= f->indices)
7695 txq -= f->indices;
c4cf55e5 7696
97488bd1 7697 return txq + f->offset;
f663dd9a 7698#else
99932d4f 7699 return fallback(dev, skb);
f663dd9a 7700#endif
09a3b1f8
SH		 7701}
7702
fc77dc3c 7703netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7704 struct ixgbe_adapter *adapter,
7705 struct ixgbe_ring *tx_ring)
9a799d71 7706{
d3d00239 7707 struct ixgbe_tx_buffer *first;
5f715823 7708 int tso;
d3d00239 7709 u32 tx_flags = 0;
a535c30e 7710 unsigned short f;
a535c30e 7711 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7712 __be16 protocol = skb->protocol;
63544e9c 7713 u8 hdr_len = 0;
5e09a105 7714
a535c30e
AD		 7715 /*
7716 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7717 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7718 * + 2 desc gap to keep tail from touching head,
7719 * + 1 desc for context descriptor,
7720 * otherwise try next time
7721 */
a535c30e
AD		 7722 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7723 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7724
a535c30e
AD		 7725 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7726 tx_ring->tx_stats.tx_busy++;
7727 return NETDEV_TX_BUSY;
7728 }
7729
fd0db0ed
AD		 7730 /* record the location of the first descriptor for this packet */
7731 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7732 first->skb = skb;
091a6246
AD		 7733 first->bytecount = skb->len;
7734 first->gso_segs = 1;
fd0db0ed 7735
66f32a8b 7736 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7737 if (skb_vlan_tag_present(skb)) {
7738 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7739 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7740 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7741 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7742 struct vlan_hdr *vhdr, _vhdr;
7743 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7744 if (!vhdr)
7745 goto out_drop;
7746
9e0c5648
AD		 7747 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7748 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7749 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7750 }
0213668f 7751 protocol = vlan_get_protocol(skb);
66f32a8b 7752
d5234933
MR		 7753 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7754 adapter->ptp_clock &&
7755 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7756 &adapter->state)) {
3a6a4eda
JK		 7757 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7758 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7759
7760 /* schedule check for Tx timestamp */
7761 adapter->ptp_tx_skb = skb_get(skb);
7762 adapter->ptp_tx_start = jiffies;
7763 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7764 }
3a6a4eda 7765
ff29a86e
JK		 7766 skb_tx_timestamp(skb);
7767
9e0c5648
AD		 7768#ifdef CONFIG_PCI_IOV
7769 /*
7770 * Use the l2switch_enable flag - would be false if the DMA
7771 * Tx switch had been disabled.
7772 */
7773 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7774 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7775
7776#endif
32701dc2 7777 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7778 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7779 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7780 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7781 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7782 tx_flags |= (skb->priority & 0x7) <<
7783 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7784 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7785 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7786
7787 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7788 goto out_drop;
7789 vhdr = (struct vlan_ethhdr *)skb->data;
7790 vhdr->h_vlan_TCI = htons(tx_flags >>
7791 IXGBE_TX_FLAGS_VLAN_SHIFT);
7792 } else {
7793 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7794 }
9a799d71 7795 }
eacd73f7 7796
244e27ad
AD		 7797 /* record initial flags and protocol */
7798 first->tx_flags = tx_flags;
7799 first->protocol = protocol;
7800
eacd73f7 7801#ifdef IXGBE_FCOE
66f32a8b 7802 /* setup tx offload for FCoE */
a1108ffd 7803 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7804 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7805 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7806 if (tso < 0)
7807 goto out_drop;
9a799d71 7808
66f32a8b 7809 goto xmit_fcoe;
eacd73f7 7810 }
9a799d71 7811
66f32a8b 7812#endif /* IXGBE_FCOE */
244e27ad 7813 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7814 if (tso < 0)
897ab156 7815 goto out_drop;
244e27ad
AD		 7816 else if (!tso)
7817 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7818
7819 /* add the ATR filter if ATR is on */
7820 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7821 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7822
7823#ifdef IXGBE_FCOE
7824xmit_fcoe:
7825#endif /* IXGBE_FCOE */
244e27ad 7826 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7827
9a799d71 7828 return NETDEV_TX_OK;
897ab156
AD		 7829
7830out_drop:
fd0db0ed
AD		 7831 dev_kfree_skb_any(first->skb);
7832 first->skb = NULL;
7833
897ab156 7834 return NETDEV_TX_OK;
9a799d71
AK		 7835}
7836
2a47fa45
JF		 7837static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7838 struct net_device *netdev,
7839 struct ixgbe_ring *ring)
84418e3b
AD		 7840{
7841 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7842 struct ixgbe_ring *tx_ring;
7843
a50c29dd
AD		 7844 /*
7845 * The minimum packet size for olinfo paylen is 17 so pad the skb
7846 * in order to meet this minimum size requirement.
7847 */
a94d9e22
AD		 7848 if (skb_put_padto(skb, 17))
7849 return NETDEV_TX_OK;
a50c29dd 7850
2a47fa45
JF		 7851 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7852
fc77dc3c 7853 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7854}
7855
2a47fa45
JF		 7856static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7857 struct net_device *netdev)
7858{
7859 return __ixgbe_xmit_frame(skb, netdev, NULL);
7860}
7861
9a799d71
AK		 7862/**
7863 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7864 * @netdev: network interface device structure
7865 * @p: pointer to an address structure
7866 *
7867 * Returns 0 on success, negative on failure
7868 **/
7869static int ixgbe_set_mac(struct net_device *netdev, void *p)
7870{
7871 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7872 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7873 struct sockaddr *addr = p;
7874
7875 if (!is_valid_ether_addr(addr->sa_data))
7876 return -EADDRNOTAVAIL;
7877
7878 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7879 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7880
c9f53e63
AD		 7881 ixgbe_mac_set_default_filter(adapter);
7882
7883 return 0;
9a799d71
AK		 7884}
7885
6b73e10d
BH		 7886static int
7887ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7888{
7889 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7890 struct ixgbe_hw *hw = &adapter->hw;
7891 u16 value;
7892 int rc;
7893
7894 if (prtad != hw->phy.mdio.prtad)
7895 return -EINVAL;
7896 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7897 if (!rc)
7898 rc = value;
7899 return rc;
7900}
7901
7902static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7903 u16 addr, u16 value)
7904{
7905 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7906 struct ixgbe_hw *hw = &adapter->hw;
7907
7908 if (prtad != hw->phy.mdio.prtad)
7909 return -EINVAL;
7910 return hw->phy.ops.write_reg(hw, addr, devad, value);
7911}
7912
7913static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7914{
7915 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7916
3a6a4eda 7917 switch (cmd) {
3a6a4eda 7918 case SIOCSHWTSTAMP:
93501d48
JK		 7919 return ixgbe_ptp_set_ts_config(adapter, req);
7920 case SIOCGHWTSTAMP:
7921 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7922 default:
7923 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7924 }
6b73e10d
BH		 7925}
7926
0365e6e4
PW		 7927/**
7928 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7929 * netdev->dev_addrs
0365e6e4
PW		 7930 * @netdev: network interface device structure
7931 *
7932 * Returns non-zero on failure
7933 **/
7934static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7935{
7936 int err = 0;
7937 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7938 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7939
7fa7c9dc 7940 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7941 rtnl_lock();
7fa7c9dc 7942 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7943 rtnl_unlock();
7fa7c9dc
AD		 7944
7945 /* update SAN MAC vmdq pool selection */
7946 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7947 }
7948 return err;
7949}
7950
7951/**
7952 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7953 * netdev->dev_addrs
0365e6e4
PW		 7954 * @netdev: network interface device structure
7955 *
7956 * Returns non-zero on failure
7957 **/
7958static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7959{
7960 int err = 0;
7961 struct ixgbe_adapter *adapter = netdev_priv(dev);
7962 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7963
7964 if (is_valid_ether_addr(mac->san_addr)) {
7965 rtnl_lock();
7966 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7967 rtnl_unlock();
7968 }
7969 return err;
7970}
7971
9a799d71
AK		 7972#ifdef CONFIG_NET_POLL_CONTROLLER
7973/*
7974 * Polling 'interrupt' - used by things like netconsole to send skbs
7975 * without having to re-enable interrupts. It's not called while
7976 * the interrupt routine is executing.
7977 */
7978static void ixgbe_netpoll(struct net_device *netdev)
7979{
7980 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7981 int i;
9a799d71 7982
1a647bd2
AD		 7983 /* if interface is down do nothing */
7984 if (test_bit(__IXGBE_DOWN, &adapter->state))
7985 return;
7986
856f606e
AD		 7987 /* loop through and schedule all active queues */
7988 for (i = 0; i < adapter->num_q_vectors; i++)
7989 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 7990}
9a799d71 7991
581330ba 7992#endif
de1036b1
ED		 7993static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7994 struct rtnl_link_stats64 *stats)
7995{
7996 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7997 int i;
7998
1a51502b 7999 rcu_read_lock();
de1036b1 8000 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 8001 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8002 u64 bytes, packets;
8003 unsigned int start;
8004
1a51502b
ED		 8005 if (ring) {
8006 do {
57a7744e 8007 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8008 packets = ring->stats.packets;
8009 bytes = ring->stats.bytes;
57a7744e 8010 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8011 stats->rx_packets += packets;
8012 stats->rx_bytes += bytes;
8013 }
de1036b1 8014 }
1ac9ad13
ED		 8015
8016 for (i = 0; i < adapter->num_tx_queues; i++) {
8017 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8018 u64 bytes, packets;
8019 unsigned int start;
8020
8021 if (ring) {
8022 do {
57a7744e 8023 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 8024 packets = ring->stats.packets;
8025 bytes = ring->stats.bytes;
57a7744e 8026 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 8027 stats->tx_packets += packets;
8028 stats->tx_bytes += bytes;
8029 }
8030 }
1a51502b 8031 rcu_read_unlock();
de1036b1
ED		 8032 /* following stats updated by ixgbe_watchdog_task() */
8033 stats->multicast = netdev->stats.multicast;
8034 stats->rx_errors = netdev->stats.rx_errors;
8035 stats->rx_length_errors = netdev->stats.rx_length_errors;
8036 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8037 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8038 return stats;
8039}
8040
8af3c33f 8041#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8042/**
8043 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8044 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8045 * @tc: number of traffic classes currently enabled
8046 *
8047 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8048 * 802.1Q priority maps to a packet buffer that exists.
8049 */
8050static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8051{
8052 struct ixgbe_hw *hw = &adapter->hw;
8053 u32 reg, rsave;
8054 int i;
8055
8056 /* 82598 have a static priority to TC mapping that can not
8057 * be changed so no validation is needed.
8058 */
8059 if (hw->mac.type == ixgbe_mac_82598EB)
8060 return;
8061
8062 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8063 rsave = reg;
8064
8065 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8066 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8067
8068 /* If up2tc is out of bounds default to zero */
8069 if (up2tc > tc)
8070 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8071 }
8072
8073 if (reg != rsave)
8074 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8075
8076 return;
8077}
8078
02debdc9
AD		 8079/**
8080 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8081 * @adapter: Pointer to adapter struct
8082 *
8083 * Populate the netdev user priority to tc map
8084 */
8085static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8086{
8087 struct net_device *dev = adapter->netdev;
8088 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8089 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8090 u8 prio;
8091
8092 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8093 u8 tc = 0;
8094
8095 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8096 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8097 else if (ets)
8098 tc = ets->prio_tc[prio];
8099
8100 netdev_set_prio_tc_map(dev, prio, tc);
8101 }
8102}
8103
cca73c59 8104#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 8105/**
8106 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 8107 *
8108 * @netdev: net device to configure
8109 * @tc: number of traffic classes to enable
8110 */
8111int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8112{
8b1c0b24
JF		 8113 struct ixgbe_adapter *adapter = netdev_priv(dev);
8114 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 8115 bool pools;
8b1c0b24 8116
8b1c0b24 8117 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 8118 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8119 return -EINVAL;
8120
8121 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 8122 return -EINVAL;
8123
2a47fa45
JF		 8124 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8125 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8126 return -EBUSY;
8127
8b1c0b24 8128 /* Hardware has to reinitialize queues and interrupts to
52f33af8 8129 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 8130 * hardware is not flexible enough to do this dynamically.
8131 */
8132 if (netif_running(dev))
8133 ixgbe_close(dev);
8134 ixgbe_clear_interrupt_scheme(adapter);
8135
cca73c59 8136#ifdef CONFIG_IXGBE_DCB
e7589eab 8137 if (tc) {
8b1c0b24 8138 netdev_set_num_tc(dev, tc);
02debdc9
AD		 8139 ixgbe_set_prio_tc_map(adapter);
8140
e7589eab 8141 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 8142
943561d3
AD		 8143 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8144 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 8145 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 8146 }
e7589eab 8147 } else {
8b1c0b24 8148 netdev_reset_tc(dev);
02debdc9 8149
943561d3
AD		 8150 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8151 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 8152
8153 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 8154
8155 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8156 adapter->dcb_cfg.pfc_mode_enable = false;
8157 }
8158
8b1c0b24 8159 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 8160
8161#endif /* CONFIG_IXGBE_DCB */
8162 ixgbe_init_interrupt_scheme(adapter);
8163
8b1c0b24 8164 if (netif_running(dev))
cca73c59 8165 return ixgbe_open(dev);
8b1c0b24
JF		 8166
8167 return 0;
8168}
de1036b1 8169
da36b647
GR		 8170#ifdef CONFIG_PCI_IOV
8171void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8172{
8173 struct net_device *netdev = adapter->netdev;
8174
8175 rtnl_lock();
da36b647 8176 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 8177 rtnl_unlock();
8178}
8179
8180#endif
082757af
DS		 8181void ixgbe_do_reset(struct net_device *netdev)
8182{
8183 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8184
8185 if (netif_running(netdev))
8186 ixgbe_reinit_locked(adapter);
8187 else
8188 ixgbe_reset(adapter);
8189}
8190
c8f44aff 8191static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 8192 netdev_features_t features)
082757af
DS		 8193{
8194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8195
082757af 8196 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 8197 if (!(features & NETIF_F_RXCSUM))
8198 features &= ~NETIF_F_LRO;
082757af 8199
567d2de2
AD		 8200 /* Turn off LRO if not RSC capable */
8201 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8202 features &= ~NETIF_F_LRO;
8e2813f5 8203
567d2de2 8204 return features;
082757af
DS		 8205}
8206
c8f44aff 8207static int ixgbe_set_features(struct net_device *netdev,
567d2de2 8208 netdev_features_t features)
082757af
DS		 8209{
8210 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 8211 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 8212 bool need_reset = false;
8213
082757af 8214 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 8215 if (!(features & NETIF_F_LRO)) {
8216 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8217 need_reset = true;
567d2de2
AD		 8218 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8219 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8220 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8221 if (adapter->rx_itr_setting == 1 ||
8222 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8223 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8224 need_reset = true;
8225 } else if ((changed ^ features) & NETIF_F_LRO) {
8226 e_info(probe, "rx-usecs set too low, "
8227 "disabling RSC\n");
082757af
DS		 8228 }
8229 }
8230
8231 /*
8232 * Check if Flow Director n-tuple support was enabled or disabled. If
8233 * the state changed, we need to reset.
8234 */
39cb681b
AD		 8235 switch (features & NETIF_F_NTUPLE) {
8236 case NETIF_F_NTUPLE:
567d2de2 8237 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8238 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8239 need_reset = true;
8240
567d2de2
AD		 8241 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8242 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 8243 break;
8244 default:
8245 /* turn off perfect filters, enable ATR and reset */
8246 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8247 need_reset = true;
8248
8249 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8250
8251 /* We cannot enable ATR if SR-IOV is enabled */
8252 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8253 break;
8254
8255 /* We cannot enable ATR if we have 2 or more traffic classes */
8256 if (netdev_get_num_tc(netdev) > 1)
8257 break;
8258
8259 /* We cannot enable ATR if RSS is disabled */
8260 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8261 break;
8262
8263 /* A sample rate of 0 indicates ATR disabled */
8264 if (!adapter->atr_sample_rate)
8265 break;
8266
8267 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8268 break;
082757af
DS		 8269 }
8270
f646968f 8271 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 8272 ixgbe_vlan_strip_enable(adapter);
8273 else
8274 ixgbe_vlan_strip_disable(adapter);
8275
3f2d1c0f
BG		 8276 if (changed & NETIF_F_RXALL)
8277 need_reset = true;
8278
567d2de2 8279 netdev->features = features;
67359c3c
MR		 8280
8281#ifdef CONFIG_IXGBE_VXLAN
8282 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8283 if (features & NETIF_F_RXCSUM)
8284 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8285 else
8286 ixgbe_clear_vxlan_port(adapter);
8287 }
8288#endif /* CONFIG_IXGBE_VXLAN */
8289
082757af
DS		 8290 if (need_reset)
8291 ixgbe_do_reset(netdev);
8292
8293 return 0;
082757af
DS		 8294}
8295
67359c3c 8296#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8297/**
8298 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8299 * @dev: The port's netdev
8300 * @sa_family: Socket Family that VXLAN is notifiying us about
8301 * @port: New UDP port number that VXLAN started listening to
8302 **/
8303static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8304 __be16 port)
8305{
8306 struct ixgbe_adapter *adapter = netdev_priv(dev);
8307 struct ixgbe_hw *hw = &adapter->hw;
8308 u16 new_port = ntohs(port);
8309
67359c3c
MR		 8310 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8311 return;
8312
3f207800
DS		 8313 if (sa_family == AF_INET6)
8314 return;
8315
67359c3c 8316 if (adapter->vxlan_port == new_port)
3f207800 8317 return;
3f207800
DS		 8318
8319 if (adapter->vxlan_port) {
8320 netdev_info(dev,
67359c3c 8321 "Hit Max num of VXLAN ports, not adding port %d\n",
3f207800
DS		 8322 new_port);
8323 return;
8324 }
8325
8326 adapter->vxlan_port = new_port;
8327 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8328}
8329
8330/**
8331 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8332 * @dev: The port's netdev
8333 * @sa_family: Socket Family that VXLAN is notifying us about
8334 * @port: UDP port number that VXLAN stopped listening to
8335 **/
8336static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8337 __be16 port)
8338{
8339 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800
DS		 8340 u16 new_port = ntohs(port);
8341
67359c3c
MR		 8342 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8343 return;
8344
3f207800
DS		 8345 if (sa_family == AF_INET6)
8346 return;
8347
8348 if (adapter->vxlan_port != new_port) {
8349 netdev_info(dev, "Port %d was not found, not deleting\n",
8350 new_port);
8351 return;
8352 }
8353
67359c3c
MR		 8354 ixgbe_clear_vxlan_port(adapter);
8355 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8356}
67359c3c 8357#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8358
edc7d573 8359static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8360 struct net_device *dev,
f6f6424b 8361 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8362 u16 flags)
8363{
bcfd3432 8364 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8365 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 8366 struct ixgbe_adapter *adapter = netdev_priv(dev);
8367 u16 pool = VMDQ_P(0);
8368
8369 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 8370 return -ENOMEM;
0f4b0add
JF		 8371 }
8372
f6f6424b 8373 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8374}
8375
219efe97
DS		 8376/**
8377 * ixgbe_configure_bridge_mode - set various bridge modes
8378 * @adapter - the private structure
8379 * @mode - requested bridge mode
8380 *
8381 * Configure some settings require for various bridge modes.
8382 **/
8383static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8384 __u16 mode)
8385{
6d4c96ad
DS		 8386 struct ixgbe_hw *hw = &adapter->hw;
8387 unsigned int p, num_pools;
8388 u32 vmdctl;
8389
219efe97
DS		 8390 switch (mode) {
8391 case BRIDGE_MODE_VEPA:
6d4c96ad 8392 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8394
8395 /* must enable Rx switching replication to allow multicast
8396 * packet reception on all VFs, and to enable source address
8397 * pruning.
8398 */
8399 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8400 vmdctl |= IXGBE_VT_CTL_REPLEN;
8401 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8402
8403 /* enable Rx source address pruning. Note, this requires
8404 * replication to be enabled or else it does nothing.
8405 */
8406 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8407 for (p = 0; p < num_pools; p++) {
8408 if (hw->mac.ops.set_source_address_pruning)
8409 hw->mac.ops.set_source_address_pruning(hw,
8410 true,
8411 p);
8412 }
219efe97
DS		 8413 break;
8414 case BRIDGE_MODE_VEB:
6d4c96ad 8415 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8417 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8418
8419 /* disable Rx switching replication unless we have SR-IOV
8420 * virtual functions
8421 */
8422 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8423 if (!adapter->num_vfs)
8424 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8425 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8426
8427 /* disable Rx source address pruning, since we don't expect to
8428 * be receiving external loopback of our transmitted frames.
8429 */
8430 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8431 for (p = 0; p < num_pools; p++) {
8432 if (hw->mac.ops.set_source_address_pruning)
8433 hw->mac.ops.set_source_address_pruning(hw,
8434 false,
8435 p);
8436 }
219efe97
DS		 8437 break;
8438 default:
8439 return -EINVAL;
8440 }
8441
8442 adapter->bridge_mode = mode;
8443
8444 e_info(drv, "enabling bridge mode: %s\n",
8445 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8446
8447 return 0;
8448}
8449
815cccbf 8450static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8451 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8452{
8453 struct ixgbe_adapter *adapter = netdev_priv(dev);
8454 struct nlattr *attr, *br_spec;
8455 int rem;
8456
8457 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8458 return -EOPNOTSUPP;
8459
8460 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8461 if (!br_spec)
8462 return -EINVAL;
815cccbf
JF		 8463
8464 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8465 int status;
815cccbf 8466 __u16 mode;
815cccbf
JF		 8467
8468 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8469 continue;
8470
b7c1a314
TG		 8471 if (nla_len(attr) < sizeof(mode))
8472 return -EINVAL;
8473
815cccbf 8474 mode = nla_get_u16(attr);
219efe97
DS		 8475 status = ixgbe_configure_bridge_mode(adapter, mode);
8476 if (status)
8477 return status;
aa2bacb6
DS		 8478
8479 break;
815cccbf
JF		 8480 }
8481
8482 return 0;
8483}
8484
8485static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8486 struct net_device *dev,
46c264da 8487 u32 filter_mask, int nlflags)
815cccbf
JF		 8488{
8489 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8490
8491 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8492 return 0;
8493
aa2bacb6 8494 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8495 adapter->bridge_mode, 0, 0, nlflags,
8496 filter_mask, NULL);
815cccbf
JF		 8497}
8498
2a47fa45
JF		 8499static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8500{
8501 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8502 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8503 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8504 unsigned int limit;
2a47fa45
JF		 8505 int pool, err;
8506
aac2f1bf
JK		 8507 /* Hardware has a limited number of available pools. Each VF, and the
8508 * PF require a pool. Check to ensure we don't attempt to use more
8509 * then the available number of pools.
8510 */
8511 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8512 return ERR_PTR(-EINVAL);
8513
219354d4
JF		 8514#ifdef CONFIG_RPS
8515 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8516 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8517 vdev->name);
8518 return ERR_PTR(-EINVAL);
8519 }
8520#endif
2a47fa45 8521 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8522 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8523 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8524 netdev_info(pdev,
8525 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8526 pdev->name);
8527 return ERR_PTR(-EINVAL);
8528 }
8529
8530 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8531 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8532 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8533 return ERR_PTR(-EBUSY);
8534
bc52f951 8535 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8536 if (!fwd_adapter)
8537 return ERR_PTR(-ENOMEM);
8538
8539 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8540 adapter->num_rx_pools++;
8541 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8542 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8543
8544 /* Enable VMDq flag so device will be set in VM mode */
8545 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8546 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8547 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8548
8549 /* Force reinit of ring allocation with VMDQ enabled */
8550 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8551 if (err)
8552 goto fwd_add_err;
8553 fwd_adapter->pool = pool;
8554 fwd_adapter->real_adapter = adapter;
8555 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8556 if (err)
8557 goto fwd_add_err;
8558 netif_tx_start_all_queues(vdev);
8559 return fwd_adapter;
8560fwd_add_err:
8561 /* unwind counter and free adapter struct */
8562 netdev_info(pdev,
8563 "%s: dfwd hardware acceleration failed\n", vdev->name);
8564 clear_bit(pool, &adapter->fwd_bitmask);
8565 adapter->num_rx_pools--;
8566 kfree(fwd_adapter);
8567 return ERR_PTR(err);
8568}
8569
8570static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8571{
8572 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8573 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8574 unsigned int limit;
2a47fa45
JF		 8575
8576 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8577 adapter->num_rx_pools--;
8578
51f3773b
JF		 8579 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8580 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8581 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8582 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8583 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8584 fwd_adapter->pool, adapter->num_rx_pools,
8585 fwd_adapter->rx_base_queue,
8586 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8587 adapter->fwd_bitmask);
8588 kfree(fwd_adapter);
8589}
8590
f467bc06
MR		 8591#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8592static netdev_features_t
8593ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8594 netdev_features_t features)
8595{
8596 if (!skb->encapsulation)
8597 return features;
8598
8599 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8600 IXGBE_MAX_TUNNEL_HDR_LEN))
8601 return features & ~NETIF_F_ALL_CSUM;
8602
8603 return features;
8604}
8605
0edc3527 8606static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8607 .ndo_open = ixgbe_open,
0edc3527 8608 .ndo_stop = ixgbe_close,
00829823 8609 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8610 .ndo_select_queue = ixgbe_select_queue,
581330ba 8611 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8612 .ndo_validate_addr = eth_validate_addr,
8613 .ndo_set_mac_address = ixgbe_set_mac,
8614 .ndo_change_mtu = ixgbe_change_mtu,
8615 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8616 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8617 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8618 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8619 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8620 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8621 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8622 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8623 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 8624 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 8625 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8626 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8627#ifdef CONFIG_IXGBE_DCB
24095aa3 8628 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8629#endif
0edc3527
SH		 8630#ifdef CONFIG_NET_POLL_CONTROLLER
8631 .ndo_poll_controller = ixgbe_netpoll,
8632#endif
e0d1095a 8633#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8634 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8635#endif
332d4a7d
YZ		 8636#ifdef IXGBE_FCOE
8637 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8638 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8639 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8640 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8641 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8642 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8643 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8644#endif /* IXGBE_FCOE */
082757af
DS		 8645 .ndo_set_features = ixgbe_set_features,
8646 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8647 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8648 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8649 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8650 .ndo_dfwd_add_station = ixgbe_fwd_add,
8651 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8652#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8653 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8654 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8655#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8656 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8657};
8658
e027d1ae
JK		 8659/**
8660 * ixgbe_enumerate_functions - Get the number of ports this device has
8661 * @adapter: adapter structure
8662 *
8663 * This function enumerates the phsyical functions co-located on a single slot,
8664 * in order to determine how many ports a device has. This is most useful in
8665 * determining the required GT/s of PCIe bandwidth necessary for optimal
8666 * performance.
8667 **/
8668static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8669{
caafb95d 8670 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8671 int physfns = 0;
8672
f1f96579
JK		 8673 /* Some cards can not use the generic count PCIe functions method,
8674 * because they are behind a parent switch, so we hardcode these with
8675 * the correct number of functions.
e027d1ae 8676 */
8818970d 8677 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8678 physfns = 4;
8818970d
JK		 8679
8680 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8681 /* don't count virtual functions */
caafb95d
JK		 8682 if (entry->is_virtfn)
8683 continue;
8684
8685 /* When the devices on the bus don't all match our device ID,
8686 * we can't reliably determine the correct number of
8687 * functions. This can occur if a function has been direct
8688 * attached to a virtual machine using VT-d, for example. In
8689 * this case, simply return -1 to indicate this.
8690 */
8691 if ((entry->vendor != pdev->vendor) ||
8692 (entry->device != pdev->device))
8693 return -1;
8694
8695 physfns++;
e027d1ae
JK		 8696 }
8697
8698 return physfns;
8699}
8700
8e2813f5
JK		 8701/**
8702 * ixgbe_wol_supported - Check whether device supports WoL
8703 * @hw: hw specific details
8704 * @device_id: the device ID
8705 * @subdev_id: the subsystem device ID
8706 *
8707 * This function is used by probe and ethtool to determine
8708 * which devices have WoL support
8709 *
8710 **/
8711int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8712 u16 subdevice_id)
8713{
8714 struct ixgbe_hw *hw = &adapter->hw;
8715 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8716 int is_wol_supported = 0;
8717
8718 switch (device_id) {
8719 case IXGBE_DEV_ID_82599_SFP:
8720 /* Only these subdevices could supports WOL */
8721 switch (subdevice_id) {
87557440 8722 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8723 case IXGBE_SUBDEV_ID_82599_560FLR:
8724 /* only support first port */
8725 if (hw->bus.func != 0)
8726 break;
5700ff26 8727 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8728 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8729 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8730 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8731 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8732 is_wol_supported = 1;
8733 break;
8734 }
8735 break;
5daebbb0
DS		 8736 case IXGBE_DEV_ID_82599EN_SFP:
8737 /* Only this subdevice supports WOL */
8738 switch (subdevice_id) {
8739 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8740 is_wol_supported = 1;
8741 break;
8742 }
8743 break;
8e2813f5
JK		 8744 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8745 /* All except this subdevice support WOL */
8746 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8747 is_wol_supported = 1;
8748 break;
8749 case IXGBE_DEV_ID_82599_KX4:
8750 is_wol_supported = 1;
8751 break;
8752 case IXGBE_DEV_ID_X540T:
df376f0d 8753 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8754 case IXGBE_DEV_ID_X550T:
8755 case IXGBE_DEV_ID_X550EM_X_KX4:
8756 case IXGBE_DEV_ID_X550EM_X_KR:
8757 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8758 /* check eeprom to see if enabled wol */
8759 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8760 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8761 (hw->bus.func == 0))) {
8762 is_wol_supported = 1;
8763 }
8764 break;
8765 }
8766
8767 return is_wol_supported;
8768}
8769
c762dff2
MP		 8770/**
8771 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8772 * @adapter: Pointer to adapter struct
8773 */
8774static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8775{
8776#ifdef CONFIG_OF
8777 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8778 struct ixgbe_hw *hw = &adapter->hw;
8779 const unsigned char *addr;
8780
8781 addr = of_get_mac_address(dp);
8782 if (addr) {
8783 ether_addr_copy(hw->mac.perm_addr, addr);
8784 return;
8785 }
8786#endif /* CONFIG_OF */
8787
8788#ifdef CONFIG_SPARC
8789 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8790#endif /* CONFIG_SPARC */
8791}
8792
9a799d71
AK		 8793/**
8794 * ixgbe_probe - Device Initialization Routine
8795 * @pdev: PCI device information struct
8796 * @ent: entry in ixgbe_pci_tbl
8797 *
8798 * Returns 0 on success, negative on failure
8799 *
8800 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8801 * The OS initialization, configuring of the adapter private structure,
8802 * and a hardware reset occur.
8803 **/
1dd06ae8 8804static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8805{
8806 struct net_device *netdev;
8807 struct ixgbe_adapter *adapter = NULL;
8808 struct ixgbe_hw *hw;
8809 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8810 int i, err, pci_using_dac, expected_gts;
d3cb9869 8811 unsigned int indices = MAX_TX_QUEUES;
289700db 8812 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8813 bool disable_dev = false;
eacd73f7
YZ		 8814#ifdef IXGBE_FCOE
8815 u16 device_caps;
8816#endif
289700db 8817 u32 eec;
9a799d71 8818
bded64a7
AG		 8819 /* Catch broken hardware that put the wrong VF device ID in
8820 * the PCIe SR-IOV capability.
8821 */
8822 if (pdev->is_virtfn) {
8823 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8824 pci_name(pdev), pdev->vendor, pdev->device);
8825 return -EINVAL;
8826 }
8827
9ce77666 8828 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8829 if (err)
8830 return err;
8831
f5f2eda8 8832 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8833 pci_using_dac = 1;
8834 } else {
f5f2eda8 8835 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8836 if (err) {
f5f2eda8
RK		 8837 dev_err(&pdev->dev,
8838 "No usable DMA configuration, aborting\n");
8839 goto err_dma;
9a799d71
AK		 8840 }
8841 pci_using_dac = 0;
8842 }
8843
9ce77666 8844 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8845 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8846 if (err) {
b8bc0421
DC		 8847 dev_err(&pdev->dev,
8848 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8849 goto err_pci_reg;
8850 }
8851
19d5afd4 8852 pci_enable_pcie_error_reporting(pdev);
6fabd715 8853
9a799d71 8854 pci_set_master(pdev);
fb3b27bc 8855 pci_save_state(pdev);
9a799d71 8856
d3cb9869 8857 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8858#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8859 /* 8 TC w/ 4 queues per TC */
8860 indices = 4 * MAX_TRAFFIC_CLASS;
8861#else
8862 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8863#endif
d3cb9869 8864 }
e901acd6 8865
c85a2618 8866 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8867 if (!netdev) {
8868 err = -ENOMEM;
8869 goto err_alloc_etherdev;
8870 }
8871
9a799d71
AK		 8872 SET_NETDEV_DEV(netdev, &pdev->dev);
8873
9a799d71
AK		 8874 adapter = netdev_priv(netdev);
8875
8876 adapter->netdev = netdev;
8877 adapter->pdev = pdev;
8878 hw = &adapter->hw;
8879 hw->back = adapter;
b3f4d599 8880 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8881
05857980 8882 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8883 pci_resource_len(pdev, 0));
2a1a091c 8884 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8885 if (!hw->hw_addr) {
8886 err = -EIO;
8887 goto err_ioremap;
8888 }
8889
0edc3527 8890 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8891 ixgbe_set_ethtool_ops(netdev);
9a799d71 8892 netdev->watchdog_timeo = 5 * HZ;
339de30f 8893 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8894
9a799d71
AK		 8895 /* Setup hw api */
8896 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8897 hw->mac.type = ii->mac;
9a900eca 8898 hw->mvals = ii->mvals;
9a799d71 8899
c44ade9e
JB		 8900 /* EEPROM */
8901 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 8902 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 8903 if (ixgbe_removed(hw->hw_addr)) {
8904 err = -EIO;
8905 goto err_ioremap;
8906 }
c44ade9e
JB		 8907 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8908 if (!(eec & (1 << 8)))
8909 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8910
8911 /* PHY */
8912 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8913 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8914 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8915 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8916 hw->phy.mdio.mmds = 0;
8917 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8918 hw->phy.mdio.dev = netdev;
8919 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8920 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8921
8ca783ab 8922 ii->get_invariants(hw);
9a799d71
AK		 8923
8924 /* setup the private structure */
8925 err = ixgbe_sw_init(adapter);
8926 if (err)
8927 goto err_sw_init;
8928
e86bff0e 8929 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8930 switch (adapter->hw.mac.type) {
8931 case ixgbe_mac_82599EB:
8932 case ixgbe_mac_X540:
9a75a1ac
DS		 8933 case ixgbe_mac_X550:
8934 case ixgbe_mac_X550EM_x:
e86bff0e 8935 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8936 break;
8937 default:
8938 break;
8939 }
e86bff0e 8940
bf069c97
DS		 8941 /*
8942 * If there is a fan on this device and it has failed log the
8943 * failure.
8944 */
8945 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8946 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8947 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8948 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8949 }
8950
8ef78adc
PWJ		 8951 if (allow_unsupported_sfp)
8952 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8953
c44ade9e 8954 /* reset_hw fills in the perm_addr as well */
119fc60a 8955 hw->phy.reset_if_overtemp = true;
c44ade9e 8956 err = hw->mac.ops.reset_hw(hw);
119fc60a 8957 hw->phy.reset_if_overtemp = false;
29a8dca1 8958 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 8959 err = 0;
8960 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8961 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8962 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8963 goto err_sw_init;
8964 } else if (err) {
849c4542 8965 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8966 goto err_sw_init;
8967 }
8968
99d74487 8969#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8970 /* SR-IOV not supported on the 82598 */
8971 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8972 goto skip_sriov;
8973 /* Mailbox */
8974 ixgbe_init_mbx_params_pf(hw);
8975 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8976 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8977 ixgbe_enable_sriov(adapter);
60a1a680 8978skip_sriov:
1cdd1ec8 8979
99d74487 8980#endif
396e799c 8981 netdev->features = NETIF_F_SG |
e8e9f696 8982 NETIF_F_IP_CSUM |
082757af 8983 NETIF_F_IPV6_CSUM |
f646968f
PM		 8984 NETIF_F_HW_VLAN_CTAG_TX |
8985 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 8986 NETIF_F_TSO |
8987 NETIF_F_TSO6 |
082757af 8988 NETIF_F_RXHASH |
8bf1264d 8989 NETIF_F_RXCSUM;
9a799d71 8990
8bf1264d 8991 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8992
58be7666
DS		 8993 switch (adapter->hw.mac.type) {
8994 case ixgbe_mac_82599EB:
8995 case ixgbe_mac_X540:
9a75a1ac
DS		 8996 case ixgbe_mac_X550:
8997 case ixgbe_mac_X550EM_x:
45a5ead0 8998 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8999 netdev->hw_features |= NETIF_F_SCTP_CSUM |
9000 NETIF_F_NTUPLE;
58be7666
DS		 9001 break;
9002 default:
9003 break;
9004 }
45a5ead0 9005
3f2d1c0f 9006 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 9007 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 9008
ad31c402
JK		 9009 netdev->vlan_features |= NETIF_F_TSO;
9010 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 9011 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 9012 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 9013 netdev->vlan_features |= NETIF_F_SG;
9014
f467bc06
MR		 9015 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
9016 NETIF_F_IPV6_CSUM;
9017
01789349 9018 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 9019 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 9020
67359c3c 9021#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 9022 switch (adapter->hw.mac.type) {
9023 case ixgbe_mac_X550:
9024 case ixgbe_mac_X550EM_x:
67359c3c
MR		 9025 netdev->hw_enc_features |= NETIF_F_RXCSUM |
9026 NETIF_F_IP_CSUM |
9027 NETIF_F_IPV6_CSUM;
3f207800
DS		 9028 break;
9029 default:
9030 break;
9031 }
67359c3c 9032#endif /* CONFIG_IXGBE_VXLAN */
3f207800 9033
7a6b6f51 9034#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 9035 netdev->dcbnl_ops = &dcbnl_ops;
9036#endif
9037
eacd73f7 9038#ifdef IXGBE_FCOE
0d551589 9039 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 9040 unsigned int fcoe_l;
9041
eacd73f7
YZ		 9042 if (hw->mac.ops.get_device_caps) {
9043 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 9044 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9045 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 9046 }
7c8ae65a 9047
d3cb9869
AD		 9048
9049 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9050 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 9051
a58915c7
AD		 9052 netdev->features |= NETIF_F_FSO |
9053 NETIF_F_FCOE_CRC;
9054
7c8ae65a
AD		 9055 netdev->vlan_features |= NETIF_F_FSO |
9056 NETIF_F_FCOE_CRC |
9057 NETIF_F_FCOE_MTU;
5e09d7f6 9058 }
eacd73f7 9059#endif /* IXGBE_FCOE */
7b872a55 9060 if (pci_using_dac) {
9a799d71 9061 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 9062 netdev->vlan_features |= NETIF_F_HIGHDMA;
9063 }
9a799d71 9064
082757af
DS		 9065 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9066 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 9067 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 9068 netdev->features |= NETIF_F_LRO;
9069
9a799d71 9070 /* make sure the EEPROM is good */
c44ade9e 9071 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 9072 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 9073 err = -EIO;
35937c05 9074 goto err_sw_init;
9a799d71
AK		 9075 }
9076
c762dff2
MP		 9077 ixgbe_get_platform_mac_addr(adapter);
9078
9a799d71 9079 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 9080
aaeb6cdf 9081 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 9082 e_dev_err("invalid MAC address\n");
9a799d71 9083 err = -EIO;
35937c05 9084 goto err_sw_init;
9a799d71
AK		 9085 }
9086
c9f53e63 9087 ixgbe_mac_set_default_filter(adapter);
5d7daa35 9088
7086400d 9089 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 9090 (unsigned long) adapter);
9a799d71 9091
58cf663f
MR		 9092 if (ixgbe_removed(hw->hw_addr)) {
9093 err = -EIO;
9094 goto err_sw_init;
9095 }
7086400d 9096 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 9097 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 9098 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 9099
021230d4
AV		 9100 err = ixgbe_init_interrupt_scheme(adapter);
9101 if (err)
9102 goto err_sw_init;
9a799d71 9103
8e2813f5 9104 /* WOL not supported for all devices */
c23f5b6b 9105 adapter->wol = 0;
8e2813f5 9106 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 9107 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 9108 pdev->subsystem_device);
6b92b0ba 9109 if (hw->wol_enabled)
9417c464 9110 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 9111
e8e26350
PW		 9112 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9113
15e5209f
ET		 9114 /* save off EEPROM version number */
9115 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9116 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9117
04f165ef 9118 /* pick up the PCI bus settings for reporting later */
e027d1ae 9119 if (ixgbe_pcie_from_parent(hw))
b8e82001 9120 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 9121 else
9122 hw->mac.ops.get_bus_info(hw);
04f165ef 9123
e027d1ae
JK		 9124 /* calculate the expected PCIe bandwidth required for optimal
9125 * performance. Note that some older parts will never have enough
9126 * bandwidth due to being older generation PCIe parts. We clamp these
9127 * parts to ensure no warning is displayed if it can't be fixed.
9128 */
9129 switch (hw->mac.type) {
9130 case ixgbe_mac_82598EB:
9131 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9132 break;
9133 default:
9134 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9135 break;
0c254d86 9136 }
caafb95d
JK		 9137
9138 /* don't check link if we failed to enumerate functions */
9139 if (expected_gts > 0)
9140 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 9141
339de30f 9142 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 9143 if (err)
339de30f 9144 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 9145 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9146 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9147 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 9148 part_str);
6a2aae5a
JK		 9149 else
9150 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9151 hw->mac.type, hw->phy.type, part_str);
9152
9153 e_dev_info("%pM\n", netdev->dev_addr);
9154
9a799d71 9155 /* reset the hardware with the new settings */
794caeb2 9156 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 9157 if (err == IXGBE_ERR_EEPROM_VERSION) {
9158 /* We are running on a pre-production device, log a warning */
849c4542
ET		 9159 e_dev_warn("This device is a pre-production adapter/LOM. "
9160 "Please be aware there may be issues associated "
9161 "with your hardware. If you are experiencing "
9162 "problems please contact your Intel or hardware "
9163 "representative who provided you with this "
9164 "hardware.\n");
794caeb2 9165 }
9a799d71
AK		 9166 strcpy(netdev->name, "eth%d");
9167 err = register_netdev(netdev);
9168 if (err)
9169 goto err_register;
9170
0fb6a55c
ET		 9171 pci_set_drvdata(pdev, adapter);
9172
ec74a471
ET		 9173 /* power down the optics for 82599 SFP+ fiber */
9174 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 9175 hw->mac.ops.disable_tx_laser(hw);
9176
54386467
JB		 9177 /* carrier off reporting is important to ethtool even BEFORE open */
9178 netif_carrier_off(netdev);
9179
5dd2d332 9180#ifdef CONFIG_IXGBE_DCA
652f093f 9181 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 9182 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 9183 ixgbe_setup_dca(adapter);
9184 }
9185#endif
1cdd1ec8 9186 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 9187 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 9188 for (i = 0; i < adapter->num_vfs; i++)
9189 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9190 }
9191
2466dd9c
JK		 9192 /* firmware requires driver version to be 0xFFFFFFFF
9193 * since os does not support feature
9194 */
9612de92 9195 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 9196 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9197 0xFF);
9612de92 9198
0365e6e4
PW		 9199 /* add san mac addr to netdev */
9200 ixgbe_add_sanmac_netdev(netdev);
9a799d71 9201
ea81875a 9202 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 9203
1210982b 9204#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 9205 if (ixgbe_sysfs_init(adapter))
9206 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 9207#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9208
00949167 9209 ixgbe_dbg_adapter_init(adapter);
00949167 9210
d1a35ee2
ET		 9211 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9212 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 9213 hw->mac.ops.setup_link(hw,
9214 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9215 true);
9216
9a799d71
AK		 9217 return 0;
9218
9219err_register:
5eba3699 9220 ixgbe_release_hw_control(adapter);
7a921c93 9221 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 9222err_sw_init:
99d74487 9223 ixgbe_disable_sriov(adapter);
7086400d 9224 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 9225 iounmap(adapter->io_addr);
5d7daa35 9226 kfree(adapter->mac_table);
9a799d71 9227err_ioremap:
b5b2ffc0 9228 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9229 free_netdev(netdev);
9230err_alloc_etherdev:
e8e9f696
JP		 9231 pci_release_selected_regions(pdev,
9232 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 9233err_pci_reg:
9234err_dma:
b5b2ffc0 9235 if (!adapter || disable_dev)
41c62843 9236 pci_disable_device(pdev);
9a799d71
AK		 9237 return err;
9238}
9239
9240/**
9241 * ixgbe_remove - Device Removal Routine
9242 * @pdev: PCI device information struct
9243 *
9244 * ixgbe_remove is called by the PCI subsystem to alert the driver
9245 * that it should release a PCI device. The could be caused by a
9246 * Hot-Plug event, or because the driver is going to be removed from
9247 * memory.
9248 **/
9f9a12f8 9249static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9250{
c60fbb00 9251 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9252 struct net_device *netdev;
b5b2ffc0 9253 bool disable_dev;
9a799d71 9254
0fb6a55c
ET		 9255 /* if !adapter then we already cleaned up in probe */
9256 if (!adapter)
9257 return;
9258
9259 netdev = adapter->netdev;
00949167 9260 ixgbe_dbg_adapter_exit(adapter);
00949167 9261
09f40aed 9262 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9263 cancel_work_sync(&adapter->service_task);
9a799d71 9264
3a6a4eda 9265
5dd2d332 9266#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9267 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9268 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9269 dca_remove_requester(&pdev->dev);
9de7605e
MR		 9270 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9271 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 9272 }
9273
9274#endif
1210982b 9275#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9276 ixgbe_sysfs_exit(adapter);
1210982b 9277#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9278
0365e6e4
PW		 9279 /* remove the added san mac */
9280 ixgbe_del_sanmac_netdev(netdev);
9281
da36b647 9282#ifdef CONFIG_PCI_IOV
7837e286 9283 ixgbe_disable_sriov(adapter);
da36b647 9284#endif
6b010e9b
AW		 9285 if (netdev->reg_state == NETREG_REGISTERED)
9286 unregister_netdev(netdev);
9287
7a921c93 9288 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9289
021230d4 9290 ixgbe_release_hw_control(adapter);
9a799d71 9291
2b1588c3
AD		 9292#ifdef CONFIG_DCB
9293 kfree(adapter->ixgbe_ieee_pfc);
9294 kfree(adapter->ixgbe_ieee_ets);
9295
9296#endif
2a1a091c 9297 iounmap(adapter->io_addr);
9ce77666 9298 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9299 IORESOURCE_MEM));
9a799d71 9300
849c4542 9301 e_dev_info("complete\n");
021230d4 9302
5d7daa35 9303 kfree(adapter->mac_table);
b5b2ffc0 9304 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9305 free_netdev(netdev);
9306
19d5afd4 9307 pci_disable_pcie_error_reporting(pdev);
6fabd715 9308
b5b2ffc0 9309 if (disable_dev)
41c62843 9310 pci_disable_device(pdev);
9a799d71
AK		 9311}
9312
9313/**
9314 * ixgbe_io_error_detected - called when PCI error is detected
9315 * @pdev: Pointer to PCI device
9316 * @state: The current pci connection state
9317 *
9318 * This function is called after a PCI bus error affecting
9319 * this device has been detected.
9320 */
9321static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9322 pci_channel_state_t state)
9a799d71 9323{
c60fbb00
AD		 9324 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9325 struct net_device *netdev = adapter->netdev;
9a799d71 9326
83c61fa9 9327#ifdef CONFIG_PCI_IOV
14438464 9328 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9329 struct pci_dev *bdev, *vfdev;
9330 u32 dw0, dw1, dw2, dw3;
9331 int vf, pos;
9332 u16 req_id, pf_func;
9333
9334 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9335 adapter->num_vfs == 0)
9336 goto skip_bad_vf_detection;
9337
9338 bdev = pdev->bus->self;
62f87c0e 9339 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9340 bdev = bdev->bus->self;
9341
9342 if (!bdev)
9343 goto skip_bad_vf_detection;
9344
9345 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9346 if (!pos)
9347 goto skip_bad_vf_detection;
9348
14438464
MR		 9349 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9350 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9351 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9352 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9353 if (ixgbe_removed(hw->hw_addr))
9354 goto skip_bad_vf_detection;
83c61fa9
GR		 9355
9356 req_id = dw1 >> 16;
9357 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9358 if (!(req_id & 0x0080))
9359 goto skip_bad_vf_detection;
9360
9361 pf_func = req_id & 0x01;
9362 if ((pf_func & 1) == (pdev->devfn & 1)) {
9363 unsigned int device_id;
9364
9365 vf = (req_id & 0x7F) >> 1;
9366 e_dev_err("VF %d has caused a PCIe error\n", vf);
9367 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9368 "%8.8x\tdw3: %8.8x\n",
9369 dw0, dw1, dw2, dw3);
9370 switch (adapter->hw.mac.type) {
9371 case ixgbe_mac_82599EB:
9372 device_id = IXGBE_82599_VF_DEVICE_ID;
9373 break;
9374 case ixgbe_mac_X540:
9375 device_id = IXGBE_X540_VF_DEVICE_ID;
9376 break;
9a75a1ac
DS		 9377 case ixgbe_mac_X550:
9378 device_id = IXGBE_DEV_ID_X550_VF;
9379 break;
9380 case ixgbe_mac_X550EM_x:
9381 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9382 break;
83c61fa9
GR		 9383 default:
9384 device_id = 0;
9385 break;
9386 }
9387
9388 /* Find the pci device of the offending VF */
36e90319 9389 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9390 while (vfdev) {
9391 if (vfdev->devfn == (req_id & 0xFF))
9392 break;
36e90319 9393 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9394 device_id, vfdev);
9395 }
9396 /*
9397 * There's a slim chance the VF could have been hot plugged,
9398 * so if it is no longer present we don't need to issue the
9399 * VFLR. Just clean up the AER in that case.
9400 */
9401 if (vfdev) {
9079e416 9402 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9403 /* Free device reference count */
9404 pci_dev_put(vfdev);
83c61fa9
GR		 9405 }
9406
9407 pci_cleanup_aer_uncorrect_error_status(pdev);
9408 }
9409
9410 /*
9411 * Even though the error may have occurred on the other port
9412 * we still need to increment the vf error reference count for
9413 * both ports because the I/O resume function will be called
9414 * for both of them.
9415 */
9416 adapter->vferr_refcount++;
9417
9418 return PCI_ERS_RESULT_RECOVERED;
9419
9420skip_bad_vf_detection:
9421#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9422 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9423 return PCI_ERS_RESULT_DISCONNECT;
9424
41c62843 9425 rtnl_lock();
9a799d71
AK		 9426 netif_device_detach(netdev);
9427
41c62843
MR		 9428 if (state == pci_channel_io_perm_failure) {
9429 rtnl_unlock();
3044b8d1 9430 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9431 }
3044b8d1 9432
9a799d71
AK		 9433 if (netif_running(netdev))
9434 ixgbe_down(adapter);
41c62843
MR		 9435
9436 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9437 pci_disable_device(pdev);
9438 rtnl_unlock();
9a799d71 9439
b4617240 9440 /* Request a slot reset. */
9a799d71
AK		 9441 return PCI_ERS_RESULT_NEED_RESET;
9442}
9443
9444/**
9445 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9446 * @pdev: Pointer to PCI device
9447 *
9448 * Restart the card from scratch, as if from a cold-boot.
9449 */
9450static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9451{
c60fbb00 9452 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9453 pci_ers_result_t result;
9454 int err;
9a799d71 9455
9ce77666 9456 if (pci_enable_device_mem(pdev)) {
396e799c 9457 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9458 result = PCI_ERS_RESULT_DISCONNECT;
9459 } else {
4e857c58 9460 smp_mb__before_atomic();
41c62843 9461 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9462 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9463 pci_set_master(pdev);
9464 pci_restore_state(pdev);
c0e1f68b 9465 pci_save_state(pdev);
9a799d71 9466
dd4d8ca6 9467 pci_wake_from_d3(pdev, false);
9a799d71 9468
6fabd715 9469 ixgbe_reset(adapter);
88512539 9470 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9471 result = PCI_ERS_RESULT_RECOVERED;
9472 }
9473
9474 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9475 if (err) {
849c4542
ET		 9476 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9477 "failed 0x%0x\n", err);
6fabd715
PWJ		 9478 /* non-fatal, continue */
9479 }
9a799d71 9480
6fabd715 9481 return result;
9a799d71
AK		 9482}
9483
9484/**
9485 * ixgbe_io_resume - called when traffic can start flowing again.
9486 * @pdev: Pointer to PCI device
9487 *
9488 * This callback is called when the error recovery driver tells us that
9489 * its OK to resume normal operation.
9490 */
9491static void ixgbe_io_resume(struct pci_dev *pdev)
9492{
c60fbb00
AD		 9493 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9494 struct net_device *netdev = adapter->netdev;
9a799d71 9495
83c61fa9
GR		 9496#ifdef CONFIG_PCI_IOV
9497 if (adapter->vferr_refcount) {
9498 e_info(drv, "Resuming after VF err\n");
9499 adapter->vferr_refcount--;
9500 return;
9501 }
9502
9503#endif
c7ccde0f
AD		 9504 if (netif_running(netdev))
9505 ixgbe_up(adapter);
9a799d71
AK		 9506
9507 netif_device_attach(netdev);
9a799d71
AK		 9508}
9509
3646f0e5 9510static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9511 .error_detected = ixgbe_io_error_detected,
9512 .slot_reset = ixgbe_io_slot_reset,
9513 .resume = ixgbe_io_resume,
9514};
9515
9516static struct pci_driver ixgbe_driver = {
9517 .name = ixgbe_driver_name,
9518 .id_table = ixgbe_pci_tbl,
9519 .probe = ixgbe_probe,
9f9a12f8 9520 .remove = ixgbe_remove,
9a799d71
AK		 9521#ifdef CONFIG_PM
9522 .suspend = ixgbe_suspend,
9523 .resume = ixgbe_resume,
9524#endif
9525 .shutdown = ixgbe_shutdown,
da36b647 9526 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9527 .err_handler = &ixgbe_err_handler
9528};
9529
9530/**
9531 * ixgbe_init_module - Driver Registration Routine
9532 *
9533 * ixgbe_init_module is the first routine called when the driver is
9534 * loaded. All it does is register with the PCI subsystem.
9535 **/
9536static int __init ixgbe_init_module(void)
9537{
9538 int ret;
c7689578 9539 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9540 pr_info("%s\n", ixgbe_copyright);
9a799d71 9541
780484d8
MR		 9542 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9543 if (!ixgbe_wq) {
9544 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9545 return -ENOMEM;
9546 }
9547
00949167 9548 ixgbe_dbg_init();
00949167 9549
f01fc1a8
JK		 9550 ret = pci_register_driver(&ixgbe_driver);
9551 if (ret) {
f01fc1a8 9552 ixgbe_dbg_exit();
f01fc1a8
JK		 9553 return ret;
9554 }
9555
5dd2d332 9556#ifdef CONFIG_IXGBE_DCA
bd0362dd 9557 dca_register_notify(&dca_notifier);
bd0362dd 9558#endif
5dd2d332 9559
f01fc1a8 9560 return 0;
9a799d71 9561}
b4617240 9562
9a799d71
AK		 9563module_init(ixgbe_init_module);
9564
9565/**
9566 * ixgbe_exit_module - Driver Exit Cleanup Routine
9567 *
9568 * ixgbe_exit_module is called just before the driver is removed
9569 * from memory.
9570 **/
9571static void __exit ixgbe_exit_module(void)
9572{
5dd2d332 9573#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9574 dca_unregister_notify(&dca_notifier);
9575#endif
9a799d71 9576 pci_unregister_driver(&ixgbe_driver);
00949167 9577
00949167 9578 ixgbe_dbg_exit();
780484d8
MR		 9579 if (ixgbe_wq) {
9580 destroy_workqueue(ixgbe_wq);
9581 ixgbe_wq = NULL;
9582 }
9a799d71 9583}
bd0362dd 9584
5dd2d332 9585#ifdef CONFIG_IXGBE_DCA
bd0362dd 9586static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9587 void *p)
bd0362dd
JC		 9588{
9589 int ret_val;
9590
9591 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9592 __ixgbe_notify_dca);
bd0362dd
JC		 9593
9594 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9595}
b453368d 9596
5dd2d332 9597#endif /* CONFIG_IXGBE_DCA */
849c4542 9598
9a799d71
AK		 9599module_exit(ixgbe_exit_module);
9600
9601/* ixgbe_main.c */
Linux kernel - Deliverables
This page took 2.448513 seconds and 5 git commands to generate.