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igb: Don't receive packets when the napi budget == 0
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/ethtool.h>
01789349 46#include <linux/if.h>
9a799d71 47#include <linux/if_vlan.h>
2a47fa45 48#include <linux/if_macvlan.h>
815cccbf 49#include <linux/if_bridge.h>
70c71606 50#include <linux/prefetch.h>
eacd73f7 51#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 52
53#include "ixgbe.h"
54#include "ixgbe_common.h"
ee5f784a 55#include "ixgbe_dcb_82599.h"
1cdd1ec8 56#include "ixgbe_sriov.h"
9a799d71
AK		 57
58char ixgbe_driver_name[] = "ixgbe";
9c8eb720 59static const char ixgbe_driver_string[] =
e8e9f696 60 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 61#ifdef IXGBE_FCOE
ea81875a
NP		 62char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 64#else
65static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67#endif
f341c4e0 68#define DRV_VERSION "3.19.1-k"
9c8eb720 69const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 70static const char ixgbe_copyright[] =
0391bbe3 71 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 72
73static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 74 [board_82598] = &ixgbe_82598_info,
e8e26350 75 [board_82599] = &ixgbe_82599_info,
fe15e8e1 76 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 77};
78
79/* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 118 /* required last entry */
119 {0, }
120};
121MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
5dd2d332 123#ifdef CONFIG_IXGBE_DCA
bd0362dd 124static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 125 void *p);
bd0362dd
JC		 126static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130};
131#endif
132
1cdd1ec8
GR		 133#ifdef CONFIG_PCI_IOV
134static unsigned int max_vfs;
135module_param(max_vfs, uint, 0);
e8e9f696 136MODULE_PARM_DESC(max_vfs,
170e8543 137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 138#endif /* CONFIG_PCI_IOV */
139
8ef78adc
PWJ		 140static unsigned int allow_unsupported_sfp;
141module_param(allow_unsupported_sfp, uint, 0);
142MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
b3f4d599 145#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146static int debug = -1;
147module_param(debug, int, 0);
148MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
9a799d71
AK		 150MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
14438464
MR		 155static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
b8e82001
JK		 157static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159{
b8e82001
JK		 160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
c0798edf 171 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 172 return -1;
173
c0798edf 174 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
b8e82001
JK		 178 return 0;
179}
180
181static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182{
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202}
203
e027d1ae
JK		 204/**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214{
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 218 return true;
219 default:
220 return false;
221 }
222}
223
224static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226{
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
9f0a433c 255 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 273 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282}
283
7086400d
AD		 284static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285{
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290}
291
2a1a091c
MR		 292static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293{
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
b0483c8f 300 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 301}
302
303void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
304{
305 u32 value;
306
307 /* The following check not only optimizes a bit by not
308 * performing a read on the status register when the
309 * register just read was a status register read that
310 * returned IXGBE_FAILED_READ_REG. It also blocks any
311 * potential recursion.
312 */
313 if (reg == IXGBE_STATUS) {
314 ixgbe_remove_adapter(hw);
315 return;
316 }
317 value = ixgbe_read_reg(hw, IXGBE_STATUS);
318 if (value == IXGBE_FAILED_READ_REG)
319 ixgbe_remove_adapter(hw);
320}
321
14438464
MR		 322static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
323{
324 u16 value;
325
326 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
327 if (value == IXGBE_FAILED_READ_CFG_WORD) {
328 ixgbe_remove_adapter(hw);
329 return true;
330 }
331 return false;
332}
333
334u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
335{
336 struct ixgbe_adapter *adapter = hw->back;
337 u16 value;
338
339 if (ixgbe_removed(hw->hw_addr))
340 return IXGBE_FAILED_READ_CFG_WORD;
341 pci_read_config_word(adapter->pdev, reg, &value);
342 if (value == IXGBE_FAILED_READ_CFG_WORD &&
343 ixgbe_check_cfg_remove(hw, adapter->pdev))
344 return IXGBE_FAILED_READ_CFG_WORD;
345 return value;
346}
347
348#ifdef CONFIG_PCI_IOV
349static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
350{
351 struct ixgbe_adapter *adapter = hw->back;
352 u32 value;
353
354 if (ixgbe_removed(hw->hw_addr))
355 return IXGBE_FAILED_READ_CFG_DWORD;
356 pci_read_config_dword(adapter->pdev, reg, &value);
357 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
358 ixgbe_check_cfg_remove(hw, adapter->pdev))
359 return IXGBE_FAILED_READ_CFG_DWORD;
360 return value;
361}
362#endif /* CONFIG_PCI_IOV */
363
7086400d
AD		 364static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
365{
366 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
367
52f33af8 368 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 369 smp_mb__before_clear_bit();
370 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
371}
372
dcd79aeb
TI		 373struct ixgbe_reg_info {
374 u32 ofs;
375 char *name;
376};
377
378static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
379
380 /* General Registers */
381 {IXGBE_CTRL, "CTRL"},
382 {IXGBE_STATUS, "STATUS"},
383 {IXGBE_CTRL_EXT, "CTRL_EXT"},
384
385 /* Interrupt Registers */
386 {IXGBE_EICR, "EICR"},
387
388 /* RX Registers */
389 {IXGBE_SRRCTL(0), "SRRCTL"},
390 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
391 {IXGBE_RDLEN(0), "RDLEN"},
392 {IXGBE_RDH(0), "RDH"},
393 {IXGBE_RDT(0), "RDT"},
394 {IXGBE_RXDCTL(0), "RXDCTL"},
395 {IXGBE_RDBAL(0), "RDBAL"},
396 {IXGBE_RDBAH(0), "RDBAH"},
397
398 /* TX Registers */
399 {IXGBE_TDBAL(0), "TDBAL"},
400 {IXGBE_TDBAH(0), "TDBAH"},
401 {IXGBE_TDLEN(0), "TDLEN"},
402 {IXGBE_TDH(0), "TDH"},
403 {IXGBE_TDT(0), "TDT"},
404 {IXGBE_TXDCTL(0), "TXDCTL"},
405
406 /* List Terminator */
407 {}
408};
409
410
411/*
412 * ixgbe_regdump - register printout routine
413 */
414static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
415{
416 int i = 0, j = 0;
417 char rname[16];
418 u32 regs[64];
419
420 switch (reginfo->ofs) {
421 case IXGBE_SRRCTL(0):
422 for (i = 0; i < 64; i++)
423 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
424 break;
425 case IXGBE_DCA_RXCTRL(0):
426 for (i = 0; i < 64; i++)
427 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
428 break;
429 case IXGBE_RDLEN(0):
430 for (i = 0; i < 64; i++)
431 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
432 break;
433 case IXGBE_RDH(0):
434 for (i = 0; i < 64; i++)
435 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
436 break;
437 case IXGBE_RDT(0):
438 for (i = 0; i < 64; i++)
439 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
440 break;
441 case IXGBE_RXDCTL(0):
442 for (i = 0; i < 64; i++)
443 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
444 break;
445 case IXGBE_RDBAL(0):
446 for (i = 0; i < 64; i++)
447 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
448 break;
449 case IXGBE_RDBAH(0):
450 for (i = 0; i < 64; i++)
451 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
452 break;
453 case IXGBE_TDBAL(0):
454 for (i = 0; i < 64; i++)
455 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
456 break;
457 case IXGBE_TDBAH(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
460 break;
461 case IXGBE_TDLEN(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
464 break;
465 case IXGBE_TDH(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
468 break;
469 case IXGBE_TDT(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
472 break;
473 case IXGBE_TXDCTL(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
476 break;
477 default:
c7689578 478 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 479 IXGBE_READ_REG(hw, reginfo->ofs));
480 return;
481 }
482
483 for (i = 0; i < 8; i++) {
484 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 485 pr_err("%-15s", rname);
dcd79aeb 486 for (j = 0; j < 8; j++)
c7689578
JP		 487 pr_cont(" %08x", regs[i*8+j]);
488 pr_cont("\n");
dcd79aeb
TI		 489 }
490
491}
492
493/*
494 * ixgbe_dump - Print registers, tx-rings and rx-rings
495 */
496static void ixgbe_dump(struct ixgbe_adapter *adapter)
497{
498 struct net_device *netdev = adapter->netdev;
499 struct ixgbe_hw *hw = &adapter->hw;
500 struct ixgbe_reg_info *reginfo;
501 int n = 0;
502 struct ixgbe_ring *tx_ring;
729739b7 503 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 504 union ixgbe_adv_tx_desc *tx_desc;
505 struct my_u0 { u64 a; u64 b; } *u0;
506 struct ixgbe_ring *rx_ring;
507 union ixgbe_adv_rx_desc *rx_desc;
508 struct ixgbe_rx_buffer *rx_buffer_info;
509 u32 staterr;
510 int i = 0;
511
512 if (!netif_msg_hw(adapter))
513 return;
514
515 /* Print netdevice Info */
516 if (netdev) {
517 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 518 pr_info("Device Name state "
dcd79aeb 519 "trans_start last_rx\n");
c7689578
JP		 520 pr_info("%-15s %016lX %016lX %016lX\n",
521 netdev->name,
522 netdev->state,
523 netdev->trans_start,
524 netdev->last_rx);
dcd79aeb
TI		 525 }
526
527 /* Print Registers */
528 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 529 pr_info(" Register Name Value\n");
dcd79aeb
TI		 530 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
531 reginfo->name; reginfo++) {
532 ixgbe_regdump(hw, reginfo);
533 }
534
535 /* Print TX Ring Summary */
536 if (!netdev || !netif_running(netdev))
537 goto exit;
538
539 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 540 pr_info(" %s %s %s %s\n",
541 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
542 "leng", "ntw", "timestamp");
dcd79aeb
TI		 543 for (n = 0; n < adapter->num_tx_queues; n++) {
544 tx_ring = adapter->tx_ring[n];
729739b7 545 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 546 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 547 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 548 (u64)dma_unmap_addr(tx_buffer, dma),
549 dma_unmap_len(tx_buffer, len),
550 tx_buffer->next_to_watch,
551 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 552 }
553
554 /* Print TX Rings */
555 if (!netif_msg_tx_done(adapter))
556 goto rx_ring_summary;
557
558 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
559
560 /* Transmit Descriptor Formats
561 *
39ac868a 562 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 563 * +--------------------------------------------------------------+
564 * 0 | Buffer Address [63:0] |
565 * +--------------------------------------------------------------+
39ac868a 566 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 567 * +--------------------------------------------------------------+
568 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 569 *
570 * 82598 Advanced Transmit Descriptor (Write-Back Format)
571 * +--------------------------------------------------------------+
572 * 0 | RSV [63:0] |
573 * +--------------------------------------------------------------+
574 * 8 | RSV | STA | NXTSEQ |
575 * +--------------------------------------------------------------+
576 * 63 36 35 32 31 0
577 *
578 * 82599+ Advanced Transmit Descriptor
579 * +--------------------------------------------------------------+
580 * 0 | Buffer Address [63:0] |
581 * +--------------------------------------------------------------+
582 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
583 * +--------------------------------------------------------------+
584 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
585 *
586 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
587 * +--------------------------------------------------------------+
588 * 0 | RSV [63:0] |
589 * +--------------------------------------------------------------+
590 * 8 | RSV | STA | RSV |
591 * +--------------------------------------------------------------+
592 * 63 36 35 32 31 0
dcd79aeb
TI		 593 */
594
595 for (n = 0; n < adapter->num_tx_queues; n++) {
596 tx_ring = adapter->tx_ring[n];
c7689578
JP		 597 pr_info("------------------------------------\n");
598 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
599 pr_info("------------------------------------\n");
8ad88e37
JH		 600 pr_info("%s%s %s %s %s %s\n",
601 "T [desc] [address 63:0 ] ",
602 "[PlPOIdStDDt Ln] [bi->dma ] ",
603 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 604
605 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 606 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 607 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 608 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 609 if (dma_unmap_len(tx_buffer, len) > 0) {
610 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
611 i,
612 le64_to_cpu(u0->a),
613 le64_to_cpu(u0->b),
614 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 615 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 616 tx_buffer->next_to_watch,
617 (u64)tx_buffer->time_stamp,
618 tx_buffer->skb);
619 if (i == tx_ring->next_to_use &&
620 i == tx_ring->next_to_clean)
621 pr_cont(" NTC/U\n");
622 else if (i == tx_ring->next_to_use)
623 pr_cont(" NTU\n");
624 else if (i == tx_ring->next_to_clean)
625 pr_cont(" NTC\n");
626 else
627 pr_cont("\n");
628
629 if (netif_msg_pktdata(adapter) &&
630 tx_buffer->skb)
631 print_hex_dump(KERN_INFO, "",
632 DUMP_PREFIX_ADDRESS, 16, 1,
633 tx_buffer->skb->data,
634 dma_unmap_len(tx_buffer, len),
635 true);
636 }
dcd79aeb
TI		 637 }
638 }
639
640 /* Print RX Rings Summary */
641rx_ring_summary:
642 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 643 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 644 for (n = 0; n < adapter->num_rx_queues; n++) {
645 rx_ring = adapter->rx_ring[n];
c7689578
JP		 646 pr_info("%5d %5X %5X\n",
647 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 648 }
649
650 /* Print RX Rings */
651 if (!netif_msg_rx_status(adapter))
652 goto exit;
653
654 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
655
39ac868a
JH		 656 /* Receive Descriptor Formats
657 *
658 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 659 * 63 1 0
660 * +-----------------------------------------------------+
661 * 0 | Packet Buffer Address [63:1] |A0/NSE|
662 * +----------------------------------------------+------+
663 * 8 | Header Buffer Address [63:1] | DD |
664 * +-----------------------------------------------------+
665 *
666 *
39ac868a 667 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 668 *
669 * 63 48 47 32 31 30 21 20 16 15 4 3 0
670 * +------------------------------------------------------+
39ac868a
JH		 671 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
672 * | Packet | IP | | | | Type | Type |
673 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 674 * +------------------------------------------------------+
675 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
676 * +------------------------------------------------------+
677 * 63 48 47 32 31 20 19 0
39ac868a
JH		 678 *
679 * 82599+ Advanced Receive Descriptor (Read) Format
680 * 63 1 0
681 * +-----------------------------------------------------+
682 * 0 | Packet Buffer Address [63:1] |A0/NSE|
683 * +----------------------------------------------+------+
684 * 8 | Header Buffer Address [63:1] | DD |
685 * +-----------------------------------------------------+
686 *
687 *
688 * 82599+ Advanced Receive Descriptor (Write-Back) Format
689 *
690 * 63 48 47 32 31 30 21 20 17 16 4 3 0
691 * +------------------------------------------------------+
692 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
693 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
694 * |/ Flow Dir Flt ID | | | | | |
695 * +------------------------------------------------------+
696 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
697 * +------------------------------------------------------+
698 * 63 48 47 32 31 20 19 0
dcd79aeb 699 */
39ac868a 700
dcd79aeb
TI		 701 for (n = 0; n < adapter->num_rx_queues; n++) {
702 rx_ring = adapter->rx_ring[n];
c7689578
JP		 703 pr_info("------------------------------------\n");
704 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
705 pr_info("------------------------------------\n");
8ad88e37
JH		 706 pr_info("%s%s%s",
707 "R [desc] [ PktBuf A0] ",
708 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 709 "<-- Adv Rx Read format\n");
8ad88e37
JH		 710 pr_info("%s%s%s",
711 "RWB[desc] [PcsmIpSHl PtRs] ",
712 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 713 "<-- Adv Rx Write-Back format\n");
714
715 for (i = 0; i < rx_ring->count; i++) {
716 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 717 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 718 u0 = (struct my_u0 *)rx_desc;
719 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
720 if (staterr & IXGBE_RXD_STAT_DD) {
721 /* Descriptor Done */
c7689578 722 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 723 "%016llX ---------------- %p", i,
724 le64_to_cpu(u0->a),
725 le64_to_cpu(u0->b),
726 rx_buffer_info->skb);
727 } else {
c7689578 728 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 729 "%016llX %016llX %p", i,
730 le64_to_cpu(u0->a),
731 le64_to_cpu(u0->b),
732 (u64)rx_buffer_info->dma,
733 rx_buffer_info->skb);
734
9c50c035
ET		 735 if (netif_msg_pktdata(adapter) &&
736 rx_buffer_info->dma) {
dcd79aeb
TI		 737 print_hex_dump(KERN_INFO, "",
738 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 739 page_address(rx_buffer_info->page) +
740 rx_buffer_info->page_offset,
f800326d 741 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 742 }
743 }
744
745 if (i == rx_ring->next_to_use)
c7689578 746 pr_cont(" NTU\n");
dcd79aeb 747 else if (i == rx_ring->next_to_clean)
c7689578 748 pr_cont(" NTC\n");
dcd79aeb 749 else
c7689578 750 pr_cont("\n");
dcd79aeb
TI		 751
752 }
753 }
754
755exit:
756 return;
757}
758
5eba3699
AV		 759static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
760{
761 u32 ctrl_ext;
762
763 /* Let firmware take over control of h/w */
764 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
765 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 766 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 767}
768
769static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
770{
771 u32 ctrl_ext;
772
773 /* Let firmware know the driver has taken over */
774 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
775 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 776 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 777}
9a799d71 778
49ce9c2c 779/**
e8e26350
PW		 780 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
781 * @adapter: pointer to adapter struct
782 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
783 * @queue: queue to map the corresponding interrupt to
784 * @msix_vector: the vector to map to the corresponding queue
785 *
786 */
787static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 788 u8 queue, u8 msix_vector)
9a799d71
AK		 789{
790 u32 ivar, index;
e8e26350
PW		 791 struct ixgbe_hw *hw = &adapter->hw;
792 switch (hw->mac.type) {
793 case ixgbe_mac_82598EB:
794 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
795 if (direction == -1)
796 direction = 0;
797 index = (((direction * 64) + queue) >> 2) & 0x1F;
798 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
799 ivar &= ~(0xFF << (8 * (queue & 0x3)));
800 ivar |= (msix_vector << (8 * (queue & 0x3)));
801 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
802 break;
803 case ixgbe_mac_82599EB:
b93a2226 804 case ixgbe_mac_X540:
e8e26350
PW		 805 if (direction == -1) {
806 /* other causes */
807 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
808 index = ((queue & 1) * 8);
809 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
810 ivar &= ~(0xFF << index);
811 ivar |= (msix_vector << index);
812 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
813 break;
814 } else {
815 /* tx or rx causes */
816 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
817 index = ((16 * (queue & 1)) + (8 * direction));
818 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
819 ivar &= ~(0xFF << index);
820 ivar |= (msix_vector << index);
821 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
822 break;
823 }
824 default:
825 break;
826 }
9a799d71
AK		 827}
828
fe49f04a 829static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 830 u64 qmask)
fe49f04a
AD		 831{
832 u32 mask;
833
bd508178
AD		 834 switch (adapter->hw.mac.type) {
835 case ixgbe_mac_82598EB:
fe49f04a
AD		 836 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 838 break;
839 case ixgbe_mac_82599EB:
b93a2226 840 case ixgbe_mac_X540:
fe49f04a
AD		 841 mask = (qmask & 0xFFFFFFFF);
842 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
843 mask = (qmask >> 32);
844 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 845 break;
846 default:
847 break;
fe49f04a
AD		 848 }
849}
850
729739b7
AD		 851void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
852 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 853{
729739b7
AD		 854 if (tx_buffer->skb) {
855 dev_kfree_skb_any(tx_buffer->skb);
856 if (dma_unmap_len(tx_buffer, len))
d3d00239 857 dma_unmap_single(ring->dev,
729739b7
AD		 858 dma_unmap_addr(tx_buffer, dma),
859 dma_unmap_len(tx_buffer, len),
860 DMA_TO_DEVICE);
861 } else if (dma_unmap_len(tx_buffer, len)) {
862 dma_unmap_page(ring->dev,
863 dma_unmap_addr(tx_buffer, dma),
864 dma_unmap_len(tx_buffer, len),
865 DMA_TO_DEVICE);
e5a43549 866 }
729739b7
AD		 867 tx_buffer->next_to_watch = NULL;
868 tx_buffer->skb = NULL;
869 dma_unmap_len_set(tx_buffer, len, 0);
870 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 871}
872
943561d3 873static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 874{
875 struct ixgbe_hw *hw = &adapter->hw;
876 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 877 int i;
943561d3 878 u32 data;
c84d324c 879
943561d3
AD		 880 if ((hw->fc.current_mode != ixgbe_fc_full) &&
881 (hw->fc.current_mode != ixgbe_fc_rx_pause))
882 return;
c84d324c 883
943561d3
AD		 884 switch (hw->mac.type) {
885 case ixgbe_mac_82598EB:
886 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
887 break;
888 default:
889 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
890 }
891 hwstats->lxoffrxc += data;
c84d324c 892
943561d3
AD		 893 /* refill credits (no tx hang) if we received xoff */
894 if (!data)
c84d324c 895 return;
943561d3
AD		 896
897 for (i = 0; i < adapter->num_tx_queues; i++)
898 clear_bit(__IXGBE_HANG_CHECK_ARMED,
899 &adapter->tx_ring[i]->state);
900}
901
902static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
903{
904 struct ixgbe_hw *hw = &adapter->hw;
905 struct ixgbe_hw_stats *hwstats = &adapter->stats;
906 u32 xoff[8] = {0};
2afaa00d 907 u8 tc;
943561d3
AD		 908 int i;
909 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
910
911 if (adapter->ixgbe_ieee_pfc)
912 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
913
914 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
915 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 916 return;
943561d3 917 }
c84d324c
JF		 918
919 /* update stats for each tc, only valid with PFC enabled */
920 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 921 u32 pxoffrxc;
922
c84d324c
JF		 923 switch (hw->mac.type) {
924 case ixgbe_mac_82598EB:
2afaa00d 925 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 926 break;
c84d324c 927 default:
2afaa00d 928 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 929 }
2afaa00d
PN		 930 hwstats->pxoffrxc[i] += pxoffrxc;
931 /* Get the TC for given UP */
932 tc = netdev_get_prio_tc_map(adapter->netdev, i);
933 xoff[tc] += pxoffrxc;
c84d324c
JF		 934 }
935
936 /* disarm tx queues that have received xoff frames */
937 for (i = 0; i < adapter->num_tx_queues; i++) {
938 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 939
2afaa00d 940 tc = tx_ring->dcb_tc;
c84d324c
JF		 941 if (xoff[tc])
942 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 943 }
26f23d82
YZ		 944}
945
c84d324c 946static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 947{
7d7ce682 948 return ring->stats.packets;
c84d324c
JF		 949}
950
951static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
952{
2a47fa45
JF		 953 struct ixgbe_adapter *adapter;
954 struct ixgbe_hw *hw;
955 u32 head, tail;
956
957 if (ring->l2_accel_priv)
958 adapter = ring->l2_accel_priv->real_adapter;
959 else
960 adapter = netdev_priv(ring->netdev);
e01c31a5 961
2a47fa45
JF		 962 hw = &adapter->hw;
963 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
964 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 965
966 if (head != tail)
967 return (head < tail) ?
968 tail - head : (tail + ring->count - head);
969
970 return 0;
971}
972
973static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
974{
975 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
976 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
977 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
978 bool ret = false;
979
7d637bcc 980 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 981
982 /*
983 * Check for a hung queue, but be thorough. This verifies
984 * that a transmit has been completed since the previous
985 * check AND there is at least one packet pending. The
986 * ARMED bit is set to indicate a potential hang. The
987 * bit is cleared if a pause frame is received to remove
988 * false hang detection due to PFC or 802.3x frames. By
989 * requiring this to fail twice we avoid races with
990 * pfc clearing the ARMED bit and conditions where we
991 * run the check_tx_hang logic with a transmit completion
992 * pending but without time to complete it yet.
993 */
994 if ((tx_done_old == tx_done) && tx_pending) {
995 /* make sure it is true for two checks in a row */
996 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
997 &tx_ring->state);
998 } else {
999 /* update completed stats and continue */
1000 tx_ring->tx_stats.tx_done_old = tx_done;
1001 /* reset the countdown */
1002 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 1003 }
1004
c84d324c 1005 return ret;
9a799d71
AK		 1006}
1007
c83c6cbd
AD		 1008/**
1009 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1010 * @adapter: driver private struct
1011 **/
1012static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1013{
1014
1015 /* Do the reset outside of interrupt context */
1016 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1017 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1018 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1019 ixgbe_service_event_schedule(adapter);
1020 }
1021}
e01c31a5 1022
9a799d71
AK		 1023/**
1024 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1025 * @q_vector: structure containing interrupt and ring information
e01c31a5 1026 * @tx_ring: tx ring to clean
9a799d71 1027 **/
fe49f04a 1028static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1029 struct ixgbe_ring *tx_ring)
9a799d71 1030{
fe49f04a 1031 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1032 struct ixgbe_tx_buffer *tx_buffer;
1033 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1034 unsigned int total_bytes = 0, total_packets = 0;
59224555 1035 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1036 unsigned int i = tx_ring->next_to_clean;
1037
1038 if (test_bit(__IXGBE_DOWN, &adapter->state))
1039 return true;
9a799d71 1040
d3d00239 1041 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1042 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1043 i -= tx_ring->count;
12207e49 1044
729739b7 1045 do {
d3d00239
AD		 1046 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1047
1048 /* if next_to_watch is not set then there is no work pending */
1049 if (!eop_desc)
1050 break;
1051
7f83a9e6 1052 /* prevent any other reads prior to eop_desc */
7e63bf49 1053 read_barrier_depends();
7f83a9e6 1054
d3d00239
AD		 1055 /* if DD is not set pending work has not been completed */
1056 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1057 break;
8ad494b0 1058
d3d00239
AD		 1059 /* clear next_to_watch to prevent false hangs */
1060 tx_buffer->next_to_watch = NULL;
8ad494b0 1061
091a6246
AD		 1062 /* update the statistics for this packet */
1063 total_bytes += tx_buffer->bytecount;
1064 total_packets += tx_buffer->gso_segs;
1065
fd0db0ed
AD		 1066 /* free the skb */
1067 dev_kfree_skb_any(tx_buffer->skb);
1068
729739b7
AD		 1069 /* unmap skb header data */
1070 dma_unmap_single(tx_ring->dev,
1071 dma_unmap_addr(tx_buffer, dma),
1072 dma_unmap_len(tx_buffer, len),
1073 DMA_TO_DEVICE);
1074
fd0db0ed
AD		 1075 /* clear tx_buffer data */
1076 tx_buffer->skb = NULL;
729739b7 1077 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1078
729739b7
AD		 1079 /* unmap remaining buffers */
1080 while (tx_desc != eop_desc) {
d3d00239
AD		 1081 tx_buffer++;
1082 tx_desc++;
8ad494b0 1083 i++;
729739b7
AD		 1084 if (unlikely(!i)) {
1085 i -= tx_ring->count;
d3d00239 1086 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1087 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1088 }
e01c31a5 1089
729739b7
AD		 1090 /* unmap any remaining paged data */
1091 if (dma_unmap_len(tx_buffer, len)) {
1092 dma_unmap_page(tx_ring->dev,
1093 dma_unmap_addr(tx_buffer, dma),
1094 dma_unmap_len(tx_buffer, len),
1095 DMA_TO_DEVICE);
1096 dma_unmap_len_set(tx_buffer, len, 0);
1097 }
1098 }
1099
1100 /* move us one more past the eop_desc for start of next pkt */
1101 tx_buffer++;
1102 tx_desc++;
1103 i++;
1104 if (unlikely(!i)) {
1105 i -= tx_ring->count;
1106 tx_buffer = tx_ring->tx_buffer_info;
1107 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1108 }
1109
1110 /* issue prefetch for next Tx descriptor */
1111 prefetch(tx_desc);
12207e49 1112
729739b7
AD		 1113 /* update budget accounting */
1114 budget--;
1115 } while (likely(budget));
1116
1117 i += tx_ring->count;
9a799d71 1118 tx_ring->next_to_clean = i;
d3d00239 1119 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1120 tx_ring->stats.bytes += total_bytes;
bd198058 1121 tx_ring->stats.packets += total_packets;
d3d00239 1122 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1123 q_vector->tx.total_bytes += total_bytes;
1124 q_vector->tx.total_packets += total_packets;
b953799e 1125
c84d324c
JF		 1126 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1127 /* schedule immediate reset if we believe we hung */
1128 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1129 e_err(drv, "Detected Tx Unit Hang\n"
1130 " Tx Queue <%d>\n"
1131 " TDH, TDT <%x>, <%x>\n"
1132 " next_to_use <%x>\n"
1133 " next_to_clean <%x>\n"
1134 "tx_buffer_info[next_to_clean]\n"
1135 " time_stamp <%lx>\n"
1136 " jiffies <%lx>\n",
1137 tx_ring->queue_index,
1138 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1139 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1140 tx_ring->next_to_use, i,
1141 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1142
1143 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1144
1145 e_info(probe,
1146 "tx hang %d detected on queue %d, resetting adapter\n",
1147 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1148
b953799e 1149 /* schedule immediate reset if we believe we hung */
c83c6cbd 1150 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1151
1152 /* the adapter is about to reset, no point in enabling stuff */
59224555 1153 return true;
b953799e 1154 }
9a799d71 1155
b2d96e0a
AD		 1156 netdev_tx_completed_queue(txring_txq(tx_ring),
1157 total_packets, total_bytes);
1158
e092be60 1159#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1160 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1161 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1162 /* Make sure that anybody stopping the queue after this
1163 * sees the new next_to_clean.
1164 */
1165 smp_mb();
729739b7
AD		 1166 if (__netif_subqueue_stopped(tx_ring->netdev,
1167 tx_ring->queue_index)
1168 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1169 netif_wake_subqueue(tx_ring->netdev,
1170 tx_ring->queue_index);
5b7da515 1171 ++tx_ring->tx_stats.restart_queue;
30eba97a 1172 }
e092be60 1173 }
9a799d71 1174
59224555 1175 return !!budget;
9a799d71
AK		 1176}
1177
5dd2d332 1178#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1179static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1180 struct ixgbe_ring *tx_ring,
33cf09c9 1181 int cpu)
bd0362dd 1182{
33cf09c9 1183 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1184 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1185 u16 reg_offset;
33cf09c9 1186
33cf09c9
AD		 1187 switch (hw->mac.type) {
1188 case ixgbe_mac_82598EB:
bdda1a61 1189 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1190 break;
1191 case ixgbe_mac_82599EB:
b93a2226 1192 case ixgbe_mac_X540:
bdda1a61
AD		 1193 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1194 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1195 break;
1196 default:
bdda1a61
AD		 1197 /* for unknown hardware do not write register */
1198 return;
bd0362dd 1199 }
bdda1a61
AD		 1200
1201 /*
1202 * We can enable relaxed ordering for reads, but not writes when
1203 * DCA is enabled. This is due to a known issue in some chipsets
1204 * which will cause the DCA tag to be cleared.
1205 */
1206 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1207 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1208 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1209
1210 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1211}
1212
bdda1a61
AD		 1213static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1214 struct ixgbe_ring *rx_ring,
33cf09c9 1215 int cpu)
bd0362dd 1216{
33cf09c9 1217 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1218 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1219 u8 reg_idx = rx_ring->reg_idx;
1220
33cf09c9
AD		 1221
1222 switch (hw->mac.type) {
33cf09c9 1223 case ixgbe_mac_82599EB:
b93a2226 1224 case ixgbe_mac_X540:
bdda1a61 1225 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1226 break;
1227 default:
1228 break;
1229 }
bdda1a61
AD		 1230
1231 /*
1232 * We can enable relaxed ordering for reads, but not writes when
1233 * DCA is enabled. This is due to a known issue in some chipsets
1234 * which will cause the DCA tag to be cleared.
1235 */
1236 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1237 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1238
1239 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1240}
1241
1242static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1243{
1244 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1245 struct ixgbe_ring *ring;
bd0362dd 1246 int cpu = get_cpu();
bd0362dd 1247
33cf09c9
AD		 1248 if (q_vector->cpu == cpu)
1249 goto out_no_update;
1250
a557928e 1251 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1252 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1253
a557928e 1254 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1255 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1256
1257 q_vector->cpu = cpu;
1258out_no_update:
bd0362dd
JC		 1259 put_cpu();
1260}
1261
1262static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1263{
1264 int i;
1265
1266 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1267 return;
1268
e35ec126
AD		 1269 /* always use CB2 mode, difference is masked in the CB driver */
1270 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1271
49c7ffbe 1272 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1273 adapter->q_vector[i]->cpu = -1;
1274 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1275 }
1276}
1277
1278static int __ixgbe_notify_dca(struct device *dev, void *data)
1279{
c60fbb00 1280 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1281 unsigned long event = *(unsigned long *)data;
1282
2a72c31e 1283 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1284 return 0;
1285
bd0362dd
JC		 1286 switch (event) {
1287 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1288 /* if we're already enabled, don't do it again */
1289 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1290 break;
652f093f 1291 if (dca_add_requester(dev) == 0) {
96b0e0f6 1292 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1293 ixgbe_setup_dca(adapter);
1294 break;
1295 }
1296 /* Fall Through since DCA is disabled. */
1297 case DCA_PROVIDER_REMOVE:
1298 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1299 dca_remove_requester(dev);
1300 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1301 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1302 }
1303 break;
1304 }
1305
652f093f 1306 return 0;
bd0362dd 1307}
67a74ee2 1308
bdda1a61 1309#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1310static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1311 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1312 struct sk_buff *skb)
1313{
8a0da21b 1314 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1315 skb_set_hash(skb,
1316 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1317 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1318}
1319
f800326d 1320#ifdef IXGBE_FCOE
ff886dfc
AD		 1321/**
1322 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1323 * @ring: structure containing ring specific data
ff886dfc
AD		 1324 * @rx_desc: advanced rx descriptor
1325 *
1326 * Returns : true if it is FCoE pkt
1327 */
57efd44c 1328static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1329 union ixgbe_adv_rx_desc *rx_desc)
1330{
1331 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1332
57efd44c 1333 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1334 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1335 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1336 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1337}
1338
f800326d 1339#endif /* IXGBE_FCOE */
e59bd25d
AV		 1340/**
1341 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1342 * @ring: structure containing ring specific data
1343 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1344 * @skb: skb currently being received and modified
1345 **/
8a0da21b 1346static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1347 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1348 struct sk_buff *skb)
9a799d71 1349{
8a0da21b 1350 skb_checksum_none_assert(skb);
9a799d71 1351
712744be 1352 /* Rx csum disabled */
8a0da21b 1353 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1354 return;
e59bd25d
AV		 1355
1356 /* if IP and error */
f56e0cb1
AD		 1357 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1358 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1359 ring->rx_stats.csum_err++;
9a799d71
AK		 1360 return;
1361 }
e59bd25d 1362
f56e0cb1 1363 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1364 return;
1365
f56e0cb1 1366 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1367 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1368
1369 /*
1370 * 82599 errata, UDP frames with a 0 checksum can be marked as
1371 * checksum errors.
1372 */
8a0da21b
AD		 1373 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1374 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1375 return;
1376
8a0da21b 1377 ring->rx_stats.csum_err++;
e59bd25d
AV		 1378 return;
1379 }
1380
9a799d71 1381 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1382 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1383}
1384
84ea2591 1385static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1386{
f56e0cb1 1387 rx_ring->next_to_use = val;
f800326d
AD		 1388
1389 /* update next to alloc since we have filled the ring */
1390 rx_ring->next_to_alloc = val;
e8e26350
PW		 1391 /*
1392 * Force memory writes to complete before letting h/w
1393 * know there are new descriptors to fetch. (Only
1394 * applicable for weak-ordered memory model archs,
1395 * such as IA-64).
1396 */
1397 wmb();
84227bcd 1398 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1399}
1400
f990b79b
AD		 1401static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1402 struct ixgbe_rx_buffer *bi)
1403{
1404 struct page *page = bi->page;
f800326d 1405 dma_addr_t dma = bi->dma;
f990b79b 1406
f800326d
AD		 1407 /* since we are recycling buffers we should seldom need to alloc */
1408 if (likely(dma))
f990b79b
AD		 1409 return true;
1410
f800326d
AD		 1411 /* alloc new page for storage */
1412 if (likely(!page)) {
0614002b
MG		 1413 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1414 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1415 if (unlikely(!page)) {
1416 rx_ring->rx_stats.alloc_rx_page_failed++;
1417 return false;
1418 }
f800326d 1419 bi->page = page;
f990b79b
AD		 1420 }
1421
f800326d
AD		 1422 /* map page for use */
1423 dma = dma_map_page(rx_ring->dev, page, 0,
1424 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1425
1426 /*
1427 * if mapping failed free memory back to system since
1428 * there isn't much point in holding memory we can't use
1429 */
1430 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1431 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1432 bi->page = NULL;
f990b79b 1433
f990b79b
AD		 1434 rx_ring->rx_stats.alloc_rx_page_failed++;
1435 return false;
1436 }
1437
f800326d 1438 bi->dma = dma;
afaa9459 1439 bi->page_offset = 0;
f800326d 1440
f990b79b
AD		 1441 return true;
1442}
1443
9a799d71 1444/**
f990b79b 1445 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1446 * @rx_ring: ring to place buffers on
1447 * @cleaned_count: number of buffers to replace
9a799d71 1448 **/
fc77dc3c 1449void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1450{
9a799d71 1451 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1452 struct ixgbe_rx_buffer *bi;
d5f398ed 1453 u16 i = rx_ring->next_to_use;
9a799d71 1454
f800326d
AD		 1455 /* nothing to do */
1456 if (!cleaned_count)
fc77dc3c
AD		 1457 return;
1458
e4f74028 1459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1460 bi = &rx_ring->rx_buffer_info[i];
1461 i -= rx_ring->count;
9a799d71 1462
f800326d
AD		 1463 do {
1464 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1465 break;
d5f398ed 1466
f800326d
AD		 1467 /*
1468 * Refresh the desc even if buffer_addrs didn't change
1469 * because each write-back erases this info.
1470 */
1471 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1472
f990b79b
AD		 1473 rx_desc++;
1474 bi++;
9a799d71 1475 i++;
f990b79b 1476 if (unlikely(!i)) {
e4f74028 1477 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1478 bi = rx_ring->rx_buffer_info;
1479 i -= rx_ring->count;
1480 }
1481
1482 /* clear the hdr_addr for the next_to_use descriptor */
1483 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1484
1485 cleaned_count--;
1486 } while (cleaned_count);
7c6e0a43 1487
f990b79b
AD		 1488 i += rx_ring->count;
1489
f56e0cb1 1490 if (rx_ring->next_to_use != i)
84ea2591 1491 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1492}
1493
1d2024f6
AD		 1494/**
1495 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1496 * @data: pointer to the start of the headers
1497 * @max_len: total length of section to find headers in
1498 *
1499 * This function is meant to determine the length of headers that will
1500 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1501 * motivation of doing this is to only perform one pull for IPv4 TCP
1502 * packets so that we can do basic things like calculating the gso_size
1503 * based on the average data per packet.
1504 **/
1505static unsigned int ixgbe_get_headlen(unsigned char *data,
1506 unsigned int max_len)
1507{
1508 union {
1509 unsigned char *network;
1510 /* l2 headers */
1511 struct ethhdr *eth;
1512 struct vlan_hdr *vlan;
1513 /* l3 headers */
1514 struct iphdr *ipv4;
a048b40e 1515 struct ipv6hdr *ipv6;
1d2024f6
AD		 1516 } hdr;
1517 __be16 protocol;
1518 u8 nexthdr = 0; /* default to not TCP */
1519 u8 hlen;
1520
1521 /* this should never happen, but better safe than sorry */
1522 if (max_len < ETH_HLEN)
1523 return max_len;
1524
1525 /* initialize network frame pointer */
1526 hdr.network = data;
1527
1528 /* set first protocol and move network header forward */
1529 protocol = hdr.eth->h_proto;
1530 hdr.network += ETH_HLEN;
1531
1532 /* handle any vlan tag if present */
1533 if (protocol == __constant_htons(ETH_P_8021Q)) {
1534 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1535 return max_len;
1536
1537 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1538 hdr.network += VLAN_HLEN;
1539 }
1540
1541 /* handle L3 protocols */
1542 if (protocol == __constant_htons(ETH_P_IP)) {
1543 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1544 return max_len;
1545
1546 /* access ihl as a u8 to avoid unaligned access on ia64 */
1547 hlen = (hdr.network[0] & 0x0F) << 2;
1548
1549 /* verify hlen meets minimum size requirements */
1550 if (hlen < sizeof(struct iphdr))
1551 return hdr.network - data;
1552
ed83da12 1553 /* record next protocol if header is present */
20967f42 1554 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1555 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1556 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1557 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1558 return max_len;
1559
1560 /* record next protocol */
1561 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1562 hlen = sizeof(struct ipv6hdr);
f800326d 1563#ifdef IXGBE_FCOE
1d2024f6
AD		 1564 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1565 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1566 return max_len;
ed83da12 1567 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1568#endif
1569 } else {
1570 return hdr.network - data;
1571 }
1572
ed83da12
AD		 1573 /* relocate pointer to start of L4 header */
1574 hdr.network += hlen;
1575
a048b40e 1576 /* finally sort out TCP/UDP */
1d2024f6
AD		 1577 if (nexthdr == IPPROTO_TCP) {
1578 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1579 return max_len;
1580
1581 /* access doff as a u8 to avoid unaligned access on ia64 */
1582 hlen = (hdr.network[12] & 0xF0) >> 2;
1583
1584 /* verify hlen meets minimum size requirements */
1585 if (hlen < sizeof(struct tcphdr))
1586 return hdr.network - data;
1587
1588 hdr.network += hlen;
a048b40e
AD		 1589 } else if (nexthdr == IPPROTO_UDP) {
1590 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1591 return max_len;
1592
1593 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1594 }
1595
1596 /*
1597 * If everything has gone correctly hdr.network should be the
1598 * data section of the packet and will be the end of the header.
1599 * If not then it probably represents the end of the last recognized
1600 * header.
1601 */
1602 if ((hdr.network - data) < max_len)
1603 return hdr.network - data;
1604 else
1605 return max_len;
1606}
1607
1d2024f6
AD		 1608static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1609 struct sk_buff *skb)
1610{
f800326d 1611 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1612
1613 /* set gso_size to avoid messing up TCP MSS */
1614 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1615 IXGBE_CB(skb)->append_cnt);
96be80ab 1616 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1617}
1618
1619static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1620 struct sk_buff *skb)
1621{
1622 /* if append_cnt is 0 then frame is not RSC */
1623 if (!IXGBE_CB(skb)->append_cnt)
1624 return;
1625
1626 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1627 rx_ring->rx_stats.rsc_flush++;
1628
1629 ixgbe_set_rsc_gso_size(rx_ring, skb);
1630
1631 /* gso_size is computed using append_cnt so always clear it last */
1632 IXGBE_CB(skb)->append_cnt = 0;
1633}
1634
8a0da21b
AD		 1635/**
1636 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1637 * @rx_ring: rx descriptor ring packet is being transacted on
1638 * @rx_desc: pointer to the EOP Rx descriptor
1639 * @skb: pointer to current skb being populated
f8212f97 1640 *
8a0da21b
AD		 1641 * This function checks the ring, descriptor, and packet information in
1642 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1643 * other fields within the skb.
f8212f97 1644 **/
8a0da21b
AD		 1645static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1646 union ixgbe_adv_rx_desc *rx_desc,
1647 struct sk_buff *skb)
f8212f97 1648{
43e95f11
JF		 1649 struct net_device *dev = rx_ring->netdev;
1650
8a0da21b
AD		 1651 ixgbe_update_rsc_stats(rx_ring, skb);
1652
1653 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1654
8a0da21b
AD		 1655 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1656
6cb562d6 1657 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1658
f646968f 1659 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1660 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1661 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1662 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1663 }
1664
8a0da21b 1665 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1666
43e95f11 1667 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1668}
1669
8a0da21b
AD		 1670static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1671 struct sk_buff *skb)
aa80175a 1672{
8a0da21b
AD		 1673 struct ixgbe_adapter *adapter = q_vector->adapter;
1674
b4640030 1675 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1676 netif_receive_skb(skb);
1677 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1678 napi_gro_receive(&q_vector->napi, skb);
1679 else
1680 netif_rx(skb);
aa80175a 1681}
43634e82 1682
f800326d
AD		 1683/**
1684 * ixgbe_is_non_eop - process handling of non-EOP buffers
1685 * @rx_ring: Rx ring being processed
1686 * @rx_desc: Rx descriptor for current buffer
1687 * @skb: Current socket buffer containing buffer in progress
1688 *
1689 * This function updates next to clean. If the buffer is an EOP buffer
1690 * this function exits returning false, otherwise it will place the
1691 * sk_buff in the next buffer to be chained and return true indicating
1692 * that this is in fact a non-EOP buffer.
1693 **/
1694static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1695 union ixgbe_adv_rx_desc *rx_desc,
1696 struct sk_buff *skb)
1697{
1698 u32 ntc = rx_ring->next_to_clean + 1;
1699
1700 /* fetch, update, and store next to clean */
1701 ntc = (ntc < rx_ring->count) ? ntc : 0;
1702 rx_ring->next_to_clean = ntc;
1703
1704 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1705
5a02cbd1
AD		 1706 /* update RSC append count if present */
1707 if (ring_is_rsc_enabled(rx_ring)) {
1708 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1709 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1710
1711 if (unlikely(rsc_enabled)) {
1712 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1713
1714 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1715 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1716
5a02cbd1
AD		 1717 /* update ntc based on RSC value */
1718 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1719 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1720 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1721 }
f800326d
AD		 1722 }
1723
5a02cbd1
AD		 1724 /* if we are the last buffer then there is nothing else to do */
1725 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1726 return false;
1727
f800326d
AD		 1728 /* place skb in next buffer to be received */
1729 rx_ring->rx_buffer_info[ntc].skb = skb;
1730 rx_ring->rx_stats.non_eop_descs++;
1731
1732 return true;
1733}
1734
19861ce2
AD		 1735/**
1736 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1737 * @rx_ring: rx descriptor ring packet is being transacted on
1738 * @skb: pointer to current skb being adjusted
1739 *
1740 * This function is an ixgbe specific version of __pskb_pull_tail. The
1741 * main difference between this version and the original function is that
1742 * this function can make several assumptions about the state of things
1743 * that allow for significant optimizations versus the standard function.
1744 * As a result we can do things like drop a frag and maintain an accurate
1745 * truesize for the skb.
1746 */
1747static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1748 struct sk_buff *skb)
1749{
1750 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1751 unsigned char *va;
1752 unsigned int pull_len;
1753
1754 /*
1755 * it is valid to use page_address instead of kmap since we are
1756 * working with pages allocated out of the lomem pool per
1757 * alloc_page(GFP_ATOMIC)
1758 */
1759 va = skb_frag_address(frag);
1760
1761 /*
1762 * we need the header to contain the greater of either ETH_HLEN or
1763 * 60 bytes if the skb->len is less than 60 for skb_pad.
1764 */
cf3fe7ac 1765 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1766
1767 /* align pull length to size of long to optimize memcpy performance */
1768 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1769
1770 /* update all of the pointers */
1771 skb_frag_size_sub(frag, pull_len);
1772 frag->page_offset += pull_len;
1773 skb->data_len -= pull_len;
1774 skb->tail += pull_len;
19861ce2
AD		 1775}
1776
42073d91
AD		 1777/**
1778 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1779 * @rx_ring: rx descriptor ring packet is being transacted on
1780 * @skb: pointer to current skb being updated
1781 *
1782 * This function provides a basic DMA sync up for the first fragment of an
1783 * skb. The reason for doing this is that the first fragment cannot be
1784 * unmapped until we have reached the end of packet descriptor for a buffer
1785 * chain.
1786 */
1787static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1788 struct sk_buff *skb)
1789{
1790 /* if the page was released unmap it, else just sync our portion */
1791 if (unlikely(IXGBE_CB(skb)->page_released)) {
1792 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1793 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1794 IXGBE_CB(skb)->page_released = false;
1795 } else {
1796 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1797
1798 dma_sync_single_range_for_cpu(rx_ring->dev,
1799 IXGBE_CB(skb)->dma,
1800 frag->page_offset,
1801 ixgbe_rx_bufsz(rx_ring),
1802 DMA_FROM_DEVICE);
1803 }
1804 IXGBE_CB(skb)->dma = 0;
1805}
1806
f800326d
AD		 1807/**
1808 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1809 * @rx_ring: rx descriptor ring packet is being transacted on
1810 * @rx_desc: pointer to the EOP Rx descriptor
1811 * @skb: pointer to current skb being fixed
1812 *
1813 * Check for corrupted packet headers caused by senders on the local L2
1814 * embedded NIC switch not setting up their Tx Descriptors right. These
1815 * should be very rare.
1816 *
1817 * Also address the case where we are pulling data in on pages only
1818 * and as such no data is present in the skb header.
1819 *
1820 * In addition if skb is not at least 60 bytes we need to pad it so that
1821 * it is large enough to qualify as a valid Ethernet frame.
1822 *
1823 * Returns true if an error was encountered and skb was freed.
1824 **/
1825static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1826 union ixgbe_adv_rx_desc *rx_desc,
1827 struct sk_buff *skb)
1828{
f800326d 1829 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1830
1831 /* verify that the packet does not have any known errors */
1832 if (unlikely(ixgbe_test_staterr(rx_desc,
1833 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1834 !(netdev->features & NETIF_F_RXALL))) {
1835 dev_kfree_skb_any(skb);
1836 return true;
1837 }
1838
19861ce2 1839 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1840 if (skb_is_nonlinear(skb))
1841 ixgbe_pull_tail(rx_ring, skb);
f800326d 1842
57efd44c
AD		 1843#ifdef IXGBE_FCOE
1844 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1845 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1846 return false;
1847
1848#endif
f800326d
AD		 1849 /* if skb_pad returns an error the skb was freed */
1850 if (unlikely(skb->len < 60)) {
1851 int pad_len = 60 - skb->len;
1852
1853 if (skb_pad(skb, pad_len))
1854 return true;
1855 __skb_put(skb, pad_len);
1856 }
1857
1858 return false;
1859}
1860
f800326d
AD		 1861/**
1862 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1863 * @rx_ring: rx descriptor ring to store buffers on
1864 * @old_buff: donor buffer to have page reused
1865 *
0549ae20 1866 * Synchronizes page for reuse by the adapter
f800326d
AD		 1867 **/
1868static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1869 struct ixgbe_rx_buffer *old_buff)
1870{
1871 struct ixgbe_rx_buffer *new_buff;
1872 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1873
1874 new_buff = &rx_ring->rx_buffer_info[nta];
1875
1876 /* update, and store next to alloc */
1877 nta++;
1878 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1879
1880 /* transfer page from old buffer to new buffer */
1881 new_buff->page = old_buff->page;
1882 new_buff->dma = old_buff->dma;
0549ae20 1883 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1884
1885 /* sync the buffer for use by the device */
1886 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1887 new_buff->page_offset,
1888 ixgbe_rx_bufsz(rx_ring),
f800326d 1889 DMA_FROM_DEVICE);
f800326d
AD		 1890}
1891
1892/**
1893 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1894 * @rx_ring: rx descriptor ring to transact packets on
1895 * @rx_buffer: buffer containing page to add
1896 * @rx_desc: descriptor containing length of buffer written by hardware
1897 * @skb: sk_buff to place the data into
1898 *
0549ae20
AD		 1899 * This function will add the data contained in rx_buffer->page to the skb.
1900 * This is done either through a direct copy if the data in the buffer is
1901 * less than the skb header size, otherwise it will just attach the page as
1902 * a frag to the skb.
1903 *
1904 * The function will then update the page offset if necessary and return
1905 * true if the buffer can be reused by the adapter.
f800326d 1906 **/
0549ae20 1907static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1908 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1909 union ixgbe_adv_rx_desc *rx_desc,
1910 struct sk_buff *skb)
f800326d 1911{
0549ae20
AD		 1912 struct page *page = rx_buffer->page;
1913 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1914#if (PAGE_SIZE < 8192)
0549ae20 1915 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1916#else
1917 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1918 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1919 ixgbe_rx_bufsz(rx_ring);
1920#endif
0549ae20 1921
cf3fe7ac
AD		 1922 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1923 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1924
1925 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1926
1927 /* we can reuse buffer as-is, just make sure it is local */
1928 if (likely(page_to_nid(page) == numa_node_id()))
1929 return true;
1930
1931 /* this page cannot be reused so discard it */
1932 put_page(page);
1933 return false;
1934 }
1935
0549ae20
AD		 1936 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1937 rx_buffer->page_offset, size, truesize);
1938
09816fbe
AD		 1939 /* avoid re-using remote pages */
1940 if (unlikely(page_to_nid(page) != numa_node_id()))
1941 return false;
1942
1943#if (PAGE_SIZE < 8192)
1944 /* if we are only owner of page we can reuse it */
1945 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1946 return false;
1947
1948 /* flip page offset to other buffer */
1949 rx_buffer->page_offset ^= truesize;
1950
09816fbe
AD		 1951 /*
1952 * since we are the only owner of the page and we need to
1953 * increment it, just set the value to 2 in order to avoid
1954 * an unecessary locked operation
1955 */
1956 atomic_set(&page->_count, 2);
1957#else
1958 /* move offset up to the next cache line */
1959 rx_buffer->page_offset += truesize;
1960
1961 if (rx_buffer->page_offset > last_offset)
1962 return false;
1963
0549ae20
AD		 1964 /* bump ref count on page before it is given to the stack */
1965 get_page(page);
09816fbe 1966#endif
0549ae20
AD		 1967
1968 return true;
f800326d
AD		 1969}
1970
18806c9e
AD		 1971static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1972 union ixgbe_adv_rx_desc *rx_desc)
1973{
1974 struct ixgbe_rx_buffer *rx_buffer;
1975 struct sk_buff *skb;
1976 struct page *page;
1977
1978 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1979 page = rx_buffer->page;
1980 prefetchw(page);
1981
1982 skb = rx_buffer->skb;
1983
1984 if (likely(!skb)) {
1985 void *page_addr = page_address(page) +
1986 rx_buffer->page_offset;
1987
1988 /* prefetch first cache line of first page */
1989 prefetch(page_addr);
1990#if L1_CACHE_BYTES < 128
1991 prefetch(page_addr + L1_CACHE_BYTES);
1992#endif
1993
1994 /* allocate a skb to store the frags */
1995 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1996 IXGBE_RX_HDR_SIZE);
1997 if (unlikely(!skb)) {
1998 rx_ring->rx_stats.alloc_rx_buff_failed++;
1999 return NULL;
2000 }
2001
2002 /*
2003 * we will be copying header into skb->data in
2004 * pskb_may_pull so it is in our interest to prefetch
2005 * it now to avoid a possible cache miss
2006 */
2007 prefetchw(skb->data);
2008
2009 /*
2010 * Delay unmapping of the first packet. It carries the
2011 * header information, HW may still access the header
2012 * after the writeback. Only unmap it when EOP is
2013 * reached
2014 */
2015 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2016 goto dma_sync;
2017
2018 IXGBE_CB(skb)->dma = rx_buffer->dma;
2019 } else {
2020 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2021 ixgbe_dma_sync_frag(rx_ring, skb);
2022
2023dma_sync:
2024 /* we are reusing so sync this buffer for CPU use */
2025 dma_sync_single_range_for_cpu(rx_ring->dev,
2026 rx_buffer->dma,
2027 rx_buffer->page_offset,
2028 ixgbe_rx_bufsz(rx_ring),
2029 DMA_FROM_DEVICE);
2030 }
2031
2032 /* pull page into skb */
2033 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2034 /* hand second half of page back to the ring */
2035 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2036 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2037 /* the page has been released from the ring */
2038 IXGBE_CB(skb)->page_released = true;
2039 } else {
2040 /* we are not reusing the buffer so unmap it */
2041 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2042 ixgbe_rx_pg_size(rx_ring),
2043 DMA_FROM_DEVICE);
2044 }
2045
2046 /* clear contents of buffer_info */
2047 rx_buffer->skb = NULL;
2048 rx_buffer->dma = 0;
2049 rx_buffer->page = NULL;
2050
2051 return skb;
f800326d
AD		 2052}
2053
2054/**
2055 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2056 * @q_vector: structure containing interrupt and ring information
2057 * @rx_ring: rx descriptor ring to transact packets on
2058 * @budget: Total limit on number of packets to process
2059 *
2060 * This function provides a "bounce buffer" approach to Rx interrupt
2061 * processing. The advantage to this is that on systems that have
2062 * expensive overhead for IOMMU access this provides a means of avoiding
2063 * it by maintaining the mapping of the page to the syste.
2064 *
5a85e737 2065 * Returns amount of work completed
f800326d 2066 **/
5a85e737 2067static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2068 struct ixgbe_ring *rx_ring,
f4de00ed 2069 const int budget)
9a799d71 2070{
d2f4fbe2 2071 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2072#ifdef IXGBE_FCOE
f800326d 2073 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2074 int ddp_bytes;
2075 unsigned int mss = 0;
3d8fd385 2076#endif /* IXGBE_FCOE */
f800326d 2077 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2078
f800326d 2079 do {
f800326d
AD		 2080 union ixgbe_adv_rx_desc *rx_desc;
2081 struct sk_buff *skb;
f800326d
AD		 2082
2083 /* return some buffers to hardware, one at a time is too slow */
2084 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2085 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2086 cleaned_count = 0;
2087 }
2088
18806c9e 2089 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2090
2091 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2092 break;
9a799d71 2093
f800326d
AD		 2094 /*
2095 * This memory barrier is needed to keep us from reading
2096 * any other fields out of the rx_desc until we know the
2097 * RXD_STAT_DD bit is set
2098 */
2099 rmb();
9a799d71 2100
18806c9e
AD		 2101 /* retrieve a buffer from the ring */
2102 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2103
18806c9e
AD		 2104 /* exit if we failed to retrieve a buffer */
2105 if (!skb)
2106 break;
9a799d71 2107
9a799d71 2108 cleaned_count++;
f8212f97 2109
f800326d
AD		 2110 /* place incomplete frames back on ring for completion */
2111 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2112 continue;
c267fc16 2113
f800326d
AD		 2114 /* verify the packet layout is correct */
2115 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2116 continue;
9a799d71 2117
d2f4fbe2
AV		 2118 /* probably a little skewed due to removing CRC */
2119 total_rx_bytes += skb->len;
d2f4fbe2 2120
8a0da21b
AD		 2121 /* populate checksum, timestamp, VLAN, and protocol */
2122 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2123
332d4a7d
YZ		 2124#ifdef IXGBE_FCOE
2125 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2126 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2127 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2128 /* include DDPed FCoE data */
2129 if (ddp_bytes > 0) {
2130 if (!mss) {
2131 mss = rx_ring->netdev->mtu -
2132 sizeof(struct fcoe_hdr) -
2133 sizeof(struct fc_frame_header) -
2134 sizeof(struct fcoe_crc_eof);
2135 if (mss > 512)
2136 mss &= ~511;
2137 }
2138 total_rx_bytes += ddp_bytes;
2139 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2140 mss);
2141 }
63d635b2
AD		 2142 if (!ddp_bytes) {
2143 dev_kfree_skb_any(skb);
f800326d 2144 continue;
63d635b2 2145 }
3d8fd385 2146 }
f800326d 2147
332d4a7d 2148#endif /* IXGBE_FCOE */
8b80cda5 2149 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2150 ixgbe_rx_skb(q_vector, skb);
9a799d71 2151
f800326d 2152 /* update budget accounting */
f4de00ed
AD		 2153 total_rx_packets++;
2154 } while (likely(total_rx_packets < budget));
9a799d71 2155
c267fc16
AD		 2156 u64_stats_update_begin(&rx_ring->syncp);
2157 rx_ring->stats.packets += total_rx_packets;
2158 rx_ring->stats.bytes += total_rx_bytes;
2159 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2160 q_vector->rx.total_packets += total_rx_packets;
2161 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2162
f800326d
AD		 2163 if (cleaned_count)
2164 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2165
5a85e737 2166 return total_rx_packets;
9a799d71
AK		 2167}
2168
e0d1095a 2169#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2170/* must be called with local_bh_disable()d */
2171static int ixgbe_low_latency_recv(struct napi_struct *napi)
2172{
2173 struct ixgbe_q_vector *q_vector =
2174 container_of(napi, struct ixgbe_q_vector, napi);
2175 struct ixgbe_adapter *adapter = q_vector->adapter;
2176 struct ixgbe_ring *ring;
2177 int found = 0;
2178
2179 if (test_bit(__IXGBE_DOWN, &adapter->state))
2180 return LL_FLUSH_FAILED;
2181
2182 if (!ixgbe_qv_lock_poll(q_vector))
2183 return LL_FLUSH_BUSY;
2184
2185 ixgbe_for_each_ring(ring, q_vector->rx) {
2186 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2187#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2188 if (found)
2189 ring->stats.cleaned += found;
2190 else
2191 ring->stats.misses++;
2192#endif
5a85e737
ET		 2193 if (found)
2194 break;
2195 }
2196
2197 ixgbe_qv_unlock_poll(q_vector);
2198
2199 return found;
2200}
e0d1095a 2201#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2202
9a799d71
AK		 2203/**
2204 * ixgbe_configure_msix - Configure MSI-X hardware
2205 * @adapter: board private structure
2206 *
2207 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2208 * interrupts.
2209 **/
2210static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2211{
021230d4 2212 struct ixgbe_q_vector *q_vector;
49c7ffbe 2213 int v_idx;
021230d4 2214 u32 mask;
9a799d71 2215
8e34d1aa
AD		 2216 /* Populate MSIX to EITR Select */
2217 if (adapter->num_vfs > 32) {
2218 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2219 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2220 }
2221
4df10466
JB		 2222 /*
2223 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2224 * corresponding register.
2225 */
49c7ffbe 2226 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2227 struct ixgbe_ring *ring;
7a921c93 2228 q_vector = adapter->q_vector[v_idx];
021230d4 2229
a557928e 2230 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2231 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2232
a557928e 2233 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2234 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2235
fe49f04a 2236 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2237 }
2238
bd508178
AD		 2239 switch (adapter->hw.mac.type) {
2240 case ixgbe_mac_82598EB:
e8e26350 2241 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2242 v_idx);
bd508178
AD		 2243 break;
2244 case ixgbe_mac_82599EB:
b93a2226 2245 case ixgbe_mac_X540:
e8e26350 2246 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2247 break;
bd508178
AD		 2248 default:
2249 break;
2250 }
021230d4
AV		 2251 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2252
41fb9248 2253 /* set up to autoclear timer, and the vectors */
021230d4 2254 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2255 mask &= ~(IXGBE_EIMS_OTHER |
2256 IXGBE_EIMS_MAILBOX |
2257 IXGBE_EIMS_LSC);
2258
021230d4 2259 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2260}
2261
f494e8fa
AV		 2262enum latency_range {
2263 lowest_latency = 0,
2264 low_latency = 1,
2265 bulk_latency = 2,
2266 latency_invalid = 255
2267};
2268
2269/**
2270 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2271 * @q_vector: structure containing interrupt and ring information
2272 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2273 *
2274 * Stores a new ITR value based on packets and byte
2275 * counts during the last interrupt. The advantage of per interrupt
2276 * computation is faster updates and more accurate ITR for the current
2277 * traffic pattern. Constants in this function were computed
2278 * based on theoretical maximum wire speed and thresholds were set based
2279 * on testing data as well as attempting to minimize response time
2280 * while increasing bulk throughput.
2281 * this functionality is controlled by the InterruptThrottleRate module
2282 * parameter (see ixgbe_param.c)
2283 **/
bd198058
AD		 2284static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2285 struct ixgbe_ring_container *ring_container)
f494e8fa 2286{
bd198058
AD		 2287 int bytes = ring_container->total_bytes;
2288 int packets = ring_container->total_packets;
2289 u32 timepassed_us;
621bd70e 2290 u64 bytes_perint;
bd198058 2291 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2292
2293 if (packets == 0)
bd198058 2294 return;
f494e8fa
AV		 2295
2296 /* simple throttlerate management
621bd70e
AD		 2297 * 0-10MB/s lowest (100000 ints/s)
2298 * 10-20MB/s low (20000 ints/s)
2299 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2300 */
2301 /* what was last interrupt timeslice? */
d5bf4f67 2302 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2303 if (timepassed_us == 0)
2304 return;
2305
f494e8fa
AV		 2306 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2307
2308 switch (itr_setting) {
2309 case lowest_latency:
621bd70e 2310 if (bytes_perint > 10)
bd198058 2311 itr_setting = low_latency;
f494e8fa
AV		 2312 break;
2313 case low_latency:
621bd70e 2314 if (bytes_perint > 20)
bd198058 2315 itr_setting = bulk_latency;
621bd70e 2316 else if (bytes_perint <= 10)
bd198058 2317 itr_setting = lowest_latency;
f494e8fa
AV		 2318 break;
2319 case bulk_latency:
621bd70e 2320 if (bytes_perint <= 20)
bd198058 2321 itr_setting = low_latency;
f494e8fa
AV		 2322 break;
2323 }
2324
bd198058
AD		 2325 /* clear work counters since we have the values we need */
2326 ring_container->total_bytes = 0;
2327 ring_container->total_packets = 0;
2328
2329 /* write updated itr to ring container */
2330 ring_container->itr = itr_setting;
f494e8fa
AV		 2331}
2332
509ee935
JB		 2333/**
2334 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2335 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2336 *
2337 * This function is made to be called by ethtool and by the driver
2338 * when it needs to update EITR registers at runtime. Hardware
2339 * specific quirks/differences are taken care of here.
2340 */
fe49f04a 2341void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2342{
fe49f04a 2343 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2344 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2345 int v_idx = q_vector->v_idx;
5d967eb7 2346 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2347
bd508178
AD		 2348 switch (adapter->hw.mac.type) {
2349 case ixgbe_mac_82598EB:
509ee935
JB		 2350 /* must write high and low 16 bits to reset counter */
2351 itr_reg |= (itr_reg << 16);
bd508178
AD		 2352 break;
2353 case ixgbe_mac_82599EB:
b93a2226 2354 case ixgbe_mac_X540:
509ee935
JB		 2355 /*
2356 * set the WDIS bit to not clear the timer bits and cause an
2357 * immediate assertion of the interrupt
2358 */
2359 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2360 break;
2361 default:
2362 break;
509ee935
JB		 2363 }
2364 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2365}
2366
bd198058 2367static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2368{
d5bf4f67 2369 u32 new_itr = q_vector->itr;
bd198058 2370 u8 current_itr;
f494e8fa 2371
bd198058
AD		 2372 ixgbe_update_itr(q_vector, &q_vector->tx);
2373 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2374
08c8833b 2375 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2376
2377 switch (current_itr) {
2378 /* counts and packets in update_itr are dependent on these numbers */
2379 case lowest_latency:
d5bf4f67 2380 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2381 break;
2382 case low_latency:
d5bf4f67 2383 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2384 break;
2385 case bulk_latency:
d5bf4f67 2386 new_itr = IXGBE_8K_ITR;
f494e8fa 2387 break;
bd198058
AD		 2388 default:
2389 break;
f494e8fa
AV		 2390 }
2391
d5bf4f67 2392 if (new_itr != q_vector->itr) {
fe49f04a 2393 /* do an exponential smoothing */
d5bf4f67
ET		 2394 new_itr = (10 * new_itr * q_vector->itr) /
2395 ((9 * new_itr) + q_vector->itr);
509ee935 2396
bd198058 2397 /* save the algorithm value here */
5d967eb7 2398 q_vector->itr = new_itr;
fe49f04a
AD		 2399
2400 ixgbe_write_eitr(q_vector);
f494e8fa 2401 }
f494e8fa
AV		 2402}
2403
119fc60a 2404/**
de88eeeb 2405 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2406 * @adapter: pointer to adapter
119fc60a 2407 **/
f0f9778d 2408static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2409{
119fc60a
MC		 2410 struct ixgbe_hw *hw = &adapter->hw;
2411 u32 eicr = adapter->interrupt_event;
2412
f0f9778d 2413 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2414 return;
2415
f0f9778d
AD		 2416 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2417 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2418 return;
2419
2420 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2421
7ca647bd 2422 switch (hw->device_id) {
f0f9778d
AD		 2423 case IXGBE_DEV_ID_82599_T3_LOM:
2424 /*
2425 * Since the warning interrupt is for both ports
2426 * we don't have to check if:
2427 * - This interrupt wasn't for our port.
2428 * - We may have missed the interrupt so always have to
2429 * check if we got a LSC
2430 */
2431 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2432 !(eicr & IXGBE_EICR_LSC))
2433 return;
2434
2435 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2436 u32 speed;
f0f9778d 2437 bool link_up = false;
7ca647bd 2438
3d292265 2439 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2440
f0f9778d
AD		 2441 if (link_up)
2442 return;
2443 }
2444
2445 /* Check if this is not due to overtemp */
2446 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2447 return;
2448
2449 break;
7ca647bd
JP		 2450 default:
2451 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2452 return;
7ca647bd 2453 break;
119fc60a 2454 }
7ca647bd
JP		 2455 e_crit(drv,
2456 "Network adapter has been stopped because it has over heated. "
2457 "Restart the computer. If the problem persists, "
2458 "power off the system and replace the adapter\n");
f0f9778d
AD		 2459
2460 adapter->interrupt_event = 0;
119fc60a
MC		 2461}
2462
0befdb3e
JB		 2463static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2464{
2465 struct ixgbe_hw *hw = &adapter->hw;
2466
2467 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2468 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2469 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2470 /* write to clear the interrupt */
2471 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2472 }
2473}
cf8280ee 2474
4f51bf70
JK		 2475static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2476{
2477 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2478 return;
2479
2480 switch (adapter->hw.mac.type) {
2481 case ixgbe_mac_82599EB:
2482 /*
2483 * Need to check link state so complete overtemp check
2484 * on service task
2485 */
2486 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2487 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2488 adapter->interrupt_event = eicr;
2489 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2490 ixgbe_service_event_schedule(adapter);
2491 return;
2492 }
2493 return;
2494 case ixgbe_mac_X540:
2495 if (!(eicr & IXGBE_EICR_TS))
2496 return;
2497 break;
2498 default:
2499 return;
2500 }
2501
2502 e_crit(drv,
2503 "Network adapter has been stopped because it has over heated. "
2504 "Restart the computer. If the problem persists, "
2505 "power off the system and replace the adapter\n");
2506}
2507
e8e26350
PW		 2508static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2509{
2510 struct ixgbe_hw *hw = &adapter->hw;
2511
73c4b7cd
AD		 2512 if (eicr & IXGBE_EICR_GPI_SDP2) {
2513 /* Clear the interrupt */
2514 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2515 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2516 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2517 ixgbe_service_event_schedule(adapter);
2518 }
73c4b7cd
AD		 2519 }
2520
e8e26350
PW		 2521 if (eicr & IXGBE_EICR_GPI_SDP1) {
2522 /* Clear the interrupt */
2523 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2524 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2525 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2526 ixgbe_service_event_schedule(adapter);
2527 }
e8e26350
PW		 2528 }
2529}
2530
cf8280ee
JB		 2531static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2532{
2533 struct ixgbe_hw *hw = &adapter->hw;
2534
2535 adapter->lsc_int++;
2536 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2537 adapter->link_check_timeout = jiffies;
2538 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2539 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2540 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2541 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2542 }
2543}
2544
fe49f04a
AD		 2545static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2546 u64 qmask)
2547{
2548 u32 mask;
bd508178 2549 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2550
bd508178
AD		 2551 switch (hw->mac.type) {
2552 case ixgbe_mac_82598EB:
fe49f04a 2553 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2554 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2555 break;
2556 case ixgbe_mac_82599EB:
b93a2226 2557 case ixgbe_mac_X540:
fe49f04a 2558 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2559 if (mask)
2560 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2561 mask = (qmask >> 32);
bd508178
AD		 2562 if (mask)
2563 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2564 break;
2565 default:
2566 break;
fe49f04a
AD		 2567 }
2568 /* skip the flush */
2569}
2570
2571static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2572 u64 qmask)
fe49f04a
AD		 2573{
2574 u32 mask;
bd508178 2575 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2576
bd508178
AD		 2577 switch (hw->mac.type) {
2578 case ixgbe_mac_82598EB:
fe49f04a 2579 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2580 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2581 break;
2582 case ixgbe_mac_82599EB:
b93a2226 2583 case ixgbe_mac_X540:
fe49f04a 2584 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2585 if (mask)
2586 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2587 mask = (qmask >> 32);
bd508178
AD		 2588 if (mask)
2589 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2590 break;
2591 default:
2592 break;
fe49f04a
AD		 2593 }
2594 /* skip the flush */
2595}
2596
021230d4 2597/**
2c4af694
AD		 2598 * ixgbe_irq_enable - Enable default interrupt generation settings
2599 * @adapter: board private structure
021230d4 2600 **/
2c4af694
AD		 2601static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2602 bool flush)
9a799d71 2603{
2c4af694 2604 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2605
2c4af694
AD		 2606 /* don't reenable LSC while waiting for link */
2607 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2608 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2609
2c4af694 2610 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2611 switch (adapter->hw.mac.type) {
2612 case ixgbe_mac_82599EB:
2613 mask |= IXGBE_EIMS_GPI_SDP0;
2614 break;
2615 case ixgbe_mac_X540:
2616 mask |= IXGBE_EIMS_TS;
2617 break;
2618 default:
2619 break;
2620 }
2c4af694
AD		 2621 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2622 mask |= IXGBE_EIMS_GPI_SDP1;
2623 switch (adapter->hw.mac.type) {
2624 case ixgbe_mac_82599EB:
2c4af694
AD		 2625 mask |= IXGBE_EIMS_GPI_SDP1;
2626 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2627 case ixgbe_mac_X540:
2628 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2629 mask |= IXGBE_EIMS_MAILBOX;
2630 break;
2631 default:
2632 break;
9a799d71 2633 }
db0677fa 2634
db0677fa
JK		 2635 if (adapter->hw.mac.type == ixgbe_mac_X540)
2636 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2637
2c4af694
AD		 2638 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2639 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2640 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2641
2c4af694
AD		 2642 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2643 if (queues)
2644 ixgbe_irq_enable_queues(adapter, ~0);
2645 if (flush)
2646 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2647}
2648
2c4af694 2649static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2650{
a65151ba 2651 struct ixgbe_adapter *adapter = data;
9a799d71 2652 struct ixgbe_hw *hw = &adapter->hw;
54037505 2653 u32 eicr;
91281fd3 2654
54037505
DS		 2655 /*
2656 * Workaround for Silicon errata. Use clear-by-write instead
2657 * of clear-by-read. Reading with EICS will return the
2658 * interrupt causes without clearing, which later be done
2659 * with the write to EICR.
2660 */
2661 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2662
2663 /* The lower 16bits of the EICR register are for the queue interrupts
2664 * which should be masked here in order to not accidently clear them if
2665 * the bits are high when ixgbe_msix_other is called. There is a race
2666 * condition otherwise which results in possible performance loss
2667 * especially if the ixgbe_msix_other interrupt is triggering
2668 * consistently (as it would when PPS is turned on for the X540 device)
2669 */
2670 eicr &= 0xFFFF0000;
2671
54037505 2672 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2673
cf8280ee
JB		 2674 if (eicr & IXGBE_EICR_LSC)
2675 ixgbe_check_lsc(adapter);
f0848276 2676
1cdd1ec8
GR		 2677 if (eicr & IXGBE_EICR_MAILBOX)
2678 ixgbe_msg_task(adapter);
efe3d3c8 2679
bd508178
AD		 2680 switch (hw->mac.type) {
2681 case ixgbe_mac_82599EB:
b93a2226 2682 case ixgbe_mac_X540:
d773ce2d
DS		 2683 if (eicr & IXGBE_EICR_ECC) {
2684 e_info(link, "Received ECC Err, initiating reset\n");
2685 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2686 ixgbe_service_event_schedule(adapter);
2687 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2688 }
c4cf55e5
PWJ		 2689 /* Handle Flow Director Full threshold interrupt */
2690 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2691 int reinit_count = 0;
c4cf55e5 2692 int i;
c4cf55e5 2693 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2694 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2695 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2696 &ring->state))
2697 reinit_count++;
2698 }
2699 if (reinit_count) {
2700 /* no more flow director interrupts until after init */
2701 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2702 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2703 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2704 }
2705 }
f0f9778d 2706 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2707 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2708 break;
2709 default:
2710 break;
c4cf55e5 2711 }
f0848276 2712
bd508178 2713 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2714
db0677fa
JK		 2715 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2716 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2717
7086400d 2718 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2719 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2720 ixgbe_irq_enable(adapter, false, false);
f0848276 2721
9a799d71 2722 return IRQ_HANDLED;
f0848276 2723}
91281fd3 2724
4ff7fb12 2725static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2726{
021230d4 2727 struct ixgbe_q_vector *q_vector = data;
91281fd3 2728
9b471446 2729 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2730
4ff7fb12
AD		 2731 if (q_vector->rx.ring || q_vector->tx.ring)
2732 napi_schedule(&q_vector->napi);
91281fd3 2733
9a799d71 2734 return IRQ_HANDLED;
91281fd3
AD		 2735}
2736
eb01b975
AD		 2737/**
2738 * ixgbe_poll - NAPI Rx polling callback
2739 * @napi: structure for representing this polling device
2740 * @budget: how many packets driver is allowed to clean
2741 *
2742 * This function is used for legacy and MSI, NAPI mode
2743 **/
8af3c33f 2744int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2745{
2746 struct ixgbe_q_vector *q_vector =
2747 container_of(napi, struct ixgbe_q_vector, napi);
2748 struct ixgbe_adapter *adapter = q_vector->adapter;
2749 struct ixgbe_ring *ring;
2750 int per_ring_budget;
2751 bool clean_complete = true;
2752
2753#ifdef CONFIG_IXGBE_DCA
2754 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2755 ixgbe_update_dca(q_vector);
2756#endif
2757
2758 ixgbe_for_each_ring(ring, q_vector->tx)
2759 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2760
5a85e737
ET		 2761 if (!ixgbe_qv_lock_napi(q_vector))
2762 return budget;
2763
eb01b975
AD		 2764 /* attempt to distribute budget to each queue fairly, but don't allow
2765 * the budget to go below 1 because we'll exit polling */
2766 if (q_vector->rx.count > 1)
2767 per_ring_budget = max(budget/q_vector->rx.count, 1);
2768 else
2769 per_ring_budget = budget;
2770
2771 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2772 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2773 per_ring_budget) < per_ring_budget);
eb01b975 2774
5a85e737 2775 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2776 /* If all work not completed, return budget and keep polling */
2777 if (!clean_complete)
2778 return budget;
2779
2780 /* all work done, exit the polling mode */
2781 napi_complete(napi);
2782 if (adapter->rx_itr_setting & 1)
2783 ixgbe_set_itr(q_vector);
2784 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2785 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2786
2787 return 0;
2788}
2789
021230d4
AV		 2790/**
2791 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2792 * @adapter: board private structure
2793 *
2794 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2795 * interrupts from the kernel.
2796 **/
2797static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2798{
2799 struct net_device *netdev = adapter->netdev;
207867f5 2800 int vector, err;
e8e9f696 2801 int ri = 0, ti = 0;
021230d4 2802
49c7ffbe 2803 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2804 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2805 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2806
4ff7fb12 2807 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2808 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2809 "%s-%s-%d", netdev->name, "TxRx", ri++);
2810 ti++;
2811 } else if (q_vector->rx.ring) {
9fe93afd 2812 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2813 "%s-%s-%d", netdev->name, "rx", ri++);
2814 } else if (q_vector->tx.ring) {
9fe93afd 2815 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2816 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2817 } else {
2818 /* skip this unused q_vector */
2819 continue;
32aa77a4 2820 }
207867f5
AD		 2821 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2822 q_vector->name, q_vector);
9a799d71 2823 if (err) {
396e799c 2824 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2825 "Error: %d\n", err);
021230d4 2826 goto free_queue_irqs;
9a799d71 2827 }
207867f5
AD		 2828 /* If Flow Director is enabled, set interrupt affinity */
2829 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2830 /* assign the mask for this irq */
2831 irq_set_affinity_hint(entry->vector,
de88eeeb 2832 &q_vector->affinity_mask);
207867f5 2833 }
9a799d71
AK		 2834 }
2835
021230d4 2836 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2837 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2838 if (err) {
de88eeeb 2839 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2840 goto free_queue_irqs;
9a799d71
AK		 2841 }
2842
9a799d71
AK		 2843 return 0;
2844
021230d4 2845free_queue_irqs:
207867f5
AD		 2846 while (vector) {
2847 vector--;
2848 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2849 NULL);
2850 free_irq(adapter->msix_entries[vector].vector,
2851 adapter->q_vector[vector]);
2852 }
021230d4
AV		 2853 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2854 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2855 kfree(adapter->msix_entries);
2856 adapter->msix_entries = NULL;
9a799d71
AK		 2857 return err;
2858}
2859
2860/**
021230d4 2861 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2862 * @irq: interrupt number
2863 * @data: pointer to a network interface device structure
9a799d71
AK		 2864 **/
2865static irqreturn_t ixgbe_intr(int irq, void *data)
2866{
a65151ba 2867 struct ixgbe_adapter *adapter = data;
9a799d71 2868 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2869 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2870 u32 eicr;
2871
54037505 2872 /*
24ddd967 2873 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2874 * before the read of EICR.
2875 */
2876 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2877
021230d4 2878 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2879 * therefore no explicit interrupt disable is necessary */
021230d4 2880 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2881 if (!eicr) {
6af3b9eb
ET		 2882 /*
2883 * shared interrupt alert!
f47cf66e 2884 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2885 * have disabled interrupts due to EIAM
2886 * finish the workaround of silicon errata on 82598. Unmask
2887 * the interrupt that we masked before the EICR read.
2888 */
2889 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2890 ixgbe_irq_enable(adapter, true, true);
9a799d71 2891 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2892 }
9a799d71 2893
cf8280ee
JB		 2894 if (eicr & IXGBE_EICR_LSC)
2895 ixgbe_check_lsc(adapter);
021230d4 2896
bd508178
AD		 2897 switch (hw->mac.type) {
2898 case ixgbe_mac_82599EB:
e8e26350 2899 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2900 /* Fall through */
2901 case ixgbe_mac_X540:
d773ce2d
DS		 2902 if (eicr & IXGBE_EICR_ECC) {
2903 e_info(link, "Received ECC Err, initiating reset\n");
2904 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2905 ixgbe_service_event_schedule(adapter);
2906 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2907 }
4f51bf70 2908 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2909 break;
2910 default:
2911 break;
2912 }
e8e26350 2913
0befdb3e 2914 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2915 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2916 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2917
b9f6ed2b
AD		 2918 /* would disable interrupts here but EIAM disabled it */
2919 napi_schedule(&q_vector->napi);
9a799d71 2920
6af3b9eb
ET		 2921 /*
2922 * re-enable link(maybe) and non-queue interrupts, no flush.
2923 * ixgbe_poll will re-enable the queue interrupts
2924 */
6af3b9eb
ET		 2925 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2926 ixgbe_irq_enable(adapter, false, false);
2927
9a799d71
AK		 2928 return IRQ_HANDLED;
2929}
2930
2931/**
2932 * ixgbe_request_irq - initialize interrupts
2933 * @adapter: board private structure
2934 *
2935 * Attempts to configure interrupts using the best available
2936 * capabilities of the hardware and kernel.
2937 **/
021230d4 2938static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2939{
2940 struct net_device *netdev = adapter->netdev;
021230d4 2941 int err;
9a799d71 2942
4cc6df29 2943 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2944 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2945 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2946 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2947 netdev->name, adapter);
4cc6df29 2948 else
a0607fd3 2949 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2950 netdev->name, adapter);
9a799d71 2951
de88eeeb 2952 if (err)
396e799c 2953 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2954
9a799d71
AK		 2955 return err;
2956}
2957
2958static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2959{
49c7ffbe 2960 int vector;
9a799d71 2961
49c7ffbe
AD		 2962 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2963 free_irq(adapter->pdev->irq, adapter);
2964 return;
2965 }
4cc6df29 2966
49c7ffbe
AD		 2967 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2968 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2969 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2970
49c7ffbe
AD		 2971 /* free only the irqs that were actually requested */
2972 if (!q_vector->rx.ring && !q_vector->tx.ring)
2973 continue;
207867f5 2974
49c7ffbe
AD		 2975 /* clear the affinity_mask in the IRQ descriptor */
2976 irq_set_affinity_hint(entry->vector, NULL);
2977
2978 free_irq(entry->vector, q_vector);
9a799d71 2979 }
49c7ffbe
AD		 2980
2981 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2982}
2983
22d5a71b
JB		 2984/**
2985 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2986 * @adapter: board private structure
2987 **/
2988static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2989{
bd508178
AD		 2990 switch (adapter->hw.mac.type) {
2991 case ixgbe_mac_82598EB:
835462fc 2992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2993 break;
2994 case ixgbe_mac_82599EB:
b93a2226 2995 case ixgbe_mac_X540:
835462fc
NS		 2996 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2997 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2998 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2999 break;
3000 default:
3001 break;
22d5a71b
JB		 3002 }
3003 IXGBE_WRITE_FLUSH(&adapter->hw);
3004 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3005 int vector;
3006
3007 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3008 synchronize_irq(adapter->msix_entries[vector].vector);
3009
3010 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3011 } else {
3012 synchronize_irq(adapter->pdev->irq);
3013 }
3014}
3015
9a799d71
AK		 3016/**
3017 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3018 *
3019 **/
3020static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3021{
d5bf4f67 3022 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3023
d5bf4f67 3024 ixgbe_write_eitr(q_vector);
9a799d71 3025
e8e26350
PW		 3026 ixgbe_set_ivar(adapter, 0, 0, 0);
3027 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3028
396e799c 3029 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3030}
3031
43e69bf0
AD		 3032/**
3033 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3034 * @adapter: board private structure
3035 * @ring: structure containing ring specific data
3036 *
3037 * Configure the Tx descriptor ring after a reset.
3038 **/
84418e3b
AD		 3039void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3040 struct ixgbe_ring *ring)
43e69bf0
AD		 3041{
3042 struct ixgbe_hw *hw = &adapter->hw;
3043 u64 tdba = ring->dma;
2f1860b8 3044 int wait_loop = 10;
b88c6de2 3045 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3046 u8 reg_idx = ring->reg_idx;
43e69bf0 3047
2f1860b8 3048 /* disable queue to avoid issues while updating state */
b88c6de2 3049 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3050 IXGBE_WRITE_FLUSH(hw);
3051
43e69bf0 3052 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3053 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3054 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3055 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3056 ring->count * sizeof(union ixgbe_adv_tx_desc));
3057 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3058 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3059 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3060
b88c6de2
AD		 3061 /*
3062 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3063 * higher than 1 when:
3064 * - ITR is 0 as it could cause false TX hangs
3065 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3066 *
3067 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3068 * to or less than the number of on chip descriptors, which is
3069 * currently 40.
3070 */
67da097e
ET		 3071#if IS_ENABLED(CONFIG_BQL)
3072 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3073#else
e954b374 3074 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 3075#endif
b88c6de2
AD		 3076 txdctl |= (1 << 16); /* WTHRESH = 1 */
3077 else
3078 txdctl |= (8 << 16); /* WTHRESH = 8 */
3079
e954b374
AD		 3080 /*
3081 * Setting PTHRESH to 32 both improves performance
3082 * and avoids a TX hang with DFP enabled
3083 */
b88c6de2
AD		 3084 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3085 32; /* PTHRESH = 32 */
2f1860b8
AD		 3086
3087 /* reinitialize flowdirector state */
39cb681b 3088 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3089 ring->atr_sample_rate = adapter->atr_sample_rate;
3090 ring->atr_count = 0;
3091 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3092 } else {
3093 ring->atr_sample_rate = 0;
3094 }
2f1860b8 3095
fd786b7b
AD		 3096 /* initialize XPS */
3097 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3098 struct ixgbe_q_vector *q_vector = ring->q_vector;
3099
3100 if (q_vector)
2a47fa45 3101 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3102 &q_vector->affinity_mask,
3103 ring->queue_index);
3104 }
3105
c84d324c
JF		 3106 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3107
2f1860b8 3108 /* enable queue */
2f1860b8
AD		 3109 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3110
3111 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3112 if (hw->mac.type == ixgbe_mac_82598EB &&
3113 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3114 return;
3115
3116 /* poll to verify queue is enabled */
3117 do {
032b4325 3118 usleep_range(1000, 2000);
2f1860b8
AD		 3119 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3120 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3121 if (!wait_loop)
3122 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3123}
3124
120ff942
AD		 3125static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3126{
3127 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3128 u32 rttdcs, mtqc;
8b1c0b24 3129 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3130
3131 if (hw->mac.type == ixgbe_mac_82598EB)
3132 return;
3133
3134 /* disable the arbiter while setting MTQC */
3135 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3136 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3137 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3138
3139 /* set transmit pool layout */
671c0adb
AD		 3140 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3141 mtqc = IXGBE_MTQC_VT_ENA;
3142 if (tcs > 4)
3143 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3144 else if (tcs > 1)
3145 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3146 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3147 mtqc |= IXGBE_MTQC_32VF;
3148 else
3149 mtqc |= IXGBE_MTQC_64VF;
3150 } else {
3151 if (tcs > 4)
3152 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3153 else if (tcs > 1)
3154 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3155 else
671c0adb
AD		 3156 mtqc = IXGBE_MTQC_64Q_1PB;
3157 }
120ff942 3158
671c0adb 3159 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3160
671c0adb
AD		 3161 /* Enable Security TX Buffer IFG for multiple pb */
3162 if (tcs) {
3163 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3164 sectx |= IXGBE_SECTX_DCB;
3165 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3166 }
3167
3168 /* re-enable the arbiter */
3169 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3170 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3171}
3172
9a799d71 3173/**
3a581073 3174 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3175 * @adapter: board private structure
3176 *
3177 * Configure the Tx unit of the MAC after a reset.
3178 **/
3179static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3180{
2f1860b8
AD		 3181 struct ixgbe_hw *hw = &adapter->hw;
3182 u32 dmatxctl;
43e69bf0 3183 u32 i;
9a799d71 3184
2f1860b8
AD		 3185 ixgbe_setup_mtqc(adapter);
3186
3187 if (hw->mac.type != ixgbe_mac_82598EB) {
3188 /* DMATXCTL.EN must be before Tx queues are enabled */
3189 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3190 dmatxctl |= IXGBE_DMATXCTL_TE;
3191 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3192 }
3193
9a799d71 3194 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3195 for (i = 0; i < adapter->num_tx_queues; i++)
3196 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3197}
3198
3ebe8fde
AD		 3199static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3200 struct ixgbe_ring *ring)
3201{
3202 struct ixgbe_hw *hw = &adapter->hw;
3203 u8 reg_idx = ring->reg_idx;
3204 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3205
3206 srrctl |= IXGBE_SRRCTL_DROP_EN;
3207
3208 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3209}
3210
3211static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3212 struct ixgbe_ring *ring)
3213{
3214 struct ixgbe_hw *hw = &adapter->hw;
3215 u8 reg_idx = ring->reg_idx;
3216 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3217
3218 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3219
3220 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3221}
3222
3223#ifdef CONFIG_IXGBE_DCB
3224void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3225#else
3226static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3227#endif
3228{
3229 int i;
3230 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3231
3232 if (adapter->ixgbe_ieee_pfc)
3233 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3234
3235 /*
3236 * We should set the drop enable bit if:
3237 * SR-IOV is enabled
3238 * or
3239 * Number of Rx queues > 1 and flow control is disabled
3240 *
3241 * This allows us to avoid head of line blocking for security
3242 * and performance reasons.
3243 */
3244 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3245 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3246 for (i = 0; i < adapter->num_rx_queues; i++)
3247 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3248 } else {
3249 for (i = 0; i < adapter->num_rx_queues; i++)
3250 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3251 }
3252}
3253
e8e26350 3254#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3255
a6616b42 3256static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3257 struct ixgbe_ring *rx_ring)
cc41ac7c 3258{
45e9baa5 3259 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3260 u32 srrctl;
bf29ee6c 3261 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3262
45e9baa5
AD		 3263 if (hw->mac.type == ixgbe_mac_82598EB) {
3264 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3265
45e9baa5
AD		 3266 /*
3267 * if VMDq is not active we must program one srrctl register
3268 * per RSS queue since we have enabled RDRXCTL.MVMEN
3269 */
3270 reg_idx &= mask;
3271 }
cc41ac7c 3272
45e9baa5
AD		 3273 /* configure header buffer length, needed for RSC */
3274 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3275
45e9baa5 3276 /* configure the packet buffer length */
f800326d 3277 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3278
3279 /* configure descriptor type */
f800326d 3280 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3281
45e9baa5 3282 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3283}
9a799d71 3284
05abb126 3285static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3286{
05abb126
AD		 3287 struct ixgbe_hw *hw = &adapter->hw;
3288 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3289 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3290 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3291 u32 mrqc = 0, reta = 0;
3292 u32 rxcsum;
3293 int i, j;
671c0adb
AD		 3294 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3295
671c0adb
AD		 3296 /*
3297 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3298 * make full use of any rings they may have. We will use the
3299 * PSRTYPE register to control how many rings we use within the PF.
3300 */
3301 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3302 rss_i = 2;
0cefafad 3303
05abb126
AD		 3304 /* Fill out hash function seeds */
3305 for (i = 0; i < 10; i++)
3306 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3307
3308 /* Fill out redirection table */
3309 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3310 if (j == rss_i)
05abb126
AD		 3311 j = 0;
3312 /* reta = 4-byte sliding window of
3313 * 0x00..(indices-1)(indices-1)00..etc. */
3314 reta = (reta << 8) | (j * 0x11);
3315 if ((i & 3) == 3)
3316 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3317 }
0cefafad 3318
05abb126
AD		 3319 /* Disable indicating checksum in descriptor, enables RSS hash */
3320 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3321 rxcsum |= IXGBE_RXCSUM_PCSD;
3322 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3323
671c0adb 3324 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3325 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3326 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3327 } else {
671c0adb
AD		 3328 u8 tcs = netdev_get_num_tc(adapter->netdev);
3329
3330 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3331 if (tcs > 4)
3332 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3333 else if (tcs > 1)
3334 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3335 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3336 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3337 else
671c0adb
AD		 3338 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3339 } else {
3340 if (tcs > 4)
8b1c0b24 3341 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3342 else if (tcs > 1)
3343 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3344 else
3345 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3346 }
0cefafad
JB		 3347 }
3348
05abb126 3349 /* Perform hash on these packet types */
671c0adb
AD		 3350 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3351 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3352 IXGBE_MRQC_RSS_FIELD_IPV6 |
3353 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3354
ef6afc0c
AD		 3355 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3356 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3357 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3358 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3359
05abb126 3360 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3361}
3362
bb5a9ad2
NS		 3363/**
3364 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3365 * @adapter: address of board private structure
3366 * @index: index of ring to set
bb5a9ad2 3367 **/
082757af 3368static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3369 struct ixgbe_ring *ring)
bb5a9ad2 3370{
bb5a9ad2 3371 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3372 u32 rscctrl;
bf29ee6c 3373 u8 reg_idx = ring->reg_idx;
7367096a 3374
7d637bcc 3375 if (!ring_is_rsc_enabled(ring))
7367096a 3376 return;
bb5a9ad2 3377
7367096a 3378 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3379 rscctrl |= IXGBE_RSCCTL_RSCEN;
3380 /*
3381 * we must limit the number of descriptors so that the
3382 * total size of max desc * buf_len is not greater
642c680e 3383 * than 65536
bb5a9ad2 3384 */
f800326d 3385 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3386 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3387}
3388
9e10e045
AD		 3389#define IXGBE_MAX_RX_DESC_POLL 10
3390static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3391 struct ixgbe_ring *ring)
3392{
3393 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3394 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3395 u32 rxdctl;
bf29ee6c 3396 u8 reg_idx = ring->reg_idx;
9e10e045 3397
b0483c8f
MR		 3398 if (ixgbe_removed(hw->hw_addr))
3399 return;
9e10e045
AD		 3400 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3401 if (hw->mac.type == ixgbe_mac_82598EB &&
3402 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3403 return;
3404
3405 do {
032b4325 3406 usleep_range(1000, 2000);
9e10e045
AD		 3407 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3408 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3409
3410 if (!wait_loop) {
3411 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3412 "the polling period\n", reg_idx);
3413 }
3414}
3415
2d39d576
YZ		 3416void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3417 struct ixgbe_ring *ring)
3418{
3419 struct ixgbe_hw *hw = &adapter->hw;
3420 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3421 u32 rxdctl;
3422 u8 reg_idx = ring->reg_idx;
3423
b0483c8f
MR		 3424 if (ixgbe_removed(hw->hw_addr))
3425 return;
2d39d576
YZ		 3426 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3427 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3428
3429 /* write value back with RXDCTL.ENABLE bit cleared */
3430 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3431
3432 if (hw->mac.type == ixgbe_mac_82598EB &&
3433 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3434 return;
3435
3436 /* the hardware may take up to 100us to really disable the rx queue */
3437 do {
3438 udelay(10);
3439 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3440 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3441
3442 if (!wait_loop) {
3443 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3444 "the polling period\n", reg_idx);
3445 }
3446}
3447
84418e3b
AD		 3448void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3449 struct ixgbe_ring *ring)
acd37177
AD		 3450{
3451 struct ixgbe_hw *hw = &adapter->hw;
3452 u64 rdba = ring->dma;
9e10e045 3453 u32 rxdctl;
bf29ee6c 3454 u8 reg_idx = ring->reg_idx;
acd37177 3455
9e10e045
AD		 3456 /* disable queue to avoid issues while updating state */
3457 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3458 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3459
acd37177
AD		 3460 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3461 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3462 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3463 ring->count * sizeof(union ixgbe_adv_rx_desc));
3464 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3465 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3466 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3467
3468 ixgbe_configure_srrctl(adapter, ring);
3469 ixgbe_configure_rscctl(adapter, ring);
3470
3471 if (hw->mac.type == ixgbe_mac_82598EB) {
3472 /*
3473 * enable cache line friendly hardware writes:
3474 * PTHRESH=32 descriptors (half the internal cache),
3475 * this also removes ugly rx_no_buffer_count increment
3476 * HTHRESH=4 descriptors (to minimize latency on fetch)
3477 * WTHRESH=8 burst writeback up to two cache lines
3478 */
3479 rxdctl &= ~0x3FFFFF;
3480 rxdctl |= 0x080420;
3481 }
3482
3483 /* enable receive descriptor ring */
3484 rxdctl |= IXGBE_RXDCTL_ENABLE;
3485 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3486
3487 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3488 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3489}
3490
48654521
AD		 3491static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3492{
3493 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3494 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3495 u16 pool;
48654521
AD		 3496
3497 /* PSRTYPE must be initialized in non 82598 adapters */
3498 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3499 IXGBE_PSRTYPE_UDPHDR |
3500 IXGBE_PSRTYPE_IPV4HDR |
48654521 3501 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3502 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3503
3504 if (hw->mac.type == ixgbe_mac_82598EB)
3505 return;
3506
fbe7ca7f
AD		 3507 if (rss_i > 3)
3508 psrtype |= 2 << 29;
3509 else if (rss_i > 1)
3510 psrtype |= 1 << 29;
48654521 3511
2a47fa45
JF		 3512 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3513 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3514}
3515
f5b4a52e
AD		 3516static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3517{
3518 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3519 u32 reg_offset, vf_shift;
435b19f6 3520 u32 gcr_ext, vmdctl;
de4c7f65 3521 int i;
f5b4a52e
AD		 3522
3523 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3524 return;
3525
3526 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3527 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3528 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3529 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3530 vmdctl |= IXGBE_VT_CTL_REPLEN;
3531 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3532
1d9c0bfd
AD		 3533 vf_shift = VMDQ_P(0) % 32;
3534 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3535
3536 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3537 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3538 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3539 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3540 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3541 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3542 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3543
3544 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3545 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3546
3547 /*
3548 * Set up VF register offsets for selected VT Mode,
3549 * i.e. 32 or 64 VFs for SR-IOV
3550 */
73079ea0
AD		 3551 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3552 case IXGBE_82599_VMDQ_8Q_MASK:
3553 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3554 break;
3555 case IXGBE_82599_VMDQ_4Q_MASK:
3556 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3557 break;
3558 default:
3559 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3560 break;
3561 }
3562
f5b4a52e
AD		 3563 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3564
435b19f6 3565
a985b6c3 3566 /* Enable MAC Anti-Spoofing */
435b19f6 3567 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3568 adapter->num_vfs);
de4c7f65
GR		 3569 /* For VFs that have spoof checking turned off */
3570 for (i = 0; i < adapter->num_vfs; i++) {
3571 if (!adapter->vfinfo[i].spoofchk_enabled)
3572 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3573 }
f5b4a52e
AD		 3574}
3575
477de6ed 3576static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3577{
9a799d71
AK		 3578 struct ixgbe_hw *hw = &adapter->hw;
3579 struct net_device *netdev = adapter->netdev;
3580 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3581 struct ixgbe_ring *rx_ring;
3582 int i;
3583 u32 mhadd, hlreg0;
48654521 3584
63f39bd1 3585#ifdef IXGBE_FCOE
477de6ed
AD		 3586 /* adjust max frame to be able to do baby jumbo for FCoE */
3587 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3588 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3589 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3590
477de6ed 3591#endif /* IXGBE_FCOE */
872844dd
AD		 3592
3593 /* adjust max frame to be at least the size of a standard frame */
3594 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3595 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3596
477de6ed
AD		 3597 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3598 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3599 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3600 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3601
3602 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3603 }
3604
3605 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3606 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3607 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3608 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3609
0cefafad
JB		 3610 /*
3611 * Setup the HW Rx Head and Tail Descriptor Pointers and
3612 * the Base and Length of the Rx Descriptor Ring
3613 */
9a799d71 3614 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3615 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3616 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3617 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3618 else
7d637bcc 3619 clear_ring_rsc_enabled(rx_ring);
477de6ed 3620 }
477de6ed
AD		 3621}
3622
7367096a
AD		 3623static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3624{
3625 struct ixgbe_hw *hw = &adapter->hw;
3626 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3627
3628 switch (hw->mac.type) {
3629 case ixgbe_mac_82598EB:
3630 /*
3631 * For VMDq support of different descriptor types or
3632 * buffer sizes through the use of multiple SRRCTL
3633 * registers, RDRXCTL.MVMEN must be set to 1
3634 *
3635 * also, the manual doesn't mention it clearly but DCA hints
3636 * will only use queue 0's tags unless this bit is set. Side
3637 * effects of setting this bit are only that SRRCTL must be
3638 * fully programmed [0..15]
3639 */
3640 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3641 break;
3642 case ixgbe_mac_82599EB:
b93a2226 3643 case ixgbe_mac_X540:
7367096a
AD		 3644 /* Disable RSC for ACK packets */
3645 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3646 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3647 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3648 /* hardware requires some bits to be set by default */
3649 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3650 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3651 break;
3652 default:
3653 /* We should do nothing since we don't know this hardware */
3654 return;
3655 }
3656
3657 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3658}
3659
477de6ed
AD		 3660/**
3661 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3662 * @adapter: board private structure
3663 *
3664 * Configure the Rx unit of the MAC after a reset.
3665 **/
3666static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3667{
3668 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3669 int i;
6dcc28b9 3670 u32 rxctrl, rfctl;
477de6ed
AD		 3671
3672 /* disable receives while setting up the descriptors */
3673 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3674 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3675
3676 ixgbe_setup_psrtype(adapter);
7367096a 3677 ixgbe_setup_rdrxctl(adapter);
477de6ed 3678
6dcc28b9
JK		 3679 /* RSC Setup */
3680 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3681 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3682 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3683 rfctl |= IXGBE_RFCTL_RSC_DIS;
3684 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3685
9e10e045 3686 /* Program registers for the distribution of queues */
f5b4a52e 3687 ixgbe_setup_mrqc(adapter);
f5b4a52e 3688
477de6ed
AD		 3689 /* set_rx_buffer_len must be called before ring initialization */
3690 ixgbe_set_rx_buffer_len(adapter);
3691
3692 /*
3693 * Setup the HW Rx Head and Tail Descriptor Pointers and
3694 * the Base and Length of the Rx Descriptor Ring
3695 */
9e10e045
AD		 3696 for (i = 0; i < adapter->num_rx_queues; i++)
3697 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3698
9e10e045
AD		 3699 /* disable drop enable for 82598 parts */
3700 if (hw->mac.type == ixgbe_mac_82598EB)
3701 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3702
3703 /* enable all receives */
3704 rxctrl |= IXGBE_RXCTRL_RXEN;
3705 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3706}
3707
80d5c368
PM		 3708static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3709 __be16 proto, u16 vid)
068c89b0
DS		 3710{
3711 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3712 struct ixgbe_hw *hw = &adapter->hw;
3713
3714 /* add VID to filter table */
1d9c0bfd 3715 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3716 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3717
3718 return 0;
068c89b0
DS		 3719}
3720
80d5c368
PM		 3721static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3722 __be16 proto, u16 vid)
068c89b0
DS		 3723{
3724 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3725 struct ixgbe_hw *hw = &adapter->hw;
3726
068c89b0 3727 /* remove VID from filter table */
1d9c0bfd 3728 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3729 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3730
3731 return 0;
068c89b0
DS		 3732}
3733
5f6c0181
JB		 3734/**
3735 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3736 * @adapter: driver data
3737 */
3738static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3739{
3740 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3741 u32 vlnctrl;
3742
3743 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3744 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3745 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3746}
3747
3748/**
3749 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3750 * @adapter: driver data
3751 */
3752static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3753{
3754 struct ixgbe_hw *hw = &adapter->hw;
3755 u32 vlnctrl;
3756
3757 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3758 vlnctrl |= IXGBE_VLNCTRL_VFE;
3759 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3760 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3761}
3762
3763/**
3764 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3765 * @adapter: driver data
3766 */
3767static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3768{
3769 struct ixgbe_hw *hw = &adapter->hw;
3770 u32 vlnctrl;
5f6c0181
JB		 3771 int i, j;
3772
3773 switch (hw->mac.type) {
3774 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3775 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3776 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3777 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3778 break;
3779 case ixgbe_mac_82599EB:
b93a2226 3780 case ixgbe_mac_X540:
5f6c0181 3781 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3782 struct ixgbe_ring *ring = adapter->rx_ring[i];
3783
3784 if (ring->l2_accel_priv)
3785 continue;
3786 j = ring->reg_idx;
5f6c0181
JB		 3787 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3788 vlnctrl &= ~IXGBE_RXDCTL_VME;
3789 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3790 }
3791 break;
3792 default:
3793 break;
3794 }
3795}
3796
3797/**
f62bbb5e 3798 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3799 * @adapter: driver data
3800 */
f62bbb5e 3801static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3802{
3803 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3804 u32 vlnctrl;
5f6c0181
JB		 3805 int i, j;
3806
3807 switch (hw->mac.type) {
3808 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3809 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3810 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3811 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3812 break;
3813 case ixgbe_mac_82599EB:
b93a2226 3814 case ixgbe_mac_X540:
5f6c0181 3815 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3816 struct ixgbe_ring *ring = adapter->rx_ring[i];
3817
3818 if (ring->l2_accel_priv)
3819 continue;
3820 j = ring->reg_idx;
5f6c0181
JB		 3821 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3822 vlnctrl |= IXGBE_RXDCTL_VME;
3823 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3824 }
3825 break;
3826 default:
3827 break;
3828 }
3829}
3830
9a799d71
AK		 3831static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3832{
f62bbb5e 3833 u16 vid;
9a799d71 3834
80d5c368 3835 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3836
3837 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3838 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3839}
3840
2850062a
AD		 3841/**
3842 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3843 * @netdev: network interface device structure
3844 *
3845 * Writes unicast address list to the RAR table.
3846 * Returns: -ENOMEM on failure/insufficient address space
3847 * 0 on no addresses written
3848 * X on writing X addresses to the RAR table
3849 **/
3850static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3851{
3852 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3853 struct ixgbe_hw *hw = &adapter->hw;
95447461 3854 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3855 int count = 0;
3856
2a47fa45 3857 /* In SR-IOV/VMDQ modes significantly less RAR entries are available */
95447461
JF		 3858 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3859 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3860
2850062a
AD		 3861 /* return ENOMEM indicating insufficient memory for addresses */
3862 if (netdev_uc_count(netdev) > rar_entries)
3863 return -ENOMEM;
3864
95447461 3865 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3866 struct netdev_hw_addr *ha;
3867 /* return error if we do not support writing to RAR table */
3868 if (!hw->mac.ops.set_rar)
3869 return -ENOMEM;
3870
3871 netdev_for_each_uc_addr(ha, netdev) {
3872 if (!rar_entries)
3873 break;
3874 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3875 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3876 count++;
3877 }
3878 }
3879 /* write the addresses in reverse order to avoid write combining */
3880 for (; rar_entries > 0 ; rar_entries--)
3881 hw->mac.ops.clear_rar(hw, rar_entries);
3882
3883 return count;
3884}
3885
9a799d71 3886/**
2c5645cf 3887 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3888 * @netdev: network interface device structure
3889 *
2c5645cf
CL		 3890 * The set_rx_method entry point is called whenever the unicast/multicast
3891 * address list or the network interface flags are updated. This routine is
3892 * responsible for configuring the hardware for proper unicast, multicast and
3893 * promiscuous mode.
9a799d71 3894 **/
7f870475 3895void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3896{
3897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3898 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3899 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3900 int count;
9a799d71
AK		 3901
3902 /* Check for Promiscuous and All Multicast modes */
3903
3904 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3905
f5dc442b 3906 /* set all bits that we expect to always be set */
3f2d1c0f 3907 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3908 fctrl |= IXGBE_FCTRL_BAM;
3909 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3910 fctrl |= IXGBE_FCTRL_PMCF;
3911
2850062a
AD		 3912 /* clear the bits we are changing the status of */
3913 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3914
9a799d71 3915 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3916 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3917 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3918 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3919 /* Only disable hardware filter vlans in promiscuous mode
3920 * if SR-IOV and VMDQ are disabled - otherwise ensure
3921 * that hardware VLAN filters remain enabled.
3922 */
3923 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3924 IXGBE_FLAG_SRIOV_ENABLED)))
3925 ixgbe_vlan_filter_disable(adapter);
3926 else
3927 ixgbe_vlan_filter_enable(adapter);
9a799d71 3928 } else {
746b9f02
PM		 3929 if (netdev->flags & IFF_ALLMULTI) {
3930 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3931 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3932 }
5f6c0181 3933 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3934 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3935 }
3936
3937 /*
3938 * Write addresses to available RAR registers, if there is not
3939 * sufficient space to store all the addresses then enable
3940 * unicast promiscuous mode
3941 */
3942 count = ixgbe_write_uc_addr_list(netdev);
3943 if (count < 0) {
3944 fctrl |= IXGBE_FCTRL_UPE;
3945 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3946 }
3947
cf78959c
ET		 3948 /* Write addresses to the MTA, if the attempt fails
3949 * then we should just turn on promiscuous mode so
3950 * that we can at least receive multicast traffic
3951 */
3952 hw->mac.ops.update_mc_addr_list(hw, netdev);
3953 vmolr |= IXGBE_VMOLR_ROMPE;
3954
1d9c0bfd 3955 if (adapter->num_vfs)
1cdd1ec8 3956 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3957
3958 if (hw->mac.type != ixgbe_mac_82598EB) {
3959 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3960 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3961 IXGBE_VMOLR_ROPE);
1d9c0bfd 3962 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3963 }
3964
3f2d1c0f
BG		 3965 /* This is useful for sniffing bad packets. */
3966 if (adapter->netdev->features & NETIF_F_RXALL) {
3967 /* UPE and MPE will be handled by normal PROMISC logic
3968 * in e1000e_set_rx_mode */
3969 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3970 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3971 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3972
3973 fctrl &= ~(IXGBE_FCTRL_DPF);
3974 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3975 }
3976
2850062a 3977 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3978
f646968f 3979 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3980 ixgbe_vlan_strip_enable(adapter);
3981 else
3982 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3983}
3984
021230d4
AV		 3985static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3986{
3987 int q_idx;
021230d4 3988
5a85e737
ET		 3989 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3990 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 3991 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 3992 }
021230d4
AV		 3993}
3994
3995static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3996{
3997 int q_idx;
021230d4 3998
5a85e737 3999 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4000 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4001 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4002 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4003 usleep_range(1000, 20000);
5a85e737
ET		 4004 }
4005 }
021230d4
AV		 4006}
4007
7a6b6f51 4008#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4009/**
2f90b865
AD		 4010 * ixgbe_configure_dcb - Configure DCB hardware
4011 * @adapter: ixgbe adapter struct
4012 *
4013 * This is called by the driver on open to configure the DCB hardware.
4014 * This is also called by the gennetlink interface when reconfiguring
4015 * the DCB state.
4016 */
4017static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4018{
4019 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4020 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4021
67ebd791
AD		 4022 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4023 if (hw->mac.type == ixgbe_mac_82598EB)
4024 netif_set_gso_max_size(adapter->netdev, 65536);
4025 return;
4026 }
4027
4028 if (hw->mac.type == ixgbe_mac_82598EB)
4029 netif_set_gso_max_size(adapter->netdev, 32768);
4030
971060b1 4031#ifdef IXGBE_FCOE
b120818e
JF		 4032 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4033 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4034#endif
b120818e
JF		 4035
4036 /* reconfigure the hardware */
4037 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4038 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4039 DCB_TX_CONFIG);
4040 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4041 DCB_RX_CONFIG);
4042 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4043 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4044 ixgbe_dcb_hw_ets(&adapter->hw,
4045 adapter->ixgbe_ieee_ets,
4046 max_frame);
4047 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4048 adapter->ixgbe_ieee_pfc->pfc_en,
4049 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4050 }
8187cd48
JF		 4051
4052 /* Enable RSS Hash per TC */
4053 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4054 u32 msb = 0;
4055 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4056
d411a936
AD		 4057 while (rss_i) {
4058 msb++;
4059 rss_i >>= 1;
4060 }
8187cd48 4061
4ae63730
AD		 4062 /* write msb to all 8 TCs in one write */
4063 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4064 }
2f90b865 4065}
9da712d2
JF		 4066#endif
4067
4068/* Additional bittime to account for IXGBE framing */
4069#define IXGBE_ETH_FRAMING 20
4070
49ce9c2c 4071/**
9da712d2
JF		 4072 * ixgbe_hpbthresh - calculate high water mark for flow control
4073 *
4074 * @adapter: board private structure to calculate for
49ce9c2c 4075 * @pb: packet buffer to calculate
9da712d2
JF		 4076 */
4077static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4078{
4079 struct ixgbe_hw *hw = &adapter->hw;
4080 struct net_device *dev = adapter->netdev;
4081 int link, tc, kb, marker;
4082 u32 dv_id, rx_pba;
4083
4084 /* Calculate max LAN frame size */
4085 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4086
4087#ifdef IXGBE_FCOE
4088 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4089 if ((dev->features & NETIF_F_FCOE_MTU) &&
4090 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4091 (pb == ixgbe_fcoe_get_tc(adapter)))
4092 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 4093
4094#endif
9da712d2
JF		 4095 /* Calculate delay value for device */
4096 switch (hw->mac.type) {
4097 case ixgbe_mac_X540:
4098 dv_id = IXGBE_DV_X540(link, tc);
4099 break;
4100 default:
4101 dv_id = IXGBE_DV(link, tc);
4102 break;
4103 }
4104
4105 /* Loopback switch introduces additional latency */
4106 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4107 dv_id += IXGBE_B2BT(tc);
4108
4109 /* Delay value is calculated in bit times convert to KB */
4110 kb = IXGBE_BT2KB(dv_id);
4111 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4112
4113 marker = rx_pba - kb;
4114
4115 /* It is possible that the packet buffer is not large enough
4116 * to provide required headroom. In this case throw an error
4117 * to user and a do the best we can.
4118 */
4119 if (marker < 0) {
4120 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4121 "headroom to support flow control."
4122 "Decrease MTU or number of traffic classes\n", pb);
4123 marker = tc + 1;
4124 }
4125
4126 return marker;
4127}
4128
49ce9c2c 4129/**
9da712d2
JF		 4130 * ixgbe_lpbthresh - calculate low water mark for for flow control
4131 *
4132 * @adapter: board private structure to calculate for
49ce9c2c 4133 * @pb: packet buffer to calculate
9da712d2
JF		 4134 */
4135static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4136{
4137 struct ixgbe_hw *hw = &adapter->hw;
4138 struct net_device *dev = adapter->netdev;
4139 int tc;
4140 u32 dv_id;
4141
4142 /* Calculate max LAN frame size */
4143 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4144
4145 /* Calculate delay value for device */
4146 switch (hw->mac.type) {
4147 case ixgbe_mac_X540:
4148 dv_id = IXGBE_LOW_DV_X540(tc);
4149 break;
4150 default:
4151 dv_id = IXGBE_LOW_DV(tc);
4152 break;
4153 }
4154
4155 /* Delay value is calculated in bit times convert to KB */
4156 return IXGBE_BT2KB(dv_id);
4157}
4158
4159/*
4160 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4161 */
4162static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4163{
4164 struct ixgbe_hw *hw = &adapter->hw;
4165 int num_tc = netdev_get_num_tc(adapter->netdev);
4166 int i;
4167
4168 if (!num_tc)
4169 num_tc = 1;
4170
4171 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4172
4173 for (i = 0; i < num_tc; i++) {
4174 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4175
4176 /* Low water marks must not be larger than high water marks */
4177 if (hw->fc.low_water > hw->fc.high_water[i])
4178 hw->fc.low_water = 0;
4179 }
4180}
4181
80605c65
JF		 4182static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4183{
80605c65 4184 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4185 int hdrm;
4186 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4187
4188 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4189 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4190 hdrm = 32 << adapter->fdir_pballoc;
4191 else
4192 hdrm = 0;
80605c65 4193
f7e1027f 4194 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4195 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4196}
4197
e4911d57
AD		 4198static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4199{
4200 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4201 struct hlist_node *node2;
e4911d57
AD		 4202 struct ixgbe_fdir_filter *filter;
4203
4204 spin_lock(&adapter->fdir_perfect_lock);
4205
4206 if (!hlist_empty(&adapter->fdir_filter_list))
4207 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4208
b67bfe0d 4209 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4210 &adapter->fdir_filter_list, fdir_node) {
4211 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4212 &filter->filter,
4213 filter->sw_idx,
4214 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4215 IXGBE_FDIR_DROP_QUEUE :
4216 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4217 }
4218
4219 spin_unlock(&adapter->fdir_perfect_lock);
4220}
4221
2a47fa45
JF		 4222static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4223 struct ixgbe_adapter *adapter)
4224{
4225 struct ixgbe_hw *hw = &adapter->hw;
4226 u32 vmolr;
4227
4228 /* No unicast promiscuous support for VMDQ devices. */
4229 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4230 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4231
4232 /* clear the affected bit */
4233 vmolr &= ~IXGBE_VMOLR_MPE;
4234
4235 if (dev->flags & IFF_ALLMULTI) {
4236 vmolr |= IXGBE_VMOLR_MPE;
4237 } else {
4238 vmolr |= IXGBE_VMOLR_ROMPE;
4239 hw->mac.ops.update_mc_addr_list(hw, dev);
4240 }
4241 ixgbe_write_uc_addr_list(adapter->netdev);
4242 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4243}
4244
4245static void ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4246 u8 *addr, u16 pool)
4247{
4248 struct ixgbe_hw *hw = &adapter->hw;
4249 unsigned int entry;
4250
4251 entry = hw->mac.num_rar_entries - pool;
4252 hw->mac.ops.set_rar(hw, entry, addr, VMDQ_P(pool), IXGBE_RAH_AV);
4253}
4254
4255static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4256{
4257 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4258 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4259 struct ixgbe_hw *hw = &adapter->hw;
4260 u16 pool = vadapter->pool;
4261 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4262 IXGBE_PSRTYPE_UDPHDR |
4263 IXGBE_PSRTYPE_IPV4HDR |
4264 IXGBE_PSRTYPE_L2HDR |
4265 IXGBE_PSRTYPE_IPV6HDR;
4266
4267 if (hw->mac.type == ixgbe_mac_82598EB)
4268 return;
4269
4270 if (rss_i > 3)
4271 psrtype |= 2 << 29;
4272 else if (rss_i > 1)
4273 psrtype |= 1 << 29;
4274
4275 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4276}
4277
4278/**
4279 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4280 * @rx_ring: ring to free buffers from
4281 **/
4282static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4283{
4284 struct device *dev = rx_ring->dev;
4285 unsigned long size;
4286 u16 i;
4287
4288 /* ring already cleared, nothing to do */
4289 if (!rx_ring->rx_buffer_info)
4290 return;
4291
4292 /* Free all the Rx ring sk_buffs */
4293 for (i = 0; i < rx_ring->count; i++) {
4294 struct ixgbe_rx_buffer *rx_buffer;
4295
4296 rx_buffer = &rx_ring->rx_buffer_info[i];
4297 if (rx_buffer->skb) {
4298 struct sk_buff *skb = rx_buffer->skb;
4299 if (IXGBE_CB(skb)->page_released) {
4300 dma_unmap_page(dev,
4301 IXGBE_CB(skb)->dma,
4302 ixgbe_rx_bufsz(rx_ring),
4303 DMA_FROM_DEVICE);
4304 IXGBE_CB(skb)->page_released = false;
4305 }
4306 dev_kfree_skb(skb);
4307 }
4308 rx_buffer->skb = NULL;
4309 if (rx_buffer->dma)
4310 dma_unmap_page(dev, rx_buffer->dma,
4311 ixgbe_rx_pg_size(rx_ring),
4312 DMA_FROM_DEVICE);
4313 rx_buffer->dma = 0;
4314 if (rx_buffer->page)
4315 __free_pages(rx_buffer->page,
4316 ixgbe_rx_pg_order(rx_ring));
4317 rx_buffer->page = NULL;
4318 }
4319
4320 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4321 memset(rx_ring->rx_buffer_info, 0, size);
4322
4323 /* Zero out the descriptor ring */
4324 memset(rx_ring->desc, 0, rx_ring->size);
4325
4326 rx_ring->next_to_alloc = 0;
4327 rx_ring->next_to_clean = 0;
4328 rx_ring->next_to_use = 0;
4329}
4330
4331static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4332 struct ixgbe_ring *rx_ring)
4333{
4334 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4335 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4336
4337 /* shutdown specific queue receive and wait for dma to settle */
4338 ixgbe_disable_rx_queue(adapter, rx_ring);
4339 usleep_range(10000, 20000);
4340 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4341 ixgbe_clean_rx_ring(rx_ring);
4342 rx_ring->l2_accel_priv = NULL;
4343}
4344
ae72c8d0
JF		 4345static int ixgbe_fwd_ring_down(struct net_device *vdev,
4346 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4347{
4348 struct ixgbe_adapter *adapter = accel->real_adapter;
4349 unsigned int rxbase = accel->rx_base_queue;
4350 unsigned int txbase = accel->tx_base_queue;
4351 int i;
4352
4353 netif_tx_stop_all_queues(vdev);
4354
4355 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4356 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4357 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4358 }
4359
4360 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4361 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4362 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4363 }
4364
4365
4366 return 0;
4367}
4368
4369static int ixgbe_fwd_ring_up(struct net_device *vdev,
4370 struct ixgbe_fwd_adapter *accel)
4371{
4372 struct ixgbe_adapter *adapter = accel->real_adapter;
4373 unsigned int rxbase, txbase, queues;
4374 int i, baseq, err = 0;
4375
4376 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4377 return 0;
4378
4379 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4380 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4381 accel->pool, adapter->num_rx_pools,
4382 baseq, baseq + adapter->num_rx_queues_per_pool,
4383 adapter->fwd_bitmask);
4384
4385 accel->netdev = vdev;
4386 accel->rx_base_queue = rxbase = baseq;
4387 accel->tx_base_queue = txbase = baseq;
4388
4389 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4390 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4391
4392 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4393 adapter->rx_ring[rxbase + i]->netdev = vdev;
4394 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4395 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4396 }
4397
4398 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4399 adapter->tx_ring[txbase + i]->netdev = vdev;
4400 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4401 }
4402
4403 queues = min_t(unsigned int,
4404 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4405 err = netif_set_real_num_tx_queues(vdev, queues);
4406 if (err)
4407 goto fwd_queue_err;
4408
2a47fa45
JF		 4409 err = netif_set_real_num_rx_queues(vdev, queues);
4410 if (err)
4411 goto fwd_queue_err;
4412
4413 if (is_valid_ether_addr(vdev->dev_addr))
4414 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4415
4416 ixgbe_fwd_psrtype(accel);
4417 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4418 return err;
4419fwd_queue_err:
4420 ixgbe_fwd_ring_down(vdev, accel);
4421 return err;
4422}
4423
4424static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4425{
4426 struct net_device *upper;
4427 struct list_head *iter;
4428 int err;
4429
4430 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4431 if (netif_is_macvlan(upper)) {
4432 struct macvlan_dev *dfwd = netdev_priv(upper);
4433 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4434
4435 if (dfwd->fwd_priv) {
4436 err = ixgbe_fwd_ring_up(upper, vadapter);
4437 if (err)
4438 continue;
4439 }
4440 }
4441 }
4442}
4443
9a799d71
AK		 4444static void ixgbe_configure(struct ixgbe_adapter *adapter)
4445{
d2f5e7f3
AS		 4446 struct ixgbe_hw *hw = &adapter->hw;
4447
80605c65 4448 ixgbe_configure_pb(adapter);
7a6b6f51 4449#ifdef CONFIG_IXGBE_DCB
67ebd791 4450 ixgbe_configure_dcb(adapter);
2f90b865 4451#endif
b35d4d42
AD		 4452 /*
4453 * We must restore virtualization before VLANs or else
4454 * the VLVF registers will not be populated
4455 */
4456 ixgbe_configure_virtualization(adapter);
9a799d71 4457
4c1d7b4b 4458 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4459 ixgbe_restore_vlan(adapter);
4460
d2f5e7f3
AS		 4461 switch (hw->mac.type) {
4462 case ixgbe_mac_82599EB:
4463 case ixgbe_mac_X540:
4464 hw->mac.ops.disable_rx_buff(hw);
4465 break;
4466 default:
4467 break;
4468 }
4469
c4cf55e5 4470 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4471 ixgbe_init_fdir_signature_82599(&adapter->hw,
4472 adapter->fdir_pballoc);
e4911d57
AD		 4473 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4474 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4475 adapter->fdir_pballoc);
4476 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4477 }
4c1d7b4b 4478
d2f5e7f3
AS		 4479 switch (hw->mac.type) {
4480 case ixgbe_mac_82599EB:
4481 case ixgbe_mac_X540:
4482 hw->mac.ops.enable_rx_buff(hw);
4483 break;
4484 default:
4485 break;
4486 }
4487
7c8ae65a
AD		 4488#ifdef IXGBE_FCOE
4489 /* configure FCoE L2 filters, redirection table, and Rx control */
4490 ixgbe_configure_fcoe(adapter);
4491
4492#endif /* IXGBE_FCOE */
9a799d71
AK		 4493 ixgbe_configure_tx(adapter);
4494 ixgbe_configure_rx(adapter);
2a47fa45 4495 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4496}
4497
e8e26350
PW		 4498static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4499{
4500 switch (hw->phy.type) {
4501 case ixgbe_phy_sfp_avago:
4502 case ixgbe_phy_sfp_ftl:
4503 case ixgbe_phy_sfp_intel:
4504 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4505 case ixgbe_phy_sfp_passive_tyco:
4506 case ixgbe_phy_sfp_passive_unknown:
4507 case ixgbe_phy_sfp_active_unknown:
4508 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4509 case ixgbe_phy_qsfp_passive_unknown:
4510 case ixgbe_phy_qsfp_active_unknown:
4511 case ixgbe_phy_qsfp_intel:
4512 case ixgbe_phy_qsfp_unknown:
e8e26350 4513 return true;
8917b447
AD		 4514 case ixgbe_phy_nl:
4515 if (hw->mac.type == ixgbe_mac_82598EB)
4516 return true;
e8e26350
PW		 4517 default:
4518 return false;
4519 }
4520}
4521
0ecc061d 4522/**
e8e26350
PW		 4523 * ixgbe_sfp_link_config - set up SFP+ link
4524 * @adapter: pointer to private adapter struct
4525 **/
4526static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4527{
7086400d 4528 /*
52f33af8 4529 * We are assuming the worst case scenario here, and that
7086400d
AD		 4530 * is that an SFP was inserted/removed after the reset
4531 * but before SFP detection was enabled. As such the best
4532 * solution is to just start searching as soon as we start
4533 */
4534 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4535 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4536
7086400d 4537 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4538}
4539
4540/**
4541 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4542 * @hw: pointer to private hardware struct
4543 *
4544 * Returns 0 on success, negative on failure
4545 **/
e8e26350 4546static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4547{
3d292265
JH		 4548 u32 speed;
4549 bool autoneg, link_up = false;
0ecc061d
PWJ		 4550 u32 ret = IXGBE_ERR_LINK_SETUP;
4551
4552 if (hw->mac.ops.check_link)
3d292265 4553 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4554
4555 if (ret)
4556 goto link_cfg_out;
4557
3d292265
JH		 4558 speed = hw->phy.autoneg_advertised;
4559 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4560 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4561 &autoneg);
0ecc061d
PWJ		 4562 if (ret)
4563 goto link_cfg_out;
4564
8620a103 4565 if (hw->mac.ops.setup_link)
fd0326f2 4566 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4567link_cfg_out:
4568 return ret;
4569}
4570
a34bcfff 4571static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4572{
9a799d71 4573 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4574 u32 gpie = 0;
9a799d71 4575
9b471446 4576 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4577 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4578 IXGBE_GPIE_OCD;
4579 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4580 /*
4581 * use EIAM to auto-mask when MSI-X interrupt is asserted
4582 * this saves a register write for every interrupt
4583 */
4584 switch (hw->mac.type) {
4585 case ixgbe_mac_82598EB:
4586 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4587 break;
9b471446 4588 case ixgbe_mac_82599EB:
b93a2226
DS		 4589 case ixgbe_mac_X540:
4590 default:
9b471446
JB		 4591 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4592 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4593 break;
4594 }
4595 } else {
021230d4
AV		 4596 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4597 * specifically only auto mask tx and rx interrupts */
4598 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4599 }
9a799d71 4600
a34bcfff
AD		 4601 /* XXX: to interrupt immediately for EICS writes, enable this */
4602 /* gpie |= IXGBE_GPIE_EIMEN; */
4603
4604 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4605 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4606
4607 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4608 case IXGBE_82599_VMDQ_8Q_MASK:
4609 gpie |= IXGBE_GPIE_VTMODE_16;
4610 break;
4611 case IXGBE_82599_VMDQ_4Q_MASK:
4612 gpie |= IXGBE_GPIE_VTMODE_32;
4613 break;
4614 default:
4615 gpie |= IXGBE_GPIE_VTMODE_64;
4616 break;
4617 }
119fc60a
MC		 4618 }
4619
5fdd31f9 4620 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4621 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4622 switch (adapter->hw.mac.type) {
4623 case ixgbe_mac_82599EB:
4624 gpie |= IXGBE_SDP0_GPIEN;
4625 break;
4626 case ixgbe_mac_X540:
4627 gpie |= IXGBE_EIMS_TS;
4628 break;
4629 default:
4630 break;
4631 }
4632 }
5fdd31f9 4633
a34bcfff
AD		 4634 /* Enable fan failure interrupt */
4635 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4636 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4637
2698b208 4638 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4639 gpie |= IXGBE_SDP1_GPIEN;
4640 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4641 }
a34bcfff
AD		 4642
4643 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4644}
4645
c7ccde0f 4646static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4647{
4648 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4649 struct net_device *upper;
4650 struct list_head *iter;
a34bcfff 4651 int err;
a34bcfff
AD		 4652 u32 ctrl_ext;
4653
4654 ixgbe_get_hw_control(adapter);
4655 ixgbe_setup_gpie(adapter);
e8e26350 4656
9a799d71
AK		 4657 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4658 ixgbe_configure_msix(adapter);
4659 else
4660 ixgbe_configure_msi_and_legacy(adapter);
4661
ec74a471
ET		 4662 /* enable the optics for 82599 SFP+ fiber */
4663 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4664 hw->mac.ops.enable_tx_laser(hw);
4665
c3049c8f 4666 smp_mb__before_clear_bit();
9a799d71 4667 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4668 ixgbe_napi_enable_all(adapter);
4669
73c4b7cd
AD		 4670 if (ixgbe_is_sfp(hw)) {
4671 ixgbe_sfp_link_config(adapter);
4672 } else {
4673 err = ixgbe_non_sfp_link_config(hw);
4674 if (err)
4675 e_err(probe, "link_config FAILED %d\n", err);
4676 }
4677
021230d4
AV		 4678 /* clear any pending interrupts, may auto mask */
4679 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4680 ixgbe_irq_enable(adapter, true, true);
9a799d71 4681
bf069c97
DS		 4682 /*
4683 * If this adapter has a fan, check to see if we had a failure
4684 * before we enabled the interrupt.
4685 */
4686 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4687 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4688 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4689 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4690 }
4691
1da100bb 4692 /* enable transmits */
477de6ed 4693 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4694
2a47fa45
JF		 4695 /* enable any upper devices */
4696 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4697 if (netif_is_macvlan(upper)) {
4698 struct macvlan_dev *vlan = netdev_priv(upper);
4699
4700 if (vlan->fwd_priv)
4701 netif_tx_start_all_queues(upper);
4702 }
4703 }
4704
9a799d71
AK		 4705 /* bring the link up in the watchdog, this could race with our first
4706 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4707 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4708 adapter->link_check_timeout = jiffies;
7086400d 4709 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4710
4711 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4712 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4713 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4714 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4715}
4716
d4f80882
AV		 4717void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4718{
4719 WARN_ON(in_interrupt());
7086400d
AD		 4720 /* put off any impending NetWatchDogTimeout */
4721 adapter->netdev->trans_start = jiffies;
4722
d4f80882 4723 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4724 usleep_range(1000, 2000);
d4f80882 4725 ixgbe_down(adapter);
5809a1ae
GR		 4726 /*
4727 * If SR-IOV enabled then wait a bit before bringing the adapter
4728 * back up to give the VFs time to respond to the reset. The
4729 * two second wait is based upon the watchdog timer cycle in
4730 * the VF driver.
4731 */
4732 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4733 msleep(2000);
d4f80882
AV		 4734 ixgbe_up(adapter);
4735 clear_bit(__IXGBE_RESETTING, &adapter->state);
4736}
4737
c7ccde0f 4738void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4739{
4740 /* hardware has been reset, we need to reload some things */
4741 ixgbe_configure(adapter);
4742
c7ccde0f 4743 ixgbe_up_complete(adapter);
9a799d71
AK		 4744}
4745
4746void ixgbe_reset(struct ixgbe_adapter *adapter)
4747{
c44ade9e 4748 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4749 int err;
4750
b0483c8f
MR		 4751 if (ixgbe_removed(hw->hw_addr))
4752 return;
7086400d
AD		 4753 /* lock SFP init bit to prevent race conditions with the watchdog */
4754 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4755 usleep_range(1000, 2000);
4756
4757 /* clear all SFP and link config related flags while holding SFP_INIT */
4758 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4759 IXGBE_FLAG2_SFP_NEEDS_RESET);
4760 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4761
8ca783ab 4762 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4763 switch (err) {
4764 case 0:
4765 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4766 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4767 break;
4768 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4769 e_dev_err("master disable timed out\n");
da4dd0f7 4770 break;
794caeb2
PWJ		 4771 case IXGBE_ERR_EEPROM_VERSION:
4772 /* We are running on a pre-production device, log a warning */
849c4542 4773 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4774 "Please be aware there may be issues associated with "
849c4542
ET		 4775 "your hardware. If you are experiencing problems "
4776 "please contact your Intel or hardware "
4777 "representative who provided you with this "
4778 "hardware.\n");
794caeb2 4779 break;
da4dd0f7 4780 default:
849c4542 4781 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4782 }
9a799d71 4783
7086400d
AD		 4784 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4785
9a799d71 4786 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4787 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4788
4789 /* update SAN MAC vmdq pool selection */
4790 if (hw->mac.san_mac_rar_index)
4791 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4792
8fecf67c 4793 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4794 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4795}
4796
9a799d71
AK		 4797/**
4798 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4799 * @tx_ring: ring to be cleaned
4800 **/
b6ec895e 4801static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4802{
4803 struct ixgbe_tx_buffer *tx_buffer_info;
4804 unsigned long size;
b6ec895e 4805 u16 i;
9a799d71 4806
84418e3b
AD		 4807 /* ring already cleared, nothing to do */
4808 if (!tx_ring->tx_buffer_info)
4809 return;
9a799d71 4810
84418e3b 4811 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4812 for (i = 0; i < tx_ring->count; i++) {
4813 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4814 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4815 }
4816
dad8a3b3
JF		 4817 netdev_tx_reset_queue(txring_txq(tx_ring));
4818
9a799d71
AK		 4819 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4820 memset(tx_ring->tx_buffer_info, 0, size);
4821
4822 /* Zero out the descriptor ring */
4823 memset(tx_ring->desc, 0, tx_ring->size);
4824
4825 tx_ring->next_to_use = 0;
4826 tx_ring->next_to_clean = 0;
9a799d71
AK		 4827}
4828
4829/**
021230d4 4830 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4831 * @adapter: board private structure
4832 **/
021230d4 4833static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4834{
4835 int i;
4836
021230d4 4837 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4838 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4839}
4840
4841/**
021230d4 4842 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4843 * @adapter: board private structure
4844 **/
021230d4 4845static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4846{
4847 int i;
4848
021230d4 4849 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4850 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4851}
4852
e4911d57
AD		 4853static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4854{
b67bfe0d 4855 struct hlist_node *node2;
e4911d57
AD		 4856 struct ixgbe_fdir_filter *filter;
4857
4858 spin_lock(&adapter->fdir_perfect_lock);
4859
b67bfe0d 4860 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4861 &adapter->fdir_filter_list, fdir_node) {
4862 hlist_del(&filter->fdir_node);
4863 kfree(filter);
4864 }
4865 adapter->fdir_filter_count = 0;
4866
4867 spin_unlock(&adapter->fdir_perfect_lock);
4868}
4869
9a799d71
AK		 4870void ixgbe_down(struct ixgbe_adapter *adapter)
4871{
4872 struct net_device *netdev = adapter->netdev;
7f821875 4873 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4874 struct net_device *upper;
4875 struct list_head *iter;
9a799d71 4876 u32 rxctrl;
bf29ee6c 4877 int i;
9a799d71
AK		 4878
4879 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 4880 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4881 return; /* do nothing if already down */
9a799d71
AK		 4882
4883 /* disable receives */
7f821875
JB		 4884 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4885 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4886
2d39d576
YZ		 4887 /* disable all enabled rx queues */
4888 for (i = 0; i < adapter->num_rx_queues; i++)
4889 /* this call also flushes the previous write */
4890 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4891
032b4325 4892 usleep_range(10000, 20000);
9a799d71 4893
7f821875
JB		 4894 netif_tx_stop_all_queues(netdev);
4895
7086400d 4896 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4897 netif_carrier_off(netdev);
4898 netif_tx_disable(netdev);
4899
2a47fa45
JF		 4900 /* disable any upper devices */
4901 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4902 if (netif_is_macvlan(upper)) {
4903 struct macvlan_dev *vlan = netdev_priv(upper);
4904
4905 if (vlan->fwd_priv) {
4906 netif_tx_stop_all_queues(upper);
4907 netif_carrier_off(upper);
4908 netif_tx_disable(upper);
4909 }
4910 }
4911 }
4912
c0dfb90e
JF		 4913 ixgbe_irq_disable(adapter);
4914
4915 ixgbe_napi_disable_all(adapter);
4916
d034acf1
AD		 4917 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4918 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4919 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4920
4921 del_timer_sync(&adapter->service_timer);
4922
34cecbbf 4923 if (adapter->num_vfs) {
8e34d1aa
AD		 4924 /* Clear EITR Select mapping */
4925 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4926
4927 /* Mark all the VFs as inactive */
4928 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4929 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4930
34cecbbf
AD		 4931 /* ping all the active vfs to let them know we are going down */
4932 ixgbe_ping_all_vfs(adapter);
4933
4934 /* Disable all VFTE/VFRE TX/RX */
4935 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4936 }
4937
7f821875
JB		 4938 /* disable transmits in the hardware now that interrupts are off */
4939 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4940 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4941 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4942 }
34cecbbf
AD		 4943
4944 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4945 switch (hw->mac.type) {
4946 case ixgbe_mac_82599EB:
b93a2226 4947 case ixgbe_mac_X540:
88512539 4948 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4949 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4950 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4951 break;
4952 default:
4953 break;
4954 }
7f821875 4955
6f4a0e45
PL		 4956 if (!pci_channel_offline(adapter->pdev))
4957 ixgbe_reset(adapter);
c6ecf39a 4958
ec74a471
ET		 4959 /* power down the optics for 82599 SFP+ fiber */
4960 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4961 hw->mac.ops.disable_tx_laser(hw);
4962
9a799d71
AK		 4963 ixgbe_clean_all_tx_rings(adapter);
4964 ixgbe_clean_all_rx_rings(adapter);
4965
5dd2d332 4966#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4967 /* since we reset the hardware DCA settings were cleared */
e35ec126 4968 ixgbe_setup_dca(adapter);
96b0e0f6 4969#endif
9a799d71
AK		 4970}
4971
9a799d71
AK		 4972/**
4973 * ixgbe_tx_timeout - Respond to a Tx Hang
4974 * @netdev: network interface device structure
4975 **/
4976static void ixgbe_tx_timeout(struct net_device *netdev)
4977{
4978 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4979
4980 /* Do the reset outside of interrupt context */
c83c6cbd 4981 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4982}
4983
9a799d71
AK		 4984/**
4985 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4986 * @adapter: board private structure to initialize
4987 *
4988 * ixgbe_sw_init initializes the Adapter private data structure.
4989 * Fields are initialized based on PCI device information and
4990 * OS network device settings (MTU size).
4991 **/
9f9a12f8 4992static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4993{
4994 struct ixgbe_hw *hw = &adapter->hw;
4995 struct pci_dev *pdev = adapter->pdev;
d3cb9869 4996 unsigned int rss, fdir;
cb6d0f5e 4997 u32 fwsm;
7a6b6f51 4998#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4999 int j;
5000 struct tc_configuration *tc;
5001#endif
021230d4 5002
c44ade9e
JB		 5003 /* PCI config space info */
5004
5005 hw->vendor_id = pdev->vendor;
5006 hw->device_id = pdev->device;
5007 hw->revision_id = pdev->revision;
5008 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5009 hw->subsystem_device_id = pdev->subsystem_device;
5010
8fc3bb6d 5011 /* Set common capability flags and settings */
3ed69d7e 5012 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5013 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5014 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5015 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5016 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5017 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5018 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5019 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5020 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5021#ifdef CONFIG_IXGBE_DCA
5022 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5023#endif
5024#ifdef IXGBE_FCOE
5025 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5026 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5027#ifdef CONFIG_IXGBE_DCB
5028 /* Default traffic class to use for FCoE */
5029 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5030#endif /* CONFIG_IXGBE_DCB */
5031#endif /* IXGBE_FCOE */
5032
5033 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5034 switch (hw->mac.type) {
5035 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5036 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5037 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5038
bf069c97
DS		 5039 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5040 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5041
49c7ffbe 5042 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5043 adapter->ring_feature[RING_F_FDIR].limit = 0;
5044 adapter->atr_sample_rate = 0;
5045 adapter->fdir_pballoc = 0;
5046#ifdef IXGBE_FCOE
5047 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5048 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5049#ifdef CONFIG_IXGBE_DCB
5050 adapter->fcoe.up = 0;
5051#endif /* IXGBE_DCB */
5052#endif /* IXGBE_FCOE */
5053 break;
5054 case ixgbe_mac_82599EB:
5055 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5056 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5057 break;
b93a2226 5058 case ixgbe_mac_X540:
cb6d0f5e
JK		 5059 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5060 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5061 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 5062 break;
5063 default:
5064 break;
f8212f97 5065 }
2f90b865 5066
7c8ae65a
AD		 5067#ifdef IXGBE_FCOE
5068 /* FCoE support exists, always init the FCoE lock */
5069 spin_lock_init(&adapter->fcoe.lock);
5070
5071#endif
1fc5f038
AD		 5072 /* n-tuple support exists, always init our spinlock */
5073 spin_lock_init(&adapter->fdir_perfect_lock);
5074
7a6b6f51 5075#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5076 switch (hw->mac.type) {
5077 case ixgbe_mac_X540:
5078 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5079 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5080 break;
5081 default:
5082 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5083 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5084 break;
5085 }
5086
2f90b865
AD		 5087 /* Configure DCB traffic classes */
5088 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5089 tc = &adapter->dcb_cfg.tc_config[j];
5090 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5091 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5092 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5093 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5094 tc->dcb_pfc = pfc_disabled;
5095 }
4de2a022
JF		 5096
5097 /* Initialize default user to priority mapping, UPx->TC0 */
5098 tc = &adapter->dcb_cfg.tc_config[0];
5099 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5100 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5101
2f90b865
AD		 5102 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5103 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5104 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5105 adapter->dcb_set_bitmap = 0x00;
3032309b 5106 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5107 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5108 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5109
5110#endif
9a799d71
AK		 5111
5112 /* default flow control settings */
cd7664f6 5113 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5114 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5115 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5116 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5117 hw->fc.send_xon = true;
73d80953 5118 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5119
99d74487 5120#ifdef CONFIG_PCI_IOV
170e8543
JK		 5121 if (max_vfs > 0)
5122 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5123
99d74487 5124 /* assign number of SR-IOV VFs */
170e8543 5125 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5126 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5127 adapter->num_vfs = 0;
5128 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5129 } else {
5130 adapter->num_vfs = max_vfs;
5131 }
5132 }
5133#endif /* CONFIG_PCI_IOV */
99d74487 5134
30efa5a3 5135 /* enable itr by default in dynamic mode */
f7554a2b 5136 adapter->rx_itr_setting = 1;
f7554a2b 5137 adapter->tx_itr_setting = 1;
30efa5a3 5138
30efa5a3
JB		 5139 /* set default ring sizes */
5140 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5141 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5142
bd198058 5143 /* set default work limits */
59224555 5144 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5145
9a799d71 5146 /* initialize eeprom parameters */
c44ade9e 5147 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5148 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5149 return -EIO;
5150 }
5151
2a47fa45
JF		 5152 /* PF holds first pool slot */
5153 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5154 set_bit(__IXGBE_DOWN, &adapter->state);
5155
5156 return 0;
5157}
5158
5159/**
5160 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5161 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5162 *
5163 * Return 0 on success, negative on failure
5164 **/
b6ec895e 5165int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5166{
b6ec895e 5167 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5168 int orig_node = dev_to_node(dev);
5169 int numa_node = -1;
9a799d71
AK		 5170 int size;
5171
3a581073 5172 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5173
5174 if (tx_ring->q_vector)
5175 numa_node = tx_ring->q_vector->numa_node;
5176
5177 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5178 if (!tx_ring->tx_buffer_info)
89bf67f1 5179 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5180 if (!tx_ring->tx_buffer_info)
5181 goto err;
9a799d71 5182
827da44c
JS		 5183 u64_stats_init(&tx_ring->syncp);
5184
9a799d71 5185 /* round up to nearest 4K */
12207e49 5186 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5187 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5188
de88eeeb
AD		 5189 set_dev_node(dev, numa_node);
5190 tx_ring->desc = dma_alloc_coherent(dev,
5191 tx_ring->size,
5192 &tx_ring->dma,
5193 GFP_KERNEL);
5194 set_dev_node(dev, orig_node);
5195 if (!tx_ring->desc)
5196 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5197 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5198 if (!tx_ring->desc)
5199 goto err;
9a799d71 5200
3a581073
JB		 5201 tx_ring->next_to_use = 0;
5202 tx_ring->next_to_clean = 0;
9a799d71 5203 return 0;
e01c31a5
JB		 5204
5205err:
5206 vfree(tx_ring->tx_buffer_info);
5207 tx_ring->tx_buffer_info = NULL;
b6ec895e 5208 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5209 return -ENOMEM;
9a799d71
AK		 5210}
5211
69888674
AD		 5212/**
5213 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5214 * @adapter: board private structure
5215 *
5216 * If this function returns with an error, then it's possible one or
5217 * more of the rings is populated (while the rest are not). It is the
5218 * callers duty to clean those orphaned rings.
5219 *
5220 * Return 0 on success, negative on failure
5221 **/
5222static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5223{
5224 int i, err = 0;
5225
5226 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5227 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5228 if (!err)
5229 continue;
de3d5b94 5230
396e799c 5231 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5232 goto err_setup_tx;
69888674
AD		 5233 }
5234
de3d5b94
AD		 5235 return 0;
5236err_setup_tx:
5237 /* rewind the index freeing the rings as we go */
5238 while (i--)
5239 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5240 return err;
5241}
5242
9a799d71
AK		 5243/**
5244 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5245 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5246 *
5247 * Returns 0 on success, negative on failure
5248 **/
b6ec895e 5249int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5250{
b6ec895e 5251 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5252 int orig_node = dev_to_node(dev);
5253 int numa_node = -1;
021230d4 5254 int size;
9a799d71 5255
3a581073 5256 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5257
5258 if (rx_ring->q_vector)
5259 numa_node = rx_ring->q_vector->numa_node;
5260
5261 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5262 if (!rx_ring->rx_buffer_info)
89bf67f1 5263 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5264 if (!rx_ring->rx_buffer_info)
5265 goto err;
9a799d71 5266
827da44c
JS		 5267 u64_stats_init(&rx_ring->syncp);
5268
9a799d71 5269 /* Round up to nearest 4K */
3a581073
JB		 5270 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5271 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5272
de88eeeb
AD		 5273 set_dev_node(dev, numa_node);
5274 rx_ring->desc = dma_alloc_coherent(dev,
5275 rx_ring->size,
5276 &rx_ring->dma,
5277 GFP_KERNEL);
5278 set_dev_node(dev, orig_node);
5279 if (!rx_ring->desc)
5280 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5281 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5282 if (!rx_ring->desc)
5283 goto err;
9a799d71 5284
3a581073
JB		 5285 rx_ring->next_to_clean = 0;
5286 rx_ring->next_to_use = 0;
9a799d71
AK		 5287
5288 return 0;
b6ec895e
AD		 5289err:
5290 vfree(rx_ring->rx_buffer_info);
5291 rx_ring->rx_buffer_info = NULL;
5292 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5293 return -ENOMEM;
9a799d71
AK		 5294}
5295
69888674
AD		 5296/**
5297 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5298 * @adapter: board private structure
5299 *
5300 * If this function returns with an error, then it's possible one or
5301 * more of the rings is populated (while the rest are not). It is the
5302 * callers duty to clean those orphaned rings.
5303 *
5304 * Return 0 on success, negative on failure
5305 **/
69888674
AD		 5306static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5307{
5308 int i, err = 0;
5309
5310 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5311 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5312 if (!err)
5313 continue;
de3d5b94 5314
396e799c 5315 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5316 goto err_setup_rx;
69888674
AD		 5317 }
5318
7c8ae65a
AD		 5319#ifdef IXGBE_FCOE
5320 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5321 if (!err)
5322#endif
5323 return 0;
de3d5b94
AD		 5324err_setup_rx:
5325 /* rewind the index freeing the rings as we go */
5326 while (i--)
5327 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5328 return err;
5329}
5330
9a799d71
AK		 5331/**
5332 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5333 * @tx_ring: Tx descriptor ring for a specific queue
5334 *
5335 * Free all transmit software resources
5336 **/
b6ec895e 5337void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5338{
b6ec895e 5339 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5340
5341 vfree(tx_ring->tx_buffer_info);
5342 tx_ring->tx_buffer_info = NULL;
5343
b6ec895e
AD		 5344 /* if not set, then don't free */
5345 if (!tx_ring->desc)
5346 return;
5347
5348 dma_free_coherent(tx_ring->dev, tx_ring->size,
5349 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5350
5351 tx_ring->desc = NULL;
5352}
5353
5354/**
5355 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5356 * @adapter: board private structure
5357 *
5358 * Free all transmit software resources
5359 **/
5360static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5361{
5362 int i;
5363
5364 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5365 if (adapter->tx_ring[i]->desc)
b6ec895e 5366 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5367}
5368
5369/**
b4617240 5370 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5371 * @rx_ring: ring to clean the resources from
5372 *
5373 * Free all receive software resources
5374 **/
b6ec895e 5375void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5376{
b6ec895e 5377 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5378
5379 vfree(rx_ring->rx_buffer_info);
5380 rx_ring->rx_buffer_info = NULL;
5381
b6ec895e
AD		 5382 /* if not set, then don't free */
5383 if (!rx_ring->desc)
5384 return;
5385
5386 dma_free_coherent(rx_ring->dev, rx_ring->size,
5387 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5388
5389 rx_ring->desc = NULL;
5390}
5391
5392/**
5393 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5394 * @adapter: board private structure
5395 *
5396 * Free all receive software resources
5397 **/
5398static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5399{
5400 int i;
5401
7c8ae65a
AD		 5402#ifdef IXGBE_FCOE
5403 ixgbe_free_fcoe_ddp_resources(adapter);
5404
5405#endif
9a799d71 5406 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5407 if (adapter->rx_ring[i]->desc)
b6ec895e 5408 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5409}
5410
9a799d71
AK		 5411/**
5412 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5413 * @netdev: network interface device structure
5414 * @new_mtu: new value for maximum frame size
5415 *
5416 * Returns 0 on success, negative on failure
5417 **/
5418static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5419{
5420 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5421 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5422
42c783c5 5423 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5424 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5425 return -EINVAL;
5426
5427 /*
872844dd
AD		 5428 * For 82599EB we cannot allow legacy VFs to enable their receive
5429 * paths when MTU greater than 1500 is configured. So display a
5430 * warning that legacy VFs will be disabled.
655309e9
AD		 5431 */
5432 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5433 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5434 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5435 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5436
396e799c 5437 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5438
021230d4 5439 /* must set new MTU before calling down or up */
9a799d71
AK		 5440 netdev->mtu = new_mtu;
5441
d4f80882
AV		 5442 if (netif_running(netdev))
5443 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5444
5445 return 0;
5446}
5447
5448/**
5449 * ixgbe_open - Called when a network interface is made active
5450 * @netdev: network interface device structure
5451 *
5452 * Returns 0 on success, negative value on failure
5453 *
5454 * The open entry point is called when a network interface is made
5455 * active by the system (IFF_UP). At this point all resources needed
5456 * for transmit and receive operations are allocated, the interrupt
5457 * handler is registered with the OS, the watchdog timer is started,
5458 * and the stack is notified that the interface is ready.
5459 **/
5460static int ixgbe_open(struct net_device *netdev)
5461{
5462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5463 int err, queues;
4bebfaa5
AK		 5464
5465 /* disallow open during test */
5466 if (test_bit(__IXGBE_TESTING, &adapter->state))
5467 return -EBUSY;
9a799d71 5468
54386467
JB		 5469 netif_carrier_off(netdev);
5470
9a799d71
AK		 5471 /* allocate transmit descriptors */
5472 err = ixgbe_setup_all_tx_resources(adapter);
5473 if (err)
5474 goto err_setup_tx;
5475
9a799d71
AK		 5476 /* allocate receive descriptors */
5477 err = ixgbe_setup_all_rx_resources(adapter);
5478 if (err)
5479 goto err_setup_rx;
5480
5481 ixgbe_configure(adapter);
5482
021230d4 5483 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5484 if (err)
5485 goto err_req_irq;
5486
ac802f5d 5487 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5488 if (adapter->num_rx_pools > 1)
5489 queues = adapter->num_rx_queues_per_pool;
5490 else
5491 queues = adapter->num_tx_queues;
5492
5493 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5494 if (err)
5495 goto err_set_queues;
5496
2a47fa45
JF		 5497 if (adapter->num_rx_pools > 1 &&
5498 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5499 queues = IXGBE_MAX_L2A_QUEUES;
5500 else
5501 queues = adapter->num_rx_queues;
5502 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5503 if (err)
5504 goto err_set_queues;
5505
1a71ab24 5506 ixgbe_ptp_init(adapter);
1a71ab24 5507
c7ccde0f 5508 ixgbe_up_complete(adapter);
9a799d71
AK		 5509
5510 return 0;
5511
ac802f5d
AD		 5512err_set_queues:
5513 ixgbe_free_irq(adapter);
9a799d71 5514err_req_irq:
a20a1199 5515 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5516err_setup_rx:
a20a1199 5517 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5518err_setup_tx:
9a799d71
AK		 5519 ixgbe_reset(adapter);
5520
5521 return err;
5522}
5523
5524/**
5525 * ixgbe_close - Disables a network interface
5526 * @netdev: network interface device structure
5527 *
5528 * Returns 0, this is not allowed to fail
5529 *
5530 * The close entry point is called when an interface is de-activated
5531 * by the OS. The hardware is still under the drivers control, but
5532 * needs to be disabled. A global MAC reset is issued to stop the
5533 * hardware, and all transmit and receive resources are freed.
5534 **/
5535static int ixgbe_close(struct net_device *netdev)
5536{
5537 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5538
1a71ab24 5539 ixgbe_ptp_stop(adapter);
1a71ab24 5540
9a799d71
AK		 5541 ixgbe_down(adapter);
5542 ixgbe_free_irq(adapter);
5543
e4911d57
AD		 5544 ixgbe_fdir_filter_exit(adapter);
5545
9a799d71
AK		 5546 ixgbe_free_all_tx_resources(adapter);
5547 ixgbe_free_all_rx_resources(adapter);
5548
5eba3699 5549 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5550
5551 return 0;
5552}
5553
b3c8b4ba
AD		 5554#ifdef CONFIG_PM
5555static int ixgbe_resume(struct pci_dev *pdev)
5556{
c60fbb00
AD		 5557 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5558 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5559 u32 err;
5560
0391bbe3 5561 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5562 pci_set_power_state(pdev, PCI_D0);
5563 pci_restore_state(pdev);
656ab817
DS		 5564 /*
5565 * pci_restore_state clears dev->state_saved so call
5566 * pci_save_state to restore it.
5567 */
5568 pci_save_state(pdev);
9ce77666 5569
5570 err = pci_enable_device_mem(pdev);
b3c8b4ba 5571 if (err) {
849c4542 5572 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5573 return err;
5574 }
5575 pci_set_master(pdev);
5576
dd4d8ca6 5577 pci_wake_from_d3(pdev, false);
b3c8b4ba 5578
b3c8b4ba
AD		 5579 ixgbe_reset(adapter);
5580
495dce12
WJP		 5581 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5582
ac802f5d
AD		 5583 rtnl_lock();
5584 err = ixgbe_init_interrupt_scheme(adapter);
5585 if (!err && netif_running(netdev))
c60fbb00 5586 err = ixgbe_open(netdev);
ac802f5d
AD		 5587
5588 rtnl_unlock();
5589
5590 if (err)
5591 return err;
b3c8b4ba
AD		 5592
5593 netif_device_attach(netdev);
5594
5595 return 0;
5596}
b3c8b4ba 5597#endif /* CONFIG_PM */
9d8d05ae
RW		 5598
5599static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5600{
c60fbb00
AD		 5601 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5602 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5603 struct ixgbe_hw *hw = &adapter->hw;
5604 u32 ctrl, fctrl;
5605 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5606#ifdef CONFIG_PM
5607 int retval = 0;
5608#endif
5609
5610 netif_device_detach(netdev);
5611
499ab5cc 5612 rtnl_lock();
b3c8b4ba
AD		 5613 if (netif_running(netdev)) {
5614 ixgbe_down(adapter);
5615 ixgbe_free_irq(adapter);
5616 ixgbe_free_all_tx_resources(adapter);
5617 ixgbe_free_all_rx_resources(adapter);
5618 }
499ab5cc 5619 rtnl_unlock();
b3c8b4ba 5620
5f5ae6fc
AD		 5621 ixgbe_clear_interrupt_scheme(adapter);
5622
b3c8b4ba
AD		 5623#ifdef CONFIG_PM
5624 retval = pci_save_state(pdev);
5625 if (retval)
5626 return retval;
4df10466 5627
b3c8b4ba 5628#endif
f4f1040a
JK		 5629 if (hw->mac.ops.stop_link_on_d3)
5630 hw->mac.ops.stop_link_on_d3(hw);
5631
e8e26350
PW		 5632 if (wufc) {
5633 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5634
ec74a471
ET		 5635 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5636 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5637 hw->mac.ops.enable_tx_laser(hw);
5638
e8e26350
PW		 5639 /* turn on all-multi mode if wake on multicast is enabled */
5640 if (wufc & IXGBE_WUFC_MC) {
5641 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5642 fctrl |= IXGBE_FCTRL_MPE;
5643 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5644 }
5645
5646 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5647 ctrl |= IXGBE_CTRL_GIO_DIS;
5648 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5649
5650 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5651 } else {
5652 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5653 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5654 }
5655
bd508178
AD		 5656 switch (hw->mac.type) {
5657 case ixgbe_mac_82598EB:
dd4d8ca6 5658 pci_wake_from_d3(pdev, false);
bd508178
AD		 5659 break;
5660 case ixgbe_mac_82599EB:
b93a2226 5661 case ixgbe_mac_X540:
bd508178
AD		 5662 pci_wake_from_d3(pdev, !!wufc);
5663 break;
5664 default:
5665 break;
5666 }
b3c8b4ba 5667
9d8d05ae
RW		 5668 *enable_wake = !!wufc;
5669
b3c8b4ba
AD		 5670 ixgbe_release_hw_control(adapter);
5671
5672 pci_disable_device(pdev);
5673
9d8d05ae
RW		 5674 return 0;
5675}
5676
5677#ifdef CONFIG_PM
5678static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5679{
5680 int retval;
5681 bool wake;
5682
5683 retval = __ixgbe_shutdown(pdev, &wake);
5684 if (retval)
5685 return retval;
5686
5687 if (wake) {
5688 pci_prepare_to_sleep(pdev);
5689 } else {
5690 pci_wake_from_d3(pdev, false);
5691 pci_set_power_state(pdev, PCI_D3hot);
5692 }
b3c8b4ba
AD		 5693
5694 return 0;
5695}
9d8d05ae 5696#endif /* CONFIG_PM */
b3c8b4ba
AD		 5697
5698static void ixgbe_shutdown(struct pci_dev *pdev)
5699{
9d8d05ae
RW		 5700 bool wake;
5701
5702 __ixgbe_shutdown(pdev, &wake);
5703
5704 if (system_state == SYSTEM_POWER_OFF) {
5705 pci_wake_from_d3(pdev, wake);
5706 pci_set_power_state(pdev, PCI_D3hot);
5707 }
b3c8b4ba
AD		 5708}
5709
9a799d71
AK		 5710/**
5711 * ixgbe_update_stats - Update the board statistics counters.
5712 * @adapter: board private structure
5713 **/
5714void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5715{
2d86f139 5716 struct net_device *netdev = adapter->netdev;
9a799d71 5717 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5718 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5719 u64 total_mpc = 0;
5720 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5721 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5722 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5723 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5724
d08935c2
DS		 5725 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5726 test_bit(__IXGBE_RESETTING, &adapter->state))
5727 return;
5728
94b982b2 5729 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5730 u64 rsc_count = 0;
94b982b2 5731 u64 rsc_flush = 0;
94b982b2 5732 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5733 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5734 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5735 }
5736 adapter->rsc_total_count = rsc_count;
5737 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5738 }
5739
5b7da515
AD		 5740 for (i = 0; i < adapter->num_rx_queues; i++) {
5741 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5742 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5743 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5744 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5745 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5746 bytes += rx_ring->stats.bytes;
5747 packets += rx_ring->stats.packets;
5748 }
5749 adapter->non_eop_descs = non_eop_descs;
5750 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5751 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5752 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5753 netdev->stats.rx_bytes = bytes;
5754 netdev->stats.rx_packets = packets;
5755
5756 bytes = 0;
5757 packets = 0;
7ca3bc58 5758 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5759 for (i = 0; i < adapter->num_tx_queues; i++) {
5760 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5761 restart_queue += tx_ring->tx_stats.restart_queue;
5762 tx_busy += tx_ring->tx_stats.tx_busy;
5763 bytes += tx_ring->stats.bytes;
5764 packets += tx_ring->stats.packets;
5765 }
eb985f09 5766 adapter->restart_queue = restart_queue;
5b7da515
AD		 5767 adapter->tx_busy = tx_busy;
5768 netdev->stats.tx_bytes = bytes;
5769 netdev->stats.tx_packets = packets;
7ca3bc58 5770
7ca647bd 5771 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5772
5773 /* 8 register reads */
6f11eef7
AV		 5774 for (i = 0; i < 8; i++) {
5775 /* for packet buffers not used, the register should read 0 */
5776 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5777 missed_rx += mpc;
7ca647bd
JP		 5778 hwstats->mpc[i] += mpc;
5779 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5780 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5781 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5782 switch (hw->mac.type) {
5783 case ixgbe_mac_82598EB:
1a70db4b
ET		 5784 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5785 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5786 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5787 hwstats->pxonrxc[i] +=
5788 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5789 break;
5790 case ixgbe_mac_82599EB:
b93a2226 5791 case ixgbe_mac_X540:
bd508178
AD		 5792 hwstats->pxonrxc[i] +=
5793 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5794 break;
5795 default:
5796 break;
e8e26350 5797 }
6f11eef7 5798 }
1a70db4b
ET		 5799
5800 /*16 register reads */
5801 for (i = 0; i < 16; i++) {
5802 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5803 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5804 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5805 (hw->mac.type == ixgbe_mac_X540)) {
5806 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5807 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5808 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5809 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5810 }
5811 }
5812
7ca647bd 5813 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5814 /* work around hardware counting issue */
7ca647bd 5815 hwstats->gprc -= missed_rx;
6f11eef7 5816
c84d324c
JF		 5817 ixgbe_update_xoff_received(adapter);
5818
6f11eef7 5819 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5820 switch (hw->mac.type) {
5821 case ixgbe_mac_82598EB:
5822 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5823 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5824 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5825 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5826 break;
b93a2226 5827 case ixgbe_mac_X540:
58f6bcf9
ET		 5828 /* OS2BMC stats are X540 only*/
5829 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5830 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5831 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5832 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5833 case ixgbe_mac_82599EB:
a4d4f629
AD		 5834 for (i = 0; i < 16; i++)
5835 adapter->hw_rx_no_dma_resources +=
5836 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5837 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5838 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5839 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5840 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5841 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5842 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5843 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5844 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5845 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5846#ifdef IXGBE_FCOE
7ca647bd
JP		 5847 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5848 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5849 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5850 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5851 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5852 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5853 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5854 if (adapter->fcoe.ddp_pool) {
5855 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5856 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5857 unsigned int cpu;
5858 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5859 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5860 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5861 noddp += ddp_pool->noddp;
5862 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5863 }
5a1ee270
AD		 5864 hwstats->fcoe_noddp = noddp;
5865 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5866 }
6d45522c 5867#endif /* IXGBE_FCOE */
bd508178
AD		 5868 break;
5869 default:
5870 break;
e8e26350 5871 }
9a799d71 5872 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5873 hwstats->bprc += bprc;
5874 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5875 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5876 hwstats->mprc -= bprc;
5877 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5878 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5879 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5880 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5881 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5882 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5883 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5884 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5885 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5886 hwstats->lxontxc += lxon;
6f11eef7 5887 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5888 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5889 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5890 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5891 /*
5892 * 82598 errata - tx of flow control packets is included in tx counters
5893 */
5894 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5895 hwstats->gptc -= xon_off_tot;
5896 hwstats->mptc -= xon_off_tot;
5897 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5898 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5899 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5900 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5901 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5902 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5903 hwstats->ptc64 -= xon_off_tot;
5904 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5905 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5906 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5907 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5908 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5909 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5910
5911 /* Fill out the OS statistics structure */
7ca647bd 5912 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5913
5914 /* Rx Errors */
7ca647bd 5915 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5916 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5917 netdev->stats.rx_length_errors = hwstats->rlec;
5918 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5919 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5920}
5921
5922/**
d034acf1 5923 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5924 * @adapter: pointer to the device adapter structure
9a799d71 5925 **/
d034acf1 5926static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5927{
cf8280ee 5928 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5929 int i;
cf8280ee 5930
d034acf1
AD		 5931 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5932 return;
5933
5934 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5935
d034acf1 5936 /* if interface is down do nothing */
fe49f04a 5937 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5938 return;
5939
5940 /* do nothing if we are not using signature filters */
5941 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5942 return;
5943
5944 adapter->fdir_overflow++;
5945
93c52dd0
AD		 5946 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5947 for (i = 0; i < adapter->num_tx_queues; i++)
5948 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5949 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5950 /* re-enable flow director interrupts */
5951 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5952 } else {
5953 e_err(probe, "failed to finish FDIR re-initialization, "
5954 "ignored adding FDIR ATR filters\n");
5955 }
93c52dd0
AD		 5956}
5957
5958/**
5959 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5960 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5961 *
5962 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5963 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5964 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5965 * determine if a hang has occurred.
93c52dd0
AD		 5966 */
5967static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5968{
cf8280ee 5969 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5970 u64 eics = 0;
5971 int i;
cf8280ee 5972
09f40aed 5973 /* If we're down, removing or resetting, just bail */
93c52dd0 5974 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 5975 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 5976 test_bit(__IXGBE_RESETTING, &adapter->state))
5977 return;
22d5a71b 5978
93c52dd0
AD		 5979 /* Force detection of hung controller */
5980 if (netif_carrier_ok(adapter->netdev)) {
5981 for (i = 0; i < adapter->num_tx_queues; i++)
5982 set_check_for_tx_hang(adapter->tx_ring[i]);
5983 }
22d5a71b 5984
fe49f04a
AD		 5985 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5986 /*
5987 * for legacy and MSI interrupts don't set any bits
5988 * that are enabled for EIAM, because this operation
5989 * would set *both* EIMS and EICS for any bit in EIAM
5990 */
5991 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5992 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5993 } else {
5994 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5995 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5996 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5997 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5998 eics |= ((u64)1 << i);
5999 }
cf8280ee 6000 }
9a799d71 6001
93c52dd0 6002 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6003 ixgbe_irq_rearm_queues(adapter, eics);
6004
cf8280ee
JB		 6005}
6006
e8e26350 6007/**
93c52dd0 6008 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6009 * @adapter: pointer to the device adapter structure
6010 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6011 **/
93c52dd0 6012static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6013{
e8e26350 6014 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6015 u32 link_speed = adapter->link_speed;
6016 bool link_up = adapter->link_up;
041441d0 6017 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6018
93c52dd0
AD		 6019 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6020 return;
6021
6022 if (hw->mac.ops.check_link) {
6023 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6024 } else {
93c52dd0
AD		 6025 /* always assume link is up, if no check link function */
6026 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6027 link_up = true;
c4cf55e5 6028 }
041441d0
AD		 6029
6030 if (adapter->ixgbe_ieee_pfc)
6031 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6032
3ebe8fde 6033 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6034 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6035 ixgbe_set_rx_drop_en(adapter);
6036 }
93c52dd0
AD		 6037
6038 if (link_up ||
6039 time_after(jiffies, (adapter->link_check_timeout +
6040 IXGBE_TRY_LINK_TIMEOUT))) {
6041 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6042 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6043 IXGBE_WRITE_FLUSH(hw);
6044 }
6045
6046 adapter->link_up = link_up;
6047 adapter->link_speed = link_speed;
e8e26350
PW		 6048}
6049
107d3018
AD		 6050static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6051{
6052#ifdef CONFIG_IXGBE_DCB
6053 struct net_device *netdev = adapter->netdev;
6054 struct dcb_app app = {
6055 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6056 .protocol = 0,
6057 };
6058 u8 up = 0;
6059
6060 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6061 up = dcb_ieee_getapp_mask(netdev, &app);
6062
6063 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6064#endif
6065}
6066
e8e26350 6067/**
93c52dd0
AD		 6068 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6069 * print link up message
49ce9c2c 6070 * @adapter: pointer to the device adapter structure
e8e26350 6071 **/
93c52dd0 6072static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6073{
93c52dd0 6074 struct net_device *netdev = adapter->netdev;
e8e26350 6075 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6076 u32 link_speed = adapter->link_speed;
6077 bool flow_rx, flow_tx;
e8e26350 6078
93c52dd0
AD		 6079 /* only continue if link was previously down */
6080 if (netif_carrier_ok(netdev))
a985b6c3 6081 return;
63d6e1d8 6082
93c52dd0 6083 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6084
93c52dd0
AD		 6085 switch (hw->mac.type) {
6086 case ixgbe_mac_82598EB: {
6087 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6088 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6089 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6090 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6091 }
6092 break;
6093 case ixgbe_mac_X540:
6094 case ixgbe_mac_82599EB: {
6095 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6096 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6097 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6098 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6099 }
6100 break;
6101 default:
6102 flow_tx = false;
6103 flow_rx = false;
6104 break;
e8e26350 6105 }
3a6a4eda 6106
6cb562d6
JK		 6107 adapter->last_rx_ptp_check = jiffies;
6108
8fecf67c 6109 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6110 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6111
93c52dd0
AD		 6112 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6113 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6114 "10 Gbps" :
6115 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6116 "1 Gbps" :
6117 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6118 "100 Mbps" :
6119 "unknown speed"))),
6120 ((flow_rx && flow_tx) ? "RX/TX" :
6121 (flow_rx ? "RX" :
6122 (flow_tx ? "TX" : "None"))));
e8e26350 6123
93c52dd0 6124 netif_carrier_on(netdev);
93c52dd0 6125 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6126
107d3018
AD		 6127 /* update the default user priority for VFs */
6128 ixgbe_update_default_up(adapter);
6129
befa2af7
AD		 6130 /* ping all the active vfs to let them know link has changed */
6131 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6132}
6133
c4cf55e5 6134/**
93c52dd0
AD		 6135 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6136 * print link down message
49ce9c2c 6137 * @adapter: pointer to the adapter structure
c4cf55e5 6138 **/
581330ba 6139static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6140{
cf8280ee 6141 struct net_device *netdev = adapter->netdev;
c4cf55e5 6142 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6143
93c52dd0
AD		 6144 adapter->link_up = false;
6145 adapter->link_speed = 0;
cf8280ee 6146
93c52dd0
AD		 6147 /* only continue if link was up previously */
6148 if (!netif_carrier_ok(netdev))
6149 return;
264857b8 6150
93c52dd0
AD		 6151 /* poll for SFP+ cable when link is down */
6152 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6153 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6154
8fecf67c 6155 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6156 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6157
93c52dd0
AD		 6158 e_info(drv, "NIC Link is Down\n");
6159 netif_carrier_off(netdev);
befa2af7
AD		 6160
6161 /* ping all the active vfs to let them know link has changed */
6162 ixgbe_ping_all_vfs(adapter);
93c52dd0 6163}
e8e26350 6164
93c52dd0
AD		 6165/**
6166 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6167 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6168 **/
6169static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6170{
c4cf55e5 6171 int i;
93c52dd0 6172 int some_tx_pending = 0;
c4cf55e5 6173
93c52dd0 6174 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6175 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6176 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6177 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6178 some_tx_pending = 1;
6179 break;
6180 }
6181 }
6182
6183 if (some_tx_pending) {
6184 /* We've lost link, so the controller stops DMA,
6185 * but we've got queued Tx work that's never going
6186 * to get done, so reset controller to flush Tx.
6187 * (Do the reset outside of interrupt context).
6188 */
12ff3f3b 6189 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6190 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6191 }
c4cf55e5 6192 }
c4cf55e5
PWJ		 6193}
6194
a985b6c3
GR		 6195static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6196{
6197 u32 ssvpc;
6198
0584d999
GR		 6199 /* Do not perform spoof check for 82598 or if not in IOV mode */
6200 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6201 adapter->num_vfs == 0)
a985b6c3
GR		 6202 return;
6203
6204 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6205
6206 /*
6207 * ssvpc register is cleared on read, if zero then no
6208 * spoofed packets in the last interval.
6209 */
6210 if (!ssvpc)
6211 return;
6212
d6ea0754 6213 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6214}
6215
93c52dd0
AD		 6216/**
6217 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6218 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6219 **/
6220static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6221{
09f40aed 6222 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6223 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6224 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6225 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6226 return;
6227
6228 ixgbe_watchdog_update_link(adapter);
6229
6230 if (adapter->link_up)
6231 ixgbe_watchdog_link_is_up(adapter);
6232 else
6233 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6234
a985b6c3 6235 ixgbe_spoof_check(adapter);
9a799d71 6236 ixgbe_update_stats(adapter);
93c52dd0
AD		 6237
6238 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6239}
10eec955 6240
cf8280ee 6241/**
7086400d 6242 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6243 * @adapter: the ixgbe adapter structure
cf8280ee 6244 **/
7086400d 6245static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6246{
cf8280ee 6247 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6248 s32 err;
cf8280ee 6249
7086400d
AD		 6250 /* not searching for SFP so there is nothing to do here */
6251 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6252 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6253 return;
10eec955 6254
7086400d
AD		 6255 /* someone else is in init, wait until next service event */
6256 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6257 return;
cf8280ee 6258
7086400d
AD		 6259 err = hw->phy.ops.identify_sfp(hw);
6260 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6261 goto sfp_out;
264857b8 6262
7086400d
AD		 6263 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6264 /* If no cable is present, then we need to reset
6265 * the next time we find a good cable. */
6266 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6267 }
9a799d71 6268
7086400d
AD		 6269 /* exit on error */
6270 if (err)
6271 goto sfp_out;
e8e26350 6272
7086400d
AD		 6273 /* exit if reset not needed */
6274 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6275 goto sfp_out;
9a799d71 6276
7086400d 6277 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6278
7086400d
AD		 6279 /*
6280 * A module may be identified correctly, but the EEPROM may not have
6281 * support for that module. setup_sfp() will fail in that case, so
6282 * we should not allow that module to load.
6283 */
6284 if (hw->mac.type == ixgbe_mac_82598EB)
6285 err = hw->phy.ops.reset(hw);
6286 else
6287 err = hw->mac.ops.setup_sfp(hw);
6288
6289 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6290 goto sfp_out;
6291
6292 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6293 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6294
6295sfp_out:
6296 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6297
6298 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6299 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6300 e_dev_err("failed to initialize because an unsupported "
6301 "SFP+ module type was detected.\n");
6302 e_dev_err("Reload the driver after installing a "
6303 "supported module.\n");
6304 unregister_netdev(adapter->netdev);
bc59fcda 6305 }
7086400d 6306}
bc59fcda 6307
7086400d
AD		 6308/**
6309 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6310 * @adapter: the ixgbe adapter structure
7086400d
AD		 6311 **/
6312static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6313{
6314 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6315 u32 speed;
6316 bool autoneg = false;
7086400d
AD		 6317
6318 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6319 return;
6320
6321 /* someone else is in init, wait until next service event */
6322 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6323 return;
6324
6325 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6326
3d292265 6327 speed = hw->phy.autoneg_advertised;
ed33ff66 6328 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6329 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6330
6331 /* setup the highest link when no autoneg */
6332 if (!autoneg) {
6333 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6334 speed = IXGBE_LINK_SPEED_10GB_FULL;
6335 }
6336 }
6337
7086400d 6338 if (hw->mac.ops.setup_link)
fd0326f2 6339 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6340
6341 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6342 adapter->link_check_timeout = jiffies;
6343 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6344}
6345
83c61fa9
GR		 6346#ifdef CONFIG_PCI_IOV
6347static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6348{
6349 int vf;
6350 struct ixgbe_hw *hw = &adapter->hw;
6351 struct net_device *netdev = adapter->netdev;
6352 u32 gpc;
6353 u32 ciaa, ciad;
6354
6355 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6356 if (gpc) /* If incrementing then no need for the check below */
6357 return;
6358 /*
6359 * Check to see if a bad DMA write target from an errant or
6360 * malicious VF has caused a PCIe error. If so then we can
6361 * issue a VFLR to the offending VF(s) and then resume without
6362 * requesting a full slot reset.
6363 */
6364
6365 for (vf = 0; vf < adapter->num_vfs; vf++) {
6366 ciaa = (vf << 16) | 0x80000000;
6367 /* 32 bit read so align, we really want status at offset 6 */
6368 ciaa |= PCI_COMMAND;
6369 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6370 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6371 ciaa &= 0x7FFFFFFF;
6372 /* disable debug mode asap after reading data */
6373 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6374 /* Get the upper 16 bits which will be the PCI status reg */
6375 ciad >>= 16;
6376 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6377 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6378 /* Issue VFLR */
6379 ciaa = (vf << 16) | 0x80000000;
6380 ciaa |= 0xA8;
6381 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6382 ciad = 0x00008000; /* VFLR */
6383 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6384 ciaa &= 0x7FFFFFFF;
6385 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6386 }
6387 }
6388}
6389
6390#endif
7086400d
AD		 6391/**
6392 * ixgbe_service_timer - Timer Call-back
6393 * @data: pointer to adapter cast into an unsigned long
6394 **/
6395static void ixgbe_service_timer(unsigned long data)
6396{
6397 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6398 unsigned long next_event_offset;
83c61fa9 6399 bool ready = true;
7086400d 6400
6bb78cfb
AD		 6401 /* poll faster when waiting for link */
6402 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6403 next_event_offset = HZ / 10;
6404 else
6405 next_event_offset = HZ * 2;
83c61fa9 6406
6bb78cfb 6407#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6408 /*
6409 * don't bother with SR-IOV VF DMA hang check if there are
6410 * no VFs or the link is down
6411 */
6412 if (!adapter->num_vfs ||
6bb78cfb 6413 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6414 goto normal_timer_service;
83c61fa9
GR		 6415
6416 /* If we have VFs allocated then we must check for DMA hangs */
6417 ixgbe_check_for_bad_vf(adapter);
6418 next_event_offset = HZ / 50;
6419 adapter->timer_event_accumulator++;
6420
6bb78cfb 6421 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6422 adapter->timer_event_accumulator = 0;
7086400d 6423 else
6bb78cfb 6424 ready = false;
7086400d 6425
6bb78cfb 6426normal_timer_service:
83c61fa9 6427#endif
7086400d
AD		 6428 /* Reset the timer */
6429 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6430
83c61fa9
GR		 6431 if (ready)
6432 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6433}
6434
c83c6cbd
AD		 6435static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6436{
6437 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6438 return;
6439
6440 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6441
09f40aed 6442 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6443 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6444 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6445 test_bit(__IXGBE_RESETTING, &adapter->state))
6446 return;
6447
6448 ixgbe_dump(adapter);
6449 netdev_err(adapter->netdev, "Reset adapter\n");
6450 adapter->tx_timeout_count++;
6451
8f4c5c9f 6452 rtnl_lock();
c83c6cbd 6453 ixgbe_reinit_locked(adapter);
8f4c5c9f 6454 rtnl_unlock();
c83c6cbd
AD		 6455}
6456
7086400d
AD		 6457/**
6458 * ixgbe_service_task - manages and runs subtasks
6459 * @work: pointer to work_struct containing our data
6460 **/
6461static void ixgbe_service_task(struct work_struct *work)
6462{
6463 struct ixgbe_adapter *adapter = container_of(work,
6464 struct ixgbe_adapter,
6465 service_task);
b0483c8f
MR		 6466 if (ixgbe_removed(adapter->hw.hw_addr)) {
6467 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6468 rtnl_lock();
6469 ixgbe_down(adapter);
6470 rtnl_unlock();
6471 }
6472 ixgbe_service_event_complete(adapter);
6473 return;
6474 }
c83c6cbd 6475 ixgbe_reset_subtask(adapter);
7086400d
AD		 6476 ixgbe_sfp_detection_subtask(adapter);
6477 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6478 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6479 ixgbe_watchdog_subtask(adapter);
d034acf1 6480 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6481 ixgbe_check_hang_subtask(adapter);
891dc082 6482
8fecf67c 6483 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6484 ixgbe_ptp_overflow_check(adapter);
6485 ixgbe_ptp_rx_hang(adapter);
6486 }
7086400d
AD		 6487
6488 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6489}
6490
fd0db0ed
AD		 6491static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6492 struct ixgbe_tx_buffer *first,
244e27ad 6493 u8 *hdr_len)
897ab156 6494{
fd0db0ed 6495 struct sk_buff *skb = first->skb;
897ab156
AD		 6496 u32 vlan_macip_lens, type_tucmd;
6497 u32 mss_l4len_idx, l4len;
9a799d71 6498
8f4fbb9b
AD		 6499 if (skb->ip_summed != CHECKSUM_PARTIAL)
6500 return 0;
6501
897ab156
AD		 6502 if (!skb_is_gso(skb))
6503 return 0;
9a799d71 6504
897ab156 6505 if (skb_header_cloned(skb)) {
244e27ad 6506 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 6507 if (err)
6508 return err;
9a799d71 6509 }
9a799d71 6510
897ab156
AD		 6511 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6512 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6513
244e27ad 6514 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 6515 struct iphdr *iph = ip_hdr(skb);
6516 iph->tot_len = 0;
6517 iph->check = 0;
6518 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6519 iph->daddr, 0,
6520 IPPROTO_TCP,
6521 0);
6522 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6523 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6524 IXGBE_TX_FLAGS_CSUM |
6525 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6526 } else if (skb_is_gso_v6(skb)) {
6527 ipv6_hdr(skb)->payload_len = 0;
6528 tcp_hdr(skb)->check =
6529 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6530 &ipv6_hdr(skb)->daddr,
6531 0, IPPROTO_TCP, 0);
244e27ad
AD		 6532 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6533 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6534 }
6535
091a6246 6536 /* compute header lengths */
897ab156
AD		 6537 l4len = tcp_hdrlen(skb);
6538 *hdr_len = skb_transport_offset(skb) + l4len;
6539
091a6246
AD		 6540 /* update gso size and bytecount with header size */
6541 first->gso_segs = skb_shinfo(skb)->gso_segs;
6542 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6543
c44f5f51 6544 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6545 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6546 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6547
6548 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6549 vlan_macip_lens = skb_network_header_len(skb);
6550 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6551 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6552
6553 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6554 mss_l4len_idx);
897ab156
AD		 6555
6556 return 1;
6557}
6558
244e27ad
AD		 6559static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6560 struct ixgbe_tx_buffer *first)
7ca647bd 6561{
fd0db0ed 6562 struct sk_buff *skb = first->skb;
897ab156
AD		 6563 u32 vlan_macip_lens = 0;
6564 u32 mss_l4len_idx = 0;
6565 u32 type_tucmd = 0;
7ca647bd 6566
897ab156 6567 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6568 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6569 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6570 return;
897ab156
AD		 6571 } else {
6572 u8 l4_hdr = 0;
244e27ad 6573 switch (first->protocol) {
897ab156
AD		 6574 case __constant_htons(ETH_P_IP):
6575 vlan_macip_lens |= skb_network_header_len(skb);
6576 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6577 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6578 break;
897ab156
AD		 6579 case __constant_htons(ETH_P_IPV6):
6580 vlan_macip_lens |= skb_network_header_len(skb);
6581 l4_hdr = ipv6_hdr(skb)->nexthdr;
6582 break;
6583 default:
6584 if (unlikely(net_ratelimit())) {
6585 dev_warn(tx_ring->dev,
6586 "partial checksum but proto=%x!\n",
244e27ad 6587 first->protocol);
897ab156 6588 }
7ca647bd
JP		 6589 break;
6590 }
897ab156
AD		 6591
6592 switch (l4_hdr) {
7ca647bd 6593 case IPPROTO_TCP:
897ab156
AD		 6594 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6595 mss_l4len_idx = tcp_hdrlen(skb) <<
6596 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6597 break;
6598 case IPPROTO_SCTP:
897ab156
AD		 6599 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6600 mss_l4len_idx = sizeof(struct sctphdr) <<
6601 IXGBE_ADVTXD_L4LEN_SHIFT;
6602 break;
6603 case IPPROTO_UDP:
6604 mss_l4len_idx = sizeof(struct udphdr) <<
6605 IXGBE_ADVTXD_L4LEN_SHIFT;
6606 break;
6607 default:
6608 if (unlikely(net_ratelimit())) {
6609 dev_warn(tx_ring->dev,
6610 "partial checksum but l4 proto=%x!\n",
244e27ad 6611 l4_hdr);
897ab156 6612 }
7ca647bd
JP		 6613 break;
6614 }
244e27ad
AD		 6615
6616 /* update TX checksum flag */
6617 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6618 }
6619
244e27ad 6620 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6621 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6622 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6623
897ab156
AD		 6624 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6625 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6626}
6627
472148c3
AD		 6628#define IXGBE_SET_FLAG(_input, _flag, _result) \
6629 ((_flag <= _result) ? \
6630 ((u32)(_input & _flag) * (_result / _flag)) : \
6631 ((u32)(_input & _flag) / (_flag / _result)))
6632
6633static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6634{
d3d00239 6635 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6636 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6637 IXGBE_ADVTXD_DCMD_DEXT |
6638 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6639
d3d00239 6640 /* set HW vlan bit if vlan is present */
472148c3
AD		 6641 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6642 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6643
d3d00239 6644 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6645 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6646 IXGBE_ADVTXD_DCMD_TSE);
6647
6648 /* set timestamp bit if present */
6649 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6650 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6651
62748b7b 6652 /* insert frame checksum */
472148c3 6653 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6654
d3d00239
AD		 6655 return cmd_type;
6656}
9a799d71 6657
729739b7
AD		 6658static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6659 u32 tx_flags, unsigned int paylen)
d3d00239 6660{
472148c3 6661 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6662
d3d00239 6663 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6664 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6665 IXGBE_TX_FLAGS_CSUM,
6666 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6667
93f5b3c1 6668 /* enble IPv4 checksum for TSO */
472148c3
AD		 6669 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6670 IXGBE_TX_FLAGS_IPV4,
6671 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6672
7f9643fd
AD		 6673 /*
6674 * Check Context must be set if Tx switch is enabled, which it
6675 * always is for case where virtual functions are running
6676 */
472148c3
AD		 6677 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6678 IXGBE_TX_FLAGS_CC,
6679 IXGBE_ADVTXD_CC);
7f9643fd 6680
472148c3 6681 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6682}
44df32c5 6683
d3d00239
AD		 6684#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6685 IXGBE_TXD_CMD_RS)
6686
6687static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6688 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6689 const u8 hdr_len)
6690{
fd0db0ed 6691 struct sk_buff *skb = first->skb;
729739b7 6692 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6693 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6694 struct skb_frag_struct *frag;
6695 dma_addr_t dma;
6696 unsigned int data_len, size;
244e27ad 6697 u32 tx_flags = first->tx_flags;
472148c3 6698 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6699 u16 i = tx_ring->next_to_use;
d3d00239 6700
729739b7
AD		 6701 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6702
ec718254
AD		 6703 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6704
6705 size = skb_headlen(skb);
6706 data_len = skb->data_len;
729739b7 6707
d3d00239
AD		 6708#ifdef IXGBE_FCOE
6709 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6710 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6711 size -= sizeof(struct fcoe_crc_eof) - data_len;
6712 data_len = 0;
729739b7
AD		 6713 } else {
6714 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6715 }
6716 }
44df32c5 6717
d3d00239 6718#endif
729739b7 6719 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6720
ec718254 6721 tx_buffer = first;
9a799d71 6722
ec718254
AD		 6723 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6724 if (dma_mapping_error(tx_ring->dev, dma))
6725 goto dma_error;
6726
6727 /* record length, and DMA address */
6728 dma_unmap_len_set(tx_buffer, len, size);
6729 dma_unmap_addr_set(tx_buffer, dma, dma);
6730
6731 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6732
729739b7 6733 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6734 tx_desc->read.cmd_type_len =
472148c3 6735 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6736
d3d00239 6737 i++;
729739b7 6738 tx_desc++;
d3d00239 6739 if (i == tx_ring->count) {
e4f74028 6740 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6741 i = 0;
6742 }
ec718254 6743 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6744
6745 dma += IXGBE_MAX_DATA_PER_TXD;
6746 size -= IXGBE_MAX_DATA_PER_TXD;
6747
6748 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6749 }
e5a43549 6750
729739b7
AD		 6751 if (likely(!data_len))
6752 break;
9a799d71 6753
472148c3 6754 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6755
729739b7
AD		 6756 i++;
6757 tx_desc++;
6758 if (i == tx_ring->count) {
6759 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6760 i = 0;
6761 }
ec718254 6762 tx_desc->read.olinfo_status = 0;
9a799d71 6763
d3d00239 6764#ifdef IXGBE_FCOE
9e903e08 6765 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6766#else
9e903e08 6767 size = skb_frag_size(frag);
d3d00239
AD		 6768#endif
6769 data_len -= size;
9a799d71 6770
729739b7
AD		 6771 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6772 DMA_TO_DEVICE);
9a799d71 6773
729739b7 6774 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6775 }
9a799d71 6776
729739b7 6777 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6778 cmd_type |= size | IXGBE_TXD_CMD;
6779 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6780
091a6246 6781 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6782
d3d00239
AD		 6783 /* set the timestamp */
6784 first->time_stamp = jiffies;
9a799d71
AK		 6785
6786 /*
729739b7
AD		 6787 * Force memory writes to complete before letting h/w know there
6788 * are new descriptors to fetch. (Only applicable for weak-ordered
6789 * memory model archs, such as IA-64).
6790 *
6791 * We also need this memory barrier to make certain all of the
6792 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6793 */
6794 wmb();
6795
d3d00239
AD		 6796 /* set next_to_watch value indicating a packet is present */
6797 first->next_to_watch = tx_desc;
6798
729739b7
AD		 6799 i++;
6800 if (i == tx_ring->count)
6801 i = 0;
6802
6803 tx_ring->next_to_use = i;
6804
d3d00239 6805 /* notify HW of packet */
84227bcd 6806 ixgbe_write_tail(tx_ring, i);
d3d00239
AD		 6807
6808 return;
6809dma_error:
729739b7 6810 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6811
6812 /* clear dma mappings for failed tx_buffer_info map */
6813 for (;;) {
729739b7
AD		 6814 tx_buffer = &tx_ring->tx_buffer_info[i];
6815 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6816 if (tx_buffer == first)
d3d00239
AD		 6817 break;
6818 if (i == 0)
6819 i = tx_ring->count;
6820 i--;
6821 }
6822
d3d00239 6823 tx_ring->next_to_use = i;
9a799d71
AK		 6824}
6825
fd0db0ed 6826static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6827 struct ixgbe_tx_buffer *first)
69830529
AD		 6828{
6829 struct ixgbe_q_vector *q_vector = ring->q_vector;
6830 union ixgbe_atr_hash_dword input = { .dword = 0 };
6831 union ixgbe_atr_hash_dword common = { .dword = 0 };
6832 union {
6833 unsigned char *network;
6834 struct iphdr *ipv4;
6835 struct ipv6hdr *ipv6;
6836 } hdr;
ee9e0f0b 6837 struct tcphdr *th;
905e4a41 6838 __be16 vlan_id;
c4cf55e5 6839
69830529
AD		 6840 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6841 if (!q_vector)
6842 return;
6843
6844 /* do nothing if sampling is disabled */
6845 if (!ring->atr_sample_rate)
d3ead241 6846 return;
c4cf55e5 6847
69830529 6848 ring->atr_count++;
c4cf55e5 6849
69830529 6850 /* snag network header to get L4 type and address */
fd0db0ed 6851 hdr.network = skb_network_header(first->skb);
69830529
AD		 6852
6853 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6854 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6855 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6856 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6857 hdr.ipv4->protocol != IPPROTO_TCP))
6858 return;
ee9e0f0b 6859
fd0db0ed 6860 th = tcp_hdr(first->skb);
c4cf55e5 6861
66f32a8b
AD		 6862 /* skip this packet since it is invalid or the socket is closing */
6863 if (!th || th->fin)
69830529
AD		 6864 return;
6865
6866 /* sample on all syn packets or once every atr sample count */
6867 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6868 return;
6869
6870 /* reset sample count */
6871 ring->atr_count = 0;
6872
244e27ad 6873 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6874
6875 /*
6876 * src and dst are inverted, think how the receiver sees them
6877 *
6878 * The input is broken into two sections, a non-compressed section
6879 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6880 * is XORed together and stored in the compressed dword.
6881 */
6882 input.formatted.vlan_id = vlan_id;
6883
6884 /*
6885 * since src port and flex bytes occupy the same word XOR them together
6886 * and write the value to source port portion of compressed dword
6887 */
244e27ad 6888 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6889 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6890 else
244e27ad 6891 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6892 common.port.dst ^= th->source;
6893
244e27ad 6894 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6895 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6896 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6897 } else {
6898 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6899 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6900 hdr.ipv6->saddr.s6_addr32[1] ^
6901 hdr.ipv6->saddr.s6_addr32[2] ^
6902 hdr.ipv6->saddr.s6_addr32[3] ^
6903 hdr.ipv6->daddr.s6_addr32[0] ^
6904 hdr.ipv6->daddr.s6_addr32[1] ^
6905 hdr.ipv6->daddr.s6_addr32[2] ^
6906 hdr.ipv6->daddr.s6_addr32[3];
6907 }
c4cf55e5
PWJ		 6908
6909 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6910 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6911 input, common, ring->queue_index);
c4cf55e5
PWJ		 6912}
6913
63544e9c 6914static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6915{
fc77dc3c 6916 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6917 /* Herbert's original patch had:
6918 * smp_mb__after_netif_stop_queue();
6919 * but since that doesn't exist yet, just open code it. */
6920 smp_mb();
6921
6922 /* We need to check again in a case another CPU has just
6923 * made room available. */
7d4987de 6924 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6925 return -EBUSY;
6926
6927 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6928 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6929 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6930 return 0;
6931}
6932
82d4e46e 6933static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6934{
7d4987de 6935 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6936 return 0;
fc77dc3c 6937 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6938}
6939
f663dd9a 6940static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 6941 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 6942{
f663dd9a
JW		 6943 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
6944#ifdef IXGBE_FCOE
97488bd1
AD		 6945 struct ixgbe_adapter *adapter;
6946 struct ixgbe_ring_feature *f;
6947 int txq;
f663dd9a
JW		 6948#endif
6949
6950 if (fwd_adapter)
6951 return skb->queue_mapping + fwd_adapter->tx_base_queue;
6952
6953#ifdef IXGBE_FCOE
5e09a105 6954
97488bd1
AD		 6955 /*
6956 * only execute the code below if protocol is FCoE
6957 * or FIP and we have FCoE enabled on the adapter
6958 */
6959 switch (vlan_get_protocol(skb)) {
6960 case __constant_htons(ETH_P_FCOE):
6961 case __constant_htons(ETH_P_FIP):
6962 adapter = netdev_priv(dev);
c087663e 6963
97488bd1
AD		 6964 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6965 break;
6966 default:
99932d4f 6967 return fallback(dev, skb);
97488bd1 6968 }
c087663e 6969
97488bd1 6970 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6971
97488bd1
AD		 6972 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6973 smp_processor_id();
56075a98 6974
97488bd1
AD		 6975 while (txq >= f->indices)
6976 txq -= f->indices;
c4cf55e5 6977
97488bd1 6978 return txq + f->offset;
f663dd9a 6979#else
99932d4f 6980 return fallback(dev, skb);
f663dd9a 6981#endif
09a3b1f8
SH		 6982}
6983
fc77dc3c 6984netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6985 struct ixgbe_adapter *adapter,
6986 struct ixgbe_ring *tx_ring)
9a799d71 6987{
d3d00239 6988 struct ixgbe_tx_buffer *first;
5f715823 6989 int tso;
d3d00239 6990 u32 tx_flags = 0;
a535c30e 6991 unsigned short f;
a535c30e 6992 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6993 __be16 protocol = skb->protocol;
63544e9c 6994 u8 hdr_len = 0;
5e09a105 6995
a535c30e
AD		 6996 /*
6997 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6998 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6999 * + 2 desc gap to keep tail from touching head,
7000 * + 1 desc for context descriptor,
7001 * otherwise try next time
7002 */
a535c30e
AD		 7003 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7004 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7005
a535c30e
AD		 7006 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7007 tx_ring->tx_stats.tx_busy++;
7008 return NETDEV_TX_BUSY;
7009 }
7010
fd0db0ed
AD		 7011 /* record the location of the first descriptor for this packet */
7012 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7013 first->skb = skb;
091a6246
AD		 7014 first->bytecount = skb->len;
7015 first->gso_segs = 1;
fd0db0ed 7016
66f32a8b 7017 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7018 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7019 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7020 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7021 /* else if it is a SW VLAN check the next protocol and store the tag */
7022 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7023 struct vlan_hdr *vhdr, _vhdr;
7024 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7025 if (!vhdr)
7026 goto out_drop;
7027
7028 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7029 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7030 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7031 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7032 }
7033
aa7bd467
JK		 7034 skb_tx_timestamp(skb);
7035
3a6a4eda
JK		 7036 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
7037 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7038 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7039
7040 /* schedule check for Tx timestamp */
7041 adapter->ptp_tx_skb = skb_get(skb);
7042 adapter->ptp_tx_start = jiffies;
7043 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7044 }
3a6a4eda 7045
9e0c5648
AD		 7046#ifdef CONFIG_PCI_IOV
7047 /*
7048 * Use the l2switch_enable flag - would be false if the DMA
7049 * Tx switch had been disabled.
7050 */
7051 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7052 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7053
7054#endif
32701dc2 7055 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7056 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7057 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7058 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7059 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7060 tx_flags |= (skb->priority & 0x7) <<
7061 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7062 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7063 struct vlan_ethhdr *vhdr;
7064 if (skb_header_cloned(skb) &&
7065 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7066 goto out_drop;
7067 vhdr = (struct vlan_ethhdr *)skb->data;
7068 vhdr->h_vlan_TCI = htons(tx_flags >>
7069 IXGBE_TX_FLAGS_VLAN_SHIFT);
7070 } else {
7071 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7072 }
9a799d71 7073 }
eacd73f7 7074
244e27ad
AD		 7075 /* record initial flags and protocol */
7076 first->tx_flags = tx_flags;
7077 first->protocol = protocol;
7078
eacd73f7 7079#ifdef IXGBE_FCOE
66f32a8b
AD		 7080 /* setup tx offload for FCoE */
7081 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 7082 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7083 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7084 if (tso < 0)
7085 goto out_drop;
9a799d71 7086
66f32a8b 7087 goto xmit_fcoe;
eacd73f7 7088 }
9a799d71 7089
66f32a8b 7090#endif /* IXGBE_FCOE */
244e27ad 7091 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7092 if (tso < 0)
897ab156 7093 goto out_drop;
244e27ad
AD		 7094 else if (!tso)
7095 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7096
7097 /* add the ATR filter if ATR is on */
7098 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7099 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7100
7101#ifdef IXGBE_FCOE
7102xmit_fcoe:
7103#endif /* IXGBE_FCOE */
244e27ad 7104 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 7105
7106 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7107
7108 return NETDEV_TX_OK;
897ab156
AD		 7109
7110out_drop:
fd0db0ed
AD		 7111 dev_kfree_skb_any(first->skb);
7112 first->skb = NULL;
7113
897ab156 7114 return NETDEV_TX_OK;
9a799d71
AK		 7115}
7116
2a47fa45
JF		 7117static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7118 struct net_device *netdev,
7119 struct ixgbe_ring *ring)
84418e3b
AD		 7120{
7121 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7122 struct ixgbe_ring *tx_ring;
7123
a50c29dd
AD		 7124 /*
7125 * The minimum packet size for olinfo paylen is 17 so pad the skb
7126 * in order to meet this minimum size requirement.
7127 */
f73332fc
SH		 7128 if (unlikely(skb->len < 17)) {
7129 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7130 return NETDEV_TX_OK;
7131 skb->len = 17;
71a49f77 7132 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7133 }
7134
2a47fa45
JF		 7135 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7136
fc77dc3c 7137 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7138}
7139
2a47fa45
JF		 7140static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7141 struct net_device *netdev)
7142{
7143 return __ixgbe_xmit_frame(skb, netdev, NULL);
7144}
7145
9a799d71
AK		 7146/**
7147 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7148 * @netdev: network interface device structure
7149 * @p: pointer to an address structure
7150 *
7151 * Returns 0 on success, negative on failure
7152 **/
7153static int ixgbe_set_mac(struct net_device *netdev, void *p)
7154{
7155 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7156 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7157 struct sockaddr *addr = p;
7158
7159 if (!is_valid_ether_addr(addr->sa_data))
7160 return -EADDRNOTAVAIL;
7161
7162 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7163 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7164
1d9c0bfd 7165 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 7166
7167 return 0;
7168}
7169
6b73e10d
BH		 7170static int
7171ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7172{
7173 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7174 struct ixgbe_hw *hw = &adapter->hw;
7175 u16 value;
7176 int rc;
7177
7178 if (prtad != hw->phy.mdio.prtad)
7179 return -EINVAL;
7180 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7181 if (!rc)
7182 rc = value;
7183 return rc;
7184}
7185
7186static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7187 u16 addr, u16 value)
7188{
7189 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7190 struct ixgbe_hw *hw = &adapter->hw;
7191
7192 if (prtad != hw->phy.mdio.prtad)
7193 return -EINVAL;
7194 return hw->phy.ops.write_reg(hw, addr, devad, value);
7195}
7196
7197static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7198{
7199 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7200
3a6a4eda 7201 switch (cmd) {
3a6a4eda 7202 case SIOCSHWTSTAMP:
93501d48
JK		 7203 return ixgbe_ptp_set_ts_config(adapter, req);
7204 case SIOCGHWTSTAMP:
7205 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7206 default:
7207 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7208 }
6b73e10d
BH		 7209}
7210
0365e6e4
PW		 7211/**
7212 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7213 * netdev->dev_addrs
0365e6e4
PW		 7214 * @netdev: network interface device structure
7215 *
7216 * Returns non-zero on failure
7217 **/
7218static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7219{
7220 int err = 0;
7221 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7222 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7223
7fa7c9dc 7224 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7225 rtnl_lock();
7fa7c9dc 7226 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7227 rtnl_unlock();
7fa7c9dc
AD		 7228
7229 /* update SAN MAC vmdq pool selection */
7230 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7231 }
7232 return err;
7233}
7234
7235/**
7236 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7237 * netdev->dev_addrs
0365e6e4
PW		 7238 * @netdev: network interface device structure
7239 *
7240 * Returns non-zero on failure
7241 **/
7242static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7243{
7244 int err = 0;
7245 struct ixgbe_adapter *adapter = netdev_priv(dev);
7246 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7247
7248 if (is_valid_ether_addr(mac->san_addr)) {
7249 rtnl_lock();
7250 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7251 rtnl_unlock();
7252 }
7253 return err;
7254}
7255
9a799d71
AK		 7256#ifdef CONFIG_NET_POLL_CONTROLLER
7257/*
7258 * Polling 'interrupt' - used by things like netconsole to send skbs
7259 * without having to re-enable interrupts. It's not called while
7260 * the interrupt routine is executing.
7261 */
7262static void ixgbe_netpoll(struct net_device *netdev)
7263{
7264 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7265 int i;
9a799d71 7266
1a647bd2
AD		 7267 /* if interface is down do nothing */
7268 if (test_bit(__IXGBE_DOWN, &adapter->state))
7269 return;
7270
9a799d71 7271 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7272 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7273 for (i = 0; i < adapter->num_q_vectors; i++)
7274 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7275 } else {
7276 ixgbe_intr(adapter->pdev->irq, netdev);
7277 }
9a799d71 7278 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7279}
9a799d71 7280
581330ba 7281#endif
de1036b1
ED		 7282static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7283 struct rtnl_link_stats64 *stats)
7284{
7285 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7286 int i;
7287
1a51502b 7288 rcu_read_lock();
de1036b1 7289 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7290 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7291 u64 bytes, packets;
7292 unsigned int start;
7293
1a51502b
ED		 7294 if (ring) {
7295 do {
57a7744e 7296 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7297 packets = ring->stats.packets;
7298 bytes = ring->stats.bytes;
57a7744e 7299 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7300 stats->rx_packets += packets;
7301 stats->rx_bytes += bytes;
7302 }
de1036b1 7303 }
1ac9ad13
ED		 7304
7305 for (i = 0; i < adapter->num_tx_queues; i++) {
7306 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7307 u64 bytes, packets;
7308 unsigned int start;
7309
7310 if (ring) {
7311 do {
57a7744e 7312 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7313 packets = ring->stats.packets;
7314 bytes = ring->stats.bytes;
57a7744e 7315 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7316 stats->tx_packets += packets;
7317 stats->tx_bytes += bytes;
7318 }
7319 }
1a51502b 7320 rcu_read_unlock();
de1036b1
ED		 7321 /* following stats updated by ixgbe_watchdog_task() */
7322 stats->multicast = netdev->stats.multicast;
7323 stats->rx_errors = netdev->stats.rx_errors;
7324 stats->rx_length_errors = netdev->stats.rx_length_errors;
7325 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7326 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7327 return stats;
7328}
7329
8af3c33f 7330#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7331/**
7332 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7333 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7334 * @tc: number of traffic classes currently enabled
7335 *
7336 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7337 * 802.1Q priority maps to a packet buffer that exists.
7338 */
7339static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7340{
7341 struct ixgbe_hw *hw = &adapter->hw;
7342 u32 reg, rsave;
7343 int i;
7344
7345 /* 82598 have a static priority to TC mapping that can not
7346 * be changed so no validation is needed.
7347 */
7348 if (hw->mac.type == ixgbe_mac_82598EB)
7349 return;
7350
7351 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7352 rsave = reg;
7353
7354 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7355 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7356
7357 /* If up2tc is out of bounds default to zero */
7358 if (up2tc > tc)
7359 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7360 }
7361
7362 if (reg != rsave)
7363 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7364
7365 return;
7366}
7367
02debdc9
AD		 7368/**
7369 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7370 * @adapter: Pointer to adapter struct
7371 *
7372 * Populate the netdev user priority to tc map
7373 */
7374static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7375{
7376 struct net_device *dev = adapter->netdev;
7377 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7378 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7379 u8 prio;
7380
7381 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7382 u8 tc = 0;
7383
7384 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7385 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7386 else if (ets)
7387 tc = ets->prio_tc[prio];
7388
7389 netdev_set_prio_tc_map(dev, prio, tc);
7390 }
7391}
7392
cca73c59 7393#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7394/**
7395 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7396 *
7397 * @netdev: net device to configure
7398 * @tc: number of traffic classes to enable
7399 */
7400int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7401{
8b1c0b24
JF		 7402 struct ixgbe_adapter *adapter = netdev_priv(dev);
7403 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7404 bool pools;
8b1c0b24 7405
8b1c0b24 7406 /* Hardware supports up to 8 traffic classes */
4de2a022 7407 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7408 (hw->mac.type == ixgbe_mac_82598EB &&
7409 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7410 return -EINVAL;
7411
2a47fa45
JF		 7412 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7413 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7414 return -EBUSY;
7415
8b1c0b24 7416 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7417 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7418 * hardware is not flexible enough to do this dynamically.
7419 */
7420 if (netif_running(dev))
7421 ixgbe_close(dev);
7422 ixgbe_clear_interrupt_scheme(adapter);
7423
cca73c59 7424#ifdef CONFIG_IXGBE_DCB
e7589eab 7425 if (tc) {
8b1c0b24 7426 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7427 ixgbe_set_prio_tc_map(adapter);
7428
e7589eab 7429 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7430
943561d3
AD		 7431 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7432 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7433 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7434 }
e7589eab 7435 } else {
8b1c0b24 7436 netdev_reset_tc(dev);
02debdc9 7437
943561d3
AD		 7438 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7439 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7440
7441 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7442
7443 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7444 adapter->dcb_cfg.pfc_mode_enable = false;
7445 }
7446
8b1c0b24 7447 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7448
7449#endif /* CONFIG_IXGBE_DCB */
7450 ixgbe_init_interrupt_scheme(adapter);
7451
8b1c0b24 7452 if (netif_running(dev))
cca73c59 7453 return ixgbe_open(dev);
8b1c0b24
JF		 7454
7455 return 0;
7456}
de1036b1 7457
da36b647
GR		 7458#ifdef CONFIG_PCI_IOV
7459void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7460{
7461 struct net_device *netdev = adapter->netdev;
7462
7463 rtnl_lock();
da36b647 7464 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7465 rtnl_unlock();
7466}
7467
7468#endif
082757af
DS		 7469void ixgbe_do_reset(struct net_device *netdev)
7470{
7471 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7472
7473 if (netif_running(netdev))
7474 ixgbe_reinit_locked(adapter);
7475 else
7476 ixgbe_reset(adapter);
7477}
7478
c8f44aff 7479static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7480 netdev_features_t features)
082757af
DS		 7481{
7482 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7483
082757af 7484 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7485 if (!(features & NETIF_F_RXCSUM))
7486 features &= ~NETIF_F_LRO;
082757af 7487
567d2de2
AD		 7488 /* Turn off LRO if not RSC capable */
7489 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7490 features &= ~NETIF_F_LRO;
8e2813f5 7491
567d2de2 7492 return features;
082757af
DS		 7493}
7494
c8f44aff 7495static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7496 netdev_features_t features)
082757af
DS		 7497{
7498 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7499 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7500 bool need_reset = false;
7501
082757af 7502 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7503 if (!(features & NETIF_F_LRO)) {
7504 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7505 need_reset = true;
567d2de2
AD		 7506 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7507 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7508 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7509 if (adapter->rx_itr_setting == 1 ||
7510 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7511 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7512 need_reset = true;
7513 } else if ((changed ^ features) & NETIF_F_LRO) {
7514 e_info(probe, "rx-usecs set too low, "
7515 "disabling RSC\n");
082757af
DS		 7516 }
7517 }
7518
7519 /*
7520 * Check if Flow Director n-tuple support was enabled or disabled. If
7521 * the state changed, we need to reset.
7522 */
39cb681b
AD		 7523 switch (features & NETIF_F_NTUPLE) {
7524 case NETIF_F_NTUPLE:
567d2de2 7525 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7526 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7527 need_reset = true;
7528
567d2de2
AD		 7529 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7530 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7531 break;
7532 default:
7533 /* turn off perfect filters, enable ATR and reset */
7534 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7535 need_reset = true;
7536
7537 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7538
7539 /* We cannot enable ATR if SR-IOV is enabled */
7540 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7541 break;
7542
7543 /* We cannot enable ATR if we have 2 or more traffic classes */
7544 if (netdev_get_num_tc(netdev) > 1)
7545 break;
7546
7547 /* We cannot enable ATR if RSS is disabled */
7548 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7549 break;
7550
7551 /* A sample rate of 0 indicates ATR disabled */
7552 if (!adapter->atr_sample_rate)
7553 break;
7554
7555 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7556 break;
082757af
DS		 7557 }
7558
f646968f 7559 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7560 ixgbe_vlan_strip_enable(adapter);
7561 else
7562 ixgbe_vlan_strip_disable(adapter);
7563
3f2d1c0f
BG		 7564 if (changed & NETIF_F_RXALL)
7565 need_reset = true;
7566
567d2de2 7567 netdev->features = features;
082757af
DS		 7568 if (need_reset)
7569 ixgbe_do_reset(netdev);
7570
7571 return 0;
082757af
DS		 7572}
7573
edc7d573 7574static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7575 struct net_device *dev,
6b6e2725 7576 const unsigned char *addr,
0f4b0add
JF		 7577 u16 flags)
7578{
7579 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7580 int err;
7581
7582 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7583 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7584
b1ac1ef7
JF		 7585 /* Hardware does not support aging addresses so if a
7586 * ndm_state is given only allow permanent addresses
7587 */
7588 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7589 pr_info("%s: FDB only supports static addresses\n",
7590 ixgbe_driver_name);
7591 return -EINVAL;
7592 }
7593
46acc460 7594 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7595 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7596
7597 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7598 err = dev_uc_add_excl(dev, addr);
0f4b0add 7599 else
95447461
JF		 7600 err = -ENOMEM;
7601 } else if (is_multicast_ether_addr(addr)) {
7602 err = dev_mc_add_excl(dev, addr);
7603 } else {
7604 err = -EINVAL;
0f4b0add
JF		 7605 }
7606
7607 /* Only return duplicate errors if NLM_F_EXCL is set */
7608 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7609 err = 0;
7610
7611 return err;
7612}
7613
815cccbf
JF		 7614static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7615 struct nlmsghdr *nlh)
7616{
7617 struct ixgbe_adapter *adapter = netdev_priv(dev);
7618 struct nlattr *attr, *br_spec;
7619 int rem;
7620
7621 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7622 return -EOPNOTSUPP;
7623
7624 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7625
7626 nla_for_each_nested(attr, br_spec, rem) {
7627 __u16 mode;
7628 u32 reg = 0;
7629
7630 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7631 continue;
7632
7633 mode = nla_get_u16(attr);
9b735984 7634 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7635 reg = 0;
9b735984
GR		 7636 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7637 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7638 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7639 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7640 } else
815cccbf
JF		 7641 return -EINVAL;
7642
7643 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7644
7645 e_info(drv, "enabling bridge mode: %s\n",
7646 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7647 }
7648
7649 return 0;
7650}
7651
7652static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7653 struct net_device *dev,
7654 u32 filter_mask)
815cccbf
JF		 7655{
7656 struct ixgbe_adapter *adapter = netdev_priv(dev);
7657 u16 mode;
7658
7659 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7660 return 0;
7661
9b735984 7662 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7663 mode = BRIDGE_MODE_VEB;
7664 else
7665 mode = BRIDGE_MODE_VEPA;
7666
7667 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7668}
7669
2a47fa45
JF		 7670static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7671{
7672 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7673 struct ixgbe_adapter *adapter = netdev_priv(pdev);
51f3773b 7674 unsigned int limit;
2a47fa45
JF		 7675 int pool, err;
7676
219354d4
JF		 7677#ifdef CONFIG_RPS
7678 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7679 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7680 vdev->name);
7681 return ERR_PTR(-EINVAL);
7682 }
7683#endif
2a47fa45 7684 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7685 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7686 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7687 netdev_info(pdev,
7688 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7689 pdev->name);
7690 return ERR_PTR(-EINVAL);
7691 }
7692
7693 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7694 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7695 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7696 return ERR_PTR(-EBUSY);
7697
7698 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7699 if (!fwd_adapter)
7700 return ERR_PTR(-ENOMEM);
7701
7702 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7703 adapter->num_rx_pools++;
7704 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7705 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7706
7707 /* Enable VMDq flag so device will be set in VM mode */
7708 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7709 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7710 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7711
7712 /* Force reinit of ring allocation with VMDQ enabled */
7713 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7714 if (err)
7715 goto fwd_add_err;
7716 fwd_adapter->pool = pool;
7717 fwd_adapter->real_adapter = adapter;
7718 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7719 if (err)
7720 goto fwd_add_err;
7721 netif_tx_start_all_queues(vdev);
7722 return fwd_adapter;
7723fwd_add_err:
7724 /* unwind counter and free adapter struct */
7725 netdev_info(pdev,
7726 "%s: dfwd hardware acceleration failed\n", vdev->name);
7727 clear_bit(pool, &adapter->fwd_bitmask);
7728 adapter->num_rx_pools--;
7729 kfree(fwd_adapter);
7730 return ERR_PTR(err);
7731}
7732
7733static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7734{
7735 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7736 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7737 unsigned int limit;
2a47fa45
JF		 7738
7739 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7740 adapter->num_rx_pools--;
7741
51f3773b
JF		 7742 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7743 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7744 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7745 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7746 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7747 fwd_adapter->pool, adapter->num_rx_pools,
7748 fwd_adapter->rx_base_queue,
7749 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7750 adapter->fwd_bitmask);
7751 kfree(fwd_adapter);
7752}
7753
0edc3527 7754static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7755 .ndo_open = ixgbe_open,
0edc3527 7756 .ndo_stop = ixgbe_close,
00829823 7757 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7758 .ndo_select_queue = ixgbe_select_queue,
581330ba 7759 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7760 .ndo_validate_addr = eth_validate_addr,
7761 .ndo_set_mac_address = ixgbe_set_mac,
7762 .ndo_change_mtu = ixgbe_change_mtu,
7763 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7764 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7765 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7766 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7767 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7768 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7769 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7770 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7771 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7772 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7773#ifdef CONFIG_IXGBE_DCB
24095aa3 7774 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7775#endif
0edc3527
SH		 7776#ifdef CONFIG_NET_POLL_CONTROLLER
7777 .ndo_poll_controller = ixgbe_netpoll,
7778#endif
e0d1095a 7779#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7780 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7781#endif
332d4a7d
YZ		 7782#ifdef IXGBE_FCOE
7783 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7784 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7785 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7786 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7787 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7788 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7789 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7790#endif /* IXGBE_FCOE */
082757af
DS		 7791 .ndo_set_features = ixgbe_set_features,
7792 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7793 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7794 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7795 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7796 .ndo_dfwd_add_station = ixgbe_fwd_add,
7797 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7798};
7799
e027d1ae
JK		 7800/**
7801 * ixgbe_enumerate_functions - Get the number of ports this device has
7802 * @adapter: adapter structure
7803 *
7804 * This function enumerates the phsyical functions co-located on a single slot,
7805 * in order to determine how many ports a device has. This is most useful in
7806 * determining the required GT/s of PCIe bandwidth necessary for optimal
7807 * performance.
7808 **/
7809static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7810{
e027d1ae
JK		 7811 struct list_head *entry;
7812 int physfns = 0;
7813
f1f96579
JK		 7814 /* Some cards can not use the generic count PCIe functions method,
7815 * because they are behind a parent switch, so we hardcode these with
7816 * the correct number of functions.
e027d1ae 7817 */
f1f96579 7818 if (ixgbe_pcie_from_parent(&adapter->hw)) {
e027d1ae 7819 physfns = 4;
f1f96579 7820 } else {
e027d1ae
JK		 7821 list_for_each(entry, &adapter->pdev->bus_list) {
7822 struct pci_dev *pdev =
7823 list_entry(entry, struct pci_dev, bus_list);
7824 /* don't count virtual functions */
7825 if (!pdev->is_virtfn)
7826 physfns++;
7827 }
7828 }
7829
7830 return physfns;
7831}
7832
8e2813f5
JK		 7833/**
7834 * ixgbe_wol_supported - Check whether device supports WoL
7835 * @hw: hw specific details
7836 * @device_id: the device ID
7837 * @subdev_id: the subsystem device ID
7838 *
7839 * This function is used by probe and ethtool to determine
7840 * which devices have WoL support
7841 *
7842 **/
7843int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7844 u16 subdevice_id)
7845{
7846 struct ixgbe_hw *hw = &adapter->hw;
7847 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7848 int is_wol_supported = 0;
7849
7850 switch (device_id) {
7851 case IXGBE_DEV_ID_82599_SFP:
7852 /* Only these subdevices could supports WOL */
7853 switch (subdevice_id) {
87557440 7854 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 7855 case IXGBE_SUBDEV_ID_82599_560FLR:
7856 /* only support first port */
7857 if (hw->bus.func != 0)
7858 break;
5700ff26 7859 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7860 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7861 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7862 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7863 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7864 is_wol_supported = 1;
7865 break;
7866 }
7867 break;
5daebbb0
DS		 7868 case IXGBE_DEV_ID_82599EN_SFP:
7869 /* Only this subdevice supports WOL */
7870 switch (subdevice_id) {
7871 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7872 is_wol_supported = 1;
7873 break;
7874 }
7875 break;
8e2813f5
JK		 7876 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7877 /* All except this subdevice support WOL */
7878 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7879 is_wol_supported = 1;
7880 break;
7881 case IXGBE_DEV_ID_82599_KX4:
7882 is_wol_supported = 1;
7883 break;
7884 case IXGBE_DEV_ID_X540T:
df376f0d 7885 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7886 /* check eeprom to see if enabled wol */
7887 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7888 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7889 (hw->bus.func == 0))) {
7890 is_wol_supported = 1;
7891 }
7892 break;
7893 }
7894
7895 return is_wol_supported;
7896}
7897
9a799d71
AK		 7898/**
7899 * ixgbe_probe - Device Initialization Routine
7900 * @pdev: PCI device information struct
7901 * @ent: entry in ixgbe_pci_tbl
7902 *
7903 * Returns 0 on success, negative on failure
7904 *
7905 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7906 * The OS initialization, configuring of the adapter private structure,
7907 * and a hardware reset occur.
7908 **/
1dd06ae8 7909static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7910{
7911 struct net_device *netdev;
7912 struct ixgbe_adapter *adapter = NULL;
7913 struct ixgbe_hw *hw;
7914 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 7915 static int cards_found;
e027d1ae 7916 int i, err, pci_using_dac, expected_gts;
d3cb9869 7917 unsigned int indices = MAX_TX_QUEUES;
289700db 7918 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7919#ifdef IXGBE_FCOE
7920 u16 device_caps;
7921#endif
289700db 7922 u32 eec;
9a799d71 7923
bded64a7
AG		 7924 /* Catch broken hardware that put the wrong VF device ID in
7925 * the PCIe SR-IOV capability.
7926 */
7927 if (pdev->is_virtfn) {
7928 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7929 pci_name(pdev), pdev->vendor, pdev->device);
7930 return -EINVAL;
7931 }
7932
9ce77666 7933 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7934 if (err)
7935 return err;
7936
f5f2eda8 7937 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7938 pci_using_dac = 1;
7939 } else {
f5f2eda8 7940 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7941 if (err) {
f5f2eda8
RK		 7942 dev_err(&pdev->dev,
7943 "No usable DMA configuration, aborting\n");
7944 goto err_dma;
9a799d71
AK		 7945 }
7946 pci_using_dac = 0;
7947 }
7948
9ce77666 7949 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7950 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7951 if (err) {
b8bc0421
DC		 7952 dev_err(&pdev->dev,
7953 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7954 goto err_pci_reg;
7955 }
7956
19d5afd4 7957 pci_enable_pcie_error_reporting(pdev);
6fabd715 7958
9a799d71 7959 pci_set_master(pdev);
fb3b27bc 7960 pci_save_state(pdev);
9a799d71 7961
d3cb9869 7962 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7963#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7964 /* 8 TC w/ 4 queues per TC */
7965 indices = 4 * MAX_TRAFFIC_CLASS;
7966#else
7967 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7968#endif
d3cb9869 7969 }
e901acd6 7970
c85a2618 7971 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7972 if (!netdev) {
7973 err = -ENOMEM;
7974 goto err_alloc_etherdev;
7975 }
7976
9a799d71
AK		 7977 SET_NETDEV_DEV(netdev, &pdev->dev);
7978
9a799d71 7979 adapter = netdev_priv(netdev);
c60fbb00 7980 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7981
7982 adapter->netdev = netdev;
7983 adapter->pdev = pdev;
7984 hw = &adapter->hw;
7985 hw->back = adapter;
b3f4d599 7986 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7987
05857980 7988 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7989 pci_resource_len(pdev, 0));
2a1a091c 7990 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 7991 if (!hw->hw_addr) {
7992 err = -EIO;
7993 goto err_ioremap;
7994 }
7995
0edc3527 7996 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7997 ixgbe_set_ethtool_ops(netdev);
9a799d71 7998 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7999 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 8000
9a799d71
AK		 8001 adapter->bd_number = cards_found;
8002
9a799d71
AK		 8003 /* Setup hw api */
8004 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8005 hw->mac.type = ii->mac;
9a799d71 8006
c44ade9e
JB		 8007 /* EEPROM */
8008 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8009 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
8010 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8011 if (!(eec & (1 << 8)))
8012 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8013
8014 /* PHY */
8015 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8016 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8017 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8018 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8019 hw->phy.mdio.mmds = 0;
8020 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8021 hw->phy.mdio.dev = netdev;
8022 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8023 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8024
8ca783ab 8025 ii->get_invariants(hw);
9a799d71
AK		 8026
8027 /* setup the private structure */
8028 err = ixgbe_sw_init(adapter);
8029 if (err)
8030 goto err_sw_init;
8031
0b2679d6
DS		 8032 /* Cache if MNG FW is up so we don't have to read the REG later */
8033 if (hw->mac.ops.mng_fw_enabled)
8034 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
8035
e86bff0e 8036 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8037 switch (adapter->hw.mac.type) {
8038 case ixgbe_mac_82599EB:
8039 case ixgbe_mac_X540:
e86bff0e 8040 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8041 break;
8042 default:
8043 break;
8044 }
e86bff0e 8045
bf069c97
DS		 8046 /*
8047 * If there is a fan on this device and it has failed log the
8048 * failure.
8049 */
8050 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8051 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8052 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8053 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8054 }
8055
8ef78adc
PWJ		 8056 if (allow_unsupported_sfp)
8057 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8058
c44ade9e 8059 /* reset_hw fills in the perm_addr as well */
119fc60a 8060 hw->phy.reset_if_overtemp = true;
c44ade9e 8061 err = hw->mac.ops.reset_hw(hw);
119fc60a 8062 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8063 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8064 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8065 err = 0;
8066 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8067 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8068 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8069 goto err_sw_init;
8070 } else if (err) {
849c4542 8071 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8072 goto err_sw_init;
8073 }
8074
99d74487 8075#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8076 /* SR-IOV not supported on the 82598 */
8077 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8078 goto skip_sriov;
8079 /* Mailbox */
8080 ixgbe_init_mbx_params_pf(hw);
8081 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8082 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8083 ixgbe_enable_sriov(adapter);
60a1a680 8084skip_sriov:
1cdd1ec8 8085
99d74487 8086#endif
396e799c 8087 netdev->features = NETIF_F_SG |
e8e9f696 8088 NETIF_F_IP_CSUM |
082757af 8089 NETIF_F_IPV6_CSUM |
f646968f
PM		 8090 NETIF_F_HW_VLAN_CTAG_TX |
8091 NETIF_F_HW_VLAN_CTAG_RX |
8092 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8093 NETIF_F_TSO |
8094 NETIF_F_TSO6 |
082757af 8095 NETIF_F_RXHASH |
8bf1264d 8096 NETIF_F_RXCSUM;
9a799d71 8097
8bf1264d 8098 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8099
58be7666
DS		 8100 switch (adapter->hw.mac.type) {
8101 case ixgbe_mac_82599EB:
8102 case ixgbe_mac_X540:
45a5ead0 8103 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8104 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8105 NETIF_F_NTUPLE;
58be7666
DS		 8106 break;
8107 default:
8108 break;
8109 }
45a5ead0 8110
3f2d1c0f
BG		 8111 netdev->hw_features |= NETIF_F_RXALL;
8112
ad31c402
JK		 8113 netdev->vlan_features |= NETIF_F_TSO;
8114 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8115 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8116 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8117 netdev->vlan_features |= NETIF_F_SG;
8118
01789349 8119 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8120 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8121
7a6b6f51 8122#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8123 netdev->dcbnl_ops = &dcbnl_ops;
8124#endif
8125
eacd73f7 8126#ifdef IXGBE_FCOE
0d551589 8127 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8128 unsigned int fcoe_l;
8129
eacd73f7
YZ		 8130 if (hw->mac.ops.get_device_caps) {
8131 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8132 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8133 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8134 }
7c8ae65a 8135
d3cb9869
AD		 8136
8137 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8138 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8139
a58915c7
AD		 8140 netdev->features |= NETIF_F_FSO |
8141 NETIF_F_FCOE_CRC;
8142
7c8ae65a
AD		 8143 netdev->vlan_features |= NETIF_F_FSO |
8144 NETIF_F_FCOE_CRC |
8145 NETIF_F_FCOE_MTU;
5e09d7f6 8146 }
eacd73f7 8147#endif /* IXGBE_FCOE */
7b872a55 8148 if (pci_using_dac) {
9a799d71 8149 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8150 netdev->vlan_features |= NETIF_F_HIGHDMA;
8151 }
9a799d71 8152
082757af
DS		 8153 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8154 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8155 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8156 netdev->features |= NETIF_F_LRO;
8157
9a799d71 8158 /* make sure the EEPROM is good */
c44ade9e 8159 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8160 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8161 err = -EIO;
35937c05 8162 goto err_sw_init;
9a799d71
AK		 8163 }
8164
8165 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8166
aaeb6cdf 8167 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8168 e_dev_err("invalid MAC address\n");
9a799d71 8169 err = -EIO;
35937c05 8170 goto err_sw_init;
9a799d71
AK		 8171 }
8172
7086400d 8173 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8174 (unsigned long) adapter);
9a799d71 8175
7086400d
AD		 8176 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8177 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8178
021230d4
AV		 8179 err = ixgbe_init_interrupt_scheme(adapter);
8180 if (err)
8181 goto err_sw_init;
9a799d71 8182
8e2813f5 8183 /* WOL not supported for all devices */
c23f5b6b 8184 adapter->wol = 0;
8e2813f5 8185 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8186 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8187 pdev->subsystem_device);
6b92b0ba 8188 if (hw->wol_enabled)
9417c464 8189 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8190
e8e26350
PW		 8191 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8192
15e5209f
ET		 8193 /* save off EEPROM version number */
8194 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8195 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8196
04f165ef
PW		 8197 /* pick up the PCI bus settings for reporting later */
8198 hw->mac.ops.get_bus_info(hw);
e027d1ae 8199 if (ixgbe_pcie_from_parent(hw))
b8e82001 8200 ixgbe_get_parent_bus_info(adapter);
04f165ef 8201
e027d1ae
JK		 8202 /* calculate the expected PCIe bandwidth required for optimal
8203 * performance. Note that some older parts will never have enough
8204 * bandwidth due to being older generation PCIe parts. We clamp these
8205 * parts to ensure no warning is displayed if it can't be fixed.
8206 */
8207 switch (hw->mac.type) {
8208 case ixgbe_mac_82598EB:
8209 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8210 break;
8211 default:
8212 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8213 break;
0c254d86 8214 }
e027d1ae 8215 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8216
6a2aae5a
JK		 8217 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8218 if (err)
8219 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8220 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8221 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8222 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8223 part_str);
8224 else
8225 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8226 hw->mac.type, hw->phy.type, part_str);
8227
8228 e_dev_info("%pM\n", netdev->dev_addr);
8229
9a799d71 8230 /* reset the hardware with the new settings */
794caeb2 8231 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8232 if (err == IXGBE_ERR_EEPROM_VERSION) {
8233 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8234 e_dev_warn("This device is a pre-production adapter/LOM. "
8235 "Please be aware there may be issues associated "
8236 "with your hardware. If you are experiencing "
8237 "problems please contact your Intel or hardware "
8238 "representative who provided you with this "
8239 "hardware.\n");
794caeb2 8240 }
9a799d71
AK		 8241 strcpy(netdev->name, "eth%d");
8242 err = register_netdev(netdev);
8243 if (err)
8244 goto err_register;
8245
ec74a471
ET		 8246 /* power down the optics for 82599 SFP+ fiber */
8247 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8248 hw->mac.ops.disable_tx_laser(hw);
8249
54386467
JB		 8250 /* carrier off reporting is important to ethtool even BEFORE open */
8251 netif_carrier_off(netdev);
8252
5dd2d332 8253#ifdef CONFIG_IXGBE_DCA
652f093f 8254 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8255 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8256 ixgbe_setup_dca(adapter);
8257 }
8258#endif
1cdd1ec8 8259 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8260 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8261 for (i = 0; i < adapter->num_vfs; i++)
8262 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8263 }
8264
2466dd9c
JK		 8265 /* firmware requires driver version to be 0xFFFFFFFF
8266 * since os does not support feature
8267 */
9612de92 8268 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8269 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8270 0xFF);
9612de92 8271
0365e6e4
PW		 8272 /* add san mac addr to netdev */
8273 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8274
ea81875a 8275 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8276 cards_found++;
3ca8bc6d 8277
1210982b 8278#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8279 if (ixgbe_sysfs_init(adapter))
8280 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8281#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8282
00949167 8283 ixgbe_dbg_adapter_init(adapter);
00949167 8284
0b2679d6
DS		 8285 /* Need link setup for MNG FW, else wait for IXGBE_UP */
8286 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
8287 hw->mac.ops.setup_link(hw,
8288 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8289 true);
8290
9a799d71
AK		 8291 return 0;
8292
8293err_register:
5eba3699 8294 ixgbe_release_hw_control(adapter);
7a921c93 8295 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8296err_sw_init:
99d74487 8297 ixgbe_disable_sriov(adapter);
7086400d 8298 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8299 iounmap(adapter->io_addr);
9a799d71
AK		 8300err_ioremap:
8301 free_netdev(netdev);
8302err_alloc_etherdev:
e8e9f696
JP		 8303 pci_release_selected_regions(pdev,
8304 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8305err_pci_reg:
8306err_dma:
8307 pci_disable_device(pdev);
8308 return err;
8309}
8310
8311/**
8312 * ixgbe_remove - Device Removal Routine
8313 * @pdev: PCI device information struct
8314 *
8315 * ixgbe_remove is called by the PCI subsystem to alert the driver
8316 * that it should release a PCI device. The could be caused by a
8317 * Hot-Plug event, or because the driver is going to be removed from
8318 * memory.
8319 **/
9f9a12f8 8320static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8321{
c60fbb00
AD		 8322 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8323 struct net_device *netdev = adapter->netdev;
9a799d71 8324
00949167 8325 ixgbe_dbg_adapter_exit(adapter);
00949167 8326
09f40aed 8327 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8328 cancel_work_sync(&adapter->service_task);
9a799d71 8329
3a6a4eda 8330
5dd2d332 8331#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8332 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8333 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8334 dca_remove_requester(&pdev->dev);
8335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8336 }
8337
8338#endif
1210982b 8339#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8340 ixgbe_sysfs_exit(adapter);
1210982b 8341#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8342
0365e6e4
PW		 8343 /* remove the added san mac */
8344 ixgbe_del_sanmac_netdev(netdev);
8345
c4900be0
DS		 8346 if (netdev->reg_state == NETREG_REGISTERED)
8347 unregister_netdev(netdev);
9a799d71 8348
da36b647
GR		 8349#ifdef CONFIG_PCI_IOV
8350 /*
8351 * Only disable SR-IOV on unload if the user specified the now
8352 * deprecated max_vfs module parameter.
8353 */
8354 if (max_vfs)
8355 ixgbe_disable_sriov(adapter);
8356#endif
7a921c93 8357 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8358
021230d4 8359 ixgbe_release_hw_control(adapter);
9a799d71 8360
2b1588c3
AD		 8361#ifdef CONFIG_DCB
8362 kfree(adapter->ixgbe_ieee_pfc);
8363 kfree(adapter->ixgbe_ieee_ets);
8364
8365#endif
2a1a091c 8366 iounmap(adapter->io_addr);
9ce77666 8367 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8368 IORESOURCE_MEM));
9a799d71 8369
849c4542 8370 e_dev_info("complete\n");
021230d4 8371
9a799d71
AK		 8372 free_netdev(netdev);
8373
19d5afd4 8374 pci_disable_pcie_error_reporting(pdev);
6fabd715 8375
9a799d71
AK		 8376 pci_disable_device(pdev);
8377}
8378
8379/**
8380 * ixgbe_io_error_detected - called when PCI error is detected
8381 * @pdev: Pointer to PCI device
8382 * @state: The current pci connection state
8383 *
8384 * This function is called after a PCI bus error affecting
8385 * this device has been detected.
8386 */
8387static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8388 pci_channel_state_t state)
9a799d71 8389{
c60fbb00
AD		 8390 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8391 struct net_device *netdev = adapter->netdev;
9a799d71 8392
83c61fa9 8393#ifdef CONFIG_PCI_IOV
14438464 8394 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8395 struct pci_dev *bdev, *vfdev;
8396 u32 dw0, dw1, dw2, dw3;
8397 int vf, pos;
8398 u16 req_id, pf_func;
8399
8400 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8401 adapter->num_vfs == 0)
8402 goto skip_bad_vf_detection;
8403
8404 bdev = pdev->bus->self;
62f87c0e 8405 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8406 bdev = bdev->bus->self;
8407
8408 if (!bdev)
8409 goto skip_bad_vf_detection;
8410
8411 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8412 if (!pos)
8413 goto skip_bad_vf_detection;
8414
14438464
MR		 8415 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8416 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8417 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8418 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8419 if (ixgbe_removed(hw->hw_addr))
8420 goto skip_bad_vf_detection;
83c61fa9
GR		 8421
8422 req_id = dw1 >> 16;
8423 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8424 if (!(req_id & 0x0080))
8425 goto skip_bad_vf_detection;
8426
8427 pf_func = req_id & 0x01;
8428 if ((pf_func & 1) == (pdev->devfn & 1)) {
8429 unsigned int device_id;
8430
8431 vf = (req_id & 0x7F) >> 1;
8432 e_dev_err("VF %d has caused a PCIe error\n", vf);
8433 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8434 "%8.8x\tdw3: %8.8x\n",
8435 dw0, dw1, dw2, dw3);
8436 switch (adapter->hw.mac.type) {
8437 case ixgbe_mac_82599EB:
8438 device_id = IXGBE_82599_VF_DEVICE_ID;
8439 break;
8440 case ixgbe_mac_X540:
8441 device_id = IXGBE_X540_VF_DEVICE_ID;
8442 break;
8443 default:
8444 device_id = 0;
8445 break;
8446 }
8447
8448 /* Find the pci device of the offending VF */
36e90319 8449 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8450 while (vfdev) {
8451 if (vfdev->devfn == (req_id & 0xFF))
8452 break;
36e90319 8453 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8454 device_id, vfdev);
8455 }
8456 /*
8457 * There's a slim chance the VF could have been hot plugged,
8458 * so if it is no longer present we don't need to issue the
8459 * VFLR. Just clean up the AER in that case.
8460 */
8461 if (vfdev) {
8462 e_dev_err("Issuing VFLR to VF %d\n", vf);
8463 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8464 /* Free device reference count */
8465 pci_dev_put(vfdev);
83c61fa9
GR		 8466 }
8467
8468 pci_cleanup_aer_uncorrect_error_status(pdev);
8469 }
8470
8471 /*
8472 * Even though the error may have occurred on the other port
8473 * we still need to increment the vf error reference count for
8474 * both ports because the I/O resume function will be called
8475 * for both of them.
8476 */
8477 adapter->vferr_refcount++;
8478
8479 return PCI_ERS_RESULT_RECOVERED;
8480
8481skip_bad_vf_detection:
8482#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8483 netif_device_detach(netdev);
8484
3044b8d1
BL		 8485 if (state == pci_channel_io_perm_failure)
8486 return PCI_ERS_RESULT_DISCONNECT;
8487
9a799d71
AK		 8488 if (netif_running(netdev))
8489 ixgbe_down(adapter);
8490 pci_disable_device(pdev);
8491
b4617240 8492 /* Request a slot reset. */
9a799d71
AK		 8493 return PCI_ERS_RESULT_NEED_RESET;
8494}
8495
8496/**
8497 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8498 * @pdev: Pointer to PCI device
8499 *
8500 * Restart the card from scratch, as if from a cold-boot.
8501 */
8502static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8503{
c60fbb00 8504 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8505 pci_ers_result_t result;
8506 int err;
9a799d71 8507
9ce77666 8508 if (pci_enable_device_mem(pdev)) {
396e799c 8509 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8510 result = PCI_ERS_RESULT_DISCONNECT;
8511 } else {
0391bbe3 8512 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8513 pci_set_master(pdev);
8514 pci_restore_state(pdev);
c0e1f68b 8515 pci_save_state(pdev);
9a799d71 8516
dd4d8ca6 8517 pci_wake_from_d3(pdev, false);
9a799d71 8518
6fabd715 8519 ixgbe_reset(adapter);
88512539 8520 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8521 result = PCI_ERS_RESULT_RECOVERED;
8522 }
8523
8524 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8525 if (err) {
849c4542
ET		 8526 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8527 "failed 0x%0x\n", err);
6fabd715
PWJ		 8528 /* non-fatal, continue */
8529 }
9a799d71 8530
6fabd715 8531 return result;
9a799d71
AK		 8532}
8533
8534/**
8535 * ixgbe_io_resume - called when traffic can start flowing again.
8536 * @pdev: Pointer to PCI device
8537 *
8538 * This callback is called when the error recovery driver tells us that
8539 * its OK to resume normal operation.
8540 */
8541static void ixgbe_io_resume(struct pci_dev *pdev)
8542{
c60fbb00
AD		 8543 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8544 struct net_device *netdev = adapter->netdev;
9a799d71 8545
83c61fa9
GR		 8546#ifdef CONFIG_PCI_IOV
8547 if (adapter->vferr_refcount) {
8548 e_info(drv, "Resuming after VF err\n");
8549 adapter->vferr_refcount--;
8550 return;
8551 }
8552
8553#endif
c7ccde0f
AD		 8554 if (netif_running(netdev))
8555 ixgbe_up(adapter);
9a799d71
AK		 8556
8557 netif_device_attach(netdev);
9a799d71
AK		 8558}
8559
3646f0e5 8560static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8561 .error_detected = ixgbe_io_error_detected,
8562 .slot_reset = ixgbe_io_slot_reset,
8563 .resume = ixgbe_io_resume,
8564};
8565
8566static struct pci_driver ixgbe_driver = {
8567 .name = ixgbe_driver_name,
8568 .id_table = ixgbe_pci_tbl,
8569 .probe = ixgbe_probe,
9f9a12f8 8570 .remove = ixgbe_remove,
9a799d71
AK		 8571#ifdef CONFIG_PM
8572 .suspend = ixgbe_suspend,
8573 .resume = ixgbe_resume,
8574#endif
8575 .shutdown = ixgbe_shutdown,
da36b647 8576 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8577 .err_handler = &ixgbe_err_handler
8578};
8579
8580/**
8581 * ixgbe_init_module - Driver Registration Routine
8582 *
8583 * ixgbe_init_module is the first routine called when the driver is
8584 * loaded. All it does is register with the PCI subsystem.
8585 **/
8586static int __init ixgbe_init_module(void)
8587{
8588 int ret;
c7689578 8589 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8590 pr_info("%s\n", ixgbe_copyright);
9a799d71 8591
00949167 8592 ixgbe_dbg_init();
00949167 8593
f01fc1a8
JK		 8594 ret = pci_register_driver(&ixgbe_driver);
8595 if (ret) {
f01fc1a8 8596 ixgbe_dbg_exit();
f01fc1a8
JK		 8597 return ret;
8598 }
8599
5dd2d332 8600#ifdef CONFIG_IXGBE_DCA
bd0362dd 8601 dca_register_notify(&dca_notifier);
bd0362dd 8602#endif
5dd2d332 8603
f01fc1a8 8604 return 0;
9a799d71 8605}
b4617240 8606
9a799d71
AK		 8607module_init(ixgbe_init_module);
8608
8609/**
8610 * ixgbe_exit_module - Driver Exit Cleanup Routine
8611 *
8612 * ixgbe_exit_module is called just before the driver is removed
8613 * from memory.
8614 **/
8615static void __exit ixgbe_exit_module(void)
8616{
5dd2d332 8617#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8618 dca_unregister_notify(&dca_notifier);
8619#endif
9a799d71 8620 pci_unregister_driver(&ixgbe_driver);
00949167 8621
00949167 8622 ixgbe_dbg_exit();
00949167 8623
1a51502b 8624 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8625}
bd0362dd 8626
5dd2d332 8627#ifdef CONFIG_IXGBE_DCA
bd0362dd 8628static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8629 void *p)
bd0362dd
JC		 8630{
8631 int ret_val;
8632
8633 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8634 __ixgbe_notify_dca);
bd0362dd
JC		 8635
8636 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8637}
b453368d 8638
5dd2d332 8639#endif /* CONFIG_IXGBE_DCA */
849c4542 8640
9a799d71
AK		 8641module_exit(ixgbe_exit_module);
8642
8643/* ixgbe_main.c */
Linux kernel - Deliverables
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