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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
eacd73f7 | 48 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
49 | |
50 | #include "ixgbe.h" | |
51 | #include "ixgbe_common.h" | |
ee5f784a | 52 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 53 | #include "ixgbe_sriov.h" |
9a799d71 AK |
54 | |
55 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 56 | static const char ixgbe_driver_string[] = |
e8e9f696 | 57 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
ea81875a NP |
58 | char ixgbe_default_device_descr[] = |
59 | "Intel(R) 10 Gigabit Network Connection"; | |
75e3d3c6 | 60 | #define MAJ 3 |
19d478bb DS |
61 | #define MIN 6 |
62 | #define BUILD 7 | |
75e3d3c6 | 63 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
a38a104d | 64 | __stringify(BUILD) "-k" |
9c8eb720 | 65 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 66 | static const char ixgbe_copyright[] = |
94971820 | 67 | "Copyright (c) 1999-2012 Intel Corporation."; |
9a799d71 AK |
68 | |
69 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 70 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 71 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 72 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
73 | }; |
74 | ||
75 | /* ixgbe_pci_tbl - PCI Device ID Table | |
76 | * | |
77 | * Wildcard entries (PCI_ANY_ID) should come last | |
78 | * Last entry must be all 0s | |
79 | * | |
80 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
81 | * Class, Class Mask, private data (not used) } | |
82 | */ | |
a3aa1884 | 83 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
84 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
86 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
88 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
7d145282 | 110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
9a799d71 AK |
112 | /* required last entry */ |
113 | {0, } | |
114 | }; | |
115 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
116 | ||
5dd2d332 | 117 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 118 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 119 | void *p); |
bd0362dd JC |
120 | static struct notifier_block dca_notifier = { |
121 | .notifier_call = ixgbe_notify_dca, | |
122 | .next = NULL, | |
123 | .priority = 0 | |
124 | }; | |
125 | #endif | |
126 | ||
1cdd1ec8 GR |
127 | #ifdef CONFIG_PCI_IOV |
128 | static unsigned int max_vfs; | |
129 | module_param(max_vfs, uint, 0); | |
e8e9f696 JP |
130 | MODULE_PARM_DESC(max_vfs, |
131 | "Maximum number of virtual functions to allocate per physical function"); | |
1cdd1ec8 GR |
132 | #endif /* CONFIG_PCI_IOV */ |
133 | ||
8ef78adc PWJ |
134 | static unsigned int allow_unsupported_sfp; |
135 | module_param(allow_unsupported_sfp, uint, 0); | |
136 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
137 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
138 | ||
9a799d71 AK |
139 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
140 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
141 | MODULE_LICENSE("GPL"); | |
142 | MODULE_VERSION(DRV_VERSION); | |
143 | ||
144 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
145 | ||
7086400d AD |
146 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
147 | { | |
148 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
149 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
150 | schedule_work(&adapter->service_task); | |
151 | } | |
152 | ||
153 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
154 | { | |
155 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
156 | ||
52f33af8 | 157 | /* flush memory to make sure state is correct before next watchdog */ |
7086400d AD |
158 | smp_mb__before_clear_bit(); |
159 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
160 | } | |
161 | ||
dcd79aeb TI |
162 | struct ixgbe_reg_info { |
163 | u32 ofs; | |
164 | char *name; | |
165 | }; | |
166 | ||
167 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
168 | ||
169 | /* General Registers */ | |
170 | {IXGBE_CTRL, "CTRL"}, | |
171 | {IXGBE_STATUS, "STATUS"}, | |
172 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
173 | ||
174 | /* Interrupt Registers */ | |
175 | {IXGBE_EICR, "EICR"}, | |
176 | ||
177 | /* RX Registers */ | |
178 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
179 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
180 | {IXGBE_RDLEN(0), "RDLEN"}, | |
181 | {IXGBE_RDH(0), "RDH"}, | |
182 | {IXGBE_RDT(0), "RDT"}, | |
183 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
184 | {IXGBE_RDBAL(0), "RDBAL"}, | |
185 | {IXGBE_RDBAH(0), "RDBAH"}, | |
186 | ||
187 | /* TX Registers */ | |
188 | {IXGBE_TDBAL(0), "TDBAL"}, | |
189 | {IXGBE_TDBAH(0), "TDBAH"}, | |
190 | {IXGBE_TDLEN(0), "TDLEN"}, | |
191 | {IXGBE_TDH(0), "TDH"}, | |
192 | {IXGBE_TDT(0), "TDT"}, | |
193 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
194 | ||
195 | /* List Terminator */ | |
196 | {} | |
197 | }; | |
198 | ||
199 | ||
200 | /* | |
201 | * ixgbe_regdump - register printout routine | |
202 | */ | |
203 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
204 | { | |
205 | int i = 0, j = 0; | |
206 | char rname[16]; | |
207 | u32 regs[64]; | |
208 | ||
209 | switch (reginfo->ofs) { | |
210 | case IXGBE_SRRCTL(0): | |
211 | for (i = 0; i < 64; i++) | |
212 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
213 | break; | |
214 | case IXGBE_DCA_RXCTRL(0): | |
215 | for (i = 0; i < 64; i++) | |
216 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
217 | break; | |
218 | case IXGBE_RDLEN(0): | |
219 | for (i = 0; i < 64; i++) | |
220 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
221 | break; | |
222 | case IXGBE_RDH(0): | |
223 | for (i = 0; i < 64; i++) | |
224 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
225 | break; | |
226 | case IXGBE_RDT(0): | |
227 | for (i = 0; i < 64; i++) | |
228 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
229 | break; | |
230 | case IXGBE_RXDCTL(0): | |
231 | for (i = 0; i < 64; i++) | |
232 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
233 | break; | |
234 | case IXGBE_RDBAL(0): | |
235 | for (i = 0; i < 64; i++) | |
236 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
237 | break; | |
238 | case IXGBE_RDBAH(0): | |
239 | for (i = 0; i < 64; i++) | |
240 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
241 | break; | |
242 | case IXGBE_TDBAL(0): | |
243 | for (i = 0; i < 64; i++) | |
244 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
245 | break; | |
246 | case IXGBE_TDBAH(0): | |
247 | for (i = 0; i < 64; i++) | |
248 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
249 | break; | |
250 | case IXGBE_TDLEN(0): | |
251 | for (i = 0; i < 64; i++) | |
252 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
253 | break; | |
254 | case IXGBE_TDH(0): | |
255 | for (i = 0; i < 64; i++) | |
256 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
257 | break; | |
258 | case IXGBE_TDT(0): | |
259 | for (i = 0; i < 64; i++) | |
260 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
261 | break; | |
262 | case IXGBE_TXDCTL(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
265 | break; | |
266 | default: | |
c7689578 | 267 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
268 | IXGBE_READ_REG(hw, reginfo->ofs)); |
269 | return; | |
270 | } | |
271 | ||
272 | for (i = 0; i < 8; i++) { | |
273 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 274 | pr_err("%-15s", rname); |
dcd79aeb | 275 | for (j = 0; j < 8; j++) |
c7689578 JP |
276 | pr_cont(" %08x", regs[i*8+j]); |
277 | pr_cont("\n"); | |
dcd79aeb TI |
278 | } |
279 | ||
280 | } | |
281 | ||
282 | /* | |
283 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
284 | */ | |
285 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
286 | { | |
287 | struct net_device *netdev = adapter->netdev; | |
288 | struct ixgbe_hw *hw = &adapter->hw; | |
289 | struct ixgbe_reg_info *reginfo; | |
290 | int n = 0; | |
291 | struct ixgbe_ring *tx_ring; | |
729739b7 | 292 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
293 | union ixgbe_adv_tx_desc *tx_desc; |
294 | struct my_u0 { u64 a; u64 b; } *u0; | |
295 | struct ixgbe_ring *rx_ring; | |
296 | union ixgbe_adv_rx_desc *rx_desc; | |
297 | struct ixgbe_rx_buffer *rx_buffer_info; | |
298 | u32 staterr; | |
299 | int i = 0; | |
300 | ||
301 | if (!netif_msg_hw(adapter)) | |
302 | return; | |
303 | ||
304 | /* Print netdevice Info */ | |
305 | if (netdev) { | |
306 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 307 | pr_info("Device Name state " |
dcd79aeb | 308 | "trans_start last_rx\n"); |
c7689578 JP |
309 | pr_info("%-15s %016lX %016lX %016lX\n", |
310 | netdev->name, | |
311 | netdev->state, | |
312 | netdev->trans_start, | |
313 | netdev->last_rx); | |
dcd79aeb TI |
314 | } |
315 | ||
316 | /* Print Registers */ | |
317 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 318 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
319 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
320 | reginfo->name; reginfo++) { | |
321 | ixgbe_regdump(hw, reginfo); | |
322 | } | |
323 | ||
324 | /* Print TX Ring Summary */ | |
325 | if (!netdev || !netif_running(netdev)) | |
326 | goto exit; | |
327 | ||
328 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 329 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
330 | for (n = 0; n < adapter->num_tx_queues; n++) { |
331 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 332 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
d3d00239 | 333 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
dcd79aeb | 334 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
335 | (u64)dma_unmap_addr(tx_buffer, dma), |
336 | dma_unmap_len(tx_buffer, len), | |
337 | tx_buffer->next_to_watch, | |
338 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
339 | } |
340 | ||
341 | /* Print TX Rings */ | |
342 | if (!netif_msg_tx_done(adapter)) | |
343 | goto rx_ring_summary; | |
344 | ||
345 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
346 | ||
347 | /* Transmit Descriptor Formats | |
348 | * | |
349 | * Advanced Transmit Descriptor | |
350 | * +--------------------------------------------------------------+ | |
351 | * 0 | Buffer Address [63:0] | | |
352 | * +--------------------------------------------------------------+ | |
353 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
354 | * +--------------------------------------------------------------+ | |
355 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
356 | */ | |
357 | ||
358 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
359 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
360 | pr_info("------------------------------------\n"); |
361 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
362 | pr_info("------------------------------------\n"); | |
363 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
364 | "[PlPOIdStDDt Ln] [bi->dma ] " |
365 | "leng ntw timestamp bi->skb\n"); | |
366 | ||
367 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 368 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 369 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 370 | u0 = (struct my_u0 *)tx_desc; |
c7689578 | 371 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
d3d00239 | 372 | " %04X %p %016llX %p", i, |
dcd79aeb TI |
373 | le64_to_cpu(u0->a), |
374 | le64_to_cpu(u0->b), | |
729739b7 AD |
375 | (u64)dma_unmap_addr(tx_buffer, dma), |
376 | dma_unmap_len(tx_buffer, len), | |
377 | tx_buffer->next_to_watch, | |
378 | (u64)tx_buffer->time_stamp, | |
379 | tx_buffer->skb); | |
dcd79aeb TI |
380 | if (i == tx_ring->next_to_use && |
381 | i == tx_ring->next_to_clean) | |
c7689578 | 382 | pr_cont(" NTC/U\n"); |
dcd79aeb | 383 | else if (i == tx_ring->next_to_use) |
c7689578 | 384 | pr_cont(" NTU\n"); |
dcd79aeb | 385 | else if (i == tx_ring->next_to_clean) |
c7689578 | 386 | pr_cont(" NTC\n"); |
dcd79aeb | 387 | else |
c7689578 | 388 | pr_cont("\n"); |
dcd79aeb TI |
389 | |
390 | if (netif_msg_pktdata(adapter) && | |
729739b7 | 391 | dma_unmap_len(tx_buffer, len) != 0) |
dcd79aeb TI |
392 | print_hex_dump(KERN_INFO, "", |
393 | DUMP_PREFIX_ADDRESS, 16, 1, | |
729739b7 AD |
394 | phys_to_virt(dma_unmap_addr(tx_buffer, |
395 | dma)), | |
396 | dma_unmap_len(tx_buffer, len), | |
397 | true); | |
dcd79aeb TI |
398 | } |
399 | } | |
400 | ||
401 | /* Print RX Rings Summary */ | |
402 | rx_ring_summary: | |
403 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 404 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
405 | for (n = 0; n < adapter->num_rx_queues; n++) { |
406 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
407 | pr_info("%5d %5X %5X\n", |
408 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
409 | } |
410 | ||
411 | /* Print RX Rings */ | |
412 | if (!netif_msg_rx_status(adapter)) | |
413 | goto exit; | |
414 | ||
415 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
416 | ||
417 | /* Advanced Receive Descriptor (Read) Format | |
418 | * 63 1 0 | |
419 | * +-----------------------------------------------------+ | |
420 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
421 | * +----------------------------------------------+------+ | |
422 | * 8 | Header Buffer Address [63:1] | DD | | |
423 | * +-----------------------------------------------------+ | |
424 | * | |
425 | * | |
426 | * Advanced Receive Descriptor (Write-Back) Format | |
427 | * | |
428 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
429 | * +------------------------------------------------------+ | |
430 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
431 | * | Checksum Ident | | | | Type | Type | | |
432 | * +------------------------------------------------------+ | |
433 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
434 | * +------------------------------------------------------+ | |
435 | * 63 48 47 32 31 20 19 0 | |
436 | */ | |
437 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
438 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
439 | pr_info("------------------------------------\n"); |
440 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
441 | pr_info("------------------------------------\n"); | |
442 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
443 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
444 | "<-- Adv Rx Read format\n"); | |
c7689578 | 445 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
446 | "[vl er S cks ln] ---------------- [bi->skb] " |
447 | "<-- Adv Rx Write-Back format\n"); | |
448 | ||
449 | for (i = 0; i < rx_ring->count; i++) { | |
450 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 451 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
452 | u0 = (struct my_u0 *)rx_desc; |
453 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
454 | if (staterr & IXGBE_RXD_STAT_DD) { | |
455 | /* Descriptor Done */ | |
c7689578 | 456 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
457 | "%016llX ---------------- %p", i, |
458 | le64_to_cpu(u0->a), | |
459 | le64_to_cpu(u0->b), | |
460 | rx_buffer_info->skb); | |
461 | } else { | |
c7689578 | 462 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
463 | "%016llX %016llX %p", i, |
464 | le64_to_cpu(u0->a), | |
465 | le64_to_cpu(u0->b), | |
466 | (u64)rx_buffer_info->dma, | |
467 | rx_buffer_info->skb); | |
468 | ||
469 | if (netif_msg_pktdata(adapter)) { | |
470 | print_hex_dump(KERN_INFO, "", | |
471 | DUMP_PREFIX_ADDRESS, 16, 1, | |
472 | phys_to_virt(rx_buffer_info->dma), | |
f800326d | 473 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
474 | } |
475 | } | |
476 | ||
477 | if (i == rx_ring->next_to_use) | |
c7689578 | 478 | pr_cont(" NTU\n"); |
dcd79aeb | 479 | else if (i == rx_ring->next_to_clean) |
c7689578 | 480 | pr_cont(" NTC\n"); |
dcd79aeb | 481 | else |
c7689578 | 482 | pr_cont("\n"); |
dcd79aeb TI |
483 | |
484 | } | |
485 | } | |
486 | ||
487 | exit: | |
488 | return; | |
489 | } | |
490 | ||
5eba3699 AV |
491 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
492 | { | |
493 | u32 ctrl_ext; | |
494 | ||
495 | /* Let firmware take over control of h/w */ | |
496 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
497 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 498 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
499 | } |
500 | ||
501 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
502 | { | |
503 | u32 ctrl_ext; | |
504 | ||
505 | /* Let firmware know the driver has taken over */ | |
506 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
507 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 508 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 509 | } |
9a799d71 | 510 | |
e8e26350 PW |
511 | /* |
512 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
513 | * @adapter: pointer to adapter struct | |
514 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
515 | * @queue: queue to map the corresponding interrupt to | |
516 | * @msix_vector: the vector to map to the corresponding queue | |
517 | * | |
518 | */ | |
519 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 520 | u8 queue, u8 msix_vector) |
9a799d71 AK |
521 | { |
522 | u32 ivar, index; | |
e8e26350 PW |
523 | struct ixgbe_hw *hw = &adapter->hw; |
524 | switch (hw->mac.type) { | |
525 | case ixgbe_mac_82598EB: | |
526 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
527 | if (direction == -1) | |
528 | direction = 0; | |
529 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
530 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
531 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
532 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
533 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
534 | break; | |
535 | case ixgbe_mac_82599EB: | |
b93a2226 | 536 | case ixgbe_mac_X540: |
e8e26350 PW |
537 | if (direction == -1) { |
538 | /* other causes */ | |
539 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
540 | index = ((queue & 1) * 8); | |
541 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
542 | ivar &= ~(0xFF << index); | |
543 | ivar |= (msix_vector << index); | |
544 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
545 | break; | |
546 | } else { | |
547 | /* tx or rx causes */ | |
548 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
549 | index = ((16 * (queue & 1)) + (8 * direction)); | |
550 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
551 | ivar &= ~(0xFF << index); | |
552 | ivar |= (msix_vector << index); | |
553 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
554 | break; | |
555 | } | |
556 | default: | |
557 | break; | |
558 | } | |
9a799d71 AK |
559 | } |
560 | ||
fe49f04a | 561 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 562 | u64 qmask) |
fe49f04a AD |
563 | { |
564 | u32 mask; | |
565 | ||
bd508178 AD |
566 | switch (adapter->hw.mac.type) { |
567 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
568 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
569 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
570 | break; |
571 | case ixgbe_mac_82599EB: | |
b93a2226 | 572 | case ixgbe_mac_X540: |
fe49f04a AD |
573 | mask = (qmask & 0xFFFFFFFF); |
574 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
575 | mask = (qmask >> 32); | |
576 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
577 | break; |
578 | default: | |
579 | break; | |
fe49f04a AD |
580 | } |
581 | } | |
582 | ||
729739b7 AD |
583 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
584 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 585 | { |
729739b7 AD |
586 | if (tx_buffer->skb) { |
587 | dev_kfree_skb_any(tx_buffer->skb); | |
588 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 589 | dma_unmap_single(ring->dev, |
729739b7 AD |
590 | dma_unmap_addr(tx_buffer, dma), |
591 | dma_unmap_len(tx_buffer, len), | |
592 | DMA_TO_DEVICE); | |
593 | } else if (dma_unmap_len(tx_buffer, len)) { | |
594 | dma_unmap_page(ring->dev, | |
595 | dma_unmap_addr(tx_buffer, dma), | |
596 | dma_unmap_len(tx_buffer, len), | |
597 | DMA_TO_DEVICE); | |
e5a43549 | 598 | } |
729739b7 AD |
599 | tx_buffer->next_to_watch = NULL; |
600 | tx_buffer->skb = NULL; | |
601 | dma_unmap_len_set(tx_buffer, len, 0); | |
602 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
603 | } |
604 | ||
c84d324c JF |
605 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) |
606 | { | |
607 | struct ixgbe_hw *hw = &adapter->hw; | |
608 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
609 | u32 data = 0; | |
610 | u32 xoff[8] = {0}; | |
611 | int i; | |
612 | ||
613 | if ((hw->fc.current_mode == ixgbe_fc_full) || | |
614 | (hw->fc.current_mode == ixgbe_fc_rx_pause)) { | |
615 | switch (hw->mac.type) { | |
616 | case ixgbe_mac_82598EB: | |
617 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
6837e895 PW |
618 | break; |
619 | default: | |
c84d324c JF |
620 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); |
621 | } | |
622 | hwstats->lxoffrxc += data; | |
623 | ||
624 | /* refill credits (no tx hang) if we received xoff */ | |
625 | if (!data) | |
626 | return; | |
627 | ||
628 | for (i = 0; i < adapter->num_tx_queues; i++) | |
629 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
630 | &adapter->tx_ring[i]->state); | |
631 | return; | |
632 | } else if (!(adapter->dcb_cfg.pfc_mode_enable)) | |
633 | return; | |
634 | ||
635 | /* update stats for each tc, only valid with PFC enabled */ | |
636 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
637 | switch (hw->mac.type) { | |
638 | case ixgbe_mac_82598EB: | |
639 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 640 | break; |
c84d324c JF |
641 | default: |
642 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 643 | } |
c84d324c JF |
644 | hwstats->pxoffrxc[i] += xoff[i]; |
645 | } | |
646 | ||
647 | /* disarm tx queues that have received xoff frames */ | |
648 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
649 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
fb5475ff | 650 | u8 tc = tx_ring->dcb_tc; |
c84d324c JF |
651 | |
652 | if (xoff[tc]) | |
653 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 654 | } |
26f23d82 YZ |
655 | } |
656 | ||
c84d324c | 657 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 658 | { |
7d7ce682 | 659 | return ring->stats.packets; |
c84d324c JF |
660 | } |
661 | ||
662 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
663 | { | |
664 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 665 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 666 | |
c84d324c JF |
667 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
668 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
669 | ||
670 | if (head != tail) | |
671 | return (head < tail) ? | |
672 | tail - head : (tail + ring->count - head); | |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
677 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
678 | { | |
679 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
680 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
681 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
682 | bool ret = false; | |
683 | ||
7d637bcc | 684 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
685 | |
686 | /* | |
687 | * Check for a hung queue, but be thorough. This verifies | |
688 | * that a transmit has been completed since the previous | |
689 | * check AND there is at least one packet pending. The | |
690 | * ARMED bit is set to indicate a potential hang. The | |
691 | * bit is cleared if a pause frame is received to remove | |
692 | * false hang detection due to PFC or 802.3x frames. By | |
693 | * requiring this to fail twice we avoid races with | |
694 | * pfc clearing the ARMED bit and conditions where we | |
695 | * run the check_tx_hang logic with a transmit completion | |
696 | * pending but without time to complete it yet. | |
697 | */ | |
698 | if ((tx_done_old == tx_done) && tx_pending) { | |
699 | /* make sure it is true for two checks in a row */ | |
700 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
701 | &tx_ring->state); | |
702 | } else { | |
703 | /* update completed stats and continue */ | |
704 | tx_ring->tx_stats.tx_done_old = tx_done; | |
705 | /* reset the countdown */ | |
706 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
707 | } |
708 | ||
c84d324c | 709 | return ret; |
9a799d71 AK |
710 | } |
711 | ||
c83c6cbd AD |
712 | /** |
713 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
714 | * @adapter: driver private struct | |
715 | **/ | |
716 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
717 | { | |
718 | ||
719 | /* Do the reset outside of interrupt context */ | |
720 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
721 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
722 | ixgbe_service_event_schedule(adapter); | |
723 | } | |
724 | } | |
e01c31a5 | 725 | |
9a799d71 AK |
726 | /** |
727 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 728 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 729 | * @tx_ring: tx ring to clean |
9a799d71 | 730 | **/ |
fe49f04a | 731 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 732 | struct ixgbe_ring *tx_ring) |
9a799d71 | 733 | { |
fe49f04a | 734 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
735 | struct ixgbe_tx_buffer *tx_buffer; |
736 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 737 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 738 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
739 | unsigned int i = tx_ring->next_to_clean; |
740 | ||
741 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
742 | return true; | |
9a799d71 | 743 | |
d3d00239 | 744 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 745 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 746 | i -= tx_ring->count; |
12207e49 | 747 | |
729739b7 | 748 | do { |
d3d00239 AD |
749 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
750 | ||
751 | /* if next_to_watch is not set then there is no work pending */ | |
752 | if (!eop_desc) | |
753 | break; | |
754 | ||
7f83a9e6 AD |
755 | /* prevent any other reads prior to eop_desc */ |
756 | rmb(); | |
757 | ||
d3d00239 AD |
758 | /* if DD is not set pending work has not been completed */ |
759 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
760 | break; | |
8ad494b0 | 761 | |
d3d00239 AD |
762 | /* clear next_to_watch to prevent false hangs */ |
763 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 764 | |
091a6246 AD |
765 | /* update the statistics for this packet */ |
766 | total_bytes += tx_buffer->bytecount; | |
767 | total_packets += tx_buffer->gso_segs; | |
768 | ||
fd0db0ed AD |
769 | /* free the skb */ |
770 | dev_kfree_skb_any(tx_buffer->skb); | |
771 | ||
729739b7 AD |
772 | /* unmap skb header data */ |
773 | dma_unmap_single(tx_ring->dev, | |
774 | dma_unmap_addr(tx_buffer, dma), | |
775 | dma_unmap_len(tx_buffer, len), | |
776 | DMA_TO_DEVICE); | |
777 | ||
fd0db0ed AD |
778 | /* clear tx_buffer data */ |
779 | tx_buffer->skb = NULL; | |
729739b7 | 780 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 781 | |
729739b7 AD |
782 | /* unmap remaining buffers */ |
783 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
784 | tx_buffer++; |
785 | tx_desc++; | |
8ad494b0 | 786 | i++; |
729739b7 AD |
787 | if (unlikely(!i)) { |
788 | i -= tx_ring->count; | |
d3d00239 | 789 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 790 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 791 | } |
e01c31a5 | 792 | |
729739b7 AD |
793 | /* unmap any remaining paged data */ |
794 | if (dma_unmap_len(tx_buffer, len)) { | |
795 | dma_unmap_page(tx_ring->dev, | |
796 | dma_unmap_addr(tx_buffer, dma), | |
797 | dma_unmap_len(tx_buffer, len), | |
798 | DMA_TO_DEVICE); | |
799 | dma_unmap_len_set(tx_buffer, len, 0); | |
800 | } | |
801 | } | |
802 | ||
803 | /* move us one more past the eop_desc for start of next pkt */ | |
804 | tx_buffer++; | |
805 | tx_desc++; | |
806 | i++; | |
807 | if (unlikely(!i)) { | |
808 | i -= tx_ring->count; | |
809 | tx_buffer = tx_ring->tx_buffer_info; | |
810 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
811 | } | |
812 | ||
813 | /* issue prefetch for next Tx descriptor */ | |
814 | prefetch(tx_desc); | |
12207e49 | 815 | |
729739b7 AD |
816 | /* update budget accounting */ |
817 | budget--; | |
818 | } while (likely(budget)); | |
819 | ||
820 | i += tx_ring->count; | |
9a799d71 | 821 | tx_ring->next_to_clean = i; |
d3d00239 | 822 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 823 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 824 | tx_ring->stats.packets += total_packets; |
d3d00239 | 825 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
826 | q_vector->tx.total_bytes += total_bytes; |
827 | q_vector->tx.total_packets += total_packets; | |
b953799e | 828 | |
c84d324c JF |
829 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
830 | /* schedule immediate reset if we believe we hung */ | |
831 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
832 | e_err(drv, "Detected Tx Unit Hang\n" |
833 | " Tx Queue <%d>\n" | |
834 | " TDH, TDT <%x>, <%x>\n" | |
835 | " next_to_use <%x>\n" | |
836 | " next_to_clean <%x>\n" | |
837 | "tx_buffer_info[next_to_clean]\n" | |
838 | " time_stamp <%lx>\n" | |
839 | " jiffies <%lx>\n", | |
840 | tx_ring->queue_index, | |
841 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
842 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
843 | tx_ring->next_to_use, i, |
844 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
845 | |
846 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
847 | ||
848 | e_info(probe, | |
849 | "tx hang %d detected on queue %d, resetting adapter\n", | |
850 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
851 | ||
b953799e | 852 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 853 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
854 | |
855 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 856 | return true; |
b953799e | 857 | } |
9a799d71 | 858 | |
b2d96e0a AD |
859 | netdev_tx_completed_queue(txring_txq(tx_ring), |
860 | total_packets, total_bytes); | |
861 | ||
e092be60 | 862 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 863 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 864 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
865 | /* Make sure that anybody stopping the queue after this |
866 | * sees the new next_to_clean. | |
867 | */ | |
868 | smp_mb(); | |
729739b7 AD |
869 | if (__netif_subqueue_stopped(tx_ring->netdev, |
870 | tx_ring->queue_index) | |
871 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
872 | netif_wake_subqueue(tx_ring->netdev, | |
873 | tx_ring->queue_index); | |
5b7da515 | 874 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 875 | } |
e092be60 | 876 | } |
9a799d71 | 877 | |
59224555 | 878 | return !!budget; |
9a799d71 AK |
879 | } |
880 | ||
5dd2d332 | 881 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
882 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
883 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 884 | int cpu) |
bd0362dd | 885 | { |
33cf09c9 | 886 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
887 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
888 | u16 reg_offset; | |
33cf09c9 | 889 | |
33cf09c9 AD |
890 | switch (hw->mac.type) { |
891 | case ixgbe_mac_82598EB: | |
bdda1a61 | 892 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
893 | break; |
894 | case ixgbe_mac_82599EB: | |
b93a2226 | 895 | case ixgbe_mac_X540: |
bdda1a61 AD |
896 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
897 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
898 | break; |
899 | default: | |
bdda1a61 AD |
900 | /* for unknown hardware do not write register */ |
901 | return; | |
bd0362dd | 902 | } |
bdda1a61 AD |
903 | |
904 | /* | |
905 | * We can enable relaxed ordering for reads, but not writes when | |
906 | * DCA is enabled. This is due to a known issue in some chipsets | |
907 | * which will cause the DCA tag to be cleared. | |
908 | */ | |
909 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
910 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
911 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
912 | ||
913 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
914 | } |
915 | ||
bdda1a61 AD |
916 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
917 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 918 | int cpu) |
bd0362dd | 919 | { |
33cf09c9 | 920 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
921 | u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); |
922 | u8 reg_idx = rx_ring->reg_idx; | |
923 | ||
33cf09c9 AD |
924 | |
925 | switch (hw->mac.type) { | |
33cf09c9 | 926 | case ixgbe_mac_82599EB: |
b93a2226 | 927 | case ixgbe_mac_X540: |
bdda1a61 | 928 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
929 | break; |
930 | default: | |
931 | break; | |
932 | } | |
bdda1a61 AD |
933 | |
934 | /* | |
935 | * We can enable relaxed ordering for reads, but not writes when | |
936 | * DCA is enabled. This is due to a known issue in some chipsets | |
937 | * which will cause the DCA tag to be cleared. | |
938 | */ | |
939 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
940 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | | |
941 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; | |
942 | ||
943 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
944 | } |
945 | ||
946 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
947 | { | |
948 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 949 | struct ixgbe_ring *ring; |
bd0362dd | 950 | int cpu = get_cpu(); |
bd0362dd | 951 | |
33cf09c9 AD |
952 | if (q_vector->cpu == cpu) |
953 | goto out_no_update; | |
954 | ||
a557928e | 955 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 956 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 957 | |
a557928e | 958 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 959 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
960 | |
961 | q_vector->cpu = cpu; | |
962 | out_no_update: | |
bd0362dd JC |
963 | put_cpu(); |
964 | } | |
965 | ||
966 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
967 | { | |
33cf09c9 | 968 | int num_q_vectors; |
bd0362dd JC |
969 | int i; |
970 | ||
971 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
972 | return; | |
973 | ||
e35ec126 AD |
974 | /* always use CB2 mode, difference is masked in the CB driver */ |
975 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
976 | ||
33cf09c9 AD |
977 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
978 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
979 | else | |
980 | num_q_vectors = 1; | |
981 | ||
982 | for (i = 0; i < num_q_vectors; i++) { | |
983 | adapter->q_vector[i]->cpu = -1; | |
984 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
985 | } |
986 | } | |
987 | ||
988 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
989 | { | |
c60fbb00 | 990 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
991 | unsigned long event = *(unsigned long *)data; |
992 | ||
2a72c31e | 993 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
994 | return 0; |
995 | ||
bd0362dd JC |
996 | switch (event) { |
997 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
998 | /* if we're already enabled, don't do it again */ |
999 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1000 | break; | |
652f093f | 1001 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1002 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1003 | ixgbe_setup_dca(adapter); |
1004 | break; | |
1005 | } | |
1006 | /* Fall Through since DCA is disabled. */ | |
1007 | case DCA_PROVIDER_REMOVE: | |
1008 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1009 | dca_remove_requester(dev); | |
1010 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1011 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1012 | } | |
1013 | break; | |
1014 | } | |
1015 | ||
652f093f | 1016 | return 0; |
bd0362dd | 1017 | } |
67a74ee2 | 1018 | |
bdda1a61 | 1019 | #endif /* CONFIG_IXGBE_DCA */ |
8a0da21b AD |
1020 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1021 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1022 | struct sk_buff *skb) |
1023 | { | |
8a0da21b AD |
1024 | if (ring->netdev->features & NETIF_F_RXHASH) |
1025 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
67a74ee2 ET |
1026 | } |
1027 | ||
f800326d | 1028 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1029 | /** |
1030 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
1031 | * @adapter: address of board private structure | |
1032 | * @rx_desc: advanced rx descriptor | |
1033 | * | |
1034 | * Returns : true if it is FCoE pkt | |
1035 | */ | |
1036 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter, | |
1037 | union ixgbe_adv_rx_desc *rx_desc) | |
1038 | { | |
1039 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1040 | ||
1041 | return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
1042 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == | |
1043 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1044 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1045 | } | |
1046 | ||
f800326d | 1047 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1048 | /** |
1049 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1050 | * @ring: structure containing ring specific data |
1051 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1052 | * @skb: skb currently being received and modified |
1053 | **/ | |
8a0da21b | 1054 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1055 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1056 | struct sk_buff *skb) |
9a799d71 | 1057 | { |
8a0da21b | 1058 | skb_checksum_none_assert(skb); |
9a799d71 | 1059 | |
712744be | 1060 | /* Rx csum disabled */ |
8a0da21b | 1061 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1062 | return; |
e59bd25d AV |
1063 | |
1064 | /* if IP and error */ | |
f56e0cb1 AD |
1065 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1066 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1067 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1068 | return; |
1069 | } | |
e59bd25d | 1070 | |
f56e0cb1 | 1071 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1072 | return; |
1073 | ||
f56e0cb1 | 1074 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
f800326d | 1075 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
8bae1b2b DS |
1076 | |
1077 | /* | |
1078 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1079 | * checksum errors. | |
1080 | */ | |
8a0da21b AD |
1081 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1082 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1083 | return; |
1084 | ||
8a0da21b | 1085 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1086 | return; |
1087 | } | |
1088 | ||
9a799d71 | 1089 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1090 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1091 | } |
1092 | ||
84ea2591 | 1093 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 | 1094 | { |
f56e0cb1 | 1095 | rx_ring->next_to_use = val; |
f800326d AD |
1096 | |
1097 | /* update next to alloc since we have filled the ring */ | |
1098 | rx_ring->next_to_alloc = val; | |
e8e26350 PW |
1099 | /* |
1100 | * Force memory writes to complete before letting h/w | |
1101 | * know there are new descriptors to fetch. (Only | |
1102 | * applicable for weak-ordered memory model archs, | |
1103 | * such as IA-64). | |
1104 | */ | |
1105 | wmb(); | |
84ea2591 | 1106 | writel(val, rx_ring->tail); |
e8e26350 PW |
1107 | } |
1108 | ||
f990b79b AD |
1109 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1110 | struct ixgbe_rx_buffer *bi) | |
1111 | { | |
1112 | struct page *page = bi->page; | |
f800326d | 1113 | dma_addr_t dma = bi->dma; |
f990b79b | 1114 | |
f800326d AD |
1115 | /* since we are recycling buffers we should seldom need to alloc */ |
1116 | if (likely(dma)) | |
f990b79b AD |
1117 | return true; |
1118 | ||
f800326d AD |
1119 | /* alloc new page for storage */ |
1120 | if (likely(!page)) { | |
1121 | page = alloc_pages(GFP_ATOMIC | __GFP_COLD, | |
1122 | ixgbe_rx_pg_order(rx_ring)); | |
f990b79b AD |
1123 | if (unlikely(!page)) { |
1124 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1125 | return false; | |
1126 | } | |
f800326d | 1127 | bi->page = page; |
f990b79b AD |
1128 | } |
1129 | ||
f800326d AD |
1130 | /* map page for use */ |
1131 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1132 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1133 | ||
1134 | /* | |
1135 | * if mapping failed free memory back to system since | |
1136 | * there isn't much point in holding memory we can't use | |
1137 | */ | |
1138 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
1139 | put_page(page); | |
1140 | bi->page = NULL; | |
f990b79b | 1141 | |
f990b79b AD |
1142 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1143 | return false; | |
1144 | } | |
1145 | ||
f800326d AD |
1146 | bi->dma = dma; |
1147 | bi->page_offset ^= ixgbe_rx_bufsz(rx_ring); | |
1148 | ||
f990b79b AD |
1149 | return true; |
1150 | } | |
1151 | ||
9a799d71 | 1152 | /** |
f990b79b | 1153 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1154 | * @rx_ring: ring to place buffers on |
1155 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1156 | **/ |
fc77dc3c | 1157 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1158 | { |
9a799d71 | 1159 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1160 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1161 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1162 | |
f800326d AD |
1163 | /* nothing to do */ |
1164 | if (!cleaned_count) | |
fc77dc3c AD |
1165 | return; |
1166 | ||
e4f74028 | 1167 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1168 | bi = &rx_ring->rx_buffer_info[i]; |
1169 | i -= rx_ring->count; | |
9a799d71 | 1170 | |
f800326d AD |
1171 | do { |
1172 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1173 | break; |
d5f398ed | 1174 | |
f800326d AD |
1175 | /* |
1176 | * Refresh the desc even if buffer_addrs didn't change | |
1177 | * because each write-back erases this info. | |
1178 | */ | |
1179 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1180 | |
f990b79b AD |
1181 | rx_desc++; |
1182 | bi++; | |
9a799d71 | 1183 | i++; |
f990b79b | 1184 | if (unlikely(!i)) { |
e4f74028 | 1185 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1186 | bi = rx_ring->rx_buffer_info; |
1187 | i -= rx_ring->count; | |
1188 | } | |
1189 | ||
1190 | /* clear the hdr_addr for the next_to_use descriptor */ | |
1191 | rx_desc->read.hdr_addr = 0; | |
f800326d AD |
1192 | |
1193 | cleaned_count--; | |
1194 | } while (cleaned_count); | |
7c6e0a43 | 1195 | |
f990b79b AD |
1196 | i += rx_ring->count; |
1197 | ||
f56e0cb1 | 1198 | if (rx_ring->next_to_use != i) |
84ea2591 | 1199 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1200 | } |
1201 | ||
1d2024f6 AD |
1202 | /** |
1203 | * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE | |
1204 | * @data: pointer to the start of the headers | |
1205 | * @max_len: total length of section to find headers in | |
1206 | * | |
1207 | * This function is meant to determine the length of headers that will | |
1208 | * be recognized by hardware for LRO, GRO, and RSC offloads. The main | |
1209 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
1210 | * packets so that we can do basic things like calculating the gso_size | |
1211 | * based on the average data per packet. | |
1212 | **/ | |
1213 | static unsigned int ixgbe_get_headlen(unsigned char *data, | |
1214 | unsigned int max_len) | |
1215 | { | |
1216 | union { | |
1217 | unsigned char *network; | |
1218 | /* l2 headers */ | |
1219 | struct ethhdr *eth; | |
1220 | struct vlan_hdr *vlan; | |
1221 | /* l3 headers */ | |
1222 | struct iphdr *ipv4; | |
1223 | } hdr; | |
1224 | __be16 protocol; | |
1225 | u8 nexthdr = 0; /* default to not TCP */ | |
1226 | u8 hlen; | |
1227 | ||
1228 | /* this should never happen, but better safe than sorry */ | |
1229 | if (max_len < ETH_HLEN) | |
1230 | return max_len; | |
1231 | ||
1232 | /* initialize network frame pointer */ | |
1233 | hdr.network = data; | |
1234 | ||
1235 | /* set first protocol and move network header forward */ | |
1236 | protocol = hdr.eth->h_proto; | |
1237 | hdr.network += ETH_HLEN; | |
1238 | ||
1239 | /* handle any vlan tag if present */ | |
1240 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
1241 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
1242 | return max_len; | |
1243 | ||
1244 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
1245 | hdr.network += VLAN_HLEN; | |
1246 | } | |
1247 | ||
1248 | /* handle L3 protocols */ | |
1249 | if (protocol == __constant_htons(ETH_P_IP)) { | |
1250 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
1251 | return max_len; | |
1252 | ||
1253 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1254 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1255 | ||
1256 | /* verify hlen meets minimum size requirements */ | |
1257 | if (hlen < sizeof(struct iphdr)) | |
1258 | return hdr.network - data; | |
1259 | ||
1260 | /* record next protocol */ | |
1261 | nexthdr = hdr.ipv4->protocol; | |
1262 | hdr.network += hlen; | |
f800326d | 1263 | #ifdef IXGBE_FCOE |
1d2024f6 AD |
1264 | } else if (protocol == __constant_htons(ETH_P_FCOE)) { |
1265 | if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) | |
1266 | return max_len; | |
1267 | hdr.network += FCOE_HEADER_LEN; | |
1268 | #endif | |
1269 | } else { | |
1270 | return hdr.network - data; | |
1271 | } | |
1272 | ||
1273 | /* finally sort out TCP */ | |
1274 | if (nexthdr == IPPROTO_TCP) { | |
1275 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
1276 | return max_len; | |
1277 | ||
1278 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
1279 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
1280 | ||
1281 | /* verify hlen meets minimum size requirements */ | |
1282 | if (hlen < sizeof(struct tcphdr)) | |
1283 | return hdr.network - data; | |
1284 | ||
1285 | hdr.network += hlen; | |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * If everything has gone correctly hdr.network should be the | |
1290 | * data section of the packet and will be the end of the header. | |
1291 | * If not then it probably represents the end of the last recognized | |
1292 | * header. | |
1293 | */ | |
1294 | if ((hdr.network - data) < max_len) | |
1295 | return hdr.network - data; | |
1296 | else | |
1297 | return max_len; | |
1298 | } | |
1299 | ||
4c1975d7 AD |
1300 | static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring, |
1301 | union ixgbe_adv_rx_desc *rx_desc, | |
1302 | struct sk_buff *skb) | |
aa80175a | 1303 | { |
4c1975d7 AD |
1304 | __le32 rsc_enabled; |
1305 | u32 rsc_cnt; | |
1306 | ||
1307 | if (!ring_is_rsc_enabled(rx_ring)) | |
1308 | return; | |
1309 | ||
1310 | rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1311 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1312 | ||
1313 | /* If this is an RSC frame rsc_cnt should be non-zero */ | |
1314 | if (!rsc_enabled) | |
1315 | return; | |
1316 | ||
1317 | rsc_cnt = le32_to_cpu(rsc_enabled); | |
1318 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1319 | ||
1320 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
aa80175a | 1321 | } |
43634e82 | 1322 | |
1d2024f6 AD |
1323 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1324 | struct sk_buff *skb) | |
1325 | { | |
f800326d | 1326 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1327 | |
1328 | /* set gso_size to avoid messing up TCP MSS */ | |
1329 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1330 | IXGBE_CB(skb)->append_cnt); | |
1331 | } | |
1332 | ||
1333 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1334 | struct sk_buff *skb) | |
1335 | { | |
1336 | /* if append_cnt is 0 then frame is not RSC */ | |
1337 | if (!IXGBE_CB(skb)->append_cnt) | |
1338 | return; | |
1339 | ||
1340 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1341 | rx_ring->rx_stats.rsc_flush++; | |
1342 | ||
1343 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1344 | ||
1345 | /* gso_size is computed using append_cnt so always clear it last */ | |
1346 | IXGBE_CB(skb)->append_cnt = 0; | |
1347 | } | |
1348 | ||
8a0da21b AD |
1349 | /** |
1350 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1351 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1352 | * @rx_desc: pointer to the EOP Rx descriptor | |
1353 | * @skb: pointer to current skb being populated | |
f8212f97 | 1354 | * |
8a0da21b AD |
1355 | * This function checks the ring, descriptor, and packet information in |
1356 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1357 | * other fields within the skb. | |
f8212f97 | 1358 | **/ |
8a0da21b AD |
1359 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1360 | union ixgbe_adv_rx_desc *rx_desc, | |
1361 | struct sk_buff *skb) | |
f8212f97 | 1362 | { |
8a0da21b AD |
1363 | ixgbe_update_rsc_stats(rx_ring, skb); |
1364 | ||
1365 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1366 | |
8a0da21b AD |
1367 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1368 | ||
1369 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
1370 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
1371 | __vlan_hwaccel_put_tag(skb, vid); | |
f8212f97 AD |
1372 | } |
1373 | ||
8a0da21b | 1374 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1375 | |
8a0da21b | 1376 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
f8212f97 AD |
1377 | } |
1378 | ||
8a0da21b AD |
1379 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1380 | struct sk_buff *skb) | |
aa80175a | 1381 | { |
8a0da21b AD |
1382 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1383 | ||
1384 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1385 | napi_gro_receive(&q_vector->napi, skb); | |
1386 | else | |
1387 | netif_rx(skb); | |
aa80175a | 1388 | } |
43634e82 | 1389 | |
f800326d AD |
1390 | /** |
1391 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1392 | * @rx_ring: Rx ring being processed | |
1393 | * @rx_desc: Rx descriptor for current buffer | |
1394 | * @skb: Current socket buffer containing buffer in progress | |
1395 | * | |
1396 | * This function updates next to clean. If the buffer is an EOP buffer | |
1397 | * this function exits returning false, otherwise it will place the | |
1398 | * sk_buff in the next buffer to be chained and return true indicating | |
1399 | * that this is in fact a non-EOP buffer. | |
1400 | **/ | |
1401 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1402 | union ixgbe_adv_rx_desc *rx_desc, | |
1403 | struct sk_buff *skb) | |
1404 | { | |
1405 | u32 ntc = rx_ring->next_to_clean + 1; | |
1406 | ||
1407 | /* fetch, update, and store next to clean */ | |
1408 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1409 | rx_ring->next_to_clean = ntc; | |
1410 | ||
1411 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1412 | ||
1413 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1414 | return false; | |
1415 | ||
1416 | /* append_cnt indicates packet is RSC, if so fetch nextp */ | |
1417 | if (IXGBE_CB(skb)->append_cnt) { | |
1418 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1419 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1420 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1421 | } | |
1422 | ||
1423 | /* place skb in next buffer to be received */ | |
1424 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1425 | rx_ring->rx_stats.non_eop_descs++; | |
1426 | ||
1427 | return true; | |
1428 | } | |
1429 | ||
1430 | /** | |
1431 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1432 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1433 | * @rx_desc: pointer to the EOP Rx descriptor | |
1434 | * @skb: pointer to current skb being fixed | |
1435 | * | |
1436 | * Check for corrupted packet headers caused by senders on the local L2 | |
1437 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1438 | * should be very rare. | |
1439 | * | |
1440 | * Also address the case where we are pulling data in on pages only | |
1441 | * and as such no data is present in the skb header. | |
1442 | * | |
1443 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1444 | * it is large enough to qualify as a valid Ethernet frame. | |
1445 | * | |
1446 | * Returns true if an error was encountered and skb was freed. | |
1447 | **/ | |
1448 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1449 | union ixgbe_adv_rx_desc *rx_desc, | |
1450 | struct sk_buff *skb) | |
1451 | { | |
1452 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1453 | struct net_device *netdev = rx_ring->netdev; | |
1454 | unsigned char *va; | |
1455 | unsigned int pull_len; | |
1456 | ||
1457 | /* if the page was released unmap it, else just sync our portion */ | |
1458 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1459 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1460 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1461 | IXGBE_CB(skb)->page_released = false; | |
1462 | } else { | |
1463 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1464 | IXGBE_CB(skb)->dma, | |
1465 | frag->page_offset, | |
1466 | ixgbe_rx_bufsz(rx_ring), | |
1467 | DMA_FROM_DEVICE); | |
1468 | } | |
1469 | IXGBE_CB(skb)->dma = 0; | |
1470 | ||
1471 | /* verify that the packet does not have any known errors */ | |
1472 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1473 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1474 | !(netdev->features & NETIF_F_RXALL))) { | |
1475 | dev_kfree_skb_any(skb); | |
1476 | return true; | |
1477 | } | |
1478 | ||
1479 | /* | |
1480 | * it is valid to use page_address instead of kmap since we are | |
1481 | * working with pages allocated out of the lomem pool per | |
1482 | * alloc_page(GFP_ATOMIC) | |
1483 | */ | |
1484 | va = skb_frag_address(frag); | |
1485 | ||
1486 | /* | |
1487 | * we need the header to contain the greater of either ETH_HLEN or | |
1488 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1489 | */ | |
1490 | pull_len = skb_frag_size(frag); | |
1491 | if (pull_len > 256) | |
1492 | pull_len = ixgbe_get_headlen(va, pull_len); | |
1493 | ||
1494 | /* align pull length to size of long to optimize memcpy performance */ | |
1495 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1496 | ||
1497 | /* update all of the pointers */ | |
1498 | skb_frag_size_sub(frag, pull_len); | |
1499 | frag->page_offset += pull_len; | |
1500 | skb->data_len -= pull_len; | |
1501 | skb->tail += pull_len; | |
1502 | ||
1503 | /* | |
1504 | * if we sucked the frag empty then we should free it, | |
1505 | * if there are other frags here something is screwed up in hardware | |
1506 | */ | |
1507 | if (skb_frag_size(frag) == 0) { | |
1508 | BUG_ON(skb_shinfo(skb)->nr_frags != 1); | |
1509 | skb_shinfo(skb)->nr_frags = 0; | |
1510 | __skb_frag_unref(frag); | |
1511 | skb->truesize -= ixgbe_rx_bufsz(rx_ring); | |
1512 | } | |
1513 | ||
1514 | /* if skb_pad returns an error the skb was freed */ | |
1515 | if (unlikely(skb->len < 60)) { | |
1516 | int pad_len = 60 - skb->len; | |
1517 | ||
1518 | if (skb_pad(skb, pad_len)) | |
1519 | return true; | |
1520 | __skb_put(skb, pad_len); | |
1521 | } | |
1522 | ||
1523 | return false; | |
1524 | } | |
1525 | ||
1526 | /** | |
1527 | * ixgbe_can_reuse_page - determine if we can reuse a page | |
1528 | * @rx_buffer: pointer to rx_buffer containing the page we want to reuse | |
1529 | * | |
1530 | * Returns true if page can be reused in another Rx buffer | |
1531 | **/ | |
1532 | static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer) | |
1533 | { | |
1534 | struct page *page = rx_buffer->page; | |
1535 | ||
1536 | /* if we are only owner of page and it is local we can reuse it */ | |
1537 | return likely(page_count(page) == 1) && | |
1538 | likely(page_to_nid(page) == numa_node_id()); | |
1539 | } | |
1540 | ||
1541 | /** | |
1542 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1543 | * @rx_ring: rx descriptor ring to store buffers on | |
1544 | * @old_buff: donor buffer to have page reused | |
1545 | * | |
1546 | * Syncronizes page for reuse by the adapter | |
1547 | **/ | |
1548 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1549 | struct ixgbe_rx_buffer *old_buff) | |
1550 | { | |
1551 | struct ixgbe_rx_buffer *new_buff; | |
1552 | u16 nta = rx_ring->next_to_alloc; | |
1553 | u16 bufsz = ixgbe_rx_bufsz(rx_ring); | |
1554 | ||
1555 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1556 | ||
1557 | /* update, and store next to alloc */ | |
1558 | nta++; | |
1559 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1560 | ||
1561 | /* transfer page from old buffer to new buffer */ | |
1562 | new_buff->page = old_buff->page; | |
1563 | new_buff->dma = old_buff->dma; | |
1564 | ||
1565 | /* flip page offset to other buffer and store to new_buff */ | |
1566 | new_buff->page_offset = old_buff->page_offset ^ bufsz; | |
1567 | ||
1568 | /* sync the buffer for use by the device */ | |
1569 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
1570 | new_buff->page_offset, bufsz, | |
1571 | DMA_FROM_DEVICE); | |
1572 | ||
1573 | /* bump ref count on page before it is given to the stack */ | |
1574 | get_page(new_buff->page); | |
1575 | } | |
1576 | ||
1577 | /** | |
1578 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1579 | * @rx_ring: rx descriptor ring to transact packets on | |
1580 | * @rx_buffer: buffer containing page to add | |
1581 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1582 | * @skb: sk_buff to place the data into | |
1583 | * | |
1584 | * This function is based on skb_add_rx_frag. I would have used that | |
1585 | * function however it doesn't handle the truesize case correctly since we | |
1586 | * are allocating more memory than might be used for a single receive. | |
1587 | **/ | |
1588 | static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, | |
1589 | struct ixgbe_rx_buffer *rx_buffer, | |
1590 | struct sk_buff *skb, int size) | |
1591 | { | |
1592 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
1593 | rx_buffer->page, rx_buffer->page_offset, | |
1594 | size); | |
1595 | skb->len += size; | |
1596 | skb->data_len += size; | |
1597 | skb->truesize += ixgbe_rx_bufsz(rx_ring); | |
1598 | } | |
1599 | ||
1600 | /** | |
1601 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1602 | * @q_vector: structure containing interrupt and ring information | |
1603 | * @rx_ring: rx descriptor ring to transact packets on | |
1604 | * @budget: Total limit on number of packets to process | |
1605 | * | |
1606 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1607 | * processing. The advantage to this is that on systems that have | |
1608 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1609 | * it by maintaining the mapping of the page to the syste. | |
1610 | * | |
1611 | * Returns true if all work is completed without reaching budget | |
1612 | **/ | |
4ff7fb12 | 1613 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1614 | struct ixgbe_ring *rx_ring, |
4ff7fb12 | 1615 | int budget) |
9a799d71 | 1616 | { |
d2f4fbe2 | 1617 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 1618 | #ifdef IXGBE_FCOE |
f800326d | 1619 | struct ixgbe_adapter *adapter = q_vector->adapter; |
3d8fd385 YZ |
1620 | int ddp_bytes = 0; |
1621 | #endif /* IXGBE_FCOE */ | |
f800326d | 1622 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 1623 | |
f800326d AD |
1624 | do { |
1625 | struct ixgbe_rx_buffer *rx_buffer; | |
1626 | union ixgbe_adv_rx_desc *rx_desc; | |
1627 | struct sk_buff *skb; | |
1628 | struct page *page; | |
1629 | u16 ntc; | |
1630 | ||
1631 | /* return some buffers to hardware, one at a time is too slow */ | |
1632 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1633 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1634 | cleaned_count = 0; | |
1635 | } | |
1636 | ||
1637 | ntc = rx_ring->next_to_clean; | |
1638 | rx_desc = IXGBE_RX_DESC(rx_ring, ntc); | |
1639 | rx_buffer = &rx_ring->rx_buffer_info[ntc]; | |
1640 | ||
1641 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) | |
1642 | break; | |
9a799d71 | 1643 | |
f800326d AD |
1644 | /* |
1645 | * This memory barrier is needed to keep us from reading | |
1646 | * any other fields out of the rx_desc until we know the | |
1647 | * RXD_STAT_DD bit is set | |
1648 | */ | |
1649 | rmb(); | |
9a799d71 | 1650 | |
f800326d AD |
1651 | page = rx_buffer->page; |
1652 | prefetchw(page); | |
9a799d71 | 1653 | |
f800326d | 1654 | skb = rx_buffer->skb; |
c267fc16 | 1655 | |
f800326d AD |
1656 | if (likely(!skb)) { |
1657 | void *page_addr = page_address(page) + | |
1658 | rx_buffer->page_offset; | |
9a799d71 | 1659 | |
f800326d AD |
1660 | /* prefetch first cache line of first page */ |
1661 | prefetch(page_addr); | |
1662 | #if L1_CACHE_BYTES < 128 | |
1663 | prefetch(page_addr + L1_CACHE_BYTES); | |
1664 | #endif | |
1665 | ||
1666 | /* allocate a skb to store the frags */ | |
1667 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1668 | IXGBE_RX_HDR_SIZE); | |
1669 | if (unlikely(!skb)) { | |
1670 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1671 | break; | |
c267fc16 AD |
1672 | } |
1673 | ||
f800326d AD |
1674 | /* |
1675 | * we will be copying header into skb->data in | |
1676 | * pskb_may_pull so it is in our interest to prefetch | |
1677 | * it now to avoid a possible cache miss | |
1678 | */ | |
1679 | prefetchw(skb->data); | |
4c1975d7 AD |
1680 | |
1681 | /* | |
1682 | * Delay unmapping of the first packet. It carries the | |
1683 | * header information, HW may still access the header | |
f800326d AD |
1684 | * after the writeback. Only unmap it when EOP is |
1685 | * reached | |
4c1975d7 | 1686 | */ |
f800326d | 1687 | IXGBE_CB(skb)->dma = rx_buffer->dma; |
c267fc16 | 1688 | } else { |
f800326d AD |
1689 | /* we are reusing so sync this buffer for CPU use */ |
1690 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1691 | rx_buffer->dma, | |
1692 | rx_buffer->page_offset, | |
1693 | ixgbe_rx_bufsz(rx_ring), | |
1694 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1695 | } |
1696 | ||
f800326d AD |
1697 | /* pull page into skb */ |
1698 | ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, | |
1699 | le16_to_cpu(rx_desc->wb.upper.length)); | |
9a799d71 | 1700 | |
f800326d AD |
1701 | if (ixgbe_can_reuse_page(rx_buffer)) { |
1702 | /* hand second half of page back to the ring */ | |
1703 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
1704 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
1705 | /* the page has been released from the ring */ | |
1706 | IXGBE_CB(skb)->page_released = true; | |
1707 | } else { | |
1708 | /* we are not reusing the buffer so unmap it */ | |
1709 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
1710 | ixgbe_rx_pg_size(rx_ring), | |
1711 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1712 | } |
1713 | ||
f800326d AD |
1714 | /* clear contents of buffer_info */ |
1715 | rx_buffer->skb = NULL; | |
1716 | rx_buffer->dma = 0; | |
1717 | rx_buffer->page = NULL; | |
4c1975d7 | 1718 | |
f800326d | 1719 | ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb); |
9a799d71 | 1720 | |
9a799d71 | 1721 | cleaned_count++; |
f8212f97 | 1722 | |
f800326d AD |
1723 | /* place incomplete frames back on ring for completion */ |
1724 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
1725 | continue; | |
c267fc16 | 1726 | |
f800326d AD |
1727 | /* verify the packet layout is correct */ |
1728 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
1729 | continue; | |
9a799d71 | 1730 | |
d2f4fbe2 AV |
1731 | /* probably a little skewed due to removing CRC */ |
1732 | total_rx_bytes += skb->len; | |
1733 | total_rx_packets++; | |
1734 | ||
8a0da21b AD |
1735 | /* populate checksum, timestamp, VLAN, and protocol */ |
1736 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
1737 | ||
332d4a7d YZ |
1738 | #ifdef IXGBE_FCOE |
1739 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
ff886dfc | 1740 | if (ixgbe_rx_is_fcoe(adapter, rx_desc)) { |
f56e0cb1 | 1741 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
63d635b2 AD |
1742 | if (!ddp_bytes) { |
1743 | dev_kfree_skb_any(skb); | |
f800326d | 1744 | continue; |
63d635b2 | 1745 | } |
3d8fd385 | 1746 | } |
f800326d | 1747 | |
332d4a7d | 1748 | #endif /* IXGBE_FCOE */ |
8a0da21b | 1749 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 1750 | |
f800326d | 1751 | /* update budget accounting */ |
4ff7fb12 | 1752 | budget--; |
f800326d | 1753 | } while (likely(budget)); |
9a799d71 | 1754 | |
3d8fd385 YZ |
1755 | #ifdef IXGBE_FCOE |
1756 | /* include DDPed FCoE data */ | |
1757 | if (ddp_bytes > 0) { | |
1758 | unsigned int mss; | |
1759 | ||
fc77dc3c | 1760 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1761 | sizeof(struct fc_frame_header) - |
1762 | sizeof(struct fcoe_crc_eof); | |
1763 | if (mss > 512) | |
1764 | mss &= ~511; | |
1765 | total_rx_bytes += ddp_bytes; | |
1766 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1767 | } | |
3d8fd385 | 1768 | |
f800326d | 1769 | #endif /* IXGBE_FCOE */ |
c267fc16 AD |
1770 | u64_stats_update_begin(&rx_ring->syncp); |
1771 | rx_ring->stats.packets += total_rx_packets; | |
1772 | rx_ring->stats.bytes += total_rx_bytes; | |
1773 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1774 | q_vector->rx.total_packets += total_rx_packets; |
1775 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 1776 | |
f800326d AD |
1777 | if (cleaned_count) |
1778 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1779 | ||
4ff7fb12 | 1780 | return !!budget; |
9a799d71 AK |
1781 | } |
1782 | ||
9a799d71 AK |
1783 | /** |
1784 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1785 | * @adapter: board private structure | |
1786 | * | |
1787 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1788 | * interrupts. | |
1789 | **/ | |
1790 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1791 | { | |
021230d4 | 1792 | struct ixgbe_q_vector *q_vector; |
efe3d3c8 | 1793 | int q_vectors, v_idx; |
021230d4 | 1794 | u32 mask; |
9a799d71 | 1795 | |
021230d4 | 1796 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1797 | |
8e34d1aa AD |
1798 | /* Populate MSIX to EITR Select */ |
1799 | if (adapter->num_vfs > 32) { | |
1800 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1801 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1802 | } | |
1803 | ||
4df10466 JB |
1804 | /* |
1805 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1806 | * corresponding register. |
1807 | */ | |
1808 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
efe3d3c8 | 1809 | struct ixgbe_ring *ring; |
7a921c93 | 1810 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1811 | |
a557928e | 1812 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
1813 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
1814 | ||
a557928e | 1815 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
1816 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
1817 | ||
d5bf4f67 ET |
1818 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
1819 | /* tx only vector */ | |
1820 | if (adapter->tx_itr_setting == 1) | |
1821 | q_vector->itr = IXGBE_10K_ITR; | |
1822 | else | |
1823 | q_vector->itr = adapter->tx_itr_setting; | |
1824 | } else { | |
1825 | /* rx or rx/tx vector */ | |
1826 | if (adapter->rx_itr_setting == 1) | |
1827 | q_vector->itr = IXGBE_20K_ITR; | |
1828 | else | |
1829 | q_vector->itr = adapter->rx_itr_setting; | |
1830 | } | |
021230d4 | 1831 | |
fe49f04a | 1832 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1833 | } |
1834 | ||
bd508178 AD |
1835 | switch (adapter->hw.mac.type) { |
1836 | case ixgbe_mac_82598EB: | |
e8e26350 | 1837 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1838 | v_idx); |
bd508178 AD |
1839 | break; |
1840 | case ixgbe_mac_82599EB: | |
b93a2226 | 1841 | case ixgbe_mac_X540: |
e8e26350 | 1842 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 1843 | break; |
bd508178 AD |
1844 | default: |
1845 | break; | |
1846 | } | |
021230d4 AV |
1847 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1848 | ||
41fb9248 | 1849 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1850 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
1851 | mask &= ~(IXGBE_EIMS_OTHER | |
1852 | IXGBE_EIMS_MAILBOX | | |
1853 | IXGBE_EIMS_LSC); | |
1854 | ||
021230d4 | 1855 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1856 | } |
1857 | ||
f494e8fa AV |
1858 | enum latency_range { |
1859 | lowest_latency = 0, | |
1860 | low_latency = 1, | |
1861 | bulk_latency = 2, | |
1862 | latency_invalid = 255 | |
1863 | }; | |
1864 | ||
1865 | /** | |
1866 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
1867 | * @q_vector: structure containing interrupt and ring information |
1868 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
1869 | * |
1870 | * Stores a new ITR value based on packets and byte | |
1871 | * counts during the last interrupt. The advantage of per interrupt | |
1872 | * computation is faster updates and more accurate ITR for the current | |
1873 | * traffic pattern. Constants in this function were computed | |
1874 | * based on theoretical maximum wire speed and thresholds were set based | |
1875 | * on testing data as well as attempting to minimize response time | |
1876 | * while increasing bulk throughput. | |
1877 | * this functionality is controlled by the InterruptThrottleRate module | |
1878 | * parameter (see ixgbe_param.c) | |
1879 | **/ | |
bd198058 AD |
1880 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
1881 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 1882 | { |
bd198058 AD |
1883 | int bytes = ring_container->total_bytes; |
1884 | int packets = ring_container->total_packets; | |
1885 | u32 timepassed_us; | |
621bd70e | 1886 | u64 bytes_perint; |
bd198058 | 1887 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
1888 | |
1889 | if (packets == 0) | |
bd198058 | 1890 | return; |
f494e8fa AV |
1891 | |
1892 | /* simple throttlerate management | |
621bd70e AD |
1893 | * 0-10MB/s lowest (100000 ints/s) |
1894 | * 10-20MB/s low (20000 ints/s) | |
1895 | * 20-1249MB/s bulk (8000 ints/s) | |
f494e8fa AV |
1896 | */ |
1897 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 1898 | timepassed_us = q_vector->itr >> 2; |
f494e8fa AV |
1899 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1900 | ||
1901 | switch (itr_setting) { | |
1902 | case lowest_latency: | |
621bd70e | 1903 | if (bytes_perint > 10) |
bd198058 | 1904 | itr_setting = low_latency; |
f494e8fa AV |
1905 | break; |
1906 | case low_latency: | |
621bd70e | 1907 | if (bytes_perint > 20) |
bd198058 | 1908 | itr_setting = bulk_latency; |
621bd70e | 1909 | else if (bytes_perint <= 10) |
bd198058 | 1910 | itr_setting = lowest_latency; |
f494e8fa AV |
1911 | break; |
1912 | case bulk_latency: | |
621bd70e | 1913 | if (bytes_perint <= 20) |
bd198058 | 1914 | itr_setting = low_latency; |
f494e8fa AV |
1915 | break; |
1916 | } | |
1917 | ||
bd198058 AD |
1918 | /* clear work counters since we have the values we need */ |
1919 | ring_container->total_bytes = 0; | |
1920 | ring_container->total_packets = 0; | |
1921 | ||
1922 | /* write updated itr to ring container */ | |
1923 | ring_container->itr = itr_setting; | |
f494e8fa AV |
1924 | } |
1925 | ||
509ee935 JB |
1926 | /** |
1927 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1928 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1929 | * |
1930 | * This function is made to be called by ethtool and by the driver | |
1931 | * when it needs to update EITR registers at runtime. Hardware | |
1932 | * specific quirks/differences are taken care of here. | |
1933 | */ | |
fe49f04a | 1934 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1935 | { |
fe49f04a | 1936 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1937 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1938 | int v_idx = q_vector->v_idx; |
5d967eb7 | 1939 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 1940 | |
bd508178 AD |
1941 | switch (adapter->hw.mac.type) { |
1942 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1943 | /* must write high and low 16 bits to reset counter */ |
1944 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1945 | break; |
1946 | case ixgbe_mac_82599EB: | |
b93a2226 | 1947 | case ixgbe_mac_X540: |
509ee935 JB |
1948 | /* |
1949 | * set the WDIS bit to not clear the timer bits and cause an | |
1950 | * immediate assertion of the interrupt | |
1951 | */ | |
1952 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1953 | break; |
1954 | default: | |
1955 | break; | |
509ee935 JB |
1956 | } |
1957 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1958 | } | |
1959 | ||
bd198058 | 1960 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 1961 | { |
d5bf4f67 | 1962 | u32 new_itr = q_vector->itr; |
bd198058 | 1963 | u8 current_itr; |
f494e8fa | 1964 | |
bd198058 AD |
1965 | ixgbe_update_itr(q_vector, &q_vector->tx); |
1966 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 1967 | |
08c8833b | 1968 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
1969 | |
1970 | switch (current_itr) { | |
1971 | /* counts and packets in update_itr are dependent on these numbers */ | |
1972 | case lowest_latency: | |
d5bf4f67 | 1973 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
1974 | break; |
1975 | case low_latency: | |
d5bf4f67 | 1976 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
1977 | break; |
1978 | case bulk_latency: | |
d5bf4f67 | 1979 | new_itr = IXGBE_8K_ITR; |
f494e8fa | 1980 | break; |
bd198058 AD |
1981 | default: |
1982 | break; | |
f494e8fa AV |
1983 | } |
1984 | ||
d5bf4f67 | 1985 | if (new_itr != q_vector->itr) { |
fe49f04a | 1986 | /* do an exponential smoothing */ |
d5bf4f67 ET |
1987 | new_itr = (10 * new_itr * q_vector->itr) / |
1988 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 1989 | |
bd198058 | 1990 | /* save the algorithm value here */ |
5d967eb7 | 1991 | q_vector->itr = new_itr; |
fe49f04a AD |
1992 | |
1993 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 1994 | } |
f494e8fa AV |
1995 | } |
1996 | ||
119fc60a | 1997 | /** |
de88eeeb | 1998 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 1999 | * @adapter: pointer to adapter |
119fc60a | 2000 | **/ |
f0f9778d | 2001 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2002 | { |
119fc60a MC |
2003 | struct ixgbe_hw *hw = &adapter->hw; |
2004 | u32 eicr = adapter->interrupt_event; | |
2005 | ||
f0f9778d | 2006 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2007 | return; |
2008 | ||
f0f9778d AD |
2009 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2010 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2011 | return; | |
2012 | ||
2013 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2014 | ||
7ca647bd | 2015 | switch (hw->device_id) { |
f0f9778d AD |
2016 | case IXGBE_DEV_ID_82599_T3_LOM: |
2017 | /* | |
2018 | * Since the warning interrupt is for both ports | |
2019 | * we don't have to check if: | |
2020 | * - This interrupt wasn't for our port. | |
2021 | * - We may have missed the interrupt so always have to | |
2022 | * check if we got a LSC | |
2023 | */ | |
2024 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
2025 | !(eicr & IXGBE_EICR_LSC)) | |
2026 | return; | |
2027 | ||
2028 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
2029 | u32 autoneg; | |
2030 | bool link_up = false; | |
7ca647bd | 2031 | |
7ca647bd JP |
2032 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
2033 | ||
f0f9778d AD |
2034 | if (link_up) |
2035 | return; | |
2036 | } | |
2037 | ||
2038 | /* Check if this is not due to overtemp */ | |
2039 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2040 | return; | |
2041 | ||
2042 | break; | |
7ca647bd JP |
2043 | default: |
2044 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 2045 | return; |
7ca647bd | 2046 | break; |
119fc60a | 2047 | } |
7ca647bd JP |
2048 | e_crit(drv, |
2049 | "Network adapter has been stopped because it has over heated. " | |
2050 | "Restart the computer. If the problem persists, " | |
2051 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
2052 | |
2053 | adapter->interrupt_event = 0; | |
119fc60a MC |
2054 | } |
2055 | ||
0befdb3e JB |
2056 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2057 | { | |
2058 | struct ixgbe_hw *hw = &adapter->hw; | |
2059 | ||
2060 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
2061 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 2062 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
2063 | /* write to clear the interrupt */ |
2064 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
2065 | } | |
2066 | } | |
cf8280ee | 2067 | |
4f51bf70 JK |
2068 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2069 | { | |
2070 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) | |
2071 | return; | |
2072 | ||
2073 | switch (adapter->hw.mac.type) { | |
2074 | case ixgbe_mac_82599EB: | |
2075 | /* | |
2076 | * Need to check link state so complete overtemp check | |
2077 | * on service task | |
2078 | */ | |
2079 | if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && | |
2080 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { | |
2081 | adapter->interrupt_event = eicr; | |
2082 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2083 | ixgbe_service_event_schedule(adapter); | |
2084 | return; | |
2085 | } | |
2086 | return; | |
2087 | case ixgbe_mac_X540: | |
2088 | if (!(eicr & IXGBE_EICR_TS)) | |
2089 | return; | |
2090 | break; | |
2091 | default: | |
2092 | return; | |
2093 | } | |
2094 | ||
2095 | e_crit(drv, | |
2096 | "Network adapter has been stopped because it has over heated. " | |
2097 | "Restart the computer. If the problem persists, " | |
2098 | "power off the system and replace the adapter\n"); | |
2099 | } | |
2100 | ||
e8e26350 PW |
2101 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2102 | { | |
2103 | struct ixgbe_hw *hw = &adapter->hw; | |
2104 | ||
73c4b7cd AD |
2105 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
2106 | /* Clear the interrupt */ | |
2107 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
2108 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2109 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
2110 | ixgbe_service_event_schedule(adapter); | |
2111 | } | |
73c4b7cd AD |
2112 | } |
2113 | ||
e8e26350 PW |
2114 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
2115 | /* Clear the interrupt */ | |
2116 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
2117 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2118 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2119 | ixgbe_service_event_schedule(adapter); | |
2120 | } | |
e8e26350 PW |
2121 | } |
2122 | } | |
2123 | ||
cf8280ee JB |
2124 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2125 | { | |
2126 | struct ixgbe_hw *hw = &adapter->hw; | |
2127 | ||
2128 | adapter->lsc_int++; | |
2129 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2130 | adapter->link_check_timeout = jiffies; | |
2131 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2132 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2133 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2134 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2135 | } |
2136 | } | |
2137 | ||
fe49f04a AD |
2138 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2139 | u64 qmask) | |
2140 | { | |
2141 | u32 mask; | |
bd508178 | 2142 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2143 | |
bd508178 AD |
2144 | switch (hw->mac.type) { |
2145 | case ixgbe_mac_82598EB: | |
fe49f04a | 2146 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2147 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2148 | break; | |
2149 | case ixgbe_mac_82599EB: | |
b93a2226 | 2150 | case ixgbe_mac_X540: |
fe49f04a | 2151 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2152 | if (mask) |
2153 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2154 | mask = (qmask >> 32); |
bd508178 AD |
2155 | if (mask) |
2156 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2157 | break; | |
2158 | default: | |
2159 | break; | |
fe49f04a AD |
2160 | } |
2161 | /* skip the flush */ | |
2162 | } | |
2163 | ||
2164 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2165 | u64 qmask) |
fe49f04a AD |
2166 | { |
2167 | u32 mask; | |
bd508178 | 2168 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2169 | |
bd508178 AD |
2170 | switch (hw->mac.type) { |
2171 | case ixgbe_mac_82598EB: | |
fe49f04a | 2172 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2173 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2174 | break; | |
2175 | case ixgbe_mac_82599EB: | |
b93a2226 | 2176 | case ixgbe_mac_X540: |
fe49f04a | 2177 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2178 | if (mask) |
2179 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2180 | mask = (qmask >> 32); |
bd508178 AD |
2181 | if (mask) |
2182 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2183 | break; | |
2184 | default: | |
2185 | break; | |
fe49f04a AD |
2186 | } |
2187 | /* skip the flush */ | |
2188 | } | |
2189 | ||
021230d4 | 2190 | /** |
2c4af694 AD |
2191 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2192 | * @adapter: board private structure | |
021230d4 | 2193 | **/ |
2c4af694 AD |
2194 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2195 | bool flush) | |
9a799d71 | 2196 | { |
2c4af694 | 2197 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2198 | |
2c4af694 AD |
2199 | /* don't reenable LSC while waiting for link */ |
2200 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2201 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2202 | |
2c4af694 | 2203 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2204 | switch (adapter->hw.mac.type) { |
2205 | case ixgbe_mac_82599EB: | |
2206 | mask |= IXGBE_EIMS_GPI_SDP0; | |
2207 | break; | |
2208 | case ixgbe_mac_X540: | |
2209 | mask |= IXGBE_EIMS_TS; | |
2210 | break; | |
2211 | default: | |
2212 | break; | |
2213 | } | |
2c4af694 AD |
2214 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2215 | mask |= IXGBE_EIMS_GPI_SDP1; | |
2216 | switch (adapter->hw.mac.type) { | |
2217 | case ixgbe_mac_82599EB: | |
2c4af694 AD |
2218 | mask |= IXGBE_EIMS_GPI_SDP1; |
2219 | mask |= IXGBE_EIMS_GPI_SDP2; | |
858bc081 DS |
2220 | case ixgbe_mac_X540: |
2221 | mask |= IXGBE_EIMS_ECC; | |
2c4af694 AD |
2222 | mask |= IXGBE_EIMS_MAILBOX; |
2223 | break; | |
2224 | default: | |
2225 | break; | |
9a799d71 | 2226 | } |
2c4af694 AD |
2227 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2228 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2229 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2230 | |
2c4af694 AD |
2231 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2232 | if (queues) | |
2233 | ixgbe_irq_enable_queues(adapter, ~0); | |
2234 | if (flush) | |
2235 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2236 | } |
2237 | ||
2c4af694 | 2238 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2239 | { |
a65151ba | 2240 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2241 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2242 | u32 eicr; |
91281fd3 | 2243 | |
54037505 DS |
2244 | /* |
2245 | * Workaround for Silicon errata. Use clear-by-write instead | |
2246 | * of clear-by-read. Reading with EICS will return the | |
2247 | * interrupt causes without clearing, which later be done | |
2248 | * with the write to EICR. | |
2249 | */ | |
2250 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
2251 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 2252 | |
cf8280ee JB |
2253 | if (eicr & IXGBE_EICR_LSC) |
2254 | ixgbe_check_lsc(adapter); | |
f0848276 | 2255 | |
1cdd1ec8 GR |
2256 | if (eicr & IXGBE_EICR_MAILBOX) |
2257 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2258 | |
bd508178 AD |
2259 | switch (hw->mac.type) { |
2260 | case ixgbe_mac_82599EB: | |
b93a2226 | 2261 | case ixgbe_mac_X540: |
2c4af694 AD |
2262 | if (eicr & IXGBE_EICR_ECC) |
2263 | e_info(link, "Received unrecoverable ECC Err, please " | |
2264 | "reboot\n"); | |
c4cf55e5 PWJ |
2265 | /* Handle Flow Director Full threshold interrupt */ |
2266 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2267 | int reinit_count = 0; |
c4cf55e5 | 2268 | int i; |
c4cf55e5 | 2269 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2270 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2271 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2272 | &ring->state)) |
2273 | reinit_count++; | |
2274 | } | |
2275 | if (reinit_count) { | |
2276 | /* no more flow director interrupts until after init */ | |
2277 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2278 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2279 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2280 | } |
2281 | } | |
f0f9778d | 2282 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2283 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2284 | break; |
2285 | default: | |
2286 | break; | |
c4cf55e5 | 2287 | } |
f0848276 | 2288 | |
bd508178 | 2289 | ixgbe_check_fan_failure(adapter, eicr); |
efe3d3c8 | 2290 | |
7086400d | 2291 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2292 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2293 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2294 | |
9a799d71 | 2295 | return IRQ_HANDLED; |
f0848276 | 2296 | } |
91281fd3 | 2297 | |
4ff7fb12 | 2298 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2299 | { |
021230d4 | 2300 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2301 | |
9b471446 | 2302 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2303 | |
4ff7fb12 AD |
2304 | if (q_vector->rx.ring || q_vector->tx.ring) |
2305 | napi_schedule(&q_vector->napi); | |
91281fd3 | 2306 | |
9a799d71 | 2307 | return IRQ_HANDLED; |
91281fd3 AD |
2308 | } |
2309 | ||
eb01b975 AD |
2310 | /** |
2311 | * ixgbe_poll - NAPI Rx polling callback | |
2312 | * @napi: structure for representing this polling device | |
2313 | * @budget: how many packets driver is allowed to clean | |
2314 | * | |
2315 | * This function is used for legacy and MSI, NAPI mode | |
2316 | **/ | |
2317 | static int ixgbe_poll(struct napi_struct *napi, int budget) | |
2318 | { | |
2319 | struct ixgbe_q_vector *q_vector = | |
2320 | container_of(napi, struct ixgbe_q_vector, napi); | |
2321 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2322 | struct ixgbe_ring *ring; | |
2323 | int per_ring_budget; | |
2324 | bool clean_complete = true; | |
2325 | ||
2326 | #ifdef CONFIG_IXGBE_DCA | |
2327 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2328 | ixgbe_update_dca(q_vector); | |
2329 | #endif | |
2330 | ||
2331 | ixgbe_for_each_ring(ring, q_vector->tx) | |
2332 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); | |
2333 | ||
2334 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2335 | * the budget to go below 1 because we'll exit polling */ | |
2336 | if (q_vector->rx.count > 1) | |
2337 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2338 | else | |
2339 | per_ring_budget = budget; | |
2340 | ||
2341 | ixgbe_for_each_ring(ring, q_vector->rx) | |
2342 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, | |
2343 | per_ring_budget); | |
2344 | ||
2345 | /* If all work not completed, return budget and keep polling */ | |
2346 | if (!clean_complete) | |
2347 | return budget; | |
2348 | ||
2349 | /* all work done, exit the polling mode */ | |
2350 | napi_complete(napi); | |
2351 | if (adapter->rx_itr_setting & 1) | |
2352 | ixgbe_set_itr(q_vector); | |
2353 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2354 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2355 | ||
2356 | return 0; | |
2357 | } | |
2358 | ||
021230d4 AV |
2359 | /** |
2360 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2361 | * @adapter: board private structure | |
2362 | * | |
2363 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2364 | * interrupts from the kernel. | |
2365 | **/ | |
2366 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2367 | { | |
2368 | struct net_device *netdev = adapter->netdev; | |
207867f5 AD |
2369 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2370 | int vector, err; | |
e8e9f696 | 2371 | int ri = 0, ti = 0; |
021230d4 | 2372 | |
021230d4 | 2373 | for (vector = 0; vector < q_vectors; vector++) { |
d0759ebb | 2374 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2375 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2376 | |
4ff7fb12 | 2377 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2378 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2379 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2380 | ti++; | |
2381 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2382 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2383 | "%s-%s-%d", netdev->name, "rx", ri++); |
2384 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2385 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2386 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2387 | } else { |
2388 | /* skip this unused q_vector */ | |
2389 | continue; | |
32aa77a4 | 2390 | } |
207867f5 AD |
2391 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2392 | q_vector->name, q_vector); | |
9a799d71 | 2393 | if (err) { |
396e799c | 2394 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2395 | "Error: %d\n", err); |
021230d4 | 2396 | goto free_queue_irqs; |
9a799d71 | 2397 | } |
207867f5 AD |
2398 | /* If Flow Director is enabled, set interrupt affinity */ |
2399 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2400 | /* assign the mask for this irq */ | |
2401 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2402 | &q_vector->affinity_mask); |
207867f5 | 2403 | } |
9a799d71 AK |
2404 | } |
2405 | ||
021230d4 | 2406 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2407 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2408 | if (err) { |
de88eeeb | 2409 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2410 | goto free_queue_irqs; |
9a799d71 AK |
2411 | } |
2412 | ||
9a799d71 AK |
2413 | return 0; |
2414 | ||
021230d4 | 2415 | free_queue_irqs: |
207867f5 AD |
2416 | while (vector) { |
2417 | vector--; | |
2418 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2419 | NULL); | |
2420 | free_irq(adapter->msix_entries[vector].vector, | |
2421 | adapter->q_vector[vector]); | |
2422 | } | |
021230d4 AV |
2423 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2424 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2425 | kfree(adapter->msix_entries); |
2426 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2427 | return err; |
2428 | } | |
2429 | ||
2430 | /** | |
021230d4 | 2431 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2432 | * @irq: interrupt number |
2433 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2434 | **/ |
2435 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2436 | { | |
a65151ba | 2437 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2438 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2439 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2440 | u32 eicr; |
2441 | ||
54037505 | 2442 | /* |
24ddd967 | 2443 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2444 | * before the read of EICR. |
2445 | */ | |
2446 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2447 | ||
021230d4 | 2448 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2449 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2450 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2451 | if (!eicr) { |
6af3b9eb ET |
2452 | /* |
2453 | * shared interrupt alert! | |
f47cf66e | 2454 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2455 | * have disabled interrupts due to EIAM |
2456 | * finish the workaround of silicon errata on 82598. Unmask | |
2457 | * the interrupt that we masked before the EICR read. | |
2458 | */ | |
2459 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2460 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2461 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2462 | } |
9a799d71 | 2463 | |
cf8280ee JB |
2464 | if (eicr & IXGBE_EICR_LSC) |
2465 | ixgbe_check_lsc(adapter); | |
021230d4 | 2466 | |
bd508178 AD |
2467 | switch (hw->mac.type) { |
2468 | case ixgbe_mac_82599EB: | |
e8e26350 | 2469 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2470 | /* Fall through */ |
2471 | case ixgbe_mac_X540: | |
2472 | if (eicr & IXGBE_EICR_ECC) | |
2473 | e_info(link, "Received unrecoverable ECC err, please " | |
2474 | "reboot\n"); | |
4f51bf70 | 2475 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2476 | break; |
2477 | default: | |
2478 | break; | |
2479 | } | |
e8e26350 | 2480 | |
0befdb3e JB |
2481 | ixgbe_check_fan_failure(adapter, eicr); |
2482 | ||
b9f6ed2b AD |
2483 | /* would disable interrupts here but EIAM disabled it */ |
2484 | napi_schedule(&q_vector->napi); | |
9a799d71 | 2485 | |
6af3b9eb ET |
2486 | /* |
2487 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2488 | * ixgbe_poll will re-enable the queue interrupts | |
2489 | */ | |
6af3b9eb ET |
2490 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2491 | ixgbe_irq_enable(adapter, false, false); | |
2492 | ||
9a799d71 AK |
2493 | return IRQ_HANDLED; |
2494 | } | |
2495 | ||
2496 | /** | |
2497 | * ixgbe_request_irq - initialize interrupts | |
2498 | * @adapter: board private structure | |
2499 | * | |
2500 | * Attempts to configure interrupts using the best available | |
2501 | * capabilities of the hardware and kernel. | |
2502 | **/ | |
021230d4 | 2503 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2504 | { |
2505 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2506 | int err; |
9a799d71 | 2507 | |
4cc6df29 | 2508 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2509 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2510 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2511 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2512 | netdev->name, adapter); |
4cc6df29 | 2513 | else |
a0607fd3 | 2514 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2515 | netdev->name, adapter); |
9a799d71 | 2516 | |
de88eeeb | 2517 | if (err) |
396e799c | 2518 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2519 | |
9a799d71 AK |
2520 | return err; |
2521 | } | |
2522 | ||
2523 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2524 | { | |
9a799d71 | 2525 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
021230d4 | 2526 | int i, q_vectors; |
9a799d71 | 2527 | |
021230d4 | 2528 | q_vectors = adapter->num_msix_vectors; |
021230d4 | 2529 | i = q_vectors - 1; |
a65151ba | 2530 | free_irq(adapter->msix_entries[i].vector, adapter); |
021230d4 | 2531 | i--; |
4cc6df29 | 2532 | |
021230d4 | 2533 | for (; i >= 0; i--) { |
894ff7cf | 2534 | /* free only the irqs that were actually requested */ |
4ff7fb12 AD |
2535 | if (!adapter->q_vector[i]->rx.ring && |
2536 | !adapter->q_vector[i]->tx.ring) | |
894ff7cf AD |
2537 | continue; |
2538 | ||
207867f5 AD |
2539 | /* clear the affinity_mask in the IRQ descriptor */ |
2540 | irq_set_affinity_hint(adapter->msix_entries[i].vector, | |
2541 | NULL); | |
2542 | ||
021230d4 | 2543 | free_irq(adapter->msix_entries[i].vector, |
e8e9f696 | 2544 | adapter->q_vector[i]); |
021230d4 | 2545 | } |
021230d4 | 2546 | } else { |
a65151ba | 2547 | free_irq(adapter->pdev->irq, adapter); |
9a799d71 AK |
2548 | } |
2549 | } | |
2550 | ||
22d5a71b JB |
2551 | /** |
2552 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2553 | * @adapter: board private structure | |
2554 | **/ | |
2555 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2556 | { | |
bd508178 AD |
2557 | switch (adapter->hw.mac.type) { |
2558 | case ixgbe_mac_82598EB: | |
835462fc | 2559 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2560 | break; |
2561 | case ixgbe_mac_82599EB: | |
b93a2226 | 2562 | case ixgbe_mac_X540: |
835462fc NS |
2563 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2564 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2565 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2566 | break; |
2567 | default: | |
2568 | break; | |
22d5a71b JB |
2569 | } |
2570 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2571 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2572 | int i; | |
2573 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2574 | synchronize_irq(adapter->msix_entries[i].vector); | |
2575 | } else { | |
2576 | synchronize_irq(adapter->pdev->irq); | |
2577 | } | |
2578 | } | |
2579 | ||
9a799d71 AK |
2580 | /** |
2581 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2582 | * | |
2583 | **/ | |
2584 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2585 | { | |
d5bf4f67 | 2586 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 2587 | |
d5bf4f67 ET |
2588 | /* rx/tx vector */ |
2589 | if (adapter->rx_itr_setting == 1) | |
2590 | q_vector->itr = IXGBE_20K_ITR; | |
2591 | else | |
2592 | q_vector->itr = adapter->rx_itr_setting; | |
2593 | ||
2594 | ixgbe_write_eitr(q_vector); | |
9a799d71 | 2595 | |
e8e26350 PW |
2596 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2597 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2598 | |
396e799c | 2599 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2600 | } |
2601 | ||
43e69bf0 AD |
2602 | /** |
2603 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2604 | * @adapter: board private structure | |
2605 | * @ring: structure containing ring specific data | |
2606 | * | |
2607 | * Configure the Tx descriptor ring after a reset. | |
2608 | **/ | |
84418e3b AD |
2609 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2610 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2611 | { |
2612 | struct ixgbe_hw *hw = &adapter->hw; | |
2613 | u64 tdba = ring->dma; | |
2f1860b8 | 2614 | int wait_loop = 10; |
b88c6de2 | 2615 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2616 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2617 | |
2f1860b8 | 2618 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2619 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2620 | IXGBE_WRITE_FLUSH(hw); |
2621 | ||
43e69bf0 | 2622 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2623 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2624 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2625 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2626 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2627 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2628 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2629 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2630 | |
b88c6de2 AD |
2631 | /* |
2632 | * set WTHRESH to encourage burst writeback, it should not be set | |
2633 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2634 | * | |
2635 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2636 | * to or less than the number of on chip descriptors, which is | |
2637 | * currently 40. | |
2638 | */ | |
e954b374 | 2639 | if (!ring->q_vector || (ring->q_vector->itr < 8)) |
b88c6de2 AD |
2640 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
2641 | else | |
2642 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2643 | ||
e954b374 AD |
2644 | /* |
2645 | * Setting PTHRESH to 32 both improves performance | |
2646 | * and avoids a TX hang with DFP enabled | |
2647 | */ | |
b88c6de2 AD |
2648 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
2649 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2650 | |
2651 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2652 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2653 | adapter->atr_sample_rate) { | |
2654 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2655 | ring->atr_count = 0; | |
2656 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2657 | } else { | |
2658 | ring->atr_sample_rate = 0; | |
2659 | } | |
2f1860b8 | 2660 | |
c84d324c JF |
2661 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2662 | ||
2f1860b8 | 2663 | /* enable queue */ |
2f1860b8 AD |
2664 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2665 | ||
b2d96e0a AD |
2666 | netdev_tx_reset_queue(txring_txq(ring)); |
2667 | ||
2f1860b8 AD |
2668 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ |
2669 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2670 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2671 | return; | |
2672 | ||
2673 | /* poll to verify queue is enabled */ | |
2674 | do { | |
032b4325 | 2675 | usleep_range(1000, 2000); |
2f1860b8 AD |
2676 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2677 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2678 | if (!wait_loop) | |
2679 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2680 | } |
2681 | ||
120ff942 AD |
2682 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2683 | { | |
2684 | struct ixgbe_hw *hw = &adapter->hw; | |
2685 | u32 rttdcs; | |
72a32f1f | 2686 | u32 reg; |
8b1c0b24 | 2687 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2688 | |
2689 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2690 | return; | |
2691 | ||
2692 | /* disable the arbiter while setting MTQC */ | |
2693 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2694 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2695 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2696 | ||
2697 | /* set transmit pool layout */ | |
8b1c0b24 | 2698 | switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
120ff942 AD |
2699 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2700 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2701 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2702 | break; | |
8b1c0b24 JF |
2703 | default: |
2704 | if (!tcs) | |
2705 | reg = IXGBE_MTQC_64Q_1PB; | |
2706 | else if (tcs <= 4) | |
2707 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2708 | else | |
2709 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
120ff942 | 2710 | |
8b1c0b24 | 2711 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); |
120ff942 | 2712 | |
8b1c0b24 JF |
2713 | /* Enable Security TX Buffer IFG for multiple pb */ |
2714 | if (tcs) { | |
2715 | reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2716 | reg |= IXGBE_SECTX_DCB; | |
2717 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); | |
2718 | } | |
120ff942 AD |
2719 | break; |
2720 | } | |
2721 | ||
2722 | /* re-enable the arbiter */ | |
2723 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2724 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2725 | } | |
2726 | ||
9a799d71 | 2727 | /** |
3a581073 | 2728 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2729 | * @adapter: board private structure |
2730 | * | |
2731 | * Configure the Tx unit of the MAC after a reset. | |
2732 | **/ | |
2733 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2734 | { | |
2f1860b8 AD |
2735 | struct ixgbe_hw *hw = &adapter->hw; |
2736 | u32 dmatxctl; | |
43e69bf0 | 2737 | u32 i; |
9a799d71 | 2738 | |
2f1860b8 AD |
2739 | ixgbe_setup_mtqc(adapter); |
2740 | ||
2741 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2742 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2743 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2744 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2745 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2746 | } | |
2747 | ||
9a799d71 | 2748 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2749 | for (i = 0; i < adapter->num_tx_queues; i++) |
2750 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2751 | } |
2752 | ||
e8e26350 | 2753 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2754 | |
a6616b42 | 2755 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2756 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2757 | { |
cc41ac7c | 2758 | u32 srrctl; |
bf29ee6c | 2759 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2760 | |
bd508178 AD |
2761 | switch (adapter->hw.mac.type) { |
2762 | case ixgbe_mac_82598EB: { | |
2763 | struct ixgbe_ring_feature *feature = adapter->ring_feature; | |
2764 | const int mask = feature[RING_F_RSS].mask; | |
bf29ee6c | 2765 | reg_idx = reg_idx & mask; |
cc41ac7c | 2766 | } |
bd508178 AD |
2767 | break; |
2768 | case ixgbe_mac_82599EB: | |
b93a2226 | 2769 | case ixgbe_mac_X540: |
bd508178 AD |
2770 | default: |
2771 | break; | |
2772 | } | |
2773 | ||
bf29ee6c | 2774 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx)); |
cc41ac7c JB |
2775 | |
2776 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2777 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2778 | if (adapter->num_vfs) |
2779 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2780 | |
afafd5b0 AD |
2781 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2782 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2783 | ||
f800326d AD |
2784 | #if PAGE_SIZE > IXGBE_MAX_RXBUFFER |
2785 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
afafd5b0 | 2786 | #else |
f800326d | 2787 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
afafd5b0 | 2788 | #endif |
f800326d | 2789 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 2790 | |
bf29ee6c | 2791 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2792 | } |
9a799d71 | 2793 | |
05abb126 | 2794 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2795 | { |
05abb126 AD |
2796 | struct ixgbe_hw *hw = &adapter->hw; |
2797 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2798 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2799 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2800 | u32 mrqc = 0, reta = 0; |
2801 | u32 rxcsum; | |
2802 | int i, j; | |
8b1c0b24 | 2803 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
86b4db3b JF |
2804 | int maxq = adapter->ring_feature[RING_F_RSS].indices; |
2805 | ||
2806 | if (tcs) | |
2807 | maxq = min(maxq, adapter->num_tx_queues / tcs); | |
0cefafad | 2808 | |
05abb126 AD |
2809 | /* Fill out hash function seeds */ |
2810 | for (i = 0; i < 10; i++) | |
2811 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2812 | ||
2813 | /* Fill out redirection table */ | |
2814 | for (i = 0, j = 0; i < 128; i++, j++) { | |
86b4db3b | 2815 | if (j == maxq) |
05abb126 AD |
2816 | j = 0; |
2817 | /* reta = 4-byte sliding window of | |
2818 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2819 | reta = (reta << 8) | (j * 0x11); | |
2820 | if ((i & 3) == 3) | |
2821 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2822 | } | |
0cefafad | 2823 | |
05abb126 AD |
2824 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2825 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2826 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2827 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2828 | ||
8b1c0b24 JF |
2829 | if (adapter->hw.mac.type == ixgbe_mac_82598EB && |
2830 | (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { | |
0cefafad | 2831 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 JF |
2832 | } else { |
2833 | int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2834 | | IXGBE_FLAG_SRIOV_ENABLED); | |
2835 | ||
2836 | switch (mask) { | |
2837 | case (IXGBE_FLAG_RSS_ENABLED): | |
2838 | if (!tcs) | |
2839 | mrqc = IXGBE_MRQC_RSSEN; | |
2840 | else if (tcs <= 4) | |
2841 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
2842 | else | |
2843 | mrqc = IXGBE_MRQC_RTRSS8TCEN; | |
2844 | break; | |
2845 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2846 | mrqc = IXGBE_MRQC_VMDQEN; | |
2847 | break; | |
2848 | default: | |
2849 | break; | |
2850 | } | |
0cefafad JB |
2851 | } |
2852 | ||
05abb126 AD |
2853 | /* Perform hash on these packet types */ |
2854 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2855 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2856 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2857 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2858 | ||
2859 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
0cefafad JB |
2860 | } |
2861 | ||
bb5a9ad2 NS |
2862 | /** |
2863 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2864 | * @adapter: address of board private structure | |
2865 | * @index: index of ring to set | |
bb5a9ad2 | 2866 | **/ |
082757af | 2867 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2868 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2869 | { |
bb5a9ad2 | 2870 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2871 | u32 rscctrl; |
bf29ee6c | 2872 | u8 reg_idx = ring->reg_idx; |
7367096a | 2873 | |
7d637bcc | 2874 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2875 | return; |
bb5a9ad2 | 2876 | |
7367096a | 2877 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
2878 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2879 | /* | |
2880 | * we must limit the number of descriptors so that the | |
2881 | * total size of max desc * buf_len is not greater | |
642c680e | 2882 | * than 65536 |
bb5a9ad2 | 2883 | */ |
f800326d AD |
2884 | #if (PAGE_SIZE <= 8192) |
2885 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2886 | #elif (PAGE_SIZE <= 16384) | |
2887 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
bb5a9ad2 | 2888 | #else |
f800326d | 2889 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; |
bb5a9ad2 | 2890 | #endif |
7367096a | 2891 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2892 | } |
2893 | ||
9e10e045 AD |
2894 | /** |
2895 | * ixgbe_set_uta - Set unicast filter table address | |
2896 | * @adapter: board private structure | |
2897 | * | |
2898 | * The unicast table address is a register array of 32-bit registers. | |
2899 | * The table is meant to be used in a way similar to how the MTA is used | |
2900 | * however due to certain limitations in the hardware it is necessary to | |
2901 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous | |
2902 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
2903 | **/ | |
2904 | static void ixgbe_set_uta(struct ixgbe_adapter *adapter) | |
2905 | { | |
2906 | struct ixgbe_hw *hw = &adapter->hw; | |
2907 | int i; | |
2908 | ||
2909 | /* The UTA table only exists on 82599 hardware and newer */ | |
2910 | if (hw->mac.type < ixgbe_mac_82599EB) | |
2911 | return; | |
2912 | ||
2913 | /* we only need to do this if VMDq is enabled */ | |
2914 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2915 | return; | |
2916 | ||
2917 | for (i = 0; i < 128; i++) | |
2918 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); | |
2919 | } | |
2920 | ||
2921 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
2922 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2923 | struct ixgbe_ring *ring) | |
2924 | { | |
2925 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
2926 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
2927 | u32 rxdctl; | |
bf29ee6c | 2928 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
2929 | |
2930 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2931 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2932 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2933 | return; | |
2934 | ||
2935 | do { | |
032b4325 | 2936 | usleep_range(1000, 2000); |
9e10e045 AD |
2937 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
2938 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2939 | ||
2940 | if (!wait_loop) { | |
2941 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
2942 | "the polling period\n", reg_idx); | |
2943 | } | |
2944 | } | |
2945 | ||
2d39d576 YZ |
2946 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
2947 | struct ixgbe_ring *ring) | |
2948 | { | |
2949 | struct ixgbe_hw *hw = &adapter->hw; | |
2950 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
2951 | u32 rxdctl; | |
2952 | u8 reg_idx = ring->reg_idx; | |
2953 | ||
2954 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2955 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
2956 | ||
2957 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
2958 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
2959 | ||
2960 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2961 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2962 | return; | |
2963 | ||
2964 | /* the hardware may take up to 100us to really disable the rx queue */ | |
2965 | do { | |
2966 | udelay(10); | |
2967 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2968 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2969 | ||
2970 | if (!wait_loop) { | |
2971 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
2972 | "the polling period\n", reg_idx); | |
2973 | } | |
2974 | } | |
2975 | ||
84418e3b AD |
2976 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
2977 | struct ixgbe_ring *ring) | |
acd37177 AD |
2978 | { |
2979 | struct ixgbe_hw *hw = &adapter->hw; | |
2980 | u64 rdba = ring->dma; | |
9e10e045 | 2981 | u32 rxdctl; |
bf29ee6c | 2982 | u8 reg_idx = ring->reg_idx; |
acd37177 | 2983 | |
9e10e045 AD |
2984 | /* disable queue to avoid issues while updating state */ |
2985 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 2986 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 2987 | |
acd37177 AD |
2988 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
2989 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
2990 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
2991 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
2992 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
2993 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 2994 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
2995 | |
2996 | ixgbe_configure_srrctl(adapter, ring); | |
2997 | ixgbe_configure_rscctl(adapter, ring); | |
2998 | ||
e9f98072 GR |
2999 | /* If operating in IOV mode set RLPML for X540 */ |
3000 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
3001 | hw->mac.type == ixgbe_mac_X540) { | |
3002 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
3003 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
3004 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
3005 | } | |
3006 | ||
9e10e045 AD |
3007 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3008 | /* | |
3009 | * enable cache line friendly hardware writes: | |
3010 | * PTHRESH=32 descriptors (half the internal cache), | |
3011 | * this also removes ugly rx_no_buffer_count increment | |
3012 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3013 | * WTHRESH=8 burst writeback up to two cache lines | |
3014 | */ | |
3015 | rxdctl &= ~0x3FFFFF; | |
3016 | rxdctl |= 0x080420; | |
3017 | } | |
3018 | ||
3019 | /* enable receive descriptor ring */ | |
3020 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3021 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3022 | ||
3023 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3024 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3025 | } |
3026 | ||
48654521 AD |
3027 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3028 | { | |
3029 | struct ixgbe_hw *hw = &adapter->hw; | |
3030 | int p; | |
3031 | ||
3032 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3033 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3034 | IXGBE_PSRTYPE_UDPHDR | |
3035 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3036 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3037 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3038 | |
3039 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3040 | return; | |
3041 | ||
3042 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
3043 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
3044 | ||
3045 | for (p = 0; p < adapter->num_rx_pools; p++) | |
3046 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
3047 | psrtype); | |
3048 | } | |
3049 | ||
f5b4a52e AD |
3050 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3051 | { | |
3052 | struct ixgbe_hw *hw = &adapter->hw; | |
3053 | u32 gcr_ext; | |
3054 | u32 vt_reg_bits; | |
3055 | u32 reg_offset, vf_shift; | |
3056 | u32 vmdctl; | |
de4c7f65 | 3057 | int i; |
f5b4a52e AD |
3058 | |
3059 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3060 | return; | |
3061 | ||
3062 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
3063 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
3064 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
3065 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
3066 | ||
3067 | vf_shift = adapter->num_vfs % 32; | |
4cd6923d | 3068 | reg_offset = (adapter->num_vfs >= 32) ? 1 : 0; |
f5b4a52e AD |
3069 | |
3070 | /* Enable only the PF's pool for Tx/Rx */ | |
3071 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
3072 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
3073 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
3074 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
3075 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
3076 | ||
3077 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3078 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3079 | ||
3080 | /* | |
3081 | * Set up VF register offsets for selected VT Mode, | |
3082 | * i.e. 32 or 64 VFs for SR-IOV | |
3083 | */ | |
3084 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3085 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
3086 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
3087 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3088 | ||
3089 | /* enable Tx loopback for VF/PF communication */ | |
3090 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 | 3091 | /* Enable MAC Anti-Spoofing */ |
a1cbb15c | 3092 | hw->mac.ops.set_mac_anti_spoofing(hw, |
de4c7f65 | 3093 | (adapter->num_vfs != 0), |
a985b6c3 | 3094 | adapter->num_vfs); |
de4c7f65 GR |
3095 | /* For VFs that have spoof checking turned off */ |
3096 | for (i = 0; i < adapter->num_vfs; i++) { | |
3097 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3098 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
3099 | } | |
f5b4a52e AD |
3100 | } |
3101 | ||
477de6ed | 3102 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3103 | { |
9a799d71 AK |
3104 | struct ixgbe_hw *hw = &adapter->hw; |
3105 | struct net_device *netdev = adapter->netdev; | |
3106 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3107 | struct ixgbe_ring *rx_ring; |
3108 | int i; | |
3109 | u32 mhadd, hlreg0; | |
48654521 | 3110 | |
63f39bd1 | 3111 | #ifdef IXGBE_FCOE |
477de6ed AD |
3112 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3113 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3114 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3115 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3116 | |
477de6ed AD |
3117 | #endif /* IXGBE_FCOE */ |
3118 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3119 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3120 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3121 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3122 | ||
3123 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3124 | } | |
3125 | ||
919e78a6 AD |
3126 | /* MHADD will allow an extra 4 bytes past for vlan tagged frames */ |
3127 | max_frame += VLAN_HLEN; | |
3128 | ||
477de6ed AD |
3129 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
3130 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3131 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3132 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3133 | |
0cefafad JB |
3134 | /* |
3135 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3136 | * the Base and Length of the Rx Descriptor Ring | |
3137 | */ | |
9a799d71 | 3138 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3139 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3140 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3141 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3142 | else |
7d637bcc | 3143 | clear_ring_rsc_enabled(rx_ring); |
63f39bd1 | 3144 | #ifdef IXGBE_FCOE |
e8e9f696 | 3145 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
3146 | struct ixgbe_ring_feature *f; |
3147 | f = &adapter->ring_feature[RING_F_FCOE]; | |
f800326d AD |
3148 | if ((i >= f->mask) && (i < f->mask + f->indices)) |
3149 | set_bit(__IXGBE_RX_FCOE_BUFSZ, &rx_ring->state); | |
63f39bd1 | 3150 | } |
63f39bd1 | 3151 | #endif /* IXGBE_FCOE */ |
477de6ed | 3152 | } |
477de6ed AD |
3153 | } |
3154 | ||
7367096a AD |
3155 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3156 | { | |
3157 | struct ixgbe_hw *hw = &adapter->hw; | |
3158 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3159 | ||
3160 | switch (hw->mac.type) { | |
3161 | case ixgbe_mac_82598EB: | |
3162 | /* | |
3163 | * For VMDq support of different descriptor types or | |
3164 | * buffer sizes through the use of multiple SRRCTL | |
3165 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3166 | * | |
3167 | * also, the manual doesn't mention it clearly but DCA hints | |
3168 | * will only use queue 0's tags unless this bit is set. Side | |
3169 | * effects of setting this bit are only that SRRCTL must be | |
3170 | * fully programmed [0..15] | |
3171 | */ | |
3172 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3173 | break; | |
3174 | case ixgbe_mac_82599EB: | |
b93a2226 | 3175 | case ixgbe_mac_X540: |
7367096a AD |
3176 | /* Disable RSC for ACK packets */ |
3177 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3178 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3179 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3180 | /* hardware requires some bits to be set by default */ | |
3181 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3182 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3183 | break; | |
3184 | default: | |
3185 | /* We should do nothing since we don't know this hardware */ | |
3186 | return; | |
3187 | } | |
3188 | ||
3189 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3190 | } | |
3191 | ||
477de6ed AD |
3192 | /** |
3193 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3194 | * @adapter: board private structure | |
3195 | * | |
3196 | * Configure the Rx unit of the MAC after a reset. | |
3197 | **/ | |
3198 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3199 | { | |
3200 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3201 | int i; |
3202 | u32 rxctrl; | |
477de6ed AD |
3203 | |
3204 | /* disable receives while setting up the descriptors */ | |
3205 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3206 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3207 | ||
3208 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3209 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3210 | |
9e10e045 | 3211 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3212 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3213 | |
9e10e045 AD |
3214 | ixgbe_set_uta(adapter); |
3215 | ||
477de6ed AD |
3216 | /* set_rx_buffer_len must be called before ring initialization */ |
3217 | ixgbe_set_rx_buffer_len(adapter); | |
3218 | ||
3219 | /* | |
3220 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3221 | * the Base and Length of the Rx Descriptor Ring | |
3222 | */ | |
9e10e045 AD |
3223 | for (i = 0; i < adapter->num_rx_queues; i++) |
3224 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3225 | |
9e10e045 AD |
3226 | /* disable drop enable for 82598 parts */ |
3227 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3228 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3229 | ||
3230 | /* enable all receives */ | |
3231 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3232 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3233 | } |
3234 | ||
8e586137 | 3235 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3236 | { |
3237 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3238 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3239 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3240 | |
3241 | /* add VID to filter table */ | |
1ada1b1b | 3242 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3243 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3244 | |
3245 | return 0; | |
068c89b0 DS |
3246 | } |
3247 | ||
8e586137 | 3248 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3249 | { |
3250 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3251 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3252 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3253 | |
068c89b0 | 3254 | /* remove VID from filter table */ |
1ada1b1b | 3255 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3256 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3257 | |
3258 | return 0; | |
068c89b0 DS |
3259 | } |
3260 | ||
5f6c0181 JB |
3261 | /** |
3262 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3263 | * @adapter: driver data | |
3264 | */ | |
3265 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3266 | { | |
3267 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3268 | u32 vlnctrl; |
3269 | ||
3270 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3271 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3272 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3273 | } | |
3274 | ||
3275 | /** | |
3276 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3277 | * @adapter: driver data | |
3278 | */ | |
3279 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3280 | { | |
3281 | struct ixgbe_hw *hw = &adapter->hw; | |
3282 | u32 vlnctrl; | |
3283 | ||
3284 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3285 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3286 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3287 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3288 | } | |
3289 | ||
3290 | /** | |
3291 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3292 | * @adapter: driver data | |
3293 | */ | |
3294 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3295 | { | |
3296 | struct ixgbe_hw *hw = &adapter->hw; | |
3297 | u32 vlnctrl; | |
5f6c0181 JB |
3298 | int i, j; |
3299 | ||
3300 | switch (hw->mac.type) { | |
3301 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3302 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3303 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3304 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3305 | break; | |
3306 | case ixgbe_mac_82599EB: | |
b93a2226 | 3307 | case ixgbe_mac_X540: |
5f6c0181 JB |
3308 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3309 | j = adapter->rx_ring[i]->reg_idx; | |
3310 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3311 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3312 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3313 | } | |
3314 | break; | |
3315 | default: | |
3316 | break; | |
3317 | } | |
3318 | } | |
3319 | ||
3320 | /** | |
f62bbb5e | 3321 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3322 | * @adapter: driver data |
3323 | */ | |
f62bbb5e | 3324 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3325 | { |
3326 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3327 | u32 vlnctrl; |
5f6c0181 JB |
3328 | int i, j; |
3329 | ||
3330 | switch (hw->mac.type) { | |
3331 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3332 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3333 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3334 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3335 | break; | |
3336 | case ixgbe_mac_82599EB: | |
b93a2226 | 3337 | case ixgbe_mac_X540: |
5f6c0181 JB |
3338 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3339 | j = adapter->rx_ring[i]->reg_idx; | |
3340 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3341 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3342 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3343 | } | |
3344 | break; | |
3345 | default: | |
3346 | break; | |
3347 | } | |
3348 | } | |
3349 | ||
9a799d71 AK |
3350 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3351 | { | |
f62bbb5e | 3352 | u16 vid; |
9a799d71 | 3353 | |
f62bbb5e JG |
3354 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3355 | ||
3356 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3357 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3358 | } |
3359 | ||
2850062a AD |
3360 | /** |
3361 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3362 | * @netdev: network interface device structure | |
3363 | * | |
3364 | * Writes unicast address list to the RAR table. | |
3365 | * Returns: -ENOMEM on failure/insufficient address space | |
3366 | * 0 on no addresses written | |
3367 | * X on writing X addresses to the RAR table | |
3368 | **/ | |
3369 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3370 | { | |
3371 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3372 | struct ixgbe_hw *hw = &adapter->hw; | |
3373 | unsigned int vfn = adapter->num_vfs; | |
a1cbb15c | 3374 | unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS; |
2850062a AD |
3375 | int count = 0; |
3376 | ||
3377 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3378 | if (netdev_uc_count(netdev) > rar_entries) | |
3379 | return -ENOMEM; | |
3380 | ||
3381 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3382 | struct netdev_hw_addr *ha; | |
3383 | /* return error if we do not support writing to RAR table */ | |
3384 | if (!hw->mac.ops.set_rar) | |
3385 | return -ENOMEM; | |
3386 | ||
3387 | netdev_for_each_uc_addr(ha, netdev) { | |
3388 | if (!rar_entries) | |
3389 | break; | |
3390 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3391 | vfn, IXGBE_RAH_AV); | |
3392 | count++; | |
3393 | } | |
3394 | } | |
3395 | /* write the addresses in reverse order to avoid write combining */ | |
3396 | for (; rar_entries > 0 ; rar_entries--) | |
3397 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3398 | ||
3399 | return count; | |
3400 | } | |
3401 | ||
9a799d71 | 3402 | /** |
2c5645cf | 3403 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3404 | * @netdev: network interface device structure |
3405 | * | |
2c5645cf CL |
3406 | * The set_rx_method entry point is called whenever the unicast/multicast |
3407 | * address list or the network interface flags are updated. This routine is | |
3408 | * responsible for configuring the hardware for proper unicast, multicast and | |
3409 | * promiscuous mode. | |
9a799d71 | 3410 | **/ |
7f870475 | 3411 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3412 | { |
3413 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3414 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3415 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3416 | int count; | |
9a799d71 AK |
3417 | |
3418 | /* Check for Promiscuous and All Multicast modes */ | |
3419 | ||
3420 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3421 | ||
f5dc442b | 3422 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 3423 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
3424 | fctrl |= IXGBE_FCTRL_BAM; |
3425 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3426 | fctrl |= IXGBE_FCTRL_PMCF; | |
3427 | ||
2850062a AD |
3428 | /* clear the bits we are changing the status of */ |
3429 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3430 | ||
9a799d71 | 3431 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3432 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3433 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3434 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3435 | /* don't hardware filter vlans in promisc mode */ |
3436 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3437 | } else { |
746b9f02 PM |
3438 | if (netdev->flags & IFF_ALLMULTI) { |
3439 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3440 | vmolr |= IXGBE_VMOLR_MPE; |
3441 | } else { | |
3442 | /* | |
3443 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3444 | * then we should just turn on promiscuous mode so |
2850062a AD |
3445 | * that we can at least receive multicast traffic |
3446 | */ | |
3447 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3448 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3449 | } |
5f6c0181 | 3450 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3451 | hw->addr_ctrl.user_set_promisc = false; |
2850062a AD |
3452 | /* |
3453 | * Write addresses to available RAR registers, if there is not | |
3454 | * sufficient space to store all the addresses then enable | |
25985edc | 3455 | * unicast promiscuous mode |
2850062a AD |
3456 | */ |
3457 | count = ixgbe_write_uc_addr_list(netdev); | |
3458 | if (count < 0) { | |
3459 | fctrl |= IXGBE_FCTRL_UPE; | |
3460 | vmolr |= IXGBE_VMOLR_ROPE; | |
3461 | } | |
9a799d71 AK |
3462 | } |
3463 | ||
2850062a | 3464 | if (adapter->num_vfs) { |
1cdd1ec8 | 3465 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3466 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3467 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3468 | IXGBE_VMOLR_ROPE); | |
3469 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3470 | } | |
3471 | ||
3f2d1c0f BG |
3472 | /* This is useful for sniffing bad packets. */ |
3473 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3474 | /* UPE and MPE will be handled by normal PROMISC logic | |
3475 | * in e1000e_set_rx_mode */ | |
3476 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
3477 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
3478 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3479 | ||
3480 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
3481 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
3482 | } | |
3483 | ||
2850062a | 3484 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e JG |
3485 | |
3486 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3487 | ixgbe_vlan_strip_enable(adapter); | |
3488 | else | |
3489 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3490 | } |
3491 | ||
021230d4 AV |
3492 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3493 | { | |
3494 | int q_idx; | |
3495 | struct ixgbe_q_vector *q_vector; | |
3496 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3497 | ||
3498 | /* legacy and MSI only use one vector */ | |
3499 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3500 | q_vectors = 1; | |
3501 | ||
3502 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3503 | q_vector = adapter->q_vector[q_idx]; |
4ff7fb12 | 3504 | napi_enable(&q_vector->napi); |
021230d4 AV |
3505 | } |
3506 | } | |
3507 | ||
3508 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3509 | { | |
3510 | int q_idx; | |
3511 | struct ixgbe_q_vector *q_vector; | |
3512 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3513 | ||
3514 | /* legacy and MSI only use one vector */ | |
3515 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3516 | q_vectors = 1; | |
3517 | ||
3518 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3519 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3520 | napi_disable(&q_vector->napi); |
3521 | } | |
3522 | } | |
3523 | ||
7a6b6f51 | 3524 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3525 | /* |
3526 | * ixgbe_configure_dcb - Configure DCB hardware | |
3527 | * @adapter: ixgbe adapter struct | |
3528 | * | |
3529 | * This is called by the driver on open to configure the DCB hardware. | |
3530 | * This is also called by the gennetlink interface when reconfiguring | |
3531 | * the DCB state. | |
3532 | */ | |
3533 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3534 | { | |
3535 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3536 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3537 | |
67ebd791 AD |
3538 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3539 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3540 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3541 | return; | |
3542 | } | |
3543 | ||
3544 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3545 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3546 | ||
2f90b865 | 3547 | |
2f90b865 | 3548 | /* Enable VLAN tag insert/strip */ |
f62bbb5e | 3549 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3550 | |
2f90b865 | 3551 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 | 3552 | |
971060b1 | 3553 | #ifdef IXGBE_FCOE |
b120818e JF |
3554 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3555 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 3556 | #endif |
b120818e JF |
3557 | |
3558 | /* reconfigure the hardware */ | |
3559 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
3560 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
3561 | DCB_TX_CONFIG); | |
3562 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3563 | DCB_RX_CONFIG); | |
3564 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
3565 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
3566 | ixgbe_dcb_hw_ets(&adapter->hw, | |
3567 | adapter->ixgbe_ieee_ets, | |
3568 | max_frame); | |
3569 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
3570 | adapter->ixgbe_ieee_pfc->pfc_en, | |
3571 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 3572 | } |
8187cd48 JF |
3573 | |
3574 | /* Enable RSS Hash per TC */ | |
3575 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3576 | int i; | |
3577 | u32 reg = 0; | |
3578 | ||
3579 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
3580 | u8 msb = 0; | |
3581 | u8 cnt = adapter->netdev->tc_to_txq[i].count; | |
3582 | ||
3583 | while (cnt >>= 1) | |
3584 | msb++; | |
3585 | ||
3586 | reg |= msb << IXGBE_RQTC_SHIFT_TC(i); | |
3587 | } | |
3588 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); | |
3589 | } | |
2f90b865 | 3590 | } |
9da712d2 JF |
3591 | #endif |
3592 | ||
3593 | /* Additional bittime to account for IXGBE framing */ | |
3594 | #define IXGBE_ETH_FRAMING 20 | |
3595 | ||
3596 | /* | |
3597 | * ixgbe_hpbthresh - calculate high water mark for flow control | |
3598 | * | |
3599 | * @adapter: board private structure to calculate for | |
3600 | * @pb - packet buffer to calculate | |
3601 | */ | |
3602 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
3603 | { | |
3604 | struct ixgbe_hw *hw = &adapter->hw; | |
3605 | struct net_device *dev = adapter->netdev; | |
3606 | int link, tc, kb, marker; | |
3607 | u32 dv_id, rx_pba; | |
3608 | ||
3609 | /* Calculate max LAN frame size */ | |
3610 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
3611 | ||
3612 | #ifdef IXGBE_FCOE | |
3613 | /* FCoE traffic class uses FCOE jumbo frames */ | |
3614 | if (dev->features & NETIF_F_FCOE_MTU) { | |
3615 | int fcoe_pb = 0; | |
2f90b865 | 3616 | |
9da712d2 JF |
3617 | #ifdef CONFIG_IXGBE_DCB |
3618 | fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up); | |
3619 | ||
3620 | #endif | |
3621 | if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
3622 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
3623 | } | |
2f90b865 | 3624 | #endif |
80605c65 | 3625 | |
9da712d2 JF |
3626 | /* Calculate delay value for device */ |
3627 | switch (hw->mac.type) { | |
3628 | case ixgbe_mac_X540: | |
3629 | dv_id = IXGBE_DV_X540(link, tc); | |
3630 | break; | |
3631 | default: | |
3632 | dv_id = IXGBE_DV(link, tc); | |
3633 | break; | |
3634 | } | |
3635 | ||
3636 | /* Loopback switch introduces additional latency */ | |
3637 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3638 | dv_id += IXGBE_B2BT(tc); | |
3639 | ||
3640 | /* Delay value is calculated in bit times convert to KB */ | |
3641 | kb = IXGBE_BT2KB(dv_id); | |
3642 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
3643 | ||
3644 | marker = rx_pba - kb; | |
3645 | ||
3646 | /* It is possible that the packet buffer is not large enough | |
3647 | * to provide required headroom. In this case throw an error | |
3648 | * to user and a do the best we can. | |
3649 | */ | |
3650 | if (marker < 0) { | |
3651 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
3652 | "headroom to support flow control." | |
3653 | "Decrease MTU or number of traffic classes\n", pb); | |
3654 | marker = tc + 1; | |
3655 | } | |
3656 | ||
3657 | return marker; | |
3658 | } | |
3659 | ||
3660 | /* | |
3661 | * ixgbe_lpbthresh - calculate low water mark for for flow control | |
3662 | * | |
3663 | * @adapter: board private structure to calculate for | |
3664 | * @pb - packet buffer to calculate | |
3665 | */ | |
3666 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) | |
3667 | { | |
3668 | struct ixgbe_hw *hw = &adapter->hw; | |
3669 | struct net_device *dev = adapter->netdev; | |
3670 | int tc; | |
3671 | u32 dv_id; | |
3672 | ||
3673 | /* Calculate max LAN frame size */ | |
3674 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
3675 | ||
3676 | /* Calculate delay value for device */ | |
3677 | switch (hw->mac.type) { | |
3678 | case ixgbe_mac_X540: | |
3679 | dv_id = IXGBE_LOW_DV_X540(tc); | |
3680 | break; | |
3681 | default: | |
3682 | dv_id = IXGBE_LOW_DV(tc); | |
3683 | break; | |
3684 | } | |
3685 | ||
3686 | /* Delay value is calculated in bit times convert to KB */ | |
3687 | return IXGBE_BT2KB(dv_id); | |
3688 | } | |
3689 | ||
3690 | /* | |
3691 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
3692 | */ | |
3693 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
3694 | { | |
3695 | struct ixgbe_hw *hw = &adapter->hw; | |
3696 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3697 | int i; | |
3698 | ||
3699 | if (!num_tc) | |
3700 | num_tc = 1; | |
3701 | ||
3702 | hw->fc.low_water = ixgbe_lpbthresh(adapter); | |
3703 | ||
3704 | for (i = 0; i < num_tc; i++) { | |
3705 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
3706 | ||
3707 | /* Low water marks must not be larger than high water marks */ | |
3708 | if (hw->fc.low_water > hw->fc.high_water[i]) | |
3709 | hw->fc.low_water = 0; | |
3710 | } | |
3711 | } | |
3712 | ||
80605c65 JF |
3713 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
3714 | { | |
80605c65 | 3715 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3716 | int hdrm; |
3717 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3718 | |
3719 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3720 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3721 | hdrm = 32 << adapter->fdir_pballoc; |
3722 | else | |
3723 | hdrm = 0; | |
80605c65 | 3724 | |
f7e1027f | 3725 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 3726 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
3727 | } |
3728 | ||
e4911d57 AD |
3729 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3730 | { | |
3731 | struct ixgbe_hw *hw = &adapter->hw; | |
3732 | struct hlist_node *node, *node2; | |
3733 | struct ixgbe_fdir_filter *filter; | |
3734 | ||
3735 | spin_lock(&adapter->fdir_perfect_lock); | |
3736 | ||
3737 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3738 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3739 | ||
3740 | hlist_for_each_entry_safe(filter, node, node2, | |
3741 | &adapter->fdir_filter_list, fdir_node) { | |
3742 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3743 | &filter->filter, |
3744 | filter->sw_idx, | |
3745 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3746 | IXGBE_FDIR_DROP_QUEUE : | |
3747 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3748 | } |
3749 | ||
3750 | spin_unlock(&adapter->fdir_perfect_lock); | |
3751 | } | |
3752 | ||
9a799d71 AK |
3753 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3754 | { | |
d2f5e7f3 AS |
3755 | struct ixgbe_hw *hw = &adapter->hw; |
3756 | ||
80605c65 | 3757 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3758 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3759 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3760 | #endif |
9a799d71 | 3761 | |
4c1d7b4b | 3762 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3763 | ixgbe_restore_vlan(adapter); |
3764 | ||
eacd73f7 YZ |
3765 | #ifdef IXGBE_FCOE |
3766 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3767 | ixgbe_configure_fcoe(adapter); | |
3768 | ||
3769 | #endif /* IXGBE_FCOE */ | |
d2f5e7f3 AS |
3770 | |
3771 | switch (hw->mac.type) { | |
3772 | case ixgbe_mac_82599EB: | |
3773 | case ixgbe_mac_X540: | |
3774 | hw->mac.ops.disable_rx_buff(hw); | |
3775 | break; | |
3776 | default: | |
3777 | break; | |
3778 | } | |
3779 | ||
c4cf55e5 | 3780 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3781 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3782 | adapter->fdir_pballoc); | |
e4911d57 AD |
3783 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3784 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3785 | adapter->fdir_pballoc); | |
3786 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3787 | } |
4c1d7b4b | 3788 | |
d2f5e7f3 AS |
3789 | switch (hw->mac.type) { |
3790 | case ixgbe_mac_82599EB: | |
3791 | case ixgbe_mac_X540: | |
3792 | hw->mac.ops.enable_rx_buff(hw); | |
3793 | break; | |
3794 | default: | |
3795 | break; | |
3796 | } | |
3797 | ||
933d41f1 | 3798 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3799 | |
9a799d71 AK |
3800 | ixgbe_configure_tx(adapter); |
3801 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3802 | } |
3803 | ||
e8e26350 PW |
3804 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3805 | { | |
3806 | switch (hw->phy.type) { | |
3807 | case ixgbe_phy_sfp_avago: | |
3808 | case ixgbe_phy_sfp_ftl: | |
3809 | case ixgbe_phy_sfp_intel: | |
3810 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3811 | case ixgbe_phy_sfp_passive_tyco: |
3812 | case ixgbe_phy_sfp_passive_unknown: | |
3813 | case ixgbe_phy_sfp_active_unknown: | |
3814 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3815 | return true; |
8917b447 AD |
3816 | case ixgbe_phy_nl: |
3817 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3818 | return true; | |
e8e26350 PW |
3819 | default: |
3820 | return false; | |
3821 | } | |
3822 | } | |
3823 | ||
0ecc061d | 3824 | /** |
e8e26350 PW |
3825 | * ixgbe_sfp_link_config - set up SFP+ link |
3826 | * @adapter: pointer to private adapter struct | |
3827 | **/ | |
3828 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3829 | { | |
7086400d | 3830 | /* |
52f33af8 | 3831 | * We are assuming the worst case scenario here, and that |
7086400d AD |
3832 | * is that an SFP was inserted/removed after the reset |
3833 | * but before SFP detection was enabled. As such the best | |
3834 | * solution is to just start searching as soon as we start | |
3835 | */ | |
3836 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3837 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3838 | |
7086400d | 3839 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3840 | } |
3841 | ||
3842 | /** | |
3843 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3844 | * @hw: pointer to private hardware struct |
3845 | * | |
3846 | * Returns 0 on success, negative on failure | |
3847 | **/ | |
e8e26350 | 3848 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3849 | { |
3850 | u32 autoneg; | |
8620a103 | 3851 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3852 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3853 | ||
3854 | if (hw->mac.ops.check_link) | |
3855 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3856 | ||
3857 | if (ret) | |
3858 | goto link_cfg_out; | |
3859 | ||
0b0c2b31 ET |
3860 | autoneg = hw->phy.autoneg_advertised; |
3861 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3862 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3863 | &negotiation); | |
0ecc061d PWJ |
3864 | if (ret) |
3865 | goto link_cfg_out; | |
3866 | ||
8620a103 MC |
3867 | if (hw->mac.ops.setup_link) |
3868 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3869 | link_cfg_out: |
3870 | return ret; | |
3871 | } | |
3872 | ||
a34bcfff | 3873 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3874 | { |
9a799d71 | 3875 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3876 | u32 gpie = 0; |
9a799d71 | 3877 | |
9b471446 | 3878 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3879 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3880 | IXGBE_GPIE_OCD; | |
3881 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3882 | /* |
3883 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3884 | * this saves a register write for every interrupt | |
3885 | */ | |
3886 | switch (hw->mac.type) { | |
3887 | case ixgbe_mac_82598EB: | |
3888 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3889 | break; | |
9b471446 | 3890 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3891 | case ixgbe_mac_X540: |
3892 | default: | |
9b471446 JB |
3893 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3894 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3895 | break; | |
3896 | } | |
3897 | } else { | |
021230d4 AV |
3898 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3899 | * specifically only auto mask tx and rx interrupts */ | |
3900 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3901 | } | |
9a799d71 | 3902 | |
a34bcfff AD |
3903 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3904 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3905 | ||
3906 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3907 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3908 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3909 | } |
3910 | ||
5fdd31f9 | 3911 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
3912 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
3913 | switch (adapter->hw.mac.type) { | |
3914 | case ixgbe_mac_82599EB: | |
3915 | gpie |= IXGBE_SDP0_GPIEN; | |
3916 | break; | |
3917 | case ixgbe_mac_X540: | |
3918 | gpie |= IXGBE_EIMS_TS; | |
3919 | break; | |
3920 | default: | |
3921 | break; | |
3922 | } | |
3923 | } | |
5fdd31f9 | 3924 | |
a34bcfff AD |
3925 | /* Enable fan failure interrupt */ |
3926 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3927 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3928 | |
2698b208 | 3929 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3930 | gpie |= IXGBE_SDP1_GPIEN; |
3931 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3932 | } |
a34bcfff AD |
3933 | |
3934 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3935 | } | |
3936 | ||
c7ccde0f | 3937 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
3938 | { |
3939 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3940 | int err; |
a34bcfff AD |
3941 | u32 ctrl_ext; |
3942 | ||
3943 | ixgbe_get_hw_control(adapter); | |
3944 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3945 | |
9a799d71 AK |
3946 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3947 | ixgbe_configure_msix(adapter); | |
3948 | else | |
3949 | ixgbe_configure_msi_and_legacy(adapter); | |
3950 | ||
c6ecf39a DS |
3951 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3952 | if (hw->mac.ops.enable_tx_laser && | |
3953 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3954 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3955 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3956 | hw->mac.ops.enable_tx_laser(hw); |
3957 | ||
9a799d71 | 3958 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3959 | ixgbe_napi_enable_all(adapter); |
3960 | ||
73c4b7cd AD |
3961 | if (ixgbe_is_sfp(hw)) { |
3962 | ixgbe_sfp_link_config(adapter); | |
3963 | } else { | |
3964 | err = ixgbe_non_sfp_link_config(hw); | |
3965 | if (err) | |
3966 | e_err(probe, "link_config FAILED %d\n", err); | |
3967 | } | |
3968 | ||
021230d4 AV |
3969 | /* clear any pending interrupts, may auto mask */ |
3970 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3971 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3972 | |
bf069c97 DS |
3973 | /* |
3974 | * If this adapter has a fan, check to see if we had a failure | |
3975 | * before we enabled the interrupt. | |
3976 | */ | |
3977 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3978 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3979 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3980 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3981 | } |
3982 | ||
1da100bb | 3983 | /* enable transmits */ |
477de6ed | 3984 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 3985 | |
9a799d71 AK |
3986 | /* bring the link up in the watchdog, this could race with our first |
3987 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3988 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3989 | adapter->link_check_timeout = jiffies; | |
7086400d | 3990 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
3991 | |
3992 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3993 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3994 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3995 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
3996 | } |
3997 | ||
d4f80882 AV |
3998 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3999 | { | |
4000 | WARN_ON(in_interrupt()); | |
7086400d AD |
4001 | /* put off any impending NetWatchDogTimeout */ |
4002 | adapter->netdev->trans_start = jiffies; | |
4003 | ||
d4f80882 | 4004 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 4005 | usleep_range(1000, 2000); |
d4f80882 | 4006 | ixgbe_down(adapter); |
5809a1ae GR |
4007 | /* |
4008 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
4009 | * back up to give the VFs time to respond to the reset. The | |
4010 | * two second wait is based upon the watchdog timer cycle in | |
4011 | * the VF driver. | |
4012 | */ | |
4013 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4014 | msleep(2000); | |
d4f80882 AV |
4015 | ixgbe_up(adapter); |
4016 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
4017 | } | |
4018 | ||
c7ccde0f | 4019 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4020 | { |
4021 | /* hardware has been reset, we need to reload some things */ | |
4022 | ixgbe_configure(adapter); | |
4023 | ||
c7ccde0f | 4024 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4025 | } |
4026 | ||
4027 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
4028 | { | |
c44ade9e | 4029 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
4030 | int err; |
4031 | ||
7086400d AD |
4032 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
4033 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
4034 | usleep_range(1000, 2000); | |
4035 | ||
4036 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
4037 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
4038 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
4039 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
4040 | ||
8ca783ab | 4041 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
4042 | switch (err) { |
4043 | case 0: | |
4044 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 4045 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
4046 | break; |
4047 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 4048 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 4049 | break; |
794caeb2 PWJ |
4050 | case IXGBE_ERR_EEPROM_VERSION: |
4051 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 4052 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 4053 | "Please be aware there may be issues associated with " |
849c4542 ET |
4054 | "your hardware. If you are experiencing problems " |
4055 | "please contact your Intel or hardware " | |
4056 | "representative who provided you with this " | |
4057 | "hardware.\n"); | |
794caeb2 | 4058 | break; |
da4dd0f7 | 4059 | default: |
849c4542 | 4060 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 4061 | } |
9a799d71 | 4062 | |
7086400d AD |
4063 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
4064 | ||
9a799d71 | 4065 | /* reprogram the RAR[0] in case user changed it. */ |
1cdd1ec8 GR |
4066 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
4067 | IXGBE_RAH_AV); | |
9a799d71 AK |
4068 | } |
4069 | ||
f800326d AD |
4070 | /** |
4071 | * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers | |
4072 | * @rx_ring: ring to setup | |
4073 | * | |
4074 | * On many IA platforms the L1 cache has a critical stride of 4K, this | |
4075 | * results in each receive buffer starting in the same cache set. To help | |
4076 | * reduce the pressure on this cache set we can interleave the offsets so | |
4077 | * that only every other buffer will be in the same cache set. | |
4078 | **/ | |
4079 | static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring) | |
4080 | { | |
4081 | struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info; | |
4082 | u16 i; | |
4083 | ||
4084 | for (i = 0; i < rx_ring->count; i += 2) { | |
4085 | rx_buffer[0].page_offset = 0; | |
4086 | rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring); | |
4087 | rx_buffer = &rx_buffer[2]; | |
4088 | } | |
4089 | } | |
4090 | ||
9a799d71 AK |
4091 | /** |
4092 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4093 | * @rx_ring: ring to free buffers from |
4094 | **/ | |
b6ec895e | 4095 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4096 | { |
b6ec895e | 4097 | struct device *dev = rx_ring->dev; |
9a799d71 | 4098 | unsigned long size; |
b6ec895e | 4099 | u16 i; |
9a799d71 | 4100 | |
84418e3b AD |
4101 | /* ring already cleared, nothing to do */ |
4102 | if (!rx_ring->rx_buffer_info) | |
4103 | return; | |
9a799d71 | 4104 | |
84418e3b | 4105 | /* Free all the Rx ring sk_buffs */ |
9a799d71 | 4106 | for (i = 0; i < rx_ring->count; i++) { |
f800326d AD |
4107 | struct ixgbe_rx_buffer *rx_buffer; |
4108 | ||
4109 | rx_buffer = &rx_ring->rx_buffer_info[i]; | |
4110 | if (rx_buffer->skb) { | |
4111 | struct sk_buff *skb = rx_buffer->skb; | |
4112 | if (IXGBE_CB(skb)->page_released) { | |
4113 | dma_unmap_page(dev, | |
4114 | IXGBE_CB(skb)->dma, | |
4115 | ixgbe_rx_bufsz(rx_ring), | |
4116 | DMA_FROM_DEVICE); | |
4117 | IXGBE_CB(skb)->page_released = false; | |
4c1975d7 AD |
4118 | } |
4119 | dev_kfree_skb(skb); | |
9a799d71 | 4120 | } |
f800326d AD |
4121 | rx_buffer->skb = NULL; |
4122 | if (rx_buffer->dma) | |
4123 | dma_unmap_page(dev, rx_buffer->dma, | |
4124 | ixgbe_rx_pg_size(rx_ring), | |
4125 | DMA_FROM_DEVICE); | |
4126 | rx_buffer->dma = 0; | |
4127 | if (rx_buffer->page) | |
4128 | put_page(rx_buffer->page); | |
4129 | rx_buffer->page = NULL; | |
9a799d71 AK |
4130 | } |
4131 | ||
4132 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4133 | memset(rx_ring->rx_buffer_info, 0, size); | |
4134 | ||
f800326d AD |
4135 | ixgbe_init_rx_page_offset(rx_ring); |
4136 | ||
9a799d71 AK |
4137 | /* Zero out the descriptor ring */ |
4138 | memset(rx_ring->desc, 0, rx_ring->size); | |
4139 | ||
f800326d | 4140 | rx_ring->next_to_alloc = 0; |
9a799d71 AK |
4141 | rx_ring->next_to_clean = 0; |
4142 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4143 | } |
4144 | ||
4145 | /** | |
4146 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4147 | * @tx_ring: ring to be cleaned |
4148 | **/ | |
b6ec895e | 4149 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4150 | { |
4151 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4152 | unsigned long size; | |
b6ec895e | 4153 | u16 i; |
9a799d71 | 4154 | |
84418e3b AD |
4155 | /* ring already cleared, nothing to do */ |
4156 | if (!tx_ring->tx_buffer_info) | |
4157 | return; | |
9a799d71 | 4158 | |
84418e3b | 4159 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4160 | for (i = 0; i < tx_ring->count; i++) { |
4161 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4162 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4163 | } |
4164 | ||
4165 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
4166 | memset(tx_ring->tx_buffer_info, 0, size); | |
4167 | ||
4168 | /* Zero out the descriptor ring */ | |
4169 | memset(tx_ring->desc, 0, tx_ring->size); | |
4170 | ||
4171 | tx_ring->next_to_use = 0; | |
4172 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4173 | } |
4174 | ||
4175 | /** | |
021230d4 | 4176 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4177 | * @adapter: board private structure |
4178 | **/ | |
021230d4 | 4179 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4180 | { |
4181 | int i; | |
4182 | ||
021230d4 | 4183 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4184 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4185 | } |
4186 | ||
4187 | /** | |
021230d4 | 4188 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4189 | * @adapter: board private structure |
4190 | **/ | |
021230d4 | 4191 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4192 | { |
4193 | int i; | |
4194 | ||
021230d4 | 4195 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4196 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4197 | } |
4198 | ||
e4911d57 AD |
4199 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
4200 | { | |
4201 | struct hlist_node *node, *node2; | |
4202 | struct ixgbe_fdir_filter *filter; | |
4203 | ||
4204 | spin_lock(&adapter->fdir_perfect_lock); | |
4205 | ||
4206 | hlist_for_each_entry_safe(filter, node, node2, | |
4207 | &adapter->fdir_filter_list, fdir_node) { | |
4208 | hlist_del(&filter->fdir_node); | |
4209 | kfree(filter); | |
4210 | } | |
4211 | adapter->fdir_filter_count = 0; | |
4212 | ||
4213 | spin_unlock(&adapter->fdir_perfect_lock); | |
4214 | } | |
4215 | ||
9a799d71 AK |
4216 | void ixgbe_down(struct ixgbe_adapter *adapter) |
4217 | { | |
4218 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4219 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4220 | u32 rxctrl; |
bf29ee6c | 4221 | int i; |
9a799d71 AK |
4222 | |
4223 | /* signal that we are down to the interrupt handler */ | |
4224 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4225 | ||
4226 | /* disable receives */ | |
7f821875 JB |
4227 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4228 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4229 | |
2d39d576 YZ |
4230 | /* disable all enabled rx queues */ |
4231 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4232 | /* this call also flushes the previous write */ | |
4233 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4234 | ||
032b4325 | 4235 | usleep_range(10000, 20000); |
9a799d71 | 4236 | |
7f821875 JB |
4237 | netif_tx_stop_all_queues(netdev); |
4238 | ||
7086400d | 4239 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4240 | netif_carrier_off(netdev); |
4241 | netif_tx_disable(netdev); | |
4242 | ||
4243 | ixgbe_irq_disable(adapter); | |
4244 | ||
4245 | ixgbe_napi_disable_all(adapter); | |
4246 | ||
d034acf1 AD |
4247 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4248 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4249 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4250 | ||
4251 | del_timer_sync(&adapter->service_timer); | |
4252 | ||
34cecbbf | 4253 | if (adapter->num_vfs) { |
8e34d1aa AD |
4254 | /* Clear EITR Select mapping */ |
4255 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
4256 | |
4257 | /* Mark all the VFs as inactive */ | |
4258 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 4259 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 4260 | |
34cecbbf AD |
4261 | /* ping all the active vfs to let them know we are going down */ |
4262 | ixgbe_ping_all_vfs(adapter); | |
4263 | ||
4264 | /* Disable all VFTE/VFRE TX/RX */ | |
4265 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
4266 | } |
4267 | ||
7f821875 JB |
4268 | /* disable transmits in the hardware now that interrupts are off */ |
4269 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4270 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4271 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4272 | } |
34cecbbf AD |
4273 | |
4274 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4275 | switch (hw->mac.type) { |
4276 | case ixgbe_mac_82599EB: | |
b93a2226 | 4277 | case ixgbe_mac_X540: |
88512539 | 4278 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4279 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4280 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4281 | break; |
4282 | default: | |
4283 | break; | |
4284 | } | |
7f821875 | 4285 | |
6f4a0e45 PL |
4286 | if (!pci_channel_offline(adapter->pdev)) |
4287 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4288 | |
4289 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4290 | if (hw->mac.ops.disable_tx_laser && | |
4291 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4292 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4293 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4294 | hw->mac.ops.disable_tx_laser(hw); | |
4295 | ||
9a799d71 AK |
4296 | ixgbe_clean_all_tx_rings(adapter); |
4297 | ixgbe_clean_all_rx_rings(adapter); | |
4298 | ||
5dd2d332 | 4299 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4300 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4301 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4302 | #endif |
9a799d71 AK |
4303 | } |
4304 | ||
9a799d71 AK |
4305 | /** |
4306 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4307 | * @netdev: network interface device structure | |
4308 | **/ | |
4309 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4310 | { | |
4311 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4312 | ||
4313 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4314 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4315 | } |
4316 | ||
4df10466 JB |
4317 | /** |
4318 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
4319 | * @adapter: board private structure to initialize | |
4320 | * | |
4321 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
4322 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
4323 | * | |
4324 | **/ | |
bc97114d PWJ |
4325 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
4326 | { | |
4327 | bool ret = false; | |
0cefafad | 4328 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
4329 | |
4330 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
4331 | f->mask = 0xF; |
4332 | adapter->num_rx_queues = f->indices; | |
4333 | adapter->num_tx_queues = f->indices; | |
bc97114d | 4334 | ret = true; |
b9804972 JB |
4335 | } |
4336 | ||
bc97114d PWJ |
4337 | return ret; |
4338 | } | |
4339 | ||
c4cf55e5 PWJ |
4340 | /** |
4341 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
4342 | * @adapter: board private structure to initialize | |
4343 | * | |
4344 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
4345 | * to the original CPU that initiated the Tx session. This runs in addition | |
4346 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
4347 | * Rx load across CPUs using RSS. | |
4348 | * | |
4349 | **/ | |
e8e9f696 | 4350 | static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4351 | { |
4352 | bool ret = false; | |
4353 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
4354 | ||
6ca43507 | 4355 | f_fdir->indices = min_t(int, num_online_cpus(), f_fdir->indices); |
c4cf55e5 PWJ |
4356 | f_fdir->mask = 0; |
4357 | ||
24ddd967 AD |
4358 | /* |
4359 | * Use RSS in addition to Flow Director to ensure the best | |
4360 | * distribution of flows across cores, even when an FDIR flow | |
4361 | * isn't matched. | |
4362 | */ | |
03ecf91a AD |
4363 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && |
4364 | (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) { | |
c4cf55e5 PWJ |
4365 | adapter->num_tx_queues = f_fdir->indices; |
4366 | adapter->num_rx_queues = f_fdir->indices; | |
4367 | ret = true; | |
4368 | } else { | |
4369 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
c4cf55e5 PWJ |
4370 | } |
4371 | return ret; | |
4372 | } | |
4373 | ||
0331a832 YZ |
4374 | #ifdef IXGBE_FCOE |
4375 | /** | |
4376 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
4377 | * @adapter: board private structure to initialize | |
4378 | * | |
4379 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
4380 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
4381 | * rx queues out of the max number of rx queues, instead, it is used as the | |
4382 | * index of the first rx queue used by FCoE. | |
4383 | * | |
4384 | **/ | |
4385 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
4386 | { | |
0331a832 YZ |
4387 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
4388 | ||
e5b64635 JF |
4389 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) |
4390 | return false; | |
4391 | ||
3ed69d7e | 4392 | f->indices = min_t(int, num_online_cpus(), f->indices); |
e5b64635 | 4393 | |
e901acd6 JF |
4394 | adapter->num_rx_queues = 1; |
4395 | adapter->num_tx_queues = 1; | |
e5b64635 | 4396 | |
e901acd6 JF |
4397 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
4398 | e_info(probe, "FCoE enabled with RSS\n"); | |
03ecf91a | 4399 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
e901acd6 JF |
4400 | ixgbe_set_fdir_queues(adapter); |
4401 | else | |
4402 | ixgbe_set_rss_queues(adapter); | |
e5b64635 | 4403 | } |
03ecf91a | 4404 | |
e901acd6 JF |
4405 | /* adding FCoE rx rings to the end */ |
4406 | f->mask = adapter->num_rx_queues; | |
4407 | adapter->num_rx_queues += f->indices; | |
4408 | adapter->num_tx_queues += f->indices; | |
0331a832 | 4409 | |
e5b64635 JF |
4410 | return true; |
4411 | } | |
4412 | #endif /* IXGBE_FCOE */ | |
4413 | ||
e901acd6 JF |
4414 | /* Artificial max queue cap per traffic class in DCB mode */ |
4415 | #define DCB_QUEUE_CAP 8 | |
4416 | ||
e5b64635 JF |
4417 | #ifdef CONFIG_IXGBE_DCB |
4418 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
4419 | { | |
e901acd6 JF |
4420 | int per_tc_q, q, i, offset = 0; |
4421 | struct net_device *dev = adapter->netdev; | |
4422 | int tcs = netdev_get_num_tc(dev); | |
e5b64635 | 4423 | |
e901acd6 JF |
4424 | if (!tcs) |
4425 | return false; | |
e5b64635 | 4426 | |
e901acd6 | 4427 | /* Map queue offset and counts onto allocated tx queues */ |
3ed69d7e JB |
4428 | per_tc_q = min_t(unsigned int, dev->num_tx_queues / tcs, DCB_QUEUE_CAP); |
4429 | q = min_t(int, num_online_cpus(), per_tc_q); | |
8b1c0b24 | 4430 | |
8b1c0b24 | 4431 | for (i = 0; i < tcs; i++) { |
e901acd6 JF |
4432 | netdev_set_tc_queue(dev, i, q, offset); |
4433 | offset += q; | |
0331a832 YZ |
4434 | } |
4435 | ||
e901acd6 JF |
4436 | adapter->num_tx_queues = q * tcs; |
4437 | adapter->num_rx_queues = q * tcs; | |
e5b64635 JF |
4438 | |
4439 | #ifdef IXGBE_FCOE | |
e901acd6 JF |
4440 | /* FCoE enabled queues require special configuration indexed |
4441 | * by feature specific indices and mask. Here we map FCoE | |
4442 | * indices onto the DCB queue pairs allowing FCoE to own | |
4443 | * configuration later. | |
e5b64635 | 4444 | */ |
e901acd6 | 4445 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
cdf485be | 4446 | u8 prio_tc[MAX_USER_PRIORITY] = {0}; |
e901acd6 JF |
4447 | int tc; |
4448 | struct ixgbe_ring_feature *f = | |
4449 | &adapter->ring_feature[RING_F_FCOE]; | |
4450 | ||
cdf485be JF |
4451 | ixgbe_dcb_unpack_map(&adapter->dcb_cfg, DCB_TX_CONFIG, prio_tc); |
4452 | tc = prio_tc[adapter->fcoe.up]; | |
e901acd6 JF |
4453 | f->indices = dev->tc_to_txq[tc].count; |
4454 | f->mask = dev->tc_to_txq[tc].offset; | |
4455 | } | |
e5b64635 JF |
4456 | #endif |
4457 | ||
e901acd6 | 4458 | return true; |
0331a832 | 4459 | } |
e5b64635 | 4460 | #endif |
0331a832 | 4461 | |
1cdd1ec8 GR |
4462 | /** |
4463 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
4464 | * @adapter: board private structure to initialize | |
4465 | * | |
4466 | * IOV doesn't actually use anything, so just NAK the | |
4467 | * request for now and let the other queue routines | |
4468 | * figure out what to do. | |
4469 | */ | |
4470 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
4471 | { | |
4472 | return false; | |
4473 | } | |
4474 | ||
4df10466 | 4475 | /* |
25985edc | 4476 | * ixgbe_set_num_queues: Allocate queues for device, feature dependent |
4df10466 JB |
4477 | * @adapter: board private structure to initialize |
4478 | * | |
4479 | * This is the top level queue allocation routine. The order here is very | |
4480 | * important, starting with the "most" number of features turned on at once, | |
4481 | * and ending with the smallest set of features. This way large combinations | |
4482 | * can be allocated if they're turned on, and smaller combinations are the | |
4483 | * fallthrough conditions. | |
4484 | * | |
4485 | **/ | |
847f53ff | 4486 | static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
bc97114d | 4487 | { |
1cdd1ec8 GR |
4488 | /* Start with base case */ |
4489 | adapter->num_rx_queues = 1; | |
4490 | adapter->num_tx_queues = 1; | |
4491 | adapter->num_rx_pools = adapter->num_rx_queues; | |
4492 | adapter->num_rx_queues_per_pool = 1; | |
4493 | ||
4494 | if (ixgbe_set_sriov_queues(adapter)) | |
847f53ff | 4495 | goto done; |
1cdd1ec8 | 4496 | |
bc97114d PWJ |
4497 | #ifdef CONFIG_IXGBE_DCB |
4498 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 4499 | goto done; |
bc97114d PWJ |
4500 | |
4501 | #endif | |
e5b64635 JF |
4502 | #ifdef IXGBE_FCOE |
4503 | if (ixgbe_set_fcoe_queues(adapter)) | |
4504 | goto done; | |
4505 | ||
4506 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
4507 | if (ixgbe_set_fdir_queues(adapter)) |
4508 | goto done; | |
4509 | ||
bc97114d | 4510 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
4511 | goto done; |
4512 | ||
4513 | /* fallback to base case */ | |
4514 | adapter->num_rx_queues = 1; | |
4515 | adapter->num_tx_queues = 1; | |
4516 | ||
4517 | done: | |
9d837ea2 YZ |
4518 | if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) || |
4519 | (adapter->netdev->reg_state == NETREG_UNREGISTERING)) | |
4520 | return 0; | |
4521 | ||
847f53ff | 4522 | /* Notify the stack of the (possibly) reduced queue counts. */ |
f0796d5c | 4523 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); |
847f53ff BH |
4524 | return netif_set_real_num_rx_queues(adapter->netdev, |
4525 | adapter->num_rx_queues); | |
b9804972 JB |
4526 | } |
4527 | ||
021230d4 | 4528 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
e8e9f696 | 4529 | int vectors) |
021230d4 AV |
4530 | { |
4531 | int err, vector_threshold; | |
4532 | ||
8f15486d AD |
4533 | /* We'll want at least 2 (vector_threshold): |
4534 | * 1) TxQ[0] + RxQ[0] handler | |
4535 | * 2) Other (Link Status Change, etc.) | |
021230d4 AV |
4536 | */ |
4537 | vector_threshold = MIN_MSIX_COUNT; | |
4538 | ||
24ddd967 AD |
4539 | /* |
4540 | * The more we get, the more we will assign to Tx/Rx Cleanup | |
021230d4 AV |
4541 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. |
4542 | * Right now, we simply care about how many we'll get; we'll | |
4543 | * set them up later while requesting irq's. | |
4544 | */ | |
4545 | while (vectors >= vector_threshold) { | |
4546 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
e8e9f696 | 4547 | vectors); |
021230d4 AV |
4548 | if (!err) /* Success in acquiring all requested vectors. */ |
4549 | break; | |
4550 | else if (err < 0) | |
4551 | vectors = 0; /* Nasty failure, quit now */ | |
4552 | else /* err == number of vectors we should try again with */ | |
4553 | vectors = err; | |
4554 | } | |
4555 | ||
4556 | if (vectors < vector_threshold) { | |
4557 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
4558 | * This just means we'll go with either a single MSI | |
4559 | * vector or fall back to legacy interrupts. | |
4560 | */ | |
849c4542 ET |
4561 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4562 | "Unable to allocate MSI-X interrupts\n"); | |
021230d4 AV |
4563 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
4564 | kfree(adapter->msix_entries); | |
4565 | adapter->msix_entries = NULL; | |
021230d4 AV |
4566 | } else { |
4567 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
4568 | /* |
4569 | * Adjust for only the vectors we'll use, which is minimum | |
4570 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
4571 | * vectors we were allocated. | |
4572 | */ | |
4573 | adapter->num_msix_vectors = min(vectors, | |
e8e9f696 | 4574 | adapter->max_msix_q_vectors + NON_Q_VECTORS); |
021230d4 AV |
4575 | } |
4576 | } | |
4577 | ||
021230d4 | 4578 | /** |
bc97114d | 4579 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
4580 | * @adapter: board private structure to initialize |
4581 | * | |
bc97114d PWJ |
4582 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
4583 | * | |
021230d4 | 4584 | **/ |
bc97114d | 4585 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 4586 | { |
bc97114d | 4587 | int i; |
bc97114d | 4588 | |
9d6b758f AD |
4589 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) |
4590 | return false; | |
bc97114d | 4591 | |
9d6b758f AD |
4592 | for (i = 0; i < adapter->num_rx_queues; i++) |
4593 | adapter->rx_ring[i]->reg_idx = i; | |
4594 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4595 | adapter->tx_ring[i]->reg_idx = i; | |
4596 | ||
4597 | return true; | |
bc97114d PWJ |
4598 | } |
4599 | ||
4600 | #ifdef CONFIG_IXGBE_DCB | |
e5b64635 JF |
4601 | |
4602 | /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ | |
b32c8dcc JF |
4603 | static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, |
4604 | unsigned int *tx, unsigned int *rx) | |
e5b64635 JF |
4605 | { |
4606 | struct net_device *dev = adapter->netdev; | |
4607 | struct ixgbe_hw *hw = &adapter->hw; | |
4608 | u8 num_tcs = netdev_get_num_tc(dev); | |
4609 | ||
4610 | *tx = 0; | |
4611 | *rx = 0; | |
4612 | ||
4613 | switch (hw->mac.type) { | |
4614 | case ixgbe_mac_82598EB: | |
aba70d5e JF |
4615 | *tx = tc << 2; |
4616 | *rx = tc << 3; | |
e5b64635 JF |
4617 | break; |
4618 | case ixgbe_mac_82599EB: | |
4619 | case ixgbe_mac_X540: | |
4fa2e0e1 | 4620 | if (num_tcs > 4) { |
e5b64635 JF |
4621 | if (tc < 3) { |
4622 | *tx = tc << 5; | |
4623 | *rx = tc << 4; | |
4624 | } else if (tc < 5) { | |
4625 | *tx = ((tc + 2) << 4); | |
4626 | *rx = tc << 4; | |
4627 | } else if (tc < num_tcs) { | |
4628 | *tx = ((tc + 8) << 3); | |
4629 | *rx = tc << 4; | |
4630 | } | |
4fa2e0e1 | 4631 | } else { |
e5b64635 JF |
4632 | *rx = tc << 5; |
4633 | switch (tc) { | |
4634 | case 0: | |
4635 | *tx = 0; | |
4636 | break; | |
4637 | case 1: | |
4638 | *tx = 64; | |
4639 | break; | |
4640 | case 2: | |
4641 | *tx = 96; | |
4642 | break; | |
4643 | case 3: | |
4644 | *tx = 112; | |
4645 | break; | |
4646 | default: | |
4647 | break; | |
4648 | } | |
4649 | } | |
4650 | break; | |
4651 | default: | |
4652 | break; | |
4653 | } | |
4654 | } | |
4655 | ||
bc97114d PWJ |
4656 | /** |
4657 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
4658 | * @adapter: board private structure to initialize | |
4659 | * | |
4660 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
4661 | * | |
4662 | **/ | |
4663 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
4664 | { | |
e5b64635 JF |
4665 | struct net_device *dev = adapter->netdev; |
4666 | int i, j, k; | |
4667 | u8 num_tcs = netdev_get_num_tc(dev); | |
bc97114d | 4668 | |
8b1c0b24 | 4669 | if (!num_tcs) |
bd508178 | 4670 | return false; |
f92ef202 | 4671 | |
e5b64635 JF |
4672 | for (i = 0, k = 0; i < num_tcs; i++) { |
4673 | unsigned int tx_s, rx_s; | |
4674 | u16 count = dev->tc_to_txq[i].count; | |
4675 | ||
4676 | ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); | |
4677 | for (j = 0; j < count; j++, k++) { | |
4678 | adapter->tx_ring[k]->reg_idx = tx_s + j; | |
4679 | adapter->rx_ring[k]->reg_idx = rx_s + j; | |
4680 | adapter->tx_ring[k]->dcb_tc = i; | |
4681 | adapter->rx_ring[k]->dcb_tc = i; | |
021230d4 | 4682 | } |
021230d4 | 4683 | } |
e5b64635 JF |
4684 | |
4685 | return true; | |
bc97114d PWJ |
4686 | } |
4687 | #endif | |
4688 | ||
c4cf55e5 PWJ |
4689 | /** |
4690 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
4691 | * @adapter: board private structure to initialize | |
4692 | * | |
4693 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
4694 | * | |
4695 | **/ | |
e8e9f696 | 4696 | static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4697 | { |
4698 | int i; | |
4699 | bool ret = false; | |
4700 | ||
03ecf91a AD |
4701 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && |
4702 | (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) { | |
c4cf55e5 | 4703 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 4704 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 4705 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4706 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
4707 | ret = true; |
4708 | } | |
4709 | ||
4710 | return ret; | |
4711 | } | |
4712 | ||
0331a832 YZ |
4713 | #ifdef IXGBE_FCOE |
4714 | /** | |
4715 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
4716 | * @adapter: board private structure to initialize | |
4717 | * | |
4718 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
4719 | * | |
4720 | */ | |
4721 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
4722 | { | |
0331a832 | 4723 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
bf29ee6c AD |
4724 | int i; |
4725 | u8 fcoe_rx_i = 0, fcoe_tx_i = 0; | |
4726 | ||
4727 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
4728 | return false; | |
0331a832 | 4729 | |
bf29ee6c | 4730 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
03ecf91a | 4731 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
bf29ee6c AD |
4732 | ixgbe_cache_ring_fdir(adapter); |
4733 | else | |
4734 | ixgbe_cache_ring_rss(adapter); | |
8faa2a78 | 4735 | |
bf29ee6c AD |
4736 | fcoe_rx_i = f->mask; |
4737 | fcoe_tx_i = f->mask; | |
0331a832 | 4738 | } |
bf29ee6c AD |
4739 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { |
4740 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; | |
4741 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
4742 | } | |
4743 | return true; | |
0331a832 YZ |
4744 | } |
4745 | ||
4746 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4747 | /** |
4748 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
4749 | * @adapter: board private structure to initialize | |
4750 | * | |
4751 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
4752 | * no other mapping is used. | |
4753 | * | |
4754 | */ | |
4755 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
4756 | { | |
4a0b9ca0 PW |
4757 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
4758 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
4759 | if (adapter->num_vfs) |
4760 | return true; | |
4761 | else | |
4762 | return false; | |
4763 | } | |
4764 | ||
bc97114d PWJ |
4765 | /** |
4766 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
4767 | * @adapter: board private structure to initialize | |
4768 | * | |
4769 | * Once we know the feature-set enabled for the device, we'll cache | |
4770 | * the register offset the descriptor ring is assigned to. | |
4771 | * | |
4772 | * Note, the order the various feature calls is important. It must start with | |
4773 | * the "most" features enabled at the same time, then trickle down to the | |
4774 | * least amount of features turned on at once. | |
4775 | **/ | |
4776 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
4777 | { | |
4778 | /* start with default case */ | |
4a0b9ca0 PW |
4779 | adapter->rx_ring[0]->reg_idx = 0; |
4780 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 4781 | |
1cdd1ec8 GR |
4782 | if (ixgbe_cache_ring_sriov(adapter)) |
4783 | return; | |
4784 | ||
e5b64635 JF |
4785 | #ifdef CONFIG_IXGBE_DCB |
4786 | if (ixgbe_cache_ring_dcb(adapter)) | |
4787 | return; | |
4788 | #endif | |
4789 | ||
0331a832 YZ |
4790 | #ifdef IXGBE_FCOE |
4791 | if (ixgbe_cache_ring_fcoe(adapter)) | |
4792 | return; | |
0331a832 | 4793 | #endif /* IXGBE_FCOE */ |
bc97114d | 4794 | |
c4cf55e5 PWJ |
4795 | if (ixgbe_cache_ring_fdir(adapter)) |
4796 | return; | |
4797 | ||
bc97114d PWJ |
4798 | if (ixgbe_cache_ring_rss(adapter)) |
4799 | return; | |
021230d4 AV |
4800 | } |
4801 | ||
021230d4 AV |
4802 | /** |
4803 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
4804 | * @adapter: board private structure to initialize | |
4805 | * | |
4806 | * Attempt to configure the interrupts using the best available | |
4807 | * capabilities of the hardware and the kernel. | |
4808 | **/ | |
feea6a57 | 4809 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 4810 | { |
8be0e467 | 4811 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
4812 | int err = 0; |
4813 | int vector, v_budget; | |
4814 | ||
4815 | /* | |
4816 | * It's easy to be greedy for MSI-X vectors, but it really | |
4817 | * doesn't do us much good if we have a lot more vectors | |
4818 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 4819 | * (roughly) the same number of vectors as there are CPU's. |
8f15486d | 4820 | * The default is to use pairs of vectors. |
021230d4 | 4821 | */ |
8f15486d AD |
4822 | v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues); |
4823 | v_budget = min_t(int, v_budget, num_online_cpus()); | |
4824 | v_budget += NON_Q_VECTORS; | |
021230d4 AV |
4825 | |
4826 | /* | |
4827 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
4828 | * hw.mac->max_msix_vectors vectors. With features |
4829 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
4830 | * descriptor queues supported by our device. Thus, we cap it off in | |
4831 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 4832 | */ |
de88eeeb | 4833 | v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); |
021230d4 AV |
4834 | |
4835 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
4836 | * mean we disable MSI-X capabilities of the adapter. */ | |
4837 | adapter->msix_entries = kcalloc(v_budget, | |
e8e9f696 | 4838 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
4839 | if (adapter->msix_entries) { |
4840 | for (vector = 0; vector < v_budget; vector++) | |
4841 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 4842 | |
7a921c93 | 4843 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 4844 | |
7a921c93 AD |
4845 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4846 | goto out; | |
4847 | } | |
26d27844 | 4848 | |
7a921c93 AD |
4849 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
4850 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
03ecf91a | 4851 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
45b9f509 | 4852 | e_err(probe, |
03ecf91a | 4853 | "ATR is not supported while multiple " |
45b9f509 AD |
4854 | "queues are disabled. Disabling Flow Director\n"); |
4855 | } | |
c4cf55e5 | 4856 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
c4cf55e5 | 4857 | adapter->atr_sample_rate = 0; |
1cdd1ec8 GR |
4858 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
4859 | ixgbe_disable_sriov(adapter); | |
4860 | ||
847f53ff BH |
4861 | err = ixgbe_set_num_queues(adapter); |
4862 | if (err) | |
4863 | return err; | |
021230d4 | 4864 | |
021230d4 AV |
4865 | err = pci_enable_msi(adapter->pdev); |
4866 | if (!err) { | |
4867 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
4868 | } else { | |
849c4542 ET |
4869 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4870 | "Unable to allocate MSI interrupt, " | |
4871 | "falling back to legacy. Error: %d\n", err); | |
021230d4 AV |
4872 | /* reset err */ |
4873 | err = 0; | |
4874 | } | |
4875 | ||
4876 | out: | |
021230d4 AV |
4877 | return err; |
4878 | } | |
4879 | ||
de88eeeb AD |
4880 | static void ixgbe_add_ring(struct ixgbe_ring *ring, |
4881 | struct ixgbe_ring_container *head) | |
4882 | { | |
4883 | ring->next = head->ring; | |
4884 | head->ring = ring; | |
4885 | head->count++; | |
4886 | } | |
4887 | ||
4888 | /** | |
4889 | * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector | |
4890 | * @adapter: board private structure to initialize | |
4891 | * @v_idx: index of vector in adapter struct | |
4892 | * | |
4893 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
4894 | **/ | |
4895 | static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, int v_idx, | |
4896 | int txr_count, int txr_idx, | |
4897 | int rxr_count, int rxr_idx) | |
4898 | { | |
4899 | struct ixgbe_q_vector *q_vector; | |
4900 | struct ixgbe_ring *ring; | |
4901 | int node = -1; | |
4902 | int cpu = -1; | |
4903 | int ring_count, size; | |
4904 | ||
4905 | ring_count = txr_count + rxr_count; | |
4906 | size = sizeof(struct ixgbe_q_vector) + | |
4907 | (sizeof(struct ixgbe_ring) * ring_count); | |
4908 | ||
4909 | /* customize cpu for Flow Director mapping */ | |
4910 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
4911 | if (cpu_online(v_idx)) { | |
4912 | cpu = v_idx; | |
4913 | node = cpu_to_node(cpu); | |
4914 | } | |
4915 | } | |
4916 | ||
4917 | /* allocate q_vector and rings */ | |
4918 | q_vector = kzalloc_node(size, GFP_KERNEL, node); | |
4919 | if (!q_vector) | |
4920 | q_vector = kzalloc(size, GFP_KERNEL); | |
4921 | if (!q_vector) | |
4922 | return -ENOMEM; | |
4923 | ||
4924 | /* setup affinity mask and node */ | |
4925 | if (cpu != -1) | |
4926 | cpumask_set_cpu(cpu, &q_vector->affinity_mask); | |
4927 | else | |
4928 | cpumask_copy(&q_vector->affinity_mask, cpu_online_mask); | |
4929 | q_vector->numa_node = node; | |
4930 | ||
4931 | /* initialize NAPI */ | |
4932 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
4933 | ixgbe_poll, 64); | |
4934 | ||
4935 | /* tie q_vector and adapter together */ | |
4936 | adapter->q_vector[v_idx] = q_vector; | |
4937 | q_vector->adapter = adapter; | |
4938 | q_vector->v_idx = v_idx; | |
4939 | ||
4940 | /* initialize work limits */ | |
4941 | q_vector->tx.work_limit = adapter->tx_work_limit; | |
4942 | ||
4943 | /* initialize pointer to rings */ | |
4944 | ring = q_vector->ring; | |
4945 | ||
4946 | while (txr_count) { | |
4947 | /* assign generic ring traits */ | |
4948 | ring->dev = &adapter->pdev->dev; | |
4949 | ring->netdev = adapter->netdev; | |
4950 | ||
4951 | /* configure backlink on ring */ | |
4952 | ring->q_vector = q_vector; | |
4953 | ||
4954 | /* update q_vector Tx values */ | |
4955 | ixgbe_add_ring(ring, &q_vector->tx); | |
4956 | ||
4957 | /* apply Tx specific ring traits */ | |
4958 | ring->count = adapter->tx_ring_count; | |
4959 | ring->queue_index = txr_idx; | |
4960 | ||
4961 | /* assign ring to adapter */ | |
4962 | adapter->tx_ring[txr_idx] = ring; | |
4963 | ||
4964 | /* update count and index */ | |
4965 | txr_count--; | |
4966 | txr_idx++; | |
4967 | ||
4968 | /* push pointer to next ring */ | |
4969 | ring++; | |
4970 | } | |
4971 | ||
4972 | while (rxr_count) { | |
4973 | /* assign generic ring traits */ | |
4974 | ring->dev = &adapter->pdev->dev; | |
4975 | ring->netdev = adapter->netdev; | |
4976 | ||
4977 | /* configure backlink on ring */ | |
4978 | ring->q_vector = q_vector; | |
4979 | ||
4980 | /* update q_vector Rx values */ | |
4981 | ixgbe_add_ring(ring, &q_vector->rx); | |
4982 | ||
4983 | /* | |
4984 | * 82599 errata, UDP frames with a 0 checksum | |
4985 | * can be marked as checksum errors. | |
4986 | */ | |
4987 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
4988 | set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); | |
4989 | ||
4990 | /* apply Rx specific ring traits */ | |
4991 | ring->count = adapter->rx_ring_count; | |
4992 | ring->queue_index = rxr_idx; | |
4993 | ||
4994 | /* assign ring to adapter */ | |
4995 | adapter->rx_ring[rxr_idx] = ring; | |
4996 | ||
4997 | /* update count and index */ | |
4998 | rxr_count--; | |
4999 | rxr_idx++; | |
5000 | ||
5001 | /* push pointer to next ring */ | |
5002 | ring++; | |
5003 | } | |
5004 | ||
5005 | return 0; | |
5006 | } | |
5007 | ||
5008 | /** | |
5009 | * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector | |
5010 | * @adapter: board private structure to initialize | |
5011 | * @v_idx: Index of vector to be freed | |
5012 | * | |
5013 | * This function frees the memory allocated to the q_vector. In addition if | |
5014 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
5015 | * to freeing the q_vector. | |
5016 | **/ | |
5017 | static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx) | |
5018 | { | |
5019 | struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; | |
5020 | struct ixgbe_ring *ring; | |
5021 | ||
a557928e | 5022 | ixgbe_for_each_ring(ring, q_vector->tx) |
de88eeeb AD |
5023 | adapter->tx_ring[ring->queue_index] = NULL; |
5024 | ||
a557928e | 5025 | ixgbe_for_each_ring(ring, q_vector->rx) |
de88eeeb AD |
5026 | adapter->rx_ring[ring->queue_index] = NULL; |
5027 | ||
5028 | adapter->q_vector[v_idx] = NULL; | |
5029 | netif_napi_del(&q_vector->napi); | |
5030 | ||
5031 | /* | |
5032 | * ixgbe_get_stats64() might access the rings on this vector, | |
5033 | * we must wait a grace period before freeing it. | |
5034 | */ | |
5035 | kfree_rcu(q_vector, rcu); | |
5036 | } | |
5037 | ||
7a921c93 AD |
5038 | /** |
5039 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
5040 | * @adapter: board private structure to initialize | |
5041 | * | |
5042 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
5043 | * return -ENOMEM. | |
5044 | **/ | |
5045 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
5046 | { | |
de88eeeb AD |
5047 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
5048 | int rxr_remaining = adapter->num_rx_queues; | |
5049 | int txr_remaining = adapter->num_tx_queues; | |
5050 | int rxr_idx = 0, txr_idx = 0, v_idx = 0; | |
5051 | int err; | |
7a921c93 | 5052 | |
de88eeeb AD |
5053 | /* only one q_vector if MSI-X is disabled. */ |
5054 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
5055 | q_vectors = 1; | |
7a921c93 | 5056 | |
de88eeeb AD |
5057 | if (q_vectors >= (rxr_remaining + txr_remaining)) { |
5058 | for (; rxr_remaining; v_idx++, q_vectors--) { | |
5059 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors); | |
5060 | err = ixgbe_alloc_q_vector(adapter, v_idx, | |
5061 | 0, 0, rqpv, rxr_idx); | |
4ff7fb12 | 5062 | |
de88eeeb AD |
5063 | if (err) |
5064 | goto err_out; | |
5065 | ||
5066 | /* update counts and index */ | |
5067 | rxr_remaining -= rqpv; | |
5068 | rxr_idx += rqpv; | |
5069 | } | |
5070 | } | |
4ff7fb12 | 5071 | |
de88eeeb AD |
5072 | for (; q_vectors; v_idx++, q_vectors--) { |
5073 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors); | |
5074 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors); | |
5075 | err = ixgbe_alloc_q_vector(adapter, v_idx, | |
5076 | tqpv, txr_idx, | |
5077 | rqpv, rxr_idx); | |
5078 | ||
5079 | if (err) | |
207867f5 | 5080 | goto err_out; |
de88eeeb AD |
5081 | |
5082 | /* update counts and index */ | |
5083 | rxr_remaining -= rqpv; | |
5084 | rxr_idx += rqpv; | |
5085 | txr_remaining -= tqpv; | |
5086 | txr_idx += tqpv; | |
7a921c93 AD |
5087 | } |
5088 | ||
5089 | return 0; | |
5090 | ||
5091 | err_out: | |
4ff7fb12 AD |
5092 | while (v_idx) { |
5093 | v_idx--; | |
de88eeeb | 5094 | ixgbe_free_q_vector(adapter, v_idx); |
7a921c93 | 5095 | } |
de88eeeb | 5096 | |
7a921c93 AD |
5097 | return -ENOMEM; |
5098 | } | |
5099 | ||
5100 | /** | |
5101 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
5102 | * @adapter: board private structure to initialize | |
5103 | * | |
5104 | * This function frees the memory allocated to the q_vectors. In addition if | |
5105 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
5106 | * to freeing the q_vector. | |
5107 | **/ | |
5108 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
5109 | { | |
de88eeeb | 5110 | int v_idx, q_vectors; |
7a921c93 | 5111 | |
91281fd3 | 5112 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
de88eeeb | 5113 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 5114 | else |
de88eeeb | 5115 | q_vectors = 1; |
7a921c93 | 5116 | |
de88eeeb AD |
5117 | for (v_idx = 0; v_idx < q_vectors; v_idx++) |
5118 | ixgbe_free_q_vector(adapter, v_idx); | |
7a921c93 AD |
5119 | } |
5120 | ||
7b25cdba | 5121 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
5122 | { |
5123 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
5124 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
5125 | pci_disable_msix(adapter->pdev); | |
5126 | kfree(adapter->msix_entries); | |
5127 | adapter->msix_entries = NULL; | |
5128 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
5129 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
5130 | pci_disable_msi(adapter->pdev); | |
5131 | } | |
021230d4 AV |
5132 | } |
5133 | ||
5134 | /** | |
5135 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
5136 | * @adapter: board private structure to initialize | |
5137 | * | |
5138 | * We determine which interrupt scheme to use based on... | |
5139 | * - Kernel support (MSI, MSI-X) | |
5140 | * - which can be user-defined (via MODULE_PARAM) | |
5141 | * - Hardware queue count (num_*_queues) | |
5142 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
5143 | **/ | |
2f90b865 | 5144 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
5145 | { |
5146 | int err; | |
5147 | ||
5148 | /* Number of supported queues */ | |
847f53ff BH |
5149 | err = ixgbe_set_num_queues(adapter); |
5150 | if (err) | |
5151 | return err; | |
021230d4 | 5152 | |
021230d4 AV |
5153 | err = ixgbe_set_interrupt_capability(adapter); |
5154 | if (err) { | |
849c4542 | 5155 | e_dev_err("Unable to setup interrupt capabilities\n"); |
021230d4 | 5156 | goto err_set_interrupt; |
9a799d71 AK |
5157 | } |
5158 | ||
7a921c93 AD |
5159 | err = ixgbe_alloc_q_vectors(adapter); |
5160 | if (err) { | |
849c4542 | 5161 | e_dev_err("Unable to allocate memory for queue vectors\n"); |
7a921c93 AD |
5162 | goto err_alloc_q_vectors; |
5163 | } | |
5164 | ||
de88eeeb | 5165 | ixgbe_cache_ring_register(adapter); |
7a921c93 | 5166 | |
849c4542 | 5167 | e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", |
396e799c ET |
5168 | (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", |
5169 | adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
5170 | |
5171 | set_bit(__IXGBE_DOWN, &adapter->state); | |
5172 | ||
9a799d71 | 5173 | return 0; |
021230d4 | 5174 | |
7a921c93 AD |
5175 | err_alloc_q_vectors: |
5176 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 5177 | err_set_interrupt: |
7a921c93 AD |
5178 | return err; |
5179 | } | |
5180 | ||
5181 | /** | |
5182 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
5183 | * @adapter: board private structure to clear interrupt scheme on | |
5184 | * | |
5185 | * We go through and clear interrupt specific resources and reset the structure | |
5186 | * to pre-load conditions | |
5187 | **/ | |
5188 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
5189 | { | |
b8eb3a10 DS |
5190 | adapter->num_tx_queues = 0; |
5191 | adapter->num_rx_queues = 0; | |
5192 | ||
7a921c93 AD |
5193 | ixgbe_free_q_vectors(adapter); |
5194 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
5195 | } |
5196 | ||
5197 | /** | |
5198 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
5199 | * @adapter: board private structure to initialize | |
5200 | * | |
5201 | * ixgbe_sw_init initializes the Adapter private data structure. | |
5202 | * Fields are initialized based on PCI device information and | |
5203 | * OS network device settings (MTU size). | |
5204 | **/ | |
5205 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
5206 | { | |
5207 | struct ixgbe_hw *hw = &adapter->hw; | |
5208 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 5209 | unsigned int rss; |
7a6b6f51 | 5210 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5211 | int j; |
5212 | struct tc_configuration *tc; | |
5213 | #endif | |
021230d4 | 5214 | |
c44ade9e JB |
5215 | /* PCI config space info */ |
5216 | ||
5217 | hw->vendor_id = pdev->vendor; | |
5218 | hw->device_id = pdev->device; | |
5219 | hw->revision_id = pdev->revision; | |
5220 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
5221 | hw->subsystem_device_id = pdev->subsystem_device; | |
5222 | ||
021230d4 | 5223 | /* Set capability flags */ |
3ed69d7e | 5224 | rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); |
021230d4 AV |
5225 | adapter->ring_feature[RING_F_RSS].indices = rss; |
5226 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
bd508178 AD |
5227 | switch (hw->mac.type) { |
5228 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
5229 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
5230 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 5231 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bd508178 | 5232 | break; |
b93a2226 | 5233 | case ixgbe_mac_X540: |
4f51bf70 JK |
5234 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; |
5235 | case ixgbe_mac_82599EB: | |
e8e26350 | 5236 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
5237 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
5238 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
5239 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
5240 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
5241 | /* Flow Director hash filters enabled */ |
5242 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
5243 | adapter->atr_sample_rate = 20; | |
c4cf55e5 | 5244 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 5245 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 5246 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 5247 | #ifdef IXGBE_FCOE |
0d551589 YZ |
5248 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
5249 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5250 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 5251 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 5252 | /* Default traffic class to use for FCoE */ |
56075a98 | 5253 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 5254 | #endif |
eacd73f7 | 5255 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5256 | break; |
5257 | default: | |
5258 | break; | |
f8212f97 | 5259 | } |
2f90b865 | 5260 | |
1fc5f038 AD |
5261 | /* n-tuple support exists, always init our spinlock */ |
5262 | spin_lock_init(&adapter->fdir_perfect_lock); | |
5263 | ||
7a6b6f51 | 5264 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
5265 | switch (hw->mac.type) { |
5266 | case ixgbe_mac_X540: | |
5267 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
5268 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
5269 | break; | |
5270 | default: | |
5271 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
5272 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
5273 | break; | |
5274 | } | |
5275 | ||
2f90b865 AD |
5276 | /* Configure DCB traffic classes */ |
5277 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
5278 | tc = &adapter->dcb_cfg.tc_config[j]; | |
5279 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
5280 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
5281 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
5282 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
5283 | tc->dcb_pfc = pfc_disabled; | |
5284 | } | |
4de2a022 JF |
5285 | |
5286 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
5287 | tc = &adapter->dcb_cfg.tc_config[0]; | |
5288 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5289 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5290 | ||
2f90b865 AD |
5291 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
5292 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 5293 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 5294 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 5295 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
2f90b865 | 5296 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, |
e5b64635 | 5297 | MAX_TRAFFIC_CLASS); |
2f90b865 AD |
5298 | |
5299 | #endif | |
9a799d71 AK |
5300 | |
5301 | /* default flow control settings */ | |
cd7664f6 | 5302 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 5303 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
5304 | #ifdef CONFIG_DCB |
5305 | adapter->last_lfc_mode = hw->fc.current_mode; | |
5306 | #endif | |
9da712d2 | 5307 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
5308 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
5309 | hw->fc.send_xon = true; | |
71fd570b | 5310 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 5311 | |
30efa5a3 | 5312 | /* enable itr by default in dynamic mode */ |
f7554a2b | 5313 | adapter->rx_itr_setting = 1; |
f7554a2b | 5314 | adapter->tx_itr_setting = 1; |
30efa5a3 | 5315 | |
30efa5a3 JB |
5316 | /* set default ring sizes */ |
5317 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
5318 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
5319 | ||
bd198058 | 5320 | /* set default work limits */ |
59224555 | 5321 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 5322 | |
9a799d71 | 5323 | /* initialize eeprom parameters */ |
c44ade9e | 5324 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 5325 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
5326 | return -EIO; |
5327 | } | |
5328 | ||
9a799d71 AK |
5329 | set_bit(__IXGBE_DOWN, &adapter->state); |
5330 | ||
5331 | return 0; | |
5332 | } | |
5333 | ||
5334 | /** | |
5335 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 5336 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5337 | * |
5338 | * Return 0 on success, negative on failure | |
5339 | **/ | |
b6ec895e | 5340 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5341 | { |
b6ec895e | 5342 | struct device *dev = tx_ring->dev; |
de88eeeb AD |
5343 | int orig_node = dev_to_node(dev); |
5344 | int numa_node = -1; | |
9a799d71 AK |
5345 | int size; |
5346 | ||
3a581073 | 5347 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
5348 | |
5349 | if (tx_ring->q_vector) | |
5350 | numa_node = tx_ring->q_vector->numa_node; | |
5351 | ||
5352 | tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 5353 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 5354 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
5355 | if (!tx_ring->tx_buffer_info) |
5356 | goto err; | |
9a799d71 AK |
5357 | |
5358 | /* round up to nearest 4K */ | |
12207e49 | 5359 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 5360 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 5361 | |
de88eeeb AD |
5362 | set_dev_node(dev, numa_node); |
5363 | tx_ring->desc = dma_alloc_coherent(dev, | |
5364 | tx_ring->size, | |
5365 | &tx_ring->dma, | |
5366 | GFP_KERNEL); | |
5367 | set_dev_node(dev, orig_node); | |
5368 | if (!tx_ring->desc) | |
5369 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
5370 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
5371 | if (!tx_ring->desc) |
5372 | goto err; | |
9a799d71 | 5373 | |
3a581073 JB |
5374 | tx_ring->next_to_use = 0; |
5375 | tx_ring->next_to_clean = 0; | |
9a799d71 | 5376 | return 0; |
e01c31a5 JB |
5377 | |
5378 | err: | |
5379 | vfree(tx_ring->tx_buffer_info); | |
5380 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 5381 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 5382 | return -ENOMEM; |
9a799d71 AK |
5383 | } |
5384 | ||
69888674 AD |
5385 | /** |
5386 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
5387 | * @adapter: board private structure | |
5388 | * | |
5389 | * If this function returns with an error, then it's possible one or | |
5390 | * more of the rings is populated (while the rest are not). It is the | |
5391 | * callers duty to clean those orphaned rings. | |
5392 | * | |
5393 | * Return 0 on success, negative on failure | |
5394 | **/ | |
5395 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
5396 | { | |
5397 | int i, err = 0; | |
5398 | ||
5399 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 5400 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
5401 | if (!err) |
5402 | continue; | |
396e799c | 5403 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
5404 | break; |
5405 | } | |
5406 | ||
5407 | return err; | |
5408 | } | |
5409 | ||
9a799d71 AK |
5410 | /** |
5411 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 5412 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5413 | * |
5414 | * Returns 0 on success, negative on failure | |
5415 | **/ | |
b6ec895e | 5416 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5417 | { |
b6ec895e | 5418 | struct device *dev = rx_ring->dev; |
de88eeeb AD |
5419 | int orig_node = dev_to_node(dev); |
5420 | int numa_node = -1; | |
021230d4 | 5421 | int size; |
9a799d71 | 5422 | |
3a581073 | 5423 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
5424 | |
5425 | if (rx_ring->q_vector) | |
5426 | numa_node = rx_ring->q_vector->numa_node; | |
5427 | ||
5428 | rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 5429 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 5430 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
5431 | if (!rx_ring->rx_buffer_info) |
5432 | goto err; | |
9a799d71 | 5433 | |
9a799d71 | 5434 | /* Round up to nearest 4K */ |
3a581073 JB |
5435 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5436 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5437 | |
de88eeeb AD |
5438 | set_dev_node(dev, numa_node); |
5439 | rx_ring->desc = dma_alloc_coherent(dev, | |
5440 | rx_ring->size, | |
5441 | &rx_ring->dma, | |
5442 | GFP_KERNEL); | |
5443 | set_dev_node(dev, orig_node); | |
5444 | if (!rx_ring->desc) | |
5445 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
5446 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
5447 | if (!rx_ring->desc) |
5448 | goto err; | |
9a799d71 | 5449 | |
3a581073 JB |
5450 | rx_ring->next_to_clean = 0; |
5451 | rx_ring->next_to_use = 0; | |
9a799d71 | 5452 | |
f800326d AD |
5453 | ixgbe_init_rx_page_offset(rx_ring); |
5454 | ||
9a799d71 | 5455 | return 0; |
b6ec895e AD |
5456 | err: |
5457 | vfree(rx_ring->rx_buffer_info); | |
5458 | rx_ring->rx_buffer_info = NULL; | |
5459 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 5460 | return -ENOMEM; |
9a799d71 AK |
5461 | } |
5462 | ||
69888674 AD |
5463 | /** |
5464 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5465 | * @adapter: board private structure | |
5466 | * | |
5467 | * If this function returns with an error, then it's possible one or | |
5468 | * more of the rings is populated (while the rest are not). It is the | |
5469 | * callers duty to clean those orphaned rings. | |
5470 | * | |
5471 | * Return 0 on success, negative on failure | |
5472 | **/ | |
69888674 AD |
5473 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
5474 | { | |
5475 | int i, err = 0; | |
5476 | ||
5477 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 5478 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
5479 | if (!err) |
5480 | continue; | |
396e799c | 5481 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
5482 | break; |
5483 | } | |
5484 | ||
5485 | return err; | |
5486 | } | |
5487 | ||
9a799d71 AK |
5488 | /** |
5489 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
5490 | * @tx_ring: Tx descriptor ring for a specific queue |
5491 | * | |
5492 | * Free all transmit software resources | |
5493 | **/ | |
b6ec895e | 5494 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5495 | { |
b6ec895e | 5496 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
5497 | |
5498 | vfree(tx_ring->tx_buffer_info); | |
5499 | tx_ring->tx_buffer_info = NULL; | |
5500 | ||
b6ec895e AD |
5501 | /* if not set, then don't free */ |
5502 | if (!tx_ring->desc) | |
5503 | return; | |
5504 | ||
5505 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
5506 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
5507 | |
5508 | tx_ring->desc = NULL; | |
5509 | } | |
5510 | ||
5511 | /** | |
5512 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
5513 | * @adapter: board private structure | |
5514 | * | |
5515 | * Free all transmit software resources | |
5516 | **/ | |
5517 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
5518 | { | |
5519 | int i; | |
5520 | ||
5521 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5522 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 5523 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
5524 | } |
5525 | ||
5526 | /** | |
b4617240 | 5527 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
5528 | * @rx_ring: ring to clean the resources from |
5529 | * | |
5530 | * Free all receive software resources | |
5531 | **/ | |
b6ec895e | 5532 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5533 | { |
b6ec895e | 5534 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
5535 | |
5536 | vfree(rx_ring->rx_buffer_info); | |
5537 | rx_ring->rx_buffer_info = NULL; | |
5538 | ||
b6ec895e AD |
5539 | /* if not set, then don't free */ |
5540 | if (!rx_ring->desc) | |
5541 | return; | |
5542 | ||
5543 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
5544 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
5545 | |
5546 | rx_ring->desc = NULL; | |
5547 | } | |
5548 | ||
5549 | /** | |
5550 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5551 | * @adapter: board private structure | |
5552 | * | |
5553 | * Free all receive software resources | |
5554 | **/ | |
5555 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5556 | { | |
5557 | int i; | |
5558 | ||
5559 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 5560 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 5561 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
5562 | } |
5563 | ||
9a799d71 AK |
5564 | /** |
5565 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5566 | * @netdev: network interface device structure | |
5567 | * @new_mtu: new value for maximum frame size | |
5568 | * | |
5569 | * Returns 0 on success, negative on failure | |
5570 | **/ | |
5571 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5572 | { | |
5573 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5574 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
5575 | ||
42c783c5 | 5576 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
5577 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
5578 | return -EINVAL; | |
5579 | ||
5580 | /* | |
5581 | * For 82599EB we cannot allow PF to change MTU greater than 1500 | |
5582 | * in SR-IOV mode as it may cause buffer overruns in guest VFs that | |
5583 | * don't allocate and chain buffers correctly. | |
5584 | */ | |
5585 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
5586 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
5587 | (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
e9f98072 | 5588 | return -EINVAL; |
9a799d71 | 5589 | |
396e799c | 5590 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 5591 | |
021230d4 | 5592 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5593 | netdev->mtu = new_mtu; |
5594 | ||
d4f80882 AV |
5595 | if (netif_running(netdev)) |
5596 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5597 | |
5598 | return 0; | |
5599 | } | |
5600 | ||
5601 | /** | |
5602 | * ixgbe_open - Called when a network interface is made active | |
5603 | * @netdev: network interface device structure | |
5604 | * | |
5605 | * Returns 0 on success, negative value on failure | |
5606 | * | |
5607 | * The open entry point is called when a network interface is made | |
5608 | * active by the system (IFF_UP). At this point all resources needed | |
5609 | * for transmit and receive operations are allocated, the interrupt | |
5610 | * handler is registered with the OS, the watchdog timer is started, | |
5611 | * and the stack is notified that the interface is ready. | |
5612 | **/ | |
5613 | static int ixgbe_open(struct net_device *netdev) | |
5614 | { | |
5615 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5616 | int err; | |
4bebfaa5 AK |
5617 | |
5618 | /* disallow open during test */ | |
5619 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
5620 | return -EBUSY; | |
9a799d71 | 5621 | |
54386467 JB |
5622 | netif_carrier_off(netdev); |
5623 | ||
9a799d71 AK |
5624 | /* allocate transmit descriptors */ |
5625 | err = ixgbe_setup_all_tx_resources(adapter); | |
5626 | if (err) | |
5627 | goto err_setup_tx; | |
5628 | ||
9a799d71 AK |
5629 | /* allocate receive descriptors */ |
5630 | err = ixgbe_setup_all_rx_resources(adapter); | |
5631 | if (err) | |
5632 | goto err_setup_rx; | |
5633 | ||
5634 | ixgbe_configure(adapter); | |
5635 | ||
021230d4 | 5636 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
5637 | if (err) |
5638 | goto err_req_irq; | |
5639 | ||
c7ccde0f | 5640 | ixgbe_up_complete(adapter); |
9a799d71 AK |
5641 | |
5642 | return 0; | |
5643 | ||
9a799d71 | 5644 | err_req_irq: |
9a799d71 | 5645 | err_setup_rx: |
a20a1199 | 5646 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 5647 | err_setup_tx: |
a20a1199 | 5648 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
5649 | ixgbe_reset(adapter); |
5650 | ||
5651 | return err; | |
5652 | } | |
5653 | ||
5654 | /** | |
5655 | * ixgbe_close - Disables a network interface | |
5656 | * @netdev: network interface device structure | |
5657 | * | |
5658 | * Returns 0, this is not allowed to fail | |
5659 | * | |
5660 | * The close entry point is called when an interface is de-activated | |
5661 | * by the OS. The hardware is still under the drivers control, but | |
5662 | * needs to be disabled. A global MAC reset is issued to stop the | |
5663 | * hardware, and all transmit and receive resources are freed. | |
5664 | **/ | |
5665 | static int ixgbe_close(struct net_device *netdev) | |
5666 | { | |
5667 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
5668 | |
5669 | ixgbe_down(adapter); | |
5670 | ixgbe_free_irq(adapter); | |
5671 | ||
e4911d57 AD |
5672 | ixgbe_fdir_filter_exit(adapter); |
5673 | ||
9a799d71 AK |
5674 | ixgbe_free_all_tx_resources(adapter); |
5675 | ixgbe_free_all_rx_resources(adapter); | |
5676 | ||
5eba3699 | 5677 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5678 | |
5679 | return 0; | |
5680 | } | |
5681 | ||
b3c8b4ba AD |
5682 | #ifdef CONFIG_PM |
5683 | static int ixgbe_resume(struct pci_dev *pdev) | |
5684 | { | |
c60fbb00 AD |
5685 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5686 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
5687 | u32 err; |
5688 | ||
5689 | pci_set_power_state(pdev, PCI_D0); | |
5690 | pci_restore_state(pdev); | |
656ab817 DS |
5691 | /* |
5692 | * pci_restore_state clears dev->state_saved so call | |
5693 | * pci_save_state to restore it. | |
5694 | */ | |
5695 | pci_save_state(pdev); | |
9ce77666 | 5696 | |
5697 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 5698 | if (err) { |
849c4542 | 5699 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
5700 | return err; |
5701 | } | |
5702 | pci_set_master(pdev); | |
5703 | ||
dd4d8ca6 | 5704 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
5705 | |
5706 | err = ixgbe_init_interrupt_scheme(adapter); | |
5707 | if (err) { | |
849c4542 | 5708 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
5709 | return err; |
5710 | } | |
5711 | ||
b3c8b4ba AD |
5712 | ixgbe_reset(adapter); |
5713 | ||
495dce12 WJP |
5714 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5715 | ||
b3c8b4ba | 5716 | if (netif_running(netdev)) { |
c60fbb00 | 5717 | err = ixgbe_open(netdev); |
b3c8b4ba AD |
5718 | if (err) |
5719 | return err; | |
5720 | } | |
5721 | ||
5722 | netif_device_attach(netdev); | |
5723 | ||
5724 | return 0; | |
5725 | } | |
b3c8b4ba | 5726 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5727 | |
5728 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 5729 | { |
c60fbb00 AD |
5730 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5731 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
5732 | struct ixgbe_hw *hw = &adapter->hw; |
5733 | u32 ctrl, fctrl; | |
5734 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5735 | #ifdef CONFIG_PM |
5736 | int retval = 0; | |
5737 | #endif | |
5738 | ||
5739 | netif_device_detach(netdev); | |
5740 | ||
5741 | if (netif_running(netdev)) { | |
5742 | ixgbe_down(adapter); | |
5743 | ixgbe_free_irq(adapter); | |
5744 | ixgbe_free_all_tx_resources(adapter); | |
5745 | ixgbe_free_all_rx_resources(adapter); | |
5746 | } | |
b3c8b4ba | 5747 | |
5f5ae6fc | 5748 | ixgbe_clear_interrupt_scheme(adapter); |
d033d526 JF |
5749 | #ifdef CONFIG_DCB |
5750 | kfree(adapter->ixgbe_ieee_pfc); | |
5751 | kfree(adapter->ixgbe_ieee_ets); | |
5752 | #endif | |
5f5ae6fc | 5753 | |
b3c8b4ba AD |
5754 | #ifdef CONFIG_PM |
5755 | retval = pci_save_state(pdev); | |
5756 | if (retval) | |
5757 | return retval; | |
4df10466 | 5758 | |
b3c8b4ba | 5759 | #endif |
e8e26350 PW |
5760 | if (wufc) { |
5761 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5762 | |
e8e26350 PW |
5763 | /* turn on all-multi mode if wake on multicast is enabled */ |
5764 | if (wufc & IXGBE_WUFC_MC) { | |
5765 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5766 | fctrl |= IXGBE_FCTRL_MPE; | |
5767 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5768 | } | |
5769 | ||
5770 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5771 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5772 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5773 | ||
5774 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5775 | } else { | |
5776 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5777 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5778 | } | |
5779 | ||
bd508178 AD |
5780 | switch (hw->mac.type) { |
5781 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 5782 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
5783 | break; |
5784 | case ixgbe_mac_82599EB: | |
b93a2226 | 5785 | case ixgbe_mac_X540: |
bd508178 AD |
5786 | pci_wake_from_d3(pdev, !!wufc); |
5787 | break; | |
5788 | default: | |
5789 | break; | |
5790 | } | |
b3c8b4ba | 5791 | |
9d8d05ae RW |
5792 | *enable_wake = !!wufc; |
5793 | ||
b3c8b4ba AD |
5794 | ixgbe_release_hw_control(adapter); |
5795 | ||
5796 | pci_disable_device(pdev); | |
5797 | ||
9d8d05ae RW |
5798 | return 0; |
5799 | } | |
5800 | ||
5801 | #ifdef CONFIG_PM | |
5802 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5803 | { | |
5804 | int retval; | |
5805 | bool wake; | |
5806 | ||
5807 | retval = __ixgbe_shutdown(pdev, &wake); | |
5808 | if (retval) | |
5809 | return retval; | |
5810 | ||
5811 | if (wake) { | |
5812 | pci_prepare_to_sleep(pdev); | |
5813 | } else { | |
5814 | pci_wake_from_d3(pdev, false); | |
5815 | pci_set_power_state(pdev, PCI_D3hot); | |
5816 | } | |
b3c8b4ba AD |
5817 | |
5818 | return 0; | |
5819 | } | |
9d8d05ae | 5820 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5821 | |
5822 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5823 | { | |
9d8d05ae RW |
5824 | bool wake; |
5825 | ||
5826 | __ixgbe_shutdown(pdev, &wake); | |
5827 | ||
5828 | if (system_state == SYSTEM_POWER_OFF) { | |
5829 | pci_wake_from_d3(pdev, wake); | |
5830 | pci_set_power_state(pdev, PCI_D3hot); | |
5831 | } | |
b3c8b4ba AD |
5832 | } |
5833 | ||
9a799d71 AK |
5834 | /** |
5835 | * ixgbe_update_stats - Update the board statistics counters. | |
5836 | * @adapter: board private structure | |
5837 | **/ | |
5838 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5839 | { | |
2d86f139 | 5840 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5841 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5842 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5843 | u64 total_mpc = 0; |
5844 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5845 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5846 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 5847 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
7b859ebc AH |
5848 | #ifdef IXGBE_FCOE |
5849 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
5850 | unsigned int cpu; | |
5851 | u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0; | |
5852 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 5853 | |
d08935c2 DS |
5854 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5855 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5856 | return; | |
5857 | ||
94b982b2 | 5858 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5859 | u64 rsc_count = 0; |
94b982b2 | 5860 | u64 rsc_flush = 0; |
d51019a4 PW |
5861 | for (i = 0; i < 16; i++) |
5862 | adapter->hw_rx_no_dma_resources += | |
7ca647bd | 5863 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); |
94b982b2 | 5864 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5865 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5866 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5867 | } |
5868 | adapter->rsc_total_count = rsc_count; | |
5869 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5870 | } |
5871 | ||
5b7da515 AD |
5872 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5873 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5874 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5875 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5876 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 5877 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
5878 | bytes += rx_ring->stats.bytes; |
5879 | packets += rx_ring->stats.packets; | |
5880 | } | |
5881 | adapter->non_eop_descs = non_eop_descs; | |
5882 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5883 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 5884 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
5885 | netdev->stats.rx_bytes = bytes; |
5886 | netdev->stats.rx_packets = packets; | |
5887 | ||
5888 | bytes = 0; | |
5889 | packets = 0; | |
7ca3bc58 | 5890 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5891 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5892 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5893 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5894 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5895 | bytes += tx_ring->stats.bytes; | |
5896 | packets += tx_ring->stats.packets; | |
5897 | } | |
eb985f09 | 5898 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5899 | adapter->tx_busy = tx_busy; |
5900 | netdev->stats.tx_bytes = bytes; | |
5901 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5902 | |
7ca647bd | 5903 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5904 | |
5905 | /* 8 register reads */ | |
6f11eef7 AV |
5906 | for (i = 0; i < 8; i++) { |
5907 | /* for packet buffers not used, the register should read 0 */ | |
5908 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5909 | missed_rx += mpc; | |
7ca647bd JP |
5910 | hwstats->mpc[i] += mpc; |
5911 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5912 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5913 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5914 | switch (hw->mac.type) { |
5915 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5916 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5917 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5918 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5919 | hwstats->pxonrxc[i] += |
5920 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5921 | break; |
5922 | case ixgbe_mac_82599EB: | |
b93a2226 | 5923 | case ixgbe_mac_X540: |
bd508178 AD |
5924 | hwstats->pxonrxc[i] += |
5925 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5926 | break; |
5927 | default: | |
5928 | break; | |
e8e26350 | 5929 | } |
6f11eef7 | 5930 | } |
1a70db4b ET |
5931 | |
5932 | /*16 register reads */ | |
5933 | for (i = 0; i < 16; i++) { | |
5934 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5935 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5936 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5937 | (hw->mac.type == ixgbe_mac_X540)) { | |
5938 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5939 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5940 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5941 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5942 | } | |
5943 | } | |
5944 | ||
7ca647bd | 5945 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5946 | /* work around hardware counting issue */ |
7ca647bd | 5947 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5948 | |
c84d324c JF |
5949 | ixgbe_update_xoff_received(adapter); |
5950 | ||
6f11eef7 | 5951 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5952 | switch (hw->mac.type) { |
5953 | case ixgbe_mac_82598EB: | |
5954 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5955 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5956 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5957 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5958 | break; | |
b93a2226 | 5959 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5960 | /* OS2BMC stats are X540 only*/ |
5961 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5962 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5963 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5964 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5965 | case ixgbe_mac_82599EB: | |
7ca647bd | 5966 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5967 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5968 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5969 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5970 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5971 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5972 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5973 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5974 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5975 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5976 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5977 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5978 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5979 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5980 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5981 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc AH |
5982 | /* Add up per cpu counters for total ddp aloc fail */ |
5983 | if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) { | |
5984 | for_each_possible_cpu(cpu) { | |
5985 | fcoe_noddp_counts_sum += | |
5986 | *per_cpu_ptr(fcoe->pcpu_noddp, cpu); | |
5987 | fcoe_noddp_ext_buff_counts_sum += | |
5988 | *per_cpu_ptr(fcoe-> | |
5989 | pcpu_noddp_ext_buff, cpu); | |
5990 | } | |
5991 | } | |
5992 | hwstats->fcoe_noddp = fcoe_noddp_counts_sum; | |
5993 | hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum; | |
6d45522c | 5994 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5995 | break; |
5996 | default: | |
5997 | break; | |
e8e26350 | 5998 | } |
9a799d71 | 5999 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
6000 | hwstats->bprc += bprc; |
6001 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 6002 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
6003 | hwstats->mprc -= bprc; |
6004 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
6005 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
6006 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
6007 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
6008 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
6009 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
6010 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
6011 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 6012 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 6013 | hwstats->lxontxc += lxon; |
6f11eef7 | 6014 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 6015 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
6016 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
6017 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
6018 | /* |
6019 | * 82598 errata - tx of flow control packets is included in tx counters | |
6020 | */ | |
6021 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
6022 | hwstats->gptc -= xon_off_tot; |
6023 | hwstats->mptc -= xon_off_tot; | |
6024 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
6025 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
6026 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
6027 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
6028 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
6029 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6030 | hwstats->ptc64 -= xon_off_tot; | |
6031 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
6032 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
6033 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
6034 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
6035 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
6036 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
6037 | |
6038 | /* Fill out the OS statistics structure */ | |
7ca647bd | 6039 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
6040 | |
6041 | /* Rx Errors */ | |
7ca647bd | 6042 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 6043 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
6044 | netdev->stats.rx_length_errors = hwstats->rlec; |
6045 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 6046 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
6047 | } |
6048 | ||
6049 | /** | |
d034acf1 AD |
6050 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
6051 | * @adapter - pointer to the device adapter structure | |
9a799d71 | 6052 | **/ |
d034acf1 | 6053 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 6054 | { |
cf8280ee | 6055 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 6056 | int i; |
cf8280ee | 6057 | |
d034acf1 AD |
6058 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
6059 | return; | |
6060 | ||
6061 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 6062 | |
d034acf1 | 6063 | /* if interface is down do nothing */ |
fe49f04a | 6064 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
6065 | return; |
6066 | ||
6067 | /* do nothing if we are not using signature filters */ | |
6068 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
6069 | return; | |
6070 | ||
6071 | adapter->fdir_overflow++; | |
6072 | ||
93c52dd0 AD |
6073 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
6074 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6075 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 6076 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
6077 | /* re-enable flow director interrupts */ |
6078 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
6079 | } else { |
6080 | e_err(probe, "failed to finish FDIR re-initialization, " | |
6081 | "ignored adding FDIR ATR filters\n"); | |
6082 | } | |
93c52dd0 AD |
6083 | } |
6084 | ||
6085 | /** | |
6086 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
6087 | * @adapter - pointer to the device adapter structure | |
6088 | * | |
6089 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 6090 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 6091 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 6092 | * determine if a hang has occurred. |
93c52dd0 AD |
6093 | */ |
6094 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 6095 | { |
cf8280ee | 6096 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
6097 | u64 eics = 0; |
6098 | int i; | |
cf8280ee | 6099 | |
93c52dd0 AD |
6100 | /* If we're down or resetting, just bail */ |
6101 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
6102 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6103 | return; | |
22d5a71b | 6104 | |
93c52dd0 AD |
6105 | /* Force detection of hung controller */ |
6106 | if (netif_carrier_ok(adapter->netdev)) { | |
6107 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6108 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
6109 | } | |
22d5a71b | 6110 | |
fe49f04a AD |
6111 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
6112 | /* | |
6113 | * for legacy and MSI interrupts don't set any bits | |
6114 | * that are enabled for EIAM, because this operation | |
6115 | * would set *both* EIMS and EICS for any bit in EIAM | |
6116 | */ | |
6117 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
6118 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
6119 | } else { |
6120 | /* get one bit for every active tx/rx interrupt vector */ | |
6121 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
6122 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
efe3d3c8 | 6123 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
6124 | eics |= ((u64)1 << i); |
6125 | } | |
cf8280ee | 6126 | } |
9a799d71 | 6127 | |
93c52dd0 | 6128 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
6129 | ixgbe_irq_rearm_queues(adapter, eics); |
6130 | ||
cf8280ee JB |
6131 | } |
6132 | ||
e8e26350 | 6133 | /** |
93c52dd0 AD |
6134 | * ixgbe_watchdog_update_link - update the link status |
6135 | * @adapter - pointer to the device adapter structure | |
6136 | * @link_speed - pointer to a u32 to store the link_speed | |
e8e26350 | 6137 | **/ |
93c52dd0 | 6138 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 6139 | { |
e8e26350 | 6140 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
6141 | u32 link_speed = adapter->link_speed; |
6142 | bool link_up = adapter->link_up; | |
c4cf55e5 | 6143 | int i; |
e8e26350 | 6144 | |
93c52dd0 AD |
6145 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
6146 | return; | |
6147 | ||
6148 | if (hw->mac.ops.check_link) { | |
6149 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 6150 | } else { |
93c52dd0 AD |
6151 | /* always assume link is up, if no check link function */ |
6152 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
6153 | link_up = true; | |
c4cf55e5 | 6154 | } |
93c52dd0 AD |
6155 | if (link_up) { |
6156 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
6157 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
6158 | hw->mac.ops.fc_enable(hw, i); | |
6159 | } else { | |
6160 | hw->mac.ops.fc_enable(hw, 0); | |
6161 | } | |
6162 | } | |
6163 | ||
6164 | if (link_up || | |
6165 | time_after(jiffies, (adapter->link_check_timeout + | |
6166 | IXGBE_TRY_LINK_TIMEOUT))) { | |
6167 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
6168 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
6169 | IXGBE_WRITE_FLUSH(hw); | |
6170 | } | |
6171 | ||
6172 | adapter->link_up = link_up; | |
6173 | adapter->link_speed = link_speed; | |
e8e26350 PW |
6174 | } |
6175 | ||
6176 | /** | |
93c52dd0 AD |
6177 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
6178 | * print link up message | |
6179 | * @adapter - pointer to the device adapter structure | |
e8e26350 | 6180 | **/ |
93c52dd0 | 6181 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 6182 | { |
93c52dd0 | 6183 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 6184 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
6185 | u32 link_speed = adapter->link_speed; |
6186 | bool flow_rx, flow_tx; | |
e8e26350 | 6187 | |
93c52dd0 AD |
6188 | /* only continue if link was previously down */ |
6189 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 6190 | return; |
63d6e1d8 | 6191 | |
93c52dd0 | 6192 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 6193 | |
93c52dd0 AD |
6194 | switch (hw->mac.type) { |
6195 | case ixgbe_mac_82598EB: { | |
6196 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
6197 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
6198 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
6199 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
6200 | } | |
6201 | break; | |
6202 | case ixgbe_mac_X540: | |
6203 | case ixgbe_mac_82599EB: { | |
6204 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
6205 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
6206 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
6207 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
6208 | } | |
6209 | break; | |
6210 | default: | |
6211 | flow_tx = false; | |
6212 | flow_rx = false; | |
6213 | break; | |
e8e26350 | 6214 | } |
93c52dd0 AD |
6215 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
6216 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
6217 | "10 Gbps" : | |
6218 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
6219 | "1 Gbps" : | |
6220 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
6221 | "100 Mbps" : | |
6222 | "unknown speed"))), | |
6223 | ((flow_rx && flow_tx) ? "RX/TX" : | |
6224 | (flow_rx ? "RX" : | |
6225 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 6226 | |
93c52dd0 | 6227 | netif_carrier_on(netdev); |
93c52dd0 | 6228 | ixgbe_check_vf_rate_limit(adapter); |
e8e26350 PW |
6229 | } |
6230 | ||
c4cf55e5 | 6231 | /** |
93c52dd0 AD |
6232 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
6233 | * print link down message | |
6234 | * @adapter - pointer to the adapter structure | |
c4cf55e5 | 6235 | **/ |
581330ba | 6236 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 6237 | { |
cf8280ee | 6238 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 6239 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 6240 | |
93c52dd0 AD |
6241 | adapter->link_up = false; |
6242 | adapter->link_speed = 0; | |
cf8280ee | 6243 | |
93c52dd0 AD |
6244 | /* only continue if link was up previously */ |
6245 | if (!netif_carrier_ok(netdev)) | |
6246 | return; | |
264857b8 | 6247 | |
93c52dd0 AD |
6248 | /* poll for SFP+ cable when link is down */ |
6249 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
6250 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 6251 | |
93c52dd0 AD |
6252 | e_info(drv, "NIC Link is Down\n"); |
6253 | netif_carrier_off(netdev); | |
6254 | } | |
e8e26350 | 6255 | |
93c52dd0 AD |
6256 | /** |
6257 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
6258 | * @adapter - pointer to the device adapter structure | |
6259 | **/ | |
6260 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
6261 | { | |
c4cf55e5 | 6262 | int i; |
93c52dd0 | 6263 | int some_tx_pending = 0; |
c4cf55e5 | 6264 | |
93c52dd0 | 6265 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 6266 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 6267 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
6268 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
6269 | some_tx_pending = 1; | |
6270 | break; | |
6271 | } | |
6272 | } | |
6273 | ||
6274 | if (some_tx_pending) { | |
6275 | /* We've lost link, so the controller stops DMA, | |
6276 | * but we've got queued Tx work that's never going | |
6277 | * to get done, so reset controller to flush Tx. | |
6278 | * (Do the reset outside of interrupt context). | |
6279 | */ | |
c83c6cbd | 6280 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 6281 | } |
c4cf55e5 | 6282 | } |
c4cf55e5 PWJ |
6283 | } |
6284 | ||
a985b6c3 GR |
6285 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
6286 | { | |
6287 | u32 ssvpc; | |
6288 | ||
6289 | /* Do not perform spoof check for 82598 */ | |
6290 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
6291 | return; | |
6292 | ||
6293 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
6294 | ||
6295 | /* | |
6296 | * ssvpc register is cleared on read, if zero then no | |
6297 | * spoofed packets in the last interval. | |
6298 | */ | |
6299 | if (!ssvpc) | |
6300 | return; | |
6301 | ||
6302 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
6303 | } | |
6304 | ||
93c52dd0 AD |
6305 | /** |
6306 | * ixgbe_watchdog_subtask - check and bring link up | |
6307 | * @adapter - pointer to the device adapter structure | |
6308 | **/ | |
6309 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
6310 | { | |
6311 | /* if interface is down do nothing */ | |
7edebf9a ET |
6312 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
6313 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
93c52dd0 AD |
6314 | return; |
6315 | ||
6316 | ixgbe_watchdog_update_link(adapter); | |
6317 | ||
6318 | if (adapter->link_up) | |
6319 | ixgbe_watchdog_link_is_up(adapter); | |
6320 | else | |
6321 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 6322 | |
a985b6c3 | 6323 | ixgbe_spoof_check(adapter); |
9a799d71 | 6324 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
6325 | |
6326 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 6327 | } |
10eec955 | 6328 | |
cf8280ee | 6329 | /** |
7086400d AD |
6330 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
6331 | * @adapter - the ixgbe adapter structure | |
cf8280ee | 6332 | **/ |
7086400d | 6333 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 6334 | { |
cf8280ee | 6335 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 6336 | s32 err; |
cf8280ee | 6337 | |
7086400d AD |
6338 | /* not searching for SFP so there is nothing to do here */ |
6339 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
6340 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
6341 | return; | |
10eec955 | 6342 | |
7086400d AD |
6343 | /* someone else is in init, wait until next service event */ |
6344 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
6345 | return; | |
cf8280ee | 6346 | |
7086400d AD |
6347 | err = hw->phy.ops.identify_sfp(hw); |
6348 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
6349 | goto sfp_out; | |
264857b8 | 6350 | |
7086400d AD |
6351 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
6352 | /* If no cable is present, then we need to reset | |
6353 | * the next time we find a good cable. */ | |
6354 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 6355 | } |
9a799d71 | 6356 | |
7086400d AD |
6357 | /* exit on error */ |
6358 | if (err) | |
6359 | goto sfp_out; | |
e8e26350 | 6360 | |
7086400d AD |
6361 | /* exit if reset not needed */ |
6362 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
6363 | goto sfp_out; | |
9a799d71 | 6364 | |
7086400d | 6365 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 6366 | |
7086400d AD |
6367 | /* |
6368 | * A module may be identified correctly, but the EEPROM may not have | |
6369 | * support for that module. setup_sfp() will fail in that case, so | |
6370 | * we should not allow that module to load. | |
6371 | */ | |
6372 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6373 | err = hw->phy.ops.reset(hw); | |
6374 | else | |
6375 | err = hw->mac.ops.setup_sfp(hw); | |
6376 | ||
6377 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
6378 | goto sfp_out; | |
6379 | ||
6380 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
6381 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
6382 | ||
6383 | sfp_out: | |
6384 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
6385 | ||
6386 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
6387 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
6388 | e_dev_err("failed to initialize because an unsupported " | |
6389 | "SFP+ module type was detected.\n"); | |
6390 | e_dev_err("Reload the driver after installing a " | |
6391 | "supported module.\n"); | |
6392 | unregister_netdev(adapter->netdev); | |
bc59fcda | 6393 | } |
7086400d | 6394 | } |
bc59fcda | 6395 | |
7086400d AD |
6396 | /** |
6397 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
6398 | * @adapter - the ixgbe adapter structure | |
6399 | **/ | |
6400 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
6401 | { | |
6402 | struct ixgbe_hw *hw = &adapter->hw; | |
6403 | u32 autoneg; | |
6404 | bool negotiation; | |
6405 | ||
6406 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
6407 | return; | |
6408 | ||
6409 | /* someone else is in init, wait until next service event */ | |
6410 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
6411 | return; | |
6412 | ||
6413 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
6414 | ||
6415 | autoneg = hw->phy.autoneg_advertised; | |
6416 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
6417 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
7086400d AD |
6418 | if (hw->mac.ops.setup_link) |
6419 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
6420 | ||
6421 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
6422 | adapter->link_check_timeout = jiffies; | |
6423 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
6424 | } | |
6425 | ||
83c61fa9 GR |
6426 | #ifdef CONFIG_PCI_IOV |
6427 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
6428 | { | |
6429 | int vf; | |
6430 | struct ixgbe_hw *hw = &adapter->hw; | |
6431 | struct net_device *netdev = adapter->netdev; | |
6432 | u32 gpc; | |
6433 | u32 ciaa, ciad; | |
6434 | ||
6435 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
6436 | if (gpc) /* If incrementing then no need for the check below */ | |
6437 | return; | |
6438 | /* | |
6439 | * Check to see if a bad DMA write target from an errant or | |
6440 | * malicious VF has caused a PCIe error. If so then we can | |
6441 | * issue a VFLR to the offending VF(s) and then resume without | |
6442 | * requesting a full slot reset. | |
6443 | */ | |
6444 | ||
6445 | for (vf = 0; vf < adapter->num_vfs; vf++) { | |
6446 | ciaa = (vf << 16) | 0x80000000; | |
6447 | /* 32 bit read so align, we really want status at offset 6 */ | |
6448 | ciaa |= PCI_COMMAND; | |
6449 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
6450 | ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); | |
6451 | ciaa &= 0x7FFFFFFF; | |
6452 | /* disable debug mode asap after reading data */ | |
6453 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
6454 | /* Get the upper 16 bits which will be the PCI status reg */ | |
6455 | ciad >>= 16; | |
6456 | if (ciad & PCI_STATUS_REC_MASTER_ABORT) { | |
6457 | netdev_err(netdev, "VF %d Hung DMA\n", vf); | |
6458 | /* Issue VFLR */ | |
6459 | ciaa = (vf << 16) | 0x80000000; | |
6460 | ciaa |= 0xA8; | |
6461 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
6462 | ciad = 0x00008000; /* VFLR */ | |
6463 | IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); | |
6464 | ciaa &= 0x7FFFFFFF; | |
6465 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
6466 | } | |
6467 | } | |
6468 | } | |
6469 | ||
6470 | #endif | |
7086400d AD |
6471 | /** |
6472 | * ixgbe_service_timer - Timer Call-back | |
6473 | * @data: pointer to adapter cast into an unsigned long | |
6474 | **/ | |
6475 | static void ixgbe_service_timer(unsigned long data) | |
6476 | { | |
6477 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
6478 | unsigned long next_event_offset; | |
83c61fa9 | 6479 | bool ready = true; |
7086400d | 6480 | |
6bb78cfb AD |
6481 | /* poll faster when waiting for link */ |
6482 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
6483 | next_event_offset = HZ / 10; | |
6484 | else | |
6485 | next_event_offset = HZ * 2; | |
83c61fa9 | 6486 | |
6bb78cfb | 6487 | #ifdef CONFIG_PCI_IOV |
83c61fa9 GR |
6488 | /* |
6489 | * don't bother with SR-IOV VF DMA hang check if there are | |
6490 | * no VFs or the link is down | |
6491 | */ | |
6492 | if (!adapter->num_vfs || | |
6bb78cfb | 6493 | (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
83c61fa9 | 6494 | goto normal_timer_service; |
83c61fa9 GR |
6495 | |
6496 | /* If we have VFs allocated then we must check for DMA hangs */ | |
6497 | ixgbe_check_for_bad_vf(adapter); | |
6498 | next_event_offset = HZ / 50; | |
6499 | adapter->timer_event_accumulator++; | |
6500 | ||
6bb78cfb | 6501 | if (adapter->timer_event_accumulator >= 100) |
83c61fa9 | 6502 | adapter->timer_event_accumulator = 0; |
7086400d | 6503 | else |
6bb78cfb | 6504 | ready = false; |
7086400d | 6505 | |
6bb78cfb | 6506 | normal_timer_service: |
83c61fa9 | 6507 | #endif |
7086400d AD |
6508 | /* Reset the timer */ |
6509 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
6510 | ||
83c61fa9 GR |
6511 | if (ready) |
6512 | ixgbe_service_event_schedule(adapter); | |
7086400d AD |
6513 | } |
6514 | ||
c83c6cbd AD |
6515 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
6516 | { | |
6517 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
6518 | return; | |
6519 | ||
6520 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
6521 | ||
6522 | /* If we're already down or resetting, just bail */ | |
6523 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
6524 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6525 | return; | |
6526 | ||
6527 | ixgbe_dump(adapter); | |
6528 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
6529 | adapter->tx_timeout_count++; | |
6530 | ||
6531 | ixgbe_reinit_locked(adapter); | |
6532 | } | |
6533 | ||
7086400d AD |
6534 | /** |
6535 | * ixgbe_service_task - manages and runs subtasks | |
6536 | * @work: pointer to work_struct containing our data | |
6537 | **/ | |
6538 | static void ixgbe_service_task(struct work_struct *work) | |
6539 | { | |
6540 | struct ixgbe_adapter *adapter = container_of(work, | |
6541 | struct ixgbe_adapter, | |
6542 | service_task); | |
6543 | ||
c83c6cbd | 6544 | ixgbe_reset_subtask(adapter); |
7086400d AD |
6545 | ixgbe_sfp_detection_subtask(adapter); |
6546 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 6547 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 6548 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 6549 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 6550 | ixgbe_check_hang_subtask(adapter); |
7086400d AD |
6551 | |
6552 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
6553 | } |
6554 | ||
897ab156 AD |
6555 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens, |
6556 | u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) | |
9a799d71 AK |
6557 | { |
6558 | struct ixgbe_adv_tx_context_desc *context_desc; | |
897ab156 | 6559 | u16 i = tx_ring->next_to_use; |
9a799d71 | 6560 | |
e4f74028 | 6561 | context_desc = IXGBE_TX_CTXTDESC(tx_ring, i); |
9a799d71 | 6562 | |
897ab156 AD |
6563 | i++; |
6564 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
9a799d71 | 6565 | |
897ab156 AD |
6566 | /* set bits to identify this as an advanced context descriptor */ |
6567 | type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; | |
9a799d71 | 6568 | |
897ab156 AD |
6569 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); |
6570 | context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); | |
6571 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
6572 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
6573 | } | |
9a799d71 | 6574 | |
fd0db0ed AD |
6575 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
6576 | struct ixgbe_tx_buffer *first, | |
244e27ad | 6577 | u8 *hdr_len) |
897ab156 | 6578 | { |
fd0db0ed | 6579 | struct sk_buff *skb = first->skb; |
897ab156 AD |
6580 | u32 vlan_macip_lens, type_tucmd; |
6581 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 6582 | |
897ab156 AD |
6583 | if (!skb_is_gso(skb)) |
6584 | return 0; | |
9a799d71 | 6585 | |
897ab156 | 6586 | if (skb_header_cloned(skb)) { |
244e27ad | 6587 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
897ab156 AD |
6588 | if (err) |
6589 | return err; | |
9a799d71 | 6590 | } |
9a799d71 | 6591 | |
897ab156 AD |
6592 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
6593 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6594 | ||
244e27ad | 6595 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
897ab156 AD |
6596 | struct iphdr *iph = ip_hdr(skb); |
6597 | iph->tot_len = 0; | |
6598 | iph->check = 0; | |
6599 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6600 | iph->daddr, 0, | |
6601 | IPPROTO_TCP, | |
6602 | 0); | |
6603 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
244e27ad AD |
6604 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
6605 | IXGBE_TX_FLAGS_CSUM | | |
6606 | IXGBE_TX_FLAGS_IPV4; | |
897ab156 AD |
6607 | } else if (skb_is_gso_v6(skb)) { |
6608 | ipv6_hdr(skb)->payload_len = 0; | |
6609 | tcp_hdr(skb)->check = | |
6610 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
6611 | &ipv6_hdr(skb)->daddr, | |
6612 | 0, IPPROTO_TCP, 0); | |
244e27ad AD |
6613 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
6614 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
6615 | } |
6616 | ||
091a6246 | 6617 | /* compute header lengths */ |
897ab156 AD |
6618 | l4len = tcp_hdrlen(skb); |
6619 | *hdr_len = skb_transport_offset(skb) + l4len; | |
6620 | ||
091a6246 AD |
6621 | /* update gso size and bytecount with header size */ |
6622 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
6623 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
6624 | ||
897ab156 AD |
6625 | /* mss_l4len_id: use 1 as index for TSO */ |
6626 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
6627 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
6628 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
6629 | ||
6630 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
6631 | vlan_macip_lens = skb_network_header_len(skb); | |
6632 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 6633 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
6634 | |
6635 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 6636 | mss_l4len_idx); |
897ab156 AD |
6637 | |
6638 | return 1; | |
6639 | } | |
6640 | ||
244e27ad AD |
6641 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
6642 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 6643 | { |
fd0db0ed | 6644 | struct sk_buff *skb = first->skb; |
897ab156 AD |
6645 | u32 vlan_macip_lens = 0; |
6646 | u32 mss_l4len_idx = 0; | |
6647 | u32 type_tucmd = 0; | |
7ca647bd | 6648 | |
897ab156 | 6649 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
244e27ad AD |
6650 | if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
6651 | !(first->tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
6652 | return; | |
897ab156 AD |
6653 | } else { |
6654 | u8 l4_hdr = 0; | |
244e27ad | 6655 | switch (first->protocol) { |
897ab156 AD |
6656 | case __constant_htons(ETH_P_IP): |
6657 | vlan_macip_lens |= skb_network_header_len(skb); | |
6658 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
6659 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 6660 | break; |
897ab156 AD |
6661 | case __constant_htons(ETH_P_IPV6): |
6662 | vlan_macip_lens |= skb_network_header_len(skb); | |
6663 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
6664 | break; | |
6665 | default: | |
6666 | if (unlikely(net_ratelimit())) { | |
6667 | dev_warn(tx_ring->dev, | |
6668 | "partial checksum but proto=%x!\n", | |
244e27ad | 6669 | first->protocol); |
897ab156 | 6670 | } |
7ca647bd JP |
6671 | break; |
6672 | } | |
897ab156 AD |
6673 | |
6674 | switch (l4_hdr) { | |
7ca647bd | 6675 | case IPPROTO_TCP: |
897ab156 AD |
6676 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
6677 | mss_l4len_idx = tcp_hdrlen(skb) << | |
6678 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
6679 | break; |
6680 | case IPPROTO_SCTP: | |
897ab156 AD |
6681 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
6682 | mss_l4len_idx = sizeof(struct sctphdr) << | |
6683 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
6684 | break; | |
6685 | case IPPROTO_UDP: | |
6686 | mss_l4len_idx = sizeof(struct udphdr) << | |
6687 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
6688 | break; | |
6689 | default: | |
6690 | if (unlikely(net_ratelimit())) { | |
6691 | dev_warn(tx_ring->dev, | |
6692 | "partial checksum but l4 proto=%x!\n", | |
244e27ad | 6693 | l4_hdr); |
897ab156 | 6694 | } |
7ca647bd JP |
6695 | break; |
6696 | } | |
244e27ad AD |
6697 | |
6698 | /* update TX checksum flag */ | |
6699 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7ca647bd JP |
6700 | } |
6701 | ||
244e27ad | 6702 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
897ab156 | 6703 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 6704 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 6705 | |
897ab156 AD |
6706 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
6707 | type_tucmd, mss_l4len_idx); | |
9a799d71 AK |
6708 | } |
6709 | ||
d3d00239 | 6710 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 6711 | { |
d3d00239 AD |
6712 | /* set type for advanced descriptor with frame checksum insertion */ |
6713 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
6714 | IXGBE_ADVTXD_DCMD_IFCS | | |
6715 | IXGBE_ADVTXD_DCMD_DEXT); | |
9a799d71 | 6716 | |
d3d00239 | 6717 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 6718 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 6719 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 6720 | |
d3d00239 AD |
6721 | /* set segmentation enable bits for TSO/FSO */ |
6722 | #ifdef IXGBE_FCOE | |
93f5b3c1 | 6723 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) |
d3d00239 AD |
6724 | #else |
6725 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
6726 | #endif | |
6727 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 6728 | |
d3d00239 AD |
6729 | return cmd_type; |
6730 | } | |
9a799d71 | 6731 | |
729739b7 AD |
6732 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
6733 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 6734 | { |
93f5b3c1 | 6735 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); |
9a799d71 | 6736 | |
d3d00239 AD |
6737 | /* enable L4 checksum for TSO and TX checksum offload */ |
6738 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
6739 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 6740 | |
93f5b3c1 AD |
6741 | /* enble IPv4 checksum for TSO */ |
6742 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
6743 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 6744 | |
93f5b3c1 AD |
6745 | /* use index 1 context for TSO/FSO/FCOE */ |
6746 | #ifdef IXGBE_FCOE | |
6747 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) | |
6748 | #else | |
6749 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
d3d00239 | 6750 | #endif |
93f5b3c1 AD |
6751 | olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); |
6752 | ||
7f9643fd AD |
6753 | /* |
6754 | * Check Context must be set if Tx switch is enabled, which it | |
6755 | * always is for case where virtual functions are running | |
6756 | */ | |
93f5b3c1 AD |
6757 | #ifdef IXGBE_FCOE |
6758 | if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) | |
6759 | #else | |
7f9643fd | 6760 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) |
93f5b3c1 | 6761 | #endif |
7f9643fd AD |
6762 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); |
6763 | ||
729739b7 | 6764 | tx_desc->read.olinfo_status = olinfo_status; |
d3d00239 | 6765 | } |
44df32c5 | 6766 | |
d3d00239 AD |
6767 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
6768 | IXGBE_TXD_CMD_RS) | |
6769 | ||
6770 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 6771 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
6772 | const u8 hdr_len) |
6773 | { | |
729739b7 | 6774 | dma_addr_t dma; |
fd0db0ed | 6775 | struct sk_buff *skb = first->skb; |
729739b7 | 6776 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 6777 | union ixgbe_adv_tx_desc *tx_desc; |
729739b7 | 6778 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
d3d00239 AD |
6779 | unsigned int data_len = skb->data_len; |
6780 | unsigned int size = skb_headlen(skb); | |
729739b7 | 6781 | unsigned int paylen = skb->len - hdr_len; |
244e27ad | 6782 | u32 tx_flags = first->tx_flags; |
729739b7 | 6783 | __le32 cmd_type; |
d3d00239 | 6784 | u16 i = tx_ring->next_to_use; |
d3d00239 | 6785 | |
729739b7 AD |
6786 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
6787 | ||
6788 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen); | |
6789 | cmd_type = ixgbe_tx_cmd_type(tx_flags); | |
6790 | ||
d3d00239 AD |
6791 | #ifdef IXGBE_FCOE |
6792 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 6793 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
6794 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
6795 | data_len = 0; | |
729739b7 AD |
6796 | } else { |
6797 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
6798 | } |
6799 | } | |
44df32c5 | 6800 | |
d3d00239 | 6801 | #endif |
729739b7 AD |
6802 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
6803 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6804 | goto dma_error; |
8ad494b0 | 6805 | |
729739b7 AD |
6806 | /* record length, and DMA address */ |
6807 | dma_unmap_len_set(first, len, size); | |
6808 | dma_unmap_addr_set(first, dma, dma); | |
9a799d71 | 6809 | |
729739b7 | 6810 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
e5a43549 | 6811 | |
d3d00239 | 6812 | for (;;) { |
729739b7 | 6813 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 AD |
6814 | tx_desc->read.cmd_type_len = |
6815 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
e5a43549 | 6816 | |
d3d00239 | 6817 | i++; |
729739b7 | 6818 | tx_desc++; |
d3d00239 | 6819 | if (i == tx_ring->count) { |
e4f74028 | 6820 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
6821 | i = 0; |
6822 | } | |
729739b7 AD |
6823 | |
6824 | dma += IXGBE_MAX_DATA_PER_TXD; | |
6825 | size -= IXGBE_MAX_DATA_PER_TXD; | |
6826 | ||
6827 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
6828 | tx_desc->read.olinfo_status = 0; | |
d3d00239 | 6829 | } |
e5a43549 | 6830 | |
729739b7 AD |
6831 | if (likely(!data_len)) |
6832 | break; | |
9a799d71 | 6833 | |
f43f313e BG |
6834 | if (unlikely(skb->no_fcs)) |
6835 | cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS)); | |
d3d00239 | 6836 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9a799d71 | 6837 | |
729739b7 AD |
6838 | i++; |
6839 | tx_desc++; | |
6840 | if (i == tx_ring->count) { | |
6841 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
6842 | i = 0; | |
6843 | } | |
9a799d71 | 6844 | |
d3d00239 | 6845 | #ifdef IXGBE_FCOE |
9e903e08 | 6846 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 6847 | #else |
9e903e08 | 6848 | size = skb_frag_size(frag); |
d3d00239 AD |
6849 | #endif |
6850 | data_len -= size; | |
9a799d71 | 6851 | |
729739b7 AD |
6852 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
6853 | DMA_TO_DEVICE); | |
6854 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6855 | goto dma_error; |
9a799d71 | 6856 | |
729739b7 AD |
6857 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6858 | dma_unmap_len_set(tx_buffer, len, size); | |
6859 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
9a799d71 | 6860 | |
729739b7 AD |
6861 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
6862 | tx_desc->read.olinfo_status = 0; | |
9a799d71 | 6863 | |
729739b7 AD |
6864 | frag++; |
6865 | } | |
9a799d71 | 6866 | |
729739b7 AD |
6867 | /* write last descriptor with RS and EOP bits */ |
6868 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); | |
6869 | tx_desc->read.cmd_type_len = cmd_type; | |
eacd73f7 | 6870 | |
091a6246 | 6871 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 6872 | |
d3d00239 AD |
6873 | /* set the timestamp */ |
6874 | first->time_stamp = jiffies; | |
9a799d71 AK |
6875 | |
6876 | /* | |
729739b7 AD |
6877 | * Force memory writes to complete before letting h/w know there |
6878 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
6879 | * memory model archs, such as IA-64). | |
6880 | * | |
6881 | * We also need this memory barrier to make certain all of the | |
6882 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
6883 | */ |
6884 | wmb(); | |
6885 | ||
d3d00239 AD |
6886 | /* set next_to_watch value indicating a packet is present */ |
6887 | first->next_to_watch = tx_desc; | |
6888 | ||
729739b7 AD |
6889 | i++; |
6890 | if (i == tx_ring->count) | |
6891 | i = 0; | |
6892 | ||
6893 | tx_ring->next_to_use = i; | |
6894 | ||
d3d00239 | 6895 | /* notify HW of packet */ |
84ea2591 | 6896 | writel(i, tx_ring->tail); |
d3d00239 AD |
6897 | |
6898 | return; | |
6899 | dma_error: | |
729739b7 | 6900 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
6901 | |
6902 | /* clear dma mappings for failed tx_buffer_info map */ | |
6903 | for (;;) { | |
729739b7 AD |
6904 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6905 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
6906 | if (tx_buffer == first) | |
d3d00239 AD |
6907 | break; |
6908 | if (i == 0) | |
6909 | i = tx_ring->count; | |
6910 | i--; | |
6911 | } | |
6912 | ||
d3d00239 | 6913 | tx_ring->next_to_use = i; |
9a799d71 AK |
6914 | } |
6915 | ||
fd0db0ed | 6916 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 6917 | struct ixgbe_tx_buffer *first) |
69830529 AD |
6918 | { |
6919 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6920 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6921 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6922 | union { | |
6923 | unsigned char *network; | |
6924 | struct iphdr *ipv4; | |
6925 | struct ipv6hdr *ipv6; | |
6926 | } hdr; | |
ee9e0f0b | 6927 | struct tcphdr *th; |
905e4a41 | 6928 | __be16 vlan_id; |
c4cf55e5 | 6929 | |
69830529 AD |
6930 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6931 | if (!q_vector) | |
6932 | return; | |
6933 | ||
6934 | /* do nothing if sampling is disabled */ | |
6935 | if (!ring->atr_sample_rate) | |
d3ead241 | 6936 | return; |
c4cf55e5 | 6937 | |
69830529 | 6938 | ring->atr_count++; |
c4cf55e5 | 6939 | |
69830529 | 6940 | /* snag network header to get L4 type and address */ |
fd0db0ed | 6941 | hdr.network = skb_network_header(first->skb); |
69830529 AD |
6942 | |
6943 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
244e27ad | 6944 | if ((first->protocol != __constant_htons(ETH_P_IPV6) || |
69830529 | 6945 | hdr.ipv6->nexthdr != IPPROTO_TCP) && |
244e27ad | 6946 | (first->protocol != __constant_htons(ETH_P_IP) || |
69830529 AD |
6947 | hdr.ipv4->protocol != IPPROTO_TCP)) |
6948 | return; | |
ee9e0f0b | 6949 | |
fd0db0ed | 6950 | th = tcp_hdr(first->skb); |
c4cf55e5 | 6951 | |
66f32a8b AD |
6952 | /* skip this packet since it is invalid or the socket is closing */ |
6953 | if (!th || th->fin) | |
69830529 AD |
6954 | return; |
6955 | ||
6956 | /* sample on all syn packets or once every atr sample count */ | |
6957 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6958 | return; | |
6959 | ||
6960 | /* reset sample count */ | |
6961 | ring->atr_count = 0; | |
6962 | ||
244e27ad | 6963 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
6964 | |
6965 | /* | |
6966 | * src and dst are inverted, think how the receiver sees them | |
6967 | * | |
6968 | * The input is broken into two sections, a non-compressed section | |
6969 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6970 | * is XORed together and stored in the compressed dword. | |
6971 | */ | |
6972 | input.formatted.vlan_id = vlan_id; | |
6973 | ||
6974 | /* | |
6975 | * since src port and flex bytes occupy the same word XOR them together | |
6976 | * and write the value to source port portion of compressed dword | |
6977 | */ | |
244e27ad | 6978 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6979 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6980 | else | |
244e27ad | 6981 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
6982 | common.port.dst ^= th->source; |
6983 | ||
244e27ad | 6984 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
69830529 AD |
6985 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
6986 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6987 | } else { | |
6988 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6989 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6990 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6991 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6992 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6993 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6994 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6995 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6996 | hdr.ipv6->daddr.s6_addr32[3]; | |
6997 | } | |
c4cf55e5 PWJ |
6998 | |
6999 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
7000 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
7001 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
7002 | } |
7003 | ||
63544e9c | 7004 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 7005 | { |
fc77dc3c | 7006 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
7007 | /* Herbert's original patch had: |
7008 | * smp_mb__after_netif_stop_queue(); | |
7009 | * but since that doesn't exist yet, just open code it. */ | |
7010 | smp_mb(); | |
7011 | ||
7012 | /* We need to check again in a case another CPU has just | |
7013 | * made room available. */ | |
7d4987de | 7014 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
7015 | return -EBUSY; |
7016 | ||
7017 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 7018 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 7019 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
7020 | return 0; |
7021 | } | |
7022 | ||
82d4e46e | 7023 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 7024 | { |
7d4987de | 7025 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 7026 | return 0; |
fc77dc3c | 7027 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
7028 | } |
7029 | ||
09a3b1f8 SH |
7030 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
7031 | { | |
7032 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
7033 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
7034 | smp_processor_id(); | |
56075a98 | 7035 | #ifdef IXGBE_FCOE |
6440752c | 7036 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 7037 | |
e5b64635 JF |
7038 | if (((protocol == htons(ETH_P_FCOE)) || |
7039 | (protocol == htons(ETH_P_FIP))) && | |
7040 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
7041 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
7042 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
7043 | return txq; | |
56075a98 JF |
7044 | } |
7045 | #endif | |
7046 | ||
fdd3d631 KK |
7047 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
7048 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
7049 | txq -= dev->real_num_tx_queues; | |
5f715823 | 7050 | return txq; |
fdd3d631 | 7051 | } |
c4cf55e5 | 7052 | |
09a3b1f8 SH |
7053 | return skb_tx_hash(dev, skb); |
7054 | } | |
7055 | ||
fc77dc3c | 7056 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
7057 | struct ixgbe_adapter *adapter, |
7058 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 7059 | { |
d3d00239 | 7060 | struct ixgbe_tx_buffer *first; |
5f715823 | 7061 | int tso; |
d3d00239 | 7062 | u32 tx_flags = 0; |
a535c30e AD |
7063 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
7064 | unsigned short f; | |
7065 | #endif | |
a535c30e | 7066 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 7067 | __be16 protocol = skb->protocol; |
63544e9c | 7068 | u8 hdr_len = 0; |
5e09a105 | 7069 | |
a535c30e AD |
7070 | /* |
7071 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 7072 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
7073 | * + 2 desc gap to keep tail from touching head, |
7074 | * + 1 desc for context descriptor, | |
7075 | * otherwise try next time | |
7076 | */ | |
7077 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
7078 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
7079 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
7080 | #else | |
7081 | count += skb_shinfo(skb)->nr_frags; | |
7082 | #endif | |
7083 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
7084 | tx_ring->tx_stats.tx_busy++; | |
7085 | return NETDEV_TX_BUSY; | |
7086 | } | |
7087 | ||
fd0db0ed AD |
7088 | /* record the location of the first descriptor for this packet */ |
7089 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
7090 | first->skb = skb; | |
091a6246 AD |
7091 | first->bytecount = skb->len; |
7092 | first->gso_segs = 1; | |
fd0db0ed | 7093 | |
66f32a8b | 7094 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 7095 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
7096 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
7097 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
7098 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
7099 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
7100 | struct vlan_hdr *vhdr, _vhdr; | |
7101 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
7102 | if (!vhdr) | |
7103 | goto out_drop; | |
7104 | ||
7105 | protocol = vhdr->h_vlan_encapsulated_proto; | |
9e0c5648 AD |
7106 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
7107 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
7108 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
7109 | } | |
7110 | ||
9e0c5648 AD |
7111 | #ifdef CONFIG_PCI_IOV |
7112 | /* | |
7113 | * Use the l2switch_enable flag - would be false if the DMA | |
7114 | * Tx switch had been disabled. | |
7115 | */ | |
7116 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
7117 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
7118 | ||
7119 | #endif | |
32701dc2 | 7120 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 7121 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
7122 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
7123 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 7124 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
7125 | tx_flags |= (skb->priority & 0x7) << |
7126 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
7127 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
7128 | struct vlan_ethhdr *vhdr; | |
7129 | if (skb_header_cloned(skb) && | |
7130 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
7131 | goto out_drop; | |
7132 | vhdr = (struct vlan_ethhdr *)skb->data; | |
7133 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
7134 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
7135 | } else { | |
7136 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 7137 | } |
9a799d71 | 7138 | } |
eacd73f7 | 7139 | |
244e27ad AD |
7140 | /* record initial flags and protocol */ |
7141 | first->tx_flags = tx_flags; | |
7142 | first->protocol = protocol; | |
7143 | ||
eacd73f7 | 7144 | #ifdef IXGBE_FCOE |
66f32a8b AD |
7145 | /* setup tx offload for FCoE */ |
7146 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
7147 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
244e27ad | 7148 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
7149 | if (tso < 0) |
7150 | goto out_drop; | |
9a799d71 | 7151 | |
66f32a8b | 7152 | goto xmit_fcoe; |
eacd73f7 | 7153 | } |
9a799d71 | 7154 | |
66f32a8b | 7155 | #endif /* IXGBE_FCOE */ |
244e27ad | 7156 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 7157 | if (tso < 0) |
897ab156 | 7158 | goto out_drop; |
244e27ad AD |
7159 | else if (!tso) |
7160 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
7161 | |
7162 | /* add the ATR filter if ATR is on */ | |
7163 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 7164 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
7165 | |
7166 | #ifdef IXGBE_FCOE | |
7167 | xmit_fcoe: | |
7168 | #endif /* IXGBE_FCOE */ | |
244e27ad | 7169 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 AD |
7170 | |
7171 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
7172 | |
7173 | return NETDEV_TX_OK; | |
897ab156 AD |
7174 | |
7175 | out_drop: | |
fd0db0ed AD |
7176 | dev_kfree_skb_any(first->skb); |
7177 | first->skb = NULL; | |
7178 | ||
897ab156 | 7179 | return NETDEV_TX_OK; |
9a799d71 AK |
7180 | } |
7181 | ||
a50c29dd AD |
7182 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
7183 | struct net_device *netdev) | |
84418e3b AD |
7184 | { |
7185 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7186 | struct ixgbe_ring *tx_ring; | |
7187 | ||
a50c29dd AD |
7188 | if (skb->len <= 0) { |
7189 | dev_kfree_skb_any(skb); | |
7190 | return NETDEV_TX_OK; | |
7191 | } | |
7192 | ||
7193 | /* | |
7194 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
7195 | * in order to meet this minimum size requirement. | |
7196 | */ | |
7197 | if (skb->len < 17) { | |
7198 | if (skb_padto(skb, 17)) | |
7199 | return NETDEV_TX_OK; | |
7200 | skb->len = 17; | |
7201 | } | |
7202 | ||
84418e3b | 7203 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
fc77dc3c | 7204 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
7205 | } |
7206 | ||
9a799d71 AK |
7207 | /** |
7208 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
7209 | * @netdev: network interface device structure | |
7210 | * @p: pointer to an address structure | |
7211 | * | |
7212 | * Returns 0 on success, negative on failure | |
7213 | **/ | |
7214 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
7215 | { | |
7216 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 7217 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
7218 | struct sockaddr *addr = p; |
7219 | ||
7220 | if (!is_valid_ether_addr(addr->sa_data)) | |
7221 | return -EADDRNOTAVAIL; | |
7222 | ||
7223 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 7224 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 7225 | |
1cdd1ec8 GR |
7226 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
7227 | IXGBE_RAH_AV); | |
9a799d71 AK |
7228 | |
7229 | return 0; | |
7230 | } | |
7231 | ||
6b73e10d BH |
7232 | static int |
7233 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
7234 | { | |
7235 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7236 | struct ixgbe_hw *hw = &adapter->hw; | |
7237 | u16 value; | |
7238 | int rc; | |
7239 | ||
7240 | if (prtad != hw->phy.mdio.prtad) | |
7241 | return -EINVAL; | |
7242 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
7243 | if (!rc) | |
7244 | rc = value; | |
7245 | return rc; | |
7246 | } | |
7247 | ||
7248 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
7249 | u16 addr, u16 value) | |
7250 | { | |
7251 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7252 | struct ixgbe_hw *hw = &adapter->hw; | |
7253 | ||
7254 | if (prtad != hw->phy.mdio.prtad) | |
7255 | return -EINVAL; | |
7256 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
7257 | } | |
7258 | ||
7259 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
7260 | { | |
7261 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7262 | ||
7263 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
7264 | } | |
7265 | ||
0365e6e4 PW |
7266 | /** |
7267 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 7268 | * netdev->dev_addrs |
0365e6e4 PW |
7269 | * @netdev: network interface device structure |
7270 | * | |
7271 | * Returns non-zero on failure | |
7272 | **/ | |
7273 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
7274 | { | |
7275 | int err = 0; | |
7276 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7277 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
7278 | ||
7279 | if (is_valid_ether_addr(mac->san_addr)) { | |
7280 | rtnl_lock(); | |
7281 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
7282 | rtnl_unlock(); | |
7283 | } | |
7284 | return err; | |
7285 | } | |
7286 | ||
7287 | /** | |
7288 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 7289 | * netdev->dev_addrs |
0365e6e4 PW |
7290 | * @netdev: network interface device structure |
7291 | * | |
7292 | * Returns non-zero on failure | |
7293 | **/ | |
7294 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
7295 | { | |
7296 | int err = 0; | |
7297 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7298 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
7299 | ||
7300 | if (is_valid_ether_addr(mac->san_addr)) { | |
7301 | rtnl_lock(); | |
7302 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
7303 | rtnl_unlock(); | |
7304 | } | |
7305 | return err; | |
7306 | } | |
7307 | ||
9a799d71 AK |
7308 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7309 | /* | |
7310 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
7311 | * without having to re-enable interrupts. It's not called while | |
7312 | * the interrupt routine is executing. | |
7313 | */ | |
7314 | static void ixgbe_netpoll(struct net_device *netdev) | |
7315 | { | |
7316 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 7317 | int i; |
9a799d71 | 7318 | |
1a647bd2 AD |
7319 | /* if interface is down do nothing */ |
7320 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
7321 | return; | |
7322 | ||
9a799d71 | 7323 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
7324 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
7325 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
7326 | for (i = 0; i < num_q_vectors; i++) { | |
7327 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
4ff7fb12 | 7328 | ixgbe_msix_clean_rings(0, q_vector); |
8f9a7167 PWJ |
7329 | } |
7330 | } else { | |
7331 | ixgbe_intr(adapter->pdev->irq, netdev); | |
7332 | } | |
9a799d71 | 7333 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 | 7334 | } |
9a799d71 | 7335 | |
581330ba | 7336 | #endif |
de1036b1 ED |
7337 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
7338 | struct rtnl_link_stats64 *stats) | |
7339 | { | |
7340 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7341 | int i; | |
7342 | ||
1a51502b | 7343 | rcu_read_lock(); |
de1036b1 | 7344 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 7345 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
7346 | u64 bytes, packets; |
7347 | unsigned int start; | |
7348 | ||
1a51502b ED |
7349 | if (ring) { |
7350 | do { | |
7351 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
7352 | packets = ring->stats.packets; | |
7353 | bytes = ring->stats.bytes; | |
7354 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
7355 | stats->rx_packets += packets; | |
7356 | stats->rx_bytes += bytes; | |
7357 | } | |
de1036b1 | 7358 | } |
1ac9ad13 ED |
7359 | |
7360 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
7361 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
7362 | u64 bytes, packets; | |
7363 | unsigned int start; | |
7364 | ||
7365 | if (ring) { | |
7366 | do { | |
7367 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
7368 | packets = ring->stats.packets; | |
7369 | bytes = ring->stats.bytes; | |
7370 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
7371 | stats->tx_packets += packets; | |
7372 | stats->tx_bytes += bytes; | |
7373 | } | |
7374 | } | |
1a51502b | 7375 | rcu_read_unlock(); |
de1036b1 ED |
7376 | /* following stats updated by ixgbe_watchdog_task() */ |
7377 | stats->multicast = netdev->stats.multicast; | |
7378 | stats->rx_errors = netdev->stats.rx_errors; | |
7379 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
7380 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
7381 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
7382 | return stats; | |
7383 | } | |
7384 | ||
8b1c0b24 JF |
7385 | /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. |
7386 | * #adapter: pointer to ixgbe_adapter | |
7387 | * @tc: number of traffic classes currently enabled | |
7388 | * | |
7389 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
7390 | * 802.1Q priority maps to a packet buffer that exists. | |
7391 | */ | |
7392 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
7393 | { | |
7394 | struct ixgbe_hw *hw = &adapter->hw; | |
7395 | u32 reg, rsave; | |
7396 | int i; | |
7397 | ||
7398 | /* 82598 have a static priority to TC mapping that can not | |
7399 | * be changed so no validation is needed. | |
7400 | */ | |
7401 | if (hw->mac.type == ixgbe_mac_82598EB) | |
7402 | return; | |
7403 | ||
7404 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
7405 | rsave = reg; | |
7406 | ||
7407 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
7408 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
7409 | ||
7410 | /* If up2tc is out of bounds default to zero */ | |
7411 | if (up2tc > tc) | |
7412 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
7413 | } | |
7414 | ||
7415 | if (reg != rsave) | |
7416 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
7417 | ||
7418 | return; | |
7419 | } | |
7420 | ||
8b1c0b24 JF |
7421 | /* ixgbe_setup_tc - routine to configure net_device for multiple traffic |
7422 | * classes. | |
7423 | * | |
7424 | * @netdev: net device to configure | |
7425 | * @tc: number of traffic classes to enable | |
7426 | */ | |
7427 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
7428 | { | |
8b1c0b24 JF |
7429 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
7430 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 7431 | |
e7589eab JF |
7432 | /* Multiple traffic classes requires multiple queues */ |
7433 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { | |
7434 | e_err(drv, "Enable failed, needs MSI-X\n"); | |
7435 | return -EINVAL; | |
7436 | } | |
8b1c0b24 JF |
7437 | |
7438 | /* Hardware supports up to 8 traffic classes */ | |
4de2a022 | 7439 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || |
581330ba AD |
7440 | (hw->mac.type == ixgbe_mac_82598EB && |
7441 | tc < MAX_TRAFFIC_CLASS)) | |
8b1c0b24 JF |
7442 | return -EINVAL; |
7443 | ||
7444 | /* Hardware has to reinitialize queues and interrupts to | |
52f33af8 | 7445 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
7446 | * hardware is not flexible enough to do this dynamically. |
7447 | */ | |
7448 | if (netif_running(dev)) | |
7449 | ixgbe_close(dev); | |
7450 | ixgbe_clear_interrupt_scheme(adapter); | |
7451 | ||
e7589eab | 7452 | if (tc) { |
8b1c0b24 | 7453 | netdev_set_num_tc(dev, tc); |
e7589eab | 7454 | adapter->last_lfc_mode = adapter->hw.fc.current_mode; |
e7589eab JF |
7455 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
7456 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7457 | ||
7458 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
7459 | adapter->hw.fc.requested_mode = ixgbe_fc_none; | |
7460 | } else { | |
8b1c0b24 | 7461 | netdev_reset_tc(dev); |
e7589eab JF |
7462 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; |
7463 | ||
7464 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
7465 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7466 | ||
7467 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
7468 | adapter->dcb_cfg.pfc_mode_enable = false; | |
7469 | } | |
7470 | ||
8b1c0b24 JF |
7471 | ixgbe_init_interrupt_scheme(adapter); |
7472 | ixgbe_validate_rtr(adapter, tc); | |
7473 | if (netif_running(dev)) | |
7474 | ixgbe_open(dev); | |
7475 | ||
7476 | return 0; | |
7477 | } | |
de1036b1 | 7478 | |
082757af DS |
7479 | void ixgbe_do_reset(struct net_device *netdev) |
7480 | { | |
7481 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7482 | ||
7483 | if (netif_running(netdev)) | |
7484 | ixgbe_reinit_locked(adapter); | |
7485 | else | |
7486 | ixgbe_reset(adapter); | |
7487 | } | |
7488 | ||
c8f44aff MM |
7489 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
7490 | netdev_features_t data) | |
082757af DS |
7491 | { |
7492 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7493 | ||
7494 | #ifdef CONFIG_DCB | |
7495 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
7496 | data &= ~NETIF_F_HW_VLAN_RX; | |
7497 | #endif | |
7498 | ||
7499 | /* return error if RXHASH is being enabled when RSS is not supported */ | |
7500 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) | |
7501 | data &= ~NETIF_F_RXHASH; | |
7502 | ||
7503 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ | |
7504 | if (!(data & NETIF_F_RXCSUM)) | |
7505 | data &= ~NETIF_F_LRO; | |
7506 | ||
7507 | /* Turn off LRO if not RSC capable or invalid ITR settings */ | |
7508 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) { | |
7509 | data &= ~NETIF_F_LRO; | |
7510 | } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && | |
7511 | (adapter->rx_itr_setting != 1 && | |
7512 | adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) { | |
7513 | data &= ~NETIF_F_LRO; | |
7514 | e_info(probe, "rx-usecs set too low, not enabling RSC\n"); | |
7515 | } | |
7516 | ||
7517 | return data; | |
7518 | } | |
7519 | ||
c8f44aff MM |
7520 | static int ixgbe_set_features(struct net_device *netdev, |
7521 | netdev_features_t data) | |
082757af DS |
7522 | { |
7523 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3f2d1c0f | 7524 | netdev_features_t changed = netdev->features ^ data; |
082757af DS |
7525 | bool need_reset = false; |
7526 | ||
082757af DS |
7527 | /* Make sure RSC matches LRO, reset if change */ |
7528 | if (!!(data & NETIF_F_LRO) != | |
7529 | !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
7530 | adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED; | |
7531 | switch (adapter->hw.mac.type) { | |
7532 | case ixgbe_mac_X540: | |
7533 | case ixgbe_mac_82599EB: | |
7534 | need_reset = true; | |
7535 | break; | |
7536 | default: | |
7537 | break; | |
7538 | } | |
7539 | } | |
7540 | ||
7541 | /* | |
7542 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
7543 | * the state changed, we need to reset. | |
7544 | */ | |
7545 | if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
7546 | /* turn off ATR, enable perfect filters and reset */ | |
7547 | if (data & NETIF_F_NTUPLE) { | |
7548 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7549 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
7550 | need_reset = true; | |
7551 | } | |
7552 | } else if (!(data & NETIF_F_NTUPLE)) { | |
7553 | /* turn off Flow Director, set ATR and reset */ | |
7554 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
7555 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && | |
7556 | !(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
7557 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7558 | need_reset = true; | |
7559 | } | |
7560 | ||
3f2d1c0f BG |
7561 | if (changed & NETIF_F_RXALL) |
7562 | need_reset = true; | |
7563 | ||
7564 | netdev->features = data; | |
082757af DS |
7565 | if (need_reset) |
7566 | ixgbe_do_reset(netdev); | |
7567 | ||
7568 | return 0; | |
7569 | ||
7570 | } | |
7571 | ||
0edc3527 | 7572 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 7573 | .ndo_open = ixgbe_open, |
0edc3527 | 7574 | .ndo_stop = ixgbe_close, |
00829823 | 7575 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 7576 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 7577 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
7578 | .ndo_validate_addr = eth_validate_addr, |
7579 | .ndo_set_mac_address = ixgbe_set_mac, | |
7580 | .ndo_change_mtu = ixgbe_change_mtu, | |
7581 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
7582 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
7583 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 7584 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
7585 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
7586 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
7587 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
581330ba | 7588 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
7f01648a | 7589 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 7590 | .ndo_get_stats64 = ixgbe_get_stats64, |
24095aa3 | 7591 | .ndo_setup_tc = ixgbe_setup_tc, |
0edc3527 SH |
7592 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7593 | .ndo_poll_controller = ixgbe_netpoll, | |
7594 | #endif | |
332d4a7d YZ |
7595 | #ifdef IXGBE_FCOE |
7596 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 7597 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 7598 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
7599 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
7600 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 7601 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 7602 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 7603 | #endif /* IXGBE_FCOE */ |
082757af DS |
7604 | .ndo_set_features = ixgbe_set_features, |
7605 | .ndo_fix_features = ixgbe_fix_features, | |
0edc3527 SH |
7606 | }; |
7607 | ||
1cdd1ec8 GR |
7608 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
7609 | const struct ixgbe_info *ii) | |
7610 | { | |
7611 | #ifdef CONFIG_PCI_IOV | |
7612 | struct ixgbe_hw *hw = &adapter->hw; | |
1cdd1ec8 | 7613 | |
c6bda30a | 7614 | if (hw->mac.type == ixgbe_mac_82598EB) |
1cdd1ec8 GR |
7615 | return; |
7616 | ||
7617 | /* The 82599 supports up to 64 VFs per physical function | |
7618 | * but this implementation limits allocation to 63 so that | |
7619 | * basic networking resources are still available to the | |
7620 | * physical function | |
7621 | */ | |
7622 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
c6bda30a | 7623 | ixgbe_enable_sriov(adapter, ii); |
1cdd1ec8 GR |
7624 | #endif /* CONFIG_PCI_IOV */ |
7625 | } | |
7626 | ||
9a799d71 AK |
7627 | /** |
7628 | * ixgbe_probe - Device Initialization Routine | |
7629 | * @pdev: PCI device information struct | |
7630 | * @ent: entry in ixgbe_pci_tbl | |
7631 | * | |
7632 | * Returns 0 on success, negative on failure | |
7633 | * | |
7634 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7635 | * The OS initialization, configuring of the adapter private structure, | |
7636 | * and a hardware reset occur. | |
7637 | **/ | |
7638 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7639 | const struct pci_device_id *ent) |
9a799d71 AK |
7640 | { |
7641 | struct net_device *netdev; | |
7642 | struct ixgbe_adapter *adapter = NULL; | |
7643 | struct ixgbe_hw *hw; | |
7644 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7645 | static int cards_found; |
7646 | int i, err, pci_using_dac; | |
289700db | 7647 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7648 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
7649 | #ifdef IXGBE_FCOE |
7650 | u16 device_caps; | |
7651 | #endif | |
289700db | 7652 | u32 eec; |
c23f5b6b | 7653 | u16 wol_cap; |
9a799d71 | 7654 | |
bded64a7 AG |
7655 | /* Catch broken hardware that put the wrong VF device ID in |
7656 | * the PCIe SR-IOV capability. | |
7657 | */ | |
7658 | if (pdev->is_virtfn) { | |
7659 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7660 | pci_name(pdev), pdev->vendor, pdev->device); | |
7661 | return -EINVAL; | |
7662 | } | |
7663 | ||
9ce77666 | 7664 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7665 | if (err) |
7666 | return err; | |
7667 | ||
1b507730 NN |
7668 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7669 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7670 | pci_using_dac = 1; |
7671 | } else { | |
1b507730 | 7672 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7673 | if (err) { |
1b507730 NN |
7674 | err = dma_set_coherent_mask(&pdev->dev, |
7675 | DMA_BIT_MASK(32)); | |
9a799d71 | 7676 | if (err) { |
b8bc0421 DC |
7677 | dev_err(&pdev->dev, |
7678 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7679 | goto err_dma; |
7680 | } | |
7681 | } | |
7682 | pci_using_dac = 0; | |
7683 | } | |
7684 | ||
9ce77666 | 7685 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7686 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7687 | if (err) { |
b8bc0421 DC |
7688 | dev_err(&pdev->dev, |
7689 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7690 | goto err_pci_reg; |
7691 | } | |
7692 | ||
19d5afd4 | 7693 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7694 | |
9a799d71 | 7695 | pci_set_master(pdev); |
fb3b27bc | 7696 | pci_save_state(pdev); |
9a799d71 | 7697 | |
e901acd6 JF |
7698 | #ifdef CONFIG_IXGBE_DCB |
7699 | indices *= MAX_TRAFFIC_CLASS; | |
7700 | #endif | |
7701 | ||
c85a2618 JF |
7702 | if (ii->mac == ixgbe_mac_82598EB) |
7703 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
7704 | else | |
7705 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7706 | ||
e901acd6 | 7707 | #ifdef IXGBE_FCOE |
c85a2618 JF |
7708 | indices += min_t(unsigned int, num_possible_cpus(), |
7709 | IXGBE_MAX_FCOE_INDICES); | |
7710 | #endif | |
c85a2618 | 7711 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7712 | if (!netdev) { |
7713 | err = -ENOMEM; | |
7714 | goto err_alloc_etherdev; | |
7715 | } | |
7716 | ||
9a799d71 AK |
7717 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7718 | ||
9a799d71 | 7719 | adapter = netdev_priv(netdev); |
c60fbb00 | 7720 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7721 | |
7722 | adapter->netdev = netdev; | |
7723 | adapter->pdev = pdev; | |
7724 | hw = &adapter->hw; | |
7725 | hw->back = adapter; | |
7726 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
7727 | ||
05857980 | 7728 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7729 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7730 | if (!hw->hw_addr) { |
7731 | err = -EIO; | |
7732 | goto err_ioremap; | |
7733 | } | |
7734 | ||
7735 | for (i = 1; i <= 5; i++) { | |
7736 | if (pci_resource_len(pdev, i) == 0) | |
7737 | continue; | |
7738 | } | |
7739 | ||
0edc3527 | 7740 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7741 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7742 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7743 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7744 | |
9a799d71 AK |
7745 | adapter->bd_number = cards_found; |
7746 | ||
9a799d71 AK |
7747 | /* Setup hw api */ |
7748 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7749 | hw->mac.type = ii->mac; |
9a799d71 | 7750 | |
c44ade9e JB |
7751 | /* EEPROM */ |
7752 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7753 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7754 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7755 | if (!(eec & (1 << 8))) | |
7756 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7757 | ||
7758 | /* PHY */ | |
7759 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7760 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7761 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7762 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7763 | hw->phy.mdio.mmds = 0; | |
7764 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7765 | hw->phy.mdio.dev = netdev; | |
7766 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7767 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 7768 | |
8ca783ab | 7769 | ii->get_invariants(hw); |
9a799d71 AK |
7770 | |
7771 | /* setup the private structure */ | |
7772 | err = ixgbe_sw_init(adapter); | |
7773 | if (err) | |
7774 | goto err_sw_init; | |
7775 | ||
e86bff0e | 7776 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7777 | switch (adapter->hw.mac.type) { |
7778 | case ixgbe_mac_82599EB: | |
7779 | case ixgbe_mac_X540: | |
e86bff0e | 7780 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7781 | break; |
7782 | default: | |
7783 | break; | |
7784 | } | |
e86bff0e | 7785 | |
bf069c97 DS |
7786 | /* |
7787 | * If there is a fan on this device and it has failed log the | |
7788 | * failure. | |
7789 | */ | |
7790 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7791 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7792 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7793 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7794 | } |
7795 | ||
8ef78adc PWJ |
7796 | if (allow_unsupported_sfp) |
7797 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
7798 | ||
c44ade9e | 7799 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7800 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7801 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7802 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7803 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7804 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7805 | err = 0; |
7806 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7807 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7808 | "module type was detected.\n"); |
7809 | e_dev_err("Reload the driver after installing a supported " | |
7810 | "module.\n"); | |
04f165ef PW |
7811 | goto err_sw_init; |
7812 | } else if (err) { | |
849c4542 | 7813 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7814 | goto err_sw_init; |
7815 | } | |
7816 | ||
1cdd1ec8 GR |
7817 | ixgbe_probe_vf(adapter, ii); |
7818 | ||
396e799c | 7819 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7820 | NETIF_F_IP_CSUM | |
082757af | 7821 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7822 | NETIF_F_HW_VLAN_TX | |
7823 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7824 | NETIF_F_HW_VLAN_FILTER | |
7825 | NETIF_F_TSO | | |
7826 | NETIF_F_TSO6 | | |
082757af DS |
7827 | NETIF_F_RXHASH | |
7828 | NETIF_F_RXCSUM; | |
9a799d71 | 7829 | |
082757af | 7830 | netdev->hw_features = netdev->features; |
ad31c402 | 7831 | |
58be7666 DS |
7832 | switch (adapter->hw.mac.type) { |
7833 | case ixgbe_mac_82599EB: | |
7834 | case ixgbe_mac_X540: | |
45a5ead0 | 7835 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7836 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7837 | NETIF_F_NTUPLE; | |
58be7666 DS |
7838 | break; |
7839 | default: | |
7840 | break; | |
7841 | } | |
45a5ead0 | 7842 | |
3f2d1c0f BG |
7843 | netdev->hw_features |= NETIF_F_RXALL; |
7844 | ||
ad31c402 JK |
7845 | netdev->vlan_features |= NETIF_F_TSO; |
7846 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7847 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7848 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7849 | netdev->vlan_features |= NETIF_F_SG; |
7850 | ||
01789349 | 7851 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 7852 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 7853 | |
1cdd1ec8 GR |
7854 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7855 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7856 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 | 7857 | |
7a6b6f51 | 7858 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7859 | netdev->dcbnl_ops = &dcbnl_ops; |
7860 | #endif | |
7861 | ||
eacd73f7 | 7862 | #ifdef IXGBE_FCOE |
0d551589 | 7863 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7864 | if (hw->mac.ops.get_device_caps) { |
7865 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7866 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7867 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7868 | } |
7869 | } | |
5e09d7f6 YZ |
7870 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7871 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7872 | netdev->vlan_features |= NETIF_F_FSO; | |
7873 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7874 | } | |
eacd73f7 | 7875 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7876 | if (pci_using_dac) { |
9a799d71 | 7877 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7878 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7879 | } | |
9a799d71 | 7880 | |
082757af DS |
7881 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7882 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7883 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7884 | netdev->features |= NETIF_F_LRO; |
7885 | ||
9a799d71 | 7886 | /* make sure the EEPROM is good */ |
c44ade9e | 7887 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7888 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 7889 | err = -EIO; |
35937c05 | 7890 | goto err_sw_init; |
9a799d71 AK |
7891 | } |
7892 | ||
7893 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7894 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7895 | ||
c44ade9e | 7896 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7897 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 7898 | err = -EIO; |
35937c05 | 7899 | goto err_sw_init; |
9a799d71 AK |
7900 | } |
7901 | ||
7086400d | 7902 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 7903 | (unsigned long) adapter); |
9a799d71 | 7904 | |
7086400d AD |
7905 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7906 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7907 | |
021230d4 AV |
7908 | err = ixgbe_init_interrupt_scheme(adapter); |
7909 | if (err) | |
7910 | goto err_sw_init; | |
9a799d71 | 7911 | |
082757af DS |
7912 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { |
7913 | netdev->hw_features &= ~NETIF_F_RXHASH; | |
67a74ee2 | 7914 | netdev->features &= ~NETIF_F_RXHASH; |
082757af | 7915 | } |
67a74ee2 | 7916 | |
c23f5b6b ET |
7917 | /* WOL not supported for all but the following */ |
7918 | adapter->wol = 0; | |
e8e26350 | 7919 | switch (pdev->device) { |
0b077fea | 7920 | case IXGBE_DEV_ID_82599_SFP: |
0e22d043 DS |
7921 | /* Only these subdevice supports WOL */ |
7922 | switch (pdev->subsystem_device) { | |
7923 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
7924 | /* only support first port */ | |
7925 | if (hw->bus.func != 0) | |
7926 | break; | |
7927 | case IXGBE_SUBDEV_ID_82599_SFP: | |
9417c464 | 7928 | adapter->wol = IXGBE_WUFC_MAG; |
0e22d043 DS |
7929 | break; |
7930 | } | |
0b077fea | 7931 | break; |
50d6c681 AD |
7932 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
7933 | /* All except this subdevice support WOL */ | |
0b077fea | 7934 | if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) |
9417c464 | 7935 | adapter->wol = IXGBE_WUFC_MAG; |
0b077fea | 7936 | break; |
e8e26350 | 7937 | case IXGBE_DEV_ID_82599_KX4: |
9417c464 | 7938 | adapter->wol = IXGBE_WUFC_MAG; |
e8e26350 | 7939 | break; |
c23f5b6b ET |
7940 | case IXGBE_DEV_ID_X540T: |
7941 | /* Check eeprom to see if it is enabled */ | |
7942 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); | |
7943 | wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
7944 | ||
7945 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
7946 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
7947 | (hw->bus.func == 0))) | |
7948 | adapter->wol = IXGBE_WUFC_MAG; | |
e8e26350 PW |
7949 | break; |
7950 | } | |
e8e26350 PW |
7951 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7952 | ||
15e5209f ET |
7953 | /* save off EEPROM version number */ |
7954 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
7955 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
7956 | ||
04f165ef PW |
7957 | /* pick up the PCI bus settings for reporting later */ |
7958 | hw->mac.ops.get_bus_info(hw); | |
7959 | ||
9a799d71 | 7960 | /* print bus type/speed/width info */ |
849c4542 | 7961 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7962 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7963 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7964 | "Unknown"), |
7965 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7966 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7967 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7968 | "Unknown"), | |
7969 | netdev->dev_addr); | |
289700db DS |
7970 | |
7971 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7972 | if (err) | |
9fe93afd | 7973 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7974 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7975 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7976 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7977 | part_str); |
e8e26350 | 7978 | else |
289700db DS |
7979 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7980 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7981 | |
e8e26350 | 7982 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7983 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7984 | "not sufficient for optimal performance.\n"); | |
7985 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7986 | "is required.\n"); | |
0c254d86 AK |
7987 | } |
7988 | ||
9a799d71 | 7989 | /* reset the hardware with the new settings */ |
794caeb2 | 7990 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
7991 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7992 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7993 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7994 | "Please be aware there may be issues associated " | |
7995 | "with your hardware. If you are experiencing " | |
7996 | "problems please contact your Intel or hardware " | |
7997 | "representative who provided you with this " | |
7998 | "hardware.\n"); | |
794caeb2 | 7999 | } |
9a799d71 AK |
8000 | strcpy(netdev->name, "eth%d"); |
8001 | err = register_netdev(netdev); | |
8002 | if (err) | |
8003 | goto err_register; | |
8004 | ||
93d3ce8f ET |
8005 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
8006 | if (hw->mac.ops.disable_tx_laser && | |
8007 | ((hw->phy.multispeed_fiber) || | |
8008 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && | |
8009 | (hw->mac.type == ixgbe_mac_82599EB)))) | |
8010 | hw->mac.ops.disable_tx_laser(hw); | |
8011 | ||
54386467 JB |
8012 | /* carrier off reporting is important to ethtool even BEFORE open */ |
8013 | netif_carrier_off(netdev); | |
8014 | ||
5dd2d332 | 8015 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 8016 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 8017 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
8018 | ixgbe_setup_dca(adapter); |
8019 | } | |
8020 | #endif | |
1cdd1ec8 | 8021 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 8022 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
8023 | for (i = 0; i < adapter->num_vfs; i++) |
8024 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
8025 | } | |
8026 | ||
2466dd9c JK |
8027 | /* firmware requires driver version to be 0xFFFFFFFF |
8028 | * since os does not support feature | |
8029 | */ | |
9612de92 | 8030 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
8031 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
8032 | 0xFF); | |
9612de92 | 8033 | |
0365e6e4 PW |
8034 | /* add san mac addr to netdev */ |
8035 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 8036 | |
ea81875a | 8037 | e_dev_info("%s\n", ixgbe_default_device_descr); |
9a799d71 AK |
8038 | cards_found++; |
8039 | return 0; | |
8040 | ||
8041 | err_register: | |
5eba3699 | 8042 | ixgbe_release_hw_control(adapter); |
7a921c93 | 8043 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 8044 | err_sw_init: |
1cdd1ec8 GR |
8045 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
8046 | ixgbe_disable_sriov(adapter); | |
7086400d | 8047 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
8048 | iounmap(hw->hw_addr); |
8049 | err_ioremap: | |
8050 | free_netdev(netdev); | |
8051 | err_alloc_etherdev: | |
e8e9f696 JP |
8052 | pci_release_selected_regions(pdev, |
8053 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
8054 | err_pci_reg: |
8055 | err_dma: | |
8056 | pci_disable_device(pdev); | |
8057 | return err; | |
8058 | } | |
8059 | ||
8060 | /** | |
8061 | * ixgbe_remove - Device Removal Routine | |
8062 | * @pdev: PCI device information struct | |
8063 | * | |
8064 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
8065 | * that it should release a PCI device. The could be caused by a | |
8066 | * Hot-Plug event, or because the driver is going to be removed from | |
8067 | * memory. | |
8068 | **/ | |
8069 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
8070 | { | |
c60fbb00 AD |
8071 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
8072 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
8073 | |
8074 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 8075 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 8076 | |
5dd2d332 | 8077 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
8078 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
8079 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
8080 | dca_remove_requester(&pdev->dev); | |
8081 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
8082 | } | |
8083 | ||
8084 | #endif | |
332d4a7d YZ |
8085 | #ifdef IXGBE_FCOE |
8086 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
8087 | ixgbe_cleanup_fcoe(adapter); | |
8088 | ||
8089 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
8090 | |
8091 | /* remove the added san mac */ | |
8092 | ixgbe_del_sanmac_netdev(netdev); | |
8093 | ||
c4900be0 DS |
8094 | if (netdev->reg_state == NETREG_REGISTERED) |
8095 | unregister_netdev(netdev); | |
9a799d71 | 8096 | |
c6bda30a GR |
8097 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
8098 | if (!(ixgbe_check_vf_assignment(adapter))) | |
8099 | ixgbe_disable_sriov(adapter); | |
8100 | else | |
8101 | e_dev_warn("Unloading driver while VFs are assigned " | |
8102 | "- VFs will not be deallocated\n"); | |
8103 | } | |
1cdd1ec8 | 8104 | |
7a921c93 | 8105 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 8106 | |
021230d4 | 8107 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
8108 | |
8109 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 8110 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 8111 | IORESOURCE_MEM)); |
9a799d71 | 8112 | |
849c4542 | 8113 | e_dev_info("complete\n"); |
021230d4 | 8114 | |
9a799d71 AK |
8115 | free_netdev(netdev); |
8116 | ||
19d5afd4 | 8117 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 8118 | |
9a799d71 AK |
8119 | pci_disable_device(pdev); |
8120 | } | |
8121 | ||
8122 | /** | |
8123 | * ixgbe_io_error_detected - called when PCI error is detected | |
8124 | * @pdev: Pointer to PCI device | |
8125 | * @state: The current pci connection state | |
8126 | * | |
8127 | * This function is called after a PCI bus error affecting | |
8128 | * this device has been detected. | |
8129 | */ | |
8130 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 8131 | pci_channel_state_t state) |
9a799d71 | 8132 | { |
c60fbb00 AD |
8133 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
8134 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 8135 | |
83c61fa9 GR |
8136 | #ifdef CONFIG_PCI_IOV |
8137 | struct pci_dev *bdev, *vfdev; | |
8138 | u32 dw0, dw1, dw2, dw3; | |
8139 | int vf, pos; | |
8140 | u16 req_id, pf_func; | |
8141 | ||
8142 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
8143 | adapter->num_vfs == 0) | |
8144 | goto skip_bad_vf_detection; | |
8145 | ||
8146 | bdev = pdev->bus->self; | |
8147 | while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT)) | |
8148 | bdev = bdev->bus->self; | |
8149 | ||
8150 | if (!bdev) | |
8151 | goto skip_bad_vf_detection; | |
8152 | ||
8153 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
8154 | if (!pos) | |
8155 | goto skip_bad_vf_detection; | |
8156 | ||
8157 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); | |
8158 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); | |
8159 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); | |
8160 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); | |
8161 | ||
8162 | req_id = dw1 >> 16; | |
8163 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
8164 | if (!(req_id & 0x0080)) | |
8165 | goto skip_bad_vf_detection; | |
8166 | ||
8167 | pf_func = req_id & 0x01; | |
8168 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
8169 | unsigned int device_id; | |
8170 | ||
8171 | vf = (req_id & 0x7F) >> 1; | |
8172 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
8173 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
8174 | "%8.8x\tdw3: %8.8x\n", | |
8175 | dw0, dw1, dw2, dw3); | |
8176 | switch (adapter->hw.mac.type) { | |
8177 | case ixgbe_mac_82599EB: | |
8178 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
8179 | break; | |
8180 | case ixgbe_mac_X540: | |
8181 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
8182 | break; | |
8183 | default: | |
8184 | device_id = 0; | |
8185 | break; | |
8186 | } | |
8187 | ||
8188 | /* Find the pci device of the offending VF */ | |
8189 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL); | |
8190 | while (vfdev) { | |
8191 | if (vfdev->devfn == (req_id & 0xFF)) | |
8192 | break; | |
8193 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, | |
8194 | device_id, vfdev); | |
8195 | } | |
8196 | /* | |
8197 | * There's a slim chance the VF could have been hot plugged, | |
8198 | * so if it is no longer present we don't need to issue the | |
8199 | * VFLR. Just clean up the AER in that case. | |
8200 | */ | |
8201 | if (vfdev) { | |
8202 | e_dev_err("Issuing VFLR to VF %d\n", vf); | |
8203 | pci_write_config_dword(vfdev, 0xA8, 0x00008000); | |
8204 | } | |
8205 | ||
8206 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
8207 | } | |
8208 | ||
8209 | /* | |
8210 | * Even though the error may have occurred on the other port | |
8211 | * we still need to increment the vf error reference count for | |
8212 | * both ports because the I/O resume function will be called | |
8213 | * for both of them. | |
8214 | */ | |
8215 | adapter->vferr_refcount++; | |
8216 | ||
8217 | return PCI_ERS_RESULT_RECOVERED; | |
8218 | ||
8219 | skip_bad_vf_detection: | |
8220 | #endif /* CONFIG_PCI_IOV */ | |
9a799d71 AK |
8221 | netif_device_detach(netdev); |
8222 | ||
3044b8d1 BL |
8223 | if (state == pci_channel_io_perm_failure) |
8224 | return PCI_ERS_RESULT_DISCONNECT; | |
8225 | ||
9a799d71 AK |
8226 | if (netif_running(netdev)) |
8227 | ixgbe_down(adapter); | |
8228 | pci_disable_device(pdev); | |
8229 | ||
b4617240 | 8230 | /* Request a slot reset. */ |
9a799d71 AK |
8231 | return PCI_ERS_RESULT_NEED_RESET; |
8232 | } | |
8233 | ||
8234 | /** | |
8235 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
8236 | * @pdev: Pointer to PCI device | |
8237 | * | |
8238 | * Restart the card from scratch, as if from a cold-boot. | |
8239 | */ | |
8240 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
8241 | { | |
c60fbb00 | 8242 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
8243 | pci_ers_result_t result; |
8244 | int err; | |
9a799d71 | 8245 | |
9ce77666 | 8246 | if (pci_enable_device_mem(pdev)) { |
396e799c | 8247 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
8248 | result = PCI_ERS_RESULT_DISCONNECT; |
8249 | } else { | |
8250 | pci_set_master(pdev); | |
8251 | pci_restore_state(pdev); | |
c0e1f68b | 8252 | pci_save_state(pdev); |
9a799d71 | 8253 | |
dd4d8ca6 | 8254 | pci_wake_from_d3(pdev, false); |
9a799d71 | 8255 | |
6fabd715 | 8256 | ixgbe_reset(adapter); |
88512539 | 8257 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
8258 | result = PCI_ERS_RESULT_RECOVERED; |
8259 | } | |
8260 | ||
8261 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
8262 | if (err) { | |
849c4542 ET |
8263 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
8264 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
8265 | /* non-fatal, continue */ |
8266 | } | |
9a799d71 | 8267 | |
6fabd715 | 8268 | return result; |
9a799d71 AK |
8269 | } |
8270 | ||
8271 | /** | |
8272 | * ixgbe_io_resume - called when traffic can start flowing again. | |
8273 | * @pdev: Pointer to PCI device | |
8274 | * | |
8275 | * This callback is called when the error recovery driver tells us that | |
8276 | * its OK to resume normal operation. | |
8277 | */ | |
8278 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
8279 | { | |
c60fbb00 AD |
8280 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
8281 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 8282 | |
83c61fa9 GR |
8283 | #ifdef CONFIG_PCI_IOV |
8284 | if (adapter->vferr_refcount) { | |
8285 | e_info(drv, "Resuming after VF err\n"); | |
8286 | adapter->vferr_refcount--; | |
8287 | return; | |
8288 | } | |
8289 | ||
8290 | #endif | |
c7ccde0f AD |
8291 | if (netif_running(netdev)) |
8292 | ixgbe_up(adapter); | |
9a799d71 AK |
8293 | |
8294 | netif_device_attach(netdev); | |
9a799d71 AK |
8295 | } |
8296 | ||
8297 | static struct pci_error_handlers ixgbe_err_handler = { | |
8298 | .error_detected = ixgbe_io_error_detected, | |
8299 | .slot_reset = ixgbe_io_slot_reset, | |
8300 | .resume = ixgbe_io_resume, | |
8301 | }; | |
8302 | ||
8303 | static struct pci_driver ixgbe_driver = { | |
8304 | .name = ixgbe_driver_name, | |
8305 | .id_table = ixgbe_pci_tbl, | |
8306 | .probe = ixgbe_probe, | |
8307 | .remove = __devexit_p(ixgbe_remove), | |
8308 | #ifdef CONFIG_PM | |
8309 | .suspend = ixgbe_suspend, | |
8310 | .resume = ixgbe_resume, | |
8311 | #endif | |
8312 | .shutdown = ixgbe_shutdown, | |
8313 | .err_handler = &ixgbe_err_handler | |
8314 | }; | |
8315 | ||
8316 | /** | |
8317 | * ixgbe_init_module - Driver Registration Routine | |
8318 | * | |
8319 | * ixgbe_init_module is the first routine called when the driver is | |
8320 | * loaded. All it does is register with the PCI subsystem. | |
8321 | **/ | |
8322 | static int __init ixgbe_init_module(void) | |
8323 | { | |
8324 | int ret; | |
c7689578 | 8325 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 8326 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 8327 | |
5dd2d332 | 8328 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 8329 | dca_register_notify(&dca_notifier); |
bd0362dd | 8330 | #endif |
5dd2d332 | 8331 | |
9a799d71 AK |
8332 | ret = pci_register_driver(&ixgbe_driver); |
8333 | return ret; | |
8334 | } | |
b4617240 | 8335 | |
9a799d71 AK |
8336 | module_init(ixgbe_init_module); |
8337 | ||
8338 | /** | |
8339 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
8340 | * | |
8341 | * ixgbe_exit_module is called just before the driver is removed | |
8342 | * from memory. | |
8343 | **/ | |
8344 | static void __exit ixgbe_exit_module(void) | |
8345 | { | |
5dd2d332 | 8346 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
8347 | dca_unregister_notify(&dca_notifier); |
8348 | #endif | |
9a799d71 | 8349 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 8350 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 8351 | } |
bd0362dd | 8352 | |
5dd2d332 | 8353 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 8354 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 8355 | void *p) |
bd0362dd JC |
8356 | { |
8357 | int ret_val; | |
8358 | ||
8359 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 8360 | __ixgbe_notify_dca); |
bd0362dd JC |
8361 | |
8362 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
8363 | } | |
b453368d | 8364 | |
5dd2d332 | 8365 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 8366 | |
9a799d71 AK |
8367 | module_exit(ixgbe_exit_module); |
8368 | ||
8369 | /* ixgbe_main.c */ |