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ixgbe: cleanup logic in ixgbe_change_mtu
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
ea81875a
NP		 58char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
75e3d3c6 60#define MAJ 3
19d478bb
DS		 61#define MIN 6
62#define BUILD 7
75e3d3c6 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 64 __stringify(BUILD) "-k"
9c8eb720 65const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 66static const char ixgbe_copyright[] =
94971820 67 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 68
69static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 70 [board_82598] = &ixgbe_82598_info,
e8e26350 71 [board_82599] = &ixgbe_82599_info,
fe15e8e1 72 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 73};
74
75/* ixgbe_pci_tbl - PCI Device ID Table
76 *
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
79 *
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
82 */
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
1cdd1ec8
GR		 127#ifdef CONFIG_PCI_IOV
128static unsigned int max_vfs;
129module_param(max_vfs, uint, 0);
e8e9f696
JP		 130MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 132#endif /* CONFIG_PCI_IOV */
133
8ef78adc
PWJ		 134static unsigned int allow_unsupported_sfp;
135module_param(allow_unsupported_sfp, uint, 0);
136MODULE_PARM_DESC(allow_unsupported_sfp,
137 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
138
9a799d71
AK		 139MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_VERSION);
143
144#define DEFAULT_DEBUG_LEVEL_SHIFT 3
145
7086400d
AD		 146static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
147{
148 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
149 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
150 schedule_work(&adapter->service_task);
151}
152
153static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
154{
155 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
156
52f33af8 157 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 158 smp_mb__before_clear_bit();
159 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
160}
161
dcd79aeb
TI		 162struct ixgbe_reg_info {
163 u32 ofs;
164 char *name;
165};
166
167static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
168
169 /* General Registers */
170 {IXGBE_CTRL, "CTRL"},
171 {IXGBE_STATUS, "STATUS"},
172 {IXGBE_CTRL_EXT, "CTRL_EXT"},
173
174 /* Interrupt Registers */
175 {IXGBE_EICR, "EICR"},
176
177 /* RX Registers */
178 {IXGBE_SRRCTL(0), "SRRCTL"},
179 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
180 {IXGBE_RDLEN(0), "RDLEN"},
181 {IXGBE_RDH(0), "RDH"},
182 {IXGBE_RDT(0), "RDT"},
183 {IXGBE_RXDCTL(0), "RXDCTL"},
184 {IXGBE_RDBAL(0), "RDBAL"},
185 {IXGBE_RDBAH(0), "RDBAH"},
186
187 /* TX Registers */
188 {IXGBE_TDBAL(0), "TDBAL"},
189 {IXGBE_TDBAH(0), "TDBAH"},
190 {IXGBE_TDLEN(0), "TDLEN"},
191 {IXGBE_TDH(0), "TDH"},
192 {IXGBE_TDT(0), "TDT"},
193 {IXGBE_TXDCTL(0), "TXDCTL"},
194
195 /* List Terminator */
196 {}
197};
198
199
200/*
201 * ixgbe_regdump - register printout routine
202 */
203static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
204{
205 int i = 0, j = 0;
206 char rname[16];
207 u32 regs[64];
208
209 switch (reginfo->ofs) {
210 case IXGBE_SRRCTL(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
213 break;
214 case IXGBE_DCA_RXCTRL(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
217 break;
218 case IXGBE_RDLEN(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
221 break;
222 case IXGBE_RDH(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
225 break;
226 case IXGBE_RDT(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
229 break;
230 case IXGBE_RXDCTL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
233 break;
234 case IXGBE_RDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
237 break;
238 case IXGBE_RDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
241 break;
242 case IXGBE_TDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
245 break;
246 case IXGBE_TDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
249 break;
250 case IXGBE_TDLEN(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
253 break;
254 case IXGBE_TDH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
257 break;
258 case IXGBE_TDT(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
261 break;
262 case IXGBE_TXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
265 break;
266 default:
c7689578 267 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 268 IXGBE_READ_REG(hw, reginfo->ofs));
269 return;
270 }
271
272 for (i = 0; i < 8; i++) {
273 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 274 pr_err("%-15s", rname);
dcd79aeb 275 for (j = 0; j < 8; j++)
c7689578
JP		 276 pr_cont(" %08x", regs[i*8+j]);
277 pr_cont("\n");
dcd79aeb
TI		 278 }
279
280}
281
282/*
283 * ixgbe_dump - Print registers, tx-rings and rx-rings
284 */
285static void ixgbe_dump(struct ixgbe_adapter *adapter)
286{
287 struct net_device *netdev = adapter->netdev;
288 struct ixgbe_hw *hw = &adapter->hw;
289 struct ixgbe_reg_info *reginfo;
290 int n = 0;
291 struct ixgbe_ring *tx_ring;
292 struct ixgbe_tx_buffer *tx_buffer_info;
293 union ixgbe_adv_tx_desc *tx_desc;
294 struct my_u0 { u64 a; u64 b; } *u0;
295 struct ixgbe_ring *rx_ring;
296 union ixgbe_adv_rx_desc *rx_desc;
297 struct ixgbe_rx_buffer *rx_buffer_info;
298 u32 staterr;
299 int i = 0;
300
301 if (!netif_msg_hw(adapter))
302 return;
303
304 /* Print netdevice Info */
305 if (netdev) {
306 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 307 pr_info("Device Name state "
dcd79aeb 308 "trans_start last_rx\n");
c7689578
JP		 309 pr_info("%-15s %016lX %016lX %016lX\n",
310 netdev->name,
311 netdev->state,
312 netdev->trans_start,
313 netdev->last_rx);
dcd79aeb
TI		 314 }
315
316 /* Print Registers */
317 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 318 pr_info(" Register Name Value\n");
dcd79aeb
TI		 319 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
320 reginfo->name; reginfo++) {
321 ixgbe_regdump(hw, reginfo);
322 }
323
324 /* Print TX Ring Summary */
325 if (!netdev || !netif_running(netdev))
326 goto exit;
327
328 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 329 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 330 for (n = 0; n < adapter->num_tx_queues; n++) {
331 tx_ring = adapter->tx_ring[n];
332 tx_buffer_info =
333 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 334 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 335 n, tx_ring->next_to_use, tx_ring->next_to_clean,
336 (u64)tx_buffer_info->dma,
337 tx_buffer_info->length,
338 tx_buffer_info->next_to_watch,
339 (u64)tx_buffer_info->time_stamp);
340 }
341
342 /* Print TX Rings */
343 if (!netif_msg_tx_done(adapter))
344 goto rx_ring_summary;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
347
348 /* Transmit Descriptor Formats
349 *
350 * Advanced Transmit Descriptor
351 * +--------------------------------------------------------------+
352 * 0 | Buffer Address [63:0] |
353 * +--------------------------------------------------------------+
354 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
355 * +--------------------------------------------------------------+
356 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
357 */
358
359 for (n = 0; n < adapter->num_tx_queues; n++) {
360 tx_ring = adapter->tx_ring[n];
c7689578
JP		 361 pr_info("------------------------------------\n");
362 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
363 pr_info("------------------------------------\n");
364 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 365 "[PlPOIdStDDt Ln] [bi->dma ] "
366 "leng ntw timestamp bi->skb\n");
367
368 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 369 tx_desc = IXGBE_TX_DESC(tx_ring, i);
dcd79aeb
TI		 370 tx_buffer_info = &tx_ring->tx_buffer_info[i];
371 u0 = (struct my_u0 *)tx_desc;
c7689578 372 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 373 " %04X %p %016llX %p", i,
dcd79aeb
TI		 374 le64_to_cpu(u0->a),
375 le64_to_cpu(u0->b),
376 (u64)tx_buffer_info->dma,
377 tx_buffer_info->length,
378 tx_buffer_info->next_to_watch,
379 (u64)tx_buffer_info->time_stamp,
380 tx_buffer_info->skb);
381 if (i == tx_ring->next_to_use &&
382 i == tx_ring->next_to_clean)
c7689578 383 pr_cont(" NTC/U\n");
dcd79aeb 384 else if (i == tx_ring->next_to_use)
c7689578 385 pr_cont(" NTU\n");
dcd79aeb 386 else if (i == tx_ring->next_to_clean)
c7689578 387 pr_cont(" NTC\n");
dcd79aeb 388 else
c7689578 389 pr_cont("\n");
dcd79aeb
TI		 390
391 if (netif_msg_pktdata(adapter) &&
392 tx_buffer_info->dma != 0)
393 print_hex_dump(KERN_INFO, "",
394 DUMP_PREFIX_ADDRESS, 16, 1,
395 phys_to_virt(tx_buffer_info->dma),
396 tx_buffer_info->length, true);
397 }
398 }
399
400 /* Print RX Rings Summary */
401rx_ring_summary:
402 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 403 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 404 for (n = 0; n < adapter->num_rx_queues; n++) {
405 rx_ring = adapter->rx_ring[n];
c7689578
JP		 406 pr_info("%5d %5X %5X\n",
407 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 408 }
409
410 /* Print RX Rings */
411 if (!netif_msg_rx_status(adapter))
412 goto exit;
413
414 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
415
416 /* Advanced Receive Descriptor (Read) Format
417 * 63 1 0
418 * +-----------------------------------------------------+
419 * 0 | Packet Buffer Address [63:1] |A0/NSE|
420 * +----------------------------------------------+------+
421 * 8 | Header Buffer Address [63:1] | DD |
422 * +-----------------------------------------------------+
423 *
424 *
425 * Advanced Receive Descriptor (Write-Back) Format
426 *
427 * 63 48 47 32 31 30 21 20 16 15 4 3 0
428 * +------------------------------------------------------+
429 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
430 * | Checksum Ident | | | | Type | Type |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
435 */
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 442 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
443 "<-- Adv Rx Read format\n");
c7689578 444 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 445 "[vl er S cks ln] ---------------- [bi->skb] "
446 "<-- Adv Rx Write-Back format\n");
447
448 for (i = 0; i < rx_ring->count; i++) {
449 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 450 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 451 u0 = (struct my_u0 *)rx_desc;
452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
453 if (staterr & IXGBE_RXD_STAT_DD) {
454 /* Descriptor Done */
c7689578 455 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 456 "%016llX ---------------- %p", i,
457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
459 rx_buffer_info->skb);
460 } else {
c7689578 461 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 462 "%016llX %016llX %p", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)rx_buffer_info->dma,
466 rx_buffer_info->skb);
467
468 if (netif_msg_pktdata(adapter)) {
469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(rx_buffer_info->dma),
f800326d 472 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 473 }
474 }
475
476 if (i == rx_ring->next_to_use)
c7689578 477 pr_cont(" NTU\n");
dcd79aeb 478 else if (i == rx_ring->next_to_clean)
c7689578 479 pr_cont(" NTC\n");
dcd79aeb 480 else
c7689578 481 pr_cont("\n");
dcd79aeb
TI		 482
483 }
484 }
485
486exit:
487 return;
488}
489
5eba3699
AV		 490static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
491{
492 u32 ctrl_ext;
493
494 /* Let firmware take over control of h/w */
495 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
496 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 497 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 498}
499
500static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware know the driver has taken over */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 508}
9a799d71 509
e8e26350
PW		 510/*
511 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
512 * @adapter: pointer to adapter struct
513 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
514 * @queue: queue to map the corresponding interrupt to
515 * @msix_vector: the vector to map to the corresponding queue
516 *
517 */
518static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 519 u8 queue, u8 msix_vector)
9a799d71
AK		 520{
521 u32 ivar, index;
e8e26350
PW		 522 struct ixgbe_hw *hw = &adapter->hw;
523 switch (hw->mac.type) {
524 case ixgbe_mac_82598EB:
525 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
526 if (direction == -1)
527 direction = 0;
528 index = (((direction * 64) + queue) >> 2) & 0x1F;
529 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
530 ivar &= ~(0xFF << (8 * (queue & 0x3)));
531 ivar |= (msix_vector << (8 * (queue & 0x3)));
532 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
533 break;
534 case ixgbe_mac_82599EB:
b93a2226 535 case ixgbe_mac_X540:
e8e26350
PW		 536 if (direction == -1) {
537 /* other causes */
538 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
539 index = ((queue & 1) * 8);
540 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
541 ivar &= ~(0xFF << index);
542 ivar |= (msix_vector << index);
543 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
544 break;
545 } else {
546 /* tx or rx causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((16 * (queue & 1)) + (8 * direction));
549 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
553 break;
554 }
555 default:
556 break;
557 }
9a799d71
AK		 558}
559
fe49f04a 560static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 561 u64 qmask)
fe49f04a
AD		 562{
563 u32 mask;
564
bd508178
AD		 565 switch (adapter->hw.mac.type) {
566 case ixgbe_mac_82598EB:
fe49f04a
AD		 567 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 569 break;
570 case ixgbe_mac_82599EB:
b93a2226 571 case ixgbe_mac_X540:
fe49f04a
AD		 572 mask = (qmask & 0xFFFFFFFF);
573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
574 mask = (qmask >> 32);
575 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 576 break;
577 default:
578 break;
fe49f04a
AD		 579 }
580}
581
d3d00239
AD		 582static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
583 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 584{
d3d00239
AD		 585 if (tx_buffer->dma) {
586 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
587 dma_unmap_page(ring->dev,
588 tx_buffer->dma,
589 tx_buffer->length,
590 DMA_TO_DEVICE);
e5a43549 591 else
d3d00239
AD		 592 dma_unmap_single(ring->dev,
593 tx_buffer->dma,
594 tx_buffer->length,
595 DMA_TO_DEVICE);
e5a43549 596 }
d3d00239
AD		 597 tx_buffer->dma = 0;
598}
599
600void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
601 struct ixgbe_tx_buffer *tx_buffer_info)
602{
603 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
604 if (tx_buffer_info->skb)
9a799d71 605 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 606 tx_buffer_info->skb = NULL;
9a799d71
AK		 607 /* tx_buffer_info must be completely set up in the transmit path */
608}
609
c84d324c
JF		 610static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
611{
612 struct ixgbe_hw *hw = &adapter->hw;
613 struct ixgbe_hw_stats *hwstats = &adapter->stats;
614 u32 data = 0;
615 u32 xoff[8] = {0};
616 int i;
617
618 if ((hw->fc.current_mode == ixgbe_fc_full) ||
619 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
620 switch (hw->mac.type) {
621 case ixgbe_mac_82598EB:
622 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 623 break;
624 default:
c84d324c
JF		 625 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
626 }
627 hwstats->lxoffrxc += data;
628
629 /* refill credits (no tx hang) if we received xoff */
630 if (!data)
631 return;
632
633 for (i = 0; i < adapter->num_tx_queues; i++)
634 clear_bit(__IXGBE_HANG_CHECK_ARMED,
635 &adapter->tx_ring[i]->state);
636 return;
637 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
638 return;
639
640 /* update stats for each tc, only valid with PFC enabled */
641 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
642 switch (hw->mac.type) {
643 case ixgbe_mac_82598EB:
644 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 645 break;
c84d324c
JF		 646 default:
647 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 648 }
c84d324c
JF		 649 hwstats->pxoffrxc[i] += xoff[i];
650 }
651
652 /* disarm tx queues that have received xoff frames */
653 for (i = 0; i < adapter->num_tx_queues; i++) {
654 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 655 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 656
657 if (xoff[tc])
658 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 659 }
26f23d82
YZ		 660}
661
c84d324c 662static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 663{
c84d324c
JF		 664 return ring->tx_stats.completed;
665}
666
667static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
668{
669 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 670 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 671
c84d324c
JF		 672 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
673 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
674
675 if (head != tail)
676 return (head < tail) ?
677 tail - head : (tail + ring->count - head);
678
679 return 0;
680}
681
682static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
683{
684 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
685 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
686 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
687 bool ret = false;
688
7d637bcc 689 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 690
691 /*
692 * Check for a hung queue, but be thorough. This verifies
693 * that a transmit has been completed since the previous
694 * check AND there is at least one packet pending. The
695 * ARMED bit is set to indicate a potential hang. The
696 * bit is cleared if a pause frame is received to remove
697 * false hang detection due to PFC or 802.3x frames. By
698 * requiring this to fail twice we avoid races with
699 * pfc clearing the ARMED bit and conditions where we
700 * run the check_tx_hang logic with a transmit completion
701 * pending but without time to complete it yet.
702 */
703 if ((tx_done_old == tx_done) && tx_pending) {
704 /* make sure it is true for two checks in a row */
705 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
706 &tx_ring->state);
707 } else {
708 /* update completed stats and continue */
709 tx_ring->tx_stats.tx_done_old = tx_done;
710 /* reset the countdown */
711 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 712 }
713
c84d324c 714 return ret;
9a799d71
AK		 715}
716
c83c6cbd
AD		 717/**
718 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
719 * @adapter: driver private struct
720 **/
721static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
722{
723
724 /* Do the reset outside of interrupt context */
725 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
726 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
727 ixgbe_service_event_schedule(adapter);
728 }
729}
e01c31a5 730
9a799d71
AK		 731/**
732 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 733 * @q_vector: structure containing interrupt and ring information
e01c31a5 734 * @tx_ring: tx ring to clean
9a799d71 735 **/
fe49f04a 736static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 737 struct ixgbe_ring *tx_ring)
9a799d71 738{
fe49f04a 739 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 740 struct ixgbe_tx_buffer *tx_buffer;
741 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 742 unsigned int total_bytes = 0, total_packets = 0;
59224555 743 unsigned int budget = q_vector->tx.work_limit;
d3d00239 744 u16 i = tx_ring->next_to_clean;
9a799d71 745
d3d00239 746 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 747 tx_desc = IXGBE_TX_DESC(tx_ring, i);
12207e49 748
30065e63 749 for (; budget; budget--) {
d3d00239
AD		 750 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
751
752 /* if next_to_watch is not set then there is no work pending */
753 if (!eop_desc)
754 break;
755
7f83a9e6
AD		 756 /* prevent any other reads prior to eop_desc */
757 rmb();
758
d3d00239
AD		 759 /* if DD is not set pending work has not been completed */
760 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
761 break;
8ad494b0 762
d3d00239
AD		 763 /* count the packet as being completed */
764 tx_ring->tx_stats.completed++;
765
766 /* clear next_to_watch to prevent false hangs */
767 tx_buffer->next_to_watch = NULL;
8ad494b0 768
d3d00239
AD		 769 do {
770 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
d3d00239
AD		 771 if (likely(tx_desc == eop_desc)) {
772 eop_desc = NULL;
773 dev_kfree_skb_any(tx_buffer->skb);
774 tx_buffer->skb = NULL;
775
776 total_bytes += tx_buffer->bytecount;
777 total_packets += tx_buffer->gso_segs;
778 }
9a799d71 779
d3d00239
AD		 780 tx_buffer++;
781 tx_desc++;
8ad494b0 782 i++;
d3d00239 783 if (unlikely(i == tx_ring->count)) {
8ad494b0 784 i = 0;
e01c31a5 785
d3d00239 786 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 787 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 788 }
e01c31a5 789
d3d00239 790 } while (eop_desc);
12207e49
PWJ		 791 }
792
9a799d71 793 tx_ring->next_to_clean = i;
d3d00239 794 u64_stats_update_begin(&tx_ring->syncp);
b953799e 795 tx_ring->stats.bytes += total_bytes;
bd198058 796 tx_ring->stats.packets += total_packets;
d3d00239 797 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 798 q_vector->tx.total_bytes += total_bytes;
799 q_vector->tx.total_packets += total_packets;
b953799e 800
c84d324c
JF		 801 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
802 /* schedule immediate reset if we believe we hung */
803 struct ixgbe_hw *hw = &adapter->hw;
e4f74028 804 tx_desc = IXGBE_TX_DESC(tx_ring, i);
c84d324c
JF		 805 e_err(drv, "Detected Tx Unit Hang\n"
806 " Tx Queue <%d>\n"
807 " TDH, TDT <%x>, <%x>\n"
808 " next_to_use <%x>\n"
809 " next_to_clean <%x>\n"
810 "tx_buffer_info[next_to_clean]\n"
811 " time_stamp <%lx>\n"
812 " jiffies <%lx>\n",
813 tx_ring->queue_index,
814 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
815 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 816 tx_ring->next_to_use, i,
817 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 818
819 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
820
821 e_info(probe,
822 "tx hang %d detected on queue %d, resetting adapter\n",
823 adapter->tx_timeout_count + 1, tx_ring->queue_index);
824
b953799e 825 /* schedule immediate reset if we believe we hung */
c83c6cbd 826 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 827
828 /* the adapter is about to reset, no point in enabling stuff */
59224555 829 return true;
b953799e 830 }
9a799d71 831
b2d96e0a
AD		 832 netdev_tx_completed_queue(txring_txq(tx_ring),
833 total_packets, total_bytes);
834
e092be60 835#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 836 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 837 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 838 /* Make sure that anybody stopping the queue after this
839 * sees the new next_to_clean.
840 */
841 smp_mb();
fc77dc3c 842 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 843 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 844 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 845 ++tx_ring->tx_stats.restart_queue;
30eba97a 846 }
e092be60 847 }
9a799d71 848
59224555 849 return !!budget;
9a799d71
AK		 850}
851
5dd2d332 852#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 853static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
854 struct ixgbe_ring *tx_ring,
33cf09c9 855 int cpu)
bd0362dd 856{
33cf09c9 857 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 858 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
859 u16 reg_offset;
33cf09c9 860
33cf09c9
AD		 861 switch (hw->mac.type) {
862 case ixgbe_mac_82598EB:
bdda1a61 863 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 864 break;
865 case ixgbe_mac_82599EB:
b93a2226 866 case ixgbe_mac_X540:
bdda1a61
AD		 867 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
868 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 869 break;
870 default:
bdda1a61
AD		 871 /* for unknown hardware do not write register */
872 return;
bd0362dd 873 }
bdda1a61
AD		 874
875 /*
876 * We can enable relaxed ordering for reads, but not writes when
877 * DCA is enabled. This is due to a known issue in some chipsets
878 * which will cause the DCA tag to be cleared.
879 */
880 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
881 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
882 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883
884 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 885}
886
bdda1a61
AD		 887static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
888 struct ixgbe_ring *rx_ring,
33cf09c9 889 int cpu)
bd0362dd 890{
33cf09c9 891 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 892 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
893 u8 reg_idx = rx_ring->reg_idx;
894
33cf09c9
AD		 895
896 switch (hw->mac.type) {
33cf09c9 897 case ixgbe_mac_82599EB:
b93a2226 898 case ixgbe_mac_X540:
bdda1a61 899 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 900 break;
901 default:
902 break;
903 }
bdda1a61
AD		 904
905 /*
906 * We can enable relaxed ordering for reads, but not writes when
907 * DCA is enabled. This is due to a known issue in some chipsets
908 * which will cause the DCA tag to be cleared.
909 */
910 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
911 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
912 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
913
914 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 915}
916
917static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
918{
919 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 920 struct ixgbe_ring *ring;
bd0362dd 921 int cpu = get_cpu();
bd0362dd 922
33cf09c9
AD		 923 if (q_vector->cpu == cpu)
924 goto out_no_update;
925
a557928e 926 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 927 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 928
a557928e 929 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 930 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 931
932 q_vector->cpu = cpu;
933out_no_update:
bd0362dd
JC		 934 put_cpu();
935}
936
937static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
938{
33cf09c9 939 int num_q_vectors;
bd0362dd
JC		 940 int i;
941
942 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
943 return;
944
e35ec126
AD		 945 /* always use CB2 mode, difference is masked in the CB driver */
946 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
947
33cf09c9
AD		 948 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
949 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
950 else
951 num_q_vectors = 1;
952
953 for (i = 0; i < num_q_vectors; i++) {
954 adapter->q_vector[i]->cpu = -1;
955 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 956 }
957}
958
959static int __ixgbe_notify_dca(struct device *dev, void *data)
960{
c60fbb00 961 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 962 unsigned long event = *(unsigned long *)data;
963
2a72c31e 964 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 965 return 0;
966
bd0362dd
JC		 967 switch (event) {
968 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 969 /* if we're already enabled, don't do it again */
970 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
971 break;
652f093f 972 if (dca_add_requester(dev) == 0) {
96b0e0f6 973 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 974 ixgbe_setup_dca(adapter);
975 break;
976 }
977 /* Fall Through since DCA is disabled. */
978 case DCA_PROVIDER_REMOVE:
979 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
980 dca_remove_requester(dev);
981 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
982 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
983 }
984 break;
985 }
986
652f093f 987 return 0;
bd0362dd 988}
67a74ee2 989
bdda1a61 990#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 991static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
992 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 993 struct sk_buff *skb)
994{
8a0da21b
AD		 995 if (ring->netdev->features & NETIF_F_RXHASH)
996 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 997}
998
f800326d 999#ifdef IXGBE_FCOE
ff886dfc
AD		 1000/**
1001 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1002 * @adapter: address of board private structure
1003 * @rx_desc: advanced rx descriptor
1004 *
1005 * Returns : true if it is FCoE pkt
1006 */
1007static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1008 union ixgbe_adv_rx_desc *rx_desc)
1009{
1010 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1011
1012 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1013 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1014 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1015 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1016}
1017
f800326d 1018#endif /* IXGBE_FCOE */
e59bd25d
AV		 1019/**
1020 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1021 * @ring: structure containing ring specific data
1022 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1023 * @skb: skb currently being received and modified
1024 **/
8a0da21b 1025static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1026 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1027 struct sk_buff *skb)
9a799d71 1028{
8a0da21b 1029 skb_checksum_none_assert(skb);
9a799d71 1030
712744be 1031 /* Rx csum disabled */
8a0da21b 1032 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1033 return;
e59bd25d
AV		 1034
1035 /* if IP and error */
f56e0cb1
AD		 1036 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1037 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1038 ring->rx_stats.csum_err++;
9a799d71
AK		 1039 return;
1040 }
e59bd25d 1041
f56e0cb1 1042 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1043 return;
1044
f56e0cb1 1045 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1046 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1047
1048 /*
1049 * 82599 errata, UDP frames with a 0 checksum can be marked as
1050 * checksum errors.
1051 */
8a0da21b
AD		 1052 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1053 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1054 return;
1055
8a0da21b 1056 ring->rx_stats.csum_err++;
e59bd25d
AV		 1057 return;
1058 }
1059
9a799d71 1060 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1061 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1062}
1063
84ea2591 1064static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1065{
f56e0cb1 1066 rx_ring->next_to_use = val;
f800326d
AD		 1067
1068 /* update next to alloc since we have filled the ring */
1069 rx_ring->next_to_alloc = val;
e8e26350
PW		 1070 /*
1071 * Force memory writes to complete before letting h/w
1072 * know there are new descriptors to fetch. (Only
1073 * applicable for weak-ordered memory model archs,
1074 * such as IA-64).
1075 */
1076 wmb();
84ea2591 1077 writel(val, rx_ring->tail);
e8e26350
PW		 1078}
1079
f990b79b
AD		 1080static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1081 struct ixgbe_rx_buffer *bi)
1082{
1083 struct page *page = bi->page;
f800326d 1084 dma_addr_t dma = bi->dma;
f990b79b 1085
f800326d
AD		 1086 /* since we are recycling buffers we should seldom need to alloc */
1087 if (likely(dma))
f990b79b
AD		 1088 return true;
1089
f800326d
AD		 1090 /* alloc new page for storage */
1091 if (likely(!page)) {
1092 page = alloc_pages(GFP_ATOMIC | __GFP_COLD,
1093 ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1094 if (unlikely(!page)) {
1095 rx_ring->rx_stats.alloc_rx_page_failed++;
1096 return false;
1097 }
f800326d 1098 bi->page = page;
f990b79b
AD		 1099 }
1100
f800326d
AD		 1101 /* map page for use */
1102 dma = dma_map_page(rx_ring->dev, page, 0,
1103 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1104
1105 /*
1106 * if mapping failed free memory back to system since
1107 * there isn't much point in holding memory we can't use
1108 */
1109 if (dma_mapping_error(rx_ring->dev, dma)) {
1110 put_page(page);
1111 bi->page = NULL;
f990b79b 1112
f990b79b
AD		 1113 rx_ring->rx_stats.alloc_rx_page_failed++;
1114 return false;
1115 }
1116
f800326d
AD		 1117 bi->dma = dma;
1118 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1119
f990b79b
AD		 1120 return true;
1121}
1122
9a799d71 1123/**
f990b79b 1124 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1125 * @rx_ring: ring to place buffers on
1126 * @cleaned_count: number of buffers to replace
9a799d71 1127 **/
fc77dc3c 1128void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1129{
9a799d71 1130 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1131 struct ixgbe_rx_buffer *bi;
d5f398ed 1132 u16 i = rx_ring->next_to_use;
9a799d71 1133
f800326d
AD		 1134 /* nothing to do */
1135 if (!cleaned_count)
fc77dc3c
AD		 1136 return;
1137
e4f74028 1138 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1139 bi = &rx_ring->rx_buffer_info[i];
1140 i -= rx_ring->count;
9a799d71 1141
f800326d
AD		 1142 do {
1143 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1144 break;
d5f398ed 1145
f800326d
AD		 1146 /*
1147 * Refresh the desc even if buffer_addrs didn't change
1148 * because each write-back erases this info.
1149 */
1150 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1151
f990b79b
AD		 1152 rx_desc++;
1153 bi++;
9a799d71 1154 i++;
f990b79b 1155 if (unlikely(!i)) {
e4f74028 1156 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1157 bi = rx_ring->rx_buffer_info;
1158 i -= rx_ring->count;
1159 }
1160
1161 /* clear the hdr_addr for the next_to_use descriptor */
1162 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1163
1164 cleaned_count--;
1165 } while (cleaned_count);
7c6e0a43 1166
f990b79b
AD		 1167 i += rx_ring->count;
1168
f56e0cb1 1169 if (rx_ring->next_to_use != i)
84ea2591 1170 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1171}
1172
1d2024f6
AD		 1173/**
1174 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1175 * @data: pointer to the start of the headers
1176 * @max_len: total length of section to find headers in
1177 *
1178 * This function is meant to determine the length of headers that will
1179 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1180 * motivation of doing this is to only perform one pull for IPv4 TCP
1181 * packets so that we can do basic things like calculating the gso_size
1182 * based on the average data per packet.
1183 **/
1184static unsigned int ixgbe_get_headlen(unsigned char *data,
1185 unsigned int max_len)
1186{
1187 union {
1188 unsigned char *network;
1189 /* l2 headers */
1190 struct ethhdr *eth;
1191 struct vlan_hdr *vlan;
1192 /* l3 headers */
1193 struct iphdr *ipv4;
1194 } hdr;
1195 __be16 protocol;
1196 u8 nexthdr = 0; /* default to not TCP */
1197 u8 hlen;
1198
1199 /* this should never happen, but better safe than sorry */
1200 if (max_len < ETH_HLEN)
1201 return max_len;
1202
1203 /* initialize network frame pointer */
1204 hdr.network = data;
1205
1206 /* set first protocol and move network header forward */
1207 protocol = hdr.eth->h_proto;
1208 hdr.network += ETH_HLEN;
1209
1210 /* handle any vlan tag if present */
1211 if (protocol == __constant_htons(ETH_P_8021Q)) {
1212 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1213 return max_len;
1214
1215 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1216 hdr.network += VLAN_HLEN;
1217 }
1218
1219 /* handle L3 protocols */
1220 if (protocol == __constant_htons(ETH_P_IP)) {
1221 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1222 return max_len;
1223
1224 /* access ihl as a u8 to avoid unaligned access on ia64 */
1225 hlen = (hdr.network[0] & 0x0F) << 2;
1226
1227 /* verify hlen meets minimum size requirements */
1228 if (hlen < sizeof(struct iphdr))
1229 return hdr.network - data;
1230
1231 /* record next protocol */
1232 nexthdr = hdr.ipv4->protocol;
1233 hdr.network += hlen;
f800326d 1234#ifdef IXGBE_FCOE
1d2024f6
AD		 1235 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1236 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1237 return max_len;
1238 hdr.network += FCOE_HEADER_LEN;
1239#endif
1240 } else {
1241 return hdr.network - data;
1242 }
1243
1244 /* finally sort out TCP */
1245 if (nexthdr == IPPROTO_TCP) {
1246 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1247 return max_len;
1248
1249 /* access doff as a u8 to avoid unaligned access on ia64 */
1250 hlen = (hdr.network[12] & 0xF0) >> 2;
1251
1252 /* verify hlen meets minimum size requirements */
1253 if (hlen < sizeof(struct tcphdr))
1254 return hdr.network - data;
1255
1256 hdr.network += hlen;
1257 }
1258
1259 /*
1260 * If everything has gone correctly hdr.network should be the
1261 * data section of the packet and will be the end of the header.
1262 * If not then it probably represents the end of the last recognized
1263 * header.
1264 */
1265 if ((hdr.network - data) < max_len)
1266 return hdr.network - data;
1267 else
1268 return max_len;
1269}
1270
4c1975d7
AD		 1271static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1272 union ixgbe_adv_rx_desc *rx_desc,
1273 struct sk_buff *skb)
aa80175a 1274{
4c1975d7
AD		 1275 __le32 rsc_enabled;
1276 u32 rsc_cnt;
1277
1278 if (!ring_is_rsc_enabled(rx_ring))
1279 return;
1280
1281 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1282 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1283
1284 /* If this is an RSC frame rsc_cnt should be non-zero */
1285 if (!rsc_enabled)
1286 return;
1287
1288 rsc_cnt = le32_to_cpu(rsc_enabled);
1289 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1290
1291 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1292}
43634e82 1293
1d2024f6
AD		 1294static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1295 struct sk_buff *skb)
1296{
f800326d 1297 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1298
1299 /* set gso_size to avoid messing up TCP MSS */
1300 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1301 IXGBE_CB(skb)->append_cnt);
1302}
1303
1304static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1305 struct sk_buff *skb)
1306{
1307 /* if append_cnt is 0 then frame is not RSC */
1308 if (!IXGBE_CB(skb)->append_cnt)
1309 return;
1310
1311 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1312 rx_ring->rx_stats.rsc_flush++;
1313
1314 ixgbe_set_rsc_gso_size(rx_ring, skb);
1315
1316 /* gso_size is computed using append_cnt so always clear it last */
1317 IXGBE_CB(skb)->append_cnt = 0;
1318}
1319
8a0da21b
AD		 1320/**
1321 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1322 * @rx_ring: rx descriptor ring packet is being transacted on
1323 * @rx_desc: pointer to the EOP Rx descriptor
1324 * @skb: pointer to current skb being populated
f8212f97 1325 *
8a0da21b
AD		 1326 * This function checks the ring, descriptor, and packet information in
1327 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1328 * other fields within the skb.
f8212f97 1329 **/
8a0da21b
AD		 1330static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1331 union ixgbe_adv_rx_desc *rx_desc,
1332 struct sk_buff *skb)
f8212f97 1333{
8a0da21b
AD		 1334 ixgbe_update_rsc_stats(rx_ring, skb);
1335
1336 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1337
8a0da21b
AD		 1338 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1339
1340 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1341 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1342 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1343 }
1344
8a0da21b 1345 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1346
8a0da21b 1347 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
f8212f97
AD		 1348}
1349
8a0da21b
AD		 1350static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1351 struct sk_buff *skb)
aa80175a 1352{
8a0da21b
AD		 1353 struct ixgbe_adapter *adapter = q_vector->adapter;
1354
1355 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1356 napi_gro_receive(&q_vector->napi, skb);
1357 else
1358 netif_rx(skb);
aa80175a 1359}
43634e82 1360
f800326d
AD		 1361/**
1362 * ixgbe_is_non_eop - process handling of non-EOP buffers
1363 * @rx_ring: Rx ring being processed
1364 * @rx_desc: Rx descriptor for current buffer
1365 * @skb: Current socket buffer containing buffer in progress
1366 *
1367 * This function updates next to clean. If the buffer is an EOP buffer
1368 * this function exits returning false, otherwise it will place the
1369 * sk_buff in the next buffer to be chained and return true indicating
1370 * that this is in fact a non-EOP buffer.
1371 **/
1372static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1373 union ixgbe_adv_rx_desc *rx_desc,
1374 struct sk_buff *skb)
1375{
1376 u32 ntc = rx_ring->next_to_clean + 1;
1377
1378 /* fetch, update, and store next to clean */
1379 ntc = (ntc < rx_ring->count) ? ntc : 0;
1380 rx_ring->next_to_clean = ntc;
1381
1382 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1383
1384 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1385 return false;
1386
1387 /* append_cnt indicates packet is RSC, if so fetch nextp */
1388 if (IXGBE_CB(skb)->append_cnt) {
1389 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1390 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1391 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1392 }
1393
1394 /* place skb in next buffer to be received */
1395 rx_ring->rx_buffer_info[ntc].skb = skb;
1396 rx_ring->rx_stats.non_eop_descs++;
1397
1398 return true;
1399}
1400
1401/**
1402 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1403 * @rx_ring: rx descriptor ring packet is being transacted on
1404 * @rx_desc: pointer to the EOP Rx descriptor
1405 * @skb: pointer to current skb being fixed
1406 *
1407 * Check for corrupted packet headers caused by senders on the local L2
1408 * embedded NIC switch not setting up their Tx Descriptors right. These
1409 * should be very rare.
1410 *
1411 * Also address the case where we are pulling data in on pages only
1412 * and as such no data is present in the skb header.
1413 *
1414 * In addition if skb is not at least 60 bytes we need to pad it so that
1415 * it is large enough to qualify as a valid Ethernet frame.
1416 *
1417 * Returns true if an error was encountered and skb was freed.
1418 **/
1419static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1420 union ixgbe_adv_rx_desc *rx_desc,
1421 struct sk_buff *skb)
1422{
1423 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1424 struct net_device *netdev = rx_ring->netdev;
1425 unsigned char *va;
1426 unsigned int pull_len;
1427
1428 /* if the page was released unmap it, else just sync our portion */
1429 if (unlikely(IXGBE_CB(skb)->page_released)) {
1430 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1431 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1432 IXGBE_CB(skb)->page_released = false;
1433 } else {
1434 dma_sync_single_range_for_cpu(rx_ring->dev,
1435 IXGBE_CB(skb)->dma,
1436 frag->page_offset,
1437 ixgbe_rx_bufsz(rx_ring),
1438 DMA_FROM_DEVICE);
1439 }
1440 IXGBE_CB(skb)->dma = 0;
1441
1442 /* verify that the packet does not have any known errors */
1443 if (unlikely(ixgbe_test_staterr(rx_desc,
1444 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1445 !(netdev->features & NETIF_F_RXALL))) {
1446 dev_kfree_skb_any(skb);
1447 return true;
1448 }
1449
1450 /*
1451 * it is valid to use page_address instead of kmap since we are
1452 * working with pages allocated out of the lomem pool per
1453 * alloc_page(GFP_ATOMIC)
1454 */
1455 va = skb_frag_address(frag);
1456
1457 /*
1458 * we need the header to contain the greater of either ETH_HLEN or
1459 * 60 bytes if the skb->len is less than 60 for skb_pad.
1460 */
1461 pull_len = skb_frag_size(frag);
1462 if (pull_len > 256)
1463 pull_len = ixgbe_get_headlen(va, pull_len);
1464
1465 /* align pull length to size of long to optimize memcpy performance */
1466 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1467
1468 /* update all of the pointers */
1469 skb_frag_size_sub(frag, pull_len);
1470 frag->page_offset += pull_len;
1471 skb->data_len -= pull_len;
1472 skb->tail += pull_len;
1473
1474 /*
1475 * if we sucked the frag empty then we should free it,
1476 * if there are other frags here something is screwed up in hardware
1477 */
1478 if (skb_frag_size(frag) == 0) {
1479 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1480 skb_shinfo(skb)->nr_frags = 0;
1481 __skb_frag_unref(frag);
1482 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1483 }
1484
1485 /* if skb_pad returns an error the skb was freed */
1486 if (unlikely(skb->len < 60)) {
1487 int pad_len = 60 - skb->len;
1488
1489 if (skb_pad(skb, pad_len))
1490 return true;
1491 __skb_put(skb, pad_len);
1492 }
1493
1494 return false;
1495}
1496
1497/**
1498 * ixgbe_can_reuse_page - determine if we can reuse a page
1499 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1500 *
1501 * Returns true if page can be reused in another Rx buffer
1502 **/
1503static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1504{
1505 struct page *page = rx_buffer->page;
1506
1507 /* if we are only owner of page and it is local we can reuse it */
1508 return likely(page_count(page) == 1) &&
1509 likely(page_to_nid(page) == numa_node_id());
1510}
1511
1512/**
1513 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1514 * @rx_ring: rx descriptor ring to store buffers on
1515 * @old_buff: donor buffer to have page reused
1516 *
1517 * Syncronizes page for reuse by the adapter
1518 **/
1519static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1520 struct ixgbe_rx_buffer *old_buff)
1521{
1522 struct ixgbe_rx_buffer *new_buff;
1523 u16 nta = rx_ring->next_to_alloc;
1524 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1525
1526 new_buff = &rx_ring->rx_buffer_info[nta];
1527
1528 /* update, and store next to alloc */
1529 nta++;
1530 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1531
1532 /* transfer page from old buffer to new buffer */
1533 new_buff->page = old_buff->page;
1534 new_buff->dma = old_buff->dma;
1535
1536 /* flip page offset to other buffer and store to new_buff */
1537 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1538
1539 /* sync the buffer for use by the device */
1540 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1541 new_buff->page_offset, bufsz,
1542 DMA_FROM_DEVICE);
1543
1544 /* bump ref count on page before it is given to the stack */
1545 get_page(new_buff->page);
1546}
1547
1548/**
1549 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1550 * @rx_ring: rx descriptor ring to transact packets on
1551 * @rx_buffer: buffer containing page to add
1552 * @rx_desc: descriptor containing length of buffer written by hardware
1553 * @skb: sk_buff to place the data into
1554 *
1555 * This function is based on skb_add_rx_frag. I would have used that
1556 * function however it doesn't handle the truesize case correctly since we
1557 * are allocating more memory than might be used for a single receive.
1558 **/
1559static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1560 struct ixgbe_rx_buffer *rx_buffer,
1561 struct sk_buff *skb, int size)
1562{
1563 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1564 rx_buffer->page, rx_buffer->page_offset,
1565 size);
1566 skb->len += size;
1567 skb->data_len += size;
1568 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1569}
1570
1571/**
1572 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1573 * @q_vector: structure containing interrupt and ring information
1574 * @rx_ring: rx descriptor ring to transact packets on
1575 * @budget: Total limit on number of packets to process
1576 *
1577 * This function provides a "bounce buffer" approach to Rx interrupt
1578 * processing. The advantage to this is that on systems that have
1579 * expensive overhead for IOMMU access this provides a means of avoiding
1580 * it by maintaining the mapping of the page to the syste.
1581 *
1582 * Returns true if all work is completed without reaching budget
1583 **/
4ff7fb12 1584static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1585 struct ixgbe_ring *rx_ring,
4ff7fb12 1586 int budget)
9a799d71 1587{
d2f4fbe2 1588 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1589#ifdef IXGBE_FCOE
f800326d 1590 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1591 int ddp_bytes = 0;
1592#endif /* IXGBE_FCOE */
f800326d 1593 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1594
f800326d
AD		 1595 do {
1596 struct ixgbe_rx_buffer *rx_buffer;
1597 union ixgbe_adv_rx_desc *rx_desc;
1598 struct sk_buff *skb;
1599 struct page *page;
1600 u16 ntc;
1601
1602 /* return some buffers to hardware, one at a time is too slow */
1603 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1604 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1605 cleaned_count = 0;
1606 }
1607
1608 ntc = rx_ring->next_to_clean;
1609 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1610 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1611
1612 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1613 break;
9a799d71 1614
f800326d
AD		 1615 /*
1616 * This memory barrier is needed to keep us from reading
1617 * any other fields out of the rx_desc until we know the
1618 * RXD_STAT_DD bit is set
1619 */
1620 rmb();
9a799d71 1621
f800326d
AD		 1622 page = rx_buffer->page;
1623 prefetchw(page);
9a799d71 1624
f800326d 1625 skb = rx_buffer->skb;
c267fc16 1626
f800326d
AD		 1627 if (likely(!skb)) {
1628 void *page_addr = page_address(page) +
1629 rx_buffer->page_offset;
9a799d71 1630
f800326d
AD		 1631 /* prefetch first cache line of first page */
1632 prefetch(page_addr);
1633#if L1_CACHE_BYTES < 128
1634 prefetch(page_addr + L1_CACHE_BYTES);
1635#endif
1636
1637 /* allocate a skb to store the frags */
1638 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1639 IXGBE_RX_HDR_SIZE);
1640 if (unlikely(!skb)) {
1641 rx_ring->rx_stats.alloc_rx_buff_failed++;
1642 break;
c267fc16
AD		 1643 }
1644
f800326d
AD		 1645 /*
1646 * we will be copying header into skb->data in
1647 * pskb_may_pull so it is in our interest to prefetch
1648 * it now to avoid a possible cache miss
1649 */
1650 prefetchw(skb->data);
4c1975d7
AD		 1651
1652 /*
1653 * Delay unmapping of the first packet. It carries the
1654 * header information, HW may still access the header
f800326d
AD		 1655 * after the writeback. Only unmap it when EOP is
1656 * reached
4c1975d7 1657 */
f800326d 1658 IXGBE_CB(skb)->dma = rx_buffer->dma;
c267fc16 1659 } else {
f800326d
AD		 1660 /* we are reusing so sync this buffer for CPU use */
1661 dma_sync_single_range_for_cpu(rx_ring->dev,
1662 rx_buffer->dma,
1663 rx_buffer->page_offset,
1664 ixgbe_rx_bufsz(rx_ring),
1665 DMA_FROM_DEVICE);
9a799d71
AK		 1666 }
1667
f800326d
AD		 1668 /* pull page into skb */
1669 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1670 le16_to_cpu(rx_desc->wb.upper.length));
9a799d71 1671
f800326d
AD		 1672 if (ixgbe_can_reuse_page(rx_buffer)) {
1673 /* hand second half of page back to the ring */
1674 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1675 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1676 /* the page has been released from the ring */
1677 IXGBE_CB(skb)->page_released = true;
1678 } else {
1679 /* we are not reusing the buffer so unmap it */
1680 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1681 ixgbe_rx_pg_size(rx_ring),
1682 DMA_FROM_DEVICE);
9a799d71
AK		 1683 }
1684
f800326d
AD		 1685 /* clear contents of buffer_info */
1686 rx_buffer->skb = NULL;
1687 rx_buffer->dma = 0;
1688 rx_buffer->page = NULL;
4c1975d7 1689
f800326d 1690 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
9a799d71 1691
9a799d71 1692 cleaned_count++;
f8212f97 1693
f800326d
AD		 1694 /* place incomplete frames back on ring for completion */
1695 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1696 continue;
c267fc16 1697
f800326d
AD		 1698 /* verify the packet layout is correct */
1699 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1700 continue;
9a799d71 1701
d2f4fbe2
AV		 1702 /* probably a little skewed due to removing CRC */
1703 total_rx_bytes += skb->len;
1704 total_rx_packets++;
1705
8a0da21b
AD		 1706 /* populate checksum, timestamp, VLAN, and protocol */
1707 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1708
332d4a7d
YZ		 1709#ifdef IXGBE_FCOE
1710 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc 1711 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
f56e0cb1 1712 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1713 if (!ddp_bytes) {
1714 dev_kfree_skb_any(skb);
f800326d 1715 continue;
63d635b2 1716 }
3d8fd385 1717 }
f800326d 1718
332d4a7d 1719#endif /* IXGBE_FCOE */
8a0da21b 1720 ixgbe_rx_skb(q_vector, skb);
9a799d71 1721
f800326d 1722 /* update budget accounting */
4ff7fb12 1723 budget--;
f800326d 1724 } while (likely(budget));
9a799d71 1725
3d8fd385
YZ		 1726#ifdef IXGBE_FCOE
1727 /* include DDPed FCoE data */
1728 if (ddp_bytes > 0) {
1729 unsigned int mss;
1730
fc77dc3c 1731 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1732 sizeof(struct fc_frame_header) -
1733 sizeof(struct fcoe_crc_eof);
1734 if (mss > 512)
1735 mss &= ~511;
1736 total_rx_bytes += ddp_bytes;
1737 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1738 }
3d8fd385 1739
f800326d 1740#endif /* IXGBE_FCOE */
c267fc16
AD		 1741 u64_stats_update_begin(&rx_ring->syncp);
1742 rx_ring->stats.packets += total_rx_packets;
1743 rx_ring->stats.bytes += total_rx_bytes;
1744 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1745 q_vector->rx.total_packets += total_rx_packets;
1746 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1747
f800326d
AD		 1748 if (cleaned_count)
1749 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1750
4ff7fb12 1751 return !!budget;
9a799d71
AK		 1752}
1753
9a799d71
AK		 1754/**
1755 * ixgbe_configure_msix - Configure MSI-X hardware
1756 * @adapter: board private structure
1757 *
1758 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1759 * interrupts.
1760 **/
1761static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1762{
021230d4 1763 struct ixgbe_q_vector *q_vector;
efe3d3c8 1764 int q_vectors, v_idx;
021230d4 1765 u32 mask;
9a799d71 1766
021230d4 1767 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1768
8e34d1aa
AD		 1769 /* Populate MSIX to EITR Select */
1770 if (adapter->num_vfs > 32) {
1771 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1773 }
1774
4df10466
JB		 1775 /*
1776 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1777 * corresponding register.
1778 */
1779 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1780 struct ixgbe_ring *ring;
7a921c93 1781 q_vector = adapter->q_vector[v_idx];
021230d4 1782
a557928e 1783 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1784 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1785
a557928e 1786 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1787 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1788
d5bf4f67
ET		 1789 if (q_vector->tx.ring && !q_vector->rx.ring) {
1790 /* tx only vector */
1791 if (adapter->tx_itr_setting == 1)
1792 q_vector->itr = IXGBE_10K_ITR;
1793 else
1794 q_vector->itr = adapter->tx_itr_setting;
1795 } else {
1796 /* rx or rx/tx vector */
1797 if (adapter->rx_itr_setting == 1)
1798 q_vector->itr = IXGBE_20K_ITR;
1799 else
1800 q_vector->itr = adapter->rx_itr_setting;
1801 }
021230d4 1802
fe49f04a 1803 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1804 }
1805
bd508178
AD		 1806 switch (adapter->hw.mac.type) {
1807 case ixgbe_mac_82598EB:
e8e26350 1808 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1809 v_idx);
bd508178
AD		 1810 break;
1811 case ixgbe_mac_82599EB:
b93a2226 1812 case ixgbe_mac_X540:
e8e26350 1813 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1814 break;
bd508178
AD		 1815 default:
1816 break;
1817 }
021230d4
AV		 1818 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1819
41fb9248 1820 /* set up to autoclear timer, and the vectors */
021230d4 1821 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1822 mask &= ~(IXGBE_EIMS_OTHER |
1823 IXGBE_EIMS_MAILBOX |
1824 IXGBE_EIMS_LSC);
1825
021230d4 1826 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1827}
1828
f494e8fa
AV		 1829enum latency_range {
1830 lowest_latency = 0,
1831 low_latency = 1,
1832 bulk_latency = 2,
1833 latency_invalid = 255
1834};
1835
1836/**
1837 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1838 * @q_vector: structure containing interrupt and ring information
1839 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1840 *
1841 * Stores a new ITR value based on packets and byte
1842 * counts during the last interrupt. The advantage of per interrupt
1843 * computation is faster updates and more accurate ITR for the current
1844 * traffic pattern. Constants in this function were computed
1845 * based on theoretical maximum wire speed and thresholds were set based
1846 * on testing data as well as attempting to minimize response time
1847 * while increasing bulk throughput.
1848 * this functionality is controlled by the InterruptThrottleRate module
1849 * parameter (see ixgbe_param.c)
1850 **/
bd198058
AD		 1851static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1852 struct ixgbe_ring_container *ring_container)
f494e8fa 1853{
bd198058
AD		 1854 int bytes = ring_container->total_bytes;
1855 int packets = ring_container->total_packets;
1856 u32 timepassed_us;
621bd70e 1857 u64 bytes_perint;
bd198058 1858 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1859
1860 if (packets == 0)
bd198058 1861 return;
f494e8fa
AV		 1862
1863 /* simple throttlerate management
621bd70e
AD		 1864 * 0-10MB/s lowest (100000 ints/s)
1865 * 10-20MB/s low (20000 ints/s)
1866 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1867 */
1868 /* what was last interrupt timeslice? */
d5bf4f67 1869 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1870 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1871
1872 switch (itr_setting) {
1873 case lowest_latency:
621bd70e 1874 if (bytes_perint > 10)
bd198058 1875 itr_setting = low_latency;
f494e8fa
AV		 1876 break;
1877 case low_latency:
621bd70e 1878 if (bytes_perint > 20)
bd198058 1879 itr_setting = bulk_latency;
621bd70e 1880 else if (bytes_perint <= 10)
bd198058 1881 itr_setting = lowest_latency;
f494e8fa
AV		 1882 break;
1883 case bulk_latency:
621bd70e 1884 if (bytes_perint <= 20)
bd198058 1885 itr_setting = low_latency;
f494e8fa
AV		 1886 break;
1887 }
1888
bd198058
AD		 1889 /* clear work counters since we have the values we need */
1890 ring_container->total_bytes = 0;
1891 ring_container->total_packets = 0;
1892
1893 /* write updated itr to ring container */
1894 ring_container->itr = itr_setting;
f494e8fa
AV		 1895}
1896
509ee935
JB		 1897/**
1898 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1899 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1900 *
1901 * This function is made to be called by ethtool and by the driver
1902 * when it needs to update EITR registers at runtime. Hardware
1903 * specific quirks/differences are taken care of here.
1904 */
fe49f04a 1905void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1906{
fe49f04a 1907 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1908 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1909 int v_idx = q_vector->v_idx;
5d967eb7 1910 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 1911
bd508178
AD		 1912 switch (adapter->hw.mac.type) {
1913 case ixgbe_mac_82598EB:
509ee935
JB		 1914 /* must write high and low 16 bits to reset counter */
1915 itr_reg |= (itr_reg << 16);
bd508178
AD		 1916 break;
1917 case ixgbe_mac_82599EB:
b93a2226 1918 case ixgbe_mac_X540:
509ee935
JB		 1919 /*
1920 * set the WDIS bit to not clear the timer bits and cause an
1921 * immediate assertion of the interrupt
1922 */
1923 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1924 break;
1925 default:
1926 break;
509ee935
JB		 1927 }
1928 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1929}
1930
bd198058 1931static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1932{
d5bf4f67 1933 u32 new_itr = q_vector->itr;
bd198058 1934 u8 current_itr;
f494e8fa 1935
bd198058
AD		 1936 ixgbe_update_itr(q_vector, &q_vector->tx);
1937 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1938
08c8833b 1939 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1940
1941 switch (current_itr) {
1942 /* counts and packets in update_itr are dependent on these numbers */
1943 case lowest_latency:
d5bf4f67 1944 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1945 break;
1946 case low_latency:
d5bf4f67 1947 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1948 break;
1949 case bulk_latency:
d5bf4f67 1950 new_itr = IXGBE_8K_ITR;
f494e8fa 1951 break;
bd198058
AD		 1952 default:
1953 break;
f494e8fa
AV		 1954 }
1955
d5bf4f67 1956 if (new_itr != q_vector->itr) {
fe49f04a 1957 /* do an exponential smoothing */
d5bf4f67
ET		 1958 new_itr = (10 * new_itr * q_vector->itr) /
1959 ((9 * new_itr) + q_vector->itr);
509ee935 1960
bd198058 1961 /* save the algorithm value here */
5d967eb7 1962 q_vector->itr = new_itr;
fe49f04a
AD		 1963
1964 ixgbe_write_eitr(q_vector);
f494e8fa 1965 }
f494e8fa
AV		 1966}
1967
119fc60a 1968/**
de88eeeb 1969 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 1970 * @adapter: pointer to adapter
119fc60a 1971 **/
f0f9778d 1972static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1973{
119fc60a
MC		 1974 struct ixgbe_hw *hw = &adapter->hw;
1975 u32 eicr = adapter->interrupt_event;
1976
f0f9778d 1977 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1978 return;
1979
f0f9778d
AD		 1980 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1981 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1982 return;
1983
1984 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1985
7ca647bd 1986 switch (hw->device_id) {
f0f9778d
AD		 1987 case IXGBE_DEV_ID_82599_T3_LOM:
1988 /*
1989 * Since the warning interrupt is for both ports
1990 * we don't have to check if:
1991 * - This interrupt wasn't for our port.
1992 * - We may have missed the interrupt so always have to
1993 * check if we got a LSC
1994 */
1995 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1996 !(eicr & IXGBE_EICR_LSC))
1997 return;
1998
1999 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2000 u32 autoneg;
2001 bool link_up = false;
7ca647bd 2002
7ca647bd
JP		 2003 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2004
f0f9778d
AD		 2005 if (link_up)
2006 return;
2007 }
2008
2009 /* Check if this is not due to overtemp */
2010 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2011 return;
2012
2013 break;
7ca647bd
JP		 2014 default:
2015 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2016 return;
7ca647bd 2017 break;
119fc60a 2018 }
7ca647bd
JP		 2019 e_crit(drv,
2020 "Network adapter has been stopped because it has over heated. "
2021 "Restart the computer. If the problem persists, "
2022 "power off the system and replace the adapter\n");
f0f9778d
AD		 2023
2024 adapter->interrupt_event = 0;
119fc60a
MC		 2025}
2026
0befdb3e
JB		 2027static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2028{
2029 struct ixgbe_hw *hw = &adapter->hw;
2030
2031 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2032 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2033 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2034 /* write to clear the interrupt */
2035 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2036 }
2037}
cf8280ee 2038
4f51bf70
JK		 2039static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2040{
2041 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2042 return;
2043
2044 switch (adapter->hw.mac.type) {
2045 case ixgbe_mac_82599EB:
2046 /*
2047 * Need to check link state so complete overtemp check
2048 * on service task
2049 */
2050 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2051 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2052 adapter->interrupt_event = eicr;
2053 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2054 ixgbe_service_event_schedule(adapter);
2055 return;
2056 }
2057 return;
2058 case ixgbe_mac_X540:
2059 if (!(eicr & IXGBE_EICR_TS))
2060 return;
2061 break;
2062 default:
2063 return;
2064 }
2065
2066 e_crit(drv,
2067 "Network adapter has been stopped because it has over heated. "
2068 "Restart the computer. If the problem persists, "
2069 "power off the system and replace the adapter\n");
2070}
2071
e8e26350
PW		 2072static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2073{
2074 struct ixgbe_hw *hw = &adapter->hw;
2075
73c4b7cd
AD		 2076 if (eicr & IXGBE_EICR_GPI_SDP2) {
2077 /* Clear the interrupt */
2078 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2080 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2081 ixgbe_service_event_schedule(adapter);
2082 }
73c4b7cd
AD		 2083 }
2084
e8e26350
PW		 2085 if (eicr & IXGBE_EICR_GPI_SDP1) {
2086 /* Clear the interrupt */
2087 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2088 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2089 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2090 ixgbe_service_event_schedule(adapter);
2091 }
e8e26350
PW		 2092 }
2093}
2094
cf8280ee
JB		 2095static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2096{
2097 struct ixgbe_hw *hw = &adapter->hw;
2098
2099 adapter->lsc_int++;
2100 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2101 adapter->link_check_timeout = jiffies;
2102 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2103 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2104 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2105 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2106 }
2107}
2108
fe49f04a
AD		 2109static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2110 u64 qmask)
2111{
2112 u32 mask;
bd508178 2113 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2114
bd508178
AD		 2115 switch (hw->mac.type) {
2116 case ixgbe_mac_82598EB:
fe49f04a 2117 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2118 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2119 break;
2120 case ixgbe_mac_82599EB:
b93a2226 2121 case ixgbe_mac_X540:
fe49f04a 2122 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2123 if (mask)
2124 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2125 mask = (qmask >> 32);
bd508178
AD		 2126 if (mask)
2127 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2128 break;
2129 default:
2130 break;
fe49f04a
AD		 2131 }
2132 /* skip the flush */
2133}
2134
2135static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2136 u64 qmask)
fe49f04a
AD		 2137{
2138 u32 mask;
bd508178 2139 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2140
bd508178
AD		 2141 switch (hw->mac.type) {
2142 case ixgbe_mac_82598EB:
fe49f04a 2143 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2144 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2145 break;
2146 case ixgbe_mac_82599EB:
b93a2226 2147 case ixgbe_mac_X540:
fe49f04a 2148 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2149 if (mask)
2150 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2151 mask = (qmask >> 32);
bd508178
AD		 2152 if (mask)
2153 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2154 break;
2155 default:
2156 break;
fe49f04a
AD		 2157 }
2158 /* skip the flush */
2159}
2160
021230d4 2161/**
2c4af694
AD		 2162 * ixgbe_irq_enable - Enable default interrupt generation settings
2163 * @adapter: board private structure
021230d4 2164 **/
2c4af694
AD		 2165static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2166 bool flush)
9a799d71 2167{
2c4af694 2168 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2169
2c4af694
AD		 2170 /* don't reenable LSC while waiting for link */
2171 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2172 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2173
2c4af694 2174 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2175 switch (adapter->hw.mac.type) {
2176 case ixgbe_mac_82599EB:
2177 mask |= IXGBE_EIMS_GPI_SDP0;
2178 break;
2179 case ixgbe_mac_X540:
2180 mask |= IXGBE_EIMS_TS;
2181 break;
2182 default:
2183 break;
2184 }
2c4af694
AD		 2185 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2186 mask |= IXGBE_EIMS_GPI_SDP1;
2187 switch (adapter->hw.mac.type) {
2188 case ixgbe_mac_82599EB:
2c4af694
AD		 2189 mask |= IXGBE_EIMS_GPI_SDP1;
2190 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2191 case ixgbe_mac_X540:
2192 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2193 mask |= IXGBE_EIMS_MAILBOX;
2194 break;
2195 default:
2196 break;
9a799d71 2197 }
2c4af694
AD		 2198 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2199 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2200 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2201
2c4af694
AD		 2202 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2203 if (queues)
2204 ixgbe_irq_enable_queues(adapter, ~0);
2205 if (flush)
2206 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2207}
2208
2c4af694 2209static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2210{
a65151ba 2211 struct ixgbe_adapter *adapter = data;
9a799d71 2212 struct ixgbe_hw *hw = &adapter->hw;
54037505 2213 u32 eicr;
91281fd3 2214
54037505
DS		 2215 /*
2216 * Workaround for Silicon errata. Use clear-by-write instead
2217 * of clear-by-read. Reading with EICS will return the
2218 * interrupt causes without clearing, which later be done
2219 * with the write to EICR.
2220 */
2221 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2222 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2223
cf8280ee
JB		 2224 if (eicr & IXGBE_EICR_LSC)
2225 ixgbe_check_lsc(adapter);
f0848276 2226
1cdd1ec8
GR		 2227 if (eicr & IXGBE_EICR_MAILBOX)
2228 ixgbe_msg_task(adapter);
efe3d3c8 2229
bd508178
AD		 2230 switch (hw->mac.type) {
2231 case ixgbe_mac_82599EB:
b93a2226 2232 case ixgbe_mac_X540:
2c4af694
AD		 2233 if (eicr & IXGBE_EICR_ECC)
2234 e_info(link, "Received unrecoverable ECC Err, please "
2235 "reboot\n");
c4cf55e5
PWJ		 2236 /* Handle Flow Director Full threshold interrupt */
2237 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2238 int reinit_count = 0;
c4cf55e5 2239 int i;
c4cf55e5 2240 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2241 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2242 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2243 &ring->state))
2244 reinit_count++;
2245 }
2246 if (reinit_count) {
2247 /* no more flow director interrupts until after init */
2248 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2249 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2250 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2251 }
2252 }
f0f9778d 2253 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2254 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2255 break;
2256 default:
2257 break;
c4cf55e5 2258 }
f0848276 2259
bd508178 2260 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 2261
7086400d 2262 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2263 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2264 ixgbe_irq_enable(adapter, false, false);
f0848276 2265
9a799d71 2266 return IRQ_HANDLED;
f0848276 2267}
91281fd3 2268
4ff7fb12 2269static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2270{
021230d4 2271 struct ixgbe_q_vector *q_vector = data;
91281fd3 2272
9b471446 2273 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2274
4ff7fb12
AD		 2275 if (q_vector->rx.ring || q_vector->tx.ring)
2276 napi_schedule(&q_vector->napi);
91281fd3 2277
9a799d71 2278 return IRQ_HANDLED;
91281fd3
AD		 2279}
2280
021230d4
AV		 2281/**
2282 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2283 * @adapter: board private structure
2284 *
2285 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2286 * interrupts from the kernel.
2287 **/
2288static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2289{
2290 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2291 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2292 int vector, err;
e8e9f696 2293 int ri = 0, ti = 0;
021230d4 2294
021230d4 2295 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2296 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2297 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2298
4ff7fb12 2299 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2300 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2301 "%s-%s-%d", netdev->name, "TxRx", ri++);
2302 ti++;
2303 } else if (q_vector->rx.ring) {
9fe93afd 2304 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2305 "%s-%s-%d", netdev->name, "rx", ri++);
2306 } else if (q_vector->tx.ring) {
9fe93afd 2307 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2308 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2309 } else {
2310 /* skip this unused q_vector */
2311 continue;
32aa77a4 2312 }
207867f5
AD		 2313 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2314 q_vector->name, q_vector);
9a799d71 2315 if (err) {
396e799c 2316 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2317 "Error: %d\n", err);
021230d4 2318 goto free_queue_irqs;
9a799d71 2319 }
207867f5
AD		 2320 /* If Flow Director is enabled, set interrupt affinity */
2321 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2322 /* assign the mask for this irq */
2323 irq_set_affinity_hint(entry->vector,
de88eeeb 2324 &q_vector->affinity_mask);
207867f5 2325 }
9a799d71
AK		 2326 }
2327
021230d4 2328 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2329 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2330 if (err) {
de88eeeb 2331 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2332 goto free_queue_irqs;
9a799d71
AK		 2333 }
2334
9a799d71
AK		 2335 return 0;
2336
021230d4 2337free_queue_irqs:
207867f5
AD		 2338 while (vector) {
2339 vector--;
2340 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2341 NULL);
2342 free_irq(adapter->msix_entries[vector].vector,
2343 adapter->q_vector[vector]);
2344 }
021230d4
AV		 2345 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2346 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2347 kfree(adapter->msix_entries);
2348 adapter->msix_entries = NULL;
9a799d71
AK		 2349 return err;
2350}
2351
2352/**
021230d4 2353 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2354 * @irq: interrupt number
2355 * @data: pointer to a network interface device structure
9a799d71
AK		 2356 **/
2357static irqreturn_t ixgbe_intr(int irq, void *data)
2358{
a65151ba 2359 struct ixgbe_adapter *adapter = data;
9a799d71 2360 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2361 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2362 u32 eicr;
2363
54037505 2364 /*
24ddd967 2365 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2366 * before the read of EICR.
2367 */
2368 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2369
021230d4 2370 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2371 * therefore no explicit interrupt disable is necessary */
021230d4 2372 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2373 if (!eicr) {
6af3b9eb
ET		 2374 /*
2375 * shared interrupt alert!
f47cf66e 2376 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2377 * have disabled interrupts due to EIAM
2378 * finish the workaround of silicon errata on 82598. Unmask
2379 * the interrupt that we masked before the EICR read.
2380 */
2381 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2382 ixgbe_irq_enable(adapter, true, true);
9a799d71 2383 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2384 }
9a799d71 2385
cf8280ee
JB		 2386 if (eicr & IXGBE_EICR_LSC)
2387 ixgbe_check_lsc(adapter);
021230d4 2388
bd508178
AD		 2389 switch (hw->mac.type) {
2390 case ixgbe_mac_82599EB:
e8e26350 2391 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2392 /* Fall through */
2393 case ixgbe_mac_X540:
2394 if (eicr & IXGBE_EICR_ECC)
2395 e_info(link, "Received unrecoverable ECC err, please "
2396 "reboot\n");
4f51bf70 2397 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2398 break;
2399 default:
2400 break;
2401 }
e8e26350 2402
0befdb3e
JB		 2403 ixgbe_check_fan_failure(adapter, eicr);
2404
b9f6ed2b
AD		 2405 /* would disable interrupts here but EIAM disabled it */
2406 napi_schedule(&q_vector->napi);
9a799d71 2407
6af3b9eb
ET		 2408 /*
2409 * re-enable link(maybe) and non-queue interrupts, no flush.
2410 * ixgbe_poll will re-enable the queue interrupts
2411 */
6af3b9eb
ET		 2412 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2413 ixgbe_irq_enable(adapter, false, false);
2414
9a799d71
AK		 2415 return IRQ_HANDLED;
2416}
2417
2418/**
2419 * ixgbe_request_irq - initialize interrupts
2420 * @adapter: board private structure
2421 *
2422 * Attempts to configure interrupts using the best available
2423 * capabilities of the hardware and kernel.
2424 **/
021230d4 2425static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2426{
2427 struct net_device *netdev = adapter->netdev;
021230d4 2428 int err;
9a799d71 2429
4cc6df29 2430 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2431 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2432 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2433 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2434 netdev->name, adapter);
4cc6df29 2435 else
a0607fd3 2436 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2437 netdev->name, adapter);
9a799d71 2438
de88eeeb 2439 if (err)
396e799c 2440 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2441
9a799d71
AK		 2442 return err;
2443}
2444
2445static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2446{
9a799d71 2447 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2448 int i, q_vectors;
9a799d71 2449
021230d4 2450 q_vectors = adapter->num_msix_vectors;
021230d4 2451 i = q_vectors - 1;
a65151ba 2452 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2453 i--;
4cc6df29 2454
021230d4 2455 for (; i >= 0; i--) {
894ff7cf 2456 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2457 if (!adapter->q_vector[i]->rx.ring &&
2458 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2459 continue;
2460
207867f5
AD		 2461 /* clear the affinity_mask in the IRQ descriptor */
2462 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2463 NULL);
2464
021230d4 2465 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2466 adapter->q_vector[i]);
021230d4 2467 }
021230d4 2468 } else {
a65151ba 2469 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2470 }
2471}
2472
22d5a71b
JB		 2473/**
2474 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2475 * @adapter: board private structure
2476 **/
2477static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2478{
bd508178
AD		 2479 switch (adapter->hw.mac.type) {
2480 case ixgbe_mac_82598EB:
835462fc 2481 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2482 break;
2483 case ixgbe_mac_82599EB:
b93a2226 2484 case ixgbe_mac_X540:
835462fc
NS		 2485 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2486 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2488 break;
2489 default:
2490 break;
22d5a71b
JB		 2491 }
2492 IXGBE_WRITE_FLUSH(&adapter->hw);
2493 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2494 int i;
2495 for (i = 0; i < adapter->num_msix_vectors; i++)
2496 synchronize_irq(adapter->msix_entries[i].vector);
2497 } else {
2498 synchronize_irq(adapter->pdev->irq);
2499 }
2500}
2501
9a799d71
AK		 2502/**
2503 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2504 *
2505 **/
2506static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2507{
d5bf4f67 2508 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2509
d5bf4f67
ET		 2510 /* rx/tx vector */
2511 if (adapter->rx_itr_setting == 1)
2512 q_vector->itr = IXGBE_20K_ITR;
2513 else
2514 q_vector->itr = adapter->rx_itr_setting;
2515
2516 ixgbe_write_eitr(q_vector);
9a799d71 2517
e8e26350
PW		 2518 ixgbe_set_ivar(adapter, 0, 0, 0);
2519 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2520
396e799c 2521 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2522}
2523
43e69bf0
AD		 2524/**
2525 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2526 * @adapter: board private structure
2527 * @ring: structure containing ring specific data
2528 *
2529 * Configure the Tx descriptor ring after a reset.
2530 **/
84418e3b
AD		 2531void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2532 struct ixgbe_ring *ring)
43e69bf0
AD		 2533{
2534 struct ixgbe_hw *hw = &adapter->hw;
2535 u64 tdba = ring->dma;
2f1860b8 2536 int wait_loop = 10;
b88c6de2 2537 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2538 u8 reg_idx = ring->reg_idx;
43e69bf0 2539
2f1860b8 2540 /* disable queue to avoid issues while updating state */
b88c6de2 2541 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2542 IXGBE_WRITE_FLUSH(hw);
2543
43e69bf0 2544 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2545 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2546 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2547 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2548 ring->count * sizeof(union ixgbe_adv_tx_desc));
2549 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2550 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2551 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2552
b88c6de2
AD		 2553 /*
2554 * set WTHRESH to encourage burst writeback, it should not be set
2555 * higher than 1 when ITR is 0 as it could cause false TX hangs
2556 *
2557 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2558 * to or less than the number of on chip descriptors, which is
2559 * currently 40.
2560 */
e954b374 2561 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2562 txdctl |= (1 << 16); /* WTHRESH = 1 */
2563 else
2564 txdctl |= (8 << 16); /* WTHRESH = 8 */
2565
e954b374
AD		 2566 /*
2567 * Setting PTHRESH to 32 both improves performance
2568 * and avoids a TX hang with DFP enabled
2569 */
b88c6de2
AD		 2570 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2571 32; /* PTHRESH = 32 */
2f1860b8
AD		 2572
2573 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2574 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2575 adapter->atr_sample_rate) {
2576 ring->atr_sample_rate = adapter->atr_sample_rate;
2577 ring->atr_count = 0;
2578 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2579 } else {
2580 ring->atr_sample_rate = 0;
2581 }
2f1860b8 2582
c84d324c
JF		 2583 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2584
2f1860b8 2585 /* enable queue */
2f1860b8
AD		 2586 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2587
b2d96e0a
AD		 2588 netdev_tx_reset_queue(txring_txq(ring));
2589
2f1860b8
AD		 2590 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2591 if (hw->mac.type == ixgbe_mac_82598EB &&
2592 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2593 return;
2594
2595 /* poll to verify queue is enabled */
2596 do {
032b4325 2597 usleep_range(1000, 2000);
2f1860b8
AD		 2598 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2599 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2600 if (!wait_loop)
2601 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2602}
2603
120ff942
AD		 2604static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2605{
2606 struct ixgbe_hw *hw = &adapter->hw;
2607 u32 rttdcs;
72a32f1f 2608 u32 reg;
8b1c0b24 2609 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2610
2611 if (hw->mac.type == ixgbe_mac_82598EB)
2612 return;
2613
2614 /* disable the arbiter while setting MTQC */
2615 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2616 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2617 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2618
2619 /* set transmit pool layout */
8b1c0b24 2620 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2621 case (IXGBE_FLAG_SRIOV_ENABLED):
2622 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2623 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2624 break;
8b1c0b24
JF		 2625 default:
2626 if (!tcs)
2627 reg = IXGBE_MTQC_64Q_1PB;
2628 else if (tcs <= 4)
2629 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2630 else
2631 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2632
8b1c0b24 2633 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2634
8b1c0b24
JF		 2635 /* Enable Security TX Buffer IFG for multiple pb */
2636 if (tcs) {
2637 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2638 reg |= IXGBE_SECTX_DCB;
2639 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2640 }
120ff942
AD		 2641 break;
2642 }
2643
2644 /* re-enable the arbiter */
2645 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2646 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2647}
2648
9a799d71 2649/**
3a581073 2650 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2651 * @adapter: board private structure
2652 *
2653 * Configure the Tx unit of the MAC after a reset.
2654 **/
2655static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2656{
2f1860b8
AD		 2657 struct ixgbe_hw *hw = &adapter->hw;
2658 u32 dmatxctl;
43e69bf0 2659 u32 i;
9a799d71 2660
2f1860b8
AD		 2661 ixgbe_setup_mtqc(adapter);
2662
2663 if (hw->mac.type != ixgbe_mac_82598EB) {
2664 /* DMATXCTL.EN must be before Tx queues are enabled */
2665 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2666 dmatxctl |= IXGBE_DMATXCTL_TE;
2667 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2668 }
2669
9a799d71 2670 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2671 for (i = 0; i < adapter->num_tx_queues; i++)
2672 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2673}
2674
e8e26350 2675#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2676
a6616b42 2677static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2678 struct ixgbe_ring *rx_ring)
cc41ac7c 2679{
cc41ac7c 2680 u32 srrctl;
bf29ee6c 2681 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2682
bd508178
AD		 2683 switch (adapter->hw.mac.type) {
2684 case ixgbe_mac_82598EB: {
2685 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2686 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2687 reg_idx = reg_idx & mask;
cc41ac7c 2688 }
bd508178
AD		 2689 break;
2690 case ixgbe_mac_82599EB:
b93a2226 2691 case ixgbe_mac_X540:
bd508178
AD		 2692 default:
2693 break;
2694 }
2695
bf29ee6c 2696 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2697
2698 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2699 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2700 if (adapter->num_vfs)
2701 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2702
afafd5b0
AD		 2703 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2704 IXGBE_SRRCTL_BSIZEHDR_MASK;
2705
f800326d
AD		 2706#if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2707 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2708#else
f800326d 2709 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2710#endif
f800326d 2711 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2712
bf29ee6c 2713 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2714}
9a799d71 2715
05abb126 2716static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2717{
05abb126
AD		 2718 struct ixgbe_hw *hw = &adapter->hw;
2719 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2720 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2721 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2722 u32 mrqc = 0, reta = 0;
2723 u32 rxcsum;
2724 int i, j;
8b1c0b24 2725 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2726 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2727
2728 if (tcs)
2729 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2730
05abb126
AD		 2731 /* Fill out hash function seeds */
2732 for (i = 0; i < 10; i++)
2733 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2734
2735 /* Fill out redirection table */
2736 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2737 if (j == maxq)
05abb126
AD		 2738 j = 0;
2739 /* reta = 4-byte sliding window of
2740 * 0x00..(indices-1)(indices-1)00..etc. */
2741 reta = (reta << 8) | (j * 0x11);
2742 if ((i & 3) == 3)
2743 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2744 }
0cefafad 2745
05abb126
AD		 2746 /* Disable indicating checksum in descriptor, enables RSS hash */
2747 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2748 rxcsum |= IXGBE_RXCSUM_PCSD;
2749 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2750
8b1c0b24
JF		 2751 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2752 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2753 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2754 } else {
2755 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2756 | IXGBE_FLAG_SRIOV_ENABLED);
2757
2758 switch (mask) {
2759 case (IXGBE_FLAG_RSS_ENABLED):
2760 if (!tcs)
2761 mrqc = IXGBE_MRQC_RSSEN;
2762 else if (tcs <= 4)
2763 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2764 else
2765 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2766 break;
2767 case (IXGBE_FLAG_SRIOV_ENABLED):
2768 mrqc = IXGBE_MRQC_VMDQEN;
2769 break;
2770 default:
2771 break;
2772 }
0cefafad
JB		 2773 }
2774
05abb126
AD		 2775 /* Perform hash on these packet types */
2776 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2777 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2778 | IXGBE_MRQC_RSS_FIELD_IPV6
2779 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2780
2781 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2782}
2783
bb5a9ad2
NS		 2784/**
2785 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2786 * @adapter: address of board private structure
2787 * @index: index of ring to set
bb5a9ad2 2788 **/
082757af 2789static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2790 struct ixgbe_ring *ring)
bb5a9ad2 2791{
bb5a9ad2 2792 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2793 u32 rscctrl;
bf29ee6c 2794 u8 reg_idx = ring->reg_idx;
7367096a 2795
7d637bcc 2796 if (!ring_is_rsc_enabled(ring))
7367096a 2797 return;
bb5a9ad2 2798
7367096a 2799 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2800 rscctrl |= IXGBE_RSCCTL_RSCEN;
2801 /*
2802 * we must limit the number of descriptors so that the
2803 * total size of max desc * buf_len is not greater
642c680e 2804 * than 65536
bb5a9ad2 2805 */
f800326d
AD		 2806#if (PAGE_SIZE <= 8192)
2807 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2808#elif (PAGE_SIZE <= 16384)
2809 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
bb5a9ad2 2810#else
f800326d 2811 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
bb5a9ad2 2812#endif
7367096a 2813 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2814}
2815
9e10e045
AD		 2816/**
2817 * ixgbe_set_uta - Set unicast filter table address
2818 * @adapter: board private structure
2819 *
2820 * The unicast table address is a register array of 32-bit registers.
2821 * The table is meant to be used in a way similar to how the MTA is used
2822 * however due to certain limitations in the hardware it is necessary to
2823 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2824 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2825 **/
2826static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2827{
2828 struct ixgbe_hw *hw = &adapter->hw;
2829 int i;
2830
2831 /* The UTA table only exists on 82599 hardware and newer */
2832 if (hw->mac.type < ixgbe_mac_82599EB)
2833 return;
2834
2835 /* we only need to do this if VMDq is enabled */
2836 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2837 return;
2838
2839 for (i = 0; i < 128; i++)
2840 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2841}
2842
2843#define IXGBE_MAX_RX_DESC_POLL 10
2844static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2845 struct ixgbe_ring *ring)
2846{
2847 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2848 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2849 u32 rxdctl;
bf29ee6c 2850 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2851
2852 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2853 if (hw->mac.type == ixgbe_mac_82598EB &&
2854 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2855 return;
2856
2857 do {
032b4325 2858 usleep_range(1000, 2000);
9e10e045
AD		 2859 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2860 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2861
2862 if (!wait_loop) {
2863 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2864 "the polling period\n", reg_idx);
2865 }
2866}
2867
2d39d576
YZ		 2868void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2869 struct ixgbe_ring *ring)
2870{
2871 struct ixgbe_hw *hw = &adapter->hw;
2872 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2873 u32 rxdctl;
2874 u8 reg_idx = ring->reg_idx;
2875
2876 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2877 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2878
2879 /* write value back with RXDCTL.ENABLE bit cleared */
2880 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2881
2882 if (hw->mac.type == ixgbe_mac_82598EB &&
2883 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2884 return;
2885
2886 /* the hardware may take up to 100us to really disable the rx queue */
2887 do {
2888 udelay(10);
2889 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2890 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2891
2892 if (!wait_loop) {
2893 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2894 "the polling period\n", reg_idx);
2895 }
2896}
2897
84418e3b
AD		 2898void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2899 struct ixgbe_ring *ring)
acd37177
AD		 2900{
2901 struct ixgbe_hw *hw = &adapter->hw;
2902 u64 rdba = ring->dma;
9e10e045 2903 u32 rxdctl;
bf29ee6c 2904 u8 reg_idx = ring->reg_idx;
acd37177 2905
9e10e045
AD		 2906 /* disable queue to avoid issues while updating state */
2907 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2908 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2909
acd37177
AD		 2910 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2911 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2912 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2913 ring->count * sizeof(union ixgbe_adv_rx_desc));
2914 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2915 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2916 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2917
2918 ixgbe_configure_srrctl(adapter, ring);
2919 ixgbe_configure_rscctl(adapter, ring);
2920
e9f98072
GR		 2921 /* If operating in IOV mode set RLPML for X540 */
2922 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2923 hw->mac.type == ixgbe_mac_X540) {
2924 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2925 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2926 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2927 }
2928
9e10e045
AD		 2929 if (hw->mac.type == ixgbe_mac_82598EB) {
2930 /*
2931 * enable cache line friendly hardware writes:
2932 * PTHRESH=32 descriptors (half the internal cache),
2933 * this also removes ugly rx_no_buffer_count increment
2934 * HTHRESH=4 descriptors (to minimize latency on fetch)
2935 * WTHRESH=8 burst writeback up to two cache lines
2936 */
2937 rxdctl &= ~0x3FFFFF;
2938 rxdctl |= 0x080420;
2939 }
2940
2941 /* enable receive descriptor ring */
2942 rxdctl |= IXGBE_RXDCTL_ENABLE;
2943 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2944
2945 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2946 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2947}
2948
48654521
AD		 2949static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2950{
2951 struct ixgbe_hw *hw = &adapter->hw;
2952 int p;
2953
2954 /* PSRTYPE must be initialized in non 82598 adapters */
2955 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2956 IXGBE_PSRTYPE_UDPHDR |
2957 IXGBE_PSRTYPE_IPV4HDR |
48654521 2958 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2959 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2960
2961 if (hw->mac.type == ixgbe_mac_82598EB)
2962 return;
2963
2964 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2965 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2966
2967 for (p = 0; p < adapter->num_rx_pools; p++)
2968 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2969 psrtype);
2970}
2971
f5b4a52e
AD		 2972static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2973{
2974 struct ixgbe_hw *hw = &adapter->hw;
2975 u32 gcr_ext;
2976 u32 vt_reg_bits;
2977 u32 reg_offset, vf_shift;
2978 u32 vmdctl;
de4c7f65 2979 int i;
f5b4a52e
AD		 2980
2981 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2982 return;
2983
2984 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2985 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2986 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2987 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2988
2989 vf_shift = adapter->num_vfs % 32;
4cd6923d 2990 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 2991
2992 /* Enable only the PF's pool for Tx/Rx */
2993 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2994 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2995 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2996 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2997 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2998
2999 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3000 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3001
3002 /*
3003 * Set up VF register offsets for selected VT Mode,
3004 * i.e. 32 or 64 VFs for SR-IOV
3005 */
3006 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3007 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3008 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3009 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3010
3011 /* enable Tx loopback for VF/PF communication */
3012 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3013 /* Enable MAC Anti-Spoofing */
a1cbb15c 3014 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 3015 (adapter->num_vfs != 0),
a985b6c3 3016 adapter->num_vfs);
de4c7f65
GR		 3017 /* For VFs that have spoof checking turned off */
3018 for (i = 0; i < adapter->num_vfs; i++) {
3019 if (!adapter->vfinfo[i].spoofchk_enabled)
3020 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3021 }
f5b4a52e
AD		 3022}
3023
477de6ed 3024static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3025{
9a799d71
AK		 3026 struct ixgbe_hw *hw = &adapter->hw;
3027 struct net_device *netdev = adapter->netdev;
3028 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3029 struct ixgbe_ring *rx_ring;
3030 int i;
3031 u32 mhadd, hlreg0;
48654521 3032
63f39bd1 3033#ifdef IXGBE_FCOE
477de6ed
AD		 3034 /* adjust max frame to be able to do baby jumbo for FCoE */
3035 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3036 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3037 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3038
477de6ed
AD		 3039#endif /* IXGBE_FCOE */
3040 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3041 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3042 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3043 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3044
3045 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3046 }
3047
919e78a6
AD		 3048 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3049 max_frame += VLAN_HLEN;
3050
477de6ed
AD		 3051 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3052 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3053 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3054 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3055
0cefafad
JB		 3056 /*
3057 * Setup the HW Rx Head and Tail Descriptor Pointers and
3058 * the Base and Length of the Rx Descriptor Ring
3059 */
9a799d71 3060 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3061 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3062 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3063 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3064 else
7d637bcc 3065 clear_ring_rsc_enabled(rx_ring);
63f39bd1 3066#ifdef IXGBE_FCOE
e8e9f696 3067 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3068 struct ixgbe_ring_feature *f;
3069 f = &adapter->ring_feature[RING_F_FCOE];
f800326d
AD		 3070 if ((i >= f->mask) && (i < f->mask + f->indices))
3071 set_bit(__IXGBE_RX_FCOE_BUFSZ, &rx_ring->state);
63f39bd1 3072 }
63f39bd1 3073#endif /* IXGBE_FCOE */
477de6ed 3074 }
477de6ed
AD		 3075}
3076
7367096a
AD		 3077static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3078{
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3081
3082 switch (hw->mac.type) {
3083 case ixgbe_mac_82598EB:
3084 /*
3085 * For VMDq support of different descriptor types or
3086 * buffer sizes through the use of multiple SRRCTL
3087 * registers, RDRXCTL.MVMEN must be set to 1
3088 *
3089 * also, the manual doesn't mention it clearly but DCA hints
3090 * will only use queue 0's tags unless this bit is set. Side
3091 * effects of setting this bit are only that SRRCTL must be
3092 * fully programmed [0..15]
3093 */
3094 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3095 break;
3096 case ixgbe_mac_82599EB:
b93a2226 3097 case ixgbe_mac_X540:
7367096a
AD		 3098 /* Disable RSC for ACK packets */
3099 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3100 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3101 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3102 /* hardware requires some bits to be set by default */
3103 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3104 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3105 break;
3106 default:
3107 /* We should do nothing since we don't know this hardware */
3108 return;
3109 }
3110
3111 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3112}
3113
477de6ed
AD		 3114/**
3115 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3116 * @adapter: board private structure
3117 *
3118 * Configure the Rx unit of the MAC after a reset.
3119 **/
3120static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3121{
3122 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3123 int i;
3124 u32 rxctrl;
477de6ed
AD		 3125
3126 /* disable receives while setting up the descriptors */
3127 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3128 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3129
3130 ixgbe_setup_psrtype(adapter);
7367096a 3131 ixgbe_setup_rdrxctl(adapter);
477de6ed 3132
9e10e045 3133 /* Program registers for the distribution of queues */
f5b4a52e 3134 ixgbe_setup_mrqc(adapter);
f5b4a52e 3135
9e10e045
AD		 3136 ixgbe_set_uta(adapter);
3137
477de6ed
AD		 3138 /* set_rx_buffer_len must be called before ring initialization */
3139 ixgbe_set_rx_buffer_len(adapter);
3140
3141 /*
3142 * Setup the HW Rx Head and Tail Descriptor Pointers and
3143 * the Base and Length of the Rx Descriptor Ring
3144 */
9e10e045
AD		 3145 for (i = 0; i < adapter->num_rx_queues; i++)
3146 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3147
9e10e045
AD		 3148 /* disable drop enable for 82598 parts */
3149 if (hw->mac.type == ixgbe_mac_82598EB)
3150 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3151
3152 /* enable all receives */
3153 rxctrl |= IXGBE_RXCTRL_RXEN;
3154 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3155}
3156
8e586137 3157static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3158{
3159 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3160 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3161 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3162
3163 /* add VID to filter table */
1ada1b1b 3164 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3165 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3166
3167 return 0;
068c89b0
DS		 3168}
3169
8e586137 3170static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3171{
3172 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3173 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3174 int pool_ndx = adapter->num_vfs;
068c89b0 3175
068c89b0 3176 /* remove VID from filter table */
1ada1b1b 3177 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3178 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3179
3180 return 0;
068c89b0
DS		 3181}
3182
5f6c0181
JB		 3183/**
3184 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3185 * @adapter: driver data
3186 */
3187static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3188{
3189 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3190 u32 vlnctrl;
3191
3192 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3193 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3194 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3195}
3196
3197/**
3198 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3199 * @adapter: driver data
3200 */
3201static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3202{
3203 struct ixgbe_hw *hw = &adapter->hw;
3204 u32 vlnctrl;
3205
3206 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3207 vlnctrl |= IXGBE_VLNCTRL_VFE;
3208 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3209 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3210}
3211
3212/**
3213 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3214 * @adapter: driver data
3215 */
3216static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3217{
3218 struct ixgbe_hw *hw = &adapter->hw;
3219 u32 vlnctrl;
5f6c0181
JB		 3220 int i, j;
3221
3222 switch (hw->mac.type) {
3223 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3224 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3225 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3226 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3227 break;
3228 case ixgbe_mac_82599EB:
b93a2226 3229 case ixgbe_mac_X540:
5f6c0181
JB		 3230 for (i = 0; i < adapter->num_rx_queues; i++) {
3231 j = adapter->rx_ring[i]->reg_idx;
3232 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3233 vlnctrl &= ~IXGBE_RXDCTL_VME;
3234 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3235 }
3236 break;
3237 default:
3238 break;
3239 }
3240}
3241
3242/**
f62bbb5e 3243 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3244 * @adapter: driver data
3245 */
f62bbb5e 3246static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3247{
3248 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3249 u32 vlnctrl;
5f6c0181
JB		 3250 int i, j;
3251
3252 switch (hw->mac.type) {
3253 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3254 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3255 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3256 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3257 break;
3258 case ixgbe_mac_82599EB:
b93a2226 3259 case ixgbe_mac_X540:
5f6c0181
JB		 3260 for (i = 0; i < adapter->num_rx_queues; i++) {
3261 j = adapter->rx_ring[i]->reg_idx;
3262 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3263 vlnctrl |= IXGBE_RXDCTL_VME;
3264 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3265 }
3266 break;
3267 default:
3268 break;
3269 }
3270}
3271
9a799d71
AK		 3272static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3273{
f62bbb5e 3274 u16 vid;
9a799d71 3275
f62bbb5e
JG		 3276 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3277
3278 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3279 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3280}
3281
2850062a
AD		 3282/**
3283 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3284 * @netdev: network interface device structure
3285 *
3286 * Writes unicast address list to the RAR table.
3287 * Returns: -ENOMEM on failure/insufficient address space
3288 * 0 on no addresses written
3289 * X on writing X addresses to the RAR table
3290 **/
3291static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3292{
3293 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3294 struct ixgbe_hw *hw = &adapter->hw;
3295 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3296 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3297 int count = 0;
3298
3299 /* return ENOMEM indicating insufficient memory for addresses */
3300 if (netdev_uc_count(netdev) > rar_entries)
3301 return -ENOMEM;
3302
3303 if (!netdev_uc_empty(netdev) && rar_entries) {
3304 struct netdev_hw_addr *ha;
3305 /* return error if we do not support writing to RAR table */
3306 if (!hw->mac.ops.set_rar)
3307 return -ENOMEM;
3308
3309 netdev_for_each_uc_addr(ha, netdev) {
3310 if (!rar_entries)
3311 break;
3312 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3313 vfn, IXGBE_RAH_AV);
3314 count++;
3315 }
3316 }
3317 /* write the addresses in reverse order to avoid write combining */
3318 for (; rar_entries > 0 ; rar_entries--)
3319 hw->mac.ops.clear_rar(hw, rar_entries);
3320
3321 return count;
3322}
3323
9a799d71 3324/**
2c5645cf 3325 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3326 * @netdev: network interface device structure
3327 *
2c5645cf
CL		 3328 * The set_rx_method entry point is called whenever the unicast/multicast
3329 * address list or the network interface flags are updated. This routine is
3330 * responsible for configuring the hardware for proper unicast, multicast and
3331 * promiscuous mode.
9a799d71 3332 **/
7f870475 3333void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3334{
3335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3336 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3337 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3338 int count;
9a799d71
AK		 3339
3340 /* Check for Promiscuous and All Multicast modes */
3341
3342 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3343
f5dc442b 3344 /* set all bits that we expect to always be set */
3f2d1c0f 3345 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3346 fctrl |= IXGBE_FCTRL_BAM;
3347 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3348 fctrl |= IXGBE_FCTRL_PMCF;
3349
2850062a
AD		 3350 /* clear the bits we are changing the status of */
3351 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3352
9a799d71 3353 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3354 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3355 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3356 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3357 /* don't hardware filter vlans in promisc mode */
3358 ixgbe_vlan_filter_disable(adapter);
9a799d71 3359 } else {
746b9f02
PM		 3360 if (netdev->flags & IFF_ALLMULTI) {
3361 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3362 vmolr |= IXGBE_VMOLR_MPE;
3363 } else {
3364 /*
3365 * Write addresses to the MTA, if the attempt fails
25985edc 3366 * then we should just turn on promiscuous mode so
2850062a
AD		 3367 * that we can at least receive multicast traffic
3368 */
3369 hw->mac.ops.update_mc_addr_list(hw, netdev);
3370 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3371 }
5f6c0181 3372 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3373 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3374 /*
3375 * Write addresses to available RAR registers, if there is not
3376 * sufficient space to store all the addresses then enable
25985edc 3377 * unicast promiscuous mode
2850062a
AD		 3378 */
3379 count = ixgbe_write_uc_addr_list(netdev);
3380 if (count < 0) {
3381 fctrl |= IXGBE_FCTRL_UPE;
3382 vmolr |= IXGBE_VMOLR_ROPE;
3383 }
9a799d71
AK		 3384 }
3385
2850062a 3386 if (adapter->num_vfs) {
1cdd1ec8 3387 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3388 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3389 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3390 IXGBE_VMOLR_ROPE);
3391 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3392 }
3393
3f2d1c0f
BG		 3394 /* This is useful for sniffing bad packets. */
3395 if (adapter->netdev->features & NETIF_F_RXALL) {
3396 /* UPE and MPE will be handled by normal PROMISC logic
3397 * in e1000e_set_rx_mode */
3398 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3399 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3400 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3401
3402 fctrl &= ~(IXGBE_FCTRL_DPF);
3403 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3404 }
3405
2850062a 3406 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3407
3408 if (netdev->features & NETIF_F_HW_VLAN_RX)
3409 ixgbe_vlan_strip_enable(adapter);
3410 else
3411 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3412}
3413
021230d4
AV		 3414static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3415{
3416 int q_idx;
3417 struct ixgbe_q_vector *q_vector;
3418 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3419
3420 /* legacy and MSI only use one vector */
3421 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3422 q_vectors = 1;
3423
3424 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3425 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3426 napi_enable(&q_vector->napi);
021230d4
AV		 3427 }
3428}
3429
3430static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3431{
3432 int q_idx;
3433 struct ixgbe_q_vector *q_vector;
3434 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3435
3436 /* legacy and MSI only use one vector */
3437 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3438 q_vectors = 1;
3439
3440 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3441 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3442 napi_disable(&q_vector->napi);
3443 }
3444}
3445
7a6b6f51 3446#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3447/*
3448 * ixgbe_configure_dcb - Configure DCB hardware
3449 * @adapter: ixgbe adapter struct
3450 *
3451 * This is called by the driver on open to configure the DCB hardware.
3452 * This is also called by the gennetlink interface when reconfiguring
3453 * the DCB state.
3454 */
3455static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3456{
3457 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3458 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3459
67ebd791
AD		 3460 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3461 if (hw->mac.type == ixgbe_mac_82598EB)
3462 netif_set_gso_max_size(adapter->netdev, 65536);
3463 return;
3464 }
3465
3466 if (hw->mac.type == ixgbe_mac_82598EB)
3467 netif_set_gso_max_size(adapter->netdev, 32768);
3468
2f90b865 3469
2f90b865 3470 /* Enable VLAN tag insert/strip */
f62bbb5e 3471 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3472
2f90b865 3473 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3474
971060b1 3475#ifdef IXGBE_FCOE
b120818e
JF		 3476 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3477 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3478#endif
b120818e
JF		 3479
3480 /* reconfigure the hardware */
3481 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3482 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3483 DCB_TX_CONFIG);
3484 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3485 DCB_RX_CONFIG);
3486 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3487 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3488 ixgbe_dcb_hw_ets(&adapter->hw,
3489 adapter->ixgbe_ieee_ets,
3490 max_frame);
3491 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3492 adapter->ixgbe_ieee_pfc->pfc_en,
3493 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3494 }
8187cd48
JF		 3495
3496 /* Enable RSS Hash per TC */
3497 if (hw->mac.type != ixgbe_mac_82598EB) {
3498 int i;
3499 u32 reg = 0;
3500
3501 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3502 u8 msb = 0;
3503 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3504
3505 while (cnt >>= 1)
3506 msb++;
3507
3508 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3509 }
3510 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3511 }
2f90b865 3512}
9da712d2
JF		 3513#endif
3514
3515/* Additional bittime to account for IXGBE framing */
3516#define IXGBE_ETH_FRAMING 20
3517
3518/*
3519 * ixgbe_hpbthresh - calculate high water mark for flow control
3520 *
3521 * @adapter: board private structure to calculate for
3522 * @pb - packet buffer to calculate
3523 */
3524static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3525{
3526 struct ixgbe_hw *hw = &adapter->hw;
3527 struct net_device *dev = adapter->netdev;
3528 int link, tc, kb, marker;
3529 u32 dv_id, rx_pba;
3530
3531 /* Calculate max LAN frame size */
3532 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3533
3534#ifdef IXGBE_FCOE
3535 /* FCoE traffic class uses FCOE jumbo frames */
3536 if (dev->features & NETIF_F_FCOE_MTU) {
3537 int fcoe_pb = 0;
2f90b865 3538
9da712d2
JF		 3539#ifdef CONFIG_IXGBE_DCB
3540 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3541
3542#endif
3543 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3544 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3545 }
2f90b865 3546#endif
80605c65 3547
9da712d2
JF		 3548 /* Calculate delay value for device */
3549 switch (hw->mac.type) {
3550 case ixgbe_mac_X540:
3551 dv_id = IXGBE_DV_X540(link, tc);
3552 break;
3553 default:
3554 dv_id = IXGBE_DV(link, tc);
3555 break;
3556 }
3557
3558 /* Loopback switch introduces additional latency */
3559 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3560 dv_id += IXGBE_B2BT(tc);
3561
3562 /* Delay value is calculated in bit times convert to KB */
3563 kb = IXGBE_BT2KB(dv_id);
3564 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3565
3566 marker = rx_pba - kb;
3567
3568 /* It is possible that the packet buffer is not large enough
3569 * to provide required headroom. In this case throw an error
3570 * to user and a do the best we can.
3571 */
3572 if (marker < 0) {
3573 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3574 "headroom to support flow control."
3575 "Decrease MTU or number of traffic classes\n", pb);
3576 marker = tc + 1;
3577 }
3578
3579 return marker;
3580}
3581
3582/*
3583 * ixgbe_lpbthresh - calculate low water mark for for flow control
3584 *
3585 * @adapter: board private structure to calculate for
3586 * @pb - packet buffer to calculate
3587 */
3588static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3589{
3590 struct ixgbe_hw *hw = &adapter->hw;
3591 struct net_device *dev = adapter->netdev;
3592 int tc;
3593 u32 dv_id;
3594
3595 /* Calculate max LAN frame size */
3596 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3597
3598 /* Calculate delay value for device */
3599 switch (hw->mac.type) {
3600 case ixgbe_mac_X540:
3601 dv_id = IXGBE_LOW_DV_X540(tc);
3602 break;
3603 default:
3604 dv_id = IXGBE_LOW_DV(tc);
3605 break;
3606 }
3607
3608 /* Delay value is calculated in bit times convert to KB */
3609 return IXGBE_BT2KB(dv_id);
3610}
3611
3612/*
3613 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3614 */
3615static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3616{
3617 struct ixgbe_hw *hw = &adapter->hw;
3618 int num_tc = netdev_get_num_tc(adapter->netdev);
3619 int i;
3620
3621 if (!num_tc)
3622 num_tc = 1;
3623
3624 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3625
3626 for (i = 0; i < num_tc; i++) {
3627 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3628
3629 /* Low water marks must not be larger than high water marks */
3630 if (hw->fc.low_water > hw->fc.high_water[i])
3631 hw->fc.low_water = 0;
3632 }
3633}
3634
80605c65
JF		 3635static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3636{
80605c65 3637 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3638 int hdrm;
3639 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3640
3641 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3642 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3643 hdrm = 32 << adapter->fdir_pballoc;
3644 else
3645 hdrm = 0;
80605c65 3646
f7e1027f 3647 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3648 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3649}
3650
e4911d57
AD		 3651static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3652{
3653 struct ixgbe_hw *hw = &adapter->hw;
3654 struct hlist_node *node, *node2;
3655 struct ixgbe_fdir_filter *filter;
3656
3657 spin_lock(&adapter->fdir_perfect_lock);
3658
3659 if (!hlist_empty(&adapter->fdir_filter_list))
3660 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3661
3662 hlist_for_each_entry_safe(filter, node, node2,
3663 &adapter->fdir_filter_list, fdir_node) {
3664 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3665 &filter->filter,
3666 filter->sw_idx,
3667 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3668 IXGBE_FDIR_DROP_QUEUE :
3669 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3670 }
3671
3672 spin_unlock(&adapter->fdir_perfect_lock);
3673}
3674
9a799d71
AK		 3675static void ixgbe_configure(struct ixgbe_adapter *adapter)
3676{
d2f5e7f3
AS		 3677 struct ixgbe_hw *hw = &adapter->hw;
3678
80605c65 3679 ixgbe_configure_pb(adapter);
7a6b6f51 3680#ifdef CONFIG_IXGBE_DCB
67ebd791 3681 ixgbe_configure_dcb(adapter);
2f90b865 3682#endif
9a799d71 3683
4c1d7b4b 3684 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3685 ixgbe_restore_vlan(adapter);
3686
eacd73f7
YZ		 3687#ifdef IXGBE_FCOE
3688 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3689 ixgbe_configure_fcoe(adapter);
3690
3691#endif /* IXGBE_FCOE */
d2f5e7f3
AS		 3692
3693 switch (hw->mac.type) {
3694 case ixgbe_mac_82599EB:
3695 case ixgbe_mac_X540:
3696 hw->mac.ops.disable_rx_buff(hw);
3697 break;
3698 default:
3699 break;
3700 }
3701
c4cf55e5 3702 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3703 ixgbe_init_fdir_signature_82599(&adapter->hw,
3704 adapter->fdir_pballoc);
e4911d57
AD		 3705 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3706 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3707 adapter->fdir_pballoc);
3708 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3709 }
4c1d7b4b 3710
d2f5e7f3
AS		 3711 switch (hw->mac.type) {
3712 case ixgbe_mac_82599EB:
3713 case ixgbe_mac_X540:
3714 hw->mac.ops.enable_rx_buff(hw);
3715 break;
3716 default:
3717 break;
3718 }
3719
933d41f1 3720 ixgbe_configure_virtualization(adapter);
c4cf55e5 3721
9a799d71
AK		 3722 ixgbe_configure_tx(adapter);
3723 ixgbe_configure_rx(adapter);
9a799d71
AK		 3724}
3725
e8e26350
PW		 3726static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3727{
3728 switch (hw->phy.type) {
3729 case ixgbe_phy_sfp_avago:
3730 case ixgbe_phy_sfp_ftl:
3731 case ixgbe_phy_sfp_intel:
3732 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3733 case ixgbe_phy_sfp_passive_tyco:
3734 case ixgbe_phy_sfp_passive_unknown:
3735 case ixgbe_phy_sfp_active_unknown:
3736 case ixgbe_phy_sfp_ftl_active:
e8e26350 3737 return true;
8917b447
AD		 3738 case ixgbe_phy_nl:
3739 if (hw->mac.type == ixgbe_mac_82598EB)
3740 return true;
e8e26350
PW		 3741 default:
3742 return false;
3743 }
3744}
3745
0ecc061d 3746/**
e8e26350
PW		 3747 * ixgbe_sfp_link_config - set up SFP+ link
3748 * @adapter: pointer to private adapter struct
3749 **/
3750static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3751{
7086400d 3752 /*
52f33af8 3753 * We are assuming the worst case scenario here, and that
7086400d
AD		 3754 * is that an SFP was inserted/removed after the reset
3755 * but before SFP detection was enabled. As such the best
3756 * solution is to just start searching as soon as we start
3757 */
3758 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3759 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3760
7086400d 3761 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3762}
3763
3764/**
3765 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3766 * @hw: pointer to private hardware struct
3767 *
3768 * Returns 0 on success, negative on failure
3769 **/
e8e26350 3770static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3771{
3772 u32 autoneg;
8620a103 3773 bool negotiation, link_up = false;
0ecc061d
PWJ		 3774 u32 ret = IXGBE_ERR_LINK_SETUP;
3775
3776 if (hw->mac.ops.check_link)
3777 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3778
3779 if (ret)
3780 goto link_cfg_out;
3781
0b0c2b31
ET		 3782 autoneg = hw->phy.autoneg_advertised;
3783 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3784 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3785 &negotiation);
0ecc061d
PWJ		 3786 if (ret)
3787 goto link_cfg_out;
3788
8620a103
MC		 3789 if (hw->mac.ops.setup_link)
3790 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3791link_cfg_out:
3792 return ret;
3793}
3794
a34bcfff 3795static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3796{
9a799d71 3797 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3798 u32 gpie = 0;
9a799d71 3799
9b471446 3800 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3801 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3802 IXGBE_GPIE_OCD;
3803 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3804 /*
3805 * use EIAM to auto-mask when MSI-X interrupt is asserted
3806 * this saves a register write for every interrupt
3807 */
3808 switch (hw->mac.type) {
3809 case ixgbe_mac_82598EB:
3810 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3811 break;
9b471446 3812 case ixgbe_mac_82599EB:
b93a2226
DS		 3813 case ixgbe_mac_X540:
3814 default:
9b471446
JB		 3815 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3816 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3817 break;
3818 }
3819 } else {
021230d4
AV		 3820 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3821 * specifically only auto mask tx and rx interrupts */
3822 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3823 }
9a799d71 3824
a34bcfff
AD		 3825 /* XXX: to interrupt immediately for EICS writes, enable this */
3826 /* gpie |= IXGBE_GPIE_EIMEN; */
3827
3828 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3829 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3830 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3831 }
3832
5fdd31f9 3833 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3834 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3835 switch (adapter->hw.mac.type) {
3836 case ixgbe_mac_82599EB:
3837 gpie |= IXGBE_SDP0_GPIEN;
3838 break;
3839 case ixgbe_mac_X540:
3840 gpie |= IXGBE_EIMS_TS;
3841 break;
3842 default:
3843 break;
3844 }
3845 }
5fdd31f9 3846
a34bcfff
AD		 3847 /* Enable fan failure interrupt */
3848 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3849 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3850
2698b208 3851 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3852 gpie |= IXGBE_SDP1_GPIEN;
3853 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3854 }
a34bcfff
AD		 3855
3856 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3857}
3858
c7ccde0f 3859static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3860{
3861 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3862 int err;
a34bcfff
AD		 3863 u32 ctrl_ext;
3864
3865 ixgbe_get_hw_control(adapter);
3866 ixgbe_setup_gpie(adapter);
e8e26350 3867
9a799d71
AK		 3868 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3869 ixgbe_configure_msix(adapter);
3870 else
3871 ixgbe_configure_msi_and_legacy(adapter);
3872
c6ecf39a
DS		 3873 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3874 if (hw->mac.ops.enable_tx_laser &&
3875 ((hw->phy.multispeed_fiber) ||
9f911707 3876 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3877 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3878 hw->mac.ops.enable_tx_laser(hw);
3879
9a799d71 3880 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3881 ixgbe_napi_enable_all(adapter);
3882
73c4b7cd
AD		 3883 if (ixgbe_is_sfp(hw)) {
3884 ixgbe_sfp_link_config(adapter);
3885 } else {
3886 err = ixgbe_non_sfp_link_config(hw);
3887 if (err)
3888 e_err(probe, "link_config FAILED %d\n", err);
3889 }
3890
021230d4
AV		 3891 /* clear any pending interrupts, may auto mask */
3892 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3893 ixgbe_irq_enable(adapter, true, true);
9a799d71 3894
bf069c97
DS		 3895 /*
3896 * If this adapter has a fan, check to see if we had a failure
3897 * before we enabled the interrupt.
3898 */
3899 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3900 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3901 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3902 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3903 }
3904
1da100bb 3905 /* enable transmits */
477de6ed 3906 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3907
9a799d71
AK		 3908 /* bring the link up in the watchdog, this could race with our first
3909 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3910 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3911 adapter->link_check_timeout = jiffies;
7086400d 3912 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3913
3914 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3915 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3916 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3917 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3918}
3919
d4f80882
AV		 3920void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3921{
3922 WARN_ON(in_interrupt());
7086400d
AD		 3923 /* put off any impending NetWatchDogTimeout */
3924 adapter->netdev->trans_start = jiffies;
3925
d4f80882 3926 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3927 usleep_range(1000, 2000);
d4f80882 3928 ixgbe_down(adapter);
5809a1ae
GR		 3929 /*
3930 * If SR-IOV enabled then wait a bit before bringing the adapter
3931 * back up to give the VFs time to respond to the reset. The
3932 * two second wait is based upon the watchdog timer cycle in
3933 * the VF driver.
3934 */
3935 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3936 msleep(2000);
d4f80882
AV		 3937 ixgbe_up(adapter);
3938 clear_bit(__IXGBE_RESETTING, &adapter->state);
3939}
3940
c7ccde0f 3941void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3942{
3943 /* hardware has been reset, we need to reload some things */
3944 ixgbe_configure(adapter);
3945
c7ccde0f 3946 ixgbe_up_complete(adapter);
9a799d71
AK		 3947}
3948
3949void ixgbe_reset(struct ixgbe_adapter *adapter)
3950{
c44ade9e 3951 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3952 int err;
3953
7086400d
AD		 3954 /* lock SFP init bit to prevent race conditions with the watchdog */
3955 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3956 usleep_range(1000, 2000);
3957
3958 /* clear all SFP and link config related flags while holding SFP_INIT */
3959 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3960 IXGBE_FLAG2_SFP_NEEDS_RESET);
3961 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3962
8ca783ab 3963 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3964 switch (err) {
3965 case 0:
3966 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3967 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3968 break;
3969 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3970 e_dev_err("master disable timed out\n");
da4dd0f7 3971 break;
794caeb2
PWJ		 3972 case IXGBE_ERR_EEPROM_VERSION:
3973 /* We are running on a pre-production device, log a warning */
849c4542 3974 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 3975 "Please be aware there may be issues associated with "
849c4542
ET		 3976 "your hardware. If you are experiencing problems "
3977 "please contact your Intel or hardware "
3978 "representative who provided you with this "
3979 "hardware.\n");
794caeb2 3980 break;
da4dd0f7 3981 default:
849c4542 3982 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3983 }
9a799d71 3984
7086400d
AD		 3985 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3986
9a799d71 3987 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3988 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3989 IXGBE_RAH_AV);
9a799d71
AK		 3990}
3991
f800326d
AD		 3992/**
3993 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
3994 * @rx_ring: ring to setup
3995 *
3996 * On many IA platforms the L1 cache has a critical stride of 4K, this
3997 * results in each receive buffer starting in the same cache set. To help
3998 * reduce the pressure on this cache set we can interleave the offsets so
3999 * that only every other buffer will be in the same cache set.
4000 **/
4001static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4002{
4003 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4004 u16 i;
4005
4006 for (i = 0; i < rx_ring->count; i += 2) {
4007 rx_buffer[0].page_offset = 0;
4008 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4009 rx_buffer = &rx_buffer[2];
4010 }
4011}
4012
9a799d71
AK		 4013/**
4014 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4015 * @rx_ring: ring to free buffers from
4016 **/
b6ec895e 4017static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4018{
b6ec895e 4019 struct device *dev = rx_ring->dev;
9a799d71 4020 unsigned long size;
b6ec895e 4021 u16 i;
9a799d71 4022
84418e3b
AD		 4023 /* ring already cleared, nothing to do */
4024 if (!rx_ring->rx_buffer_info)
4025 return;
9a799d71 4026
84418e3b 4027 /* Free all the Rx ring sk_buffs */
9a799d71 4028 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4029 struct ixgbe_rx_buffer *rx_buffer;
4030
4031 rx_buffer = &rx_ring->rx_buffer_info[i];
4032 if (rx_buffer->skb) {
4033 struct sk_buff *skb = rx_buffer->skb;
4034 if (IXGBE_CB(skb)->page_released) {
4035 dma_unmap_page(dev,
4036 IXGBE_CB(skb)->dma,
4037 ixgbe_rx_bufsz(rx_ring),
4038 DMA_FROM_DEVICE);
4039 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4040 }
4041 dev_kfree_skb(skb);
9a799d71 4042 }
f800326d
AD		 4043 rx_buffer->skb = NULL;
4044 if (rx_buffer->dma)
4045 dma_unmap_page(dev, rx_buffer->dma,
4046 ixgbe_rx_pg_size(rx_ring),
4047 DMA_FROM_DEVICE);
4048 rx_buffer->dma = 0;
4049 if (rx_buffer->page)
4050 put_page(rx_buffer->page);
4051 rx_buffer->page = NULL;
9a799d71
AK		 4052 }
4053
4054 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4055 memset(rx_ring->rx_buffer_info, 0, size);
4056
f800326d
AD		 4057 ixgbe_init_rx_page_offset(rx_ring);
4058
9a799d71
AK		 4059 /* Zero out the descriptor ring */
4060 memset(rx_ring->desc, 0, rx_ring->size);
4061
f800326d 4062 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4063 rx_ring->next_to_clean = 0;
4064 rx_ring->next_to_use = 0;
9a799d71
AK		 4065}
4066
4067/**
4068 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4069 * @tx_ring: ring to be cleaned
4070 **/
b6ec895e 4071static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4072{
4073 struct ixgbe_tx_buffer *tx_buffer_info;
4074 unsigned long size;
b6ec895e 4075 u16 i;
9a799d71 4076
84418e3b
AD		 4077 /* ring already cleared, nothing to do */
4078 if (!tx_ring->tx_buffer_info)
4079 return;
9a799d71 4080
84418e3b 4081 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4082 for (i = 0; i < tx_ring->count; i++) {
4083 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4084 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4085 }
4086
4087 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4088 memset(tx_ring->tx_buffer_info, 0, size);
4089
4090 /* Zero out the descriptor ring */
4091 memset(tx_ring->desc, 0, tx_ring->size);
4092
4093 tx_ring->next_to_use = 0;
4094 tx_ring->next_to_clean = 0;
9a799d71
AK		 4095}
4096
4097/**
021230d4 4098 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4099 * @adapter: board private structure
4100 **/
021230d4 4101static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4102{
4103 int i;
4104
021230d4 4105 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4106 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4107}
4108
4109/**
021230d4 4110 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4111 * @adapter: board private structure
4112 **/
021230d4 4113static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4114{
4115 int i;
4116
021230d4 4117 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4118 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4119}
4120
e4911d57
AD		 4121static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4122{
4123 struct hlist_node *node, *node2;
4124 struct ixgbe_fdir_filter *filter;
4125
4126 spin_lock(&adapter->fdir_perfect_lock);
4127
4128 hlist_for_each_entry_safe(filter, node, node2,
4129 &adapter->fdir_filter_list, fdir_node) {
4130 hlist_del(&filter->fdir_node);
4131 kfree(filter);
4132 }
4133 adapter->fdir_filter_count = 0;
4134
4135 spin_unlock(&adapter->fdir_perfect_lock);
4136}
4137
9a799d71
AK		 4138void ixgbe_down(struct ixgbe_adapter *adapter)
4139{
4140 struct net_device *netdev = adapter->netdev;
7f821875 4141 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4142 u32 rxctrl;
bf29ee6c 4143 int i;
9a799d71
AK		 4144
4145 /* signal that we are down to the interrupt handler */
4146 set_bit(__IXGBE_DOWN, &adapter->state);
4147
4148 /* disable receives */
7f821875
JB		 4149 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4150 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4151
2d39d576
YZ		 4152 /* disable all enabled rx queues */
4153 for (i = 0; i < adapter->num_rx_queues; i++)
4154 /* this call also flushes the previous write */
4155 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4156
032b4325 4157 usleep_range(10000, 20000);
9a799d71 4158
7f821875
JB		 4159 netif_tx_stop_all_queues(netdev);
4160
7086400d 4161 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4162 netif_carrier_off(netdev);
4163 netif_tx_disable(netdev);
4164
4165 ixgbe_irq_disable(adapter);
4166
4167 ixgbe_napi_disable_all(adapter);
4168
d034acf1
AD		 4169 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4170 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4171 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4172
4173 del_timer_sync(&adapter->service_timer);
4174
34cecbbf 4175 if (adapter->num_vfs) {
8e34d1aa
AD		 4176 /* Clear EITR Select mapping */
4177 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4178
4179 /* Mark all the VFs as inactive */
4180 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4181 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4182
34cecbbf
AD		 4183 /* ping all the active vfs to let them know we are going down */
4184 ixgbe_ping_all_vfs(adapter);
4185
4186 /* Disable all VFTE/VFRE TX/RX */
4187 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4188 }
4189
7f821875
JB		 4190 /* disable transmits in the hardware now that interrupts are off */
4191 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4192 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4193 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4194 }
34cecbbf
AD		 4195
4196 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4197 switch (hw->mac.type) {
4198 case ixgbe_mac_82599EB:
b93a2226 4199 case ixgbe_mac_X540:
88512539 4200 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4201 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4202 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4203 break;
4204 default:
4205 break;
4206 }
7f821875 4207
6f4a0e45
PL		 4208 if (!pci_channel_offline(adapter->pdev))
4209 ixgbe_reset(adapter);
c6ecf39a
DS		 4210
4211 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4212 if (hw->mac.ops.disable_tx_laser &&
4213 ((hw->phy.multispeed_fiber) ||
9f911707 4214 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4215 (hw->mac.type == ixgbe_mac_82599EB))))
4216 hw->mac.ops.disable_tx_laser(hw);
4217
9a799d71
AK		 4218 ixgbe_clean_all_tx_rings(adapter);
4219 ixgbe_clean_all_rx_rings(adapter);
4220
5dd2d332 4221#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4222 /* since we reset the hardware DCA settings were cleared */
e35ec126 4223 ixgbe_setup_dca(adapter);
96b0e0f6 4224#endif
9a799d71
AK		 4225}
4226
9a799d71 4227/**
021230d4
AV		 4228 * ixgbe_poll - NAPI Rx polling callback
4229 * @napi: structure for representing this polling device
4230 * @budget: how many packets driver is allowed to clean
4231 *
4232 * This function is used for legacy and MSI, NAPI mode
9a799d71 4233 **/
021230d4 4234static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4235{
9a1a69ad 4236 struct ixgbe_q_vector *q_vector =
e8e9f696 4237 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4238 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4239 struct ixgbe_ring *ring;
4240 int per_ring_budget;
4241 bool clean_complete = true;
9a799d71 4242
5dd2d332 4243#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4244 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4245 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4246#endif
4247
a557928e 4248 ixgbe_for_each_ring(ring, q_vector->tx)
4ff7fb12 4249 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4250
4ff7fb12
AD		 4251 /* attempt to distribute budget to each queue fairly, but don't allow
4252 * the budget to go below 1 because we'll exit polling */
4253 if (q_vector->rx.count > 1)
4254 per_ring_budget = max(budget/q_vector->rx.count, 1);
4255 else
4256 per_ring_budget = budget;
d2c7ddd6 4257
a557928e 4258 ixgbe_for_each_ring(ring, q_vector->rx)
4ff7fb12
AD		 4259 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4260 per_ring_budget);
4261
4262 /* If all work not completed, return budget and keep polling */
4263 if (!clean_complete)
4264 return budget;
4265
4266 /* all work done, exit the polling mode */
4267 napi_complete(napi);
4268 if (adapter->rx_itr_setting & 1)
4269 ixgbe_set_itr(q_vector);
4270 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4271 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4272
4273 return 0;
9a799d71
AK		 4274}
4275
4276/**
4277 * ixgbe_tx_timeout - Respond to a Tx Hang
4278 * @netdev: network interface device structure
4279 **/
4280static void ixgbe_tx_timeout(struct net_device *netdev)
4281{
4282 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4283
4284 /* Do the reset outside of interrupt context */
c83c6cbd 4285 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4286}
4287
4df10466
JB		 4288/**
4289 * ixgbe_set_rss_queues: Allocate queues for RSS
4290 * @adapter: board private structure to initialize
4291 *
4292 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4293 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4294 *
4295 **/
bc97114d
PWJ		 4296static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4297{
4298 bool ret = false;
0cefafad 4299 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4300
4301 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4302 f->mask = 0xF;
4303 adapter->num_rx_queues = f->indices;
4304 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4305 ret = true;
4306 } else {
bc97114d 4307 ret = false;
b9804972
JB		 4308 }
4309
bc97114d
PWJ		 4310 return ret;
4311}
4312
c4cf55e5
PWJ		 4313/**
4314 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4315 * @adapter: board private structure to initialize
4316 *
4317 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4318 * to the original CPU that initiated the Tx session. This runs in addition
4319 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4320 * Rx load across CPUs using RSS.
4321 *
4322 **/
e8e9f696 4323static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4324{
4325 bool ret = false;
4326 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4327
4328 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4329 f_fdir->mask = 0;
4330
24ddd967
AD		 4331 /*
4332 * Use RSS in addition to Flow Director to ensure the best
4333 * distribution of flows across cores, even when an FDIR flow
4334 * isn't matched.
4335 */
03ecf91a
AD		 4336 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4337 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4338 adapter->num_tx_queues = f_fdir->indices;
4339 adapter->num_rx_queues = f_fdir->indices;
4340 ret = true;
4341 } else {
4342 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4343 }
4344 return ret;
4345}
4346
0331a832
YZ		 4347#ifdef IXGBE_FCOE
4348/**
4349 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4350 * @adapter: board private structure to initialize
4351 *
4352 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4353 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4354 * rx queues out of the max number of rx queues, instead, it is used as the
4355 * index of the first rx queue used by FCoE.
4356 *
4357 **/
4358static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4359{
0331a832
YZ		 4360 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4361
e5b64635
JF		 4362 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4363 return false;
4364
3ed69d7e 4365 f->indices = min_t(int, num_online_cpus(), f->indices);
e5b64635 4366
e901acd6
JF		 4367 adapter->num_rx_queues = 1;
4368 adapter->num_tx_queues = 1;
e5b64635 4369
e901acd6
JF		 4370 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4371 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4372 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4373 ixgbe_set_fdir_queues(adapter);
4374 else
4375 ixgbe_set_rss_queues(adapter);
e5b64635 4376 }
03ecf91a 4377
e901acd6
JF		 4378 /* adding FCoE rx rings to the end */
4379 f->mask = adapter->num_rx_queues;
4380 adapter->num_rx_queues += f->indices;
4381 adapter->num_tx_queues += f->indices;
0331a832 4382
e5b64635
JF		 4383 return true;
4384}
4385#endif /* IXGBE_FCOE */
4386
e901acd6
JF		 4387/* Artificial max queue cap per traffic class in DCB mode */
4388#define DCB_QUEUE_CAP 8
4389
e5b64635
JF		 4390#ifdef CONFIG_IXGBE_DCB
4391static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4392{
e901acd6
JF		 4393 int per_tc_q, q, i, offset = 0;
4394 struct net_device *dev = adapter->netdev;
4395 int tcs = netdev_get_num_tc(dev);
e5b64635 4396
e901acd6
JF		 4397 if (!tcs)
4398 return false;
e5b64635 4399
e901acd6 4400 /* Map queue offset and counts onto allocated tx queues */
3ed69d7e
JB		 4401 per_tc_q = min_t(unsigned int, dev->num_tx_queues / tcs, DCB_QUEUE_CAP);
4402 q = min_t(int, num_online_cpus(), per_tc_q);
8b1c0b24 4403
8b1c0b24 4404 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4405 netdev_set_tc_queue(dev, i, q, offset);
4406 offset += q;
0331a832
YZ		 4407 }
4408
e901acd6
JF		 4409 adapter->num_tx_queues = q * tcs;
4410 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4411
4412#ifdef IXGBE_FCOE
e901acd6
JF		 4413 /* FCoE enabled queues require special configuration indexed
4414 * by feature specific indices and mask. Here we map FCoE
4415 * indices onto the DCB queue pairs allowing FCoE to own
4416 * configuration later.
e5b64635 4417 */
e901acd6 4418 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
cdf485be 4419 u8 prio_tc[MAX_USER_PRIORITY] = {0};
e901acd6
JF		 4420 int tc;
4421 struct ixgbe_ring_feature *f =
4422 &adapter->ring_feature[RING_F_FCOE];
4423
cdf485be
JF		 4424 ixgbe_dcb_unpack_map(&adapter->dcb_cfg, DCB_TX_CONFIG, prio_tc);
4425 tc = prio_tc[adapter->fcoe.up];
e901acd6
JF		 4426 f->indices = dev->tc_to_txq[tc].count;
4427 f->mask = dev->tc_to_txq[tc].offset;
4428 }
e5b64635
JF		 4429#endif
4430
e901acd6 4431 return true;
0331a832 4432}
e5b64635 4433#endif
0331a832 4434
1cdd1ec8
GR		 4435/**
4436 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4437 * @adapter: board private structure to initialize
4438 *
4439 * IOV doesn't actually use anything, so just NAK the
4440 * request for now and let the other queue routines
4441 * figure out what to do.
4442 */
4443static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4444{
4445 return false;
4446}
4447
4df10466 4448/*
25985edc 4449 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4450 * @adapter: board private structure to initialize
4451 *
4452 * This is the top level queue allocation routine. The order here is very
4453 * important, starting with the "most" number of features turned on at once,
4454 * and ending with the smallest set of features. This way large combinations
4455 * can be allocated if they're turned on, and smaller combinations are the
4456 * fallthrough conditions.
4457 *
4458 **/
847f53ff 4459static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4460{
1cdd1ec8
GR		 4461 /* Start with base case */
4462 adapter->num_rx_queues = 1;
4463 adapter->num_tx_queues = 1;
4464 adapter->num_rx_pools = adapter->num_rx_queues;
4465 adapter->num_rx_queues_per_pool = 1;
4466
4467 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4468 goto done;
1cdd1ec8 4469
bc97114d
PWJ		 4470#ifdef CONFIG_IXGBE_DCB
4471 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4472 goto done;
bc97114d
PWJ		 4473
4474#endif
e5b64635
JF		 4475#ifdef IXGBE_FCOE
4476 if (ixgbe_set_fcoe_queues(adapter))
4477 goto done;
4478
4479#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4480 if (ixgbe_set_fdir_queues(adapter))
4481 goto done;
4482
bc97114d 4483 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4484 goto done;
4485
4486 /* fallback to base case */
4487 adapter->num_rx_queues = 1;
4488 adapter->num_tx_queues = 1;
4489
4490done:
9d837ea2
YZ		 4491 if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) ||
4492 (adapter->netdev->reg_state == NETREG_UNREGISTERING))
4493 return 0;
4494
847f53ff 4495 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4496 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4497 return netif_set_real_num_rx_queues(adapter->netdev,
4498 adapter->num_rx_queues);
b9804972
JB		 4499}
4500
021230d4 4501static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4502 int vectors)
021230d4
AV		 4503{
4504 int err, vector_threshold;
4505
8f15486d
AD		 4506 /* We'll want at least 2 (vector_threshold):
4507 * 1) TxQ[0] + RxQ[0] handler
4508 * 2) Other (Link Status Change, etc.)
021230d4
AV		 4509 */
4510 vector_threshold = MIN_MSIX_COUNT;
4511
24ddd967
AD		 4512 /*
4513 * The more we get, the more we will assign to Tx/Rx Cleanup
021230d4
AV		 4514 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4515 * Right now, we simply care about how many we'll get; we'll
4516 * set them up later while requesting irq's.
4517 */
4518 while (vectors >= vector_threshold) {
4519 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4520 vectors);
021230d4
AV		 4521 if (!err) /* Success in acquiring all requested vectors. */
4522 break;
4523 else if (err < 0)
4524 vectors = 0; /* Nasty failure, quit now */
4525 else /* err == number of vectors we should try again with */
4526 vectors = err;
4527 }
4528
4529 if (vectors < vector_threshold) {
4530 /* Can't allocate enough MSI-X interrupts? Oh well.
4531 * This just means we'll go with either a single MSI
4532 * vector or fall back to legacy interrupts.
4533 */
849c4542
ET		 4534 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4535 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4536 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4537 kfree(adapter->msix_entries);
4538 adapter->msix_entries = NULL;
021230d4
AV		 4539 } else {
4540 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4541 /*
4542 * Adjust for only the vectors we'll use, which is minimum
4543 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4544 * vectors we were allocated.
4545 */
4546 adapter->num_msix_vectors = min(vectors,
e8e9f696 4547 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4548 }
4549}
4550
021230d4 4551/**
bc97114d 4552 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4553 * @adapter: board private structure to initialize
4554 *
bc97114d
PWJ		 4555 * Cache the descriptor ring offsets for RSS to the assigned rings.
4556 *
021230d4 4557 **/
bc97114d 4558static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4559{
bc97114d 4560 int i;
bc97114d 4561
9d6b758f
AD		 4562 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4563 return false;
bc97114d 4564
9d6b758f
AD		 4565 for (i = 0; i < adapter->num_rx_queues; i++)
4566 adapter->rx_ring[i]->reg_idx = i;
4567 for (i = 0; i < adapter->num_tx_queues; i++)
4568 adapter->tx_ring[i]->reg_idx = i;
4569
4570 return true;
bc97114d
PWJ		 4571}
4572
4573#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4574
4575/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4576static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4577 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4578{
4579 struct net_device *dev = adapter->netdev;
4580 struct ixgbe_hw *hw = &adapter->hw;
4581 u8 num_tcs = netdev_get_num_tc(dev);
4582
4583 *tx = 0;
4584 *rx = 0;
4585
4586 switch (hw->mac.type) {
4587 case ixgbe_mac_82598EB:
aba70d5e
JF		 4588 *tx = tc << 2;
4589 *rx = tc << 3;
e5b64635
JF		 4590 break;
4591 case ixgbe_mac_82599EB:
4592 case ixgbe_mac_X540:
4fa2e0e1 4593 if (num_tcs > 4) {
e5b64635
JF		 4594 if (tc < 3) {
4595 *tx = tc << 5;
4596 *rx = tc << 4;
4597 } else if (tc < 5) {
4598 *tx = ((tc + 2) << 4);
4599 *rx = tc << 4;
4600 } else if (tc < num_tcs) {
4601 *tx = ((tc + 8) << 3);
4602 *rx = tc << 4;
4603 }
4fa2e0e1 4604 } else {
e5b64635
JF		 4605 *rx = tc << 5;
4606 switch (tc) {
4607 case 0:
4608 *tx = 0;
4609 break;
4610 case 1:
4611 *tx = 64;
4612 break;
4613 case 2:
4614 *tx = 96;
4615 break;
4616 case 3:
4617 *tx = 112;
4618 break;
4619 default:
4620 break;
4621 }
4622 }
4623 break;
4624 default:
4625 break;
4626 }
4627}
4628
bc97114d
PWJ		 4629/**
4630 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4631 * @adapter: board private structure to initialize
4632 *
4633 * Cache the descriptor ring offsets for DCB to the assigned rings.
4634 *
4635 **/
4636static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4637{
e5b64635
JF		 4638 struct net_device *dev = adapter->netdev;
4639 int i, j, k;
4640 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4641
8b1c0b24 4642 if (!num_tcs)
bd508178 4643 return false;
f92ef202 4644
e5b64635
JF		 4645 for (i = 0, k = 0; i < num_tcs; i++) {
4646 unsigned int tx_s, rx_s;
4647 u16 count = dev->tc_to_txq[i].count;
4648
4649 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4650 for (j = 0; j < count; j++, k++) {
4651 adapter->tx_ring[k]->reg_idx = tx_s + j;
4652 adapter->rx_ring[k]->reg_idx = rx_s + j;
4653 adapter->tx_ring[k]->dcb_tc = i;
4654 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4655 }
021230d4 4656 }
e5b64635
JF		 4657
4658 return true;
bc97114d
PWJ		 4659}
4660#endif
4661
c4cf55e5
PWJ		 4662/**
4663 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4664 * @adapter: board private structure to initialize
4665 *
4666 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4667 *
4668 **/
e8e9f696 4669static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4670{
4671 int i;
4672 bool ret = false;
4673
03ecf91a
AD		 4674 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4675 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4676 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4677 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4678 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4679 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4680 ret = true;
4681 }
4682
4683 return ret;
4684}
4685
0331a832
YZ		 4686#ifdef IXGBE_FCOE
4687/**
4688 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4689 * @adapter: board private structure to initialize
4690 *
4691 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4692 *
4693 */
4694static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4695{
0331a832 4696 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4697 int i;
4698 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4699
4700 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4701 return false;
0331a832 4702
bf29ee6c 4703 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4704 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4705 ixgbe_cache_ring_fdir(adapter);
4706 else
4707 ixgbe_cache_ring_rss(adapter);
8faa2a78 4708
bf29ee6c
AD		 4709 fcoe_rx_i = f->mask;
4710 fcoe_tx_i = f->mask;
0331a832 4711 }
bf29ee6c
AD		 4712 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4713 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4714 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4715 }
4716 return true;
0331a832
YZ		 4717}
4718
4719#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4720/**
4721 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4722 * @adapter: board private structure to initialize
4723 *
4724 * SR-IOV doesn't use any descriptor rings but changes the default if
4725 * no other mapping is used.
4726 *
4727 */
4728static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4729{
4a0b9ca0
PW		 4730 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4731 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4732 if (adapter->num_vfs)
4733 return true;
4734 else
4735 return false;
4736}
4737
bc97114d
PWJ		 4738/**
4739 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4740 * @adapter: board private structure to initialize
4741 *
4742 * Once we know the feature-set enabled for the device, we'll cache
4743 * the register offset the descriptor ring is assigned to.
4744 *
4745 * Note, the order the various feature calls is important. It must start with
4746 * the "most" features enabled at the same time, then trickle down to the
4747 * least amount of features turned on at once.
4748 **/
4749static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4750{
4751 /* start with default case */
4a0b9ca0
PW		 4752 adapter->rx_ring[0]->reg_idx = 0;
4753 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4754
1cdd1ec8
GR		 4755 if (ixgbe_cache_ring_sriov(adapter))
4756 return;
4757
e5b64635
JF		 4758#ifdef CONFIG_IXGBE_DCB
4759 if (ixgbe_cache_ring_dcb(adapter))
4760 return;
4761#endif
4762
0331a832
YZ		 4763#ifdef IXGBE_FCOE
4764 if (ixgbe_cache_ring_fcoe(adapter))
4765 return;
0331a832 4766#endif /* IXGBE_FCOE */
bc97114d 4767
c4cf55e5
PWJ		 4768 if (ixgbe_cache_ring_fdir(adapter))
4769 return;
4770
bc97114d
PWJ		 4771 if (ixgbe_cache_ring_rss(adapter))
4772 return;
021230d4
AV		 4773}
4774
021230d4
AV		 4775/**
4776 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4777 * @adapter: board private structure to initialize
4778 *
4779 * Attempt to configure the interrupts using the best available
4780 * capabilities of the hardware and the kernel.
4781 **/
feea6a57 4782static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4783{
8be0e467 4784 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4785 int err = 0;
4786 int vector, v_budget;
4787
4788 /*
4789 * It's easy to be greedy for MSI-X vectors, but it really
4790 * doesn't do us much good if we have a lot more vectors
4791 * than CPU's. So let's be conservative and only ask for
342bde1b 4792 * (roughly) the same number of vectors as there are CPU's.
8f15486d 4793 * The default is to use pairs of vectors.
021230d4 4794 */
8f15486d
AD		 4795 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues);
4796 v_budget = min_t(int, v_budget, num_online_cpus());
4797 v_budget += NON_Q_VECTORS;
021230d4
AV		 4798
4799 /*
4800 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4801 * hw.mac->max_msix_vectors vectors. With features
4802 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4803 * descriptor queues supported by our device. Thus, we cap it off in
4804 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4805 */
de88eeeb 4806 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors);
021230d4
AV		 4807
4808 /* A failure in MSI-X entry allocation isn't fatal, but it does
4809 * mean we disable MSI-X capabilities of the adapter. */
4810 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4811 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4812 if (adapter->msix_entries) {
4813 for (vector = 0; vector < v_budget; vector++)
4814 adapter->msix_entries[vector].entry = vector;
021230d4 4815
7a921c93 4816 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4817
7a921c93
AD		 4818 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4819 goto out;
4820 }
26d27844 4821
7a921c93
AD		 4822 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4823 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4824 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4825 e_err(probe,
03ecf91a 4826 "ATR is not supported while multiple "
45b9f509
AD		 4827 "queues are disabled. Disabling Flow Director\n");
4828 }
c4cf55e5 4829 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4830 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4831 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4832 ixgbe_disable_sriov(adapter);
4833
847f53ff
BH		 4834 err = ixgbe_set_num_queues(adapter);
4835 if (err)
4836 return err;
021230d4 4837
021230d4
AV		 4838 err = pci_enable_msi(adapter->pdev);
4839 if (!err) {
4840 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4841 } else {
849c4542
ET		 4842 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4843 "Unable to allocate MSI interrupt, "
4844 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4845 /* reset err */
4846 err = 0;
4847 }
4848
4849out:
021230d4
AV		 4850 return err;
4851}
4852
de88eeeb
AD		 4853static void ixgbe_add_ring(struct ixgbe_ring *ring,
4854 struct ixgbe_ring_container *head)
4855{
4856 ring->next = head->ring;
4857 head->ring = ring;
4858 head->count++;
4859}
4860
4861/**
4862 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
4863 * @adapter: board private structure to initialize
4864 * @v_idx: index of vector in adapter struct
4865 *
4866 * We allocate one q_vector. If allocation fails we return -ENOMEM.
4867 **/
4868static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, int v_idx,
4869 int txr_count, int txr_idx,
4870 int rxr_count, int rxr_idx)
4871{
4872 struct ixgbe_q_vector *q_vector;
4873 struct ixgbe_ring *ring;
4874 int node = -1;
4875 int cpu = -1;
4876 int ring_count, size;
4877
4878 ring_count = txr_count + rxr_count;
4879 size = sizeof(struct ixgbe_q_vector) +
4880 (sizeof(struct ixgbe_ring) * ring_count);
4881
4882 /* customize cpu for Flow Director mapping */
4883 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4884 if (cpu_online(v_idx)) {
4885 cpu = v_idx;
4886 node = cpu_to_node(cpu);
4887 }
4888 }
4889
4890 /* allocate q_vector and rings */
4891 q_vector = kzalloc_node(size, GFP_KERNEL, node);
4892 if (!q_vector)
4893 q_vector = kzalloc(size, GFP_KERNEL);
4894 if (!q_vector)
4895 return -ENOMEM;
4896
4897 /* setup affinity mask and node */
4898 if (cpu != -1)
4899 cpumask_set_cpu(cpu, &q_vector->affinity_mask);
4900 else
4901 cpumask_copy(&q_vector->affinity_mask, cpu_online_mask);
4902 q_vector->numa_node = node;
4903
4904 /* initialize NAPI */
4905 netif_napi_add(adapter->netdev, &q_vector->napi,
4906 ixgbe_poll, 64);
4907
4908 /* tie q_vector and adapter together */
4909 adapter->q_vector[v_idx] = q_vector;
4910 q_vector->adapter = adapter;
4911 q_vector->v_idx = v_idx;
4912
4913 /* initialize work limits */
4914 q_vector->tx.work_limit = adapter->tx_work_limit;
4915
4916 /* initialize pointer to rings */
4917 ring = q_vector->ring;
4918
4919 while (txr_count) {
4920 /* assign generic ring traits */
4921 ring->dev = &adapter->pdev->dev;
4922 ring->netdev = adapter->netdev;
4923
4924 /* configure backlink on ring */
4925 ring->q_vector = q_vector;
4926
4927 /* update q_vector Tx values */
4928 ixgbe_add_ring(ring, &q_vector->tx);
4929
4930 /* apply Tx specific ring traits */
4931 ring->count = adapter->tx_ring_count;
4932 ring->queue_index = txr_idx;
4933
4934 /* assign ring to adapter */
4935 adapter->tx_ring[txr_idx] = ring;
4936
4937 /* update count and index */
4938 txr_count--;
4939 txr_idx++;
4940
4941 /* push pointer to next ring */
4942 ring++;
4943 }
4944
4945 while (rxr_count) {
4946 /* assign generic ring traits */
4947 ring->dev = &adapter->pdev->dev;
4948 ring->netdev = adapter->netdev;
4949
4950 /* configure backlink on ring */
4951 ring->q_vector = q_vector;
4952
4953 /* update q_vector Rx values */
4954 ixgbe_add_ring(ring, &q_vector->rx);
4955
4956 /*
4957 * 82599 errata, UDP frames with a 0 checksum
4958 * can be marked as checksum errors.
4959 */
4960 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4961 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
4962
4963 /* apply Rx specific ring traits */
4964 ring->count = adapter->rx_ring_count;
4965 ring->queue_index = rxr_idx;
4966
4967 /* assign ring to adapter */
4968 adapter->rx_ring[rxr_idx] = ring;
4969
4970 /* update count and index */
4971 rxr_count--;
4972 rxr_idx++;
4973
4974 /* push pointer to next ring */
4975 ring++;
4976 }
4977
4978 return 0;
4979}
4980
4981/**
4982 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
4983 * @adapter: board private structure to initialize
4984 * @v_idx: Index of vector to be freed
4985 *
4986 * This function frees the memory allocated to the q_vector. In addition if
4987 * NAPI is enabled it will delete any references to the NAPI struct prior
4988 * to freeing the q_vector.
4989 **/
4990static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx)
4991{
4992 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4993 struct ixgbe_ring *ring;
4994
a557928e 4995 ixgbe_for_each_ring(ring, q_vector->tx)
de88eeeb
AD		 4996 adapter->tx_ring[ring->queue_index] = NULL;
4997
a557928e 4998 ixgbe_for_each_ring(ring, q_vector->rx)
de88eeeb
AD		 4999 adapter->rx_ring[ring->queue_index] = NULL;
5000
5001 adapter->q_vector[v_idx] = NULL;
5002 netif_napi_del(&q_vector->napi);
5003
5004 /*
5005 * ixgbe_get_stats64() might access the rings on this vector,
5006 * we must wait a grace period before freeing it.
5007 */
5008 kfree_rcu(q_vector, rcu);
5009}
5010
7a921c93
AD		 5011/**
5012 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
5013 * @adapter: board private structure to initialize
5014 *
5015 * We allocate one q_vector per queue interrupt. If allocation fails we
5016 * return -ENOMEM.
5017 **/
5018static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
5019{
de88eeeb
AD		 5020 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5021 int rxr_remaining = adapter->num_rx_queues;
5022 int txr_remaining = adapter->num_tx_queues;
5023 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
5024 int err;
7a921c93 5025
de88eeeb
AD		 5026 /* only one q_vector if MSI-X is disabled. */
5027 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
5028 q_vectors = 1;
7a921c93 5029
de88eeeb
AD		 5030 if (q_vectors >= (rxr_remaining + txr_remaining)) {
5031 for (; rxr_remaining; v_idx++, q_vectors--) {
5032 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors);
5033 err = ixgbe_alloc_q_vector(adapter, v_idx,
5034 0, 0, rqpv, rxr_idx);
4ff7fb12 5035
de88eeeb
AD		 5036 if (err)
5037 goto err_out;
5038
5039 /* update counts and index */
5040 rxr_remaining -= rqpv;
5041 rxr_idx += rqpv;
5042 }
5043 }
4ff7fb12 5044
de88eeeb
AD		 5045 for (; q_vectors; v_idx++, q_vectors--) {
5046 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors);
5047 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors);
5048 err = ixgbe_alloc_q_vector(adapter, v_idx,
5049 tqpv, txr_idx,
5050 rqpv, rxr_idx);
5051
5052 if (err)
207867f5 5053 goto err_out;
de88eeeb
AD		 5054
5055 /* update counts and index */
5056 rxr_remaining -= rqpv;
5057 rxr_idx += rqpv;
5058 txr_remaining -= tqpv;
5059 txr_idx += tqpv;
7a921c93
AD		 5060 }
5061
5062 return 0;
5063
5064err_out:
4ff7fb12
AD		 5065 while (v_idx) {
5066 v_idx--;
de88eeeb 5067 ixgbe_free_q_vector(adapter, v_idx);
7a921c93 5068 }
de88eeeb 5069
7a921c93
AD		 5070 return -ENOMEM;
5071}
5072
5073/**
5074 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5075 * @adapter: board private structure to initialize
5076 *
5077 * This function frees the memory allocated to the q_vectors. In addition if
5078 * NAPI is enabled it will delete any references to the NAPI struct prior
5079 * to freeing the q_vector.
5080 **/
5081static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5082{
de88eeeb 5083 int v_idx, q_vectors;
7a921c93 5084
91281fd3 5085 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
de88eeeb 5086 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5087 else
de88eeeb 5088 q_vectors = 1;
7a921c93 5089
de88eeeb
AD		 5090 for (v_idx = 0; v_idx < q_vectors; v_idx++)
5091 ixgbe_free_q_vector(adapter, v_idx);
7a921c93
AD		 5092}
5093
7b25cdba 5094static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5095{
5096 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5097 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5098 pci_disable_msix(adapter->pdev);
5099 kfree(adapter->msix_entries);
5100 adapter->msix_entries = NULL;
5101 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5102 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5103 pci_disable_msi(adapter->pdev);
5104 }
021230d4
AV		 5105}
5106
5107/**
5108 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5109 * @adapter: board private structure to initialize
5110 *
5111 * We determine which interrupt scheme to use based on...
5112 * - Kernel support (MSI, MSI-X)
5113 * - which can be user-defined (via MODULE_PARAM)
5114 * - Hardware queue count (num_*_queues)
5115 * - defined by miscellaneous hardware support/features (RSS, etc.)
5116 **/
2f90b865 5117int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5118{
5119 int err;
5120
5121 /* Number of supported queues */
847f53ff
BH		 5122 err = ixgbe_set_num_queues(adapter);
5123 if (err)
5124 return err;
021230d4 5125
021230d4
AV		 5126 err = ixgbe_set_interrupt_capability(adapter);
5127 if (err) {
849c4542 5128 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5129 goto err_set_interrupt;
9a799d71
AK		 5130 }
5131
7a921c93
AD		 5132 err = ixgbe_alloc_q_vectors(adapter);
5133 if (err) {
849c4542 5134 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5135 goto err_alloc_q_vectors;
5136 }
5137
de88eeeb 5138 ixgbe_cache_ring_register(adapter);
7a921c93 5139
849c4542 5140 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5141 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5142 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5143
5144 set_bit(__IXGBE_DOWN, &adapter->state);
5145
9a799d71 5146 return 0;
021230d4 5147
7a921c93
AD		 5148err_alloc_q_vectors:
5149 ixgbe_reset_interrupt_capability(adapter);
021230d4 5150err_set_interrupt:
7a921c93
AD		 5151 return err;
5152}
5153
5154/**
5155 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5156 * @adapter: board private structure to clear interrupt scheme on
5157 *
5158 * We go through and clear interrupt specific resources and reset the structure
5159 * to pre-load conditions
5160 **/
5161void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5162{
b8eb3a10
DS		 5163 adapter->num_tx_queues = 0;
5164 adapter->num_rx_queues = 0;
5165
7a921c93
AD		 5166 ixgbe_free_q_vectors(adapter);
5167 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5168}
5169
5170/**
5171 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5172 * @adapter: board private structure to initialize
5173 *
5174 * ixgbe_sw_init initializes the Adapter private data structure.
5175 * Fields are initialized based on PCI device information and
5176 * OS network device settings (MTU size).
5177 **/
5178static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5179{
5180 struct ixgbe_hw *hw = &adapter->hw;
5181 struct pci_dev *pdev = adapter->pdev;
021230d4 5182 unsigned int rss;
7a6b6f51 5183#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5184 int j;
5185 struct tc_configuration *tc;
5186#endif
021230d4 5187
c44ade9e
JB		 5188 /* PCI config space info */
5189
5190 hw->vendor_id = pdev->vendor;
5191 hw->device_id = pdev->device;
5192 hw->revision_id = pdev->revision;
5193 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5194 hw->subsystem_device_id = pdev->subsystem_device;
5195
021230d4 5196 /* Set capability flags */
3ed69d7e 5197 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
021230d4
AV		 5198 adapter->ring_feature[RING_F_RSS].indices = rss;
5199 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5200 switch (hw->mac.type) {
5201 case ixgbe_mac_82598EB:
bf069c97
DS		 5202 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5203 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5204 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 5205 break;
b93a2226 5206 case ixgbe_mac_X540:
4f51bf70
JK		 5207 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5208 case ixgbe_mac_82599EB:
e8e26350 5209 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5210 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5211 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5212 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5213 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5214 /* Flow Director hash filters enabled */
5215 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5216 adapter->atr_sample_rate = 20;
c4cf55e5 5217 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5218 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5219 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5220#ifdef IXGBE_FCOE
0d551589
YZ		 5221 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5222 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5223 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5224#ifdef CONFIG_IXGBE_DCB
6ee16520 5225 /* Default traffic class to use for FCoE */
56075a98 5226 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5227#endif
eacd73f7 5228#endif /* IXGBE_FCOE */
bd508178
AD		 5229 break;
5230 default:
5231 break;
f8212f97 5232 }
2f90b865 5233
1fc5f038
AD		 5234 /* n-tuple support exists, always init our spinlock */
5235 spin_lock_init(&adapter->fdir_perfect_lock);
5236
7a6b6f51 5237#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5238 switch (hw->mac.type) {
5239 case ixgbe_mac_X540:
5240 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5241 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5242 break;
5243 default:
5244 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5245 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5246 break;
5247 }
5248
2f90b865
AD		 5249 /* Configure DCB traffic classes */
5250 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5251 tc = &adapter->dcb_cfg.tc_config[j];
5252 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5253 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5254 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5255 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5256 tc->dcb_pfc = pfc_disabled;
5257 }
4de2a022
JF		 5258
5259 /* Initialize default user to priority mapping, UPx->TC0 */
5260 tc = &adapter->dcb_cfg.tc_config[0];
5261 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5262 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5263
2f90b865
AD		 5264 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5265 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5266 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5267 adapter->dcb_set_bitmap = 0x00;
3032309b 5268 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5269 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5270 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5271
5272#endif
9a799d71
AK		 5273
5274 /* default flow control settings */
cd7664f6 5275 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5276 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5277#ifdef CONFIG_DCB
5278 adapter->last_lfc_mode = hw->fc.current_mode;
5279#endif
9da712d2 5280 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5281 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5282 hw->fc.send_xon = true;
71fd570b 5283 hw->fc.disable_fc_autoneg = false;
9a799d71 5284
30efa5a3 5285 /* enable itr by default in dynamic mode */
f7554a2b 5286 adapter->rx_itr_setting = 1;
f7554a2b 5287 adapter->tx_itr_setting = 1;
30efa5a3 5288
30efa5a3
JB		 5289 /* set default ring sizes */
5290 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5291 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5292
bd198058 5293 /* set default work limits */
59224555 5294 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5295
9a799d71 5296 /* initialize eeprom parameters */
c44ade9e 5297 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5298 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5299 return -EIO;
5300 }
5301
9a799d71
AK		 5302 set_bit(__IXGBE_DOWN, &adapter->state);
5303
5304 return 0;
5305}
5306
5307/**
5308 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5309 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5310 *
5311 * Return 0 on success, negative on failure
5312 **/
b6ec895e 5313int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5314{
b6ec895e 5315 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5316 int orig_node = dev_to_node(dev);
5317 int numa_node = -1;
9a799d71
AK		 5318 int size;
5319
3a581073 5320 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5321
5322 if (tx_ring->q_vector)
5323 numa_node = tx_ring->q_vector->numa_node;
5324
5325 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5326 if (!tx_ring->tx_buffer_info)
89bf67f1 5327 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5328 if (!tx_ring->tx_buffer_info)
5329 goto err;
9a799d71
AK		 5330
5331 /* round up to nearest 4K */
12207e49 5332 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5333 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5334
de88eeeb
AD		 5335 set_dev_node(dev, numa_node);
5336 tx_ring->desc = dma_alloc_coherent(dev,
5337 tx_ring->size,
5338 &tx_ring->dma,
5339 GFP_KERNEL);
5340 set_dev_node(dev, orig_node);
5341 if (!tx_ring->desc)
5342 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5343 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5344 if (!tx_ring->desc)
5345 goto err;
9a799d71 5346
3a581073
JB		 5347 tx_ring->next_to_use = 0;
5348 tx_ring->next_to_clean = 0;
9a799d71 5349 return 0;
e01c31a5
JB		 5350
5351err:
5352 vfree(tx_ring->tx_buffer_info);
5353 tx_ring->tx_buffer_info = NULL;
b6ec895e 5354 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5355 return -ENOMEM;
9a799d71
AK		 5356}
5357
69888674
AD		 5358/**
5359 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5360 * @adapter: board private structure
5361 *
5362 * If this function returns with an error, then it's possible one or
5363 * more of the rings is populated (while the rest are not). It is the
5364 * callers duty to clean those orphaned rings.
5365 *
5366 * Return 0 on success, negative on failure
5367 **/
5368static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5369{
5370 int i, err = 0;
5371
5372 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5373 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5374 if (!err)
5375 continue;
396e799c 5376 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5377 break;
5378 }
5379
5380 return err;
5381}
5382
9a799d71
AK		 5383/**
5384 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5385 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5386 *
5387 * Returns 0 on success, negative on failure
5388 **/
b6ec895e 5389int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5390{
b6ec895e 5391 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5392 int orig_node = dev_to_node(dev);
5393 int numa_node = -1;
021230d4 5394 int size;
9a799d71 5395
3a581073 5396 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5397
5398 if (rx_ring->q_vector)
5399 numa_node = rx_ring->q_vector->numa_node;
5400
5401 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5402 if (!rx_ring->rx_buffer_info)
89bf67f1 5403 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5404 if (!rx_ring->rx_buffer_info)
5405 goto err;
9a799d71 5406
9a799d71 5407 /* Round up to nearest 4K */
3a581073
JB		 5408 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5409 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5410
de88eeeb
AD		 5411 set_dev_node(dev, numa_node);
5412 rx_ring->desc = dma_alloc_coherent(dev,
5413 rx_ring->size,
5414 &rx_ring->dma,
5415 GFP_KERNEL);
5416 set_dev_node(dev, orig_node);
5417 if (!rx_ring->desc)
5418 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5419 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5420 if (!rx_ring->desc)
5421 goto err;
9a799d71 5422
3a581073
JB		 5423 rx_ring->next_to_clean = 0;
5424 rx_ring->next_to_use = 0;
9a799d71 5425
f800326d
AD		 5426 ixgbe_init_rx_page_offset(rx_ring);
5427
9a799d71 5428 return 0;
b6ec895e
AD		 5429err:
5430 vfree(rx_ring->rx_buffer_info);
5431 rx_ring->rx_buffer_info = NULL;
5432 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5433 return -ENOMEM;
9a799d71
AK		 5434}
5435
69888674
AD		 5436/**
5437 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5438 * @adapter: board private structure
5439 *
5440 * If this function returns with an error, then it's possible one or
5441 * more of the rings is populated (while the rest are not). It is the
5442 * callers duty to clean those orphaned rings.
5443 *
5444 * Return 0 on success, negative on failure
5445 **/
69888674
AD		 5446static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5447{
5448 int i, err = 0;
5449
5450 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5451 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5452 if (!err)
5453 continue;
396e799c 5454 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5455 break;
5456 }
5457
5458 return err;
5459}
5460
9a799d71
AK		 5461/**
5462 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5463 * @tx_ring: Tx descriptor ring for a specific queue
5464 *
5465 * Free all transmit software resources
5466 **/
b6ec895e 5467void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5468{
b6ec895e 5469 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5470
5471 vfree(tx_ring->tx_buffer_info);
5472 tx_ring->tx_buffer_info = NULL;
5473
b6ec895e
AD		 5474 /* if not set, then don't free */
5475 if (!tx_ring->desc)
5476 return;
5477
5478 dma_free_coherent(tx_ring->dev, tx_ring->size,
5479 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5480
5481 tx_ring->desc = NULL;
5482}
5483
5484/**
5485 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5486 * @adapter: board private structure
5487 *
5488 * Free all transmit software resources
5489 **/
5490static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5491{
5492 int i;
5493
5494 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5495 if (adapter->tx_ring[i]->desc)
b6ec895e 5496 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5497}
5498
5499/**
b4617240 5500 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5501 * @rx_ring: ring to clean the resources from
5502 *
5503 * Free all receive software resources
5504 **/
b6ec895e 5505void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5506{
b6ec895e 5507 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5508
5509 vfree(rx_ring->rx_buffer_info);
5510 rx_ring->rx_buffer_info = NULL;
5511
b6ec895e
AD		 5512 /* if not set, then don't free */
5513 if (!rx_ring->desc)
5514 return;
5515
5516 dma_free_coherent(rx_ring->dev, rx_ring->size,
5517 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5518
5519 rx_ring->desc = NULL;
5520}
5521
5522/**
5523 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5524 * @adapter: board private structure
5525 *
5526 * Free all receive software resources
5527 **/
5528static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5529{
5530 int i;
5531
5532 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5533 if (adapter->rx_ring[i]->desc)
b6ec895e 5534 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5535}
5536
9a799d71
AK		 5537/**
5538 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5539 * @netdev: network interface device structure
5540 * @new_mtu: new value for maximum frame size
5541 *
5542 * Returns 0 on success, negative on failure
5543 **/
5544static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5545{
5546 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5547 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5548
42c783c5 5549 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5550 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5551 return -EINVAL;
5552
5553 /*
5554 * For 82599EB we cannot allow PF to change MTU greater than 1500
5555 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
5556 * don't allocate and chain buffers correctly.
5557 */
5558 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5559 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5560 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 5561 return -EINVAL;
9a799d71 5562
396e799c 5563 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5564
021230d4 5565 /* must set new MTU before calling down or up */
9a799d71
AK		 5566 netdev->mtu = new_mtu;
5567
d4f80882
AV		 5568 if (netif_running(netdev))
5569 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5570
5571 return 0;
5572}
5573
5574/**
5575 * ixgbe_open - Called when a network interface is made active
5576 * @netdev: network interface device structure
5577 *
5578 * Returns 0 on success, negative value on failure
5579 *
5580 * The open entry point is called when a network interface is made
5581 * active by the system (IFF_UP). At this point all resources needed
5582 * for transmit and receive operations are allocated, the interrupt
5583 * handler is registered with the OS, the watchdog timer is started,
5584 * and the stack is notified that the interface is ready.
5585 **/
5586static int ixgbe_open(struct net_device *netdev)
5587{
5588 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5589 int err;
4bebfaa5
AK		 5590
5591 /* disallow open during test */
5592 if (test_bit(__IXGBE_TESTING, &adapter->state))
5593 return -EBUSY;
9a799d71 5594
54386467
JB		 5595 netif_carrier_off(netdev);
5596
9a799d71
AK		 5597 /* allocate transmit descriptors */
5598 err = ixgbe_setup_all_tx_resources(adapter);
5599 if (err)
5600 goto err_setup_tx;
5601
9a799d71
AK		 5602 /* allocate receive descriptors */
5603 err = ixgbe_setup_all_rx_resources(adapter);
5604 if (err)
5605 goto err_setup_rx;
5606
5607 ixgbe_configure(adapter);
5608
021230d4 5609 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5610 if (err)
5611 goto err_req_irq;
5612
c7ccde0f 5613 ixgbe_up_complete(adapter);
9a799d71
AK		 5614
5615 return 0;
5616
9a799d71 5617err_req_irq:
9a799d71 5618err_setup_rx:
a20a1199 5619 ixgbe_free_all_rx_resources(adapter);
9a799d71 5620err_setup_tx:
a20a1199 5621 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5622 ixgbe_reset(adapter);
5623
5624 return err;
5625}
5626
5627/**
5628 * ixgbe_close - Disables a network interface
5629 * @netdev: network interface device structure
5630 *
5631 * Returns 0, this is not allowed to fail
5632 *
5633 * The close entry point is called when an interface is de-activated
5634 * by the OS. The hardware is still under the drivers control, but
5635 * needs to be disabled. A global MAC reset is issued to stop the
5636 * hardware, and all transmit and receive resources are freed.
5637 **/
5638static int ixgbe_close(struct net_device *netdev)
5639{
5640 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5641
5642 ixgbe_down(adapter);
5643 ixgbe_free_irq(adapter);
5644
e4911d57
AD		 5645 ixgbe_fdir_filter_exit(adapter);
5646
9a799d71
AK		 5647 ixgbe_free_all_tx_resources(adapter);
5648 ixgbe_free_all_rx_resources(adapter);
5649
5eba3699 5650 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5651
5652 return 0;
5653}
5654
b3c8b4ba
AD		 5655#ifdef CONFIG_PM
5656static int ixgbe_resume(struct pci_dev *pdev)
5657{
c60fbb00
AD		 5658 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5659 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5660 u32 err;
5661
5662 pci_set_power_state(pdev, PCI_D0);
5663 pci_restore_state(pdev);
656ab817
DS		 5664 /*
5665 * pci_restore_state clears dev->state_saved so call
5666 * pci_save_state to restore it.
5667 */
5668 pci_save_state(pdev);
9ce77666 5669
5670 err = pci_enable_device_mem(pdev);
b3c8b4ba 5671 if (err) {
849c4542 5672 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5673 return err;
5674 }
5675 pci_set_master(pdev);
5676
dd4d8ca6 5677 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5678
5679 err = ixgbe_init_interrupt_scheme(adapter);
5680 if (err) {
849c4542 5681 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5682 return err;
5683 }
5684
b3c8b4ba
AD		 5685 ixgbe_reset(adapter);
5686
495dce12
WJP		 5687 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5688
b3c8b4ba 5689 if (netif_running(netdev)) {
c60fbb00 5690 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5691 if (err)
5692 return err;
5693 }
5694
5695 netif_device_attach(netdev);
5696
5697 return 0;
5698}
b3c8b4ba 5699#endif /* CONFIG_PM */
9d8d05ae
RW		 5700
5701static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5702{
c60fbb00
AD		 5703 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5704 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5705 struct ixgbe_hw *hw = &adapter->hw;
5706 u32 ctrl, fctrl;
5707 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5708#ifdef CONFIG_PM
5709 int retval = 0;
5710#endif
5711
5712 netif_device_detach(netdev);
5713
5714 if (netif_running(netdev)) {
5715 ixgbe_down(adapter);
5716 ixgbe_free_irq(adapter);
5717 ixgbe_free_all_tx_resources(adapter);
5718 ixgbe_free_all_rx_resources(adapter);
5719 }
b3c8b4ba 5720
5f5ae6fc 5721 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5722#ifdef CONFIG_DCB
5723 kfree(adapter->ixgbe_ieee_pfc);
5724 kfree(adapter->ixgbe_ieee_ets);
5725#endif
5f5ae6fc 5726
b3c8b4ba
AD		 5727#ifdef CONFIG_PM
5728 retval = pci_save_state(pdev);
5729 if (retval)
5730 return retval;
4df10466 5731
b3c8b4ba 5732#endif
e8e26350
PW		 5733 if (wufc) {
5734 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5735
e8e26350
PW		 5736 /* turn on all-multi mode if wake on multicast is enabled */
5737 if (wufc & IXGBE_WUFC_MC) {
5738 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5739 fctrl |= IXGBE_FCTRL_MPE;
5740 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5741 }
5742
5743 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5744 ctrl |= IXGBE_CTRL_GIO_DIS;
5745 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5746
5747 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5748 } else {
5749 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5750 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5751 }
5752
bd508178
AD		 5753 switch (hw->mac.type) {
5754 case ixgbe_mac_82598EB:
dd4d8ca6 5755 pci_wake_from_d3(pdev, false);
bd508178
AD		 5756 break;
5757 case ixgbe_mac_82599EB:
b93a2226 5758 case ixgbe_mac_X540:
bd508178
AD		 5759 pci_wake_from_d3(pdev, !!wufc);
5760 break;
5761 default:
5762 break;
5763 }
b3c8b4ba 5764
9d8d05ae
RW		 5765 *enable_wake = !!wufc;
5766
b3c8b4ba
AD		 5767 ixgbe_release_hw_control(adapter);
5768
5769 pci_disable_device(pdev);
5770
9d8d05ae
RW		 5771 return 0;
5772}
5773
5774#ifdef CONFIG_PM
5775static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5776{
5777 int retval;
5778 bool wake;
5779
5780 retval = __ixgbe_shutdown(pdev, &wake);
5781 if (retval)
5782 return retval;
5783
5784 if (wake) {
5785 pci_prepare_to_sleep(pdev);
5786 } else {
5787 pci_wake_from_d3(pdev, false);
5788 pci_set_power_state(pdev, PCI_D3hot);
5789 }
b3c8b4ba
AD		 5790
5791 return 0;
5792}
9d8d05ae 5793#endif /* CONFIG_PM */
b3c8b4ba
AD		 5794
5795static void ixgbe_shutdown(struct pci_dev *pdev)
5796{
9d8d05ae
RW		 5797 bool wake;
5798
5799 __ixgbe_shutdown(pdev, &wake);
5800
5801 if (system_state == SYSTEM_POWER_OFF) {
5802 pci_wake_from_d3(pdev, wake);
5803 pci_set_power_state(pdev, PCI_D3hot);
5804 }
b3c8b4ba
AD		 5805}
5806
9a799d71
AK		 5807/**
5808 * ixgbe_update_stats - Update the board statistics counters.
5809 * @adapter: board private structure
5810 **/
5811void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5812{
2d86f139 5813 struct net_device *netdev = adapter->netdev;
9a799d71 5814 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5815 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5816 u64 total_mpc = 0;
5817 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5818 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5819 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5820 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7b859ebc
AH		 5821#ifdef IXGBE_FCOE
5822 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5823 unsigned int cpu;
5824 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5825#endif /* IXGBE_FCOE */
9a799d71 5826
d08935c2
DS		 5827 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5828 test_bit(__IXGBE_RESETTING, &adapter->state))
5829 return;
5830
94b982b2 5831 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5832 u64 rsc_count = 0;
94b982b2 5833 u64 rsc_flush = 0;
d51019a4
PW		 5834 for (i = 0; i < 16; i++)
5835 adapter->hw_rx_no_dma_resources +=
7ca647bd 5836 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5837 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5838 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5839 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5840 }
5841 adapter->rsc_total_count = rsc_count;
5842 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5843 }
5844
5b7da515
AD		 5845 for (i = 0; i < adapter->num_rx_queues; i++) {
5846 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5847 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5848 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5849 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5850 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5851 bytes += rx_ring->stats.bytes;
5852 packets += rx_ring->stats.packets;
5853 }
5854 adapter->non_eop_descs = non_eop_descs;
5855 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5856 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5857 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5858 netdev->stats.rx_bytes = bytes;
5859 netdev->stats.rx_packets = packets;
5860
5861 bytes = 0;
5862 packets = 0;
7ca3bc58 5863 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5864 for (i = 0; i < adapter->num_tx_queues; i++) {
5865 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5866 restart_queue += tx_ring->tx_stats.restart_queue;
5867 tx_busy += tx_ring->tx_stats.tx_busy;
5868 bytes += tx_ring->stats.bytes;
5869 packets += tx_ring->stats.packets;
5870 }
eb985f09 5871 adapter->restart_queue = restart_queue;
5b7da515
AD		 5872 adapter->tx_busy = tx_busy;
5873 netdev->stats.tx_bytes = bytes;
5874 netdev->stats.tx_packets = packets;
7ca3bc58 5875
7ca647bd 5876 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5877
5878 /* 8 register reads */
6f11eef7
AV		 5879 for (i = 0; i < 8; i++) {
5880 /* for packet buffers not used, the register should read 0 */
5881 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5882 missed_rx += mpc;
7ca647bd
JP		 5883 hwstats->mpc[i] += mpc;
5884 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5885 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5886 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5887 switch (hw->mac.type) {
5888 case ixgbe_mac_82598EB:
1a70db4b
ET		 5889 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5890 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5891 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5892 hwstats->pxonrxc[i] +=
5893 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5894 break;
5895 case ixgbe_mac_82599EB:
b93a2226 5896 case ixgbe_mac_X540:
bd508178
AD		 5897 hwstats->pxonrxc[i] +=
5898 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5899 break;
5900 default:
5901 break;
e8e26350 5902 }
6f11eef7 5903 }
1a70db4b
ET		 5904
5905 /*16 register reads */
5906 for (i = 0; i < 16; i++) {
5907 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5908 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5909 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5910 (hw->mac.type == ixgbe_mac_X540)) {
5911 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5912 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5913 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5914 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5915 }
5916 }
5917
7ca647bd 5918 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5919 /* work around hardware counting issue */
7ca647bd 5920 hwstats->gprc -= missed_rx;
6f11eef7 5921
c84d324c
JF		 5922 ixgbe_update_xoff_received(adapter);
5923
6f11eef7 5924 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5925 switch (hw->mac.type) {
5926 case ixgbe_mac_82598EB:
5927 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5928 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5929 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5930 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5931 break;
b93a2226 5932 case ixgbe_mac_X540:
58f6bcf9
ET		 5933 /* OS2BMC stats are X540 only*/
5934 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5935 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5936 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5937 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5938 case ixgbe_mac_82599EB:
7ca647bd 5939 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5940 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5941 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5942 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5943 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5944 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5945 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5946 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5947 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5948#ifdef IXGBE_FCOE
7ca647bd
JP		 5949 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5950 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5951 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5952 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5953 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5954 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5955 /* Add up per cpu counters for total ddp aloc fail */
5956 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5957 for_each_possible_cpu(cpu) {
5958 fcoe_noddp_counts_sum +=
5959 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5960 fcoe_noddp_ext_buff_counts_sum +=
5961 *per_cpu_ptr(fcoe->
5962 pcpu_noddp_ext_buff, cpu);
5963 }
5964 }
5965 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5966 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5967#endif /* IXGBE_FCOE */
bd508178
AD		 5968 break;
5969 default:
5970 break;
e8e26350 5971 }
9a799d71 5972 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5973 hwstats->bprc += bprc;
5974 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5975 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5976 hwstats->mprc -= bprc;
5977 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5978 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5979 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5980 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5981 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5982 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5983 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5984 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5985 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5986 hwstats->lxontxc += lxon;
6f11eef7 5987 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5988 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5989 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5990 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5991 /*
5992 * 82598 errata - tx of flow control packets is included in tx counters
5993 */
5994 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5995 hwstats->gptc -= xon_off_tot;
5996 hwstats->mptc -= xon_off_tot;
5997 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5998 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5999 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6000 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6001 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6002 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6003 hwstats->ptc64 -= xon_off_tot;
6004 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6005 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6006 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6007 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6008 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6009 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6010
6011 /* Fill out the OS statistics structure */
7ca647bd 6012 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6013
6014 /* Rx Errors */
7ca647bd 6015 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6016 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6017 netdev->stats.rx_length_errors = hwstats->rlec;
6018 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6019 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6020}
6021
6022/**
d034acf1
AD		 6023 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6024 * @adapter - pointer to the device adapter structure
9a799d71 6025 **/
d034acf1 6026static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6027{
cf8280ee 6028 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6029 int i;
cf8280ee 6030
d034acf1
AD		 6031 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6032 return;
6033
6034 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6035
d034acf1 6036 /* if interface is down do nothing */
fe49f04a 6037 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6038 return;
6039
6040 /* do nothing if we are not using signature filters */
6041 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6042 return;
6043
6044 adapter->fdir_overflow++;
6045
93c52dd0
AD		 6046 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6047 for (i = 0; i < adapter->num_tx_queues; i++)
6048 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 6049 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6050 /* re-enable flow director interrupts */
6051 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6052 } else {
6053 e_err(probe, "failed to finish FDIR re-initialization, "
6054 "ignored adding FDIR ATR filters\n");
6055 }
93c52dd0
AD		 6056}
6057
6058/**
6059 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6060 * @adapter - pointer to the device adapter structure
6061 *
6062 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6063 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6064 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6065 * determine if a hang has occurred.
93c52dd0
AD		 6066 */
6067static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6068{
cf8280ee 6069 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6070 u64 eics = 0;
6071 int i;
cf8280ee 6072
93c52dd0
AD		 6073 /* If we're down or resetting, just bail */
6074 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6075 test_bit(__IXGBE_RESETTING, &adapter->state))
6076 return;
22d5a71b 6077
93c52dd0
AD		 6078 /* Force detection of hung controller */
6079 if (netif_carrier_ok(adapter->netdev)) {
6080 for (i = 0; i < adapter->num_tx_queues; i++)
6081 set_check_for_tx_hang(adapter->tx_ring[i]);
6082 }
22d5a71b 6083
fe49f04a
AD		 6084 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6085 /*
6086 * for legacy and MSI interrupts don't set any bits
6087 * that are enabled for EIAM, because this operation
6088 * would set *both* EIMS and EICS for any bit in EIAM
6089 */
6090 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6091 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6092 } else {
6093 /* get one bit for every active tx/rx interrupt vector */
6094 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6095 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6096 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6097 eics |= ((u64)1 << i);
6098 }
cf8280ee 6099 }
9a799d71 6100
93c52dd0 6101 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6102 ixgbe_irq_rearm_queues(adapter, eics);
6103
cf8280ee
JB		 6104}
6105
e8e26350 6106/**
93c52dd0
AD		 6107 * ixgbe_watchdog_update_link - update the link status
6108 * @adapter - pointer to the device adapter structure
6109 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 6110 **/
93c52dd0 6111static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6112{
e8e26350 6113 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6114 u32 link_speed = adapter->link_speed;
6115 bool link_up = adapter->link_up;
c4cf55e5 6116 int i;
e8e26350 6117
93c52dd0
AD		 6118 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6119 return;
6120
6121 if (hw->mac.ops.check_link) {
6122 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6123 } else {
93c52dd0
AD		 6124 /* always assume link is up, if no check link function */
6125 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6126 link_up = true;
c4cf55e5 6127 }
93c52dd0
AD		 6128 if (link_up) {
6129 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6130 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6131 hw->mac.ops.fc_enable(hw, i);
6132 } else {
6133 hw->mac.ops.fc_enable(hw, 0);
6134 }
6135 }
6136
6137 if (link_up ||
6138 time_after(jiffies, (adapter->link_check_timeout +
6139 IXGBE_TRY_LINK_TIMEOUT))) {
6140 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6141 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6142 IXGBE_WRITE_FLUSH(hw);
6143 }
6144
6145 adapter->link_up = link_up;
6146 adapter->link_speed = link_speed;
e8e26350
PW		 6147}
6148
6149/**
93c52dd0
AD		 6150 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6151 * print link up message
6152 * @adapter - pointer to the device adapter structure
e8e26350 6153 **/
93c52dd0 6154static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6155{
93c52dd0 6156 struct net_device *netdev = adapter->netdev;
e8e26350 6157 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6158 u32 link_speed = adapter->link_speed;
6159 bool flow_rx, flow_tx;
e8e26350 6160
93c52dd0
AD		 6161 /* only continue if link was previously down */
6162 if (netif_carrier_ok(netdev))
a985b6c3 6163 return;
63d6e1d8 6164
93c52dd0 6165 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6166
93c52dd0
AD		 6167 switch (hw->mac.type) {
6168 case ixgbe_mac_82598EB: {
6169 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6170 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6171 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6172 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6173 }
6174 break;
6175 case ixgbe_mac_X540:
6176 case ixgbe_mac_82599EB: {
6177 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6178 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6179 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6180 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6181 }
6182 break;
6183 default:
6184 flow_tx = false;
6185 flow_rx = false;
6186 break;
e8e26350 6187 }
93c52dd0
AD		 6188 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6189 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6190 "10 Gbps" :
6191 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6192 "1 Gbps" :
6193 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6194 "100 Mbps" :
6195 "unknown speed"))),
6196 ((flow_rx && flow_tx) ? "RX/TX" :
6197 (flow_rx ? "RX" :
6198 (flow_tx ? "TX" : "None"))));
e8e26350 6199
93c52dd0 6200 netif_carrier_on(netdev);
93c52dd0 6201 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 6202}
6203
c4cf55e5 6204/**
93c52dd0
AD		 6205 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6206 * print link down message
6207 * @adapter - pointer to the adapter structure
c4cf55e5 6208 **/
93c52dd0 6209static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6210{
cf8280ee 6211 struct net_device *netdev = adapter->netdev;
c4cf55e5 6212 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6213
93c52dd0
AD		 6214 adapter->link_up = false;
6215 adapter->link_speed = 0;
cf8280ee 6216
93c52dd0
AD		 6217 /* only continue if link was up previously */
6218 if (!netif_carrier_ok(netdev))
6219 return;
264857b8 6220
93c52dd0
AD		 6221 /* poll for SFP+ cable when link is down */
6222 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6223 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6224
93c52dd0
AD		 6225 e_info(drv, "NIC Link is Down\n");
6226 netif_carrier_off(netdev);
6227}
e8e26350 6228
93c52dd0
AD		 6229/**
6230 * ixgbe_watchdog_flush_tx - flush queues on link down
6231 * @adapter - pointer to the device adapter structure
6232 **/
6233static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6234{
c4cf55e5 6235 int i;
93c52dd0 6236 int some_tx_pending = 0;
c4cf55e5 6237
93c52dd0 6238 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6239 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6240 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6241 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6242 some_tx_pending = 1;
6243 break;
6244 }
6245 }
6246
6247 if (some_tx_pending) {
6248 /* We've lost link, so the controller stops DMA,
6249 * but we've got queued Tx work that's never going
6250 * to get done, so reset controller to flush Tx.
6251 * (Do the reset outside of interrupt context).
6252 */
c83c6cbd 6253 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6254 }
c4cf55e5 6255 }
c4cf55e5
PWJ		 6256}
6257
a985b6c3
GR		 6258static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6259{
6260 u32 ssvpc;
6261
6262 /* Do not perform spoof check for 82598 */
6263 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6264 return;
6265
6266 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6267
6268 /*
6269 * ssvpc register is cleared on read, if zero then no
6270 * spoofed packets in the last interval.
6271 */
6272 if (!ssvpc)
6273 return;
6274
6275 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6276}
6277
93c52dd0
AD		 6278/**
6279 * ixgbe_watchdog_subtask - check and bring link up
6280 * @adapter - pointer to the device adapter structure
6281 **/
6282static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6283{
6284 /* if interface is down do nothing */
7edebf9a
ET		 6285 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6286 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6287 return;
6288
6289 ixgbe_watchdog_update_link(adapter);
6290
6291 if (adapter->link_up)
6292 ixgbe_watchdog_link_is_up(adapter);
6293 else
6294 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6295
a985b6c3 6296 ixgbe_spoof_check(adapter);
9a799d71 6297 ixgbe_update_stats(adapter);
93c52dd0
AD		 6298
6299 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6300}
10eec955 6301
cf8280ee 6302/**
7086400d
AD		 6303 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6304 * @adapter - the ixgbe adapter structure
cf8280ee 6305 **/
7086400d 6306static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6307{
cf8280ee 6308 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6309 s32 err;
cf8280ee 6310
7086400d
AD		 6311 /* not searching for SFP so there is nothing to do here */
6312 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6313 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6314 return;
10eec955 6315
7086400d
AD		 6316 /* someone else is in init, wait until next service event */
6317 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6318 return;
cf8280ee 6319
7086400d
AD		 6320 err = hw->phy.ops.identify_sfp(hw);
6321 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6322 goto sfp_out;
264857b8 6323
7086400d
AD		 6324 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6325 /* If no cable is present, then we need to reset
6326 * the next time we find a good cable. */
6327 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6328 }
9a799d71 6329
7086400d
AD		 6330 /* exit on error */
6331 if (err)
6332 goto sfp_out;
e8e26350 6333
7086400d
AD		 6334 /* exit if reset not needed */
6335 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6336 goto sfp_out;
9a799d71 6337
7086400d 6338 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6339
7086400d
AD		 6340 /*
6341 * A module may be identified correctly, but the EEPROM may not have
6342 * support for that module. setup_sfp() will fail in that case, so
6343 * we should not allow that module to load.
6344 */
6345 if (hw->mac.type == ixgbe_mac_82598EB)
6346 err = hw->phy.ops.reset(hw);
6347 else
6348 err = hw->mac.ops.setup_sfp(hw);
6349
6350 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6351 goto sfp_out;
6352
6353 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6354 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6355
6356sfp_out:
6357 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6358
6359 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6360 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6361 e_dev_err("failed to initialize because an unsupported "
6362 "SFP+ module type was detected.\n");
6363 e_dev_err("Reload the driver after installing a "
6364 "supported module.\n");
6365 unregister_netdev(adapter->netdev);
bc59fcda 6366 }
7086400d 6367}
bc59fcda 6368
7086400d
AD		 6369/**
6370 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6371 * @adapter - the ixgbe adapter structure
6372 **/
6373static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6374{
6375 struct ixgbe_hw *hw = &adapter->hw;
6376 u32 autoneg;
6377 bool negotiation;
6378
6379 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6380 return;
6381
6382 /* someone else is in init, wait until next service event */
6383 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6384 return;
6385
6386 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6387
6388 autoneg = hw->phy.autoneg_advertised;
6389 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6390 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6391 if (hw->mac.ops.setup_link)
6392 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6393
6394 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6395 adapter->link_check_timeout = jiffies;
6396 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6397}
6398
83c61fa9
GR		 6399#ifdef CONFIG_PCI_IOV
6400static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6401{
6402 int vf;
6403 struct ixgbe_hw *hw = &adapter->hw;
6404 struct net_device *netdev = adapter->netdev;
6405 u32 gpc;
6406 u32 ciaa, ciad;
6407
6408 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6409 if (gpc) /* If incrementing then no need for the check below */
6410 return;
6411 /*
6412 * Check to see if a bad DMA write target from an errant or
6413 * malicious VF has caused a PCIe error. If so then we can
6414 * issue a VFLR to the offending VF(s) and then resume without
6415 * requesting a full slot reset.
6416 */
6417
6418 for (vf = 0; vf < adapter->num_vfs; vf++) {
6419 ciaa = (vf << 16) | 0x80000000;
6420 /* 32 bit read so align, we really want status at offset 6 */
6421 ciaa |= PCI_COMMAND;
6422 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6423 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6424 ciaa &= 0x7FFFFFFF;
6425 /* disable debug mode asap after reading data */
6426 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6427 /* Get the upper 16 bits which will be the PCI status reg */
6428 ciad >>= 16;
6429 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6430 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6431 /* Issue VFLR */
6432 ciaa = (vf << 16) | 0x80000000;
6433 ciaa |= 0xA8;
6434 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6435 ciad = 0x00008000; /* VFLR */
6436 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6437 ciaa &= 0x7FFFFFFF;
6438 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6439 }
6440 }
6441}
6442
6443#endif
7086400d
AD		 6444/**
6445 * ixgbe_service_timer - Timer Call-back
6446 * @data: pointer to adapter cast into an unsigned long
6447 **/
6448static void ixgbe_service_timer(unsigned long data)
6449{
6450 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6451 unsigned long next_event_offset;
83c61fa9 6452 bool ready = true;
7086400d 6453
83c61fa9
GR		 6454#ifdef CONFIG_PCI_IOV
6455 ready = false;
6456
6457 /*
6458 * don't bother with SR-IOV VF DMA hang check if there are
6459 * no VFs or the link is down
6460 */
6461 if (!adapter->num_vfs ||
6462 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6463 ready = true;
6464 goto normal_timer_service;
6465 }
6466
6467 /* If we have VFs allocated then we must check for DMA hangs */
6468 ixgbe_check_for_bad_vf(adapter);
6469 next_event_offset = HZ / 50;
6470 adapter->timer_event_accumulator++;
6471
6472 if (adapter->timer_event_accumulator >= 100) {
6473 ready = true;
6474 adapter->timer_event_accumulator = 0;
6475 }
6476
6477 goto schedule_event;
6478
6479normal_timer_service:
6480#endif
7086400d
AD		 6481 /* poll faster when waiting for link */
6482 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6483 next_event_offset = HZ / 10;
6484 else
6485 next_event_offset = HZ * 2;
6486
83c61fa9
GR		 6487#ifdef CONFIG_PCI_IOV
6488schedule_event:
6489#endif
7086400d
AD		 6490 /* Reset the timer */
6491 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6492
83c61fa9
GR		 6493 if (ready)
6494 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6495}
6496
c83c6cbd
AD		 6497static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6498{
6499 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6500 return;
6501
6502 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6503
6504 /* If we're already down or resetting, just bail */
6505 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6506 test_bit(__IXGBE_RESETTING, &adapter->state))
6507 return;
6508
6509 ixgbe_dump(adapter);
6510 netdev_err(adapter->netdev, "Reset adapter\n");
6511 adapter->tx_timeout_count++;
6512
6513 ixgbe_reinit_locked(adapter);
6514}
6515
7086400d
AD		 6516/**
6517 * ixgbe_service_task - manages and runs subtasks
6518 * @work: pointer to work_struct containing our data
6519 **/
6520static void ixgbe_service_task(struct work_struct *work)
6521{
6522 struct ixgbe_adapter *adapter = container_of(work,
6523 struct ixgbe_adapter,
6524 service_task);
6525
c83c6cbd 6526 ixgbe_reset_subtask(adapter);
7086400d
AD		 6527 ixgbe_sfp_detection_subtask(adapter);
6528 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6529 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6530 ixgbe_watchdog_subtask(adapter);
d034acf1 6531 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6532 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6533
6534 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6535}
6536
897ab156
AD		 6537void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6538 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6539{
6540 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6541 u16 i = tx_ring->next_to_use;
9a799d71 6542
e4f74028 6543 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
9a799d71 6544
897ab156
AD		 6545 i++;
6546 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6547
897ab156
AD		 6548 /* set bits to identify this as an advanced context descriptor */
6549 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6550
897ab156
AD		 6551 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6552 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6553 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6554 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6555}
9a799d71 6556
897ab156
AD		 6557static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6558 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6559{
6560 int err;
6561 u32 vlan_macip_lens, type_tucmd;
6562 u32 mss_l4len_idx, l4len;
9a799d71 6563
897ab156
AD		 6564 if (!skb_is_gso(skb))
6565 return 0;
9a799d71 6566
897ab156
AD		 6567 if (skb_header_cloned(skb)) {
6568 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6569 if (err)
6570 return err;
9a799d71 6571 }
9a799d71 6572
897ab156
AD		 6573 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6574 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6575
6576 if (protocol == __constant_htons(ETH_P_IP)) {
6577 struct iphdr *iph = ip_hdr(skb);
6578 iph->tot_len = 0;
6579 iph->check = 0;
6580 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6581 iph->daddr, 0,
6582 IPPROTO_TCP,
6583 0);
6584 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6585 } else if (skb_is_gso_v6(skb)) {
6586 ipv6_hdr(skb)->payload_len = 0;
6587 tcp_hdr(skb)->check =
6588 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6589 &ipv6_hdr(skb)->daddr,
6590 0, IPPROTO_TCP, 0);
6591 }
6592
6593 l4len = tcp_hdrlen(skb);
6594 *hdr_len = skb_transport_offset(skb) + l4len;
6595
6596 /* mss_l4len_id: use 1 as index for TSO */
6597 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6598 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6599 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6600
6601 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6602 vlan_macip_lens = skb_network_header_len(skb);
6603 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6604 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6605
6606 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6607 mss_l4len_idx);
6608
6609 return 1;
6610}
6611
6612static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6613 struct sk_buff *skb, u32 tx_flags,
6614 __be16 protocol)
7ca647bd 6615{
897ab156
AD		 6616 u32 vlan_macip_lens = 0;
6617 u32 mss_l4len_idx = 0;
6618 u32 type_tucmd = 0;
7ca647bd 6619
897ab156 6620 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6621 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6622 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6623 return false;
6624 } else {
6625 u8 l4_hdr = 0;
6626 switch (protocol) {
6627 case __constant_htons(ETH_P_IP):
6628 vlan_macip_lens |= skb_network_header_len(skb);
6629 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6630 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6631 break;
897ab156
AD		 6632 case __constant_htons(ETH_P_IPV6):
6633 vlan_macip_lens |= skb_network_header_len(skb);
6634 l4_hdr = ipv6_hdr(skb)->nexthdr;
6635 break;
6636 default:
6637 if (unlikely(net_ratelimit())) {
6638 dev_warn(tx_ring->dev,
6639 "partial checksum but proto=%x!\n",
6640 skb->protocol);
6641 }
7ca647bd
JP		 6642 break;
6643 }
897ab156
AD		 6644
6645 switch (l4_hdr) {
7ca647bd 6646 case IPPROTO_TCP:
897ab156
AD		 6647 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6648 mss_l4len_idx = tcp_hdrlen(skb) <<
6649 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6650 break;
6651 case IPPROTO_SCTP:
897ab156
AD		 6652 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6653 mss_l4len_idx = sizeof(struct sctphdr) <<
6654 IXGBE_ADVTXD_L4LEN_SHIFT;
6655 break;
6656 case IPPROTO_UDP:
6657 mss_l4len_idx = sizeof(struct udphdr) <<
6658 IXGBE_ADVTXD_L4LEN_SHIFT;
6659 break;
6660 default:
6661 if (unlikely(net_ratelimit())) {
6662 dev_warn(tx_ring->dev,
6663 "partial checksum but l4 proto=%x!\n",
6664 skb->protocol);
6665 }
7ca647bd
JP		 6666 break;
6667 }
7ca647bd
JP		 6668 }
6669
897ab156
AD		 6670 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6671 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6672
897ab156
AD		 6673 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6674 type_tucmd, mss_l4len_idx);
9a799d71 6675
897ab156 6676 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6677}
6678
d3d00239 6679static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6680{
d3d00239
AD		 6681 /* set type for advanced descriptor with frame checksum insertion */
6682 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6683 IXGBE_ADVTXD_DCMD_IFCS |
6684 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6685
d3d00239 6686 /* set HW vlan bit if vlan is present */
66f32a8b 6687 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6688 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6689
d3d00239
AD		 6690 /* set segmentation enable bits for TSO/FSO */
6691#ifdef IXGBE_FCOE
6692 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6693#else
6694 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6695#endif
6696 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6697
d3d00239
AD		 6698 return cmd_type;
6699}
9a799d71 6700
d3d00239
AD		 6701static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6702{
6703 __le32 olinfo_status =
6704 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6705
d3d00239
AD		 6706 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6707 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6708 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6709 /* enble IPv4 checksum for TSO */
6710 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6711 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6712 }
6713
d3d00239
AD		 6714 /* enable L4 checksum for TSO and TX checksum offload */
6715 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6716 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6717
d3d00239
AD		 6718#ifdef IXGBE_FCOE
6719 /* use index 1 context for FCOE/FSO */
6720 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6721 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6722 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6723
d3d00239 6724#endif
7f9643fd
AD		 6725 /*
6726 * Check Context must be set if Tx switch is enabled, which it
6727 * always is for case where virtual functions are running
6728 */
6729 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6730 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6731
d3d00239
AD		 6732 return olinfo_status;
6733}
44df32c5 6734
d3d00239
AD		 6735#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6736 IXGBE_TXD_CMD_RS)
6737
6738static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6739 struct sk_buff *skb,
6740 struct ixgbe_tx_buffer *first,
6741 u32 tx_flags,
6742 const u8 hdr_len)
6743{
6744 struct device *dev = tx_ring->dev;
6745 struct ixgbe_tx_buffer *tx_buffer_info;
6746 union ixgbe_adv_tx_desc *tx_desc;
6747 dma_addr_t dma;
6748 __le32 cmd_type, olinfo_status;
6749 struct skb_frag_struct *frag;
6750 unsigned int f = 0;
6751 unsigned int data_len = skb->data_len;
6752 unsigned int size = skb_headlen(skb);
6753 u32 offset = 0;
6754 u32 paylen = skb->len - hdr_len;
6755 u16 i = tx_ring->next_to_use;
6756 u16 gso_segs;
6757
6758#ifdef IXGBE_FCOE
6759 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6760 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6761 data_len -= sizeof(struct fcoe_crc_eof);
6762 } else {
6763 size -= sizeof(struct fcoe_crc_eof) - data_len;
6764 data_len = 0;
9a799d71
AK		 6765 }
6766 }
44df32c5 6767
d3d00239
AD		 6768#endif
6769 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6770 if (dma_mapping_error(dev, dma))
6771 goto dma_error;
8ad494b0 6772
d3d00239
AD		 6773 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6774 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6775
e4f74028 6776 tx_desc = IXGBE_TX_DESC(tx_ring, i);
e5a43549 6777
d3d00239
AD		 6778 for (;;) {
6779 while (size > IXGBE_MAX_DATA_PER_TXD) {
6780 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6781 tx_desc->read.cmd_type_len =
6782 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6783 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6784
d3d00239
AD		 6785 offset += IXGBE_MAX_DATA_PER_TXD;
6786 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6787
d3d00239
AD		 6788 tx_desc++;
6789 i++;
6790 if (i == tx_ring->count) {
e4f74028 6791 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6792 i = 0;
6793 }
6794 }
e5a43549 6795
e5a43549 6796 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6797 tx_buffer_info->length = offset + size;
6798 tx_buffer_info->tx_flags = tx_flags;
6799 tx_buffer_info->dma = dma;
9a799d71 6800
d3d00239 6801 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
f43f313e
BG		 6802 if (unlikely(skb->no_fcs))
6803 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239
AD		 6804 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6805 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6806
d3d00239
AD		 6807 if (!data_len)
6808 break;
9a799d71 6809
d3d00239
AD		 6810 frag = &skb_shinfo(skb)->frags[f];
6811#ifdef IXGBE_FCOE
9e903e08 6812 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6813#else
9e903e08 6814 size = skb_frag_size(frag);
d3d00239
AD		 6815#endif
6816 data_len -= size;
6817 f++;
9a799d71 6818
d3d00239
AD		 6819 offset = 0;
6820 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6821
877749bf 6822 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6823 if (dma_mapping_error(dev, dma))
6824 goto dma_error;
9a799d71 6825
d3d00239
AD		 6826 tx_desc++;
6827 i++;
6828 if (i == tx_ring->count) {
e4f74028 6829 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6830 i = 0;
6831 }
6832 }
9a799d71 6833
d3d00239 6834 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6835
d3d00239
AD		 6836 i++;
6837 if (i == tx_ring->count)
6838 i = 0;
9a799d71 6839
d3d00239 6840 tx_ring->next_to_use = i;
eacd73f7 6841
d3d00239
AD		 6842 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6843 gso_segs = skb_shinfo(skb)->gso_segs;
6844#ifdef IXGBE_FCOE
6845 /* adjust for FCoE Sequence Offload */
6846 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6847 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6848 skb_shinfo(skb)->gso_size);
6849#endif /* IXGBE_FCOE */
6850 else
6851 gso_segs = 1;
9a799d71 6852
d3d00239
AD		 6853 /* multiply data chunks by size of headers */
6854 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6855 tx_buffer_info->gso_segs = gso_segs;
6856 tx_buffer_info->skb = skb;
9a799d71 6857
b2d96e0a
AD		 6858 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer_info->bytecount);
6859
d3d00239
AD		 6860 /* set the timestamp */
6861 first->time_stamp = jiffies;
9a799d71
AK		 6862
6863 /*
6864 * Force memory writes to complete before letting h/w
6865 * know there are new descriptors to fetch. (Only
6866 * applicable for weak-ordered memory model archs,
6867 * such as IA-64).
6868 */
6869 wmb();
6870
d3d00239
AD		 6871 /* set next_to_watch value indicating a packet is present */
6872 first->next_to_watch = tx_desc;
6873
6874 /* notify HW of packet */
84ea2591 6875 writel(i, tx_ring->tail);
d3d00239
AD		 6876
6877 return;
6878dma_error:
6879 dev_err(dev, "TX DMA map failed\n");
6880
6881 /* clear dma mappings for failed tx_buffer_info map */
6882 for (;;) {
6883 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6884 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6885 if (tx_buffer_info == first)
6886 break;
6887 if (i == 0)
6888 i = tx_ring->count;
6889 i--;
6890 }
6891
6892 dev_kfree_skb_any(skb);
6893
6894 tx_ring->next_to_use = i;
9a799d71
AK		 6895}
6896
69830529
AD		 6897static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6898 u32 tx_flags, __be16 protocol)
6899{
6900 struct ixgbe_q_vector *q_vector = ring->q_vector;
6901 union ixgbe_atr_hash_dword input = { .dword = 0 };
6902 union ixgbe_atr_hash_dword common = { .dword = 0 };
6903 union {
6904 unsigned char *network;
6905 struct iphdr *ipv4;
6906 struct ipv6hdr *ipv6;
6907 } hdr;
ee9e0f0b 6908 struct tcphdr *th;
905e4a41 6909 __be16 vlan_id;
c4cf55e5 6910
69830529
AD		 6911 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6912 if (!q_vector)
6913 return;
6914
6915 /* do nothing if sampling is disabled */
6916 if (!ring->atr_sample_rate)
d3ead241 6917 return;
c4cf55e5 6918
69830529 6919 ring->atr_count++;
c4cf55e5 6920
69830529
AD		 6921 /* snag network header to get L4 type and address */
6922 hdr.network = skb_network_header(skb);
6923
6924 /* Currently only IPv4/IPv6 with TCP is supported */
6925 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6926 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6927 (protocol != __constant_htons(ETH_P_IP) ||
6928 hdr.ipv4->protocol != IPPROTO_TCP))
6929 return;
ee9e0f0b
AD		 6930
6931 th = tcp_hdr(skb);
c4cf55e5 6932
66f32a8b
AD		 6933 /* skip this packet since it is invalid or the socket is closing */
6934 if (!th || th->fin)
69830529
AD		 6935 return;
6936
6937 /* sample on all syn packets or once every atr sample count */
6938 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6939 return;
6940
6941 /* reset sample count */
6942 ring->atr_count = 0;
6943
6944 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6945
6946 /*
6947 * src and dst are inverted, think how the receiver sees them
6948 *
6949 * The input is broken into two sections, a non-compressed section
6950 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6951 * is XORed together and stored in the compressed dword.
6952 */
6953 input.formatted.vlan_id = vlan_id;
6954
6955 /*
6956 * since src port and flex bytes occupy the same word XOR them together
6957 * and write the value to source port portion of compressed dword
6958 */
66f32a8b 6959 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6960 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6961 else
6962 common.port.src ^= th->dest ^ protocol;
6963 common.port.dst ^= th->source;
6964
6965 if (protocol == __constant_htons(ETH_P_IP)) {
6966 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6967 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6968 } else {
6969 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6970 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6971 hdr.ipv6->saddr.s6_addr32[1] ^
6972 hdr.ipv6->saddr.s6_addr32[2] ^
6973 hdr.ipv6->saddr.s6_addr32[3] ^
6974 hdr.ipv6->daddr.s6_addr32[0] ^
6975 hdr.ipv6->daddr.s6_addr32[1] ^
6976 hdr.ipv6->daddr.s6_addr32[2] ^
6977 hdr.ipv6->daddr.s6_addr32[3];
6978 }
c4cf55e5
PWJ		 6979
6980 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6981 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6982 input, common, ring->queue_index);
c4cf55e5
PWJ		 6983}
6984
63544e9c 6985static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6986{
fc77dc3c 6987 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6988 /* Herbert's original patch had:
6989 * smp_mb__after_netif_stop_queue();
6990 * but since that doesn't exist yet, just open code it. */
6991 smp_mb();
6992
6993 /* We need to check again in a case another CPU has just
6994 * made room available. */
7d4987de 6995 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6996 return -EBUSY;
6997
6998 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6999 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 7000 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 7001 return 0;
7002}
7003
82d4e46e 7004static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 7005{
7d4987de 7006 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 7007 return 0;
fc77dc3c 7008 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 7009}
7010
09a3b1f8
SH		 7011static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
7012{
7013 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 7014 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7015 smp_processor_id();
56075a98 7016#ifdef IXGBE_FCOE
6440752c 7017 __be16 protocol = vlan_get_protocol(skb);
5e09a105 7018
e5b64635
JF		 7019 if (((protocol == htons(ETH_P_FCOE)) ||
7020 (protocol == htons(ETH_P_FIP))) &&
7021 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
7022 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
7023 txq += adapter->ring_feature[RING_F_FCOE].mask;
7024 return txq;
56075a98
JF		 7025 }
7026#endif
7027
fdd3d631
KK		 7028 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
7029 while (unlikely(txq >= dev->real_num_tx_queues))
7030 txq -= dev->real_num_tx_queues;
5f715823 7031 return txq;
fdd3d631 7032 }
c4cf55e5 7033
09a3b1f8
SH		 7034 return skb_tx_hash(dev, skb);
7035}
7036
fc77dc3c 7037netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7038 struct ixgbe_adapter *adapter,
7039 struct ixgbe_ring *tx_ring)
9a799d71 7040{
d3d00239 7041 struct ixgbe_tx_buffer *first;
5f715823 7042 int tso;
d3d00239 7043 u32 tx_flags = 0;
a535c30e
AD		 7044#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7045 unsigned short f;
7046#endif
a535c30e 7047 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7048 __be16 protocol = skb->protocol;
63544e9c 7049 u8 hdr_len = 0;
5e09a105 7050
a535c30e
AD		 7051 /*
7052 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7053 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7054 * + 2 desc gap to keep tail from touching head,
7055 * + 1 desc for context descriptor,
7056 * otherwise try next time
7057 */
7058#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7059 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7060 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7061#else
7062 count += skb_shinfo(skb)->nr_frags;
7063#endif
7064 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7065 tx_ring->tx_stats.tx_busy++;
7066 return NETDEV_TX_BUSY;
7067 }
7068
66f32a8b 7069 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7070 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7071 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7072 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7073 /* else if it is a SW VLAN check the next protocol and store the tag */
7074 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7075 struct vlan_hdr *vhdr, _vhdr;
7076 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7077 if (!vhdr)
7078 goto out_drop;
7079
7080 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7081 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7082 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7083 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7084 }
7085
9e0c5648
AD		 7086#ifdef CONFIG_PCI_IOV
7087 /*
7088 * Use the l2switch_enable flag - would be false if the DMA
7089 * Tx switch had been disabled.
7090 */
7091 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7092 tx_flags |= IXGBE_TX_FLAGS_TXSW;
7093
7094#endif
32701dc2 7095 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7096 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7097 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7098 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7099 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7100 tx_flags |= (skb->priority & 0x7) <<
7101 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7102 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7103 struct vlan_ethhdr *vhdr;
7104 if (skb_header_cloned(skb) &&
7105 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7106 goto out_drop;
7107 vhdr = (struct vlan_ethhdr *)skb->data;
7108 vhdr->h_vlan_TCI = htons(tx_flags >>
7109 IXGBE_TX_FLAGS_VLAN_SHIFT);
7110 } else {
7111 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7112 }
9a799d71 7113 }
eacd73f7 7114
a535c30e 7115 /* record the location of the first descriptor for this packet */
d3d00239 7116 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 7117
eacd73f7 7118#ifdef IXGBE_FCOE
66f32a8b
AD		 7119 /* setup tx offload for FCoE */
7120 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
7121 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 7122 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
7123 if (tso < 0)
7124 goto out_drop;
7125 else if (tso)
66f32a8b
AD		 7126 tx_flags |= IXGBE_TX_FLAGS_FSO |
7127 IXGBE_TX_FLAGS_FCOE;
7128 else
7129 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 7130
66f32a8b 7131 goto xmit_fcoe;
eacd73f7 7132 }
9a799d71 7133
66f32a8b
AD		 7134#endif /* IXGBE_FCOE */
7135 /* setup IPv4/IPv6 offloads */
7136 if (protocol == __constant_htons(ETH_P_IP))
7137 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 7138
66f32a8b
AD		 7139 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
7140 if (tso < 0)
897ab156 7141 goto out_drop;
66f32a8b
AD		 7142 else if (tso)
7143 tx_flags |= IXGBE_TX_FLAGS_TSO;
7144 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
7145 tx_flags |= IXGBE_TX_FLAGS_CSUM;
7146
7147 /* add the ATR filter if ATR is on */
7148 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7149 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7150
7151#ifdef IXGBE_FCOE
7152xmit_fcoe:
7153#endif /* IXGBE_FCOE */
d3d00239
AD		 7154 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
7155
7156 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7157
7158 return NETDEV_TX_OK;
897ab156
AD		 7159
7160out_drop:
7161 dev_kfree_skb_any(skb);
7162 return NETDEV_TX_OK;
9a799d71
AK		 7163}
7164
84418e3b
AD		 7165static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7166{
7167 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7168 struct ixgbe_ring *tx_ring;
7169
7170 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 7171 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7172}
7173
9a799d71
AK		 7174/**
7175 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7176 * @netdev: network interface device structure
7177 * @p: pointer to an address structure
7178 *
7179 * Returns 0 on success, negative on failure
7180 **/
7181static int ixgbe_set_mac(struct net_device *netdev, void *p)
7182{
7183 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7184 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7185 struct sockaddr *addr = p;
7186
7187 if (!is_valid_ether_addr(addr->sa_data))
7188 return -EADDRNOTAVAIL;
7189
7190 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7191 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7192
1cdd1ec8
GR		 7193 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7194 IXGBE_RAH_AV);
9a799d71
AK		 7195
7196 return 0;
7197}
7198
6b73e10d
BH		 7199static int
7200ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7201{
7202 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7203 struct ixgbe_hw *hw = &adapter->hw;
7204 u16 value;
7205 int rc;
7206
7207 if (prtad != hw->phy.mdio.prtad)
7208 return -EINVAL;
7209 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7210 if (!rc)
7211 rc = value;
7212 return rc;
7213}
7214
7215static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7216 u16 addr, u16 value)
7217{
7218 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7219 struct ixgbe_hw *hw = &adapter->hw;
7220
7221 if (prtad != hw->phy.mdio.prtad)
7222 return -EINVAL;
7223 return hw->phy.ops.write_reg(hw, addr, devad, value);
7224}
7225
7226static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7227{
7228 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7229
7230 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7231}
7232
0365e6e4
PW		 7233/**
7234 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7235 * netdev->dev_addrs
0365e6e4
PW		 7236 * @netdev: network interface device structure
7237 *
7238 * Returns non-zero on failure
7239 **/
7240static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7241{
7242 int err = 0;
7243 struct ixgbe_adapter *adapter = netdev_priv(dev);
7244 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7245
7246 if (is_valid_ether_addr(mac->san_addr)) {
7247 rtnl_lock();
7248 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7249 rtnl_unlock();
7250 }
7251 return err;
7252}
7253
7254/**
7255 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7256 * netdev->dev_addrs
0365e6e4
PW		 7257 * @netdev: network interface device structure
7258 *
7259 * Returns non-zero on failure
7260 **/
7261static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7262{
7263 int err = 0;
7264 struct ixgbe_adapter *adapter = netdev_priv(dev);
7265 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7266
7267 if (is_valid_ether_addr(mac->san_addr)) {
7268 rtnl_lock();
7269 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7270 rtnl_unlock();
7271 }
7272 return err;
7273}
7274
9a799d71
AK		 7275#ifdef CONFIG_NET_POLL_CONTROLLER
7276/*
7277 * Polling 'interrupt' - used by things like netconsole to send skbs
7278 * without having to re-enable interrupts. It's not called while
7279 * the interrupt routine is executing.
7280 */
7281static void ixgbe_netpoll(struct net_device *netdev)
7282{
7283 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7284 int i;
9a799d71 7285
1a647bd2
AD		 7286 /* if interface is down do nothing */
7287 if (test_bit(__IXGBE_DOWN, &adapter->state))
7288 return;
7289
9a799d71 7290 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7291 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7292 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7293 for (i = 0; i < num_q_vectors; i++) {
7294 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7295 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7296 }
7297 } else {
7298 ixgbe_intr(adapter->pdev->irq, netdev);
7299 }
9a799d71 7300 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7301}
7302#endif
7303
de1036b1
ED		 7304static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7305 struct rtnl_link_stats64 *stats)
7306{
7307 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7308 int i;
7309
1a51502b 7310 rcu_read_lock();
de1036b1 7311 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7312 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7313 u64 bytes, packets;
7314 unsigned int start;
7315
1a51502b
ED		 7316 if (ring) {
7317 do {
7318 start = u64_stats_fetch_begin_bh(&ring->syncp);
7319 packets = ring->stats.packets;
7320 bytes = ring->stats.bytes;
7321 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7322 stats->rx_packets += packets;
7323 stats->rx_bytes += bytes;
7324 }
de1036b1 7325 }
1ac9ad13
ED		 7326
7327 for (i = 0; i < adapter->num_tx_queues; i++) {
7328 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7329 u64 bytes, packets;
7330 unsigned int start;
7331
7332 if (ring) {
7333 do {
7334 start = u64_stats_fetch_begin_bh(&ring->syncp);
7335 packets = ring->stats.packets;
7336 bytes = ring->stats.bytes;
7337 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7338 stats->tx_packets += packets;
7339 stats->tx_bytes += bytes;
7340 }
7341 }
1a51502b 7342 rcu_read_unlock();
de1036b1
ED		 7343 /* following stats updated by ixgbe_watchdog_task() */
7344 stats->multicast = netdev->stats.multicast;
7345 stats->rx_errors = netdev->stats.rx_errors;
7346 stats->rx_length_errors = netdev->stats.rx_length_errors;
7347 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7348 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7349 return stats;
7350}
7351
8b1c0b24
JF		 7352/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7353 * #adapter: pointer to ixgbe_adapter
7354 * @tc: number of traffic classes currently enabled
7355 *
7356 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7357 * 802.1Q priority maps to a packet buffer that exists.
7358 */
7359static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7360{
7361 struct ixgbe_hw *hw = &adapter->hw;
7362 u32 reg, rsave;
7363 int i;
7364
7365 /* 82598 have a static priority to TC mapping that can not
7366 * be changed so no validation is needed.
7367 */
7368 if (hw->mac.type == ixgbe_mac_82598EB)
7369 return;
7370
7371 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7372 rsave = reg;
7373
7374 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7375 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7376
7377 /* If up2tc is out of bounds default to zero */
7378 if (up2tc > tc)
7379 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7380 }
7381
7382 if (reg != rsave)
7383 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7384
7385 return;
7386}
7387
7388
7389/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7390 * classes.
7391 *
7392 * @netdev: net device to configure
7393 * @tc: number of traffic classes to enable
7394 */
7395int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7396{
8b1c0b24
JF		 7397 struct ixgbe_adapter *adapter = netdev_priv(dev);
7398 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7399
e7589eab
JF		 7400 /* Multiple traffic classes requires multiple queues */
7401 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7402 e_err(drv, "Enable failed, needs MSI-X\n");
7403 return -EINVAL;
7404 }
8b1c0b24
JF		 7405
7406 /* Hardware supports up to 8 traffic classes */
4de2a022 7407 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7408 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7409 return -EINVAL;
7410
7411 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7412 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7413 * hardware is not flexible enough to do this dynamically.
7414 */
7415 if (netif_running(dev))
7416 ixgbe_close(dev);
7417 ixgbe_clear_interrupt_scheme(adapter);
7418
e7589eab 7419 if (tc) {
8b1c0b24 7420 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7421 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7422
7423 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7424 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7425
7426 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7427 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7428 } else {
8b1c0b24
JF		 7429 netdev_reset_tc(dev);
7430
e7589eab
JF		 7431 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7432
7433 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7434 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7435
7436 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7437 adapter->dcb_cfg.pfc_mode_enable = false;
7438 }
7439
8b1c0b24
JF		 7440 ixgbe_init_interrupt_scheme(adapter);
7441 ixgbe_validate_rtr(adapter, tc);
7442 if (netif_running(dev))
7443 ixgbe_open(dev);
7444
7445 return 0;
7446}
de1036b1 7447
082757af
DS		 7448void ixgbe_do_reset(struct net_device *netdev)
7449{
7450 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7451
7452 if (netif_running(netdev))
7453 ixgbe_reinit_locked(adapter);
7454 else
7455 ixgbe_reset(adapter);
7456}
7457
c8f44aff
MM		 7458static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7459 netdev_features_t data)
082757af
DS		 7460{
7461 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7462
7463#ifdef CONFIG_DCB
7464 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7465 data &= ~NETIF_F_HW_VLAN_RX;
7466#endif
7467
7468 /* return error if RXHASH is being enabled when RSS is not supported */
7469 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7470 data &= ~NETIF_F_RXHASH;
7471
7472 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7473 if (!(data & NETIF_F_RXCSUM))
7474 data &= ~NETIF_F_LRO;
7475
7476 /* Turn off LRO if not RSC capable or invalid ITR settings */
7477 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7478 data &= ~NETIF_F_LRO;
7479 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7480 (adapter->rx_itr_setting != 1 &&
7481 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7482 data &= ~NETIF_F_LRO;
7483 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7484 }
7485
7486 return data;
7487}
7488
c8f44aff
MM		 7489static int ixgbe_set_features(struct net_device *netdev,
7490 netdev_features_t data)
082757af
DS		 7491{
7492 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3f2d1c0f 7493 netdev_features_t changed = netdev->features ^ data;
082757af
DS		 7494 bool need_reset = false;
7495
082757af
DS		 7496 /* Make sure RSC matches LRO, reset if change */
7497 if (!!(data & NETIF_F_LRO) !=
7498 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7499 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7500 switch (adapter->hw.mac.type) {
7501 case ixgbe_mac_X540:
7502 case ixgbe_mac_82599EB:
7503 need_reset = true;
7504 break;
7505 default:
7506 break;
7507 }
7508 }
7509
7510 /*
7511 * Check if Flow Director n-tuple support was enabled or disabled. If
7512 * the state changed, we need to reset.
7513 */
7514 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7515 /* turn off ATR, enable perfect filters and reset */
7516 if (data & NETIF_F_NTUPLE) {
7517 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7518 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7519 need_reset = true;
7520 }
7521 } else if (!(data & NETIF_F_NTUPLE)) {
7522 /* turn off Flow Director, set ATR and reset */
7523 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7524 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7525 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7526 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7527 need_reset = true;
7528 }
7529
3f2d1c0f
BG		 7530 if (changed & NETIF_F_RXALL)
7531 need_reset = true;
7532
7533 netdev->features = data;
082757af
DS		 7534 if (need_reset)
7535 ixgbe_do_reset(netdev);
7536
7537 return 0;
7538
7539}
7540
0edc3527 7541static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7542 .ndo_open = ixgbe_open,
0edc3527 7543 .ndo_stop = ixgbe_close,
00829823 7544 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7545 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7546 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7547 .ndo_validate_addr = eth_validate_addr,
7548 .ndo_set_mac_address = ixgbe_set_mac,
7549 .ndo_change_mtu = ixgbe_change_mtu,
7550 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7551 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7552 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7553 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7554 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7555 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7556 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7557 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7558 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7559 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7560 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7561#ifdef CONFIG_NET_POLL_CONTROLLER
7562 .ndo_poll_controller = ixgbe_netpoll,
7563#endif
332d4a7d
YZ		 7564#ifdef IXGBE_FCOE
7565 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7566 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7567 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7568 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7569 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7570 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7571 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7572#endif /* IXGBE_FCOE */
082757af
DS		 7573 .ndo_set_features = ixgbe_set_features,
7574 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7575};
7576
1cdd1ec8
GR		 7577static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7578 const struct ixgbe_info *ii)
7579{
7580#ifdef CONFIG_PCI_IOV
7581 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7582
c6bda30a 7583 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7584 return;
7585
7586 /* The 82599 supports up to 64 VFs per physical function
7587 * but this implementation limits allocation to 63 so that
7588 * basic networking resources are still available to the
7589 * physical function
7590 */
7591 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7592 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7593#endif /* CONFIG_PCI_IOV */
7594}
7595
9a799d71
AK		 7596/**
7597 * ixgbe_probe - Device Initialization Routine
7598 * @pdev: PCI device information struct
7599 * @ent: entry in ixgbe_pci_tbl
7600 *
7601 * Returns 0 on success, negative on failure
7602 *
7603 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7604 * The OS initialization, configuring of the adapter private structure,
7605 * and a hardware reset occur.
7606 **/
7607static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7608 const struct pci_device_id *ent)
9a799d71
AK		 7609{
7610 struct net_device *netdev;
7611 struct ixgbe_adapter *adapter = NULL;
7612 struct ixgbe_hw *hw;
7613 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7614 static int cards_found;
7615 int i, err, pci_using_dac;
289700db 7616 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7617 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7618#ifdef IXGBE_FCOE
7619 u16 device_caps;
7620#endif
289700db 7621 u32 eec;
c23f5b6b 7622 u16 wol_cap;
9a799d71 7623
bded64a7
AG		 7624 /* Catch broken hardware that put the wrong VF device ID in
7625 * the PCIe SR-IOV capability.
7626 */
7627 if (pdev->is_virtfn) {
7628 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7629 pci_name(pdev), pdev->vendor, pdev->device);
7630 return -EINVAL;
7631 }
7632
9ce77666 7633 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7634 if (err)
7635 return err;
7636
1b507730
NN		 7637 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7638 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7639 pci_using_dac = 1;
7640 } else {
1b507730 7641 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7642 if (err) {
1b507730
NN		 7643 err = dma_set_coherent_mask(&pdev->dev,
7644 DMA_BIT_MASK(32));
9a799d71 7645 if (err) {
b8bc0421
DC		 7646 dev_err(&pdev->dev,
7647 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7648 goto err_dma;
7649 }
7650 }
7651 pci_using_dac = 0;
7652 }
7653
9ce77666 7654 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7655 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7656 if (err) {
b8bc0421
DC		 7657 dev_err(&pdev->dev,
7658 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7659 goto err_pci_reg;
7660 }
7661
19d5afd4 7662 pci_enable_pcie_error_reporting(pdev);
6fabd715 7663
9a799d71 7664 pci_set_master(pdev);
fb3b27bc 7665 pci_save_state(pdev);
9a799d71 7666
e901acd6
JF		 7667#ifdef CONFIG_IXGBE_DCB
7668 indices *= MAX_TRAFFIC_CLASS;
7669#endif
7670
c85a2618
JF		 7671 if (ii->mac == ixgbe_mac_82598EB)
7672 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7673 else
7674 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7675
e901acd6 7676#ifdef IXGBE_FCOE
c85a2618
JF		 7677 indices += min_t(unsigned int, num_possible_cpus(),
7678 IXGBE_MAX_FCOE_INDICES);
7679#endif
c85a2618 7680 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7681 if (!netdev) {
7682 err = -ENOMEM;
7683 goto err_alloc_etherdev;
7684 }
7685
9a799d71
AK		 7686 SET_NETDEV_DEV(netdev, &pdev->dev);
7687
9a799d71 7688 adapter = netdev_priv(netdev);
c60fbb00 7689 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7690
7691 adapter->netdev = netdev;
7692 adapter->pdev = pdev;
7693 hw = &adapter->hw;
7694 hw->back = adapter;
7695 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7696
05857980 7697 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7698 pci_resource_len(pdev, 0));
9a799d71
AK		 7699 if (!hw->hw_addr) {
7700 err = -EIO;
7701 goto err_ioremap;
7702 }
7703
7704 for (i = 1; i <= 5; i++) {
7705 if (pci_resource_len(pdev, i) == 0)
7706 continue;
7707 }
7708
0edc3527 7709 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7710 ixgbe_set_ethtool_ops(netdev);
9a799d71 7711 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7712 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7713
9a799d71
AK		 7714 adapter->bd_number = cards_found;
7715
9a799d71
AK		 7716 /* Setup hw api */
7717 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7718 hw->mac.type = ii->mac;
9a799d71 7719
c44ade9e
JB		 7720 /* EEPROM */
7721 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7722 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7723 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7724 if (!(eec & (1 << 8)))
7725 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7726
7727 /* PHY */
7728 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7729 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7730 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7731 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7732 hw->phy.mdio.mmds = 0;
7733 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7734 hw->phy.mdio.dev = netdev;
7735 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7736 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7737
8ca783ab 7738 ii->get_invariants(hw);
9a799d71
AK		 7739
7740 /* setup the private structure */
7741 err = ixgbe_sw_init(adapter);
7742 if (err)
7743 goto err_sw_init;
7744
e86bff0e 7745 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7746 switch (adapter->hw.mac.type) {
7747 case ixgbe_mac_82599EB:
7748 case ixgbe_mac_X540:
e86bff0e 7749 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7750 break;
7751 default:
7752 break;
7753 }
e86bff0e 7754
bf069c97
DS		 7755 /*
7756 * If there is a fan on this device and it has failed log the
7757 * failure.
7758 */
7759 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7760 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7761 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7762 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7763 }
7764
8ef78adc
PWJ		 7765 if (allow_unsupported_sfp)
7766 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7767
c44ade9e 7768 /* reset_hw fills in the perm_addr as well */
119fc60a 7769 hw->phy.reset_if_overtemp = true;
c44ade9e 7770 err = hw->mac.ops.reset_hw(hw);
119fc60a 7771 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7772 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7773 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7774 err = 0;
7775 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7776 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7777 "module type was detected.\n");
7778 e_dev_err("Reload the driver after installing a supported "
7779 "module.\n");
04f165ef
PW		 7780 goto err_sw_init;
7781 } else if (err) {
849c4542 7782 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7783 goto err_sw_init;
7784 }
7785
1cdd1ec8
GR		 7786 ixgbe_probe_vf(adapter, ii);
7787
396e799c 7788 netdev->features = NETIF_F_SG |
e8e9f696 7789 NETIF_F_IP_CSUM |
082757af 7790 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7791 NETIF_F_HW_VLAN_TX |
7792 NETIF_F_HW_VLAN_RX |
082757af
DS		 7793 NETIF_F_HW_VLAN_FILTER |
7794 NETIF_F_TSO |
7795 NETIF_F_TSO6 |
082757af
DS		 7796 NETIF_F_RXHASH |
7797 NETIF_F_RXCSUM;
9a799d71 7798
082757af 7799 netdev->hw_features = netdev->features;
ad31c402 7800
58be7666
DS		 7801 switch (adapter->hw.mac.type) {
7802 case ixgbe_mac_82599EB:
7803 case ixgbe_mac_X540:
45a5ead0 7804 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7805 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7806 NETIF_F_NTUPLE;
58be7666
DS		 7807 break;
7808 default:
7809 break;
7810 }
45a5ead0 7811
3f2d1c0f
BG		 7812 netdev->hw_features |= NETIF_F_RXALL;
7813
ad31c402
JK		 7814 netdev->vlan_features |= NETIF_F_TSO;
7815 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7816 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7817 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7818 netdev->vlan_features |= NETIF_F_SG;
7819
01789349 7820 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7821 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7822
1cdd1ec8
GR		 7823 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7824 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7825 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7826
7a6b6f51 7827#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7828 netdev->dcbnl_ops = &dcbnl_ops;
7829#endif
7830
eacd73f7 7831#ifdef IXGBE_FCOE
0d551589 7832 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7833 if (hw->mac.ops.get_device_caps) {
7834 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7835 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7836 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7837 }
7838 }
5e09d7f6
YZ		 7839 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7840 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7841 netdev->vlan_features |= NETIF_F_FSO;
7842 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7843 }
eacd73f7 7844#endif /* IXGBE_FCOE */
7b872a55 7845 if (pci_using_dac) {
9a799d71 7846 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7847 netdev->vlan_features |= NETIF_F_HIGHDMA;
7848 }
9a799d71 7849
082757af
DS		 7850 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7851 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7852 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7853 netdev->features |= NETIF_F_LRO;
7854
9a799d71 7855 /* make sure the EEPROM is good */
c44ade9e 7856 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7857 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7858 err = -EIO;
7859 goto err_eeprom;
7860 }
7861
7862 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7863 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7864
c44ade9e 7865 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7866 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7867 err = -EIO;
7868 goto err_eeprom;
7869 }
7870
7086400d
AD		 7871 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7872 (unsigned long) adapter);
9a799d71 7873
7086400d
AD		 7874 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7875 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7876
021230d4
AV		 7877 err = ixgbe_init_interrupt_scheme(adapter);
7878 if (err)
7879 goto err_sw_init;
9a799d71 7880
082757af
DS		 7881 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7882 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7883 netdev->features &= ~NETIF_F_RXHASH;
082757af 7884 }
67a74ee2 7885
c23f5b6b
ET		 7886 /* WOL not supported for all but the following */
7887 adapter->wol = 0;
e8e26350 7888 switch (pdev->device) {
0b077fea 7889 case IXGBE_DEV_ID_82599_SFP:
0e22d043
DS		 7890 /* Only these subdevice supports WOL */
7891 switch (pdev->subsystem_device) {
7892 case IXGBE_SUBDEV_ID_82599_560FLR:
7893 /* only support first port */
7894 if (hw->bus.func != 0)
7895 break;
7896 case IXGBE_SUBDEV_ID_82599_SFP:
9417c464 7897 adapter->wol = IXGBE_WUFC_MAG;
0e22d043
DS		 7898 break;
7899 }
0b077fea 7900 break;
50d6c681
AD		 7901 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7902 /* All except this subdevice support WOL */
0b077fea 7903 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7904 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7905 break;
e8e26350 7906 case IXGBE_DEV_ID_82599_KX4:
9417c464 7907 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7908 break;
c23f5b6b
ET		 7909 case IXGBE_DEV_ID_X540T:
7910 /* Check eeprom to see if it is enabled */
7911 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7912 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7913
7914 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7915 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7916 (hw->bus.func == 0)))
7917 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7918 break;
7919 }
e8e26350
PW		 7920 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7921
15e5209f
ET		 7922 /* save off EEPROM version number */
7923 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7924 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7925
04f165ef
PW		 7926 /* pick up the PCI bus settings for reporting later */
7927 hw->mac.ops.get_bus_info(hw);
7928
9a799d71 7929 /* print bus type/speed/width info */
849c4542 7930 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7931 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7932 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7933 "Unknown"),
7934 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7935 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7936 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7937 "Unknown"),
7938 netdev->dev_addr);
289700db
DS		 7939
7940 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7941 if (err)
9fe93afd 7942 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7943 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7944 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7945 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7946 part_str);
e8e26350 7947 else
289700db
DS		 7948 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7949 hw->mac.type, hw->phy.type, part_str);
9a799d71 7950
e8e26350 7951 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7952 e_dev_warn("PCI-Express bandwidth available for this card is "
7953 "not sufficient for optimal performance.\n");
7954 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7955 "is required.\n");
0c254d86
AK		 7956 }
7957
9a799d71 7958 /* reset the hardware with the new settings */
794caeb2 7959 err = hw->mac.ops.start_hw(hw);
c44ade9e 7960
794caeb2
PWJ		 7961 if (err == IXGBE_ERR_EEPROM_VERSION) {
7962 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7963 e_dev_warn("This device is a pre-production adapter/LOM. "
7964 "Please be aware there may be issues associated "
7965 "with your hardware. If you are experiencing "
7966 "problems please contact your Intel or hardware "
7967 "representative who provided you with this "
7968 "hardware.\n");
794caeb2 7969 }
9a799d71
AK		 7970 strcpy(netdev->name, "eth%d");
7971 err = register_netdev(netdev);
7972 if (err)
7973 goto err_register;
7974
93d3ce8f
ET		 7975 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7976 if (hw->mac.ops.disable_tx_laser &&
7977 ((hw->phy.multispeed_fiber) ||
7978 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7979 (hw->mac.type == ixgbe_mac_82599EB))))
7980 hw->mac.ops.disable_tx_laser(hw);
7981
54386467
JB		 7982 /* carrier off reporting is important to ethtool even BEFORE open */
7983 netif_carrier_off(netdev);
7984
5dd2d332 7985#ifdef CONFIG_IXGBE_DCA
652f093f 7986 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7987 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7988 ixgbe_setup_dca(adapter);
7989 }
7990#endif
1cdd1ec8 7991 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7992 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7993 for (i = 0; i < adapter->num_vfs; i++)
7994 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7995 }
7996
2466dd9c
JK		 7997 /* firmware requires driver version to be 0xFFFFFFFF
7998 * since os does not support feature
7999 */
9612de92 8000 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8001 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8002 0xFF);
9612de92 8003
0365e6e4
PW		 8004 /* add san mac addr to netdev */
8005 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8006
ea81875a 8007 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71
AK		 8008 cards_found++;
8009 return 0;
8010
8011err_register:
5eba3699 8012 ixgbe_release_hw_control(adapter);
7a921c93 8013 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 8014err_sw_init:
8015err_eeprom:
1cdd1ec8
GR		 8016 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8017 ixgbe_disable_sriov(adapter);
7086400d 8018 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 8019 iounmap(hw->hw_addr);
8020err_ioremap:
8021 free_netdev(netdev);
8022err_alloc_etherdev:
e8e9f696
JP		 8023 pci_release_selected_regions(pdev,
8024 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8025err_pci_reg:
8026err_dma:
8027 pci_disable_device(pdev);
8028 return err;
8029}
8030
8031/**
8032 * ixgbe_remove - Device Removal Routine
8033 * @pdev: PCI device information struct
8034 *
8035 * ixgbe_remove is called by the PCI subsystem to alert the driver
8036 * that it should release a PCI device. The could be caused by a
8037 * Hot-Plug event, or because the driver is going to be removed from
8038 * memory.
8039 **/
8040static void __devexit ixgbe_remove(struct pci_dev *pdev)
8041{
c60fbb00
AD		 8042 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8043 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 8044
8045 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 8046 cancel_work_sync(&adapter->service_task);
9a799d71 8047
5dd2d332 8048#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8049 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8050 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8051 dca_remove_requester(&pdev->dev);
8052 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8053 }
8054
8055#endif
332d4a7d
YZ		 8056#ifdef IXGBE_FCOE
8057 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
8058 ixgbe_cleanup_fcoe(adapter);
8059
8060#endif /* IXGBE_FCOE */
0365e6e4
PW		 8061
8062 /* remove the added san mac */
8063 ixgbe_del_sanmac_netdev(netdev);
8064
c4900be0
DS		 8065 if (netdev->reg_state == NETREG_REGISTERED)
8066 unregister_netdev(netdev);
9a799d71 8067
c6bda30a
GR		 8068 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8069 if (!(ixgbe_check_vf_assignment(adapter)))
8070 ixgbe_disable_sriov(adapter);
8071 else
8072 e_dev_warn("Unloading driver while VFs are assigned "
8073 "- VFs will not be deallocated\n");
8074 }
1cdd1ec8 8075
7a921c93 8076 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8077
021230d4 8078 ixgbe_release_hw_control(adapter);
9a799d71
AK		 8079
8080 iounmap(adapter->hw.hw_addr);
9ce77666 8081 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8082 IORESOURCE_MEM));
9a799d71 8083
849c4542 8084 e_dev_info("complete\n");
021230d4 8085
9a799d71
AK		 8086 free_netdev(netdev);
8087
19d5afd4 8088 pci_disable_pcie_error_reporting(pdev);
6fabd715 8089
9a799d71
AK		 8090 pci_disable_device(pdev);
8091}
8092
8093/**
8094 * ixgbe_io_error_detected - called when PCI error is detected
8095 * @pdev: Pointer to PCI device
8096 * @state: The current pci connection state
8097 *
8098 * This function is called after a PCI bus error affecting
8099 * this device has been detected.
8100 */
8101static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8102 pci_channel_state_t state)
9a799d71 8103{
c60fbb00
AD		 8104 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8105 struct net_device *netdev = adapter->netdev;
9a799d71 8106
83c61fa9
GR		 8107#ifdef CONFIG_PCI_IOV
8108 struct pci_dev *bdev, *vfdev;
8109 u32 dw0, dw1, dw2, dw3;
8110 int vf, pos;
8111 u16 req_id, pf_func;
8112
8113 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8114 adapter->num_vfs == 0)
8115 goto skip_bad_vf_detection;
8116
8117 bdev = pdev->bus->self;
8118 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
8119 bdev = bdev->bus->self;
8120
8121 if (!bdev)
8122 goto skip_bad_vf_detection;
8123
8124 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8125 if (!pos)
8126 goto skip_bad_vf_detection;
8127
8128 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8129 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8130 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8131 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8132
8133 req_id = dw1 >> 16;
8134 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8135 if (!(req_id & 0x0080))
8136 goto skip_bad_vf_detection;
8137
8138 pf_func = req_id & 0x01;
8139 if ((pf_func & 1) == (pdev->devfn & 1)) {
8140 unsigned int device_id;
8141
8142 vf = (req_id & 0x7F) >> 1;
8143 e_dev_err("VF %d has caused a PCIe error\n", vf);
8144 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8145 "%8.8x\tdw3: %8.8x\n",
8146 dw0, dw1, dw2, dw3);
8147 switch (adapter->hw.mac.type) {
8148 case ixgbe_mac_82599EB:
8149 device_id = IXGBE_82599_VF_DEVICE_ID;
8150 break;
8151 case ixgbe_mac_X540:
8152 device_id = IXGBE_X540_VF_DEVICE_ID;
8153 break;
8154 default:
8155 device_id = 0;
8156 break;
8157 }
8158
8159 /* Find the pci device of the offending VF */
8160 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
8161 while (vfdev) {
8162 if (vfdev->devfn == (req_id & 0xFF))
8163 break;
8164 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
8165 device_id, vfdev);
8166 }
8167 /*
8168 * There's a slim chance the VF could have been hot plugged,
8169 * so if it is no longer present we don't need to issue the
8170 * VFLR. Just clean up the AER in that case.
8171 */
8172 if (vfdev) {
8173 e_dev_err("Issuing VFLR to VF %d\n", vf);
8174 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8175 }
8176
8177 pci_cleanup_aer_uncorrect_error_status(pdev);
8178 }
8179
8180 /*
8181 * Even though the error may have occurred on the other port
8182 * we still need to increment the vf error reference count for
8183 * both ports because the I/O resume function will be called
8184 * for both of them.
8185 */
8186 adapter->vferr_refcount++;
8187
8188 return PCI_ERS_RESULT_RECOVERED;
8189
8190skip_bad_vf_detection:
8191#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8192 netif_device_detach(netdev);
8193
3044b8d1
BL		 8194 if (state == pci_channel_io_perm_failure)
8195 return PCI_ERS_RESULT_DISCONNECT;
8196
9a799d71
AK		 8197 if (netif_running(netdev))
8198 ixgbe_down(adapter);
8199 pci_disable_device(pdev);
8200
b4617240 8201 /* Request a slot reset. */
9a799d71
AK		 8202 return PCI_ERS_RESULT_NEED_RESET;
8203}
8204
8205/**
8206 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8207 * @pdev: Pointer to PCI device
8208 *
8209 * Restart the card from scratch, as if from a cold-boot.
8210 */
8211static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8212{
c60fbb00 8213 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8214 pci_ers_result_t result;
8215 int err;
9a799d71 8216
9ce77666 8217 if (pci_enable_device_mem(pdev)) {
396e799c 8218 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8219 result = PCI_ERS_RESULT_DISCONNECT;
8220 } else {
8221 pci_set_master(pdev);
8222 pci_restore_state(pdev);
c0e1f68b 8223 pci_save_state(pdev);
9a799d71 8224
dd4d8ca6 8225 pci_wake_from_d3(pdev, false);
9a799d71 8226
6fabd715 8227 ixgbe_reset(adapter);
88512539 8228 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8229 result = PCI_ERS_RESULT_RECOVERED;
8230 }
8231
8232 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8233 if (err) {
849c4542
ET		 8234 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8235 "failed 0x%0x\n", err);
6fabd715
PWJ		 8236 /* non-fatal, continue */
8237 }
9a799d71 8238
6fabd715 8239 return result;
9a799d71
AK		 8240}
8241
8242/**
8243 * ixgbe_io_resume - called when traffic can start flowing again.
8244 * @pdev: Pointer to PCI device
8245 *
8246 * This callback is called when the error recovery driver tells us that
8247 * its OK to resume normal operation.
8248 */
8249static void ixgbe_io_resume(struct pci_dev *pdev)
8250{
c60fbb00
AD		 8251 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8252 struct net_device *netdev = adapter->netdev;
9a799d71 8253
83c61fa9
GR		 8254#ifdef CONFIG_PCI_IOV
8255 if (adapter->vferr_refcount) {
8256 e_info(drv, "Resuming after VF err\n");
8257 adapter->vferr_refcount--;
8258 return;
8259 }
8260
8261#endif
c7ccde0f
AD		 8262 if (netif_running(netdev))
8263 ixgbe_up(adapter);
9a799d71
AK		 8264
8265 netif_device_attach(netdev);
9a799d71
AK		 8266}
8267
8268static struct pci_error_handlers ixgbe_err_handler = {
8269 .error_detected = ixgbe_io_error_detected,
8270 .slot_reset = ixgbe_io_slot_reset,
8271 .resume = ixgbe_io_resume,
8272};
8273
8274static struct pci_driver ixgbe_driver = {
8275 .name = ixgbe_driver_name,
8276 .id_table = ixgbe_pci_tbl,
8277 .probe = ixgbe_probe,
8278 .remove = __devexit_p(ixgbe_remove),
8279#ifdef CONFIG_PM
8280 .suspend = ixgbe_suspend,
8281 .resume = ixgbe_resume,
8282#endif
8283 .shutdown = ixgbe_shutdown,
8284 .err_handler = &ixgbe_err_handler
8285};
8286
8287/**
8288 * ixgbe_init_module - Driver Registration Routine
8289 *
8290 * ixgbe_init_module is the first routine called when the driver is
8291 * loaded. All it does is register with the PCI subsystem.
8292 **/
8293static int __init ixgbe_init_module(void)
8294{
8295 int ret;
c7689578 8296 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8297 pr_info("%s\n", ixgbe_copyright);
9a799d71 8298
5dd2d332 8299#ifdef CONFIG_IXGBE_DCA
bd0362dd 8300 dca_register_notify(&dca_notifier);
bd0362dd 8301#endif
5dd2d332 8302
9a799d71
AK		 8303 ret = pci_register_driver(&ixgbe_driver);
8304 return ret;
8305}
b4617240 8306
9a799d71
AK		 8307module_init(ixgbe_init_module);
8308
8309/**
8310 * ixgbe_exit_module - Driver Exit Cleanup Routine
8311 *
8312 * ixgbe_exit_module is called just before the driver is removed
8313 * from memory.
8314 **/
8315static void __exit ixgbe_exit_module(void)
8316{
5dd2d332 8317#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8318 dca_unregister_notify(&dca_notifier);
8319#endif
9a799d71 8320 pci_unregister_driver(&ixgbe_driver);
1a51502b 8321 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8322}
bd0362dd 8323
5dd2d332 8324#ifdef CONFIG_IXGBE_DCA
bd0362dd 8325static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8326 void *p)
bd0362dd
JC		 8327{
8328 int ret_val;
8329
8330 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8331 __ixgbe_notify_dca);
bd0362dd
JC		 8332
8333 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8334}
b453368d 8335
5dd2d332 8336#endif /* CONFIG_IXGBE_DCA */
849c4542 8337
9a799d71
AK		 8338module_exit(ixgbe_exit_module);
8339
8340/* ixgbe_main.c */
Linux kernel - Deliverables
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