Commit | Line | Data |
---|---|---|
9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
37689010 | 4 | Copyright(c) 1999 - 2016 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
b89aae71 | 23 | Linux NICS <linux.nics@intel.com> |
9a799d71 AK |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/types.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/netdevice.h> | |
33 | #include <linux/vmalloc.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/in.h> | |
a6b7a407 | 36 | #include <linux/interrupt.h> |
9a799d71 AK |
37 | #include <linux/ip.h> |
38 | #include <linux/tcp.h> | |
897ab156 | 39 | #include <linux/sctp.h> |
60127865 | 40 | #include <linux/pkt_sched.h> |
9a799d71 | 41 | #include <linux/ipv6.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
9a799d71 AK |
43 | #include <net/checksum.h> |
44 | #include <net/ip6_checksum.h> | |
c762dff2 | 45 | #include <linux/etherdevice.h> |
9a799d71 | 46 | #include <linux/ethtool.h> |
01789349 | 47 | #include <linux/if.h> |
9a799d71 | 48 | #include <linux/if_vlan.h> |
2a47fa45 | 49 | #include <linux/if_macvlan.h> |
815cccbf | 50 | #include <linux/if_bridge.h> |
70c71606 | 51 | #include <linux/prefetch.h> |
eacd73f7 | 52 | #include <scsi/fc/fc_fcoe.h> |
3f207800 | 53 | #include <net/vxlan.h> |
b82b17d9 JF |
54 | #include <net/pkt_cls.h> |
55 | #include <net/tc_act/tc_gact.h> | |
947f8a45 | 56 | #include <net/tc_act/tc_mirred.h> |
9a799d71 AK |
57 | |
58 | #include "ixgbe.h" | |
59 | #include "ixgbe_common.h" | |
ee5f784a | 60 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 61 | #include "ixgbe_sriov.h" |
b82b17d9 | 62 | #include "ixgbe_model.h" |
9a799d71 AK |
63 | |
64 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 65 | static const char ixgbe_driver_string[] = |
e8e9f696 | 66 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 67 | #ifdef IXGBE_FCOE |
ea81875a NP |
68 | char ixgbe_default_device_descr[] = |
69 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
70 | #else |
71 | static char ixgbe_default_device_descr[] = | |
72 | "Intel(R) 10 Gigabit Network Connection"; | |
73 | #endif | |
10ef00fe | 74 | #define DRV_VERSION "4.4.0-k" |
9c8eb720 | 75 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 76 | static const char ixgbe_copyright[] = |
49425dfc | 77 | "Copyright (c) 1999-2016 Intel Corporation."; |
9a799d71 | 78 | |
f44e751b DS |
79 | static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter"; |
80 | ||
9a799d71 | 81 | static const struct ixgbe_info *ixgbe_info_tbl[] = { |
6a14ee0c DS |
82 | [board_82598] = &ixgbe_82598_info, |
83 | [board_82599] = &ixgbe_82599_info, | |
84 | [board_X540] = &ixgbe_X540_info, | |
85 | [board_X550] = &ixgbe_X550_info, | |
86 | [board_X550EM_x] = &ixgbe_X550EM_x_info, | |
49425dfc | 87 | [board_x550em_a] = &ixgbe_x550em_a_info, |
9a799d71 AK |
88 | }; |
89 | ||
90 | /* ixgbe_pci_tbl - PCI Device ID Table | |
91 | * | |
92 | * Wildcard entries (PCI_ANY_ID) should come last | |
93 | * Last entry must be all 0s | |
94 | * | |
95 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
96 | * Class, Class Mask, private data (not used) } | |
97 | */ | |
9baa3c34 | 98 | static const struct pci_device_id ixgbe_pci_tbl[] = { |
54239c67 AD |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
117 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
118 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
119 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
120 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
121 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
122 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
123 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
124 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
8f58332b | 125 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 }, |
7d145282 | 126 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 127 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
df376f0d | 128 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 }, |
6a14ee0c | 129 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550}, |
a711ad89 | 130 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550}, |
6a14ee0c DS |
131 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x}, |
132 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x}, | |
deda562a | 133 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x}, |
018d7146 | 134 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x}, |
f572b2c4 MR |
135 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a }, |
136 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a }, | |
49425dfc | 137 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a }, |
200157c2 MR |
138 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a }, |
139 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a }, | |
2d40cd17 | 140 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a }, |
9a799d71 AK |
141 | /* required last entry */ |
142 | {0, } | |
143 | }; | |
144 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
145 | ||
5dd2d332 | 146 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 147 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 148 | void *p); |
bd0362dd JC |
149 | static struct notifier_block dca_notifier = { |
150 | .notifier_call = ixgbe_notify_dca, | |
151 | .next = NULL, | |
152 | .priority = 0 | |
153 | }; | |
154 | #endif | |
155 | ||
1cdd1ec8 GR |
156 | #ifdef CONFIG_PCI_IOV |
157 | static unsigned int max_vfs; | |
158 | module_param(max_vfs, uint, 0); | |
e8e9f696 | 159 | MODULE_PARM_DESC(max_vfs, |
170e8543 | 160 | "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)"); |
1cdd1ec8 GR |
161 | #endif /* CONFIG_PCI_IOV */ |
162 | ||
8ef78adc PWJ |
163 | static unsigned int allow_unsupported_sfp; |
164 | module_param(allow_unsupported_sfp, uint, 0); | |
165 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
166 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
167 | ||
b3f4d599 | 168 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
169 | static int debug = -1; | |
170 | module_param(debug, int, 0); | |
171 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
172 | ||
9a799d71 AK |
173 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
174 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
175 | MODULE_LICENSE("GPL"); | |
176 | MODULE_VERSION(DRV_VERSION); | |
177 | ||
780484d8 MR |
178 | static struct workqueue_struct *ixgbe_wq; |
179 | ||
14438464 MR |
180 | static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev); |
181 | ||
b8e82001 JK |
182 | static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter, |
183 | u32 reg, u16 *value) | |
184 | { | |
b8e82001 JK |
185 | struct pci_dev *parent_dev; |
186 | struct pci_bus *parent_bus; | |
187 | ||
188 | parent_bus = adapter->pdev->bus->parent; | |
189 | if (!parent_bus) | |
190 | return -1; | |
191 | ||
192 | parent_dev = parent_bus->self; | |
193 | if (!parent_dev) | |
194 | return -1; | |
195 | ||
c0798edf | 196 | if (!pci_is_pcie(parent_dev)) |
b8e82001 JK |
197 | return -1; |
198 | ||
c0798edf | 199 | pcie_capability_read_word(parent_dev, reg, value); |
14438464 MR |
200 | if (*value == IXGBE_FAILED_READ_CFG_WORD && |
201 | ixgbe_check_cfg_remove(&adapter->hw, parent_dev)) | |
202 | return -1; | |
b8e82001 JK |
203 | return 0; |
204 | } | |
205 | ||
206 | static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter) | |
207 | { | |
208 | struct ixgbe_hw *hw = &adapter->hw; | |
209 | u16 link_status = 0; | |
210 | int err; | |
211 | ||
212 | hw->bus.type = ixgbe_bus_type_pci_express; | |
213 | ||
214 | /* Get the negotiated link width and speed from PCI config space of the | |
215 | * parent, as this device is behind a switch | |
216 | */ | |
217 | err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status); | |
218 | ||
219 | /* assume caller will handle error case */ | |
220 | if (err) | |
221 | return err; | |
222 | ||
223 | hw->bus.width = ixgbe_convert_bus_width(link_status); | |
224 | hw->bus.speed = ixgbe_convert_bus_speed(link_status); | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
e027d1ae JK |
229 | /** |
230 | * ixgbe_check_from_parent - Determine whether PCIe info should come from parent | |
231 | * @hw: hw specific details | |
232 | * | |
233 | * This function is used by probe to determine whether a device's PCI-Express | |
234 | * bandwidth details should be gathered from the parent bus instead of from the | |
235 | * device. Used to ensure that various locations all have the correct device ID | |
236 | * checks. | |
237 | */ | |
238 | static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw) | |
239 | { | |
240 | switch (hw->device_id) { | |
241 | case IXGBE_DEV_ID_82599_SFP_SF_QP: | |
8f58332b | 242 | case IXGBE_DEV_ID_82599_QSFP_SF_QP: |
e027d1ae JK |
243 | return true; |
244 | default: | |
245 | return false; | |
246 | } | |
247 | } | |
248 | ||
249 | static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter, | |
250 | int expected_gts) | |
251 | { | |
f9328bc6 | 252 | struct ixgbe_hw *hw = &adapter->hw; |
e027d1ae JK |
253 | int max_gts = 0; |
254 | enum pci_bus_speed speed = PCI_SPEED_UNKNOWN; | |
255 | enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN; | |
256 | struct pci_dev *pdev; | |
257 | ||
f9328bc6 DS |
258 | /* Some devices are not connected over PCIe and thus do not negotiate |
259 | * speed. These devices do not have valid bus info, and thus any report | |
260 | * we generate may not be correct. | |
261 | */ | |
262 | if (hw->bus.type == ixgbe_bus_type_internal) | |
263 | return; | |
264 | ||
56d1392f | 265 | /* determine whether to use the parent device */ |
e027d1ae JK |
266 | if (ixgbe_pcie_from_parent(&adapter->hw)) |
267 | pdev = adapter->pdev->bus->parent->self; | |
268 | else | |
269 | pdev = adapter->pdev; | |
270 | ||
271 | if (pcie_get_minimum_link(pdev, &speed, &width) || | |
272 | speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { | |
273 | e_dev_warn("Unable to determine PCI Express bandwidth.\n"); | |
274 | return; | |
275 | } | |
276 | ||
277 | switch (speed) { | |
278 | case PCIE_SPEED_2_5GT: | |
279 | /* 8b/10b encoding reduces max throughput by 20% */ | |
280 | max_gts = 2 * width; | |
281 | break; | |
282 | case PCIE_SPEED_5_0GT: | |
283 | /* 8b/10b encoding reduces max throughput by 20% */ | |
284 | max_gts = 4 * width; | |
285 | break; | |
286 | case PCIE_SPEED_8_0GT: | |
9f0a433c | 287 | /* 128b/130b encoding reduces throughput by less than 2% */ |
e027d1ae JK |
288 | max_gts = 8 * width; |
289 | break; | |
290 | default: | |
291 | e_dev_warn("Unable to determine PCI Express bandwidth.\n"); | |
292 | return; | |
293 | } | |
294 | ||
295 | e_dev_info("PCI Express bandwidth of %dGT/s available\n", | |
296 | max_gts); | |
297 | e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n", | |
298 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : | |
299 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : | |
300 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : | |
301 | "Unknown"), | |
302 | width, | |
303 | (speed == PCIE_SPEED_2_5GT ? "20%" : | |
304 | speed == PCIE_SPEED_5_0GT ? "20%" : | |
9f0a433c | 305 | speed == PCIE_SPEED_8_0GT ? "<2%" : |
e027d1ae JK |
306 | "Unknown")); |
307 | ||
308 | if (max_gts < expected_gts) { | |
309 | e_dev_warn("This is not sufficient for optimal performance of this card.\n"); | |
310 | e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n", | |
311 | expected_gts); | |
312 | e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n"); | |
313 | } | |
314 | } | |
315 | ||
7086400d AD |
316 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
317 | { | |
318 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
09f40aed | 319 | !test_bit(__IXGBE_REMOVING, &adapter->state) && |
7086400d | 320 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) |
780484d8 | 321 | queue_work(ixgbe_wq, &adapter->service_task); |
7086400d AD |
322 | } |
323 | ||
2a1a091c MR |
324 | static void ixgbe_remove_adapter(struct ixgbe_hw *hw) |
325 | { | |
326 | struct ixgbe_adapter *adapter = hw->back; | |
327 | ||
328 | if (!hw->hw_addr) | |
329 | return; | |
330 | hw->hw_addr = NULL; | |
331 | e_dev_err("Adapter removed\n"); | |
58cf663f MR |
332 | if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) |
333 | ixgbe_service_event_schedule(adapter); | |
2a1a091c MR |
334 | } |
335 | ||
f8e2472f | 336 | static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg) |
2a1a091c MR |
337 | { |
338 | u32 value; | |
339 | ||
340 | /* The following check not only optimizes a bit by not | |
341 | * performing a read on the status register when the | |
342 | * register just read was a status register read that | |
343 | * returned IXGBE_FAILED_READ_REG. It also blocks any | |
344 | * potential recursion. | |
345 | */ | |
346 | if (reg == IXGBE_STATUS) { | |
347 | ixgbe_remove_adapter(hw); | |
348 | return; | |
349 | } | |
350 | value = ixgbe_read_reg(hw, IXGBE_STATUS); | |
351 | if (value == IXGBE_FAILED_READ_REG) | |
352 | ixgbe_remove_adapter(hw); | |
353 | } | |
354 | ||
f8e2472f MR |
355 | /** |
356 | * ixgbe_read_reg - Read from device register | |
357 | * @hw: hw specific details | |
358 | * @reg: offset of register to read | |
359 | * | |
360 | * Returns : value read or IXGBE_FAILED_READ_REG if removed | |
361 | * | |
362 | * This function is used to read device registers. It checks for device | |
363 | * removal by confirming any read that returns all ones by checking the | |
364 | * status register value for all ones. This function avoids reading from | |
365 | * the hardware if a removal was previously detected in which case it | |
366 | * returns IXGBE_FAILED_READ_REG (all ones). | |
367 | */ | |
368 | u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg) | |
369 | { | |
370 | u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr); | |
371 | u32 value; | |
372 | ||
373 | if (ixgbe_removed(reg_addr)) | |
374 | return IXGBE_FAILED_READ_REG; | |
2f2219be MR |
375 | if (unlikely(hw->phy.nw_mng_if_sel & |
376 | IXGBE_NW_MNG_IF_SEL_ENABLE_10_100M)) { | |
377 | struct ixgbe_adapter *adapter; | |
378 | int i; | |
379 | ||
380 | for (i = 0; i < 200; ++i) { | |
381 | value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY); | |
382 | if (likely(!value)) | |
383 | goto writes_completed; | |
384 | if (value == IXGBE_FAILED_READ_REG) { | |
385 | ixgbe_remove_adapter(hw); | |
386 | return IXGBE_FAILED_READ_REG; | |
387 | } | |
388 | udelay(5); | |
389 | } | |
390 | ||
391 | adapter = hw->back; | |
392 | e_warn(hw, "register writes incomplete %08x\n", value); | |
393 | } | |
394 | ||
395 | writes_completed: | |
f8e2472f MR |
396 | value = readl(reg_addr + reg); |
397 | if (unlikely(value == IXGBE_FAILED_READ_REG)) | |
398 | ixgbe_check_remove(hw, reg); | |
399 | return value; | |
400 | } | |
401 | ||
14438464 MR |
402 | static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev) |
403 | { | |
404 | u16 value; | |
405 | ||
406 | pci_read_config_word(pdev, PCI_VENDOR_ID, &value); | |
407 | if (value == IXGBE_FAILED_READ_CFG_WORD) { | |
408 | ixgbe_remove_adapter(hw); | |
409 | return true; | |
410 | } | |
411 | return false; | |
412 | } | |
413 | ||
414 | u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg) | |
415 | { | |
416 | struct ixgbe_adapter *adapter = hw->back; | |
417 | u16 value; | |
418 | ||
419 | if (ixgbe_removed(hw->hw_addr)) | |
420 | return IXGBE_FAILED_READ_CFG_WORD; | |
421 | pci_read_config_word(adapter->pdev, reg, &value); | |
422 | if (value == IXGBE_FAILED_READ_CFG_WORD && | |
423 | ixgbe_check_cfg_remove(hw, adapter->pdev)) | |
424 | return IXGBE_FAILED_READ_CFG_WORD; | |
425 | return value; | |
426 | } | |
427 | ||
428 | #ifdef CONFIG_PCI_IOV | |
429 | static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg) | |
430 | { | |
431 | struct ixgbe_adapter *adapter = hw->back; | |
432 | u32 value; | |
433 | ||
434 | if (ixgbe_removed(hw->hw_addr)) | |
435 | return IXGBE_FAILED_READ_CFG_DWORD; | |
436 | pci_read_config_dword(adapter->pdev, reg, &value); | |
437 | if (value == IXGBE_FAILED_READ_CFG_DWORD && | |
438 | ixgbe_check_cfg_remove(hw, adapter->pdev)) | |
439 | return IXGBE_FAILED_READ_CFG_DWORD; | |
440 | return value; | |
441 | } | |
442 | #endif /* CONFIG_PCI_IOV */ | |
443 | ||
ed19231c JK |
444 | void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value) |
445 | { | |
446 | struct ixgbe_adapter *adapter = hw->back; | |
447 | ||
448 | if (ixgbe_removed(hw->hw_addr)) | |
449 | return; | |
450 | pci_write_config_word(adapter->pdev, reg, value); | |
451 | } | |
452 | ||
7086400d AD |
453 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) |
454 | { | |
455 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
456 | ||
52f33af8 | 457 | /* flush memory to make sure state is correct before next watchdog */ |
4e857c58 | 458 | smp_mb__before_atomic(); |
7086400d AD |
459 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); |
460 | } | |
461 | ||
dcd79aeb TI |
462 | struct ixgbe_reg_info { |
463 | u32 ofs; | |
464 | char *name; | |
465 | }; | |
466 | ||
467 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
468 | ||
469 | /* General Registers */ | |
470 | {IXGBE_CTRL, "CTRL"}, | |
471 | {IXGBE_STATUS, "STATUS"}, | |
472 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
473 | ||
474 | /* Interrupt Registers */ | |
475 | {IXGBE_EICR, "EICR"}, | |
476 | ||
477 | /* RX Registers */ | |
478 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
479 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
480 | {IXGBE_RDLEN(0), "RDLEN"}, | |
481 | {IXGBE_RDH(0), "RDH"}, | |
482 | {IXGBE_RDT(0), "RDT"}, | |
483 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
484 | {IXGBE_RDBAL(0), "RDBAL"}, | |
485 | {IXGBE_RDBAH(0), "RDBAH"}, | |
486 | ||
487 | /* TX Registers */ | |
488 | {IXGBE_TDBAL(0), "TDBAL"}, | |
489 | {IXGBE_TDBAH(0), "TDBAH"}, | |
490 | {IXGBE_TDLEN(0), "TDLEN"}, | |
491 | {IXGBE_TDH(0), "TDH"}, | |
492 | {IXGBE_TDT(0), "TDT"}, | |
493 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
494 | ||
495 | /* List Terminator */ | |
ca8dfe25 | 496 | { .name = NULL } |
dcd79aeb TI |
497 | }; |
498 | ||
499 | ||
500 | /* | |
501 | * ixgbe_regdump - register printout routine | |
502 | */ | |
503 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
504 | { | |
505 | int i = 0, j = 0; | |
506 | char rname[16]; | |
507 | u32 regs[64]; | |
508 | ||
509 | switch (reginfo->ofs) { | |
510 | case IXGBE_SRRCTL(0): | |
511 | for (i = 0; i < 64; i++) | |
512 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
513 | break; | |
514 | case IXGBE_DCA_RXCTRL(0): | |
515 | for (i = 0; i < 64; i++) | |
516 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
517 | break; | |
518 | case IXGBE_RDLEN(0): | |
519 | for (i = 0; i < 64; i++) | |
520 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
521 | break; | |
522 | case IXGBE_RDH(0): | |
523 | for (i = 0; i < 64; i++) | |
524 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
525 | break; | |
526 | case IXGBE_RDT(0): | |
527 | for (i = 0; i < 64; i++) | |
528 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
529 | break; | |
530 | case IXGBE_RXDCTL(0): | |
531 | for (i = 0; i < 64; i++) | |
532 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
533 | break; | |
534 | case IXGBE_RDBAL(0): | |
535 | for (i = 0; i < 64; i++) | |
536 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
537 | break; | |
538 | case IXGBE_RDBAH(0): | |
539 | for (i = 0; i < 64; i++) | |
540 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
541 | break; | |
542 | case IXGBE_TDBAL(0): | |
543 | for (i = 0; i < 64; i++) | |
544 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
545 | break; | |
546 | case IXGBE_TDBAH(0): | |
547 | for (i = 0; i < 64; i++) | |
548 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
549 | break; | |
550 | case IXGBE_TDLEN(0): | |
551 | for (i = 0; i < 64; i++) | |
552 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
553 | break; | |
554 | case IXGBE_TDH(0): | |
555 | for (i = 0; i < 64; i++) | |
556 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
557 | break; | |
558 | case IXGBE_TDT(0): | |
559 | for (i = 0; i < 64; i++) | |
560 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
561 | break; | |
562 | case IXGBE_TXDCTL(0): | |
563 | for (i = 0; i < 64; i++) | |
564 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
565 | break; | |
566 | default: | |
c7689578 | 567 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
568 | IXGBE_READ_REG(hw, reginfo->ofs)); |
569 | return; | |
570 | } | |
571 | ||
572 | for (i = 0; i < 8; i++) { | |
573 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 574 | pr_err("%-15s", rname); |
dcd79aeb | 575 | for (j = 0; j < 8; j++) |
c7689578 JP |
576 | pr_cont(" %08x", regs[i*8+j]); |
577 | pr_cont("\n"); | |
dcd79aeb TI |
578 | } |
579 | ||
580 | } | |
581 | ||
582 | /* | |
583 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
584 | */ | |
585 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
586 | { | |
587 | struct net_device *netdev = adapter->netdev; | |
588 | struct ixgbe_hw *hw = &adapter->hw; | |
589 | struct ixgbe_reg_info *reginfo; | |
590 | int n = 0; | |
591 | struct ixgbe_ring *tx_ring; | |
729739b7 | 592 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
593 | union ixgbe_adv_tx_desc *tx_desc; |
594 | struct my_u0 { u64 a; u64 b; } *u0; | |
595 | struct ixgbe_ring *rx_ring; | |
596 | union ixgbe_adv_rx_desc *rx_desc; | |
597 | struct ixgbe_rx_buffer *rx_buffer_info; | |
598 | u32 staterr; | |
599 | int i = 0; | |
600 | ||
601 | if (!netif_msg_hw(adapter)) | |
602 | return; | |
603 | ||
604 | /* Print netdevice Info */ | |
605 | if (netdev) { | |
606 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 607 | pr_info("Device Name state " |
dcd79aeb | 608 | "trans_start last_rx\n"); |
c7689578 JP |
609 | pr_info("%-15s %016lX %016lX %016lX\n", |
610 | netdev->name, | |
611 | netdev->state, | |
4d0e9657 | 612 | dev_trans_start(netdev), |
c7689578 | 613 | netdev->last_rx); |
dcd79aeb TI |
614 | } |
615 | ||
616 | /* Print Registers */ | |
617 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 618 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
619 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
620 | reginfo->name; reginfo++) { | |
621 | ixgbe_regdump(hw, reginfo); | |
622 | } | |
623 | ||
624 | /* Print TX Ring Summary */ | |
625 | if (!netdev || !netif_running(netdev)) | |
e90dd264 | 626 | return; |
dcd79aeb TI |
627 | |
628 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
8ad88e37 JH |
629 | pr_info(" %s %s %s %s\n", |
630 | "Queue [NTU] [NTC] [bi(ntc)->dma ]", | |
631 | "leng", "ntw", "timestamp"); | |
dcd79aeb TI |
632 | for (n = 0; n < adapter->num_tx_queues; n++) { |
633 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 634 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
8ad88e37 | 635 | pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n", |
dcd79aeb | 636 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
637 | (u64)dma_unmap_addr(tx_buffer, dma), |
638 | dma_unmap_len(tx_buffer, len), | |
639 | tx_buffer->next_to_watch, | |
640 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
641 | } |
642 | ||
643 | /* Print TX Rings */ | |
644 | if (!netif_msg_tx_done(adapter)) | |
645 | goto rx_ring_summary; | |
646 | ||
647 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
648 | ||
649 | /* Transmit Descriptor Formats | |
650 | * | |
39ac868a | 651 | * 82598 Advanced Transmit Descriptor |
dcd79aeb TI |
652 | * +--------------------------------------------------------------+ |
653 | * 0 | Buffer Address [63:0] | | |
654 | * +--------------------------------------------------------------+ | |
39ac868a | 655 | * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | |
dcd79aeb TI |
656 | * +--------------------------------------------------------------+ |
657 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
39ac868a JH |
658 | * |
659 | * 82598 Advanced Transmit Descriptor (Write-Back Format) | |
660 | * +--------------------------------------------------------------+ | |
661 | * 0 | RSV [63:0] | | |
662 | * +--------------------------------------------------------------+ | |
663 | * 8 | RSV | STA | NXTSEQ | | |
664 | * +--------------------------------------------------------------+ | |
665 | * 63 36 35 32 31 0 | |
666 | * | |
667 | * 82599+ Advanced Transmit Descriptor | |
668 | * +--------------------------------------------------------------+ | |
669 | * 0 | Buffer Address [63:0] | | |
670 | * +--------------------------------------------------------------+ | |
671 | * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN | | |
672 | * +--------------------------------------------------------------+ | |
673 | * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0 | |
674 | * | |
675 | * 82599+ Advanced Transmit Descriptor (Write-Back Format) | |
676 | * +--------------------------------------------------------------+ | |
677 | * 0 | RSV [63:0] | | |
678 | * +--------------------------------------------------------------+ | |
679 | * 8 | RSV | STA | RSV | | |
680 | * +--------------------------------------------------------------+ | |
681 | * 63 36 35 32 31 0 | |
dcd79aeb TI |
682 | */ |
683 | ||
684 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
685 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
686 | pr_info("------------------------------------\n"); |
687 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
688 | pr_info("------------------------------------\n"); | |
8ad88e37 JH |
689 | pr_info("%s%s %s %s %s %s\n", |
690 | "T [desc] [address 63:0 ] ", | |
691 | "[PlPOIdStDDt Ln] [bi->dma ] ", | |
692 | "leng", "ntw", "timestamp", "bi->skb"); | |
dcd79aeb TI |
693 | |
694 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 695 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 696 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 697 | u0 = (struct my_u0 *)tx_desc; |
8ad88e37 JH |
698 | if (dma_unmap_len(tx_buffer, len) > 0) { |
699 | pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p", | |
700 | i, | |
701 | le64_to_cpu(u0->a), | |
702 | le64_to_cpu(u0->b), | |
703 | (u64)dma_unmap_addr(tx_buffer, dma), | |
729739b7 | 704 | dma_unmap_len(tx_buffer, len), |
8ad88e37 JH |
705 | tx_buffer->next_to_watch, |
706 | (u64)tx_buffer->time_stamp, | |
707 | tx_buffer->skb); | |
708 | if (i == tx_ring->next_to_use && | |
709 | i == tx_ring->next_to_clean) | |
710 | pr_cont(" NTC/U\n"); | |
711 | else if (i == tx_ring->next_to_use) | |
712 | pr_cont(" NTU\n"); | |
713 | else if (i == tx_ring->next_to_clean) | |
714 | pr_cont(" NTC\n"); | |
715 | else | |
716 | pr_cont("\n"); | |
717 | ||
718 | if (netif_msg_pktdata(adapter) && | |
719 | tx_buffer->skb) | |
720 | print_hex_dump(KERN_INFO, "", | |
721 | DUMP_PREFIX_ADDRESS, 16, 1, | |
722 | tx_buffer->skb->data, | |
723 | dma_unmap_len(tx_buffer, len), | |
724 | true); | |
725 | } | |
dcd79aeb TI |
726 | } |
727 | } | |
728 | ||
729 | /* Print RX Rings Summary */ | |
730 | rx_ring_summary: | |
731 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 732 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
733 | for (n = 0; n < adapter->num_rx_queues; n++) { |
734 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
735 | pr_info("%5d %5X %5X\n", |
736 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
737 | } |
738 | ||
739 | /* Print RX Rings */ | |
740 | if (!netif_msg_rx_status(adapter)) | |
e90dd264 | 741 | return; |
dcd79aeb TI |
742 | |
743 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
744 | ||
39ac868a JH |
745 | /* Receive Descriptor Formats |
746 | * | |
747 | * 82598 Advanced Receive Descriptor (Read) Format | |
dcd79aeb TI |
748 | * 63 1 0 |
749 | * +-----------------------------------------------------+ | |
750 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
751 | * +----------------------------------------------+------+ | |
752 | * 8 | Header Buffer Address [63:1] | DD | | |
753 | * +-----------------------------------------------------+ | |
754 | * | |
755 | * | |
39ac868a | 756 | * 82598 Advanced Receive Descriptor (Write-Back) Format |
dcd79aeb TI |
757 | * |
758 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
759 | * +------------------------------------------------------+ | |
39ac868a JH |
760 | * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS | |
761 | * | Packet | IP | | | | Type | Type | | |
762 | * | Checksum | Ident | | | | | | | |
dcd79aeb TI |
763 | * +------------------------------------------------------+ |
764 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
765 | * +------------------------------------------------------+ | |
766 | * 63 48 47 32 31 20 19 0 | |
39ac868a JH |
767 | * |
768 | * 82599+ Advanced Receive Descriptor (Read) Format | |
769 | * 63 1 0 | |
770 | * +-----------------------------------------------------+ | |
771 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
772 | * +----------------------------------------------+------+ | |
773 | * 8 | Header Buffer Address [63:1] | DD | | |
774 | * +-----------------------------------------------------+ | |
775 | * | |
776 | * | |
777 | * 82599+ Advanced Receive Descriptor (Write-Back) Format | |
778 | * | |
779 | * 63 48 47 32 31 30 21 20 17 16 4 3 0 | |
780 | * +------------------------------------------------------+ | |
781 | * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS | | |
782 | * |/ RTT / PCoE_PARAM | | | CNT | Type | Type | | |
783 | * |/ Flow Dir Flt ID | | | | | | | |
784 | * +------------------------------------------------------+ | |
785 | * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP | | |
786 | * +------------------------------------------------------+ | |
787 | * 63 48 47 32 31 20 19 0 | |
dcd79aeb | 788 | */ |
39ac868a | 789 | |
dcd79aeb TI |
790 | for (n = 0; n < adapter->num_rx_queues; n++) { |
791 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
792 | pr_info("------------------------------------\n"); |
793 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
794 | pr_info("------------------------------------\n"); | |
8ad88e37 JH |
795 | pr_info("%s%s%s", |
796 | "R [desc] [ PktBuf A0] ", | |
797 | "[ HeadBuf DD] [bi->dma ] [bi->skb ] ", | |
dcd79aeb | 798 | "<-- Adv Rx Read format\n"); |
8ad88e37 JH |
799 | pr_info("%s%s%s", |
800 | "RWB[desc] [PcsmIpSHl PtRs] ", | |
801 | "[vl er S cks ln] ---------------- [bi->skb ] ", | |
dcd79aeb TI |
802 | "<-- Adv Rx Write-Back format\n"); |
803 | ||
804 | for (i = 0; i < rx_ring->count; i++) { | |
805 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 806 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
807 | u0 = (struct my_u0 *)rx_desc; |
808 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
809 | if (staterr & IXGBE_RXD_STAT_DD) { | |
810 | /* Descriptor Done */ | |
c7689578 | 811 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
812 | "%016llX ---------------- %p", i, |
813 | le64_to_cpu(u0->a), | |
814 | le64_to_cpu(u0->b), | |
815 | rx_buffer_info->skb); | |
816 | } else { | |
c7689578 | 817 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
818 | "%016llX %016llX %p", i, |
819 | le64_to_cpu(u0->a), | |
820 | le64_to_cpu(u0->b), | |
821 | (u64)rx_buffer_info->dma, | |
822 | rx_buffer_info->skb); | |
823 | ||
9c50c035 ET |
824 | if (netif_msg_pktdata(adapter) && |
825 | rx_buffer_info->dma) { | |
dcd79aeb TI |
826 | print_hex_dump(KERN_INFO, "", |
827 | DUMP_PREFIX_ADDRESS, 16, 1, | |
9c50c035 ET |
828 | page_address(rx_buffer_info->page) + |
829 | rx_buffer_info->page_offset, | |
f800326d | 830 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
831 | } |
832 | } | |
833 | ||
834 | if (i == rx_ring->next_to_use) | |
c7689578 | 835 | pr_cont(" NTU\n"); |
dcd79aeb | 836 | else if (i == rx_ring->next_to_clean) |
c7689578 | 837 | pr_cont(" NTC\n"); |
dcd79aeb | 838 | else |
c7689578 | 839 | pr_cont("\n"); |
dcd79aeb TI |
840 | |
841 | } | |
842 | } | |
dcd79aeb TI |
843 | } |
844 | ||
5eba3699 AV |
845 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
846 | { | |
847 | u32 ctrl_ext; | |
848 | ||
849 | /* Let firmware take over control of h/w */ | |
850 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
851 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 852 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
853 | } |
854 | ||
855 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
856 | { | |
857 | u32 ctrl_ext; | |
858 | ||
859 | /* Let firmware know the driver has taken over */ | |
860 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
861 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 862 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 863 | } |
9a799d71 | 864 | |
49ce9c2c | 865 | /** |
e8e26350 PW |
866 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors |
867 | * @adapter: pointer to adapter struct | |
868 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
869 | * @queue: queue to map the corresponding interrupt to | |
870 | * @msix_vector: the vector to map to the corresponding queue | |
871 | * | |
872 | */ | |
873 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 874 | u8 queue, u8 msix_vector) |
9a799d71 AK |
875 | { |
876 | u32 ivar, index; | |
e8e26350 PW |
877 | struct ixgbe_hw *hw = &adapter->hw; |
878 | switch (hw->mac.type) { | |
879 | case ixgbe_mac_82598EB: | |
880 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
881 | if (direction == -1) | |
882 | direction = 0; | |
883 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
884 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
885 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
886 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
887 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
888 | break; | |
889 | case ixgbe_mac_82599EB: | |
b93a2226 | 890 | case ixgbe_mac_X540: |
9a75a1ac DS |
891 | case ixgbe_mac_X550: |
892 | case ixgbe_mac_X550EM_x: | |
49425dfc | 893 | case ixgbe_mac_x550em_a: |
e8e26350 PW |
894 | if (direction == -1) { |
895 | /* other causes */ | |
896 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
897 | index = ((queue & 1) * 8); | |
898 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
899 | ivar &= ~(0xFF << index); | |
900 | ivar |= (msix_vector << index); | |
901 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
902 | break; | |
903 | } else { | |
904 | /* tx or rx causes */ | |
905 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
906 | index = ((16 * (queue & 1)) + (8 * direction)); | |
907 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
908 | ivar &= ~(0xFF << index); | |
909 | ivar |= (msix_vector << index); | |
910 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
911 | break; | |
912 | } | |
913 | default: | |
914 | break; | |
915 | } | |
9a799d71 AK |
916 | } |
917 | ||
fe49f04a | 918 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 919 | u64 qmask) |
fe49f04a AD |
920 | { |
921 | u32 mask; | |
922 | ||
bd508178 AD |
923 | switch (adapter->hw.mac.type) { |
924 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
925 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
926 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
927 | break; |
928 | case ixgbe_mac_82599EB: | |
b93a2226 | 929 | case ixgbe_mac_X540: |
9a75a1ac DS |
930 | case ixgbe_mac_X550: |
931 | case ixgbe_mac_X550EM_x: | |
49425dfc | 932 | case ixgbe_mac_x550em_a: |
fe49f04a AD |
933 | mask = (qmask & 0xFFFFFFFF); |
934 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
935 | mask = (qmask >> 32); | |
936 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
937 | break; |
938 | default: | |
939 | break; | |
fe49f04a AD |
940 | } |
941 | } | |
942 | ||
729739b7 AD |
943 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
944 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 945 | { |
729739b7 AD |
946 | if (tx_buffer->skb) { |
947 | dev_kfree_skb_any(tx_buffer->skb); | |
948 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 949 | dma_unmap_single(ring->dev, |
729739b7 AD |
950 | dma_unmap_addr(tx_buffer, dma), |
951 | dma_unmap_len(tx_buffer, len), | |
952 | DMA_TO_DEVICE); | |
953 | } else if (dma_unmap_len(tx_buffer, len)) { | |
954 | dma_unmap_page(ring->dev, | |
955 | dma_unmap_addr(tx_buffer, dma), | |
956 | dma_unmap_len(tx_buffer, len), | |
957 | DMA_TO_DEVICE); | |
e5a43549 | 958 | } |
729739b7 AD |
959 | tx_buffer->next_to_watch = NULL; |
960 | tx_buffer->skb = NULL; | |
961 | dma_unmap_len_set(tx_buffer, len, 0); | |
962 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
963 | } |
964 | ||
943561d3 | 965 | static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) |
c84d324c JF |
966 | { |
967 | struct ixgbe_hw *hw = &adapter->hw; | |
968 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
c84d324c | 969 | int i; |
943561d3 | 970 | u32 data; |
c84d324c | 971 | |
943561d3 AD |
972 | if ((hw->fc.current_mode != ixgbe_fc_full) && |
973 | (hw->fc.current_mode != ixgbe_fc_rx_pause)) | |
974 | return; | |
c84d324c | 975 | |
943561d3 AD |
976 | switch (hw->mac.type) { |
977 | case ixgbe_mac_82598EB: | |
978 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
979 | break; | |
980 | default: | |
981 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
982 | } | |
983 | hwstats->lxoffrxc += data; | |
c84d324c | 984 | |
943561d3 AD |
985 | /* refill credits (no tx hang) if we received xoff */ |
986 | if (!data) | |
c84d324c | 987 | return; |
943561d3 AD |
988 | |
989 | for (i = 0; i < adapter->num_tx_queues; i++) | |
990 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
991 | &adapter->tx_ring[i]->state); | |
992 | } | |
993 | ||
994 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
995 | { | |
996 | struct ixgbe_hw *hw = &adapter->hw; | |
997 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
998 | u32 xoff[8] = {0}; | |
2afaa00d | 999 | u8 tc; |
943561d3 AD |
1000 | int i; |
1001 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
1002 | ||
1003 | if (adapter->ixgbe_ieee_pfc) | |
1004 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
1005 | ||
1006 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { | |
1007 | ixgbe_update_xoff_rx_lfc(adapter); | |
c84d324c | 1008 | return; |
943561d3 | 1009 | } |
c84d324c JF |
1010 | |
1011 | /* update stats for each tc, only valid with PFC enabled */ | |
1012 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
2afaa00d PN |
1013 | u32 pxoffrxc; |
1014 | ||
c84d324c JF |
1015 | switch (hw->mac.type) { |
1016 | case ixgbe_mac_82598EB: | |
2afaa00d | 1017 | pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); |
bd508178 | 1018 | break; |
c84d324c | 1019 | default: |
2afaa00d | 1020 | pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); |
26f23d82 | 1021 | } |
2afaa00d PN |
1022 | hwstats->pxoffrxc[i] += pxoffrxc; |
1023 | /* Get the TC for given UP */ | |
1024 | tc = netdev_get_prio_tc_map(adapter->netdev, i); | |
1025 | xoff[tc] += pxoffrxc; | |
c84d324c JF |
1026 | } |
1027 | ||
1028 | /* disarm tx queues that have received xoff frames */ | |
1029 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
1030 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
c84d324c | 1031 | |
2afaa00d | 1032 | tc = tx_ring->dcb_tc; |
c84d324c JF |
1033 | if (xoff[tc]) |
1034 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 1035 | } |
26f23d82 YZ |
1036 | } |
1037 | ||
c84d324c | 1038 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 1039 | { |
7d7ce682 | 1040 | return ring->stats.packets; |
c84d324c JF |
1041 | } |
1042 | ||
1043 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
1044 | { | |
2a47fa45 JF |
1045 | struct ixgbe_adapter *adapter; |
1046 | struct ixgbe_hw *hw; | |
1047 | u32 head, tail; | |
1048 | ||
1049 | if (ring->l2_accel_priv) | |
1050 | adapter = ring->l2_accel_priv->real_adapter; | |
1051 | else | |
1052 | adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 1053 | |
2a47fa45 JF |
1054 | hw = &adapter->hw; |
1055 | head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); | |
1056 | tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
c84d324c JF |
1057 | |
1058 | if (head != tail) | |
1059 | return (head < tail) ? | |
1060 | tail - head : (tail + ring->count - head); | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
1066 | { | |
1067 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
1068 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
1069 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
c84d324c | 1070 | |
7d637bcc | 1071 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
1072 | |
1073 | /* | |
1074 | * Check for a hung queue, but be thorough. This verifies | |
1075 | * that a transmit has been completed since the previous | |
1076 | * check AND there is at least one packet pending. The | |
1077 | * ARMED bit is set to indicate a potential hang. The | |
1078 | * bit is cleared if a pause frame is received to remove | |
1079 | * false hang detection due to PFC or 802.3x frames. By | |
1080 | * requiring this to fail twice we avoid races with | |
1081 | * pfc clearing the ARMED bit and conditions where we | |
1082 | * run the check_tx_hang logic with a transmit completion | |
1083 | * pending but without time to complete it yet. | |
1084 | */ | |
e90dd264 | 1085 | if (tx_done_old == tx_done && tx_pending) |
c84d324c | 1086 | /* make sure it is true for two checks in a row */ |
e90dd264 MR |
1087 | return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, |
1088 | &tx_ring->state); | |
1089 | /* update completed stats and continue */ | |
1090 | tx_ring->tx_stats.tx_done_old = tx_done; | |
1091 | /* reset the countdown */ | |
1092 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 | 1093 | |
e90dd264 | 1094 | return false; |
9a799d71 AK |
1095 | } |
1096 | ||
c83c6cbd AD |
1097 | /** |
1098 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
1099 | * @adapter: driver private struct | |
1100 | **/ | |
1101 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
1102 | { | |
1103 | ||
1104 | /* Do the reset outside of interrupt context */ | |
1105 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1106 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
12ff3f3b | 1107 | e_warn(drv, "initiating reset due to tx timeout\n"); |
c83c6cbd AD |
1108 | ixgbe_service_event_schedule(adapter); |
1109 | } | |
1110 | } | |
e01c31a5 | 1111 | |
c04f90e5 RP |
1112 | /** |
1113 | * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate | |
1114 | **/ | |
1115 | static int ixgbe_tx_maxrate(struct net_device *netdev, | |
1116 | int queue_index, u32 maxrate) | |
1117 | { | |
1118 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
1119 | struct ixgbe_hw *hw = &adapter->hw; | |
1120 | u32 bcnrc_val = ixgbe_link_mbps(adapter); | |
1121 | ||
1122 | if (!maxrate) | |
1123 | return 0; | |
1124 | ||
1125 | /* Calculate the rate factor values to set */ | |
1126 | bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT; | |
1127 | bcnrc_val /= maxrate; | |
1128 | ||
1129 | /* clear everything but the rate factor */ | |
1130 | bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK | | |
1131 | IXGBE_RTTBCNRC_RF_DEC_MASK; | |
1132 | ||
1133 | /* enable the rate scheduler */ | |
1134 | bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA; | |
1135 | ||
1136 | IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index); | |
1137 | IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val); | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
9a799d71 AK |
1142 | /** |
1143 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 1144 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 1145 | * @tx_ring: tx ring to clean |
8220bbc1 | 1146 | * @napi_budget: Used to determine if we are in netpoll |
9a799d71 | 1147 | **/ |
fe49f04a | 1148 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
a3a8749d | 1149 | struct ixgbe_ring *tx_ring, int napi_budget) |
9a799d71 | 1150 | { |
fe49f04a | 1151 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
1152 | struct ixgbe_tx_buffer *tx_buffer; |
1153 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 1154 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 1155 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
1156 | unsigned int i = tx_ring->next_to_clean; |
1157 | ||
1158 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
1159 | return true; | |
9a799d71 | 1160 | |
d3d00239 | 1161 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 1162 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 1163 | i -= tx_ring->count; |
12207e49 | 1164 | |
729739b7 | 1165 | do { |
d3d00239 AD |
1166 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
1167 | ||
1168 | /* if next_to_watch is not set then there is no work pending */ | |
1169 | if (!eop_desc) | |
1170 | break; | |
1171 | ||
7f83a9e6 | 1172 | /* prevent any other reads prior to eop_desc */ |
7e63bf49 | 1173 | read_barrier_depends(); |
7f83a9e6 | 1174 | |
d3d00239 AD |
1175 | /* if DD is not set pending work has not been completed */ |
1176 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
1177 | break; | |
8ad494b0 | 1178 | |
d3d00239 AD |
1179 | /* clear next_to_watch to prevent false hangs */ |
1180 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 1181 | |
091a6246 AD |
1182 | /* update the statistics for this packet */ |
1183 | total_bytes += tx_buffer->bytecount; | |
1184 | total_packets += tx_buffer->gso_segs; | |
1185 | ||
fd0db0ed | 1186 | /* free the skb */ |
a3a8749d | 1187 | napi_consume_skb(tx_buffer->skb, napi_budget); |
fd0db0ed | 1188 | |
729739b7 AD |
1189 | /* unmap skb header data */ |
1190 | dma_unmap_single(tx_ring->dev, | |
1191 | dma_unmap_addr(tx_buffer, dma), | |
1192 | dma_unmap_len(tx_buffer, len), | |
1193 | DMA_TO_DEVICE); | |
1194 | ||
fd0db0ed AD |
1195 | /* clear tx_buffer data */ |
1196 | tx_buffer->skb = NULL; | |
729739b7 | 1197 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 1198 | |
729739b7 AD |
1199 | /* unmap remaining buffers */ |
1200 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
1201 | tx_buffer++; |
1202 | tx_desc++; | |
8ad494b0 | 1203 | i++; |
729739b7 AD |
1204 | if (unlikely(!i)) { |
1205 | i -= tx_ring->count; | |
d3d00239 | 1206 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 1207 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 1208 | } |
e01c31a5 | 1209 | |
729739b7 AD |
1210 | /* unmap any remaining paged data */ |
1211 | if (dma_unmap_len(tx_buffer, len)) { | |
1212 | dma_unmap_page(tx_ring->dev, | |
1213 | dma_unmap_addr(tx_buffer, dma), | |
1214 | dma_unmap_len(tx_buffer, len), | |
1215 | DMA_TO_DEVICE); | |
1216 | dma_unmap_len_set(tx_buffer, len, 0); | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | /* move us one more past the eop_desc for start of next pkt */ | |
1221 | tx_buffer++; | |
1222 | tx_desc++; | |
1223 | i++; | |
1224 | if (unlikely(!i)) { | |
1225 | i -= tx_ring->count; | |
1226 | tx_buffer = tx_ring->tx_buffer_info; | |
1227 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
1228 | } | |
1229 | ||
1230 | /* issue prefetch for next Tx descriptor */ | |
1231 | prefetch(tx_desc); | |
12207e49 | 1232 | |
729739b7 AD |
1233 | /* update budget accounting */ |
1234 | budget--; | |
1235 | } while (likely(budget)); | |
1236 | ||
1237 | i += tx_ring->count; | |
9a799d71 | 1238 | tx_ring->next_to_clean = i; |
d3d00239 | 1239 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 1240 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 1241 | tx_ring->stats.packets += total_packets; |
d3d00239 | 1242 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
1243 | q_vector->tx.total_bytes += total_bytes; |
1244 | q_vector->tx.total_packets += total_packets; | |
b953799e | 1245 | |
c84d324c JF |
1246 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
1247 | /* schedule immediate reset if we believe we hung */ | |
1248 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
1249 | e_err(drv, "Detected Tx Unit Hang\n" |
1250 | " Tx Queue <%d>\n" | |
1251 | " TDH, TDT <%x>, <%x>\n" | |
1252 | " next_to_use <%x>\n" | |
1253 | " next_to_clean <%x>\n" | |
1254 | "tx_buffer_info[next_to_clean]\n" | |
1255 | " time_stamp <%lx>\n" | |
1256 | " jiffies <%lx>\n", | |
1257 | tx_ring->queue_index, | |
1258 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
1259 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
1260 | tx_ring->next_to_use, i, |
1261 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
1262 | |
1263 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
1264 | ||
1265 | e_info(probe, | |
1266 | "tx hang %d detected on queue %d, resetting adapter\n", | |
1267 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
1268 | ||
b953799e | 1269 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 1270 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
1271 | |
1272 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 1273 | return true; |
b953799e | 1274 | } |
9a799d71 | 1275 | |
b2d96e0a AD |
1276 | netdev_tx_completed_queue(txring_txq(tx_ring), |
1277 | total_packets, total_bytes); | |
1278 | ||
e092be60 | 1279 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 1280 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 1281 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
1282 | /* Make sure that anybody stopping the queue after this |
1283 | * sees the new next_to_clean. | |
1284 | */ | |
1285 | smp_mb(); | |
729739b7 AD |
1286 | if (__netif_subqueue_stopped(tx_ring->netdev, |
1287 | tx_ring->queue_index) | |
1288 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1289 | netif_wake_subqueue(tx_ring->netdev, | |
1290 | tx_ring->queue_index); | |
5b7da515 | 1291 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 1292 | } |
e092be60 | 1293 | } |
9a799d71 | 1294 | |
59224555 | 1295 | return !!budget; |
9a799d71 AK |
1296 | } |
1297 | ||
5dd2d332 | 1298 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
1299 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
1300 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 1301 | int cpu) |
bd0362dd | 1302 | { |
33cf09c9 | 1303 | struct ixgbe_hw *hw = &adapter->hw; |
9de7605e | 1304 | u32 txctrl = 0; |
bdda1a61 | 1305 | u16 reg_offset; |
33cf09c9 | 1306 | |
9de7605e MR |
1307 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1308 | txctrl = dca3_get_tag(tx_ring->dev, cpu); | |
1309 | ||
33cf09c9 AD |
1310 | switch (hw->mac.type) { |
1311 | case ixgbe_mac_82598EB: | |
bdda1a61 | 1312 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
1313 | break; |
1314 | case ixgbe_mac_82599EB: | |
b93a2226 | 1315 | case ixgbe_mac_X540: |
bdda1a61 AD |
1316 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
1317 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
1318 | break; |
1319 | default: | |
bdda1a61 AD |
1320 | /* for unknown hardware do not write register */ |
1321 | return; | |
bd0362dd | 1322 | } |
bdda1a61 AD |
1323 | |
1324 | /* | |
1325 | * We can enable relaxed ordering for reads, but not writes when | |
1326 | * DCA is enabled. This is due to a known issue in some chipsets | |
1327 | * which will cause the DCA tag to be cleared. | |
1328 | */ | |
1329 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
1330 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
1331 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
1332 | ||
1333 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
1334 | } |
1335 | ||
bdda1a61 AD |
1336 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
1337 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 1338 | int cpu) |
bd0362dd | 1339 | { |
33cf09c9 | 1340 | struct ixgbe_hw *hw = &adapter->hw; |
9de7605e | 1341 | u32 rxctrl = 0; |
bdda1a61 AD |
1342 | u8 reg_idx = rx_ring->reg_idx; |
1343 | ||
9de7605e MR |
1344 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1345 | rxctrl = dca3_get_tag(rx_ring->dev, cpu); | |
33cf09c9 AD |
1346 | |
1347 | switch (hw->mac.type) { | |
33cf09c9 | 1348 | case ixgbe_mac_82599EB: |
b93a2226 | 1349 | case ixgbe_mac_X540: |
bdda1a61 | 1350 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
1351 | break; |
1352 | default: | |
1353 | break; | |
1354 | } | |
bdda1a61 AD |
1355 | |
1356 | /* | |
1357 | * We can enable relaxed ordering for reads, but not writes when | |
1358 | * DCA is enabled. This is due to a known issue in some chipsets | |
1359 | * which will cause the DCA tag to be cleared. | |
1360 | */ | |
1361 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
9de7605e | 1362 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | |
bdda1a61 AD |
1363 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
1364 | ||
1365 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
1366 | } |
1367 | ||
1368 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
1369 | { | |
1370 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 1371 | struct ixgbe_ring *ring; |
bd0362dd | 1372 | int cpu = get_cpu(); |
bd0362dd | 1373 | |
33cf09c9 AD |
1374 | if (q_vector->cpu == cpu) |
1375 | goto out_no_update; | |
1376 | ||
a557928e | 1377 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 1378 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 1379 | |
a557928e | 1380 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 1381 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
1382 | |
1383 | q_vector->cpu = cpu; | |
1384 | out_no_update: | |
bd0362dd JC |
1385 | put_cpu(); |
1386 | } | |
1387 | ||
1388 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
1389 | { | |
1390 | int i; | |
1391 | ||
e35ec126 | 1392 | /* always use CB2 mode, difference is masked in the CB driver */ |
9de7605e MR |
1393 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
1394 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, | |
1395 | IXGBE_DCA_CTRL_DCA_MODE_CB2); | |
1396 | else | |
1397 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, | |
1398 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
e35ec126 | 1399 | |
49c7ffbe | 1400 | for (i = 0; i < adapter->num_q_vectors; i++) { |
33cf09c9 AD |
1401 | adapter->q_vector[i]->cpu = -1; |
1402 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1403 | } |
1404 | } | |
1405 | ||
1406 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1407 | { | |
c60fbb00 | 1408 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1409 | unsigned long event = *(unsigned long *)data; |
1410 | ||
2a72c31e | 1411 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1412 | return 0; |
1413 | ||
bd0362dd JC |
1414 | switch (event) { |
1415 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1416 | /* if we're already enabled, don't do it again */ |
1417 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1418 | break; | |
652f093f | 1419 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1420 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
9de7605e MR |
1421 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
1422 | IXGBE_DCA_CTRL_DCA_MODE_CB2); | |
bd0362dd JC |
1423 | break; |
1424 | } | |
1425 | /* Fall Through since DCA is disabled. */ | |
1426 | case DCA_PROVIDER_REMOVE: | |
1427 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1428 | dca_remove_requester(dev); | |
1429 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
9de7605e MR |
1430 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
1431 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
bd0362dd JC |
1432 | } |
1433 | break; | |
1434 | } | |
1435 | ||
652f093f | 1436 | return 0; |
bd0362dd | 1437 | } |
67a74ee2 | 1438 | |
bdda1a61 | 1439 | #endif /* CONFIG_IXGBE_DCA */ |
7edda4b8 FD |
1440 | |
1441 | #define IXGBE_RSS_L4_TYPES_MASK \ | |
1442 | ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \ | |
1443 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \ | |
1444 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \ | |
1445 | (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP)) | |
1446 | ||
8a0da21b AD |
1447 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1448 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1449 | struct sk_buff *skb) |
1450 | { | |
7edda4b8 FD |
1451 | u16 rss_type; |
1452 | ||
1453 | if (!(ring->netdev->features & NETIF_F_RXHASH)) | |
1454 | return; | |
1455 | ||
1456 | rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) & | |
1457 | IXGBE_RXDADV_RSSTYPE_MASK; | |
1458 | ||
1459 | if (!rss_type) | |
1460 | return; | |
1461 | ||
1462 | skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), | |
1463 | (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ? | |
1464 | PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); | |
67a74ee2 ET |
1465 | } |
1466 | ||
f800326d | 1467 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1468 | /** |
1469 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
57efd44c | 1470 | * @ring: structure containing ring specific data |
ff886dfc AD |
1471 | * @rx_desc: advanced rx descriptor |
1472 | * | |
1473 | * Returns : true if it is FCoE pkt | |
1474 | */ | |
57efd44c | 1475 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, |
ff886dfc AD |
1476 | union ixgbe_adv_rx_desc *rx_desc) |
1477 | { | |
1478 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1479 | ||
57efd44c | 1480 | return test_bit(__IXGBE_RX_FCOE, &ring->state) && |
ff886dfc AD |
1481 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == |
1482 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1483 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1484 | } | |
1485 | ||
f800326d | 1486 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1487 | /** |
1488 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1489 | * @ring: structure containing ring specific data |
1490 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1491 | * @skb: skb currently being received and modified |
1492 | **/ | |
8a0da21b | 1493 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1494 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1495 | struct sk_buff *skb) |
9a799d71 | 1496 | { |
3f207800 DS |
1497 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
1498 | __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info; | |
1499 | bool encap_pkt = false; | |
1500 | ||
8a0da21b | 1501 | skb_checksum_none_assert(skb); |
9a799d71 | 1502 | |
712744be | 1503 | /* Rx csum disabled */ |
8a0da21b | 1504 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1505 | return; |
e59bd25d | 1506 | |
3f207800 DS |
1507 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) && |
1508 | (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) { | |
1509 | encap_pkt = true; | |
1510 | skb->encapsulation = 1; | |
3f207800 DS |
1511 | } |
1512 | ||
e59bd25d | 1513 | /* if IP and error */ |
f56e0cb1 AD |
1514 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1515 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1516 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1517 | return; |
1518 | } | |
e59bd25d | 1519 | |
f56e0cb1 | 1520 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1521 | return; |
1522 | ||
f56e0cb1 | 1523 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
8bae1b2b DS |
1524 | /* |
1525 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1526 | * checksum errors. | |
1527 | */ | |
8a0da21b AD |
1528 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1529 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1530 | return; |
1531 | ||
8a0da21b | 1532 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1533 | return; |
1534 | } | |
1535 | ||
9a799d71 | 1536 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1537 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
3f207800 DS |
1538 | if (encap_pkt) { |
1539 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS)) | |
1540 | return; | |
1541 | ||
1542 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) { | |
d469251b | 1543 | skb->ip_summed = CHECKSUM_NONE; |
3f207800 DS |
1544 | return; |
1545 | } | |
1546 | /* If we checked the outer header let the stack know */ | |
1547 | skb->csum_level = 1; | |
1548 | } | |
9a799d71 AK |
1549 | } |
1550 | ||
f990b79b AD |
1551 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1552 | struct ixgbe_rx_buffer *bi) | |
1553 | { | |
1554 | struct page *page = bi->page; | |
18cb652a | 1555 | dma_addr_t dma; |
f990b79b | 1556 | |
f800326d | 1557 | /* since we are recycling buffers we should seldom need to alloc */ |
18cb652a | 1558 | if (likely(page)) |
f990b79b AD |
1559 | return true; |
1560 | ||
f800326d | 1561 | /* alloc new page for storage */ |
18cb652a AD |
1562 | page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring)); |
1563 | if (unlikely(!page)) { | |
1564 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1565 | return false; | |
f990b79b AD |
1566 | } |
1567 | ||
f800326d AD |
1568 | /* map page for use */ |
1569 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1570 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1571 | ||
1572 | /* | |
1573 | * if mapping failed free memory back to system since | |
1574 | * there isn't much point in holding memory we can't use | |
1575 | */ | |
1576 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
dd411ec4 | 1577 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
f990b79b | 1578 | |
f990b79b AD |
1579 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1580 | return false; | |
1581 | } | |
1582 | ||
f800326d | 1583 | bi->dma = dma; |
18cb652a | 1584 | bi->page = page; |
afaa9459 | 1585 | bi->page_offset = 0; |
f800326d | 1586 | |
f990b79b AD |
1587 | return true; |
1588 | } | |
1589 | ||
9a799d71 | 1590 | /** |
f990b79b | 1591 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1592 | * @rx_ring: ring to place buffers on |
1593 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1594 | **/ |
fc77dc3c | 1595 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1596 | { |
9a799d71 | 1597 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1598 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1599 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1600 | |
f800326d AD |
1601 | /* nothing to do */ |
1602 | if (!cleaned_count) | |
fc77dc3c AD |
1603 | return; |
1604 | ||
e4f74028 | 1605 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1606 | bi = &rx_ring->rx_buffer_info[i]; |
1607 | i -= rx_ring->count; | |
9a799d71 | 1608 | |
f800326d AD |
1609 | do { |
1610 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1611 | break; |
d5f398ed | 1612 | |
f800326d AD |
1613 | /* |
1614 | * Refresh the desc even if buffer_addrs didn't change | |
1615 | * because each write-back erases this info. | |
1616 | */ | |
1617 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1618 | |
f990b79b AD |
1619 | rx_desc++; |
1620 | bi++; | |
9a799d71 | 1621 | i++; |
f990b79b | 1622 | if (unlikely(!i)) { |
e4f74028 | 1623 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1624 | bi = rx_ring->rx_buffer_info; |
1625 | i -= rx_ring->count; | |
1626 | } | |
1627 | ||
18cb652a AD |
1628 | /* clear the status bits for the next_to_use descriptor */ |
1629 | rx_desc->wb.upper.status_error = 0; | |
f800326d AD |
1630 | |
1631 | cleaned_count--; | |
1632 | } while (cleaned_count); | |
7c6e0a43 | 1633 | |
f990b79b AD |
1634 | i += rx_ring->count; |
1635 | ||
ad435ec6 AD |
1636 | if (rx_ring->next_to_use != i) { |
1637 | rx_ring->next_to_use = i; | |
1638 | ||
1639 | /* update next to alloc since we have filled the ring */ | |
1640 | rx_ring->next_to_alloc = i; | |
1641 | ||
1642 | /* Force memory writes to complete before letting h/w | |
1643 | * know there are new descriptors to fetch. (Only | |
1644 | * applicable for weak-ordered memory model archs, | |
1645 | * such as IA-64). | |
1646 | */ | |
1647 | wmb(); | |
1648 | writel(i, rx_ring->tail); | |
1649 | } | |
9a799d71 AK |
1650 | } |
1651 | ||
1d2024f6 AD |
1652 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1653 | struct sk_buff *skb) | |
1654 | { | |
f800326d | 1655 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1656 | |
1657 | /* set gso_size to avoid messing up TCP MSS */ | |
1658 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1659 | IXGBE_CB(skb)->append_cnt); | |
96be80ab | 1660 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; |
1d2024f6 AD |
1661 | } |
1662 | ||
1663 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1664 | struct sk_buff *skb) | |
1665 | { | |
1666 | /* if append_cnt is 0 then frame is not RSC */ | |
1667 | if (!IXGBE_CB(skb)->append_cnt) | |
1668 | return; | |
1669 | ||
1670 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1671 | rx_ring->rx_stats.rsc_flush++; | |
1672 | ||
1673 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1674 | ||
1675 | /* gso_size is computed using append_cnt so always clear it last */ | |
1676 | IXGBE_CB(skb)->append_cnt = 0; | |
1677 | } | |
1678 | ||
8a0da21b AD |
1679 | /** |
1680 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1681 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1682 | * @rx_desc: pointer to the EOP Rx descriptor | |
1683 | * @skb: pointer to current skb being populated | |
f8212f97 | 1684 | * |
8a0da21b AD |
1685 | * This function checks the ring, descriptor, and packet information in |
1686 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1687 | * other fields within the skb. | |
f8212f97 | 1688 | **/ |
8a0da21b AD |
1689 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1690 | union ixgbe_adv_rx_desc *rx_desc, | |
1691 | struct sk_buff *skb) | |
f8212f97 | 1692 | { |
43e95f11 | 1693 | struct net_device *dev = rx_ring->netdev; |
a9763f3c | 1694 | u32 flags = rx_ring->q_vector->adapter->flags; |
43e95f11 | 1695 | |
8a0da21b AD |
1696 | ixgbe_update_rsc_stats(rx_ring, skb); |
1697 | ||
1698 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1699 | |
8a0da21b AD |
1700 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1701 | ||
a9763f3c MR |
1702 | if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED)) |
1703 | ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); | |
3a6a4eda | 1704 | |
f646968f | 1705 | if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
43e95f11 | 1706 | ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { |
8a0da21b | 1707 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); |
86a9bad3 | 1708 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
f8212f97 AD |
1709 | } |
1710 | ||
8a0da21b | 1711 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1712 | |
43e95f11 | 1713 | skb->protocol = eth_type_trans(skb, dev); |
f8212f97 AD |
1714 | } |
1715 | ||
8a0da21b AD |
1716 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1717 | struct sk_buff *skb) | |
aa80175a | 1718 | { |
93f93a44 | 1719 | skb_mark_napi_id(skb, &q_vector->napi); |
b4640030 | 1720 | if (ixgbe_qv_busy_polling(q_vector)) |
5a85e737 | 1721 | netif_receive_skb(skb); |
8a0da21b | 1722 | else |
856f606e | 1723 | napi_gro_receive(&q_vector->napi, skb); |
aa80175a | 1724 | } |
43634e82 | 1725 | |
f800326d AD |
1726 | /** |
1727 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1728 | * @rx_ring: Rx ring being processed | |
1729 | * @rx_desc: Rx descriptor for current buffer | |
1730 | * @skb: Current socket buffer containing buffer in progress | |
1731 | * | |
1732 | * This function updates next to clean. If the buffer is an EOP buffer | |
1733 | * this function exits returning false, otherwise it will place the | |
1734 | * sk_buff in the next buffer to be chained and return true indicating | |
1735 | * that this is in fact a non-EOP buffer. | |
1736 | **/ | |
1737 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1738 | union ixgbe_adv_rx_desc *rx_desc, | |
1739 | struct sk_buff *skb) | |
1740 | { | |
1741 | u32 ntc = rx_ring->next_to_clean + 1; | |
1742 | ||
1743 | /* fetch, update, and store next to clean */ | |
1744 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1745 | rx_ring->next_to_clean = ntc; | |
1746 | ||
1747 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1748 | ||
5a02cbd1 AD |
1749 | /* update RSC append count if present */ |
1750 | if (ring_is_rsc_enabled(rx_ring)) { | |
1751 | __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1752 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1753 | ||
1754 | if (unlikely(rsc_enabled)) { | |
1755 | u32 rsc_cnt = le32_to_cpu(rsc_enabled); | |
1756 | ||
1757 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1758 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
f800326d | 1759 | |
5a02cbd1 AD |
1760 | /* update ntc based on RSC value */ |
1761 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1762 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1763 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1764 | } | |
f800326d AD |
1765 | } |
1766 | ||
5a02cbd1 AD |
1767 | /* if we are the last buffer then there is nothing else to do */ |
1768 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1769 | return false; | |
1770 | ||
f800326d AD |
1771 | /* place skb in next buffer to be received */ |
1772 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1773 | rx_ring->rx_stats.non_eop_descs++; | |
1774 | ||
1775 | return true; | |
1776 | } | |
1777 | ||
19861ce2 AD |
1778 | /** |
1779 | * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail | |
1780 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1781 | * @skb: pointer to current skb being adjusted | |
1782 | * | |
1783 | * This function is an ixgbe specific version of __pskb_pull_tail. The | |
1784 | * main difference between this version and the original function is that | |
1785 | * this function can make several assumptions about the state of things | |
1786 | * that allow for significant optimizations versus the standard function. | |
1787 | * As a result we can do things like drop a frag and maintain an accurate | |
1788 | * truesize for the skb. | |
1789 | */ | |
1790 | static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring, | |
1791 | struct sk_buff *skb) | |
1792 | { | |
1793 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1794 | unsigned char *va; | |
1795 | unsigned int pull_len; | |
1796 | ||
1797 | /* | |
1798 | * it is valid to use page_address instead of kmap since we are | |
1799 | * working with pages allocated out of the lomem pool per | |
1800 | * alloc_page(GFP_ATOMIC) | |
1801 | */ | |
1802 | va = skb_frag_address(frag); | |
1803 | ||
1804 | /* | |
1805 | * we need the header to contain the greater of either ETH_HLEN or | |
1806 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1807 | */ | |
8496e338 | 1808 | pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE); |
19861ce2 AD |
1809 | |
1810 | /* align pull length to size of long to optimize memcpy performance */ | |
1811 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1812 | ||
1813 | /* update all of the pointers */ | |
1814 | skb_frag_size_sub(frag, pull_len); | |
1815 | frag->page_offset += pull_len; | |
1816 | skb->data_len -= pull_len; | |
1817 | skb->tail += pull_len; | |
19861ce2 AD |
1818 | } |
1819 | ||
42073d91 AD |
1820 | /** |
1821 | * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB | |
1822 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1823 | * @skb: pointer to current skb being updated | |
1824 | * | |
1825 | * This function provides a basic DMA sync up for the first fragment of an | |
1826 | * skb. The reason for doing this is that the first fragment cannot be | |
1827 | * unmapped until we have reached the end of packet descriptor for a buffer | |
1828 | * chain. | |
1829 | */ | |
1830 | static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring, | |
1831 | struct sk_buff *skb) | |
1832 | { | |
1833 | /* if the page was released unmap it, else just sync our portion */ | |
1834 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1835 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1836 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1837 | IXGBE_CB(skb)->page_released = false; | |
1838 | } else { | |
1839 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1840 | ||
1841 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1842 | IXGBE_CB(skb)->dma, | |
1843 | frag->page_offset, | |
1844 | ixgbe_rx_bufsz(rx_ring), | |
1845 | DMA_FROM_DEVICE); | |
1846 | } | |
1847 | IXGBE_CB(skb)->dma = 0; | |
1848 | } | |
1849 | ||
f800326d AD |
1850 | /** |
1851 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1852 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1853 | * @rx_desc: pointer to the EOP Rx descriptor | |
1854 | * @skb: pointer to current skb being fixed | |
1855 | * | |
1856 | * Check for corrupted packet headers caused by senders on the local L2 | |
1857 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1858 | * should be very rare. | |
1859 | * | |
1860 | * Also address the case where we are pulling data in on pages only | |
1861 | * and as such no data is present in the skb header. | |
1862 | * | |
1863 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1864 | * it is large enough to qualify as a valid Ethernet frame. | |
1865 | * | |
1866 | * Returns true if an error was encountered and skb was freed. | |
1867 | **/ | |
1868 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1869 | union ixgbe_adv_rx_desc *rx_desc, | |
1870 | struct sk_buff *skb) | |
1871 | { | |
f800326d | 1872 | struct net_device *netdev = rx_ring->netdev; |
f800326d AD |
1873 | |
1874 | /* verify that the packet does not have any known errors */ | |
1875 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1876 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1877 | !(netdev->features & NETIF_F_RXALL))) { | |
1878 | dev_kfree_skb_any(skb); | |
1879 | return true; | |
1880 | } | |
1881 | ||
19861ce2 | 1882 | /* place header in linear portion of buffer */ |
cf3fe7ac AD |
1883 | if (skb_is_nonlinear(skb)) |
1884 | ixgbe_pull_tail(rx_ring, skb); | |
f800326d | 1885 | |
57efd44c AD |
1886 | #ifdef IXGBE_FCOE |
1887 | /* do not attempt to pad FCoE Frames as this will disrupt DDP */ | |
1888 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) | |
1889 | return false; | |
1890 | ||
1891 | #endif | |
a94d9e22 AD |
1892 | /* if eth_skb_pad returns an error the skb was freed */ |
1893 | if (eth_skb_pad(skb)) | |
1894 | return true; | |
f800326d AD |
1895 | |
1896 | return false; | |
1897 | } | |
1898 | ||
f800326d AD |
1899 | /** |
1900 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1901 | * @rx_ring: rx descriptor ring to store buffers on | |
1902 | * @old_buff: donor buffer to have page reused | |
1903 | * | |
0549ae20 | 1904 | * Synchronizes page for reuse by the adapter |
f800326d AD |
1905 | **/ |
1906 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1907 | struct ixgbe_rx_buffer *old_buff) | |
1908 | { | |
1909 | struct ixgbe_rx_buffer *new_buff; | |
1910 | u16 nta = rx_ring->next_to_alloc; | |
f800326d AD |
1911 | |
1912 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1913 | ||
1914 | /* update, and store next to alloc */ | |
1915 | nta++; | |
1916 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1917 | ||
1918 | /* transfer page from old buffer to new buffer */ | |
18cb652a | 1919 | *new_buff = *old_buff; |
f800326d AD |
1920 | |
1921 | /* sync the buffer for use by the device */ | |
1922 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
0549ae20 AD |
1923 | new_buff->page_offset, |
1924 | ixgbe_rx_bufsz(rx_ring), | |
f800326d | 1925 | DMA_FROM_DEVICE); |
f800326d AD |
1926 | } |
1927 | ||
18cb652a AD |
1928 | static inline bool ixgbe_page_is_reserved(struct page *page) |
1929 | { | |
2f064f34 | 1930 | return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page); |
18cb652a AD |
1931 | } |
1932 | ||
f800326d AD |
1933 | /** |
1934 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1935 | * @rx_ring: rx descriptor ring to transact packets on | |
1936 | * @rx_buffer: buffer containing page to add | |
1937 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1938 | * @skb: sk_buff to place the data into | |
1939 | * | |
0549ae20 AD |
1940 | * This function will add the data contained in rx_buffer->page to the skb. |
1941 | * This is done either through a direct copy if the data in the buffer is | |
1942 | * less than the skb header size, otherwise it will just attach the page as | |
1943 | * a frag to the skb. | |
1944 | * | |
1945 | * The function will then update the page offset if necessary and return | |
1946 | * true if the buffer can be reused by the adapter. | |
f800326d | 1947 | **/ |
0549ae20 | 1948 | static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, |
f800326d | 1949 | struct ixgbe_rx_buffer *rx_buffer, |
0549ae20 AD |
1950 | union ixgbe_adv_rx_desc *rx_desc, |
1951 | struct sk_buff *skb) | |
f800326d | 1952 | { |
0549ae20 AD |
1953 | struct page *page = rx_buffer->page; |
1954 | unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); | |
09816fbe | 1955 | #if (PAGE_SIZE < 8192) |
0549ae20 | 1956 | unsigned int truesize = ixgbe_rx_bufsz(rx_ring); |
09816fbe AD |
1957 | #else |
1958 | unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); | |
1959 | unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) - | |
1960 | ixgbe_rx_bufsz(rx_ring); | |
1961 | #endif | |
0549ae20 | 1962 | |
cf3fe7ac AD |
1963 | if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) { |
1964 | unsigned char *va = page_address(page) + rx_buffer->page_offset; | |
1965 | ||
1966 | memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); | |
1967 | ||
18cb652a AD |
1968 | /* page is not reserved, we can reuse buffer as-is */ |
1969 | if (likely(!ixgbe_page_is_reserved(page))) | |
cf3fe7ac AD |
1970 | return true; |
1971 | ||
1972 | /* this page cannot be reused so discard it */ | |
18cb652a | 1973 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
cf3fe7ac AD |
1974 | return false; |
1975 | } | |
1976 | ||
0549ae20 AD |
1977 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, |
1978 | rx_buffer->page_offset, size, truesize); | |
1979 | ||
09816fbe | 1980 | /* avoid re-using remote pages */ |
18cb652a | 1981 | if (unlikely(ixgbe_page_is_reserved(page))) |
09816fbe AD |
1982 | return false; |
1983 | ||
1984 | #if (PAGE_SIZE < 8192) | |
1985 | /* if we are only owner of page we can reuse it */ | |
1986 | if (unlikely(page_count(page) != 1)) | |
0549ae20 AD |
1987 | return false; |
1988 | ||
1989 | /* flip page offset to other buffer */ | |
1990 | rx_buffer->page_offset ^= truesize; | |
09816fbe AD |
1991 | #else |
1992 | /* move offset up to the next cache line */ | |
1993 | rx_buffer->page_offset += truesize; | |
1994 | ||
1995 | if (rx_buffer->page_offset > last_offset) | |
1996 | return false; | |
09816fbe | 1997 | #endif |
0549ae20 | 1998 | |
18cb652a AD |
1999 | /* Even if we own the page, we are not allowed to use atomic_set() |
2000 | * This would break get_page_unless_zero() users. | |
2001 | */ | |
fe896d18 | 2002 | page_ref_inc(page); |
18cb652a | 2003 | |
0549ae20 | 2004 | return true; |
f800326d AD |
2005 | } |
2006 | ||
18806c9e AD |
2007 | static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring, |
2008 | union ixgbe_adv_rx_desc *rx_desc) | |
2009 | { | |
2010 | struct ixgbe_rx_buffer *rx_buffer; | |
2011 | struct sk_buff *skb; | |
2012 | struct page *page; | |
2013 | ||
2014 | rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; | |
2015 | page = rx_buffer->page; | |
2016 | prefetchw(page); | |
2017 | ||
2018 | skb = rx_buffer->skb; | |
2019 | ||
2020 | if (likely(!skb)) { | |
2021 | void *page_addr = page_address(page) + | |
2022 | rx_buffer->page_offset; | |
2023 | ||
2024 | /* prefetch first cache line of first page */ | |
2025 | prefetch(page_addr); | |
2026 | #if L1_CACHE_BYTES < 128 | |
2027 | prefetch(page_addr + L1_CACHE_BYTES); | |
2028 | #endif | |
2029 | ||
2030 | /* allocate a skb to store the frags */ | |
67fd893e AD |
2031 | skb = napi_alloc_skb(&rx_ring->q_vector->napi, |
2032 | IXGBE_RX_HDR_SIZE); | |
18806c9e AD |
2033 | if (unlikely(!skb)) { |
2034 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
2035 | return NULL; | |
2036 | } | |
2037 | ||
2038 | /* | |
2039 | * we will be copying header into skb->data in | |
2040 | * pskb_may_pull so it is in our interest to prefetch | |
2041 | * it now to avoid a possible cache miss | |
2042 | */ | |
2043 | prefetchw(skb->data); | |
2044 | ||
2045 | /* | |
2046 | * Delay unmapping of the first packet. It carries the | |
2047 | * header information, HW may still access the header | |
2048 | * after the writeback. Only unmap it when EOP is | |
2049 | * reached | |
2050 | */ | |
2051 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
2052 | goto dma_sync; | |
2053 | ||
2054 | IXGBE_CB(skb)->dma = rx_buffer->dma; | |
2055 | } else { | |
2056 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) | |
2057 | ixgbe_dma_sync_frag(rx_ring, skb); | |
2058 | ||
2059 | dma_sync: | |
2060 | /* we are reusing so sync this buffer for CPU use */ | |
2061 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
2062 | rx_buffer->dma, | |
2063 | rx_buffer->page_offset, | |
2064 | ixgbe_rx_bufsz(rx_ring), | |
2065 | DMA_FROM_DEVICE); | |
18cb652a AD |
2066 | |
2067 | rx_buffer->skb = NULL; | |
18806c9e AD |
2068 | } |
2069 | ||
2070 | /* pull page into skb */ | |
2071 | if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { | |
2072 | /* hand second half of page back to the ring */ | |
2073 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
2074 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
2075 | /* the page has been released from the ring */ | |
2076 | IXGBE_CB(skb)->page_released = true; | |
2077 | } else { | |
2078 | /* we are not reusing the buffer so unmap it */ | |
2079 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
2080 | ixgbe_rx_pg_size(rx_ring), | |
2081 | DMA_FROM_DEVICE); | |
2082 | } | |
2083 | ||
2084 | /* clear contents of buffer_info */ | |
18806c9e AD |
2085 | rx_buffer->page = NULL; |
2086 | ||
2087 | return skb; | |
f800326d AD |
2088 | } |
2089 | ||
2090 | /** | |
2091 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
2092 | * @q_vector: structure containing interrupt and ring information | |
2093 | * @rx_ring: rx descriptor ring to transact packets on | |
2094 | * @budget: Total limit on number of packets to process | |
2095 | * | |
2096 | * This function provides a "bounce buffer" approach to Rx interrupt | |
2097 | * processing. The advantage to this is that on systems that have | |
2098 | * expensive overhead for IOMMU access this provides a means of avoiding | |
2099 | * it by maintaining the mapping of the page to the syste. | |
2100 | * | |
5a85e737 | 2101 | * Returns amount of work completed |
f800326d | 2102 | **/ |
5a85e737 | 2103 | static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 2104 | struct ixgbe_ring *rx_ring, |
f4de00ed | 2105 | const int budget) |
9a799d71 | 2106 | { |
d2f4fbe2 | 2107 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 2108 | #ifdef IXGBE_FCOE |
f800326d | 2109 | struct ixgbe_adapter *adapter = q_vector->adapter; |
4ffdf91a MR |
2110 | int ddp_bytes; |
2111 | unsigned int mss = 0; | |
3d8fd385 | 2112 | #endif /* IXGBE_FCOE */ |
f800326d | 2113 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 2114 | |
fdabfc8a | 2115 | while (likely(total_rx_packets < budget)) { |
f800326d AD |
2116 | union ixgbe_adv_rx_desc *rx_desc; |
2117 | struct sk_buff *skb; | |
f800326d AD |
2118 | |
2119 | /* return some buffers to hardware, one at a time is too slow */ | |
2120 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
2121 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
2122 | cleaned_count = 0; | |
2123 | } | |
2124 | ||
18806c9e | 2125 | rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); |
f800326d | 2126 | |
124b74c1 | 2127 | if (!rx_desc->wb.upper.status_error) |
f800326d | 2128 | break; |
9a799d71 | 2129 | |
124b74c1 | 2130 | /* This memory barrier is needed to keep us from reading |
f800326d | 2131 | * any other fields out of the rx_desc until we know the |
124b74c1 | 2132 | * descriptor has been written back |
f800326d | 2133 | */ |
124b74c1 | 2134 | dma_rmb(); |
9a799d71 | 2135 | |
18806c9e AD |
2136 | /* retrieve a buffer from the ring */ |
2137 | skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc); | |
f800326d | 2138 | |
18806c9e AD |
2139 | /* exit if we failed to retrieve a buffer */ |
2140 | if (!skb) | |
2141 | break; | |
9a799d71 | 2142 | |
9a799d71 | 2143 | cleaned_count++; |
f8212f97 | 2144 | |
f800326d AD |
2145 | /* place incomplete frames back on ring for completion */ |
2146 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
2147 | continue; | |
c267fc16 | 2148 | |
f800326d AD |
2149 | /* verify the packet layout is correct */ |
2150 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
2151 | continue; | |
9a799d71 | 2152 | |
d2f4fbe2 AV |
2153 | /* probably a little skewed due to removing CRC */ |
2154 | total_rx_bytes += skb->len; | |
d2f4fbe2 | 2155 | |
8a0da21b AD |
2156 | /* populate checksum, timestamp, VLAN, and protocol */ |
2157 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
2158 | ||
332d4a7d YZ |
2159 | #ifdef IXGBE_FCOE |
2160 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
57efd44c | 2161 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { |
f56e0cb1 | 2162 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
4ffdf91a MR |
2163 | /* include DDPed FCoE data */ |
2164 | if (ddp_bytes > 0) { | |
2165 | if (!mss) { | |
2166 | mss = rx_ring->netdev->mtu - | |
2167 | sizeof(struct fcoe_hdr) - | |
2168 | sizeof(struct fc_frame_header) - | |
2169 | sizeof(struct fcoe_crc_eof); | |
2170 | if (mss > 512) | |
2171 | mss &= ~511; | |
2172 | } | |
2173 | total_rx_bytes += ddp_bytes; | |
2174 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, | |
2175 | mss); | |
2176 | } | |
63d635b2 AD |
2177 | if (!ddp_bytes) { |
2178 | dev_kfree_skb_any(skb); | |
f800326d | 2179 | continue; |
63d635b2 | 2180 | } |
3d8fd385 | 2181 | } |
f800326d | 2182 | |
332d4a7d | 2183 | #endif /* IXGBE_FCOE */ |
8a0da21b | 2184 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 2185 | |
f800326d | 2186 | /* update budget accounting */ |
f4de00ed | 2187 | total_rx_packets++; |
fdabfc8a | 2188 | } |
9a799d71 | 2189 | |
c267fc16 AD |
2190 | u64_stats_update_begin(&rx_ring->syncp); |
2191 | rx_ring->stats.packets += total_rx_packets; | |
2192 | rx_ring->stats.bytes += total_rx_bytes; | |
2193 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
2194 | q_vector->rx.total_packets += total_rx_packets; |
2195 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 2196 | |
5a85e737 | 2197 | return total_rx_packets; |
9a799d71 AK |
2198 | } |
2199 | ||
e0d1095a | 2200 | #ifdef CONFIG_NET_RX_BUSY_POLL |
5a85e737 ET |
2201 | /* must be called with local_bh_disable()d */ |
2202 | static int ixgbe_low_latency_recv(struct napi_struct *napi) | |
2203 | { | |
2204 | struct ixgbe_q_vector *q_vector = | |
2205 | container_of(napi, struct ixgbe_q_vector, napi); | |
2206 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2207 | struct ixgbe_ring *ring; | |
2208 | int found = 0; | |
2209 | ||
2210 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
2211 | return LL_FLUSH_FAILED; | |
2212 | ||
2213 | if (!ixgbe_qv_lock_poll(q_vector)) | |
2214 | return LL_FLUSH_BUSY; | |
2215 | ||
2216 | ixgbe_for_each_ring(ring, q_vector->rx) { | |
2217 | found = ixgbe_clean_rx_irq(q_vector, ring, 4); | |
b4640030 | 2218 | #ifdef BP_EXTENDED_STATS |
7e15b90f ET |
2219 | if (found) |
2220 | ring->stats.cleaned += found; | |
2221 | else | |
2222 | ring->stats.misses++; | |
2223 | #endif | |
5a85e737 ET |
2224 | if (found) |
2225 | break; | |
2226 | } | |
2227 | ||
2228 | ixgbe_qv_unlock_poll(q_vector); | |
2229 | ||
2230 | return found; | |
2231 | } | |
e0d1095a | 2232 | #endif /* CONFIG_NET_RX_BUSY_POLL */ |
5a85e737 | 2233 | |
9a799d71 AK |
2234 | /** |
2235 | * ixgbe_configure_msix - Configure MSI-X hardware | |
2236 | * @adapter: board private structure | |
2237 | * | |
2238 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
2239 | * interrupts. | |
2240 | **/ | |
2241 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
2242 | { | |
021230d4 | 2243 | struct ixgbe_q_vector *q_vector; |
49c7ffbe | 2244 | int v_idx; |
021230d4 | 2245 | u32 mask; |
9a799d71 | 2246 | |
8e34d1aa AD |
2247 | /* Populate MSIX to EITR Select */ |
2248 | if (adapter->num_vfs > 32) { | |
b4f47a48 | 2249 | u32 eitrsel = BIT(adapter->num_vfs - 32) - 1; |
8e34d1aa AD |
2250 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); |
2251 | } | |
2252 | ||
4df10466 JB |
2253 | /* |
2254 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
2255 | * corresponding register. |
2256 | */ | |
49c7ffbe | 2257 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { |
efe3d3c8 | 2258 | struct ixgbe_ring *ring; |
7a921c93 | 2259 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 2260 | |
a557928e | 2261 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
2262 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
2263 | ||
a557928e | 2264 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
2265 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
2266 | ||
fe49f04a | 2267 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
2268 | } |
2269 | ||
bd508178 AD |
2270 | switch (adapter->hw.mac.type) { |
2271 | case ixgbe_mac_82598EB: | |
e8e26350 | 2272 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 2273 | v_idx); |
bd508178 AD |
2274 | break; |
2275 | case ixgbe_mac_82599EB: | |
b93a2226 | 2276 | case ixgbe_mac_X540: |
9a75a1ac DS |
2277 | case ixgbe_mac_X550: |
2278 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2279 | case ixgbe_mac_x550em_a: |
e8e26350 | 2280 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 2281 | break; |
bd508178 AD |
2282 | default: |
2283 | break; | |
2284 | } | |
021230d4 AV |
2285 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
2286 | ||
41fb9248 | 2287 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 2288 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
2289 | mask &= ~(IXGBE_EIMS_OTHER | |
2290 | IXGBE_EIMS_MAILBOX | | |
2291 | IXGBE_EIMS_LSC); | |
2292 | ||
021230d4 | 2293 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
2294 | } |
2295 | ||
f494e8fa AV |
2296 | enum latency_range { |
2297 | lowest_latency = 0, | |
2298 | low_latency = 1, | |
2299 | bulk_latency = 2, | |
2300 | latency_invalid = 255 | |
2301 | }; | |
2302 | ||
2303 | /** | |
2304 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
2305 | * @q_vector: structure containing interrupt and ring information |
2306 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
2307 | * |
2308 | * Stores a new ITR value based on packets and byte | |
2309 | * counts during the last interrupt. The advantage of per interrupt | |
2310 | * computation is faster updates and more accurate ITR for the current | |
2311 | * traffic pattern. Constants in this function were computed | |
2312 | * based on theoretical maximum wire speed and thresholds were set based | |
2313 | * on testing data as well as attempting to minimize response time | |
2314 | * while increasing bulk throughput. | |
2315 | * this functionality is controlled by the InterruptThrottleRate module | |
2316 | * parameter (see ixgbe_param.c) | |
2317 | **/ | |
bd198058 AD |
2318 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
2319 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 2320 | { |
bd198058 AD |
2321 | int bytes = ring_container->total_bytes; |
2322 | int packets = ring_container->total_packets; | |
2323 | u32 timepassed_us; | |
621bd70e | 2324 | u64 bytes_perint; |
bd198058 | 2325 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
2326 | |
2327 | if (packets == 0) | |
bd198058 | 2328 | return; |
f494e8fa AV |
2329 | |
2330 | /* simple throttlerate management | |
621bd70e AD |
2331 | * 0-10MB/s lowest (100000 ints/s) |
2332 | * 10-20MB/s low (20000 ints/s) | |
8ac34f10 | 2333 | * 20-1249MB/s bulk (12000 ints/s) |
f494e8fa AV |
2334 | */ |
2335 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 2336 | timepassed_us = q_vector->itr >> 2; |
bdbeefe8 DS |
2337 | if (timepassed_us == 0) |
2338 | return; | |
2339 | ||
f494e8fa AV |
2340 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
2341 | ||
2342 | switch (itr_setting) { | |
2343 | case lowest_latency: | |
621bd70e | 2344 | if (bytes_perint > 10) |
bd198058 | 2345 | itr_setting = low_latency; |
f494e8fa AV |
2346 | break; |
2347 | case low_latency: | |
621bd70e | 2348 | if (bytes_perint > 20) |
bd198058 | 2349 | itr_setting = bulk_latency; |
621bd70e | 2350 | else if (bytes_perint <= 10) |
bd198058 | 2351 | itr_setting = lowest_latency; |
f494e8fa AV |
2352 | break; |
2353 | case bulk_latency: | |
621bd70e | 2354 | if (bytes_perint <= 20) |
bd198058 | 2355 | itr_setting = low_latency; |
f494e8fa AV |
2356 | break; |
2357 | } | |
2358 | ||
bd198058 AD |
2359 | /* clear work counters since we have the values we need */ |
2360 | ring_container->total_bytes = 0; | |
2361 | ring_container->total_packets = 0; | |
2362 | ||
2363 | /* write updated itr to ring container */ | |
2364 | ring_container->itr = itr_setting; | |
f494e8fa AV |
2365 | } |
2366 | ||
509ee935 JB |
2367 | /** |
2368 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 2369 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
2370 | * |
2371 | * This function is made to be called by ethtool and by the driver | |
2372 | * when it needs to update EITR registers at runtime. Hardware | |
2373 | * specific quirks/differences are taken care of here. | |
2374 | */ | |
fe49f04a | 2375 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 2376 | { |
fe49f04a | 2377 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 2378 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2379 | int v_idx = q_vector->v_idx; |
5d967eb7 | 2380 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 2381 | |
bd508178 AD |
2382 | switch (adapter->hw.mac.type) { |
2383 | case ixgbe_mac_82598EB: | |
509ee935 JB |
2384 | /* must write high and low 16 bits to reset counter */ |
2385 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
2386 | break; |
2387 | case ixgbe_mac_82599EB: | |
b93a2226 | 2388 | case ixgbe_mac_X540: |
9a75a1ac DS |
2389 | case ixgbe_mac_X550: |
2390 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2391 | case ixgbe_mac_x550em_a: |
509ee935 JB |
2392 | /* |
2393 | * set the WDIS bit to not clear the timer bits and cause an | |
2394 | * immediate assertion of the interrupt | |
2395 | */ | |
2396 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
2397 | break; |
2398 | default: | |
2399 | break; | |
509ee935 JB |
2400 | } |
2401 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
2402 | } | |
2403 | ||
bd198058 | 2404 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 2405 | { |
d5bf4f67 | 2406 | u32 new_itr = q_vector->itr; |
bd198058 | 2407 | u8 current_itr; |
f494e8fa | 2408 | |
bd198058 AD |
2409 | ixgbe_update_itr(q_vector, &q_vector->tx); |
2410 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 2411 | |
08c8833b | 2412 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
2413 | |
2414 | switch (current_itr) { | |
2415 | /* counts and packets in update_itr are dependent on these numbers */ | |
2416 | case lowest_latency: | |
d5bf4f67 | 2417 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
2418 | break; |
2419 | case low_latency: | |
d5bf4f67 | 2420 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
2421 | break; |
2422 | case bulk_latency: | |
8ac34f10 | 2423 | new_itr = IXGBE_12K_ITR; |
f494e8fa | 2424 | break; |
bd198058 AD |
2425 | default: |
2426 | break; | |
f494e8fa AV |
2427 | } |
2428 | ||
d5bf4f67 | 2429 | if (new_itr != q_vector->itr) { |
fe49f04a | 2430 | /* do an exponential smoothing */ |
d5bf4f67 ET |
2431 | new_itr = (10 * new_itr * q_vector->itr) / |
2432 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 2433 | |
bd198058 | 2434 | /* save the algorithm value here */ |
5d967eb7 | 2435 | q_vector->itr = new_itr; |
fe49f04a AD |
2436 | |
2437 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2438 | } |
f494e8fa AV |
2439 | } |
2440 | ||
119fc60a | 2441 | /** |
de88eeeb | 2442 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2443 | * @adapter: pointer to adapter |
119fc60a | 2444 | **/ |
f0f9778d | 2445 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2446 | { |
119fc60a MC |
2447 | struct ixgbe_hw *hw = &adapter->hw; |
2448 | u32 eicr = adapter->interrupt_event; | |
2449 | ||
f0f9778d | 2450 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2451 | return; |
2452 | ||
f0f9778d AD |
2453 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2454 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2455 | return; | |
2456 | ||
2457 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2458 | ||
7ca647bd | 2459 | switch (hw->device_id) { |
f0f9778d AD |
2460 | case IXGBE_DEV_ID_82599_T3_LOM: |
2461 | /* | |
2462 | * Since the warning interrupt is for both ports | |
2463 | * we don't have to check if: | |
2464 | * - This interrupt wasn't for our port. | |
2465 | * - We may have missed the interrupt so always have to | |
2466 | * check if we got a LSC | |
2467 | */ | |
9a900eca | 2468 | if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) && |
f0f9778d AD |
2469 | !(eicr & IXGBE_EICR_LSC)) |
2470 | return; | |
2471 | ||
2472 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
3d292265 | 2473 | u32 speed; |
f0f9778d | 2474 | bool link_up = false; |
7ca647bd | 2475 | |
3d292265 | 2476 | hw->mac.ops.check_link(hw, &speed, &link_up, false); |
7ca647bd | 2477 | |
f0f9778d AD |
2478 | if (link_up) |
2479 | return; | |
2480 | } | |
2481 | ||
2482 | /* Check if this is not due to overtemp */ | |
2483 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2484 | return; | |
2485 | ||
2486 | break; | |
7ca647bd | 2487 | default: |
597f22d6 DS |
2488 | if (adapter->hw.mac.type >= ixgbe_mac_X540) |
2489 | return; | |
9a900eca | 2490 | if (!(eicr & IXGBE_EICR_GPI_SDP0(hw))) |
119fc60a | 2491 | return; |
7ca647bd | 2492 | break; |
119fc60a | 2493 | } |
f44e751b | 2494 | e_crit(drv, "%s\n", ixgbe_overheat_msg); |
f0f9778d AD |
2495 | |
2496 | adapter->interrupt_event = 0; | |
119fc60a MC |
2497 | } |
2498 | ||
0befdb3e JB |
2499 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2500 | { | |
2501 | struct ixgbe_hw *hw = &adapter->hw; | |
2502 | ||
2503 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
9a900eca | 2504 | (eicr & IXGBE_EICR_GPI_SDP1(hw))) { |
396e799c | 2505 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e | 2506 | /* write to clear the interrupt */ |
9a900eca | 2507 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); |
0befdb3e JB |
2508 | } |
2509 | } | |
cf8280ee | 2510 | |
4f51bf70 JK |
2511 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2512 | { | |
9a900eca DS |
2513 | struct ixgbe_hw *hw = &adapter->hw; |
2514 | ||
4f51bf70 JK |
2515 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) |
2516 | return; | |
2517 | ||
2518 | switch (adapter->hw.mac.type) { | |
2519 | case ixgbe_mac_82599EB: | |
2520 | /* | |
2521 | * Need to check link state so complete overtemp check | |
2522 | * on service task | |
2523 | */ | |
9a900eca DS |
2524 | if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) || |
2525 | (eicr & IXGBE_EICR_LSC)) && | |
4f51bf70 JK |
2526 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { |
2527 | adapter->interrupt_event = eicr; | |
2528 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2529 | ixgbe_service_event_schedule(adapter); | |
2530 | return; | |
2531 | } | |
2532 | return; | |
2533 | case ixgbe_mac_X540: | |
2534 | if (!(eicr & IXGBE_EICR_TS)) | |
2535 | return; | |
2536 | break; | |
2537 | default: | |
2538 | return; | |
2539 | } | |
2540 | ||
f44e751b | 2541 | e_crit(drv, "%s\n", ixgbe_overheat_msg); |
4f51bf70 JK |
2542 | } |
2543 | ||
45788d2a DS |
2544 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
2545 | { | |
2546 | switch (hw->mac.type) { | |
2547 | case ixgbe_mac_82598EB: | |
2548 | if (hw->phy.type == ixgbe_phy_nl) | |
2549 | return true; | |
2550 | return false; | |
2551 | case ixgbe_mac_82599EB: | |
2552 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2553 | case ixgbe_mac_x550em_a: |
45788d2a DS |
2554 | switch (hw->mac.ops.get_media_type(hw)) { |
2555 | case ixgbe_media_type_fiber: | |
2556 | case ixgbe_media_type_fiber_qsfp: | |
2557 | return true; | |
2558 | default: | |
2559 | return false; | |
2560 | } | |
2561 | default: | |
2562 | return false; | |
2563 | } | |
2564 | } | |
2565 | ||
e8e26350 PW |
2566 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2567 | { | |
2568 | struct ixgbe_hw *hw = &adapter->hw; | |
4ccc650c | 2569 | u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw); |
e8e26350 | 2570 | |
4ccc650c DS |
2571 | if (!ixgbe_is_sfp(hw)) |
2572 | return; | |
2573 | ||
2574 | /* Later MAC's use different SDP */ | |
2575 | if (hw->mac.type >= ixgbe_mac_X540) | |
2576 | eicr_mask = IXGBE_EICR_GPI_SDP0_X540; | |
2577 | ||
2578 | if (eicr & eicr_mask) { | |
73c4b7cd | 2579 | /* Clear the interrupt */ |
4ccc650c | 2580 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask); |
7086400d AD |
2581 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2582 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
58e7cd24 | 2583 | adapter->sfp_poll_time = 0; |
7086400d AD |
2584 | ixgbe_service_event_schedule(adapter); |
2585 | } | |
73c4b7cd AD |
2586 | } |
2587 | ||
4ccc650c DS |
2588 | if (adapter->hw.mac.type == ixgbe_mac_82599EB && |
2589 | (eicr & IXGBE_EICR_GPI_SDP1(hw))) { | |
e8e26350 | 2590 | /* Clear the interrupt */ |
9a900eca | 2591 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw)); |
7086400d AD |
2592 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2593 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2594 | ixgbe_service_event_schedule(adapter); | |
2595 | } | |
e8e26350 PW |
2596 | } |
2597 | } | |
2598 | ||
cf8280ee JB |
2599 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2600 | { | |
2601 | struct ixgbe_hw *hw = &adapter->hw; | |
2602 | ||
2603 | adapter->lsc_int++; | |
2604 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2605 | adapter->link_check_timeout = jiffies; | |
2606 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2607 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2608 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2609 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2610 | } |
2611 | } | |
2612 | ||
fe49f04a AD |
2613 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2614 | u64 qmask) | |
2615 | { | |
2616 | u32 mask; | |
bd508178 | 2617 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2618 | |
bd508178 AD |
2619 | switch (hw->mac.type) { |
2620 | case ixgbe_mac_82598EB: | |
fe49f04a | 2621 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2622 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2623 | break; | |
2624 | case ixgbe_mac_82599EB: | |
b93a2226 | 2625 | case ixgbe_mac_X540: |
9a75a1ac DS |
2626 | case ixgbe_mac_X550: |
2627 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2628 | case ixgbe_mac_x550em_a: |
fe49f04a | 2629 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2630 | if (mask) |
2631 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2632 | mask = (qmask >> 32); |
bd508178 AD |
2633 | if (mask) |
2634 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2635 | break; | |
2636 | default: | |
2637 | break; | |
fe49f04a AD |
2638 | } |
2639 | /* skip the flush */ | |
2640 | } | |
2641 | ||
2642 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2643 | u64 qmask) |
fe49f04a AD |
2644 | { |
2645 | u32 mask; | |
bd508178 | 2646 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2647 | |
bd508178 AD |
2648 | switch (hw->mac.type) { |
2649 | case ixgbe_mac_82598EB: | |
fe49f04a | 2650 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2651 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2652 | break; | |
2653 | case ixgbe_mac_82599EB: | |
b93a2226 | 2654 | case ixgbe_mac_X540: |
9a75a1ac DS |
2655 | case ixgbe_mac_X550: |
2656 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2657 | case ixgbe_mac_x550em_a: |
fe49f04a | 2658 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2659 | if (mask) |
2660 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2661 | mask = (qmask >> 32); |
bd508178 AD |
2662 | if (mask) |
2663 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2664 | break; | |
2665 | default: | |
2666 | break; | |
fe49f04a AD |
2667 | } |
2668 | /* skip the flush */ | |
2669 | } | |
2670 | ||
021230d4 | 2671 | /** |
2c4af694 AD |
2672 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2673 | * @adapter: board private structure | |
021230d4 | 2674 | **/ |
2c4af694 AD |
2675 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2676 | bool flush) | |
9a799d71 | 2677 | { |
9a900eca | 2678 | struct ixgbe_hw *hw = &adapter->hw; |
2c4af694 | 2679 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2680 | |
2c4af694 AD |
2681 | /* don't reenable LSC while waiting for link */ |
2682 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2683 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2684 | |
2c4af694 | 2685 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2686 | switch (adapter->hw.mac.type) { |
2687 | case ixgbe_mac_82599EB: | |
9a900eca | 2688 | mask |= IXGBE_EIMS_GPI_SDP0(hw); |
4f51bf70 JK |
2689 | break; |
2690 | case ixgbe_mac_X540: | |
9a75a1ac DS |
2691 | case ixgbe_mac_X550: |
2692 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2693 | case ixgbe_mac_x550em_a: |
4f51bf70 JK |
2694 | mask |= IXGBE_EIMS_TS; |
2695 | break; | |
2696 | default: | |
2697 | break; | |
2698 | } | |
2c4af694 | 2699 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
9a900eca | 2700 | mask |= IXGBE_EIMS_GPI_SDP1(hw); |
2c4af694 AD |
2701 | switch (adapter->hw.mac.type) { |
2702 | case ixgbe_mac_82599EB: | |
9a900eca DS |
2703 | mask |= IXGBE_EIMS_GPI_SDP1(hw); |
2704 | mask |= IXGBE_EIMS_GPI_SDP2(hw); | |
9a75a1ac | 2705 | /* fall through */ |
858bc081 | 2706 | case ixgbe_mac_X540: |
9a75a1ac DS |
2707 | case ixgbe_mac_X550: |
2708 | case ixgbe_mac_X550EM_x: | |
49425dfc MR |
2709 | case ixgbe_mac_x550em_a: |
2710 | if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP || | |
2d40cd17 | 2711 | adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP || |
49425dfc | 2712 | adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N) |
cbd45ec7 | 2713 | mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw); |
597f22d6 DS |
2714 | if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t) |
2715 | mask |= IXGBE_EICR_GPI_SDP0_X540; | |
858bc081 | 2716 | mask |= IXGBE_EIMS_ECC; |
2c4af694 AD |
2717 | mask |= IXGBE_EIMS_MAILBOX; |
2718 | break; | |
2719 | default: | |
2720 | break; | |
9a799d71 | 2721 | } |
db0677fa | 2722 | |
2c4af694 AD |
2723 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2724 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2725 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2726 | |
2c4af694 AD |
2727 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2728 | if (queues) | |
2729 | ixgbe_irq_enable_queues(adapter, ~0); | |
2730 | if (flush) | |
2731 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2732 | } |
2733 | ||
2c4af694 | 2734 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2735 | { |
a65151ba | 2736 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2737 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2738 | u32 eicr; |
91281fd3 | 2739 | |
54037505 DS |
2740 | /* |
2741 | * Workaround for Silicon errata. Use clear-by-write instead | |
2742 | * of clear-by-read. Reading with EICS will return the | |
2743 | * interrupt causes without clearing, which later be done | |
2744 | * with the write to EICR. | |
2745 | */ | |
2746 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
d87d8307 JK |
2747 | |
2748 | /* The lower 16bits of the EICR register are for the queue interrupts | |
dbedd44e | 2749 | * which should be masked here in order to not accidentally clear them if |
d87d8307 JK |
2750 | * the bits are high when ixgbe_msix_other is called. There is a race |
2751 | * condition otherwise which results in possible performance loss | |
2752 | * especially if the ixgbe_msix_other interrupt is triggering | |
2753 | * consistently (as it would when PPS is turned on for the X540 device) | |
2754 | */ | |
2755 | eicr &= 0xFFFF0000; | |
2756 | ||
54037505 | 2757 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); |
33cf09c9 | 2758 | |
cf8280ee JB |
2759 | if (eicr & IXGBE_EICR_LSC) |
2760 | ixgbe_check_lsc(adapter); | |
f0848276 | 2761 | |
1cdd1ec8 GR |
2762 | if (eicr & IXGBE_EICR_MAILBOX) |
2763 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2764 | |
bd508178 AD |
2765 | switch (hw->mac.type) { |
2766 | case ixgbe_mac_82599EB: | |
b93a2226 | 2767 | case ixgbe_mac_X540: |
9a75a1ac DS |
2768 | case ixgbe_mac_X550: |
2769 | case ixgbe_mac_X550EM_x: | |
49425dfc | 2770 | case ixgbe_mac_x550em_a: |
597f22d6 DS |
2771 | if (hw->phy.type == ixgbe_phy_x550em_ext_t && |
2772 | (eicr & IXGBE_EICR_GPI_SDP0_X540)) { | |
2773 | adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT; | |
2774 | ixgbe_service_event_schedule(adapter); | |
2775 | IXGBE_WRITE_REG(hw, IXGBE_EICR, | |
2776 | IXGBE_EICR_GPI_SDP0_X540); | |
2777 | } | |
d773ce2d DS |
2778 | if (eicr & IXGBE_EICR_ECC) { |
2779 | e_info(link, "Received ECC Err, initiating reset\n"); | |
2780 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
2781 | ixgbe_service_event_schedule(adapter); | |
2782 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); | |
2783 | } | |
c4cf55e5 PWJ |
2784 | /* Handle Flow Director Full threshold interrupt */ |
2785 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2786 | int reinit_count = 0; |
c4cf55e5 | 2787 | int i; |
c4cf55e5 | 2788 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2789 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2790 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2791 | &ring->state)) |
2792 | reinit_count++; | |
2793 | } | |
2794 | if (reinit_count) { | |
2795 | /* no more flow director interrupts until after init */ | |
2796 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2797 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2798 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2799 | } |
2800 | } | |
f0f9778d | 2801 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2802 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2803 | break; |
2804 | default: | |
2805 | break; | |
c4cf55e5 | 2806 | } |
f0848276 | 2807 | |
bd508178 | 2808 | ixgbe_check_fan_failure(adapter, eicr); |
db0677fa | 2809 | |
db0677fa | 2810 | if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) |
a9763f3c | 2811 | ixgbe_ptp_check_pps_event(adapter); |
efe3d3c8 | 2812 | |
7086400d | 2813 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2814 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2815 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2816 | |
9a799d71 | 2817 | return IRQ_HANDLED; |
f0848276 | 2818 | } |
91281fd3 | 2819 | |
4ff7fb12 | 2820 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2821 | { |
021230d4 | 2822 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2823 | |
9b471446 | 2824 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2825 | |
4ff7fb12 | 2826 | if (q_vector->rx.ring || q_vector->tx.ring) |
ef2662b2 | 2827 | napi_schedule_irqoff(&q_vector->napi); |
91281fd3 | 2828 | |
9a799d71 | 2829 | return IRQ_HANDLED; |
91281fd3 AD |
2830 | } |
2831 | ||
eb01b975 AD |
2832 | /** |
2833 | * ixgbe_poll - NAPI Rx polling callback | |
2834 | * @napi: structure for representing this polling device | |
2835 | * @budget: how many packets driver is allowed to clean | |
2836 | * | |
2837 | * This function is used for legacy and MSI, NAPI mode | |
2838 | **/ | |
8af3c33f | 2839 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
2840 | { |
2841 | struct ixgbe_q_vector *q_vector = | |
2842 | container_of(napi, struct ixgbe_q_vector, napi); | |
2843 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2844 | struct ixgbe_ring *ring; | |
32b3e08f | 2845 | int per_ring_budget, work_done = 0; |
eb01b975 AD |
2846 | bool clean_complete = true; |
2847 | ||
2848 | #ifdef CONFIG_IXGBE_DCA | |
2849 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2850 | ixgbe_update_dca(q_vector); | |
2851 | #endif | |
2852 | ||
8220bbc1 AD |
2853 | ixgbe_for_each_ring(ring, q_vector->tx) { |
2854 | if (!ixgbe_clean_tx_irq(q_vector, ring, budget)) | |
2855 | clean_complete = false; | |
2856 | } | |
eb01b975 | 2857 | |
5d6002b7 AD |
2858 | /* Exit if we are called by netpoll or busy polling is active */ |
2859 | if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector)) | |
5a85e737 ET |
2860 | return budget; |
2861 | ||
eb01b975 AD |
2862 | /* attempt to distribute budget to each queue fairly, but don't allow |
2863 | * the budget to go below 1 because we'll exit polling */ | |
2864 | if (q_vector->rx.count > 1) | |
2865 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2866 | else | |
2867 | per_ring_budget = budget; | |
2868 | ||
32b3e08f JB |
2869 | ixgbe_for_each_ring(ring, q_vector->rx) { |
2870 | int cleaned = ixgbe_clean_rx_irq(q_vector, ring, | |
2871 | per_ring_budget); | |
2872 | ||
2873 | work_done += cleaned; | |
8220bbc1 AD |
2874 | if (cleaned >= per_ring_budget) |
2875 | clean_complete = false; | |
32b3e08f | 2876 | } |
eb01b975 | 2877 | |
5a85e737 | 2878 | ixgbe_qv_unlock_napi(q_vector); |
eb01b975 AD |
2879 | /* If all work not completed, return budget and keep polling */ |
2880 | if (!clean_complete) | |
2881 | return budget; | |
2882 | ||
2883 | /* all work done, exit the polling mode */ | |
32b3e08f | 2884 | napi_complete_done(napi, work_done); |
eb01b975 AD |
2885 | if (adapter->rx_itr_setting & 1) |
2886 | ixgbe_set_itr(q_vector); | |
2887 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
b4f47a48 | 2888 | ixgbe_irq_enable_queues(adapter, BIT_ULL(q_vector->v_idx)); |
eb01b975 AD |
2889 | |
2890 | return 0; | |
2891 | } | |
2892 | ||
021230d4 AV |
2893 | /** |
2894 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2895 | * @adapter: board private structure | |
2896 | * | |
2897 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2898 | * interrupts from the kernel. | |
2899 | **/ | |
2900 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2901 | { | |
2902 | struct net_device *netdev = adapter->netdev; | |
207867f5 | 2903 | int vector, err; |
e8e9f696 | 2904 | int ri = 0, ti = 0; |
021230d4 | 2905 | |
49c7ffbe | 2906 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
d0759ebb | 2907 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2908 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2909 | |
4ff7fb12 | 2910 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2911 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2912 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2913 | ti++; | |
2914 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2915 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2916 | "%s-%s-%d", netdev->name, "rx", ri++); |
2917 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2918 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2919 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2920 | } else { |
2921 | /* skip this unused q_vector */ | |
2922 | continue; | |
32aa77a4 | 2923 | } |
207867f5 AD |
2924 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2925 | q_vector->name, q_vector); | |
9a799d71 | 2926 | if (err) { |
396e799c | 2927 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2928 | "Error: %d\n", err); |
021230d4 | 2929 | goto free_queue_irqs; |
9a799d71 | 2930 | } |
207867f5 AD |
2931 | /* If Flow Director is enabled, set interrupt affinity */ |
2932 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2933 | /* assign the mask for this irq */ | |
2934 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2935 | &q_vector->affinity_mask); |
207867f5 | 2936 | } |
9a799d71 AK |
2937 | } |
2938 | ||
021230d4 | 2939 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2940 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2941 | if (err) { |
de88eeeb | 2942 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2943 | goto free_queue_irqs; |
9a799d71 AK |
2944 | } |
2945 | ||
9a799d71 AK |
2946 | return 0; |
2947 | ||
021230d4 | 2948 | free_queue_irqs: |
207867f5 AD |
2949 | while (vector) { |
2950 | vector--; | |
2951 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2952 | NULL); | |
2953 | free_irq(adapter->msix_entries[vector].vector, | |
2954 | adapter->q_vector[vector]); | |
2955 | } | |
021230d4 AV |
2956 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2957 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2958 | kfree(adapter->msix_entries); |
2959 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2960 | return err; |
2961 | } | |
2962 | ||
2963 | /** | |
021230d4 | 2964 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2965 | * @irq: interrupt number |
2966 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2967 | **/ |
2968 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2969 | { | |
a65151ba | 2970 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2971 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2972 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2973 | u32 eicr; |
2974 | ||
54037505 | 2975 | /* |
24ddd967 | 2976 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2977 | * before the read of EICR. |
2978 | */ | |
2979 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2980 | ||
021230d4 | 2981 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2982 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2983 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2984 | if (!eicr) { |
6af3b9eb ET |
2985 | /* |
2986 | * shared interrupt alert! | |
f47cf66e | 2987 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2988 | * have disabled interrupts due to EIAM |
2989 | * finish the workaround of silicon errata on 82598. Unmask | |
2990 | * the interrupt that we masked before the EICR read. | |
2991 | */ | |
2992 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2993 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2994 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2995 | } |
9a799d71 | 2996 | |
cf8280ee JB |
2997 | if (eicr & IXGBE_EICR_LSC) |
2998 | ixgbe_check_lsc(adapter); | |
021230d4 | 2999 | |
bd508178 AD |
3000 | switch (hw->mac.type) { |
3001 | case ixgbe_mac_82599EB: | |
e8e26350 | 3002 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
3003 | /* Fall through */ |
3004 | case ixgbe_mac_X540: | |
9a75a1ac DS |
3005 | case ixgbe_mac_X550: |
3006 | case ixgbe_mac_X550EM_x: | |
49425dfc | 3007 | case ixgbe_mac_x550em_a: |
d773ce2d DS |
3008 | if (eicr & IXGBE_EICR_ECC) { |
3009 | e_info(link, "Received ECC Err, initiating reset\n"); | |
3010 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
3011 | ixgbe_service_event_schedule(adapter); | |
3012 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC); | |
3013 | } | |
4f51bf70 | 3014 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
3015 | break; |
3016 | default: | |
3017 | break; | |
3018 | } | |
e8e26350 | 3019 | |
0befdb3e | 3020 | ixgbe_check_fan_failure(adapter, eicr); |
db0677fa | 3021 | if (unlikely(eicr & IXGBE_EICR_TIMESYNC)) |
a9763f3c | 3022 | ixgbe_ptp_check_pps_event(adapter); |
0befdb3e | 3023 | |
b9f6ed2b | 3024 | /* would disable interrupts here but EIAM disabled it */ |
ef2662b2 | 3025 | napi_schedule_irqoff(&q_vector->napi); |
9a799d71 | 3026 | |
6af3b9eb ET |
3027 | /* |
3028 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
3029 | * ixgbe_poll will re-enable the queue interrupts | |
3030 | */ | |
6af3b9eb ET |
3031 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
3032 | ixgbe_irq_enable(adapter, false, false); | |
3033 | ||
9a799d71 AK |
3034 | return IRQ_HANDLED; |
3035 | } | |
3036 | ||
3037 | /** | |
3038 | * ixgbe_request_irq - initialize interrupts | |
3039 | * @adapter: board private structure | |
3040 | * | |
3041 | * Attempts to configure interrupts using the best available | |
3042 | * capabilities of the hardware and kernel. | |
3043 | **/ | |
021230d4 | 3044 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3045 | { |
3046 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 3047 | int err; |
9a799d71 | 3048 | |
4cc6df29 | 3049 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 3050 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 3051 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 3052 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 3053 | netdev->name, adapter); |
4cc6df29 | 3054 | else |
a0607fd3 | 3055 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 3056 | netdev->name, adapter); |
9a799d71 | 3057 | |
de88eeeb | 3058 | if (err) |
396e799c | 3059 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 3060 | |
9a799d71 AK |
3061 | return err; |
3062 | } | |
3063 | ||
3064 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
3065 | { | |
49c7ffbe | 3066 | int vector; |
9a799d71 | 3067 | |
49c7ffbe AD |
3068 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
3069 | free_irq(adapter->pdev->irq, adapter); | |
3070 | return; | |
3071 | } | |
4cc6df29 | 3072 | |
49c7ffbe AD |
3073 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
3074 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; | |
3075 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
894ff7cf | 3076 | |
49c7ffbe AD |
3077 | /* free only the irqs that were actually requested */ |
3078 | if (!q_vector->rx.ring && !q_vector->tx.ring) | |
3079 | continue; | |
207867f5 | 3080 | |
49c7ffbe AD |
3081 | /* clear the affinity_mask in the IRQ descriptor */ |
3082 | irq_set_affinity_hint(entry->vector, NULL); | |
3083 | ||
3084 | free_irq(entry->vector, q_vector); | |
9a799d71 | 3085 | } |
49c7ffbe AD |
3086 | |
3087 | free_irq(adapter->msix_entries[vector++].vector, adapter); | |
9a799d71 AK |
3088 | } |
3089 | ||
22d5a71b JB |
3090 | /** |
3091 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
3092 | * @adapter: board private structure | |
3093 | **/ | |
3094 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
3095 | { | |
bd508178 AD |
3096 | switch (adapter->hw.mac.type) { |
3097 | case ixgbe_mac_82598EB: | |
835462fc | 3098 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
3099 | break; |
3100 | case ixgbe_mac_82599EB: | |
b93a2226 | 3101 | case ixgbe_mac_X540: |
9a75a1ac DS |
3102 | case ixgbe_mac_X550: |
3103 | case ixgbe_mac_X550EM_x: | |
49425dfc | 3104 | case ixgbe_mac_x550em_a: |
835462fc NS |
3105 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
3106 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 3107 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
3108 | break; |
3109 | default: | |
3110 | break; | |
22d5a71b JB |
3111 | } |
3112 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
3113 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
49c7ffbe AD |
3114 | int vector; |
3115 | ||
3116 | for (vector = 0; vector < adapter->num_q_vectors; vector++) | |
3117 | synchronize_irq(adapter->msix_entries[vector].vector); | |
3118 | ||
3119 | synchronize_irq(adapter->msix_entries[vector++].vector); | |
22d5a71b JB |
3120 | } else { |
3121 | synchronize_irq(adapter->pdev->irq); | |
3122 | } | |
3123 | } | |
3124 | ||
9a799d71 AK |
3125 | /** |
3126 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
3127 | * | |
3128 | **/ | |
3129 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
3130 | { | |
d5bf4f67 | 3131 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 3132 | |
d5bf4f67 | 3133 | ixgbe_write_eitr(q_vector); |
9a799d71 | 3134 | |
e8e26350 PW |
3135 | ixgbe_set_ivar(adapter, 0, 0, 0); |
3136 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 3137 | |
396e799c | 3138 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
3139 | } |
3140 | ||
43e69bf0 AD |
3141 | /** |
3142 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
3143 | * @adapter: board private structure | |
3144 | * @ring: structure containing ring specific data | |
3145 | * | |
3146 | * Configure the Tx descriptor ring after a reset. | |
3147 | **/ | |
84418e3b AD |
3148 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
3149 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
3150 | { |
3151 | struct ixgbe_hw *hw = &adapter->hw; | |
3152 | u64 tdba = ring->dma; | |
2f1860b8 | 3153 | int wait_loop = 10; |
b88c6de2 | 3154 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 3155 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 3156 | |
2f1860b8 | 3157 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 3158 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
3159 | IXGBE_WRITE_FLUSH(hw); |
3160 | ||
43e69bf0 | 3161 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 3162 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
3163 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
3164 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
3165 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
3166 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
3167 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
2a1a091c | 3168 | ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 3169 | |
b88c6de2 AD |
3170 | /* |
3171 | * set WTHRESH to encourage burst writeback, it should not be set | |
67da097e ET |
3172 | * higher than 1 when: |
3173 | * - ITR is 0 as it could cause false TX hangs | |
3174 | * - ITR is set to > 100k int/sec and BQL is enabled | |
b88c6de2 AD |
3175 | * |
3176 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
3177 | * to or less than the number of on chip descriptors, which is | |
3178 | * currently 40. | |
3179 | */ | |
67da097e | 3180 | if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR)) |
b4f47a48 | 3181 | txdctl |= 1u << 16; /* WTHRESH = 1 */ |
b88c6de2 | 3182 | else |
b4f47a48 | 3183 | txdctl |= 8u << 16; /* WTHRESH = 8 */ |
b88c6de2 | 3184 | |
e954b374 AD |
3185 | /* |
3186 | * Setting PTHRESH to 32 both improves performance | |
3187 | * and avoids a TX hang with DFP enabled | |
3188 | */ | |
b4f47a48 | 3189 | txdctl |= (1u << 8) | /* HTHRESH = 1 */ |
b88c6de2 | 3190 | 32; /* PTHRESH = 32 */ |
2f1860b8 AD |
3191 | |
3192 | /* reinitialize flowdirector state */ | |
39cb681b | 3193 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
ee9e0f0b AD |
3194 | ring->atr_sample_rate = adapter->atr_sample_rate; |
3195 | ring->atr_count = 0; | |
3196 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
3197 | } else { | |
3198 | ring->atr_sample_rate = 0; | |
3199 | } | |
2f1860b8 | 3200 | |
fd786b7b AD |
3201 | /* initialize XPS */ |
3202 | if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) { | |
3203 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
3204 | ||
3205 | if (q_vector) | |
2a47fa45 | 3206 | netif_set_xps_queue(ring->netdev, |
fd786b7b AD |
3207 | &q_vector->affinity_mask, |
3208 | ring->queue_index); | |
3209 | } | |
3210 | ||
c84d324c JF |
3211 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
3212 | ||
2f1860b8 | 3213 | /* enable queue */ |
2f1860b8 AD |
3214 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
3215 | ||
3216 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
3217 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3218 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3219 | return; | |
3220 | ||
3221 | /* poll to verify queue is enabled */ | |
3222 | do { | |
032b4325 | 3223 | usleep_range(1000, 2000); |
2f1860b8 AD |
3224 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
3225 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
3226 | if (!wait_loop) | |
3227 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
3228 | } |
3229 | ||
120ff942 AD |
3230 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
3231 | { | |
3232 | struct ixgbe_hw *hw = &adapter->hw; | |
671c0adb | 3233 | u32 rttdcs, mtqc; |
8b1c0b24 | 3234 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
3235 | |
3236 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3237 | return; | |
3238 | ||
3239 | /* disable the arbiter while setting MTQC */ | |
3240 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
3241 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
3242 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
3243 | ||
3244 | /* set transmit pool layout */ | |
671c0adb AD |
3245 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
3246 | mtqc = IXGBE_MTQC_VT_ENA; | |
3247 | if (tcs > 4) | |
3248 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
3249 | else if (tcs > 1) | |
3250 | mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
3251 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
3252 | mtqc |= IXGBE_MTQC_32VF; | |
3253 | else | |
3254 | mtqc |= IXGBE_MTQC_64VF; | |
3255 | } else { | |
3256 | if (tcs > 4) | |
3257 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
3258 | else if (tcs > 1) | |
3259 | mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
8b1c0b24 | 3260 | else |
671c0adb AD |
3261 | mtqc = IXGBE_MTQC_64Q_1PB; |
3262 | } | |
120ff942 | 3263 | |
671c0adb | 3264 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc); |
120ff942 | 3265 | |
671c0adb AD |
3266 | /* Enable Security TX Buffer IFG for multiple pb */ |
3267 | if (tcs) { | |
3268 | u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
3269 | sectx |= IXGBE_SECTX_DCB; | |
3270 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx); | |
120ff942 AD |
3271 | } |
3272 | ||
3273 | /* re-enable the arbiter */ | |
3274 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
3275 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
3276 | } | |
3277 | ||
9a799d71 | 3278 | /** |
3a581073 | 3279 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
3280 | * @adapter: board private structure |
3281 | * | |
3282 | * Configure the Tx unit of the MAC after a reset. | |
3283 | **/ | |
3284 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
3285 | { | |
2f1860b8 AD |
3286 | struct ixgbe_hw *hw = &adapter->hw; |
3287 | u32 dmatxctl; | |
43e69bf0 | 3288 | u32 i; |
9a799d71 | 3289 | |
2f1860b8 AD |
3290 | ixgbe_setup_mtqc(adapter); |
3291 | ||
3292 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3293 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
3294 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
3295 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
3296 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
3297 | } | |
3298 | ||
9a799d71 | 3299 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
3300 | for (i = 0; i < adapter->num_tx_queues; i++) |
3301 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
3302 | } |
3303 | ||
3ebe8fde AD |
3304 | static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, |
3305 | struct ixgbe_ring *ring) | |
3306 | { | |
3307 | struct ixgbe_hw *hw = &adapter->hw; | |
3308 | u8 reg_idx = ring->reg_idx; | |
3309 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
3310 | ||
3311 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
3312 | ||
3313 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
3314 | } | |
3315 | ||
3316 | static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, | |
3317 | struct ixgbe_ring *ring) | |
3318 | { | |
3319 | struct ixgbe_hw *hw = &adapter->hw; | |
3320 | u8 reg_idx = ring->reg_idx; | |
3321 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
3322 | ||
3323 | srrctl &= ~IXGBE_SRRCTL_DROP_EN; | |
3324 | ||
3325 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
3326 | } | |
3327 | ||
3328 | #ifdef CONFIG_IXGBE_DCB | |
3329 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
3330 | #else | |
3331 | static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
3332 | #endif | |
3333 | { | |
3334 | int i; | |
3335 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
3336 | ||
3337 | if (adapter->ixgbe_ieee_pfc) | |
3338 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
3339 | ||
3340 | /* | |
3341 | * We should set the drop enable bit if: | |
3342 | * SR-IOV is enabled | |
3343 | * or | |
3344 | * Number of Rx queues > 1 and flow control is disabled | |
3345 | * | |
3346 | * This allows us to avoid head of line blocking for security | |
3347 | * and performance reasons. | |
3348 | */ | |
3349 | if (adapter->num_vfs || (adapter->num_rx_queues > 1 && | |
3350 | !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { | |
3351 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3352 | ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); | |
3353 | } else { | |
3354 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3355 | ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); | |
3356 | } | |
3357 | } | |
3358 | ||
e8e26350 | 3359 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 3360 | |
a6616b42 | 3361 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 3362 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 3363 | { |
45e9baa5 | 3364 | struct ixgbe_hw *hw = &adapter->hw; |
cc41ac7c | 3365 | u32 srrctl; |
bf29ee6c | 3366 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 3367 | |
45e9baa5 AD |
3368 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3369 | u16 mask = adapter->ring_feature[RING_F_RSS].mask; | |
cc41ac7c | 3370 | |
45e9baa5 AD |
3371 | /* |
3372 | * if VMDq is not active we must program one srrctl register | |
3373 | * per RSS queue since we have enabled RDRXCTL.MVMEN | |
3374 | */ | |
3375 | reg_idx &= mask; | |
3376 | } | |
cc41ac7c | 3377 | |
45e9baa5 AD |
3378 | /* configure header buffer length, needed for RSC */ |
3379 | srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; | |
afafd5b0 | 3380 | |
45e9baa5 | 3381 | /* configure the packet buffer length */ |
f800326d | 3382 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
45e9baa5 AD |
3383 | |
3384 | /* configure descriptor type */ | |
f800326d | 3385 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 3386 | |
45e9baa5 | 3387 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 3388 | } |
9a799d71 | 3389 | |
dfaf891d | 3390 | /** |
a897a2ad | 3391 | * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries |
dfaf891d VZ |
3392 | * @adapter: device handle |
3393 | * | |
3394 | * - 82598/82599/X540: 128 | |
3395 | * - X550(non-SRIOV mode): 512 | |
3396 | * - X550(SRIOV mode): 64 | |
3397 | */ | |
7f276efb | 3398 | u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter) |
dfaf891d VZ |
3399 | { |
3400 | if (adapter->hw.mac.type < ixgbe_mac_X550) | |
3401 | return 128; | |
3402 | else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3403 | return 64; | |
3404 | else | |
3405 | return 512; | |
3406 | } | |
3407 | ||
3408 | /** | |
a897a2ad | 3409 | * ixgbe_store_reta - Write the RETA table to HW |
dfaf891d VZ |
3410 | * @adapter: device handle |
3411 | * | |
3412 | * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. | |
3413 | */ | |
1c7cf078 | 3414 | void ixgbe_store_reta(struct ixgbe_adapter *adapter) |
0cefafad | 3415 | { |
dfaf891d | 3416 | u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); |
05abb126 | 3417 | struct ixgbe_hw *hw = &adapter->hw; |
d1b849b9 | 3418 | u32 reta = 0; |
dfaf891d VZ |
3419 | u32 indices_multi; |
3420 | u8 *indir_tbl = adapter->rss_indir_tbl; | |
05abb126 | 3421 | |
0f9b232b | 3422 | /* Fill out the redirection table as follows: |
dfaf891d VZ |
3423 | * - 82598: 8 bit wide entries containing pair of 4 bit RSS |
3424 | * indices. | |
3425 | * - 82599/X540: 8 bit wide entries containing 4 bit RSS index | |
3426 | * - X550: 8 bit wide entries containing 6 bit RSS index | |
0f9b232b DS |
3427 | */ |
3428 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3429 | indices_multi = 0x11; | |
3430 | else | |
3431 | indices_multi = 0x1; | |
3432 | ||
dfaf891d VZ |
3433 | /* Write redirection table to HW */ |
3434 | for (i = 0; i < reta_entries; i++) { | |
3435 | reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8; | |
0f9b232b DS |
3436 | if ((i & 3) == 3) { |
3437 | if (i < 128) | |
3438 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
3439 | else | |
3440 | IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32), | |
3441 | reta); | |
dfaf891d | 3442 | reta = 0; |
0f9b232b DS |
3443 | } |
3444 | } | |
3445 | } | |
3446 | ||
dfaf891d | 3447 | /** |
a897a2ad | 3448 | * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode) |
dfaf891d VZ |
3449 | * @adapter: device handle |
3450 | * | |
3451 | * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW. | |
3452 | */ | |
3453 | static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter) | |
0f9b232b | 3454 | { |
dfaf891d | 3455 | u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter); |
0f9b232b DS |
3456 | struct ixgbe_hw *hw = &adapter->hw; |
3457 | u32 vfreta = 0; | |
dfaf891d VZ |
3458 | unsigned int pf_pool = adapter->num_vfs; |
3459 | ||
3460 | /* Write redirection table to HW */ | |
3461 | for (i = 0; i < reta_entries; i++) { | |
3462 | vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8; | |
3463 | if ((i & 3) == 3) { | |
3464 | IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool), | |
3465 | vfreta); | |
3466 | vfreta = 0; | |
3467 | } | |
3468 | } | |
3469 | } | |
3470 | ||
3471 | static void ixgbe_setup_reta(struct ixgbe_adapter *adapter) | |
3472 | { | |
3473 | struct ixgbe_hw *hw = &adapter->hw; | |
3474 | u32 i, j; | |
3475 | u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); | |
3476 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; | |
3477 | ||
3478 | /* Program table for at least 2 queues w/ SR-IOV so that VFs can | |
3479 | * make full use of any rings they may have. We will use the | |
3480 | * PSRTYPE register to control how many rings we use within the PF. | |
3481 | */ | |
3482 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2)) | |
3483 | rss_i = 2; | |
3484 | ||
3485 | /* Fill out hash function seeds */ | |
3486 | for (i = 0; i < 10; i++) | |
3487 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]); | |
3488 | ||
3489 | /* Fill out redirection table */ | |
3490 | memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl)); | |
3491 | ||
3492 | for (i = 0, j = 0; i < reta_entries; i++, j++) { | |
3493 | if (j == rss_i) | |
3494 | j = 0; | |
3495 | ||
3496 | adapter->rss_indir_tbl[i] = j; | |
3497 | } | |
3498 | ||
3499 | ixgbe_store_reta(adapter); | |
3500 | } | |
3501 | ||
3502 | static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter) | |
3503 | { | |
3504 | struct ixgbe_hw *hw = &adapter->hw; | |
0f9b232b DS |
3505 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices; |
3506 | unsigned int pf_pool = adapter->num_vfs; | |
3507 | int i, j; | |
3508 | ||
3509 | /* Fill out hash function seeds */ | |
3510 | for (i = 0; i < 10; i++) | |
dfaf891d VZ |
3511 | IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool), |
3512 | adapter->rss_key[i]); | |
0f9b232b DS |
3513 | |
3514 | /* Fill out the redirection table */ | |
3515 | for (i = 0, j = 0; i < 64; i++, j++) { | |
671c0adb | 3516 | if (j == rss_i) |
05abb126 | 3517 | j = 0; |
dfaf891d VZ |
3518 | |
3519 | adapter->rss_indir_tbl[i] = j; | |
05abb126 | 3520 | } |
dfaf891d VZ |
3521 | |
3522 | ixgbe_store_vfreta(adapter); | |
d1b849b9 DS |
3523 | } |
3524 | ||
3525 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) | |
3526 | { | |
3527 | struct ixgbe_hw *hw = &adapter->hw; | |
0f9b232b | 3528 | u32 mrqc = 0, rss_field = 0, vfmrqc = 0; |
d1b849b9 | 3529 | u32 rxcsum; |
0cefafad | 3530 | |
05abb126 AD |
3531 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
3532 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
3533 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
3534 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
3535 | ||
671c0adb | 3536 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
fbe7ca7f | 3537 | if (adapter->ring_feature[RING_F_RSS].mask) |
671c0adb | 3538 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 | 3539 | } else { |
671c0adb AD |
3540 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
3541 | ||
3542 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3543 | if (tcs > 4) | |
3544 | mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */ | |
3545 | else if (tcs > 1) | |
3546 | mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */ | |
3547 | else if (adapter->ring_feature[RING_F_RSS].indices == 4) | |
3548 | mrqc = IXGBE_MRQC_VMDQRSS32EN; | |
8b1c0b24 | 3549 | else |
671c0adb AD |
3550 | mrqc = IXGBE_MRQC_VMDQRSS64EN; |
3551 | } else { | |
3552 | if (tcs > 4) | |
8b1c0b24 | 3553 | mrqc = IXGBE_MRQC_RTRSS8TCEN; |
671c0adb AD |
3554 | else if (tcs > 1) |
3555 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
3556 | else | |
3557 | mrqc = IXGBE_MRQC_RSSEN; | |
8b1c0b24 | 3558 | } |
0cefafad JB |
3559 | } |
3560 | ||
05abb126 | 3561 | /* Perform hash on these packet types */ |
d1b849b9 DS |
3562 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
3563 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | | |
3564 | IXGBE_MRQC_RSS_FIELD_IPV6 | | |
3565 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
05abb126 | 3566 | |
ef6afc0c | 3567 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
d1b849b9 | 3568 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; |
ef6afc0c | 3569 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) |
d1b849b9 | 3570 | rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; |
ef6afc0c | 3571 | |
dfaf891d | 3572 | netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key)); |
0f9b232b DS |
3573 | if ((hw->mac.type >= ixgbe_mac_X550) && |
3574 | (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) { | |
3575 | unsigned int pf_pool = adapter->num_vfs; | |
3576 | ||
3577 | /* Enable VF RSS mode */ | |
3578 | mrqc |= IXGBE_MRQC_MULTIPLE_RSS; | |
3579 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
3580 | ||
3581 | /* Setup RSS through the VF registers */ | |
dfaf891d | 3582 | ixgbe_setup_vfreta(adapter); |
0f9b232b DS |
3583 | vfmrqc = IXGBE_MRQC_RSSEN; |
3584 | vfmrqc |= rss_field; | |
3585 | IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc); | |
3586 | } else { | |
dfaf891d | 3587 | ixgbe_setup_reta(adapter); |
0f9b232b DS |
3588 | mrqc |= rss_field; |
3589 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
3590 | } | |
0cefafad JB |
3591 | } |
3592 | ||
bb5a9ad2 NS |
3593 | /** |
3594 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
3595 | * @adapter: address of board private structure | |
3596 | * @index: index of ring to set | |
bb5a9ad2 | 3597 | **/ |
082757af | 3598 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 3599 | struct ixgbe_ring *ring) |
bb5a9ad2 | 3600 | { |
bb5a9ad2 | 3601 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 3602 | u32 rscctrl; |
bf29ee6c | 3603 | u8 reg_idx = ring->reg_idx; |
7367096a | 3604 | |
7d637bcc | 3605 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 3606 | return; |
bb5a9ad2 | 3607 | |
7367096a | 3608 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
3609 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
3610 | /* | |
3611 | * we must limit the number of descriptors so that the | |
3612 | * total size of max desc * buf_len is not greater | |
642c680e | 3613 | * than 65536 |
bb5a9ad2 | 3614 | */ |
f800326d | 3615 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; |
7367096a | 3616 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
3617 | } |
3618 | ||
9e10e045 AD |
3619 | #define IXGBE_MAX_RX_DESC_POLL 10 |
3620 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
3621 | struct ixgbe_ring *ring) | |
3622 | { | |
3623 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
3624 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
3625 | u32 rxdctl; | |
bf29ee6c | 3626 | u8 reg_idx = ring->reg_idx; |
9e10e045 | 3627 | |
b0483c8f MR |
3628 | if (ixgbe_removed(hw->hw_addr)) |
3629 | return; | |
9e10e045 AD |
3630 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ |
3631 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3632 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3633 | return; | |
3634 | ||
3635 | do { | |
032b4325 | 3636 | usleep_range(1000, 2000); |
9e10e045 AD |
3637 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3638 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3639 | ||
3640 | if (!wait_loop) { | |
3641 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3642 | "the polling period\n", reg_idx); | |
3643 | } | |
3644 | } | |
3645 | ||
2d39d576 YZ |
3646 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3647 | struct ixgbe_ring *ring) | |
3648 | { | |
3649 | struct ixgbe_hw *hw = &adapter->hw; | |
3650 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3651 | u32 rxdctl; | |
3652 | u8 reg_idx = ring->reg_idx; | |
3653 | ||
b0483c8f MR |
3654 | if (ixgbe_removed(hw->hw_addr)) |
3655 | return; | |
2d39d576 YZ |
3656 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3657 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3658 | ||
3659 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3660 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3661 | ||
3662 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3663 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3664 | return; | |
3665 | ||
3666 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3667 | do { | |
3668 | udelay(10); | |
3669 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3670 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3671 | ||
3672 | if (!wait_loop) { | |
3673 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3674 | "the polling period\n", reg_idx); | |
3675 | } | |
3676 | } | |
3677 | ||
84418e3b AD |
3678 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3679 | struct ixgbe_ring *ring) | |
acd37177 AD |
3680 | { |
3681 | struct ixgbe_hw *hw = &adapter->hw; | |
3682 | u64 rdba = ring->dma; | |
9e10e045 | 3683 | u32 rxdctl; |
bf29ee6c | 3684 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3685 | |
9e10e045 AD |
3686 | /* disable queue to avoid issues while updating state */ |
3687 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3688 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3689 | |
acd37177 AD |
3690 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3691 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3692 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3693 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
8b75451b NP |
3694 | /* Force flushing of IXGBE_RDLEN to prevent MDD */ |
3695 | IXGBE_WRITE_FLUSH(hw); | |
3696 | ||
acd37177 AD |
3697 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); |
3698 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
2a1a091c | 3699 | ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3700 | |
3701 | ixgbe_configure_srrctl(adapter, ring); | |
3702 | ixgbe_configure_rscctl(adapter, ring); | |
3703 | ||
3704 | if (hw->mac.type == ixgbe_mac_82598EB) { | |
3705 | /* | |
3706 | * enable cache line friendly hardware writes: | |
3707 | * PTHRESH=32 descriptors (half the internal cache), | |
3708 | * this also removes ugly rx_no_buffer_count increment | |
3709 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3710 | * WTHRESH=8 burst writeback up to two cache lines | |
3711 | */ | |
3712 | rxdctl &= ~0x3FFFFF; | |
3713 | rxdctl |= 0x080420; | |
3714 | } | |
3715 | ||
3716 | /* enable receive descriptor ring */ | |
3717 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3718 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3719 | ||
3720 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3721 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3722 | } |
3723 | ||
48654521 AD |
3724 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3725 | { | |
3726 | struct ixgbe_hw *hw = &adapter->hw; | |
fbe7ca7f | 3727 | int rss_i = adapter->ring_feature[RING_F_RSS].indices; |
2a47fa45 | 3728 | u16 pool; |
48654521 AD |
3729 | |
3730 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3731 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3732 | IXGBE_PSRTYPE_UDPHDR | |
3733 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3734 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3735 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3736 | |
3737 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3738 | return; | |
3739 | ||
fbe7ca7f | 3740 | if (rss_i > 3) |
b4f47a48 | 3741 | psrtype |= 2u << 29; |
fbe7ca7f | 3742 | else if (rss_i > 1) |
b4f47a48 | 3743 | psrtype |= 1u << 29; |
48654521 | 3744 | |
2a47fa45 JF |
3745 | for_each_set_bit(pool, &adapter->fwd_bitmask, 32) |
3746 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); | |
48654521 AD |
3747 | } |
3748 | ||
f5b4a52e AD |
3749 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3750 | { | |
3751 | struct ixgbe_hw *hw = &adapter->hw; | |
f5b4a52e | 3752 | u32 reg_offset, vf_shift; |
435b19f6 | 3753 | u32 gcr_ext, vmdctl; |
de4c7f65 | 3754 | int i; |
f5b4a52e AD |
3755 | |
3756 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3757 | return; | |
3758 | ||
3759 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
435b19f6 AD |
3760 | vmdctl |= IXGBE_VMD_CTL_VMDQ_EN; |
3761 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
1d9c0bfd | 3762 | vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT; |
435b19f6 AD |
3763 | vmdctl |= IXGBE_VT_CTL_REPLEN; |
3764 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
f5b4a52e | 3765 | |
1d9c0bfd AD |
3766 | vf_shift = VMDQ_P(0) % 32; |
3767 | reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0; | |
f5b4a52e AD |
3768 | |
3769 | /* Enable only the PF's pool for Tx/Rx */ | |
11f2b494 | 3770 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift)); |
435b19f6 | 3771 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1); |
11f2b494 | 3772 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift)); |
435b19f6 | 3773 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1); |
aa2bacb6 | 3774 | if (adapter->bridge_mode == BRIDGE_MODE_VEB) |
9b735984 | 3775 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); |
f5b4a52e AD |
3776 | |
3777 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
1d9c0bfd | 3778 | hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0)); |
f5b4a52e | 3779 | |
16369564 AD |
3780 | /* clear VLAN promisc flag so VFTA will be updated if necessary */ |
3781 | adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; | |
3782 | ||
f5b4a52e AD |
3783 | /* |
3784 | * Set up VF register offsets for selected VT Mode, | |
3785 | * i.e. 32 or 64 VFs for SR-IOV | |
3786 | */ | |
73079ea0 AD |
3787 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { |
3788 | case IXGBE_82599_VMDQ_8Q_MASK: | |
3789 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_16; | |
3790 | break; | |
3791 | case IXGBE_82599_VMDQ_4Q_MASK: | |
3792 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_32; | |
3793 | break; | |
3794 | default: | |
3795 | gcr_ext = IXGBE_GCR_EXT_VT_MODE_64; | |
3796 | break; | |
3797 | } | |
3798 | ||
f5b4a52e AD |
3799 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); |
3800 | ||
de4c7f65 | 3801 | for (i = 0; i < adapter->num_vfs; i++) { |
77f192af ET |
3802 | /* configure spoof checking */ |
3803 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, | |
3804 | adapter->vfinfo[i].spoofchk_enabled); | |
e65ce0d3 VZ |
3805 | |
3806 | /* Enable/Disable RSS query feature */ | |
3807 | ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i, | |
3808 | adapter->vfinfo[i].rss_query_enabled); | |
de4c7f65 | 3809 | } |
f5b4a52e AD |
3810 | } |
3811 | ||
477de6ed | 3812 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3813 | { |
9a799d71 AK |
3814 | struct ixgbe_hw *hw = &adapter->hw; |
3815 | struct net_device *netdev = adapter->netdev; | |
3816 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3817 | struct ixgbe_ring *rx_ring; |
3818 | int i; | |
3819 | u32 mhadd, hlreg0; | |
48654521 | 3820 | |
63f39bd1 | 3821 | #ifdef IXGBE_FCOE |
477de6ed AD |
3822 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3823 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3824 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3825 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3826 | |
477de6ed | 3827 | #endif /* IXGBE_FCOE */ |
872844dd AD |
3828 | |
3829 | /* adjust max frame to be at least the size of a standard frame */ | |
3830 | if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) | |
3831 | max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); | |
3832 | ||
477de6ed AD |
3833 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); |
3834 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3835 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3836 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3837 | ||
3838 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3839 | } | |
3840 | ||
3841 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); | |
3842 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3843 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3844 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3845 | |
0cefafad JB |
3846 | /* |
3847 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3848 | * the Base and Length of the Rx Descriptor Ring | |
3849 | */ | |
9a799d71 | 3850 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3851 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3852 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3853 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3854 | else |
7d637bcc | 3855 | clear_ring_rsc_enabled(rx_ring); |
477de6ed | 3856 | } |
477de6ed AD |
3857 | } |
3858 | ||
7367096a AD |
3859 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3860 | { | |
3861 | struct ixgbe_hw *hw = &adapter->hw; | |
3862 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3863 | ||
3864 | switch (hw->mac.type) { | |
3865 | case ixgbe_mac_82598EB: | |
3866 | /* | |
3867 | * For VMDq support of different descriptor types or | |
3868 | * buffer sizes through the use of multiple SRRCTL | |
3869 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3870 | * | |
3871 | * also, the manual doesn't mention it clearly but DCA hints | |
3872 | * will only use queue 0's tags unless this bit is set. Side | |
3873 | * effects of setting this bit are only that SRRCTL must be | |
3874 | * fully programmed [0..15] | |
3875 | */ | |
3876 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3877 | break; | |
052a1a72 MR |
3878 | case ixgbe_mac_X550: |
3879 | case ixgbe_mac_X550EM_x: | |
49425dfc | 3880 | case ixgbe_mac_x550em_a: |
f961ddae MR |
3881 | if (adapter->num_vfs) |
3882 | rdrxctl |= IXGBE_RDRXCTL_PSP; | |
3883 | /* fall through for older HW */ | |
7367096a | 3884 | case ixgbe_mac_82599EB: |
b93a2226 | 3885 | case ixgbe_mac_X540: |
7367096a AD |
3886 | /* Disable RSC for ACK packets */ |
3887 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3888 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3889 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3890 | /* hardware requires some bits to be set by default */ | |
3891 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3892 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3893 | break; | |
3894 | default: | |
3895 | /* We should do nothing since we don't know this hardware */ | |
3896 | return; | |
3897 | } | |
3898 | ||
3899 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3900 | } | |
3901 | ||
477de6ed AD |
3902 | /** |
3903 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3904 | * @adapter: board private structure | |
3905 | * | |
3906 | * Configure the Rx unit of the MAC after a reset. | |
3907 | **/ | |
3908 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3909 | { | |
3910 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed | 3911 | int i; |
6dcc28b9 | 3912 | u32 rxctrl, rfctl; |
477de6ed AD |
3913 | |
3914 | /* disable receives while setting up the descriptors */ | |
1f9ac57c | 3915 | hw->mac.ops.disable_rx(hw); |
477de6ed AD |
3916 | |
3917 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3918 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3919 | |
6dcc28b9 JK |
3920 | /* RSC Setup */ |
3921 | rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL); | |
3922 | rfctl &= ~IXGBE_RFCTL_RSC_DIS; | |
3923 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
3924 | rfctl |= IXGBE_RFCTL_RSC_DIS; | |
3925 | IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl); | |
3926 | ||
9e10e045 | 3927 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3928 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3929 | |
477de6ed AD |
3930 | /* set_rx_buffer_len must be called before ring initialization */ |
3931 | ixgbe_set_rx_buffer_len(adapter); | |
3932 | ||
3933 | /* | |
3934 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3935 | * the Base and Length of the Rx Descriptor Ring | |
3936 | */ | |
9e10e045 AD |
3937 | for (i = 0; i < adapter->num_rx_queues; i++) |
3938 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3939 | |
1f9ac57c | 3940 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
9e10e045 AD |
3941 | /* disable drop enable for 82598 parts */ |
3942 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3943 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3944 | ||
3945 | /* enable all receives */ | |
3946 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3947 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3948 | } |
3949 | ||
80d5c368 PM |
3950 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, |
3951 | __be16 proto, u16 vid) | |
068c89b0 DS |
3952 | { |
3953 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3954 | struct ixgbe_hw *hw = &adapter->hw; | |
3955 | ||
3956 | /* add VID to filter table */ | |
18be4fce AD |
3957 | if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) |
3958 | hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid); | |
3959 | ||
f62bbb5e | 3960 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3961 | |
3962 | return 0; | |
068c89b0 DS |
3963 | } |
3964 | ||
e1d0a2af AD |
3965 | static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan) |
3966 | { | |
3967 | u32 vlvf; | |
3968 | int idx; | |
3969 | ||
3970 | /* short cut the special case */ | |
3971 | if (vlan == 0) | |
3972 | return 0; | |
3973 | ||
3974 | /* Search for the vlan id in the VLVF entries */ | |
3975 | for (idx = IXGBE_VLVF_ENTRIES; --idx;) { | |
3976 | vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx)); | |
3977 | if ((vlvf & VLAN_VID_MASK) == vlan) | |
3978 | break; | |
3979 | } | |
3980 | ||
3981 | return idx; | |
3982 | } | |
3983 | ||
3984 | void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid) | |
3985 | { | |
3986 | struct ixgbe_hw *hw = &adapter->hw; | |
3987 | u32 bits, word; | |
3988 | int idx; | |
3989 | ||
3990 | idx = ixgbe_find_vlvf_entry(hw, vid); | |
3991 | if (!idx) | |
3992 | return; | |
3993 | ||
3994 | /* See if any other pools are set for this VLAN filter | |
3995 | * entry other than the PF. | |
3996 | */ | |
3997 | word = idx * 2 + (VMDQ_P(0) / 32); | |
b4f47a48 | 3998 | bits = ~BIT(VMDQ_P(0) % 32); |
e1d0a2af AD |
3999 | bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); |
4000 | ||
4001 | /* Disable the filter so this falls into the default pool. */ | |
4002 | if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) { | |
4003 | if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) | |
4004 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0); | |
4005 | IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0); | |
4006 | } | |
4007 | } | |
4008 | ||
80d5c368 PM |
4009 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, |
4010 | __be16 proto, u16 vid) | |
068c89b0 DS |
4011 | { |
4012 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4013 | struct ixgbe_hw *hw = &adapter->hw; | |
4014 | ||
068c89b0 | 4015 | /* remove VID from filter table */ |
18be4fce | 4016 | if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) |
e1d0a2af AD |
4017 | hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true); |
4018 | ||
f62bbb5e | 4019 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
4020 | |
4021 | return 0; | |
068c89b0 DS |
4022 | } |
4023 | ||
f62bbb5e JG |
4024 | /** |
4025 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
4026 | * @adapter: driver data | |
4027 | */ | |
4028 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
4029 | { | |
4030 | struct ixgbe_hw *hw = &adapter->hw; | |
4031 | u32 vlnctrl; | |
5f6c0181 JB |
4032 | int i, j; |
4033 | ||
4034 | switch (hw->mac.type) { | |
4035 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
4036 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
4037 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
4038 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
4039 | break; | |
4040 | case ixgbe_mac_82599EB: | |
b93a2226 | 4041 | case ixgbe_mac_X540: |
9a75a1ac DS |
4042 | case ixgbe_mac_X550: |
4043 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4044 | case ixgbe_mac_x550em_a: |
5f6c0181 | 4045 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2a47fa45 JF |
4046 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4047 | ||
4048 | if (ring->l2_accel_priv) | |
4049 | continue; | |
4050 | j = ring->reg_idx; | |
5f6c0181 JB |
4051 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
4052 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
4053 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
4054 | } | |
4055 | break; | |
4056 | default: | |
4057 | break; | |
4058 | } | |
4059 | } | |
4060 | ||
4061 | /** | |
f62bbb5e | 4062 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
4063 | * @adapter: driver data |
4064 | */ | |
f62bbb5e | 4065 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
4066 | { |
4067 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 4068 | u32 vlnctrl; |
5f6c0181 JB |
4069 | int i, j; |
4070 | ||
4071 | switch (hw->mac.type) { | |
4072 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
4073 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
4074 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
4075 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
4076 | break; | |
4077 | case ixgbe_mac_82599EB: | |
b93a2226 | 4078 | case ixgbe_mac_X540: |
9a75a1ac DS |
4079 | case ixgbe_mac_X550: |
4080 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4081 | case ixgbe_mac_x550em_a: |
5f6c0181 | 4082 | for (i = 0; i < adapter->num_rx_queues; i++) { |
2a47fa45 JF |
4083 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4084 | ||
4085 | if (ring->l2_accel_priv) | |
4086 | continue; | |
4087 | j = ring->reg_idx; | |
5f6c0181 JB |
4088 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); |
4089 | vlnctrl |= IXGBE_RXDCTL_VME; | |
4090 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
4091 | } | |
4092 | break; | |
4093 | default: | |
4094 | break; | |
4095 | } | |
4096 | } | |
4097 | ||
16369564 AD |
4098 | static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter) |
4099 | { | |
4100 | struct ixgbe_hw *hw = &adapter->hw; | |
4101 | u32 vlnctrl, i; | |
4102 | ||
4103 | switch (hw->mac.type) { | |
4104 | case ixgbe_mac_82599EB: | |
4105 | case ixgbe_mac_X540: | |
4106 | case ixgbe_mac_X550: | |
4107 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4108 | case ixgbe_mac_x550em_a: |
16369564 AD |
4109 | default: |
4110 | if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) | |
4111 | break; | |
4112 | /* fall through */ | |
4113 | case ixgbe_mac_82598EB: | |
4114 | /* legacy case, we can just disable VLAN filtering */ | |
4115 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
4116 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
4117 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
4118 | return; | |
4119 | } | |
4120 | ||
4121 | /* We are already in VLAN promisc, nothing to do */ | |
4122 | if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC) | |
4123 | return; | |
4124 | ||
4125 | /* Set flag so we don't redo unnecessary work */ | |
4126 | adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC; | |
4127 | ||
4128 | /* Add PF to all active pools */ | |
4129 | for (i = IXGBE_VLVF_ENTRIES; --i;) { | |
4130 | u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32); | |
4131 | u32 vlvfb = IXGBE_READ_REG(hw, reg_offset); | |
4132 | ||
b4f47a48 | 4133 | vlvfb |= BIT(VMDQ_P(0) % 32); |
16369564 AD |
4134 | IXGBE_WRITE_REG(hw, reg_offset, vlvfb); |
4135 | } | |
4136 | ||
4137 | /* Set all bits in the VLAN filter table array */ | |
4138 | for (i = hw->mac.vft_size; i--;) | |
4139 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U); | |
4140 | } | |
4141 | ||
4142 | #define VFTA_BLOCK_SIZE 8 | |
4143 | static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset) | |
4144 | { | |
4145 | struct ixgbe_hw *hw = &adapter->hw; | |
4146 | u32 vfta[VFTA_BLOCK_SIZE] = { 0 }; | |
4147 | u32 vid_start = vfta_offset * 32; | |
4148 | u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32); | |
4149 | u32 i, vid, word, bits; | |
4150 | ||
4151 | for (i = IXGBE_VLVF_ENTRIES; --i;) { | |
4152 | u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i)); | |
4153 | ||
4154 | /* pull VLAN ID from VLVF */ | |
4155 | vid = vlvf & VLAN_VID_MASK; | |
4156 | ||
4157 | /* only concern outselves with a certain range */ | |
4158 | if (vid < vid_start || vid >= vid_end) | |
4159 | continue; | |
4160 | ||
4161 | if (vlvf) { | |
4162 | /* record VLAN ID in VFTA */ | |
b4f47a48 | 4163 | vfta[(vid - vid_start) / 32] |= BIT(vid % 32); |
16369564 AD |
4164 | |
4165 | /* if PF is part of this then continue */ | |
4166 | if (test_bit(vid, adapter->active_vlans)) | |
4167 | continue; | |
4168 | } | |
4169 | ||
4170 | /* remove PF from the pool */ | |
4171 | word = i * 2 + VMDQ_P(0) / 32; | |
b4f47a48 | 4172 | bits = ~BIT(VMDQ_P(0) % 32); |
16369564 AD |
4173 | bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word)); |
4174 | IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits); | |
4175 | } | |
4176 | ||
4177 | /* extract values from active_vlans and write back to VFTA */ | |
4178 | for (i = VFTA_BLOCK_SIZE; i--;) { | |
4179 | vid = (vfta_offset + i) * 32; | |
4180 | word = vid / BITS_PER_LONG; | |
4181 | bits = vid % BITS_PER_LONG; | |
4182 | ||
4183 | vfta[i] |= adapter->active_vlans[word] >> bits; | |
4184 | ||
4185 | IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]); | |
4186 | } | |
4187 | } | |
4188 | ||
4189 | static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter) | |
4190 | { | |
4191 | struct ixgbe_hw *hw = &adapter->hw; | |
4192 | u32 vlnctrl, i; | |
4193 | ||
4194 | switch (hw->mac.type) { | |
4195 | case ixgbe_mac_82599EB: | |
4196 | case ixgbe_mac_X540: | |
4197 | case ixgbe_mac_X550: | |
4198 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4199 | case ixgbe_mac_x550em_a: |
16369564 AD |
4200 | default: |
4201 | if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) | |
4202 | break; | |
4203 | /* fall through */ | |
4204 | case ixgbe_mac_82598EB: | |
4205 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
4206 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
4207 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
4208 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
4209 | return; | |
4210 | } | |
4211 | ||
4212 | /* We are not in VLAN promisc, nothing to do */ | |
4213 | if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)) | |
4214 | return; | |
4215 | ||
4216 | /* Set flag so we don't redo unnecessary work */ | |
4217 | adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC; | |
4218 | ||
4219 | for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE) | |
4220 | ixgbe_scrub_vfta(adapter, i); | |
4221 | } | |
4222 | ||
9a799d71 AK |
4223 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
4224 | { | |
06bb1c39 | 4225 | u16 vid = 1; |
9a799d71 | 4226 | |
80d5c368 | 4227 | ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); |
f62bbb5e | 4228 | |
06bb1c39 | 4229 | for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID) |
80d5c368 | 4230 | ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); |
9a799d71 AK |
4231 | } |
4232 | ||
b335e75b JK |
4233 | /** |
4234 | * ixgbe_write_mc_addr_list - write multicast addresses to MTA | |
4235 | * @netdev: network interface device structure | |
4236 | * | |
4237 | * Writes multicast address list to the MTA hash table. | |
4238 | * Returns: -ENOMEM on failure | |
4239 | * 0 on no addresses written | |
4240 | * X on writing X addresses to MTA | |
4241 | **/ | |
4242 | static int ixgbe_write_mc_addr_list(struct net_device *netdev) | |
4243 | { | |
4244 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4245 | struct ixgbe_hw *hw = &adapter->hw; | |
4246 | ||
4247 | if (!netif_running(netdev)) | |
4248 | return 0; | |
4249 | ||
4250 | if (hw->mac.ops.update_mc_addr_list) | |
4251 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
4252 | else | |
4253 | return -ENOMEM; | |
4254 | ||
4255 | #ifdef CONFIG_PCI_IOV | |
5d7daa35 | 4256 | ixgbe_restore_vf_multicasts(adapter); |
b335e75b JK |
4257 | #endif |
4258 | ||
4259 | return netdev_mc_count(netdev); | |
4260 | } | |
4261 | ||
5d7daa35 JK |
4262 | #ifdef CONFIG_PCI_IOV |
4263 | void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter) | |
4264 | { | |
c9f53e63 | 4265 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4266 | struct ixgbe_hw *hw = &adapter->hw; |
4267 | int i; | |
c9f53e63 AD |
4268 | |
4269 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { | |
4270 | mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; | |
4271 | ||
4272 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
4273 | hw->mac.ops.set_rar(hw, i, | |
4274 | mac_table->addr, | |
4275 | mac_table->pool, | |
5d7daa35 JK |
4276 | IXGBE_RAH_AV); |
4277 | else | |
4278 | hw->mac.ops.clear_rar(hw, i); | |
5d7daa35 JK |
4279 | } |
4280 | } | |
5d7daa35 | 4281 | |
c9f53e63 | 4282 | #endif |
5d7daa35 JK |
4283 | static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter) |
4284 | { | |
c9f53e63 | 4285 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4286 | struct ixgbe_hw *hw = &adapter->hw; |
4287 | int i; | |
5d7daa35 | 4288 | |
c9f53e63 AD |
4289 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4290 | if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED)) | |
4291 | continue; | |
4292 | ||
4293 | mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED; | |
4294 | ||
4295 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
4296 | hw->mac.ops.set_rar(hw, i, | |
4297 | mac_table->addr, | |
4298 | mac_table->pool, | |
4299 | IXGBE_RAH_AV); | |
4300 | else | |
4301 | hw->mac.ops.clear_rar(hw, i); | |
5d7daa35 JK |
4302 | } |
4303 | } | |
4304 | ||
4305 | static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter) | |
4306 | { | |
c9f53e63 | 4307 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 | 4308 | struct ixgbe_hw *hw = &adapter->hw; |
c9f53e63 | 4309 | int i; |
5d7daa35 | 4310 | |
c9f53e63 AD |
4311 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4312 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED; | |
4313 | mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; | |
5d7daa35 | 4314 | } |
c9f53e63 | 4315 | |
5d7daa35 JK |
4316 | ixgbe_sync_mac_table(adapter); |
4317 | } | |
4318 | ||
c9f53e63 | 4319 | static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool) |
5d7daa35 | 4320 | { |
c9f53e63 | 4321 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4322 | struct ixgbe_hw *hw = &adapter->hw; |
4323 | int i, count = 0; | |
4324 | ||
c9f53e63 AD |
4325 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4326 | /* do not count default RAR as available */ | |
4327 | if (mac_table->state & IXGBE_MAC_STATE_DEFAULT) | |
4328 | continue; | |
4329 | ||
4330 | /* only count unused and addresses that belong to us */ | |
4331 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) { | |
4332 | if (mac_table->pool != pool) | |
4333 | continue; | |
4334 | } | |
4335 | ||
4336 | count++; | |
5d7daa35 | 4337 | } |
c9f53e63 | 4338 | |
5d7daa35 JK |
4339 | return count; |
4340 | } | |
4341 | ||
4342 | /* this function destroys the first RAR entry */ | |
c9f53e63 | 4343 | static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter) |
5d7daa35 | 4344 | { |
c9f53e63 | 4345 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4346 | struct ixgbe_hw *hw = &adapter->hw; |
4347 | ||
c9f53e63 AD |
4348 | memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN); |
4349 | mac_table->pool = VMDQ_P(0); | |
4350 | ||
4351 | mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE; | |
4352 | ||
4353 | hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool, | |
5d7daa35 JK |
4354 | IXGBE_RAH_AV); |
4355 | } | |
4356 | ||
c9f53e63 AD |
4357 | int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, |
4358 | const u8 *addr, u16 pool) | |
5d7daa35 | 4359 | { |
c9f53e63 | 4360 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 JK |
4361 | struct ixgbe_hw *hw = &adapter->hw; |
4362 | int i; | |
4363 | ||
4364 | if (is_zero_ether_addr(addr)) | |
4365 | return -EINVAL; | |
4366 | ||
c9f53e63 AD |
4367 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { |
4368 | if (mac_table->state & IXGBE_MAC_STATE_IN_USE) | |
5d7daa35 | 4369 | continue; |
c9f53e63 AD |
4370 | |
4371 | ether_addr_copy(mac_table->addr, addr); | |
4372 | mac_table->pool = pool; | |
4373 | ||
4374 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED | | |
4375 | IXGBE_MAC_STATE_IN_USE; | |
4376 | ||
5d7daa35 | 4377 | ixgbe_sync_mac_table(adapter); |
c9f53e63 | 4378 | |
5d7daa35 JK |
4379 | return i; |
4380 | } | |
c9f53e63 | 4381 | |
5d7daa35 JK |
4382 | return -ENOMEM; |
4383 | } | |
4384 | ||
c9f53e63 AD |
4385 | int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, |
4386 | const u8 *addr, u16 pool) | |
5d7daa35 | 4387 | { |
c9f53e63 | 4388 | struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0]; |
5d7daa35 | 4389 | struct ixgbe_hw *hw = &adapter->hw; |
c9f53e63 | 4390 | int i; |
5d7daa35 JK |
4391 | |
4392 | if (is_zero_ether_addr(addr)) | |
4393 | return -EINVAL; | |
4394 | ||
c9f53e63 AD |
4395 | /* search table for addr, if found clear IN_USE flag and sync */ |
4396 | for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) { | |
4397 | /* we can only delete an entry if it is in use */ | |
4398 | if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE)) | |
4399 | continue; | |
4400 | /* we only care about entries that belong to the given pool */ | |
4401 | if (mac_table->pool != pool) | |
4402 | continue; | |
4403 | /* we only care about a specific MAC address */ | |
4404 | if (!ether_addr_equal(addr, mac_table->addr)) | |
4405 | continue; | |
4406 | ||
4407 | mac_table->state |= IXGBE_MAC_STATE_MODIFIED; | |
4408 | mac_table->state &= ~IXGBE_MAC_STATE_IN_USE; | |
4409 | ||
4410 | ixgbe_sync_mac_table(adapter); | |
4411 | ||
4412 | return 0; | |
5d7daa35 | 4413 | } |
c9f53e63 | 4414 | |
5d7daa35 JK |
4415 | return -ENOMEM; |
4416 | } | |
2850062a AD |
4417 | /** |
4418 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
4419 | * @netdev: network interface device structure | |
4420 | * | |
4421 | * Writes unicast address list to the RAR table. | |
4422 | * Returns: -ENOMEM on failure/insufficient address space | |
4423 | * 0 on no addresses written | |
4424 | * X on writing X addresses to the RAR table | |
4425 | **/ | |
5d7daa35 | 4426 | static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn) |
2850062a AD |
4427 | { |
4428 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
2850062a AD |
4429 | int count = 0; |
4430 | ||
4431 | /* return ENOMEM indicating insufficient memory for addresses */ | |
c9f53e63 | 4432 | if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn)) |
2850062a AD |
4433 | return -ENOMEM; |
4434 | ||
95447461 | 4435 | if (!netdev_uc_empty(netdev)) { |
2850062a | 4436 | struct netdev_hw_addr *ha; |
2850062a | 4437 | netdev_for_each_uc_addr(ha, netdev) { |
5d7daa35 JK |
4438 | ixgbe_del_mac_filter(adapter, ha->addr, vfn); |
4439 | ixgbe_add_mac_filter(adapter, ha->addr, vfn); | |
2850062a AD |
4440 | count++; |
4441 | } | |
4442 | } | |
2850062a AD |
4443 | return count; |
4444 | } | |
4445 | ||
0f079d22 AD |
4446 | static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr) |
4447 | { | |
4448 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4449 | int ret; | |
4450 | ||
4451 | ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0)); | |
4452 | ||
4453 | return min_t(int, ret, 0); | |
4454 | } | |
4455 | ||
4456 | static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr) | |
4457 | { | |
4458 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4459 | ||
4460 | ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0)); | |
4461 | ||
4462 | return 0; | |
4463 | } | |
4464 | ||
9a799d71 | 4465 | /** |
2c5645cf | 4466 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
4467 | * @netdev: network interface device structure |
4468 | * | |
2c5645cf CL |
4469 | * The set_rx_method entry point is called whenever the unicast/multicast |
4470 | * address list or the network interface flags are updated. This routine is | |
4471 | * responsible for configuring the hardware for proper unicast, multicast and | |
4472 | * promiscuous mode. | |
9a799d71 | 4473 | **/ |
7f870475 | 4474 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
4475 | { |
4476 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4477 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a | 4478 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
0c5a6166 | 4479 | netdev_features_t features = netdev->features; |
2850062a | 4480 | int count; |
9a799d71 AK |
4481 | |
4482 | /* Check for Promiscuous and All Multicast modes */ | |
9a799d71 AK |
4483 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); |
4484 | ||
f5dc442b | 4485 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 4486 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
4487 | fctrl |= IXGBE_FCTRL_BAM; |
4488 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
4489 | fctrl |= IXGBE_FCTRL_PMCF; | |
4490 | ||
2850062a AD |
4491 | /* clear the bits we are changing the status of */ |
4492 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
9a799d71 | 4493 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 4494 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 4495 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
b335e75b | 4496 | vmolr |= IXGBE_VMOLR_MPE; |
0c5a6166 | 4497 | features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; |
9a799d71 | 4498 | } else { |
746b9f02 PM |
4499 | if (netdev->flags & IFF_ALLMULTI) { |
4500 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a | 4501 | vmolr |= IXGBE_VMOLR_MPE; |
746b9f02 | 4502 | } |
e433ea1f | 4503 | hw->addr_ctrl.user_set_promisc = false; |
9dcb373c JF |
4504 | } |
4505 | ||
4506 | /* | |
4507 | * Write addresses to available RAR registers, if there is not | |
4508 | * sufficient space to store all the addresses then enable | |
4509 | * unicast promiscuous mode | |
4510 | */ | |
0f079d22 | 4511 | if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) { |
9dcb373c JF |
4512 | fctrl |= IXGBE_FCTRL_UPE; |
4513 | vmolr |= IXGBE_VMOLR_ROPE; | |
9a799d71 AK |
4514 | } |
4515 | ||
cf78959c ET |
4516 | /* Write addresses to the MTA, if the attempt fails |
4517 | * then we should just turn on promiscuous mode so | |
4518 | * that we can at least receive multicast traffic | |
4519 | */ | |
b335e75b JK |
4520 | count = ixgbe_write_mc_addr_list(netdev); |
4521 | if (count < 0) { | |
4522 | fctrl |= IXGBE_FCTRL_MPE; | |
4523 | vmolr |= IXGBE_VMOLR_MPE; | |
4524 | } else if (count) { | |
4525 | vmolr |= IXGBE_VMOLR_ROMPE; | |
4526 | } | |
1d9c0bfd AD |
4527 | |
4528 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4529 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) & | |
2850062a AD |
4530 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | |
4531 | IXGBE_VMOLR_ROPE); | |
1d9c0bfd | 4532 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr); |
2850062a AD |
4533 | } |
4534 | ||
3f2d1c0f | 4535 | /* This is useful for sniffing bad packets. */ |
0c5a6166 | 4536 | if (features & NETIF_F_RXALL) { |
3f2d1c0f BG |
4537 | /* UPE and MPE will be handled by normal PROMISC logic |
4538 | * in e1000e_set_rx_mode */ | |
4539 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
4540 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
4541 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
4542 | ||
4543 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
4544 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
4545 | } | |
4546 | ||
2850062a | 4547 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e | 4548 | |
0c5a6166 | 4549 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
f62bbb5e JG |
4550 | ixgbe_vlan_strip_enable(adapter); |
4551 | else | |
4552 | ixgbe_vlan_strip_disable(adapter); | |
0c5a6166 AD |
4553 | |
4554 | if (features & NETIF_F_HW_VLAN_CTAG_FILTER) | |
4555 | ixgbe_vlan_promisc_disable(adapter); | |
4556 | else | |
4557 | ixgbe_vlan_promisc_enable(adapter); | |
9a799d71 AK |
4558 | } |
4559 | ||
021230d4 AV |
4560 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
4561 | { | |
4562 | int q_idx; | |
021230d4 | 4563 | |
5a85e737 ET |
4564 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { |
4565 | ixgbe_qv_init_lock(adapter->q_vector[q_idx]); | |
49c7ffbe | 4566 | napi_enable(&adapter->q_vector[q_idx]->napi); |
5a85e737 | 4567 | } |
021230d4 AV |
4568 | } |
4569 | ||
4570 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
4571 | { | |
4572 | int q_idx; | |
021230d4 | 4573 | |
5a85e737 | 4574 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) { |
49c7ffbe | 4575 | napi_disable(&adapter->q_vector[q_idx]->napi); |
27d9ce4f | 4576 | while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) { |
5a85e737 | 4577 | pr_info("QV %d locked\n", q_idx); |
27d9ce4f | 4578 | usleep_range(1000, 20000); |
5a85e737 ET |
4579 | } |
4580 | } | |
021230d4 AV |
4581 | } |
4582 | ||
67359c3c MR |
4583 | static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter) |
4584 | { | |
4585 | switch (adapter->hw.mac.type) { | |
4586 | case ixgbe_mac_X550: | |
4587 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4588 | case ixgbe_mac_x550em_a: |
67359c3c | 4589 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0); |
67359c3c | 4590 | adapter->vxlan_port = 0; |
67359c3c MR |
4591 | break; |
4592 | default: | |
4593 | break; | |
4594 | } | |
4595 | } | |
4596 | ||
7a6b6f51 | 4597 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c | 4598 | /** |
2f90b865 AD |
4599 | * ixgbe_configure_dcb - Configure DCB hardware |
4600 | * @adapter: ixgbe adapter struct | |
4601 | * | |
4602 | * This is called by the driver on open to configure the DCB hardware. | |
4603 | * This is also called by the gennetlink interface when reconfiguring | |
4604 | * the DCB state. | |
4605 | */ | |
4606 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
4607 | { | |
4608 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 4609 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 4610 | |
67ebd791 AD |
4611 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
4612 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4613 | netif_set_gso_max_size(adapter->netdev, 65536); | |
4614 | return; | |
4615 | } | |
4616 | ||
4617 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4618 | netif_set_gso_max_size(adapter->netdev, 32768); | |
4619 | ||
971060b1 | 4620 | #ifdef IXGBE_FCOE |
b120818e JF |
4621 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
4622 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 4623 | #endif |
b120818e JF |
4624 | |
4625 | /* reconfigure the hardware */ | |
4626 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
4627 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
4628 | DCB_TX_CONFIG); | |
4629 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
4630 | DCB_RX_CONFIG); | |
4631 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
4632 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
4633 | ixgbe_dcb_hw_ets(&adapter->hw, | |
4634 | adapter->ixgbe_ieee_ets, | |
4635 | max_frame); | |
4636 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
4637 | adapter->ixgbe_ieee_pfc->pfc_en, | |
4638 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 4639 | } |
8187cd48 JF |
4640 | |
4641 | /* Enable RSS Hash per TC */ | |
4642 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
4ae63730 AD |
4643 | u32 msb = 0; |
4644 | u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1; | |
8187cd48 | 4645 | |
d411a936 AD |
4646 | while (rss_i) { |
4647 | msb++; | |
4648 | rss_i >>= 1; | |
4649 | } | |
8187cd48 | 4650 | |
4ae63730 AD |
4651 | /* write msb to all 8 TCs in one write */ |
4652 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111); | |
8187cd48 | 4653 | } |
2f90b865 | 4654 | } |
9da712d2 JF |
4655 | #endif |
4656 | ||
4657 | /* Additional bittime to account for IXGBE framing */ | |
4658 | #define IXGBE_ETH_FRAMING 20 | |
4659 | ||
49ce9c2c | 4660 | /** |
9da712d2 JF |
4661 | * ixgbe_hpbthresh - calculate high water mark for flow control |
4662 | * | |
4663 | * @adapter: board private structure to calculate for | |
49ce9c2c | 4664 | * @pb: packet buffer to calculate |
9da712d2 JF |
4665 | */ |
4666 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
4667 | { | |
4668 | struct ixgbe_hw *hw = &adapter->hw; | |
4669 | struct net_device *dev = adapter->netdev; | |
4670 | int link, tc, kb, marker; | |
4671 | u32 dv_id, rx_pba; | |
4672 | ||
4673 | /* Calculate max LAN frame size */ | |
4674 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
4675 | ||
4676 | #ifdef IXGBE_FCOE | |
4677 | /* FCoE traffic class uses FCOE jumbo frames */ | |
800bd607 AD |
4678 | if ((dev->features & NETIF_F_FCOE_MTU) && |
4679 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
4680 | (pb == ixgbe_fcoe_get_tc(adapter))) | |
4681 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9da712d2 | 4682 | #endif |
e5776620 | 4683 | |
9da712d2 JF |
4684 | /* Calculate delay value for device */ |
4685 | switch (hw->mac.type) { | |
4686 | case ixgbe_mac_X540: | |
9a75a1ac DS |
4687 | case ixgbe_mac_X550: |
4688 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4689 | case ixgbe_mac_x550em_a: |
9da712d2 JF |
4690 | dv_id = IXGBE_DV_X540(link, tc); |
4691 | break; | |
4692 | default: | |
4693 | dv_id = IXGBE_DV(link, tc); | |
4694 | break; | |
4695 | } | |
4696 | ||
4697 | /* Loopback switch introduces additional latency */ | |
4698 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4699 | dv_id += IXGBE_B2BT(tc); | |
4700 | ||
4701 | /* Delay value is calculated in bit times convert to KB */ | |
4702 | kb = IXGBE_BT2KB(dv_id); | |
4703 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
4704 | ||
4705 | marker = rx_pba - kb; | |
4706 | ||
4707 | /* It is possible that the packet buffer is not large enough | |
4708 | * to provide required headroom. In this case throw an error | |
4709 | * to user and a do the best we can. | |
4710 | */ | |
4711 | if (marker < 0) { | |
4712 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
4713 | "headroom to support flow control." | |
4714 | "Decrease MTU or number of traffic classes\n", pb); | |
4715 | marker = tc + 1; | |
4716 | } | |
4717 | ||
4718 | return marker; | |
4719 | } | |
4720 | ||
49ce9c2c | 4721 | /** |
9da712d2 JF |
4722 | * ixgbe_lpbthresh - calculate low water mark for for flow control |
4723 | * | |
4724 | * @adapter: board private structure to calculate for | |
49ce9c2c | 4725 | * @pb: packet buffer to calculate |
9da712d2 | 4726 | */ |
e5776620 | 4727 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb) |
9da712d2 JF |
4728 | { |
4729 | struct ixgbe_hw *hw = &adapter->hw; | |
4730 | struct net_device *dev = adapter->netdev; | |
4731 | int tc; | |
4732 | u32 dv_id; | |
4733 | ||
4734 | /* Calculate max LAN frame size */ | |
4735 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
4736 | ||
e5776620 JK |
4737 | #ifdef IXGBE_FCOE |
4738 | /* FCoE traffic class uses FCOE jumbo frames */ | |
4739 | if ((dev->features & NETIF_F_FCOE_MTU) && | |
4740 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
4741 | (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up))) | |
4742 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
4743 | #endif | |
4744 | ||
9da712d2 JF |
4745 | /* Calculate delay value for device */ |
4746 | switch (hw->mac.type) { | |
4747 | case ixgbe_mac_X540: | |
9a75a1ac DS |
4748 | case ixgbe_mac_X550: |
4749 | case ixgbe_mac_X550EM_x: | |
49425dfc | 4750 | case ixgbe_mac_x550em_a: |
9da712d2 JF |
4751 | dv_id = IXGBE_LOW_DV_X540(tc); |
4752 | break; | |
4753 | default: | |
4754 | dv_id = IXGBE_LOW_DV(tc); | |
4755 | break; | |
4756 | } | |
4757 | ||
4758 | /* Delay value is calculated in bit times convert to KB */ | |
4759 | return IXGBE_BT2KB(dv_id); | |
4760 | } | |
4761 | ||
4762 | /* | |
4763 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
4764 | */ | |
4765 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
4766 | { | |
4767 | struct ixgbe_hw *hw = &adapter->hw; | |
4768 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
4769 | int i; | |
4770 | ||
4771 | if (!num_tc) | |
4772 | num_tc = 1; | |
4773 | ||
9da712d2 JF |
4774 | for (i = 0; i < num_tc; i++) { |
4775 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
e5776620 | 4776 | hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i); |
9da712d2 JF |
4777 | |
4778 | /* Low water marks must not be larger than high water marks */ | |
e5776620 JK |
4779 | if (hw->fc.low_water[i] > hw->fc.high_water[i]) |
4780 | hw->fc.low_water[i] = 0; | |
9da712d2 | 4781 | } |
e5776620 JK |
4782 | |
4783 | for (; i < MAX_TRAFFIC_CLASS; i++) | |
4784 | hw->fc.high_water[i] = 0; | |
9da712d2 JF |
4785 | } |
4786 | ||
80605c65 JF |
4787 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
4788 | { | |
80605c65 | 4789 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
4790 | int hdrm; |
4791 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
4792 | |
4793 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
4794 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
4795 | hdrm = 32 << adapter->fdir_pballoc; |
4796 | else | |
4797 | hdrm = 0; | |
80605c65 | 4798 | |
f7e1027f | 4799 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 4800 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
4801 | } |
4802 | ||
e4911d57 AD |
4803 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
4804 | { | |
4805 | struct ixgbe_hw *hw = &adapter->hw; | |
b67bfe0d | 4806 | struct hlist_node *node2; |
e4911d57 AD |
4807 | struct ixgbe_fdir_filter *filter; |
4808 | ||
4809 | spin_lock(&adapter->fdir_perfect_lock); | |
4810 | ||
4811 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
4812 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
4813 | ||
b67bfe0d | 4814 | hlist_for_each_entry_safe(filter, node2, |
e4911d57 AD |
4815 | &adapter->fdir_filter_list, fdir_node) { |
4816 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
4817 | &filter->filter, |
4818 | filter->sw_idx, | |
4819 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
4820 | IXGBE_FDIR_DROP_QUEUE : | |
4821 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
4822 | } |
4823 | ||
4824 | spin_unlock(&adapter->fdir_perfect_lock); | |
4825 | } | |
4826 | ||
2a47fa45 JF |
4827 | static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool, |
4828 | struct ixgbe_adapter *adapter) | |
4829 | { | |
4830 | struct ixgbe_hw *hw = &adapter->hw; | |
4831 | u32 vmolr; | |
4832 | ||
4833 | /* No unicast promiscuous support for VMDQ devices. */ | |
4834 | vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool)); | |
4835 | vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE); | |
4836 | ||
4837 | /* clear the affected bit */ | |
4838 | vmolr &= ~IXGBE_VMOLR_MPE; | |
4839 | ||
4840 | if (dev->flags & IFF_ALLMULTI) { | |
4841 | vmolr |= IXGBE_VMOLR_MPE; | |
4842 | } else { | |
4843 | vmolr |= IXGBE_VMOLR_ROMPE; | |
4844 | hw->mac.ops.update_mc_addr_list(hw, dev); | |
4845 | } | |
5d7daa35 | 4846 | ixgbe_write_uc_addr_list(adapter->netdev, pool); |
2a47fa45 JF |
4847 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr); |
4848 | } | |
4849 | ||
2a47fa45 JF |
4850 | static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter) |
4851 | { | |
4852 | struct ixgbe_adapter *adapter = vadapter->real_adapter; | |
219354d4 | 4853 | int rss_i = adapter->num_rx_queues_per_pool; |
2a47fa45 JF |
4854 | struct ixgbe_hw *hw = &adapter->hw; |
4855 | u16 pool = vadapter->pool; | |
4856 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
4857 | IXGBE_PSRTYPE_UDPHDR | | |
4858 | IXGBE_PSRTYPE_IPV4HDR | | |
4859 | IXGBE_PSRTYPE_L2HDR | | |
4860 | IXGBE_PSRTYPE_IPV6HDR; | |
4861 | ||
4862 | if (hw->mac.type == ixgbe_mac_82598EB) | |
4863 | return; | |
4864 | ||
4865 | if (rss_i > 3) | |
b4f47a48 | 4866 | psrtype |= 2u << 29; |
2a47fa45 | 4867 | else if (rss_i > 1) |
b4f47a48 | 4868 | psrtype |= 1u << 29; |
2a47fa45 JF |
4869 | |
4870 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype); | |
4871 | } | |
4872 | ||
4873 | /** | |
4874 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
4875 | * @rx_ring: ring to free buffers from | |
4876 | **/ | |
4877 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) | |
4878 | { | |
4879 | struct device *dev = rx_ring->dev; | |
4880 | unsigned long size; | |
4881 | u16 i; | |
4882 | ||
4883 | /* ring already cleared, nothing to do */ | |
4884 | if (!rx_ring->rx_buffer_info) | |
4885 | return; | |
4886 | ||
4887 | /* Free all the Rx ring sk_buffs */ | |
4888 | for (i = 0; i < rx_ring->count; i++) { | |
18cb652a | 4889 | struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i]; |
2a47fa45 | 4890 | |
2a47fa45 JF |
4891 | if (rx_buffer->skb) { |
4892 | struct sk_buff *skb = rx_buffer->skb; | |
18cb652a | 4893 | if (IXGBE_CB(skb)->page_released) |
2a47fa45 JF |
4894 | dma_unmap_page(dev, |
4895 | IXGBE_CB(skb)->dma, | |
4896 | ixgbe_rx_bufsz(rx_ring), | |
4897 | DMA_FROM_DEVICE); | |
2a47fa45 | 4898 | dev_kfree_skb(skb); |
4d2fcfbc | 4899 | rx_buffer->skb = NULL; |
2a47fa45 | 4900 | } |
18cb652a AD |
4901 | |
4902 | if (!rx_buffer->page) | |
4903 | continue; | |
4904 | ||
4905 | dma_unmap_page(dev, rx_buffer->dma, | |
4906 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
4907 | __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring)); | |
4908 | ||
2a47fa45 JF |
4909 | rx_buffer->page = NULL; |
4910 | } | |
4911 | ||
4912 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4913 | memset(rx_ring->rx_buffer_info, 0, size); | |
4914 | ||
4915 | /* Zero out the descriptor ring */ | |
4916 | memset(rx_ring->desc, 0, rx_ring->size); | |
4917 | ||
4918 | rx_ring->next_to_alloc = 0; | |
4919 | rx_ring->next_to_clean = 0; | |
4920 | rx_ring->next_to_use = 0; | |
4921 | } | |
4922 | ||
4923 | static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter, | |
4924 | struct ixgbe_ring *rx_ring) | |
4925 | { | |
4926 | struct ixgbe_adapter *adapter = vadapter->real_adapter; | |
4927 | int index = rx_ring->queue_index + vadapter->rx_base_queue; | |
4928 | ||
4929 | /* shutdown specific queue receive and wait for dma to settle */ | |
4930 | ixgbe_disable_rx_queue(adapter, rx_ring); | |
4931 | usleep_range(10000, 20000); | |
b4f47a48 | 4932 | ixgbe_irq_disable_queues(adapter, BIT_ULL(index)); |
2a47fa45 JF |
4933 | ixgbe_clean_rx_ring(rx_ring); |
4934 | rx_ring->l2_accel_priv = NULL; | |
4935 | } | |
4936 | ||
ae72c8d0 JF |
4937 | static int ixgbe_fwd_ring_down(struct net_device *vdev, |
4938 | struct ixgbe_fwd_adapter *accel) | |
2a47fa45 JF |
4939 | { |
4940 | struct ixgbe_adapter *adapter = accel->real_adapter; | |
4941 | unsigned int rxbase = accel->rx_base_queue; | |
4942 | unsigned int txbase = accel->tx_base_queue; | |
4943 | int i; | |
4944 | ||
4945 | netif_tx_stop_all_queues(vdev); | |
4946 | ||
4947 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
4948 | ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); | |
4949 | adapter->rx_ring[rxbase + i]->netdev = adapter->netdev; | |
4950 | } | |
4951 | ||
4952 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
4953 | adapter->tx_ring[txbase + i]->l2_accel_priv = NULL; | |
4954 | adapter->tx_ring[txbase + i]->netdev = adapter->netdev; | |
4955 | } | |
4956 | ||
4957 | ||
4958 | return 0; | |
4959 | } | |
4960 | ||
4961 | static int ixgbe_fwd_ring_up(struct net_device *vdev, | |
4962 | struct ixgbe_fwd_adapter *accel) | |
4963 | { | |
4964 | struct ixgbe_adapter *adapter = accel->real_adapter; | |
4965 | unsigned int rxbase, txbase, queues; | |
4966 | int i, baseq, err = 0; | |
4967 | ||
4968 | if (!test_bit(accel->pool, &adapter->fwd_bitmask)) | |
4969 | return 0; | |
4970 | ||
4971 | baseq = accel->pool * adapter->num_rx_queues_per_pool; | |
4972 | netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", | |
4973 | accel->pool, adapter->num_rx_pools, | |
4974 | baseq, baseq + adapter->num_rx_queues_per_pool, | |
4975 | adapter->fwd_bitmask); | |
4976 | ||
4977 | accel->netdev = vdev; | |
4978 | accel->rx_base_queue = rxbase = baseq; | |
4979 | accel->tx_base_queue = txbase = baseq; | |
4980 | ||
4981 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) | |
4982 | ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]); | |
4983 | ||
4984 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
4985 | adapter->rx_ring[rxbase + i]->netdev = vdev; | |
4986 | adapter->rx_ring[rxbase + i]->l2_accel_priv = accel; | |
4987 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]); | |
4988 | } | |
4989 | ||
4990 | for (i = 0; i < adapter->num_rx_queues_per_pool; i++) { | |
4991 | adapter->tx_ring[txbase + i]->netdev = vdev; | |
4992 | adapter->tx_ring[txbase + i]->l2_accel_priv = accel; | |
4993 | } | |
4994 | ||
4995 | queues = min_t(unsigned int, | |
4996 | adapter->num_rx_queues_per_pool, vdev->num_tx_queues); | |
4997 | err = netif_set_real_num_tx_queues(vdev, queues); | |
4998 | if (err) | |
4999 | goto fwd_queue_err; | |
5000 | ||
2a47fa45 JF |
5001 | err = netif_set_real_num_rx_queues(vdev, queues); |
5002 | if (err) | |
5003 | goto fwd_queue_err; | |
5004 | ||
5005 | if (is_valid_ether_addr(vdev->dev_addr)) | |
5006 | ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool); | |
5007 | ||
5008 | ixgbe_fwd_psrtype(accel); | |
5009 | ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter); | |
5010 | return err; | |
5011 | fwd_queue_err: | |
5012 | ixgbe_fwd_ring_down(vdev, accel); | |
5013 | return err; | |
5014 | } | |
5015 | ||
5016 | static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter) | |
5017 | { | |
5018 | struct net_device *upper; | |
5019 | struct list_head *iter; | |
5020 | int err; | |
5021 | ||
5022 | netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { | |
5023 | if (netif_is_macvlan(upper)) { | |
5024 | struct macvlan_dev *dfwd = netdev_priv(upper); | |
5025 | struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; | |
5026 | ||
5027 | if (dfwd->fwd_priv) { | |
5028 | err = ixgbe_fwd_ring_up(upper, vadapter); | |
5029 | if (err) | |
5030 | continue; | |
5031 | } | |
5032 | } | |
5033 | } | |
5034 | } | |
5035 | ||
9a799d71 AK |
5036 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
5037 | { | |
d2f5e7f3 AS |
5038 | struct ixgbe_hw *hw = &adapter->hw; |
5039 | ||
80605c65 | 5040 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 5041 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 5042 | ixgbe_configure_dcb(adapter); |
2f90b865 | 5043 | #endif |
b35d4d42 AD |
5044 | /* |
5045 | * We must restore virtualization before VLANs or else | |
5046 | * the VLVF registers will not be populated | |
5047 | */ | |
5048 | ixgbe_configure_virtualization(adapter); | |
9a799d71 | 5049 | |
4c1d7b4b | 5050 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
5051 | ixgbe_restore_vlan(adapter); |
5052 | ||
d2f5e7f3 AS |
5053 | switch (hw->mac.type) { |
5054 | case ixgbe_mac_82599EB: | |
5055 | case ixgbe_mac_X540: | |
5056 | hw->mac.ops.disable_rx_buff(hw); | |
5057 | break; | |
5058 | default: | |
5059 | break; | |
5060 | } | |
5061 | ||
c4cf55e5 | 5062 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
5063 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
5064 | adapter->fdir_pballoc); | |
e4911d57 AD |
5065 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
5066 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
5067 | adapter->fdir_pballoc); | |
5068 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 5069 | } |
4c1d7b4b | 5070 | |
d2f5e7f3 AS |
5071 | switch (hw->mac.type) { |
5072 | case ixgbe_mac_82599EB: | |
5073 | case ixgbe_mac_X540: | |
5074 | hw->mac.ops.enable_rx_buff(hw); | |
5075 | break; | |
5076 | default: | |
5077 | break; | |
5078 | } | |
5079 | ||
9de7605e MR |
5080 | #ifdef CONFIG_IXGBE_DCA |
5081 | /* configure DCA */ | |
5082 | if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE) | |
5083 | ixgbe_setup_dca(adapter); | |
5084 | #endif /* CONFIG_IXGBE_DCA */ | |
5085 | ||
7c8ae65a AD |
5086 | #ifdef IXGBE_FCOE |
5087 | /* configure FCoE L2 filters, redirection table, and Rx control */ | |
5088 | ixgbe_configure_fcoe(adapter); | |
5089 | ||
5090 | #endif /* IXGBE_FCOE */ | |
9a799d71 AK |
5091 | ixgbe_configure_tx(adapter); |
5092 | ixgbe_configure_rx(adapter); | |
2a47fa45 | 5093 | ixgbe_configure_dfwd(adapter); |
9a799d71 AK |
5094 | } |
5095 | ||
0ecc061d | 5096 | /** |
e8e26350 PW |
5097 | * ixgbe_sfp_link_config - set up SFP+ link |
5098 | * @adapter: pointer to private adapter struct | |
5099 | **/ | |
5100 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
5101 | { | |
7086400d | 5102 | /* |
52f33af8 | 5103 | * We are assuming the worst case scenario here, and that |
7086400d AD |
5104 | * is that an SFP was inserted/removed after the reset |
5105 | * but before SFP detection was enabled. As such the best | |
5106 | * solution is to just start searching as soon as we start | |
5107 | */ | |
5108 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5109 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 5110 | |
7086400d | 5111 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
58e7cd24 | 5112 | adapter->sfp_poll_time = 0; |
e8e26350 PW |
5113 | } |
5114 | ||
5115 | /** | |
5116 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
5117 | * @hw: pointer to private hardware struct |
5118 | * | |
5119 | * Returns 0 on success, negative on failure | |
5120 | **/ | |
e8e26350 | 5121 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d | 5122 | { |
3d292265 JH |
5123 | u32 speed; |
5124 | bool autoneg, link_up = false; | |
a1e869de | 5125 | int ret = IXGBE_ERR_LINK_SETUP; |
0ecc061d PWJ |
5126 | |
5127 | if (hw->mac.ops.check_link) | |
3d292265 | 5128 | ret = hw->mac.ops.check_link(hw, &speed, &link_up, false); |
0ecc061d PWJ |
5129 | |
5130 | if (ret) | |
e90dd264 | 5131 | return ret; |
0ecc061d | 5132 | |
3d292265 JH |
5133 | speed = hw->phy.autoneg_advertised; |
5134 | if ((!speed) && (hw->mac.ops.get_link_capabilities)) | |
5135 | ret = hw->mac.ops.get_link_capabilities(hw, &speed, | |
5136 | &autoneg); | |
0ecc061d | 5137 | if (ret) |
e90dd264 | 5138 | return ret; |
0ecc061d | 5139 | |
8620a103 | 5140 | if (hw->mac.ops.setup_link) |
fd0326f2 | 5141 | ret = hw->mac.ops.setup_link(hw, speed, link_up); |
e90dd264 | 5142 | |
0ecc061d PWJ |
5143 | return ret; |
5144 | } | |
5145 | ||
a34bcfff | 5146 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 5147 | { |
9a799d71 | 5148 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 5149 | u32 gpie = 0; |
9a799d71 | 5150 | |
9b471446 | 5151 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
5152 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
5153 | IXGBE_GPIE_OCD; | |
5154 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
5155 | /* |
5156 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
5157 | * this saves a register write for every interrupt | |
5158 | */ | |
5159 | switch (hw->mac.type) { | |
5160 | case ixgbe_mac_82598EB: | |
5161 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
5162 | break; | |
9b471446 | 5163 | case ixgbe_mac_82599EB: |
b93a2226 | 5164 | case ixgbe_mac_X540: |
9a75a1ac DS |
5165 | case ixgbe_mac_X550: |
5166 | case ixgbe_mac_X550EM_x: | |
49425dfc | 5167 | case ixgbe_mac_x550em_a: |
b93a2226 | 5168 | default: |
9b471446 JB |
5169 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
5170 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
5171 | break; | |
5172 | } | |
5173 | } else { | |
021230d4 AV |
5174 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
5175 | * specifically only auto mask tx and rx interrupts */ | |
5176 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
5177 | } | |
9a799d71 | 5178 | |
a34bcfff AD |
5179 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
5180 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
5181 | ||
5182 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
5183 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
73079ea0 AD |
5184 | |
5185 | switch (adapter->ring_feature[RING_F_VMDQ].mask) { | |
5186 | case IXGBE_82599_VMDQ_8Q_MASK: | |
5187 | gpie |= IXGBE_GPIE_VTMODE_16; | |
5188 | break; | |
5189 | case IXGBE_82599_VMDQ_4Q_MASK: | |
5190 | gpie |= IXGBE_GPIE_VTMODE_32; | |
5191 | break; | |
5192 | default: | |
5193 | gpie |= IXGBE_GPIE_VTMODE_64; | |
5194 | break; | |
5195 | } | |
119fc60a MC |
5196 | } |
5197 | ||
5fdd31f9 | 5198 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
5199 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
5200 | switch (adapter->hw.mac.type) { | |
5201 | case ixgbe_mac_82599EB: | |
9a900eca | 5202 | gpie |= IXGBE_SDP0_GPIEN_8259X; |
f3df98ec | 5203 | break; |
f3df98ec DS |
5204 | default: |
5205 | break; | |
5206 | } | |
5207 | } | |
5fdd31f9 | 5208 | |
a34bcfff AD |
5209 | /* Enable fan failure interrupt */ |
5210 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
9a900eca | 5211 | gpie |= IXGBE_SDP1_GPIEN(hw); |
0befdb3e | 5212 | |
a023bbd0 DS |
5213 | switch (hw->mac.type) { |
5214 | case ixgbe_mac_82599EB: | |
5215 | gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X; | |
5216 | break; | |
5217 | case ixgbe_mac_X550EM_x: | |
49425dfc | 5218 | case ixgbe_mac_x550em_a: |
a023bbd0 DS |
5219 | gpie |= IXGBE_SDP0_GPIEN_X540; |
5220 | break; | |
5221 | default: | |
5222 | break; | |
2698b208 | 5223 | } |
a34bcfff AD |
5224 | |
5225 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
5226 | } | |
5227 | ||
c7ccde0f | 5228 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
5229 | { |
5230 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 5231 | int err; |
a34bcfff AD |
5232 | u32 ctrl_ext; |
5233 | ||
5234 | ixgbe_get_hw_control(adapter); | |
5235 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 5236 | |
9a799d71 AK |
5237 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
5238 | ixgbe_configure_msix(adapter); | |
5239 | else | |
5240 | ixgbe_configure_msi_and_legacy(adapter); | |
5241 | ||
ec74a471 ET |
5242 | /* enable the optics for 82599 SFP+ fiber */ |
5243 | if (hw->mac.ops.enable_tx_laser) | |
61fac744 PW |
5244 | hw->mac.ops.enable_tx_laser(hw); |
5245 | ||
961fac88 DS |
5246 | if (hw->phy.ops.set_phy_power) |
5247 | hw->phy.ops.set_phy_power(hw, true); | |
5248 | ||
4e857c58 | 5249 | smp_mb__before_atomic(); |
9a799d71 | 5250 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
5251 | ixgbe_napi_enable_all(adapter); |
5252 | ||
73c4b7cd AD |
5253 | if (ixgbe_is_sfp(hw)) { |
5254 | ixgbe_sfp_link_config(adapter); | |
5255 | } else { | |
5256 | err = ixgbe_non_sfp_link_config(hw); | |
5257 | if (err) | |
5258 | e_err(probe, "link_config FAILED %d\n", err); | |
5259 | } | |
5260 | ||
021230d4 AV |
5261 | /* clear any pending interrupts, may auto mask */ |
5262 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 5263 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 5264 | |
bf069c97 DS |
5265 | /* |
5266 | * If this adapter has a fan, check to see if we had a failure | |
5267 | * before we enabled the interrupt. | |
5268 | */ | |
5269 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
5270 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
5271 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 5272 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
5273 | } |
5274 | ||
9a799d71 AK |
5275 | /* bring the link up in the watchdog, this could race with our first |
5276 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
5277 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
5278 | adapter->link_check_timeout = jiffies; | |
7086400d | 5279 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
5280 | |
5281 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
5282 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
5283 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
5284 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
5285 | } |
5286 | ||
d4f80882 AV |
5287 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
5288 | { | |
5289 | WARN_ON(in_interrupt()); | |
7086400d | 5290 | /* put off any impending NetWatchDogTimeout */ |
860e9538 | 5291 | netif_trans_update(adapter->netdev); |
7086400d | 5292 | |
d4f80882 | 5293 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 5294 | usleep_range(1000, 2000); |
d4f80882 | 5295 | ixgbe_down(adapter); |
5809a1ae GR |
5296 | /* |
5297 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
5298 | * back up to give the VFs time to respond to the reset. The | |
5299 | * two second wait is based upon the watchdog timer cycle in | |
5300 | * the VF driver. | |
5301 | */ | |
5302 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
5303 | msleep(2000); | |
d4f80882 AV |
5304 | ixgbe_up(adapter); |
5305 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
5306 | } | |
5307 | ||
c7ccde0f | 5308 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5309 | { |
5310 | /* hardware has been reset, we need to reload some things */ | |
5311 | ixgbe_configure(adapter); | |
5312 | ||
c7ccde0f | 5313 | ixgbe_up_complete(adapter); |
9a799d71 AK |
5314 | } |
5315 | ||
5316 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
5317 | { | |
c44ade9e | 5318 | struct ixgbe_hw *hw = &adapter->hw; |
5d7daa35 | 5319 | struct net_device *netdev = adapter->netdev; |
8ca783ab DS |
5320 | int err; |
5321 | ||
b0483c8f MR |
5322 | if (ixgbe_removed(hw->hw_addr)) |
5323 | return; | |
7086400d AD |
5324 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
5325 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5326 | usleep_range(1000, 2000); | |
5327 | ||
5328 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
5329 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
5330 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
5331 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5332 | ||
8ca783ab | 5333 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
5334 | switch (err) { |
5335 | case 0: | |
5336 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 5337 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
5338 | break; |
5339 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 5340 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 5341 | break; |
794caeb2 PWJ |
5342 | case IXGBE_ERR_EEPROM_VERSION: |
5343 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 5344 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 5345 | "Please be aware there may be issues associated with " |
849c4542 ET |
5346 | "your hardware. If you are experiencing problems " |
5347 | "please contact your Intel or hardware " | |
5348 | "representative who provided you with this " | |
5349 | "hardware.\n"); | |
794caeb2 | 5350 | break; |
da4dd0f7 | 5351 | default: |
849c4542 | 5352 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 5353 | } |
9a799d71 | 5354 | |
7086400d | 5355 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
0f079d22 AD |
5356 | |
5357 | /* flush entries out of MAC table */ | |
5d7daa35 | 5358 | ixgbe_flush_sw_mac_table(adapter); |
0f079d22 AD |
5359 | __dev_uc_unsync(netdev, NULL); |
5360 | ||
5361 | /* do not flush user set addresses */ | |
c9f53e63 | 5362 | ixgbe_mac_set_default_filter(adapter); |
7fa7c9dc AD |
5363 | |
5364 | /* update SAN MAC vmdq pool selection */ | |
5365 | if (hw->mac.san_mac_rar_index) | |
5366 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
1a71ab24 | 5367 | |
8fecf67c | 5368 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 5369 | ixgbe_ptp_reset(adapter); |
961fac88 DS |
5370 | |
5371 | if (hw->phy.ops.set_phy_power) { | |
5372 | if (!netif_running(adapter->netdev) && !adapter->wol) | |
5373 | hw->phy.ops.set_phy_power(hw, false); | |
5374 | else | |
5375 | hw->phy.ops.set_phy_power(hw, true); | |
5376 | } | |
9a799d71 AK |
5377 | } |
5378 | ||
9a799d71 AK |
5379 | /** |
5380 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
5381 | * @tx_ring: ring to be cleaned |
5382 | **/ | |
b6ec895e | 5383 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
5384 | { |
5385 | struct ixgbe_tx_buffer *tx_buffer_info; | |
5386 | unsigned long size; | |
b6ec895e | 5387 | u16 i; |
9a799d71 | 5388 | |
84418e3b AD |
5389 | /* ring already cleared, nothing to do */ |
5390 | if (!tx_ring->tx_buffer_info) | |
5391 | return; | |
9a799d71 | 5392 | |
84418e3b | 5393 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
5394 | for (i = 0; i < tx_ring->count; i++) { |
5395 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 5396 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
5397 | } |
5398 | ||
dad8a3b3 JF |
5399 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
5400 | ||
9a799d71 AK |
5401 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
5402 | memset(tx_ring->tx_buffer_info, 0, size); | |
5403 | ||
5404 | /* Zero out the descriptor ring */ | |
5405 | memset(tx_ring->desc, 0, tx_ring->size); | |
5406 | ||
5407 | tx_ring->next_to_use = 0; | |
5408 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
5409 | } |
5410 | ||
5411 | /** | |
021230d4 | 5412 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
5413 | * @adapter: board private structure |
5414 | **/ | |
021230d4 | 5415 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5416 | { |
5417 | int i; | |
5418 | ||
021230d4 | 5419 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 5420 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
5421 | } |
5422 | ||
5423 | /** | |
021230d4 | 5424 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
5425 | * @adapter: board private structure |
5426 | **/ | |
021230d4 | 5427 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5428 | { |
5429 | int i; | |
5430 | ||
021230d4 | 5431 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 5432 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
5433 | } |
5434 | ||
e4911d57 AD |
5435 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
5436 | { | |
b67bfe0d | 5437 | struct hlist_node *node2; |
e4911d57 AD |
5438 | struct ixgbe_fdir_filter *filter; |
5439 | ||
5440 | spin_lock(&adapter->fdir_perfect_lock); | |
5441 | ||
b67bfe0d | 5442 | hlist_for_each_entry_safe(filter, node2, |
e4911d57 AD |
5443 | &adapter->fdir_filter_list, fdir_node) { |
5444 | hlist_del(&filter->fdir_node); | |
5445 | kfree(filter); | |
5446 | } | |
5447 | adapter->fdir_filter_count = 0; | |
5448 | ||
5449 | spin_unlock(&adapter->fdir_perfect_lock); | |
5450 | } | |
5451 | ||
9a799d71 AK |
5452 | void ixgbe_down(struct ixgbe_adapter *adapter) |
5453 | { | |
5454 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 5455 | struct ixgbe_hw *hw = &adapter->hw; |
2a47fa45 JF |
5456 | struct net_device *upper; |
5457 | struct list_head *iter; | |
bf29ee6c | 5458 | int i; |
9a799d71 AK |
5459 | |
5460 | /* signal that we are down to the interrupt handler */ | |
c3049c8f MR |
5461 | if (test_and_set_bit(__IXGBE_DOWN, &adapter->state)) |
5462 | return; /* do nothing if already down */ | |
9a799d71 AK |
5463 | |
5464 | /* disable receives */ | |
1f9ac57c | 5465 | hw->mac.ops.disable_rx(hw); |
9a799d71 | 5466 | |
2d39d576 YZ |
5467 | /* disable all enabled rx queues */ |
5468 | for (i = 0; i < adapter->num_rx_queues; i++) | |
5469 | /* this call also flushes the previous write */ | |
5470 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
5471 | ||
032b4325 | 5472 | usleep_range(10000, 20000); |
9a799d71 | 5473 | |
7f821875 JB |
5474 | netif_tx_stop_all_queues(netdev); |
5475 | ||
7086400d | 5476 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
5477 | netif_carrier_off(netdev); |
5478 | netif_tx_disable(netdev); | |
5479 | ||
2a47fa45 JF |
5480 | /* disable any upper devices */ |
5481 | netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { | |
5482 | if (netif_is_macvlan(upper)) { | |
5483 | struct macvlan_dev *vlan = netdev_priv(upper); | |
5484 | ||
5485 | if (vlan->fwd_priv) { | |
5486 | netif_tx_stop_all_queues(upper); | |
5487 | netif_carrier_off(upper); | |
5488 | netif_tx_disable(upper); | |
5489 | } | |
5490 | } | |
5491 | } | |
5492 | ||
c0dfb90e JF |
5493 | ixgbe_irq_disable(adapter); |
5494 | ||
5495 | ixgbe_napi_disable_all(adapter); | |
5496 | ||
d034acf1 AD |
5497 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
5498 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
5499 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
5500 | ||
5501 | del_timer_sync(&adapter->service_timer); | |
5502 | ||
34cecbbf | 5503 | if (adapter->num_vfs) { |
8e34d1aa AD |
5504 | /* Clear EITR Select mapping */ |
5505 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
5506 | |
5507 | /* Mark all the VFs as inactive */ | |
5508 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 5509 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 5510 | |
34cecbbf AD |
5511 | /* ping all the active vfs to let them know we are going down */ |
5512 | ixgbe_ping_all_vfs(adapter); | |
5513 | ||
5514 | /* Disable all VFTE/VFRE TX/RX */ | |
5515 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
5516 | } |
5517 | ||
7f821875 JB |
5518 | /* disable transmits in the hardware now that interrupts are off */ |
5519 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 5520 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 5521 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 5522 | } |
34cecbbf | 5523 | |
9a75a1ac | 5524 | /* Disable the Tx DMA engine on 82599 and later MAC */ |
bd508178 AD |
5525 | switch (hw->mac.type) { |
5526 | case ixgbe_mac_82599EB: | |
b93a2226 | 5527 | case ixgbe_mac_X540: |
9a75a1ac DS |
5528 | case ixgbe_mac_X550: |
5529 | case ixgbe_mac_X550EM_x: | |
49425dfc | 5530 | case ixgbe_mac_x550em_a: |
88512539 | 5531 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
5532 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
5533 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
5534 | break; |
5535 | default: | |
5536 | break; | |
5537 | } | |
7f821875 | 5538 | |
6f4a0e45 PL |
5539 | if (!pci_channel_offline(adapter->pdev)) |
5540 | ixgbe_reset(adapter); | |
c6ecf39a | 5541 | |
ec74a471 ET |
5542 | /* power down the optics for 82599 SFP+ fiber */ |
5543 | if (hw->mac.ops.disable_tx_laser) | |
c6ecf39a DS |
5544 | hw->mac.ops.disable_tx_laser(hw); |
5545 | ||
9a799d71 AK |
5546 | ixgbe_clean_all_tx_rings(adapter); |
5547 | ixgbe_clean_all_rx_rings(adapter); | |
9a799d71 AK |
5548 | } |
5549 | ||
9a799d71 AK |
5550 | /** |
5551 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
5552 | * @netdev: network interface device structure | |
5553 | **/ | |
5554 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
5555 | { | |
5556 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5557 | ||
5558 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 5559 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
5560 | } |
5561 | ||
8829009d UK |
5562 | #ifdef CONFIG_IXGBE_DCB |
5563 | static void ixgbe_init_dcb(struct ixgbe_adapter *adapter) | |
5564 | { | |
5565 | struct ixgbe_hw *hw = &adapter->hw; | |
5566 | struct tc_configuration *tc; | |
5567 | int j; | |
5568 | ||
5569 | switch (hw->mac.type) { | |
5570 | case ixgbe_mac_82598EB: | |
5571 | case ixgbe_mac_82599EB: | |
5572 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
5573 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
5574 | break; | |
5575 | case ixgbe_mac_X540: | |
5576 | case ixgbe_mac_X550: | |
5577 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
5578 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
5579 | break; | |
5580 | case ixgbe_mac_X550EM_x: | |
5581 | case ixgbe_mac_x550em_a: | |
5582 | default: | |
5583 | adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS; | |
5584 | adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS; | |
5585 | break; | |
5586 | } | |
5587 | ||
5588 | /* Configure DCB traffic classes */ | |
5589 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
5590 | tc = &adapter->dcb_cfg.tc_config[j]; | |
5591 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
5592 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
5593 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
5594 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
5595 | tc->dcb_pfc = pfc_disabled; | |
5596 | } | |
5597 | ||
5598 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
5599 | tc = &adapter->dcb_cfg.tc_config[0]; | |
5600 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5601 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5602 | ||
5603 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
5604 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
5605 | adapter->dcb_cfg.pfc_mode_enable = false; | |
5606 | adapter->dcb_set_bitmap = 0x00; | |
5607 | if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) | |
5608 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; | |
5609 | memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, | |
5610 | sizeof(adapter->temp_dcb_cfg)); | |
5611 | } | |
5612 | #endif | |
5613 | ||
9a799d71 AK |
5614 | /** |
5615 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
5616 | * @adapter: board private structure to initialize | |
5617 | * | |
5618 | * ixgbe_sw_init initializes the Adapter private data structure. | |
5619 | * Fields are initialized based on PCI device information and | |
5620 | * OS network device settings (MTU size). | |
5621 | **/ | |
9f9a12f8 | 5622 | static int ixgbe_sw_init(struct ixgbe_adapter *adapter) |
9a799d71 AK |
5623 | { |
5624 | struct ixgbe_hw *hw = &adapter->hw; | |
5625 | struct pci_dev *pdev = adapter->pdev; | |
d3cb9869 | 5626 | unsigned int rss, fdir; |
cb6d0f5e | 5627 | u32 fwsm; |
4319a797 | 5628 | u16 device_caps; |
1cdaaf54 | 5629 | int i; |
021230d4 | 5630 | |
c44ade9e JB |
5631 | /* PCI config space info */ |
5632 | ||
5633 | hw->vendor_id = pdev->vendor; | |
5634 | hw->device_id = pdev->device; | |
5635 | hw->revision_id = pdev->revision; | |
5636 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
5637 | hw->subsystem_device_id = pdev->subsystem_device; | |
5638 | ||
8fc3bb6d | 5639 | /* Set common capability flags and settings */ |
0f9b232b | 5640 | rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus()); |
c087663e | 5641 | adapter->ring_feature[RING_F_RSS].limit = rss; |
8fc3bb6d | 5642 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
8fc3bb6d ET |
5643 | adapter->max_q_vectors = MAX_Q_VECTORS_82599; |
5644 | adapter->atr_sample_rate = 20; | |
d3cb9869 AD |
5645 | fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus()); |
5646 | adapter->ring_feature[RING_F_FDIR].limit = fdir; | |
8fc3bb6d ET |
5647 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
5648 | #ifdef CONFIG_IXGBE_DCA | |
5649 | adapter->flags |= IXGBE_FLAG_DCA_CAPABLE; | |
5650 | #endif | |
8829009d UK |
5651 | #ifdef CONFIG_IXGBE_DCB |
5652 | adapter->flags |= IXGBE_FLAG_DCB_CAPABLE; | |
5653 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
5654 | #endif | |
8fc3bb6d ET |
5655 | #ifdef IXGBE_FCOE |
5656 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; | |
5657 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5658 | #ifdef CONFIG_IXGBE_DCB | |
5659 | /* Default traffic class to use for FCoE */ | |
5660 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; | |
5661 | #endif /* CONFIG_IXGBE_DCB */ | |
5662 | #endif /* IXGBE_FCOE */ | |
5663 | ||
b82b17d9 | 5664 | /* initialize static ixgbe jump table entries */ |
1cdaaf54 AN |
5665 | adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]), |
5666 | GFP_KERNEL); | |
5667 | if (!adapter->jump_tables[0]) | |
5668 | return -ENOMEM; | |
5669 | adapter->jump_tables[0]->mat = ixgbe_ipv4_fields; | |
5670 | ||
5671 | for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) | |
5672 | adapter->jump_tables[i] = NULL; | |
b82b17d9 | 5673 | |
5d7daa35 JK |
5674 | adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) * |
5675 | hw->mac.num_rar_entries, | |
5676 | GFP_ATOMIC); | |
530fd82a AD |
5677 | if (!adapter->mac_table) |
5678 | return -ENOMEM; | |
5d7daa35 | 5679 | |
8fc3bb6d | 5680 | /* Set MAC specific capability flags and exceptions */ |
bd508178 AD |
5681 | switch (hw->mac.type) { |
5682 | case ixgbe_mac_82598EB: | |
8fc3bb6d | 5683 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE; |
8fc3bb6d | 5684 | |
bf069c97 DS |
5685 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
5686 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
8fc3bb6d | 5687 | |
49c7ffbe | 5688 | adapter->max_q_vectors = MAX_Q_VECTORS_82598; |
8fc3bb6d ET |
5689 | adapter->ring_feature[RING_F_FDIR].limit = 0; |
5690 | adapter->atr_sample_rate = 0; | |
5691 | adapter->fdir_pballoc = 0; | |
5692 | #ifdef IXGBE_FCOE | |
5693 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
5694 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5695 | #ifdef CONFIG_IXGBE_DCB | |
5696 | adapter->fcoe.up = 0; | |
5697 | #endif /* IXGBE_DCB */ | |
5698 | #endif /* IXGBE_FCOE */ | |
5699 | break; | |
5700 | case ixgbe_mac_82599EB: | |
5701 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) | |
5702 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
bd508178 | 5703 | break; |
b93a2226 | 5704 | case ixgbe_mac_X540: |
9a900eca | 5705 | fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); |
cb6d0f5e JK |
5706 | if (fwsm & IXGBE_FWSM_TS_ENABLED) |
5707 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
bd508178 | 5708 | break; |
9a75a1ac | 5709 | case ixgbe_mac_X550EM_x: |
49425dfc | 5710 | case ixgbe_mac_x550em_a: |
8829009d UK |
5711 | #ifdef CONFIG_IXGBE_DCB |
5712 | adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE; | |
5713 | #endif | |
5714 | #ifdef IXGBE_FCOE | |
5715 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
5716 | #ifdef CONFIG_IXGBE_DCB | |
5717 | adapter->fcoe.up = 0; | |
5718 | #endif /* IXGBE_DCB */ | |
5719 | #endif /* IXGBE_FCOE */ | |
5720 | /* Fall Through */ | |
9a75a1ac DS |
5721 | case ixgbe_mac_X550: |
5722 | #ifdef CONFIG_IXGBE_DCA | |
5723 | adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE; | |
67359c3c MR |
5724 | #endif |
5725 | #ifdef CONFIG_IXGBE_VXLAN | |
5726 | adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE; | |
9a75a1ac DS |
5727 | #endif |
5728 | break; | |
bd508178 AD |
5729 | default: |
5730 | break; | |
f8212f97 | 5731 | } |
2f90b865 | 5732 | |
7c8ae65a AD |
5733 | #ifdef IXGBE_FCOE |
5734 | /* FCoE support exists, always init the FCoE lock */ | |
5735 | spin_lock_init(&adapter->fcoe.lock); | |
5736 | ||
5737 | #endif | |
1fc5f038 AD |
5738 | /* n-tuple support exists, always init our spinlock */ |
5739 | spin_lock_init(&adapter->fdir_perfect_lock); | |
5740 | ||
7a6b6f51 | 5741 | #ifdef CONFIG_IXGBE_DCB |
8829009d | 5742 | ixgbe_init_dcb(adapter); |
2f90b865 | 5743 | #endif |
9a799d71 AK |
5744 | |
5745 | /* default flow control settings */ | |
cd7664f6 | 5746 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 5747 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
9da712d2 | 5748 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
5749 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
5750 | hw->fc.send_xon = true; | |
73d80953 | 5751 | hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw); |
9a799d71 | 5752 | |
99d74487 | 5753 | #ifdef CONFIG_PCI_IOV |
170e8543 JK |
5754 | if (max_vfs > 0) |
5755 | e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n"); | |
5756 | ||
99d74487 | 5757 | /* assign number of SR-IOV VFs */ |
170e8543 | 5758 | if (hw->mac.type != ixgbe_mac_82598EB) { |
dcc23e3a | 5759 | if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) { |
170e8543 JK |
5760 | adapter->num_vfs = 0; |
5761 | e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n"); | |
5762 | } else { | |
5763 | adapter->num_vfs = max_vfs; | |
5764 | } | |
5765 | } | |
5766 | #endif /* CONFIG_PCI_IOV */ | |
99d74487 | 5767 | |
30efa5a3 | 5768 | /* enable itr by default in dynamic mode */ |
f7554a2b | 5769 | adapter->rx_itr_setting = 1; |
f7554a2b | 5770 | adapter->tx_itr_setting = 1; |
30efa5a3 | 5771 | |
30efa5a3 JB |
5772 | /* set default ring sizes */ |
5773 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
5774 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
5775 | ||
4319a797 DS |
5776 | /* Cache bit indicating need for crosstalk fix */ |
5777 | switch (hw->mac.type) { | |
5778 | case ixgbe_mac_82599EB: | |
5779 | case ixgbe_mac_X550EM_x: | |
5780 | case ixgbe_mac_x550em_a: | |
5781 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
5782 | if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR) | |
5783 | adapter->need_crosstalk_fix = false; | |
5784 | else | |
5785 | adapter->need_crosstalk_fix = true; | |
5786 | break; | |
5787 | default: | |
5788 | adapter->need_crosstalk_fix = false; | |
5789 | break; | |
5790 | } | |
5791 | ||
bd198058 | 5792 | /* set default work limits */ |
59224555 | 5793 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 5794 | |
9a799d71 | 5795 | /* initialize eeprom parameters */ |
c44ade9e | 5796 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 5797 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
5798 | return -EIO; |
5799 | } | |
5800 | ||
2a47fa45 JF |
5801 | /* PF holds first pool slot */ |
5802 | set_bit(0, &adapter->fwd_bitmask); | |
9a799d71 AK |
5803 | set_bit(__IXGBE_DOWN, &adapter->state); |
5804 | ||
5805 | return 0; | |
5806 | } | |
5807 | ||
5808 | /** | |
5809 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 5810 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5811 | * |
5812 | * Return 0 on success, negative on failure | |
5813 | **/ | |
b6ec895e | 5814 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5815 | { |
b6ec895e | 5816 | struct device *dev = tx_ring->dev; |
de88eeeb | 5817 | int orig_node = dev_to_node(dev); |
ca8dfe25 | 5818 | int ring_node = -1; |
9a799d71 AK |
5819 | int size; |
5820 | ||
3a581073 | 5821 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
5822 | |
5823 | if (tx_ring->q_vector) | |
ca8dfe25 | 5824 | ring_node = tx_ring->q_vector->numa_node; |
de88eeeb | 5825 | |
ca8dfe25 | 5826 | tx_ring->tx_buffer_info = vzalloc_node(size, ring_node); |
1a6c14a2 | 5827 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 5828 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
5829 | if (!tx_ring->tx_buffer_info) |
5830 | goto err; | |
9a799d71 | 5831 | |
827da44c JS |
5832 | u64_stats_init(&tx_ring->syncp); |
5833 | ||
9a799d71 | 5834 | /* round up to nearest 4K */ |
12207e49 | 5835 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 5836 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 5837 | |
ca8dfe25 | 5838 | set_dev_node(dev, ring_node); |
de88eeeb AD |
5839 | tx_ring->desc = dma_alloc_coherent(dev, |
5840 | tx_ring->size, | |
5841 | &tx_ring->dma, | |
5842 | GFP_KERNEL); | |
5843 | set_dev_node(dev, orig_node); | |
5844 | if (!tx_ring->desc) | |
5845 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
5846 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
5847 | if (!tx_ring->desc) |
5848 | goto err; | |
9a799d71 | 5849 | |
3a581073 JB |
5850 | tx_ring->next_to_use = 0; |
5851 | tx_ring->next_to_clean = 0; | |
9a799d71 | 5852 | return 0; |
e01c31a5 JB |
5853 | |
5854 | err: | |
5855 | vfree(tx_ring->tx_buffer_info); | |
5856 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 5857 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 5858 | return -ENOMEM; |
9a799d71 AK |
5859 | } |
5860 | ||
69888674 AD |
5861 | /** |
5862 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
5863 | * @adapter: board private structure | |
5864 | * | |
5865 | * If this function returns with an error, then it's possible one or | |
5866 | * more of the rings is populated (while the rest are not). It is the | |
5867 | * callers duty to clean those orphaned rings. | |
5868 | * | |
5869 | * Return 0 on success, negative on failure | |
5870 | **/ | |
5871 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
5872 | { | |
5873 | int i, err = 0; | |
5874 | ||
5875 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 5876 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
5877 | if (!err) |
5878 | continue; | |
de3d5b94 | 5879 | |
396e799c | 5880 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
de3d5b94 | 5881 | goto err_setup_tx; |
69888674 AD |
5882 | } |
5883 | ||
de3d5b94 AD |
5884 | return 0; |
5885 | err_setup_tx: | |
5886 | /* rewind the index freeing the rings as we go */ | |
5887 | while (i--) | |
5888 | ixgbe_free_tx_resources(adapter->tx_ring[i]); | |
69888674 AD |
5889 | return err; |
5890 | } | |
5891 | ||
9a799d71 AK |
5892 | /** |
5893 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 5894 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5895 | * |
5896 | * Returns 0 on success, negative on failure | |
5897 | **/ | |
b6ec895e | 5898 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5899 | { |
b6ec895e | 5900 | struct device *dev = rx_ring->dev; |
de88eeeb | 5901 | int orig_node = dev_to_node(dev); |
ca8dfe25 | 5902 | int ring_node = -1; |
021230d4 | 5903 | int size; |
9a799d71 | 5904 | |
3a581073 | 5905 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
5906 | |
5907 | if (rx_ring->q_vector) | |
ca8dfe25 | 5908 | ring_node = rx_ring->q_vector->numa_node; |
de88eeeb | 5909 | |
ca8dfe25 | 5910 | rx_ring->rx_buffer_info = vzalloc_node(size, ring_node); |
1a6c14a2 | 5911 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 5912 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
5913 | if (!rx_ring->rx_buffer_info) |
5914 | goto err; | |
9a799d71 | 5915 | |
827da44c JS |
5916 | u64_stats_init(&rx_ring->syncp); |
5917 | ||
9a799d71 | 5918 | /* Round up to nearest 4K */ |
3a581073 JB |
5919 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5920 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5921 | |
ca8dfe25 | 5922 | set_dev_node(dev, ring_node); |
de88eeeb AD |
5923 | rx_ring->desc = dma_alloc_coherent(dev, |
5924 | rx_ring->size, | |
5925 | &rx_ring->dma, | |
5926 | GFP_KERNEL); | |
5927 | set_dev_node(dev, orig_node); | |
5928 | if (!rx_ring->desc) | |
5929 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
5930 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
5931 | if (!rx_ring->desc) |
5932 | goto err; | |
9a799d71 | 5933 | |
3a581073 JB |
5934 | rx_ring->next_to_clean = 0; |
5935 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
5936 | |
5937 | return 0; | |
b6ec895e AD |
5938 | err: |
5939 | vfree(rx_ring->rx_buffer_info); | |
5940 | rx_ring->rx_buffer_info = NULL; | |
5941 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 5942 | return -ENOMEM; |
9a799d71 AK |
5943 | } |
5944 | ||
69888674 AD |
5945 | /** |
5946 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5947 | * @adapter: board private structure | |
5948 | * | |
5949 | * If this function returns with an error, then it's possible one or | |
5950 | * more of the rings is populated (while the rest are not). It is the | |
5951 | * callers duty to clean those orphaned rings. | |
5952 | * | |
5953 | * Return 0 on success, negative on failure | |
5954 | **/ | |
69888674 AD |
5955 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
5956 | { | |
5957 | int i, err = 0; | |
5958 | ||
5959 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 5960 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
5961 | if (!err) |
5962 | continue; | |
de3d5b94 | 5963 | |
396e799c | 5964 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
de3d5b94 | 5965 | goto err_setup_rx; |
69888674 AD |
5966 | } |
5967 | ||
7c8ae65a AD |
5968 | #ifdef IXGBE_FCOE |
5969 | err = ixgbe_setup_fcoe_ddp_resources(adapter); | |
5970 | if (!err) | |
5971 | #endif | |
5972 | return 0; | |
de3d5b94 AD |
5973 | err_setup_rx: |
5974 | /* rewind the index freeing the rings as we go */ | |
5975 | while (i--) | |
5976 | ixgbe_free_rx_resources(adapter->rx_ring[i]); | |
69888674 AD |
5977 | return err; |
5978 | } | |
5979 | ||
9a799d71 AK |
5980 | /** |
5981 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
5982 | * @tx_ring: Tx descriptor ring for a specific queue |
5983 | * | |
5984 | * Free all transmit software resources | |
5985 | **/ | |
b6ec895e | 5986 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5987 | { |
b6ec895e | 5988 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
5989 | |
5990 | vfree(tx_ring->tx_buffer_info); | |
5991 | tx_ring->tx_buffer_info = NULL; | |
5992 | ||
b6ec895e AD |
5993 | /* if not set, then don't free */ |
5994 | if (!tx_ring->desc) | |
5995 | return; | |
5996 | ||
5997 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
5998 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
5999 | |
6000 | tx_ring->desc = NULL; | |
6001 | } | |
6002 | ||
6003 | /** | |
6004 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
6005 | * @adapter: board private structure | |
6006 | * | |
6007 | * Free all transmit software resources | |
6008 | **/ | |
6009 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
6010 | { | |
6011 | int i; | |
6012 | ||
6013 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 6014 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 6015 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
6016 | } |
6017 | ||
6018 | /** | |
b4617240 | 6019 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
6020 | * @rx_ring: ring to clean the resources from |
6021 | * | |
6022 | * Free all receive software resources | |
6023 | **/ | |
b6ec895e | 6024 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 6025 | { |
b6ec895e | 6026 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
6027 | |
6028 | vfree(rx_ring->rx_buffer_info); | |
6029 | rx_ring->rx_buffer_info = NULL; | |
6030 | ||
b6ec895e AD |
6031 | /* if not set, then don't free */ |
6032 | if (!rx_ring->desc) | |
6033 | return; | |
6034 | ||
6035 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
6036 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
6037 | |
6038 | rx_ring->desc = NULL; | |
6039 | } | |
6040 | ||
6041 | /** | |
6042 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
6043 | * @adapter: board private structure | |
6044 | * | |
6045 | * Free all receive software resources | |
6046 | **/ | |
6047 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
6048 | { | |
6049 | int i; | |
6050 | ||
7c8ae65a AD |
6051 | #ifdef IXGBE_FCOE |
6052 | ixgbe_free_fcoe_ddp_resources(adapter); | |
6053 | ||
6054 | #endif | |
9a799d71 | 6055 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 6056 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 6057 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
6058 | } |
6059 | ||
9a799d71 AK |
6060 | /** |
6061 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
6062 | * @netdev: network interface device structure | |
6063 | * @new_mtu: new value for maximum frame size | |
6064 | * | |
6065 | * Returns 0 on success, negative on failure | |
6066 | **/ | |
6067 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
6068 | { | |
6069 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6070 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
6071 | ||
42c783c5 | 6072 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
6073 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
6074 | return -EINVAL; | |
6075 | ||
6076 | /* | |
872844dd AD |
6077 | * For 82599EB we cannot allow legacy VFs to enable their receive |
6078 | * paths when MTU greater than 1500 is configured. So display a | |
6079 | * warning that legacy VFs will be disabled. | |
655309e9 AD |
6080 | */ |
6081 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
6082 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
c560451c | 6083 | (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN))) |
872844dd | 6084 | e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n"); |
9a799d71 | 6085 | |
396e799c | 6086 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 6087 | |
021230d4 | 6088 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
6089 | netdev->mtu = new_mtu; |
6090 | ||
d4f80882 AV |
6091 | if (netif_running(netdev)) |
6092 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
6093 | |
6094 | return 0; | |
6095 | } | |
6096 | ||
6097 | /** | |
6098 | * ixgbe_open - Called when a network interface is made active | |
6099 | * @netdev: network interface device structure | |
6100 | * | |
6101 | * Returns 0 on success, negative value on failure | |
6102 | * | |
6103 | * The open entry point is called when a network interface is made | |
6104 | * active by the system (IFF_UP). At this point all resources needed | |
6105 | * for transmit and receive operations are allocated, the interrupt | |
6106 | * handler is registered with the OS, the watchdog timer is started, | |
6107 | * and the stack is notified that the interface is ready. | |
6108 | **/ | |
6c211fe1 | 6109 | int ixgbe_open(struct net_device *netdev) |
9a799d71 AK |
6110 | { |
6111 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
961fac88 | 6112 | struct ixgbe_hw *hw = &adapter->hw; |
2a47fa45 | 6113 | int err, queues; |
4bebfaa5 AK |
6114 | |
6115 | /* disallow open during test */ | |
6116 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
6117 | return -EBUSY; | |
9a799d71 | 6118 | |
54386467 JB |
6119 | netif_carrier_off(netdev); |
6120 | ||
9a799d71 AK |
6121 | /* allocate transmit descriptors */ |
6122 | err = ixgbe_setup_all_tx_resources(adapter); | |
6123 | if (err) | |
6124 | goto err_setup_tx; | |
6125 | ||
9a799d71 AK |
6126 | /* allocate receive descriptors */ |
6127 | err = ixgbe_setup_all_rx_resources(adapter); | |
6128 | if (err) | |
6129 | goto err_setup_rx; | |
6130 | ||
6131 | ixgbe_configure(adapter); | |
6132 | ||
021230d4 | 6133 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
6134 | if (err) |
6135 | goto err_req_irq; | |
6136 | ||
ac802f5d | 6137 | /* Notify the stack of the actual queue counts. */ |
2a47fa45 JF |
6138 | if (adapter->num_rx_pools > 1) |
6139 | queues = adapter->num_rx_queues_per_pool; | |
6140 | else | |
6141 | queues = adapter->num_tx_queues; | |
6142 | ||
6143 | err = netif_set_real_num_tx_queues(netdev, queues); | |
ac802f5d AD |
6144 | if (err) |
6145 | goto err_set_queues; | |
6146 | ||
2a47fa45 JF |
6147 | if (adapter->num_rx_pools > 1 && |
6148 | adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES) | |
6149 | queues = IXGBE_MAX_L2A_QUEUES; | |
6150 | else | |
6151 | queues = adapter->num_rx_queues; | |
6152 | err = netif_set_real_num_rx_queues(netdev, queues); | |
ac802f5d AD |
6153 | if (err) |
6154 | goto err_set_queues; | |
6155 | ||
1a71ab24 | 6156 | ixgbe_ptp_init(adapter); |
1a71ab24 | 6157 | |
c7ccde0f | 6158 | ixgbe_up_complete(adapter); |
9a799d71 | 6159 | |
67359c3c MR |
6160 | ixgbe_clear_vxlan_port(adapter); |
6161 | #ifdef CONFIG_IXGBE_VXLAN | |
3f207800 | 6162 | vxlan_get_rx_port(netdev); |
3f207800 | 6163 | #endif |
67359c3c | 6164 | |
9a799d71 AK |
6165 | return 0; |
6166 | ||
ac802f5d AD |
6167 | err_set_queues: |
6168 | ixgbe_free_irq(adapter); | |
9a799d71 | 6169 | err_req_irq: |
a20a1199 | 6170 | ixgbe_free_all_rx_resources(adapter); |
961fac88 DS |
6171 | if (hw->phy.ops.set_phy_power && !adapter->wol) |
6172 | hw->phy.ops.set_phy_power(&adapter->hw, false); | |
de3d5b94 | 6173 | err_setup_rx: |
a20a1199 | 6174 | ixgbe_free_all_tx_resources(adapter); |
de3d5b94 | 6175 | err_setup_tx: |
9a799d71 AK |
6176 | ixgbe_reset(adapter); |
6177 | ||
6178 | return err; | |
6179 | } | |
6180 | ||
a0cccce2 JK |
6181 | static void ixgbe_close_suspend(struct ixgbe_adapter *adapter) |
6182 | { | |
6183 | ixgbe_ptp_suspend(adapter); | |
6184 | ||
6ac74394 DS |
6185 | if (adapter->hw.phy.ops.enter_lplu) { |
6186 | adapter->hw.phy.reset_disable = true; | |
6187 | ixgbe_down(adapter); | |
6188 | adapter->hw.phy.ops.enter_lplu(&adapter->hw); | |
6189 | adapter->hw.phy.reset_disable = false; | |
6190 | } else { | |
6191 | ixgbe_down(adapter); | |
6192 | } | |
6193 | ||
a0cccce2 JK |
6194 | ixgbe_free_irq(adapter); |
6195 | ||
6196 | ixgbe_free_all_tx_resources(adapter); | |
6197 | ixgbe_free_all_rx_resources(adapter); | |
6198 | } | |
6199 | ||
9a799d71 AK |
6200 | /** |
6201 | * ixgbe_close - Disables a network interface | |
6202 | * @netdev: network interface device structure | |
6203 | * | |
6204 | * Returns 0, this is not allowed to fail | |
6205 | * | |
6206 | * The close entry point is called when an interface is de-activated | |
6207 | * by the OS. The hardware is still under the drivers control, but | |
6208 | * needs to be disabled. A global MAC reset is issued to stop the | |
6209 | * hardware, and all transmit and receive resources are freed. | |
6210 | **/ | |
6c211fe1 | 6211 | int ixgbe_close(struct net_device *netdev) |
9a799d71 AK |
6212 | { |
6213 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 | 6214 | |
1a71ab24 | 6215 | ixgbe_ptp_stop(adapter); |
1a71ab24 | 6216 | |
a0cccce2 | 6217 | ixgbe_close_suspend(adapter); |
9a799d71 | 6218 | |
e4911d57 AD |
6219 | ixgbe_fdir_filter_exit(adapter); |
6220 | ||
5eba3699 | 6221 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
6222 | |
6223 | return 0; | |
6224 | } | |
6225 | ||
b3c8b4ba AD |
6226 | #ifdef CONFIG_PM |
6227 | static int ixgbe_resume(struct pci_dev *pdev) | |
6228 | { | |
c60fbb00 AD |
6229 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6230 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
6231 | u32 err; |
6232 | ||
0391bbe3 | 6233 | adapter->hw.hw_addr = adapter->io_addr; |
b3c8b4ba AD |
6234 | pci_set_power_state(pdev, PCI_D0); |
6235 | pci_restore_state(pdev); | |
656ab817 DS |
6236 | /* |
6237 | * pci_restore_state clears dev->state_saved so call | |
6238 | * pci_save_state to restore it. | |
6239 | */ | |
6240 | pci_save_state(pdev); | |
9ce77666 | 6241 | |
6242 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 6243 | if (err) { |
849c4542 | 6244 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
6245 | return err; |
6246 | } | |
4e857c58 | 6247 | smp_mb__before_atomic(); |
41c62843 | 6248 | clear_bit(__IXGBE_DISABLED, &adapter->state); |
b3c8b4ba AD |
6249 | pci_set_master(pdev); |
6250 | ||
dd4d8ca6 | 6251 | pci_wake_from_d3(pdev, false); |
b3c8b4ba | 6252 | |
b3c8b4ba AD |
6253 | ixgbe_reset(adapter); |
6254 | ||
495dce12 WJP |
6255 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6256 | ||
ac802f5d AD |
6257 | rtnl_lock(); |
6258 | err = ixgbe_init_interrupt_scheme(adapter); | |
6259 | if (!err && netif_running(netdev)) | |
c60fbb00 | 6260 | err = ixgbe_open(netdev); |
ac802f5d AD |
6261 | |
6262 | rtnl_unlock(); | |
6263 | ||
6264 | if (err) | |
6265 | return err; | |
b3c8b4ba AD |
6266 | |
6267 | netif_device_attach(netdev); | |
6268 | ||
6269 | return 0; | |
6270 | } | |
b3c8b4ba | 6271 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
6272 | |
6273 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 6274 | { |
c60fbb00 AD |
6275 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6276 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
6277 | struct ixgbe_hw *hw = &adapter->hw; |
6278 | u32 ctrl, fctrl; | |
6279 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
6280 | #ifdef CONFIG_PM |
6281 | int retval = 0; | |
6282 | #endif | |
6283 | ||
6284 | netif_device_detach(netdev); | |
6285 | ||
499ab5cc | 6286 | rtnl_lock(); |
a0cccce2 JK |
6287 | if (netif_running(netdev)) |
6288 | ixgbe_close_suspend(adapter); | |
499ab5cc | 6289 | rtnl_unlock(); |
b3c8b4ba | 6290 | |
5f5ae6fc AD |
6291 | ixgbe_clear_interrupt_scheme(adapter); |
6292 | ||
b3c8b4ba AD |
6293 | #ifdef CONFIG_PM |
6294 | retval = pci_save_state(pdev); | |
6295 | if (retval) | |
6296 | return retval; | |
4df10466 | 6297 | |
b3c8b4ba | 6298 | #endif |
f4f1040a JK |
6299 | if (hw->mac.ops.stop_link_on_d3) |
6300 | hw->mac.ops.stop_link_on_d3(hw); | |
6301 | ||
e8e26350 PW |
6302 | if (wufc) { |
6303 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 6304 | |
ec74a471 ET |
6305 | /* enable the optics for 82599 SFP+ fiber as we can WoL */ |
6306 | if (hw->mac.ops.enable_tx_laser) | |
c509e754 DS |
6307 | hw->mac.ops.enable_tx_laser(hw); |
6308 | ||
e8e26350 PW |
6309 | /* turn on all-multi mode if wake on multicast is enabled */ |
6310 | if (wufc & IXGBE_WUFC_MC) { | |
6311 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
6312 | fctrl |= IXGBE_FCTRL_MPE; | |
6313 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
6314 | } | |
6315 | ||
6316 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
6317 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
6318 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
6319 | ||
6320 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
6321 | } else { | |
6322 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
6323 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
6324 | } | |
6325 | ||
bd508178 AD |
6326 | switch (hw->mac.type) { |
6327 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 6328 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
6329 | break; |
6330 | case ixgbe_mac_82599EB: | |
b93a2226 | 6331 | case ixgbe_mac_X540: |
9a75a1ac DS |
6332 | case ixgbe_mac_X550: |
6333 | case ixgbe_mac_X550EM_x: | |
49425dfc | 6334 | case ixgbe_mac_x550em_a: |
bd508178 AD |
6335 | pci_wake_from_d3(pdev, !!wufc); |
6336 | break; | |
6337 | default: | |
6338 | break; | |
6339 | } | |
b3c8b4ba | 6340 | |
9d8d05ae | 6341 | *enable_wake = !!wufc; |
961fac88 DS |
6342 | if (hw->phy.ops.set_phy_power && !*enable_wake) |
6343 | hw->phy.ops.set_phy_power(hw, false); | |
9d8d05ae | 6344 | |
b3c8b4ba AD |
6345 | ixgbe_release_hw_control(adapter); |
6346 | ||
41c62843 MR |
6347 | if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) |
6348 | pci_disable_device(pdev); | |
b3c8b4ba | 6349 | |
9d8d05ae RW |
6350 | return 0; |
6351 | } | |
6352 | ||
6353 | #ifdef CONFIG_PM | |
6354 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
6355 | { | |
6356 | int retval; | |
6357 | bool wake; | |
6358 | ||
6359 | retval = __ixgbe_shutdown(pdev, &wake); | |
6360 | if (retval) | |
6361 | return retval; | |
6362 | ||
6363 | if (wake) { | |
6364 | pci_prepare_to_sleep(pdev); | |
6365 | } else { | |
6366 | pci_wake_from_d3(pdev, false); | |
6367 | pci_set_power_state(pdev, PCI_D3hot); | |
6368 | } | |
b3c8b4ba AD |
6369 | |
6370 | return 0; | |
6371 | } | |
9d8d05ae | 6372 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
6373 | |
6374 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
6375 | { | |
9d8d05ae RW |
6376 | bool wake; |
6377 | ||
6378 | __ixgbe_shutdown(pdev, &wake); | |
6379 | ||
6380 | if (system_state == SYSTEM_POWER_OFF) { | |
6381 | pci_wake_from_d3(pdev, wake); | |
6382 | pci_set_power_state(pdev, PCI_D3hot); | |
6383 | } | |
b3c8b4ba AD |
6384 | } |
6385 | ||
9a799d71 AK |
6386 | /** |
6387 | * ixgbe_update_stats - Update the board statistics counters. | |
6388 | * @adapter: board private structure | |
6389 | **/ | |
6390 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
6391 | { | |
2d86f139 | 6392 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 6393 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 6394 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
6395 | u64 total_mpc = 0; |
6396 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
6397 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
6398 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 6399 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
9a799d71 | 6400 | |
d08935c2 DS |
6401 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
6402 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6403 | return; | |
6404 | ||
94b982b2 | 6405 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 6406 | u64 rsc_count = 0; |
94b982b2 | 6407 | u64 rsc_flush = 0; |
94b982b2 | 6408 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
6409 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
6410 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
6411 | } |
6412 | adapter->rsc_total_count = rsc_count; | |
6413 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
6414 | } |
6415 | ||
5b7da515 AD |
6416 | for (i = 0; i < adapter->num_rx_queues; i++) { |
6417 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
6418 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
6419 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
6420 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 6421 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
6422 | bytes += rx_ring->stats.bytes; |
6423 | packets += rx_ring->stats.packets; | |
6424 | } | |
6425 | adapter->non_eop_descs = non_eop_descs; | |
6426 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
6427 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 6428 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
6429 | netdev->stats.rx_bytes = bytes; |
6430 | netdev->stats.rx_packets = packets; | |
6431 | ||
6432 | bytes = 0; | |
6433 | packets = 0; | |
7ca3bc58 | 6434 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
6435 | for (i = 0; i < adapter->num_tx_queues; i++) { |
6436 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
6437 | restart_queue += tx_ring->tx_stats.restart_queue; | |
6438 | tx_busy += tx_ring->tx_stats.tx_busy; | |
6439 | bytes += tx_ring->stats.bytes; | |
6440 | packets += tx_ring->stats.packets; | |
6441 | } | |
eb985f09 | 6442 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
6443 | adapter->tx_busy = tx_busy; |
6444 | netdev->stats.tx_bytes = bytes; | |
6445 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 6446 | |
7ca647bd | 6447 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
6448 | |
6449 | /* 8 register reads */ | |
6f11eef7 AV |
6450 | for (i = 0; i < 8; i++) { |
6451 | /* for packet buffers not used, the register should read 0 */ | |
6452 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
6453 | missed_rx += mpc; | |
7ca647bd JP |
6454 | hwstats->mpc[i] += mpc; |
6455 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
6456 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
6457 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
6458 | switch (hw->mac.type) { |
6459 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
6460 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
6461 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
6462 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
6463 | hwstats->pxonrxc[i] += |
6464 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
6465 | break; |
6466 | case ixgbe_mac_82599EB: | |
b93a2226 | 6467 | case ixgbe_mac_X540: |
9a75a1ac DS |
6468 | case ixgbe_mac_X550: |
6469 | case ixgbe_mac_X550EM_x: | |
49425dfc | 6470 | case ixgbe_mac_x550em_a: |
bd508178 AD |
6471 | hwstats->pxonrxc[i] += |
6472 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
6473 | break; |
6474 | default: | |
6475 | break; | |
e8e26350 | 6476 | } |
6f11eef7 | 6477 | } |
1a70db4b ET |
6478 | |
6479 | /*16 register reads */ | |
6480 | for (i = 0; i < 16; i++) { | |
6481 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
6482 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
6483 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
9a75a1ac DS |
6484 | (hw->mac.type == ixgbe_mac_X540) || |
6485 | (hw->mac.type == ixgbe_mac_X550) || | |
49425dfc MR |
6486 | (hw->mac.type == ixgbe_mac_X550EM_x) || |
6487 | (hw->mac.type == ixgbe_mac_x550em_a)) { | |
1a70db4b ET |
6488 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); |
6489 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
6490 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
6491 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
6492 | } | |
6493 | } | |
6494 | ||
7ca647bd | 6495 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 6496 | /* work around hardware counting issue */ |
7ca647bd | 6497 | hwstats->gprc -= missed_rx; |
6f11eef7 | 6498 | |
c84d324c JF |
6499 | ixgbe_update_xoff_received(adapter); |
6500 | ||
6f11eef7 | 6501 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
6502 | switch (hw->mac.type) { |
6503 | case ixgbe_mac_82598EB: | |
6504 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
6505 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
6506 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
6507 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
6508 | break; | |
b93a2226 | 6509 | case ixgbe_mac_X540: |
9a75a1ac DS |
6510 | case ixgbe_mac_X550: |
6511 | case ixgbe_mac_X550EM_x: | |
49425dfc | 6512 | case ixgbe_mac_x550em_a: |
9a75a1ac | 6513 | /* OS2BMC stats are X540 and later */ |
58f6bcf9 ET |
6514 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); |
6515 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
6516 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
6517 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
6518 | case ixgbe_mac_82599EB: | |
a4d4f629 AD |
6519 | for (i = 0; i < 16; i++) |
6520 | adapter->hw_rx_no_dma_resources += | |
6521 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
7ca647bd | 6522 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 6523 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 6524 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 6525 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 6526 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 6527 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 6528 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
6529 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
6530 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 6531 | #ifdef IXGBE_FCOE |
7ca647bd JP |
6532 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
6533 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
6534 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
6535 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
6536 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
6537 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc | 6538 | /* Add up per cpu counters for total ddp aloc fail */ |
5a1ee270 AD |
6539 | if (adapter->fcoe.ddp_pool) { |
6540 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
6541 | struct ixgbe_fcoe_ddp_pool *ddp_pool; | |
6542 | unsigned int cpu; | |
6543 | u64 noddp = 0, noddp_ext_buff = 0; | |
7b859ebc | 6544 | for_each_possible_cpu(cpu) { |
5a1ee270 AD |
6545 | ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu); |
6546 | noddp += ddp_pool->noddp; | |
6547 | noddp_ext_buff += ddp_pool->noddp_ext_buff; | |
7b859ebc | 6548 | } |
5a1ee270 AD |
6549 | hwstats->fcoe_noddp = noddp; |
6550 | hwstats->fcoe_noddp_ext_buff = noddp_ext_buff; | |
7b859ebc | 6551 | } |
6d45522c | 6552 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
6553 | break; |
6554 | default: | |
6555 | break; | |
e8e26350 | 6556 | } |
9a799d71 | 6557 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
6558 | hwstats->bprc += bprc; |
6559 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 6560 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
6561 | hwstats->mprc -= bprc; |
6562 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
6563 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
6564 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
6565 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
6566 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
6567 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
6568 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
6569 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 6570 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 6571 | hwstats->lxontxc += lxon; |
6f11eef7 | 6572 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 6573 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
6574 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
6575 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
6576 | /* |
6577 | * 82598 errata - tx of flow control packets is included in tx counters | |
6578 | */ | |
6579 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
6580 | hwstats->gptc -= xon_off_tot; |
6581 | hwstats->mptc -= xon_off_tot; | |
6582 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
6583 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
6584 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
6585 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
6586 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
6587 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6588 | hwstats->ptc64 -= xon_off_tot; | |
6589 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
6590 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
6591 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
6592 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
6593 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
6594 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
6595 | |
6596 | /* Fill out the OS statistics structure */ | |
7ca647bd | 6597 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
6598 | |
6599 | /* Rx Errors */ | |
7ca647bd | 6600 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 6601 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
6602 | netdev->stats.rx_length_errors = hwstats->rlec; |
6603 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 6604 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
6605 | } |
6606 | ||
6607 | /** | |
d034acf1 | 6608 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
49ce9c2c | 6609 | * @adapter: pointer to the device adapter structure |
9a799d71 | 6610 | **/ |
d034acf1 | 6611 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 6612 | { |
cf8280ee | 6613 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 6614 | int i; |
cf8280ee | 6615 | |
d034acf1 AD |
6616 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
6617 | return; | |
6618 | ||
6619 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 6620 | |
d034acf1 | 6621 | /* if interface is down do nothing */ |
fe49f04a | 6622 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
6623 | return; |
6624 | ||
6625 | /* do nothing if we are not using signature filters */ | |
6626 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
6627 | return; | |
6628 | ||
6629 | adapter->fdir_overflow++; | |
6630 | ||
93c52dd0 AD |
6631 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
6632 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6633 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
e7cf745b | 6634 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
6635 | /* re-enable flow director interrupts */ |
6636 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
6637 | } else { |
6638 | e_err(probe, "failed to finish FDIR re-initialization, " | |
6639 | "ignored adding FDIR ATR filters\n"); | |
6640 | } | |
93c52dd0 AD |
6641 | } |
6642 | ||
6643 | /** | |
6644 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
49ce9c2c | 6645 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
6646 | * |
6647 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 6648 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 6649 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 6650 | * determine if a hang has occurred. |
93c52dd0 AD |
6651 | */ |
6652 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 6653 | { |
cf8280ee | 6654 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
6655 | u64 eics = 0; |
6656 | int i; | |
cf8280ee | 6657 | |
09f40aed | 6658 | /* If we're down, removing or resetting, just bail */ |
93c52dd0 | 6659 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 6660 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
93c52dd0 AD |
6661 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
6662 | return; | |
22d5a71b | 6663 | |
93c52dd0 AD |
6664 | /* Force detection of hung controller */ |
6665 | if (netif_carrier_ok(adapter->netdev)) { | |
6666 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6667 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
6668 | } | |
22d5a71b | 6669 | |
fe49f04a AD |
6670 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
6671 | /* | |
6672 | * for legacy and MSI interrupts don't set any bits | |
6673 | * that are enabled for EIAM, because this operation | |
6674 | * would set *both* EIMS and EICS for any bit in EIAM | |
6675 | */ | |
6676 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
6677 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
6678 | } else { |
6679 | /* get one bit for every active tx/rx interrupt vector */ | |
49c7ffbe | 6680 | for (i = 0; i < adapter->num_q_vectors; i++) { |
93c52dd0 | 6681 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; |
efe3d3c8 | 6682 | if (qv->rx.ring || qv->tx.ring) |
b4f47a48 | 6683 | eics |= BIT_ULL(i); |
93c52dd0 | 6684 | } |
cf8280ee | 6685 | } |
9a799d71 | 6686 | |
93c52dd0 | 6687 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a | 6688 | ixgbe_irq_rearm_queues(adapter, eics); |
cf8280ee JB |
6689 | } |
6690 | ||
e8e26350 | 6691 | /** |
93c52dd0 | 6692 | * ixgbe_watchdog_update_link - update the link status |
49ce9c2c BH |
6693 | * @adapter: pointer to the device adapter structure |
6694 | * @link_speed: pointer to a u32 to store the link_speed | |
e8e26350 | 6695 | **/ |
93c52dd0 | 6696 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 6697 | { |
e8e26350 | 6698 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
6699 | u32 link_speed = adapter->link_speed; |
6700 | bool link_up = adapter->link_up; | |
041441d0 | 6701 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; |
e8e26350 | 6702 | |
93c52dd0 AD |
6703 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
6704 | return; | |
6705 | ||
6706 | if (hw->mac.ops.check_link) { | |
6707 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 6708 | } else { |
93c52dd0 AD |
6709 | /* always assume link is up, if no check link function */ |
6710 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
6711 | link_up = true; | |
c4cf55e5 | 6712 | } |
041441d0 | 6713 | |
4319a797 DS |
6714 | /* If Crosstalk fix enabled do the sanity check of making sure |
6715 | * the SFP+ cage is empty. | |
6716 | */ | |
6717 | if (adapter->need_crosstalk_fix) { | |
6718 | u32 sfp_cage_full; | |
6719 | ||
6720 | sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & | |
6721 | IXGBE_ESDP_SDP2; | |
6722 | if (ixgbe_is_sfp(hw) && link_up && !sfp_cage_full) | |
6723 | link_up = false; | |
6724 | } | |
6725 | ||
041441d0 AD |
6726 | if (adapter->ixgbe_ieee_pfc) |
6727 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
6728 | ||
3ebe8fde | 6729 | if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { |
041441d0 | 6730 | hw->mac.ops.fc_enable(hw); |
3ebe8fde AD |
6731 | ixgbe_set_rx_drop_en(adapter); |
6732 | } | |
93c52dd0 AD |
6733 | |
6734 | if (link_up || | |
6735 | time_after(jiffies, (adapter->link_check_timeout + | |
6736 | IXGBE_TRY_LINK_TIMEOUT))) { | |
6737 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
6738 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
6739 | IXGBE_WRITE_FLUSH(hw); | |
6740 | } | |
6741 | ||
6742 | adapter->link_up = link_up; | |
6743 | adapter->link_speed = link_speed; | |
e8e26350 PW |
6744 | } |
6745 | ||
107d3018 AD |
6746 | static void ixgbe_update_default_up(struct ixgbe_adapter *adapter) |
6747 | { | |
6748 | #ifdef CONFIG_IXGBE_DCB | |
6749 | struct net_device *netdev = adapter->netdev; | |
6750 | struct dcb_app app = { | |
6751 | .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE, | |
6752 | .protocol = 0, | |
6753 | }; | |
6754 | u8 up = 0; | |
6755 | ||
6756 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE) | |
6757 | up = dcb_ieee_getapp_mask(netdev, &app); | |
6758 | ||
6759 | adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0; | |
6760 | #endif | |
6761 | } | |
6762 | ||
e8e26350 | 6763 | /** |
93c52dd0 AD |
6764 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
6765 | * print link up message | |
49ce9c2c | 6766 | * @adapter: pointer to the device adapter structure |
e8e26350 | 6767 | **/ |
93c52dd0 | 6768 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 6769 | { |
93c52dd0 | 6770 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 6771 | struct ixgbe_hw *hw = &adapter->hw; |
cdc04dcc ET |
6772 | struct net_device *upper; |
6773 | struct list_head *iter; | |
93c52dd0 | 6774 | u32 link_speed = adapter->link_speed; |
454adb00 | 6775 | const char *speed_str; |
93c52dd0 | 6776 | bool flow_rx, flow_tx; |
e8e26350 | 6777 | |
93c52dd0 AD |
6778 | /* only continue if link was previously down */ |
6779 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 6780 | return; |
63d6e1d8 | 6781 | |
93c52dd0 | 6782 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 6783 | |
93c52dd0 AD |
6784 | switch (hw->mac.type) { |
6785 | case ixgbe_mac_82598EB: { | |
6786 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
6787 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
6788 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
6789 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
6790 | } | |
6791 | break; | |
6792 | case ixgbe_mac_X540: | |
9a75a1ac DS |
6793 | case ixgbe_mac_X550: |
6794 | case ixgbe_mac_X550EM_x: | |
49425dfc | 6795 | case ixgbe_mac_x550em_a: |
93c52dd0 AD |
6796 | case ixgbe_mac_82599EB: { |
6797 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
6798 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
6799 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
6800 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
6801 | } | |
6802 | break; | |
6803 | default: | |
6804 | flow_tx = false; | |
6805 | flow_rx = false; | |
6806 | break; | |
e8e26350 | 6807 | } |
3a6a4eda | 6808 | |
6cb562d6 JK |
6809 | adapter->last_rx_ptp_check = jiffies; |
6810 | ||
8fecf67c | 6811 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 6812 | ixgbe_ptp_start_cyclecounter(adapter); |
3a6a4eda | 6813 | |
454adb00 MR |
6814 | switch (link_speed) { |
6815 | case IXGBE_LINK_SPEED_10GB_FULL: | |
6816 | speed_str = "10 Gbps"; | |
6817 | break; | |
6818 | case IXGBE_LINK_SPEED_2_5GB_FULL: | |
6819 | speed_str = "2.5 Gbps"; | |
6820 | break; | |
6821 | case IXGBE_LINK_SPEED_1GB_FULL: | |
6822 | speed_str = "1 Gbps"; | |
6823 | break; | |
6824 | case IXGBE_LINK_SPEED_100_FULL: | |
6825 | speed_str = "100 Mbps"; | |
6826 | break; | |
6827 | default: | |
6828 | speed_str = "unknown speed"; | |
6829 | break; | |
6830 | } | |
6831 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str, | |
93c52dd0 AD |
6832 | ((flow_rx && flow_tx) ? "RX/TX" : |
6833 | (flow_rx ? "RX" : | |
6834 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 6835 | |
93c52dd0 | 6836 | netif_carrier_on(netdev); |
93c52dd0 | 6837 | ixgbe_check_vf_rate_limit(adapter); |
befa2af7 | 6838 | |
cdc04dcc ET |
6839 | /* enable transmits */ |
6840 | netif_tx_wake_all_queues(adapter->netdev); | |
6841 | ||
6842 | /* enable any upper devices */ | |
6843 | rtnl_lock(); | |
6844 | netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { | |
6845 | if (netif_is_macvlan(upper)) { | |
6846 | struct macvlan_dev *vlan = netdev_priv(upper); | |
6847 | ||
6848 | if (vlan->fwd_priv) | |
6849 | netif_tx_wake_all_queues(upper); | |
6850 | } | |
6851 | } | |
6852 | rtnl_unlock(); | |
6853 | ||
107d3018 AD |
6854 | /* update the default user priority for VFs */ |
6855 | ixgbe_update_default_up(adapter); | |
6856 | ||
befa2af7 AD |
6857 | /* ping all the active vfs to let them know link has changed */ |
6858 | ixgbe_ping_all_vfs(adapter); | |
e8e26350 PW |
6859 | } |
6860 | ||
c4cf55e5 | 6861 | /** |
93c52dd0 AD |
6862 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
6863 | * print link down message | |
49ce9c2c | 6864 | * @adapter: pointer to the adapter structure |
c4cf55e5 | 6865 | **/ |
581330ba | 6866 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 6867 | { |
cf8280ee | 6868 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 6869 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 6870 | |
93c52dd0 AD |
6871 | adapter->link_up = false; |
6872 | adapter->link_speed = 0; | |
cf8280ee | 6873 | |
93c52dd0 AD |
6874 | /* only continue if link was up previously */ |
6875 | if (!netif_carrier_ok(netdev)) | |
6876 | return; | |
264857b8 | 6877 | |
93c52dd0 AD |
6878 | /* poll for SFP+ cable when link is down */ |
6879 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
6880 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 6881 | |
8fecf67c | 6882 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) |
1a71ab24 | 6883 | ixgbe_ptp_start_cyclecounter(adapter); |
3a6a4eda | 6884 | |
93c52dd0 AD |
6885 | e_info(drv, "NIC Link is Down\n"); |
6886 | netif_carrier_off(netdev); | |
befa2af7 AD |
6887 | |
6888 | /* ping all the active vfs to let them know link has changed */ | |
6889 | ixgbe_ping_all_vfs(adapter); | |
93c52dd0 | 6890 | } |
e8e26350 | 6891 | |
07923c17 ET |
6892 | static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter) |
6893 | { | |
6894 | int i; | |
6895 | ||
6896 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6897 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
6898 | ||
6899 | if (tx_ring->next_to_use != tx_ring->next_to_clean) | |
6900 | return true; | |
6901 | } | |
6902 | ||
6903 | return false; | |
6904 | } | |
6905 | ||
6906 | static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter) | |
6907 | { | |
6908 | struct ixgbe_hw *hw = &adapter->hw; | |
6909 | struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ]; | |
6910 | u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask); | |
6911 | ||
6912 | int i, j; | |
6913 | ||
6914 | if (!adapter->num_vfs) | |
6915 | return false; | |
6916 | ||
9a75a1ac DS |
6917 | /* resetting the PF is only needed for MAC before X550 */ |
6918 | if (hw->mac.type >= ixgbe_mac_X550) | |
6919 | return false; | |
6920 | ||
07923c17 ET |
6921 | for (i = 0; i < adapter->num_vfs; i++) { |
6922 | for (j = 0; j < q_per_pool; j++) { | |
6923 | u32 h, t; | |
6924 | ||
6925 | h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j)); | |
6926 | t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j)); | |
6927 | ||
6928 | if (h != t) | |
6929 | return true; | |
6930 | } | |
6931 | } | |
6932 | ||
6933 | return false; | |
6934 | } | |
6935 | ||
93c52dd0 AD |
6936 | /** |
6937 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
49ce9c2c | 6938 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
6939 | **/ |
6940 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
6941 | { | |
93c52dd0 | 6942 | if (!netif_carrier_ok(adapter->netdev)) { |
07923c17 ET |
6943 | if (ixgbe_ring_tx_pending(adapter) || |
6944 | ixgbe_vf_tx_pending(adapter)) { | |
bc59fcda NS |
6945 | /* We've lost link, so the controller stops DMA, |
6946 | * but we've got queued Tx work that's never going | |
6947 | * to get done, so reset controller to flush Tx. | |
6948 | * (Do the reset outside of interrupt context). | |
6949 | */ | |
12ff3f3b | 6950 | e_warn(drv, "initiating reset to clear Tx work after link loss\n"); |
c83c6cbd | 6951 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 6952 | } |
c4cf55e5 | 6953 | } |
c4cf55e5 PWJ |
6954 | } |
6955 | ||
9079e416 ET |
6956 | #ifdef CONFIG_PCI_IOV |
6957 | static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter, | |
6958 | struct pci_dev *vfdev) | |
6959 | { | |
6960 | if (!pci_wait_for_pending_transaction(vfdev)) | |
6961 | e_dev_warn("Issuing VFLR with pending transactions\n"); | |
6962 | ||
6963 | e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev)); | |
6964 | pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); | |
6965 | ||
6966 | msleep(100); | |
6967 | } | |
6968 | ||
6969 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
6970 | { | |
6971 | struct ixgbe_hw *hw = &adapter->hw; | |
6972 | struct pci_dev *pdev = adapter->pdev; | |
988d1307 | 6973 | unsigned int vf; |
9079e416 | 6974 | u32 gpc; |
9079e416 ET |
6975 | |
6976 | if (!(netif_carrier_ok(adapter->netdev))) | |
6977 | return; | |
6978 | ||
6979 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
6980 | if (gpc) /* If incrementing then no need for the check below */ | |
6981 | return; | |
6982 | /* Check to see if a bad DMA write target from an errant or | |
6983 | * malicious VF has caused a PCIe error. If so then we can | |
6984 | * issue a VFLR to the offending VF(s) and then resume without | |
6985 | * requesting a full slot reset. | |
6986 | */ | |
6987 | ||
6988 | if (!pdev) | |
6989 | return; | |
6990 | ||
9079e416 | 6991 | /* check status reg for all VFs owned by this PF */ |
988d1307 MR |
6992 | for (vf = 0; vf < adapter->num_vfs; ++vf) { |
6993 | struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev; | |
6994 | u16 status_reg; | |
9079e416 | 6995 | |
988d1307 MR |
6996 | if (!vfdev) |
6997 | continue; | |
6998 | pci_read_config_word(vfdev, PCI_STATUS, &status_reg); | |
6999 | if (status_reg != IXGBE_FAILED_READ_CFG_WORD && | |
7000 | status_reg & PCI_STATUS_REC_MASTER_ABORT) | |
7001 | ixgbe_issue_vf_flr(adapter, vfdev); | |
9079e416 ET |
7002 | } |
7003 | } | |
7004 | ||
a985b6c3 GR |
7005 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
7006 | { | |
7007 | u32 ssvpc; | |
7008 | ||
0584d999 GR |
7009 | /* Do not perform spoof check for 82598 or if not in IOV mode */ |
7010 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
7011 | adapter->num_vfs == 0) | |
a985b6c3 GR |
7012 | return; |
7013 | ||
7014 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
7015 | ||
7016 | /* | |
7017 | * ssvpc register is cleared on read, if zero then no | |
7018 | * spoofed packets in the last interval. | |
7019 | */ | |
7020 | if (!ssvpc) | |
7021 | return; | |
7022 | ||
d6ea0754 | 7023 | e_warn(drv, "%u Spoofed packets detected\n", ssvpc); |
a985b6c3 | 7024 | } |
9079e416 ET |
7025 | #else |
7026 | static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter) | |
7027 | { | |
7028 | } | |
7029 | ||
7030 | static void | |
7031 | ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter) | |
7032 | { | |
7033 | } | |
7034 | #endif /* CONFIG_PCI_IOV */ | |
7035 | ||
a985b6c3 | 7036 | |
93c52dd0 AD |
7037 | /** |
7038 | * ixgbe_watchdog_subtask - check and bring link up | |
49ce9c2c | 7039 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
7040 | **/ |
7041 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
7042 | { | |
09f40aed | 7043 | /* if interface is down, removing or resetting, do nothing */ |
7edebf9a | 7044 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 7045 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
7edebf9a | 7046 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
93c52dd0 AD |
7047 | return; |
7048 | ||
7049 | ixgbe_watchdog_update_link(adapter); | |
7050 | ||
7051 | if (adapter->link_up) | |
7052 | ixgbe_watchdog_link_is_up(adapter); | |
7053 | else | |
7054 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 7055 | |
9079e416 | 7056 | ixgbe_check_for_bad_vf(adapter); |
a985b6c3 | 7057 | ixgbe_spoof_check(adapter); |
9a799d71 | 7058 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
7059 | |
7060 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 7061 | } |
10eec955 | 7062 | |
cf8280ee | 7063 | /** |
7086400d | 7064 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
49ce9c2c | 7065 | * @adapter: the ixgbe adapter structure |
cf8280ee | 7066 | **/ |
7086400d | 7067 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 7068 | { |
cf8280ee | 7069 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 7070 | s32 err; |
cf8280ee | 7071 | |
4319a797 DS |
7072 | /* If crosstalk fix enabled verify the SFP+ cage is full */ |
7073 | if (adapter->need_crosstalk_fix) { | |
7074 | u32 sfp_cage_full; | |
7075 | ||
7076 | sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & | |
7077 | IXGBE_ESDP_SDP2; | |
7078 | if (!sfp_cage_full) | |
7079 | return; | |
7080 | } | |
7081 | ||
7086400d AD |
7082 | /* not searching for SFP so there is nothing to do here */ |
7083 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
7084 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
7085 | return; | |
10eec955 | 7086 | |
58e7cd24 MR |
7087 | if (adapter->sfp_poll_time && |
7088 | time_after(adapter->sfp_poll_time, jiffies)) | |
7089 | return; /* If not yet time to poll for SFP */ | |
7090 | ||
7086400d AD |
7091 | /* someone else is in init, wait until next service event */ |
7092 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
7093 | return; | |
cf8280ee | 7094 | |
58e7cd24 MR |
7095 | adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1; |
7096 | ||
7086400d AD |
7097 | err = hw->phy.ops.identify_sfp(hw); |
7098 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
7099 | goto sfp_out; | |
264857b8 | 7100 | |
7086400d AD |
7101 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
7102 | /* If no cable is present, then we need to reset | |
7103 | * the next time we find a good cable. */ | |
7104 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 7105 | } |
9a799d71 | 7106 | |
7086400d AD |
7107 | /* exit on error */ |
7108 | if (err) | |
7109 | goto sfp_out; | |
e8e26350 | 7110 | |
7086400d AD |
7111 | /* exit if reset not needed */ |
7112 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
7113 | goto sfp_out; | |
9a799d71 | 7114 | |
7086400d | 7115 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 7116 | |
7086400d AD |
7117 | /* |
7118 | * A module may be identified correctly, but the EEPROM may not have | |
7119 | * support for that module. setup_sfp() will fail in that case, so | |
7120 | * we should not allow that module to load. | |
7121 | */ | |
7122 | if (hw->mac.type == ixgbe_mac_82598EB) | |
7123 | err = hw->phy.ops.reset(hw); | |
7124 | else | |
7125 | err = hw->mac.ops.setup_sfp(hw); | |
7126 | ||
7127 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
7128 | goto sfp_out; | |
7129 | ||
7130 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
7131 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
7132 | ||
7133 | sfp_out: | |
7134 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
7135 | ||
7136 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
7137 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
7138 | e_dev_err("failed to initialize because an unsupported " | |
7139 | "SFP+ module type was detected.\n"); | |
7140 | e_dev_err("Reload the driver after installing a " | |
7141 | "supported module.\n"); | |
7142 | unregister_netdev(adapter->netdev); | |
bc59fcda | 7143 | } |
7086400d | 7144 | } |
bc59fcda | 7145 | |
7086400d AD |
7146 | /** |
7147 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
49ce9c2c | 7148 | * @adapter: the ixgbe adapter structure |
7086400d AD |
7149 | **/ |
7150 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
7151 | { | |
7152 | struct ixgbe_hw *hw = &adapter->hw; | |
3d292265 JH |
7153 | u32 speed; |
7154 | bool autoneg = false; | |
7086400d AD |
7155 | |
7156 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
7157 | return; | |
7158 | ||
7159 | /* someone else is in init, wait until next service event */ | |
7160 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
7161 | return; | |
7162 | ||
7163 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
7164 | ||
3d292265 | 7165 | speed = hw->phy.autoneg_advertised; |
ed33ff66 | 7166 | if ((!speed) && (hw->mac.ops.get_link_capabilities)) { |
3d292265 | 7167 | hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg); |
ed33ff66 ET |
7168 | |
7169 | /* setup the highest link when no autoneg */ | |
7170 | if (!autoneg) { | |
7171 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) | |
7172 | speed = IXGBE_LINK_SPEED_10GB_FULL; | |
7173 | } | |
7174 | } | |
7175 | ||
7086400d | 7176 | if (hw->mac.ops.setup_link) |
fd0326f2 | 7177 | hw->mac.ops.setup_link(hw, speed, true); |
7086400d AD |
7178 | |
7179 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
7180 | adapter->link_check_timeout = jiffies; | |
7181 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
7182 | } | |
7183 | ||
7184 | /** | |
7185 | * ixgbe_service_timer - Timer Call-back | |
7186 | * @data: pointer to adapter cast into an unsigned long | |
7187 | **/ | |
7188 | static void ixgbe_service_timer(unsigned long data) | |
7189 | { | |
7190 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
7191 | unsigned long next_event_offset; | |
7192 | ||
6bb78cfb AD |
7193 | /* poll faster when waiting for link */ |
7194 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
7195 | next_event_offset = HZ / 10; | |
7196 | else | |
7197 | next_event_offset = HZ * 2; | |
83c61fa9 | 7198 | |
7086400d AD |
7199 | /* Reset the timer */ |
7200 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
7201 | ||
9079e416 | 7202 | ixgbe_service_event_schedule(adapter); |
7086400d AD |
7203 | } |
7204 | ||
597f22d6 DS |
7205 | static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter) |
7206 | { | |
7207 | struct ixgbe_hw *hw = &adapter->hw; | |
7208 | u32 status; | |
7209 | ||
7210 | if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT)) | |
7211 | return; | |
7212 | ||
7213 | adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT; | |
7214 | ||
7215 | if (!hw->phy.ops.handle_lasi) | |
7216 | return; | |
7217 | ||
7218 | status = hw->phy.ops.handle_lasi(&adapter->hw); | |
7219 | if (status != IXGBE_ERR_OVERTEMP) | |
7220 | return; | |
7221 | ||
7222 | e_crit(drv, "%s\n", ixgbe_overheat_msg); | |
7223 | } | |
7224 | ||
c83c6cbd AD |
7225 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
7226 | { | |
7227 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
7228 | return; | |
7229 | ||
7230 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
7231 | ||
09f40aed | 7232 | /* If we're already down, removing or resetting, just bail */ |
c83c6cbd | 7233 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
09f40aed | 7234 | test_bit(__IXGBE_REMOVING, &adapter->state) || |
c83c6cbd AD |
7235 | test_bit(__IXGBE_RESETTING, &adapter->state)) |
7236 | return; | |
7237 | ||
7238 | ixgbe_dump(adapter); | |
7239 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
7240 | adapter->tx_timeout_count++; | |
7241 | ||
8f4c5c9f | 7242 | rtnl_lock(); |
c83c6cbd | 7243 | ixgbe_reinit_locked(adapter); |
8f4c5c9f | 7244 | rtnl_unlock(); |
c83c6cbd AD |
7245 | } |
7246 | ||
7086400d AD |
7247 | /** |
7248 | * ixgbe_service_task - manages and runs subtasks | |
7249 | * @work: pointer to work_struct containing our data | |
7250 | **/ | |
7251 | static void ixgbe_service_task(struct work_struct *work) | |
7252 | { | |
7253 | struct ixgbe_adapter *adapter = container_of(work, | |
7254 | struct ixgbe_adapter, | |
7255 | service_task); | |
b0483c8f MR |
7256 | if (ixgbe_removed(adapter->hw.hw_addr)) { |
7257 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
7258 | rtnl_lock(); | |
7259 | ixgbe_down(adapter); | |
7260 | rtnl_unlock(); | |
7261 | } | |
7262 | ixgbe_service_event_complete(adapter); | |
7263 | return; | |
7264 | } | |
67359c3c | 7265 | #ifdef CONFIG_IXGBE_VXLAN |
b1f99a78 | 7266 | rtnl_lock(); |
67359c3c MR |
7267 | if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) { |
7268 | adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED; | |
7269 | vxlan_get_rx_port(adapter->netdev); | |
7270 | } | |
b1f99a78 | 7271 | rtnl_unlock(); |
67359c3c | 7272 | #endif /* CONFIG_IXGBE_VXLAN */ |
c83c6cbd | 7273 | ixgbe_reset_subtask(adapter); |
597f22d6 | 7274 | ixgbe_phy_interrupt_subtask(adapter); |
7086400d AD |
7275 | ixgbe_sfp_detection_subtask(adapter); |
7276 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 7277 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 7278 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 7279 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 7280 | ixgbe_check_hang_subtask(adapter); |
891dc082 | 7281 | |
8fecf67c | 7282 | if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) { |
891dc082 JK |
7283 | ixgbe_ptp_overflow_check(adapter); |
7284 | ixgbe_ptp_rx_hang(adapter); | |
7285 | } | |
7086400d AD |
7286 | |
7287 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
7288 | } |
7289 | ||
fd0db0ed AD |
7290 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
7291 | struct ixgbe_tx_buffer *first, | |
244e27ad | 7292 | u8 *hdr_len) |
897ab156 | 7293 | { |
b83e3010 | 7294 | u32 vlan_macip_lens, type_tucmd, mss_l4len_idx; |
fd0db0ed | 7295 | struct sk_buff *skb = first->skb; |
b83e3010 AD |
7296 | union { |
7297 | struct iphdr *v4; | |
7298 | struct ipv6hdr *v6; | |
7299 | unsigned char *hdr; | |
7300 | } ip; | |
7301 | union { | |
7302 | struct tcphdr *tcp; | |
7303 | unsigned char *hdr; | |
7304 | } l4; | |
7305 | u32 paylen, l4_offset; | |
2049e1f6 | 7306 | int err; |
9a799d71 | 7307 | |
8f4fbb9b AD |
7308 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
7309 | return 0; | |
7310 | ||
897ab156 AD |
7311 | if (!skb_is_gso(skb)) |
7312 | return 0; | |
9a799d71 | 7313 | |
2049e1f6 FR |
7314 | err = skb_cow_head(skb, 0); |
7315 | if (err < 0) | |
7316 | return err; | |
9a799d71 | 7317 | |
b83e3010 AD |
7318 | ip.hdr = skb_network_header(skb); |
7319 | l4.hdr = skb_checksum_start(skb); | |
7320 | ||
897ab156 AD |
7321 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
7322 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
7323 | ||
b83e3010 AD |
7324 | /* initialize outer IP header fields */ |
7325 | if (ip.v4->version == 4) { | |
7326 | /* IP header will have to cancel out any data that | |
7327 | * is not a part of the outer IP header | |
7328 | */ | |
7329 | ip.v4->check = csum_fold(csum_add(lco_csum(skb), | |
7330 | csum_unfold(l4.tcp->check))); | |
897ab156 | 7331 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; |
b83e3010 AD |
7332 | |
7333 | ip.v4->tot_len = 0; | |
244e27ad AD |
7334 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
7335 | IXGBE_TX_FLAGS_CSUM | | |
7336 | IXGBE_TX_FLAGS_IPV4; | |
b83e3010 AD |
7337 | } else { |
7338 | ip.v6->payload_len = 0; | |
244e27ad AD |
7339 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
7340 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
7341 | } |
7342 | ||
b83e3010 AD |
7343 | /* determine offset of inner transport header */ |
7344 | l4_offset = l4.hdr - skb->data; | |
7345 | ||
7346 | /* compute length of segmentation header */ | |
7347 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
7348 | ||
7349 | /* remove payload length from inner checksum */ | |
7350 | paylen = skb->len - l4_offset; | |
7351 | csum_replace_by_diff(&l4.tcp->check, htonl(paylen)); | |
897ab156 | 7352 | |
091a6246 AD |
7353 | /* update gso size and bytecount with header size */ |
7354 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
7355 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
7356 | ||
c44f5f51 | 7357 | /* mss_l4len_id: use 0 as index for TSO */ |
b83e3010 | 7358 | mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT; |
897ab156 | 7359 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; |
897ab156 AD |
7360 | |
7361 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
b83e3010 AD |
7362 | vlan_macip_lens = l4.hdr - ip.hdr; |
7363 | vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 7364 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
7365 | |
7366 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 7367 | mss_l4len_idx); |
897ab156 AD |
7368 | |
7369 | return 1; | |
7370 | } | |
7371 | ||
49763de0 AD |
7372 | static inline bool ixgbe_ipv6_csum_is_sctp(struct sk_buff *skb) |
7373 | { | |
7374 | unsigned int offset = 0; | |
7375 | ||
7376 | ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL); | |
7377 | ||
7378 | return offset == skb_checksum_start_offset(skb); | |
7379 | } | |
7380 | ||
244e27ad AD |
7381 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
7382 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 7383 | { |
fd0db0ed | 7384 | struct sk_buff *skb = first->skb; |
897ab156 | 7385 | u32 vlan_macip_lens = 0; |
897ab156 | 7386 | u32 type_tucmd = 0; |
7ca647bd | 7387 | |
897ab156 | 7388 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
49763de0 AD |
7389 | csum_failed: |
7390 | if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | | |
7391 | IXGBE_TX_FLAGS_CC))) | |
472148c3 | 7392 | return; |
49763de0 AD |
7393 | goto no_csum; |
7394 | } | |
897ab156 | 7395 | |
49763de0 AD |
7396 | switch (skb->csum_offset) { |
7397 | case offsetof(struct tcphdr, check): | |
7398 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
7399 | /* fall through */ | |
7400 | case offsetof(struct udphdr, check): | |
7401 | break; | |
7402 | case offsetof(struct sctphdr, checksum): | |
7403 | /* validate that this is actually an SCTP request */ | |
7404 | if (((first->protocol == htons(ETH_P_IP)) && | |
7405 | (ip_hdr(skb)->protocol == IPPROTO_SCTP)) || | |
7406 | ((first->protocol == htons(ETH_P_IPV6)) && | |
7407 | ixgbe_ipv6_csum_is_sctp(skb))) { | |
7408 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP; | |
897ab156 | 7409 | break; |
7ca647bd | 7410 | } |
49763de0 AD |
7411 | /* fall through */ |
7412 | default: | |
7413 | skb_checksum_help(skb); | |
7414 | goto csum_failed; | |
7ca647bd JP |
7415 | } |
7416 | ||
49763de0 AD |
7417 | /* update TX checksum flag */ |
7418 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7419 | vlan_macip_lens = skb_checksum_start_offset(skb) - | |
7420 | skb_network_offset(skb); | |
36a92d71 | 7421 | no_csum: |
244e27ad | 7422 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
49763de0 | 7423 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 7424 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 7425 | |
49763de0 | 7426 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, 0); |
9a799d71 AK |
7427 | } |
7428 | ||
472148c3 AD |
7429 | #define IXGBE_SET_FLAG(_input, _flag, _result) \ |
7430 | ((_flag <= _result) ? \ | |
7431 | ((u32)(_input & _flag) * (_result / _flag)) : \ | |
7432 | ((u32)(_input & _flag) / (_flag / _result))) | |
7433 | ||
7434 | static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) | |
9a799d71 | 7435 | { |
d3d00239 | 7436 | /* set type for advanced descriptor with frame checksum insertion */ |
472148c3 AD |
7437 | u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA | |
7438 | IXGBE_ADVTXD_DCMD_DEXT | | |
7439 | IXGBE_ADVTXD_DCMD_IFCS; | |
9a799d71 | 7440 | |
d3d00239 | 7441 | /* set HW vlan bit if vlan is present */ |
472148c3 AD |
7442 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN, |
7443 | IXGBE_ADVTXD_DCMD_VLE); | |
3a6a4eda | 7444 | |
d3d00239 | 7445 | /* set segmentation enable bits for TSO/FSO */ |
472148c3 AD |
7446 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO, |
7447 | IXGBE_ADVTXD_DCMD_TSE); | |
7448 | ||
7449 | /* set timestamp bit if present */ | |
7450 | cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP, | |
7451 | IXGBE_ADVTXD_MAC_TSTAMP); | |
eacd73f7 | 7452 | |
62748b7b | 7453 | /* insert frame checksum */ |
472148c3 | 7454 | cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS); |
62748b7b | 7455 | |
d3d00239 AD |
7456 | return cmd_type; |
7457 | } | |
9a799d71 | 7458 | |
729739b7 AD |
7459 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
7460 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 7461 | { |
472148c3 | 7462 | u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT; |
9a799d71 | 7463 | |
d3d00239 | 7464 | /* enable L4 checksum for TSO and TX checksum offload */ |
472148c3 AD |
7465 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7466 | IXGBE_TX_FLAGS_CSUM, | |
7467 | IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 7468 | |
93f5b3c1 | 7469 | /* enble IPv4 checksum for TSO */ |
472148c3 AD |
7470 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7471 | IXGBE_TX_FLAGS_IPV4, | |
7472 | IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 7473 | |
7f9643fd AD |
7474 | /* |
7475 | * Check Context must be set if Tx switch is enabled, which it | |
7476 | * always is for case where virtual functions are running | |
7477 | */ | |
472148c3 AD |
7478 | olinfo_status |= IXGBE_SET_FLAG(tx_flags, |
7479 | IXGBE_TX_FLAGS_CC, | |
7480 | IXGBE_ADVTXD_CC); | |
7f9643fd | 7481 | |
472148c3 | 7482 | tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); |
d3d00239 | 7483 | } |
44df32c5 | 7484 | |
2367a173 DB |
7485 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
7486 | { | |
7487 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
7488 | ||
7489 | /* Herbert's original patch had: | |
7490 | * smp_mb__after_netif_stop_queue(); | |
7491 | * but since that doesn't exist yet, just open code it. | |
7492 | */ | |
7493 | smp_mb(); | |
7494 | ||
7495 | /* We need to check again in a case another CPU has just | |
7496 | * made room available. | |
7497 | */ | |
7498 | if (likely(ixgbe_desc_unused(tx_ring) < size)) | |
7499 | return -EBUSY; | |
7500 | ||
7501 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
7502 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
7503 | ++tx_ring->tx_stats.restart_queue; | |
7504 | return 0; | |
7505 | } | |
7506 | ||
7507 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) | |
7508 | { | |
7509 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) | |
7510 | return 0; | |
7511 | ||
7512 | return __ixgbe_maybe_stop_tx(tx_ring, size); | |
7513 | } | |
7514 | ||
d3d00239 AD |
7515 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
7516 | IXGBE_TXD_CMD_RS) | |
7517 | ||
7518 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 7519 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
7520 | const u8 hdr_len) |
7521 | { | |
fd0db0ed | 7522 | struct sk_buff *skb = first->skb; |
729739b7 | 7523 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 7524 | union ixgbe_adv_tx_desc *tx_desc; |
ec718254 AD |
7525 | struct skb_frag_struct *frag; |
7526 | dma_addr_t dma; | |
7527 | unsigned int data_len, size; | |
244e27ad | 7528 | u32 tx_flags = first->tx_flags; |
472148c3 | 7529 | u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags); |
d3d00239 | 7530 | u16 i = tx_ring->next_to_use; |
d3d00239 | 7531 | |
729739b7 AD |
7532 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
7533 | ||
ec718254 AD |
7534 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len); |
7535 | ||
7536 | size = skb_headlen(skb); | |
7537 | data_len = skb->data_len; | |
729739b7 | 7538 | |
d3d00239 AD |
7539 | #ifdef IXGBE_FCOE |
7540 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 7541 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
7542 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
7543 | data_len = 0; | |
729739b7 AD |
7544 | } else { |
7545 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
7546 | } |
7547 | } | |
44df32c5 | 7548 | |
d3d00239 | 7549 | #endif |
729739b7 | 7550 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
8ad494b0 | 7551 | |
ec718254 | 7552 | tx_buffer = first; |
9a799d71 | 7553 | |
ec718254 AD |
7554 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { |
7555 | if (dma_mapping_error(tx_ring->dev, dma)) | |
7556 | goto dma_error; | |
7557 | ||
7558 | /* record length, and DMA address */ | |
7559 | dma_unmap_len_set(tx_buffer, len, size); | |
7560 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
7561 | ||
7562 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
e5a43549 | 7563 | |
729739b7 | 7564 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 | 7565 | tx_desc->read.cmd_type_len = |
472148c3 | 7566 | cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD); |
e5a43549 | 7567 | |
d3d00239 | 7568 | i++; |
729739b7 | 7569 | tx_desc++; |
d3d00239 | 7570 | if (i == tx_ring->count) { |
e4f74028 | 7571 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
7572 | i = 0; |
7573 | } | |
ec718254 | 7574 | tx_desc->read.olinfo_status = 0; |
729739b7 AD |
7575 | |
7576 | dma += IXGBE_MAX_DATA_PER_TXD; | |
7577 | size -= IXGBE_MAX_DATA_PER_TXD; | |
7578 | ||
7579 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
d3d00239 | 7580 | } |
e5a43549 | 7581 | |
729739b7 AD |
7582 | if (likely(!data_len)) |
7583 | break; | |
9a799d71 | 7584 | |
472148c3 | 7585 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); |
9a799d71 | 7586 | |
729739b7 AD |
7587 | i++; |
7588 | tx_desc++; | |
7589 | if (i == tx_ring->count) { | |
7590 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
7591 | i = 0; | |
7592 | } | |
ec718254 | 7593 | tx_desc->read.olinfo_status = 0; |
9a799d71 | 7594 | |
d3d00239 | 7595 | #ifdef IXGBE_FCOE |
9e903e08 | 7596 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 7597 | #else |
9e903e08 | 7598 | size = skb_frag_size(frag); |
d3d00239 AD |
7599 | #endif |
7600 | data_len -= size; | |
9a799d71 | 7601 | |
729739b7 AD |
7602 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
7603 | DMA_TO_DEVICE); | |
9a799d71 | 7604 | |
729739b7 | 7605 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
729739b7 | 7606 | } |
9a799d71 | 7607 | |
729739b7 | 7608 | /* write last descriptor with RS and EOP bits */ |
472148c3 AD |
7609 | cmd_type |= size | IXGBE_TXD_CMD; |
7610 | tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); | |
eacd73f7 | 7611 | |
091a6246 | 7612 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 7613 | |
d3d00239 AD |
7614 | /* set the timestamp */ |
7615 | first->time_stamp = jiffies; | |
9a799d71 AK |
7616 | |
7617 | /* | |
729739b7 AD |
7618 | * Force memory writes to complete before letting h/w know there |
7619 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
7620 | * memory model archs, such as IA-64). | |
7621 | * | |
7622 | * We also need this memory barrier to make certain all of the | |
7623 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
7624 | */ |
7625 | wmb(); | |
7626 | ||
d3d00239 AD |
7627 | /* set next_to_watch value indicating a packet is present */ |
7628 | first->next_to_watch = tx_desc; | |
7629 | ||
729739b7 AD |
7630 | i++; |
7631 | if (i == tx_ring->count) | |
7632 | i = 0; | |
7633 | ||
7634 | tx_ring->next_to_use = i; | |
7635 | ||
2367a173 DB |
7636 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); |
7637 | ||
7638 | if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { | |
ad435ec6 AD |
7639 | writel(i, tx_ring->tail); |
7640 | ||
7641 | /* we need this if more than one processor can write to our tail | |
7642 | * at a time, it synchronizes IO on IA64/Altix systems | |
7643 | */ | |
7644 | mmiowb(); | |
9c938cdd | 7645 | } |
2367a173 | 7646 | |
d3d00239 AD |
7647 | return; |
7648 | dma_error: | |
729739b7 | 7649 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
7650 | |
7651 | /* clear dma mappings for failed tx_buffer_info map */ | |
7652 | for (;;) { | |
729739b7 AD |
7653 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
7654 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
7655 | if (tx_buffer == first) | |
d3d00239 AD |
7656 | break; |
7657 | if (i == 0) | |
7658 | i = tx_ring->count; | |
7659 | i--; | |
7660 | } | |
7661 | ||
d3d00239 | 7662 | tx_ring->next_to_use = i; |
9a799d71 AK |
7663 | } |
7664 | ||
fd0db0ed | 7665 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 7666 | struct ixgbe_tx_buffer *first) |
69830529 AD |
7667 | { |
7668 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
7669 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
7670 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
7671 | union { | |
7672 | unsigned char *network; | |
7673 | struct iphdr *ipv4; | |
7674 | struct ipv6hdr *ipv6; | |
7675 | } hdr; | |
ee9e0f0b | 7676 | struct tcphdr *th; |
e2873d43 | 7677 | unsigned int hlen; |
67359c3c | 7678 | struct sk_buff *skb; |
905e4a41 | 7679 | __be16 vlan_id; |
e2873d43 | 7680 | int l4_proto; |
c4cf55e5 | 7681 | |
69830529 AD |
7682 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
7683 | if (!q_vector) | |
7684 | return; | |
7685 | ||
7686 | /* do nothing if sampling is disabled */ | |
7687 | if (!ring->atr_sample_rate) | |
d3ead241 | 7688 | return; |
c4cf55e5 | 7689 | |
69830529 | 7690 | ring->atr_count++; |
c4cf55e5 | 7691 | |
e2873d43 AD |
7692 | /* currently only IPv4/IPv6 with TCP is supported */ |
7693 | if ((first->protocol != htons(ETH_P_IP)) && | |
7694 | (first->protocol != htons(ETH_P_IPV6))) | |
7695 | return; | |
7696 | ||
69830529 | 7697 | /* snag network header to get L4 type and address */ |
67359c3c MR |
7698 | skb = first->skb; |
7699 | hdr.network = skb_network_header(skb); | |
67359c3c | 7700 | #ifdef CONFIG_IXGBE_VXLAN |
9f12df90 AD |
7701 | if (skb->encapsulation && |
7702 | first->protocol == htons(ETH_P_IP) && | |
7703 | hdr.ipv4->protocol != IPPROTO_UDP) { | |
67359c3c | 7704 | struct ixgbe_adapter *adapter = q_vector->adapter; |
69830529 | 7705 | |
9f12df90 AD |
7706 | /* verify the port is recognized as VXLAN */ |
7707 | if (adapter->vxlan_port && | |
e2873d43 | 7708 | udp_hdr(skb)->dest == adapter->vxlan_port) |
9f12df90 | 7709 | hdr.network = skb_inner_network_header(skb); |
e19dcdeb | 7710 | } |
9f12df90 | 7711 | #endif /* CONFIG_IXGBE_VXLAN */ |
e19dcdeb MR |
7712 | |
7713 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
7714 | switch (hdr.ipv4->version) { | |
7715 | case IPVERSION: | |
e2873d43 AD |
7716 | /* access ihl as u8 to avoid unaligned access on ia64 */ |
7717 | hlen = (hdr.network[0] & 0x0F) << 2; | |
7718 | l4_proto = hdr.ipv4->protocol; | |
e19dcdeb MR |
7719 | break; |
7720 | case 6: | |
e2873d43 AD |
7721 | hlen = hdr.network - skb->data; |
7722 | l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL); | |
7723 | hlen -= hdr.network - skb->data; | |
e19dcdeb MR |
7724 | break; |
7725 | default: | |
7726 | return; | |
67359c3c | 7727 | } |
c4cf55e5 | 7728 | |
e2873d43 AD |
7729 | if (l4_proto != IPPROTO_TCP) |
7730 | return; | |
7731 | ||
7732 | th = (struct tcphdr *)(hdr.network + hlen); | |
7733 | ||
7734 | /* skip this packet since the socket is closing */ | |
7735 | if (th->fin) | |
69830529 AD |
7736 | return; |
7737 | ||
7738 | /* sample on all syn packets or once every atr sample count */ | |
7739 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
7740 | return; | |
7741 | ||
7742 | /* reset sample count */ | |
7743 | ring->atr_count = 0; | |
7744 | ||
244e27ad | 7745 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
7746 | |
7747 | /* | |
7748 | * src and dst are inverted, think how the receiver sees them | |
7749 | * | |
7750 | * The input is broken into two sections, a non-compressed section | |
7751 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
7752 | * is XORed together and stored in the compressed dword. | |
7753 | */ | |
7754 | input.formatted.vlan_id = vlan_id; | |
7755 | ||
7756 | /* | |
7757 | * since src port and flex bytes occupy the same word XOR them together | |
7758 | * and write the value to source port portion of compressed dword | |
7759 | */ | |
244e27ad | 7760 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
a1108ffd | 7761 | common.port.src ^= th->dest ^ htons(ETH_P_8021Q); |
69830529 | 7762 | else |
244e27ad | 7763 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
7764 | common.port.dst ^= th->source; |
7765 | ||
e19dcdeb MR |
7766 | switch (hdr.ipv4->version) { |
7767 | case IPVERSION: | |
69830529 AD |
7768 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
7769 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
e19dcdeb MR |
7770 | break; |
7771 | case 6: | |
69830529 AD |
7772 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; |
7773 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
7774 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
7775 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
7776 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
7777 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
7778 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
7779 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
7780 | hdr.ipv6->daddr.s6_addr32[3]; | |
e19dcdeb MR |
7781 | break; |
7782 | default: | |
7783 | break; | |
69830529 | 7784 | } |
c4cf55e5 | 7785 | |
9f12df90 | 7786 | if (hdr.network != skb_network_header(skb)) |
67359c3c | 7787 | input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK; |
67359c3c | 7788 | |
c4cf55e5 | 7789 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ |
69830529 AD |
7790 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
7791 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
7792 | } |
7793 | ||
f663dd9a | 7794 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 7795 | void *accel_priv, select_queue_fallback_t fallback) |
09a3b1f8 | 7796 | { |
f663dd9a JW |
7797 | struct ixgbe_fwd_adapter *fwd_adapter = accel_priv; |
7798 | #ifdef IXGBE_FCOE | |
97488bd1 AD |
7799 | struct ixgbe_adapter *adapter; |
7800 | struct ixgbe_ring_feature *f; | |
7801 | int txq; | |
f663dd9a JW |
7802 | #endif |
7803 | ||
7804 | if (fwd_adapter) | |
7805 | return skb->queue_mapping + fwd_adapter->tx_base_queue; | |
7806 | ||
7807 | #ifdef IXGBE_FCOE | |
5e09a105 | 7808 | |
97488bd1 AD |
7809 | /* |
7810 | * only execute the code below if protocol is FCoE | |
7811 | * or FIP and we have FCoE enabled on the adapter | |
7812 | */ | |
7813 | switch (vlan_get_protocol(skb)) { | |
a1108ffd JP |
7814 | case htons(ETH_P_FCOE): |
7815 | case htons(ETH_P_FIP): | |
97488bd1 | 7816 | adapter = netdev_priv(dev); |
c087663e | 7817 | |
97488bd1 AD |
7818 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) |
7819 | break; | |
7820 | default: | |
99932d4f | 7821 | return fallback(dev, skb); |
97488bd1 | 7822 | } |
c087663e | 7823 | |
97488bd1 | 7824 | f = &adapter->ring_feature[RING_F_FCOE]; |
c087663e | 7825 | |
97488bd1 AD |
7826 | txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
7827 | smp_processor_id(); | |
56075a98 | 7828 | |
97488bd1 AD |
7829 | while (txq >= f->indices) |
7830 | txq -= f->indices; | |
c4cf55e5 | 7831 | |
97488bd1 | 7832 | return txq + f->offset; |
f663dd9a | 7833 | #else |
99932d4f | 7834 | return fallback(dev, skb); |
f663dd9a | 7835 | #endif |
09a3b1f8 SH |
7836 | } |
7837 | ||
fc77dc3c | 7838 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
7839 | struct ixgbe_adapter *adapter, |
7840 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 7841 | { |
d3d00239 | 7842 | struct ixgbe_tx_buffer *first; |
5f715823 | 7843 | int tso; |
d3d00239 | 7844 | u32 tx_flags = 0; |
a535c30e | 7845 | unsigned short f; |
a535c30e | 7846 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 7847 | __be16 protocol = skb->protocol; |
63544e9c | 7848 | u8 hdr_len = 0; |
5e09a105 | 7849 | |
a535c30e AD |
7850 | /* |
7851 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 7852 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
7853 | * + 2 desc gap to keep tail from touching head, |
7854 | * + 1 desc for context descriptor, | |
7855 | * otherwise try next time | |
7856 | */ | |
a535c30e AD |
7857 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) |
7858 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
7f66162b | 7859 | |
a535c30e AD |
7860 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { |
7861 | tx_ring->tx_stats.tx_busy++; | |
7862 | return NETDEV_TX_BUSY; | |
7863 | } | |
7864 | ||
fd0db0ed AD |
7865 | /* record the location of the first descriptor for this packet */ |
7866 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
7867 | first->skb = skb; | |
091a6246 AD |
7868 | first->bytecount = skb->len; |
7869 | first->gso_segs = 1; | |
fd0db0ed | 7870 | |
66f32a8b | 7871 | /* if we have a HW VLAN tag being added default to the HW one */ |
df8a39de JP |
7872 | if (skb_vlan_tag_present(skb)) { |
7873 | tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
7874 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; |
7875 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
a1108ffd | 7876 | } else if (protocol == htons(ETH_P_8021Q)) { |
66f32a8b AD |
7877 | struct vlan_hdr *vhdr, _vhdr; |
7878 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
7879 | if (!vhdr) | |
7880 | goto out_drop; | |
7881 | ||
9e0c5648 AD |
7882 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
7883 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
7884 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
7885 | } | |
0213668f | 7886 | protocol = vlan_get_protocol(skb); |
66f32a8b | 7887 | |
d5234933 MR |
7888 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
7889 | adapter->ptp_clock && | |
7890 | !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS, | |
7891 | &adapter->state)) { | |
3a6a4eda JK |
7892 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
7893 | tx_flags |= IXGBE_TX_FLAGS_TSTAMP; | |
891dc082 JK |
7894 | |
7895 | /* schedule check for Tx timestamp */ | |
7896 | adapter->ptp_tx_skb = skb_get(skb); | |
7897 | adapter->ptp_tx_start = jiffies; | |
7898 | schedule_work(&adapter->ptp_tx_work); | |
3a6a4eda | 7899 | } |
3a6a4eda | 7900 | |
ff29a86e JK |
7901 | skb_tx_timestamp(skb); |
7902 | ||
9e0c5648 AD |
7903 | #ifdef CONFIG_PCI_IOV |
7904 | /* | |
7905 | * Use the l2switch_enable flag - would be false if the DMA | |
7906 | * Tx switch had been disabled. | |
7907 | */ | |
7908 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
472148c3 | 7909 | tx_flags |= IXGBE_TX_FLAGS_CC; |
9e0c5648 AD |
7910 | |
7911 | #endif | |
32701dc2 | 7912 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 7913 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
7914 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
7915 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 7916 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
7917 | tx_flags |= (skb->priority & 0x7) << |
7918 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
7919 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
7920 | struct vlan_ethhdr *vhdr; | |
2049e1f6 FR |
7921 | |
7922 | if (skb_cow_head(skb, 0)) | |
66f32a8b AD |
7923 | goto out_drop; |
7924 | vhdr = (struct vlan_ethhdr *)skb->data; | |
7925 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
7926 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
7927 | } else { | |
7928 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 7929 | } |
9a799d71 | 7930 | } |
eacd73f7 | 7931 | |
244e27ad AD |
7932 | /* record initial flags and protocol */ |
7933 | first->tx_flags = tx_flags; | |
7934 | first->protocol = protocol; | |
7935 | ||
eacd73f7 | 7936 | #ifdef IXGBE_FCOE |
66f32a8b | 7937 | /* setup tx offload for FCoE */ |
a1108ffd | 7938 | if ((protocol == htons(ETH_P_FCOE)) && |
a58915c7 | 7939 | (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) { |
244e27ad | 7940 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
7941 | if (tso < 0) |
7942 | goto out_drop; | |
9a799d71 | 7943 | |
66f32a8b | 7944 | goto xmit_fcoe; |
eacd73f7 | 7945 | } |
9a799d71 | 7946 | |
66f32a8b | 7947 | #endif /* IXGBE_FCOE */ |
244e27ad | 7948 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 7949 | if (tso < 0) |
897ab156 | 7950 | goto out_drop; |
244e27ad AD |
7951 | else if (!tso) |
7952 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
7953 | |
7954 | /* add the ATR filter if ATR is on */ | |
7955 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 7956 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
7957 | |
7958 | #ifdef IXGBE_FCOE | |
7959 | xmit_fcoe: | |
7960 | #endif /* IXGBE_FCOE */ | |
244e27ad | 7961 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 | 7962 | |
9a799d71 | 7963 | return NETDEV_TX_OK; |
897ab156 AD |
7964 | |
7965 | out_drop: | |
fd0db0ed AD |
7966 | dev_kfree_skb_any(first->skb); |
7967 | first->skb = NULL; | |
7968 | ||
897ab156 | 7969 | return NETDEV_TX_OK; |
9a799d71 AK |
7970 | } |
7971 | ||
2a47fa45 JF |
7972 | static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb, |
7973 | struct net_device *netdev, | |
7974 | struct ixgbe_ring *ring) | |
84418e3b AD |
7975 | { |
7976 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7977 | struct ixgbe_ring *tx_ring; | |
7978 | ||
a50c29dd AD |
7979 | /* |
7980 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
7981 | * in order to meet this minimum size requirement. | |
7982 | */ | |
a94d9e22 AD |
7983 | if (skb_put_padto(skb, 17)) |
7984 | return NETDEV_TX_OK; | |
a50c29dd | 7985 | |
2a47fa45 JF |
7986 | tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping]; |
7987 | ||
fc77dc3c | 7988 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
7989 | } |
7990 | ||
2a47fa45 JF |
7991 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
7992 | struct net_device *netdev) | |
7993 | { | |
7994 | return __ixgbe_xmit_frame(skb, netdev, NULL); | |
7995 | } | |
7996 | ||
9a799d71 AK |
7997 | /** |
7998 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
7999 | * @netdev: network interface device structure | |
8000 | * @p: pointer to an address structure | |
8001 | * | |
8002 | * Returns 0 on success, negative on failure | |
8003 | **/ | |
8004 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
8005 | { | |
8006 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 8007 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
8008 | struct sockaddr *addr = p; |
8009 | ||
8010 | if (!is_valid_ether_addr(addr->sa_data)) | |
8011 | return -EADDRNOTAVAIL; | |
8012 | ||
8013 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 8014 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 8015 | |
c9f53e63 AD |
8016 | ixgbe_mac_set_default_filter(adapter); |
8017 | ||
8018 | return 0; | |
9a799d71 AK |
8019 | } |
8020 | ||
6b73e10d BH |
8021 | static int |
8022 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
8023 | { | |
8024 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8025 | struct ixgbe_hw *hw = &adapter->hw; | |
8026 | u16 value; | |
8027 | int rc; | |
8028 | ||
8029 | if (prtad != hw->phy.mdio.prtad) | |
8030 | return -EINVAL; | |
8031 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
8032 | if (!rc) | |
8033 | rc = value; | |
8034 | return rc; | |
8035 | } | |
8036 | ||
8037 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
8038 | u16 addr, u16 value) | |
8039 | { | |
8040 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8041 | struct ixgbe_hw *hw = &adapter->hw; | |
8042 | ||
8043 | if (prtad != hw->phy.mdio.prtad) | |
8044 | return -EINVAL; | |
8045 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
8046 | } | |
8047 | ||
8048 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
8049 | { | |
8050 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8051 | ||
3a6a4eda | 8052 | switch (cmd) { |
3a6a4eda | 8053 | case SIOCSHWTSTAMP: |
93501d48 JK |
8054 | return ixgbe_ptp_set_ts_config(adapter, req); |
8055 | case SIOCGHWTSTAMP: | |
8056 | return ixgbe_ptp_get_ts_config(adapter, req); | |
3a6a4eda JK |
8057 | default: |
8058 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
8059 | } | |
6b73e10d BH |
8060 | } |
8061 | ||
0365e6e4 PW |
8062 | /** |
8063 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 8064 | * netdev->dev_addrs |
0365e6e4 PW |
8065 | * @netdev: network interface device structure |
8066 | * | |
8067 | * Returns non-zero on failure | |
8068 | **/ | |
8069 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
8070 | { | |
8071 | int err = 0; | |
8072 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7fa7c9dc | 8073 | struct ixgbe_hw *hw = &adapter->hw; |
0365e6e4 | 8074 | |
7fa7c9dc | 8075 | if (is_valid_ether_addr(hw->mac.san_addr)) { |
0365e6e4 | 8076 | rtnl_lock(); |
7fa7c9dc | 8077 | err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN); |
0365e6e4 | 8078 | rtnl_unlock(); |
7fa7c9dc AD |
8079 | |
8080 | /* update SAN MAC vmdq pool selection */ | |
8081 | hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0)); | |
0365e6e4 PW |
8082 | } |
8083 | return err; | |
8084 | } | |
8085 | ||
8086 | /** | |
8087 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 8088 | * netdev->dev_addrs |
0365e6e4 PW |
8089 | * @netdev: network interface device structure |
8090 | * | |
8091 | * Returns non-zero on failure | |
8092 | **/ | |
8093 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
8094 | { | |
8095 | int err = 0; | |
8096 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
8097 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
8098 | ||
8099 | if (is_valid_ether_addr(mac->san_addr)) { | |
8100 | rtnl_lock(); | |
8101 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
8102 | rtnl_unlock(); | |
8103 | } | |
8104 | return err; | |
8105 | } | |
8106 | ||
9a799d71 AK |
8107 | #ifdef CONFIG_NET_POLL_CONTROLLER |
8108 | /* | |
8109 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
8110 | * without having to re-enable interrupts. It's not called while | |
8111 | * the interrupt routine is executing. | |
8112 | */ | |
8113 | static void ixgbe_netpoll(struct net_device *netdev) | |
8114 | { | |
8115 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 8116 | int i; |
9a799d71 | 8117 | |
1a647bd2 AD |
8118 | /* if interface is down do nothing */ |
8119 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
8120 | return; | |
8121 | ||
856f606e AD |
8122 | /* loop through and schedule all active queues */ |
8123 | for (i = 0; i < adapter->num_q_vectors; i++) | |
8124 | ixgbe_msix_clean_rings(0, adapter->q_vector[i]); | |
9a799d71 | 8125 | } |
9a799d71 | 8126 | |
581330ba | 8127 | #endif |
de1036b1 ED |
8128 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
8129 | struct rtnl_link_stats64 *stats) | |
8130 | { | |
8131 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8132 | int i; | |
8133 | ||
1a51502b | 8134 | rcu_read_lock(); |
de1036b1 | 8135 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 8136 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
8137 | u64 bytes, packets; |
8138 | unsigned int start; | |
8139 | ||
1a51502b ED |
8140 | if (ring) { |
8141 | do { | |
57a7744e | 8142 | start = u64_stats_fetch_begin_irq(&ring->syncp); |
1a51502b ED |
8143 | packets = ring->stats.packets; |
8144 | bytes = ring->stats.bytes; | |
57a7744e | 8145 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); |
1a51502b ED |
8146 | stats->rx_packets += packets; |
8147 | stats->rx_bytes += bytes; | |
8148 | } | |
de1036b1 | 8149 | } |
1ac9ad13 ED |
8150 | |
8151 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
8152 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
8153 | u64 bytes, packets; | |
8154 | unsigned int start; | |
8155 | ||
8156 | if (ring) { | |
8157 | do { | |
57a7744e | 8158 | start = u64_stats_fetch_begin_irq(&ring->syncp); |
1ac9ad13 ED |
8159 | packets = ring->stats.packets; |
8160 | bytes = ring->stats.bytes; | |
57a7744e | 8161 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); |
1ac9ad13 ED |
8162 | stats->tx_packets += packets; |
8163 | stats->tx_bytes += bytes; | |
8164 | } | |
8165 | } | |
1a51502b | 8166 | rcu_read_unlock(); |
de1036b1 ED |
8167 | /* following stats updated by ixgbe_watchdog_task() */ |
8168 | stats->multicast = netdev->stats.multicast; | |
8169 | stats->rx_errors = netdev->stats.rx_errors; | |
8170 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
8171 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
8172 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
8173 | return stats; | |
8174 | } | |
8175 | ||
8af3c33f | 8176 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c BH |
8177 | /** |
8178 | * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. | |
8179 | * @adapter: pointer to ixgbe_adapter | |
8b1c0b24 JF |
8180 | * @tc: number of traffic classes currently enabled |
8181 | * | |
8182 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
8183 | * 802.1Q priority maps to a packet buffer that exists. | |
8184 | */ | |
8185 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
8186 | { | |
8187 | struct ixgbe_hw *hw = &adapter->hw; | |
8188 | u32 reg, rsave; | |
8189 | int i; | |
8190 | ||
8191 | /* 82598 have a static priority to TC mapping that can not | |
8192 | * be changed so no validation is needed. | |
8193 | */ | |
8194 | if (hw->mac.type == ixgbe_mac_82598EB) | |
8195 | return; | |
8196 | ||
8197 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
8198 | rsave = reg; | |
8199 | ||
8200 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
8201 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
8202 | ||
8203 | /* If up2tc is out of bounds default to zero */ | |
8204 | if (up2tc > tc) | |
8205 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
8206 | } | |
8207 | ||
8208 | if (reg != rsave) | |
8209 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
8210 | ||
8211 | return; | |
8212 | } | |
8213 | ||
02debdc9 AD |
8214 | /** |
8215 | * ixgbe_set_prio_tc_map - Configure netdev prio tc map | |
8216 | * @adapter: Pointer to adapter struct | |
8217 | * | |
8218 | * Populate the netdev user priority to tc map | |
8219 | */ | |
8220 | static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) | |
8221 | { | |
8222 | struct net_device *dev = adapter->netdev; | |
8223 | struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; | |
8224 | struct ieee_ets *ets = adapter->ixgbe_ieee_ets; | |
8225 | u8 prio; | |
8226 | ||
8227 | for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { | |
8228 | u8 tc = 0; | |
8229 | ||
8230 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) | |
8231 | tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); | |
8232 | else if (ets) | |
8233 | tc = ets->prio_tc[prio]; | |
8234 | ||
8235 | netdev_set_prio_tc_map(dev, prio, tc); | |
8236 | } | |
8237 | } | |
8238 | ||
cca73c59 | 8239 | #endif /* CONFIG_IXGBE_DCB */ |
49ce9c2c BH |
8240 | /** |
8241 | * ixgbe_setup_tc - configure net_device for multiple traffic classes | |
8b1c0b24 JF |
8242 | * |
8243 | * @netdev: net device to configure | |
8244 | * @tc: number of traffic classes to enable | |
8245 | */ | |
8246 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
8247 | { | |
8b1c0b24 JF |
8248 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
8249 | struct ixgbe_hw *hw = &adapter->hw; | |
2a47fa45 | 8250 | bool pools; |
8b1c0b24 | 8251 | |
8b1c0b24 | 8252 | /* Hardware supports up to 8 traffic classes */ |
7e3f5c88 ET |
8253 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs) |
8254 | return -EINVAL; | |
8255 | ||
8256 | if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS) | |
8b1c0b24 JF |
8257 | return -EINVAL; |
8258 | ||
2a47fa45 JF |
8259 | pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1); |
8260 | if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS) | |
8261 | return -EBUSY; | |
8262 | ||
8b1c0b24 | 8263 | /* Hardware has to reinitialize queues and interrupts to |
52f33af8 | 8264 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
8265 | * hardware is not flexible enough to do this dynamically. |
8266 | */ | |
8267 | if (netif_running(dev)) | |
8268 | ixgbe_close(dev); | |
bf4d67d9 AD |
8269 | else |
8270 | ixgbe_reset(adapter); | |
8271 | ||
8b1c0b24 JF |
8272 | ixgbe_clear_interrupt_scheme(adapter); |
8273 | ||
cca73c59 | 8274 | #ifdef CONFIG_IXGBE_DCB |
e7589eab | 8275 | if (tc) { |
8b1c0b24 | 8276 | netdev_set_num_tc(dev, tc); |
02debdc9 AD |
8277 | ixgbe_set_prio_tc_map(adapter); |
8278 | ||
e7589eab | 8279 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
e7589eab | 8280 | |
943561d3 AD |
8281 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
8282 | adapter->last_lfc_mode = adapter->hw.fc.requested_mode; | |
e7589eab | 8283 | adapter->hw.fc.requested_mode = ixgbe_fc_none; |
943561d3 | 8284 | } |
e7589eab | 8285 | } else { |
8b1c0b24 | 8286 | netdev_reset_tc(dev); |
02debdc9 | 8287 | |
943561d3 AD |
8288 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
8289 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; | |
e7589eab JF |
8290 | |
8291 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
e7589eab JF |
8292 | |
8293 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
8294 | adapter->dcb_cfg.pfc_mode_enable = false; | |
8295 | } | |
8296 | ||
8b1c0b24 | 8297 | ixgbe_validate_rtr(adapter, tc); |
cca73c59 AD |
8298 | |
8299 | #endif /* CONFIG_IXGBE_DCB */ | |
8300 | ixgbe_init_interrupt_scheme(adapter); | |
8301 | ||
8b1c0b24 | 8302 | if (netif_running(dev)) |
cca73c59 | 8303 | return ixgbe_open(dev); |
8b1c0b24 JF |
8304 | |
8305 | return 0; | |
8306 | } | |
de1036b1 | 8307 | |
b82b17d9 JF |
8308 | static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter, |
8309 | struct tc_cls_u32_offload *cls) | |
8310 | { | |
176621c9 SS |
8311 | u32 uhtid = TC_U32_USERHTID(cls->knode.handle); |
8312 | u32 loc; | |
b82b17d9 JF |
8313 | int err; |
8314 | ||
176621c9 SS |
8315 | if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE)) |
8316 | return -EINVAL; | |
8317 | ||
8318 | loc = cls->knode.handle & 0xfffff; | |
8319 | ||
b82b17d9 | 8320 | spin_lock(&adapter->fdir_perfect_lock); |
176621c9 | 8321 | err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc); |
b82b17d9 JF |
8322 | spin_unlock(&adapter->fdir_perfect_lock); |
8323 | return err; | |
8324 | } | |
8325 | ||
db956ae8 JF |
8326 | static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter, |
8327 | __be16 protocol, | |
8328 | struct tc_cls_u32_offload *cls) | |
8329 | { | |
176621c9 SS |
8330 | u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); |
8331 | ||
8332 | if (uhtid >= IXGBE_MAX_LINK_HANDLE) | |
8333 | return -EINVAL; | |
8334 | ||
db956ae8 JF |
8335 | /* This ixgbe devices do not support hash tables at the moment |
8336 | * so abort when given hash tables. | |
8337 | */ | |
8338 | if (cls->hnode.divisor > 0) | |
8339 | return -EINVAL; | |
8340 | ||
176621c9 | 8341 | set_bit(uhtid - 1, &adapter->tables); |
db956ae8 JF |
8342 | return 0; |
8343 | } | |
8344 | ||
8345 | static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter, | |
8346 | struct tc_cls_u32_offload *cls) | |
8347 | { | |
176621c9 SS |
8348 | u32 uhtid = TC_U32_USERHTID(cls->hnode.handle); |
8349 | ||
8350 | if (uhtid >= IXGBE_MAX_LINK_HANDLE) | |
8351 | return -EINVAL; | |
8352 | ||
8353 | clear_bit(uhtid - 1, &adapter->tables); | |
db956ae8 JF |
8354 | return 0; |
8355 | } | |
8356 | ||
947f8a45 SS |
8357 | #ifdef CONFIG_NET_CLS_ACT |
8358 | static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex, | |
8359 | u8 *queue, u64 *action) | |
8360 | { | |
8361 | unsigned int num_vfs = adapter->num_vfs, vf; | |
8362 | struct net_device *upper; | |
8363 | struct list_head *iter; | |
8364 | ||
8365 | /* redirect to a SRIOV VF */ | |
8366 | for (vf = 0; vf < num_vfs; ++vf) { | |
8367 | upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev); | |
8368 | if (upper->ifindex == ifindex) { | |
8369 | if (adapter->num_rx_pools > 1) | |
8370 | *queue = vf * 2; | |
8371 | else | |
8372 | *queue = vf * adapter->num_rx_queues_per_pool; | |
8373 | ||
8374 | *action = vf + 1; | |
8375 | *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF; | |
8376 | return 0; | |
8377 | } | |
8378 | } | |
8379 | ||
8380 | /* redirect to a offloaded macvlan netdev */ | |
8381 | netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) { | |
8382 | if (netif_is_macvlan(upper)) { | |
8383 | struct macvlan_dev *dfwd = netdev_priv(upper); | |
8384 | struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv; | |
8385 | ||
8386 | if (vadapter && vadapter->netdev->ifindex == ifindex) { | |
8387 | *queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx; | |
8388 | *action = *queue; | |
8389 | return 0; | |
8390 | } | |
8391 | } | |
8392 | } | |
8393 | ||
8394 | return -EINVAL; | |
8395 | } | |
8396 | ||
8397 | static int parse_tc_actions(struct ixgbe_adapter *adapter, | |
8398 | struct tcf_exts *exts, u64 *action, u8 *queue) | |
8399 | { | |
8400 | const struct tc_action *a; | |
8401 | int err; | |
8402 | ||
8403 | if (tc_no_actions(exts)) | |
8404 | return -EINVAL; | |
8405 | ||
8406 | tc_for_each_action(a, exts) { | |
8407 | ||
8408 | /* Drop action */ | |
8409 | if (is_tcf_gact_shot(a)) { | |
8410 | *action = IXGBE_FDIR_DROP_QUEUE; | |
8411 | *queue = IXGBE_FDIR_DROP_QUEUE; | |
8412 | return 0; | |
8413 | } | |
8414 | ||
8415 | /* Redirect to a VF or a offloaded macvlan */ | |
8416 | if (is_tcf_mirred_redirect(a)) { | |
8417 | int ifindex = tcf_mirred_ifindex(a); | |
8418 | ||
8419 | err = handle_redirect_action(adapter, ifindex, queue, | |
8420 | action); | |
8421 | if (err == 0) | |
8422 | return err; | |
8423 | } | |
8424 | } | |
8425 | ||
8426 | return -EINVAL; | |
8427 | } | |
8428 | #else | |
8429 | static int parse_tc_actions(struct ixgbe_adapter *adapter, | |
8430 | struct tcf_exts *exts, u64 *action, u8 *queue) | |
8431 | { | |
8432 | return -EINVAL; | |
8433 | } | |
8434 | #endif /* CONFIG_NET_CLS_ACT */ | |
8435 | ||
1cdaaf54 AN |
8436 | static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input, |
8437 | union ixgbe_atr_input *mask, | |
8438 | struct tc_cls_u32_offload *cls, | |
8439 | struct ixgbe_mat_field *field_ptr, | |
8440 | struct ixgbe_nexthdr *nexthdr) | |
8441 | { | |
8442 | int i, j, off; | |
8443 | __be32 val, m; | |
8444 | bool found_entry = false, found_jump_field = false; | |
8445 | ||
8446 | for (i = 0; i < cls->knode.sel->nkeys; i++) { | |
8447 | off = cls->knode.sel->keys[i].off; | |
8448 | val = cls->knode.sel->keys[i].val; | |
8449 | m = cls->knode.sel->keys[i].mask; | |
8450 | ||
8451 | for (j = 0; field_ptr[j].val; j++) { | |
8452 | if (field_ptr[j].off == off) { | |
8453 | field_ptr[j].val(input, mask, val, m); | |
8454 | input->filter.formatted.flow_type |= | |
8455 | field_ptr[j].type; | |
8456 | found_entry = true; | |
8457 | break; | |
8458 | } | |
8459 | } | |
8460 | if (nexthdr) { | |
8461 | if (nexthdr->off == cls->knode.sel->keys[i].off && | |
8462 | nexthdr->val == cls->knode.sel->keys[i].val && | |
8463 | nexthdr->mask == cls->knode.sel->keys[i].mask) | |
8464 | found_jump_field = true; | |
8465 | else | |
8466 | continue; | |
8467 | } | |
8468 | } | |
8469 | ||
8470 | if (nexthdr && !found_jump_field) | |
8471 | return -EINVAL; | |
8472 | ||
8473 | if (!found_entry) | |
8474 | return 0; | |
8475 | ||
8476 | mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | | |
8477 | IXGBE_ATR_L4TYPE_MASK; | |
8478 | ||
8479 | if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4) | |
8480 | mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK; | |
8481 | ||
8482 | return 0; | |
8483 | } | |
8484 | ||
b82b17d9 JF |
8485 | static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter, |
8486 | __be16 protocol, | |
8487 | struct tc_cls_u32_offload *cls) | |
8488 | { | |
8489 | u32 loc = cls->knode.handle & 0xfffff; | |
8490 | struct ixgbe_hw *hw = &adapter->hw; | |
8491 | struct ixgbe_mat_field *field_ptr; | |
1cdaaf54 AN |
8492 | struct ixgbe_fdir_filter *input = NULL; |
8493 | union ixgbe_atr_input *mask = NULL; | |
8494 | struct ixgbe_jump_table *jump = NULL; | |
8495 | int i, err = -EINVAL; | |
b82b17d9 | 8496 | u8 queue; |
176621c9 | 8497 | u32 uhtid, link_uhtid; |
b82b17d9 | 8498 | |
176621c9 SS |
8499 | uhtid = TC_U32_USERHTID(cls->knode.handle); |
8500 | link_uhtid = TC_U32_USERHTID(cls->knode.link_handle); | |
b82b17d9 | 8501 | |
176621c9 | 8502 | /* At the moment cls_u32 jumps to network layer and skips past |
b82b17d9 JF |
8503 | * L2 headers. The canonical method to match L2 frames is to use |
8504 | * negative values. However this is error prone at best but really | |
8505 | * just broken because there is no way to "know" what sort of hdr | |
176621c9 | 8506 | * is in front of the network layer. Fix cls_u32 to support L2 |
b82b17d9 JF |
8507 | * headers when needed. |
8508 | */ | |
8509 | if (protocol != htons(ETH_P_IP)) | |
1cdaaf54 | 8510 | return err; |
b82b17d9 JF |
8511 | |
8512 | if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) { | |
8513 | e_err(drv, "Location out of range\n"); | |
1cdaaf54 | 8514 | return err; |
b82b17d9 JF |
8515 | } |
8516 | ||
8517 | /* cls u32 is a graph starting at root node 0x800. The driver tracks | |
8518 | * links and also the fields used to advance the parser across each | |
8519 | * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map | |
8520 | * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h | |
8521 | * To add support for new nodes update ixgbe_model.h parse structures | |
8522 | * this function _should_ be generic try not to hardcode values here. | |
8523 | */ | |
176621c9 | 8524 | if (uhtid == 0x800) { |
1cdaaf54 | 8525 | field_ptr = (adapter->jump_tables[0])->mat; |
b82b17d9 | 8526 | } else { |
176621c9 | 8527 | if (uhtid >= IXGBE_MAX_LINK_HANDLE) |
1cdaaf54 AN |
8528 | return err; |
8529 | if (!adapter->jump_tables[uhtid]) | |
8530 | return err; | |
8531 | field_ptr = (adapter->jump_tables[uhtid])->mat; | |
b82b17d9 JF |
8532 | } |
8533 | ||
8534 | if (!field_ptr) | |
1cdaaf54 | 8535 | return err; |
b82b17d9 | 8536 | |
1cdaaf54 AN |
8537 | /* At this point we know the field_ptr is valid and need to either |
8538 | * build cls_u32 link or attach filter. Because adding a link to | |
8539 | * a handle that does not exist is invalid and the same for adding | |
8540 | * rules to handles that don't exist. | |
8541 | */ | |
b82b17d9 | 8542 | |
1cdaaf54 AN |
8543 | if (link_uhtid) { |
8544 | struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps; | |
b82b17d9 | 8545 | |
1cdaaf54 AN |
8546 | if (link_uhtid >= IXGBE_MAX_LINK_HANDLE) |
8547 | return err; | |
8548 | ||
8549 | if (!test_bit(link_uhtid - 1, &adapter->tables)) | |
8550 | return err; | |
8551 | ||
8552 | for (i = 0; nexthdr[i].jump; i++) { | |
8553 | if (nexthdr[i].o != cls->knode.sel->offoff || | |
8554 | nexthdr[i].s != cls->knode.sel->offshift || | |
8555 | nexthdr[i].m != cls->knode.sel->offmask) | |
8556 | return err; | |
8557 | ||
8558 | jump = kzalloc(sizeof(*jump), GFP_KERNEL); | |
8559 | if (!jump) | |
8560 | return -ENOMEM; | |
8561 | input = kzalloc(sizeof(*input), GFP_KERNEL); | |
8562 | if (!input) { | |
8563 | err = -ENOMEM; | |
8564 | goto free_jump; | |
8565 | } | |
8566 | mask = kzalloc(sizeof(*mask), GFP_KERNEL); | |
8567 | if (!mask) { | |
8568 | err = -ENOMEM; | |
8569 | goto free_input; | |
8570 | } | |
8571 | jump->input = input; | |
8572 | jump->mask = mask; | |
8573 | err = ixgbe_clsu32_build_input(input, mask, cls, | |
8574 | field_ptr, &nexthdr[i]); | |
8575 | if (!err) { | |
8576 | jump->mat = nexthdr[i].jump; | |
8577 | adapter->jump_tables[link_uhtid] = jump; | |
b82b17d9 JF |
8578 | break; |
8579 | } | |
8580 | } | |
1cdaaf54 | 8581 | return 0; |
b82b17d9 JF |
8582 | } |
8583 | ||
1cdaaf54 AN |
8584 | input = kzalloc(sizeof(*input), GFP_KERNEL); |
8585 | if (!input) | |
8586 | return -ENOMEM; | |
8587 | mask = kzalloc(sizeof(*mask), GFP_KERNEL); | |
8588 | if (!mask) { | |
8589 | err = -ENOMEM; | |
8590 | goto free_input; | |
8591 | } | |
b82b17d9 | 8592 | |
1cdaaf54 AN |
8593 | if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) { |
8594 | if ((adapter->jump_tables[uhtid])->input) | |
8595 | memcpy(input, (adapter->jump_tables[uhtid])->input, | |
8596 | sizeof(*input)); | |
8597 | if ((adapter->jump_tables[uhtid])->mask) | |
8598 | memcpy(mask, (adapter->jump_tables[uhtid])->mask, | |
8599 | sizeof(*mask)); | |
8600 | } | |
8601 | err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL); | |
8602 | if (err) | |
b82b17d9 JF |
8603 | goto err_out; |
8604 | ||
947f8a45 SS |
8605 | err = parse_tc_actions(adapter, cls->knode.exts, &input->action, |
8606 | &queue); | |
8607 | if (err < 0) | |
b82b17d9 | 8608 | goto err_out; |
b82b17d9 | 8609 | |
b82b17d9 JF |
8610 | input->sw_idx = loc; |
8611 | ||
8612 | spin_lock(&adapter->fdir_perfect_lock); | |
8613 | ||
8614 | if (hlist_empty(&adapter->fdir_filter_list)) { | |
1cdaaf54 AN |
8615 | memcpy(&adapter->fdir_mask, mask, sizeof(*mask)); |
8616 | err = ixgbe_fdir_set_input_mask_82599(hw, mask); | |
b82b17d9 JF |
8617 | if (err) |
8618 | goto err_out_w_lock; | |
1cdaaf54 | 8619 | } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) { |
b82b17d9 JF |
8620 | err = -EINVAL; |
8621 | goto err_out_w_lock; | |
8622 | } | |
8623 | ||
1cdaaf54 | 8624 | ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask); |
b82b17d9 JF |
8625 | err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter, |
8626 | input->sw_idx, queue); | |
8627 | if (!err) | |
8628 | ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx); | |
8629 | spin_unlock(&adapter->fdir_perfect_lock); | |
8630 | ||
1cdaaf54 | 8631 | kfree(mask); |
b82b17d9 JF |
8632 | return err; |
8633 | err_out_w_lock: | |
8634 | spin_unlock(&adapter->fdir_perfect_lock); | |
8635 | err_out: | |
1cdaaf54 AN |
8636 | kfree(mask); |
8637 | free_input: | |
b82b17d9 | 8638 | kfree(input); |
1cdaaf54 AN |
8639 | free_jump: |
8640 | kfree(jump); | |
8641 | return err; | |
b82b17d9 JF |
8642 | } |
8643 | ||
6e2a60b5 ET |
8644 | static int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto, |
8645 | struct tc_to_netdev *tc) | |
e4c6734e | 8646 | { |
b82b17d9 JF |
8647 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
8648 | ||
8649 | if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) && | |
8650 | tc->type == TC_SETUP_CLSU32) { | |
b82b17d9 JF |
8651 | switch (tc->cls_u32->command) { |
8652 | case TC_CLSU32_NEW_KNODE: | |
8653 | case TC_CLSU32_REPLACE_KNODE: | |
8654 | return ixgbe_configure_clsu32(adapter, | |
8655 | proto, tc->cls_u32); | |
8656 | case TC_CLSU32_DELETE_KNODE: | |
8657 | return ixgbe_delete_clsu32(adapter, tc->cls_u32); | |
db956ae8 JF |
8658 | case TC_CLSU32_NEW_HNODE: |
8659 | case TC_CLSU32_REPLACE_HNODE: | |
8660 | return ixgbe_configure_clsu32_add_hnode(adapter, proto, | |
8661 | tc->cls_u32); | |
8662 | case TC_CLSU32_DELETE_HNODE: | |
8663 | return ixgbe_configure_clsu32_del_hnode(adapter, | |
8664 | tc->cls_u32); | |
b82b17d9 JF |
8665 | default: |
8666 | return -EINVAL; | |
8667 | } | |
8668 | } | |
8669 | ||
5eb4dce3 | 8670 | if (tc->type != TC_SETUP_MQPRIO) |
e4c6734e JF |
8671 | return -EINVAL; |
8672 | ||
16e5cc64 | 8673 | return ixgbe_setup_tc(dev, tc->tc); |
e4c6734e JF |
8674 | } |
8675 | ||
da36b647 GR |
8676 | #ifdef CONFIG_PCI_IOV |
8677 | void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter) | |
8678 | { | |
8679 | struct net_device *netdev = adapter->netdev; | |
8680 | ||
8681 | rtnl_lock(); | |
da36b647 | 8682 | ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev)); |
da36b647 GR |
8683 | rtnl_unlock(); |
8684 | } | |
8685 | ||
8686 | #endif | |
082757af DS |
8687 | void ixgbe_do_reset(struct net_device *netdev) |
8688 | { | |
8689 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8690 | ||
8691 | if (netif_running(netdev)) | |
8692 | ixgbe_reinit_locked(adapter); | |
8693 | else | |
8694 | ixgbe_reset(adapter); | |
8695 | } | |
8696 | ||
c8f44aff | 8697 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 8698 | netdev_features_t features) |
082757af DS |
8699 | { |
8700 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8701 | ||
082757af | 8702 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ |
567d2de2 AD |
8703 | if (!(features & NETIF_F_RXCSUM)) |
8704 | features &= ~NETIF_F_LRO; | |
082757af | 8705 | |
567d2de2 AD |
8706 | /* Turn off LRO if not RSC capable */ |
8707 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
8708 | features &= ~NETIF_F_LRO; | |
8e2813f5 | 8709 | |
567d2de2 | 8710 | return features; |
082757af DS |
8711 | } |
8712 | ||
c8f44aff | 8713 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 8714 | netdev_features_t features) |
082757af DS |
8715 | { |
8716 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 8717 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
8718 | bool need_reset = false; |
8719 | ||
082757af | 8720 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
8721 | if (!(features & NETIF_F_LRO)) { |
8722 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 8723 | need_reset = true; |
567d2de2 AD |
8724 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
8725 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
8726 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
8727 | if (adapter->rx_itr_setting == 1 || | |
8728 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
8729 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
8730 | need_reset = true; | |
8731 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
8732 | e_info(probe, "rx-usecs set too low, " | |
8733 | "disabling RSC\n"); | |
082757af DS |
8734 | } |
8735 | } | |
8736 | ||
8737 | /* | |
b82b17d9 JF |
8738 | * Check if Flow Director n-tuple support or hw_tc support was |
8739 | * enabled or disabled. If the state changed, we need to reset. | |
082757af | 8740 | */ |
b82b17d9 | 8741 | if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) { |
567d2de2 | 8742 | /* turn off ATR, enable perfect filters and reset */ |
39cb681b AD |
8743 | if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) |
8744 | need_reset = true; | |
8745 | ||
567d2de2 AD |
8746 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
8747 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
b82b17d9 | 8748 | } else { |
39cb681b AD |
8749 | /* turn off perfect filters, enable ATR and reset */ |
8750 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
8751 | need_reset = true; | |
8752 | ||
8753 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
8754 | ||
8755 | /* We cannot enable ATR if SR-IOV is enabled */ | |
b82b17d9 JF |
8756 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED || |
8757 | /* We cannot enable ATR if we have 2 or more tcs */ | |
8758 | (netdev_get_num_tc(netdev) > 1) || | |
8759 | /* We cannot enable ATR if RSS is disabled */ | |
8760 | (adapter->ring_feature[RING_F_RSS].limit <= 1) || | |
8761 | /* A sample rate of 0 indicates ATR disabled */ | |
8762 | (!adapter->atr_sample_rate)) | |
8763 | ; /* do nothing not supported */ | |
8764 | else /* otherwise supported and set the flag */ | |
8765 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
082757af DS |
8766 | } |
8767 | ||
3f2d1c0f BG |
8768 | if (changed & NETIF_F_RXALL) |
8769 | need_reset = true; | |
8770 | ||
567d2de2 | 8771 | netdev->features = features; |
67359c3c MR |
8772 | |
8773 | #ifdef CONFIG_IXGBE_VXLAN | |
8774 | if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) { | |
8775 | if (features & NETIF_F_RXCSUM) | |
8776 | adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED; | |
8777 | else | |
8778 | ixgbe_clear_vxlan_port(adapter); | |
8779 | } | |
8780 | #endif /* CONFIG_IXGBE_VXLAN */ | |
8781 | ||
082757af DS |
8782 | if (need_reset) |
8783 | ixgbe_do_reset(netdev); | |
0c5a6166 AD |
8784 | else if (changed & (NETIF_F_HW_VLAN_CTAG_RX | |
8785 | NETIF_F_HW_VLAN_CTAG_FILTER)) | |
8786 | ixgbe_set_rx_mode(netdev); | |
082757af DS |
8787 | |
8788 | return 0; | |
082757af DS |
8789 | } |
8790 | ||
67359c3c | 8791 | #ifdef CONFIG_IXGBE_VXLAN |
3f207800 DS |
8792 | /** |
8793 | * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up | |
8794 | * @dev: The port's netdev | |
8795 | * @sa_family: Socket Family that VXLAN is notifiying us about | |
8796 | * @port: New UDP port number that VXLAN started listening to | |
8797 | **/ | |
8798 | static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family, | |
8799 | __be16 port) | |
8800 | { | |
8801 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
8802 | struct ixgbe_hw *hw = &adapter->hw; | |
3f207800 | 8803 | |
67359c3c MR |
8804 | if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) |
8805 | return; | |
8806 | ||
3f207800 DS |
8807 | if (sa_family == AF_INET6) |
8808 | return; | |
8809 | ||
9f12df90 | 8810 | if (adapter->vxlan_port == port) |
3f207800 | 8811 | return; |
3f207800 DS |
8812 | |
8813 | if (adapter->vxlan_port) { | |
8814 | netdev_info(dev, | |
67359c3c | 8815 | "Hit Max num of VXLAN ports, not adding port %d\n", |
9f12df90 | 8816 | ntohs(port)); |
3f207800 DS |
8817 | return; |
8818 | } | |
8819 | ||
9f12df90 AD |
8820 | adapter->vxlan_port = port; |
8821 | IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, ntohs(port)); | |
3f207800 DS |
8822 | } |
8823 | ||
8824 | /** | |
8825 | * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away | |
8826 | * @dev: The port's netdev | |
8827 | * @sa_family: Socket Family that VXLAN is notifying us about | |
8828 | * @port: UDP port number that VXLAN stopped listening to | |
8829 | **/ | |
8830 | static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family, | |
8831 | __be16 port) | |
8832 | { | |
8833 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
3f207800 | 8834 | |
67359c3c MR |
8835 | if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) |
8836 | return; | |
8837 | ||
3f207800 DS |
8838 | if (sa_family == AF_INET6) |
8839 | return; | |
8840 | ||
9f12df90 | 8841 | if (adapter->vxlan_port != port) { |
3f207800 | 8842 | netdev_info(dev, "Port %d was not found, not deleting\n", |
9f12df90 | 8843 | ntohs(port)); |
3f207800 DS |
8844 | return; |
8845 | } | |
8846 | ||
67359c3c MR |
8847 | ixgbe_clear_vxlan_port(adapter); |
8848 | adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED; | |
3f207800 | 8849 | } |
67359c3c | 8850 | #endif /* CONFIG_IXGBE_VXLAN */ |
3f207800 | 8851 | |
edc7d573 | 8852 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
0f4b0add | 8853 | struct net_device *dev, |
f6f6424b | 8854 | const unsigned char *addr, u16 vid, |
0f4b0add JF |
8855 | u16 flags) |
8856 | { | |
bcfd3432 | 8857 | /* guarantee we can provide a unique filter for the unicast address */ |
46acc460 | 8858 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) { |
2f9be166 AD |
8859 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
8860 | u16 pool = VMDQ_P(0); | |
8861 | ||
8862 | if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool)) | |
bcfd3432 | 8863 | return -ENOMEM; |
0f4b0add JF |
8864 | } |
8865 | ||
f6f6424b | 8866 | return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags); |
0f4b0add JF |
8867 | } |
8868 | ||
219efe97 DS |
8869 | /** |
8870 | * ixgbe_configure_bridge_mode - set various bridge modes | |
8871 | * @adapter - the private structure | |
8872 | * @mode - requested bridge mode | |
8873 | * | |
8874 | * Configure some settings require for various bridge modes. | |
8875 | **/ | |
8876 | static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter, | |
8877 | __u16 mode) | |
8878 | { | |
6d4c96ad DS |
8879 | struct ixgbe_hw *hw = &adapter->hw; |
8880 | unsigned int p, num_pools; | |
8881 | u32 vmdctl; | |
8882 | ||
219efe97 DS |
8883 | switch (mode) { |
8884 | case BRIDGE_MODE_VEPA: | |
6d4c96ad | 8885 | /* disable Tx loopback, rely on switch hairpin mode */ |
219efe97 | 8886 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0); |
6d4c96ad DS |
8887 | |
8888 | /* must enable Rx switching replication to allow multicast | |
8889 | * packet reception on all VFs, and to enable source address | |
8890 | * pruning. | |
8891 | */ | |
8892 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); | |
8893 | vmdctl |= IXGBE_VT_CTL_REPLEN; | |
8894 | IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); | |
8895 | ||
8896 | /* enable Rx source address pruning. Note, this requires | |
8897 | * replication to be enabled or else it does nothing. | |
8898 | */ | |
8899 | num_pools = adapter->num_vfs + adapter->num_rx_pools; | |
8900 | for (p = 0; p < num_pools; p++) { | |
8901 | if (hw->mac.ops.set_source_address_pruning) | |
8902 | hw->mac.ops.set_source_address_pruning(hw, | |
8903 | true, | |
8904 | p); | |
8905 | } | |
219efe97 DS |
8906 | break; |
8907 | case BRIDGE_MODE_VEB: | |
6d4c96ad | 8908 | /* enable Tx loopback for internal VF/PF communication */ |
219efe97 DS |
8909 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, |
8910 | IXGBE_PFDTXGSWC_VT_LBEN); | |
6d4c96ad DS |
8911 | |
8912 | /* disable Rx switching replication unless we have SR-IOV | |
8913 | * virtual functions | |
8914 | */ | |
8915 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL); | |
8916 | if (!adapter->num_vfs) | |
8917 | vmdctl &= ~IXGBE_VT_CTL_REPLEN; | |
8918 | IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl); | |
8919 | ||
8920 | /* disable Rx source address pruning, since we don't expect to | |
8921 | * be receiving external loopback of our transmitted frames. | |
8922 | */ | |
8923 | num_pools = adapter->num_vfs + adapter->num_rx_pools; | |
8924 | for (p = 0; p < num_pools; p++) { | |
8925 | if (hw->mac.ops.set_source_address_pruning) | |
8926 | hw->mac.ops.set_source_address_pruning(hw, | |
8927 | false, | |
8928 | p); | |
8929 | } | |
219efe97 DS |
8930 | break; |
8931 | default: | |
8932 | return -EINVAL; | |
8933 | } | |
8934 | ||
8935 | adapter->bridge_mode = mode; | |
8936 | ||
8937 | e_info(drv, "enabling bridge mode: %s\n", | |
8938 | mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
8939 | ||
8940 | return 0; | |
8941 | } | |
8942 | ||
815cccbf | 8943 | static int ixgbe_ndo_bridge_setlink(struct net_device *dev, |
add511b3 | 8944 | struct nlmsghdr *nlh, u16 flags) |
815cccbf JF |
8945 | { |
8946 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
8947 | struct nlattr *attr, *br_spec; | |
8948 | int rem; | |
8949 | ||
8950 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
8951 | return -EOPNOTSUPP; | |
8952 | ||
8953 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
4ea85e83 TG |
8954 | if (!br_spec) |
8955 | return -EINVAL; | |
815cccbf JF |
8956 | |
8957 | nla_for_each_nested(attr, br_spec, rem) { | |
a1e869de | 8958 | int status; |
815cccbf | 8959 | __u16 mode; |
815cccbf JF |
8960 | |
8961 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
8962 | continue; | |
8963 | ||
b7c1a314 TG |
8964 | if (nla_len(attr) < sizeof(mode)) |
8965 | return -EINVAL; | |
8966 | ||
815cccbf | 8967 | mode = nla_get_u16(attr); |
219efe97 DS |
8968 | status = ixgbe_configure_bridge_mode(adapter, mode); |
8969 | if (status) | |
8970 | return status; | |
aa2bacb6 DS |
8971 | |
8972 | break; | |
815cccbf JF |
8973 | } |
8974 | ||
8975 | return 0; | |
8976 | } | |
8977 | ||
8978 | static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, | |
6cbdceeb | 8979 | struct net_device *dev, |
46c264da | 8980 | u32 filter_mask, int nlflags) |
815cccbf JF |
8981 | { |
8982 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
815cccbf JF |
8983 | |
8984 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
8985 | return 0; | |
8986 | ||
aa2bacb6 | 8987 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, |
7d4f8d87 SF |
8988 | adapter->bridge_mode, 0, 0, nlflags, |
8989 | filter_mask, NULL); | |
815cccbf JF |
8990 | } |
8991 | ||
2a47fa45 JF |
8992 | static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev) |
8993 | { | |
8994 | struct ixgbe_fwd_adapter *fwd_adapter = NULL; | |
8995 | struct ixgbe_adapter *adapter = netdev_priv(pdev); | |
aac2f1bf | 8996 | int used_pools = adapter->num_vfs + adapter->num_rx_pools; |
51f3773b | 8997 | unsigned int limit; |
2a47fa45 JF |
8998 | int pool, err; |
8999 | ||
aac2f1bf JK |
9000 | /* Hardware has a limited number of available pools. Each VF, and the |
9001 | * PF require a pool. Check to ensure we don't attempt to use more | |
9002 | * then the available number of pools. | |
9003 | */ | |
9004 | if (used_pools >= IXGBE_MAX_VF_FUNCTIONS) | |
9005 | return ERR_PTR(-EINVAL); | |
9006 | ||
219354d4 JF |
9007 | #ifdef CONFIG_RPS |
9008 | if (vdev->num_rx_queues != vdev->num_tx_queues) { | |
9009 | netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n", | |
9010 | vdev->name); | |
9011 | return ERR_PTR(-EINVAL); | |
9012 | } | |
9013 | #endif | |
2a47fa45 | 9014 | /* Check for hardware restriction on number of rx/tx queues */ |
219354d4 | 9015 | if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES || |
2a47fa45 JF |
9016 | vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) { |
9017 | netdev_info(pdev, | |
9018 | "%s: Supports RX/TX Queue counts 1,2, and 4\n", | |
9019 | pdev->name); | |
9020 | return ERR_PTR(-EINVAL); | |
9021 | } | |
9022 | ||
9023 | if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && | |
9024 | adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) || | |
9025 | (adapter->num_rx_pools > IXGBE_MAX_MACVLANS)) | |
9026 | return ERR_PTR(-EBUSY); | |
9027 | ||
bc52f951 | 9028 | fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL); |
2a47fa45 JF |
9029 | if (!fwd_adapter) |
9030 | return ERR_PTR(-ENOMEM); | |
9031 | ||
9032 | pool = find_first_zero_bit(&adapter->fwd_bitmask, 32); | |
9033 | adapter->num_rx_pools++; | |
9034 | set_bit(pool, &adapter->fwd_bitmask); | |
51f3773b | 9035 | limit = find_last_bit(&adapter->fwd_bitmask, 32); |
2a47fa45 JF |
9036 | |
9037 | /* Enable VMDq flag so device will be set in VM mode */ | |
9038 | adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED; | |
51f3773b | 9039 | adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; |
219354d4 | 9040 | adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues; |
2a47fa45 JF |
9041 | |
9042 | /* Force reinit of ring allocation with VMDQ enabled */ | |
9043 | err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); | |
9044 | if (err) | |
9045 | goto fwd_add_err; | |
9046 | fwd_adapter->pool = pool; | |
9047 | fwd_adapter->real_adapter = adapter; | |
9048 | err = ixgbe_fwd_ring_up(vdev, fwd_adapter); | |
9049 | if (err) | |
9050 | goto fwd_add_err; | |
9051 | netif_tx_start_all_queues(vdev); | |
9052 | return fwd_adapter; | |
9053 | fwd_add_err: | |
9054 | /* unwind counter and free adapter struct */ | |
9055 | netdev_info(pdev, | |
9056 | "%s: dfwd hardware acceleration failed\n", vdev->name); | |
9057 | clear_bit(pool, &adapter->fwd_bitmask); | |
9058 | adapter->num_rx_pools--; | |
9059 | kfree(fwd_adapter); | |
9060 | return ERR_PTR(err); | |
9061 | } | |
9062 | ||
9063 | static void ixgbe_fwd_del(struct net_device *pdev, void *priv) | |
9064 | { | |
9065 | struct ixgbe_fwd_adapter *fwd_adapter = priv; | |
9066 | struct ixgbe_adapter *adapter = fwd_adapter->real_adapter; | |
51f3773b | 9067 | unsigned int limit; |
2a47fa45 JF |
9068 | |
9069 | clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask); | |
9070 | adapter->num_rx_pools--; | |
9071 | ||
51f3773b JF |
9072 | limit = find_last_bit(&adapter->fwd_bitmask, 32); |
9073 | adapter->ring_feature[RING_F_VMDQ].limit = limit + 1; | |
2a47fa45 JF |
9074 | ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter); |
9075 | ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev)); | |
9076 | netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n", | |
9077 | fwd_adapter->pool, adapter->num_rx_pools, | |
9078 | fwd_adapter->rx_base_queue, | |
9079 | fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool, | |
9080 | adapter->fwd_bitmask); | |
9081 | kfree(fwd_adapter); | |
9082 | } | |
9083 | ||
b83e3010 AD |
9084 | #define IXGBE_MAX_MAC_HDR_LEN 127 |
9085 | #define IXGBE_MAX_NETWORK_HDR_LEN 511 | |
9086 | ||
f467bc06 MR |
9087 | static netdev_features_t |
9088 | ixgbe_features_check(struct sk_buff *skb, struct net_device *dev, | |
9089 | netdev_features_t features) | |
9090 | { | |
b83e3010 AD |
9091 | unsigned int network_hdr_len, mac_hdr_len; |
9092 | ||
9093 | /* Make certain the headers can be described by a context descriptor */ | |
9094 | mac_hdr_len = skb_network_header(skb) - skb->data; | |
9095 | if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN)) | |
9096 | return features & ~(NETIF_F_HW_CSUM | | |
9097 | NETIF_F_SCTP_CRC | | |
9098 | NETIF_F_HW_VLAN_CTAG_TX | | |
9099 | NETIF_F_TSO | | |
9100 | NETIF_F_TSO6); | |
9101 | ||
9102 | network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb); | |
9103 | if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN)) | |
9104 | return features & ~(NETIF_F_HW_CSUM | | |
9105 | NETIF_F_SCTP_CRC | | |
9106 | NETIF_F_TSO | | |
9107 | NETIF_F_TSO6); | |
9108 | ||
9109 | /* We can only support IPV4 TSO in tunnels if we can mangle the | |
9110 | * inner IP ID field, so strip TSO if MANGLEID is not supported. | |
9111 | */ | |
9112 | if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) | |
9113 | features &= ~NETIF_F_TSO; | |
f467bc06 MR |
9114 | |
9115 | return features; | |
9116 | } | |
9117 | ||
0edc3527 | 9118 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 9119 | .ndo_open = ixgbe_open, |
0edc3527 | 9120 | .ndo_stop = ixgbe_close, |
00829823 | 9121 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 9122 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 9123 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
9124 | .ndo_validate_addr = eth_validate_addr, |
9125 | .ndo_set_mac_address = ixgbe_set_mac, | |
9126 | .ndo_change_mtu = ixgbe_change_mtu, | |
9127 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
c04f90e5 | 9128 | .ndo_set_tx_maxrate = ixgbe_tx_maxrate, |
0edc3527 SH |
9129 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
9130 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 9131 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
9132 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
9133 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
ed616689 | 9134 | .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw, |
581330ba | 9135 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
e65ce0d3 | 9136 | .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en, |
54011e4d | 9137 | .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust, |
7f01648a | 9138 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 9139 | .ndo_get_stats64 = ixgbe_get_stats64, |
e4c6734e | 9140 | .ndo_setup_tc = __ixgbe_setup_tc, |
0edc3527 SH |
9141 | #ifdef CONFIG_NET_POLL_CONTROLLER |
9142 | .ndo_poll_controller = ixgbe_netpoll, | |
9143 | #endif | |
e0d1095a | 9144 | #ifdef CONFIG_NET_RX_BUSY_POLL |
8b80cda5 | 9145 | .ndo_busy_poll = ixgbe_low_latency_recv, |
5a85e737 | 9146 | #endif |
332d4a7d YZ |
9147 | #ifdef IXGBE_FCOE |
9148 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 9149 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 9150 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
9151 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
9152 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 9153 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 9154 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 9155 | #endif /* IXGBE_FCOE */ |
082757af DS |
9156 | .ndo_set_features = ixgbe_set_features, |
9157 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add | 9158 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
815cccbf JF |
9159 | .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink, |
9160 | .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink, | |
2a47fa45 JF |
9161 | .ndo_dfwd_add_station = ixgbe_fwd_add, |
9162 | .ndo_dfwd_del_station = ixgbe_fwd_del, | |
67359c3c | 9163 | #ifdef CONFIG_IXGBE_VXLAN |
3f207800 DS |
9164 | .ndo_add_vxlan_port = ixgbe_add_vxlan_port, |
9165 | .ndo_del_vxlan_port = ixgbe_del_vxlan_port, | |
67359c3c | 9166 | #endif /* CONFIG_IXGBE_VXLAN */ |
f467bc06 | 9167 | .ndo_features_check = ixgbe_features_check, |
0edc3527 SH |
9168 | }; |
9169 | ||
e027d1ae JK |
9170 | /** |
9171 | * ixgbe_enumerate_functions - Get the number of ports this device has | |
9172 | * @adapter: adapter structure | |
9173 | * | |
9174 | * This function enumerates the phsyical functions co-located on a single slot, | |
9175 | * in order to determine how many ports a device has. This is most useful in | |
9176 | * determining the required GT/s of PCIe bandwidth necessary for optimal | |
9177 | * performance. | |
9178 | **/ | |
9179 | static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter) | |
9180 | { | |
caafb95d | 9181 | struct pci_dev *entry, *pdev = adapter->pdev; |
e027d1ae JK |
9182 | int physfns = 0; |
9183 | ||
f1f96579 JK |
9184 | /* Some cards can not use the generic count PCIe functions method, |
9185 | * because they are behind a parent switch, so we hardcode these with | |
9186 | * the correct number of functions. | |
e027d1ae | 9187 | */ |
8818970d | 9188 | if (ixgbe_pcie_from_parent(&adapter->hw)) |
e027d1ae | 9189 | physfns = 4; |
8818970d JK |
9190 | |
9191 | list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) { | |
9192 | /* don't count virtual functions */ | |
caafb95d JK |
9193 | if (entry->is_virtfn) |
9194 | continue; | |
9195 | ||
9196 | /* When the devices on the bus don't all match our device ID, | |
9197 | * we can't reliably determine the correct number of | |
9198 | * functions. This can occur if a function has been direct | |
9199 | * attached to a virtual machine using VT-d, for example. In | |
9200 | * this case, simply return -1 to indicate this. | |
9201 | */ | |
9202 | if ((entry->vendor != pdev->vendor) || | |
9203 | (entry->device != pdev->device)) | |
9204 | return -1; | |
9205 | ||
9206 | physfns++; | |
e027d1ae JK |
9207 | } |
9208 | ||
9209 | return physfns; | |
9210 | } | |
9211 | ||
8e2813f5 JK |
9212 | /** |
9213 | * ixgbe_wol_supported - Check whether device supports WoL | |
740234f0 | 9214 | * @adapter: the adapter private structure |
8e2813f5 JK |
9215 | * @device_id: the device ID |
9216 | * @subdev_id: the subsystem device ID | |
9217 | * | |
9218 | * This function is used by probe and ethtool to determine | |
9219 | * which devices have WoL support | |
9220 | * | |
9221 | **/ | |
740234f0 ET |
9222 | bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, |
9223 | u16 subdevice_id) | |
8e2813f5 JK |
9224 | { |
9225 | struct ixgbe_hw *hw = &adapter->hw; | |
9226 | u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
8e2813f5 | 9227 | |
740234f0 ET |
9228 | /* WOL not supported on 82598 */ |
9229 | if (hw->mac.type == ixgbe_mac_82598EB) | |
9230 | return false; | |
9231 | ||
9232 | /* check eeprom to see if WOL is enabled for X540 and newer */ | |
9233 | if (hw->mac.type >= ixgbe_mac_X540) { | |
9234 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
9235 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
9236 | (hw->bus.func == 0))) | |
9237 | return true; | |
9238 | } | |
9239 | ||
9240 | /* WOL is determined based on device IDs for 82599 MACs */ | |
8e2813f5 JK |
9241 | switch (device_id) { |
9242 | case IXGBE_DEV_ID_82599_SFP: | |
9243 | /* Only these subdevices could supports WOL */ | |
9244 | switch (subdevice_id) { | |
9245 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
00103a6c ET |
9246 | case IXGBE_SUBDEV_ID_82599_LOM_SNAP6: |
9247 | case IXGBE_SUBDEV_ID_82599_SFP_WOL0: | |
9248 | case IXGBE_SUBDEV_ID_82599_SFP_2OCP: | |
8e2813f5 JK |
9249 | /* only support first port */ |
9250 | if (hw->bus.func != 0) | |
9251 | break; | |
5700ff26 | 9252 | case IXGBE_SUBDEV_ID_82599_SP_560FLR: |
8e2813f5 | 9253 | case IXGBE_SUBDEV_ID_82599_SFP: |
b6dfd939 | 9254 | case IXGBE_SUBDEV_ID_82599_RNDC: |
f8a06c2c | 9255 | case IXGBE_SUBDEV_ID_82599_ECNA_DP: |
00103a6c ET |
9256 | case IXGBE_SUBDEV_ID_82599_SFP_1OCP: |
9257 | case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1: | |
9258 | case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2: | |
740234f0 | 9259 | return true; |
8e2813f5 JK |
9260 | } |
9261 | break; | |
5daebbb0 | 9262 | case IXGBE_DEV_ID_82599EN_SFP: |
740234f0 | 9263 | /* Only these subdevices support WOL */ |
5daebbb0 DS |
9264 | switch (subdevice_id) { |
9265 | case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1: | |
740234f0 | 9266 | return true; |
5daebbb0 DS |
9267 | } |
9268 | break; | |
8e2813f5 JK |
9269 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
9270 | /* All except this subdevice support WOL */ | |
9271 | if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) | |
740234f0 | 9272 | return true; |
8e2813f5 JK |
9273 | break; |
9274 | case IXGBE_DEV_ID_82599_KX4: | |
740234f0 ET |
9275 | return true; |
9276 | default: | |
8e2813f5 JK |
9277 | break; |
9278 | } | |
9279 | ||
740234f0 | 9280 | return false; |
8e2813f5 JK |
9281 | } |
9282 | ||
9a799d71 AK |
9283 | /** |
9284 | * ixgbe_probe - Device Initialization Routine | |
9285 | * @pdev: PCI device information struct | |
9286 | * @ent: entry in ixgbe_pci_tbl | |
9287 | * | |
9288 | * Returns 0 on success, negative on failure | |
9289 | * | |
9290 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
9291 | * The OS initialization, configuring of the adapter private structure, | |
9292 | * and a hardware reset occur. | |
9293 | **/ | |
1dd06ae8 | 9294 | static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
9a799d71 AK |
9295 | { |
9296 | struct net_device *netdev; | |
9297 | struct ixgbe_adapter *adapter = NULL; | |
9298 | struct ixgbe_hw *hw; | |
9299 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
e027d1ae | 9300 | int i, err, pci_using_dac, expected_gts; |
d3cb9869 | 9301 | unsigned int indices = MAX_TX_QUEUES; |
289700db | 9302 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
b5b2ffc0 | 9303 | bool disable_dev = false; |
eacd73f7 YZ |
9304 | #ifdef IXGBE_FCOE |
9305 | u16 device_caps; | |
9306 | #endif | |
289700db | 9307 | u32 eec; |
9a799d71 | 9308 | |
bded64a7 AG |
9309 | /* Catch broken hardware that put the wrong VF device ID in |
9310 | * the PCIe SR-IOV capability. | |
9311 | */ | |
9312 | if (pdev->is_virtfn) { | |
9313 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
9314 | pci_name(pdev), pdev->vendor, pdev->device); | |
9315 | return -EINVAL; | |
9316 | } | |
9317 | ||
9ce77666 | 9318 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
9319 | if (err) |
9320 | return err; | |
9321 | ||
f5f2eda8 | 9322 | if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { |
9a799d71 AK |
9323 | pci_using_dac = 1; |
9324 | } else { | |
f5f2eda8 | 9325 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 9326 | if (err) { |
f5f2eda8 RK |
9327 | dev_err(&pdev->dev, |
9328 | "No usable DMA configuration, aborting\n"); | |
9329 | goto err_dma; | |
9a799d71 AK |
9330 | } |
9331 | pci_using_dac = 0; | |
9332 | } | |
9333 | ||
9ce77666 | 9334 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 9335 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 9336 | if (err) { |
b8bc0421 DC |
9337 | dev_err(&pdev->dev, |
9338 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
9339 | goto err_pci_reg; |
9340 | } | |
9341 | ||
19d5afd4 | 9342 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 9343 | |
9a799d71 | 9344 | pci_set_master(pdev); |
fb3b27bc | 9345 | pci_save_state(pdev); |
9a799d71 | 9346 | |
d3cb9869 | 9347 | if (ii->mac == ixgbe_mac_82598EB) { |
e901acd6 | 9348 | #ifdef CONFIG_IXGBE_DCB |
d3cb9869 AD |
9349 | /* 8 TC w/ 4 queues per TC */ |
9350 | indices = 4 * MAX_TRAFFIC_CLASS; | |
9351 | #else | |
9352 | indices = IXGBE_MAX_RSS_INDICES; | |
e901acd6 | 9353 | #endif |
d3cb9869 | 9354 | } |
e901acd6 | 9355 | |
c85a2618 | 9356 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
9357 | if (!netdev) { |
9358 | err = -ENOMEM; | |
9359 | goto err_alloc_etherdev; | |
9360 | } | |
9361 | ||
9a799d71 AK |
9362 | SET_NETDEV_DEV(netdev, &pdev->dev); |
9363 | ||
9a799d71 AK |
9364 | adapter = netdev_priv(netdev); |
9365 | ||
9366 | adapter->netdev = netdev; | |
9367 | adapter->pdev = pdev; | |
9368 | hw = &adapter->hw; | |
9369 | hw->back = adapter; | |
b3f4d599 | 9370 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 9371 | |
05857980 | 9372 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 9373 | pci_resource_len(pdev, 0)); |
2a1a091c | 9374 | adapter->io_addr = hw->hw_addr; |
9a799d71 AK |
9375 | if (!hw->hw_addr) { |
9376 | err = -EIO; | |
9377 | goto err_ioremap; | |
9378 | } | |
9379 | ||
0edc3527 | 9380 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 9381 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 9382 | netdev->watchdog_timeo = 5 * HZ; |
339de30f | 9383 | strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); |
9a799d71 | 9384 | |
9a799d71 | 9385 | /* Setup hw api */ |
37689010 | 9386 | hw->mac.ops = *ii->mac_ops; |
021230d4 | 9387 | hw->mac.type = ii->mac; |
9a900eca | 9388 | hw->mvals = ii->mvals; |
9a799d71 | 9389 | |
c44ade9e | 9390 | /* EEPROM */ |
37689010 | 9391 | hw->eeprom.ops = *ii->eeprom_ops; |
9a900eca | 9392 | eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); |
58cf663f MR |
9393 | if (ixgbe_removed(hw->hw_addr)) { |
9394 | err = -EIO; | |
9395 | goto err_ioremap; | |
9396 | } | |
c44ade9e | 9397 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ |
b4f47a48 | 9398 | if (!(eec & BIT(8))) |
c44ade9e JB |
9399 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; |
9400 | ||
9401 | /* PHY */ | |
37689010 | 9402 | hw->phy.ops = *ii->phy_ops; |
c4900be0 | 9403 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
9404 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
9405 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
9406 | hw->phy.mdio.mmds = 0; | |
9407 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
9408 | hw->phy.mdio.dev = netdev; | |
9409 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
9410 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 9411 | |
8ca783ab | 9412 | ii->get_invariants(hw); |
9a799d71 AK |
9413 | |
9414 | /* setup the private structure */ | |
9415 | err = ixgbe_sw_init(adapter); | |
9416 | if (err) | |
9417 | goto err_sw_init; | |
9418 | ||
dbd15b8f DS |
9419 | /* Make sure the SWFW semaphore is in a valid state */ |
9420 | if (hw->mac.ops.init_swfw_sync) | |
9421 | hw->mac.ops.init_swfw_sync(hw); | |
9422 | ||
e86bff0e | 9423 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
9424 | switch (adapter->hw.mac.type) { |
9425 | case ixgbe_mac_82599EB: | |
9426 | case ixgbe_mac_X540: | |
9a75a1ac DS |
9427 | case ixgbe_mac_X550: |
9428 | case ixgbe_mac_X550EM_x: | |
49425dfc | 9429 | case ixgbe_mac_x550em_a: |
e86bff0e | 9430 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
9431 | break; |
9432 | default: | |
9433 | break; | |
9434 | } | |
e86bff0e | 9435 | |
bf069c97 DS |
9436 | /* |
9437 | * If there is a fan on this device and it has failed log the | |
9438 | * failure. | |
9439 | */ | |
9440 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
9441 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
9442 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 9443 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
9444 | } |
9445 | ||
8ef78adc PWJ |
9446 | if (allow_unsupported_sfp) |
9447 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
9448 | ||
c44ade9e | 9449 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 9450 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 9451 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 9452 | hw->phy.reset_if_overtemp = false; |
29a8dca1 | 9453 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
8ca783ab DS |
9454 | err = 0; |
9455 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
1b1bf31a DS |
9456 | e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n"); |
9457 | e_dev_err("Reload the driver after installing a supported module.\n"); | |
04f165ef PW |
9458 | goto err_sw_init; |
9459 | } else if (err) { | |
849c4542 | 9460 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
9461 | goto err_sw_init; |
9462 | } | |
9463 | ||
99d74487 | 9464 | #ifdef CONFIG_PCI_IOV |
60a1a680 GR |
9465 | /* SR-IOV not supported on the 82598 */ |
9466 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
9467 | goto skip_sriov; | |
9468 | /* Mailbox */ | |
9469 | ixgbe_init_mbx_params_pf(hw); | |
37689010 | 9470 | hw->mbx.ops = ii->mbx_ops; |
dcc23e3a | 9471 | pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT); |
31ac910e | 9472 | ixgbe_enable_sriov(adapter); |
60a1a680 | 9473 | skip_sriov: |
1cdd1ec8 | 9474 | |
99d74487 | 9475 | #endif |
396e799c | 9476 | netdev->features = NETIF_F_SG | |
082757af DS |
9477 | NETIF_F_TSO | |
9478 | NETIF_F_TSO6 | | |
082757af | 9479 | NETIF_F_RXHASH | |
49763de0 | 9480 | NETIF_F_RXCSUM | |
b83e3010 AD |
9481 | NETIF_F_HW_CSUM; |
9482 | ||
9483 | #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \ | |
9484 | NETIF_F_GSO_GRE_CSUM | \ | |
9485 | NETIF_F_GSO_IPIP | \ | |
9486 | NETIF_F_GSO_SIT | \ | |
9487 | NETIF_F_GSO_UDP_TUNNEL | \ | |
9488 | NETIF_F_GSO_UDP_TUNNEL_CSUM) | |
9489 | ||
9490 | netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES; | |
9491 | netdev->features |= NETIF_F_GSO_PARTIAL | | |
9492 | IXGBE_GSO_PARTIAL_FEATURES; | |
ad31c402 | 9493 | |
49763de0 | 9494 | if (hw->mac.type >= ixgbe_mac_82599EB) |
53692b1d | 9495 | netdev->features |= NETIF_F_SCTP_CRC; |
49763de0 AD |
9496 | |
9497 | /* copy netdev features into list of user selectable features */ | |
b83e3010 AD |
9498 | netdev->hw_features |= netdev->features | |
9499 | NETIF_F_HW_VLAN_CTAG_RX | | |
9500 | NETIF_F_HW_VLAN_CTAG_TX | | |
9501 | NETIF_F_RXALL | | |
49763de0 AD |
9502 | NETIF_F_HW_L2FW_DOFFLOAD; |
9503 | ||
9504 | if (hw->mac.type >= ixgbe_mac_82599EB) | |
9505 | netdev->hw_features |= NETIF_F_NTUPLE | | |
b82b17d9 | 9506 | NETIF_F_HW_TC; |
45a5ead0 | 9507 | |
b83e3010 AD |
9508 | if (pci_using_dac) |
9509 | netdev->features |= NETIF_F_HIGHDMA; | |
9510 | ||
5eee87cd AD |
9511 | netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID; |
9512 | netdev->hw_enc_features |= netdev->vlan_features; | |
9513 | netdev->mpls_features |= NETIF_F_HW_CSUM; | |
9514 | ||
b83e3010 AD |
9515 | /* set this bit last since it cannot be part of vlan_features */ |
9516 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | | |
9517 | NETIF_F_HW_VLAN_CTAG_RX | | |
9518 | NETIF_F_HW_VLAN_CTAG_TX; | |
ad31c402 | 9519 | |
01789349 | 9520 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 9521 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 9522 | |
7a6b6f51 | 9523 | #ifdef CONFIG_IXGBE_DCB |
8829009d UK |
9524 | if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE) |
9525 | netdev->dcbnl_ops = &dcbnl_ops; | |
2f90b865 AD |
9526 | #endif |
9527 | ||
eacd73f7 | 9528 | #ifdef IXGBE_FCOE |
0d551589 | 9529 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
d3cb9869 AD |
9530 | unsigned int fcoe_l; |
9531 | ||
eacd73f7 YZ |
9532 | if (hw->mac.ops.get_device_caps) { |
9533 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
9534 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
9535 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 | 9536 | } |
7c8ae65a | 9537 | |
d3cb9869 AD |
9538 | |
9539 | fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus()); | |
9540 | adapter->ring_feature[RING_F_FCOE].limit = fcoe_l; | |
7c8ae65a | 9541 | |
a58915c7 AD |
9542 | netdev->features |= NETIF_F_FSO | |
9543 | NETIF_F_FCOE_CRC; | |
9544 | ||
7c8ae65a AD |
9545 | netdev->vlan_features |= NETIF_F_FSO | |
9546 | NETIF_F_FCOE_CRC | | |
9547 | NETIF_F_FCOE_MTU; | |
5e09d7f6 | 9548 | } |
eacd73f7 | 9549 | #endif /* IXGBE_FCOE */ |
9a799d71 | 9550 | |
082757af DS |
9551 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
9552 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 9553 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
9554 | netdev->features |= NETIF_F_LRO; |
9555 | ||
9a799d71 | 9556 | /* make sure the EEPROM is good */ |
c44ade9e | 9557 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 9558 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 9559 | err = -EIO; |
35937c05 | 9560 | goto err_sw_init; |
9a799d71 AK |
9561 | } |
9562 | ||
c7374b5a SV |
9563 | eth_platform_get_mac_address(&adapter->pdev->dev, |
9564 | adapter->hw.mac.perm_addr); | |
c762dff2 | 9565 | |
9a799d71 | 9566 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); |
9a799d71 | 9567 | |
aaeb6cdf | 9568 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
849c4542 | 9569 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 9570 | err = -EIO; |
35937c05 | 9571 | goto err_sw_init; |
9a799d71 AK |
9572 | } |
9573 | ||
56768045 TD |
9574 | /* Set hw->mac.addr to permanent MAC address */ |
9575 | ether_addr_copy(hw->mac.addr, hw->mac.perm_addr); | |
c9f53e63 | 9576 | ixgbe_mac_set_default_filter(adapter); |
5d7daa35 | 9577 | |
7086400d | 9578 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 9579 | (unsigned long) adapter); |
9a799d71 | 9580 | |
58cf663f MR |
9581 | if (ixgbe_removed(hw->hw_addr)) { |
9582 | err = -EIO; | |
9583 | goto err_sw_init; | |
9584 | } | |
7086400d | 9585 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
58cf663f | 9586 | set_bit(__IXGBE_SERVICE_INITED, &adapter->state); |
7086400d | 9587 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); |
9a799d71 | 9588 | |
021230d4 AV |
9589 | err = ixgbe_init_interrupt_scheme(adapter); |
9590 | if (err) | |
9591 | goto err_sw_init; | |
9a799d71 | 9592 | |
8e2813f5 | 9593 | /* WOL not supported for all devices */ |
c23f5b6b | 9594 | adapter->wol = 0; |
8e2813f5 | 9595 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); |
6b92b0ba | 9596 | hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device, |
b8f83638 | 9597 | pdev->subsystem_device); |
6b92b0ba | 9598 | if (hw->wol_enabled) |
9417c464 | 9599 | adapter->wol = IXGBE_WUFC_MAG; |
c23f5b6b | 9600 | |
e8e26350 PW |
9601 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
9602 | ||
15e5209f ET |
9603 | /* save off EEPROM version number */ |
9604 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
9605 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
9606 | ||
04f165ef | 9607 | /* pick up the PCI bus settings for reporting later */ |
e027d1ae | 9608 | if (ixgbe_pcie_from_parent(hw)) |
b8e82001 | 9609 | ixgbe_get_parent_bus_info(adapter); |
f9328bc6 DS |
9610 | else |
9611 | hw->mac.ops.get_bus_info(hw); | |
04f165ef | 9612 | |
e027d1ae JK |
9613 | /* calculate the expected PCIe bandwidth required for optimal |
9614 | * performance. Note that some older parts will never have enough | |
9615 | * bandwidth due to being older generation PCIe parts. We clamp these | |
9616 | * parts to ensure no warning is displayed if it can't be fixed. | |
9617 | */ | |
9618 | switch (hw->mac.type) { | |
9619 | case ixgbe_mac_82598EB: | |
9620 | expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16); | |
9621 | break; | |
9622 | default: | |
9623 | expected_gts = ixgbe_enumerate_functions(adapter) * 10; | |
9624 | break; | |
0c254d86 | 9625 | } |
caafb95d JK |
9626 | |
9627 | /* don't check link if we failed to enumerate functions */ | |
9628 | if (expected_gts > 0) | |
9629 | ixgbe_check_minimum_link(adapter, expected_gts); | |
0c254d86 | 9630 | |
339de30f | 9631 | err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str)); |
6a2aae5a | 9632 | if (err) |
339de30f | 9633 | strlcpy(part_str, "Unknown", sizeof(part_str)); |
6a2aae5a JK |
9634 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
9635 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", | |
9636 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, | |
e7cf745b | 9637 | part_str); |
6a2aae5a JK |
9638 | else |
9639 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", | |
9640 | hw->mac.type, hw->phy.type, part_str); | |
9641 | ||
9642 | e_dev_info("%pM\n", netdev->dev_addr); | |
9643 | ||
9a799d71 | 9644 | /* reset the hardware with the new settings */ |
794caeb2 | 9645 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
9646 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
9647 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
9648 | e_dev_warn("This device is a pre-production adapter/LOM. " |
9649 | "Please be aware there may be issues associated " | |
9650 | "with your hardware. If you are experiencing " | |
9651 | "problems please contact your Intel or hardware " | |
9652 | "representative who provided you with this " | |
9653 | "hardware.\n"); | |
794caeb2 | 9654 | } |
9a799d71 AK |
9655 | strcpy(netdev->name, "eth%d"); |
9656 | err = register_netdev(netdev); | |
9657 | if (err) | |
9658 | goto err_register; | |
9659 | ||
0fb6a55c ET |
9660 | pci_set_drvdata(pdev, adapter); |
9661 | ||
ec74a471 ET |
9662 | /* power down the optics for 82599 SFP+ fiber */ |
9663 | if (hw->mac.ops.disable_tx_laser) | |
93d3ce8f ET |
9664 | hw->mac.ops.disable_tx_laser(hw); |
9665 | ||
54386467 JB |
9666 | /* carrier off reporting is important to ethtool even BEFORE open */ |
9667 | netif_carrier_off(netdev); | |
9668 | ||
5dd2d332 | 9669 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 9670 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 9671 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
9672 | ixgbe_setup_dca(adapter); |
9673 | } | |
9674 | #endif | |
1cdd1ec8 | 9675 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 9676 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
9677 | for (i = 0; i < adapter->num_vfs; i++) |
9678 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
9679 | } | |
9680 | ||
2466dd9c JK |
9681 | /* firmware requires driver version to be 0xFFFFFFFF |
9682 | * since os does not support feature | |
9683 | */ | |
9612de92 | 9684 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
9685 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
9686 | 0xFF); | |
9612de92 | 9687 | |
0365e6e4 PW |
9688 | /* add san mac addr to netdev */ |
9689 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 9690 | |
ea81875a | 9691 | e_dev_info("%s\n", ixgbe_default_device_descr); |
3ca8bc6d | 9692 | |
1210982b | 9693 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d DS |
9694 | if (ixgbe_sysfs_init(adapter)) |
9695 | e_err(probe, "failed to allocate sysfs resources\n"); | |
1210982b | 9696 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 9697 | |
00949167 | 9698 | ixgbe_dbg_adapter_init(adapter); |
00949167 | 9699 | |
d1a35ee2 ET |
9700 | /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */ |
9701 | if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link) | |
0b2679d6 DS |
9702 | hw->mac.ops.setup_link(hw, |
9703 | IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL, | |
9704 | true); | |
9705 | ||
9a799d71 AK |
9706 | return 0; |
9707 | ||
9708 | err_register: | |
5eba3699 | 9709 | ixgbe_release_hw_control(adapter); |
7a921c93 | 9710 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 9711 | err_sw_init: |
99d74487 | 9712 | ixgbe_disable_sriov(adapter); |
7086400d | 9713 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
2a1a091c | 9714 | iounmap(adapter->io_addr); |
1cdaaf54 | 9715 | kfree(adapter->jump_tables[0]); |
5d7daa35 | 9716 | kfree(adapter->mac_table); |
9a799d71 | 9717 | err_ioremap: |
b5b2ffc0 | 9718 | disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); |
9a799d71 AK |
9719 | free_netdev(netdev); |
9720 | err_alloc_etherdev: | |
e8e9f696 JP |
9721 | pci_release_selected_regions(pdev, |
9722 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
9723 | err_pci_reg: |
9724 | err_dma: | |
b5b2ffc0 | 9725 | if (!adapter || disable_dev) |
41c62843 | 9726 | pci_disable_device(pdev); |
9a799d71 AK |
9727 | return err; |
9728 | } | |
9729 | ||
9730 | /** | |
9731 | * ixgbe_remove - Device Removal Routine | |
9732 | * @pdev: PCI device information struct | |
9733 | * | |
9734 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
9735 | * that it should release a PCI device. The could be caused by a | |
9736 | * Hot-Plug event, or because the driver is going to be removed from | |
9737 | * memory. | |
9738 | **/ | |
9f9a12f8 | 9739 | static void ixgbe_remove(struct pci_dev *pdev) |
9a799d71 | 9740 | { |
c60fbb00 | 9741 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
0fb6a55c | 9742 | struct net_device *netdev; |
b5b2ffc0 | 9743 | bool disable_dev; |
1cdaaf54 | 9744 | int i; |
9a799d71 | 9745 | |
0fb6a55c ET |
9746 | /* if !adapter then we already cleaned up in probe */ |
9747 | if (!adapter) | |
9748 | return; | |
9749 | ||
9750 | netdev = adapter->netdev; | |
00949167 | 9751 | ixgbe_dbg_adapter_exit(adapter); |
00949167 | 9752 | |
09f40aed | 9753 | set_bit(__IXGBE_REMOVING, &adapter->state); |
7086400d | 9754 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 9755 | |
3a6a4eda | 9756 | |
5dd2d332 | 9757 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
9758 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
9759 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
9760 | dca_remove_requester(&pdev->dev); | |
9de7605e MR |
9761 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, |
9762 | IXGBE_DCA_CTRL_DCA_DISABLE); | |
bd0362dd JC |
9763 | } |
9764 | ||
9765 | #endif | |
1210982b | 9766 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d | 9767 | ixgbe_sysfs_exit(adapter); |
1210982b | 9768 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 9769 | |
0365e6e4 PW |
9770 | /* remove the added san mac */ |
9771 | ixgbe_del_sanmac_netdev(netdev); | |
9772 | ||
da36b647 | 9773 | #ifdef CONFIG_PCI_IOV |
7837e286 | 9774 | ixgbe_disable_sriov(adapter); |
da36b647 | 9775 | #endif |
6b010e9b AW |
9776 | if (netdev->reg_state == NETREG_REGISTERED) |
9777 | unregister_netdev(netdev); | |
9778 | ||
7a921c93 | 9779 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 9780 | |
021230d4 | 9781 | ixgbe_release_hw_control(adapter); |
9a799d71 | 9782 | |
2b1588c3 AD |
9783 | #ifdef CONFIG_DCB |
9784 | kfree(adapter->ixgbe_ieee_pfc); | |
9785 | kfree(adapter->ixgbe_ieee_ets); | |
9786 | ||
9787 | #endif | |
2a1a091c | 9788 | iounmap(adapter->io_addr); |
9ce77666 | 9789 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 9790 | IORESOURCE_MEM)); |
9a799d71 | 9791 | |
849c4542 | 9792 | e_dev_info("complete\n"); |
021230d4 | 9793 | |
1cdaaf54 AN |
9794 | for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) { |
9795 | if (adapter->jump_tables[i]) { | |
9796 | kfree(adapter->jump_tables[i]->input); | |
9797 | kfree(adapter->jump_tables[i]->mask); | |
9798 | } | |
9799 | kfree(adapter->jump_tables[i]); | |
9800 | } | |
9801 | ||
5d7daa35 | 9802 | kfree(adapter->mac_table); |
b5b2ffc0 | 9803 | disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state); |
9a799d71 AK |
9804 | free_netdev(netdev); |
9805 | ||
19d5afd4 | 9806 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 9807 | |
b5b2ffc0 | 9808 | if (disable_dev) |
41c62843 | 9809 | pci_disable_device(pdev); |
9a799d71 AK |
9810 | } |
9811 | ||
9812 | /** | |
9813 | * ixgbe_io_error_detected - called when PCI error is detected | |
9814 | * @pdev: Pointer to PCI device | |
9815 | * @state: The current pci connection state | |
9816 | * | |
9817 | * This function is called after a PCI bus error affecting | |
9818 | * this device has been detected. | |
9819 | */ | |
9820 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 9821 | pci_channel_state_t state) |
9a799d71 | 9822 | { |
c60fbb00 AD |
9823 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
9824 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 9825 | |
83c61fa9 | 9826 | #ifdef CONFIG_PCI_IOV |
14438464 | 9827 | struct ixgbe_hw *hw = &adapter->hw; |
83c61fa9 GR |
9828 | struct pci_dev *bdev, *vfdev; |
9829 | u32 dw0, dw1, dw2, dw3; | |
9830 | int vf, pos; | |
9831 | u16 req_id, pf_func; | |
9832 | ||
9833 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
9834 | adapter->num_vfs == 0) | |
9835 | goto skip_bad_vf_detection; | |
9836 | ||
9837 | bdev = pdev->bus->self; | |
62f87c0e | 9838 | while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT)) |
83c61fa9 GR |
9839 | bdev = bdev->bus->self; |
9840 | ||
9841 | if (!bdev) | |
9842 | goto skip_bad_vf_detection; | |
9843 | ||
9844 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
9845 | if (!pos) | |
9846 | goto skip_bad_vf_detection; | |
9847 | ||
14438464 MR |
9848 | dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); |
9849 | dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4); | |
9850 | dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8); | |
9851 | dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12); | |
9852 | if (ixgbe_removed(hw->hw_addr)) | |
9853 | goto skip_bad_vf_detection; | |
83c61fa9 GR |
9854 | |
9855 | req_id = dw1 >> 16; | |
9856 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
9857 | if (!(req_id & 0x0080)) | |
9858 | goto skip_bad_vf_detection; | |
9859 | ||
9860 | pf_func = req_id & 0x01; | |
9861 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
9862 | unsigned int device_id; | |
9863 | ||
9864 | vf = (req_id & 0x7F) >> 1; | |
9865 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
9866 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
9867 | "%8.8x\tdw3: %8.8x\n", | |
9868 | dw0, dw1, dw2, dw3); | |
9869 | switch (adapter->hw.mac.type) { | |
9870 | case ixgbe_mac_82599EB: | |
9871 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
9872 | break; | |
9873 | case ixgbe_mac_X540: | |
9874 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
9875 | break; | |
9a75a1ac DS |
9876 | case ixgbe_mac_X550: |
9877 | device_id = IXGBE_DEV_ID_X550_VF; | |
9878 | break; | |
9879 | case ixgbe_mac_X550EM_x: | |
9880 | device_id = IXGBE_DEV_ID_X550EM_X_VF; | |
9881 | break; | |
49425dfc MR |
9882 | case ixgbe_mac_x550em_a: |
9883 | device_id = IXGBE_DEV_ID_X550EM_A_VF; | |
9884 | break; | |
83c61fa9 GR |
9885 | default: |
9886 | device_id = 0; | |
9887 | break; | |
9888 | } | |
9889 | ||
9890 | /* Find the pci device of the offending VF */ | |
36e90319 | 9891 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL); |
83c61fa9 GR |
9892 | while (vfdev) { |
9893 | if (vfdev->devfn == (req_id & 0xFF)) | |
9894 | break; | |
36e90319 | 9895 | vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
83c61fa9 GR |
9896 | device_id, vfdev); |
9897 | } | |
9898 | /* | |
9899 | * There's a slim chance the VF could have been hot plugged, | |
9900 | * so if it is no longer present we don't need to issue the | |
9901 | * VFLR. Just clean up the AER in that case. | |
9902 | */ | |
9903 | if (vfdev) { | |
9079e416 | 9904 | ixgbe_issue_vf_flr(adapter, vfdev); |
b4fafbe9 GR |
9905 | /* Free device reference count */ |
9906 | pci_dev_put(vfdev); | |
83c61fa9 GR |
9907 | } |
9908 | ||
9909 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
9910 | } | |
9911 | ||
9912 | /* | |
9913 | * Even though the error may have occurred on the other port | |
9914 | * we still need to increment the vf error reference count for | |
9915 | * both ports because the I/O resume function will be called | |
9916 | * for both of them. | |
9917 | */ | |
9918 | adapter->vferr_refcount++; | |
9919 | ||
9920 | return PCI_ERS_RESULT_RECOVERED; | |
9921 | ||
9922 | skip_bad_vf_detection: | |
9923 | #endif /* CONFIG_PCI_IOV */ | |
58cf663f MR |
9924 | if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state)) |
9925 | return PCI_ERS_RESULT_DISCONNECT; | |
9926 | ||
41c62843 | 9927 | rtnl_lock(); |
9a799d71 AK |
9928 | netif_device_detach(netdev); |
9929 | ||
41c62843 MR |
9930 | if (state == pci_channel_io_perm_failure) { |
9931 | rtnl_unlock(); | |
3044b8d1 | 9932 | return PCI_ERS_RESULT_DISCONNECT; |
41c62843 | 9933 | } |
3044b8d1 | 9934 | |
9a799d71 AK |
9935 | if (netif_running(netdev)) |
9936 | ixgbe_down(adapter); | |
41c62843 MR |
9937 | |
9938 | if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state)) | |
9939 | pci_disable_device(pdev); | |
9940 | rtnl_unlock(); | |
9a799d71 | 9941 | |
b4617240 | 9942 | /* Request a slot reset. */ |
9a799d71 AK |
9943 | return PCI_ERS_RESULT_NEED_RESET; |
9944 | } | |
9945 | ||
9946 | /** | |
9947 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
9948 | * @pdev: Pointer to PCI device | |
9949 | * | |
9950 | * Restart the card from scratch, as if from a cold-boot. | |
9951 | */ | |
9952 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
9953 | { | |
c60fbb00 | 9954 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
9955 | pci_ers_result_t result; |
9956 | int err; | |
9a799d71 | 9957 | |
9ce77666 | 9958 | if (pci_enable_device_mem(pdev)) { |
396e799c | 9959 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
9960 | result = PCI_ERS_RESULT_DISCONNECT; |
9961 | } else { | |
4e857c58 | 9962 | smp_mb__before_atomic(); |
41c62843 | 9963 | clear_bit(__IXGBE_DISABLED, &adapter->state); |
0391bbe3 | 9964 | adapter->hw.hw_addr = adapter->io_addr; |
6fabd715 PWJ |
9965 | pci_set_master(pdev); |
9966 | pci_restore_state(pdev); | |
c0e1f68b | 9967 | pci_save_state(pdev); |
9a799d71 | 9968 | |
dd4d8ca6 | 9969 | pci_wake_from_d3(pdev, false); |
9a799d71 | 9970 | |
6fabd715 | 9971 | ixgbe_reset(adapter); |
88512539 | 9972 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
9973 | result = PCI_ERS_RESULT_RECOVERED; |
9974 | } | |
9975 | ||
9976 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
9977 | if (err) { | |
849c4542 ET |
9978 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
9979 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
9980 | /* non-fatal, continue */ |
9981 | } | |
9a799d71 | 9982 | |
6fabd715 | 9983 | return result; |
9a799d71 AK |
9984 | } |
9985 | ||
9986 | /** | |
9987 | * ixgbe_io_resume - called when traffic can start flowing again. | |
9988 | * @pdev: Pointer to PCI device | |
9989 | * | |
9990 | * This callback is called when the error recovery driver tells us that | |
9991 | * its OK to resume normal operation. | |
9992 | */ | |
9993 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
9994 | { | |
c60fbb00 AD |
9995 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
9996 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 9997 | |
83c61fa9 GR |
9998 | #ifdef CONFIG_PCI_IOV |
9999 | if (adapter->vferr_refcount) { | |
10000 | e_info(drv, "Resuming after VF err\n"); | |
10001 | adapter->vferr_refcount--; | |
10002 | return; | |
10003 | } | |
10004 | ||
10005 | #endif | |
c7ccde0f AD |
10006 | if (netif_running(netdev)) |
10007 | ixgbe_up(adapter); | |
9a799d71 AK |
10008 | |
10009 | netif_device_attach(netdev); | |
9a799d71 AK |
10010 | } |
10011 | ||
3646f0e5 | 10012 | static const struct pci_error_handlers ixgbe_err_handler = { |
9a799d71 AK |
10013 | .error_detected = ixgbe_io_error_detected, |
10014 | .slot_reset = ixgbe_io_slot_reset, | |
10015 | .resume = ixgbe_io_resume, | |
10016 | }; | |
10017 | ||
10018 | static struct pci_driver ixgbe_driver = { | |
10019 | .name = ixgbe_driver_name, | |
10020 | .id_table = ixgbe_pci_tbl, | |
10021 | .probe = ixgbe_probe, | |
9f9a12f8 | 10022 | .remove = ixgbe_remove, |
9a799d71 AK |
10023 | #ifdef CONFIG_PM |
10024 | .suspend = ixgbe_suspend, | |
10025 | .resume = ixgbe_resume, | |
10026 | #endif | |
10027 | .shutdown = ixgbe_shutdown, | |
da36b647 | 10028 | .sriov_configure = ixgbe_pci_sriov_configure, |
9a799d71 AK |
10029 | .err_handler = &ixgbe_err_handler |
10030 | }; | |
10031 | ||
10032 | /** | |
10033 | * ixgbe_init_module - Driver Registration Routine | |
10034 | * | |
10035 | * ixgbe_init_module is the first routine called when the driver is | |
10036 | * loaded. All it does is register with the PCI subsystem. | |
10037 | **/ | |
10038 | static int __init ixgbe_init_module(void) | |
10039 | { | |
10040 | int ret; | |
c7689578 | 10041 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 10042 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 10043 | |
780484d8 MR |
10044 | ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name); |
10045 | if (!ixgbe_wq) { | |
10046 | pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name); | |
10047 | return -ENOMEM; | |
10048 | } | |
10049 | ||
00949167 | 10050 | ixgbe_dbg_init(); |
00949167 | 10051 | |
f01fc1a8 JK |
10052 | ret = pci_register_driver(&ixgbe_driver); |
10053 | if (ret) { | |
f01fc1a8 | 10054 | ixgbe_dbg_exit(); |
f01fc1a8 JK |
10055 | return ret; |
10056 | } | |
10057 | ||
5dd2d332 | 10058 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 10059 | dca_register_notify(&dca_notifier); |
bd0362dd | 10060 | #endif |
5dd2d332 | 10061 | |
f01fc1a8 | 10062 | return 0; |
9a799d71 | 10063 | } |
b4617240 | 10064 | |
9a799d71 AK |
10065 | module_init(ixgbe_init_module); |
10066 | ||
10067 | /** | |
10068 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
10069 | * | |
10070 | * ixgbe_exit_module is called just before the driver is removed | |
10071 | * from memory. | |
10072 | **/ | |
10073 | static void __exit ixgbe_exit_module(void) | |
10074 | { | |
5dd2d332 | 10075 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
10076 | dca_unregister_notify(&dca_notifier); |
10077 | #endif | |
9a799d71 | 10078 | pci_unregister_driver(&ixgbe_driver); |
00949167 | 10079 | |
00949167 | 10080 | ixgbe_dbg_exit(); |
780484d8 MR |
10081 | if (ixgbe_wq) { |
10082 | destroy_workqueue(ixgbe_wq); | |
10083 | ixgbe_wq = NULL; | |
10084 | } | |
9a799d71 | 10085 | } |
bd0362dd | 10086 | |
5dd2d332 | 10087 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 10088 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 10089 | void *p) |
bd0362dd JC |
10090 | { |
10091 | int ret_val; | |
10092 | ||
10093 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 10094 | __ixgbe_notify_dca); |
bd0362dd JC |
10095 | |
10096 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
10097 | } | |
b453368d | 10098 | |
5dd2d332 | 10099 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 10100 | |
9a799d71 AK |
10101 | module_exit(ixgbe_exit_module); |
10102 | ||
10103 | /* ixgbe_main.c */ |