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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
a52055e0 | 4 | Copyright(c) 1999 - 2011 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
eacd73f7 | 48 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
49 | |
50 | #include "ixgbe.h" | |
51 | #include "ixgbe_common.h" | |
ee5f784a | 52 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 53 | #include "ixgbe_sriov.h" |
9a799d71 AK |
54 | |
55 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 56 | static const char ixgbe_driver_string[] = |
e8e9f696 | 57 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
75e3d3c6 | 58 | #define MAJ 3 |
a38a104d | 59 | #define MIN 4 |
c89c7112 | 60 | #define BUILD 8 |
75e3d3c6 | 61 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
a38a104d | 62 | __stringify(BUILD) "-k" |
9c8eb720 | 63 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 DS |
64 | static const char ixgbe_copyright[] = |
65 | "Copyright (c) 1999-2011 Intel Corporation."; | |
9a799d71 AK |
66 | |
67 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 68 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 69 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 70 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
71 | }; |
72 | ||
73 | /* ixgbe_pci_tbl - PCI Device ID Table | |
74 | * | |
75 | * Wildcard entries (PCI_ANY_ID) should come last | |
76 | * Last entry must be all 0s | |
77 | * | |
78 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
79 | * Class, Class Mask, private data (not used) } | |
80 | */ | |
a3aa1884 | 81 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
82 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
83 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
84 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
86 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
88 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
9a799d71 AK |
108 | /* required last entry */ |
109 | {0, } | |
110 | }; | |
111 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
112 | ||
5dd2d332 | 113 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 114 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 115 | void *p); |
bd0362dd JC |
116 | static struct notifier_block dca_notifier = { |
117 | .notifier_call = ixgbe_notify_dca, | |
118 | .next = NULL, | |
119 | .priority = 0 | |
120 | }; | |
121 | #endif | |
122 | ||
1cdd1ec8 GR |
123 | #ifdef CONFIG_PCI_IOV |
124 | static unsigned int max_vfs; | |
125 | module_param(max_vfs, uint, 0); | |
e8e9f696 JP |
126 | MODULE_PARM_DESC(max_vfs, |
127 | "Maximum number of virtual functions to allocate per physical function"); | |
1cdd1ec8 GR |
128 | #endif /* CONFIG_PCI_IOV */ |
129 | ||
9a799d71 AK |
130 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
131 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
132 | MODULE_LICENSE("GPL"); | |
133 | MODULE_VERSION(DRV_VERSION); | |
134 | ||
135 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
136 | ||
1cdd1ec8 GR |
137 | static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter) |
138 | { | |
139 | struct ixgbe_hw *hw = &adapter->hw; | |
140 | u32 gcr; | |
141 | u32 gpie; | |
142 | u32 vmdctl; | |
143 | ||
144 | #ifdef CONFIG_PCI_IOV | |
145 | /* disable iov and allow time for transactions to clear */ | |
146 | pci_disable_sriov(adapter->pdev); | |
147 | #endif | |
148 | ||
149 | /* turn off device IOV mode */ | |
150 | gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
151 | gcr &= ~(IXGBE_GCR_EXT_SRIOV); | |
152 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr); | |
153 | gpie = IXGBE_READ_REG(hw, IXGBE_GPIE); | |
154 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
155 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
156 | ||
157 | /* set default pool back to 0 */ | |
158 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
159 | vmdctl &= ~IXGBE_VT_CTL_POOL_MASK; | |
160 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl); | |
945a5151 | 161 | IXGBE_WRITE_FLUSH(hw); |
1cdd1ec8 GR |
162 | |
163 | /* take a breather then clean up driver data */ | |
164 | msleep(100); | |
e8e9f696 JP |
165 | |
166 | kfree(adapter->vfinfo); | |
1cdd1ec8 GR |
167 | adapter->vfinfo = NULL; |
168 | ||
169 | adapter->num_vfs = 0; | |
170 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
171 | } | |
172 | ||
7086400d AD |
173 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
174 | { | |
175 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
176 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
177 | schedule_work(&adapter->service_task); | |
178 | } | |
179 | ||
180 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
181 | { | |
182 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
183 | ||
184 | /* flush memory to make sure state is correct before next watchog */ | |
185 | smp_mb__before_clear_bit(); | |
186 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
187 | } | |
188 | ||
dcd79aeb TI |
189 | struct ixgbe_reg_info { |
190 | u32 ofs; | |
191 | char *name; | |
192 | }; | |
193 | ||
194 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
195 | ||
196 | /* General Registers */ | |
197 | {IXGBE_CTRL, "CTRL"}, | |
198 | {IXGBE_STATUS, "STATUS"}, | |
199 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
200 | ||
201 | /* Interrupt Registers */ | |
202 | {IXGBE_EICR, "EICR"}, | |
203 | ||
204 | /* RX Registers */ | |
205 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
206 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
207 | {IXGBE_RDLEN(0), "RDLEN"}, | |
208 | {IXGBE_RDH(0), "RDH"}, | |
209 | {IXGBE_RDT(0), "RDT"}, | |
210 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
211 | {IXGBE_RDBAL(0), "RDBAL"}, | |
212 | {IXGBE_RDBAH(0), "RDBAH"}, | |
213 | ||
214 | /* TX Registers */ | |
215 | {IXGBE_TDBAL(0), "TDBAL"}, | |
216 | {IXGBE_TDBAH(0), "TDBAH"}, | |
217 | {IXGBE_TDLEN(0), "TDLEN"}, | |
218 | {IXGBE_TDH(0), "TDH"}, | |
219 | {IXGBE_TDT(0), "TDT"}, | |
220 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
221 | ||
222 | /* List Terminator */ | |
223 | {} | |
224 | }; | |
225 | ||
226 | ||
227 | /* | |
228 | * ixgbe_regdump - register printout routine | |
229 | */ | |
230 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
231 | { | |
232 | int i = 0, j = 0; | |
233 | char rname[16]; | |
234 | u32 regs[64]; | |
235 | ||
236 | switch (reginfo->ofs) { | |
237 | case IXGBE_SRRCTL(0): | |
238 | for (i = 0; i < 64; i++) | |
239 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
240 | break; | |
241 | case IXGBE_DCA_RXCTRL(0): | |
242 | for (i = 0; i < 64; i++) | |
243 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
244 | break; | |
245 | case IXGBE_RDLEN(0): | |
246 | for (i = 0; i < 64; i++) | |
247 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
248 | break; | |
249 | case IXGBE_RDH(0): | |
250 | for (i = 0; i < 64; i++) | |
251 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
252 | break; | |
253 | case IXGBE_RDT(0): | |
254 | for (i = 0; i < 64; i++) | |
255 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
256 | break; | |
257 | case IXGBE_RXDCTL(0): | |
258 | for (i = 0; i < 64; i++) | |
259 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
260 | break; | |
261 | case IXGBE_RDBAL(0): | |
262 | for (i = 0; i < 64; i++) | |
263 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
264 | break; | |
265 | case IXGBE_RDBAH(0): | |
266 | for (i = 0; i < 64; i++) | |
267 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
268 | break; | |
269 | case IXGBE_TDBAL(0): | |
270 | for (i = 0; i < 64; i++) | |
271 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
272 | break; | |
273 | case IXGBE_TDBAH(0): | |
274 | for (i = 0; i < 64; i++) | |
275 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
276 | break; | |
277 | case IXGBE_TDLEN(0): | |
278 | for (i = 0; i < 64; i++) | |
279 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
280 | break; | |
281 | case IXGBE_TDH(0): | |
282 | for (i = 0; i < 64; i++) | |
283 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
284 | break; | |
285 | case IXGBE_TDT(0): | |
286 | for (i = 0; i < 64; i++) | |
287 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
288 | break; | |
289 | case IXGBE_TXDCTL(0): | |
290 | for (i = 0; i < 64; i++) | |
291 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
292 | break; | |
293 | default: | |
c7689578 | 294 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
295 | IXGBE_READ_REG(hw, reginfo->ofs)); |
296 | return; | |
297 | } | |
298 | ||
299 | for (i = 0; i < 8; i++) { | |
300 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 301 | pr_err("%-15s", rname); |
dcd79aeb | 302 | for (j = 0; j < 8; j++) |
c7689578 JP |
303 | pr_cont(" %08x", regs[i*8+j]); |
304 | pr_cont("\n"); | |
dcd79aeb TI |
305 | } |
306 | ||
307 | } | |
308 | ||
309 | /* | |
310 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
311 | */ | |
312 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
313 | { | |
314 | struct net_device *netdev = adapter->netdev; | |
315 | struct ixgbe_hw *hw = &adapter->hw; | |
316 | struct ixgbe_reg_info *reginfo; | |
317 | int n = 0; | |
318 | struct ixgbe_ring *tx_ring; | |
319 | struct ixgbe_tx_buffer *tx_buffer_info; | |
320 | union ixgbe_adv_tx_desc *tx_desc; | |
321 | struct my_u0 { u64 a; u64 b; } *u0; | |
322 | struct ixgbe_ring *rx_ring; | |
323 | union ixgbe_adv_rx_desc *rx_desc; | |
324 | struct ixgbe_rx_buffer *rx_buffer_info; | |
325 | u32 staterr; | |
326 | int i = 0; | |
327 | ||
328 | if (!netif_msg_hw(adapter)) | |
329 | return; | |
330 | ||
331 | /* Print netdevice Info */ | |
332 | if (netdev) { | |
333 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 334 | pr_info("Device Name state " |
dcd79aeb | 335 | "trans_start last_rx\n"); |
c7689578 JP |
336 | pr_info("%-15s %016lX %016lX %016lX\n", |
337 | netdev->name, | |
338 | netdev->state, | |
339 | netdev->trans_start, | |
340 | netdev->last_rx); | |
dcd79aeb TI |
341 | } |
342 | ||
343 | /* Print Registers */ | |
344 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 345 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
346 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
347 | reginfo->name; reginfo++) { | |
348 | ixgbe_regdump(hw, reginfo); | |
349 | } | |
350 | ||
351 | /* Print TX Ring Summary */ | |
352 | if (!netdev || !netif_running(netdev)) | |
353 | goto exit; | |
354 | ||
355 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 356 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
357 | for (n = 0; n < adapter->num_tx_queues; n++) { |
358 | tx_ring = adapter->tx_ring[n]; | |
359 | tx_buffer_info = | |
360 | &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; | |
d3d00239 | 361 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
dcd79aeb TI |
362 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
363 | (u64)tx_buffer_info->dma, | |
364 | tx_buffer_info->length, | |
365 | tx_buffer_info->next_to_watch, | |
366 | (u64)tx_buffer_info->time_stamp); | |
367 | } | |
368 | ||
369 | /* Print TX Rings */ | |
370 | if (!netif_msg_tx_done(adapter)) | |
371 | goto rx_ring_summary; | |
372 | ||
373 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
374 | ||
375 | /* Transmit Descriptor Formats | |
376 | * | |
377 | * Advanced Transmit Descriptor | |
378 | * +--------------------------------------------------------------+ | |
379 | * 0 | Buffer Address [63:0] | | |
380 | * +--------------------------------------------------------------+ | |
381 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
382 | * +--------------------------------------------------------------+ | |
383 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
384 | */ | |
385 | ||
386 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
387 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
388 | pr_info("------------------------------------\n"); |
389 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
390 | pr_info("------------------------------------\n"); | |
391 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
392 | "[PlPOIdStDDt Ln] [bi->dma ] " |
393 | "leng ntw timestamp bi->skb\n"); | |
394 | ||
395 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
31f05a2d | 396 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
dcd79aeb TI |
397 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
398 | u0 = (struct my_u0 *)tx_desc; | |
c7689578 | 399 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
d3d00239 | 400 | " %04X %p %016llX %p", i, |
dcd79aeb TI |
401 | le64_to_cpu(u0->a), |
402 | le64_to_cpu(u0->b), | |
403 | (u64)tx_buffer_info->dma, | |
404 | tx_buffer_info->length, | |
405 | tx_buffer_info->next_to_watch, | |
406 | (u64)tx_buffer_info->time_stamp, | |
407 | tx_buffer_info->skb); | |
408 | if (i == tx_ring->next_to_use && | |
409 | i == tx_ring->next_to_clean) | |
c7689578 | 410 | pr_cont(" NTC/U\n"); |
dcd79aeb | 411 | else if (i == tx_ring->next_to_use) |
c7689578 | 412 | pr_cont(" NTU\n"); |
dcd79aeb | 413 | else if (i == tx_ring->next_to_clean) |
c7689578 | 414 | pr_cont(" NTC\n"); |
dcd79aeb | 415 | else |
c7689578 | 416 | pr_cont("\n"); |
dcd79aeb TI |
417 | |
418 | if (netif_msg_pktdata(adapter) && | |
419 | tx_buffer_info->dma != 0) | |
420 | print_hex_dump(KERN_INFO, "", | |
421 | DUMP_PREFIX_ADDRESS, 16, 1, | |
422 | phys_to_virt(tx_buffer_info->dma), | |
423 | tx_buffer_info->length, true); | |
424 | } | |
425 | } | |
426 | ||
427 | /* Print RX Rings Summary */ | |
428 | rx_ring_summary: | |
429 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 430 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
431 | for (n = 0; n < adapter->num_rx_queues; n++) { |
432 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
433 | pr_info("%5d %5X %5X\n", |
434 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
435 | } |
436 | ||
437 | /* Print RX Rings */ | |
438 | if (!netif_msg_rx_status(adapter)) | |
439 | goto exit; | |
440 | ||
441 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
442 | ||
443 | /* Advanced Receive Descriptor (Read) Format | |
444 | * 63 1 0 | |
445 | * +-----------------------------------------------------+ | |
446 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
447 | * +----------------------------------------------+------+ | |
448 | * 8 | Header Buffer Address [63:1] | DD | | |
449 | * +-----------------------------------------------------+ | |
450 | * | |
451 | * | |
452 | * Advanced Receive Descriptor (Write-Back) Format | |
453 | * | |
454 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
455 | * +------------------------------------------------------+ | |
456 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
457 | * | Checksum Ident | | | | Type | Type | | |
458 | * +------------------------------------------------------+ | |
459 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
460 | * +------------------------------------------------------+ | |
461 | * 63 48 47 32 31 20 19 0 | |
462 | */ | |
463 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
464 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
465 | pr_info("------------------------------------\n"); |
466 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
467 | pr_info("------------------------------------\n"); | |
468 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
469 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
470 | "<-- Adv Rx Read format\n"); | |
c7689578 | 471 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
472 | "[vl er S cks ln] ---------------- [bi->skb] " |
473 | "<-- Adv Rx Write-Back format\n"); | |
474 | ||
475 | for (i = 0; i < rx_ring->count; i++) { | |
476 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
31f05a2d | 477 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
dcd79aeb TI |
478 | u0 = (struct my_u0 *)rx_desc; |
479 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
480 | if (staterr & IXGBE_RXD_STAT_DD) { | |
481 | /* Descriptor Done */ | |
c7689578 | 482 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
483 | "%016llX ---------------- %p", i, |
484 | le64_to_cpu(u0->a), | |
485 | le64_to_cpu(u0->b), | |
486 | rx_buffer_info->skb); | |
487 | } else { | |
c7689578 | 488 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
489 | "%016llX %016llX %p", i, |
490 | le64_to_cpu(u0->a), | |
491 | le64_to_cpu(u0->b), | |
492 | (u64)rx_buffer_info->dma, | |
493 | rx_buffer_info->skb); | |
494 | ||
495 | if (netif_msg_pktdata(adapter)) { | |
496 | print_hex_dump(KERN_INFO, "", | |
497 | DUMP_PREFIX_ADDRESS, 16, 1, | |
498 | phys_to_virt(rx_buffer_info->dma), | |
499 | rx_ring->rx_buf_len, true); | |
500 | ||
501 | if (rx_ring->rx_buf_len | |
919e78a6 | 502 | < IXGBE_RXBUFFER_2K) |
dcd79aeb TI |
503 | print_hex_dump(KERN_INFO, "", |
504 | DUMP_PREFIX_ADDRESS, 16, 1, | |
505 | phys_to_virt( | |
506 | rx_buffer_info->page_dma + | |
507 | rx_buffer_info->page_offset | |
508 | ), | |
509 | PAGE_SIZE/2, true); | |
510 | } | |
511 | } | |
512 | ||
513 | if (i == rx_ring->next_to_use) | |
c7689578 | 514 | pr_cont(" NTU\n"); |
dcd79aeb | 515 | else if (i == rx_ring->next_to_clean) |
c7689578 | 516 | pr_cont(" NTC\n"); |
dcd79aeb | 517 | else |
c7689578 | 518 | pr_cont("\n"); |
dcd79aeb TI |
519 | |
520 | } | |
521 | } | |
522 | ||
523 | exit: | |
524 | return; | |
525 | } | |
526 | ||
5eba3699 AV |
527 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
528 | { | |
529 | u32 ctrl_ext; | |
530 | ||
531 | /* Let firmware take over control of h/w */ | |
532 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
533 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 534 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
535 | } |
536 | ||
537 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
538 | { | |
539 | u32 ctrl_ext; | |
540 | ||
541 | /* Let firmware know the driver has taken over */ | |
542 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
543 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 544 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 545 | } |
9a799d71 | 546 | |
e8e26350 PW |
547 | /* |
548 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
549 | * @adapter: pointer to adapter struct | |
550 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
551 | * @queue: queue to map the corresponding interrupt to | |
552 | * @msix_vector: the vector to map to the corresponding queue | |
553 | * | |
554 | */ | |
555 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 556 | u8 queue, u8 msix_vector) |
9a799d71 AK |
557 | { |
558 | u32 ivar, index; | |
e8e26350 PW |
559 | struct ixgbe_hw *hw = &adapter->hw; |
560 | switch (hw->mac.type) { | |
561 | case ixgbe_mac_82598EB: | |
562 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
563 | if (direction == -1) | |
564 | direction = 0; | |
565 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
566 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
567 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
568 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
569 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
570 | break; | |
571 | case ixgbe_mac_82599EB: | |
b93a2226 | 572 | case ixgbe_mac_X540: |
e8e26350 PW |
573 | if (direction == -1) { |
574 | /* other causes */ | |
575 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
576 | index = ((queue & 1) * 8); | |
577 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
578 | ivar &= ~(0xFF << index); | |
579 | ivar |= (msix_vector << index); | |
580 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
581 | break; | |
582 | } else { | |
583 | /* tx or rx causes */ | |
584 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
585 | index = ((16 * (queue & 1)) + (8 * direction)); | |
586 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
587 | ivar &= ~(0xFF << index); | |
588 | ivar |= (msix_vector << index); | |
589 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
590 | break; | |
591 | } | |
592 | default: | |
593 | break; | |
594 | } | |
9a799d71 AK |
595 | } |
596 | ||
fe49f04a | 597 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 598 | u64 qmask) |
fe49f04a AD |
599 | { |
600 | u32 mask; | |
601 | ||
bd508178 AD |
602 | switch (adapter->hw.mac.type) { |
603 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
604 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
605 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
606 | break; |
607 | case ixgbe_mac_82599EB: | |
b93a2226 | 608 | case ixgbe_mac_X540: |
fe49f04a AD |
609 | mask = (qmask & 0xFFFFFFFF); |
610 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
611 | mask = (qmask >> 32); | |
612 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
613 | break; |
614 | default: | |
615 | break; | |
fe49f04a AD |
616 | } |
617 | } | |
618 | ||
d3d00239 AD |
619 | static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring, |
620 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 621 | { |
d3d00239 AD |
622 | if (tx_buffer->dma) { |
623 | if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE) | |
624 | dma_unmap_page(ring->dev, | |
625 | tx_buffer->dma, | |
626 | tx_buffer->length, | |
627 | DMA_TO_DEVICE); | |
e5a43549 | 628 | else |
d3d00239 AD |
629 | dma_unmap_single(ring->dev, |
630 | tx_buffer->dma, | |
631 | tx_buffer->length, | |
632 | DMA_TO_DEVICE); | |
e5a43549 | 633 | } |
d3d00239 AD |
634 | tx_buffer->dma = 0; |
635 | } | |
636 | ||
637 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring, | |
638 | struct ixgbe_tx_buffer *tx_buffer_info) | |
639 | { | |
640 | ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info); | |
641 | if (tx_buffer_info->skb) | |
9a799d71 | 642 | dev_kfree_skb_any(tx_buffer_info->skb); |
d3d00239 | 643 | tx_buffer_info->skb = NULL; |
9a799d71 AK |
644 | /* tx_buffer_info must be completely set up in the transmit path */ |
645 | } | |
646 | ||
c84d324c JF |
647 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) |
648 | { | |
649 | struct ixgbe_hw *hw = &adapter->hw; | |
650 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
651 | u32 data = 0; | |
652 | u32 xoff[8] = {0}; | |
653 | int i; | |
654 | ||
655 | if ((hw->fc.current_mode == ixgbe_fc_full) || | |
656 | (hw->fc.current_mode == ixgbe_fc_rx_pause)) { | |
657 | switch (hw->mac.type) { | |
658 | case ixgbe_mac_82598EB: | |
659 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
6837e895 PW |
660 | break; |
661 | default: | |
c84d324c JF |
662 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); |
663 | } | |
664 | hwstats->lxoffrxc += data; | |
665 | ||
666 | /* refill credits (no tx hang) if we received xoff */ | |
667 | if (!data) | |
668 | return; | |
669 | ||
670 | for (i = 0; i < adapter->num_tx_queues; i++) | |
671 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
672 | &adapter->tx_ring[i]->state); | |
673 | return; | |
674 | } else if (!(adapter->dcb_cfg.pfc_mode_enable)) | |
675 | return; | |
676 | ||
677 | /* update stats for each tc, only valid with PFC enabled */ | |
678 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
679 | switch (hw->mac.type) { | |
680 | case ixgbe_mac_82598EB: | |
681 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 682 | break; |
c84d324c JF |
683 | default: |
684 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 685 | } |
c84d324c JF |
686 | hwstats->pxoffrxc[i] += xoff[i]; |
687 | } | |
688 | ||
689 | /* disarm tx queues that have received xoff frames */ | |
690 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
691 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
fb5475ff | 692 | u8 tc = tx_ring->dcb_tc; |
c84d324c JF |
693 | |
694 | if (xoff[tc]) | |
695 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 696 | } |
26f23d82 YZ |
697 | } |
698 | ||
c84d324c | 699 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 700 | { |
c84d324c JF |
701 | return ring->tx_stats.completed; |
702 | } | |
703 | ||
704 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
705 | { | |
706 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 707 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 708 | |
c84d324c JF |
709 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
710 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
711 | ||
712 | if (head != tail) | |
713 | return (head < tail) ? | |
714 | tail - head : (tail + ring->count - head); | |
715 | ||
716 | return 0; | |
717 | } | |
718 | ||
719 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
720 | { | |
721 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
722 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
723 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
724 | bool ret = false; | |
725 | ||
7d637bcc | 726 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
727 | |
728 | /* | |
729 | * Check for a hung queue, but be thorough. This verifies | |
730 | * that a transmit has been completed since the previous | |
731 | * check AND there is at least one packet pending. The | |
732 | * ARMED bit is set to indicate a potential hang. The | |
733 | * bit is cleared if a pause frame is received to remove | |
734 | * false hang detection due to PFC or 802.3x frames. By | |
735 | * requiring this to fail twice we avoid races with | |
736 | * pfc clearing the ARMED bit and conditions where we | |
737 | * run the check_tx_hang logic with a transmit completion | |
738 | * pending but without time to complete it yet. | |
739 | */ | |
740 | if ((tx_done_old == tx_done) && tx_pending) { | |
741 | /* make sure it is true for two checks in a row */ | |
742 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
743 | &tx_ring->state); | |
744 | } else { | |
745 | /* update completed stats and continue */ | |
746 | tx_ring->tx_stats.tx_done_old = tx_done; | |
747 | /* reset the countdown */ | |
748 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
749 | } |
750 | ||
c84d324c | 751 | return ret; |
9a799d71 AK |
752 | } |
753 | ||
c83c6cbd AD |
754 | /** |
755 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
756 | * @adapter: driver private struct | |
757 | **/ | |
758 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
759 | { | |
760 | ||
761 | /* Do the reset outside of interrupt context */ | |
762 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
763 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
764 | ixgbe_service_event_schedule(adapter); | |
765 | } | |
766 | } | |
e01c31a5 | 767 | |
9a799d71 AK |
768 | /** |
769 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 770 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 771 | * @tx_ring: tx ring to clean |
9a799d71 | 772 | **/ |
fe49f04a | 773 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 774 | struct ixgbe_ring *tx_ring) |
9a799d71 | 775 | { |
fe49f04a | 776 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
777 | struct ixgbe_tx_buffer *tx_buffer; |
778 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 779 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 780 | unsigned int budget = q_vector->tx.work_limit; |
d3d00239 | 781 | u16 i = tx_ring->next_to_clean; |
9a799d71 | 782 | |
d3d00239 AD |
783 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
784 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); | |
12207e49 | 785 | |
30065e63 | 786 | for (; budget; budget--) { |
d3d00239 AD |
787 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
788 | ||
789 | /* if next_to_watch is not set then there is no work pending */ | |
790 | if (!eop_desc) | |
791 | break; | |
792 | ||
793 | /* if DD is not set pending work has not been completed */ | |
794 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
795 | break; | |
8ad494b0 | 796 | |
d3d00239 AD |
797 | /* count the packet as being completed */ |
798 | tx_ring->tx_stats.completed++; | |
799 | ||
800 | /* clear next_to_watch to prevent false hangs */ | |
801 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 802 | |
d3d00239 AD |
803 | /* prevent any other reads prior to eop_desc being verified */ |
804 | rmb(); | |
805 | ||
806 | do { | |
807 | ixgbe_unmap_tx_resource(tx_ring, tx_buffer); | |
8ad494b0 | 808 | tx_desc->wb.status = 0; |
d3d00239 AD |
809 | if (likely(tx_desc == eop_desc)) { |
810 | eop_desc = NULL; | |
811 | dev_kfree_skb_any(tx_buffer->skb); | |
812 | tx_buffer->skb = NULL; | |
813 | ||
814 | total_bytes += tx_buffer->bytecount; | |
815 | total_packets += tx_buffer->gso_segs; | |
816 | } | |
9a799d71 | 817 | |
d3d00239 AD |
818 | tx_buffer++; |
819 | tx_desc++; | |
8ad494b0 | 820 | i++; |
d3d00239 | 821 | if (unlikely(i == tx_ring->count)) { |
8ad494b0 | 822 | i = 0; |
e01c31a5 | 823 | |
d3d00239 AD |
824 | tx_buffer = tx_ring->tx_buffer_info; |
825 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0); | |
e092be60 | 826 | } |
e01c31a5 | 827 | |
d3d00239 | 828 | } while (eop_desc); |
12207e49 PWJ |
829 | } |
830 | ||
9a799d71 | 831 | tx_ring->next_to_clean = i; |
d3d00239 | 832 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 833 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 834 | tx_ring->stats.packets += total_packets; |
d3d00239 | 835 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
836 | q_vector->tx.total_bytes += total_bytes; |
837 | q_vector->tx.total_packets += total_packets; | |
b953799e | 838 | |
c84d324c JF |
839 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
840 | /* schedule immediate reset if we believe we hung */ | |
841 | struct ixgbe_hw *hw = &adapter->hw; | |
d3d00239 | 842 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
c84d324c JF |
843 | e_err(drv, "Detected Tx Unit Hang\n" |
844 | " Tx Queue <%d>\n" | |
845 | " TDH, TDT <%x>, <%x>\n" | |
846 | " next_to_use <%x>\n" | |
847 | " next_to_clean <%x>\n" | |
848 | "tx_buffer_info[next_to_clean]\n" | |
849 | " time_stamp <%lx>\n" | |
850 | " jiffies <%lx>\n", | |
851 | tx_ring->queue_index, | |
852 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
853 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
854 | tx_ring->next_to_use, i, |
855 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
856 | |
857 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
858 | ||
859 | e_info(probe, | |
860 | "tx hang %d detected on queue %d, resetting adapter\n", | |
861 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
862 | ||
b953799e | 863 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 864 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
865 | |
866 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 867 | return true; |
b953799e | 868 | } |
9a799d71 | 869 | |
e092be60 | 870 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 871 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 872 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
873 | /* Make sure that anybody stopping the queue after this |
874 | * sees the new next_to_clean. | |
875 | */ | |
876 | smp_mb(); | |
fc77dc3c | 877 | if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) && |
30eba97a | 878 | !test_bit(__IXGBE_DOWN, &adapter->state)) { |
fc77dc3c | 879 | netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 880 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 881 | } |
e092be60 | 882 | } |
9a799d71 | 883 | |
59224555 | 884 | return !!budget; |
9a799d71 AK |
885 | } |
886 | ||
5dd2d332 | 887 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 888 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
33cf09c9 AD |
889 | struct ixgbe_ring *rx_ring, |
890 | int cpu) | |
bd0362dd | 891 | { |
33cf09c9 | 892 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 893 | u32 rxctrl; |
33cf09c9 AD |
894 | u8 reg_idx = rx_ring->reg_idx; |
895 | ||
896 | rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx)); | |
897 | switch (hw->mac.type) { | |
898 | case ixgbe_mac_82598EB: | |
899 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK; | |
263a84e7 | 900 | rxctrl |= dca3_get_tag(rx_ring->dev, cpu); |
33cf09c9 AD |
901 | break; |
902 | case ixgbe_mac_82599EB: | |
b93a2226 | 903 | case ixgbe_mac_X540: |
33cf09c9 | 904 | rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599; |
263a84e7 | 905 | rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) << |
33cf09c9 AD |
906 | IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599); |
907 | break; | |
908 | default: | |
909 | break; | |
bd0362dd | 910 | } |
33cf09c9 AD |
911 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN; |
912 | rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN; | |
913 | rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN); | |
33cf09c9 | 914 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); |
bd0362dd JC |
915 | } |
916 | ||
917 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, | |
33cf09c9 AD |
918 | struct ixgbe_ring *tx_ring, |
919 | int cpu) | |
bd0362dd | 920 | { |
33cf09c9 | 921 | struct ixgbe_hw *hw = &adapter->hw; |
bd0362dd | 922 | u32 txctrl; |
33cf09c9 AD |
923 | u8 reg_idx = tx_ring->reg_idx; |
924 | ||
925 | switch (hw->mac.type) { | |
926 | case ixgbe_mac_82598EB: | |
927 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx)); | |
928 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK; | |
263a84e7 | 929 | txctrl |= dca3_get_tag(tx_ring->dev, cpu); |
33cf09c9 | 930 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; |
33cf09c9 AD |
931 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl); |
932 | break; | |
933 | case ixgbe_mac_82599EB: | |
b93a2226 | 934 | case ixgbe_mac_X540: |
33cf09c9 AD |
935 | txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx)); |
936 | txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599; | |
263a84e7 | 937 | txctrl |= (dca3_get_tag(tx_ring->dev, cpu) << |
33cf09c9 AD |
938 | IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599); |
939 | txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
33cf09c9 AD |
940 | IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl); |
941 | break; | |
942 | default: | |
943 | break; | |
944 | } | |
945 | } | |
946 | ||
947 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
948 | { | |
949 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 950 | struct ixgbe_ring *ring; |
bd0362dd | 951 | int cpu = get_cpu(); |
bd0362dd | 952 | |
33cf09c9 AD |
953 | if (q_vector->cpu == cpu) |
954 | goto out_no_update; | |
955 | ||
efe3d3c8 AD |
956 | for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next) |
957 | ixgbe_update_tx_dca(adapter, ring, cpu); | |
33cf09c9 | 958 | |
efe3d3c8 AD |
959 | for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next) |
960 | ixgbe_update_rx_dca(adapter, ring, cpu); | |
33cf09c9 AD |
961 | |
962 | q_vector->cpu = cpu; | |
963 | out_no_update: | |
bd0362dd JC |
964 | put_cpu(); |
965 | } | |
966 | ||
967 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
968 | { | |
33cf09c9 | 969 | int num_q_vectors; |
bd0362dd JC |
970 | int i; |
971 | ||
972 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
973 | return; | |
974 | ||
e35ec126 AD |
975 | /* always use CB2 mode, difference is masked in the CB driver */ |
976 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
977 | ||
33cf09c9 AD |
978 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
979 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
980 | else | |
981 | num_q_vectors = 1; | |
982 | ||
983 | for (i = 0; i < num_q_vectors; i++) { | |
984 | adapter->q_vector[i]->cpu = -1; | |
985 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
986 | } |
987 | } | |
988 | ||
989 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
990 | { | |
c60fbb00 | 991 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
992 | unsigned long event = *(unsigned long *)data; |
993 | ||
2a72c31e | 994 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
995 | return 0; |
996 | ||
bd0362dd JC |
997 | switch (event) { |
998 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
999 | /* if we're already enabled, don't do it again */ |
1000 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1001 | break; | |
652f093f | 1002 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1003 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1004 | ixgbe_setup_dca(adapter); |
1005 | break; | |
1006 | } | |
1007 | /* Fall Through since DCA is disabled. */ | |
1008 | case DCA_PROVIDER_REMOVE: | |
1009 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1010 | dca_remove_requester(dev); | |
1011 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1012 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1013 | } | |
1014 | break; | |
1015 | } | |
1016 | ||
652f093f | 1017 | return 0; |
bd0362dd | 1018 | } |
5dd2d332 | 1019 | #endif /* CONFIG_IXGBE_DCA */ |
67a74ee2 ET |
1020 | |
1021 | static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc, | |
1022 | struct sk_buff *skb) | |
1023 | { | |
1024 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
1025 | } | |
1026 | ||
ff886dfc AD |
1027 | /** |
1028 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
1029 | * @adapter: address of board private structure | |
1030 | * @rx_desc: advanced rx descriptor | |
1031 | * | |
1032 | * Returns : true if it is FCoE pkt | |
1033 | */ | |
1034 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter, | |
1035 | union ixgbe_adv_rx_desc *rx_desc) | |
1036 | { | |
1037 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1038 | ||
1039 | return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
1040 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == | |
1041 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1042 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1043 | } | |
1044 | ||
9a799d71 AK |
1045 | /** |
1046 | * ixgbe_receive_skb - Send a completed packet up the stack | |
1047 | * @adapter: board private structure | |
1048 | * @skb: packet to send up | |
177db6ff MC |
1049 | * @status: hardware indication of status of receive |
1050 | * @rx_ring: rx descriptor ring (for a specific queue) to setup | |
1051 | * @rx_desc: rx descriptor | |
9a799d71 | 1052 | **/ |
78b6f4ce | 1053 | static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector, |
e8e9f696 JP |
1054 | struct sk_buff *skb, u8 status, |
1055 | struct ixgbe_ring *ring, | |
1056 | union ixgbe_adv_rx_desc *rx_desc) | |
9a799d71 | 1057 | { |
78b6f4ce HX |
1058 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1059 | struct napi_struct *napi = &q_vector->napi; | |
177db6ff MC |
1060 | bool is_vlan = (status & IXGBE_RXD_STAT_VP); |
1061 | u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan); | |
9a799d71 | 1062 | |
f62bbb5e JG |
1063 | if (is_vlan && (tag & VLAN_VID_MASK)) |
1064 | __vlan_hwaccel_put_tag(skb, tag); | |
1065 | ||
1066 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1067 | napi_gro_receive(napi, skb); | |
1068 | else | |
1069 | netif_rx(skb); | |
9a799d71 AK |
1070 | } |
1071 | ||
e59bd25d AV |
1072 | /** |
1073 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
1074 | * @adapter: address of board private structure | |
1075 | * @status_err: hardware indication of status of receive | |
1076 | * @skb: skb currently being received and modified | |
ff886dfc | 1077 | * @status_err: status error value of last descriptor in packet |
e59bd25d | 1078 | **/ |
9a799d71 | 1079 | static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter, |
8bae1b2b | 1080 | union ixgbe_adv_rx_desc *rx_desc, |
ff886dfc AD |
1081 | struct sk_buff *skb, |
1082 | u32 status_err) | |
9a799d71 | 1083 | { |
ff886dfc | 1084 | skb->ip_summed = CHECKSUM_NONE; |
9a799d71 | 1085 | |
712744be JB |
1086 | /* Rx csum disabled */ |
1087 | if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED)) | |
9a799d71 | 1088 | return; |
e59bd25d AV |
1089 | |
1090 | /* if IP and error */ | |
1091 | if ((status_err & IXGBE_RXD_STAT_IPCS) && | |
1092 | (status_err & IXGBE_RXDADV_ERR_IPE)) { | |
9a799d71 AK |
1093 | adapter->hw_csum_rx_error++; |
1094 | return; | |
1095 | } | |
e59bd25d AV |
1096 | |
1097 | if (!(status_err & IXGBE_RXD_STAT_L4CS)) | |
1098 | return; | |
1099 | ||
1100 | if (status_err & IXGBE_RXDADV_ERR_TCPE) { | |
8bae1b2b DS |
1101 | u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
1102 | ||
1103 | /* | |
1104 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1105 | * checksum errors. | |
1106 | */ | |
1107 | if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) && | |
1108 | (adapter->hw.mac.type == ixgbe_mac_82599EB)) | |
1109 | return; | |
1110 | ||
e59bd25d AV |
1111 | adapter->hw_csum_rx_error++; |
1112 | return; | |
1113 | } | |
1114 | ||
9a799d71 | 1115 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1116 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1117 | } |
1118 | ||
84ea2591 | 1119 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 PW |
1120 | { |
1121 | /* | |
1122 | * Force memory writes to complete before letting h/w | |
1123 | * know there are new descriptors to fetch. (Only | |
1124 | * applicable for weak-ordered memory model archs, | |
1125 | * such as IA-64). | |
1126 | */ | |
1127 | wmb(); | |
84ea2591 | 1128 | writel(val, rx_ring->tail); |
e8e26350 PW |
1129 | } |
1130 | ||
9a799d71 AK |
1131 | /** |
1132 | * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split | |
fc77dc3c AD |
1133 | * @rx_ring: ring to place buffers on |
1134 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1135 | **/ |
fc77dc3c | 1136 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1137 | { |
9a799d71 | 1138 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1139 | struct ixgbe_rx_buffer *bi; |
d5f398ed AD |
1140 | struct sk_buff *skb; |
1141 | u16 i = rx_ring->next_to_use; | |
9a799d71 | 1142 | |
fc77dc3c AD |
1143 | /* do nothing if no valid netdev defined */ |
1144 | if (!rx_ring->netdev) | |
1145 | return; | |
1146 | ||
9a799d71 | 1147 | while (cleaned_count--) { |
31f05a2d | 1148 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
d5f398ed AD |
1149 | bi = &rx_ring->rx_buffer_info[i]; |
1150 | skb = bi->skb; | |
9a799d71 | 1151 | |
d5f398ed | 1152 | if (!skb) { |
fc77dc3c | 1153 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, |
d5f398ed | 1154 | rx_ring->rx_buf_len); |
9a799d71 | 1155 | if (!skb) { |
5b7da515 | 1156 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
9a799d71 AK |
1157 | goto no_buffers; |
1158 | } | |
d716a7d8 AD |
1159 | /* initialize queue mapping */ |
1160 | skb_record_rx_queue(skb, rx_ring->queue_index); | |
d5f398ed | 1161 | bi->skb = skb; |
d716a7d8 | 1162 | } |
9a799d71 | 1163 | |
d716a7d8 | 1164 | if (!bi->dma) { |
b6ec895e | 1165 | bi->dma = dma_map_single(rx_ring->dev, |
d5f398ed | 1166 | skb->data, |
e8e9f696 | 1167 | rx_ring->rx_buf_len, |
1b507730 | 1168 | DMA_FROM_DEVICE); |
b6ec895e | 1169 | if (dma_mapping_error(rx_ring->dev, bi->dma)) { |
5b7da515 | 1170 | rx_ring->rx_stats.alloc_rx_buff_failed++; |
d5f398ed AD |
1171 | bi->dma = 0; |
1172 | goto no_buffers; | |
1173 | } | |
9a799d71 | 1174 | } |
d5f398ed | 1175 | |
7d637bcc | 1176 | if (ring_is_ps_enabled(rx_ring)) { |
d5f398ed | 1177 | if (!bi->page) { |
fc77dc3c | 1178 | bi->page = netdev_alloc_page(rx_ring->netdev); |
d5f398ed | 1179 | if (!bi->page) { |
5b7da515 | 1180 | rx_ring->rx_stats.alloc_rx_page_failed++; |
d5f398ed AD |
1181 | goto no_buffers; |
1182 | } | |
1183 | } | |
1184 | ||
1185 | if (!bi->page_dma) { | |
1186 | /* use a half page if we're re-using */ | |
1187 | bi->page_offset ^= PAGE_SIZE / 2; | |
b6ec895e | 1188 | bi->page_dma = dma_map_page(rx_ring->dev, |
d5f398ed AD |
1189 | bi->page, |
1190 | bi->page_offset, | |
1191 | PAGE_SIZE / 2, | |
1192 | DMA_FROM_DEVICE); | |
b6ec895e | 1193 | if (dma_mapping_error(rx_ring->dev, |
d5f398ed | 1194 | bi->page_dma)) { |
5b7da515 | 1195 | rx_ring->rx_stats.alloc_rx_page_failed++; |
d5f398ed AD |
1196 | bi->page_dma = 0; |
1197 | goto no_buffers; | |
1198 | } | |
1199 | } | |
1200 | ||
1201 | /* Refresh the desc even if buffer_addrs didn't change | |
1202 | * because each write-back erases this info. */ | |
3a581073 JB |
1203 | rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); |
1204 | rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); | |
9a799d71 | 1205 | } else { |
3a581073 | 1206 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma); |
84418e3b | 1207 | rx_desc->read.hdr_addr = 0; |
9a799d71 AK |
1208 | } |
1209 | ||
1210 | i++; | |
1211 | if (i == rx_ring->count) | |
1212 | i = 0; | |
9a799d71 | 1213 | } |
7c6e0a43 | 1214 | |
9a799d71 AK |
1215 | no_buffers: |
1216 | if (rx_ring->next_to_use != i) { | |
1217 | rx_ring->next_to_use = i; | |
84ea2591 | 1218 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1219 | } |
1220 | } | |
1221 | ||
c267fc16 | 1222 | static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc) |
7c6e0a43 | 1223 | { |
c267fc16 AD |
1224 | /* HW will not DMA in data larger than the given buffer, even if it |
1225 | * parses the (NFS, of course) header to be larger. In that case, it | |
1226 | * fills the header buffer and spills the rest into the page. | |
1227 | */ | |
1228 | u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info); | |
1229 | u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >> | |
1230 | IXGBE_RXDADV_HDRBUFLEN_SHIFT; | |
1231 | if (hlen > IXGBE_RX_HDR_SIZE) | |
1232 | hlen = IXGBE_RX_HDR_SIZE; | |
1233 | return hlen; | |
7c6e0a43 JB |
1234 | } |
1235 | ||
f8212f97 AD |
1236 | /** |
1237 | * ixgbe_transform_rsc_queue - change rsc queue into a full packet | |
1238 | * @skb: pointer to the last skb in the rsc queue | |
1239 | * | |
1240 | * This function changes a queue full of hw rsc buffers into a completed | |
1241 | * packet. It uses the ->prev pointers to find the first packet and then | |
1242 | * turns it into the frag list owner. | |
1243 | **/ | |
aa80175a | 1244 | static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb) |
f8212f97 AD |
1245 | { |
1246 | unsigned int frag_list_size = 0; | |
aa80175a | 1247 | unsigned int skb_cnt = 1; |
f8212f97 AD |
1248 | |
1249 | while (skb->prev) { | |
1250 | struct sk_buff *prev = skb->prev; | |
1251 | frag_list_size += skb->len; | |
1252 | skb->prev = NULL; | |
1253 | skb = prev; | |
aa80175a | 1254 | skb_cnt++; |
f8212f97 AD |
1255 | } |
1256 | ||
1257 | skb_shinfo(skb)->frag_list = skb->next; | |
1258 | skb->next = NULL; | |
1259 | skb->len += frag_list_size; | |
1260 | skb->data_len += frag_list_size; | |
1261 | skb->truesize += frag_list_size; | |
aa80175a AD |
1262 | IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt; |
1263 | ||
f8212f97 AD |
1264 | return skb; |
1265 | } | |
1266 | ||
aa80175a AD |
1267 | static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc) |
1268 | { | |
1269 | return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) & | |
1270 | IXGBE_RXDADV_RSCCNT_MASK); | |
1271 | } | |
43634e82 | 1272 | |
4ff7fb12 | 1273 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1274 | struct ixgbe_ring *rx_ring, |
4ff7fb12 | 1275 | int budget) |
9a799d71 | 1276 | { |
78b6f4ce | 1277 | struct ixgbe_adapter *adapter = q_vector->adapter; |
9a799d71 AK |
1278 | union ixgbe_adv_rx_desc *rx_desc, *next_rxd; |
1279 | struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer; | |
1280 | struct sk_buff *skb; | |
d2f4fbe2 | 1281 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
c267fc16 | 1282 | const int current_node = numa_node_id(); |
3d8fd385 YZ |
1283 | #ifdef IXGBE_FCOE |
1284 | int ddp_bytes = 0; | |
1285 | #endif /* IXGBE_FCOE */ | |
c267fc16 AD |
1286 | u32 staterr; |
1287 | u16 i; | |
1288 | u16 cleaned_count = 0; | |
aa80175a | 1289 | bool pkt_is_rsc = false; |
9a799d71 AK |
1290 | |
1291 | i = rx_ring->next_to_clean; | |
31f05a2d | 1292 | rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1293 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
9a799d71 AK |
1294 | |
1295 | while (staterr & IXGBE_RXD_STAT_DD) { | |
7c6e0a43 | 1296 | u32 upper_len = 0; |
9a799d71 | 1297 | |
3c945e5b | 1298 | rmb(); /* read descriptor and rx_buffer_info after status DD */ |
9a799d71 | 1299 | |
c267fc16 AD |
1300 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; |
1301 | ||
9a799d71 | 1302 | skb = rx_buffer_info->skb; |
9a799d71 | 1303 | rx_buffer_info->skb = NULL; |
c267fc16 | 1304 | prefetch(skb->data); |
9a799d71 | 1305 | |
c267fc16 | 1306 | if (ring_is_rsc_enabled(rx_ring)) |
aa80175a | 1307 | pkt_is_rsc = ixgbe_get_rsc_state(rx_desc); |
c267fc16 AD |
1308 | |
1309 | /* if this is a skb from previous receive DMA will be 0 */ | |
21fa4e66 | 1310 | if (rx_buffer_info->dma) { |
c267fc16 | 1311 | u16 hlen; |
aa80175a | 1312 | if (pkt_is_rsc && |
c267fc16 AD |
1313 | !(staterr & IXGBE_RXD_STAT_EOP) && |
1314 | !skb->prev) { | |
43634e82 MC |
1315 | /* |
1316 | * When HWRSC is enabled, delay unmapping | |
1317 | * of the first packet. It carries the | |
1318 | * header information, HW may still | |
1319 | * access the header after the writeback. | |
1320 | * Only unmap it when EOP is reached | |
1321 | */ | |
e8171aaa | 1322 | IXGBE_RSC_CB(skb)->delay_unmap = true; |
43634e82 | 1323 | IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma; |
e8171aaa | 1324 | } else { |
b6ec895e | 1325 | dma_unmap_single(rx_ring->dev, |
e8e9f696 JP |
1326 | rx_buffer_info->dma, |
1327 | rx_ring->rx_buf_len, | |
1328 | DMA_FROM_DEVICE); | |
e8171aaa | 1329 | } |
4f57ca6e | 1330 | rx_buffer_info->dma = 0; |
c267fc16 AD |
1331 | |
1332 | if (ring_is_ps_enabled(rx_ring)) { | |
1333 | hlen = ixgbe_get_hlen(rx_desc); | |
1334 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
1335 | } else { | |
1336 | hlen = le16_to_cpu(rx_desc->wb.upper.length); | |
1337 | } | |
1338 | ||
1339 | skb_put(skb, hlen); | |
1340 | } else { | |
1341 | /* assume packet split since header is unmapped */ | |
1342 | upper_len = le16_to_cpu(rx_desc->wb.upper.length); | |
9a799d71 AK |
1343 | } |
1344 | ||
1345 | if (upper_len) { | |
b6ec895e AD |
1346 | dma_unmap_page(rx_ring->dev, |
1347 | rx_buffer_info->page_dma, | |
1348 | PAGE_SIZE / 2, | |
1349 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1350 | rx_buffer_info->page_dma = 0; |
1351 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
e8e9f696 JP |
1352 | rx_buffer_info->page, |
1353 | rx_buffer_info->page_offset, | |
1354 | upper_len); | |
762f4c57 | 1355 | |
c267fc16 AD |
1356 | if ((page_count(rx_buffer_info->page) == 1) && |
1357 | (page_to_nid(rx_buffer_info->page) == current_node)) | |
762f4c57 | 1358 | get_page(rx_buffer_info->page); |
c267fc16 AD |
1359 | else |
1360 | rx_buffer_info->page = NULL; | |
9a799d71 AK |
1361 | |
1362 | skb->len += upper_len; | |
1363 | skb->data_len += upper_len; | |
1364 | skb->truesize += upper_len; | |
1365 | } | |
1366 | ||
1367 | i++; | |
1368 | if (i == rx_ring->count) | |
1369 | i = 0; | |
9a799d71 | 1370 | |
31f05a2d | 1371 | next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i); |
9a799d71 | 1372 | prefetch(next_rxd); |
9a799d71 | 1373 | cleaned_count++; |
f8212f97 | 1374 | |
aa80175a | 1375 | if (pkt_is_rsc) { |
f8212f97 AD |
1376 | u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >> |
1377 | IXGBE_RXDADV_NEXTP_SHIFT; | |
1378 | next_buffer = &rx_ring->rx_buffer_info[nextp]; | |
f8212f97 AD |
1379 | } else { |
1380 | next_buffer = &rx_ring->rx_buffer_info[i]; | |
1381 | } | |
1382 | ||
c267fc16 | 1383 | if (!(staterr & IXGBE_RXD_STAT_EOP)) { |
7d637bcc | 1384 | if (ring_is_ps_enabled(rx_ring)) { |
f8212f97 AD |
1385 | rx_buffer_info->skb = next_buffer->skb; |
1386 | rx_buffer_info->dma = next_buffer->dma; | |
1387 | next_buffer->skb = skb; | |
1388 | next_buffer->dma = 0; | |
1389 | } else { | |
1390 | skb->next = next_buffer->skb; | |
1391 | skb->next->prev = skb; | |
1392 | } | |
5b7da515 | 1393 | rx_ring->rx_stats.non_eop_descs++; |
9a799d71 AK |
1394 | goto next_desc; |
1395 | } | |
1396 | ||
aa80175a AD |
1397 | if (skb->prev) { |
1398 | skb = ixgbe_transform_rsc_queue(skb); | |
1399 | /* if we got here without RSC the packet is invalid */ | |
1400 | if (!pkt_is_rsc) { | |
1401 | __pskb_trim(skb, 0); | |
1402 | rx_buffer_info->skb = skb; | |
1403 | goto next_desc; | |
1404 | } | |
1405 | } | |
c267fc16 AD |
1406 | |
1407 | if (ring_is_rsc_enabled(rx_ring)) { | |
1408 | if (IXGBE_RSC_CB(skb)->delay_unmap) { | |
1409 | dma_unmap_single(rx_ring->dev, | |
1410 | IXGBE_RSC_CB(skb)->dma, | |
1411 | rx_ring->rx_buf_len, | |
1412 | DMA_FROM_DEVICE); | |
1413 | IXGBE_RSC_CB(skb)->dma = 0; | |
1414 | IXGBE_RSC_CB(skb)->delay_unmap = false; | |
1415 | } | |
aa80175a AD |
1416 | } |
1417 | if (pkt_is_rsc) { | |
c267fc16 AD |
1418 | if (ring_is_ps_enabled(rx_ring)) |
1419 | rx_ring->rx_stats.rsc_count += | |
aa80175a | 1420 | skb_shinfo(skb)->nr_frags; |
c267fc16 | 1421 | else |
aa80175a AD |
1422 | rx_ring->rx_stats.rsc_count += |
1423 | IXGBE_RSC_CB(skb)->skb_cnt; | |
c267fc16 AD |
1424 | rx_ring->rx_stats.rsc_flush++; |
1425 | } | |
1426 | ||
1427 | /* ERR_MASK will only have valid bits if EOP set */ | |
ff886dfc AD |
1428 | if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) { |
1429 | dev_kfree_skb_any(skb); | |
9a799d71 AK |
1430 | goto next_desc; |
1431 | } | |
1432 | ||
ff886dfc | 1433 | ixgbe_rx_checksum(adapter, rx_desc, skb, staterr); |
67a74ee2 ET |
1434 | if (adapter->netdev->features & NETIF_F_RXHASH) |
1435 | ixgbe_rx_hash(rx_desc, skb); | |
d2f4fbe2 AV |
1436 | |
1437 | /* probably a little skewed due to removing CRC */ | |
1438 | total_rx_bytes += skb->len; | |
1439 | total_rx_packets++; | |
1440 | ||
fc77dc3c | 1441 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
332d4a7d YZ |
1442 | #ifdef IXGBE_FCOE |
1443 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
ff886dfc AD |
1444 | if (ixgbe_rx_is_fcoe(adapter, rx_desc)) { |
1445 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb, | |
1446 | staterr); | |
63d635b2 AD |
1447 | if (!ddp_bytes) { |
1448 | dev_kfree_skb_any(skb); | |
332d4a7d | 1449 | goto next_desc; |
63d635b2 | 1450 | } |
3d8fd385 | 1451 | } |
332d4a7d | 1452 | #endif /* IXGBE_FCOE */ |
fdaff1ce | 1453 | ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc); |
9a799d71 | 1454 | |
4ff7fb12 | 1455 | budget--; |
9a799d71 AK |
1456 | next_desc: |
1457 | rx_desc->wb.upper.status_error = 0; | |
1458 | ||
4ff7fb12 | 1459 | if (!budget) |
c267fc16 AD |
1460 | break; |
1461 | ||
9a799d71 AK |
1462 | /* return some buffers to hardware, one at a time is too slow */ |
1463 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
fc77dc3c | 1464 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); |
9a799d71 AK |
1465 | cleaned_count = 0; |
1466 | } | |
1467 | ||
1468 | /* use prefetched values */ | |
1469 | rx_desc = next_rxd; | |
9a799d71 | 1470 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); |
177db6ff MC |
1471 | } |
1472 | ||
9a799d71 | 1473 | rx_ring->next_to_clean = i; |
7d4987de | 1474 | cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 AK |
1475 | |
1476 | if (cleaned_count) | |
fc77dc3c | 1477 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); |
9a799d71 | 1478 | |
3d8fd385 YZ |
1479 | #ifdef IXGBE_FCOE |
1480 | /* include DDPed FCoE data */ | |
1481 | if (ddp_bytes > 0) { | |
1482 | unsigned int mss; | |
1483 | ||
fc77dc3c | 1484 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1485 | sizeof(struct fc_frame_header) - |
1486 | sizeof(struct fcoe_crc_eof); | |
1487 | if (mss > 512) | |
1488 | mss &= ~511; | |
1489 | total_rx_bytes += ddp_bytes; | |
1490 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1491 | } | |
1492 | #endif /* IXGBE_FCOE */ | |
1493 | ||
c267fc16 AD |
1494 | u64_stats_update_begin(&rx_ring->syncp); |
1495 | rx_ring->stats.packets += total_rx_packets; | |
1496 | rx_ring->stats.bytes += total_rx_bytes; | |
1497 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1498 | q_vector->rx.total_packets += total_rx_packets; |
1499 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 AD |
1500 | |
1501 | return !!budget; | |
9a799d71 AK |
1502 | } |
1503 | ||
9a799d71 AK |
1504 | /** |
1505 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1506 | * @adapter: board private structure | |
1507 | * | |
1508 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1509 | * interrupts. | |
1510 | **/ | |
1511 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1512 | { | |
021230d4 | 1513 | struct ixgbe_q_vector *q_vector; |
efe3d3c8 | 1514 | int q_vectors, v_idx; |
021230d4 | 1515 | u32 mask; |
9a799d71 | 1516 | |
021230d4 | 1517 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1518 | |
8e34d1aa AD |
1519 | /* Populate MSIX to EITR Select */ |
1520 | if (adapter->num_vfs > 32) { | |
1521 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1522 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1523 | } | |
1524 | ||
4df10466 JB |
1525 | /* |
1526 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1527 | * corresponding register. |
1528 | */ | |
1529 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
efe3d3c8 | 1530 | struct ixgbe_ring *ring; |
7a921c93 | 1531 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1532 | |
efe3d3c8 AD |
1533 | for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next) |
1534 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); | |
1535 | ||
1536 | for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next) | |
1537 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); | |
1538 | ||
1539 | if (q_vector->tx.ring && !q_vector->rx.ring) | |
f7554a2b NS |
1540 | /* tx only */ |
1541 | q_vector->eitr = adapter->tx_eitr_param; | |
efe3d3c8 | 1542 | else if (q_vector->rx.ring) |
f7554a2b NS |
1543 | /* rx or mixed */ |
1544 | q_vector->eitr = adapter->rx_eitr_param; | |
021230d4 | 1545 | |
fe49f04a | 1546 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1547 | } |
1548 | ||
bd508178 AD |
1549 | switch (adapter->hw.mac.type) { |
1550 | case ixgbe_mac_82598EB: | |
e8e26350 | 1551 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1552 | v_idx); |
bd508178 AD |
1553 | break; |
1554 | case ixgbe_mac_82599EB: | |
b93a2226 | 1555 | case ixgbe_mac_X540: |
e8e26350 | 1556 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 AD |
1557 | break; |
1558 | ||
1559 | default: | |
1560 | break; | |
1561 | } | |
021230d4 AV |
1562 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1563 | ||
41fb9248 | 1564 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1565 | mask = IXGBE_EIMS_ENABLE_MASK; |
1cdd1ec8 GR |
1566 | if (adapter->num_vfs) |
1567 | mask &= ~(IXGBE_EIMS_OTHER | | |
1568 | IXGBE_EIMS_MAILBOX | | |
1569 | IXGBE_EIMS_LSC); | |
1570 | else | |
1571 | mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC); | |
021230d4 | 1572 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1573 | } |
1574 | ||
f494e8fa AV |
1575 | enum latency_range { |
1576 | lowest_latency = 0, | |
1577 | low_latency = 1, | |
1578 | bulk_latency = 2, | |
1579 | latency_invalid = 255 | |
1580 | }; | |
1581 | ||
1582 | /** | |
1583 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
1584 | * @q_vector: structure containing interrupt and ring information |
1585 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
1586 | * |
1587 | * Stores a new ITR value based on packets and byte | |
1588 | * counts during the last interrupt. The advantage of per interrupt | |
1589 | * computation is faster updates and more accurate ITR for the current | |
1590 | * traffic pattern. Constants in this function were computed | |
1591 | * based on theoretical maximum wire speed and thresholds were set based | |
1592 | * on testing data as well as attempting to minimize response time | |
1593 | * while increasing bulk throughput. | |
1594 | * this functionality is controlled by the InterruptThrottleRate module | |
1595 | * parameter (see ixgbe_param.c) | |
1596 | **/ | |
bd198058 AD |
1597 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
1598 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 1599 | { |
f494e8fa | 1600 | u64 bytes_perint; |
bd198058 AD |
1601 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1602 | int bytes = ring_container->total_bytes; | |
1603 | int packets = ring_container->total_packets; | |
1604 | u32 timepassed_us; | |
1605 | u8 itr_setting = ring_container->itr; | |
f494e8fa AV |
1606 | |
1607 | if (packets == 0) | |
bd198058 | 1608 | return; |
f494e8fa AV |
1609 | |
1610 | /* simple throttlerate management | |
1611 | * 0-20MB/s lowest (100000 ints/s) | |
1612 | * 20-100MB/s low (20000 ints/s) | |
1613 | * 100-1249MB/s bulk (8000 ints/s) | |
1614 | */ | |
1615 | /* what was last interrupt timeslice? */ | |
bd198058 | 1616 | timepassed_us = 1000000/q_vector->eitr; |
f494e8fa AV |
1617 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1618 | ||
1619 | switch (itr_setting) { | |
1620 | case lowest_latency: | |
1621 | if (bytes_perint > adapter->eitr_low) | |
bd198058 | 1622 | itr_setting = low_latency; |
f494e8fa AV |
1623 | break; |
1624 | case low_latency: | |
1625 | if (bytes_perint > adapter->eitr_high) | |
bd198058 | 1626 | itr_setting = bulk_latency; |
f494e8fa | 1627 | else if (bytes_perint <= adapter->eitr_low) |
bd198058 | 1628 | itr_setting = lowest_latency; |
f494e8fa AV |
1629 | break; |
1630 | case bulk_latency: | |
1631 | if (bytes_perint <= adapter->eitr_high) | |
bd198058 | 1632 | itr_setting = low_latency; |
f494e8fa AV |
1633 | break; |
1634 | } | |
1635 | ||
bd198058 AD |
1636 | /* clear work counters since we have the values we need */ |
1637 | ring_container->total_bytes = 0; | |
1638 | ring_container->total_packets = 0; | |
1639 | ||
1640 | /* write updated itr to ring container */ | |
1641 | ring_container->itr = itr_setting; | |
f494e8fa AV |
1642 | } |
1643 | ||
509ee935 JB |
1644 | /** |
1645 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1646 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1647 | * |
1648 | * This function is made to be called by ethtool and by the driver | |
1649 | * when it needs to update EITR registers at runtime. Hardware | |
1650 | * specific quirks/differences are taken care of here. | |
1651 | */ | |
fe49f04a | 1652 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1653 | { |
fe49f04a | 1654 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1655 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
1656 | int v_idx = q_vector->v_idx; |
1657 | u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr); | |
1658 | ||
bd508178 AD |
1659 | switch (adapter->hw.mac.type) { |
1660 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1661 | /* must write high and low 16 bits to reset counter */ |
1662 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1663 | break; |
1664 | case ixgbe_mac_82599EB: | |
b93a2226 | 1665 | case ixgbe_mac_X540: |
f8d1dcaf | 1666 | /* |
b93a2226 | 1667 | * 82599 and X540 can support a value of zero, so allow it for |
f8d1dcaf JB |
1668 | * max interrupt rate, but there is an errata where it can |
1669 | * not be zero with RSC | |
1670 | */ | |
1671 | if (itr_reg == 8 && | |
1672 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) | |
1673 | itr_reg = 0; | |
1674 | ||
509ee935 JB |
1675 | /* |
1676 | * set the WDIS bit to not clear the timer bits and cause an | |
1677 | * immediate assertion of the interrupt | |
1678 | */ | |
1679 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1680 | break; |
1681 | default: | |
1682 | break; | |
509ee935 JB |
1683 | } |
1684 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1685 | } | |
1686 | ||
bd198058 | 1687 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 1688 | { |
bd198058 AD |
1689 | u32 new_itr = q_vector->eitr; |
1690 | u8 current_itr; | |
f494e8fa | 1691 | |
bd198058 AD |
1692 | ixgbe_update_itr(q_vector, &q_vector->tx); |
1693 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 1694 | |
08c8833b | 1695 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
1696 | |
1697 | switch (current_itr) { | |
1698 | /* counts and packets in update_itr are dependent on these numbers */ | |
1699 | case lowest_latency: | |
1700 | new_itr = 100000; | |
1701 | break; | |
1702 | case low_latency: | |
1703 | new_itr = 20000; /* aka hwitr = ~200 */ | |
1704 | break; | |
1705 | case bulk_latency: | |
f494e8fa AV |
1706 | new_itr = 8000; |
1707 | break; | |
bd198058 AD |
1708 | default: |
1709 | break; | |
f494e8fa AV |
1710 | } |
1711 | ||
1712 | if (new_itr != q_vector->eitr) { | |
fe49f04a | 1713 | /* do an exponential smoothing */ |
125601bf | 1714 | new_itr = ((q_vector->eitr * 9) + new_itr)/10; |
509ee935 | 1715 | |
bd198058 | 1716 | /* save the algorithm value here */ |
509ee935 | 1717 | q_vector->eitr = new_itr; |
fe49f04a AD |
1718 | |
1719 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 1720 | } |
f494e8fa AV |
1721 | } |
1722 | ||
119fc60a | 1723 | /** |
f0f9778d AD |
1724 | * ixgbe_check_overtemp_subtask - check for over tempurature |
1725 | * @adapter: pointer to adapter | |
119fc60a | 1726 | **/ |
f0f9778d | 1727 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 1728 | { |
119fc60a MC |
1729 | struct ixgbe_hw *hw = &adapter->hw; |
1730 | u32 eicr = adapter->interrupt_event; | |
1731 | ||
f0f9778d | 1732 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
1733 | return; |
1734 | ||
f0f9778d AD |
1735 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
1736 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
1737 | return; | |
1738 | ||
1739 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
1740 | ||
7ca647bd | 1741 | switch (hw->device_id) { |
f0f9778d AD |
1742 | case IXGBE_DEV_ID_82599_T3_LOM: |
1743 | /* | |
1744 | * Since the warning interrupt is for both ports | |
1745 | * we don't have to check if: | |
1746 | * - This interrupt wasn't for our port. | |
1747 | * - We may have missed the interrupt so always have to | |
1748 | * check if we got a LSC | |
1749 | */ | |
1750 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
1751 | !(eicr & IXGBE_EICR_LSC)) | |
1752 | return; | |
1753 | ||
1754 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
1755 | u32 autoneg; | |
1756 | bool link_up = false; | |
7ca647bd | 1757 | |
7ca647bd JP |
1758 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
1759 | ||
f0f9778d AD |
1760 | if (link_up) |
1761 | return; | |
1762 | } | |
1763 | ||
1764 | /* Check if this is not due to overtemp */ | |
1765 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
1766 | return; | |
1767 | ||
1768 | break; | |
7ca647bd JP |
1769 | default: |
1770 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 1771 | return; |
7ca647bd | 1772 | break; |
119fc60a | 1773 | } |
7ca647bd JP |
1774 | e_crit(drv, |
1775 | "Network adapter has been stopped because it has over heated. " | |
1776 | "Restart the computer. If the problem persists, " | |
1777 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
1778 | |
1779 | adapter->interrupt_event = 0; | |
119fc60a MC |
1780 | } |
1781 | ||
0befdb3e JB |
1782 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
1783 | { | |
1784 | struct ixgbe_hw *hw = &adapter->hw; | |
1785 | ||
1786 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
1787 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 1788 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
1789 | /* write to clear the interrupt */ |
1790 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
1791 | } | |
1792 | } | |
cf8280ee | 1793 | |
e8e26350 PW |
1794 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
1795 | { | |
1796 | struct ixgbe_hw *hw = &adapter->hw; | |
1797 | ||
73c4b7cd AD |
1798 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
1799 | /* Clear the interrupt */ | |
1800 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
1801 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
1802 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
1803 | ixgbe_service_event_schedule(adapter); | |
1804 | } | |
73c4b7cd AD |
1805 | } |
1806 | ||
e8e26350 PW |
1807 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
1808 | /* Clear the interrupt */ | |
1809 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
1810 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
1811 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
1812 | ixgbe_service_event_schedule(adapter); | |
1813 | } | |
e8e26350 PW |
1814 | } |
1815 | } | |
1816 | ||
cf8280ee JB |
1817 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
1818 | { | |
1819 | struct ixgbe_hw *hw = &adapter->hw; | |
1820 | ||
1821 | adapter->lsc_int++; | |
1822 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
1823 | adapter->link_check_timeout = jiffies; | |
1824 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1825 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 1826 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 1827 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
1828 | } |
1829 | } | |
1830 | ||
fe49f04a AD |
1831 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
1832 | u64 qmask) | |
1833 | { | |
1834 | u32 mask; | |
bd508178 | 1835 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1836 | |
bd508178 AD |
1837 | switch (hw->mac.type) { |
1838 | case ixgbe_mac_82598EB: | |
fe49f04a | 1839 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
1840 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
1841 | break; | |
1842 | case ixgbe_mac_82599EB: | |
b93a2226 | 1843 | case ixgbe_mac_X540: |
fe49f04a | 1844 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
1845 | if (mask) |
1846 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 1847 | mask = (qmask >> 32); |
bd508178 AD |
1848 | if (mask) |
1849 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
1850 | break; | |
1851 | default: | |
1852 | break; | |
fe49f04a AD |
1853 | } |
1854 | /* skip the flush */ | |
1855 | } | |
1856 | ||
1857 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 1858 | u64 qmask) |
fe49f04a AD |
1859 | { |
1860 | u32 mask; | |
bd508178 | 1861 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1862 | |
bd508178 AD |
1863 | switch (hw->mac.type) { |
1864 | case ixgbe_mac_82598EB: | |
fe49f04a | 1865 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
1866 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
1867 | break; | |
1868 | case ixgbe_mac_82599EB: | |
b93a2226 | 1869 | case ixgbe_mac_X540: |
fe49f04a | 1870 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
1871 | if (mask) |
1872 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 1873 | mask = (qmask >> 32); |
bd508178 AD |
1874 | if (mask) |
1875 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
1876 | break; | |
1877 | default: | |
1878 | break; | |
fe49f04a AD |
1879 | } |
1880 | /* skip the flush */ | |
1881 | } | |
1882 | ||
021230d4 | 1883 | /** |
2c4af694 AD |
1884 | * ixgbe_irq_enable - Enable default interrupt generation settings |
1885 | * @adapter: board private structure | |
021230d4 | 1886 | **/ |
2c4af694 AD |
1887 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
1888 | bool flush) | |
9a799d71 | 1889 | { |
2c4af694 | 1890 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 1891 | |
2c4af694 AD |
1892 | /* don't reenable LSC while waiting for link */ |
1893 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
1894 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 1895 | |
2c4af694 AD |
1896 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
1897 | mask |= IXGBE_EIMS_GPI_SDP0; | |
1898 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
1899 | mask |= IXGBE_EIMS_GPI_SDP1; | |
1900 | switch (adapter->hw.mac.type) { | |
1901 | case ixgbe_mac_82599EB: | |
1902 | case ixgbe_mac_X540: | |
1903 | mask |= IXGBE_EIMS_ECC; | |
1904 | mask |= IXGBE_EIMS_GPI_SDP1; | |
1905 | mask |= IXGBE_EIMS_GPI_SDP2; | |
1906 | mask |= IXGBE_EIMS_MAILBOX; | |
1907 | break; | |
1908 | default: | |
1909 | break; | |
9a799d71 | 1910 | } |
2c4af694 AD |
1911 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
1912 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
1913 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 1914 | |
2c4af694 AD |
1915 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
1916 | if (queues) | |
1917 | ixgbe_irq_enable_queues(adapter, ~0); | |
1918 | if (flush) | |
1919 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
1920 | } |
1921 | ||
2c4af694 | 1922 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 1923 | { |
a65151ba | 1924 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 1925 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 1926 | u32 eicr; |
91281fd3 | 1927 | |
54037505 DS |
1928 | /* |
1929 | * Workaround for Silicon errata. Use clear-by-write instead | |
1930 | * of clear-by-read. Reading with EICS will return the | |
1931 | * interrupt causes without clearing, which later be done | |
1932 | * with the write to EICR. | |
1933 | */ | |
1934 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
1935 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 1936 | |
cf8280ee JB |
1937 | if (eicr & IXGBE_EICR_LSC) |
1938 | ixgbe_check_lsc(adapter); | |
f0848276 | 1939 | |
1cdd1ec8 GR |
1940 | if (eicr & IXGBE_EICR_MAILBOX) |
1941 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 1942 | |
bd508178 AD |
1943 | switch (hw->mac.type) { |
1944 | case ixgbe_mac_82599EB: | |
b93a2226 | 1945 | case ixgbe_mac_X540: |
2c4af694 AD |
1946 | if (eicr & IXGBE_EICR_ECC) |
1947 | e_info(link, "Received unrecoverable ECC Err, please " | |
1948 | "reboot\n"); | |
c4cf55e5 PWJ |
1949 | /* Handle Flow Director Full threshold interrupt */ |
1950 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 1951 | int reinit_count = 0; |
c4cf55e5 | 1952 | int i; |
c4cf55e5 | 1953 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 1954 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 1955 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
1956 | &ring->state)) |
1957 | reinit_count++; | |
1958 | } | |
1959 | if (reinit_count) { | |
1960 | /* no more flow director interrupts until after init */ | |
1961 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
1962 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
1963 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
1964 | } |
1965 | } | |
f0f9778d AD |
1966 | ixgbe_check_sfp_event(adapter, eicr); |
1967 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && | |
1968 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) { | |
1969 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
1970 | adapter->interrupt_event = eicr; | |
1971 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
1972 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
1973 | } |
1974 | } | |
bd508178 AD |
1975 | break; |
1976 | default: | |
1977 | break; | |
c4cf55e5 | 1978 | } |
f0848276 | 1979 | |
bd508178 | 1980 | ixgbe_check_fan_failure(adapter, eicr); |
efe3d3c8 | 1981 | |
7086400d | 1982 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 1983 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 1984 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 1985 | |
9a799d71 | 1986 | return IRQ_HANDLED; |
f0848276 | 1987 | } |
91281fd3 | 1988 | |
4ff7fb12 | 1989 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 1990 | { |
021230d4 | 1991 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 1992 | |
9b471446 | 1993 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 1994 | |
4ff7fb12 AD |
1995 | if (q_vector->rx.ring || q_vector->tx.ring) |
1996 | napi_schedule(&q_vector->napi); | |
91281fd3 | 1997 | |
9a799d71 | 1998 | return IRQ_HANDLED; |
91281fd3 AD |
1999 | } |
2000 | ||
021230d4 | 2001 | static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx, |
e8e9f696 | 2002 | int r_idx) |
021230d4 | 2003 | { |
7a921c93 | 2004 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2274543f | 2005 | struct ixgbe_ring *rx_ring = a->rx_ring[r_idx]; |
7a921c93 | 2006 | |
2274543f | 2007 | rx_ring->q_vector = q_vector; |
efe3d3c8 AD |
2008 | rx_ring->next = q_vector->rx.ring; |
2009 | q_vector->rx.ring = rx_ring; | |
2010 | q_vector->rx.count++; | |
021230d4 AV |
2011 | } |
2012 | ||
2013 | static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx, | |
e8e9f696 | 2014 | int t_idx) |
021230d4 | 2015 | { |
7a921c93 | 2016 | struct ixgbe_q_vector *q_vector = a->q_vector[v_idx]; |
2274543f | 2017 | struct ixgbe_ring *tx_ring = a->tx_ring[t_idx]; |
7a921c93 | 2018 | |
2274543f | 2019 | tx_ring->q_vector = q_vector; |
efe3d3c8 AD |
2020 | tx_ring->next = q_vector->tx.ring; |
2021 | q_vector->tx.ring = tx_ring; | |
2022 | q_vector->tx.count++; | |
bd198058 | 2023 | q_vector->tx.work_limit = a->tx_work_limit; |
021230d4 AV |
2024 | } |
2025 | ||
9a799d71 | 2026 | /** |
021230d4 AV |
2027 | * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors |
2028 | * @adapter: board private structure to initialize | |
9a799d71 | 2029 | * |
021230d4 AV |
2030 | * This function maps descriptor rings to the queue-specific vectors |
2031 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
2032 | * one vector per ring/queue, but on a constrained vector budget, we | |
2033 | * group the rings as "efficiently" as possible. You would add new | |
2034 | * mapping configurations in here. | |
9a799d71 | 2035 | **/ |
4cc6df29 | 2036 | static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter) |
021230d4 | 2037 | { |
4cc6df29 AD |
2038 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2039 | int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0; | |
2040 | int txr_remaining = adapter->num_tx_queues, txr_idx = 0; | |
021230d4 | 2041 | int v_start = 0; |
021230d4 | 2042 | |
4cc6df29 | 2043 | /* only one q_vector if MSI-X is disabled. */ |
021230d4 | 2044 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) |
4cc6df29 | 2045 | q_vectors = 1; |
d0759ebb | 2046 | |
021230d4 | 2047 | /* |
4cc6df29 AD |
2048 | * If we don't have enough vectors for a 1-to-1 mapping, we'll have to |
2049 | * group them so there are multiple queues per vector. | |
2050 | * | |
2051 | * Re-adjusting *qpv takes care of the remainder. | |
021230d4 | 2052 | */ |
4cc6df29 AD |
2053 | for (; v_start < q_vectors && rxr_remaining; v_start++) { |
2054 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start); | |
2055 | for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--) | |
021230d4 | 2056 | map_vector_to_rxq(adapter, v_start, rxr_idx); |
021230d4 | 2057 | } |
9a799d71 | 2058 | |
021230d4 | 2059 | /* |
4cc6df29 AD |
2060 | * If there are not enough q_vectors for each ring to have it's own |
2061 | * vector then we must pair up Rx/Tx on a each vector | |
021230d4 | 2062 | */ |
4cc6df29 AD |
2063 | if ((v_start + txr_remaining) > q_vectors) |
2064 | v_start = 0; | |
2065 | ||
2066 | for (; v_start < q_vectors && txr_remaining; v_start++) { | |
2067 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start); | |
2068 | for (; tqpv; tqpv--, txr_idx++, txr_remaining--) | |
2069 | map_vector_to_txq(adapter, v_start, txr_idx); | |
9a799d71 | 2070 | } |
021230d4 AV |
2071 | } |
2072 | ||
2073 | /** | |
2074 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2075 | * @adapter: board private structure | |
2076 | * | |
2077 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2078 | * interrupts from the kernel. | |
2079 | **/ | |
2080 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2081 | { | |
2082 | struct net_device *netdev = adapter->netdev; | |
207867f5 AD |
2083 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2084 | int vector, err; | |
e8e9f696 | 2085 | int ri = 0, ti = 0; |
021230d4 | 2086 | |
021230d4 | 2087 | for (vector = 0; vector < q_vectors; vector++) { |
d0759ebb | 2088 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2089 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2090 | |
4ff7fb12 | 2091 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2092 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2093 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2094 | ti++; | |
2095 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2096 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2097 | "%s-%s-%d", netdev->name, "rx", ri++); |
2098 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2099 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2100 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2101 | } else { |
2102 | /* skip this unused q_vector */ | |
2103 | continue; | |
32aa77a4 | 2104 | } |
207867f5 AD |
2105 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2106 | q_vector->name, q_vector); | |
9a799d71 | 2107 | if (err) { |
396e799c | 2108 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2109 | "Error: %d\n", err); |
021230d4 | 2110 | goto free_queue_irqs; |
9a799d71 | 2111 | } |
207867f5 AD |
2112 | /* If Flow Director is enabled, set interrupt affinity */ |
2113 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2114 | /* assign the mask for this irq */ | |
2115 | irq_set_affinity_hint(entry->vector, | |
2116 | q_vector->affinity_mask); | |
2117 | } | |
9a799d71 AK |
2118 | } |
2119 | ||
021230d4 | 2120 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2121 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2122 | if (err) { |
396e799c | 2123 | e_err(probe, "request_irq for msix_lsc failed: %d\n", err); |
021230d4 | 2124 | goto free_queue_irqs; |
9a799d71 AK |
2125 | } |
2126 | ||
9a799d71 AK |
2127 | return 0; |
2128 | ||
021230d4 | 2129 | free_queue_irqs: |
207867f5 AD |
2130 | while (vector) { |
2131 | vector--; | |
2132 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2133 | NULL); | |
2134 | free_irq(adapter->msix_entries[vector].vector, | |
2135 | adapter->q_vector[vector]); | |
2136 | } | |
021230d4 AV |
2137 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2138 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2139 | kfree(adapter->msix_entries); |
2140 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2141 | return err; |
2142 | } | |
2143 | ||
2144 | /** | |
021230d4 | 2145 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2146 | * @irq: interrupt number |
2147 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2148 | **/ |
2149 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2150 | { | |
a65151ba | 2151 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2152 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2153 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2154 | u32 eicr; |
2155 | ||
54037505 | 2156 | /* |
6af3b9eb | 2157 | * Workaround for silicon errata on 82598. Mask the interrupts |
54037505 DS |
2158 | * before the read of EICR. |
2159 | */ | |
2160 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2161 | ||
021230d4 AV |
2162 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
2163 | * therefore no explict interrupt disable is necessary */ | |
2164 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); | |
f47cf66e | 2165 | if (!eicr) { |
6af3b9eb ET |
2166 | /* |
2167 | * shared interrupt alert! | |
f47cf66e | 2168 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2169 | * have disabled interrupts due to EIAM |
2170 | * finish the workaround of silicon errata on 82598. Unmask | |
2171 | * the interrupt that we masked before the EICR read. | |
2172 | */ | |
2173 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2174 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2175 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2176 | } |
9a799d71 | 2177 | |
cf8280ee JB |
2178 | if (eicr & IXGBE_EICR_LSC) |
2179 | ixgbe_check_lsc(adapter); | |
021230d4 | 2180 | |
bd508178 AD |
2181 | switch (hw->mac.type) { |
2182 | case ixgbe_mac_82599EB: | |
e8e26350 | 2183 | ixgbe_check_sfp_event(adapter, eicr); |
bd508178 AD |
2184 | if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2185 | ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) { | |
f0f9778d AD |
2186 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2187 | adapter->interrupt_event = eicr; | |
2188 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2189 | ixgbe_service_event_schedule(adapter); | |
2190 | } | |
bd508178 AD |
2191 | } |
2192 | break; | |
2193 | default: | |
2194 | break; | |
2195 | } | |
e8e26350 | 2196 | |
0befdb3e JB |
2197 | ixgbe_check_fan_failure(adapter, eicr); |
2198 | ||
7a921c93 | 2199 | if (napi_schedule_prep(&(q_vector->napi))) { |
021230d4 | 2200 | /* would disable interrupts here but EIAM disabled it */ |
7a921c93 | 2201 | __napi_schedule(&(q_vector->napi)); |
9a799d71 AK |
2202 | } |
2203 | ||
6af3b9eb ET |
2204 | /* |
2205 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2206 | * ixgbe_poll will re-enable the queue interrupts | |
2207 | */ | |
2208 | ||
2209 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2210 | ixgbe_irq_enable(adapter, false, false); | |
2211 | ||
9a799d71 AK |
2212 | return IRQ_HANDLED; |
2213 | } | |
2214 | ||
021230d4 AV |
2215 | static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter) |
2216 | { | |
efe3d3c8 AD |
2217 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2218 | int i; | |
2219 | ||
2220 | /* legacy and MSI only use one vector */ | |
2221 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
2222 | q_vectors = 1; | |
2223 | ||
2224 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
2225 | adapter->rx_ring[i]->q_vector = NULL; | |
2226 | adapter->rx_ring[i]->next = NULL; | |
2227 | } | |
2228 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
2229 | adapter->tx_ring[i]->q_vector = NULL; | |
2230 | adapter->tx_ring[i]->next = NULL; | |
2231 | } | |
021230d4 AV |
2232 | |
2233 | for (i = 0; i < q_vectors; i++) { | |
7a921c93 | 2234 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; |
efe3d3c8 AD |
2235 | memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container)); |
2236 | memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container)); | |
021230d4 AV |
2237 | } |
2238 | } | |
2239 | ||
9a799d71 AK |
2240 | /** |
2241 | * ixgbe_request_irq - initialize interrupts | |
2242 | * @adapter: board private structure | |
2243 | * | |
2244 | * Attempts to configure interrupts using the best available | |
2245 | * capabilities of the hardware and kernel. | |
2246 | **/ | |
021230d4 | 2247 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2248 | { |
2249 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2250 | int err; |
9a799d71 | 2251 | |
4cc6df29 AD |
2252 | /* map all of the rings to the q_vectors */ |
2253 | ixgbe_map_rings_to_vectors(adapter); | |
2254 | ||
2255 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) | |
021230d4 | 2256 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2257 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2258 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2259 | netdev->name, adapter); |
4cc6df29 | 2260 | else |
a0607fd3 | 2261 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2262 | netdev->name, adapter); |
9a799d71 | 2263 | |
4cc6df29 | 2264 | if (err) { |
396e799c | 2265 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2266 | |
4cc6df29 AD |
2267 | /* place q_vectors and rings back into a known good state */ |
2268 | ixgbe_reset_q_vectors(adapter); | |
2269 | } | |
2270 | ||
9a799d71 AK |
2271 | return err; |
2272 | } | |
2273 | ||
2274 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2275 | { | |
9a799d71 | 2276 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
021230d4 | 2277 | int i, q_vectors; |
9a799d71 | 2278 | |
021230d4 | 2279 | q_vectors = adapter->num_msix_vectors; |
021230d4 | 2280 | i = q_vectors - 1; |
a65151ba | 2281 | free_irq(adapter->msix_entries[i].vector, adapter); |
021230d4 | 2282 | i--; |
4cc6df29 | 2283 | |
021230d4 | 2284 | for (; i >= 0; i--) { |
894ff7cf | 2285 | /* free only the irqs that were actually requested */ |
4ff7fb12 AD |
2286 | if (!adapter->q_vector[i]->rx.ring && |
2287 | !adapter->q_vector[i]->tx.ring) | |
894ff7cf AD |
2288 | continue; |
2289 | ||
207867f5 AD |
2290 | /* clear the affinity_mask in the IRQ descriptor */ |
2291 | irq_set_affinity_hint(adapter->msix_entries[i].vector, | |
2292 | NULL); | |
2293 | ||
021230d4 | 2294 | free_irq(adapter->msix_entries[i].vector, |
e8e9f696 | 2295 | adapter->q_vector[i]); |
021230d4 | 2296 | } |
021230d4 | 2297 | } else { |
a65151ba | 2298 | free_irq(adapter->pdev->irq, adapter); |
9a799d71 | 2299 | } |
207867f5 AD |
2300 | |
2301 | /* clear q_vector state information */ | |
2302 | ixgbe_reset_q_vectors(adapter); | |
9a799d71 AK |
2303 | } |
2304 | ||
22d5a71b JB |
2305 | /** |
2306 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2307 | * @adapter: board private structure | |
2308 | **/ | |
2309 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2310 | { | |
bd508178 AD |
2311 | switch (adapter->hw.mac.type) { |
2312 | case ixgbe_mac_82598EB: | |
835462fc | 2313 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2314 | break; |
2315 | case ixgbe_mac_82599EB: | |
b93a2226 | 2316 | case ixgbe_mac_X540: |
835462fc NS |
2317 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2318 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2319 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2320 | break; |
2321 | default: | |
2322 | break; | |
22d5a71b JB |
2323 | } |
2324 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2325 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2326 | int i; | |
2327 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2328 | synchronize_irq(adapter->msix_entries[i].vector); | |
2329 | } else { | |
2330 | synchronize_irq(adapter->pdev->irq); | |
2331 | } | |
2332 | } | |
2333 | ||
9a799d71 AK |
2334 | /** |
2335 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2336 | * | |
2337 | **/ | |
2338 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2339 | { | |
9a799d71 AK |
2340 | struct ixgbe_hw *hw = &adapter->hw; |
2341 | ||
021230d4 | 2342 | IXGBE_WRITE_REG(hw, IXGBE_EITR(0), |
e8e9f696 | 2343 | EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param)); |
9a799d71 | 2344 | |
e8e26350 PW |
2345 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2346 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2347 | |
396e799c | 2348 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2349 | } |
2350 | ||
43e69bf0 AD |
2351 | /** |
2352 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2353 | * @adapter: board private structure | |
2354 | * @ring: structure containing ring specific data | |
2355 | * | |
2356 | * Configure the Tx descriptor ring after a reset. | |
2357 | **/ | |
84418e3b AD |
2358 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2359 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2360 | { |
2361 | struct ixgbe_hw *hw = &adapter->hw; | |
2362 | u64 tdba = ring->dma; | |
2f1860b8 | 2363 | int wait_loop = 10; |
b88c6de2 | 2364 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2365 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2366 | |
2f1860b8 | 2367 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2368 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2369 | IXGBE_WRITE_FLUSH(hw); |
2370 | ||
43e69bf0 | 2371 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2372 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2373 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2374 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2375 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2376 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2377 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2378 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2379 | |
b88c6de2 AD |
2380 | /* |
2381 | * set WTHRESH to encourage burst writeback, it should not be set | |
2382 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2383 | * | |
2384 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2385 | * to or less than the number of on chip descriptors, which is | |
2386 | * currently 40. | |
2387 | */ | |
2388 | if (!adapter->tx_itr_setting || !adapter->rx_itr_setting) | |
2389 | txdctl |= (1 << 16); /* WTHRESH = 1 */ | |
2390 | else | |
2391 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2392 | ||
2393 | /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */ | |
2394 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ | |
2395 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2396 | |
2397 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2398 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2399 | adapter->atr_sample_rate) { | |
2400 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2401 | ring->atr_count = 0; | |
2402 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2403 | } else { | |
2404 | ring->atr_sample_rate = 0; | |
2405 | } | |
2f1860b8 | 2406 | |
c84d324c JF |
2407 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2408 | ||
2f1860b8 | 2409 | /* enable queue */ |
2f1860b8 AD |
2410 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2411 | ||
2412 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2413 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2414 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2415 | return; | |
2416 | ||
2417 | /* poll to verify queue is enabled */ | |
2418 | do { | |
032b4325 | 2419 | usleep_range(1000, 2000); |
2f1860b8 AD |
2420 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2421 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2422 | if (!wait_loop) | |
2423 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2424 | } |
2425 | ||
120ff942 AD |
2426 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2427 | { | |
2428 | struct ixgbe_hw *hw = &adapter->hw; | |
2429 | u32 rttdcs; | |
72a32f1f | 2430 | u32 reg; |
8b1c0b24 | 2431 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2432 | |
2433 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2434 | return; | |
2435 | ||
2436 | /* disable the arbiter while setting MTQC */ | |
2437 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2438 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2439 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2440 | ||
2441 | /* set transmit pool layout */ | |
8b1c0b24 | 2442 | switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
120ff942 AD |
2443 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2444 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2445 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2446 | break; | |
8b1c0b24 JF |
2447 | default: |
2448 | if (!tcs) | |
2449 | reg = IXGBE_MTQC_64Q_1PB; | |
2450 | else if (tcs <= 4) | |
2451 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2452 | else | |
2453 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
120ff942 | 2454 | |
8b1c0b24 | 2455 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); |
120ff942 | 2456 | |
8b1c0b24 JF |
2457 | /* Enable Security TX Buffer IFG for multiple pb */ |
2458 | if (tcs) { | |
2459 | reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2460 | reg |= IXGBE_SECTX_DCB; | |
2461 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); | |
2462 | } | |
120ff942 AD |
2463 | break; |
2464 | } | |
2465 | ||
2466 | /* re-enable the arbiter */ | |
2467 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2468 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2469 | } | |
2470 | ||
9a799d71 | 2471 | /** |
3a581073 | 2472 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2473 | * @adapter: board private structure |
2474 | * | |
2475 | * Configure the Tx unit of the MAC after a reset. | |
2476 | **/ | |
2477 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2478 | { | |
2f1860b8 AD |
2479 | struct ixgbe_hw *hw = &adapter->hw; |
2480 | u32 dmatxctl; | |
43e69bf0 | 2481 | u32 i; |
9a799d71 | 2482 | |
2f1860b8 AD |
2483 | ixgbe_setup_mtqc(adapter); |
2484 | ||
2485 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2486 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2487 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2488 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2489 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2490 | } | |
2491 | ||
9a799d71 | 2492 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2493 | for (i = 0; i < adapter->num_tx_queues; i++) |
2494 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2495 | } |
2496 | ||
e8e26350 | 2497 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2498 | |
a6616b42 | 2499 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2500 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2501 | { |
cc41ac7c | 2502 | u32 srrctl; |
bf29ee6c | 2503 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2504 | |
bd508178 AD |
2505 | switch (adapter->hw.mac.type) { |
2506 | case ixgbe_mac_82598EB: { | |
2507 | struct ixgbe_ring_feature *feature = adapter->ring_feature; | |
2508 | const int mask = feature[RING_F_RSS].mask; | |
bf29ee6c | 2509 | reg_idx = reg_idx & mask; |
cc41ac7c | 2510 | } |
bd508178 AD |
2511 | break; |
2512 | case ixgbe_mac_82599EB: | |
b93a2226 | 2513 | case ixgbe_mac_X540: |
bd508178 AD |
2514 | default: |
2515 | break; | |
2516 | } | |
2517 | ||
bf29ee6c | 2518 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx)); |
cc41ac7c JB |
2519 | |
2520 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2521 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2522 | if (adapter->num_vfs) |
2523 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2524 | |
afafd5b0 AD |
2525 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2526 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2527 | ||
7d637bcc | 2528 | if (ring_is_ps_enabled(rx_ring)) { |
afafd5b0 AD |
2529 | #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER |
2530 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2531 | #else | |
2532 | srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
2533 | #endif | |
cc41ac7c | 2534 | srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; |
cc41ac7c | 2535 | } else { |
afafd5b0 AD |
2536 | srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >> |
2537 | IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
cc41ac7c | 2538 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
cc41ac7c | 2539 | } |
e8e26350 | 2540 | |
bf29ee6c | 2541 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2542 | } |
9a799d71 | 2543 | |
05abb126 | 2544 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2545 | { |
05abb126 AD |
2546 | struct ixgbe_hw *hw = &adapter->hw; |
2547 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2548 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2549 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2550 | u32 mrqc = 0, reta = 0; |
2551 | u32 rxcsum; | |
2552 | int i, j; | |
8b1c0b24 | 2553 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
86b4db3b JF |
2554 | int maxq = adapter->ring_feature[RING_F_RSS].indices; |
2555 | ||
2556 | if (tcs) | |
2557 | maxq = min(maxq, adapter->num_tx_queues / tcs); | |
0cefafad | 2558 | |
05abb126 AD |
2559 | /* Fill out hash function seeds */ |
2560 | for (i = 0; i < 10; i++) | |
2561 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2562 | ||
2563 | /* Fill out redirection table */ | |
2564 | for (i = 0, j = 0; i < 128; i++, j++) { | |
86b4db3b | 2565 | if (j == maxq) |
05abb126 AD |
2566 | j = 0; |
2567 | /* reta = 4-byte sliding window of | |
2568 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2569 | reta = (reta << 8) | (j * 0x11); | |
2570 | if ((i & 3) == 3) | |
2571 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2572 | } | |
0cefafad | 2573 | |
05abb126 AD |
2574 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2575 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2576 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2577 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2578 | ||
8b1c0b24 JF |
2579 | if (adapter->hw.mac.type == ixgbe_mac_82598EB && |
2580 | (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { | |
0cefafad | 2581 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 JF |
2582 | } else { |
2583 | int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2584 | | IXGBE_FLAG_SRIOV_ENABLED); | |
2585 | ||
2586 | switch (mask) { | |
2587 | case (IXGBE_FLAG_RSS_ENABLED): | |
2588 | if (!tcs) | |
2589 | mrqc = IXGBE_MRQC_RSSEN; | |
2590 | else if (tcs <= 4) | |
2591 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
2592 | else | |
2593 | mrqc = IXGBE_MRQC_RTRSS8TCEN; | |
2594 | break; | |
2595 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2596 | mrqc = IXGBE_MRQC_VMDQEN; | |
2597 | break; | |
2598 | default: | |
2599 | break; | |
2600 | } | |
0cefafad JB |
2601 | } |
2602 | ||
05abb126 AD |
2603 | /* Perform hash on these packet types */ |
2604 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2605 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2606 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2607 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2608 | ||
2609 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
0cefafad JB |
2610 | } |
2611 | ||
bb5a9ad2 NS |
2612 | /** |
2613 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2614 | * @adapter: address of board private structure | |
2615 | * @index: index of ring to set | |
bb5a9ad2 | 2616 | **/ |
082757af | 2617 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2618 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2619 | { |
bb5a9ad2 | 2620 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2621 | u32 rscctrl; |
edd2ea55 | 2622 | int rx_buf_len; |
bf29ee6c | 2623 | u8 reg_idx = ring->reg_idx; |
7367096a | 2624 | |
7d637bcc | 2625 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2626 | return; |
bb5a9ad2 | 2627 | |
7367096a AD |
2628 | rx_buf_len = ring->rx_buf_len; |
2629 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); | |
bb5a9ad2 NS |
2630 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2631 | /* | |
2632 | * we must limit the number of descriptors so that the | |
2633 | * total size of max desc * buf_len is not greater | |
2634 | * than 65535 | |
2635 | */ | |
7d637bcc | 2636 | if (ring_is_ps_enabled(ring)) { |
bb5a9ad2 NS |
2637 | #if (MAX_SKB_FRAGS > 16) |
2638 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2639 | #elif (MAX_SKB_FRAGS > 8) | |
2640 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
2641 | #elif (MAX_SKB_FRAGS > 4) | |
2642 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2643 | #else | |
2644 | rscctrl |= IXGBE_RSCCTL_MAXDESC_1; | |
2645 | #endif | |
2646 | } else { | |
919e78a6 | 2647 | if (rx_buf_len < IXGBE_RXBUFFER_4K) |
bb5a9ad2 | 2648 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; |
919e78a6 | 2649 | else if (rx_buf_len < IXGBE_RXBUFFER_8K) |
bb5a9ad2 NS |
2650 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; |
2651 | else | |
2652 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; | |
2653 | } | |
7367096a | 2654 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2655 | } |
2656 | ||
9e10e045 AD |
2657 | /** |
2658 | * ixgbe_set_uta - Set unicast filter table address | |
2659 | * @adapter: board private structure | |
2660 | * | |
2661 | * The unicast table address is a register array of 32-bit registers. | |
2662 | * The table is meant to be used in a way similar to how the MTA is used | |
2663 | * however due to certain limitations in the hardware it is necessary to | |
2664 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous | |
2665 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
2666 | **/ | |
2667 | static void ixgbe_set_uta(struct ixgbe_adapter *adapter) | |
2668 | { | |
2669 | struct ixgbe_hw *hw = &adapter->hw; | |
2670 | int i; | |
2671 | ||
2672 | /* The UTA table only exists on 82599 hardware and newer */ | |
2673 | if (hw->mac.type < ixgbe_mac_82599EB) | |
2674 | return; | |
2675 | ||
2676 | /* we only need to do this if VMDq is enabled */ | |
2677 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2678 | return; | |
2679 | ||
2680 | for (i = 0; i < 128; i++) | |
2681 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); | |
2682 | } | |
2683 | ||
2684 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
2685 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2686 | struct ixgbe_ring *ring) | |
2687 | { | |
2688 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
2689 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
2690 | u32 rxdctl; | |
bf29ee6c | 2691 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
2692 | |
2693 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2694 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2695 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2696 | return; | |
2697 | ||
2698 | do { | |
032b4325 | 2699 | usleep_range(1000, 2000); |
9e10e045 AD |
2700 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
2701 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2702 | ||
2703 | if (!wait_loop) { | |
2704 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
2705 | "the polling period\n", reg_idx); | |
2706 | } | |
2707 | } | |
2708 | ||
2d39d576 YZ |
2709 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
2710 | struct ixgbe_ring *ring) | |
2711 | { | |
2712 | struct ixgbe_hw *hw = &adapter->hw; | |
2713 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
2714 | u32 rxdctl; | |
2715 | u8 reg_idx = ring->reg_idx; | |
2716 | ||
2717 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2718 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
2719 | ||
2720 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
2721 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
2722 | ||
2723 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2724 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2725 | return; | |
2726 | ||
2727 | /* the hardware may take up to 100us to really disable the rx queue */ | |
2728 | do { | |
2729 | udelay(10); | |
2730 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2731 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2732 | ||
2733 | if (!wait_loop) { | |
2734 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
2735 | "the polling period\n", reg_idx); | |
2736 | } | |
2737 | } | |
2738 | ||
84418e3b AD |
2739 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
2740 | struct ixgbe_ring *ring) | |
acd37177 AD |
2741 | { |
2742 | struct ixgbe_hw *hw = &adapter->hw; | |
2743 | u64 rdba = ring->dma; | |
9e10e045 | 2744 | u32 rxdctl; |
bf29ee6c | 2745 | u8 reg_idx = ring->reg_idx; |
acd37177 | 2746 | |
9e10e045 AD |
2747 | /* disable queue to avoid issues while updating state */ |
2748 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 2749 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 2750 | |
acd37177 AD |
2751 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
2752 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
2753 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
2754 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
2755 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
2756 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 2757 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
2758 | |
2759 | ixgbe_configure_srrctl(adapter, ring); | |
2760 | ixgbe_configure_rscctl(adapter, ring); | |
2761 | ||
e9f98072 GR |
2762 | /* If operating in IOV mode set RLPML for X540 */ |
2763 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
2764 | hw->mac.type == ixgbe_mac_X540) { | |
2765 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
2766 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
2767 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
2768 | } | |
2769 | ||
9e10e045 AD |
2770 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2771 | /* | |
2772 | * enable cache line friendly hardware writes: | |
2773 | * PTHRESH=32 descriptors (half the internal cache), | |
2774 | * this also removes ugly rx_no_buffer_count increment | |
2775 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
2776 | * WTHRESH=8 burst writeback up to two cache lines | |
2777 | */ | |
2778 | rxdctl &= ~0x3FFFFF; | |
2779 | rxdctl |= 0x080420; | |
2780 | } | |
2781 | ||
2782 | /* enable receive descriptor ring */ | |
2783 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
2784 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
2785 | ||
2786 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 2787 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
2788 | } |
2789 | ||
48654521 AD |
2790 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
2791 | { | |
2792 | struct ixgbe_hw *hw = &adapter->hw; | |
2793 | int p; | |
2794 | ||
2795 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
2796 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
2797 | IXGBE_PSRTYPE_UDPHDR | |
2798 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 2799 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 2800 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
2801 | |
2802 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2803 | return; | |
2804 | ||
2805 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
2806 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
2807 | ||
2808 | for (p = 0; p < adapter->num_rx_pools; p++) | |
2809 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
2810 | psrtype); | |
2811 | } | |
2812 | ||
f5b4a52e AD |
2813 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
2814 | { | |
2815 | struct ixgbe_hw *hw = &adapter->hw; | |
2816 | u32 gcr_ext; | |
2817 | u32 vt_reg_bits; | |
2818 | u32 reg_offset, vf_shift; | |
2819 | u32 vmdctl; | |
2820 | ||
2821 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2822 | return; | |
2823 | ||
2824 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
2825 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
2826 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
2827 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
2828 | ||
2829 | vf_shift = adapter->num_vfs % 32; | |
2830 | reg_offset = (adapter->num_vfs > 32) ? 1 : 0; | |
2831 | ||
2832 | /* Enable only the PF's pool for Tx/Rx */ | |
2833 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
2834 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
2835 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
2836 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
2837 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
2838 | ||
2839 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
2840 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
2841 | ||
2842 | /* | |
2843 | * Set up VF register offsets for selected VT Mode, | |
2844 | * i.e. 32 or 64 VFs for SR-IOV | |
2845 | */ | |
2846 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
2847 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
2848 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
2849 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
2850 | ||
2851 | /* enable Tx loopback for VF/PF communication */ | |
2852 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 | 2853 | /* Enable MAC Anti-Spoofing */ |
a1cbb15c GR |
2854 | hw->mac.ops.set_mac_anti_spoofing(hw, |
2855 | (adapter->antispoofing_enabled = | |
2856 | (adapter->num_vfs != 0)), | |
a985b6c3 | 2857 | adapter->num_vfs); |
f5b4a52e AD |
2858 | } |
2859 | ||
477de6ed | 2860 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 2861 | { |
9a799d71 AK |
2862 | struct ixgbe_hw *hw = &adapter->hw; |
2863 | struct net_device *netdev = adapter->netdev; | |
2864 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
7c6e0a43 | 2865 | int rx_buf_len; |
477de6ed AD |
2866 | struct ixgbe_ring *rx_ring; |
2867 | int i; | |
2868 | u32 mhadd, hlreg0; | |
48654521 | 2869 | |
9a799d71 | 2870 | /* Decide whether to use packet split mode or not */ |
a124339a DS |
2871 | /* On by default */ |
2872 | adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED; | |
2873 | ||
1cdd1ec8 | 2874 | /* Do not use packet split if we're in SR-IOV Mode */ |
a124339a DS |
2875 | if (adapter->num_vfs) |
2876 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
2877 | ||
2878 | /* Disable packet split due to 82599 erratum #45 */ | |
2879 | if (hw->mac.type == ixgbe_mac_82599EB) | |
2880 | adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED; | |
9a799d71 | 2881 | |
63f39bd1 | 2882 | #ifdef IXGBE_FCOE |
477de6ed AD |
2883 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
2884 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
2885 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
2886 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 2887 | |
477de6ed AD |
2888 | #endif /* IXGBE_FCOE */ |
2889 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
2890 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
2891 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
2892 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
2893 | ||
2894 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
2895 | } | |
2896 | ||
919e78a6 AD |
2897 | /* MHADD will allow an extra 4 bytes past for vlan tagged frames */ |
2898 | max_frame += VLAN_HLEN; | |
2899 | ||
2900 | /* Set the RX buffer length according to the mode */ | |
2901 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) { | |
2902 | rx_buf_len = IXGBE_RX_HDR_SIZE; | |
2903 | } else { | |
2904 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && | |
2905 | (netdev->mtu <= ETH_DATA_LEN)) | |
2906 | rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE; | |
2907 | /* | |
2908 | * Make best use of allocation by using all but 1K of a | |
2909 | * power of 2 allocation that will be used for skb->head. | |
2910 | */ | |
2911 | else if (max_frame <= IXGBE_RXBUFFER_3K) | |
2912 | rx_buf_len = IXGBE_RXBUFFER_3K; | |
2913 | else if (max_frame <= IXGBE_RXBUFFER_7K) | |
2914 | rx_buf_len = IXGBE_RXBUFFER_7K; | |
2915 | else if (max_frame <= IXGBE_RXBUFFER_15K) | |
2916 | rx_buf_len = IXGBE_RXBUFFER_15K; | |
2917 | else | |
2918 | rx_buf_len = IXGBE_MAX_RXBUFFER; | |
2919 | } | |
2920 | ||
477de6ed AD |
2921 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
2922 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
2923 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
2924 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 2925 | |
0cefafad JB |
2926 | /* |
2927 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
2928 | * the Base and Length of the Rx Descriptor Ring | |
2929 | */ | |
9a799d71 | 2930 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 2931 | rx_ring = adapter->rx_ring[i]; |
a6616b42 | 2932 | rx_ring->rx_buf_len = rx_buf_len; |
cc41ac7c | 2933 | |
6e455b89 | 2934 | if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) |
7d637bcc AD |
2935 | set_ring_ps_enabled(rx_ring); |
2936 | else | |
2937 | clear_ring_ps_enabled(rx_ring); | |
2938 | ||
2939 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
2940 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 2941 | else |
7d637bcc | 2942 | clear_ring_rsc_enabled(rx_ring); |
cc41ac7c | 2943 | |
63f39bd1 | 2944 | #ifdef IXGBE_FCOE |
e8e9f696 | 2945 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
2946 | struct ixgbe_ring_feature *f; |
2947 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6e455b89 | 2948 | if ((i >= f->mask) && (i < f->mask + f->indices)) { |
7d637bcc | 2949 | clear_ring_ps_enabled(rx_ring); |
6e455b89 YZ |
2950 | if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) |
2951 | rx_ring->rx_buf_len = | |
e8e9f696 | 2952 | IXGBE_FCOE_JUMBO_FRAME_SIZE; |
7d637bcc AD |
2953 | } else if (!ring_is_rsc_enabled(rx_ring) && |
2954 | !ring_is_ps_enabled(rx_ring)) { | |
2955 | rx_ring->rx_buf_len = | |
2956 | IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
6e455b89 | 2957 | } |
63f39bd1 | 2958 | } |
63f39bd1 | 2959 | #endif /* IXGBE_FCOE */ |
477de6ed | 2960 | } |
477de6ed AD |
2961 | } |
2962 | ||
7367096a AD |
2963 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
2964 | { | |
2965 | struct ixgbe_hw *hw = &adapter->hw; | |
2966 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
2967 | ||
2968 | switch (hw->mac.type) { | |
2969 | case ixgbe_mac_82598EB: | |
2970 | /* | |
2971 | * For VMDq support of different descriptor types or | |
2972 | * buffer sizes through the use of multiple SRRCTL | |
2973 | * registers, RDRXCTL.MVMEN must be set to 1 | |
2974 | * | |
2975 | * also, the manual doesn't mention it clearly but DCA hints | |
2976 | * will only use queue 0's tags unless this bit is set. Side | |
2977 | * effects of setting this bit are only that SRRCTL must be | |
2978 | * fully programmed [0..15] | |
2979 | */ | |
2980 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
2981 | break; | |
2982 | case ixgbe_mac_82599EB: | |
b93a2226 | 2983 | case ixgbe_mac_X540: |
7367096a AD |
2984 | /* Disable RSC for ACK packets */ |
2985 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
2986 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
2987 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
2988 | /* hardware requires some bits to be set by default */ | |
2989 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
2990 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
2991 | break; | |
2992 | default: | |
2993 | /* We should do nothing since we don't know this hardware */ | |
2994 | return; | |
2995 | } | |
2996 | ||
2997 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
2998 | } | |
2999 | ||
477de6ed AD |
3000 | /** |
3001 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3002 | * @adapter: board private structure | |
3003 | * | |
3004 | * Configure the Rx unit of the MAC after a reset. | |
3005 | **/ | |
3006 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3007 | { | |
3008 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3009 | int i; |
3010 | u32 rxctrl; | |
477de6ed AD |
3011 | |
3012 | /* disable receives while setting up the descriptors */ | |
3013 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3014 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3015 | ||
3016 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3017 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3018 | |
9e10e045 | 3019 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3020 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3021 | |
9e10e045 AD |
3022 | ixgbe_set_uta(adapter); |
3023 | ||
477de6ed AD |
3024 | /* set_rx_buffer_len must be called before ring initialization */ |
3025 | ixgbe_set_rx_buffer_len(adapter); | |
3026 | ||
3027 | /* | |
3028 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3029 | * the Base and Length of the Rx Descriptor Ring | |
3030 | */ | |
9e10e045 AD |
3031 | for (i = 0; i < adapter->num_rx_queues; i++) |
3032 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3033 | |
9e10e045 AD |
3034 | /* disable drop enable for 82598 parts */ |
3035 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3036 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3037 | ||
3038 | /* enable all receives */ | |
3039 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3040 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3041 | } |
3042 | ||
068c89b0 DS |
3043 | static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
3044 | { | |
3045 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3046 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3047 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3048 | |
3049 | /* add VID to filter table */ | |
1ada1b1b | 3050 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3051 | set_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3052 | } |
3053 | ||
3054 | static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) | |
3055 | { | |
3056 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3057 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3058 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3059 | |
068c89b0 | 3060 | /* remove VID from filter table */ |
1ada1b1b | 3061 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3062 | clear_bit(vid, adapter->active_vlans); |
068c89b0 DS |
3063 | } |
3064 | ||
5f6c0181 JB |
3065 | /** |
3066 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3067 | * @adapter: driver data | |
3068 | */ | |
3069 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3070 | { | |
3071 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3072 | u32 vlnctrl; |
3073 | ||
3074 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3075 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3076 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3077 | } | |
3078 | ||
3079 | /** | |
3080 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3081 | * @adapter: driver data | |
3082 | */ | |
3083 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3084 | { | |
3085 | struct ixgbe_hw *hw = &adapter->hw; | |
3086 | u32 vlnctrl; | |
3087 | ||
3088 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3089 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3090 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3091 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3092 | } | |
3093 | ||
3094 | /** | |
3095 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3096 | * @adapter: driver data | |
3097 | */ | |
3098 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3099 | { | |
3100 | struct ixgbe_hw *hw = &adapter->hw; | |
3101 | u32 vlnctrl; | |
5f6c0181 JB |
3102 | int i, j; |
3103 | ||
3104 | switch (hw->mac.type) { | |
3105 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3106 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3107 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3108 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3109 | break; | |
3110 | case ixgbe_mac_82599EB: | |
b93a2226 | 3111 | case ixgbe_mac_X540: |
5f6c0181 JB |
3112 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3113 | j = adapter->rx_ring[i]->reg_idx; | |
3114 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3115 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3116 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3117 | } | |
3118 | break; | |
3119 | default: | |
3120 | break; | |
3121 | } | |
3122 | } | |
3123 | ||
3124 | /** | |
f62bbb5e | 3125 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3126 | * @adapter: driver data |
3127 | */ | |
f62bbb5e | 3128 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3129 | { |
3130 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3131 | u32 vlnctrl; |
5f6c0181 JB |
3132 | int i, j; |
3133 | ||
3134 | switch (hw->mac.type) { | |
3135 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3136 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3137 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3138 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3139 | break; | |
3140 | case ixgbe_mac_82599EB: | |
b93a2226 | 3141 | case ixgbe_mac_X540: |
5f6c0181 JB |
3142 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3143 | j = adapter->rx_ring[i]->reg_idx; | |
3144 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3145 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3146 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3147 | } | |
3148 | break; | |
3149 | default: | |
3150 | break; | |
3151 | } | |
3152 | } | |
3153 | ||
9a799d71 AK |
3154 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3155 | { | |
f62bbb5e | 3156 | u16 vid; |
9a799d71 | 3157 | |
f62bbb5e JG |
3158 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3159 | ||
3160 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3161 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3162 | } |
3163 | ||
2850062a AD |
3164 | /** |
3165 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3166 | * @netdev: network interface device structure | |
3167 | * | |
3168 | * Writes unicast address list to the RAR table. | |
3169 | * Returns: -ENOMEM on failure/insufficient address space | |
3170 | * 0 on no addresses written | |
3171 | * X on writing X addresses to the RAR table | |
3172 | **/ | |
3173 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3174 | { | |
3175 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3176 | struct ixgbe_hw *hw = &adapter->hw; | |
3177 | unsigned int vfn = adapter->num_vfs; | |
a1cbb15c | 3178 | unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS; |
2850062a AD |
3179 | int count = 0; |
3180 | ||
3181 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3182 | if (netdev_uc_count(netdev) > rar_entries) | |
3183 | return -ENOMEM; | |
3184 | ||
3185 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3186 | struct netdev_hw_addr *ha; | |
3187 | /* return error if we do not support writing to RAR table */ | |
3188 | if (!hw->mac.ops.set_rar) | |
3189 | return -ENOMEM; | |
3190 | ||
3191 | netdev_for_each_uc_addr(ha, netdev) { | |
3192 | if (!rar_entries) | |
3193 | break; | |
3194 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3195 | vfn, IXGBE_RAH_AV); | |
3196 | count++; | |
3197 | } | |
3198 | } | |
3199 | /* write the addresses in reverse order to avoid write combining */ | |
3200 | for (; rar_entries > 0 ; rar_entries--) | |
3201 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3202 | ||
3203 | return count; | |
3204 | } | |
3205 | ||
9a799d71 | 3206 | /** |
2c5645cf | 3207 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3208 | * @netdev: network interface device structure |
3209 | * | |
2c5645cf CL |
3210 | * The set_rx_method entry point is called whenever the unicast/multicast |
3211 | * address list or the network interface flags are updated. This routine is | |
3212 | * responsible for configuring the hardware for proper unicast, multicast and | |
3213 | * promiscuous mode. | |
9a799d71 | 3214 | **/ |
7f870475 | 3215 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3216 | { |
3217 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3218 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3219 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3220 | int count; | |
9a799d71 AK |
3221 | |
3222 | /* Check for Promiscuous and All Multicast modes */ | |
3223 | ||
3224 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3225 | ||
f5dc442b AD |
3226 | /* set all bits that we expect to always be set */ |
3227 | fctrl |= IXGBE_FCTRL_BAM; | |
3228 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3229 | fctrl |= IXGBE_FCTRL_PMCF; | |
3230 | ||
2850062a AD |
3231 | /* clear the bits we are changing the status of */ |
3232 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3233 | ||
9a799d71 | 3234 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3235 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3236 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3237 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3238 | /* don't hardware filter vlans in promisc mode */ |
3239 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3240 | } else { |
746b9f02 PM |
3241 | if (netdev->flags & IFF_ALLMULTI) { |
3242 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3243 | vmolr |= IXGBE_VMOLR_MPE; |
3244 | } else { | |
3245 | /* | |
3246 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3247 | * then we should just turn on promiscuous mode so |
2850062a AD |
3248 | * that we can at least receive multicast traffic |
3249 | */ | |
3250 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3251 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3252 | } |
5f6c0181 | 3253 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3254 | hw->addr_ctrl.user_set_promisc = false; |
2850062a AD |
3255 | /* |
3256 | * Write addresses to available RAR registers, if there is not | |
3257 | * sufficient space to store all the addresses then enable | |
25985edc | 3258 | * unicast promiscuous mode |
2850062a AD |
3259 | */ |
3260 | count = ixgbe_write_uc_addr_list(netdev); | |
3261 | if (count < 0) { | |
3262 | fctrl |= IXGBE_FCTRL_UPE; | |
3263 | vmolr |= IXGBE_VMOLR_ROPE; | |
3264 | } | |
9a799d71 AK |
3265 | } |
3266 | ||
2850062a | 3267 | if (adapter->num_vfs) { |
1cdd1ec8 | 3268 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3269 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3270 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3271 | IXGBE_VMOLR_ROPE); | |
3272 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3273 | } | |
3274 | ||
3275 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
f62bbb5e JG |
3276 | |
3277 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3278 | ixgbe_vlan_strip_enable(adapter); | |
3279 | else | |
3280 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3281 | } |
3282 | ||
021230d4 AV |
3283 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3284 | { | |
3285 | int q_idx; | |
3286 | struct ixgbe_q_vector *q_vector; | |
3287 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3288 | ||
3289 | /* legacy and MSI only use one vector */ | |
3290 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3291 | q_vectors = 1; | |
3292 | ||
3293 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3294 | q_vector = adapter->q_vector[q_idx]; |
4ff7fb12 | 3295 | napi_enable(&q_vector->napi); |
021230d4 AV |
3296 | } |
3297 | } | |
3298 | ||
3299 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3300 | { | |
3301 | int q_idx; | |
3302 | struct ixgbe_q_vector *q_vector; | |
3303 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3304 | ||
3305 | /* legacy and MSI only use one vector */ | |
3306 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3307 | q_vectors = 1; | |
3308 | ||
3309 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3310 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3311 | napi_disable(&q_vector->napi); |
3312 | } | |
3313 | } | |
3314 | ||
7a6b6f51 | 3315 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3316 | /* |
3317 | * ixgbe_configure_dcb - Configure DCB hardware | |
3318 | * @adapter: ixgbe adapter struct | |
3319 | * | |
3320 | * This is called by the driver on open to configure the DCB hardware. | |
3321 | * This is also called by the gennetlink interface when reconfiguring | |
3322 | * the DCB state. | |
3323 | */ | |
3324 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3325 | { | |
3326 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3327 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3328 | |
67ebd791 AD |
3329 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3330 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3331 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3332 | return; | |
3333 | } | |
3334 | ||
3335 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3336 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3337 | ||
2f90b865 | 3338 | |
2f90b865 | 3339 | /* Enable VLAN tag insert/strip */ |
f62bbb5e | 3340 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3341 | |
2f90b865 | 3342 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 AD |
3343 | |
3344 | /* reconfigure the hardware */ | |
6f70f6ac | 3345 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { |
971060b1 | 3346 | #ifdef IXGBE_FCOE |
c27931da JF |
3347 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3348 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
3349 | #endif | |
3350 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3351 | DCB_TX_CONFIG); | |
3352 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3353 | DCB_RX_CONFIG); | |
3354 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
3355 | } else { | |
3356 | struct net_device *dev = adapter->netdev; | |
3357 | ||
3358 | if (adapter->ixgbe_ieee_ets) | |
3359 | dev->dcbnl_ops->ieee_setets(dev, | |
3360 | adapter->ixgbe_ieee_ets); | |
3361 | if (adapter->ixgbe_ieee_pfc) | |
3362 | dev->dcbnl_ops->ieee_setpfc(dev, | |
3363 | adapter->ixgbe_ieee_pfc); | |
3364 | } | |
8187cd48 JF |
3365 | |
3366 | /* Enable RSS Hash per TC */ | |
3367 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3368 | int i; | |
3369 | u32 reg = 0; | |
3370 | ||
3371 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
3372 | u8 msb = 0; | |
3373 | u8 cnt = adapter->netdev->tc_to_txq[i].count; | |
3374 | ||
3375 | while (cnt >>= 1) | |
3376 | msb++; | |
3377 | ||
3378 | reg |= msb << IXGBE_RQTC_SHIFT_TC(i); | |
3379 | } | |
3380 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); | |
3381 | } | |
2f90b865 AD |
3382 | } |
3383 | ||
3384 | #endif | |
80605c65 JF |
3385 | |
3386 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) | |
3387 | { | |
80605c65 | 3388 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3389 | int hdrm; |
3390 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3391 | |
3392 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3393 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3394 | hdrm = 32 << adapter->fdir_pballoc; |
3395 | else | |
3396 | hdrm = 0; | |
80605c65 | 3397 | |
f7e1027f | 3398 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
80605c65 JF |
3399 | } |
3400 | ||
e4911d57 AD |
3401 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3402 | { | |
3403 | struct ixgbe_hw *hw = &adapter->hw; | |
3404 | struct hlist_node *node, *node2; | |
3405 | struct ixgbe_fdir_filter *filter; | |
3406 | ||
3407 | spin_lock(&adapter->fdir_perfect_lock); | |
3408 | ||
3409 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3410 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3411 | ||
3412 | hlist_for_each_entry_safe(filter, node, node2, | |
3413 | &adapter->fdir_filter_list, fdir_node) { | |
3414 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3415 | &filter->filter, |
3416 | filter->sw_idx, | |
3417 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3418 | IXGBE_FDIR_DROP_QUEUE : | |
3419 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3420 | } |
3421 | ||
3422 | spin_unlock(&adapter->fdir_perfect_lock); | |
3423 | } | |
3424 | ||
9a799d71 AK |
3425 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3426 | { | |
80605c65 | 3427 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3428 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3429 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3430 | #endif |
9a799d71 | 3431 | |
4c1d7b4b | 3432 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3433 | ixgbe_restore_vlan(adapter); |
3434 | ||
eacd73f7 YZ |
3435 | #ifdef IXGBE_FCOE |
3436 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3437 | ixgbe_configure_fcoe(adapter); | |
3438 | ||
3439 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 | 3440 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3441 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3442 | adapter->fdir_pballoc); | |
e4911d57 AD |
3443 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3444 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3445 | adapter->fdir_pballoc); | |
3446 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3447 | } |
4c1d7b4b | 3448 | |
933d41f1 | 3449 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3450 | |
9a799d71 AK |
3451 | ixgbe_configure_tx(adapter); |
3452 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3453 | } |
3454 | ||
e8e26350 PW |
3455 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3456 | { | |
3457 | switch (hw->phy.type) { | |
3458 | case ixgbe_phy_sfp_avago: | |
3459 | case ixgbe_phy_sfp_ftl: | |
3460 | case ixgbe_phy_sfp_intel: | |
3461 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3462 | case ixgbe_phy_sfp_passive_tyco: |
3463 | case ixgbe_phy_sfp_passive_unknown: | |
3464 | case ixgbe_phy_sfp_active_unknown: | |
3465 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3466 | return true; |
8917b447 AD |
3467 | case ixgbe_phy_nl: |
3468 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3469 | return true; | |
e8e26350 PW |
3470 | default: |
3471 | return false; | |
3472 | } | |
3473 | } | |
3474 | ||
0ecc061d | 3475 | /** |
e8e26350 PW |
3476 | * ixgbe_sfp_link_config - set up SFP+ link |
3477 | * @adapter: pointer to private adapter struct | |
3478 | **/ | |
3479 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3480 | { | |
7086400d AD |
3481 | /* |
3482 | * We are assuming the worst case scenerio here, and that | |
3483 | * is that an SFP was inserted/removed after the reset | |
3484 | * but before SFP detection was enabled. As such the best | |
3485 | * solution is to just start searching as soon as we start | |
3486 | */ | |
3487 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3488 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3489 | |
7086400d | 3490 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3491 | } |
3492 | ||
3493 | /** | |
3494 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3495 | * @hw: pointer to private hardware struct |
3496 | * | |
3497 | * Returns 0 on success, negative on failure | |
3498 | **/ | |
e8e26350 | 3499 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3500 | { |
3501 | u32 autoneg; | |
8620a103 | 3502 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3503 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3504 | ||
3505 | if (hw->mac.ops.check_link) | |
3506 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3507 | ||
3508 | if (ret) | |
3509 | goto link_cfg_out; | |
3510 | ||
0b0c2b31 ET |
3511 | autoneg = hw->phy.autoneg_advertised; |
3512 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3513 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3514 | &negotiation); | |
0ecc061d PWJ |
3515 | if (ret) |
3516 | goto link_cfg_out; | |
3517 | ||
8620a103 MC |
3518 | if (hw->mac.ops.setup_link) |
3519 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3520 | link_cfg_out: |
3521 | return ret; | |
3522 | } | |
3523 | ||
a34bcfff | 3524 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3525 | { |
9a799d71 | 3526 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3527 | u32 gpie = 0; |
9a799d71 | 3528 | |
9b471446 | 3529 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3530 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3531 | IXGBE_GPIE_OCD; | |
3532 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3533 | /* |
3534 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3535 | * this saves a register write for every interrupt | |
3536 | */ | |
3537 | switch (hw->mac.type) { | |
3538 | case ixgbe_mac_82598EB: | |
3539 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3540 | break; | |
9b471446 | 3541 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3542 | case ixgbe_mac_X540: |
3543 | default: | |
9b471446 JB |
3544 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3545 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3546 | break; | |
3547 | } | |
3548 | } else { | |
021230d4 AV |
3549 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3550 | * specifically only auto mask tx and rx interrupts */ | |
3551 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3552 | } | |
9a799d71 | 3553 | |
a34bcfff AD |
3554 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3555 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3556 | ||
3557 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3558 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3559 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3560 | } |
3561 | ||
5fdd31f9 AD |
3562 | /* Enable Thermal over heat sensor interrupt */ |
3563 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) | |
3564 | gpie |= IXGBE_SDP0_GPIEN; | |
3565 | ||
a34bcfff AD |
3566 | /* Enable fan failure interrupt */ |
3567 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3568 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3569 | |
2698b208 | 3570 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3571 | gpie |= IXGBE_SDP1_GPIEN; |
3572 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3573 | } |
a34bcfff AD |
3574 | |
3575 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3576 | } | |
3577 | ||
c7ccde0f | 3578 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
3579 | { |
3580 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3581 | int err; |
a34bcfff AD |
3582 | u32 ctrl_ext; |
3583 | ||
3584 | ixgbe_get_hw_control(adapter); | |
3585 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3586 | |
9a799d71 AK |
3587 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3588 | ixgbe_configure_msix(adapter); | |
3589 | else | |
3590 | ixgbe_configure_msi_and_legacy(adapter); | |
3591 | ||
c6ecf39a DS |
3592 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3593 | if (hw->mac.ops.enable_tx_laser && | |
3594 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3595 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3596 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3597 | hw->mac.ops.enable_tx_laser(hw); |
3598 | ||
9a799d71 | 3599 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3600 | ixgbe_napi_enable_all(adapter); |
3601 | ||
73c4b7cd AD |
3602 | if (ixgbe_is_sfp(hw)) { |
3603 | ixgbe_sfp_link_config(adapter); | |
3604 | } else { | |
3605 | err = ixgbe_non_sfp_link_config(hw); | |
3606 | if (err) | |
3607 | e_err(probe, "link_config FAILED %d\n", err); | |
3608 | } | |
3609 | ||
021230d4 AV |
3610 | /* clear any pending interrupts, may auto mask */ |
3611 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3612 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3613 | |
bf069c97 DS |
3614 | /* |
3615 | * If this adapter has a fan, check to see if we had a failure | |
3616 | * before we enabled the interrupt. | |
3617 | */ | |
3618 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3619 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3620 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3621 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3622 | } |
3623 | ||
1da100bb | 3624 | /* enable transmits */ |
477de6ed | 3625 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 3626 | |
9a799d71 AK |
3627 | /* bring the link up in the watchdog, this could race with our first |
3628 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3629 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3630 | adapter->link_check_timeout = jiffies; | |
7086400d | 3631 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
3632 | |
3633 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3634 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3635 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3636 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
3637 | } |
3638 | ||
d4f80882 AV |
3639 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3640 | { | |
3641 | WARN_ON(in_interrupt()); | |
7086400d AD |
3642 | /* put off any impending NetWatchDogTimeout */ |
3643 | adapter->netdev->trans_start = jiffies; | |
3644 | ||
d4f80882 | 3645 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 3646 | usleep_range(1000, 2000); |
d4f80882 | 3647 | ixgbe_down(adapter); |
5809a1ae GR |
3648 | /* |
3649 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3650 | * back up to give the VFs time to respond to the reset. The | |
3651 | * two second wait is based upon the watchdog timer cycle in | |
3652 | * the VF driver. | |
3653 | */ | |
3654 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3655 | msleep(2000); | |
d4f80882 AV |
3656 | ixgbe_up(adapter); |
3657 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
3658 | } | |
3659 | ||
c7ccde0f | 3660 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3661 | { |
3662 | /* hardware has been reset, we need to reload some things */ | |
3663 | ixgbe_configure(adapter); | |
3664 | ||
c7ccde0f | 3665 | ixgbe_up_complete(adapter); |
9a799d71 AK |
3666 | } |
3667 | ||
3668 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
3669 | { | |
c44ade9e | 3670 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
3671 | int err; |
3672 | ||
7086400d AD |
3673 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
3674 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
3675 | usleep_range(1000, 2000); | |
3676 | ||
3677 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
3678 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
3679 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
3680 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
3681 | ||
8ca783ab | 3682 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
3683 | switch (err) { |
3684 | case 0: | |
3685 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 3686 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
3687 | break; |
3688 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 3689 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 3690 | break; |
794caeb2 PWJ |
3691 | case IXGBE_ERR_EEPROM_VERSION: |
3692 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
3693 | e_dev_warn("This device is a pre-production adapter/LOM. " |
3694 | "Please be aware there may be issuesassociated with " | |
3695 | "your hardware. If you are experiencing problems " | |
3696 | "please contact your Intel or hardware " | |
3697 | "representative who provided you with this " | |
3698 | "hardware.\n"); | |
794caeb2 | 3699 | break; |
da4dd0f7 | 3700 | default: |
849c4542 | 3701 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 3702 | } |
9a799d71 | 3703 | |
7086400d AD |
3704 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
3705 | ||
9a799d71 | 3706 | /* reprogram the RAR[0] in case user changed it. */ |
1cdd1ec8 GR |
3707 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
3708 | IXGBE_RAH_AV); | |
9a799d71 AK |
3709 | } |
3710 | ||
9a799d71 AK |
3711 | /** |
3712 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
3713 | * @rx_ring: ring to free buffers from |
3714 | **/ | |
b6ec895e | 3715 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 3716 | { |
b6ec895e | 3717 | struct device *dev = rx_ring->dev; |
9a799d71 | 3718 | unsigned long size; |
b6ec895e | 3719 | u16 i; |
9a799d71 | 3720 | |
84418e3b AD |
3721 | /* ring already cleared, nothing to do */ |
3722 | if (!rx_ring->rx_buffer_info) | |
3723 | return; | |
9a799d71 | 3724 | |
84418e3b | 3725 | /* Free all the Rx ring sk_buffs */ |
9a799d71 AK |
3726 | for (i = 0; i < rx_ring->count; i++) { |
3727 | struct ixgbe_rx_buffer *rx_buffer_info; | |
3728 | ||
3729 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
3730 | if (rx_buffer_info->dma) { | |
b6ec895e | 3731 | dma_unmap_single(rx_ring->dev, rx_buffer_info->dma, |
e8e9f696 | 3732 | rx_ring->rx_buf_len, |
1b507730 | 3733 | DMA_FROM_DEVICE); |
9a799d71 AK |
3734 | rx_buffer_info->dma = 0; |
3735 | } | |
3736 | if (rx_buffer_info->skb) { | |
f8212f97 | 3737 | struct sk_buff *skb = rx_buffer_info->skb; |
9a799d71 | 3738 | rx_buffer_info->skb = NULL; |
f8212f97 AD |
3739 | do { |
3740 | struct sk_buff *this = skb; | |
e8171aaa | 3741 | if (IXGBE_RSC_CB(this)->delay_unmap) { |
b6ec895e | 3742 | dma_unmap_single(dev, |
1b507730 | 3743 | IXGBE_RSC_CB(this)->dma, |
e8e9f696 | 3744 | rx_ring->rx_buf_len, |
1b507730 | 3745 | DMA_FROM_DEVICE); |
fd3686a8 | 3746 | IXGBE_RSC_CB(this)->dma = 0; |
e8171aaa | 3747 | IXGBE_RSC_CB(skb)->delay_unmap = false; |
fd3686a8 | 3748 | } |
f8212f97 AD |
3749 | skb = skb->prev; |
3750 | dev_kfree_skb(this); | |
3751 | } while (skb); | |
9a799d71 AK |
3752 | } |
3753 | if (!rx_buffer_info->page) | |
3754 | continue; | |
4f57ca6e | 3755 | if (rx_buffer_info->page_dma) { |
b6ec895e | 3756 | dma_unmap_page(dev, rx_buffer_info->page_dma, |
1b507730 | 3757 | PAGE_SIZE / 2, DMA_FROM_DEVICE); |
4f57ca6e JB |
3758 | rx_buffer_info->page_dma = 0; |
3759 | } | |
9a799d71 AK |
3760 | put_page(rx_buffer_info->page); |
3761 | rx_buffer_info->page = NULL; | |
762f4c57 | 3762 | rx_buffer_info->page_offset = 0; |
9a799d71 AK |
3763 | } |
3764 | ||
3765 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
3766 | memset(rx_ring->rx_buffer_info, 0, size); | |
3767 | ||
3768 | /* Zero out the descriptor ring */ | |
3769 | memset(rx_ring->desc, 0, rx_ring->size); | |
3770 | ||
3771 | rx_ring->next_to_clean = 0; | |
3772 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
3773 | } |
3774 | ||
3775 | /** | |
3776 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
3777 | * @tx_ring: ring to be cleaned |
3778 | **/ | |
b6ec895e | 3779 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
3780 | { |
3781 | struct ixgbe_tx_buffer *tx_buffer_info; | |
3782 | unsigned long size; | |
b6ec895e | 3783 | u16 i; |
9a799d71 | 3784 | |
84418e3b AD |
3785 | /* ring already cleared, nothing to do */ |
3786 | if (!tx_ring->tx_buffer_info) | |
3787 | return; | |
9a799d71 | 3788 | |
84418e3b | 3789 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
3790 | for (i = 0; i < tx_ring->count; i++) { |
3791 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 3792 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
3793 | } |
3794 | ||
3795 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
3796 | memset(tx_ring->tx_buffer_info, 0, size); | |
3797 | ||
3798 | /* Zero out the descriptor ring */ | |
3799 | memset(tx_ring->desc, 0, tx_ring->size); | |
3800 | ||
3801 | tx_ring->next_to_use = 0; | |
3802 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
3803 | } |
3804 | ||
3805 | /** | |
021230d4 | 3806 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
3807 | * @adapter: board private structure |
3808 | **/ | |
021230d4 | 3809 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3810 | { |
3811 | int i; | |
3812 | ||
021230d4 | 3813 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 3814 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
3815 | } |
3816 | ||
3817 | /** | |
021230d4 | 3818 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
3819 | * @adapter: board private structure |
3820 | **/ | |
021230d4 | 3821 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3822 | { |
3823 | int i; | |
3824 | ||
021230d4 | 3825 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 3826 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
3827 | } |
3828 | ||
e4911d57 AD |
3829 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
3830 | { | |
3831 | struct hlist_node *node, *node2; | |
3832 | struct ixgbe_fdir_filter *filter; | |
3833 | ||
3834 | spin_lock(&adapter->fdir_perfect_lock); | |
3835 | ||
3836 | hlist_for_each_entry_safe(filter, node, node2, | |
3837 | &adapter->fdir_filter_list, fdir_node) { | |
3838 | hlist_del(&filter->fdir_node); | |
3839 | kfree(filter); | |
3840 | } | |
3841 | adapter->fdir_filter_count = 0; | |
3842 | ||
3843 | spin_unlock(&adapter->fdir_perfect_lock); | |
3844 | } | |
3845 | ||
9a799d71 AK |
3846 | void ixgbe_down(struct ixgbe_adapter *adapter) |
3847 | { | |
3848 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 3849 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 3850 | u32 rxctrl; |
bf29ee6c | 3851 | int i; |
9a799d71 AK |
3852 | |
3853 | /* signal that we are down to the interrupt handler */ | |
3854 | set_bit(__IXGBE_DOWN, &adapter->state); | |
3855 | ||
3856 | /* disable receives */ | |
7f821875 JB |
3857 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
3858 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 3859 | |
2d39d576 YZ |
3860 | /* disable all enabled rx queues */ |
3861 | for (i = 0; i < adapter->num_rx_queues; i++) | |
3862 | /* this call also flushes the previous write */ | |
3863 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
3864 | ||
032b4325 | 3865 | usleep_range(10000, 20000); |
9a799d71 | 3866 | |
7f821875 JB |
3867 | netif_tx_stop_all_queues(netdev); |
3868 | ||
7086400d | 3869 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
3870 | netif_carrier_off(netdev); |
3871 | netif_tx_disable(netdev); | |
3872 | ||
3873 | ixgbe_irq_disable(adapter); | |
3874 | ||
3875 | ixgbe_napi_disable_all(adapter); | |
3876 | ||
d034acf1 AD |
3877 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
3878 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
3879 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
3880 | ||
3881 | del_timer_sync(&adapter->service_timer); | |
3882 | ||
34cecbbf | 3883 | if (adapter->num_vfs) { |
8e34d1aa AD |
3884 | /* Clear EITR Select mapping */ |
3885 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
3886 | |
3887 | /* Mark all the VFs as inactive */ | |
3888 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3889 | adapter->vfinfo[i].clear_to_send = 0; | |
34cecbbf | 3890 | |
34cecbbf AD |
3891 | /* ping all the active vfs to let them know we are going down */ |
3892 | ixgbe_ping_all_vfs(adapter); | |
3893 | ||
3894 | /* Disable all VFTE/VFRE TX/RX */ | |
3895 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
3896 | } |
3897 | ||
7f821875 JB |
3898 | /* disable transmits in the hardware now that interrupts are off */ |
3899 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 3900 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 3901 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 3902 | } |
34cecbbf AD |
3903 | |
3904 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
3905 | switch (hw->mac.type) { |
3906 | case ixgbe_mac_82599EB: | |
b93a2226 | 3907 | case ixgbe_mac_X540: |
88512539 | 3908 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
3909 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
3910 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
3911 | break; |
3912 | default: | |
3913 | break; | |
3914 | } | |
7f821875 | 3915 | |
6f4a0e45 PL |
3916 | if (!pci_channel_offline(adapter->pdev)) |
3917 | ixgbe_reset(adapter); | |
c6ecf39a DS |
3918 | |
3919 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
3920 | if (hw->mac.ops.disable_tx_laser && | |
3921 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3922 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
3923 | (hw->mac.type == ixgbe_mac_82599EB)))) |
3924 | hw->mac.ops.disable_tx_laser(hw); | |
3925 | ||
9a799d71 AK |
3926 | ixgbe_clean_all_tx_rings(adapter); |
3927 | ixgbe_clean_all_rx_rings(adapter); | |
3928 | ||
5dd2d332 | 3929 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 3930 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 3931 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 3932 | #endif |
9a799d71 AK |
3933 | } |
3934 | ||
9a799d71 | 3935 | /** |
021230d4 AV |
3936 | * ixgbe_poll - NAPI Rx polling callback |
3937 | * @napi: structure for representing this polling device | |
3938 | * @budget: how many packets driver is allowed to clean | |
3939 | * | |
3940 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 3941 | **/ |
021230d4 | 3942 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 3943 | { |
9a1a69ad | 3944 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 3945 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 3946 | struct ixgbe_adapter *adapter = q_vector->adapter; |
4ff7fb12 AD |
3947 | struct ixgbe_ring *ring; |
3948 | int per_ring_budget; | |
3949 | bool clean_complete = true; | |
9a799d71 | 3950 | |
5dd2d332 | 3951 | #ifdef CONFIG_IXGBE_DCA |
33cf09c9 AD |
3952 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
3953 | ixgbe_update_dca(q_vector); | |
bd0362dd JC |
3954 | #endif |
3955 | ||
4ff7fb12 AD |
3956 | for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next) |
3957 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); | |
9a799d71 | 3958 | |
4ff7fb12 AD |
3959 | /* attempt to distribute budget to each queue fairly, but don't allow |
3960 | * the budget to go below 1 because we'll exit polling */ | |
3961 | if (q_vector->rx.count > 1) | |
3962 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
3963 | else | |
3964 | per_ring_budget = budget; | |
d2c7ddd6 | 3965 | |
4ff7fb12 AD |
3966 | for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next) |
3967 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, | |
3968 | per_ring_budget); | |
3969 | ||
3970 | /* If all work not completed, return budget and keep polling */ | |
3971 | if (!clean_complete) | |
3972 | return budget; | |
3973 | ||
3974 | /* all work done, exit the polling mode */ | |
3975 | napi_complete(napi); | |
3976 | if (adapter->rx_itr_setting & 1) | |
3977 | ixgbe_set_itr(q_vector); | |
3978 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
3979 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
3980 | ||
3981 | return 0; | |
9a799d71 AK |
3982 | } |
3983 | ||
3984 | /** | |
3985 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
3986 | * @netdev: network interface device structure | |
3987 | **/ | |
3988 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
3989 | { | |
3990 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3991 | ||
3992 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 3993 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
3994 | } |
3995 | ||
4df10466 JB |
3996 | /** |
3997 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
3998 | * @adapter: board private structure to initialize | |
3999 | * | |
4000 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
4001 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
4002 | * | |
4003 | **/ | |
bc97114d PWJ |
4004 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
4005 | { | |
4006 | bool ret = false; | |
0cefafad | 4007 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
4008 | |
4009 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
4010 | f->mask = 0xF; |
4011 | adapter->num_rx_queues = f->indices; | |
4012 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
4013 | ret = true; |
4014 | } else { | |
bc97114d | 4015 | ret = false; |
b9804972 JB |
4016 | } |
4017 | ||
bc97114d PWJ |
4018 | return ret; |
4019 | } | |
4020 | ||
c4cf55e5 PWJ |
4021 | /** |
4022 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
4023 | * @adapter: board private structure to initialize | |
4024 | * | |
4025 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
4026 | * to the original CPU that initiated the Tx session. This runs in addition | |
4027 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
4028 | * Rx load across CPUs using RSS. | |
4029 | * | |
4030 | **/ | |
e8e9f696 | 4031 | static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4032 | { |
4033 | bool ret = false; | |
4034 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
4035 | ||
4036 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
4037 | f_fdir->mask = 0; | |
4038 | ||
4039 | /* Flow Director must have RSS enabled */ | |
03ecf91a AD |
4040 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && |
4041 | (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) { | |
c4cf55e5 PWJ |
4042 | adapter->num_tx_queues = f_fdir->indices; |
4043 | adapter->num_rx_queues = f_fdir->indices; | |
4044 | ret = true; | |
4045 | } else { | |
4046 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
c4cf55e5 PWJ |
4047 | } |
4048 | return ret; | |
4049 | } | |
4050 | ||
0331a832 YZ |
4051 | #ifdef IXGBE_FCOE |
4052 | /** | |
4053 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
4054 | * @adapter: board private structure to initialize | |
4055 | * | |
4056 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
4057 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
4058 | * rx queues out of the max number of rx queues, instead, it is used as the | |
4059 | * index of the first rx queue used by FCoE. | |
4060 | * | |
4061 | **/ | |
4062 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
4063 | { | |
0331a832 YZ |
4064 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
4065 | ||
e5b64635 JF |
4066 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) |
4067 | return false; | |
4068 | ||
e901acd6 | 4069 | f->indices = min((int)num_online_cpus(), f->indices); |
e5b64635 | 4070 | |
e901acd6 JF |
4071 | adapter->num_rx_queues = 1; |
4072 | adapter->num_tx_queues = 1; | |
e5b64635 | 4073 | |
e901acd6 JF |
4074 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
4075 | e_info(probe, "FCoE enabled with RSS\n"); | |
03ecf91a | 4076 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
e901acd6 JF |
4077 | ixgbe_set_fdir_queues(adapter); |
4078 | else | |
4079 | ixgbe_set_rss_queues(adapter); | |
e5b64635 | 4080 | } |
03ecf91a | 4081 | |
e901acd6 JF |
4082 | /* adding FCoE rx rings to the end */ |
4083 | f->mask = adapter->num_rx_queues; | |
4084 | adapter->num_rx_queues += f->indices; | |
4085 | adapter->num_tx_queues += f->indices; | |
0331a832 | 4086 | |
e5b64635 JF |
4087 | return true; |
4088 | } | |
4089 | #endif /* IXGBE_FCOE */ | |
4090 | ||
e901acd6 JF |
4091 | /* Artificial max queue cap per traffic class in DCB mode */ |
4092 | #define DCB_QUEUE_CAP 8 | |
4093 | ||
e5b64635 JF |
4094 | #ifdef CONFIG_IXGBE_DCB |
4095 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
4096 | { | |
e901acd6 JF |
4097 | int per_tc_q, q, i, offset = 0; |
4098 | struct net_device *dev = adapter->netdev; | |
4099 | int tcs = netdev_get_num_tc(dev); | |
e5b64635 | 4100 | |
e901acd6 JF |
4101 | if (!tcs) |
4102 | return false; | |
e5b64635 | 4103 | |
e901acd6 JF |
4104 | /* Map queue offset and counts onto allocated tx queues */ |
4105 | per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP); | |
4106 | q = min((int)num_online_cpus(), per_tc_q); | |
8b1c0b24 | 4107 | |
8b1c0b24 | 4108 | for (i = 0; i < tcs; i++) { |
e901acd6 JF |
4109 | netdev_set_prio_tc_map(dev, i, i); |
4110 | netdev_set_tc_queue(dev, i, q, offset); | |
4111 | offset += q; | |
0331a832 YZ |
4112 | } |
4113 | ||
e901acd6 JF |
4114 | adapter->num_tx_queues = q * tcs; |
4115 | adapter->num_rx_queues = q * tcs; | |
e5b64635 JF |
4116 | |
4117 | #ifdef IXGBE_FCOE | |
e901acd6 JF |
4118 | /* FCoE enabled queues require special configuration indexed |
4119 | * by feature specific indices and mask. Here we map FCoE | |
4120 | * indices onto the DCB queue pairs allowing FCoE to own | |
4121 | * configuration later. | |
e5b64635 | 4122 | */ |
e901acd6 JF |
4123 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
4124 | int tc; | |
4125 | struct ixgbe_ring_feature *f = | |
4126 | &adapter->ring_feature[RING_F_FCOE]; | |
4127 | ||
4128 | tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up); | |
4129 | f->indices = dev->tc_to_txq[tc].count; | |
4130 | f->mask = dev->tc_to_txq[tc].offset; | |
4131 | } | |
e5b64635 JF |
4132 | #endif |
4133 | ||
e901acd6 | 4134 | return true; |
0331a832 | 4135 | } |
e5b64635 | 4136 | #endif |
0331a832 | 4137 | |
1cdd1ec8 GR |
4138 | /** |
4139 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
4140 | * @adapter: board private structure to initialize | |
4141 | * | |
4142 | * IOV doesn't actually use anything, so just NAK the | |
4143 | * request for now and let the other queue routines | |
4144 | * figure out what to do. | |
4145 | */ | |
4146 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
4147 | { | |
4148 | return false; | |
4149 | } | |
4150 | ||
4df10466 | 4151 | /* |
25985edc | 4152 | * ixgbe_set_num_queues: Allocate queues for device, feature dependent |
4df10466 JB |
4153 | * @adapter: board private structure to initialize |
4154 | * | |
4155 | * This is the top level queue allocation routine. The order here is very | |
4156 | * important, starting with the "most" number of features turned on at once, | |
4157 | * and ending with the smallest set of features. This way large combinations | |
4158 | * can be allocated if they're turned on, and smaller combinations are the | |
4159 | * fallthrough conditions. | |
4160 | * | |
4161 | **/ | |
847f53ff | 4162 | static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
bc97114d | 4163 | { |
1cdd1ec8 GR |
4164 | /* Start with base case */ |
4165 | adapter->num_rx_queues = 1; | |
4166 | adapter->num_tx_queues = 1; | |
4167 | adapter->num_rx_pools = adapter->num_rx_queues; | |
4168 | adapter->num_rx_queues_per_pool = 1; | |
4169 | ||
4170 | if (ixgbe_set_sriov_queues(adapter)) | |
847f53ff | 4171 | goto done; |
1cdd1ec8 | 4172 | |
bc97114d PWJ |
4173 | #ifdef CONFIG_IXGBE_DCB |
4174 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 4175 | goto done; |
bc97114d PWJ |
4176 | |
4177 | #endif | |
e5b64635 JF |
4178 | #ifdef IXGBE_FCOE |
4179 | if (ixgbe_set_fcoe_queues(adapter)) | |
4180 | goto done; | |
4181 | ||
4182 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
4183 | if (ixgbe_set_fdir_queues(adapter)) |
4184 | goto done; | |
4185 | ||
bc97114d | 4186 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
4187 | goto done; |
4188 | ||
4189 | /* fallback to base case */ | |
4190 | adapter->num_rx_queues = 1; | |
4191 | adapter->num_tx_queues = 1; | |
4192 | ||
4193 | done: | |
847f53ff | 4194 | /* Notify the stack of the (possibly) reduced queue counts. */ |
f0796d5c | 4195 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); |
847f53ff BH |
4196 | return netif_set_real_num_rx_queues(adapter->netdev, |
4197 | adapter->num_rx_queues); | |
b9804972 JB |
4198 | } |
4199 | ||
021230d4 | 4200 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
e8e9f696 | 4201 | int vectors) |
021230d4 AV |
4202 | { |
4203 | int err, vector_threshold; | |
4204 | ||
4205 | /* We'll want at least 3 (vector_threshold): | |
4206 | * 1) TxQ[0] Cleanup | |
4207 | * 2) RxQ[0] Cleanup | |
4208 | * 3) Other (Link Status Change, etc.) | |
4209 | * 4) TCP Timer (optional) | |
4210 | */ | |
4211 | vector_threshold = MIN_MSIX_COUNT; | |
4212 | ||
4213 | /* The more we get, the more we will assign to Tx/Rx Cleanup | |
4214 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. | |
4215 | * Right now, we simply care about how many we'll get; we'll | |
4216 | * set them up later while requesting irq's. | |
4217 | */ | |
4218 | while (vectors >= vector_threshold) { | |
4219 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
e8e9f696 | 4220 | vectors); |
021230d4 AV |
4221 | if (!err) /* Success in acquiring all requested vectors. */ |
4222 | break; | |
4223 | else if (err < 0) | |
4224 | vectors = 0; /* Nasty failure, quit now */ | |
4225 | else /* err == number of vectors we should try again with */ | |
4226 | vectors = err; | |
4227 | } | |
4228 | ||
4229 | if (vectors < vector_threshold) { | |
4230 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
4231 | * This just means we'll go with either a single MSI | |
4232 | * vector or fall back to legacy interrupts. | |
4233 | */ | |
849c4542 ET |
4234 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4235 | "Unable to allocate MSI-X interrupts\n"); | |
021230d4 AV |
4236 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
4237 | kfree(adapter->msix_entries); | |
4238 | adapter->msix_entries = NULL; | |
021230d4 AV |
4239 | } else { |
4240 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
4241 | /* |
4242 | * Adjust for only the vectors we'll use, which is minimum | |
4243 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
4244 | * vectors we were allocated. | |
4245 | */ | |
4246 | adapter->num_msix_vectors = min(vectors, | |
e8e9f696 | 4247 | adapter->max_msix_q_vectors + NON_Q_VECTORS); |
021230d4 AV |
4248 | } |
4249 | } | |
4250 | ||
021230d4 | 4251 | /** |
bc97114d | 4252 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
4253 | * @adapter: board private structure to initialize |
4254 | * | |
bc97114d PWJ |
4255 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
4256 | * | |
021230d4 | 4257 | **/ |
bc97114d | 4258 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 4259 | { |
bc97114d | 4260 | int i; |
bc97114d | 4261 | |
9d6b758f AD |
4262 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) |
4263 | return false; | |
bc97114d | 4264 | |
9d6b758f AD |
4265 | for (i = 0; i < adapter->num_rx_queues; i++) |
4266 | adapter->rx_ring[i]->reg_idx = i; | |
4267 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4268 | adapter->tx_ring[i]->reg_idx = i; | |
4269 | ||
4270 | return true; | |
bc97114d PWJ |
4271 | } |
4272 | ||
4273 | #ifdef CONFIG_IXGBE_DCB | |
e5b64635 JF |
4274 | |
4275 | /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ | |
b32c8dcc JF |
4276 | static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, |
4277 | unsigned int *tx, unsigned int *rx) | |
e5b64635 JF |
4278 | { |
4279 | struct net_device *dev = adapter->netdev; | |
4280 | struct ixgbe_hw *hw = &adapter->hw; | |
4281 | u8 num_tcs = netdev_get_num_tc(dev); | |
4282 | ||
4283 | *tx = 0; | |
4284 | *rx = 0; | |
4285 | ||
4286 | switch (hw->mac.type) { | |
4287 | case ixgbe_mac_82598EB: | |
aba70d5e JF |
4288 | *tx = tc << 2; |
4289 | *rx = tc << 3; | |
e5b64635 JF |
4290 | break; |
4291 | case ixgbe_mac_82599EB: | |
4292 | case ixgbe_mac_X540: | |
4fa2e0e1 | 4293 | if (num_tcs > 4) { |
e5b64635 JF |
4294 | if (tc < 3) { |
4295 | *tx = tc << 5; | |
4296 | *rx = tc << 4; | |
4297 | } else if (tc < 5) { | |
4298 | *tx = ((tc + 2) << 4); | |
4299 | *rx = tc << 4; | |
4300 | } else if (tc < num_tcs) { | |
4301 | *tx = ((tc + 8) << 3); | |
4302 | *rx = tc << 4; | |
4303 | } | |
4fa2e0e1 | 4304 | } else { |
e5b64635 JF |
4305 | *rx = tc << 5; |
4306 | switch (tc) { | |
4307 | case 0: | |
4308 | *tx = 0; | |
4309 | break; | |
4310 | case 1: | |
4311 | *tx = 64; | |
4312 | break; | |
4313 | case 2: | |
4314 | *tx = 96; | |
4315 | break; | |
4316 | case 3: | |
4317 | *tx = 112; | |
4318 | break; | |
4319 | default: | |
4320 | break; | |
4321 | } | |
4322 | } | |
4323 | break; | |
4324 | default: | |
4325 | break; | |
4326 | } | |
4327 | } | |
4328 | ||
bc97114d PWJ |
4329 | /** |
4330 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
4331 | * @adapter: board private structure to initialize | |
4332 | * | |
4333 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
4334 | * | |
4335 | **/ | |
4336 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
4337 | { | |
e5b64635 JF |
4338 | struct net_device *dev = adapter->netdev; |
4339 | int i, j, k; | |
4340 | u8 num_tcs = netdev_get_num_tc(dev); | |
bc97114d | 4341 | |
8b1c0b24 | 4342 | if (!num_tcs) |
bd508178 | 4343 | return false; |
f92ef202 | 4344 | |
e5b64635 JF |
4345 | for (i = 0, k = 0; i < num_tcs; i++) { |
4346 | unsigned int tx_s, rx_s; | |
4347 | u16 count = dev->tc_to_txq[i].count; | |
4348 | ||
4349 | ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); | |
4350 | for (j = 0; j < count; j++, k++) { | |
4351 | adapter->tx_ring[k]->reg_idx = tx_s + j; | |
4352 | adapter->rx_ring[k]->reg_idx = rx_s + j; | |
4353 | adapter->tx_ring[k]->dcb_tc = i; | |
4354 | adapter->rx_ring[k]->dcb_tc = i; | |
021230d4 | 4355 | } |
021230d4 | 4356 | } |
e5b64635 JF |
4357 | |
4358 | return true; | |
bc97114d PWJ |
4359 | } |
4360 | #endif | |
4361 | ||
c4cf55e5 PWJ |
4362 | /** |
4363 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
4364 | * @adapter: board private structure to initialize | |
4365 | * | |
4366 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
4367 | * | |
4368 | **/ | |
e8e9f696 | 4369 | static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4370 | { |
4371 | int i; | |
4372 | bool ret = false; | |
4373 | ||
03ecf91a AD |
4374 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && |
4375 | (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) { | |
c4cf55e5 | 4376 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 4377 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 4378 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4379 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
4380 | ret = true; |
4381 | } | |
4382 | ||
4383 | return ret; | |
4384 | } | |
4385 | ||
0331a832 YZ |
4386 | #ifdef IXGBE_FCOE |
4387 | /** | |
4388 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
4389 | * @adapter: board private structure to initialize | |
4390 | * | |
4391 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
4392 | * | |
4393 | */ | |
4394 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
4395 | { | |
0331a832 | 4396 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
bf29ee6c AD |
4397 | int i; |
4398 | u8 fcoe_rx_i = 0, fcoe_tx_i = 0; | |
4399 | ||
4400 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
4401 | return false; | |
0331a832 | 4402 | |
bf29ee6c | 4403 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
03ecf91a | 4404 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
bf29ee6c AD |
4405 | ixgbe_cache_ring_fdir(adapter); |
4406 | else | |
4407 | ixgbe_cache_ring_rss(adapter); | |
8faa2a78 | 4408 | |
bf29ee6c AD |
4409 | fcoe_rx_i = f->mask; |
4410 | fcoe_tx_i = f->mask; | |
0331a832 | 4411 | } |
bf29ee6c AD |
4412 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { |
4413 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; | |
4414 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
4415 | } | |
4416 | return true; | |
0331a832 YZ |
4417 | } |
4418 | ||
4419 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4420 | /** |
4421 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
4422 | * @adapter: board private structure to initialize | |
4423 | * | |
4424 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
4425 | * no other mapping is used. | |
4426 | * | |
4427 | */ | |
4428 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
4429 | { | |
4a0b9ca0 PW |
4430 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
4431 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
4432 | if (adapter->num_vfs) |
4433 | return true; | |
4434 | else | |
4435 | return false; | |
4436 | } | |
4437 | ||
bc97114d PWJ |
4438 | /** |
4439 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
4440 | * @adapter: board private structure to initialize | |
4441 | * | |
4442 | * Once we know the feature-set enabled for the device, we'll cache | |
4443 | * the register offset the descriptor ring is assigned to. | |
4444 | * | |
4445 | * Note, the order the various feature calls is important. It must start with | |
4446 | * the "most" features enabled at the same time, then trickle down to the | |
4447 | * least amount of features turned on at once. | |
4448 | **/ | |
4449 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
4450 | { | |
4451 | /* start with default case */ | |
4a0b9ca0 PW |
4452 | adapter->rx_ring[0]->reg_idx = 0; |
4453 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 4454 | |
1cdd1ec8 GR |
4455 | if (ixgbe_cache_ring_sriov(adapter)) |
4456 | return; | |
4457 | ||
e5b64635 JF |
4458 | #ifdef CONFIG_IXGBE_DCB |
4459 | if (ixgbe_cache_ring_dcb(adapter)) | |
4460 | return; | |
4461 | #endif | |
4462 | ||
0331a832 YZ |
4463 | #ifdef IXGBE_FCOE |
4464 | if (ixgbe_cache_ring_fcoe(adapter)) | |
4465 | return; | |
0331a832 | 4466 | #endif /* IXGBE_FCOE */ |
bc97114d | 4467 | |
c4cf55e5 PWJ |
4468 | if (ixgbe_cache_ring_fdir(adapter)) |
4469 | return; | |
4470 | ||
bc97114d PWJ |
4471 | if (ixgbe_cache_ring_rss(adapter)) |
4472 | return; | |
021230d4 AV |
4473 | } |
4474 | ||
9a799d71 AK |
4475 | /** |
4476 | * ixgbe_alloc_queues - Allocate memory for all rings | |
4477 | * @adapter: board private structure to initialize | |
4478 | * | |
4479 | * We allocate one ring per queue at run-time since we don't know the | |
4df10466 JB |
4480 | * number of queues at compile-time. The polling_netdev array is |
4481 | * intended for Multiqueue, but should work fine with a single queue. | |
9a799d71 | 4482 | **/ |
2f90b865 | 4483 | static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter) |
9a799d71 | 4484 | { |
e2ddeba9 | 4485 | int rx = 0, tx = 0, nid = adapter->node; |
9a799d71 | 4486 | |
e2ddeba9 ED |
4487 | if (nid < 0 || !node_online(nid)) |
4488 | nid = first_online_node; | |
4489 | ||
4490 | for (; tx < adapter->num_tx_queues; tx++) { | |
4491 | struct ixgbe_ring *ring; | |
4492 | ||
4493 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid); | |
4a0b9ca0 | 4494 | if (!ring) |
e2ddeba9 | 4495 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
4a0b9ca0 | 4496 | if (!ring) |
e2ddeba9 | 4497 | goto err_allocation; |
4a0b9ca0 | 4498 | ring->count = adapter->tx_ring_count; |
e2ddeba9 ED |
4499 | ring->queue_index = tx; |
4500 | ring->numa_node = nid; | |
b6ec895e | 4501 | ring->dev = &adapter->pdev->dev; |
fc77dc3c | 4502 | ring->netdev = adapter->netdev; |
4a0b9ca0 | 4503 | |
e2ddeba9 | 4504 | adapter->tx_ring[tx] = ring; |
021230d4 | 4505 | } |
b9804972 | 4506 | |
e2ddeba9 ED |
4507 | for (; rx < adapter->num_rx_queues; rx++) { |
4508 | struct ixgbe_ring *ring; | |
4a0b9ca0 | 4509 | |
e2ddeba9 | 4510 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid); |
4a0b9ca0 | 4511 | if (!ring) |
e2ddeba9 | 4512 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
4a0b9ca0 | 4513 | if (!ring) |
e2ddeba9 ED |
4514 | goto err_allocation; |
4515 | ring->count = adapter->rx_ring_count; | |
4516 | ring->queue_index = rx; | |
4517 | ring->numa_node = nid; | |
b6ec895e | 4518 | ring->dev = &adapter->pdev->dev; |
fc77dc3c | 4519 | ring->netdev = adapter->netdev; |
4a0b9ca0 | 4520 | |
e2ddeba9 | 4521 | adapter->rx_ring[rx] = ring; |
021230d4 AV |
4522 | } |
4523 | ||
4524 | ixgbe_cache_ring_register(adapter); | |
4525 | ||
4526 | return 0; | |
4527 | ||
e2ddeba9 ED |
4528 | err_allocation: |
4529 | while (tx) | |
4530 | kfree(adapter->tx_ring[--tx]); | |
4531 | ||
4532 | while (rx) | |
4533 | kfree(adapter->rx_ring[--rx]); | |
021230d4 AV |
4534 | return -ENOMEM; |
4535 | } | |
4536 | ||
4537 | /** | |
4538 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
4539 | * @adapter: board private structure to initialize | |
4540 | * | |
4541 | * Attempt to configure the interrupts using the best available | |
4542 | * capabilities of the hardware and the kernel. | |
4543 | **/ | |
feea6a57 | 4544 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 4545 | { |
8be0e467 | 4546 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
4547 | int err = 0; |
4548 | int vector, v_budget; | |
4549 | ||
4550 | /* | |
4551 | * It's easy to be greedy for MSI-X vectors, but it really | |
4552 | * doesn't do us much good if we have a lot more vectors | |
4553 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 4554 | * (roughly) the same number of vectors as there are CPU's. |
021230d4 AV |
4555 | */ |
4556 | v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues, | |
e8e9f696 | 4557 | (int)num_online_cpus()) + NON_Q_VECTORS; |
021230d4 AV |
4558 | |
4559 | /* | |
4560 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
4561 | * hw.mac->max_msix_vectors vectors. With features |
4562 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
4563 | * descriptor queues supported by our device. Thus, we cap it off in | |
4564 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 4565 | */ |
8be0e467 | 4566 | v_budget = min(v_budget, (int)hw->mac.max_msix_vectors); |
021230d4 AV |
4567 | |
4568 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
4569 | * mean we disable MSI-X capabilities of the adapter. */ | |
4570 | adapter->msix_entries = kcalloc(v_budget, | |
e8e9f696 | 4571 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
4572 | if (adapter->msix_entries) { |
4573 | for (vector = 0; vector < v_budget; vector++) | |
4574 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 4575 | |
7a921c93 | 4576 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 4577 | |
7a921c93 AD |
4578 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4579 | goto out; | |
4580 | } | |
26d27844 | 4581 | |
7a921c93 AD |
4582 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
4583 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
03ecf91a | 4584 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
45b9f509 | 4585 | e_err(probe, |
03ecf91a | 4586 | "ATR is not supported while multiple " |
45b9f509 AD |
4587 | "queues are disabled. Disabling Flow Director\n"); |
4588 | } | |
c4cf55e5 | 4589 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
c4cf55e5 | 4590 | adapter->atr_sample_rate = 0; |
1cdd1ec8 GR |
4591 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
4592 | ixgbe_disable_sriov(adapter); | |
4593 | ||
847f53ff BH |
4594 | err = ixgbe_set_num_queues(adapter); |
4595 | if (err) | |
4596 | return err; | |
021230d4 | 4597 | |
021230d4 AV |
4598 | err = pci_enable_msi(adapter->pdev); |
4599 | if (!err) { | |
4600 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
4601 | } else { | |
849c4542 ET |
4602 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4603 | "Unable to allocate MSI interrupt, " | |
4604 | "falling back to legacy. Error: %d\n", err); | |
021230d4 AV |
4605 | /* reset err */ |
4606 | err = 0; | |
4607 | } | |
4608 | ||
4609 | out: | |
021230d4 AV |
4610 | return err; |
4611 | } | |
4612 | ||
7a921c93 AD |
4613 | /** |
4614 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
4615 | * @adapter: board private structure to initialize | |
4616 | * | |
4617 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
4618 | * return -ENOMEM. | |
4619 | **/ | |
4620 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
4621 | { | |
4ff7fb12 | 4622 | int v_idx, num_q_vectors; |
7a921c93 | 4623 | struct ixgbe_q_vector *q_vector; |
7a921c93 | 4624 | |
4ff7fb12 | 4625 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 4626 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
4ff7fb12 | 4627 | else |
7a921c93 | 4628 | num_q_vectors = 1; |
7a921c93 | 4629 | |
4ff7fb12 | 4630 | for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { |
1a6c14a2 | 4631 | q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector), |
e8e9f696 | 4632 | GFP_KERNEL, adapter->node); |
1a6c14a2 JB |
4633 | if (!q_vector) |
4634 | q_vector = kzalloc(sizeof(struct ixgbe_q_vector), | |
e8e9f696 | 4635 | GFP_KERNEL); |
7a921c93 AD |
4636 | if (!q_vector) |
4637 | goto err_out; | |
4ff7fb12 | 4638 | |
7a921c93 | 4639 | q_vector->adapter = adapter; |
4ff7fb12 AD |
4640 | q_vector->v_idx = v_idx; |
4641 | ||
207867f5 AD |
4642 | /* Allocate the affinity_hint cpumask, configure the mask */ |
4643 | if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL)) | |
4644 | goto err_out; | |
4645 | cpumask_set_cpu(v_idx, q_vector->affinity_mask); | |
4646 | ||
08c8833b | 4647 | if (q_vector->tx.count && !q_vector->rx.count) |
f7554a2b NS |
4648 | q_vector->eitr = adapter->tx_eitr_param; |
4649 | else | |
4650 | q_vector->eitr = adapter->rx_eitr_param; | |
4ff7fb12 AD |
4651 | |
4652 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
4653 | ixgbe_poll, 64); | |
4654 | adapter->q_vector[v_idx] = q_vector; | |
7a921c93 AD |
4655 | } |
4656 | ||
4657 | return 0; | |
4658 | ||
4659 | err_out: | |
4ff7fb12 AD |
4660 | while (v_idx) { |
4661 | v_idx--; | |
4662 | q_vector = adapter->q_vector[v_idx]; | |
7a921c93 | 4663 | netif_napi_del(&q_vector->napi); |
207867f5 | 4664 | free_cpumask_var(q_vector->affinity_mask); |
7a921c93 | 4665 | kfree(q_vector); |
4ff7fb12 | 4666 | adapter->q_vector[v_idx] = NULL; |
7a921c93 AD |
4667 | } |
4668 | return -ENOMEM; | |
4669 | } | |
4670 | ||
4671 | /** | |
4672 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
4673 | * @adapter: board private structure to initialize | |
4674 | * | |
4675 | * This function frees the memory allocated to the q_vectors. In addition if | |
4676 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4677 | * to freeing the q_vector. | |
4678 | **/ | |
4679 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
4680 | { | |
207867f5 | 4681 | int v_idx, num_q_vectors; |
7a921c93 | 4682 | |
91281fd3 | 4683 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
7a921c93 | 4684 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 4685 | else |
7a921c93 | 4686 | num_q_vectors = 1; |
7a921c93 | 4687 | |
207867f5 AD |
4688 | for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { |
4689 | struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; | |
4690 | adapter->q_vector[v_idx] = NULL; | |
91281fd3 | 4691 | netif_napi_del(&q_vector->napi); |
207867f5 | 4692 | free_cpumask_var(q_vector->affinity_mask); |
7a921c93 AD |
4693 | kfree(q_vector); |
4694 | } | |
4695 | } | |
4696 | ||
7b25cdba | 4697 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
4698 | { |
4699 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
4700 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
4701 | pci_disable_msix(adapter->pdev); | |
4702 | kfree(adapter->msix_entries); | |
4703 | adapter->msix_entries = NULL; | |
4704 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
4705 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
4706 | pci_disable_msi(adapter->pdev); | |
4707 | } | |
021230d4 AV |
4708 | } |
4709 | ||
4710 | /** | |
4711 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
4712 | * @adapter: board private structure to initialize | |
4713 | * | |
4714 | * We determine which interrupt scheme to use based on... | |
4715 | * - Kernel support (MSI, MSI-X) | |
4716 | * - which can be user-defined (via MODULE_PARAM) | |
4717 | * - Hardware queue count (num_*_queues) | |
4718 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
4719 | **/ | |
2f90b865 | 4720 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
4721 | { |
4722 | int err; | |
4723 | ||
4724 | /* Number of supported queues */ | |
847f53ff BH |
4725 | err = ixgbe_set_num_queues(adapter); |
4726 | if (err) | |
4727 | return err; | |
021230d4 | 4728 | |
021230d4 AV |
4729 | err = ixgbe_set_interrupt_capability(adapter); |
4730 | if (err) { | |
849c4542 | 4731 | e_dev_err("Unable to setup interrupt capabilities\n"); |
021230d4 | 4732 | goto err_set_interrupt; |
9a799d71 AK |
4733 | } |
4734 | ||
7a921c93 AD |
4735 | err = ixgbe_alloc_q_vectors(adapter); |
4736 | if (err) { | |
849c4542 | 4737 | e_dev_err("Unable to allocate memory for queue vectors\n"); |
7a921c93 AD |
4738 | goto err_alloc_q_vectors; |
4739 | } | |
4740 | ||
4741 | err = ixgbe_alloc_queues(adapter); | |
4742 | if (err) { | |
849c4542 | 4743 | e_dev_err("Unable to allocate memory for queues\n"); |
7a921c93 AD |
4744 | goto err_alloc_queues; |
4745 | } | |
4746 | ||
849c4542 | 4747 | e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", |
396e799c ET |
4748 | (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", |
4749 | adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
4750 | |
4751 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4752 | ||
9a799d71 | 4753 | return 0; |
021230d4 | 4754 | |
7a921c93 AD |
4755 | err_alloc_queues: |
4756 | ixgbe_free_q_vectors(adapter); | |
4757 | err_alloc_q_vectors: | |
4758 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 4759 | err_set_interrupt: |
7a921c93 AD |
4760 | return err; |
4761 | } | |
4762 | ||
4763 | /** | |
4764 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4765 | * @adapter: board private structure to clear interrupt scheme on | |
4766 | * | |
4767 | * We go through and clear interrupt specific resources and reset the structure | |
4768 | * to pre-load conditions | |
4769 | **/ | |
4770 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
4771 | { | |
4a0b9ca0 PW |
4772 | int i; |
4773 | ||
4774 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
4775 | kfree(adapter->tx_ring[i]); | |
4776 | adapter->tx_ring[i] = NULL; | |
4777 | } | |
4778 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
1a51502b ED |
4779 | struct ixgbe_ring *ring = adapter->rx_ring[i]; |
4780 | ||
4781 | /* ixgbe_get_stats64() might access this ring, we must wait | |
4782 | * a grace period before freeing it. | |
4783 | */ | |
bcec8b65 | 4784 | kfree_rcu(ring, rcu); |
4a0b9ca0 PW |
4785 | adapter->rx_ring[i] = NULL; |
4786 | } | |
7a921c93 | 4787 | |
b8eb3a10 DS |
4788 | adapter->num_tx_queues = 0; |
4789 | adapter->num_rx_queues = 0; | |
4790 | ||
7a921c93 AD |
4791 | ixgbe_free_q_vectors(adapter); |
4792 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
4793 | } |
4794 | ||
4795 | /** | |
4796 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4797 | * @adapter: board private structure to initialize | |
4798 | * | |
4799 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4800 | * Fields are initialized based on PCI device information and | |
4801 | * OS network device settings (MTU size). | |
4802 | **/ | |
4803 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4804 | { | |
4805 | struct ixgbe_hw *hw = &adapter->hw; | |
4806 | struct pci_dev *pdev = adapter->pdev; | |
9a713e7c | 4807 | struct net_device *dev = adapter->netdev; |
021230d4 | 4808 | unsigned int rss; |
7a6b6f51 | 4809 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4810 | int j; |
4811 | struct tc_configuration *tc; | |
4812 | #endif | |
16b61beb | 4813 | int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN; |
021230d4 | 4814 | |
c44ade9e JB |
4815 | /* PCI config space info */ |
4816 | ||
4817 | hw->vendor_id = pdev->vendor; | |
4818 | hw->device_id = pdev->device; | |
4819 | hw->revision_id = pdev->revision; | |
4820 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4821 | hw->subsystem_device_id = pdev->subsystem_device; | |
4822 | ||
021230d4 AV |
4823 | /* Set capability flags */ |
4824 | rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus()); | |
4825 | adapter->ring_feature[RING_F_RSS].indices = rss; | |
4826 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
bd508178 AD |
4827 | switch (hw->mac.type) { |
4828 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
4829 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
4830 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 4831 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bd508178 AD |
4832 | break; |
4833 | case ixgbe_mac_82599EB: | |
b93a2226 | 4834 | case ixgbe_mac_X540: |
e8e26350 | 4835 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
4836 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4837 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4838 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4839 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
4840 | /* Flow Director hash filters enabled */ |
4841 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4842 | adapter->atr_sample_rate = 20; | |
c4cf55e5 | 4843 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 4844 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 4845 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 4846 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4847 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4848 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
4849 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 4850 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 4851 | /* Default traffic class to use for FCoE */ |
56075a98 | 4852 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 4853 | #endif |
eacd73f7 | 4854 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
4855 | break; |
4856 | default: | |
4857 | break; | |
f8212f97 | 4858 | } |
2f90b865 | 4859 | |
1fc5f038 AD |
4860 | /* n-tuple support exists, always init our spinlock */ |
4861 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4862 | ||
7a6b6f51 | 4863 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4864 | /* Configure DCB traffic classes */ |
4865 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4866 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4867 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4868 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4869 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4870 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4871 | tc->dcb_pfc = pfc_disabled; | |
4872 | } | |
4873 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; | |
4874 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 4875 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 4876 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 4877 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
2f90b865 | 4878 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, |
e5b64635 | 4879 | MAX_TRAFFIC_CLASS); |
2f90b865 AD |
4880 | |
4881 | #endif | |
9a799d71 AK |
4882 | |
4883 | /* default flow control settings */ | |
cd7664f6 | 4884 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4885 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
4886 | #ifdef CONFIG_DCB |
4887 | adapter->last_lfc_mode = hw->fc.current_mode; | |
4888 | #endif | |
16b61beb JF |
4889 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
4890 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
2b9ade93 JB |
4891 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
4892 | hw->fc.send_xon = true; | |
71fd570b | 4893 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4894 | |
30efa5a3 | 4895 | /* enable itr by default in dynamic mode */ |
f7554a2b NS |
4896 | adapter->rx_itr_setting = 1; |
4897 | adapter->rx_eitr_param = 20000; | |
4898 | adapter->tx_itr_setting = 1; | |
4899 | adapter->tx_eitr_param = 10000; | |
30efa5a3 JB |
4900 | |
4901 | /* set defaults for eitr in MegaBytes */ | |
4902 | adapter->eitr_low = 10; | |
4903 | adapter->eitr_high = 20; | |
4904 | ||
4905 | /* set default ring sizes */ | |
4906 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4907 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4908 | ||
bd198058 | 4909 | /* set default work limits */ |
59224555 | 4910 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 4911 | |
9a799d71 | 4912 | /* initialize eeprom parameters */ |
c44ade9e | 4913 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 4914 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
4915 | return -EIO; |
4916 | } | |
4917 | ||
021230d4 | 4918 | /* enable rx csum by default */ |
9a799d71 AK |
4919 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; |
4920 | ||
1a6c14a2 JB |
4921 | /* get assigned NUMA node */ |
4922 | adapter->node = dev_to_node(&pdev->dev); | |
4923 | ||
9a799d71 AK |
4924 | set_bit(__IXGBE_DOWN, &adapter->state); |
4925 | ||
4926 | return 0; | |
4927 | } | |
4928 | ||
4929 | /** | |
4930 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 4931 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4932 | * |
4933 | * Return 0 on success, negative on failure | |
4934 | **/ | |
b6ec895e | 4935 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4936 | { |
b6ec895e | 4937 | struct device *dev = tx_ring->dev; |
9a799d71 AK |
4938 | int size; |
4939 | ||
3a581073 | 4940 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
89bf67f1 | 4941 | tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node); |
1a6c14a2 | 4942 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 4943 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
4944 | if (!tx_ring->tx_buffer_info) |
4945 | goto err; | |
9a799d71 AK |
4946 | |
4947 | /* round up to nearest 4K */ | |
12207e49 | 4948 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4949 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4950 | |
b6ec895e | 4951 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, |
1b507730 | 4952 | &tx_ring->dma, GFP_KERNEL); |
e01c31a5 JB |
4953 | if (!tx_ring->desc) |
4954 | goto err; | |
9a799d71 | 4955 | |
3a581073 JB |
4956 | tx_ring->next_to_use = 0; |
4957 | tx_ring->next_to_clean = 0; | |
9a799d71 | 4958 | return 0; |
e01c31a5 JB |
4959 | |
4960 | err: | |
4961 | vfree(tx_ring->tx_buffer_info); | |
4962 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 4963 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 4964 | return -ENOMEM; |
9a799d71 AK |
4965 | } |
4966 | ||
69888674 AD |
4967 | /** |
4968 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4969 | * @adapter: board private structure | |
4970 | * | |
4971 | * If this function returns with an error, then it's possible one or | |
4972 | * more of the rings is populated (while the rest are not). It is the | |
4973 | * callers duty to clean those orphaned rings. | |
4974 | * | |
4975 | * Return 0 on success, negative on failure | |
4976 | **/ | |
4977 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4978 | { | |
4979 | int i, err = 0; | |
4980 | ||
4981 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 4982 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
4983 | if (!err) |
4984 | continue; | |
396e799c | 4985 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
4986 | break; |
4987 | } | |
4988 | ||
4989 | return err; | |
4990 | } | |
4991 | ||
9a799d71 AK |
4992 | /** |
4993 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 4994 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4995 | * |
4996 | * Returns 0 on success, negative on failure | |
4997 | **/ | |
b6ec895e | 4998 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4999 | { |
b6ec895e | 5000 | struct device *dev = rx_ring->dev; |
021230d4 | 5001 | int size; |
9a799d71 | 5002 | |
3a581073 | 5003 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
89bf67f1 | 5004 | rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node); |
1a6c14a2 | 5005 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 5006 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
5007 | if (!rx_ring->rx_buffer_info) |
5008 | goto err; | |
9a799d71 | 5009 | |
9a799d71 | 5010 | /* Round up to nearest 4K */ |
3a581073 JB |
5011 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5012 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5013 | |
b6ec895e | 5014 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, |
1b507730 | 5015 | &rx_ring->dma, GFP_KERNEL); |
9a799d71 | 5016 | |
b6ec895e AD |
5017 | if (!rx_ring->desc) |
5018 | goto err; | |
9a799d71 | 5019 | |
3a581073 JB |
5020 | rx_ring->next_to_clean = 0; |
5021 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
5022 | |
5023 | return 0; | |
b6ec895e AD |
5024 | err: |
5025 | vfree(rx_ring->rx_buffer_info); | |
5026 | rx_ring->rx_buffer_info = NULL; | |
5027 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 5028 | return -ENOMEM; |
9a799d71 AK |
5029 | } |
5030 | ||
69888674 AD |
5031 | /** |
5032 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5033 | * @adapter: board private structure | |
5034 | * | |
5035 | * If this function returns with an error, then it's possible one or | |
5036 | * more of the rings is populated (while the rest are not). It is the | |
5037 | * callers duty to clean those orphaned rings. | |
5038 | * | |
5039 | * Return 0 on success, negative on failure | |
5040 | **/ | |
69888674 AD |
5041 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
5042 | { | |
5043 | int i, err = 0; | |
5044 | ||
5045 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 5046 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
5047 | if (!err) |
5048 | continue; | |
396e799c | 5049 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
5050 | break; |
5051 | } | |
5052 | ||
5053 | return err; | |
5054 | } | |
5055 | ||
9a799d71 AK |
5056 | /** |
5057 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
5058 | * @tx_ring: Tx descriptor ring for a specific queue |
5059 | * | |
5060 | * Free all transmit software resources | |
5061 | **/ | |
b6ec895e | 5062 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5063 | { |
b6ec895e | 5064 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
5065 | |
5066 | vfree(tx_ring->tx_buffer_info); | |
5067 | tx_ring->tx_buffer_info = NULL; | |
5068 | ||
b6ec895e AD |
5069 | /* if not set, then don't free */ |
5070 | if (!tx_ring->desc) | |
5071 | return; | |
5072 | ||
5073 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
5074 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
5075 | |
5076 | tx_ring->desc = NULL; | |
5077 | } | |
5078 | ||
5079 | /** | |
5080 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
5081 | * @adapter: board private structure | |
5082 | * | |
5083 | * Free all transmit software resources | |
5084 | **/ | |
5085 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
5086 | { | |
5087 | int i; | |
5088 | ||
5089 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5090 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 5091 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
5092 | } |
5093 | ||
5094 | /** | |
b4617240 | 5095 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
5096 | * @rx_ring: ring to clean the resources from |
5097 | * | |
5098 | * Free all receive software resources | |
5099 | **/ | |
b6ec895e | 5100 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5101 | { |
b6ec895e | 5102 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
5103 | |
5104 | vfree(rx_ring->rx_buffer_info); | |
5105 | rx_ring->rx_buffer_info = NULL; | |
5106 | ||
b6ec895e AD |
5107 | /* if not set, then don't free */ |
5108 | if (!rx_ring->desc) | |
5109 | return; | |
5110 | ||
5111 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
5112 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
5113 | |
5114 | rx_ring->desc = NULL; | |
5115 | } | |
5116 | ||
5117 | /** | |
5118 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5119 | * @adapter: board private structure | |
5120 | * | |
5121 | * Free all receive software resources | |
5122 | **/ | |
5123 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5124 | { | |
5125 | int i; | |
5126 | ||
5127 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 5128 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 5129 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
5130 | } |
5131 | ||
9a799d71 AK |
5132 | /** |
5133 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5134 | * @netdev: network interface device structure | |
5135 | * @new_mtu: new value for maximum frame size | |
5136 | * | |
5137 | * Returns 0 on success, negative on failure | |
5138 | **/ | |
5139 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5140 | { | |
5141 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
16b61beb | 5142 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
5143 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
5144 | ||
42c783c5 | 5145 | /* MTU < 68 is an error and causes problems on some kernels */ |
e9f98072 GR |
5146 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED && |
5147 | hw->mac.type != ixgbe_mac_X540) { | |
5148 | if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
5149 | return -EINVAL; | |
5150 | } else { | |
5151 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) | |
5152 | return -EINVAL; | |
5153 | } | |
9a799d71 | 5154 | |
396e799c | 5155 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
021230d4 | 5156 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5157 | netdev->mtu = new_mtu; |
5158 | ||
16b61beb JF |
5159 | hw->fc.high_water = FC_HIGH_WATER(max_frame); |
5160 | hw->fc.low_water = FC_LOW_WATER(max_frame); | |
5161 | ||
d4f80882 AV |
5162 | if (netif_running(netdev)) |
5163 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5164 | |
5165 | return 0; | |
5166 | } | |
5167 | ||
5168 | /** | |
5169 | * ixgbe_open - Called when a network interface is made active | |
5170 | * @netdev: network interface device structure | |
5171 | * | |
5172 | * Returns 0 on success, negative value on failure | |
5173 | * | |
5174 | * The open entry point is called when a network interface is made | |
5175 | * active by the system (IFF_UP). At this point all resources needed | |
5176 | * for transmit and receive operations are allocated, the interrupt | |
5177 | * handler is registered with the OS, the watchdog timer is started, | |
5178 | * and the stack is notified that the interface is ready. | |
5179 | **/ | |
5180 | static int ixgbe_open(struct net_device *netdev) | |
5181 | { | |
5182 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5183 | int err; | |
4bebfaa5 AK |
5184 | |
5185 | /* disallow open during test */ | |
5186 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
5187 | return -EBUSY; | |
9a799d71 | 5188 | |
54386467 JB |
5189 | netif_carrier_off(netdev); |
5190 | ||
9a799d71 AK |
5191 | /* allocate transmit descriptors */ |
5192 | err = ixgbe_setup_all_tx_resources(adapter); | |
5193 | if (err) | |
5194 | goto err_setup_tx; | |
5195 | ||
9a799d71 AK |
5196 | /* allocate receive descriptors */ |
5197 | err = ixgbe_setup_all_rx_resources(adapter); | |
5198 | if (err) | |
5199 | goto err_setup_rx; | |
5200 | ||
5201 | ixgbe_configure(adapter); | |
5202 | ||
021230d4 | 5203 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
5204 | if (err) |
5205 | goto err_req_irq; | |
5206 | ||
c7ccde0f | 5207 | ixgbe_up_complete(adapter); |
9a799d71 AK |
5208 | |
5209 | return 0; | |
5210 | ||
9a799d71 | 5211 | err_req_irq: |
9a799d71 | 5212 | err_setup_rx: |
a20a1199 | 5213 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 5214 | err_setup_tx: |
a20a1199 | 5215 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
5216 | ixgbe_reset(adapter); |
5217 | ||
5218 | return err; | |
5219 | } | |
5220 | ||
5221 | /** | |
5222 | * ixgbe_close - Disables a network interface | |
5223 | * @netdev: network interface device structure | |
5224 | * | |
5225 | * Returns 0, this is not allowed to fail | |
5226 | * | |
5227 | * The close entry point is called when an interface is de-activated | |
5228 | * by the OS. The hardware is still under the drivers control, but | |
5229 | * needs to be disabled. A global MAC reset is issued to stop the | |
5230 | * hardware, and all transmit and receive resources are freed. | |
5231 | **/ | |
5232 | static int ixgbe_close(struct net_device *netdev) | |
5233 | { | |
5234 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
5235 | |
5236 | ixgbe_down(adapter); | |
5237 | ixgbe_free_irq(adapter); | |
5238 | ||
e4911d57 AD |
5239 | ixgbe_fdir_filter_exit(adapter); |
5240 | ||
9a799d71 AK |
5241 | ixgbe_free_all_tx_resources(adapter); |
5242 | ixgbe_free_all_rx_resources(adapter); | |
5243 | ||
5eba3699 | 5244 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5245 | |
5246 | return 0; | |
5247 | } | |
5248 | ||
b3c8b4ba AD |
5249 | #ifdef CONFIG_PM |
5250 | static int ixgbe_resume(struct pci_dev *pdev) | |
5251 | { | |
c60fbb00 AD |
5252 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5253 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
5254 | u32 err; |
5255 | ||
5256 | pci_set_power_state(pdev, PCI_D0); | |
5257 | pci_restore_state(pdev); | |
656ab817 DS |
5258 | /* |
5259 | * pci_restore_state clears dev->state_saved so call | |
5260 | * pci_save_state to restore it. | |
5261 | */ | |
5262 | pci_save_state(pdev); | |
9ce77666 | 5263 | |
5264 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 5265 | if (err) { |
849c4542 | 5266 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
5267 | return err; |
5268 | } | |
5269 | pci_set_master(pdev); | |
5270 | ||
dd4d8ca6 | 5271 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
5272 | |
5273 | err = ixgbe_init_interrupt_scheme(adapter); | |
5274 | if (err) { | |
849c4542 | 5275 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
5276 | return err; |
5277 | } | |
5278 | ||
b3c8b4ba AD |
5279 | ixgbe_reset(adapter); |
5280 | ||
495dce12 WJP |
5281 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5282 | ||
b3c8b4ba | 5283 | if (netif_running(netdev)) { |
c60fbb00 | 5284 | err = ixgbe_open(netdev); |
b3c8b4ba AD |
5285 | if (err) |
5286 | return err; | |
5287 | } | |
5288 | ||
5289 | netif_device_attach(netdev); | |
5290 | ||
5291 | return 0; | |
5292 | } | |
b3c8b4ba | 5293 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5294 | |
5295 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 5296 | { |
c60fbb00 AD |
5297 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5298 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
5299 | struct ixgbe_hw *hw = &adapter->hw; |
5300 | u32 ctrl, fctrl; | |
5301 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5302 | #ifdef CONFIG_PM |
5303 | int retval = 0; | |
5304 | #endif | |
5305 | ||
5306 | netif_device_detach(netdev); | |
5307 | ||
5308 | if (netif_running(netdev)) { | |
5309 | ixgbe_down(adapter); | |
5310 | ixgbe_free_irq(adapter); | |
5311 | ixgbe_free_all_tx_resources(adapter); | |
5312 | ixgbe_free_all_rx_resources(adapter); | |
5313 | } | |
b3c8b4ba | 5314 | |
5f5ae6fc | 5315 | ixgbe_clear_interrupt_scheme(adapter); |
d033d526 JF |
5316 | #ifdef CONFIG_DCB |
5317 | kfree(adapter->ixgbe_ieee_pfc); | |
5318 | kfree(adapter->ixgbe_ieee_ets); | |
5319 | #endif | |
5f5ae6fc | 5320 | |
b3c8b4ba AD |
5321 | #ifdef CONFIG_PM |
5322 | retval = pci_save_state(pdev); | |
5323 | if (retval) | |
5324 | return retval; | |
4df10466 | 5325 | |
b3c8b4ba | 5326 | #endif |
e8e26350 PW |
5327 | if (wufc) { |
5328 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5329 | |
e8e26350 PW |
5330 | /* turn on all-multi mode if wake on multicast is enabled */ |
5331 | if (wufc & IXGBE_WUFC_MC) { | |
5332 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5333 | fctrl |= IXGBE_FCTRL_MPE; | |
5334 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5335 | } | |
5336 | ||
5337 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5338 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5339 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5340 | ||
5341 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5342 | } else { | |
5343 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5344 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5345 | } | |
5346 | ||
bd508178 AD |
5347 | switch (hw->mac.type) { |
5348 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 5349 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
5350 | break; |
5351 | case ixgbe_mac_82599EB: | |
b93a2226 | 5352 | case ixgbe_mac_X540: |
bd508178 AD |
5353 | pci_wake_from_d3(pdev, !!wufc); |
5354 | break; | |
5355 | default: | |
5356 | break; | |
5357 | } | |
b3c8b4ba | 5358 | |
9d8d05ae RW |
5359 | *enable_wake = !!wufc; |
5360 | ||
b3c8b4ba AD |
5361 | ixgbe_release_hw_control(adapter); |
5362 | ||
5363 | pci_disable_device(pdev); | |
5364 | ||
9d8d05ae RW |
5365 | return 0; |
5366 | } | |
5367 | ||
5368 | #ifdef CONFIG_PM | |
5369 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5370 | { | |
5371 | int retval; | |
5372 | bool wake; | |
5373 | ||
5374 | retval = __ixgbe_shutdown(pdev, &wake); | |
5375 | if (retval) | |
5376 | return retval; | |
5377 | ||
5378 | if (wake) { | |
5379 | pci_prepare_to_sleep(pdev); | |
5380 | } else { | |
5381 | pci_wake_from_d3(pdev, false); | |
5382 | pci_set_power_state(pdev, PCI_D3hot); | |
5383 | } | |
b3c8b4ba AD |
5384 | |
5385 | return 0; | |
5386 | } | |
9d8d05ae | 5387 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5388 | |
5389 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5390 | { | |
9d8d05ae RW |
5391 | bool wake; |
5392 | ||
5393 | __ixgbe_shutdown(pdev, &wake); | |
5394 | ||
5395 | if (system_state == SYSTEM_POWER_OFF) { | |
5396 | pci_wake_from_d3(pdev, wake); | |
5397 | pci_set_power_state(pdev, PCI_D3hot); | |
5398 | } | |
b3c8b4ba AD |
5399 | } |
5400 | ||
9a799d71 AK |
5401 | /** |
5402 | * ixgbe_update_stats - Update the board statistics counters. | |
5403 | * @adapter: board private structure | |
5404 | **/ | |
5405 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5406 | { | |
2d86f139 | 5407 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5408 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5409 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5410 | u64 total_mpc = 0; |
5411 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5412 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5413 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
5414 | u64 bytes = 0, packets = 0; | |
9a799d71 | 5415 | |
d08935c2 DS |
5416 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5417 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5418 | return; | |
5419 | ||
94b982b2 | 5420 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5421 | u64 rsc_count = 0; |
94b982b2 | 5422 | u64 rsc_flush = 0; |
d51019a4 PW |
5423 | for (i = 0; i < 16; i++) |
5424 | adapter->hw_rx_no_dma_resources += | |
7ca647bd | 5425 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); |
94b982b2 | 5426 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5427 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5428 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5429 | } |
5430 | adapter->rsc_total_count = rsc_count; | |
5431 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5432 | } |
5433 | ||
5b7da515 AD |
5434 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5435 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5436 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5437 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5438 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
5439 | bytes += rx_ring->stats.bytes; | |
5440 | packets += rx_ring->stats.packets; | |
5441 | } | |
5442 | adapter->non_eop_descs = non_eop_descs; | |
5443 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5444 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
5445 | netdev->stats.rx_bytes = bytes; | |
5446 | netdev->stats.rx_packets = packets; | |
5447 | ||
5448 | bytes = 0; | |
5449 | packets = 0; | |
7ca3bc58 | 5450 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5451 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5452 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5453 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5454 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5455 | bytes += tx_ring->stats.bytes; | |
5456 | packets += tx_ring->stats.packets; | |
5457 | } | |
eb985f09 | 5458 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5459 | adapter->tx_busy = tx_busy; |
5460 | netdev->stats.tx_bytes = bytes; | |
5461 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5462 | |
7ca647bd | 5463 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5464 | |
5465 | /* 8 register reads */ | |
6f11eef7 AV |
5466 | for (i = 0; i < 8; i++) { |
5467 | /* for packet buffers not used, the register should read 0 */ | |
5468 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5469 | missed_rx += mpc; | |
7ca647bd JP |
5470 | hwstats->mpc[i] += mpc; |
5471 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5472 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5473 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5474 | switch (hw->mac.type) { |
5475 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5476 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5477 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5478 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5479 | hwstats->pxonrxc[i] += |
5480 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5481 | break; |
5482 | case ixgbe_mac_82599EB: | |
b93a2226 | 5483 | case ixgbe_mac_X540: |
bd508178 AD |
5484 | hwstats->pxonrxc[i] += |
5485 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5486 | break; |
5487 | default: | |
5488 | break; | |
e8e26350 | 5489 | } |
6f11eef7 | 5490 | } |
1a70db4b ET |
5491 | |
5492 | /*16 register reads */ | |
5493 | for (i = 0; i < 16; i++) { | |
5494 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5495 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5496 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5497 | (hw->mac.type == ixgbe_mac_X540)) { | |
5498 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5499 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5500 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5501 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5502 | } | |
5503 | } | |
5504 | ||
7ca647bd | 5505 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5506 | /* work around hardware counting issue */ |
7ca647bd | 5507 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5508 | |
c84d324c JF |
5509 | ixgbe_update_xoff_received(adapter); |
5510 | ||
6f11eef7 | 5511 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5512 | switch (hw->mac.type) { |
5513 | case ixgbe_mac_82598EB: | |
5514 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5515 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5516 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5517 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5518 | break; | |
b93a2226 | 5519 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5520 | /* OS2BMC stats are X540 only*/ |
5521 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5522 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5523 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5524 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5525 | case ixgbe_mac_82599EB: | |
7ca647bd | 5526 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5527 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5528 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5529 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5530 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5531 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5532 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5533 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5534 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5535 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5536 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5537 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5538 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5539 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5540 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5541 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
6d45522c | 5542 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5543 | break; |
5544 | default: | |
5545 | break; | |
e8e26350 | 5546 | } |
9a799d71 | 5547 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5548 | hwstats->bprc += bprc; |
5549 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5550 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5551 | hwstats->mprc -= bprc; |
5552 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5553 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5554 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5555 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5556 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5557 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5558 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5559 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5560 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5561 | hwstats->lxontxc += lxon; |
6f11eef7 | 5562 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 5563 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
5564 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
5565 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5566 | /* |
5567 | * 82598 errata - tx of flow control packets is included in tx counters | |
5568 | */ | |
5569 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5570 | hwstats->gptc -= xon_off_tot; |
5571 | hwstats->mptc -= xon_off_tot; | |
5572 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5573 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5574 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5575 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5576 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5577 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5578 | hwstats->ptc64 -= xon_off_tot; | |
5579 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5580 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5581 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5582 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5583 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5584 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5585 | |
5586 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5587 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5588 | |
5589 | /* Rx Errors */ | |
7ca647bd | 5590 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5591 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5592 | netdev->stats.rx_length_errors = hwstats->rlec; |
5593 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5594 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5595 | } |
5596 | ||
5597 | /** | |
d034acf1 AD |
5598 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
5599 | * @adapter - pointer to the device adapter structure | |
9a799d71 | 5600 | **/ |
d034acf1 | 5601 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 5602 | { |
cf8280ee | 5603 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 5604 | int i; |
cf8280ee | 5605 | |
d034acf1 AD |
5606 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
5607 | return; | |
5608 | ||
5609 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 5610 | |
d034acf1 | 5611 | /* if interface is down do nothing */ |
fe49f04a | 5612 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
5613 | return; |
5614 | ||
5615 | /* do nothing if we are not using signature filters */ | |
5616 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
5617 | return; | |
5618 | ||
5619 | adapter->fdir_overflow++; | |
5620 | ||
93c52dd0 AD |
5621 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
5622 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5623 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 5624 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
5625 | /* re-enable flow director interrupts */ |
5626 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
5627 | } else { |
5628 | e_err(probe, "failed to finish FDIR re-initialization, " | |
5629 | "ignored adding FDIR ATR filters\n"); | |
5630 | } | |
93c52dd0 AD |
5631 | } |
5632 | ||
5633 | /** | |
5634 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
5635 | * @adapter - pointer to the device adapter structure | |
5636 | * | |
5637 | * This function serves two purposes. First it strobes the interrupt lines | |
5638 | * in order to make certain interrupts are occuring. Secondly it sets the | |
5639 | * bits needed to check for TX hangs. As a result we should immediately | |
5640 | * determine if a hang has occured. | |
5641 | */ | |
5642 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 5643 | { |
cf8280ee | 5644 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5645 | u64 eics = 0; |
5646 | int i; | |
cf8280ee | 5647 | |
93c52dd0 AD |
5648 | /* If we're down or resetting, just bail */ |
5649 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5650 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5651 | return; | |
22d5a71b | 5652 | |
93c52dd0 AD |
5653 | /* Force detection of hung controller */ |
5654 | if (netif_carrier_ok(adapter->netdev)) { | |
5655 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5656 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
5657 | } | |
22d5a71b | 5658 | |
fe49f04a AD |
5659 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5660 | /* | |
5661 | * for legacy and MSI interrupts don't set any bits | |
5662 | * that are enabled for EIAM, because this operation | |
5663 | * would set *both* EIMS and EICS for any bit in EIAM | |
5664 | */ | |
5665 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5666 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
5667 | } else { |
5668 | /* get one bit for every active tx/rx interrupt vector */ | |
5669 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
5670 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
efe3d3c8 | 5671 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
5672 | eics |= ((u64)1 << i); |
5673 | } | |
cf8280ee | 5674 | } |
9a799d71 | 5675 | |
93c52dd0 | 5676 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
5677 | ixgbe_irq_rearm_queues(adapter, eics); |
5678 | ||
cf8280ee JB |
5679 | } |
5680 | ||
e8e26350 | 5681 | /** |
93c52dd0 AD |
5682 | * ixgbe_watchdog_update_link - update the link status |
5683 | * @adapter - pointer to the device adapter structure | |
5684 | * @link_speed - pointer to a u32 to store the link_speed | |
e8e26350 | 5685 | **/ |
93c52dd0 | 5686 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 5687 | { |
e8e26350 | 5688 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5689 | u32 link_speed = adapter->link_speed; |
5690 | bool link_up = adapter->link_up; | |
c4cf55e5 | 5691 | int i; |
e8e26350 | 5692 | |
93c52dd0 AD |
5693 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
5694 | return; | |
5695 | ||
5696 | if (hw->mac.ops.check_link) { | |
5697 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 5698 | } else { |
93c52dd0 AD |
5699 | /* always assume link is up, if no check link function */ |
5700 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
5701 | link_up = true; | |
c4cf55e5 | 5702 | } |
93c52dd0 AD |
5703 | if (link_up) { |
5704 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
5705 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
5706 | hw->mac.ops.fc_enable(hw, i); | |
5707 | } else { | |
5708 | hw->mac.ops.fc_enable(hw, 0); | |
5709 | } | |
5710 | } | |
5711 | ||
5712 | if (link_up || | |
5713 | time_after(jiffies, (adapter->link_check_timeout + | |
5714 | IXGBE_TRY_LINK_TIMEOUT))) { | |
5715 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
5716 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
5717 | IXGBE_WRITE_FLUSH(hw); | |
5718 | } | |
5719 | ||
5720 | adapter->link_up = link_up; | |
5721 | adapter->link_speed = link_speed; | |
e8e26350 PW |
5722 | } |
5723 | ||
5724 | /** | |
93c52dd0 AD |
5725 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
5726 | * print link up message | |
5727 | * @adapter - pointer to the device adapter structure | |
e8e26350 | 5728 | **/ |
93c52dd0 | 5729 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 5730 | { |
93c52dd0 | 5731 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 5732 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5733 | u32 link_speed = adapter->link_speed; |
5734 | bool flow_rx, flow_tx; | |
e8e26350 | 5735 | |
93c52dd0 AD |
5736 | /* only continue if link was previously down */ |
5737 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 5738 | return; |
63d6e1d8 | 5739 | |
93c52dd0 | 5740 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 5741 | |
93c52dd0 AD |
5742 | switch (hw->mac.type) { |
5743 | case ixgbe_mac_82598EB: { | |
5744 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5745 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
5746 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
5747 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
5748 | } | |
5749 | break; | |
5750 | case ixgbe_mac_X540: | |
5751 | case ixgbe_mac_82599EB: { | |
5752 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5753 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
5754 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
5755 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
5756 | } | |
5757 | break; | |
5758 | default: | |
5759 | flow_tx = false; | |
5760 | flow_rx = false; | |
5761 | break; | |
e8e26350 | 5762 | } |
93c52dd0 AD |
5763 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
5764 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5765 | "10 Gbps" : | |
5766 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5767 | "1 Gbps" : | |
5768 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
5769 | "100 Mbps" : | |
5770 | "unknown speed"))), | |
5771 | ((flow_rx && flow_tx) ? "RX/TX" : | |
5772 | (flow_rx ? "RX" : | |
5773 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 5774 | |
93c52dd0 | 5775 | netif_carrier_on(netdev); |
93c52dd0 | 5776 | ixgbe_check_vf_rate_limit(adapter); |
e8e26350 PW |
5777 | } |
5778 | ||
c4cf55e5 | 5779 | /** |
93c52dd0 AD |
5780 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
5781 | * print link down message | |
5782 | * @adapter - pointer to the adapter structure | |
c4cf55e5 | 5783 | **/ |
93c52dd0 | 5784 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter) |
c4cf55e5 | 5785 | { |
cf8280ee | 5786 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 5787 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 5788 | |
93c52dd0 AD |
5789 | adapter->link_up = false; |
5790 | adapter->link_speed = 0; | |
cf8280ee | 5791 | |
93c52dd0 AD |
5792 | /* only continue if link was up previously */ |
5793 | if (!netif_carrier_ok(netdev)) | |
5794 | return; | |
264857b8 | 5795 | |
93c52dd0 AD |
5796 | /* poll for SFP+ cable when link is down */ |
5797 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
5798 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 5799 | |
93c52dd0 AD |
5800 | e_info(drv, "NIC Link is Down\n"); |
5801 | netif_carrier_off(netdev); | |
5802 | } | |
e8e26350 | 5803 | |
93c52dd0 AD |
5804 | /** |
5805 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
5806 | * @adapter - pointer to the device adapter structure | |
5807 | **/ | |
5808 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
5809 | { | |
c4cf55e5 | 5810 | int i; |
93c52dd0 | 5811 | int some_tx_pending = 0; |
c4cf55e5 | 5812 | |
93c52dd0 | 5813 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 5814 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 5815 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5816 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5817 | some_tx_pending = 1; | |
5818 | break; | |
5819 | } | |
5820 | } | |
5821 | ||
5822 | if (some_tx_pending) { | |
5823 | /* We've lost link, so the controller stops DMA, | |
5824 | * but we've got queued Tx work that's never going | |
5825 | * to get done, so reset controller to flush Tx. | |
5826 | * (Do the reset outside of interrupt context). | |
5827 | */ | |
c83c6cbd | 5828 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 5829 | } |
c4cf55e5 | 5830 | } |
c4cf55e5 PWJ |
5831 | } |
5832 | ||
a985b6c3 GR |
5833 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
5834 | { | |
5835 | u32 ssvpc; | |
5836 | ||
5837 | /* Do not perform spoof check for 82598 */ | |
5838 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5839 | return; | |
5840 | ||
5841 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
5842 | ||
5843 | /* | |
5844 | * ssvpc register is cleared on read, if zero then no | |
5845 | * spoofed packets in the last interval. | |
5846 | */ | |
5847 | if (!ssvpc) | |
5848 | return; | |
5849 | ||
5850 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
5851 | } | |
5852 | ||
93c52dd0 AD |
5853 | /** |
5854 | * ixgbe_watchdog_subtask - check and bring link up | |
5855 | * @adapter - pointer to the device adapter structure | |
5856 | **/ | |
5857 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
5858 | { | |
5859 | /* if interface is down do nothing */ | |
5860 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
5861 | return; | |
5862 | ||
5863 | ixgbe_watchdog_update_link(adapter); | |
5864 | ||
5865 | if (adapter->link_up) | |
5866 | ixgbe_watchdog_link_is_up(adapter); | |
5867 | else | |
5868 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 5869 | |
a985b6c3 | 5870 | ixgbe_spoof_check(adapter); |
9a799d71 | 5871 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
5872 | |
5873 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 5874 | } |
10eec955 | 5875 | |
cf8280ee | 5876 | /** |
7086400d AD |
5877 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
5878 | * @adapter - the ixgbe adapter structure | |
cf8280ee | 5879 | **/ |
7086400d | 5880 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 5881 | { |
cf8280ee | 5882 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 5883 | s32 err; |
cf8280ee | 5884 | |
7086400d AD |
5885 | /* not searching for SFP so there is nothing to do here */ |
5886 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
5887 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5888 | return; | |
10eec955 | 5889 | |
7086400d AD |
5890 | /* someone else is in init, wait until next service event */ |
5891 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5892 | return; | |
cf8280ee | 5893 | |
7086400d AD |
5894 | err = hw->phy.ops.identify_sfp(hw); |
5895 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5896 | goto sfp_out; | |
264857b8 | 5897 | |
7086400d AD |
5898 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
5899 | /* If no cable is present, then we need to reset | |
5900 | * the next time we find a good cable. */ | |
5901 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 5902 | } |
9a799d71 | 5903 | |
7086400d AD |
5904 | /* exit on error */ |
5905 | if (err) | |
5906 | goto sfp_out; | |
e8e26350 | 5907 | |
7086400d AD |
5908 | /* exit if reset not needed */ |
5909 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5910 | goto sfp_out; | |
9a799d71 | 5911 | |
7086400d | 5912 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 5913 | |
7086400d AD |
5914 | /* |
5915 | * A module may be identified correctly, but the EEPROM may not have | |
5916 | * support for that module. setup_sfp() will fail in that case, so | |
5917 | * we should not allow that module to load. | |
5918 | */ | |
5919 | if (hw->mac.type == ixgbe_mac_82598EB) | |
5920 | err = hw->phy.ops.reset(hw); | |
5921 | else | |
5922 | err = hw->mac.ops.setup_sfp(hw); | |
5923 | ||
5924 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5925 | goto sfp_out; | |
5926 | ||
5927 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
5928 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
5929 | ||
5930 | sfp_out: | |
5931 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5932 | ||
5933 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
5934 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
5935 | e_dev_err("failed to initialize because an unsupported " | |
5936 | "SFP+ module type was detected.\n"); | |
5937 | e_dev_err("Reload the driver after installing a " | |
5938 | "supported module.\n"); | |
5939 | unregister_netdev(adapter->netdev); | |
bc59fcda | 5940 | } |
7086400d | 5941 | } |
bc59fcda | 5942 | |
7086400d AD |
5943 | /** |
5944 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
5945 | * @adapter - the ixgbe adapter structure | |
5946 | **/ | |
5947 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
5948 | { | |
5949 | struct ixgbe_hw *hw = &adapter->hw; | |
5950 | u32 autoneg; | |
5951 | bool negotiation; | |
5952 | ||
5953 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
5954 | return; | |
5955 | ||
5956 | /* someone else is in init, wait until next service event */ | |
5957 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5958 | return; | |
5959 | ||
5960 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5961 | ||
5962 | autoneg = hw->phy.autoneg_advertised; | |
5963 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
5964 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
5965 | hw->mac.autotry_restart = false; | |
5966 | if (hw->mac.ops.setup_link) | |
5967 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
5968 | ||
5969 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
5970 | adapter->link_check_timeout = jiffies; | |
5971 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5972 | } | |
5973 | ||
5974 | /** | |
5975 | * ixgbe_service_timer - Timer Call-back | |
5976 | * @data: pointer to adapter cast into an unsigned long | |
5977 | **/ | |
5978 | static void ixgbe_service_timer(unsigned long data) | |
5979 | { | |
5980 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5981 | unsigned long next_event_offset; | |
5982 | ||
5983 | /* poll faster when waiting for link */ | |
5984 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
5985 | next_event_offset = HZ / 10; | |
5986 | else | |
5987 | next_event_offset = HZ * 2; | |
5988 | ||
5989 | /* Reset the timer */ | |
5990 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
5991 | ||
5992 | ixgbe_service_event_schedule(adapter); | |
5993 | } | |
5994 | ||
c83c6cbd AD |
5995 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
5996 | { | |
5997 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
5998 | return; | |
5999 | ||
6000 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
6001 | ||
6002 | /* If we're already down or resetting, just bail */ | |
6003 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
6004 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6005 | return; | |
6006 | ||
6007 | ixgbe_dump(adapter); | |
6008 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
6009 | adapter->tx_timeout_count++; | |
6010 | ||
6011 | ixgbe_reinit_locked(adapter); | |
6012 | } | |
6013 | ||
7086400d AD |
6014 | /** |
6015 | * ixgbe_service_task - manages and runs subtasks | |
6016 | * @work: pointer to work_struct containing our data | |
6017 | **/ | |
6018 | static void ixgbe_service_task(struct work_struct *work) | |
6019 | { | |
6020 | struct ixgbe_adapter *adapter = container_of(work, | |
6021 | struct ixgbe_adapter, | |
6022 | service_task); | |
6023 | ||
c83c6cbd | 6024 | ixgbe_reset_subtask(adapter); |
7086400d AD |
6025 | ixgbe_sfp_detection_subtask(adapter); |
6026 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 6027 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 6028 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 6029 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 6030 | ixgbe_check_hang_subtask(adapter); |
7086400d AD |
6031 | |
6032 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
6033 | } |
6034 | ||
897ab156 AD |
6035 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens, |
6036 | u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) | |
9a799d71 AK |
6037 | { |
6038 | struct ixgbe_adv_tx_context_desc *context_desc; | |
897ab156 | 6039 | u16 i = tx_ring->next_to_use; |
9a799d71 | 6040 | |
897ab156 | 6041 | context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i); |
9a799d71 | 6042 | |
897ab156 AD |
6043 | i++; |
6044 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
9a799d71 | 6045 | |
897ab156 AD |
6046 | /* set bits to identify this as an advanced context descriptor */ |
6047 | type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; | |
9a799d71 | 6048 | |
897ab156 AD |
6049 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); |
6050 | context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); | |
6051 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
6052 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
6053 | } | |
9a799d71 | 6054 | |
897ab156 AD |
6055 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb, |
6056 | u32 tx_flags, __be16 protocol, u8 *hdr_len) | |
6057 | { | |
6058 | int err; | |
6059 | u32 vlan_macip_lens, type_tucmd; | |
6060 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 6061 | |
897ab156 AD |
6062 | if (!skb_is_gso(skb)) |
6063 | return 0; | |
9a799d71 | 6064 | |
897ab156 AD |
6065 | if (skb_header_cloned(skb)) { |
6066 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
6067 | if (err) | |
6068 | return err; | |
9a799d71 | 6069 | } |
9a799d71 | 6070 | |
897ab156 AD |
6071 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
6072 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6073 | ||
6074 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6075 | struct iphdr *iph = ip_hdr(skb); | |
6076 | iph->tot_len = 0; | |
6077 | iph->check = 0; | |
6078 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6079 | iph->daddr, 0, | |
6080 | IPPROTO_TCP, | |
6081 | 0); | |
6082 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
6083 | } else if (skb_is_gso_v6(skb)) { | |
6084 | ipv6_hdr(skb)->payload_len = 0; | |
6085 | tcp_hdr(skb)->check = | |
6086 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
6087 | &ipv6_hdr(skb)->daddr, | |
6088 | 0, IPPROTO_TCP, 0); | |
6089 | } | |
6090 | ||
6091 | l4len = tcp_hdrlen(skb); | |
6092 | *hdr_len = skb_transport_offset(skb) + l4len; | |
6093 | ||
6094 | /* mss_l4len_id: use 1 as index for TSO */ | |
6095 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
6096 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
6097 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
6098 | ||
6099 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
6100 | vlan_macip_lens = skb_network_header_len(skb); | |
6101 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
6102 | vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; | |
6103 | ||
6104 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
6105 | mss_l4len_idx); | |
6106 | ||
6107 | return 1; | |
6108 | } | |
6109 | ||
6110 | static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring, | |
6111 | struct sk_buff *skb, u32 tx_flags, | |
6112 | __be16 protocol) | |
7ca647bd | 6113 | { |
897ab156 AD |
6114 | u32 vlan_macip_lens = 0; |
6115 | u32 mss_l4len_idx = 0; | |
6116 | u32 type_tucmd = 0; | |
7ca647bd | 6117 | |
897ab156 | 6118 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
7f9643fd AD |
6119 | if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
6120 | !(tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
897ab156 AD |
6121 | return false; |
6122 | } else { | |
6123 | u8 l4_hdr = 0; | |
6124 | switch (protocol) { | |
6125 | case __constant_htons(ETH_P_IP): | |
6126 | vlan_macip_lens |= skb_network_header_len(skb); | |
6127 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
6128 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 6129 | break; |
897ab156 AD |
6130 | case __constant_htons(ETH_P_IPV6): |
6131 | vlan_macip_lens |= skb_network_header_len(skb); | |
6132 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
6133 | break; | |
6134 | default: | |
6135 | if (unlikely(net_ratelimit())) { | |
6136 | dev_warn(tx_ring->dev, | |
6137 | "partial checksum but proto=%x!\n", | |
6138 | skb->protocol); | |
6139 | } | |
7ca647bd JP |
6140 | break; |
6141 | } | |
897ab156 AD |
6142 | |
6143 | switch (l4_hdr) { | |
7ca647bd | 6144 | case IPPROTO_TCP: |
897ab156 AD |
6145 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
6146 | mss_l4len_idx = tcp_hdrlen(skb) << | |
6147 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
6148 | break; |
6149 | case IPPROTO_SCTP: | |
897ab156 AD |
6150 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
6151 | mss_l4len_idx = sizeof(struct sctphdr) << | |
6152 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
6153 | break; | |
6154 | case IPPROTO_UDP: | |
6155 | mss_l4len_idx = sizeof(struct udphdr) << | |
6156 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
6157 | break; | |
6158 | default: | |
6159 | if (unlikely(net_ratelimit())) { | |
6160 | dev_warn(tx_ring->dev, | |
6161 | "partial checksum but l4 proto=%x!\n", | |
6162 | skb->protocol); | |
6163 | } | |
7ca647bd JP |
6164 | break; |
6165 | } | |
7ca647bd JP |
6166 | } |
6167 | ||
897ab156 AD |
6168 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
6169 | vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; | |
9a799d71 | 6170 | |
897ab156 AD |
6171 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
6172 | type_tucmd, mss_l4len_idx); | |
9a799d71 | 6173 | |
897ab156 | 6174 | return (skb->ip_summed == CHECKSUM_PARTIAL); |
9a799d71 AK |
6175 | } |
6176 | ||
d3d00239 | 6177 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 6178 | { |
d3d00239 AD |
6179 | /* set type for advanced descriptor with frame checksum insertion */ |
6180 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
6181 | IXGBE_ADVTXD_DCMD_IFCS | | |
6182 | IXGBE_ADVTXD_DCMD_DEXT); | |
9a799d71 | 6183 | |
d3d00239 | 6184 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 6185 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 6186 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 6187 | |
d3d00239 AD |
6188 | /* set segmentation enable bits for TSO/FSO */ |
6189 | #ifdef IXGBE_FCOE | |
6190 | if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO)) | |
6191 | #else | |
6192 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
6193 | #endif | |
6194 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 6195 | |
d3d00239 AD |
6196 | return cmd_type; |
6197 | } | |
9a799d71 | 6198 | |
d3d00239 AD |
6199 | static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen) |
6200 | { | |
6201 | __le32 olinfo_status = | |
6202 | cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); | |
44df32c5 | 6203 | |
d3d00239 AD |
6204 | if (tx_flags & IXGBE_TX_FLAGS_TSO) { |
6205 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM | | |
6206 | (1 << IXGBE_ADVTXD_IDX_SHIFT)); | |
6207 | /* enble IPv4 checksum for TSO */ | |
6208 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
6209 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 AK |
6210 | } |
6211 | ||
d3d00239 AD |
6212 | /* enable L4 checksum for TSO and TX checksum offload */ |
6213 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
6214 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 6215 | |
d3d00239 AD |
6216 | #ifdef IXGBE_FCOE |
6217 | /* use index 1 context for FCOE/FSO */ | |
6218 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) | |
6219 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC | | |
6220 | (1 << IXGBE_ADVTXD_IDX_SHIFT)); | |
9a799d71 | 6221 | |
d3d00239 | 6222 | #endif |
7f9643fd AD |
6223 | /* |
6224 | * Check Context must be set if Tx switch is enabled, which it | |
6225 | * always is for case where virtual functions are running | |
6226 | */ | |
6227 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) | |
6228 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); | |
6229 | ||
d3d00239 AD |
6230 | return olinfo_status; |
6231 | } | |
44df32c5 | 6232 | |
d3d00239 AD |
6233 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
6234 | IXGBE_TXD_CMD_RS) | |
6235 | ||
6236 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
6237 | struct sk_buff *skb, | |
6238 | struct ixgbe_tx_buffer *first, | |
6239 | u32 tx_flags, | |
6240 | const u8 hdr_len) | |
6241 | { | |
6242 | struct device *dev = tx_ring->dev; | |
6243 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6244 | union ixgbe_adv_tx_desc *tx_desc; | |
6245 | dma_addr_t dma; | |
6246 | __le32 cmd_type, olinfo_status; | |
6247 | struct skb_frag_struct *frag; | |
6248 | unsigned int f = 0; | |
6249 | unsigned int data_len = skb->data_len; | |
6250 | unsigned int size = skb_headlen(skb); | |
6251 | u32 offset = 0; | |
6252 | u32 paylen = skb->len - hdr_len; | |
6253 | u16 i = tx_ring->next_to_use; | |
6254 | u16 gso_segs; | |
6255 | ||
6256 | #ifdef IXGBE_FCOE | |
6257 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
6258 | if (data_len >= sizeof(struct fcoe_crc_eof)) { | |
6259 | data_len -= sizeof(struct fcoe_crc_eof); | |
6260 | } else { | |
6261 | size -= sizeof(struct fcoe_crc_eof) - data_len; | |
6262 | data_len = 0; | |
9a799d71 AK |
6263 | } |
6264 | } | |
44df32c5 | 6265 | |
d3d00239 AD |
6266 | #endif |
6267 | dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); | |
6268 | if (dma_mapping_error(dev, dma)) | |
6269 | goto dma_error; | |
8ad494b0 | 6270 | |
d3d00239 AD |
6271 | cmd_type = ixgbe_tx_cmd_type(tx_flags); |
6272 | olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen); | |
9a799d71 | 6273 | |
d3d00239 | 6274 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i); |
e5a43549 | 6275 | |
d3d00239 AD |
6276 | for (;;) { |
6277 | while (size > IXGBE_MAX_DATA_PER_TXD) { | |
6278 | tx_desc->read.buffer_addr = cpu_to_le64(dma + offset); | |
6279 | tx_desc->read.cmd_type_len = | |
6280 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
6281 | tx_desc->read.olinfo_status = olinfo_status; | |
e5a43549 | 6282 | |
d3d00239 AD |
6283 | offset += IXGBE_MAX_DATA_PER_TXD; |
6284 | size -= IXGBE_MAX_DATA_PER_TXD; | |
e5a43549 | 6285 | |
d3d00239 AD |
6286 | tx_desc++; |
6287 | i++; | |
6288 | if (i == tx_ring->count) { | |
6289 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0); | |
6290 | i = 0; | |
6291 | } | |
6292 | } | |
e5a43549 | 6293 | |
e5a43549 | 6294 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
d3d00239 AD |
6295 | tx_buffer_info->length = offset + size; |
6296 | tx_buffer_info->tx_flags = tx_flags; | |
6297 | tx_buffer_info->dma = dma; | |
9a799d71 | 6298 | |
d3d00239 AD |
6299 | tx_desc->read.buffer_addr = cpu_to_le64(dma + offset); |
6300 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); | |
6301 | tx_desc->read.olinfo_status = olinfo_status; | |
9a799d71 | 6302 | |
d3d00239 AD |
6303 | if (!data_len) |
6304 | break; | |
9a799d71 | 6305 | |
d3d00239 AD |
6306 | frag = &skb_shinfo(skb)->frags[f]; |
6307 | #ifdef IXGBE_FCOE | |
6308 | size = min_t(unsigned int, data_len, frag->size); | |
6309 | #else | |
6310 | size = frag->size; | |
6311 | #endif | |
6312 | data_len -= size; | |
6313 | f++; | |
9a799d71 | 6314 | |
d3d00239 AD |
6315 | offset = 0; |
6316 | tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE; | |
9a799d71 | 6317 | |
877749bf | 6318 | dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); |
d3d00239 AD |
6319 | if (dma_mapping_error(dev, dma)) |
6320 | goto dma_error; | |
9a799d71 | 6321 | |
d3d00239 AD |
6322 | tx_desc++; |
6323 | i++; | |
6324 | if (i == tx_ring->count) { | |
6325 | tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0); | |
6326 | i = 0; | |
6327 | } | |
6328 | } | |
9a799d71 | 6329 | |
d3d00239 | 6330 | tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD); |
9a799d71 | 6331 | |
d3d00239 AD |
6332 | i++; |
6333 | if (i == tx_ring->count) | |
6334 | i = 0; | |
9a799d71 | 6335 | |
d3d00239 | 6336 | tx_ring->next_to_use = i; |
eacd73f7 | 6337 | |
d3d00239 AD |
6338 | if (tx_flags & IXGBE_TX_FLAGS_TSO) |
6339 | gso_segs = skb_shinfo(skb)->gso_segs; | |
6340 | #ifdef IXGBE_FCOE | |
6341 | /* adjust for FCoE Sequence Offload */ | |
6342 | else if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6343 | gso_segs = DIV_ROUND_UP(skb->len - hdr_len, | |
6344 | skb_shinfo(skb)->gso_size); | |
6345 | #endif /* IXGBE_FCOE */ | |
6346 | else | |
6347 | gso_segs = 1; | |
9a799d71 | 6348 | |
d3d00239 AD |
6349 | /* multiply data chunks by size of headers */ |
6350 | tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len); | |
6351 | tx_buffer_info->gso_segs = gso_segs; | |
6352 | tx_buffer_info->skb = skb; | |
9a799d71 | 6353 | |
d3d00239 AD |
6354 | /* set the timestamp */ |
6355 | first->time_stamp = jiffies; | |
9a799d71 AK |
6356 | |
6357 | /* | |
6358 | * Force memory writes to complete before letting h/w | |
6359 | * know there are new descriptors to fetch. (Only | |
6360 | * applicable for weak-ordered memory model archs, | |
6361 | * such as IA-64). | |
6362 | */ | |
6363 | wmb(); | |
6364 | ||
d3d00239 AD |
6365 | /* set next_to_watch value indicating a packet is present */ |
6366 | first->next_to_watch = tx_desc; | |
6367 | ||
6368 | /* notify HW of packet */ | |
84ea2591 | 6369 | writel(i, tx_ring->tail); |
d3d00239 AD |
6370 | |
6371 | return; | |
6372 | dma_error: | |
6373 | dev_err(dev, "TX DMA map failed\n"); | |
6374 | ||
6375 | /* clear dma mappings for failed tx_buffer_info map */ | |
6376 | for (;;) { | |
6377 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
6378 | ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info); | |
6379 | if (tx_buffer_info == first) | |
6380 | break; | |
6381 | if (i == 0) | |
6382 | i = tx_ring->count; | |
6383 | i--; | |
6384 | } | |
6385 | ||
6386 | dev_kfree_skb_any(skb); | |
6387 | ||
6388 | tx_ring->next_to_use = i; | |
9a799d71 AK |
6389 | } |
6390 | ||
69830529 AD |
6391 | static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb, |
6392 | u32 tx_flags, __be16 protocol) | |
6393 | { | |
6394 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6395 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6396 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6397 | union { | |
6398 | unsigned char *network; | |
6399 | struct iphdr *ipv4; | |
6400 | struct ipv6hdr *ipv6; | |
6401 | } hdr; | |
ee9e0f0b | 6402 | struct tcphdr *th; |
905e4a41 | 6403 | __be16 vlan_id; |
c4cf55e5 | 6404 | |
69830529 AD |
6405 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6406 | if (!q_vector) | |
6407 | return; | |
6408 | ||
6409 | /* do nothing if sampling is disabled */ | |
6410 | if (!ring->atr_sample_rate) | |
d3ead241 | 6411 | return; |
c4cf55e5 | 6412 | |
69830529 | 6413 | ring->atr_count++; |
c4cf55e5 | 6414 | |
69830529 AD |
6415 | /* snag network header to get L4 type and address */ |
6416 | hdr.network = skb_network_header(skb); | |
6417 | ||
6418 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
6419 | if ((protocol != __constant_htons(ETH_P_IPV6) || | |
6420 | hdr.ipv6->nexthdr != IPPROTO_TCP) && | |
6421 | (protocol != __constant_htons(ETH_P_IP) || | |
6422 | hdr.ipv4->protocol != IPPROTO_TCP)) | |
6423 | return; | |
ee9e0f0b AD |
6424 | |
6425 | th = tcp_hdr(skb); | |
c4cf55e5 | 6426 | |
66f32a8b AD |
6427 | /* skip this packet since it is invalid or the socket is closing */ |
6428 | if (!th || th->fin) | |
69830529 AD |
6429 | return; |
6430 | ||
6431 | /* sample on all syn packets or once every atr sample count */ | |
6432 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6433 | return; | |
6434 | ||
6435 | /* reset sample count */ | |
6436 | ring->atr_count = 0; | |
6437 | ||
6438 | vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6439 | ||
6440 | /* | |
6441 | * src and dst are inverted, think how the receiver sees them | |
6442 | * | |
6443 | * The input is broken into two sections, a non-compressed section | |
6444 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6445 | * is XORed together and stored in the compressed dword. | |
6446 | */ | |
6447 | input.formatted.vlan_id = vlan_id; | |
6448 | ||
6449 | /* | |
6450 | * since src port and flex bytes occupy the same word XOR them together | |
6451 | * and write the value to source port portion of compressed dword | |
6452 | */ | |
66f32a8b | 6453 | if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6454 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6455 | else | |
6456 | common.port.src ^= th->dest ^ protocol; | |
6457 | common.port.dst ^= th->source; | |
6458 | ||
6459 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6460 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; | |
6461 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6462 | } else { | |
6463 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6464 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6465 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6466 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6467 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6468 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6469 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6470 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6471 | hdr.ipv6->daddr.s6_addr32[3]; | |
6472 | } | |
c4cf55e5 PWJ |
6473 | |
6474 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6475 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6476 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6477 | } |
6478 | ||
63544e9c | 6479 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6480 | { |
fc77dc3c | 6481 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6482 | /* Herbert's original patch had: |
6483 | * smp_mb__after_netif_stop_queue(); | |
6484 | * but since that doesn't exist yet, just open code it. */ | |
6485 | smp_mb(); | |
6486 | ||
6487 | /* We need to check again in a case another CPU has just | |
6488 | * made room available. */ | |
7d4987de | 6489 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
6490 | return -EBUSY; |
6491 | ||
6492 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6493 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6494 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6495 | return 0; |
6496 | } | |
6497 | ||
82d4e46e | 6498 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6499 | { |
7d4987de | 6500 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 6501 | return 0; |
fc77dc3c | 6502 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6503 | } |
6504 | ||
09a3b1f8 SH |
6505 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6506 | { | |
6507 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
6508 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
6509 | smp_processor_id(); | |
56075a98 | 6510 | #ifdef IXGBE_FCOE |
6440752c | 6511 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 6512 | |
e5b64635 JF |
6513 | if (((protocol == htons(ETH_P_FCOE)) || |
6514 | (protocol == htons(ETH_P_FIP))) && | |
6515 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
6516 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
6517 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
6518 | return txq; | |
56075a98 JF |
6519 | } |
6520 | #endif | |
6521 | ||
fdd3d631 KK |
6522 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6523 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6524 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6525 | return txq; |
fdd3d631 | 6526 | } |
c4cf55e5 | 6527 | |
09a3b1f8 SH |
6528 | return skb_tx_hash(dev, skb); |
6529 | } | |
6530 | ||
fc77dc3c | 6531 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6532 | struct ixgbe_adapter *adapter, |
6533 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6534 | { |
d3d00239 | 6535 | struct ixgbe_tx_buffer *first; |
5f715823 | 6536 | int tso; |
d3d00239 | 6537 | u32 tx_flags = 0; |
a535c30e AD |
6538 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
6539 | unsigned short f; | |
6540 | #endif | |
a535c30e | 6541 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 6542 | __be16 protocol = skb->protocol; |
63544e9c | 6543 | u8 hdr_len = 0; |
5e09a105 | 6544 | |
a535c30e AD |
6545 | /* |
6546 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
6547 | * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD, | |
6548 | * + 2 desc gap to keep tail from touching head, | |
6549 | * + 1 desc for context descriptor, | |
6550 | * otherwise try next time | |
6551 | */ | |
6552 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
6553 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
6554 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
6555 | #else | |
6556 | count += skb_shinfo(skb)->nr_frags; | |
6557 | #endif | |
6558 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
6559 | tx_ring->tx_stats.tx_busy++; | |
6560 | return NETDEV_TX_BUSY; | |
6561 | } | |
6562 | ||
7f9643fd AD |
6563 | #ifdef CONFIG_PCI_IOV |
6564 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6565 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
6566 | ||
6567 | #endif | |
66f32a8b | 6568 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 6569 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
6570 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
6571 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
6572 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
6573 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6574 | struct vlan_hdr *vhdr, _vhdr; | |
6575 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
6576 | if (!vhdr) | |
6577 | goto out_drop; | |
6578 | ||
6579 | protocol = vhdr->h_vlan_encapsulated_proto; | |
6580 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT; | |
6581 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; | |
6582 | } | |
6583 | ||
6584 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && | |
09dca476 AD |
6585 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
6586 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b AD |
6587 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
6588 | tx_flags |= tx_ring->dcb_tc << | |
6589 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
6590 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { | |
6591 | struct vlan_ethhdr *vhdr; | |
6592 | if (skb_header_cloned(skb) && | |
6593 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
6594 | goto out_drop; | |
6595 | vhdr = (struct vlan_ethhdr *)skb->data; | |
6596 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
6597 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6598 | } else { | |
6599 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 6600 | } |
9a799d71 | 6601 | } |
eacd73f7 | 6602 | |
a535c30e | 6603 | /* record the location of the first descriptor for this packet */ |
d3d00239 | 6604 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; |
a535c30e | 6605 | |
eacd73f7 | 6606 | #ifdef IXGBE_FCOE |
66f32a8b AD |
6607 | /* setup tx offload for FCoE */ |
6608 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
6609 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
897ab156 AD |
6610 | tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len); |
6611 | if (tso < 0) | |
6612 | goto out_drop; | |
6613 | else if (tso) | |
66f32a8b AD |
6614 | tx_flags |= IXGBE_TX_FLAGS_FSO | |
6615 | IXGBE_TX_FLAGS_FCOE; | |
6616 | else | |
6617 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
9a799d71 | 6618 | |
66f32a8b | 6619 | goto xmit_fcoe; |
eacd73f7 | 6620 | } |
9a799d71 | 6621 | |
66f32a8b AD |
6622 | #endif /* IXGBE_FCOE */ |
6623 | /* setup IPv4/IPv6 offloads */ | |
6624 | if (protocol == __constant_htons(ETH_P_IP)) | |
6625 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
9a799d71 | 6626 | |
66f32a8b AD |
6627 | tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len); |
6628 | if (tso < 0) | |
897ab156 | 6629 | goto out_drop; |
66f32a8b AD |
6630 | else if (tso) |
6631 | tx_flags |= IXGBE_TX_FLAGS_TSO; | |
6632 | else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol)) | |
6633 | tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
6634 | ||
6635 | /* add the ATR filter if ATR is on */ | |
6636 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
6637 | ixgbe_atr(tx_ring, skb, tx_flags, protocol); | |
6638 | ||
6639 | #ifdef IXGBE_FCOE | |
6640 | xmit_fcoe: | |
6641 | #endif /* IXGBE_FCOE */ | |
d3d00239 AD |
6642 | ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len); |
6643 | ||
6644 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
6645 | |
6646 | return NETDEV_TX_OK; | |
897ab156 AD |
6647 | |
6648 | out_drop: | |
6649 | dev_kfree_skb_any(skb); | |
6650 | return NETDEV_TX_OK; | |
9a799d71 AK |
6651 | } |
6652 | ||
84418e3b AD |
6653 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) |
6654 | { | |
6655 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6656 | struct ixgbe_ring *tx_ring; | |
6657 | ||
6658 | tx_ring = adapter->tx_ring[skb->queue_mapping]; | |
fc77dc3c | 6659 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6660 | } |
6661 | ||
9a799d71 AK |
6662 | /** |
6663 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6664 | * @netdev: network interface device structure | |
6665 | * @p: pointer to an address structure | |
6666 | * | |
6667 | * Returns 0 on success, negative on failure | |
6668 | **/ | |
6669 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6670 | { | |
6671 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6672 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6673 | struct sockaddr *addr = p; |
6674 | ||
6675 | if (!is_valid_ether_addr(addr->sa_data)) | |
6676 | return -EADDRNOTAVAIL; | |
6677 | ||
6678 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6679 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6680 | |
1cdd1ec8 GR |
6681 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6682 | IXGBE_RAH_AV); | |
9a799d71 AK |
6683 | |
6684 | return 0; | |
6685 | } | |
6686 | ||
6b73e10d BH |
6687 | static int |
6688 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6689 | { | |
6690 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6691 | struct ixgbe_hw *hw = &adapter->hw; | |
6692 | u16 value; | |
6693 | int rc; | |
6694 | ||
6695 | if (prtad != hw->phy.mdio.prtad) | |
6696 | return -EINVAL; | |
6697 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6698 | if (!rc) | |
6699 | rc = value; | |
6700 | return rc; | |
6701 | } | |
6702 | ||
6703 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6704 | u16 addr, u16 value) | |
6705 | { | |
6706 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6707 | struct ixgbe_hw *hw = &adapter->hw; | |
6708 | ||
6709 | if (prtad != hw->phy.mdio.prtad) | |
6710 | return -EINVAL; | |
6711 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6712 | } | |
6713 | ||
6714 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6715 | { | |
6716 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6717 | ||
6718 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6719 | } | |
6720 | ||
0365e6e4 PW |
6721 | /** |
6722 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6723 | * netdev->dev_addrs |
0365e6e4 PW |
6724 | * @netdev: network interface device structure |
6725 | * | |
6726 | * Returns non-zero on failure | |
6727 | **/ | |
6728 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6729 | { | |
6730 | int err = 0; | |
6731 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6732 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6733 | ||
6734 | if (is_valid_ether_addr(mac->san_addr)) { | |
6735 | rtnl_lock(); | |
6736 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6737 | rtnl_unlock(); | |
6738 | } | |
6739 | return err; | |
6740 | } | |
6741 | ||
6742 | /** | |
6743 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6744 | * netdev->dev_addrs |
0365e6e4 PW |
6745 | * @netdev: network interface device structure |
6746 | * | |
6747 | * Returns non-zero on failure | |
6748 | **/ | |
6749 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6750 | { | |
6751 | int err = 0; | |
6752 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6753 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6754 | ||
6755 | if (is_valid_ether_addr(mac->san_addr)) { | |
6756 | rtnl_lock(); | |
6757 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6758 | rtnl_unlock(); | |
6759 | } | |
6760 | return err; | |
6761 | } | |
6762 | ||
9a799d71 AK |
6763 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6764 | /* | |
6765 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6766 | * without having to re-enable interrupts. It's not called while | |
6767 | * the interrupt routine is executing. | |
6768 | */ | |
6769 | static void ixgbe_netpoll(struct net_device *netdev) | |
6770 | { | |
6771 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6772 | int i; |
9a799d71 | 6773 | |
1a647bd2 AD |
6774 | /* if interface is down do nothing */ |
6775 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6776 | return; | |
6777 | ||
9a799d71 | 6778 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
6779 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
6780 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
6781 | for (i = 0; i < num_q_vectors; i++) { | |
6782 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
4ff7fb12 | 6783 | ixgbe_msix_clean_rings(0, q_vector); |
8f9a7167 PWJ |
6784 | } |
6785 | } else { | |
6786 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6787 | } | |
9a799d71 | 6788 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
6789 | } |
6790 | #endif | |
6791 | ||
de1036b1 ED |
6792 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6793 | struct rtnl_link_stats64 *stats) | |
6794 | { | |
6795 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6796 | int i; | |
6797 | ||
1a51502b | 6798 | rcu_read_lock(); |
de1036b1 | 6799 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6800 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6801 | u64 bytes, packets; |
6802 | unsigned int start; | |
6803 | ||
1a51502b ED |
6804 | if (ring) { |
6805 | do { | |
6806 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6807 | packets = ring->stats.packets; | |
6808 | bytes = ring->stats.bytes; | |
6809 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6810 | stats->rx_packets += packets; | |
6811 | stats->rx_bytes += bytes; | |
6812 | } | |
de1036b1 | 6813 | } |
1ac9ad13 ED |
6814 | |
6815 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6816 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
6817 | u64 bytes, packets; | |
6818 | unsigned int start; | |
6819 | ||
6820 | if (ring) { | |
6821 | do { | |
6822 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6823 | packets = ring->stats.packets; | |
6824 | bytes = ring->stats.bytes; | |
6825 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6826 | stats->tx_packets += packets; | |
6827 | stats->tx_bytes += bytes; | |
6828 | } | |
6829 | } | |
1a51502b | 6830 | rcu_read_unlock(); |
de1036b1 ED |
6831 | /* following stats updated by ixgbe_watchdog_task() */ |
6832 | stats->multicast = netdev->stats.multicast; | |
6833 | stats->rx_errors = netdev->stats.rx_errors; | |
6834 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6835 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6836 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6837 | return stats; | |
6838 | } | |
6839 | ||
8b1c0b24 JF |
6840 | /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. |
6841 | * #adapter: pointer to ixgbe_adapter | |
6842 | * @tc: number of traffic classes currently enabled | |
6843 | * | |
6844 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
6845 | * 802.1Q priority maps to a packet buffer that exists. | |
6846 | */ | |
6847 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
6848 | { | |
6849 | struct ixgbe_hw *hw = &adapter->hw; | |
6850 | u32 reg, rsave; | |
6851 | int i; | |
6852 | ||
6853 | /* 82598 have a static priority to TC mapping that can not | |
6854 | * be changed so no validation is needed. | |
6855 | */ | |
6856 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6857 | return; | |
6858 | ||
6859 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
6860 | rsave = reg; | |
6861 | ||
6862 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
6863 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
6864 | ||
6865 | /* If up2tc is out of bounds default to zero */ | |
6866 | if (up2tc > tc) | |
6867 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
6868 | } | |
6869 | ||
6870 | if (reg != rsave) | |
6871 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
6872 | ||
6873 | return; | |
6874 | } | |
6875 | ||
6876 | ||
6877 | /* ixgbe_setup_tc - routine to configure net_device for multiple traffic | |
6878 | * classes. | |
6879 | * | |
6880 | * @netdev: net device to configure | |
6881 | * @tc: number of traffic classes to enable | |
6882 | */ | |
6883 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
6884 | { | |
8b1c0b24 JF |
6885 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
6886 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 6887 | |
e7589eab JF |
6888 | /* Multiple traffic classes requires multiple queues */ |
6889 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { | |
6890 | e_err(drv, "Enable failed, needs MSI-X\n"); | |
6891 | return -EINVAL; | |
6892 | } | |
8b1c0b24 JF |
6893 | |
6894 | /* Hardware supports up to 8 traffic classes */ | |
6895 | if (tc > MAX_TRAFFIC_CLASS || | |
6896 | (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS)) | |
6897 | return -EINVAL; | |
6898 | ||
6899 | /* Hardware has to reinitialize queues and interrupts to | |
6900 | * match packet buffer alignment. Unfortunantly, the | |
6901 | * hardware is not flexible enough to do this dynamically. | |
6902 | */ | |
6903 | if (netif_running(dev)) | |
6904 | ixgbe_close(dev); | |
6905 | ixgbe_clear_interrupt_scheme(adapter); | |
6906 | ||
e7589eab | 6907 | if (tc) { |
8b1c0b24 | 6908 | netdev_set_num_tc(dev, tc); |
e7589eab JF |
6909 | adapter->last_lfc_mode = adapter->hw.fc.current_mode; |
6910 | ||
6911 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; | |
6912 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6913 | ||
6914 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
6915 | adapter->hw.fc.requested_mode = ixgbe_fc_none; | |
6916 | } else { | |
8b1c0b24 JF |
6917 | netdev_reset_tc(dev); |
6918 | ||
e7589eab JF |
6919 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; |
6920 | ||
6921 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
6922 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6923 | ||
6924 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
6925 | adapter->dcb_cfg.pfc_mode_enable = false; | |
6926 | } | |
6927 | ||
8b1c0b24 JF |
6928 | ixgbe_init_interrupt_scheme(adapter); |
6929 | ixgbe_validate_rtr(adapter, tc); | |
6930 | if (netif_running(dev)) | |
6931 | ixgbe_open(dev); | |
6932 | ||
6933 | return 0; | |
6934 | } | |
de1036b1 | 6935 | |
082757af DS |
6936 | void ixgbe_do_reset(struct net_device *netdev) |
6937 | { | |
6938 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6939 | ||
6940 | if (netif_running(netdev)) | |
6941 | ixgbe_reinit_locked(adapter); | |
6942 | else | |
6943 | ixgbe_reset(adapter); | |
6944 | } | |
6945 | ||
6946 | static u32 ixgbe_fix_features(struct net_device *netdev, u32 data) | |
6947 | { | |
6948 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6949 | ||
6950 | #ifdef CONFIG_DCB | |
6951 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
6952 | data &= ~NETIF_F_HW_VLAN_RX; | |
6953 | #endif | |
6954 | ||
6955 | /* return error if RXHASH is being enabled when RSS is not supported */ | |
6956 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) | |
6957 | data &= ~NETIF_F_RXHASH; | |
6958 | ||
6959 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ | |
6960 | if (!(data & NETIF_F_RXCSUM)) | |
6961 | data &= ~NETIF_F_LRO; | |
6962 | ||
6963 | /* Turn off LRO if not RSC capable or invalid ITR settings */ | |
6964 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) { | |
6965 | data &= ~NETIF_F_LRO; | |
6966 | } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && | |
6967 | (adapter->rx_itr_setting != 1 && | |
6968 | adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) { | |
6969 | data &= ~NETIF_F_LRO; | |
6970 | e_info(probe, "rx-usecs set too low, not enabling RSC\n"); | |
6971 | } | |
6972 | ||
6973 | return data; | |
6974 | } | |
6975 | ||
6976 | static int ixgbe_set_features(struct net_device *netdev, u32 data) | |
6977 | { | |
6978 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6979 | bool need_reset = false; | |
6980 | ||
6981 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ | |
6982 | if (!(data & NETIF_F_RXCSUM)) | |
6983 | adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED; | |
6984 | else | |
6985 | adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED; | |
6986 | ||
6987 | /* Make sure RSC matches LRO, reset if change */ | |
6988 | if (!!(data & NETIF_F_LRO) != | |
6989 | !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
6990 | adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED; | |
6991 | switch (adapter->hw.mac.type) { | |
6992 | case ixgbe_mac_X540: | |
6993 | case ixgbe_mac_82599EB: | |
6994 | need_reset = true; | |
6995 | break; | |
6996 | default: | |
6997 | break; | |
6998 | } | |
6999 | } | |
7000 | ||
7001 | /* | |
7002 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
7003 | * the state changed, we need to reset. | |
7004 | */ | |
7005 | if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
7006 | /* turn off ATR, enable perfect filters and reset */ | |
7007 | if (data & NETIF_F_NTUPLE) { | |
7008 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7009 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
7010 | need_reset = true; | |
7011 | } | |
7012 | } else if (!(data & NETIF_F_NTUPLE)) { | |
7013 | /* turn off Flow Director, set ATR and reset */ | |
7014 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
7015 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && | |
7016 | !(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
7017 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7018 | need_reset = true; | |
7019 | } | |
7020 | ||
7021 | if (need_reset) | |
7022 | ixgbe_do_reset(netdev); | |
7023 | ||
7024 | return 0; | |
7025 | ||
7026 | } | |
7027 | ||
0edc3527 | 7028 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 7029 | .ndo_open = ixgbe_open, |
0edc3527 | 7030 | .ndo_stop = ixgbe_close, |
00829823 | 7031 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 7032 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 7033 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
7034 | .ndo_validate_addr = eth_validate_addr, |
7035 | .ndo_set_mac_address = ixgbe_set_mac, | |
7036 | .ndo_change_mtu = ixgbe_change_mtu, | |
7037 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
7038 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
7039 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 7040 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
7041 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
7042 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
7043 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
7044 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, | |
de1036b1 | 7045 | .ndo_get_stats64 = ixgbe_get_stats64, |
24095aa3 | 7046 | .ndo_setup_tc = ixgbe_setup_tc, |
0edc3527 SH |
7047 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7048 | .ndo_poll_controller = ixgbe_netpoll, | |
7049 | #endif | |
332d4a7d YZ |
7050 | #ifdef IXGBE_FCOE |
7051 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 7052 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 7053 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
7054 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
7055 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 7056 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
332d4a7d | 7057 | #endif /* IXGBE_FCOE */ |
082757af DS |
7058 | .ndo_set_features = ixgbe_set_features, |
7059 | .ndo_fix_features = ixgbe_fix_features, | |
0edc3527 SH |
7060 | }; |
7061 | ||
1cdd1ec8 GR |
7062 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
7063 | const struct ixgbe_info *ii) | |
7064 | { | |
7065 | #ifdef CONFIG_PCI_IOV | |
7066 | struct ixgbe_hw *hw = &adapter->hw; | |
7067 | int err; | |
a1cbb15c GR |
7068 | int num_vf_macvlans, i; |
7069 | struct vf_macvlans *mv_list; | |
1cdd1ec8 | 7070 | |
3377eba7 | 7071 | if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs) |
1cdd1ec8 GR |
7072 | return; |
7073 | ||
7074 | /* The 82599 supports up to 64 VFs per physical function | |
7075 | * but this implementation limits allocation to 63 so that | |
7076 | * basic networking resources are still available to the | |
7077 | * physical function | |
7078 | */ | |
7079 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
7080 | adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED; | |
7081 | err = pci_enable_sriov(adapter->pdev, adapter->num_vfs); | |
7082 | if (err) { | |
396e799c | 7083 | e_err(probe, "Failed to enable PCI sriov: %d\n", err); |
1cdd1ec8 GR |
7084 | goto err_novfs; |
7085 | } | |
a1cbb15c GR |
7086 | |
7087 | num_vf_macvlans = hw->mac.num_rar_entries - | |
7088 | (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs); | |
7089 | ||
7090 | adapter->mv_list = mv_list = kcalloc(num_vf_macvlans, | |
7091 | sizeof(struct vf_macvlans), | |
7092 | GFP_KERNEL); | |
7093 | if (mv_list) { | |
7094 | /* Initialize list of VF macvlans */ | |
7095 | INIT_LIST_HEAD(&adapter->vf_mvs.l); | |
7096 | for (i = 0; i < num_vf_macvlans; i++) { | |
7097 | mv_list->vf = -1; | |
7098 | mv_list->free = true; | |
7099 | mv_list->rar_entry = hw->mac.num_rar_entries - | |
7100 | (i + adapter->num_vfs + 1); | |
7101 | list_add(&mv_list->l, &adapter->vf_mvs.l); | |
7102 | mv_list++; | |
7103 | } | |
7104 | } | |
7105 | ||
1cdd1ec8 GR |
7106 | /* If call to enable VFs succeeded then allocate memory |
7107 | * for per VF control structures. | |
7108 | */ | |
7109 | adapter->vfinfo = | |
7110 | kcalloc(adapter->num_vfs, | |
7111 | sizeof(struct vf_data_storage), GFP_KERNEL); | |
7112 | if (adapter->vfinfo) { | |
7113 | /* Now that we're sure SR-IOV is enabled | |
7114 | * and memory allocated set up the mailbox parameters | |
7115 | */ | |
7116 | ixgbe_init_mbx_params_pf(hw); | |
7117 | memcpy(&hw->mbx.ops, ii->mbx_ops, | |
7118 | sizeof(hw->mbx.ops)); | |
7119 | ||
7120 | /* Disable RSC when in SR-IOV mode */ | |
7121 | adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE | | |
7122 | IXGBE_FLAG2_RSC_ENABLED); | |
7123 | return; | |
7124 | } | |
7125 | ||
7126 | /* Oh oh */ | |
396e799c ET |
7127 | e_err(probe, "Unable to allocate memory for VF Data Storage - " |
7128 | "SRIOV disabled\n"); | |
1cdd1ec8 GR |
7129 | pci_disable_sriov(adapter->pdev); |
7130 | ||
7131 | err_novfs: | |
7132 | adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED; | |
7133 | adapter->num_vfs = 0; | |
7134 | #endif /* CONFIG_PCI_IOV */ | |
7135 | } | |
7136 | ||
9a799d71 AK |
7137 | /** |
7138 | * ixgbe_probe - Device Initialization Routine | |
7139 | * @pdev: PCI device information struct | |
7140 | * @ent: entry in ixgbe_pci_tbl | |
7141 | * | |
7142 | * Returns 0 on success, negative on failure | |
7143 | * | |
7144 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7145 | * The OS initialization, configuring of the adapter private structure, | |
7146 | * and a hardware reset occur. | |
7147 | **/ | |
7148 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7149 | const struct pci_device_id *ent) |
9a799d71 AK |
7150 | { |
7151 | struct net_device *netdev; | |
7152 | struct ixgbe_adapter *adapter = NULL; | |
7153 | struct ixgbe_hw *hw; | |
7154 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7155 | static int cards_found; |
7156 | int i, err, pci_using_dac; | |
289700db | 7157 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7158 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
7159 | #ifdef IXGBE_FCOE |
7160 | u16 device_caps; | |
7161 | #endif | |
289700db | 7162 | u32 eec; |
9a799d71 | 7163 | |
bded64a7 AG |
7164 | /* Catch broken hardware that put the wrong VF device ID in |
7165 | * the PCIe SR-IOV capability. | |
7166 | */ | |
7167 | if (pdev->is_virtfn) { | |
7168 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7169 | pci_name(pdev), pdev->vendor, pdev->device); | |
7170 | return -EINVAL; | |
7171 | } | |
7172 | ||
9ce77666 | 7173 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7174 | if (err) |
7175 | return err; | |
7176 | ||
1b507730 NN |
7177 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7178 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7179 | pci_using_dac = 1; |
7180 | } else { | |
1b507730 | 7181 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7182 | if (err) { |
1b507730 NN |
7183 | err = dma_set_coherent_mask(&pdev->dev, |
7184 | DMA_BIT_MASK(32)); | |
9a799d71 | 7185 | if (err) { |
b8bc0421 DC |
7186 | dev_err(&pdev->dev, |
7187 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7188 | goto err_dma; |
7189 | } | |
7190 | } | |
7191 | pci_using_dac = 0; | |
7192 | } | |
7193 | ||
9ce77666 | 7194 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7195 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7196 | if (err) { |
b8bc0421 DC |
7197 | dev_err(&pdev->dev, |
7198 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7199 | goto err_pci_reg; |
7200 | } | |
7201 | ||
19d5afd4 | 7202 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7203 | |
9a799d71 | 7204 | pci_set_master(pdev); |
fb3b27bc | 7205 | pci_save_state(pdev); |
9a799d71 | 7206 | |
e901acd6 JF |
7207 | #ifdef CONFIG_IXGBE_DCB |
7208 | indices *= MAX_TRAFFIC_CLASS; | |
7209 | #endif | |
7210 | ||
c85a2618 JF |
7211 | if (ii->mac == ixgbe_mac_82598EB) |
7212 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
7213 | else | |
7214 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7215 | ||
e901acd6 | 7216 | #ifdef IXGBE_FCOE |
c85a2618 JF |
7217 | indices += min_t(unsigned int, num_possible_cpus(), |
7218 | IXGBE_MAX_FCOE_INDICES); | |
7219 | #endif | |
c85a2618 | 7220 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7221 | if (!netdev) { |
7222 | err = -ENOMEM; | |
7223 | goto err_alloc_etherdev; | |
7224 | } | |
7225 | ||
9a799d71 AK |
7226 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7227 | ||
9a799d71 | 7228 | adapter = netdev_priv(netdev); |
c60fbb00 | 7229 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7230 | |
7231 | adapter->netdev = netdev; | |
7232 | adapter->pdev = pdev; | |
7233 | hw = &adapter->hw; | |
7234 | hw->back = adapter; | |
7235 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
7236 | ||
05857980 | 7237 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7238 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7239 | if (!hw->hw_addr) { |
7240 | err = -EIO; | |
7241 | goto err_ioremap; | |
7242 | } | |
7243 | ||
7244 | for (i = 1; i <= 5; i++) { | |
7245 | if (pci_resource_len(pdev, i) == 0) | |
7246 | continue; | |
7247 | } | |
7248 | ||
0edc3527 | 7249 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7250 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7251 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7252 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7253 | |
9a799d71 AK |
7254 | adapter->bd_number = cards_found; |
7255 | ||
9a799d71 AK |
7256 | /* Setup hw api */ |
7257 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7258 | hw->mac.type = ii->mac; |
9a799d71 | 7259 | |
c44ade9e JB |
7260 | /* EEPROM */ |
7261 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7262 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7263 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7264 | if (!(eec & (1 << 8))) | |
7265 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7266 | ||
7267 | /* PHY */ | |
7268 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7269 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7270 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7271 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7272 | hw->phy.mdio.mmds = 0; | |
7273 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7274 | hw->phy.mdio.dev = netdev; | |
7275 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7276 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 7277 | |
8ca783ab | 7278 | ii->get_invariants(hw); |
9a799d71 AK |
7279 | |
7280 | /* setup the private structure */ | |
7281 | err = ixgbe_sw_init(adapter); | |
7282 | if (err) | |
7283 | goto err_sw_init; | |
7284 | ||
e86bff0e | 7285 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7286 | switch (adapter->hw.mac.type) { |
7287 | case ixgbe_mac_82599EB: | |
7288 | case ixgbe_mac_X540: | |
e86bff0e | 7289 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7290 | break; |
7291 | default: | |
7292 | break; | |
7293 | } | |
e86bff0e | 7294 | |
bf069c97 DS |
7295 | /* |
7296 | * If there is a fan on this device and it has failed log the | |
7297 | * failure. | |
7298 | */ | |
7299 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7300 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7301 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7302 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7303 | } |
7304 | ||
c44ade9e | 7305 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7306 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7307 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7308 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7309 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7310 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7311 | err = 0; |
7312 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7313 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7314 | "module type was detected.\n"); |
7315 | e_dev_err("Reload the driver after installing a supported " | |
7316 | "module.\n"); | |
04f165ef PW |
7317 | goto err_sw_init; |
7318 | } else if (err) { | |
849c4542 | 7319 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7320 | goto err_sw_init; |
7321 | } | |
7322 | ||
1cdd1ec8 GR |
7323 | ixgbe_probe_vf(adapter, ii); |
7324 | ||
396e799c | 7325 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7326 | NETIF_F_IP_CSUM | |
082757af | 7327 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7328 | NETIF_F_HW_VLAN_TX | |
7329 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7330 | NETIF_F_HW_VLAN_FILTER | |
7331 | NETIF_F_TSO | | |
7332 | NETIF_F_TSO6 | | |
082757af DS |
7333 | NETIF_F_RXHASH | |
7334 | NETIF_F_RXCSUM; | |
9a799d71 | 7335 | |
082757af | 7336 | netdev->hw_features = netdev->features; |
ad31c402 | 7337 | |
58be7666 DS |
7338 | switch (adapter->hw.mac.type) { |
7339 | case ixgbe_mac_82599EB: | |
7340 | case ixgbe_mac_X540: | |
45a5ead0 | 7341 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7342 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7343 | NETIF_F_NTUPLE; | |
58be7666 DS |
7344 | break; |
7345 | default: | |
7346 | break; | |
7347 | } | |
45a5ead0 | 7348 | |
ad31c402 JK |
7349 | netdev->vlan_features |= NETIF_F_TSO; |
7350 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7351 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7352 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7353 | netdev->vlan_features |= NETIF_F_SG; |
7354 | ||
01789349 JP |
7355 | netdev->priv_flags |= IFF_UNICAST_FLT; |
7356 | ||
1cdd1ec8 GR |
7357 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7358 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7359 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 | 7360 | |
7a6b6f51 | 7361 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7362 | netdev->dcbnl_ops = &dcbnl_ops; |
7363 | #endif | |
7364 | ||
eacd73f7 | 7365 | #ifdef IXGBE_FCOE |
0d551589 | 7366 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7367 | if (hw->mac.ops.get_device_caps) { |
7368 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7369 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7370 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7371 | } |
7372 | } | |
5e09d7f6 YZ |
7373 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7374 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7375 | netdev->vlan_features |= NETIF_F_FSO; | |
7376 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7377 | } | |
eacd73f7 | 7378 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7379 | if (pci_using_dac) { |
9a799d71 | 7380 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7381 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7382 | } | |
9a799d71 | 7383 | |
082757af DS |
7384 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7385 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7386 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7387 | netdev->features |= NETIF_F_LRO; |
7388 | ||
9a799d71 | 7389 | /* make sure the EEPROM is good */ |
c44ade9e | 7390 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7391 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 AK |
7392 | err = -EIO; |
7393 | goto err_eeprom; | |
7394 | } | |
7395 | ||
7396 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7397 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7398 | ||
c44ade9e | 7399 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7400 | e_dev_err("invalid MAC address\n"); |
9a799d71 AK |
7401 | err = -EIO; |
7402 | goto err_eeprom; | |
7403 | } | |
7404 | ||
c6ecf39a DS |
7405 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7406 | if (hw->mac.ops.disable_tx_laser && | |
7407 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 7408 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 7409 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
7410 | hw->mac.ops.disable_tx_laser(hw); |
7411 | ||
7086400d AD |
7412 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
7413 | (unsigned long) adapter); | |
9a799d71 | 7414 | |
7086400d AD |
7415 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7416 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7417 | |
021230d4 AV |
7418 | err = ixgbe_init_interrupt_scheme(adapter); |
7419 | if (err) | |
7420 | goto err_sw_init; | |
9a799d71 | 7421 | |
082757af DS |
7422 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { |
7423 | netdev->hw_features &= ~NETIF_F_RXHASH; | |
67a74ee2 | 7424 | netdev->features &= ~NETIF_F_RXHASH; |
082757af | 7425 | } |
67a74ee2 | 7426 | |
e8e26350 | 7427 | switch (pdev->device) { |
0b077fea DS |
7428 | case IXGBE_DEV_ID_82599_SFP: |
7429 | /* Only this subdevice supports WOL */ | |
7430 | if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP) | |
9417c464 | 7431 | adapter->wol = IXGBE_WUFC_MAG; |
0b077fea | 7432 | break; |
50d6c681 AD |
7433 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
7434 | /* All except this subdevice support WOL */ | |
0b077fea | 7435 | if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) |
9417c464 | 7436 | adapter->wol = IXGBE_WUFC_MAG; |
0b077fea | 7437 | break; |
e8e26350 | 7438 | case IXGBE_DEV_ID_82599_KX4: |
9417c464 | 7439 | adapter->wol = IXGBE_WUFC_MAG; |
e8e26350 PW |
7440 | break; |
7441 | default: | |
7442 | adapter->wol = 0; | |
7443 | break; | |
7444 | } | |
e8e26350 PW |
7445 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7446 | ||
04f165ef PW |
7447 | /* pick up the PCI bus settings for reporting later */ |
7448 | hw->mac.ops.get_bus_info(hw); | |
7449 | ||
9a799d71 | 7450 | /* print bus type/speed/width info */ |
849c4542 | 7451 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7452 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7453 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7454 | "Unknown"), |
7455 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7456 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7457 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7458 | "Unknown"), | |
7459 | netdev->dev_addr); | |
289700db DS |
7460 | |
7461 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7462 | if (err) | |
9fe93afd | 7463 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7464 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7465 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7466 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7467 | part_str); |
e8e26350 | 7468 | else |
289700db DS |
7469 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7470 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7471 | |
e8e26350 | 7472 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7473 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7474 | "not sufficient for optimal performance.\n"); | |
7475 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7476 | "is required.\n"); | |
0c254d86 AK |
7477 | } |
7478 | ||
34b0368c PWJ |
7479 | /* save off EEPROM version number */ |
7480 | hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version); | |
7481 | ||
9a799d71 | 7482 | /* reset the hardware with the new settings */ |
794caeb2 | 7483 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 7484 | |
794caeb2 PWJ |
7485 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7486 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7487 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7488 | "Please be aware there may be issues associated " | |
7489 | "with your hardware. If you are experiencing " | |
7490 | "problems please contact your Intel or hardware " | |
7491 | "representative who provided you with this " | |
7492 | "hardware.\n"); | |
794caeb2 | 7493 | } |
9a799d71 AK |
7494 | strcpy(netdev->name, "eth%d"); |
7495 | err = register_netdev(netdev); | |
7496 | if (err) | |
7497 | goto err_register; | |
7498 | ||
54386467 JB |
7499 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7500 | netif_carrier_off(netdev); | |
7501 | ||
5dd2d332 | 7502 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7503 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7504 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7505 | ixgbe_setup_dca(adapter); |
7506 | } | |
7507 | #endif | |
1cdd1ec8 | 7508 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7509 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7510 | for (i = 0; i < adapter->num_vfs; i++) |
7511 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7512 | } | |
7513 | ||
9612de92 ET |
7514 | /* Inform firmware of driver version */ |
7515 | if (hw->mac.ops.set_fw_drv_ver) | |
a38a104d DS |
7516 | hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD, |
7517 | FW_CEM_UNUSED_VER); | |
9612de92 | 7518 | |
0365e6e4 PW |
7519 | /* add san mac addr to netdev */ |
7520 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7521 | |
849c4542 | 7522 | e_dev_info("Intel(R) 10 Gigabit Network Connection\n"); |
9a799d71 AK |
7523 | cards_found++; |
7524 | return 0; | |
7525 | ||
7526 | err_register: | |
5eba3699 | 7527 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7528 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
7529 | err_sw_init: |
7530 | err_eeprom: | |
1cdd1ec8 GR |
7531 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7532 | ixgbe_disable_sriov(adapter); | |
7086400d | 7533 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
7534 | iounmap(hw->hw_addr); |
7535 | err_ioremap: | |
7536 | free_netdev(netdev); | |
7537 | err_alloc_etherdev: | |
e8e9f696 JP |
7538 | pci_release_selected_regions(pdev, |
7539 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7540 | err_pci_reg: |
7541 | err_dma: | |
7542 | pci_disable_device(pdev); | |
7543 | return err; | |
7544 | } | |
7545 | ||
7546 | /** | |
7547 | * ixgbe_remove - Device Removal Routine | |
7548 | * @pdev: PCI device information struct | |
7549 | * | |
7550 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7551 | * that it should release a PCI device. The could be caused by a | |
7552 | * Hot-Plug event, or because the driver is going to be removed from | |
7553 | * memory. | |
7554 | **/ | |
7555 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7556 | { | |
c60fbb00 AD |
7557 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7558 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7559 | |
7560 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 7561 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 7562 | |
5dd2d332 | 7563 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7564 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7565 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7566 | dca_remove_requester(&pdev->dev); | |
7567 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7568 | } | |
7569 | ||
7570 | #endif | |
332d4a7d YZ |
7571 | #ifdef IXGBE_FCOE |
7572 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7573 | ixgbe_cleanup_fcoe(adapter); | |
7574 | ||
7575 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7576 | |
7577 | /* remove the added san mac */ | |
7578 | ixgbe_del_sanmac_netdev(netdev); | |
7579 | ||
c4900be0 DS |
7580 | if (netdev->reg_state == NETREG_REGISTERED) |
7581 | unregister_netdev(netdev); | |
9a799d71 | 7582 | |
1cdd1ec8 GR |
7583 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7584 | ixgbe_disable_sriov(adapter); | |
7585 | ||
7a921c93 | 7586 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7587 | |
021230d4 | 7588 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
7589 | |
7590 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 7591 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7592 | IORESOURCE_MEM)); |
9a799d71 | 7593 | |
849c4542 | 7594 | e_dev_info("complete\n"); |
021230d4 | 7595 | |
9a799d71 AK |
7596 | free_netdev(netdev); |
7597 | ||
19d5afd4 | 7598 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7599 | |
9a799d71 AK |
7600 | pci_disable_device(pdev); |
7601 | } | |
7602 | ||
7603 | /** | |
7604 | * ixgbe_io_error_detected - called when PCI error is detected | |
7605 | * @pdev: Pointer to PCI device | |
7606 | * @state: The current pci connection state | |
7607 | * | |
7608 | * This function is called after a PCI bus error affecting | |
7609 | * this device has been detected. | |
7610 | */ | |
7611 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7612 | pci_channel_state_t state) |
9a799d71 | 7613 | { |
c60fbb00 AD |
7614 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7615 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7616 | |
7617 | netif_device_detach(netdev); | |
7618 | ||
3044b8d1 BL |
7619 | if (state == pci_channel_io_perm_failure) |
7620 | return PCI_ERS_RESULT_DISCONNECT; | |
7621 | ||
9a799d71 AK |
7622 | if (netif_running(netdev)) |
7623 | ixgbe_down(adapter); | |
7624 | pci_disable_device(pdev); | |
7625 | ||
b4617240 | 7626 | /* Request a slot reset. */ |
9a799d71 AK |
7627 | return PCI_ERS_RESULT_NEED_RESET; |
7628 | } | |
7629 | ||
7630 | /** | |
7631 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7632 | * @pdev: Pointer to PCI device | |
7633 | * | |
7634 | * Restart the card from scratch, as if from a cold-boot. | |
7635 | */ | |
7636 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7637 | { | |
c60fbb00 | 7638 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7639 | pci_ers_result_t result; |
7640 | int err; | |
9a799d71 | 7641 | |
9ce77666 | 7642 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7643 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7644 | result = PCI_ERS_RESULT_DISCONNECT; |
7645 | } else { | |
7646 | pci_set_master(pdev); | |
7647 | pci_restore_state(pdev); | |
c0e1f68b | 7648 | pci_save_state(pdev); |
9a799d71 | 7649 | |
dd4d8ca6 | 7650 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7651 | |
6fabd715 | 7652 | ixgbe_reset(adapter); |
88512539 | 7653 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7654 | result = PCI_ERS_RESULT_RECOVERED; |
7655 | } | |
7656 | ||
7657 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7658 | if (err) { | |
849c4542 ET |
7659 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7660 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7661 | /* non-fatal, continue */ |
7662 | } | |
9a799d71 | 7663 | |
6fabd715 | 7664 | return result; |
9a799d71 AK |
7665 | } |
7666 | ||
7667 | /** | |
7668 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7669 | * @pdev: Pointer to PCI device | |
7670 | * | |
7671 | * This callback is called when the error recovery driver tells us that | |
7672 | * its OK to resume normal operation. | |
7673 | */ | |
7674 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7675 | { | |
c60fbb00 AD |
7676 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7677 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7678 | |
c7ccde0f AD |
7679 | if (netif_running(netdev)) |
7680 | ixgbe_up(adapter); | |
9a799d71 AK |
7681 | |
7682 | netif_device_attach(netdev); | |
9a799d71 AK |
7683 | } |
7684 | ||
7685 | static struct pci_error_handlers ixgbe_err_handler = { | |
7686 | .error_detected = ixgbe_io_error_detected, | |
7687 | .slot_reset = ixgbe_io_slot_reset, | |
7688 | .resume = ixgbe_io_resume, | |
7689 | }; | |
7690 | ||
7691 | static struct pci_driver ixgbe_driver = { | |
7692 | .name = ixgbe_driver_name, | |
7693 | .id_table = ixgbe_pci_tbl, | |
7694 | .probe = ixgbe_probe, | |
7695 | .remove = __devexit_p(ixgbe_remove), | |
7696 | #ifdef CONFIG_PM | |
7697 | .suspend = ixgbe_suspend, | |
7698 | .resume = ixgbe_resume, | |
7699 | #endif | |
7700 | .shutdown = ixgbe_shutdown, | |
7701 | .err_handler = &ixgbe_err_handler | |
7702 | }; | |
7703 | ||
7704 | /** | |
7705 | * ixgbe_init_module - Driver Registration Routine | |
7706 | * | |
7707 | * ixgbe_init_module is the first routine called when the driver is | |
7708 | * loaded. All it does is register with the PCI subsystem. | |
7709 | **/ | |
7710 | static int __init ixgbe_init_module(void) | |
7711 | { | |
7712 | int ret; | |
c7689578 | 7713 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7714 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7715 | |
5dd2d332 | 7716 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7717 | dca_register_notify(&dca_notifier); |
bd0362dd | 7718 | #endif |
5dd2d332 | 7719 | |
9a799d71 AK |
7720 | ret = pci_register_driver(&ixgbe_driver); |
7721 | return ret; | |
7722 | } | |
b4617240 | 7723 | |
9a799d71 AK |
7724 | module_init(ixgbe_init_module); |
7725 | ||
7726 | /** | |
7727 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7728 | * | |
7729 | * ixgbe_exit_module is called just before the driver is removed | |
7730 | * from memory. | |
7731 | **/ | |
7732 | static void __exit ixgbe_exit_module(void) | |
7733 | { | |
5dd2d332 | 7734 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7735 | dca_unregister_notify(&dca_notifier); |
7736 | #endif | |
9a799d71 | 7737 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7738 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7739 | } |
bd0362dd | 7740 | |
5dd2d332 | 7741 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7742 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7743 | void *p) |
bd0362dd JC |
7744 | { |
7745 | int ret_val; | |
7746 | ||
7747 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7748 | __ixgbe_notify_dca); |
bd0362dd JC |
7749 | |
7750 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7751 | } | |
b453368d | 7752 | |
5dd2d332 | 7753 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7754 | |
9a799d71 AK |
7755 | module_exit(ixgbe_exit_module); |
7756 | ||
7757 | /* ixgbe_main.c */ |