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vlan: rename vlan_dev_info to vlan_dev_priv
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 58#define MAJ 3
19d478bb
DS		 59#define MIN 6
60#define BUILD 7
75e3d3c6 61#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 62 __stringify(BUILD) "-k"
9c8eb720 63const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 64static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 66
67static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 68 [board_82598] = &ixgbe_82598_info,
e8e26350 69 [board_82599] = &ixgbe_82599_info,
fe15e8e1 70 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 71};
72
73/* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
a3aa1884 81static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9a799d71
AK		 109 /* required last entry */
110 {0, }
111};
112MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
113
5dd2d332 114#ifdef CONFIG_IXGBE_DCA
bd0362dd 115static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 116 void *p);
bd0362dd
JC		 117static struct notifier_block dca_notifier = {
118 .notifier_call = ixgbe_notify_dca,
119 .next = NULL,
120 .priority = 0
121};
122#endif
123
1cdd1ec8
GR		 124#ifdef CONFIG_PCI_IOV
125static unsigned int max_vfs;
126module_param(max_vfs, uint, 0);
e8e9f696
JP		 127MODULE_PARM_DESC(max_vfs,
128 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 129#endif /* CONFIG_PCI_IOV */
130
9a799d71
AK		 131MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
132MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
133MODULE_LICENSE("GPL");
134MODULE_VERSION(DRV_VERSION);
135
136#define DEFAULT_DEBUG_LEVEL_SHIFT 3
137
7086400d
AD		 138static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
139{
140 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
141 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
142 schedule_work(&adapter->service_task);
143}
144
145static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
146{
147 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
148
149 /* flush memory to make sure state is correct before next watchog */
150 smp_mb__before_clear_bit();
151 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
152}
153
dcd79aeb
TI		 154struct ixgbe_reg_info {
155 u32 ofs;
156 char *name;
157};
158
159static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
160
161 /* General Registers */
162 {IXGBE_CTRL, "CTRL"},
163 {IXGBE_STATUS, "STATUS"},
164 {IXGBE_CTRL_EXT, "CTRL_EXT"},
165
166 /* Interrupt Registers */
167 {IXGBE_EICR, "EICR"},
168
169 /* RX Registers */
170 {IXGBE_SRRCTL(0), "SRRCTL"},
171 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
172 {IXGBE_RDLEN(0), "RDLEN"},
173 {IXGBE_RDH(0), "RDH"},
174 {IXGBE_RDT(0), "RDT"},
175 {IXGBE_RXDCTL(0), "RXDCTL"},
176 {IXGBE_RDBAL(0), "RDBAL"},
177 {IXGBE_RDBAH(0), "RDBAH"},
178
179 /* TX Registers */
180 {IXGBE_TDBAL(0), "TDBAL"},
181 {IXGBE_TDBAH(0), "TDBAH"},
182 {IXGBE_TDLEN(0), "TDLEN"},
183 {IXGBE_TDH(0), "TDH"},
184 {IXGBE_TDT(0), "TDT"},
185 {IXGBE_TXDCTL(0), "TXDCTL"},
186
187 /* List Terminator */
188 {}
189};
190
191
192/*
193 * ixgbe_regdump - register printout routine
194 */
195static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
196{
197 int i = 0, j = 0;
198 char rname[16];
199 u32 regs[64];
200
201 switch (reginfo->ofs) {
202 case IXGBE_SRRCTL(0):
203 for (i = 0; i < 64; i++)
204 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
205 break;
206 case IXGBE_DCA_RXCTRL(0):
207 for (i = 0; i < 64; i++)
208 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
209 break;
210 case IXGBE_RDLEN(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
213 break;
214 case IXGBE_RDH(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
217 break;
218 case IXGBE_RDT(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
221 break;
222 case IXGBE_RXDCTL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
225 break;
226 case IXGBE_RDBAL(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
229 break;
230 case IXGBE_RDBAH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
233 break;
234 case IXGBE_TDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
237 break;
238 case IXGBE_TDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
241 break;
242 case IXGBE_TDLEN(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
245 break;
246 case IXGBE_TDH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
249 break;
250 case IXGBE_TDT(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
253 break;
254 case IXGBE_TXDCTL(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
257 break;
258 default:
c7689578 259 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 260 IXGBE_READ_REG(hw, reginfo->ofs));
261 return;
262 }
263
264 for (i = 0; i < 8; i++) {
265 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 266 pr_err("%-15s", rname);
dcd79aeb 267 for (j = 0; j < 8; j++)
c7689578
JP		 268 pr_cont(" %08x", regs[i*8+j]);
269 pr_cont("\n");
dcd79aeb
TI		 270 }
271
272}
273
274/*
275 * ixgbe_dump - Print registers, tx-rings and rx-rings
276 */
277static void ixgbe_dump(struct ixgbe_adapter *adapter)
278{
279 struct net_device *netdev = adapter->netdev;
280 struct ixgbe_hw *hw = &adapter->hw;
281 struct ixgbe_reg_info *reginfo;
282 int n = 0;
283 struct ixgbe_ring *tx_ring;
284 struct ixgbe_tx_buffer *tx_buffer_info;
285 union ixgbe_adv_tx_desc *tx_desc;
286 struct my_u0 { u64 a; u64 b; } *u0;
287 struct ixgbe_ring *rx_ring;
288 union ixgbe_adv_rx_desc *rx_desc;
289 struct ixgbe_rx_buffer *rx_buffer_info;
290 u32 staterr;
291 int i = 0;
292
293 if (!netif_msg_hw(adapter))
294 return;
295
296 /* Print netdevice Info */
297 if (netdev) {
298 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 299 pr_info("Device Name state "
dcd79aeb 300 "trans_start last_rx\n");
c7689578
JP		 301 pr_info("%-15s %016lX %016lX %016lX\n",
302 netdev->name,
303 netdev->state,
304 netdev->trans_start,
305 netdev->last_rx);
dcd79aeb
TI		 306 }
307
308 /* Print Registers */
309 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 310 pr_info(" Register Name Value\n");
dcd79aeb
TI		 311 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
312 reginfo->name; reginfo++) {
313 ixgbe_regdump(hw, reginfo);
314 }
315
316 /* Print TX Ring Summary */
317 if (!netdev || !netif_running(netdev))
318 goto exit;
319
320 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 321 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 322 for (n = 0; n < adapter->num_tx_queues; n++) {
323 tx_ring = adapter->tx_ring[n];
324 tx_buffer_info =
325 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 326 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 327 n, tx_ring->next_to_use, tx_ring->next_to_clean,
328 (u64)tx_buffer_info->dma,
329 tx_buffer_info->length,
330 tx_buffer_info->next_to_watch,
331 (u64)tx_buffer_info->time_stamp);
332 }
333
334 /* Print TX Rings */
335 if (!netif_msg_tx_done(adapter))
336 goto rx_ring_summary;
337
338 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
339
340 /* Transmit Descriptor Formats
341 *
342 * Advanced Transmit Descriptor
343 * +--------------------------------------------------------------+
344 * 0 | Buffer Address [63:0] |
345 * +--------------------------------------------------------------+
346 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
347 * +--------------------------------------------------------------+
348 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
349 */
350
351 for (n = 0; n < adapter->num_tx_queues; n++) {
352 tx_ring = adapter->tx_ring[n];
c7689578
JP		 353 pr_info("------------------------------------\n");
354 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
355 pr_info("------------------------------------\n");
356 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 357 "[PlPOIdStDDt Ln] [bi->dma ] "
358 "leng ntw timestamp bi->skb\n");
359
360 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 361 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 362 tx_buffer_info = &tx_ring->tx_buffer_info[i];
363 u0 = (struct my_u0 *)tx_desc;
c7689578 364 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 365 " %04X %p %016llX %p", i,
dcd79aeb
TI		 366 le64_to_cpu(u0->a),
367 le64_to_cpu(u0->b),
368 (u64)tx_buffer_info->dma,
369 tx_buffer_info->length,
370 tx_buffer_info->next_to_watch,
371 (u64)tx_buffer_info->time_stamp,
372 tx_buffer_info->skb);
373 if (i == tx_ring->next_to_use &&
374 i == tx_ring->next_to_clean)
c7689578 375 pr_cont(" NTC/U\n");
dcd79aeb 376 else if (i == tx_ring->next_to_use)
c7689578 377 pr_cont(" NTU\n");
dcd79aeb 378 else if (i == tx_ring->next_to_clean)
c7689578 379 pr_cont(" NTC\n");
dcd79aeb 380 else
c7689578 381 pr_cont("\n");
dcd79aeb
TI		 382
383 if (netif_msg_pktdata(adapter) &&
384 tx_buffer_info->dma != 0)
385 print_hex_dump(KERN_INFO, "",
386 DUMP_PREFIX_ADDRESS, 16, 1,
387 phys_to_virt(tx_buffer_info->dma),
388 tx_buffer_info->length, true);
389 }
390 }
391
392 /* Print RX Rings Summary */
393rx_ring_summary:
394 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 395 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 396 for (n = 0; n < adapter->num_rx_queues; n++) {
397 rx_ring = adapter->rx_ring[n];
c7689578
JP		 398 pr_info("%5d %5X %5X\n",
399 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 400 }
401
402 /* Print RX Rings */
403 if (!netif_msg_rx_status(adapter))
404 goto exit;
405
406 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
407
408 /* Advanced Receive Descriptor (Read) Format
409 * 63 1 0
410 * +-----------------------------------------------------+
411 * 0 | Packet Buffer Address [63:1] |A0/NSE|
412 * +----------------------------------------------+------+
413 * 8 | Header Buffer Address [63:1] | DD |
414 * +-----------------------------------------------------+
415 *
416 *
417 * Advanced Receive Descriptor (Write-Back) Format
418 *
419 * 63 48 47 32 31 30 21 20 16 15 4 3 0
420 * +------------------------------------------------------+
421 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
422 * | Checksum Ident | | | | Type | Type |
423 * +------------------------------------------------------+
424 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
425 * +------------------------------------------------------+
426 * 63 48 47 32 31 20 19 0
427 */
428 for (n = 0; n < adapter->num_rx_queues; n++) {
429 rx_ring = adapter->rx_ring[n];
c7689578
JP		 430 pr_info("------------------------------------\n");
431 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
432 pr_info("------------------------------------\n");
433 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 434 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
435 "<-- Adv Rx Read format\n");
c7689578 436 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 437 "[vl er S cks ln] ---------------- [bi->skb] "
438 "<-- Adv Rx Write-Back format\n");
439
440 for (i = 0; i < rx_ring->count; i++) {
441 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 442 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 443 u0 = (struct my_u0 *)rx_desc;
444 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
445 if (staterr & IXGBE_RXD_STAT_DD) {
446 /* Descriptor Done */
c7689578 447 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 448 "%016llX ---------------- %p", i,
449 le64_to_cpu(u0->a),
450 le64_to_cpu(u0->b),
451 rx_buffer_info->skb);
452 } else {
c7689578 453 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 454 "%016llX %016llX %p", i,
455 le64_to_cpu(u0->a),
456 le64_to_cpu(u0->b),
457 (u64)rx_buffer_info->dma,
458 rx_buffer_info->skb);
459
460 if (netif_msg_pktdata(adapter)) {
461 print_hex_dump(KERN_INFO, "",
462 DUMP_PREFIX_ADDRESS, 16, 1,
463 phys_to_virt(rx_buffer_info->dma),
464 rx_ring->rx_buf_len, true);
465
466 if (rx_ring->rx_buf_len
919e78a6 467 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS, 16, 1,
470 phys_to_virt(
471 rx_buffer_info->page_dma +
472 rx_buffer_info->page_offset
473 ),
474 PAGE_SIZE/2, true);
475 }
476 }
477
478 if (i == rx_ring->next_to_use)
c7689578 479 pr_cont(" NTU\n");
dcd79aeb 480 else if (i == rx_ring->next_to_clean)
c7689578 481 pr_cont(" NTC\n");
dcd79aeb 482 else
c7689578 483 pr_cont("\n");
dcd79aeb
TI		 484
485 }
486 }
487
488exit:
489 return;
490}
491
5eba3699
AV		 492static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
493{
494 u32 ctrl_ext;
495
496 /* Let firmware take over control of h/w */
497 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 499 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 500}
501
502static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
503{
504 u32 ctrl_ext;
505
506 /* Let firmware know the driver has taken over */
507 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 509 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 510}
9a799d71 511
e8e26350
PW		 512/*
513 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
514 * @adapter: pointer to adapter struct
515 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
516 * @queue: queue to map the corresponding interrupt to
517 * @msix_vector: the vector to map to the corresponding queue
518 *
519 */
520static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 521 u8 queue, u8 msix_vector)
9a799d71
AK		 522{
523 u32 ivar, index;
e8e26350
PW		 524 struct ixgbe_hw *hw = &adapter->hw;
525 switch (hw->mac.type) {
526 case ixgbe_mac_82598EB:
527 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
528 if (direction == -1)
529 direction = 0;
530 index = (((direction * 64) + queue) >> 2) & 0x1F;
531 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
532 ivar &= ~(0xFF << (8 * (queue & 0x3)));
533 ivar |= (msix_vector << (8 * (queue & 0x3)));
534 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
535 break;
536 case ixgbe_mac_82599EB:
b93a2226 537 case ixgbe_mac_X540:
e8e26350
PW		 538 if (direction == -1) {
539 /* other causes */
540 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
541 index = ((queue & 1) * 8);
542 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
543 ivar &= ~(0xFF << index);
544 ivar |= (msix_vector << index);
545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
546 break;
547 } else {
548 /* tx or rx causes */
549 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
550 index = ((16 * (queue & 1)) + (8 * direction));
551 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
552 ivar &= ~(0xFF << index);
553 ivar |= (msix_vector << index);
554 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
555 break;
556 }
557 default:
558 break;
559 }
9a799d71
AK		 560}
561
fe49f04a 562static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 563 u64 qmask)
fe49f04a
AD		 564{
565 u32 mask;
566
bd508178
AD		 567 switch (adapter->hw.mac.type) {
568 case ixgbe_mac_82598EB:
fe49f04a
AD		 569 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 571 break;
572 case ixgbe_mac_82599EB:
b93a2226 573 case ixgbe_mac_X540:
fe49f04a
AD		 574 mask = (qmask & 0xFFFFFFFF);
575 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
576 mask = (qmask >> 32);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 578 break;
579 default:
580 break;
fe49f04a
AD		 581 }
582}
583
d3d00239
AD		 584static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
585 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 586{
d3d00239
AD		 587 if (tx_buffer->dma) {
588 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
589 dma_unmap_page(ring->dev,
590 tx_buffer->dma,
591 tx_buffer->length,
592 DMA_TO_DEVICE);
e5a43549 593 else
d3d00239
AD		 594 dma_unmap_single(ring->dev,
595 tx_buffer->dma,
596 tx_buffer->length,
597 DMA_TO_DEVICE);
e5a43549 598 }
d3d00239
AD		 599 tx_buffer->dma = 0;
600}
601
602void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
603 struct ixgbe_tx_buffer *tx_buffer_info)
604{
605 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
606 if (tx_buffer_info->skb)
9a799d71 607 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 608 tx_buffer_info->skb = NULL;
9a799d71
AK		 609 /* tx_buffer_info must be completely set up in the transmit path */
610}
611
c84d324c
JF		 612static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
613{
614 struct ixgbe_hw *hw = &adapter->hw;
615 struct ixgbe_hw_stats *hwstats = &adapter->stats;
616 u32 data = 0;
617 u32 xoff[8] = {0};
618 int i;
619
620 if ((hw->fc.current_mode == ixgbe_fc_full) ||
621 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
622 switch (hw->mac.type) {
623 case ixgbe_mac_82598EB:
624 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 625 break;
626 default:
c84d324c
JF		 627 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
628 }
629 hwstats->lxoffrxc += data;
630
631 /* refill credits (no tx hang) if we received xoff */
632 if (!data)
633 return;
634
635 for (i = 0; i < adapter->num_tx_queues; i++)
636 clear_bit(__IXGBE_HANG_CHECK_ARMED,
637 &adapter->tx_ring[i]->state);
638 return;
639 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
640 return;
641
642 /* update stats for each tc, only valid with PFC enabled */
643 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
644 switch (hw->mac.type) {
645 case ixgbe_mac_82598EB:
646 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 647 break;
c84d324c
JF		 648 default:
649 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 650 }
c84d324c
JF		 651 hwstats->pxoffrxc[i] += xoff[i];
652 }
653
654 /* disarm tx queues that have received xoff frames */
655 for (i = 0; i < adapter->num_tx_queues; i++) {
656 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 657 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 658
659 if (xoff[tc])
660 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 661 }
26f23d82
YZ		 662}
663
c84d324c 664static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 665{
c84d324c
JF		 666 return ring->tx_stats.completed;
667}
668
669static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
670{
671 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 672 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 673
c84d324c
JF		 674 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
675 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
676
677 if (head != tail)
678 return (head < tail) ?
679 tail - head : (tail + ring->count - head);
680
681 return 0;
682}
683
684static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
685{
686 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
687 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
688 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
689 bool ret = false;
690
7d637bcc 691 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 692
693 /*
694 * Check for a hung queue, but be thorough. This verifies
695 * that a transmit has been completed since the previous
696 * check AND there is at least one packet pending. The
697 * ARMED bit is set to indicate a potential hang. The
698 * bit is cleared if a pause frame is received to remove
699 * false hang detection due to PFC or 802.3x frames. By
700 * requiring this to fail twice we avoid races with
701 * pfc clearing the ARMED bit and conditions where we
702 * run the check_tx_hang logic with a transmit completion
703 * pending but without time to complete it yet.
704 */
705 if ((tx_done_old == tx_done) && tx_pending) {
706 /* make sure it is true for two checks in a row */
707 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
708 &tx_ring->state);
709 } else {
710 /* update completed stats and continue */
711 tx_ring->tx_stats.tx_done_old = tx_done;
712 /* reset the countdown */
713 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 714 }
715
c84d324c 716 return ret;
9a799d71
AK		 717}
718
c83c6cbd
AD		 719/**
720 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
721 * @adapter: driver private struct
722 **/
723static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
724{
725
726 /* Do the reset outside of interrupt context */
727 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
728 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
729 ixgbe_service_event_schedule(adapter);
730 }
731}
e01c31a5 732
9a799d71
AK		 733/**
734 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 735 * @q_vector: structure containing interrupt and ring information
e01c31a5 736 * @tx_ring: tx ring to clean
9a799d71 737 **/
fe49f04a 738static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 739 struct ixgbe_ring *tx_ring)
9a799d71 740{
fe49f04a 741 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 742 struct ixgbe_tx_buffer *tx_buffer;
743 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 744 unsigned int total_bytes = 0, total_packets = 0;
59224555 745 unsigned int budget = q_vector->tx.work_limit;
d3d00239 746 u16 i = tx_ring->next_to_clean;
9a799d71 747
d3d00239
AD		 748 tx_buffer = &tx_ring->tx_buffer_info[i];
749 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 750
30065e63 751 for (; budget; budget--) {
d3d00239
AD		 752 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
753
754 /* if next_to_watch is not set then there is no work pending */
755 if (!eop_desc)
756 break;
757
758 /* if DD is not set pending work has not been completed */
759 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
760 break;
8ad494b0 761
d3d00239
AD		 762 /* count the packet as being completed */
763 tx_ring->tx_stats.completed++;
764
765 /* clear next_to_watch to prevent false hangs */
766 tx_buffer->next_to_watch = NULL;
8ad494b0 767
d3d00239
AD		 768 /* prevent any other reads prior to eop_desc being verified */
769 rmb();
770
771 do {
772 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 773 tx_desc->wb.status = 0;
d3d00239
AD		 774 if (likely(tx_desc == eop_desc)) {
775 eop_desc = NULL;
776 dev_kfree_skb_any(tx_buffer->skb);
777 tx_buffer->skb = NULL;
778
779 total_bytes += tx_buffer->bytecount;
780 total_packets += tx_buffer->gso_segs;
781 }
9a799d71 782
d3d00239
AD		 783 tx_buffer++;
784 tx_desc++;
8ad494b0 785 i++;
d3d00239 786 if (unlikely(i == tx_ring->count)) {
8ad494b0 787 i = 0;
e01c31a5 788
d3d00239
AD		 789 tx_buffer = tx_ring->tx_buffer_info;
790 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 791 }
e01c31a5 792
d3d00239 793 } while (eop_desc);
12207e49
PWJ		 794 }
795
9a799d71 796 tx_ring->next_to_clean = i;
d3d00239 797 u64_stats_update_begin(&tx_ring->syncp);
b953799e 798 tx_ring->stats.bytes += total_bytes;
bd198058 799 tx_ring->stats.packets += total_packets;
d3d00239 800 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 801 q_vector->tx.total_bytes += total_bytes;
802 q_vector->tx.total_packets += total_packets;
b953799e 803
c84d324c
JF		 804 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
805 /* schedule immediate reset if we believe we hung */
806 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 807 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 808 e_err(drv, "Detected Tx Unit Hang\n"
809 " Tx Queue <%d>\n"
810 " TDH, TDT <%x>, <%x>\n"
811 " next_to_use <%x>\n"
812 " next_to_clean <%x>\n"
813 "tx_buffer_info[next_to_clean]\n"
814 " time_stamp <%lx>\n"
815 " jiffies <%lx>\n",
816 tx_ring->queue_index,
817 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
818 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 819 tx_ring->next_to_use, i,
820 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 821
822 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
823
824 e_info(probe,
825 "tx hang %d detected on queue %d, resetting adapter\n",
826 adapter->tx_timeout_count + 1, tx_ring->queue_index);
827
b953799e 828 /* schedule immediate reset if we believe we hung */
c83c6cbd 829 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 830
831 /* the adapter is about to reset, no point in enabling stuff */
59224555 832 return true;
b953799e 833 }
9a799d71 834
e092be60 835#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 836 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 837 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 838 /* Make sure that anybody stopping the queue after this
839 * sees the new next_to_clean.
840 */
841 smp_mb();
fc77dc3c 842 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 843 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 844 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 845 ++tx_ring->tx_stats.restart_queue;
30eba97a 846 }
e092be60 847 }
9a799d71 848
59224555 849 return !!budget;
9a799d71
AK		 850}
851
5dd2d332 852#ifdef CONFIG_IXGBE_DCA
bd0362dd 853static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 854 struct ixgbe_ring *rx_ring,
855 int cpu)
bd0362dd 856{
33cf09c9 857 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 858 u32 rxctrl;
33cf09c9
AD		 859 u8 reg_idx = rx_ring->reg_idx;
860
861 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
862 switch (hw->mac.type) {
863 case ixgbe_mac_82598EB:
864 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 865 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 866 break;
867 case ixgbe_mac_82599EB:
b93a2226 868 case ixgbe_mac_X540:
33cf09c9 869 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 870 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 871 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
872 break;
873 default:
874 break;
bd0362dd 875 }
33cf09c9
AD		 876 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
877 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
878 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 879 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 880}
881
882static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 883 struct ixgbe_ring *tx_ring,
884 int cpu)
bd0362dd 885{
33cf09c9 886 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 887 u32 txctrl;
33cf09c9
AD		 888 u8 reg_idx = tx_ring->reg_idx;
889
890 switch (hw->mac.type) {
891 case ixgbe_mac_82598EB:
892 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
893 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 894 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 895 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 896 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
897 break;
898 case ixgbe_mac_82599EB:
b93a2226 899 case ixgbe_mac_X540:
33cf09c9
AD		 900 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
901 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 902 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 903 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
904 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 905 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
906 break;
907 default:
908 break;
909 }
910}
911
912static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
913{
914 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 915 struct ixgbe_ring *ring;
bd0362dd 916 int cpu = get_cpu();
bd0362dd 917
33cf09c9
AD		 918 if (q_vector->cpu == cpu)
919 goto out_no_update;
920
efe3d3c8
AD		 921 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
922 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 923
efe3d3c8
AD		 924 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
925 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 926
927 q_vector->cpu = cpu;
928out_no_update:
bd0362dd
JC		 929 put_cpu();
930}
931
932static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
933{
33cf09c9 934 int num_q_vectors;
bd0362dd
JC		 935 int i;
936
937 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
938 return;
939
e35ec126
AD		 940 /* always use CB2 mode, difference is masked in the CB driver */
941 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
942
33cf09c9
AD		 943 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
944 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
945 else
946 num_q_vectors = 1;
947
948 for (i = 0; i < num_q_vectors; i++) {
949 adapter->q_vector[i]->cpu = -1;
950 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 951 }
952}
953
954static int __ixgbe_notify_dca(struct device *dev, void *data)
955{
c60fbb00 956 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 957 unsigned long event = *(unsigned long *)data;
958
2a72c31e 959 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 960 return 0;
961
bd0362dd
JC		 962 switch (event) {
963 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 964 /* if we're already enabled, don't do it again */
965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
966 break;
652f093f 967 if (dca_add_requester(dev) == 0) {
96b0e0f6 968 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 969 ixgbe_setup_dca(adapter);
970 break;
971 }
972 /* Fall Through since DCA is disabled. */
973 case DCA_PROVIDER_REMOVE:
974 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
975 dca_remove_requester(dev);
976 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
977 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
978 }
979 break;
980 }
981
652f093f 982 return 0;
bd0362dd 983}
5dd2d332 984#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 985
986static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
987 struct sk_buff *skb)
988{
989 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
990}
991
ff886dfc
AD		 992/**
993 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
994 * @adapter: address of board private structure
995 * @rx_desc: advanced rx descriptor
996 *
997 * Returns : true if it is FCoE pkt
998 */
999static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1000 union ixgbe_adv_rx_desc *rx_desc)
1001{
1002 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1003
1004 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1005 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1006 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1007 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1008}
1009
9a799d71
AK		 1010/**
1011 * ixgbe_receive_skb - Send a completed packet up the stack
1012 * @adapter: board private structure
1013 * @skb: packet to send up
177db6ff
MC		 1014 * @status: hardware indication of status of receive
1015 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1016 * @rx_desc: rx descriptor
9a799d71 1017 **/
78b6f4ce 1018static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1019 struct sk_buff *skb, u8 status,
1020 struct ixgbe_ring *ring,
1021 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1022{
78b6f4ce
HX		 1023 struct ixgbe_adapter *adapter = q_vector->adapter;
1024 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1025 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1026 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1027
f62bbb5e
JG		 1028 if (is_vlan && (tag & VLAN_VID_MASK))
1029 __vlan_hwaccel_put_tag(skb, tag);
1030
1031 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1032 napi_gro_receive(napi, skb);
1033 else
1034 netif_rx(skb);
9a799d71
AK		 1035}
1036
e59bd25d
AV		 1037/**
1038 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1039 * @adapter: address of board private structure
1040 * @status_err: hardware indication of status of receive
1041 * @skb: skb currently being received and modified
ff886dfc 1042 * @status_err: status error value of last descriptor in packet
e59bd25d 1043 **/
9a799d71 1044static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1045 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1046 struct sk_buff *skb,
1047 u32 status_err)
9a799d71 1048{
ff886dfc 1049 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1050
712744be
JB		 1051 /* Rx csum disabled */
1052 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1053 return;
e59bd25d
AV		 1054
1055 /* if IP and error */
1056 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1057 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1058 adapter->hw_csum_rx_error++;
1059 return;
1060 }
e59bd25d
AV		 1061
1062 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1063 return;
1064
1065 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1066 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1067
1068 /*
1069 * 82599 errata, UDP frames with a 0 checksum can be marked as
1070 * checksum errors.
1071 */
1072 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1073 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1074 return;
1075
e59bd25d
AV		 1076 adapter->hw_csum_rx_error++;
1077 return;
1078 }
1079
9a799d71 1080 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1081 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1082}
1083
84ea2591 1084static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1085{
1086 /*
1087 * Force memory writes to complete before letting h/w
1088 * know there are new descriptors to fetch. (Only
1089 * applicable for weak-ordered memory model archs,
1090 * such as IA-64).
1091 */
1092 wmb();
84ea2591 1093 writel(val, rx_ring->tail);
e8e26350
PW		 1094}
1095
9a799d71
AK		 1096/**
1097 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1098 * @rx_ring: ring to place buffers on
1099 * @cleaned_count: number of buffers to replace
9a799d71 1100 **/
fc77dc3c 1101void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1102{
9a799d71 1103 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1104 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1105 struct sk_buff *skb;
1106 u16 i = rx_ring->next_to_use;
9a799d71 1107
fc77dc3c
AD		 1108 /* do nothing if no valid netdev defined */
1109 if (!rx_ring->netdev)
1110 return;
1111
9a799d71 1112 while (cleaned_count--) {
31f05a2d 1113 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1114 bi = &rx_ring->rx_buffer_info[i];
1115 skb = bi->skb;
9a799d71 1116
d5f398ed 1117 if (!skb) {
fc77dc3c 1118 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1119 rx_ring->rx_buf_len);
9a799d71 1120 if (!skb) {
5b7da515 1121 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1122 goto no_buffers;
1123 }
d716a7d8
AD		 1124 /* initialize queue mapping */
1125 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1126 bi->skb = skb;
d716a7d8 1127 }
9a799d71 1128
d716a7d8 1129 if (!bi->dma) {
b6ec895e 1130 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1131 skb->data,
e8e9f696 1132 rx_ring->rx_buf_len,
1b507730 1133 DMA_FROM_DEVICE);
b6ec895e 1134 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1135 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1136 bi->dma = 0;
1137 goto no_buffers;
1138 }
9a799d71 1139 }
d5f398ed 1140
7d637bcc 1141 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1142 if (!bi->page) {
1f2149c1 1143 bi->page = alloc_page(GFP_ATOMIC | __GFP_COLD);
d5f398ed 1144 if (!bi->page) {
5b7da515 1145 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1146 goto no_buffers;
1147 }
1148 }
1149
1150 if (!bi->page_dma) {
1151 /* use a half page if we're re-using */
1152 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1153 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1154 bi->page,
1155 bi->page_offset,
1156 PAGE_SIZE / 2,
1157 DMA_FROM_DEVICE);
b6ec895e 1158 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1159 bi->page_dma)) {
5b7da515 1160 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1161 bi->page_dma = 0;
1162 goto no_buffers;
1163 }
1164 }
1165
1166 /* Refresh the desc even if buffer_addrs didn't change
1167 * because each write-back erases this info. */
3a581073
JB		 1168 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1169 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1170 } else {
3a581073 1171 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1172 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1173 }
1174
1175 i++;
1176 if (i == rx_ring->count)
1177 i = 0;
9a799d71 1178 }
7c6e0a43 1179
9a799d71
AK		 1180no_buffers:
1181 if (rx_ring->next_to_use != i) {
1182 rx_ring->next_to_use = i;
84ea2591 1183 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1184 }
1185}
1186
c267fc16 1187static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1188{
c267fc16
AD		 1189 /* HW will not DMA in data larger than the given buffer, even if it
1190 * parses the (NFS, of course) header to be larger. In that case, it
1191 * fills the header buffer and spills the rest into the page.
1192 */
1193 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1194 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1195 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1196 if (hlen > IXGBE_RX_HDR_SIZE)
1197 hlen = IXGBE_RX_HDR_SIZE;
1198 return hlen;
7c6e0a43
JB		 1199}
1200
f8212f97
AD		 1201/**
1202 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1203 * @skb: pointer to the last skb in the rsc queue
1204 *
1205 * This function changes a queue full of hw rsc buffers into a completed
1206 * packet. It uses the ->prev pointers to find the first packet and then
1207 * turns it into the frag list owner.
1208 **/
aa80175a 1209static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1210{
1211 unsigned int frag_list_size = 0;
aa80175a 1212 unsigned int skb_cnt = 1;
f8212f97
AD		 1213
1214 while (skb->prev) {
1215 struct sk_buff *prev = skb->prev;
1216 frag_list_size += skb->len;
1217 skb->prev = NULL;
1218 skb = prev;
aa80175a 1219 skb_cnt++;
f8212f97
AD		 1220 }
1221
1222 skb_shinfo(skb)->frag_list = skb->next;
1223 skb->next = NULL;
1224 skb->len += frag_list_size;
1225 skb->data_len += frag_list_size;
1226 skb->truesize += frag_list_size;
aa80175a
AD		 1227 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1228
f8212f97
AD		 1229 return skb;
1230}
1231
aa80175a
AD		 1232static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1233{
1234 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1235 IXGBE_RXDADV_RSCCNT_MASK);
1236}
43634e82 1237
4ff7fb12 1238static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1239 struct ixgbe_ring *rx_ring,
4ff7fb12 1240 int budget)
9a799d71 1241{
78b6f4ce 1242 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1243 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1244 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1245 struct sk_buff *skb;
d2f4fbe2 1246 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1247 const int current_node = numa_node_id();
3d8fd385
YZ		 1248#ifdef IXGBE_FCOE
1249 int ddp_bytes = 0;
1250#endif /* IXGBE_FCOE */
c267fc16
AD		 1251 u32 staterr;
1252 u16 i;
1253 u16 cleaned_count = 0;
aa80175a 1254 bool pkt_is_rsc = false;
9a799d71
AK		 1255
1256 i = rx_ring->next_to_clean;
31f05a2d 1257 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1258 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1259
1260 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1261 u32 upper_len = 0;
9a799d71 1262
3c945e5b 1263 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1264
c267fc16
AD		 1265 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1266
9a799d71 1267 skb = rx_buffer_info->skb;
9a799d71 1268 rx_buffer_info->skb = NULL;
c267fc16 1269 prefetch(skb->data);
9a799d71 1270
c267fc16 1271 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1272 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16 1273
b811ce91
JB		 1274 /* linear means we are building an skb from multiple pages */
1275 if (!skb_is_nonlinear(skb)) {
c267fc16 1276 u16 hlen;
aa80175a 1277 if (pkt_is_rsc &&
c267fc16
AD		 1278 !(staterr & IXGBE_RXD_STAT_EOP) &&
1279 !skb->prev) {
43634e82
MC		 1280 /*
1281 * When HWRSC is enabled, delay unmapping
1282 * of the first packet. It carries the
1283 * header information, HW may still
1284 * access the header after the writeback.
1285 * Only unmap it when EOP is reached
1286 */
e8171aaa 1287 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1288 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1289 } else {
b6ec895e 1290 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1291 rx_buffer_info->dma,
1292 rx_ring->rx_buf_len,
1293 DMA_FROM_DEVICE);
e8171aaa 1294 }
4f57ca6e 1295 rx_buffer_info->dma = 0;
c267fc16
AD		 1296
1297 if (ring_is_ps_enabled(rx_ring)) {
1298 hlen = ixgbe_get_hlen(rx_desc);
1299 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1300 } else {
1301 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1302 }
1303
1304 skb_put(skb, hlen);
1305 } else {
1306 /* assume packet split since header is unmapped */
1307 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1308 }
1309
1310 if (upper_len) {
b6ec895e
AD		 1311 dma_unmap_page(rx_ring->dev,
1312 rx_buffer_info->page_dma,
1313 PAGE_SIZE / 2,
1314 DMA_FROM_DEVICE);
9a799d71
AK		 1315 rx_buffer_info->page_dma = 0;
1316 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1317 rx_buffer_info->page,
1318 rx_buffer_info->page_offset,
1319 upper_len);
762f4c57 1320
c267fc16
AD		 1321 if ((page_count(rx_buffer_info->page) == 1) &&
1322 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1323 get_page(rx_buffer_info->page);
c267fc16
AD		 1324 else
1325 rx_buffer_info->page = NULL;
9a799d71
AK		 1326
1327 skb->len += upper_len;
1328 skb->data_len += upper_len;
98130646 1329 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1330 }
1331
1332 i++;
1333 if (i == rx_ring->count)
1334 i = 0;
9a799d71 1335
31f05a2d 1336 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1337 prefetch(next_rxd);
9a799d71 1338 cleaned_count++;
f8212f97 1339
aa80175a 1340 if (pkt_is_rsc) {
f8212f97
AD		 1341 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1342 IXGBE_RXDADV_NEXTP_SHIFT;
1343 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1344 } else {
1345 next_buffer = &rx_ring->rx_buffer_info[i];
1346 }
1347
c267fc16 1348 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1349 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1350 rx_buffer_info->skb = next_buffer->skb;
1351 rx_buffer_info->dma = next_buffer->dma;
1352 next_buffer->skb = skb;
1353 next_buffer->dma = 0;
1354 } else {
1355 skb->next = next_buffer->skb;
1356 skb->next->prev = skb;
1357 }
5b7da515 1358 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1359 goto next_desc;
1360 }
1361
aa80175a
AD		 1362 if (skb->prev) {
1363 skb = ixgbe_transform_rsc_queue(skb);
1364 /* if we got here without RSC the packet is invalid */
1365 if (!pkt_is_rsc) {
1366 __pskb_trim(skb, 0);
1367 rx_buffer_info->skb = skb;
1368 goto next_desc;
1369 }
1370 }
c267fc16
AD		 1371
1372 if (ring_is_rsc_enabled(rx_ring)) {
1373 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1374 dma_unmap_single(rx_ring->dev,
1375 IXGBE_RSC_CB(skb)->dma,
1376 rx_ring->rx_buf_len,
1377 DMA_FROM_DEVICE);
1378 IXGBE_RSC_CB(skb)->dma = 0;
1379 IXGBE_RSC_CB(skb)->delay_unmap = false;
1380 }
aa80175a
AD		 1381 }
1382 if (pkt_is_rsc) {
c267fc16
AD		 1383 if (ring_is_ps_enabled(rx_ring))
1384 rx_ring->rx_stats.rsc_count +=
aa80175a 1385 skb_shinfo(skb)->nr_frags;
c267fc16 1386 else
aa80175a
AD		 1387 rx_ring->rx_stats.rsc_count +=
1388 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1389 rx_ring->rx_stats.rsc_flush++;
1390 }
1391
1392 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1393 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1394 dev_kfree_skb_any(skb);
9a799d71
AK		 1395 goto next_desc;
1396 }
1397
ff886dfc 1398 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1399 if (adapter->netdev->features & NETIF_F_RXHASH)
1400 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1401
1402 /* probably a little skewed due to removing CRC */
1403 total_rx_bytes += skb->len;
1404 total_rx_packets++;
1405
fc77dc3c 1406 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1407#ifdef IXGBE_FCOE
1408 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1409 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1410 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1411 staterr);
63d635b2
AD		 1412 if (!ddp_bytes) {
1413 dev_kfree_skb_any(skb);
332d4a7d 1414 goto next_desc;
63d635b2 1415 }
3d8fd385 1416 }
332d4a7d 1417#endif /* IXGBE_FCOE */
fdaff1ce 1418 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1419
4ff7fb12 1420 budget--;
9a799d71
AK		 1421next_desc:
1422 rx_desc->wb.upper.status_error = 0;
1423
4ff7fb12 1424 if (!budget)
c267fc16
AD		 1425 break;
1426
9a799d71
AK		 1427 /* return some buffers to hardware, one at a time is too slow */
1428 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1429 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1430 cleaned_count = 0;
1431 }
1432
1433 /* use prefetched values */
1434 rx_desc = next_rxd;
9a799d71 1435 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1436 }
1437
9a799d71 1438 rx_ring->next_to_clean = i;
7d4987de 1439 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1440
1441 if (cleaned_count)
fc77dc3c 1442 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1443
3d8fd385
YZ		 1444#ifdef IXGBE_FCOE
1445 /* include DDPed FCoE data */
1446 if (ddp_bytes > 0) {
1447 unsigned int mss;
1448
fc77dc3c 1449 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1450 sizeof(struct fc_frame_header) -
1451 sizeof(struct fcoe_crc_eof);
1452 if (mss > 512)
1453 mss &= ~511;
1454 total_rx_bytes += ddp_bytes;
1455 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1456 }
1457#endif /* IXGBE_FCOE */
1458
c267fc16
AD		 1459 u64_stats_update_begin(&rx_ring->syncp);
1460 rx_ring->stats.packets += total_rx_packets;
1461 rx_ring->stats.bytes += total_rx_bytes;
1462 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1463 q_vector->rx.total_packets += total_rx_packets;
1464 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1465
1466 return !!budget;
9a799d71
AK		 1467}
1468
9a799d71
AK		 1469/**
1470 * ixgbe_configure_msix - Configure MSI-X hardware
1471 * @adapter: board private structure
1472 *
1473 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1474 * interrupts.
1475 **/
1476static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1477{
021230d4 1478 struct ixgbe_q_vector *q_vector;
efe3d3c8 1479 int q_vectors, v_idx;
021230d4 1480 u32 mask;
9a799d71 1481
021230d4 1482 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1483
8e34d1aa
AD		 1484 /* Populate MSIX to EITR Select */
1485 if (adapter->num_vfs > 32) {
1486 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1488 }
1489
4df10466
JB		 1490 /*
1491 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1492 * corresponding register.
1493 */
1494 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1495 struct ixgbe_ring *ring;
7a921c93 1496 q_vector = adapter->q_vector[v_idx];
021230d4 1497
efe3d3c8
AD		 1498 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1499 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1500
1501 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1502 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1503
d5bf4f67
ET		 1504 if (q_vector->tx.ring && !q_vector->rx.ring) {
1505 /* tx only vector */
1506 if (adapter->tx_itr_setting == 1)
1507 q_vector->itr = IXGBE_10K_ITR;
1508 else
1509 q_vector->itr = adapter->tx_itr_setting;
1510 } else {
1511 /* rx or rx/tx vector */
1512 if (adapter->rx_itr_setting == 1)
1513 q_vector->itr = IXGBE_20K_ITR;
1514 else
1515 q_vector->itr = adapter->rx_itr_setting;
1516 }
021230d4 1517
fe49f04a 1518 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1519 }
1520
bd508178
AD		 1521 switch (adapter->hw.mac.type) {
1522 case ixgbe_mac_82598EB:
e8e26350 1523 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1524 v_idx);
bd508178
AD		 1525 break;
1526 case ixgbe_mac_82599EB:
b93a2226 1527 case ixgbe_mac_X540:
e8e26350 1528 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1529 break;
bd508178
AD		 1530 default:
1531 break;
1532 }
021230d4
AV		 1533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1534
41fb9248 1535 /* set up to autoclear timer, and the vectors */
021230d4 1536 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1537 mask &= ~(IXGBE_EIMS_OTHER |
1538 IXGBE_EIMS_MAILBOX |
1539 IXGBE_EIMS_LSC);
1540
021230d4 1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1542}
1543
f494e8fa
AV		 1544enum latency_range {
1545 lowest_latency = 0,
1546 low_latency = 1,
1547 bulk_latency = 2,
1548 latency_invalid = 255
1549};
1550
1551/**
1552 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1553 * @q_vector: structure containing interrupt and ring information
1554 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1555 *
1556 * Stores a new ITR value based on packets and byte
1557 * counts during the last interrupt. The advantage of per interrupt
1558 * computation is faster updates and more accurate ITR for the current
1559 * traffic pattern. Constants in this function were computed
1560 * based on theoretical maximum wire speed and thresholds were set based
1561 * on testing data as well as attempting to minimize response time
1562 * while increasing bulk throughput.
1563 * this functionality is controlled by the InterruptThrottleRate module
1564 * parameter (see ixgbe_param.c)
1565 **/
bd198058
AD		 1566static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1567 struct ixgbe_ring_container *ring_container)
f494e8fa 1568{
f494e8fa 1569 u64 bytes_perint;
bd198058
AD		 1570 struct ixgbe_adapter *adapter = q_vector->adapter;
1571 int bytes = ring_container->total_bytes;
1572 int packets = ring_container->total_packets;
1573 u32 timepassed_us;
1574 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1575
1576 if (packets == 0)
bd198058 1577 return;
f494e8fa
AV		 1578
1579 /* simple throttlerate management
1580 * 0-20MB/s lowest (100000 ints/s)
1581 * 20-100MB/s low (20000 ints/s)
1582 * 100-1249MB/s bulk (8000 ints/s)
1583 */
1584 /* what was last interrupt timeslice? */
d5bf4f67 1585 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1586 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1587
1588 switch (itr_setting) {
1589 case lowest_latency:
1590 if (bytes_perint > adapter->eitr_low)
bd198058 1591 itr_setting = low_latency;
f494e8fa
AV		 1592 break;
1593 case low_latency:
1594 if (bytes_perint > adapter->eitr_high)
bd198058 1595 itr_setting = bulk_latency;
f494e8fa 1596 else if (bytes_perint <= adapter->eitr_low)
bd198058 1597 itr_setting = lowest_latency;
f494e8fa
AV		 1598 break;
1599 case bulk_latency:
1600 if (bytes_perint <= adapter->eitr_high)
bd198058 1601 itr_setting = low_latency;
f494e8fa
AV		 1602 break;
1603 }
1604
bd198058
AD		 1605 /* clear work counters since we have the values we need */
1606 ring_container->total_bytes = 0;
1607 ring_container->total_packets = 0;
1608
1609 /* write updated itr to ring container */
1610 ring_container->itr = itr_setting;
f494e8fa
AV		 1611}
1612
509ee935
JB		 1613/**
1614 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1615 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1616 *
1617 * This function is made to be called by ethtool and by the driver
1618 * when it needs to update EITR registers at runtime. Hardware
1619 * specific quirks/differences are taken care of here.
1620 */
fe49f04a 1621void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1622{
fe49f04a 1623 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1624 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1625 int v_idx = q_vector->v_idx;
d5bf4f67 1626 u32 itr_reg = q_vector->itr;
fe49f04a 1627
bd508178
AD		 1628 switch (adapter->hw.mac.type) {
1629 case ixgbe_mac_82598EB:
509ee935
JB		 1630 /* must write high and low 16 bits to reset counter */
1631 itr_reg |= (itr_reg << 16);
bd508178
AD		 1632 break;
1633 case ixgbe_mac_82599EB:
b93a2226 1634 case ixgbe_mac_X540:
509ee935
JB		 1635 /*
1636 * set the WDIS bit to not clear the timer bits and cause an
1637 * immediate assertion of the interrupt
1638 */
1639 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1640 break;
1641 default:
1642 break;
509ee935
JB		 1643 }
1644 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1645}
1646
bd198058 1647static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1648{
d5bf4f67 1649 u32 new_itr = q_vector->itr;
bd198058 1650 u8 current_itr;
f494e8fa 1651
bd198058
AD		 1652 ixgbe_update_itr(q_vector, &q_vector->tx);
1653 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1654
08c8833b 1655 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1656
1657 switch (current_itr) {
1658 /* counts and packets in update_itr are dependent on these numbers */
1659 case lowest_latency:
d5bf4f67 1660 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1661 break;
1662 case low_latency:
d5bf4f67 1663 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1664 break;
1665 case bulk_latency:
d5bf4f67 1666 new_itr = IXGBE_8K_ITR;
f494e8fa 1667 break;
bd198058
AD		 1668 default:
1669 break;
f494e8fa
AV		 1670 }
1671
d5bf4f67 1672 if (new_itr != q_vector->itr) {
fe49f04a 1673 /* do an exponential smoothing */
d5bf4f67
ET		 1674 new_itr = (10 * new_itr * q_vector->itr) /
1675 ((9 * new_itr) + q_vector->itr);
509ee935 1676
bd198058 1677 /* save the algorithm value here */
d5bf4f67 1678 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1679
1680 ixgbe_write_eitr(q_vector);
f494e8fa 1681 }
f494e8fa
AV		 1682}
1683
119fc60a 1684/**
f0f9778d
AD		 1685 * ixgbe_check_overtemp_subtask - check for over tempurature
1686 * @adapter: pointer to adapter
119fc60a 1687 **/
f0f9778d 1688static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1689{
119fc60a
MC		 1690 struct ixgbe_hw *hw = &adapter->hw;
1691 u32 eicr = adapter->interrupt_event;
1692
f0f9778d 1693 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1694 return;
1695
f0f9778d
AD		 1696 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1697 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1698 return;
1699
1700 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1701
7ca647bd 1702 switch (hw->device_id) {
f0f9778d
AD		 1703 case IXGBE_DEV_ID_82599_T3_LOM:
1704 /*
1705 * Since the warning interrupt is for both ports
1706 * we don't have to check if:
1707 * - This interrupt wasn't for our port.
1708 * - We may have missed the interrupt so always have to
1709 * check if we got a LSC
1710 */
1711 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1712 !(eicr & IXGBE_EICR_LSC))
1713 return;
1714
1715 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1716 u32 autoneg;
1717 bool link_up = false;
7ca647bd 1718
7ca647bd
JP		 1719 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1720
f0f9778d
AD		 1721 if (link_up)
1722 return;
1723 }
1724
1725 /* Check if this is not due to overtemp */
1726 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1727 return;
1728
1729 break;
7ca647bd
JP		 1730 default:
1731 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1732 return;
7ca647bd 1733 break;
119fc60a 1734 }
7ca647bd
JP		 1735 e_crit(drv,
1736 "Network adapter has been stopped because it has over heated. "
1737 "Restart the computer. If the problem persists, "
1738 "power off the system and replace the adapter\n");
f0f9778d
AD		 1739
1740 adapter->interrupt_event = 0;
119fc60a
MC		 1741}
1742
0befdb3e
JB		 1743static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1744{
1745 struct ixgbe_hw *hw = &adapter->hw;
1746
1747 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1748 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1749 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1750 /* write to clear the interrupt */
1751 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1752 }
1753}
cf8280ee 1754
4f51bf70
JK		 1755static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1756{
1757 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1758 return;
1759
1760 switch (adapter->hw.mac.type) {
1761 case ixgbe_mac_82599EB:
1762 /*
1763 * Need to check link state so complete overtemp check
1764 * on service task
1765 */
1766 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1767 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1768 adapter->interrupt_event = eicr;
1769 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1770 ixgbe_service_event_schedule(adapter);
1771 return;
1772 }
1773 return;
1774 case ixgbe_mac_X540:
1775 if (!(eicr & IXGBE_EICR_TS))
1776 return;
1777 break;
1778 default:
1779 return;
1780 }
1781
1782 e_crit(drv,
1783 "Network adapter has been stopped because it has over heated. "
1784 "Restart the computer. If the problem persists, "
1785 "power off the system and replace the adapter\n");
1786}
1787
e8e26350
PW		 1788static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1789{
1790 struct ixgbe_hw *hw = &adapter->hw;
1791
73c4b7cd
AD		 1792 if (eicr & IXGBE_EICR_GPI_SDP2) {
1793 /* Clear the interrupt */
1794 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1795 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1796 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1797 ixgbe_service_event_schedule(adapter);
1798 }
73c4b7cd
AD		 1799 }
1800
e8e26350
PW		 1801 if (eicr & IXGBE_EICR_GPI_SDP1) {
1802 /* Clear the interrupt */
1803 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1804 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1805 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1806 ixgbe_service_event_schedule(adapter);
1807 }
e8e26350
PW		 1808 }
1809}
1810
cf8280ee
JB		 1811static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1812{
1813 struct ixgbe_hw *hw = &adapter->hw;
1814
1815 adapter->lsc_int++;
1816 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1817 adapter->link_check_timeout = jiffies;
1818 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1819 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1820 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1821 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1822 }
1823}
1824
fe49f04a
AD		 1825static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1826 u64 qmask)
1827{
1828 u32 mask;
bd508178 1829 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1830
bd508178
AD		 1831 switch (hw->mac.type) {
1832 case ixgbe_mac_82598EB:
fe49f04a 1833 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1834 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1835 break;
1836 case ixgbe_mac_82599EB:
b93a2226 1837 case ixgbe_mac_X540:
fe49f04a 1838 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1839 if (mask)
1840 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1841 mask = (qmask >> 32);
bd508178
AD		 1842 if (mask)
1843 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1844 break;
1845 default:
1846 break;
fe49f04a
AD		 1847 }
1848 /* skip the flush */
1849}
1850
1851static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1852 u64 qmask)
fe49f04a
AD		 1853{
1854 u32 mask;
bd508178 1855 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1856
bd508178
AD		 1857 switch (hw->mac.type) {
1858 case ixgbe_mac_82598EB:
fe49f04a 1859 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1860 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1861 break;
1862 case ixgbe_mac_82599EB:
b93a2226 1863 case ixgbe_mac_X540:
fe49f04a 1864 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1865 if (mask)
1866 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1867 mask = (qmask >> 32);
bd508178
AD		 1868 if (mask)
1869 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1870 break;
1871 default:
1872 break;
fe49f04a
AD		 1873 }
1874 /* skip the flush */
1875}
1876
021230d4 1877/**
2c4af694
AD		 1878 * ixgbe_irq_enable - Enable default interrupt generation settings
1879 * @adapter: board private structure
021230d4 1880 **/
2c4af694
AD		 1881static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1882 bool flush)
9a799d71 1883{
2c4af694 1884 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 1885
2c4af694
AD		 1886 /* don't reenable LSC while waiting for link */
1887 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1888 mask &= ~IXGBE_EIMS_LSC;
9a799d71 1889
2c4af694 1890 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 1891 switch (adapter->hw.mac.type) {
1892 case ixgbe_mac_82599EB:
1893 mask |= IXGBE_EIMS_GPI_SDP0;
1894 break;
1895 case ixgbe_mac_X540:
1896 mask |= IXGBE_EIMS_TS;
1897 break;
1898 default:
1899 break;
1900 }
2c4af694
AD		 1901 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1902 mask |= IXGBE_EIMS_GPI_SDP1;
1903 switch (adapter->hw.mac.type) {
1904 case ixgbe_mac_82599EB:
2c4af694
AD		 1905 mask |= IXGBE_EIMS_GPI_SDP1;
1906 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 1907 case ixgbe_mac_X540:
1908 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 1909 mask |= IXGBE_EIMS_MAILBOX;
1910 break;
1911 default:
1912 break;
9a799d71 1913 }
2c4af694
AD		 1914 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1915 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1916 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 1917
2c4af694
AD		 1918 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1919 if (queues)
1920 ixgbe_irq_enable_queues(adapter, ~0);
1921 if (flush)
1922 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1923}
1924
2c4af694 1925static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 1926{
a65151ba 1927 struct ixgbe_adapter *adapter = data;
9a799d71 1928 struct ixgbe_hw *hw = &adapter->hw;
54037505 1929 u32 eicr;
91281fd3 1930
54037505
DS		 1931 /*
1932 * Workaround for Silicon errata. Use clear-by-write instead
1933 * of clear-by-read. Reading with EICS will return the
1934 * interrupt causes without clearing, which later be done
1935 * with the write to EICR.
1936 */
1937 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1938 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 1939
cf8280ee
JB		 1940 if (eicr & IXGBE_EICR_LSC)
1941 ixgbe_check_lsc(adapter);
f0848276 1942
1cdd1ec8
GR		 1943 if (eicr & IXGBE_EICR_MAILBOX)
1944 ixgbe_msg_task(adapter);
efe3d3c8 1945
bd508178
AD		 1946 switch (hw->mac.type) {
1947 case ixgbe_mac_82599EB:
b93a2226 1948 case ixgbe_mac_X540:
2c4af694
AD		 1949 if (eicr & IXGBE_EICR_ECC)
1950 e_info(link, "Received unrecoverable ECC Err, please "
1951 "reboot\n");
c4cf55e5
PWJ		 1952 /* Handle Flow Director Full threshold interrupt */
1953 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1954 int reinit_count = 0;
c4cf55e5 1955 int i;
c4cf55e5 1956 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1957 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1958 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1959 &ring->state))
1960 reinit_count++;
1961 }
1962 if (reinit_count) {
1963 /* no more flow director interrupts until after init */
1964 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 1965 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1966 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1967 }
1968 }
f0f9778d 1969 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 1970 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 1971 break;
1972 default:
1973 break;
c4cf55e5 1974 }
f0848276 1975
bd508178 1976 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 1977
7086400d 1978 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1979 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 1980 ixgbe_irq_enable(adapter, false, false);
f0848276 1981
9a799d71 1982 return IRQ_HANDLED;
f0848276 1983}
91281fd3 1984
4ff7fb12 1985static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 1986{
021230d4 1987 struct ixgbe_q_vector *q_vector = data;
91281fd3 1988
9b471446 1989 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1990
4ff7fb12
AD		 1991 if (q_vector->rx.ring || q_vector->tx.ring)
1992 napi_schedule(&q_vector->napi);
91281fd3 1993
9a799d71 1994 return IRQ_HANDLED;
91281fd3
AD		 1995}
1996
021230d4 1997static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 1998 int r_idx)
021230d4 1999{
7a921c93 2000 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2001 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2002
2274543f 2003 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2004 rx_ring->next = q_vector->rx.ring;
2005 q_vector->rx.ring = rx_ring;
2006 q_vector->rx.count++;
021230d4
AV		 2007}
2008
2009static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2010 int t_idx)
021230d4 2011{
7a921c93 2012 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2013 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2014
2274543f 2015 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2016 tx_ring->next = q_vector->tx.ring;
2017 q_vector->tx.ring = tx_ring;
2018 q_vector->tx.count++;
bd198058 2019 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2020}
2021
9a799d71 2022/**
021230d4
AV		 2023 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2024 * @adapter: board private structure to initialize
9a799d71 2025 *
021230d4
AV		 2026 * This function maps descriptor rings to the queue-specific vectors
2027 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2028 * one vector per ring/queue, but on a constrained vector budget, we
2029 * group the rings as "efficiently" as possible. You would add new
2030 * mapping configurations in here.
9a799d71 2031 **/
4cc6df29 2032static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2033{
4cc6df29
AD		 2034 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2035 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2036 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2037 int v_start = 0;
021230d4 2038
4cc6df29 2039 /* only one q_vector if MSI-X is disabled. */
021230d4 2040 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2041 q_vectors = 1;
d0759ebb 2042
021230d4 2043 /*
4cc6df29
AD		 2044 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2045 * group them so there are multiple queues per vector.
2046 *
2047 * Re-adjusting *qpv takes care of the remainder.
021230d4 2048 */
4cc6df29
AD		 2049 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2050 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2051 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2052 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2053 }
9a799d71 2054
021230d4 2055 /*
4cc6df29
AD		 2056 * If there are not enough q_vectors for each ring to have it's own
2057 * vector then we must pair up Rx/Tx on a each vector
021230d4 2058 */
4cc6df29
AD		 2059 if ((v_start + txr_remaining) > q_vectors)
2060 v_start = 0;
2061
2062 for (; v_start < q_vectors && txr_remaining; v_start++) {
2063 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2064 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2065 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2066 }
021230d4
AV		 2067}
2068
2069/**
2070 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2071 * @adapter: board private structure
2072 *
2073 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2074 * interrupts from the kernel.
2075 **/
2076static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2077{
2078 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2079 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2080 int vector, err;
e8e9f696 2081 int ri = 0, ti = 0;
021230d4 2082
021230d4 2083 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2084 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2085 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2086
4ff7fb12 2087 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2088 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2089 "%s-%s-%d", netdev->name, "TxRx", ri++);
2090 ti++;
2091 } else if (q_vector->rx.ring) {
9fe93afd 2092 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2093 "%s-%s-%d", netdev->name, "rx", ri++);
2094 } else if (q_vector->tx.ring) {
9fe93afd 2095 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2096 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2097 } else {
2098 /* skip this unused q_vector */
2099 continue;
32aa77a4 2100 }
207867f5
AD		 2101 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2102 q_vector->name, q_vector);
9a799d71 2103 if (err) {
396e799c 2104 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2105 "Error: %d\n", err);
021230d4 2106 goto free_queue_irqs;
9a799d71 2107 }
207867f5
AD		 2108 /* If Flow Director is enabled, set interrupt affinity */
2109 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2110 /* assign the mask for this irq */
2111 irq_set_affinity_hint(entry->vector,
2112 q_vector->affinity_mask);
2113 }
9a799d71
AK		 2114 }
2115
021230d4 2116 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2117 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2118 if (err) {
396e799c 2119 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2120 goto free_queue_irqs;
9a799d71
AK		 2121 }
2122
9a799d71
AK		 2123 return 0;
2124
021230d4 2125free_queue_irqs:
207867f5
AD		 2126 while (vector) {
2127 vector--;
2128 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2129 NULL);
2130 free_irq(adapter->msix_entries[vector].vector,
2131 adapter->q_vector[vector]);
2132 }
021230d4
AV		 2133 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2134 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2135 kfree(adapter->msix_entries);
2136 adapter->msix_entries = NULL;
9a799d71
AK		 2137 return err;
2138}
2139
2140/**
021230d4 2141 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2142 * @irq: interrupt number
2143 * @data: pointer to a network interface device structure
9a799d71
AK		 2144 **/
2145static irqreturn_t ixgbe_intr(int irq, void *data)
2146{
a65151ba 2147 struct ixgbe_adapter *adapter = data;
9a799d71 2148 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2149 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2150 u32 eicr;
2151
54037505 2152 /*
6af3b9eb 2153 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2154 * before the read of EICR.
2155 */
2156 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2157
021230d4
AV		 2158 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2159 * therefore no explict interrupt disable is necessary */
2160 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2161 if (!eicr) {
6af3b9eb
ET		 2162 /*
2163 * shared interrupt alert!
f47cf66e 2164 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2165 * have disabled interrupts due to EIAM
2166 * finish the workaround of silicon errata on 82598. Unmask
2167 * the interrupt that we masked before the EICR read.
2168 */
2169 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2170 ixgbe_irq_enable(adapter, true, true);
9a799d71 2171 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2172 }
9a799d71 2173
cf8280ee
JB		 2174 if (eicr & IXGBE_EICR_LSC)
2175 ixgbe_check_lsc(adapter);
021230d4 2176
bd508178
AD		 2177 switch (hw->mac.type) {
2178 case ixgbe_mac_82599EB:
e8e26350 2179 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2180 /* Fall through */
2181 case ixgbe_mac_X540:
2182 if (eicr & IXGBE_EICR_ECC)
2183 e_info(link, "Received unrecoverable ECC err, please "
2184 "reboot\n");
4f51bf70 2185 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2186 break;
2187 default:
2188 break;
2189 }
e8e26350 2190
0befdb3e
JB		 2191 ixgbe_check_fan_failure(adapter, eicr);
2192
7a921c93 2193 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2194 /* would disable interrupts here but EIAM disabled it */
7a921c93 2195 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2196 }
2197
6af3b9eb
ET		 2198 /*
2199 * re-enable link(maybe) and non-queue interrupts, no flush.
2200 * ixgbe_poll will re-enable the queue interrupts
2201 */
2202
2203 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2204 ixgbe_irq_enable(adapter, false, false);
2205
9a799d71
AK		 2206 return IRQ_HANDLED;
2207}
2208
021230d4
AV		 2209static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2210{
efe3d3c8
AD		 2211 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2212 int i;
2213
2214 /* legacy and MSI only use one vector */
2215 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2216 q_vectors = 1;
2217
2218 for (i = 0; i < adapter->num_rx_queues; i++) {
2219 adapter->rx_ring[i]->q_vector = NULL;
2220 adapter->rx_ring[i]->next = NULL;
2221 }
2222 for (i = 0; i < adapter->num_tx_queues; i++) {
2223 adapter->tx_ring[i]->q_vector = NULL;
2224 adapter->tx_ring[i]->next = NULL;
2225 }
021230d4
AV		 2226
2227 for (i = 0; i < q_vectors; i++) {
7a921c93 2228 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2229 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2230 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2231 }
2232}
2233
9a799d71
AK		 2234/**
2235 * ixgbe_request_irq - initialize interrupts
2236 * @adapter: board private structure
2237 *
2238 * Attempts to configure interrupts using the best available
2239 * capabilities of the hardware and kernel.
2240 **/
021230d4 2241static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2242{
2243 struct net_device *netdev = adapter->netdev;
021230d4 2244 int err;
9a799d71 2245
4cc6df29
AD		 2246 /* map all of the rings to the q_vectors */
2247 ixgbe_map_rings_to_vectors(adapter);
2248
2249 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2250 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2251 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2252 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2253 netdev->name, adapter);
4cc6df29 2254 else
a0607fd3 2255 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2256 netdev->name, adapter);
9a799d71 2257
4cc6df29 2258 if (err) {
396e799c 2259 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2260
4cc6df29
AD		 2261 /* place q_vectors and rings back into a known good state */
2262 ixgbe_reset_q_vectors(adapter);
2263 }
2264
9a799d71
AK		 2265 return err;
2266}
2267
2268static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2269{
9a799d71 2270 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2271 int i, q_vectors;
9a799d71 2272
021230d4 2273 q_vectors = adapter->num_msix_vectors;
021230d4 2274 i = q_vectors - 1;
a65151ba 2275 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2276 i--;
4cc6df29 2277
021230d4 2278 for (; i >= 0; i--) {
894ff7cf 2279 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2280 if (!adapter->q_vector[i]->rx.ring &&
2281 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2282 continue;
2283
207867f5
AD		 2284 /* clear the affinity_mask in the IRQ descriptor */
2285 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2286 NULL);
2287
021230d4 2288 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2289 adapter->q_vector[i]);
021230d4 2290 }
021230d4 2291 } else {
a65151ba 2292 free_irq(adapter->pdev->irq, adapter);
9a799d71 2293 }
207867f5
AD		 2294
2295 /* clear q_vector state information */
2296 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2297}
2298
22d5a71b
JB		 2299/**
2300 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2301 * @adapter: board private structure
2302 **/
2303static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2304{
bd508178
AD		 2305 switch (adapter->hw.mac.type) {
2306 case ixgbe_mac_82598EB:
835462fc 2307 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2308 break;
2309 case ixgbe_mac_82599EB:
b93a2226 2310 case ixgbe_mac_X540:
835462fc
NS		 2311 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2312 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2314 break;
2315 default:
2316 break;
22d5a71b
JB		 2317 }
2318 IXGBE_WRITE_FLUSH(&adapter->hw);
2319 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2320 int i;
2321 for (i = 0; i < adapter->num_msix_vectors; i++)
2322 synchronize_irq(adapter->msix_entries[i].vector);
2323 } else {
2324 synchronize_irq(adapter->pdev->irq);
2325 }
2326}
2327
9a799d71
AK		 2328/**
2329 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2330 *
2331 **/
2332static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2333{
d5bf4f67 2334 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2335
d5bf4f67
ET		 2336 /* rx/tx vector */
2337 if (adapter->rx_itr_setting == 1)
2338 q_vector->itr = IXGBE_20K_ITR;
2339 else
2340 q_vector->itr = adapter->rx_itr_setting;
2341
2342 ixgbe_write_eitr(q_vector);
9a799d71 2343
e8e26350
PW		 2344 ixgbe_set_ivar(adapter, 0, 0, 0);
2345 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2346
396e799c 2347 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2348}
2349
43e69bf0
AD		 2350/**
2351 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2352 * @adapter: board private structure
2353 * @ring: structure containing ring specific data
2354 *
2355 * Configure the Tx descriptor ring after a reset.
2356 **/
84418e3b
AD		 2357void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2358 struct ixgbe_ring *ring)
43e69bf0
AD		 2359{
2360 struct ixgbe_hw *hw = &adapter->hw;
2361 u64 tdba = ring->dma;
2f1860b8 2362 int wait_loop = 10;
b88c6de2 2363 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2364 u8 reg_idx = ring->reg_idx;
43e69bf0 2365
2f1860b8 2366 /* disable queue to avoid issues while updating state */
b88c6de2 2367 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2368 IXGBE_WRITE_FLUSH(hw);
2369
43e69bf0 2370 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2371 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2372 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2373 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2374 ring->count * sizeof(union ixgbe_adv_tx_desc));
2375 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2376 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2377 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2378
b88c6de2
AD		 2379 /*
2380 * set WTHRESH to encourage burst writeback, it should not be set
2381 * higher than 1 when ITR is 0 as it could cause false TX hangs
2382 *
2383 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2384 * to or less than the number of on chip descriptors, which is
2385 * currently 40.
2386 */
2387 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2388 txdctl |= (1 << 16); /* WTHRESH = 1 */
2389 else
2390 txdctl |= (8 << 16); /* WTHRESH = 8 */
2391
2392 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2393 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2394 32; /* PTHRESH = 32 */
2f1860b8
AD		 2395
2396 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2397 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2398 adapter->atr_sample_rate) {
2399 ring->atr_sample_rate = adapter->atr_sample_rate;
2400 ring->atr_count = 0;
2401 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2402 } else {
2403 ring->atr_sample_rate = 0;
2404 }
2f1860b8 2405
c84d324c
JF		 2406 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2407
2f1860b8 2408 /* enable queue */
2f1860b8
AD		 2409 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2410
2411 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2412 if (hw->mac.type == ixgbe_mac_82598EB &&
2413 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2414 return;
2415
2416 /* poll to verify queue is enabled */
2417 do {
032b4325 2418 usleep_range(1000, 2000);
2f1860b8
AD		 2419 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2420 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2421 if (!wait_loop)
2422 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2423}
2424
120ff942
AD		 2425static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2426{
2427 struct ixgbe_hw *hw = &adapter->hw;
2428 u32 rttdcs;
72a32f1f 2429 u32 reg;
8b1c0b24 2430 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2431
2432 if (hw->mac.type == ixgbe_mac_82598EB)
2433 return;
2434
2435 /* disable the arbiter while setting MTQC */
2436 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2437 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2438 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2439
2440 /* set transmit pool layout */
8b1c0b24 2441 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2442 case (IXGBE_FLAG_SRIOV_ENABLED):
2443 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2444 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2445 break;
8b1c0b24
JF		 2446 default:
2447 if (!tcs)
2448 reg = IXGBE_MTQC_64Q_1PB;
2449 else if (tcs <= 4)
2450 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2451 else
2452 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2453
8b1c0b24 2454 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2455
8b1c0b24
JF		 2456 /* Enable Security TX Buffer IFG for multiple pb */
2457 if (tcs) {
2458 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2459 reg |= IXGBE_SECTX_DCB;
2460 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2461 }
120ff942
AD		 2462 break;
2463 }
2464
2465 /* re-enable the arbiter */
2466 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2467 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2468}
2469
9a799d71 2470/**
3a581073 2471 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2472 * @adapter: board private structure
2473 *
2474 * Configure the Tx unit of the MAC after a reset.
2475 **/
2476static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2477{
2f1860b8
AD		 2478 struct ixgbe_hw *hw = &adapter->hw;
2479 u32 dmatxctl;
43e69bf0 2480 u32 i;
9a799d71 2481
2f1860b8
AD		 2482 ixgbe_setup_mtqc(adapter);
2483
2484 if (hw->mac.type != ixgbe_mac_82598EB) {
2485 /* DMATXCTL.EN must be before Tx queues are enabled */
2486 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2487 dmatxctl |= IXGBE_DMATXCTL_TE;
2488 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2489 }
2490
9a799d71 2491 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2492 for (i = 0; i < adapter->num_tx_queues; i++)
2493 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2494}
2495
e8e26350 2496#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2497
a6616b42 2498static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2499 struct ixgbe_ring *rx_ring)
cc41ac7c 2500{
cc41ac7c 2501 u32 srrctl;
bf29ee6c 2502 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2503
bd508178
AD		 2504 switch (adapter->hw.mac.type) {
2505 case ixgbe_mac_82598EB: {
2506 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2507 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2508 reg_idx = reg_idx & mask;
cc41ac7c 2509 }
bd508178
AD		 2510 break;
2511 case ixgbe_mac_82599EB:
b93a2226 2512 case ixgbe_mac_X540:
bd508178
AD		 2513 default:
2514 break;
2515 }
2516
bf29ee6c 2517 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2518
2519 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2520 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2521 if (adapter->num_vfs)
2522 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2523
afafd5b0
AD		 2524 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2525 IXGBE_SRRCTL_BSIZEHDR_MASK;
2526
7d637bcc 2527 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2528#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2529 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2530#else
2531 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2532#endif
cc41ac7c 2533 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2534 } else {
afafd5b0
AD		 2535 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2536 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2537 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2538 }
e8e26350 2539
bf29ee6c 2540 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2541}
9a799d71 2542
05abb126 2543static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2544{
05abb126
AD		 2545 struct ixgbe_hw *hw = &adapter->hw;
2546 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2547 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2548 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2549 u32 mrqc = 0, reta = 0;
2550 u32 rxcsum;
2551 int i, j;
8b1c0b24 2552 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2553 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2554
2555 if (tcs)
2556 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2557
05abb126
AD		 2558 /* Fill out hash function seeds */
2559 for (i = 0; i < 10; i++)
2560 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2561
2562 /* Fill out redirection table */
2563 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2564 if (j == maxq)
05abb126
AD		 2565 j = 0;
2566 /* reta = 4-byte sliding window of
2567 * 0x00..(indices-1)(indices-1)00..etc. */
2568 reta = (reta << 8) | (j * 0x11);
2569 if ((i & 3) == 3)
2570 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2571 }
0cefafad 2572
05abb126
AD		 2573 /* Disable indicating checksum in descriptor, enables RSS hash */
2574 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2575 rxcsum |= IXGBE_RXCSUM_PCSD;
2576 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2577
8b1c0b24
JF		 2578 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2579 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2580 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2581 } else {
2582 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2583 | IXGBE_FLAG_SRIOV_ENABLED);
2584
2585 switch (mask) {
2586 case (IXGBE_FLAG_RSS_ENABLED):
2587 if (!tcs)
2588 mrqc = IXGBE_MRQC_RSSEN;
2589 else if (tcs <= 4)
2590 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2591 else
2592 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2593 break;
2594 case (IXGBE_FLAG_SRIOV_ENABLED):
2595 mrqc = IXGBE_MRQC_VMDQEN;
2596 break;
2597 default:
2598 break;
2599 }
0cefafad
JB		 2600 }
2601
05abb126
AD		 2602 /* Perform hash on these packet types */
2603 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2604 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2605 | IXGBE_MRQC_RSS_FIELD_IPV6
2606 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2607
2608 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2609}
2610
bb5a9ad2
NS		 2611/**
2612 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2613 * @adapter: address of board private structure
2614 * @index: index of ring to set
bb5a9ad2 2615 **/
082757af 2616static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2617 struct ixgbe_ring *ring)
bb5a9ad2 2618{
bb5a9ad2 2619 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2620 u32 rscctrl;
edd2ea55 2621 int rx_buf_len;
bf29ee6c 2622 u8 reg_idx = ring->reg_idx;
7367096a 2623
7d637bcc 2624 if (!ring_is_rsc_enabled(ring))
7367096a 2625 return;
bb5a9ad2 2626
7367096a
AD		 2627 rx_buf_len = ring->rx_buf_len;
2628 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2629 rscctrl |= IXGBE_RSCCTL_RSCEN;
2630 /*
2631 * we must limit the number of descriptors so that the
2632 * total size of max desc * buf_len is not greater
2633 * than 65535
2634 */
7d637bcc 2635 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2636#if (MAX_SKB_FRAGS > 16)
2637 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2638#elif (MAX_SKB_FRAGS > 8)
2639 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2640#elif (MAX_SKB_FRAGS > 4)
2641 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2642#else
2643 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2644#endif
2645 } else {
919e78a6 2646 if (rx_buf_len < IXGBE_RXBUFFER_4K)
bb5a9ad2 2647 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
919e78a6 2648 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2649 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2650 else
2651 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2652 }
7367096a 2653 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2654}
2655
9e10e045
AD		 2656/**
2657 * ixgbe_set_uta - Set unicast filter table address
2658 * @adapter: board private structure
2659 *
2660 * The unicast table address is a register array of 32-bit registers.
2661 * The table is meant to be used in a way similar to how the MTA is used
2662 * however due to certain limitations in the hardware it is necessary to
2663 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2664 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2665 **/
2666static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2667{
2668 struct ixgbe_hw *hw = &adapter->hw;
2669 int i;
2670
2671 /* The UTA table only exists on 82599 hardware and newer */
2672 if (hw->mac.type < ixgbe_mac_82599EB)
2673 return;
2674
2675 /* we only need to do this if VMDq is enabled */
2676 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2677 return;
2678
2679 for (i = 0; i < 128; i++)
2680 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2681}
2682
2683#define IXGBE_MAX_RX_DESC_POLL 10
2684static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2685 struct ixgbe_ring *ring)
2686{
2687 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2688 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2689 u32 rxdctl;
bf29ee6c 2690 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2691
2692 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2693 if (hw->mac.type == ixgbe_mac_82598EB &&
2694 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2695 return;
2696
2697 do {
032b4325 2698 usleep_range(1000, 2000);
9e10e045
AD		 2699 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2700 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2701
2702 if (!wait_loop) {
2703 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2704 "the polling period\n", reg_idx);
2705 }
2706}
2707
2d39d576
YZ		 2708void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2709 struct ixgbe_ring *ring)
2710{
2711 struct ixgbe_hw *hw = &adapter->hw;
2712 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2713 u32 rxdctl;
2714 u8 reg_idx = ring->reg_idx;
2715
2716 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2717 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2718
2719 /* write value back with RXDCTL.ENABLE bit cleared */
2720 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2721
2722 if (hw->mac.type == ixgbe_mac_82598EB &&
2723 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2724 return;
2725
2726 /* the hardware may take up to 100us to really disable the rx queue */
2727 do {
2728 udelay(10);
2729 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2730 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2731
2732 if (!wait_loop) {
2733 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2734 "the polling period\n", reg_idx);
2735 }
2736}
2737
84418e3b
AD		 2738void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2739 struct ixgbe_ring *ring)
acd37177
AD		 2740{
2741 struct ixgbe_hw *hw = &adapter->hw;
2742 u64 rdba = ring->dma;
9e10e045 2743 u32 rxdctl;
bf29ee6c 2744 u8 reg_idx = ring->reg_idx;
acd37177 2745
9e10e045
AD		 2746 /* disable queue to avoid issues while updating state */
2747 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2748 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2749
acd37177
AD		 2750 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2751 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2752 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2753 ring->count * sizeof(union ixgbe_adv_rx_desc));
2754 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2755 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2756 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2757
2758 ixgbe_configure_srrctl(adapter, ring);
2759 ixgbe_configure_rscctl(adapter, ring);
2760
e9f98072
GR		 2761 /* If operating in IOV mode set RLPML for X540 */
2762 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2763 hw->mac.type == ixgbe_mac_X540) {
2764 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2765 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2766 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2767 }
2768
9e10e045
AD		 2769 if (hw->mac.type == ixgbe_mac_82598EB) {
2770 /*
2771 * enable cache line friendly hardware writes:
2772 * PTHRESH=32 descriptors (half the internal cache),
2773 * this also removes ugly rx_no_buffer_count increment
2774 * HTHRESH=4 descriptors (to minimize latency on fetch)
2775 * WTHRESH=8 burst writeback up to two cache lines
2776 */
2777 rxdctl &= ~0x3FFFFF;
2778 rxdctl |= 0x080420;
2779 }
2780
2781 /* enable receive descriptor ring */
2782 rxdctl |= IXGBE_RXDCTL_ENABLE;
2783 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2784
2785 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2786 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2787}
2788
48654521
AD		 2789static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2790{
2791 struct ixgbe_hw *hw = &adapter->hw;
2792 int p;
2793
2794 /* PSRTYPE must be initialized in non 82598 adapters */
2795 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2796 IXGBE_PSRTYPE_UDPHDR |
2797 IXGBE_PSRTYPE_IPV4HDR |
48654521 2798 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2799 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2800
2801 if (hw->mac.type == ixgbe_mac_82598EB)
2802 return;
2803
2804 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2805 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2806
2807 for (p = 0; p < adapter->num_rx_pools; p++)
2808 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2809 psrtype);
2810}
2811
f5b4a52e
AD		 2812static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2813{
2814 struct ixgbe_hw *hw = &adapter->hw;
2815 u32 gcr_ext;
2816 u32 vt_reg_bits;
2817 u32 reg_offset, vf_shift;
2818 u32 vmdctl;
de4c7f65 2819 int i;
f5b4a52e
AD		 2820
2821 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2822 return;
2823
2824 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2825 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2826 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2827 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2828
2829 vf_shift = adapter->num_vfs % 32;
2830 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2831
2832 /* Enable only the PF's pool for Tx/Rx */
2833 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2834 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2835 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2836 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2837 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2838
2839 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2840 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2841
2842 /*
2843 * Set up VF register offsets for selected VT Mode,
2844 * i.e. 32 or 64 VFs for SR-IOV
2845 */
2846 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2847 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2848 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2849 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2850
2851 /* enable Tx loopback for VF/PF communication */
2852 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2853 /* Enable MAC Anti-Spoofing */
a1cbb15c 2854 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 2855 (adapter->num_vfs != 0),
a985b6c3 2856 adapter->num_vfs);
de4c7f65
GR		 2857 /* For VFs that have spoof checking turned off */
2858 for (i = 0; i < adapter->num_vfs; i++) {
2859 if (!adapter->vfinfo[i].spoofchk_enabled)
2860 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2861 }
f5b4a52e
AD		 2862}
2863
477de6ed 2864static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2865{
9a799d71
AK		 2866 struct ixgbe_hw *hw = &adapter->hw;
2867 struct net_device *netdev = adapter->netdev;
2868 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2869 int rx_buf_len;
477de6ed
AD		 2870 struct ixgbe_ring *rx_ring;
2871 int i;
2872 u32 mhadd, hlreg0;
48654521 2873
9a799d71 2874 /* Decide whether to use packet split mode or not */
a124339a
DS		 2875 /* On by default */
2876 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2877
1cdd1ec8 2878 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2879 if (adapter->num_vfs)
2880 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2881
2882 /* Disable packet split due to 82599 erratum #45 */
2883 if (hw->mac.type == ixgbe_mac_82599EB)
2884 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2885
63f39bd1 2886#ifdef IXGBE_FCOE
477de6ed
AD		 2887 /* adjust max frame to be able to do baby jumbo for FCoE */
2888 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2889 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2890 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2891
477de6ed
AD		 2892#endif /* IXGBE_FCOE */
2893 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2894 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2895 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2896 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2897
2898 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2899 }
2900
919e78a6
AD		 2901 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2902 max_frame += VLAN_HLEN;
2903
2904 /* Set the RX buffer length according to the mode */
2905 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2906 rx_buf_len = IXGBE_RX_HDR_SIZE;
2907 } else {
2908 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2909 (netdev->mtu <= ETH_DATA_LEN))
2910 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2911 /*
2912 * Make best use of allocation by using all but 1K of a
2913 * power of 2 allocation that will be used for skb->head.
2914 */
2915 else if (max_frame <= IXGBE_RXBUFFER_3K)
2916 rx_buf_len = IXGBE_RXBUFFER_3K;
2917 else if (max_frame <= IXGBE_RXBUFFER_7K)
2918 rx_buf_len = IXGBE_RXBUFFER_7K;
2919 else if (max_frame <= IXGBE_RXBUFFER_15K)
2920 rx_buf_len = IXGBE_RXBUFFER_15K;
2921 else
2922 rx_buf_len = IXGBE_MAX_RXBUFFER;
2923 }
2924
477de6ed
AD		 2925 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2926 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2927 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2928 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2929
0cefafad
JB		 2930 /*
2931 * Setup the HW Rx Head and Tail Descriptor Pointers and
2932 * the Base and Length of the Rx Descriptor Ring
2933 */
9a799d71 2934 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2935 rx_ring = adapter->rx_ring[i];
a6616b42 2936 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2937
6e455b89 2938 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2939 set_ring_ps_enabled(rx_ring);
2940 else
2941 clear_ring_ps_enabled(rx_ring);
2942
2943 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2944 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2945 else
7d637bcc 2946 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 2947
63f39bd1 2948#ifdef IXGBE_FCOE
e8e9f696 2949 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2950 struct ixgbe_ring_feature *f;
2951 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 2952 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 2953 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 2954 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2955 rx_ring->rx_buf_len =
e8e9f696 2956 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 2957 } else if (!ring_is_rsc_enabled(rx_ring) &&
2958 !ring_is_ps_enabled(rx_ring)) {
2959 rx_ring->rx_buf_len =
2960 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2961 }
63f39bd1 2962 }
63f39bd1 2963#endif /* IXGBE_FCOE */
477de6ed 2964 }
477de6ed
AD		 2965}
2966
7367096a
AD		 2967static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2968{
2969 struct ixgbe_hw *hw = &adapter->hw;
2970 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2971
2972 switch (hw->mac.type) {
2973 case ixgbe_mac_82598EB:
2974 /*
2975 * For VMDq support of different descriptor types or
2976 * buffer sizes through the use of multiple SRRCTL
2977 * registers, RDRXCTL.MVMEN must be set to 1
2978 *
2979 * also, the manual doesn't mention it clearly but DCA hints
2980 * will only use queue 0's tags unless this bit is set. Side
2981 * effects of setting this bit are only that SRRCTL must be
2982 * fully programmed [0..15]
2983 */
2984 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2985 break;
2986 case ixgbe_mac_82599EB:
b93a2226 2987 case ixgbe_mac_X540:
7367096a
AD		 2988 /* Disable RSC for ACK packets */
2989 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2990 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2991 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2992 /* hardware requires some bits to be set by default */
2993 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2994 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2995 break;
2996 default:
2997 /* We should do nothing since we don't know this hardware */
2998 return;
2999 }
3000
3001 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3002}
3003
477de6ed
AD		 3004/**
3005 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3006 * @adapter: board private structure
3007 *
3008 * Configure the Rx unit of the MAC after a reset.
3009 **/
3010static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3011{
3012 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3013 int i;
3014 u32 rxctrl;
477de6ed
AD		 3015
3016 /* disable receives while setting up the descriptors */
3017 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3018 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3019
3020 ixgbe_setup_psrtype(adapter);
7367096a 3021 ixgbe_setup_rdrxctl(adapter);
477de6ed 3022
9e10e045 3023 /* Program registers for the distribution of queues */
f5b4a52e 3024 ixgbe_setup_mrqc(adapter);
f5b4a52e 3025
9e10e045
AD		 3026 ixgbe_set_uta(adapter);
3027
477de6ed
AD		 3028 /* set_rx_buffer_len must be called before ring initialization */
3029 ixgbe_set_rx_buffer_len(adapter);
3030
3031 /*
3032 * Setup the HW Rx Head and Tail Descriptor Pointers and
3033 * the Base and Length of the Rx Descriptor Ring
3034 */
9e10e045
AD		 3035 for (i = 0; i < adapter->num_rx_queues; i++)
3036 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3037
9e10e045
AD		 3038 /* disable drop enable for 82598 parts */
3039 if (hw->mac.type == ixgbe_mac_82598EB)
3040 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3041
3042 /* enable all receives */
3043 rxctrl |= IXGBE_RXCTRL_RXEN;
3044 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3045}
3046
068c89b0
DS		 3047static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3048{
3049 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3050 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3051 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3052
3053 /* add VID to filter table */
1ada1b1b 3054 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3055 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3056}
3057
3058static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3059{
3060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3061 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3062 int pool_ndx = adapter->num_vfs;
068c89b0 3063
068c89b0 3064 /* remove VID from filter table */
1ada1b1b 3065 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3066 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3067}
3068
5f6c0181
JB		 3069/**
3070 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3071 * @adapter: driver data
3072 */
3073static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3074{
3075 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3076 u32 vlnctrl;
3077
3078 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3079 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3080 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3081}
3082
3083/**
3084 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3085 * @adapter: driver data
3086 */
3087static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3088{
3089 struct ixgbe_hw *hw = &adapter->hw;
3090 u32 vlnctrl;
3091
3092 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3093 vlnctrl |= IXGBE_VLNCTRL_VFE;
3094 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3095 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3096}
3097
3098/**
3099 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3100 * @adapter: driver data
3101 */
3102static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3103{
3104 struct ixgbe_hw *hw = &adapter->hw;
3105 u32 vlnctrl;
5f6c0181
JB		 3106 int i, j;
3107
3108 switch (hw->mac.type) {
3109 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3110 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3111 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3112 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3113 break;
3114 case ixgbe_mac_82599EB:
b93a2226 3115 case ixgbe_mac_X540:
5f6c0181
JB		 3116 for (i = 0; i < adapter->num_rx_queues; i++) {
3117 j = adapter->rx_ring[i]->reg_idx;
3118 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3119 vlnctrl &= ~IXGBE_RXDCTL_VME;
3120 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3121 }
3122 break;
3123 default:
3124 break;
3125 }
3126}
3127
3128/**
f62bbb5e 3129 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3130 * @adapter: driver data
3131 */
f62bbb5e 3132static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3133{
3134 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3135 u32 vlnctrl;
5f6c0181
JB		 3136 int i, j;
3137
3138 switch (hw->mac.type) {
3139 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3140 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3141 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3142 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3143 break;
3144 case ixgbe_mac_82599EB:
b93a2226 3145 case ixgbe_mac_X540:
5f6c0181
JB		 3146 for (i = 0; i < adapter->num_rx_queues; i++) {
3147 j = adapter->rx_ring[i]->reg_idx;
3148 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3149 vlnctrl |= IXGBE_RXDCTL_VME;
3150 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3151 }
3152 break;
3153 default:
3154 break;
3155 }
3156}
3157
9a799d71
AK		 3158static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3159{
f62bbb5e 3160 u16 vid;
9a799d71 3161
f62bbb5e
JG		 3162 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3163
3164 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3165 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3166}
3167
2850062a
AD		 3168/**
3169 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3170 * @netdev: network interface device structure
3171 *
3172 * Writes unicast address list to the RAR table.
3173 * Returns: -ENOMEM on failure/insufficient address space
3174 * 0 on no addresses written
3175 * X on writing X addresses to the RAR table
3176 **/
3177static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3178{
3179 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3180 struct ixgbe_hw *hw = &adapter->hw;
3181 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3182 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3183 int count = 0;
3184
3185 /* return ENOMEM indicating insufficient memory for addresses */
3186 if (netdev_uc_count(netdev) > rar_entries)
3187 return -ENOMEM;
3188
3189 if (!netdev_uc_empty(netdev) && rar_entries) {
3190 struct netdev_hw_addr *ha;
3191 /* return error if we do not support writing to RAR table */
3192 if (!hw->mac.ops.set_rar)
3193 return -ENOMEM;
3194
3195 netdev_for_each_uc_addr(ha, netdev) {
3196 if (!rar_entries)
3197 break;
3198 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3199 vfn, IXGBE_RAH_AV);
3200 count++;
3201 }
3202 }
3203 /* write the addresses in reverse order to avoid write combining */
3204 for (; rar_entries > 0 ; rar_entries--)
3205 hw->mac.ops.clear_rar(hw, rar_entries);
3206
3207 return count;
3208}
3209
9a799d71 3210/**
2c5645cf 3211 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3212 * @netdev: network interface device structure
3213 *
2c5645cf
CL		 3214 * The set_rx_method entry point is called whenever the unicast/multicast
3215 * address list or the network interface flags are updated. This routine is
3216 * responsible for configuring the hardware for proper unicast, multicast and
3217 * promiscuous mode.
9a799d71 3218 **/
7f870475 3219void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3220{
3221 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3222 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3223 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3224 int count;
9a799d71
AK		 3225
3226 /* Check for Promiscuous and All Multicast modes */
3227
3228 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3229
f5dc442b
AD		 3230 /* set all bits that we expect to always be set */
3231 fctrl |= IXGBE_FCTRL_BAM;
3232 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3233 fctrl |= IXGBE_FCTRL_PMCF;
3234
2850062a
AD		 3235 /* clear the bits we are changing the status of */
3236 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3237
9a799d71 3238 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3239 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3240 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3241 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3242 /* don't hardware filter vlans in promisc mode */
3243 ixgbe_vlan_filter_disable(adapter);
9a799d71 3244 } else {
746b9f02
PM		 3245 if (netdev->flags & IFF_ALLMULTI) {
3246 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3247 vmolr |= IXGBE_VMOLR_MPE;
3248 } else {
3249 /*
3250 * Write addresses to the MTA, if the attempt fails
25985edc 3251 * then we should just turn on promiscuous mode so
2850062a
AD		 3252 * that we can at least receive multicast traffic
3253 */
3254 hw->mac.ops.update_mc_addr_list(hw, netdev);
3255 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3256 }
5f6c0181 3257 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3258 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3259 /*
3260 * Write addresses to available RAR registers, if there is not
3261 * sufficient space to store all the addresses then enable
25985edc 3262 * unicast promiscuous mode
2850062a
AD		 3263 */
3264 count = ixgbe_write_uc_addr_list(netdev);
3265 if (count < 0) {
3266 fctrl |= IXGBE_FCTRL_UPE;
3267 vmolr |= IXGBE_VMOLR_ROPE;
3268 }
9a799d71
AK		 3269 }
3270
2850062a 3271 if (adapter->num_vfs) {
1cdd1ec8 3272 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3273 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3274 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3275 IXGBE_VMOLR_ROPE);
3276 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3277 }
3278
3279 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3280
3281 if (netdev->features & NETIF_F_HW_VLAN_RX)
3282 ixgbe_vlan_strip_enable(adapter);
3283 else
3284 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3285}
3286
021230d4
AV		 3287static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3288{
3289 int q_idx;
3290 struct ixgbe_q_vector *q_vector;
3291 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3292
3293 /* legacy and MSI only use one vector */
3294 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3295 q_vectors = 1;
3296
3297 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3298 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3299 napi_enable(&q_vector->napi);
021230d4
AV		 3300 }
3301}
3302
3303static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3304{
3305 int q_idx;
3306 struct ixgbe_q_vector *q_vector;
3307 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3308
3309 /* legacy and MSI only use one vector */
3310 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3311 q_vectors = 1;
3312
3313 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3314 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3315 napi_disable(&q_vector->napi);
3316 }
3317}
3318
7a6b6f51 3319#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3320/*
3321 * ixgbe_configure_dcb - Configure DCB hardware
3322 * @adapter: ixgbe adapter struct
3323 *
3324 * This is called by the driver on open to configure the DCB hardware.
3325 * This is also called by the gennetlink interface when reconfiguring
3326 * the DCB state.
3327 */
3328static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3329{
3330 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3331 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3332
67ebd791
AD		 3333 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3334 if (hw->mac.type == ixgbe_mac_82598EB)
3335 netif_set_gso_max_size(adapter->netdev, 65536);
3336 return;
3337 }
3338
3339 if (hw->mac.type == ixgbe_mac_82598EB)
3340 netif_set_gso_max_size(adapter->netdev, 32768);
3341
2f90b865 3342
2f90b865 3343 /* Enable VLAN tag insert/strip */
f62bbb5e 3344 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3345
2f90b865 3346 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3347
971060b1 3348#ifdef IXGBE_FCOE
b120818e
JF		 3349 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3350 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3351#endif
b120818e
JF		 3352
3353 /* reconfigure the hardware */
3354 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3355 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3356 DCB_TX_CONFIG);
3357 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3358 DCB_RX_CONFIG);
3359 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3360 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3361 ixgbe_dcb_hw_ets(&adapter->hw,
3362 adapter->ixgbe_ieee_ets,
3363 max_frame);
3364 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3365 adapter->ixgbe_ieee_pfc->pfc_en,
3366 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3367 }
8187cd48
JF		 3368
3369 /* Enable RSS Hash per TC */
3370 if (hw->mac.type != ixgbe_mac_82598EB) {
3371 int i;
3372 u32 reg = 0;
3373
3374 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3375 u8 msb = 0;
3376 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3377
3378 while (cnt >>= 1)
3379 msb++;
3380
3381 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3382 }
3383 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3384 }
2f90b865 3385}
9da712d2
JF		 3386#endif
3387
3388/* Additional bittime to account for IXGBE framing */
3389#define IXGBE_ETH_FRAMING 20
3390
3391/*
3392 * ixgbe_hpbthresh - calculate high water mark for flow control
3393 *
3394 * @adapter: board private structure to calculate for
3395 * @pb - packet buffer to calculate
3396 */
3397static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3398{
3399 struct ixgbe_hw *hw = &adapter->hw;
3400 struct net_device *dev = adapter->netdev;
3401 int link, tc, kb, marker;
3402 u32 dv_id, rx_pba;
3403
3404 /* Calculate max LAN frame size */
3405 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3406
3407#ifdef IXGBE_FCOE
3408 /* FCoE traffic class uses FCOE jumbo frames */
3409 if (dev->features & NETIF_F_FCOE_MTU) {
3410 int fcoe_pb = 0;
2f90b865 3411
9da712d2
JF		 3412#ifdef CONFIG_IXGBE_DCB
3413 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3414
3415#endif
3416 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3417 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3418 }
2f90b865 3419#endif
80605c65 3420
9da712d2
JF		 3421 /* Calculate delay value for device */
3422 switch (hw->mac.type) {
3423 case ixgbe_mac_X540:
3424 dv_id = IXGBE_DV_X540(link, tc);
3425 break;
3426 default:
3427 dv_id = IXGBE_DV(link, tc);
3428 break;
3429 }
3430
3431 /* Loopback switch introduces additional latency */
3432 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3433 dv_id += IXGBE_B2BT(tc);
3434
3435 /* Delay value is calculated in bit times convert to KB */
3436 kb = IXGBE_BT2KB(dv_id);
3437 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3438
3439 marker = rx_pba - kb;
3440
3441 /* It is possible that the packet buffer is not large enough
3442 * to provide required headroom. In this case throw an error
3443 * to user and a do the best we can.
3444 */
3445 if (marker < 0) {
3446 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3447 "headroom to support flow control."
3448 "Decrease MTU or number of traffic classes\n", pb);
3449 marker = tc + 1;
3450 }
3451
3452 return marker;
3453}
3454
3455/*
3456 * ixgbe_lpbthresh - calculate low water mark for for flow control
3457 *
3458 * @adapter: board private structure to calculate for
3459 * @pb - packet buffer to calculate
3460 */
3461static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3462{
3463 struct ixgbe_hw *hw = &adapter->hw;
3464 struct net_device *dev = adapter->netdev;
3465 int tc;
3466 u32 dv_id;
3467
3468 /* Calculate max LAN frame size */
3469 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3470
3471 /* Calculate delay value for device */
3472 switch (hw->mac.type) {
3473 case ixgbe_mac_X540:
3474 dv_id = IXGBE_LOW_DV_X540(tc);
3475 break;
3476 default:
3477 dv_id = IXGBE_LOW_DV(tc);
3478 break;
3479 }
3480
3481 /* Delay value is calculated in bit times convert to KB */
3482 return IXGBE_BT2KB(dv_id);
3483}
3484
3485/*
3486 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3487 */
3488static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3489{
3490 struct ixgbe_hw *hw = &adapter->hw;
3491 int num_tc = netdev_get_num_tc(adapter->netdev);
3492 int i;
3493
3494 if (!num_tc)
3495 num_tc = 1;
3496
3497 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3498
3499 for (i = 0; i < num_tc; i++) {
3500 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3501
3502 /* Low water marks must not be larger than high water marks */
3503 if (hw->fc.low_water > hw->fc.high_water[i])
3504 hw->fc.low_water = 0;
3505 }
3506}
3507
80605c65
JF		 3508static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3509{
80605c65 3510 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3511 int hdrm;
3512 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3513
3514 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3515 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3516 hdrm = 32 << adapter->fdir_pballoc;
3517 else
3518 hdrm = 0;
80605c65 3519
f7e1027f 3520 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3521 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3522}
3523
e4911d57
AD		 3524static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3525{
3526 struct ixgbe_hw *hw = &adapter->hw;
3527 struct hlist_node *node, *node2;
3528 struct ixgbe_fdir_filter *filter;
3529
3530 spin_lock(&adapter->fdir_perfect_lock);
3531
3532 if (!hlist_empty(&adapter->fdir_filter_list))
3533 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3534
3535 hlist_for_each_entry_safe(filter, node, node2,
3536 &adapter->fdir_filter_list, fdir_node) {
3537 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3538 &filter->filter,
3539 filter->sw_idx,
3540 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3541 IXGBE_FDIR_DROP_QUEUE :
3542 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3543 }
3544
3545 spin_unlock(&adapter->fdir_perfect_lock);
3546}
3547
9a799d71
AK		 3548static void ixgbe_configure(struct ixgbe_adapter *adapter)
3549{
80605c65 3550 ixgbe_configure_pb(adapter);
7a6b6f51 3551#ifdef CONFIG_IXGBE_DCB
67ebd791 3552 ixgbe_configure_dcb(adapter);
2f90b865 3553#endif
9a799d71 3554
4c1d7b4b 3555 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3556 ixgbe_restore_vlan(adapter);
3557
eacd73f7
YZ		 3558#ifdef IXGBE_FCOE
3559 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3560 ixgbe_configure_fcoe(adapter);
3561
3562#endif /* IXGBE_FCOE */
c4cf55e5 3563 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3564 ixgbe_init_fdir_signature_82599(&adapter->hw,
3565 adapter->fdir_pballoc);
e4911d57
AD		 3566 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3567 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3568 adapter->fdir_pballoc);
3569 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3570 }
4c1d7b4b 3571
933d41f1 3572 ixgbe_configure_virtualization(adapter);
c4cf55e5 3573
9a799d71
AK		 3574 ixgbe_configure_tx(adapter);
3575 ixgbe_configure_rx(adapter);
9a799d71
AK		 3576}
3577
e8e26350
PW		 3578static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3579{
3580 switch (hw->phy.type) {
3581 case ixgbe_phy_sfp_avago:
3582 case ixgbe_phy_sfp_ftl:
3583 case ixgbe_phy_sfp_intel:
3584 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3585 case ixgbe_phy_sfp_passive_tyco:
3586 case ixgbe_phy_sfp_passive_unknown:
3587 case ixgbe_phy_sfp_active_unknown:
3588 case ixgbe_phy_sfp_ftl_active:
e8e26350 3589 return true;
8917b447
AD		 3590 case ixgbe_phy_nl:
3591 if (hw->mac.type == ixgbe_mac_82598EB)
3592 return true;
e8e26350
PW		 3593 default:
3594 return false;
3595 }
3596}
3597
0ecc061d 3598/**
e8e26350
PW		 3599 * ixgbe_sfp_link_config - set up SFP+ link
3600 * @adapter: pointer to private adapter struct
3601 **/
3602static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3603{
7086400d
AD		 3604 /*
3605 * We are assuming the worst case scenerio here, and that
3606 * is that an SFP was inserted/removed after the reset
3607 * but before SFP detection was enabled. As such the best
3608 * solution is to just start searching as soon as we start
3609 */
3610 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3611 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3612
7086400d 3613 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3614}
3615
3616/**
3617 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3618 * @hw: pointer to private hardware struct
3619 *
3620 * Returns 0 on success, negative on failure
3621 **/
e8e26350 3622static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3623{
3624 u32 autoneg;
8620a103 3625 bool negotiation, link_up = false;
0ecc061d
PWJ		 3626 u32 ret = IXGBE_ERR_LINK_SETUP;
3627
3628 if (hw->mac.ops.check_link)
3629 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3630
3631 if (ret)
3632 goto link_cfg_out;
3633
0b0c2b31
ET		 3634 autoneg = hw->phy.autoneg_advertised;
3635 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3636 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3637 &negotiation);
0ecc061d
PWJ		 3638 if (ret)
3639 goto link_cfg_out;
3640
8620a103
MC		 3641 if (hw->mac.ops.setup_link)
3642 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3643link_cfg_out:
3644 return ret;
3645}
3646
a34bcfff 3647static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3648{
9a799d71 3649 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3650 u32 gpie = 0;
9a799d71 3651
9b471446 3652 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3653 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3654 IXGBE_GPIE_OCD;
3655 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3656 /*
3657 * use EIAM to auto-mask when MSI-X interrupt is asserted
3658 * this saves a register write for every interrupt
3659 */
3660 switch (hw->mac.type) {
3661 case ixgbe_mac_82598EB:
3662 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3663 break;
9b471446 3664 case ixgbe_mac_82599EB:
b93a2226
DS		 3665 case ixgbe_mac_X540:
3666 default:
9b471446
JB		 3667 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3668 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3669 break;
3670 }
3671 } else {
021230d4
AV		 3672 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3673 * specifically only auto mask tx and rx interrupts */
3674 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3675 }
9a799d71 3676
a34bcfff
AD		 3677 /* XXX: to interrupt immediately for EICS writes, enable this */
3678 /* gpie |= IXGBE_GPIE_EIMEN; */
3679
3680 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3681 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3682 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3683 }
3684
5fdd31f9 3685 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3686 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3687 switch (adapter->hw.mac.type) {
3688 case ixgbe_mac_82599EB:
3689 gpie |= IXGBE_SDP0_GPIEN;
3690 break;
3691 case ixgbe_mac_X540:
3692 gpie |= IXGBE_EIMS_TS;
3693 break;
3694 default:
3695 break;
3696 }
3697 }
5fdd31f9 3698
a34bcfff
AD		 3699 /* Enable fan failure interrupt */
3700 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3701 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3702
2698b208 3703 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3704 gpie |= IXGBE_SDP1_GPIEN;
3705 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3706 }
a34bcfff
AD		 3707
3708 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3709}
3710
c7ccde0f 3711static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3712{
3713 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3714 int err;
a34bcfff
AD		 3715 u32 ctrl_ext;
3716
3717 ixgbe_get_hw_control(adapter);
3718 ixgbe_setup_gpie(adapter);
e8e26350 3719
9a799d71
AK		 3720 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3721 ixgbe_configure_msix(adapter);
3722 else
3723 ixgbe_configure_msi_and_legacy(adapter);
3724
c6ecf39a
DS		 3725 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3726 if (hw->mac.ops.enable_tx_laser &&
3727 ((hw->phy.multispeed_fiber) ||
9f911707 3728 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3729 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3730 hw->mac.ops.enable_tx_laser(hw);
3731
9a799d71 3732 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3733 ixgbe_napi_enable_all(adapter);
3734
73c4b7cd
AD		 3735 if (ixgbe_is_sfp(hw)) {
3736 ixgbe_sfp_link_config(adapter);
3737 } else {
3738 err = ixgbe_non_sfp_link_config(hw);
3739 if (err)
3740 e_err(probe, "link_config FAILED %d\n", err);
3741 }
3742
021230d4
AV		 3743 /* clear any pending interrupts, may auto mask */
3744 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3745 ixgbe_irq_enable(adapter, true, true);
9a799d71 3746
bf069c97
DS		 3747 /*
3748 * If this adapter has a fan, check to see if we had a failure
3749 * before we enabled the interrupt.
3750 */
3751 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3752 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3753 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3754 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3755 }
3756
1da100bb 3757 /* enable transmits */
477de6ed 3758 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3759
9a799d71
AK		 3760 /* bring the link up in the watchdog, this could race with our first
3761 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3762 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3763 adapter->link_check_timeout = jiffies;
7086400d 3764 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3765
3766 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3767 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3768 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3769 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3770}
3771
d4f80882
AV		 3772void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3773{
3774 WARN_ON(in_interrupt());
7086400d
AD		 3775 /* put off any impending NetWatchDogTimeout */
3776 adapter->netdev->trans_start = jiffies;
3777
d4f80882 3778 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3779 usleep_range(1000, 2000);
d4f80882 3780 ixgbe_down(adapter);
5809a1ae
GR		 3781 /*
3782 * If SR-IOV enabled then wait a bit before bringing the adapter
3783 * back up to give the VFs time to respond to the reset. The
3784 * two second wait is based upon the watchdog timer cycle in
3785 * the VF driver.
3786 */
3787 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3788 msleep(2000);
d4f80882
AV		 3789 ixgbe_up(adapter);
3790 clear_bit(__IXGBE_RESETTING, &adapter->state);
3791}
3792
c7ccde0f 3793void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3794{
3795 /* hardware has been reset, we need to reload some things */
3796 ixgbe_configure(adapter);
3797
c7ccde0f 3798 ixgbe_up_complete(adapter);
9a799d71
AK		 3799}
3800
3801void ixgbe_reset(struct ixgbe_adapter *adapter)
3802{
c44ade9e 3803 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3804 int err;
3805
7086400d
AD		 3806 /* lock SFP init bit to prevent race conditions with the watchdog */
3807 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3808 usleep_range(1000, 2000);
3809
3810 /* clear all SFP and link config related flags while holding SFP_INIT */
3811 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3812 IXGBE_FLAG2_SFP_NEEDS_RESET);
3813 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3814
8ca783ab 3815 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3816 switch (err) {
3817 case 0:
3818 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3819 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3820 break;
3821 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3822 e_dev_err("master disable timed out\n");
da4dd0f7 3823 break;
794caeb2
PWJ		 3824 case IXGBE_ERR_EEPROM_VERSION:
3825 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3826 e_dev_warn("This device is a pre-production adapter/LOM. "
3827 "Please be aware there may be issuesassociated with "
3828 "your hardware. If you are experiencing problems "
3829 "please contact your Intel or hardware "
3830 "representative who provided you with this "
3831 "hardware.\n");
794caeb2 3832 break;
da4dd0f7 3833 default:
849c4542 3834 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3835 }
9a799d71 3836
7086400d
AD		 3837 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3838
9a799d71 3839 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3840 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3841 IXGBE_RAH_AV);
9a799d71
AK		 3842}
3843
9a799d71
AK		 3844/**
3845 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3846 * @rx_ring: ring to free buffers from
3847 **/
b6ec895e 3848static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3849{
b6ec895e 3850 struct device *dev = rx_ring->dev;
9a799d71 3851 unsigned long size;
b6ec895e 3852 u16 i;
9a799d71 3853
84418e3b
AD		 3854 /* ring already cleared, nothing to do */
3855 if (!rx_ring->rx_buffer_info)
3856 return;
9a799d71 3857
84418e3b 3858 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3859 for (i = 0; i < rx_ring->count; i++) {
3860 struct ixgbe_rx_buffer *rx_buffer_info;
3861
3862 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3863 if (rx_buffer_info->dma) {
b6ec895e 3864 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3865 rx_ring->rx_buf_len,
1b507730 3866 DMA_FROM_DEVICE);
9a799d71
AK		 3867 rx_buffer_info->dma = 0;
3868 }
3869 if (rx_buffer_info->skb) {
f8212f97 3870 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3871 rx_buffer_info->skb = NULL;
f8212f97
AD		 3872 do {
3873 struct sk_buff *this = skb;
e8171aaa 3874 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3875 dma_unmap_single(dev,
1b507730 3876 IXGBE_RSC_CB(this)->dma,
e8e9f696 3877 rx_ring->rx_buf_len,
1b507730 3878 DMA_FROM_DEVICE);
fd3686a8 3879 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3880 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3881 }
f8212f97
AD		 3882 skb = skb->prev;
3883 dev_kfree_skb(this);
3884 } while (skb);
9a799d71
AK		 3885 }
3886 if (!rx_buffer_info->page)
3887 continue;
4f57ca6e 3888 if (rx_buffer_info->page_dma) {
b6ec895e 3889 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3890 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3891 rx_buffer_info->page_dma = 0;
3892 }
9a799d71
AK		 3893 put_page(rx_buffer_info->page);
3894 rx_buffer_info->page = NULL;
762f4c57 3895 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3896 }
3897
3898 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3899 memset(rx_ring->rx_buffer_info, 0, size);
3900
3901 /* Zero out the descriptor ring */
3902 memset(rx_ring->desc, 0, rx_ring->size);
3903
3904 rx_ring->next_to_clean = 0;
3905 rx_ring->next_to_use = 0;
9a799d71
AK		 3906}
3907
3908/**
3909 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3910 * @tx_ring: ring to be cleaned
3911 **/
b6ec895e 3912static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3913{
3914 struct ixgbe_tx_buffer *tx_buffer_info;
3915 unsigned long size;
b6ec895e 3916 u16 i;
9a799d71 3917
84418e3b
AD		 3918 /* ring already cleared, nothing to do */
3919 if (!tx_ring->tx_buffer_info)
3920 return;
9a799d71 3921
84418e3b 3922 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3923 for (i = 0; i < tx_ring->count; i++) {
3924 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3925 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3926 }
3927
3928 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3929 memset(tx_ring->tx_buffer_info, 0, size);
3930
3931 /* Zero out the descriptor ring */
3932 memset(tx_ring->desc, 0, tx_ring->size);
3933
3934 tx_ring->next_to_use = 0;
3935 tx_ring->next_to_clean = 0;
9a799d71
AK		 3936}
3937
3938/**
021230d4 3939 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3940 * @adapter: board private structure
3941 **/
021230d4 3942static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3943{
3944 int i;
3945
021230d4 3946 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3947 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3948}
3949
3950/**
021230d4 3951 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3952 * @adapter: board private structure
3953 **/
021230d4 3954static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3955{
3956 int i;
3957
021230d4 3958 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3959 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3960}
3961
e4911d57
AD		 3962static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3963{
3964 struct hlist_node *node, *node2;
3965 struct ixgbe_fdir_filter *filter;
3966
3967 spin_lock(&adapter->fdir_perfect_lock);
3968
3969 hlist_for_each_entry_safe(filter, node, node2,
3970 &adapter->fdir_filter_list, fdir_node) {
3971 hlist_del(&filter->fdir_node);
3972 kfree(filter);
3973 }
3974 adapter->fdir_filter_count = 0;
3975
3976 spin_unlock(&adapter->fdir_perfect_lock);
3977}
3978
9a799d71
AK		 3979void ixgbe_down(struct ixgbe_adapter *adapter)
3980{
3981 struct net_device *netdev = adapter->netdev;
7f821875 3982 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3983 u32 rxctrl;
bf29ee6c 3984 int i;
9a799d71
AK		 3985
3986 /* signal that we are down to the interrupt handler */
3987 set_bit(__IXGBE_DOWN, &adapter->state);
3988
3989 /* disable receives */
7f821875
JB		 3990 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3991 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3992
2d39d576
YZ		 3993 /* disable all enabled rx queues */
3994 for (i = 0; i < adapter->num_rx_queues; i++)
3995 /* this call also flushes the previous write */
3996 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
3997
032b4325 3998 usleep_range(10000, 20000);
9a799d71 3999
7f821875
JB		 4000 netif_tx_stop_all_queues(netdev);
4001
7086400d 4002 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4003 netif_carrier_off(netdev);
4004 netif_tx_disable(netdev);
4005
4006 ixgbe_irq_disable(adapter);
4007
4008 ixgbe_napi_disable_all(adapter);
4009
d034acf1
AD		 4010 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4011 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4012 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4013
4014 del_timer_sync(&adapter->service_timer);
4015
34cecbbf 4016 if (adapter->num_vfs) {
8e34d1aa
AD		 4017 /* Clear EITR Select mapping */
4018 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4019
4020 /* Mark all the VFs as inactive */
4021 for (i = 0 ; i < adapter->num_vfs; i++)
4022 adapter->vfinfo[i].clear_to_send = 0;
34cecbbf 4023
34cecbbf
AD		 4024 /* ping all the active vfs to let them know we are going down */
4025 ixgbe_ping_all_vfs(adapter);
4026
4027 /* Disable all VFTE/VFRE TX/RX */
4028 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4029 }
4030
7f821875
JB		 4031 /* disable transmits in the hardware now that interrupts are off */
4032 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4033 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4034 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4035 }
34cecbbf
AD		 4036
4037 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4038 switch (hw->mac.type) {
4039 case ixgbe_mac_82599EB:
b93a2226 4040 case ixgbe_mac_X540:
88512539 4041 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4042 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4043 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4044 break;
4045 default:
4046 break;
4047 }
7f821875 4048
6f4a0e45
PL		 4049 if (!pci_channel_offline(adapter->pdev))
4050 ixgbe_reset(adapter);
c6ecf39a
DS		 4051
4052 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4053 if (hw->mac.ops.disable_tx_laser &&
4054 ((hw->phy.multispeed_fiber) ||
9f911707 4055 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4056 (hw->mac.type == ixgbe_mac_82599EB))))
4057 hw->mac.ops.disable_tx_laser(hw);
4058
9a799d71
AK		 4059 ixgbe_clean_all_tx_rings(adapter);
4060 ixgbe_clean_all_rx_rings(adapter);
4061
5dd2d332 4062#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4063 /* since we reset the hardware DCA settings were cleared */
e35ec126 4064 ixgbe_setup_dca(adapter);
96b0e0f6 4065#endif
9a799d71
AK		 4066}
4067
9a799d71 4068/**
021230d4
AV		 4069 * ixgbe_poll - NAPI Rx polling callback
4070 * @napi: structure for representing this polling device
4071 * @budget: how many packets driver is allowed to clean
4072 *
4073 * This function is used for legacy and MSI, NAPI mode
9a799d71 4074 **/
021230d4 4075static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4076{
9a1a69ad 4077 struct ixgbe_q_vector *q_vector =
e8e9f696 4078 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4079 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4080 struct ixgbe_ring *ring;
4081 int per_ring_budget;
4082 bool clean_complete = true;
9a799d71 4083
5dd2d332 4084#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4085 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4086 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4087#endif
4088
4ff7fb12
AD		 4089 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4090 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4091
4ff7fb12
AD		 4092 /* attempt to distribute budget to each queue fairly, but don't allow
4093 * the budget to go below 1 because we'll exit polling */
4094 if (q_vector->rx.count > 1)
4095 per_ring_budget = max(budget/q_vector->rx.count, 1);
4096 else
4097 per_ring_budget = budget;
d2c7ddd6 4098
4ff7fb12
AD		 4099 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4100 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4101 per_ring_budget);
4102
4103 /* If all work not completed, return budget and keep polling */
4104 if (!clean_complete)
4105 return budget;
4106
4107 /* all work done, exit the polling mode */
4108 napi_complete(napi);
4109 if (adapter->rx_itr_setting & 1)
4110 ixgbe_set_itr(q_vector);
4111 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4112 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4113
4114 return 0;
9a799d71
AK		 4115}
4116
4117/**
4118 * ixgbe_tx_timeout - Respond to a Tx Hang
4119 * @netdev: network interface device structure
4120 **/
4121static void ixgbe_tx_timeout(struct net_device *netdev)
4122{
4123 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4124
4125 /* Do the reset outside of interrupt context */
c83c6cbd 4126 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4127}
4128
4df10466
JB		 4129/**
4130 * ixgbe_set_rss_queues: Allocate queues for RSS
4131 * @adapter: board private structure to initialize
4132 *
4133 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4134 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4135 *
4136 **/
bc97114d
PWJ		 4137static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4138{
4139 bool ret = false;
0cefafad 4140 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4141
4142 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4143 f->mask = 0xF;
4144 adapter->num_rx_queues = f->indices;
4145 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4146 ret = true;
4147 } else {
bc97114d 4148 ret = false;
b9804972
JB		 4149 }
4150
bc97114d
PWJ		 4151 return ret;
4152}
4153
c4cf55e5
PWJ		 4154/**
4155 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4156 * @adapter: board private structure to initialize
4157 *
4158 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4159 * to the original CPU that initiated the Tx session. This runs in addition
4160 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4161 * Rx load across CPUs using RSS.
4162 *
4163 **/
e8e9f696 4164static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4165{
4166 bool ret = false;
4167 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4168
4169 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4170 f_fdir->mask = 0;
4171
4172 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4173 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4174 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4175 adapter->num_tx_queues = f_fdir->indices;
4176 adapter->num_rx_queues = f_fdir->indices;
4177 ret = true;
4178 } else {
4179 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4180 }
4181 return ret;
4182}
4183
0331a832
YZ		 4184#ifdef IXGBE_FCOE
4185/**
4186 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4187 * @adapter: board private structure to initialize
4188 *
4189 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4190 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4191 * rx queues out of the max number of rx queues, instead, it is used as the
4192 * index of the first rx queue used by FCoE.
4193 *
4194 **/
4195static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4196{
0331a832
YZ		 4197 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4198
e5b64635
JF		 4199 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4200 return false;
4201
e901acd6 4202 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4203
e901acd6
JF		 4204 adapter->num_rx_queues = 1;
4205 adapter->num_tx_queues = 1;
e5b64635 4206
e901acd6
JF		 4207 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4208 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4209 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4210 ixgbe_set_fdir_queues(adapter);
4211 else
4212 ixgbe_set_rss_queues(adapter);
e5b64635 4213 }
03ecf91a 4214
e901acd6
JF		 4215 /* adding FCoE rx rings to the end */
4216 f->mask = adapter->num_rx_queues;
4217 adapter->num_rx_queues += f->indices;
4218 adapter->num_tx_queues += f->indices;
0331a832 4219
e5b64635
JF		 4220 return true;
4221}
4222#endif /* IXGBE_FCOE */
4223
e901acd6
JF		 4224/* Artificial max queue cap per traffic class in DCB mode */
4225#define DCB_QUEUE_CAP 8
4226
e5b64635
JF		 4227#ifdef CONFIG_IXGBE_DCB
4228static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4229{
e901acd6
JF		 4230 int per_tc_q, q, i, offset = 0;
4231 struct net_device *dev = adapter->netdev;
4232 int tcs = netdev_get_num_tc(dev);
e5b64635 4233
e901acd6
JF		 4234 if (!tcs)
4235 return false;
e5b64635 4236
e901acd6
JF		 4237 /* Map queue offset and counts onto allocated tx queues */
4238 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4239 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4240
8b1c0b24 4241 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4242 netdev_set_tc_queue(dev, i, q, offset);
4243 offset += q;
0331a832
YZ		 4244 }
4245
e901acd6
JF		 4246 adapter->num_tx_queues = q * tcs;
4247 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4248
4249#ifdef IXGBE_FCOE
e901acd6
JF		 4250 /* FCoE enabled queues require special configuration indexed
4251 * by feature specific indices and mask. Here we map FCoE
4252 * indices onto the DCB queue pairs allowing FCoE to own
4253 * configuration later.
e5b64635 4254 */
e901acd6
JF		 4255 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4256 int tc;
4257 struct ixgbe_ring_feature *f =
4258 &adapter->ring_feature[RING_F_FCOE];
4259
4260 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4261 f->indices = dev->tc_to_txq[tc].count;
4262 f->mask = dev->tc_to_txq[tc].offset;
4263 }
e5b64635
JF		 4264#endif
4265
e901acd6 4266 return true;
0331a832 4267}
e5b64635 4268#endif
0331a832 4269
1cdd1ec8
GR		 4270/**
4271 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4272 * @adapter: board private structure to initialize
4273 *
4274 * IOV doesn't actually use anything, so just NAK the
4275 * request for now and let the other queue routines
4276 * figure out what to do.
4277 */
4278static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4279{
4280 return false;
4281}
4282
4df10466 4283/*
25985edc 4284 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4285 * @adapter: board private structure to initialize
4286 *
4287 * This is the top level queue allocation routine. The order here is very
4288 * important, starting with the "most" number of features turned on at once,
4289 * and ending with the smallest set of features. This way large combinations
4290 * can be allocated if they're turned on, and smaller combinations are the
4291 * fallthrough conditions.
4292 *
4293 **/
847f53ff 4294static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4295{
1cdd1ec8
GR		 4296 /* Start with base case */
4297 adapter->num_rx_queues = 1;
4298 adapter->num_tx_queues = 1;
4299 adapter->num_rx_pools = adapter->num_rx_queues;
4300 adapter->num_rx_queues_per_pool = 1;
4301
4302 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4303 goto done;
1cdd1ec8 4304
bc97114d
PWJ		 4305#ifdef CONFIG_IXGBE_DCB
4306 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4307 goto done;
bc97114d
PWJ		 4308
4309#endif
e5b64635
JF		 4310#ifdef IXGBE_FCOE
4311 if (ixgbe_set_fcoe_queues(adapter))
4312 goto done;
4313
4314#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4315 if (ixgbe_set_fdir_queues(adapter))
4316 goto done;
4317
bc97114d 4318 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4319 goto done;
4320
4321 /* fallback to base case */
4322 adapter->num_rx_queues = 1;
4323 adapter->num_tx_queues = 1;
4324
4325done:
847f53ff 4326 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4327 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4328 return netif_set_real_num_rx_queues(adapter->netdev,
4329 adapter->num_rx_queues);
b9804972
JB		 4330}
4331
021230d4 4332static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4333 int vectors)
021230d4
AV		 4334{
4335 int err, vector_threshold;
4336
4337 /* We'll want at least 3 (vector_threshold):
4338 * 1) TxQ[0] Cleanup
4339 * 2) RxQ[0] Cleanup
4340 * 3) Other (Link Status Change, etc.)
4341 * 4) TCP Timer (optional)
4342 */
4343 vector_threshold = MIN_MSIX_COUNT;
4344
4345 /* The more we get, the more we will assign to Tx/Rx Cleanup
4346 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4347 * Right now, we simply care about how many we'll get; we'll
4348 * set them up later while requesting irq's.
4349 */
4350 while (vectors >= vector_threshold) {
4351 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4352 vectors);
021230d4
AV		 4353 if (!err) /* Success in acquiring all requested vectors. */
4354 break;
4355 else if (err < 0)
4356 vectors = 0; /* Nasty failure, quit now */
4357 else /* err == number of vectors we should try again with */
4358 vectors = err;
4359 }
4360
4361 if (vectors < vector_threshold) {
4362 /* Can't allocate enough MSI-X interrupts? Oh well.
4363 * This just means we'll go with either a single MSI
4364 * vector or fall back to legacy interrupts.
4365 */
849c4542
ET		 4366 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4367 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4368 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4369 kfree(adapter->msix_entries);
4370 adapter->msix_entries = NULL;
021230d4
AV		 4371 } else {
4372 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4373 /*
4374 * Adjust for only the vectors we'll use, which is minimum
4375 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4376 * vectors we were allocated.
4377 */
4378 adapter->num_msix_vectors = min(vectors,
e8e9f696 4379 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4380 }
4381}
4382
021230d4 4383/**
bc97114d 4384 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4385 * @adapter: board private structure to initialize
4386 *
bc97114d
PWJ		 4387 * Cache the descriptor ring offsets for RSS to the assigned rings.
4388 *
021230d4 4389 **/
bc97114d 4390static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4391{
bc97114d 4392 int i;
bc97114d 4393
9d6b758f
AD		 4394 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4395 return false;
bc97114d 4396
9d6b758f
AD		 4397 for (i = 0; i < adapter->num_rx_queues; i++)
4398 adapter->rx_ring[i]->reg_idx = i;
4399 for (i = 0; i < adapter->num_tx_queues; i++)
4400 adapter->tx_ring[i]->reg_idx = i;
4401
4402 return true;
bc97114d
PWJ		 4403}
4404
4405#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4406
4407/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4408static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4409 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4410{
4411 struct net_device *dev = adapter->netdev;
4412 struct ixgbe_hw *hw = &adapter->hw;
4413 u8 num_tcs = netdev_get_num_tc(dev);
4414
4415 *tx = 0;
4416 *rx = 0;
4417
4418 switch (hw->mac.type) {
4419 case ixgbe_mac_82598EB:
aba70d5e
JF		 4420 *tx = tc << 2;
4421 *rx = tc << 3;
e5b64635
JF		 4422 break;
4423 case ixgbe_mac_82599EB:
4424 case ixgbe_mac_X540:
4fa2e0e1 4425 if (num_tcs > 4) {
e5b64635
JF		 4426 if (tc < 3) {
4427 *tx = tc << 5;
4428 *rx = tc << 4;
4429 } else if (tc < 5) {
4430 *tx = ((tc + 2) << 4);
4431 *rx = tc << 4;
4432 } else if (tc < num_tcs) {
4433 *tx = ((tc + 8) << 3);
4434 *rx = tc << 4;
4435 }
4fa2e0e1 4436 } else {
e5b64635
JF		 4437 *rx = tc << 5;
4438 switch (tc) {
4439 case 0:
4440 *tx = 0;
4441 break;
4442 case 1:
4443 *tx = 64;
4444 break;
4445 case 2:
4446 *tx = 96;
4447 break;
4448 case 3:
4449 *tx = 112;
4450 break;
4451 default:
4452 break;
4453 }
4454 }
4455 break;
4456 default:
4457 break;
4458 }
4459}
4460
bc97114d
PWJ		 4461/**
4462 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4463 * @adapter: board private structure to initialize
4464 *
4465 * Cache the descriptor ring offsets for DCB to the assigned rings.
4466 *
4467 **/
4468static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4469{
e5b64635
JF		 4470 struct net_device *dev = adapter->netdev;
4471 int i, j, k;
4472 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4473
8b1c0b24 4474 if (!num_tcs)
bd508178 4475 return false;
f92ef202 4476
e5b64635
JF		 4477 for (i = 0, k = 0; i < num_tcs; i++) {
4478 unsigned int tx_s, rx_s;
4479 u16 count = dev->tc_to_txq[i].count;
4480
4481 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4482 for (j = 0; j < count; j++, k++) {
4483 adapter->tx_ring[k]->reg_idx = tx_s + j;
4484 adapter->rx_ring[k]->reg_idx = rx_s + j;
4485 adapter->tx_ring[k]->dcb_tc = i;
4486 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4487 }
021230d4 4488 }
e5b64635
JF		 4489
4490 return true;
bc97114d
PWJ		 4491}
4492#endif
4493
c4cf55e5
PWJ		 4494/**
4495 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4496 * @adapter: board private structure to initialize
4497 *
4498 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4499 *
4500 **/
e8e9f696 4501static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4502{
4503 int i;
4504 bool ret = false;
4505
03ecf91a
AD		 4506 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4507 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4508 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4509 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4510 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4511 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4512 ret = true;
4513 }
4514
4515 return ret;
4516}
4517
0331a832
YZ		 4518#ifdef IXGBE_FCOE
4519/**
4520 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4521 * @adapter: board private structure to initialize
4522 *
4523 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4524 *
4525 */
4526static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4527{
0331a832 4528 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4529 int i;
4530 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4531
4532 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4533 return false;
0331a832 4534
bf29ee6c 4535 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4536 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4537 ixgbe_cache_ring_fdir(adapter);
4538 else
4539 ixgbe_cache_ring_rss(adapter);
8faa2a78 4540
bf29ee6c
AD		 4541 fcoe_rx_i = f->mask;
4542 fcoe_tx_i = f->mask;
0331a832 4543 }
bf29ee6c
AD		 4544 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4545 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4546 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4547 }
4548 return true;
0331a832
YZ		 4549}
4550
4551#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4552/**
4553 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4554 * @adapter: board private structure to initialize
4555 *
4556 * SR-IOV doesn't use any descriptor rings but changes the default if
4557 * no other mapping is used.
4558 *
4559 */
4560static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4561{
4a0b9ca0
PW		 4562 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4563 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4564 if (adapter->num_vfs)
4565 return true;
4566 else
4567 return false;
4568}
4569
bc97114d
PWJ		 4570/**
4571 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4572 * @adapter: board private structure to initialize
4573 *
4574 * Once we know the feature-set enabled for the device, we'll cache
4575 * the register offset the descriptor ring is assigned to.
4576 *
4577 * Note, the order the various feature calls is important. It must start with
4578 * the "most" features enabled at the same time, then trickle down to the
4579 * least amount of features turned on at once.
4580 **/
4581static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4582{
4583 /* start with default case */
4a0b9ca0
PW		 4584 adapter->rx_ring[0]->reg_idx = 0;
4585 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4586
1cdd1ec8
GR		 4587 if (ixgbe_cache_ring_sriov(adapter))
4588 return;
4589
e5b64635
JF		 4590#ifdef CONFIG_IXGBE_DCB
4591 if (ixgbe_cache_ring_dcb(adapter))
4592 return;
4593#endif
4594
0331a832
YZ		 4595#ifdef IXGBE_FCOE
4596 if (ixgbe_cache_ring_fcoe(adapter))
4597 return;
0331a832 4598#endif /* IXGBE_FCOE */
bc97114d 4599
c4cf55e5
PWJ		 4600 if (ixgbe_cache_ring_fdir(adapter))
4601 return;
4602
bc97114d
PWJ		 4603 if (ixgbe_cache_ring_rss(adapter))
4604 return;
021230d4
AV		 4605}
4606
9a799d71
AK		 4607/**
4608 * ixgbe_alloc_queues - Allocate memory for all rings
4609 * @adapter: board private structure to initialize
4610 *
4611 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4612 * number of queues at compile-time. The polling_netdev array is
4613 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4614 **/
2f90b865 4615static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4616{
e2ddeba9 4617 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4618
e2ddeba9
ED		 4619 if (nid < 0 || !node_online(nid))
4620 nid = first_online_node;
4621
4622 for (; tx < adapter->num_tx_queues; tx++) {
4623 struct ixgbe_ring *ring;
4624
4625 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4626 if (!ring)
e2ddeba9 4627 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4628 if (!ring)
e2ddeba9 4629 goto err_allocation;
4a0b9ca0 4630 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4631 ring->queue_index = tx;
4632 ring->numa_node = nid;
b6ec895e 4633 ring->dev = &adapter->pdev->dev;
fc77dc3c 4634 ring->netdev = adapter->netdev;
4a0b9ca0 4635
e2ddeba9 4636 adapter->tx_ring[tx] = ring;
021230d4 4637 }
b9804972 4638
e2ddeba9
ED		 4639 for (; rx < adapter->num_rx_queues; rx++) {
4640 struct ixgbe_ring *ring;
4a0b9ca0 4641
e2ddeba9 4642 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4643 if (!ring)
e2ddeba9 4644 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4645 if (!ring)
e2ddeba9
ED		 4646 goto err_allocation;
4647 ring->count = adapter->rx_ring_count;
4648 ring->queue_index = rx;
4649 ring->numa_node = nid;
b6ec895e 4650 ring->dev = &adapter->pdev->dev;
fc77dc3c 4651 ring->netdev = adapter->netdev;
4a0b9ca0 4652
e2ddeba9 4653 adapter->rx_ring[rx] = ring;
021230d4
AV		 4654 }
4655
4656 ixgbe_cache_ring_register(adapter);
4657
4658 return 0;
4659
e2ddeba9
ED		 4660err_allocation:
4661 while (tx)
4662 kfree(adapter->tx_ring[--tx]);
4663
4664 while (rx)
4665 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4666 return -ENOMEM;
4667}
4668
4669/**
4670 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4671 * @adapter: board private structure to initialize
4672 *
4673 * Attempt to configure the interrupts using the best available
4674 * capabilities of the hardware and the kernel.
4675 **/
feea6a57 4676static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4677{
8be0e467 4678 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4679 int err = 0;
4680 int vector, v_budget;
4681
4682 /*
4683 * It's easy to be greedy for MSI-X vectors, but it really
4684 * doesn't do us much good if we have a lot more vectors
4685 * than CPU's. So let's be conservative and only ask for
342bde1b 4686 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4687 */
4688 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4689 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4690
4691 /*
4692 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4693 * hw.mac->max_msix_vectors vectors. With features
4694 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4695 * descriptor queues supported by our device. Thus, we cap it off in
4696 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4697 */
8be0e467 4698 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4699
4700 /* A failure in MSI-X entry allocation isn't fatal, but it does
4701 * mean we disable MSI-X capabilities of the adapter. */
4702 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4703 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4704 if (adapter->msix_entries) {
4705 for (vector = 0; vector < v_budget; vector++)
4706 adapter->msix_entries[vector].entry = vector;
021230d4 4707
7a921c93 4708 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4709
7a921c93
AD		 4710 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4711 goto out;
4712 }
26d27844 4713
7a921c93
AD		 4714 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4715 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4716 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4717 e_err(probe,
03ecf91a 4718 "ATR is not supported while multiple "
45b9f509
AD		 4719 "queues are disabled. Disabling Flow Director\n");
4720 }
c4cf55e5 4721 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4722 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4723 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4724 ixgbe_disable_sriov(adapter);
4725
847f53ff
BH		 4726 err = ixgbe_set_num_queues(adapter);
4727 if (err)
4728 return err;
021230d4 4729
021230d4
AV		 4730 err = pci_enable_msi(adapter->pdev);
4731 if (!err) {
4732 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4733 } else {
849c4542
ET		 4734 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4735 "Unable to allocate MSI interrupt, "
4736 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4737 /* reset err */
4738 err = 0;
4739 }
4740
4741out:
021230d4
AV		 4742 return err;
4743}
4744
7a921c93
AD		 4745/**
4746 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4747 * @adapter: board private structure to initialize
4748 *
4749 * We allocate one q_vector per queue interrupt. If allocation fails we
4750 * return -ENOMEM.
4751 **/
4752static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4753{
4ff7fb12 4754 int v_idx, num_q_vectors;
7a921c93 4755 struct ixgbe_q_vector *q_vector;
7a921c93 4756
4ff7fb12 4757 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4758 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4759 else
7a921c93 4760 num_q_vectors = 1;
7a921c93 4761
4ff7fb12 4762 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4763 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4764 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4765 if (!q_vector)
4766 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4767 GFP_KERNEL);
7a921c93
AD		 4768 if (!q_vector)
4769 goto err_out;
4ff7fb12 4770
7a921c93 4771 q_vector->adapter = adapter;
4ff7fb12
AD		 4772 q_vector->v_idx = v_idx;
4773
207867f5
AD		 4774 /* Allocate the affinity_hint cpumask, configure the mask */
4775 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4776 goto err_out;
4777 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 4778 netif_napi_add(adapter->netdev, &q_vector->napi,
4779 ixgbe_poll, 64);
4780 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4781 }
4782
4783 return 0;
4784
4785err_out:
4ff7fb12
AD		 4786 while (v_idx) {
4787 v_idx--;
4788 q_vector = adapter->q_vector[v_idx];
7a921c93 4789 netif_napi_del(&q_vector->napi);
207867f5 4790 free_cpumask_var(q_vector->affinity_mask);
7a921c93 4791 kfree(q_vector);
4ff7fb12 4792 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 4793 }
4794 return -ENOMEM;
4795}
4796
4797/**
4798 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4799 * @adapter: board private structure to initialize
4800 *
4801 * This function frees the memory allocated to the q_vectors. In addition if
4802 * NAPI is enabled it will delete any references to the NAPI struct prior
4803 * to freeing the q_vector.
4804 **/
4805static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4806{
207867f5 4807 int v_idx, num_q_vectors;
7a921c93 4808
91281fd3 4809 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4810 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4811 else
7a921c93 4812 num_q_vectors = 1;
7a921c93 4813
207867f5
AD		 4814 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4815 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4816 adapter->q_vector[v_idx] = NULL;
91281fd3 4817 netif_napi_del(&q_vector->napi);
207867f5 4818 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 4819 kfree(q_vector);
4820 }
4821}
4822
7b25cdba 4823static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4824{
4825 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4826 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4827 pci_disable_msix(adapter->pdev);
4828 kfree(adapter->msix_entries);
4829 adapter->msix_entries = NULL;
4830 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4831 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4832 pci_disable_msi(adapter->pdev);
4833 }
021230d4
AV		 4834}
4835
4836/**
4837 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4838 * @adapter: board private structure to initialize
4839 *
4840 * We determine which interrupt scheme to use based on...
4841 * - Kernel support (MSI, MSI-X)
4842 * - which can be user-defined (via MODULE_PARAM)
4843 * - Hardware queue count (num_*_queues)
4844 * - defined by miscellaneous hardware support/features (RSS, etc.)
4845 **/
2f90b865 4846int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4847{
4848 int err;
4849
4850 /* Number of supported queues */
847f53ff
BH		 4851 err = ixgbe_set_num_queues(adapter);
4852 if (err)
4853 return err;
021230d4 4854
021230d4
AV		 4855 err = ixgbe_set_interrupt_capability(adapter);
4856 if (err) {
849c4542 4857 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4858 goto err_set_interrupt;
9a799d71
AK		 4859 }
4860
7a921c93
AD		 4861 err = ixgbe_alloc_q_vectors(adapter);
4862 if (err) {
849c4542 4863 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4864 goto err_alloc_q_vectors;
4865 }
4866
4867 err = ixgbe_alloc_queues(adapter);
4868 if (err) {
849c4542 4869 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4870 goto err_alloc_queues;
4871 }
4872
849c4542 4873 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4874 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4875 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4876
4877 set_bit(__IXGBE_DOWN, &adapter->state);
4878
9a799d71 4879 return 0;
021230d4 4880
7a921c93
AD		 4881err_alloc_queues:
4882 ixgbe_free_q_vectors(adapter);
4883err_alloc_q_vectors:
4884 ixgbe_reset_interrupt_capability(adapter);
021230d4 4885err_set_interrupt:
7a921c93
AD		 4886 return err;
4887}
4888
4889/**
4890 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4891 * @adapter: board private structure to clear interrupt scheme on
4892 *
4893 * We go through and clear interrupt specific resources and reset the structure
4894 * to pre-load conditions
4895 **/
4896void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4897{
4a0b9ca0
PW		 4898 int i;
4899
4900 for (i = 0; i < adapter->num_tx_queues; i++) {
4901 kfree(adapter->tx_ring[i]);
4902 adapter->tx_ring[i] = NULL;
4903 }
4904 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4905 struct ixgbe_ring *ring = adapter->rx_ring[i];
4906
4907 /* ixgbe_get_stats64() might access this ring, we must wait
4908 * a grace period before freeing it.
4909 */
bcec8b65 4910 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4911 adapter->rx_ring[i] = NULL;
4912 }
7a921c93 4913
b8eb3a10
DS		 4914 adapter->num_tx_queues = 0;
4915 adapter->num_rx_queues = 0;
4916
7a921c93
AD		 4917 ixgbe_free_q_vectors(adapter);
4918 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4919}
4920
4921/**
4922 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4923 * @adapter: board private structure to initialize
4924 *
4925 * ixgbe_sw_init initializes the Adapter private data structure.
4926 * Fields are initialized based on PCI device information and
4927 * OS network device settings (MTU size).
4928 **/
4929static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4930{
4931 struct ixgbe_hw *hw = &adapter->hw;
4932 struct pci_dev *pdev = adapter->pdev;
021230d4 4933 unsigned int rss;
7a6b6f51 4934#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4935 int j;
4936 struct tc_configuration *tc;
4937#endif
021230d4 4938
c44ade9e
JB		 4939 /* PCI config space info */
4940
4941 hw->vendor_id = pdev->vendor;
4942 hw->device_id = pdev->device;
4943 hw->revision_id = pdev->revision;
4944 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4945 hw->subsystem_device_id = pdev->subsystem_device;
4946
021230d4
AV		 4947 /* Set capability flags */
4948 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4949 adapter->ring_feature[RING_F_RSS].indices = rss;
4950 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4951 switch (hw->mac.type) {
4952 case ixgbe_mac_82598EB:
bf069c97
DS		 4953 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4954 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4955 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 4956 break;
b93a2226 4957 case ixgbe_mac_X540:
4f51bf70
JK		 4958 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4959 case ixgbe_mac_82599EB:
e8e26350 4960 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4961 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4962 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4963 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4964 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4965 /* Flow Director hash filters enabled */
4966 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4967 adapter->atr_sample_rate = 20;
c4cf55e5 4968 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4969 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4970 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4971#ifdef IXGBE_FCOE
0d551589
YZ		 4972 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4973 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4974 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4975#ifdef CONFIG_IXGBE_DCB
6ee16520 4976 /* Default traffic class to use for FCoE */
56075a98 4977 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4978#endif
eacd73f7 4979#endif /* IXGBE_FCOE */
bd508178
AD		 4980 break;
4981 default:
4982 break;
f8212f97 4983 }
2f90b865 4984
1fc5f038
AD		 4985 /* n-tuple support exists, always init our spinlock */
4986 spin_lock_init(&adapter->fdir_perfect_lock);
4987
7a6b6f51 4988#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4989 switch (hw->mac.type) {
4990 case ixgbe_mac_X540:
4991 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4992 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4993 break;
4994 default:
4995 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4996 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4997 break;
4998 }
4999
2f90b865
AD		 5000 /* Configure DCB traffic classes */
5001 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5002 tc = &adapter->dcb_cfg.tc_config[j];
5003 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5004 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5005 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5006 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5007 tc->dcb_pfc = pfc_disabled;
5008 }
4de2a022
JF		 5009
5010 /* Initialize default user to priority mapping, UPx->TC0 */
5011 tc = &adapter->dcb_cfg.tc_config[0];
5012 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5013 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5014
2f90b865
AD		 5015 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5016 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5017 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5018 adapter->dcb_set_bitmap = 0x00;
3032309b 5019 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5020 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5021 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5022
5023#endif
9a799d71
AK		 5024
5025 /* default flow control settings */
cd7664f6 5026 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5027 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5028#ifdef CONFIG_DCB
5029 adapter->last_lfc_mode = hw->fc.current_mode;
5030#endif
9da712d2 5031 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5032 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5033 hw->fc.send_xon = true;
71fd570b 5034 hw->fc.disable_fc_autoneg = false;
9a799d71 5035
30efa5a3 5036 /* enable itr by default in dynamic mode */
f7554a2b 5037 adapter->rx_itr_setting = 1;
f7554a2b 5038 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5039
5040 /* set defaults for eitr in MegaBytes */
5041 adapter->eitr_low = 10;
5042 adapter->eitr_high = 20;
5043
5044 /* set default ring sizes */
5045 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5046 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5047
bd198058 5048 /* set default work limits */
59224555 5049 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5050
9a799d71 5051 /* initialize eeprom parameters */
c44ade9e 5052 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5053 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5054 return -EIO;
5055 }
5056
021230d4 5057 /* enable rx csum by default */
9a799d71
AK		 5058 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5059
1a6c14a2
JB		 5060 /* get assigned NUMA node */
5061 adapter->node = dev_to_node(&pdev->dev);
5062
9a799d71
AK		 5063 set_bit(__IXGBE_DOWN, &adapter->state);
5064
5065 return 0;
5066}
5067
5068/**
5069 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5070 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5071 *
5072 * Return 0 on success, negative on failure
5073 **/
b6ec895e 5074int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5075{
b6ec895e 5076 struct device *dev = tx_ring->dev;
9a799d71
AK		 5077 int size;
5078
3a581073 5079 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5080 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5081 if (!tx_ring->tx_buffer_info)
89bf67f1 5082 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5083 if (!tx_ring->tx_buffer_info)
5084 goto err;
9a799d71
AK		 5085
5086 /* round up to nearest 4K */
12207e49 5087 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5088 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5089
b6ec895e 5090 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5091 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5092 if (!tx_ring->desc)
5093 goto err;
9a799d71 5094
3a581073
JB		 5095 tx_ring->next_to_use = 0;
5096 tx_ring->next_to_clean = 0;
9a799d71 5097 return 0;
e01c31a5
JB		 5098
5099err:
5100 vfree(tx_ring->tx_buffer_info);
5101 tx_ring->tx_buffer_info = NULL;
b6ec895e 5102 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5103 return -ENOMEM;
9a799d71
AK		 5104}
5105
69888674
AD		 5106/**
5107 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5108 * @adapter: board private structure
5109 *
5110 * If this function returns with an error, then it's possible one or
5111 * more of the rings is populated (while the rest are not). It is the
5112 * callers duty to clean those orphaned rings.
5113 *
5114 * Return 0 on success, negative on failure
5115 **/
5116static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5117{
5118 int i, err = 0;
5119
5120 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5121 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5122 if (!err)
5123 continue;
396e799c 5124 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5125 break;
5126 }
5127
5128 return err;
5129}
5130
9a799d71
AK		 5131/**
5132 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5133 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5134 *
5135 * Returns 0 on success, negative on failure
5136 **/
b6ec895e 5137int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5138{
b6ec895e 5139 struct device *dev = rx_ring->dev;
021230d4 5140 int size;
9a799d71 5141
3a581073 5142 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5143 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5144 if (!rx_ring->rx_buffer_info)
89bf67f1 5145 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5146 if (!rx_ring->rx_buffer_info)
5147 goto err;
9a799d71 5148
9a799d71 5149 /* Round up to nearest 4K */
3a581073
JB		 5150 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5151 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5152
b6ec895e 5153 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5154 &rx_ring->dma, GFP_KERNEL);
9a799d71 5155
b6ec895e
AD		 5156 if (!rx_ring->desc)
5157 goto err;
9a799d71 5158
3a581073
JB		 5159 rx_ring->next_to_clean = 0;
5160 rx_ring->next_to_use = 0;
9a799d71
AK		 5161
5162 return 0;
b6ec895e
AD		 5163err:
5164 vfree(rx_ring->rx_buffer_info);
5165 rx_ring->rx_buffer_info = NULL;
5166 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5167 return -ENOMEM;
9a799d71
AK		 5168}
5169
69888674
AD		 5170/**
5171 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5172 * @adapter: board private structure
5173 *
5174 * If this function returns with an error, then it's possible one or
5175 * more of the rings is populated (while the rest are not). It is the
5176 * callers duty to clean those orphaned rings.
5177 *
5178 * Return 0 on success, negative on failure
5179 **/
69888674
AD		 5180static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5181{
5182 int i, err = 0;
5183
5184 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5185 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5186 if (!err)
5187 continue;
396e799c 5188 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5189 break;
5190 }
5191
5192 return err;
5193}
5194
9a799d71
AK		 5195/**
5196 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5197 * @tx_ring: Tx descriptor ring for a specific queue
5198 *
5199 * Free all transmit software resources
5200 **/
b6ec895e 5201void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5202{
b6ec895e 5203 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5204
5205 vfree(tx_ring->tx_buffer_info);
5206 tx_ring->tx_buffer_info = NULL;
5207
b6ec895e
AD		 5208 /* if not set, then don't free */
5209 if (!tx_ring->desc)
5210 return;
5211
5212 dma_free_coherent(tx_ring->dev, tx_ring->size,
5213 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5214
5215 tx_ring->desc = NULL;
5216}
5217
5218/**
5219 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5220 * @adapter: board private structure
5221 *
5222 * Free all transmit software resources
5223 **/
5224static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5225{
5226 int i;
5227
5228 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5229 if (adapter->tx_ring[i]->desc)
b6ec895e 5230 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5231}
5232
5233/**
b4617240 5234 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5235 * @rx_ring: ring to clean the resources from
5236 *
5237 * Free all receive software resources
5238 **/
b6ec895e 5239void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5240{
b6ec895e 5241 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5242
5243 vfree(rx_ring->rx_buffer_info);
5244 rx_ring->rx_buffer_info = NULL;
5245
b6ec895e
AD		 5246 /* if not set, then don't free */
5247 if (!rx_ring->desc)
5248 return;
5249
5250 dma_free_coherent(rx_ring->dev, rx_ring->size,
5251 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5252
5253 rx_ring->desc = NULL;
5254}
5255
5256/**
5257 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5258 * @adapter: board private structure
5259 *
5260 * Free all receive software resources
5261 **/
5262static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5263{
5264 int i;
5265
5266 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5267 if (adapter->rx_ring[i]->desc)
b6ec895e 5268 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5269}
5270
9a799d71
AK		 5271/**
5272 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5273 * @netdev: network interface device structure
5274 * @new_mtu: new value for maximum frame size
5275 *
5276 * Returns 0 on success, negative on failure
5277 **/
5278static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5279{
5280 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5281 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5282 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5283
42c783c5 5284 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5285 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5286 hw->mac.type != ixgbe_mac_X540) {
5287 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5288 return -EINVAL;
5289 } else {
5290 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5291 return -EINVAL;
5292 }
9a799d71 5293
396e799c 5294 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5295 /* must set new MTU before calling down or up */
9a799d71
AK		 5296 netdev->mtu = new_mtu;
5297
d4f80882
AV		 5298 if (netif_running(netdev))
5299 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5300
5301 return 0;
5302}
5303
5304/**
5305 * ixgbe_open - Called when a network interface is made active
5306 * @netdev: network interface device structure
5307 *
5308 * Returns 0 on success, negative value on failure
5309 *
5310 * The open entry point is called when a network interface is made
5311 * active by the system (IFF_UP). At this point all resources needed
5312 * for transmit and receive operations are allocated, the interrupt
5313 * handler is registered with the OS, the watchdog timer is started,
5314 * and the stack is notified that the interface is ready.
5315 **/
5316static int ixgbe_open(struct net_device *netdev)
5317{
5318 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5319 int err;
4bebfaa5
AK		 5320
5321 /* disallow open during test */
5322 if (test_bit(__IXGBE_TESTING, &adapter->state))
5323 return -EBUSY;
9a799d71 5324
54386467
JB		 5325 netif_carrier_off(netdev);
5326
9a799d71
AK		 5327 /* allocate transmit descriptors */
5328 err = ixgbe_setup_all_tx_resources(adapter);
5329 if (err)
5330 goto err_setup_tx;
5331
9a799d71
AK		 5332 /* allocate receive descriptors */
5333 err = ixgbe_setup_all_rx_resources(adapter);
5334 if (err)
5335 goto err_setup_rx;
5336
5337 ixgbe_configure(adapter);
5338
021230d4 5339 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5340 if (err)
5341 goto err_req_irq;
5342
c7ccde0f 5343 ixgbe_up_complete(adapter);
9a799d71
AK		 5344
5345 return 0;
5346
9a799d71 5347err_req_irq:
9a799d71 5348err_setup_rx:
a20a1199 5349 ixgbe_free_all_rx_resources(adapter);
9a799d71 5350err_setup_tx:
a20a1199 5351 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5352 ixgbe_reset(adapter);
5353
5354 return err;
5355}
5356
5357/**
5358 * ixgbe_close - Disables a network interface
5359 * @netdev: network interface device structure
5360 *
5361 * Returns 0, this is not allowed to fail
5362 *
5363 * The close entry point is called when an interface is de-activated
5364 * by the OS. The hardware is still under the drivers control, but
5365 * needs to be disabled. A global MAC reset is issued to stop the
5366 * hardware, and all transmit and receive resources are freed.
5367 **/
5368static int ixgbe_close(struct net_device *netdev)
5369{
5370 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5371
5372 ixgbe_down(adapter);
5373 ixgbe_free_irq(adapter);
5374
e4911d57
AD		 5375 ixgbe_fdir_filter_exit(adapter);
5376
9a799d71
AK		 5377 ixgbe_free_all_tx_resources(adapter);
5378 ixgbe_free_all_rx_resources(adapter);
5379
5eba3699 5380 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5381
5382 return 0;
5383}
5384
b3c8b4ba
AD		 5385#ifdef CONFIG_PM
5386static int ixgbe_resume(struct pci_dev *pdev)
5387{
c60fbb00
AD		 5388 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5389 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5390 u32 err;
5391
5392 pci_set_power_state(pdev, PCI_D0);
5393 pci_restore_state(pdev);
656ab817
DS		 5394 /*
5395 * pci_restore_state clears dev->state_saved so call
5396 * pci_save_state to restore it.
5397 */
5398 pci_save_state(pdev);
9ce77666 5399
5400 err = pci_enable_device_mem(pdev);
b3c8b4ba 5401 if (err) {
849c4542 5402 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5403 return err;
5404 }
5405 pci_set_master(pdev);
5406
dd4d8ca6 5407 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5408
5409 err = ixgbe_init_interrupt_scheme(adapter);
5410 if (err) {
849c4542 5411 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5412 return err;
5413 }
5414
b3c8b4ba
AD		 5415 ixgbe_reset(adapter);
5416
495dce12
WJP		 5417 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5418
b3c8b4ba 5419 if (netif_running(netdev)) {
c60fbb00 5420 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5421 if (err)
5422 return err;
5423 }
5424
5425 netif_device_attach(netdev);
5426
5427 return 0;
5428}
b3c8b4ba 5429#endif /* CONFIG_PM */
9d8d05ae
RW		 5430
5431static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5432{
c60fbb00
AD		 5433 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5434 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5435 struct ixgbe_hw *hw = &adapter->hw;
5436 u32 ctrl, fctrl;
5437 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5438#ifdef CONFIG_PM
5439 int retval = 0;
5440#endif
5441
5442 netif_device_detach(netdev);
5443
5444 if (netif_running(netdev)) {
5445 ixgbe_down(adapter);
5446 ixgbe_free_irq(adapter);
5447 ixgbe_free_all_tx_resources(adapter);
5448 ixgbe_free_all_rx_resources(adapter);
5449 }
b3c8b4ba 5450
5f5ae6fc 5451 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5452#ifdef CONFIG_DCB
5453 kfree(adapter->ixgbe_ieee_pfc);
5454 kfree(adapter->ixgbe_ieee_ets);
5455#endif
5f5ae6fc 5456
b3c8b4ba
AD		 5457#ifdef CONFIG_PM
5458 retval = pci_save_state(pdev);
5459 if (retval)
5460 return retval;
4df10466 5461
b3c8b4ba 5462#endif
e8e26350
PW		 5463 if (wufc) {
5464 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5465
e8e26350
PW		 5466 /* turn on all-multi mode if wake on multicast is enabled */
5467 if (wufc & IXGBE_WUFC_MC) {
5468 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5469 fctrl |= IXGBE_FCTRL_MPE;
5470 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5471 }
5472
5473 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5474 ctrl |= IXGBE_CTRL_GIO_DIS;
5475 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5476
5477 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5478 } else {
5479 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5480 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5481 }
5482
bd508178
AD		 5483 switch (hw->mac.type) {
5484 case ixgbe_mac_82598EB:
dd4d8ca6 5485 pci_wake_from_d3(pdev, false);
bd508178
AD		 5486 break;
5487 case ixgbe_mac_82599EB:
b93a2226 5488 case ixgbe_mac_X540:
bd508178
AD		 5489 pci_wake_from_d3(pdev, !!wufc);
5490 break;
5491 default:
5492 break;
5493 }
b3c8b4ba 5494
9d8d05ae
RW		 5495 *enable_wake = !!wufc;
5496
b3c8b4ba
AD		 5497 ixgbe_release_hw_control(adapter);
5498
5499 pci_disable_device(pdev);
5500
9d8d05ae
RW		 5501 return 0;
5502}
5503
5504#ifdef CONFIG_PM
5505static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5506{
5507 int retval;
5508 bool wake;
5509
5510 retval = __ixgbe_shutdown(pdev, &wake);
5511 if (retval)
5512 return retval;
5513
5514 if (wake) {
5515 pci_prepare_to_sleep(pdev);
5516 } else {
5517 pci_wake_from_d3(pdev, false);
5518 pci_set_power_state(pdev, PCI_D3hot);
5519 }
b3c8b4ba
AD		 5520
5521 return 0;
5522}
9d8d05ae 5523#endif /* CONFIG_PM */
b3c8b4ba
AD		 5524
5525static void ixgbe_shutdown(struct pci_dev *pdev)
5526{
9d8d05ae
RW		 5527 bool wake;
5528
5529 __ixgbe_shutdown(pdev, &wake);
5530
5531 if (system_state == SYSTEM_POWER_OFF) {
5532 pci_wake_from_d3(pdev, wake);
5533 pci_set_power_state(pdev, PCI_D3hot);
5534 }
b3c8b4ba
AD		 5535}
5536
9a799d71
AK		 5537/**
5538 * ixgbe_update_stats - Update the board statistics counters.
5539 * @adapter: board private structure
5540 **/
5541void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5542{
2d86f139 5543 struct net_device *netdev = adapter->netdev;
9a799d71 5544 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5545 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5546 u64 total_mpc = 0;
5547 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5548 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5549 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5550 u64 bytes = 0, packets = 0;
7b859ebc
AH		 5551#ifdef IXGBE_FCOE
5552 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5553 unsigned int cpu;
5554 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5555#endif /* IXGBE_FCOE */
9a799d71 5556
d08935c2
DS		 5557 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5558 test_bit(__IXGBE_RESETTING, &adapter->state))
5559 return;
5560
94b982b2 5561 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5562 u64 rsc_count = 0;
94b982b2 5563 u64 rsc_flush = 0;
d51019a4
PW		 5564 for (i = 0; i < 16; i++)
5565 adapter->hw_rx_no_dma_resources +=
7ca647bd 5566 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5567 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5568 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5569 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5570 }
5571 adapter->rsc_total_count = rsc_count;
5572 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5573 }
5574
5b7da515
AD		 5575 for (i = 0; i < adapter->num_rx_queues; i++) {
5576 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5577 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5578 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5579 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5580 bytes += rx_ring->stats.bytes;
5581 packets += rx_ring->stats.packets;
5582 }
5583 adapter->non_eop_descs = non_eop_descs;
5584 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5585 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5586 netdev->stats.rx_bytes = bytes;
5587 netdev->stats.rx_packets = packets;
5588
5589 bytes = 0;
5590 packets = 0;
7ca3bc58 5591 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5592 for (i = 0; i < adapter->num_tx_queues; i++) {
5593 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5594 restart_queue += tx_ring->tx_stats.restart_queue;
5595 tx_busy += tx_ring->tx_stats.tx_busy;
5596 bytes += tx_ring->stats.bytes;
5597 packets += tx_ring->stats.packets;
5598 }
eb985f09 5599 adapter->restart_queue = restart_queue;
5b7da515
AD		 5600 adapter->tx_busy = tx_busy;
5601 netdev->stats.tx_bytes = bytes;
5602 netdev->stats.tx_packets = packets;
7ca3bc58 5603
7ca647bd 5604 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5605
5606 /* 8 register reads */
6f11eef7
AV		 5607 for (i = 0; i < 8; i++) {
5608 /* for packet buffers not used, the register should read 0 */
5609 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5610 missed_rx += mpc;
7ca647bd
JP		 5611 hwstats->mpc[i] += mpc;
5612 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5613 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5614 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5615 switch (hw->mac.type) {
5616 case ixgbe_mac_82598EB:
1a70db4b
ET		 5617 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5618 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5619 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5620 hwstats->pxonrxc[i] +=
5621 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5622 break;
5623 case ixgbe_mac_82599EB:
b93a2226 5624 case ixgbe_mac_X540:
bd508178
AD		 5625 hwstats->pxonrxc[i] +=
5626 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5627 break;
5628 default:
5629 break;
e8e26350 5630 }
6f11eef7 5631 }
1a70db4b
ET		 5632
5633 /*16 register reads */
5634 for (i = 0; i < 16; i++) {
5635 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5636 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5637 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5638 (hw->mac.type == ixgbe_mac_X540)) {
5639 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5640 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5641 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5642 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5643 }
5644 }
5645
7ca647bd 5646 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5647 /* work around hardware counting issue */
7ca647bd 5648 hwstats->gprc -= missed_rx;
6f11eef7 5649
c84d324c
JF		 5650 ixgbe_update_xoff_received(adapter);
5651
6f11eef7 5652 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5653 switch (hw->mac.type) {
5654 case ixgbe_mac_82598EB:
5655 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5656 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5657 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5658 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5659 break;
b93a2226 5660 case ixgbe_mac_X540:
58f6bcf9
ET		 5661 /* OS2BMC stats are X540 only*/
5662 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5663 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5664 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5665 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5666 case ixgbe_mac_82599EB:
7ca647bd 5667 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5668 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5669 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5670 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5671 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5672 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5673 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5674 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5675 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5676#ifdef IXGBE_FCOE
7ca647bd
JP		 5677 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5678 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5679 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5680 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5681 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5682 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5683 /* Add up per cpu counters for total ddp aloc fail */
5684 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5685 for_each_possible_cpu(cpu) {
5686 fcoe_noddp_counts_sum +=
5687 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5688 fcoe_noddp_ext_buff_counts_sum +=
5689 *per_cpu_ptr(fcoe->
5690 pcpu_noddp_ext_buff, cpu);
5691 }
5692 }
5693 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5694 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5695#endif /* IXGBE_FCOE */
bd508178
AD		 5696 break;
5697 default:
5698 break;
e8e26350 5699 }
9a799d71 5700 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5701 hwstats->bprc += bprc;
5702 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5703 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5704 hwstats->mprc -= bprc;
5705 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5706 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5707 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5708 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5709 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5710 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5711 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5712 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5713 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5714 hwstats->lxontxc += lxon;
6f11eef7 5715 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5716 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5717 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5718 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5719 /*
5720 * 82598 errata - tx of flow control packets is included in tx counters
5721 */
5722 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5723 hwstats->gptc -= xon_off_tot;
5724 hwstats->mptc -= xon_off_tot;
5725 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5726 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5727 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5728 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5729 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5730 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5731 hwstats->ptc64 -= xon_off_tot;
5732 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5733 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5734 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5735 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5736 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5737 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5738
5739 /* Fill out the OS statistics structure */
7ca647bd 5740 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5741
5742 /* Rx Errors */
7ca647bd 5743 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5744 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5745 netdev->stats.rx_length_errors = hwstats->rlec;
5746 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5747 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5748}
5749
5750/**
d034acf1
AD		 5751 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5752 * @adapter - pointer to the device adapter structure
9a799d71 5753 **/
d034acf1 5754static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5755{
cf8280ee 5756 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5757 int i;
cf8280ee 5758
d034acf1
AD		 5759 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5760 return;
5761
5762 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5763
d034acf1 5764 /* if interface is down do nothing */
fe49f04a 5765 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5766 return;
5767
5768 /* do nothing if we are not using signature filters */
5769 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5770 return;
5771
5772 adapter->fdir_overflow++;
5773
93c52dd0
AD		 5774 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5775 for (i = 0; i < adapter->num_tx_queues; i++)
5776 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5777 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5778 /* re-enable flow director interrupts */
5779 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5780 } else {
5781 e_err(probe, "failed to finish FDIR re-initialization, "
5782 "ignored adding FDIR ATR filters\n");
5783 }
93c52dd0
AD		 5784}
5785
5786/**
5787 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5788 * @adapter - pointer to the device adapter structure
5789 *
5790 * This function serves two purposes. First it strobes the interrupt lines
5791 * in order to make certain interrupts are occuring. Secondly it sets the
5792 * bits needed to check for TX hangs. As a result we should immediately
5793 * determine if a hang has occured.
5794 */
5795static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5796{
cf8280ee 5797 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5798 u64 eics = 0;
5799 int i;
cf8280ee 5800
93c52dd0
AD		 5801 /* If we're down or resetting, just bail */
5802 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5803 test_bit(__IXGBE_RESETTING, &adapter->state))
5804 return;
22d5a71b 5805
93c52dd0
AD		 5806 /* Force detection of hung controller */
5807 if (netif_carrier_ok(adapter->netdev)) {
5808 for (i = 0; i < adapter->num_tx_queues; i++)
5809 set_check_for_tx_hang(adapter->tx_ring[i]);
5810 }
22d5a71b 5811
fe49f04a
AD		 5812 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5813 /*
5814 * for legacy and MSI interrupts don't set any bits
5815 * that are enabled for EIAM, because this operation
5816 * would set *both* EIMS and EICS for any bit in EIAM
5817 */
5818 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5819 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5820 } else {
5821 /* get one bit for every active tx/rx interrupt vector */
5822 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5823 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5824 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5825 eics |= ((u64)1 << i);
5826 }
cf8280ee 5827 }
9a799d71 5828
93c52dd0 5829 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5830 ixgbe_irq_rearm_queues(adapter, eics);
5831
cf8280ee
JB		 5832}
5833
e8e26350 5834/**
93c52dd0
AD		 5835 * ixgbe_watchdog_update_link - update the link status
5836 * @adapter - pointer to the device adapter structure
5837 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5838 **/
93c52dd0 5839static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5840{
e8e26350 5841 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5842 u32 link_speed = adapter->link_speed;
5843 bool link_up = adapter->link_up;
c4cf55e5 5844 int i;
e8e26350 5845
93c52dd0
AD		 5846 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5847 return;
5848
5849 if (hw->mac.ops.check_link) {
5850 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5851 } else {
93c52dd0
AD		 5852 /* always assume link is up, if no check link function */
5853 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5854 link_up = true;
c4cf55e5 5855 }
93c52dd0
AD		 5856 if (link_up) {
5857 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5858 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5859 hw->mac.ops.fc_enable(hw, i);
5860 } else {
5861 hw->mac.ops.fc_enable(hw, 0);
5862 }
5863 }
5864
5865 if (link_up ||
5866 time_after(jiffies, (adapter->link_check_timeout +
5867 IXGBE_TRY_LINK_TIMEOUT))) {
5868 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5869 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5870 IXGBE_WRITE_FLUSH(hw);
5871 }
5872
5873 adapter->link_up = link_up;
5874 adapter->link_speed = link_speed;
e8e26350
PW		 5875}
5876
5877/**
93c52dd0
AD		 5878 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5879 * print link up message
5880 * @adapter - pointer to the device adapter structure
e8e26350 5881 **/
93c52dd0 5882static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5883{
93c52dd0 5884 struct net_device *netdev = adapter->netdev;
e8e26350 5885 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5886 u32 link_speed = adapter->link_speed;
5887 bool flow_rx, flow_tx;
e8e26350 5888
93c52dd0
AD		 5889 /* only continue if link was previously down */
5890 if (netif_carrier_ok(netdev))
a985b6c3 5891 return;
63d6e1d8 5892
93c52dd0 5893 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5894
93c52dd0
AD		 5895 switch (hw->mac.type) {
5896 case ixgbe_mac_82598EB: {
5897 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5898 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5899 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5900 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5901 }
5902 break;
5903 case ixgbe_mac_X540:
5904 case ixgbe_mac_82599EB: {
5905 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5906 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5907 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5908 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5909 }
5910 break;
5911 default:
5912 flow_tx = false;
5913 flow_rx = false;
5914 break;
e8e26350 5915 }
93c52dd0
AD		 5916 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5917 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5918 "10 Gbps" :
5919 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5920 "1 Gbps" :
5921 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5922 "100 Mbps" :
5923 "unknown speed"))),
5924 ((flow_rx && flow_tx) ? "RX/TX" :
5925 (flow_rx ? "RX" :
5926 (flow_tx ? "TX" : "None"))));
e8e26350 5927
93c52dd0 5928 netif_carrier_on(netdev);
93c52dd0 5929 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5930}
5931
c4cf55e5 5932/**
93c52dd0
AD		 5933 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5934 * print link down message
5935 * @adapter - pointer to the adapter structure
c4cf55e5 5936 **/
93c52dd0 5937static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5938{
cf8280ee 5939 struct net_device *netdev = adapter->netdev;
c4cf55e5 5940 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5941
93c52dd0
AD		 5942 adapter->link_up = false;
5943 adapter->link_speed = 0;
cf8280ee 5944
93c52dd0
AD		 5945 /* only continue if link was up previously */
5946 if (!netif_carrier_ok(netdev))
5947 return;
264857b8 5948
93c52dd0
AD		 5949 /* poll for SFP+ cable when link is down */
5950 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5951 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5952
93c52dd0
AD		 5953 e_info(drv, "NIC Link is Down\n");
5954 netif_carrier_off(netdev);
5955}
e8e26350 5956
93c52dd0
AD		 5957/**
5958 * ixgbe_watchdog_flush_tx - flush queues on link down
5959 * @adapter - pointer to the device adapter structure
5960 **/
5961static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5962{
c4cf55e5 5963 int i;
93c52dd0 5964 int some_tx_pending = 0;
c4cf55e5 5965
93c52dd0 5966 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5967 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5968 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5969 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5970 some_tx_pending = 1;
5971 break;
5972 }
5973 }
5974
5975 if (some_tx_pending) {
5976 /* We've lost link, so the controller stops DMA,
5977 * but we've got queued Tx work that's never going
5978 * to get done, so reset controller to flush Tx.
5979 * (Do the reset outside of interrupt context).
5980 */
c83c6cbd 5981 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5982 }
c4cf55e5 5983 }
c4cf55e5
PWJ		 5984}
5985
a985b6c3
GR		 5986static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5987{
5988 u32 ssvpc;
5989
5990 /* Do not perform spoof check for 82598 */
5991 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5992 return;
5993
5994 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5995
5996 /*
5997 * ssvpc register is cleared on read, if zero then no
5998 * spoofed packets in the last interval.
5999 */
6000 if (!ssvpc)
6001 return;
6002
6003 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6004}
6005
93c52dd0
AD		 6006/**
6007 * ixgbe_watchdog_subtask - check and bring link up
6008 * @adapter - pointer to the device adapter structure
6009 **/
6010static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6011{
6012 /* if interface is down do nothing */
7edebf9a
ET		 6013 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6014 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6015 return;
6016
6017 ixgbe_watchdog_update_link(adapter);
6018
6019 if (adapter->link_up)
6020 ixgbe_watchdog_link_is_up(adapter);
6021 else
6022 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6023
a985b6c3 6024 ixgbe_spoof_check(adapter);
9a799d71 6025 ixgbe_update_stats(adapter);
93c52dd0
AD		 6026
6027 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6028}
10eec955 6029
cf8280ee 6030/**
7086400d
AD		 6031 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6032 * @adapter - the ixgbe adapter structure
cf8280ee 6033 **/
7086400d 6034static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6035{
cf8280ee 6036 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6037 s32 err;
cf8280ee 6038
7086400d
AD		 6039 /* not searching for SFP so there is nothing to do here */
6040 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6041 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6042 return;
10eec955 6043
7086400d
AD		 6044 /* someone else is in init, wait until next service event */
6045 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6046 return;
cf8280ee 6047
7086400d
AD		 6048 err = hw->phy.ops.identify_sfp(hw);
6049 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6050 goto sfp_out;
264857b8 6051
7086400d
AD		 6052 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6053 /* If no cable is present, then we need to reset
6054 * the next time we find a good cable. */
6055 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6056 }
9a799d71 6057
7086400d
AD		 6058 /* exit on error */
6059 if (err)
6060 goto sfp_out;
e8e26350 6061
7086400d
AD		 6062 /* exit if reset not needed */
6063 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6064 goto sfp_out;
9a799d71 6065
7086400d 6066 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6067
7086400d
AD		 6068 /*
6069 * A module may be identified correctly, but the EEPROM may not have
6070 * support for that module. setup_sfp() will fail in that case, so
6071 * we should not allow that module to load.
6072 */
6073 if (hw->mac.type == ixgbe_mac_82598EB)
6074 err = hw->phy.ops.reset(hw);
6075 else
6076 err = hw->mac.ops.setup_sfp(hw);
6077
6078 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6079 goto sfp_out;
6080
6081 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6082 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6083
6084sfp_out:
6085 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6086
6087 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6088 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6089 e_dev_err("failed to initialize because an unsupported "
6090 "SFP+ module type was detected.\n");
6091 e_dev_err("Reload the driver after installing a "
6092 "supported module.\n");
6093 unregister_netdev(adapter->netdev);
bc59fcda 6094 }
7086400d 6095}
bc59fcda 6096
7086400d
AD		 6097/**
6098 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6099 * @adapter - the ixgbe adapter structure
6100 **/
6101static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6102{
6103 struct ixgbe_hw *hw = &adapter->hw;
6104 u32 autoneg;
6105 bool negotiation;
6106
6107 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6108 return;
6109
6110 /* someone else is in init, wait until next service event */
6111 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6112 return;
6113
6114 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6115
6116 autoneg = hw->phy.autoneg_advertised;
6117 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6118 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6119 if (hw->mac.ops.setup_link)
6120 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6121
6122 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6123 adapter->link_check_timeout = jiffies;
6124 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6125}
6126
83c61fa9
GR		 6127#ifdef CONFIG_PCI_IOV
6128static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6129{
6130 int vf;
6131 struct ixgbe_hw *hw = &adapter->hw;
6132 struct net_device *netdev = adapter->netdev;
6133 u32 gpc;
6134 u32 ciaa, ciad;
6135
6136 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6137 if (gpc) /* If incrementing then no need for the check below */
6138 return;
6139 /*
6140 * Check to see if a bad DMA write target from an errant or
6141 * malicious VF has caused a PCIe error. If so then we can
6142 * issue a VFLR to the offending VF(s) and then resume without
6143 * requesting a full slot reset.
6144 */
6145
6146 for (vf = 0; vf < adapter->num_vfs; vf++) {
6147 ciaa = (vf << 16) | 0x80000000;
6148 /* 32 bit read so align, we really want status at offset 6 */
6149 ciaa |= PCI_COMMAND;
6150 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6151 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6152 ciaa &= 0x7FFFFFFF;
6153 /* disable debug mode asap after reading data */
6154 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6155 /* Get the upper 16 bits which will be the PCI status reg */
6156 ciad >>= 16;
6157 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6158 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6159 /* Issue VFLR */
6160 ciaa = (vf << 16) | 0x80000000;
6161 ciaa |= 0xA8;
6162 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6163 ciad = 0x00008000; /* VFLR */
6164 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6165 ciaa &= 0x7FFFFFFF;
6166 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6167 }
6168 }
6169}
6170
6171#endif
7086400d
AD		 6172/**
6173 * ixgbe_service_timer - Timer Call-back
6174 * @data: pointer to adapter cast into an unsigned long
6175 **/
6176static void ixgbe_service_timer(unsigned long data)
6177{
6178 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6179 unsigned long next_event_offset;
83c61fa9 6180 bool ready = true;
7086400d 6181
83c61fa9
GR		 6182#ifdef CONFIG_PCI_IOV
6183 ready = false;
6184
6185 /*
6186 * don't bother with SR-IOV VF DMA hang check if there are
6187 * no VFs or the link is down
6188 */
6189 if (!adapter->num_vfs ||
6190 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6191 ready = true;
6192 goto normal_timer_service;
6193 }
6194
6195 /* If we have VFs allocated then we must check for DMA hangs */
6196 ixgbe_check_for_bad_vf(adapter);
6197 next_event_offset = HZ / 50;
6198 adapter->timer_event_accumulator++;
6199
6200 if (adapter->timer_event_accumulator >= 100) {
6201 ready = true;
6202 adapter->timer_event_accumulator = 0;
6203 }
6204
6205 goto schedule_event;
6206
6207normal_timer_service:
6208#endif
7086400d
AD		 6209 /* poll faster when waiting for link */
6210 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6211 next_event_offset = HZ / 10;
6212 else
6213 next_event_offset = HZ * 2;
6214
83c61fa9
GR		 6215#ifdef CONFIG_PCI_IOV
6216schedule_event:
6217#endif
7086400d
AD		 6218 /* Reset the timer */
6219 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6220
83c61fa9
GR		 6221 if (ready)
6222 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6223}
6224
c83c6cbd
AD		 6225static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6226{
6227 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6228 return;
6229
6230 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6231
6232 /* If we're already down or resetting, just bail */
6233 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6234 test_bit(__IXGBE_RESETTING, &adapter->state))
6235 return;
6236
6237 ixgbe_dump(adapter);
6238 netdev_err(adapter->netdev, "Reset adapter\n");
6239 adapter->tx_timeout_count++;
6240
6241 ixgbe_reinit_locked(adapter);
6242}
6243
7086400d
AD		 6244/**
6245 * ixgbe_service_task - manages and runs subtasks
6246 * @work: pointer to work_struct containing our data
6247 **/
6248static void ixgbe_service_task(struct work_struct *work)
6249{
6250 struct ixgbe_adapter *adapter = container_of(work,
6251 struct ixgbe_adapter,
6252 service_task);
6253
c83c6cbd 6254 ixgbe_reset_subtask(adapter);
7086400d
AD		 6255 ixgbe_sfp_detection_subtask(adapter);
6256 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6257 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6258 ixgbe_watchdog_subtask(adapter);
d034acf1 6259 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6260 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6261
6262 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6263}
6264
897ab156
AD		 6265void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6266 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6267{
6268 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6269 u16 i = tx_ring->next_to_use;
9a799d71 6270
897ab156 6271 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6272
897ab156
AD		 6273 i++;
6274 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6275
897ab156
AD		 6276 /* set bits to identify this as an advanced context descriptor */
6277 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6278
897ab156
AD		 6279 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6280 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6281 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6282 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6283}
9a799d71 6284
897ab156
AD		 6285static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6286 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6287{
6288 int err;
6289 u32 vlan_macip_lens, type_tucmd;
6290 u32 mss_l4len_idx, l4len;
9a799d71 6291
897ab156
AD		 6292 if (!skb_is_gso(skb))
6293 return 0;
9a799d71 6294
897ab156
AD		 6295 if (skb_header_cloned(skb)) {
6296 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6297 if (err)
6298 return err;
9a799d71 6299 }
9a799d71 6300
897ab156
AD		 6301 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6302 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6303
6304 if (protocol == __constant_htons(ETH_P_IP)) {
6305 struct iphdr *iph = ip_hdr(skb);
6306 iph->tot_len = 0;
6307 iph->check = 0;
6308 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6309 iph->daddr, 0,
6310 IPPROTO_TCP,
6311 0);
6312 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6313 } else if (skb_is_gso_v6(skb)) {
6314 ipv6_hdr(skb)->payload_len = 0;
6315 tcp_hdr(skb)->check =
6316 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6317 &ipv6_hdr(skb)->daddr,
6318 0, IPPROTO_TCP, 0);
6319 }
6320
6321 l4len = tcp_hdrlen(skb);
6322 *hdr_len = skb_transport_offset(skb) + l4len;
6323
6324 /* mss_l4len_id: use 1 as index for TSO */
6325 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6326 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6327 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6328
6329 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6330 vlan_macip_lens = skb_network_header_len(skb);
6331 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6332 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6333
6334 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6335 mss_l4len_idx);
6336
6337 return 1;
6338}
6339
6340static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6341 struct sk_buff *skb, u32 tx_flags,
6342 __be16 protocol)
7ca647bd 6343{
897ab156
AD		 6344 u32 vlan_macip_lens = 0;
6345 u32 mss_l4len_idx = 0;
6346 u32 type_tucmd = 0;
7ca647bd 6347
897ab156 6348 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6349 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6350 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6351 return false;
6352 } else {
6353 u8 l4_hdr = 0;
6354 switch (protocol) {
6355 case __constant_htons(ETH_P_IP):
6356 vlan_macip_lens |= skb_network_header_len(skb);
6357 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6358 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6359 break;
897ab156
AD		 6360 case __constant_htons(ETH_P_IPV6):
6361 vlan_macip_lens |= skb_network_header_len(skb);
6362 l4_hdr = ipv6_hdr(skb)->nexthdr;
6363 break;
6364 default:
6365 if (unlikely(net_ratelimit())) {
6366 dev_warn(tx_ring->dev,
6367 "partial checksum but proto=%x!\n",
6368 skb->protocol);
6369 }
7ca647bd
JP		 6370 break;
6371 }
897ab156
AD		 6372
6373 switch (l4_hdr) {
7ca647bd 6374 case IPPROTO_TCP:
897ab156
AD		 6375 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6376 mss_l4len_idx = tcp_hdrlen(skb) <<
6377 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6378 break;
6379 case IPPROTO_SCTP:
897ab156
AD		 6380 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6381 mss_l4len_idx = sizeof(struct sctphdr) <<
6382 IXGBE_ADVTXD_L4LEN_SHIFT;
6383 break;
6384 case IPPROTO_UDP:
6385 mss_l4len_idx = sizeof(struct udphdr) <<
6386 IXGBE_ADVTXD_L4LEN_SHIFT;
6387 break;
6388 default:
6389 if (unlikely(net_ratelimit())) {
6390 dev_warn(tx_ring->dev,
6391 "partial checksum but l4 proto=%x!\n",
6392 skb->protocol);
6393 }
7ca647bd
JP		 6394 break;
6395 }
7ca647bd
JP		 6396 }
6397
897ab156
AD		 6398 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6399 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6400
897ab156
AD		 6401 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6402 type_tucmd, mss_l4len_idx);
9a799d71 6403
897ab156 6404 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6405}
6406
d3d00239 6407static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6408{
d3d00239
AD		 6409 /* set type for advanced descriptor with frame checksum insertion */
6410 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6411 IXGBE_ADVTXD_DCMD_IFCS |
6412 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6413
d3d00239 6414 /* set HW vlan bit if vlan is present */
66f32a8b 6415 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6416 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6417
d3d00239
AD		 6418 /* set segmentation enable bits for TSO/FSO */
6419#ifdef IXGBE_FCOE
6420 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6421#else
6422 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6423#endif
6424 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6425
d3d00239
AD		 6426 return cmd_type;
6427}
9a799d71 6428
d3d00239
AD		 6429static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6430{
6431 __le32 olinfo_status =
6432 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6433
d3d00239
AD		 6434 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6435 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6436 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6437 /* enble IPv4 checksum for TSO */
6438 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6439 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6440 }
6441
d3d00239
AD		 6442 /* enable L4 checksum for TSO and TX checksum offload */
6443 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6444 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6445
d3d00239
AD		 6446#ifdef IXGBE_FCOE
6447 /* use index 1 context for FCOE/FSO */
6448 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6449 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6450 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6451
d3d00239 6452#endif
7f9643fd
AD		 6453 /*
6454 * Check Context must be set if Tx switch is enabled, which it
6455 * always is for case where virtual functions are running
6456 */
6457 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6458 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6459
d3d00239
AD		 6460 return olinfo_status;
6461}
44df32c5 6462
d3d00239
AD		 6463#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6464 IXGBE_TXD_CMD_RS)
6465
6466static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6467 struct sk_buff *skb,
6468 struct ixgbe_tx_buffer *first,
6469 u32 tx_flags,
6470 const u8 hdr_len)
6471{
6472 struct device *dev = tx_ring->dev;
6473 struct ixgbe_tx_buffer *tx_buffer_info;
6474 union ixgbe_adv_tx_desc *tx_desc;
6475 dma_addr_t dma;
6476 __le32 cmd_type, olinfo_status;
6477 struct skb_frag_struct *frag;
6478 unsigned int f = 0;
6479 unsigned int data_len = skb->data_len;
6480 unsigned int size = skb_headlen(skb);
6481 u32 offset = 0;
6482 u32 paylen = skb->len - hdr_len;
6483 u16 i = tx_ring->next_to_use;
6484 u16 gso_segs;
6485
6486#ifdef IXGBE_FCOE
6487 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6488 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6489 data_len -= sizeof(struct fcoe_crc_eof);
6490 } else {
6491 size -= sizeof(struct fcoe_crc_eof) - data_len;
6492 data_len = 0;
9a799d71
AK		 6493 }
6494 }
44df32c5 6495
d3d00239
AD		 6496#endif
6497 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6498 if (dma_mapping_error(dev, dma))
6499 goto dma_error;
8ad494b0 6500
d3d00239
AD		 6501 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6502 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6503
d3d00239 6504 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6505
d3d00239
AD		 6506 for (;;) {
6507 while (size > IXGBE_MAX_DATA_PER_TXD) {
6508 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6509 tx_desc->read.cmd_type_len =
6510 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6511 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6512
d3d00239
AD		 6513 offset += IXGBE_MAX_DATA_PER_TXD;
6514 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6515
d3d00239
AD		 6516 tx_desc++;
6517 i++;
6518 if (i == tx_ring->count) {
6519 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6520 i = 0;
6521 }
6522 }
e5a43549 6523
e5a43549 6524 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6525 tx_buffer_info->length = offset + size;
6526 tx_buffer_info->tx_flags = tx_flags;
6527 tx_buffer_info->dma = dma;
9a799d71 6528
d3d00239
AD		 6529 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6530 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6531 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6532
d3d00239
AD		 6533 if (!data_len)
6534 break;
9a799d71 6535
d3d00239
AD		 6536 frag = &skb_shinfo(skb)->frags[f];
6537#ifdef IXGBE_FCOE
9e903e08 6538 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6539#else
9e903e08 6540 size = skb_frag_size(frag);
d3d00239
AD		 6541#endif
6542 data_len -= size;
6543 f++;
9a799d71 6544
d3d00239
AD		 6545 offset = 0;
6546 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6547
877749bf 6548 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6549 if (dma_mapping_error(dev, dma))
6550 goto dma_error;
9a799d71 6551
d3d00239
AD		 6552 tx_desc++;
6553 i++;
6554 if (i == tx_ring->count) {
6555 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6556 i = 0;
6557 }
6558 }
9a799d71 6559
d3d00239 6560 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6561
d3d00239
AD		 6562 i++;
6563 if (i == tx_ring->count)
6564 i = 0;
9a799d71 6565
d3d00239 6566 tx_ring->next_to_use = i;
eacd73f7 6567
d3d00239
AD		 6568 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6569 gso_segs = skb_shinfo(skb)->gso_segs;
6570#ifdef IXGBE_FCOE
6571 /* adjust for FCoE Sequence Offload */
6572 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6573 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6574 skb_shinfo(skb)->gso_size);
6575#endif /* IXGBE_FCOE */
6576 else
6577 gso_segs = 1;
9a799d71 6578
d3d00239
AD		 6579 /* multiply data chunks by size of headers */
6580 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6581 tx_buffer_info->gso_segs = gso_segs;
6582 tx_buffer_info->skb = skb;
9a799d71 6583
d3d00239
AD		 6584 /* set the timestamp */
6585 first->time_stamp = jiffies;
9a799d71
AK		 6586
6587 /*
6588 * Force memory writes to complete before letting h/w
6589 * know there are new descriptors to fetch. (Only
6590 * applicable for weak-ordered memory model archs,
6591 * such as IA-64).
6592 */
6593 wmb();
6594
d3d00239
AD		 6595 /* set next_to_watch value indicating a packet is present */
6596 first->next_to_watch = tx_desc;
6597
6598 /* notify HW of packet */
84ea2591 6599 writel(i, tx_ring->tail);
d3d00239
AD		 6600
6601 return;
6602dma_error:
6603 dev_err(dev, "TX DMA map failed\n");
6604
6605 /* clear dma mappings for failed tx_buffer_info map */
6606 for (;;) {
6607 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6608 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6609 if (tx_buffer_info == first)
6610 break;
6611 if (i == 0)
6612 i = tx_ring->count;
6613 i--;
6614 }
6615
6616 dev_kfree_skb_any(skb);
6617
6618 tx_ring->next_to_use = i;
9a799d71
AK		 6619}
6620
69830529
AD		 6621static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6622 u32 tx_flags, __be16 protocol)
6623{
6624 struct ixgbe_q_vector *q_vector = ring->q_vector;
6625 union ixgbe_atr_hash_dword input = { .dword = 0 };
6626 union ixgbe_atr_hash_dword common = { .dword = 0 };
6627 union {
6628 unsigned char *network;
6629 struct iphdr *ipv4;
6630 struct ipv6hdr *ipv6;
6631 } hdr;
ee9e0f0b 6632 struct tcphdr *th;
905e4a41 6633 __be16 vlan_id;
c4cf55e5 6634
69830529
AD		 6635 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6636 if (!q_vector)
6637 return;
6638
6639 /* do nothing if sampling is disabled */
6640 if (!ring->atr_sample_rate)
d3ead241 6641 return;
c4cf55e5 6642
69830529 6643 ring->atr_count++;
c4cf55e5 6644
69830529
AD		 6645 /* snag network header to get L4 type and address */
6646 hdr.network = skb_network_header(skb);
6647
6648 /* Currently only IPv4/IPv6 with TCP is supported */
6649 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6650 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6651 (protocol != __constant_htons(ETH_P_IP) ||
6652 hdr.ipv4->protocol != IPPROTO_TCP))
6653 return;
ee9e0f0b
AD		 6654
6655 th = tcp_hdr(skb);
c4cf55e5 6656
66f32a8b
AD		 6657 /* skip this packet since it is invalid or the socket is closing */
6658 if (!th || th->fin)
69830529
AD		 6659 return;
6660
6661 /* sample on all syn packets or once every atr sample count */
6662 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6663 return;
6664
6665 /* reset sample count */
6666 ring->atr_count = 0;
6667
6668 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6669
6670 /*
6671 * src and dst are inverted, think how the receiver sees them
6672 *
6673 * The input is broken into two sections, a non-compressed section
6674 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6675 * is XORed together and stored in the compressed dword.
6676 */
6677 input.formatted.vlan_id = vlan_id;
6678
6679 /*
6680 * since src port and flex bytes occupy the same word XOR them together
6681 * and write the value to source port portion of compressed dword
6682 */
66f32a8b 6683 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6684 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6685 else
6686 common.port.src ^= th->dest ^ protocol;
6687 common.port.dst ^= th->source;
6688
6689 if (protocol == __constant_htons(ETH_P_IP)) {
6690 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6691 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6692 } else {
6693 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6694 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6695 hdr.ipv6->saddr.s6_addr32[1] ^
6696 hdr.ipv6->saddr.s6_addr32[2] ^
6697 hdr.ipv6->saddr.s6_addr32[3] ^
6698 hdr.ipv6->daddr.s6_addr32[0] ^
6699 hdr.ipv6->daddr.s6_addr32[1] ^
6700 hdr.ipv6->daddr.s6_addr32[2] ^
6701 hdr.ipv6->daddr.s6_addr32[3];
6702 }
c4cf55e5
PWJ		 6703
6704 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6705 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6706 input, common, ring->queue_index);
c4cf55e5
PWJ		 6707}
6708
63544e9c 6709static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6710{
fc77dc3c 6711 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6712 /* Herbert's original patch had:
6713 * smp_mb__after_netif_stop_queue();
6714 * but since that doesn't exist yet, just open code it. */
6715 smp_mb();
6716
6717 /* We need to check again in a case another CPU has just
6718 * made room available. */
7d4987de 6719 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6720 return -EBUSY;
6721
6722 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6723 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6724 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6725 return 0;
6726}
6727
82d4e46e 6728static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6729{
7d4987de 6730 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6731 return 0;
fc77dc3c 6732 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6733}
6734
09a3b1f8
SH		 6735static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6736{
6737 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6738 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6739 smp_processor_id();
56075a98 6740#ifdef IXGBE_FCOE
6440752c 6741 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6742
e5b64635
JF		 6743 if (((protocol == htons(ETH_P_FCOE)) ||
6744 (protocol == htons(ETH_P_FIP))) &&
6745 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6746 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6747 txq += adapter->ring_feature[RING_F_FCOE].mask;
6748 return txq;
56075a98
JF		 6749 }
6750#endif
6751
fdd3d631
KK		 6752 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6753 while (unlikely(txq >= dev->real_num_tx_queues))
6754 txq -= dev->real_num_tx_queues;
5f715823 6755 return txq;
fdd3d631 6756 }
c4cf55e5 6757
09a3b1f8
SH		 6758 return skb_tx_hash(dev, skb);
6759}
6760
fc77dc3c 6761netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6762 struct ixgbe_adapter *adapter,
6763 struct ixgbe_ring *tx_ring)
9a799d71 6764{
d3d00239 6765 struct ixgbe_tx_buffer *first;
5f715823 6766 int tso;
d3d00239 6767 u32 tx_flags = 0;
a535c30e
AD		 6768#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6769 unsigned short f;
6770#endif
a535c30e 6771 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6772 __be16 protocol = skb->protocol;
63544e9c 6773 u8 hdr_len = 0;
5e09a105 6774
a535c30e
AD		 6775 /*
6776 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6777 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6778 * + 2 desc gap to keep tail from touching head,
6779 * + 1 desc for context descriptor,
6780 * otherwise try next time
6781 */
6782#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6783 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6784 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6785#else
6786 count += skb_shinfo(skb)->nr_frags;
6787#endif
6788 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6789 tx_ring->tx_stats.tx_busy++;
6790 return NETDEV_TX_BUSY;
6791 }
6792
7f9643fd
AD		 6793#ifdef CONFIG_PCI_IOV
6794 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6795 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6796
6797#endif
66f32a8b 6798 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6799 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6800 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6801 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6802 /* else if it is a SW VLAN check the next protocol and store the tag */
6803 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6804 struct vlan_hdr *vhdr, _vhdr;
6805 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6806 if (!vhdr)
6807 goto out_drop;
6808
6809 protocol = vhdr->h_vlan_encapsulated_proto;
6810 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6811 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6812 }
6813
32701dc2 6814 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6815 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6816 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6817 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6818 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6819 tx_flags |= (skb->priority & 0x7) <<
6820 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6821 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6822 struct vlan_ethhdr *vhdr;
6823 if (skb_header_cloned(skb) &&
6824 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6825 goto out_drop;
6826 vhdr = (struct vlan_ethhdr *)skb->data;
6827 vhdr->h_vlan_TCI = htons(tx_flags >>
6828 IXGBE_TX_FLAGS_VLAN_SHIFT);
6829 } else {
6830 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6831 }
9a799d71 6832 }
eacd73f7 6833
a535c30e 6834 /* record the location of the first descriptor for this packet */
d3d00239 6835 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6836
eacd73f7 6837#ifdef IXGBE_FCOE
66f32a8b
AD		 6838 /* setup tx offload for FCoE */
6839 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6840 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6841 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6842 if (tso < 0)
6843 goto out_drop;
6844 else if (tso)
66f32a8b
AD		 6845 tx_flags |= IXGBE_TX_FLAGS_FSO |
6846 IXGBE_TX_FLAGS_FCOE;
6847 else
6848 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6849
66f32a8b 6850 goto xmit_fcoe;
eacd73f7 6851 }
9a799d71 6852
66f32a8b
AD		 6853#endif /* IXGBE_FCOE */
6854 /* setup IPv4/IPv6 offloads */
6855 if (protocol == __constant_htons(ETH_P_IP))
6856 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6857
66f32a8b
AD		 6858 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6859 if (tso < 0)
897ab156 6860 goto out_drop;
66f32a8b
AD		 6861 else if (tso)
6862 tx_flags |= IXGBE_TX_FLAGS_TSO;
6863 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6864 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6865
6866 /* add the ATR filter if ATR is on */
6867 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6868 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6869
6870#ifdef IXGBE_FCOE
6871xmit_fcoe:
6872#endif /* IXGBE_FCOE */
d3d00239
AD		 6873 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6874
6875 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6876
6877 return NETDEV_TX_OK;
897ab156
AD		 6878
6879out_drop:
6880 dev_kfree_skb_any(skb);
6881 return NETDEV_TX_OK;
9a799d71
AK		 6882}
6883
84418e3b
AD		 6884static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6885{
6886 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6887 struct ixgbe_ring *tx_ring;
6888
6889 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6890 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6891}
6892
9a799d71
AK		 6893/**
6894 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6895 * @netdev: network interface device structure
6896 * @p: pointer to an address structure
6897 *
6898 * Returns 0 on success, negative on failure
6899 **/
6900static int ixgbe_set_mac(struct net_device *netdev, void *p)
6901{
6902 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6903 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6904 struct sockaddr *addr = p;
6905
6906 if (!is_valid_ether_addr(addr->sa_data))
6907 return -EADDRNOTAVAIL;
6908
6909 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6910 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6911
1cdd1ec8
GR		 6912 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6913 IXGBE_RAH_AV);
9a799d71
AK		 6914
6915 return 0;
6916}
6917
6b73e10d
BH		 6918static int
6919ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6920{
6921 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6922 struct ixgbe_hw *hw = &adapter->hw;
6923 u16 value;
6924 int rc;
6925
6926 if (prtad != hw->phy.mdio.prtad)
6927 return -EINVAL;
6928 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6929 if (!rc)
6930 rc = value;
6931 return rc;
6932}
6933
6934static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6935 u16 addr, u16 value)
6936{
6937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6938 struct ixgbe_hw *hw = &adapter->hw;
6939
6940 if (prtad != hw->phy.mdio.prtad)
6941 return -EINVAL;
6942 return hw->phy.ops.write_reg(hw, addr, devad, value);
6943}
6944
6945static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6946{
6947 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6948
6949 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6950}
6951
0365e6e4
PW		 6952/**
6953 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6954 * netdev->dev_addrs
0365e6e4
PW		 6955 * @netdev: network interface device structure
6956 *
6957 * Returns non-zero on failure
6958 **/
6959static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6960{
6961 int err = 0;
6962 struct ixgbe_adapter *adapter = netdev_priv(dev);
6963 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6964
6965 if (is_valid_ether_addr(mac->san_addr)) {
6966 rtnl_lock();
6967 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6968 rtnl_unlock();
6969 }
6970 return err;
6971}
6972
6973/**
6974 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6975 * netdev->dev_addrs
0365e6e4
PW		 6976 * @netdev: network interface device structure
6977 *
6978 * Returns non-zero on failure
6979 **/
6980static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6981{
6982 int err = 0;
6983 struct ixgbe_adapter *adapter = netdev_priv(dev);
6984 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6985
6986 if (is_valid_ether_addr(mac->san_addr)) {
6987 rtnl_lock();
6988 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6989 rtnl_unlock();
6990 }
6991 return err;
6992}
6993
9a799d71
AK		 6994#ifdef CONFIG_NET_POLL_CONTROLLER
6995/*
6996 * Polling 'interrupt' - used by things like netconsole to send skbs
6997 * without having to re-enable interrupts. It's not called while
6998 * the interrupt routine is executing.
6999 */
7000static void ixgbe_netpoll(struct net_device *netdev)
7001{
7002 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7003 int i;
9a799d71 7004
1a647bd2
AD		 7005 /* if interface is down do nothing */
7006 if (test_bit(__IXGBE_DOWN, &adapter->state))
7007 return;
7008
9a799d71 7009 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7010 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7011 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7012 for (i = 0; i < num_q_vectors; i++) {
7013 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7014 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7015 }
7016 } else {
7017 ixgbe_intr(adapter->pdev->irq, netdev);
7018 }
9a799d71 7019 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7020}
7021#endif
7022
de1036b1
ED		 7023static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7024 struct rtnl_link_stats64 *stats)
7025{
7026 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7027 int i;
7028
1a51502b 7029 rcu_read_lock();
de1036b1 7030 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7031 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7032 u64 bytes, packets;
7033 unsigned int start;
7034
1a51502b
ED		 7035 if (ring) {
7036 do {
7037 start = u64_stats_fetch_begin_bh(&ring->syncp);
7038 packets = ring->stats.packets;
7039 bytes = ring->stats.bytes;
7040 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7041 stats->rx_packets += packets;
7042 stats->rx_bytes += bytes;
7043 }
de1036b1 7044 }
1ac9ad13
ED		 7045
7046 for (i = 0; i < adapter->num_tx_queues; i++) {
7047 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7048 u64 bytes, packets;
7049 unsigned int start;
7050
7051 if (ring) {
7052 do {
7053 start = u64_stats_fetch_begin_bh(&ring->syncp);
7054 packets = ring->stats.packets;
7055 bytes = ring->stats.bytes;
7056 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7057 stats->tx_packets += packets;
7058 stats->tx_bytes += bytes;
7059 }
7060 }
1a51502b 7061 rcu_read_unlock();
de1036b1
ED		 7062 /* following stats updated by ixgbe_watchdog_task() */
7063 stats->multicast = netdev->stats.multicast;
7064 stats->rx_errors = netdev->stats.rx_errors;
7065 stats->rx_length_errors = netdev->stats.rx_length_errors;
7066 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7067 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7068 return stats;
7069}
7070
8b1c0b24
JF		 7071/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7072 * #adapter: pointer to ixgbe_adapter
7073 * @tc: number of traffic classes currently enabled
7074 *
7075 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7076 * 802.1Q priority maps to a packet buffer that exists.
7077 */
7078static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7079{
7080 struct ixgbe_hw *hw = &adapter->hw;
7081 u32 reg, rsave;
7082 int i;
7083
7084 /* 82598 have a static priority to TC mapping that can not
7085 * be changed so no validation is needed.
7086 */
7087 if (hw->mac.type == ixgbe_mac_82598EB)
7088 return;
7089
7090 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7091 rsave = reg;
7092
7093 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7094 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7095
7096 /* If up2tc is out of bounds default to zero */
7097 if (up2tc > tc)
7098 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7099 }
7100
7101 if (reg != rsave)
7102 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7103
7104 return;
7105}
7106
7107
7108/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7109 * classes.
7110 *
7111 * @netdev: net device to configure
7112 * @tc: number of traffic classes to enable
7113 */
7114int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7115{
8b1c0b24
JF		 7116 struct ixgbe_adapter *adapter = netdev_priv(dev);
7117 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7118
e7589eab
JF		 7119 /* Multiple traffic classes requires multiple queues */
7120 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7121 e_err(drv, "Enable failed, needs MSI-X\n");
7122 return -EINVAL;
7123 }
8b1c0b24
JF		 7124
7125 /* Hardware supports up to 8 traffic classes */
4de2a022 7126 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7127 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7128 return -EINVAL;
7129
7130 /* Hardware has to reinitialize queues and interrupts to
7131 * match packet buffer alignment. Unfortunantly, the
7132 * hardware is not flexible enough to do this dynamically.
7133 */
7134 if (netif_running(dev))
7135 ixgbe_close(dev);
7136 ixgbe_clear_interrupt_scheme(adapter);
7137
e7589eab 7138 if (tc) {
8b1c0b24 7139 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7140 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7141
7142 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7143 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7144
7145 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7146 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7147 } else {
8b1c0b24
JF		 7148 netdev_reset_tc(dev);
7149
e7589eab
JF		 7150 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7151
7152 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7153 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7154
7155 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7156 adapter->dcb_cfg.pfc_mode_enable = false;
7157 }
7158
8b1c0b24
JF		 7159 ixgbe_init_interrupt_scheme(adapter);
7160 ixgbe_validate_rtr(adapter, tc);
7161 if (netif_running(dev))
7162 ixgbe_open(dev);
7163
7164 return 0;
7165}
de1036b1 7166
082757af
DS		 7167void ixgbe_do_reset(struct net_device *netdev)
7168{
7169 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7170
7171 if (netif_running(netdev))
7172 ixgbe_reinit_locked(adapter);
7173 else
7174 ixgbe_reset(adapter);
7175}
7176
c8f44aff
MM		 7177static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7178 netdev_features_t data)
082757af
DS		 7179{
7180 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7181
7182#ifdef CONFIG_DCB
7183 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7184 data &= ~NETIF_F_HW_VLAN_RX;
7185#endif
7186
7187 /* return error if RXHASH is being enabled when RSS is not supported */
7188 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7189 data &= ~NETIF_F_RXHASH;
7190
7191 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7192 if (!(data & NETIF_F_RXCSUM))
7193 data &= ~NETIF_F_LRO;
7194
7195 /* Turn off LRO if not RSC capable or invalid ITR settings */
7196 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7197 data &= ~NETIF_F_LRO;
7198 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7199 (adapter->rx_itr_setting != 1 &&
7200 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7201 data &= ~NETIF_F_LRO;
7202 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7203 }
7204
7205 return data;
7206}
7207
c8f44aff
MM		 7208static int ixgbe_set_features(struct net_device *netdev,
7209 netdev_features_t data)
082757af
DS		 7210{
7211 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7212 bool need_reset = false;
7213
7214 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7215 if (!(data & NETIF_F_RXCSUM))
7216 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7217 else
7218 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7219
7220 /* Make sure RSC matches LRO, reset if change */
7221 if (!!(data & NETIF_F_LRO) !=
7222 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7223 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7224 switch (adapter->hw.mac.type) {
7225 case ixgbe_mac_X540:
7226 case ixgbe_mac_82599EB:
7227 need_reset = true;
7228 break;
7229 default:
7230 break;
7231 }
7232 }
7233
7234 /*
7235 * Check if Flow Director n-tuple support was enabled or disabled. If
7236 * the state changed, we need to reset.
7237 */
7238 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7239 /* turn off ATR, enable perfect filters and reset */
7240 if (data & NETIF_F_NTUPLE) {
7241 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7242 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7243 need_reset = true;
7244 }
7245 } else if (!(data & NETIF_F_NTUPLE)) {
7246 /* turn off Flow Director, set ATR and reset */
7247 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7248 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7249 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7250 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7251 need_reset = true;
7252 }
7253
7254 if (need_reset)
7255 ixgbe_do_reset(netdev);
7256
7257 return 0;
7258
7259}
7260
0edc3527 7261static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7262 .ndo_open = ixgbe_open,
0edc3527 7263 .ndo_stop = ixgbe_close,
00829823 7264 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7265 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7266 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7267 .ndo_validate_addr = eth_validate_addr,
7268 .ndo_set_mac_address = ixgbe_set_mac,
7269 .ndo_change_mtu = ixgbe_change_mtu,
7270 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7271 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7272 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7273 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7274 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7275 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7276 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7277 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7278 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7279 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7280 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7281#ifdef CONFIG_NET_POLL_CONTROLLER
7282 .ndo_poll_controller = ixgbe_netpoll,
7283#endif
332d4a7d
YZ		 7284#ifdef IXGBE_FCOE
7285 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7286 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7287 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7288 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7289 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7290 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7291#endif /* IXGBE_FCOE */
082757af
DS		 7292 .ndo_set_features = ixgbe_set_features,
7293 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7294};
7295
1cdd1ec8
GR		 7296static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7297 const struct ixgbe_info *ii)
7298{
7299#ifdef CONFIG_PCI_IOV
7300 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7301
c6bda30a 7302 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7303 return;
7304
7305 /* The 82599 supports up to 64 VFs per physical function
7306 * but this implementation limits allocation to 63 so that
7307 * basic networking resources are still available to the
7308 * physical function
7309 */
7310 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7311 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7312#endif /* CONFIG_PCI_IOV */
7313}
7314
9a799d71
AK		 7315/**
7316 * ixgbe_probe - Device Initialization Routine
7317 * @pdev: PCI device information struct
7318 * @ent: entry in ixgbe_pci_tbl
7319 *
7320 * Returns 0 on success, negative on failure
7321 *
7322 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7323 * The OS initialization, configuring of the adapter private structure,
7324 * and a hardware reset occur.
7325 **/
7326static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7327 const struct pci_device_id *ent)
9a799d71
AK		 7328{
7329 struct net_device *netdev;
7330 struct ixgbe_adapter *adapter = NULL;
7331 struct ixgbe_hw *hw;
7332 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7333 static int cards_found;
7334 int i, err, pci_using_dac;
289700db 7335 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7336 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7337#ifdef IXGBE_FCOE
7338 u16 device_caps;
7339#endif
289700db 7340 u32 eec;
c23f5b6b 7341 u16 wol_cap;
9a799d71 7342
bded64a7
AG		 7343 /* Catch broken hardware that put the wrong VF device ID in
7344 * the PCIe SR-IOV capability.
7345 */
7346 if (pdev->is_virtfn) {
7347 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7348 pci_name(pdev), pdev->vendor, pdev->device);
7349 return -EINVAL;
7350 }
7351
9ce77666 7352 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7353 if (err)
7354 return err;
7355
1b507730
NN		 7356 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7357 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7358 pci_using_dac = 1;
7359 } else {
1b507730 7360 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7361 if (err) {
1b507730
NN		 7362 err = dma_set_coherent_mask(&pdev->dev,
7363 DMA_BIT_MASK(32));
9a799d71 7364 if (err) {
b8bc0421
DC		 7365 dev_err(&pdev->dev,
7366 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7367 goto err_dma;
7368 }
7369 }
7370 pci_using_dac = 0;
7371 }
7372
9ce77666 7373 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7374 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7375 if (err) {
b8bc0421
DC		 7376 dev_err(&pdev->dev,
7377 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7378 goto err_pci_reg;
7379 }
7380
19d5afd4 7381 pci_enable_pcie_error_reporting(pdev);
6fabd715 7382
9a799d71 7383 pci_set_master(pdev);
fb3b27bc 7384 pci_save_state(pdev);
9a799d71 7385
e901acd6
JF		 7386#ifdef CONFIG_IXGBE_DCB
7387 indices *= MAX_TRAFFIC_CLASS;
7388#endif
7389
c85a2618
JF		 7390 if (ii->mac == ixgbe_mac_82598EB)
7391 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7392 else
7393 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7394
e901acd6 7395#ifdef IXGBE_FCOE
c85a2618
JF		 7396 indices += min_t(unsigned int, num_possible_cpus(),
7397 IXGBE_MAX_FCOE_INDICES);
7398#endif
c85a2618 7399 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7400 if (!netdev) {
7401 err = -ENOMEM;
7402 goto err_alloc_etherdev;
7403 }
7404
9a799d71
AK		 7405 SET_NETDEV_DEV(netdev, &pdev->dev);
7406
9a799d71 7407 adapter = netdev_priv(netdev);
c60fbb00 7408 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7409
7410 adapter->netdev = netdev;
7411 adapter->pdev = pdev;
7412 hw = &adapter->hw;
7413 hw->back = adapter;
7414 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7415
05857980 7416 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7417 pci_resource_len(pdev, 0));
9a799d71
AK		 7418 if (!hw->hw_addr) {
7419 err = -EIO;
7420 goto err_ioremap;
7421 }
7422
7423 for (i = 1; i <= 5; i++) {
7424 if (pci_resource_len(pdev, i) == 0)
7425 continue;
7426 }
7427
0edc3527 7428 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7429 ixgbe_set_ethtool_ops(netdev);
9a799d71 7430 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7431 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7432
9a799d71
AK		 7433 adapter->bd_number = cards_found;
7434
9a799d71
AK		 7435 /* Setup hw api */
7436 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7437 hw->mac.type = ii->mac;
9a799d71 7438
c44ade9e
JB		 7439 /* EEPROM */
7440 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7441 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7442 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7443 if (!(eec & (1 << 8)))
7444 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7445
7446 /* PHY */
7447 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7448 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7449 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7450 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7451 hw->phy.mdio.mmds = 0;
7452 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7453 hw->phy.mdio.dev = netdev;
7454 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7455 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7456
8ca783ab 7457 ii->get_invariants(hw);
9a799d71
AK		 7458
7459 /* setup the private structure */
7460 err = ixgbe_sw_init(adapter);
7461 if (err)
7462 goto err_sw_init;
7463
e86bff0e 7464 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7465 switch (adapter->hw.mac.type) {
7466 case ixgbe_mac_82599EB:
7467 case ixgbe_mac_X540:
e86bff0e 7468 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7469 break;
7470 default:
7471 break;
7472 }
e86bff0e 7473
bf069c97
DS		 7474 /*
7475 * If there is a fan on this device and it has failed log the
7476 * failure.
7477 */
7478 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7479 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7480 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7481 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7482 }
7483
c44ade9e 7484 /* reset_hw fills in the perm_addr as well */
119fc60a 7485 hw->phy.reset_if_overtemp = true;
c44ade9e 7486 err = hw->mac.ops.reset_hw(hw);
119fc60a 7487 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7488 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7489 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7490 err = 0;
7491 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7492 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7493 "module type was detected.\n");
7494 e_dev_err("Reload the driver after installing a supported "
7495 "module.\n");
04f165ef
PW		 7496 goto err_sw_init;
7497 } else if (err) {
849c4542 7498 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7499 goto err_sw_init;
7500 }
7501
1cdd1ec8
GR		 7502 ixgbe_probe_vf(adapter, ii);
7503
396e799c 7504 netdev->features = NETIF_F_SG |
e8e9f696 7505 NETIF_F_IP_CSUM |
082757af 7506 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7507 NETIF_F_HW_VLAN_TX |
7508 NETIF_F_HW_VLAN_RX |
082757af
DS		 7509 NETIF_F_HW_VLAN_FILTER |
7510 NETIF_F_TSO |
7511 NETIF_F_TSO6 |
082757af
DS		 7512 NETIF_F_RXHASH |
7513 NETIF_F_RXCSUM;
9a799d71 7514
082757af 7515 netdev->hw_features = netdev->features;
ad31c402 7516
58be7666
DS		 7517 switch (adapter->hw.mac.type) {
7518 case ixgbe_mac_82599EB:
7519 case ixgbe_mac_X540:
45a5ead0 7520 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7521 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7522 NETIF_F_NTUPLE;
58be7666
DS		 7523 break;
7524 default:
7525 break;
7526 }
45a5ead0 7527
ad31c402
JK		 7528 netdev->vlan_features |= NETIF_F_TSO;
7529 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7530 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7531 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7532 netdev->vlan_features |= NETIF_F_SG;
7533
01789349
JP		 7534 netdev->priv_flags |= IFF_UNICAST_FLT;
7535
1cdd1ec8
GR		 7536 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7537 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7538 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7539
7a6b6f51 7540#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7541 netdev->dcbnl_ops = &dcbnl_ops;
7542#endif
7543
eacd73f7 7544#ifdef IXGBE_FCOE
0d551589 7545 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7546 if (hw->mac.ops.get_device_caps) {
7547 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7548 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7549 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7550 }
7551 }
5e09d7f6
YZ		 7552 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7553 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7554 netdev->vlan_features |= NETIF_F_FSO;
7555 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7556 }
eacd73f7 7557#endif /* IXGBE_FCOE */
7b872a55 7558 if (pci_using_dac) {
9a799d71 7559 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7560 netdev->vlan_features |= NETIF_F_HIGHDMA;
7561 }
9a799d71 7562
082757af
DS		 7563 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7564 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7565 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7566 netdev->features |= NETIF_F_LRO;
7567
9a799d71 7568 /* make sure the EEPROM is good */
c44ade9e 7569 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7570 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7571 err = -EIO;
7572 goto err_eeprom;
7573 }
7574
7575 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7576 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7577
c44ade9e 7578 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7579 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7580 err = -EIO;
7581 goto err_eeprom;
7582 }
7583
7086400d
AD		 7584 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7585 (unsigned long) adapter);
9a799d71 7586
7086400d
AD		 7587 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7588 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7589
021230d4
AV		 7590 err = ixgbe_init_interrupt_scheme(adapter);
7591 if (err)
7592 goto err_sw_init;
9a799d71 7593
082757af
DS		 7594 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7595 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7596 netdev->features &= ~NETIF_F_RXHASH;
082757af 7597 }
67a74ee2 7598
c23f5b6b
ET		 7599 /* WOL not supported for all but the following */
7600 adapter->wol = 0;
e8e26350 7601 switch (pdev->device) {
0b077fea
DS		 7602 case IXGBE_DEV_ID_82599_SFP:
7603 /* Only this subdevice supports WOL */
7604 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
9417c464 7605 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7606 break;
50d6c681
AD		 7607 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7608 /* All except this subdevice support WOL */
0b077fea 7609 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7610 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7611 break;
e8e26350 7612 case IXGBE_DEV_ID_82599_KX4:
9417c464 7613 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7614 break;
c23f5b6b
ET		 7615 case IXGBE_DEV_ID_X540T:
7616 /* Check eeprom to see if it is enabled */
7617 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7618 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7619
7620 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7621 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7622 (hw->bus.func == 0)))
7623 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7624 break;
7625 }
e8e26350
PW		 7626 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7627
15e5209f
ET		 7628 /* save off EEPROM version number */
7629 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7630 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7631
04f165ef
PW		 7632 /* pick up the PCI bus settings for reporting later */
7633 hw->mac.ops.get_bus_info(hw);
7634
9a799d71 7635 /* print bus type/speed/width info */
849c4542 7636 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7637 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7638 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7639 "Unknown"),
7640 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7641 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7642 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7643 "Unknown"),
7644 netdev->dev_addr);
289700db
DS		 7645
7646 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7647 if (err)
9fe93afd 7648 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7649 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7650 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7651 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7652 part_str);
e8e26350 7653 else
289700db
DS		 7654 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7655 hw->mac.type, hw->phy.type, part_str);
9a799d71 7656
e8e26350 7657 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7658 e_dev_warn("PCI-Express bandwidth available for this card is "
7659 "not sufficient for optimal performance.\n");
7660 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7661 "is required.\n");
0c254d86
AK		 7662 }
7663
9a799d71 7664 /* reset the hardware with the new settings */
794caeb2 7665 err = hw->mac.ops.start_hw(hw);
c44ade9e 7666
794caeb2
PWJ		 7667 if (err == IXGBE_ERR_EEPROM_VERSION) {
7668 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7669 e_dev_warn("This device is a pre-production adapter/LOM. "
7670 "Please be aware there may be issues associated "
7671 "with your hardware. If you are experiencing "
7672 "problems please contact your Intel or hardware "
7673 "representative who provided you with this "
7674 "hardware.\n");
794caeb2 7675 }
9a799d71
AK		 7676 strcpy(netdev->name, "eth%d");
7677 err = register_netdev(netdev);
7678 if (err)
7679 goto err_register;
7680
93d3ce8f
ET		 7681 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7682 if (hw->mac.ops.disable_tx_laser &&
7683 ((hw->phy.multispeed_fiber) ||
7684 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7685 (hw->mac.type == ixgbe_mac_82599EB))))
7686 hw->mac.ops.disable_tx_laser(hw);
7687
54386467
JB		 7688 /* carrier off reporting is important to ethtool even BEFORE open */
7689 netif_carrier_off(netdev);
7690
5dd2d332 7691#ifdef CONFIG_IXGBE_DCA
652f093f 7692 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7693 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7694 ixgbe_setup_dca(adapter);
7695 }
7696#endif
1cdd1ec8 7697 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7698 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7699 for (i = 0; i < adapter->num_vfs; i++)
7700 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7701 }
7702
2466dd9c
JK		 7703 /* firmware requires driver version to be 0xFFFFFFFF
7704 * since os does not support feature
7705 */
9612de92 7706 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7707 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7708 0xFF);
9612de92 7709
0365e6e4
PW		 7710 /* add san mac addr to netdev */
7711 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7712
849c4542 7713 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7714 cards_found++;
7715 return 0;
7716
7717err_register:
5eba3699 7718 ixgbe_release_hw_control(adapter);
7a921c93 7719 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7720err_sw_init:
7721err_eeprom:
1cdd1ec8
GR		 7722 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7723 ixgbe_disable_sriov(adapter);
7086400d 7724 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7725 iounmap(hw->hw_addr);
7726err_ioremap:
7727 free_netdev(netdev);
7728err_alloc_etherdev:
e8e9f696
JP		 7729 pci_release_selected_regions(pdev,
7730 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7731err_pci_reg:
7732err_dma:
7733 pci_disable_device(pdev);
7734 return err;
7735}
7736
7737/**
7738 * ixgbe_remove - Device Removal Routine
7739 * @pdev: PCI device information struct
7740 *
7741 * ixgbe_remove is called by the PCI subsystem to alert the driver
7742 * that it should release a PCI device. The could be caused by a
7743 * Hot-Plug event, or because the driver is going to be removed from
7744 * memory.
7745 **/
7746static void __devexit ixgbe_remove(struct pci_dev *pdev)
7747{
c60fbb00
AD		 7748 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7749 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7750
7751 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7752 cancel_work_sync(&adapter->service_task);
9a799d71 7753
5dd2d332 7754#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7755 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7756 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7757 dca_remove_requester(&pdev->dev);
7758 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7759 }
7760
7761#endif
332d4a7d
YZ		 7762#ifdef IXGBE_FCOE
7763 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7764 ixgbe_cleanup_fcoe(adapter);
7765
7766#endif /* IXGBE_FCOE */
0365e6e4
PW		 7767
7768 /* remove the added san mac */
7769 ixgbe_del_sanmac_netdev(netdev);
7770
c4900be0
DS		 7771 if (netdev->reg_state == NETREG_REGISTERED)
7772 unregister_netdev(netdev);
9a799d71 7773
c6bda30a
GR		 7774 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7775 if (!(ixgbe_check_vf_assignment(adapter)))
7776 ixgbe_disable_sriov(adapter);
7777 else
7778 e_dev_warn("Unloading driver while VFs are assigned "
7779 "- VFs will not be deallocated\n");
7780 }
1cdd1ec8 7781
7a921c93 7782 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7783
021230d4 7784 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7785
7786 iounmap(adapter->hw.hw_addr);
9ce77666 7787 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7788 IORESOURCE_MEM));
9a799d71 7789
849c4542 7790 e_dev_info("complete\n");
021230d4 7791
9a799d71
AK		 7792 free_netdev(netdev);
7793
19d5afd4 7794 pci_disable_pcie_error_reporting(pdev);
6fabd715 7795
9a799d71
AK		 7796 pci_disable_device(pdev);
7797}
7798
7799/**
7800 * ixgbe_io_error_detected - called when PCI error is detected
7801 * @pdev: Pointer to PCI device
7802 * @state: The current pci connection state
7803 *
7804 * This function is called after a PCI bus error affecting
7805 * this device has been detected.
7806 */
7807static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7808 pci_channel_state_t state)
9a799d71 7809{
c60fbb00
AD		 7810 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7811 struct net_device *netdev = adapter->netdev;
9a799d71 7812
83c61fa9
GR		 7813#ifdef CONFIG_PCI_IOV
7814 struct pci_dev *bdev, *vfdev;
7815 u32 dw0, dw1, dw2, dw3;
7816 int vf, pos;
7817 u16 req_id, pf_func;
7818
7819 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7820 adapter->num_vfs == 0)
7821 goto skip_bad_vf_detection;
7822
7823 bdev = pdev->bus->self;
7824 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7825 bdev = bdev->bus->self;
7826
7827 if (!bdev)
7828 goto skip_bad_vf_detection;
7829
7830 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7831 if (!pos)
7832 goto skip_bad_vf_detection;
7833
7834 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7835 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7836 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7837 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7838
7839 req_id = dw1 >> 16;
7840 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7841 if (!(req_id & 0x0080))
7842 goto skip_bad_vf_detection;
7843
7844 pf_func = req_id & 0x01;
7845 if ((pf_func & 1) == (pdev->devfn & 1)) {
7846 unsigned int device_id;
7847
7848 vf = (req_id & 0x7F) >> 1;
7849 e_dev_err("VF %d has caused a PCIe error\n", vf);
7850 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7851 "%8.8x\tdw3: %8.8x\n",
7852 dw0, dw1, dw2, dw3);
7853 switch (adapter->hw.mac.type) {
7854 case ixgbe_mac_82599EB:
7855 device_id = IXGBE_82599_VF_DEVICE_ID;
7856 break;
7857 case ixgbe_mac_X540:
7858 device_id = IXGBE_X540_VF_DEVICE_ID;
7859 break;
7860 default:
7861 device_id = 0;
7862 break;
7863 }
7864
7865 /* Find the pci device of the offending VF */
7866 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7867 while (vfdev) {
7868 if (vfdev->devfn == (req_id & 0xFF))
7869 break;
7870 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7871 device_id, vfdev);
7872 }
7873 /*
7874 * There's a slim chance the VF could have been hot plugged,
7875 * so if it is no longer present we don't need to issue the
7876 * VFLR. Just clean up the AER in that case.
7877 */
7878 if (vfdev) {
7879 e_dev_err("Issuing VFLR to VF %d\n", vf);
7880 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7881 }
7882
7883 pci_cleanup_aer_uncorrect_error_status(pdev);
7884 }
7885
7886 /*
7887 * Even though the error may have occurred on the other port
7888 * we still need to increment the vf error reference count for
7889 * both ports because the I/O resume function will be called
7890 * for both of them.
7891 */
7892 adapter->vferr_refcount++;
7893
7894 return PCI_ERS_RESULT_RECOVERED;
7895
7896skip_bad_vf_detection:
7897#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7898 netif_device_detach(netdev);
7899
3044b8d1
BL		 7900 if (state == pci_channel_io_perm_failure)
7901 return PCI_ERS_RESULT_DISCONNECT;
7902
9a799d71
AK		 7903 if (netif_running(netdev))
7904 ixgbe_down(adapter);
7905 pci_disable_device(pdev);
7906
b4617240 7907 /* Request a slot reset. */
9a799d71
AK		 7908 return PCI_ERS_RESULT_NEED_RESET;
7909}
7910
7911/**
7912 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7913 * @pdev: Pointer to PCI device
7914 *
7915 * Restart the card from scratch, as if from a cold-boot.
7916 */
7917static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7918{
c60fbb00 7919 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7920 pci_ers_result_t result;
7921 int err;
9a799d71 7922
9ce77666 7923 if (pci_enable_device_mem(pdev)) {
396e799c 7924 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7925 result = PCI_ERS_RESULT_DISCONNECT;
7926 } else {
7927 pci_set_master(pdev);
7928 pci_restore_state(pdev);
c0e1f68b 7929 pci_save_state(pdev);
9a799d71 7930
dd4d8ca6 7931 pci_wake_from_d3(pdev, false);
9a799d71 7932
6fabd715 7933 ixgbe_reset(adapter);
88512539 7934 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7935 result = PCI_ERS_RESULT_RECOVERED;
7936 }
7937
7938 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7939 if (err) {
849c4542
ET		 7940 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7941 "failed 0x%0x\n", err);
6fabd715
PWJ		 7942 /* non-fatal, continue */
7943 }
9a799d71 7944
6fabd715 7945 return result;
9a799d71
AK		 7946}
7947
7948/**
7949 * ixgbe_io_resume - called when traffic can start flowing again.
7950 * @pdev: Pointer to PCI device
7951 *
7952 * This callback is called when the error recovery driver tells us that
7953 * its OK to resume normal operation.
7954 */
7955static void ixgbe_io_resume(struct pci_dev *pdev)
7956{
c60fbb00
AD		 7957 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7958 struct net_device *netdev = adapter->netdev;
9a799d71 7959
83c61fa9
GR		 7960#ifdef CONFIG_PCI_IOV
7961 if (adapter->vferr_refcount) {
7962 e_info(drv, "Resuming after VF err\n");
7963 adapter->vferr_refcount--;
7964 return;
7965 }
7966
7967#endif
c7ccde0f
AD		 7968 if (netif_running(netdev))
7969 ixgbe_up(adapter);
9a799d71
AK		 7970
7971 netif_device_attach(netdev);
9a799d71
AK		 7972}
7973
7974static struct pci_error_handlers ixgbe_err_handler = {
7975 .error_detected = ixgbe_io_error_detected,
7976 .slot_reset = ixgbe_io_slot_reset,
7977 .resume = ixgbe_io_resume,
7978};
7979
7980static struct pci_driver ixgbe_driver = {
7981 .name = ixgbe_driver_name,
7982 .id_table = ixgbe_pci_tbl,
7983 .probe = ixgbe_probe,
7984 .remove = __devexit_p(ixgbe_remove),
7985#ifdef CONFIG_PM
7986 .suspend = ixgbe_suspend,
7987 .resume = ixgbe_resume,
7988#endif
7989 .shutdown = ixgbe_shutdown,
7990 .err_handler = &ixgbe_err_handler
7991};
7992
7993/**
7994 * ixgbe_init_module - Driver Registration Routine
7995 *
7996 * ixgbe_init_module is the first routine called when the driver is
7997 * loaded. All it does is register with the PCI subsystem.
7998 **/
7999static int __init ixgbe_init_module(void)
8000{
8001 int ret;
c7689578 8002 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8003 pr_info("%s\n", ixgbe_copyright);
9a799d71 8004
5dd2d332 8005#ifdef CONFIG_IXGBE_DCA
bd0362dd 8006 dca_register_notify(&dca_notifier);
bd0362dd 8007#endif
5dd2d332 8008
9a799d71
AK		 8009 ret = pci_register_driver(&ixgbe_driver);
8010 return ret;
8011}
b4617240 8012
9a799d71
AK		 8013module_init(ixgbe_init_module);
8014
8015/**
8016 * ixgbe_exit_module - Driver Exit Cleanup Routine
8017 *
8018 * ixgbe_exit_module is called just before the driver is removed
8019 * from memory.
8020 **/
8021static void __exit ixgbe_exit_module(void)
8022{
5dd2d332 8023#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8024 dca_unregister_notify(&dca_notifier);
8025#endif
9a799d71 8026 pci_unregister_driver(&ixgbe_driver);
1a51502b 8027 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8028}
bd0362dd 8029
5dd2d332 8030#ifdef CONFIG_IXGBE_DCA
bd0362dd 8031static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8032 void *p)
bd0362dd
JC		 8033{
8034 int ret_val;
8035
8036 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8037 __ixgbe_notify_dca);
bd0362dd
JC		 8038
8039 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8040}
b453368d 8041
5dd2d332 8042#endif /* CONFIG_IXGBE_DCA */
849c4542 8043
9a799d71
AK		 8044module_exit(ixgbe_exit_module);
8045
8046/* ixgbe_main.c */
Linux kernel - Deliverables
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