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ixgbe: Add support for setting CC bit when SR-IOV is enabled
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 58#define MAJ 3
a38a104d 59#define MIN 4
c89c7112 60#define BUILD 8
75e3d3c6 61#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 62 __stringify(BUILD) "-k"
9c8eb720 63const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 64static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 66
67static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 68 [board_82598] = &ixgbe_82598_info,
e8e26350 69 [board_82599] = &ixgbe_82599_info,
fe15e8e1 70 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 71};
72
73/* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
a3aa1884 81static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
1e336d0f
DS		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
83 board_82598 },
9a799d71 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
3957d63d 85 board_82598 },
9a799d71 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
3957d63d 87 board_82598 },
0befdb3e
JB		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
89 board_82598 },
3845bec0
PWJ		 90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
91 board_82598 },
9a799d71 92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
3957d63d 93 board_82598 },
8d792cd9
JB		 94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
95 board_82598 },
c4900be0
DS		 96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
97 board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
99 board_82598 },
b95f5fcb
JB		 100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
101 board_82598 },
c4900be0
DS		 102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
103 board_82598 },
2f21bdd3
DS		 104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
105 board_82598 },
e8e26350
PW		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
107 board_82599 },
1fcf03e6
PWJ		 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
109 board_82599 },
74757d49
DS		 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
111 board_82599 },
e8e26350
PW		 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
113 board_82599 },
38ad1c8e
DS		 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
115 board_82599 },
dbfec662
DS		 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
117 board_82599 },
8911184f
PWJ		 118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
119 board_82599 },
dbffcb21
DS		 120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
121 board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
123 board_82599 },
119fc60a
MC		 124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
125 board_82599 },
312eb931
DS		 126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
127 board_82599 },
b93a2226 128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
d994653d 129 board_X540 },
4c40ef02
ET		 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
131 board_82599 },
4f6290cf
DS		 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
133 board_82599 },
9a799d71
AK		 134
135 /* required last entry */
136 {0, }
137};
138MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
139
5dd2d332 140#ifdef CONFIG_IXGBE_DCA
bd0362dd 141static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 142 void *p);
bd0362dd
JC		 143static struct notifier_block dca_notifier = {
144 .notifier_call = ixgbe_notify_dca,
145 .next = NULL,
146 .priority = 0
147};
148#endif
149
1cdd1ec8
GR		 150#ifdef CONFIG_PCI_IOV
151static unsigned int max_vfs;
152module_param(max_vfs, uint, 0);
e8e9f696
JP		 153MODULE_PARM_DESC(max_vfs,
154 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 155#endif /* CONFIG_PCI_IOV */
156
9a799d71
AK		 157MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
158MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
159MODULE_LICENSE("GPL");
160MODULE_VERSION(DRV_VERSION);
161
162#define DEFAULT_DEBUG_LEVEL_SHIFT 3
163
1cdd1ec8
GR		 164static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
165{
166 struct ixgbe_hw *hw = &adapter->hw;
167 u32 gcr;
168 u32 gpie;
169 u32 vmdctl;
170
171#ifdef CONFIG_PCI_IOV
172 /* disable iov and allow time for transactions to clear */
173 pci_disable_sriov(adapter->pdev);
174#endif
175
176 /* turn off device IOV mode */
177 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
178 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
179 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
180 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
181 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
182 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
183
184 /* set default pool back to 0 */
185 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
186 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
187 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
945a5151 188 IXGBE_WRITE_FLUSH(hw);
1cdd1ec8
GR		 189
190 /* take a breather then clean up driver data */
191 msleep(100);
e8e9f696
JP		 192
193 kfree(adapter->vfinfo);
1cdd1ec8
GR		 194 adapter->vfinfo = NULL;
195
196 adapter->num_vfs = 0;
197 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
198}
199
7086400d
AD		 200static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
201{
202 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
203 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
204 schedule_work(&adapter->service_task);
205}
206
207static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
208{
209 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
210
211 /* flush memory to make sure state is correct before next watchog */
212 smp_mb__before_clear_bit();
213 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
214}
215
dcd79aeb
TI		 216struct ixgbe_reg_info {
217 u32 ofs;
218 char *name;
219};
220
221static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
222
223 /* General Registers */
224 {IXGBE_CTRL, "CTRL"},
225 {IXGBE_STATUS, "STATUS"},
226 {IXGBE_CTRL_EXT, "CTRL_EXT"},
227
228 /* Interrupt Registers */
229 {IXGBE_EICR, "EICR"},
230
231 /* RX Registers */
232 {IXGBE_SRRCTL(0), "SRRCTL"},
233 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
234 {IXGBE_RDLEN(0), "RDLEN"},
235 {IXGBE_RDH(0), "RDH"},
236 {IXGBE_RDT(0), "RDT"},
237 {IXGBE_RXDCTL(0), "RXDCTL"},
238 {IXGBE_RDBAL(0), "RDBAL"},
239 {IXGBE_RDBAH(0), "RDBAH"},
240
241 /* TX Registers */
242 {IXGBE_TDBAL(0), "TDBAL"},
243 {IXGBE_TDBAH(0), "TDBAH"},
244 {IXGBE_TDLEN(0), "TDLEN"},
245 {IXGBE_TDH(0), "TDH"},
246 {IXGBE_TDT(0), "TDT"},
247 {IXGBE_TXDCTL(0), "TXDCTL"},
248
249 /* List Terminator */
250 {}
251};
252
253
254/*
255 * ixgbe_regdump - register printout routine
256 */
257static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
258{
259 int i = 0, j = 0;
260 char rname[16];
261 u32 regs[64];
262
263 switch (reginfo->ofs) {
264 case IXGBE_SRRCTL(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
267 break;
268 case IXGBE_DCA_RXCTRL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
271 break;
272 case IXGBE_RDLEN(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
275 break;
276 case IXGBE_RDH(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
279 break;
280 case IXGBE_RDT(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
283 break;
284 case IXGBE_RXDCTL(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
287 break;
288 case IXGBE_RDBAL(0):
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
291 break;
292 case IXGBE_RDBAH(0):
293 for (i = 0; i < 64; i++)
294 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
295 break;
296 case IXGBE_TDBAL(0):
297 for (i = 0; i < 64; i++)
298 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
299 break;
300 case IXGBE_TDBAH(0):
301 for (i = 0; i < 64; i++)
302 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
303 break;
304 case IXGBE_TDLEN(0):
305 for (i = 0; i < 64; i++)
306 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
307 break;
308 case IXGBE_TDH(0):
309 for (i = 0; i < 64; i++)
310 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
311 break;
312 case IXGBE_TDT(0):
313 for (i = 0; i < 64; i++)
314 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
315 break;
316 case IXGBE_TXDCTL(0):
317 for (i = 0; i < 64; i++)
318 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
319 break;
320 default:
c7689578 321 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 322 IXGBE_READ_REG(hw, reginfo->ofs));
323 return;
324 }
325
326 for (i = 0; i < 8; i++) {
327 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 328 pr_err("%-15s", rname);
dcd79aeb 329 for (j = 0; j < 8; j++)
c7689578
JP		 330 pr_cont(" %08x", regs[i*8+j]);
331 pr_cont("\n");
dcd79aeb
TI		 332 }
333
334}
335
336/*
337 * ixgbe_dump - Print registers, tx-rings and rx-rings
338 */
339static void ixgbe_dump(struct ixgbe_adapter *adapter)
340{
341 struct net_device *netdev = adapter->netdev;
342 struct ixgbe_hw *hw = &adapter->hw;
343 struct ixgbe_reg_info *reginfo;
344 int n = 0;
345 struct ixgbe_ring *tx_ring;
346 struct ixgbe_tx_buffer *tx_buffer_info;
347 union ixgbe_adv_tx_desc *tx_desc;
348 struct my_u0 { u64 a; u64 b; } *u0;
349 struct ixgbe_ring *rx_ring;
350 union ixgbe_adv_rx_desc *rx_desc;
351 struct ixgbe_rx_buffer *rx_buffer_info;
352 u32 staterr;
353 int i = 0;
354
355 if (!netif_msg_hw(adapter))
356 return;
357
358 /* Print netdevice Info */
359 if (netdev) {
360 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 361 pr_info("Device Name state "
dcd79aeb 362 "trans_start last_rx\n");
c7689578
JP		 363 pr_info("%-15s %016lX %016lX %016lX\n",
364 netdev->name,
365 netdev->state,
366 netdev->trans_start,
367 netdev->last_rx);
dcd79aeb
TI		 368 }
369
370 /* Print Registers */
371 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 372 pr_info(" Register Name Value\n");
dcd79aeb
TI		 373 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
374 reginfo->name; reginfo++) {
375 ixgbe_regdump(hw, reginfo);
376 }
377
378 /* Print TX Ring Summary */
379 if (!netdev || !netif_running(netdev))
380 goto exit;
381
382 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 383 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
386 tx_buffer_info =
387 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 388 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 389 n, tx_ring->next_to_use, tx_ring->next_to_clean,
390 (u64)tx_buffer_info->dma,
391 tx_buffer_info->length,
392 tx_buffer_info->next_to_watch,
393 (u64)tx_buffer_info->time_stamp);
394 }
395
396 /* Print TX Rings */
397 if (!netif_msg_tx_done(adapter))
398 goto rx_ring_summary;
399
400 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
401
402 /* Transmit Descriptor Formats
403 *
404 * Advanced Transmit Descriptor
405 * +--------------------------------------------------------------+
406 * 0 | Buffer Address [63:0] |
407 * +--------------------------------------------------------------+
408 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
409 * +--------------------------------------------------------------+
410 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
411 */
412
413 for (n = 0; n < adapter->num_tx_queues; n++) {
414 tx_ring = adapter->tx_ring[n];
c7689578
JP		 415 pr_info("------------------------------------\n");
416 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
417 pr_info("------------------------------------\n");
418 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 419 "[PlPOIdStDDt Ln] [bi->dma ] "
420 "leng ntw timestamp bi->skb\n");
421
422 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 423 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 424 tx_buffer_info = &tx_ring->tx_buffer_info[i];
425 u0 = (struct my_u0 *)tx_desc;
c7689578 426 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 427 " %04X %p %016llX %p", i,
dcd79aeb
TI		 428 le64_to_cpu(u0->a),
429 le64_to_cpu(u0->b),
430 (u64)tx_buffer_info->dma,
431 tx_buffer_info->length,
432 tx_buffer_info->next_to_watch,
433 (u64)tx_buffer_info->time_stamp,
434 tx_buffer_info->skb);
435 if (i == tx_ring->next_to_use &&
436 i == tx_ring->next_to_clean)
c7689578 437 pr_cont(" NTC/U\n");
dcd79aeb 438 else if (i == tx_ring->next_to_use)
c7689578 439 pr_cont(" NTU\n");
dcd79aeb 440 else if (i == tx_ring->next_to_clean)
c7689578 441 pr_cont(" NTC\n");
dcd79aeb 442 else
c7689578 443 pr_cont("\n");
dcd79aeb
TI		 444
445 if (netif_msg_pktdata(adapter) &&
446 tx_buffer_info->dma != 0)
447 print_hex_dump(KERN_INFO, "",
448 DUMP_PREFIX_ADDRESS, 16, 1,
449 phys_to_virt(tx_buffer_info->dma),
450 tx_buffer_info->length, true);
451 }
452 }
453
454 /* Print RX Rings Summary */
455rx_ring_summary:
456 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 457 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 458 for (n = 0; n < adapter->num_rx_queues; n++) {
459 rx_ring = adapter->rx_ring[n];
c7689578
JP		 460 pr_info("%5d %5X %5X\n",
461 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 462 }
463
464 /* Print RX Rings */
465 if (!netif_msg_rx_status(adapter))
466 goto exit;
467
468 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
469
470 /* Advanced Receive Descriptor (Read) Format
471 * 63 1 0
472 * +-----------------------------------------------------+
473 * 0 | Packet Buffer Address [63:1] |A0/NSE|
474 * +----------------------------------------------+------+
475 * 8 | Header Buffer Address [63:1] | DD |
476 * +-----------------------------------------------------+
477 *
478 *
479 * Advanced Receive Descriptor (Write-Back) Format
480 *
481 * 63 48 47 32 31 30 21 20 16 15 4 3 0
482 * +------------------------------------------------------+
483 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
484 * | Checksum Ident | | | | Type | Type |
485 * +------------------------------------------------------+
486 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
487 * +------------------------------------------------------+
488 * 63 48 47 32 31 20 19 0
489 */
490 for (n = 0; n < adapter->num_rx_queues; n++) {
491 rx_ring = adapter->rx_ring[n];
c7689578
JP		 492 pr_info("------------------------------------\n");
493 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
494 pr_info("------------------------------------\n");
495 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 496 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
497 "<-- Adv Rx Read format\n");
c7689578 498 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 499 "[vl er S cks ln] ---------------- [bi->skb] "
500 "<-- Adv Rx Write-Back format\n");
501
502 for (i = 0; i < rx_ring->count; i++) {
503 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 504 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 505 u0 = (struct my_u0 *)rx_desc;
506 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
507 if (staterr & IXGBE_RXD_STAT_DD) {
508 /* Descriptor Done */
c7689578 509 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 510 "%016llX ---------------- %p", i,
511 le64_to_cpu(u0->a),
512 le64_to_cpu(u0->b),
513 rx_buffer_info->skb);
514 } else {
c7689578 515 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 516 "%016llX %016llX %p", i,
517 le64_to_cpu(u0->a),
518 le64_to_cpu(u0->b),
519 (u64)rx_buffer_info->dma,
520 rx_buffer_info->skb);
521
522 if (netif_msg_pktdata(adapter)) {
523 print_hex_dump(KERN_INFO, "",
524 DUMP_PREFIX_ADDRESS, 16, 1,
525 phys_to_virt(rx_buffer_info->dma),
526 rx_ring->rx_buf_len, true);
527
528 if (rx_ring->rx_buf_len
529 < IXGBE_RXBUFFER_2048)
530 print_hex_dump(KERN_INFO, "",
531 DUMP_PREFIX_ADDRESS, 16, 1,
532 phys_to_virt(
533 rx_buffer_info->page_dma +
534 rx_buffer_info->page_offset
535 ),
536 PAGE_SIZE/2, true);
537 }
538 }
539
540 if (i == rx_ring->next_to_use)
c7689578 541 pr_cont(" NTU\n");
dcd79aeb 542 else if (i == rx_ring->next_to_clean)
c7689578 543 pr_cont(" NTC\n");
dcd79aeb 544 else
c7689578 545 pr_cont("\n");
dcd79aeb
TI		 546
547 }
548 }
549
550exit:
551 return;
552}
553
5eba3699
AV		 554static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
555{
556 u32 ctrl_ext;
557
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 562}
563
564static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
565{
566 u32 ctrl_ext;
567
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 572}
9a799d71 573
e8e26350
PW		 574/*
575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
580 *
581 */
582static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 583 u8 queue, u8 msix_vector)
9a799d71
AK		 584{
585 u32 ivar, index;
e8e26350
PW		 586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
590 if (direction == -1)
591 direction = 0;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
597 break;
598 case ixgbe_mac_82599EB:
b93a2226 599 case ixgbe_mac_X540:
e8e26350
PW		 600 if (direction == -1) {
601 /* other causes */
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
608 break;
609 } else {
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
617 break;
618 }
619 default:
620 break;
621 }
9a799d71
AK		 622}
623
fe49f04a 624static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 625 u64 qmask)
fe49f04a
AD		 626{
627 u32 mask;
628
bd508178
AD		 629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
fe49f04a
AD		 631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 633 break;
634 case ixgbe_mac_82599EB:
b93a2226 635 case ixgbe_mac_X540:
fe49f04a
AD		 636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 640 break;
641 default:
642 break;
fe49f04a
AD		 643 }
644}
645
d3d00239
AD		 646static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
647 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 648{
d3d00239
AD		 649 if (tx_buffer->dma) {
650 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
651 dma_unmap_page(ring->dev,
652 tx_buffer->dma,
653 tx_buffer->length,
654 DMA_TO_DEVICE);
e5a43549 655 else
d3d00239
AD		 656 dma_unmap_single(ring->dev,
657 tx_buffer->dma,
658 tx_buffer->length,
659 DMA_TO_DEVICE);
e5a43549 660 }
d3d00239
AD		 661 tx_buffer->dma = 0;
662}
663
664void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
665 struct ixgbe_tx_buffer *tx_buffer_info)
666{
667 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
668 if (tx_buffer_info->skb)
9a799d71 669 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 670 tx_buffer_info->skb = NULL;
9a799d71
AK		 671 /* tx_buffer_info must be completely set up in the transmit path */
672}
673
c84d324c
JF		 674static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
675{
676 struct ixgbe_hw *hw = &adapter->hw;
677 struct ixgbe_hw_stats *hwstats = &adapter->stats;
678 u32 data = 0;
679 u32 xoff[8] = {0};
680 int i;
681
682 if ((hw->fc.current_mode == ixgbe_fc_full) ||
683 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
684 switch (hw->mac.type) {
685 case ixgbe_mac_82598EB:
686 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 687 break;
688 default:
c84d324c
JF		 689 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
690 }
691 hwstats->lxoffrxc += data;
692
693 /* refill credits (no tx hang) if we received xoff */
694 if (!data)
695 return;
696
697 for (i = 0; i < adapter->num_tx_queues; i++)
698 clear_bit(__IXGBE_HANG_CHECK_ARMED,
699 &adapter->tx_ring[i]->state);
700 return;
701 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
702 return;
703
704 /* update stats for each tc, only valid with PFC enabled */
705 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
706 switch (hw->mac.type) {
707 case ixgbe_mac_82598EB:
708 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 709 break;
c84d324c
JF		 710 default:
711 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 712 }
c84d324c
JF		 713 hwstats->pxoffrxc[i] += xoff[i];
714 }
715
716 /* disarm tx queues that have received xoff frames */
717 for (i = 0; i < adapter->num_tx_queues; i++) {
718 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 719 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 720
721 if (xoff[tc])
722 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 723 }
26f23d82
YZ		 724}
725
c84d324c 726static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 727{
c84d324c
JF		 728 return ring->tx_stats.completed;
729}
730
731static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
732{
733 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 734 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 735
c84d324c
JF		 736 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
737 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
738
739 if (head != tail)
740 return (head < tail) ?
741 tail - head : (tail + ring->count - head);
742
743 return 0;
744}
745
746static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
747{
748 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
749 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
750 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
751 bool ret = false;
752
7d637bcc 753 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 754
755 /*
756 * Check for a hung queue, but be thorough. This verifies
757 * that a transmit has been completed since the previous
758 * check AND there is at least one packet pending. The
759 * ARMED bit is set to indicate a potential hang. The
760 * bit is cleared if a pause frame is received to remove
761 * false hang detection due to PFC or 802.3x frames. By
762 * requiring this to fail twice we avoid races with
763 * pfc clearing the ARMED bit and conditions where we
764 * run the check_tx_hang logic with a transmit completion
765 * pending but without time to complete it yet.
766 */
767 if ((tx_done_old == tx_done) && tx_pending) {
768 /* make sure it is true for two checks in a row */
769 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
770 &tx_ring->state);
771 } else {
772 /* update completed stats and continue */
773 tx_ring->tx_stats.tx_done_old = tx_done;
774 /* reset the countdown */
775 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 776 }
777
c84d324c 778 return ret;
9a799d71
AK		 779}
780
c83c6cbd
AD		 781/**
782 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
783 * @adapter: driver private struct
784 **/
785static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
786{
787
788 /* Do the reset outside of interrupt context */
789 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
790 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
791 ixgbe_service_event_schedule(adapter);
792 }
793}
e01c31a5 794
9a799d71
AK		 795/**
796 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 797 * @q_vector: structure containing interrupt and ring information
e01c31a5 798 * @tx_ring: tx ring to clean
9a799d71 799 **/
fe49f04a 800static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 801 struct ixgbe_ring *tx_ring)
9a799d71 802{
fe49f04a 803 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 804 struct ixgbe_tx_buffer *tx_buffer;
805 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 806 unsigned int total_bytes = 0, total_packets = 0;
30065e63 807 u16 budget = q_vector->tx.work_limit;
d3d00239 808 u16 i = tx_ring->next_to_clean;
9a799d71 809
d3d00239
AD		 810 tx_buffer = &tx_ring->tx_buffer_info[i];
811 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 812
30065e63 813 for (; budget; budget--) {
d3d00239
AD		 814 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
815
816 /* if next_to_watch is not set then there is no work pending */
817 if (!eop_desc)
818 break;
819
820 /* if DD is not set pending work has not been completed */
821 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
822 break;
8ad494b0 823
d3d00239
AD		 824 /* count the packet as being completed */
825 tx_ring->tx_stats.completed++;
826
827 /* clear next_to_watch to prevent false hangs */
828 tx_buffer->next_to_watch = NULL;
8ad494b0 829
d3d00239
AD		 830 /* prevent any other reads prior to eop_desc being verified */
831 rmb();
832
833 do {
834 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 835 tx_desc->wb.status = 0;
d3d00239
AD		 836 if (likely(tx_desc == eop_desc)) {
837 eop_desc = NULL;
838 dev_kfree_skb_any(tx_buffer->skb);
839 tx_buffer->skb = NULL;
840
841 total_bytes += tx_buffer->bytecount;
842 total_packets += tx_buffer->gso_segs;
843 }
9a799d71 844
d3d00239
AD		 845 tx_buffer++;
846 tx_desc++;
8ad494b0 847 i++;
d3d00239 848 if (unlikely(i == tx_ring->count)) {
8ad494b0 849 i = 0;
e01c31a5 850
d3d00239
AD		 851 tx_buffer = tx_ring->tx_buffer_info;
852 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 853 }
e01c31a5 854
d3d00239 855 } while (eop_desc);
12207e49
PWJ		 856 }
857
9a799d71 858 tx_ring->next_to_clean = i;
d3d00239 859 u64_stats_update_begin(&tx_ring->syncp);
b953799e 860 tx_ring->stats.bytes += total_bytes;
bd198058 861 tx_ring->stats.packets += total_packets;
d3d00239 862 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 863 q_vector->tx.total_bytes += total_bytes;
864 q_vector->tx.total_packets += total_packets;
b953799e 865
c84d324c
JF		 866 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
867 /* schedule immediate reset if we believe we hung */
868 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 869 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 870 e_err(drv, "Detected Tx Unit Hang\n"
871 " Tx Queue <%d>\n"
872 " TDH, TDT <%x>, <%x>\n"
873 " next_to_use <%x>\n"
874 " next_to_clean <%x>\n"
875 "tx_buffer_info[next_to_clean]\n"
876 " time_stamp <%lx>\n"
877 " jiffies <%lx>\n",
878 tx_ring->queue_index,
879 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
880 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 881 tx_ring->next_to_use, i,
882 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 883
884 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
885
886 e_info(probe,
887 "tx hang %d detected on queue %d, resetting adapter\n",
888 adapter->tx_timeout_count + 1, tx_ring->queue_index);
889
b953799e 890 /* schedule immediate reset if we believe we hung */
c83c6cbd 891 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 892
893 /* the adapter is about to reset, no point in enabling stuff */
30065e63 894 return budget;
b953799e 895 }
9a799d71 896
e092be60 897#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 898 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 899 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 900 /* Make sure that anybody stopping the queue after this
901 * sees the new next_to_clean.
902 */
903 smp_mb();
fc77dc3c 904 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 905 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 906 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 907 ++tx_ring->tx_stats.restart_queue;
30eba97a 908 }
e092be60 909 }
9a799d71 910
30065e63 911 return budget;
9a799d71
AK		 912}
913
5dd2d332 914#ifdef CONFIG_IXGBE_DCA
bd0362dd 915static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 916 struct ixgbe_ring *rx_ring,
917 int cpu)
bd0362dd 918{
33cf09c9 919 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 920 u32 rxctrl;
33cf09c9
AD		 921 u8 reg_idx = rx_ring->reg_idx;
922
923 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
924 switch (hw->mac.type) {
925 case ixgbe_mac_82598EB:
926 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
927 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
928 break;
929 case ixgbe_mac_82599EB:
b93a2226 930 case ixgbe_mac_X540:
33cf09c9
AD		 931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
932 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
933 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
934 break;
935 default:
936 break;
bd0362dd 937 }
33cf09c9
AD		 938 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
939 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
940 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 941 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 942}
943
944static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 945 struct ixgbe_ring *tx_ring,
946 int cpu)
bd0362dd 947{
33cf09c9 948 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 949 u32 txctrl;
33cf09c9
AD		 950 u8 reg_idx = tx_ring->reg_idx;
951
952 switch (hw->mac.type) {
953 case ixgbe_mac_82598EB:
954 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
955 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
956 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
957 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 958 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
959 break;
960 case ixgbe_mac_82599EB:
b93a2226 961 case ixgbe_mac_X540:
33cf09c9
AD		 962 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
963 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
964 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
965 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
966 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 967 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
968 break;
969 default:
970 break;
971 }
972}
973
974static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
975{
976 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 977 struct ixgbe_ring *ring;
bd0362dd 978 int cpu = get_cpu();
bd0362dd 979
33cf09c9
AD		 980 if (q_vector->cpu == cpu)
981 goto out_no_update;
982
efe3d3c8
AD		 983 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
984 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 985
efe3d3c8
AD		 986 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
987 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 988
989 q_vector->cpu = cpu;
990out_no_update:
bd0362dd
JC		 991 put_cpu();
992}
993
994static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
995{
33cf09c9 996 int num_q_vectors;
bd0362dd
JC		 997 int i;
998
999 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000 return;
1001
e35ec126
AD		 1002 /* always use CB2 mode, difference is masked in the CB driver */
1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
33cf09c9
AD		 1005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1006 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1007 else
1008 num_q_vectors = 1;
1009
1010 for (i = 0; i < num_q_vectors; i++) {
1011 adapter->q_vector[i]->cpu = -1;
1012 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1013 }
1014}
1015
1016static int __ixgbe_notify_dca(struct device *dev, void *data)
1017{
c60fbb00 1018 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1019 unsigned long event = *(unsigned long *)data;
1020
2a72c31e 1021 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1022 return 0;
1023
bd0362dd
JC		 1024 switch (event) {
1025 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1026 /* if we're already enabled, don't do it again */
1027 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1028 break;
652f093f 1029 if (dca_add_requester(dev) == 0) {
96b0e0f6 1030 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1031 ixgbe_setup_dca(adapter);
1032 break;
1033 }
1034 /* Fall Through since DCA is disabled. */
1035 case DCA_PROVIDER_REMOVE:
1036 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1037 dca_remove_requester(dev);
1038 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1039 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1040 }
1041 break;
1042 }
1043
652f093f 1044 return 0;
bd0362dd 1045}
5dd2d332 1046#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 1047
1048static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1049 struct sk_buff *skb)
1050{
1051 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1052}
1053
ff886dfc
AD		 1054/**
1055 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1056 * @adapter: address of board private structure
1057 * @rx_desc: advanced rx descriptor
1058 *
1059 * Returns : true if it is FCoE pkt
1060 */
1061static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1062 union ixgbe_adv_rx_desc *rx_desc)
1063{
1064 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1065
1066 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1067 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1068 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1069 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1070}
1071
9a799d71
AK		 1072/**
1073 * ixgbe_receive_skb - Send a completed packet up the stack
1074 * @adapter: board private structure
1075 * @skb: packet to send up
177db6ff
MC		 1076 * @status: hardware indication of status of receive
1077 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1078 * @rx_desc: rx descriptor
9a799d71 1079 **/
78b6f4ce 1080static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1081 struct sk_buff *skb, u8 status,
1082 struct ixgbe_ring *ring,
1083 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1084{
78b6f4ce
HX		 1085 struct ixgbe_adapter *adapter = q_vector->adapter;
1086 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1087 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1088 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1089
f62bbb5e
JG		 1090 if (is_vlan && (tag & VLAN_VID_MASK))
1091 __vlan_hwaccel_put_tag(skb, tag);
1092
1093 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1094 napi_gro_receive(napi, skb);
1095 else
1096 netif_rx(skb);
9a799d71
AK		 1097}
1098
e59bd25d
AV		 1099/**
1100 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1101 * @adapter: address of board private structure
1102 * @status_err: hardware indication of status of receive
1103 * @skb: skb currently being received and modified
ff886dfc 1104 * @status_err: status error value of last descriptor in packet
e59bd25d 1105 **/
9a799d71 1106static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1107 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1108 struct sk_buff *skb,
1109 u32 status_err)
9a799d71 1110{
ff886dfc 1111 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1112
712744be
JB		 1113 /* Rx csum disabled */
1114 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1115 return;
e59bd25d
AV		 1116
1117 /* if IP and error */
1118 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1119 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1120 adapter->hw_csum_rx_error++;
1121 return;
1122 }
e59bd25d
AV		 1123
1124 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1125 return;
1126
1127 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1128 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1129
1130 /*
1131 * 82599 errata, UDP frames with a 0 checksum can be marked as
1132 * checksum errors.
1133 */
1134 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1135 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1136 return;
1137
e59bd25d
AV		 1138 adapter->hw_csum_rx_error++;
1139 return;
1140 }
1141
9a799d71 1142 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1143 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1144}
1145
84ea2591 1146static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1147{
1148 /*
1149 * Force memory writes to complete before letting h/w
1150 * know there are new descriptors to fetch. (Only
1151 * applicable for weak-ordered memory model archs,
1152 * such as IA-64).
1153 */
1154 wmb();
84ea2591 1155 writel(val, rx_ring->tail);
e8e26350
PW		 1156}
1157
9a799d71
AK		 1158/**
1159 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1160 * @rx_ring: ring to place buffers on
1161 * @cleaned_count: number of buffers to replace
9a799d71 1162 **/
fc77dc3c 1163void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1164{
9a799d71 1165 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1166 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1167 struct sk_buff *skb;
1168 u16 i = rx_ring->next_to_use;
9a799d71 1169
fc77dc3c
AD		 1170 /* do nothing if no valid netdev defined */
1171 if (!rx_ring->netdev)
1172 return;
1173
9a799d71 1174 while (cleaned_count--) {
31f05a2d 1175 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1176 bi = &rx_ring->rx_buffer_info[i];
1177 skb = bi->skb;
9a799d71 1178
d5f398ed 1179 if (!skb) {
fc77dc3c 1180 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1181 rx_ring->rx_buf_len);
9a799d71 1182 if (!skb) {
5b7da515 1183 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1184 goto no_buffers;
1185 }
d716a7d8
AD		 1186 /* initialize queue mapping */
1187 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1188 bi->skb = skb;
d716a7d8 1189 }
9a799d71 1190
d716a7d8 1191 if (!bi->dma) {
b6ec895e 1192 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1193 skb->data,
e8e9f696 1194 rx_ring->rx_buf_len,
1b507730 1195 DMA_FROM_DEVICE);
b6ec895e 1196 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1197 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1198 bi->dma = 0;
1199 goto no_buffers;
1200 }
9a799d71 1201 }
d5f398ed 1202
7d637bcc 1203 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1204 if (!bi->page) {
fc77dc3c 1205 bi->page = netdev_alloc_page(rx_ring->netdev);
d5f398ed 1206 if (!bi->page) {
5b7da515 1207 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1208 goto no_buffers;
1209 }
1210 }
1211
1212 if (!bi->page_dma) {
1213 /* use a half page if we're re-using */
1214 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1215 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1216 bi->page,
1217 bi->page_offset,
1218 PAGE_SIZE / 2,
1219 DMA_FROM_DEVICE);
b6ec895e 1220 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1221 bi->page_dma)) {
5b7da515 1222 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1223 bi->page_dma = 0;
1224 goto no_buffers;
1225 }
1226 }
1227
1228 /* Refresh the desc even if buffer_addrs didn't change
1229 * because each write-back erases this info. */
3a581073
JB		 1230 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1231 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1232 } else {
3a581073 1233 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1234 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1235 }
1236
1237 i++;
1238 if (i == rx_ring->count)
1239 i = 0;
9a799d71 1240 }
7c6e0a43 1241
9a799d71
AK		 1242no_buffers:
1243 if (rx_ring->next_to_use != i) {
1244 rx_ring->next_to_use = i;
84ea2591 1245 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1246 }
1247}
1248
c267fc16 1249static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1250{
c267fc16
AD		 1251 /* HW will not DMA in data larger than the given buffer, even if it
1252 * parses the (NFS, of course) header to be larger. In that case, it
1253 * fills the header buffer and spills the rest into the page.
1254 */
1255 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1256 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1257 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1258 if (hlen > IXGBE_RX_HDR_SIZE)
1259 hlen = IXGBE_RX_HDR_SIZE;
1260 return hlen;
7c6e0a43
JB		 1261}
1262
f8212f97
AD		 1263/**
1264 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1265 * @skb: pointer to the last skb in the rsc queue
1266 *
1267 * This function changes a queue full of hw rsc buffers into a completed
1268 * packet. It uses the ->prev pointers to find the first packet and then
1269 * turns it into the frag list owner.
1270 **/
aa80175a 1271static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1272{
1273 unsigned int frag_list_size = 0;
aa80175a 1274 unsigned int skb_cnt = 1;
f8212f97
AD		 1275
1276 while (skb->prev) {
1277 struct sk_buff *prev = skb->prev;
1278 frag_list_size += skb->len;
1279 skb->prev = NULL;
1280 skb = prev;
aa80175a 1281 skb_cnt++;
f8212f97
AD		 1282 }
1283
1284 skb_shinfo(skb)->frag_list = skb->next;
1285 skb->next = NULL;
1286 skb->len += frag_list_size;
1287 skb->data_len += frag_list_size;
1288 skb->truesize += frag_list_size;
aa80175a
AD		 1289 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1290
f8212f97
AD		 1291 return skb;
1292}
1293
aa80175a
AD		 1294static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1295{
1296 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1297 IXGBE_RXDADV_RSCCNT_MASK);
1298}
43634e82 1299
c267fc16 1300static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1301 struct ixgbe_ring *rx_ring,
1302 int *work_done, int work_to_do)
9a799d71 1303{
78b6f4ce 1304 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1305 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1306 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1307 struct sk_buff *skb;
d2f4fbe2 1308 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1309 const int current_node = numa_node_id();
3d8fd385
YZ		 1310#ifdef IXGBE_FCOE
1311 int ddp_bytes = 0;
1312#endif /* IXGBE_FCOE */
c267fc16
AD		 1313 u32 staterr;
1314 u16 i;
1315 u16 cleaned_count = 0;
aa80175a 1316 bool pkt_is_rsc = false;
9a799d71
AK		 1317
1318 i = rx_ring->next_to_clean;
31f05a2d 1319 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1320 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1321
1322 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1323 u32 upper_len = 0;
9a799d71 1324
3c945e5b 1325 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1326
c267fc16
AD		 1327 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1328
9a799d71 1329 skb = rx_buffer_info->skb;
9a799d71 1330 rx_buffer_info->skb = NULL;
c267fc16 1331 prefetch(skb->data);
9a799d71 1332
c267fc16 1333 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1334 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16
AD		 1335
1336 /* if this is a skb from previous receive DMA will be 0 */
21fa4e66 1337 if (rx_buffer_info->dma) {
c267fc16 1338 u16 hlen;
aa80175a 1339 if (pkt_is_rsc &&
c267fc16
AD		 1340 !(staterr & IXGBE_RXD_STAT_EOP) &&
1341 !skb->prev) {
43634e82
MC		 1342 /*
1343 * When HWRSC is enabled, delay unmapping
1344 * of the first packet. It carries the
1345 * header information, HW may still
1346 * access the header after the writeback.
1347 * Only unmap it when EOP is reached
1348 */
e8171aaa 1349 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1350 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1351 } else {
b6ec895e 1352 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1353 rx_buffer_info->dma,
1354 rx_ring->rx_buf_len,
1355 DMA_FROM_DEVICE);
e8171aaa 1356 }
4f57ca6e 1357 rx_buffer_info->dma = 0;
c267fc16
AD		 1358
1359 if (ring_is_ps_enabled(rx_ring)) {
1360 hlen = ixgbe_get_hlen(rx_desc);
1361 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1362 } else {
1363 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1364 }
1365
1366 skb_put(skb, hlen);
1367 } else {
1368 /* assume packet split since header is unmapped */
1369 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1370 }
1371
1372 if (upper_len) {
b6ec895e
AD		 1373 dma_unmap_page(rx_ring->dev,
1374 rx_buffer_info->page_dma,
1375 PAGE_SIZE / 2,
1376 DMA_FROM_DEVICE);
9a799d71
AK		 1377 rx_buffer_info->page_dma = 0;
1378 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1379 rx_buffer_info->page,
1380 rx_buffer_info->page_offset,
1381 upper_len);
762f4c57 1382
c267fc16
AD		 1383 if ((page_count(rx_buffer_info->page) == 1) &&
1384 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1385 get_page(rx_buffer_info->page);
c267fc16
AD		 1386 else
1387 rx_buffer_info->page = NULL;
9a799d71
AK		 1388
1389 skb->len += upper_len;
1390 skb->data_len += upper_len;
1391 skb->truesize += upper_len;
1392 }
1393
1394 i++;
1395 if (i == rx_ring->count)
1396 i = 0;
9a799d71 1397
31f05a2d 1398 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1399 prefetch(next_rxd);
9a799d71 1400 cleaned_count++;
f8212f97 1401
aa80175a 1402 if (pkt_is_rsc) {
f8212f97
AD		 1403 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1404 IXGBE_RXDADV_NEXTP_SHIFT;
1405 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1406 } else {
1407 next_buffer = &rx_ring->rx_buffer_info[i];
1408 }
1409
c267fc16 1410 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1411 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1412 rx_buffer_info->skb = next_buffer->skb;
1413 rx_buffer_info->dma = next_buffer->dma;
1414 next_buffer->skb = skb;
1415 next_buffer->dma = 0;
1416 } else {
1417 skb->next = next_buffer->skb;
1418 skb->next->prev = skb;
1419 }
5b7da515 1420 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1421 goto next_desc;
1422 }
1423
aa80175a
AD		 1424 if (skb->prev) {
1425 skb = ixgbe_transform_rsc_queue(skb);
1426 /* if we got here without RSC the packet is invalid */
1427 if (!pkt_is_rsc) {
1428 __pskb_trim(skb, 0);
1429 rx_buffer_info->skb = skb;
1430 goto next_desc;
1431 }
1432 }
c267fc16
AD		 1433
1434 if (ring_is_rsc_enabled(rx_ring)) {
1435 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1436 dma_unmap_single(rx_ring->dev,
1437 IXGBE_RSC_CB(skb)->dma,
1438 rx_ring->rx_buf_len,
1439 DMA_FROM_DEVICE);
1440 IXGBE_RSC_CB(skb)->dma = 0;
1441 IXGBE_RSC_CB(skb)->delay_unmap = false;
1442 }
aa80175a
AD		 1443 }
1444 if (pkt_is_rsc) {
c267fc16
AD		 1445 if (ring_is_ps_enabled(rx_ring))
1446 rx_ring->rx_stats.rsc_count +=
aa80175a 1447 skb_shinfo(skb)->nr_frags;
c267fc16 1448 else
aa80175a
AD		 1449 rx_ring->rx_stats.rsc_count +=
1450 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1451 rx_ring->rx_stats.rsc_flush++;
1452 }
1453
1454 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1455 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1456 dev_kfree_skb_any(skb);
9a799d71
AK		 1457 goto next_desc;
1458 }
1459
ff886dfc 1460 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1461 if (adapter->netdev->features & NETIF_F_RXHASH)
1462 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1463
1464 /* probably a little skewed due to removing CRC */
1465 total_rx_bytes += skb->len;
1466 total_rx_packets++;
1467
fc77dc3c 1468 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1469#ifdef IXGBE_FCOE
1470 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1471 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1472 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1473 staterr);
63d635b2
AD		 1474 if (!ddp_bytes) {
1475 dev_kfree_skb_any(skb);
332d4a7d 1476 goto next_desc;
63d635b2 1477 }
3d8fd385 1478 }
332d4a7d 1479#endif /* IXGBE_FCOE */
fdaff1ce 1480 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71
AK		 1481
1482next_desc:
1483 rx_desc->wb.upper.status_error = 0;
1484
c267fc16
AD		 1485 (*work_done)++;
1486 if (*work_done >= work_to_do)
1487 break;
1488
9a799d71
AK		 1489 /* return some buffers to hardware, one at a time is too slow */
1490 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1491 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1492 cleaned_count = 0;
1493 }
1494
1495 /* use prefetched values */
1496 rx_desc = next_rxd;
9a799d71 1497 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1498 }
1499
9a799d71 1500 rx_ring->next_to_clean = i;
7d4987de 1501 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1502
1503 if (cleaned_count)
fc77dc3c 1504 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1505
3d8fd385
YZ		 1506#ifdef IXGBE_FCOE
1507 /* include DDPed FCoE data */
1508 if (ddp_bytes > 0) {
1509 unsigned int mss;
1510
fc77dc3c 1511 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1512 sizeof(struct fc_frame_header) -
1513 sizeof(struct fcoe_crc_eof);
1514 if (mss > 512)
1515 mss &= ~511;
1516 total_rx_bytes += ddp_bytes;
1517 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1518 }
1519#endif /* IXGBE_FCOE */
1520
c267fc16
AD		 1521 u64_stats_update_begin(&rx_ring->syncp);
1522 rx_ring->stats.packets += total_rx_packets;
1523 rx_ring->stats.bytes += total_rx_bytes;
1524 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1525 q_vector->rx.total_packets += total_rx_packets;
1526 q_vector->rx.total_bytes += total_rx_bytes;
9a799d71
AK		 1527}
1528
021230d4 1529static int ixgbe_clean_rxonly(struct napi_struct *, int);
9a799d71
AK		 1530/**
1531 * ixgbe_configure_msix - Configure MSI-X hardware
1532 * @adapter: board private structure
1533 *
1534 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1535 * interrupts.
1536 **/
1537static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1538{
021230d4 1539 struct ixgbe_q_vector *q_vector;
efe3d3c8 1540 int q_vectors, v_idx;
021230d4 1541 u32 mask;
9a799d71 1542
021230d4 1543 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1544
4df10466
JB		 1545 /*
1546 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1547 * corresponding register.
1548 */
1549 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1550 struct ixgbe_ring *ring;
7a921c93 1551 q_vector = adapter->q_vector[v_idx];
021230d4 1552
efe3d3c8
AD		 1553 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1554 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1555
1556 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1557 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1558
1559 if (q_vector->tx.ring && !q_vector->rx.ring)
f7554a2b
NS		 1560 /* tx only */
1561 q_vector->eitr = adapter->tx_eitr_param;
efe3d3c8 1562 else if (q_vector->rx.ring)
f7554a2b
NS		 1563 /* rx or mixed */
1564 q_vector->eitr = adapter->rx_eitr_param;
021230d4 1565
fe49f04a 1566 ixgbe_write_eitr(q_vector);
03ecf91a
AD		 1567 /* If ATR is enabled, set interrupt affinity */
1568 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
b25ebfd2
PW		 1569 /*
1570 * Allocate the affinity_hint cpumask, assign the mask
1571 * for this vector, and set our affinity_hint for
1572 * this irq.
1573 */
1574 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1575 GFP_KERNEL))
1576 return;
1577 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1578 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1579 q_vector->affinity_mask);
1580 }
9a799d71
AK		 1581 }
1582
bd508178
AD		 1583 switch (adapter->hw.mac.type) {
1584 case ixgbe_mac_82598EB:
e8e26350 1585 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1586 v_idx);
bd508178
AD		 1587 break;
1588 case ixgbe_mac_82599EB:
b93a2226 1589 case ixgbe_mac_X540:
e8e26350 1590 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178
AD		 1591 break;
1592
1593 default:
1594 break;
1595 }
021230d4
AV		 1596 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1597
41fb9248 1598 /* set up to autoclear timer, and the vectors */
021230d4 1599 mask = IXGBE_EIMS_ENABLE_MASK;
1cdd1ec8
GR		 1600 if (adapter->num_vfs)
1601 mask &= ~(IXGBE_EIMS_OTHER |
1602 IXGBE_EIMS_MAILBOX |
1603 IXGBE_EIMS_LSC);
1604 else
1605 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
021230d4 1606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1607}
1608
f494e8fa
AV		 1609enum latency_range {
1610 lowest_latency = 0,
1611 low_latency = 1,
1612 bulk_latency = 2,
1613 latency_invalid = 255
1614};
1615
1616/**
1617 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1618 * @q_vector: structure containing interrupt and ring information
1619 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1620 *
1621 * Stores a new ITR value based on packets and byte
1622 * counts during the last interrupt. The advantage of per interrupt
1623 * computation is faster updates and more accurate ITR for the current
1624 * traffic pattern. Constants in this function were computed
1625 * based on theoretical maximum wire speed and thresholds were set based
1626 * on testing data as well as attempting to minimize response time
1627 * while increasing bulk throughput.
1628 * this functionality is controlled by the InterruptThrottleRate module
1629 * parameter (see ixgbe_param.c)
1630 **/
bd198058
AD		 1631static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1632 struct ixgbe_ring_container *ring_container)
f494e8fa 1633{
f494e8fa 1634 u64 bytes_perint;
bd198058
AD		 1635 struct ixgbe_adapter *adapter = q_vector->adapter;
1636 int bytes = ring_container->total_bytes;
1637 int packets = ring_container->total_packets;
1638 u32 timepassed_us;
1639 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1640
1641 if (packets == 0)
bd198058 1642 return;
f494e8fa
AV		 1643
1644 /* simple throttlerate management
1645 * 0-20MB/s lowest (100000 ints/s)
1646 * 20-100MB/s low (20000 ints/s)
1647 * 100-1249MB/s bulk (8000 ints/s)
1648 */
1649 /* what was last interrupt timeslice? */
bd198058 1650 timepassed_us = 1000000/q_vector->eitr;
f494e8fa
AV		 1651 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1652
1653 switch (itr_setting) {
1654 case lowest_latency:
1655 if (bytes_perint > adapter->eitr_low)
bd198058 1656 itr_setting = low_latency;
f494e8fa
AV		 1657 break;
1658 case low_latency:
1659 if (bytes_perint > adapter->eitr_high)
bd198058 1660 itr_setting = bulk_latency;
f494e8fa 1661 else if (bytes_perint <= adapter->eitr_low)
bd198058 1662 itr_setting = lowest_latency;
f494e8fa
AV		 1663 break;
1664 case bulk_latency:
1665 if (bytes_perint <= adapter->eitr_high)
bd198058 1666 itr_setting = low_latency;
f494e8fa
AV		 1667 break;
1668 }
1669
bd198058
AD		 1670 /* clear work counters since we have the values we need */
1671 ring_container->total_bytes = 0;
1672 ring_container->total_packets = 0;
1673
1674 /* write updated itr to ring container */
1675 ring_container->itr = itr_setting;
f494e8fa
AV		 1676}
1677
509ee935
JB		 1678/**
1679 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1680 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1681 *
1682 * This function is made to be called by ethtool and by the driver
1683 * when it needs to update EITR registers at runtime. Hardware
1684 * specific quirks/differences are taken care of here.
1685 */
fe49f04a 1686void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1687{
fe49f04a 1688 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1689 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 1690 int v_idx = q_vector->v_idx;
1691 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1692
bd508178
AD		 1693 switch (adapter->hw.mac.type) {
1694 case ixgbe_mac_82598EB:
509ee935
JB		 1695 /* must write high and low 16 bits to reset counter */
1696 itr_reg |= (itr_reg << 16);
bd508178
AD		 1697 break;
1698 case ixgbe_mac_82599EB:
b93a2226 1699 case ixgbe_mac_X540:
f8d1dcaf 1700 /*
b93a2226 1701 * 82599 and X540 can support a value of zero, so allow it for
f8d1dcaf
JB		 1702 * max interrupt rate, but there is an errata where it can
1703 * not be zero with RSC
1704 */
1705 if (itr_reg == 8 &&
1706 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1707 itr_reg = 0;
1708
509ee935
JB		 1709 /*
1710 * set the WDIS bit to not clear the timer bits and cause an
1711 * immediate assertion of the interrupt
1712 */
1713 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1714 break;
1715 default:
1716 break;
509ee935
JB		 1717 }
1718 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1719}
1720
bd198058 1721static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1722{
bd198058
AD		 1723 u32 new_itr = q_vector->eitr;
1724 u8 current_itr;
f494e8fa 1725
bd198058
AD		 1726 ixgbe_update_itr(q_vector, &q_vector->tx);
1727 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1728
08c8833b 1729 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1730
1731 switch (current_itr) {
1732 /* counts and packets in update_itr are dependent on these numbers */
1733 case lowest_latency:
1734 new_itr = 100000;
1735 break;
1736 case low_latency:
1737 new_itr = 20000; /* aka hwitr = ~200 */
1738 break;
1739 case bulk_latency:
f494e8fa
AV		 1740 new_itr = 8000;
1741 break;
bd198058
AD		 1742 default:
1743 break;
f494e8fa
AV		 1744 }
1745
1746 if (new_itr != q_vector->eitr) {
fe49f04a 1747 /* do an exponential smoothing */
125601bf 1748 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
509ee935 1749
bd198058 1750 /* save the algorithm value here */
509ee935 1751 q_vector->eitr = new_itr;
fe49f04a
AD		 1752
1753 ixgbe_write_eitr(q_vector);
f494e8fa 1754 }
f494e8fa
AV		 1755}
1756
119fc60a 1757/**
f0f9778d
AD		 1758 * ixgbe_check_overtemp_subtask - check for over tempurature
1759 * @adapter: pointer to adapter
119fc60a 1760 **/
f0f9778d 1761static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1762{
119fc60a
MC		 1763 struct ixgbe_hw *hw = &adapter->hw;
1764 u32 eicr = adapter->interrupt_event;
1765
f0f9778d 1766 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1767 return;
1768
f0f9778d
AD		 1769 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1770 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1771 return;
1772
1773 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1774
7ca647bd 1775 switch (hw->device_id) {
f0f9778d
AD		 1776 case IXGBE_DEV_ID_82599_T3_LOM:
1777 /*
1778 * Since the warning interrupt is for both ports
1779 * we don't have to check if:
1780 * - This interrupt wasn't for our port.
1781 * - We may have missed the interrupt so always have to
1782 * check if we got a LSC
1783 */
1784 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1785 !(eicr & IXGBE_EICR_LSC))
1786 return;
1787
1788 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1789 u32 autoneg;
1790 bool link_up = false;
7ca647bd 1791
7ca647bd
JP		 1792 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1793
f0f9778d
AD		 1794 if (link_up)
1795 return;
1796 }
1797
1798 /* Check if this is not due to overtemp */
1799 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1800 return;
1801
1802 break;
7ca647bd
JP		 1803 default:
1804 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1805 return;
7ca647bd 1806 break;
119fc60a 1807 }
7ca647bd
JP		 1808 e_crit(drv,
1809 "Network adapter has been stopped because it has over heated. "
1810 "Restart the computer. If the problem persists, "
1811 "power off the system and replace the adapter\n");
f0f9778d
AD		 1812
1813 adapter->interrupt_event = 0;
119fc60a
MC		 1814}
1815
0befdb3e
JB		 1816static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1817{
1818 struct ixgbe_hw *hw = &adapter->hw;
1819
1820 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1821 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1822 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1823 /* write to clear the interrupt */
1824 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1825 }
1826}
cf8280ee 1827
e8e26350
PW		 1828static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1829{
1830 struct ixgbe_hw *hw = &adapter->hw;
1831
73c4b7cd
AD		 1832 if (eicr & IXGBE_EICR_GPI_SDP2) {
1833 /* Clear the interrupt */
1834 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1835 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1836 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1837 ixgbe_service_event_schedule(adapter);
1838 }
73c4b7cd
AD		 1839 }
1840
e8e26350
PW		 1841 if (eicr & IXGBE_EICR_GPI_SDP1) {
1842 /* Clear the interrupt */
1843 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1844 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1845 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1846 ixgbe_service_event_schedule(adapter);
1847 }
e8e26350
PW		 1848 }
1849}
1850
cf8280ee
JB		 1851static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1852{
1853 struct ixgbe_hw *hw = &adapter->hw;
1854
1855 adapter->lsc_int++;
1856 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1857 adapter->link_check_timeout = jiffies;
1858 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1859 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1860 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1861 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1862 }
1863}
1864
9a799d71
AK		 1865static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1866{
a65151ba 1867 struct ixgbe_adapter *adapter = data;
9a799d71 1868 struct ixgbe_hw *hw = &adapter->hw;
54037505
DS		 1869 u32 eicr;
1870
1871 /*
1872 * Workaround for Silicon errata. Use clear-by-write instead
1873 * of clear-by-read. Reading with EICS will return the
1874 * interrupt causes without clearing, which later be done
1875 * with the write to EICR.
1876 */
1877 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1878 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
9a799d71 1879
cf8280ee
JB		 1880 if (eicr & IXGBE_EICR_LSC)
1881 ixgbe_check_lsc(adapter);
d4f80882 1882
1cdd1ec8
GR		 1883 if (eicr & IXGBE_EICR_MAILBOX)
1884 ixgbe_msg_task(adapter);
1885
bd508178
AD		 1886 switch (hw->mac.type) {
1887 case ixgbe_mac_82599EB:
b93a2226 1888 case ixgbe_mac_X540:
c4cf55e5
PWJ		 1889 /* Handle Flow Director Full threshold interrupt */
1890 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1891 int reinit_count = 0;
c4cf55e5 1892 int i;
c4cf55e5 1893 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1894 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1895 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1896 &ring->state))
1897 reinit_count++;
1898 }
1899 if (reinit_count) {
1900 /* no more flow director interrupts until after init */
1901 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1902 eicr &= ~IXGBE_EICR_FLOW_DIR;
1903 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1904 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1905 }
1906 }
f0f9778d
AD		 1907 ixgbe_check_sfp_event(adapter, eicr);
1908 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1909 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1910 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1911 adapter->interrupt_event = eicr;
1912 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1913 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1914 }
1915 }
bd508178
AD		 1916 break;
1917 default:
1918 break;
c4cf55e5 1919 }
bd508178
AD		 1920
1921 ixgbe_check_fan_failure(adapter, eicr);
1922
7086400d 1923 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1924 if (!test_bit(__IXGBE_DOWN, &adapter->state))
7086400d
AD		 1925 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1926 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
9a799d71
AK		 1927
1928 return IRQ_HANDLED;
1929}
1930
fe49f04a
AD		 1931static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1932 u64 qmask)
1933{
1934 u32 mask;
bd508178 1935 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1936
bd508178
AD		 1937 switch (hw->mac.type) {
1938 case ixgbe_mac_82598EB:
fe49f04a 1939 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1940 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1941 break;
1942 case ixgbe_mac_82599EB:
b93a2226 1943 case ixgbe_mac_X540:
fe49f04a 1944 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1945 if (mask)
1946 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1947 mask = (qmask >> 32);
bd508178
AD		 1948 if (mask)
1949 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1950 break;
1951 default:
1952 break;
fe49f04a
AD		 1953 }
1954 /* skip the flush */
1955}
1956
1957static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1958 u64 qmask)
fe49f04a
AD		 1959{
1960 u32 mask;
bd508178 1961 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1962
bd508178
AD		 1963 switch (hw->mac.type) {
1964 case ixgbe_mac_82598EB:
fe49f04a 1965 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1966 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1967 break;
1968 case ixgbe_mac_82599EB:
b93a2226 1969 case ixgbe_mac_X540:
fe49f04a 1970 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1971 if (mask)
1972 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1973 mask = (qmask >> 32);
bd508178
AD		 1974 if (mask)
1975 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1976 break;
1977 default:
1978 break;
fe49f04a
AD		 1979 }
1980 /* skip the flush */
1981}
1982
9a799d71
AK		 1983static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1984{
021230d4 1985 struct ixgbe_q_vector *q_vector = data;
021230d4 1986
08c8833b 1987 if (!q_vector->tx.count)
021230d4
AV		 1988 return IRQ_HANDLED;
1989
9b471446 1990 /* EIAM disabled interrupts (on this vector) for us */
91281fd3
AD		 1991 napi_schedule(&q_vector->napi);
1992
9a799d71
AK		 1993 return IRQ_HANDLED;
1994}
1995
021230d4
AV		 1996/**
1997 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1998 * @irq: unused
1999 * @data: pointer to our q_vector struct for this interrupt vector
2000 **/
9a799d71
AK		 2001static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2002{
021230d4 2003 struct ixgbe_q_vector *q_vector = data;
30efa5a3 2004
08c8833b 2005 if (!q_vector->rx.count)
021230d4
AV		 2006 return IRQ_HANDLED;
2007
9b471446 2008 /* EIAM disabled interrupts (on this vector) for us */
288379f0 2009 napi_schedule(&q_vector->napi);
021230d4
AV		 2010
2011 return IRQ_HANDLED;
2012}
2013
2014static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2015{
91281fd3 2016 struct ixgbe_q_vector *q_vector = data;
91281fd3 2017
08c8833b 2018 if (!q_vector->tx.count && !q_vector->rx.count)
91281fd3
AD		 2019 return IRQ_HANDLED;
2020
9b471446 2021 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2022 napi_schedule(&q_vector->napi);
9a799d71 2023
9a799d71
AK		 2024 return IRQ_HANDLED;
2025}
2026
021230d4
AV		 2027/**
2028 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2029 * @napi: napi struct with our devices info in it
2030 * @budget: amount of work driver is allowed to do this pass, in packets
2031 *
f0848276
JB		 2032 * This function is optimized for cleaning one queue only on a single
2033 * q_vector!!!
021230d4 2034 **/
9a799d71
AK		 2035static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2036{
021230d4 2037 struct ixgbe_q_vector *q_vector =
e8e9f696 2038 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 2039 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71 2040 int work_done = 0;
9a799d71 2041
5dd2d332 2042#ifdef CONFIG_IXGBE_DCA
bd0362dd 2043 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2044 ixgbe_update_dca(q_vector);
bd0362dd 2045#endif
9a799d71 2046
efe3d3c8 2047 ixgbe_clean_rx_irq(q_vector, q_vector->rx.ring, &work_done, budget);
9a799d71 2048
021230d4
AV		 2049 /* If all Rx work done, exit the polling mode */
2050 if (work_done < budget) {
288379f0 2051 napi_complete(napi);
f7554a2b 2052 if (adapter->rx_itr_setting & 1)
bd198058 2053 ixgbe_set_itr(q_vector);
9a799d71 2054 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2055 ixgbe_irq_enable_queues(adapter,
e8e9f696 2056 ((u64)1 << q_vector->v_idx));
9a799d71
AK		 2057 }
2058
2059 return work_done;
2060}
2061
f0848276 2062/**
91281fd3 2063 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
f0848276
JB		 2064 * @napi: napi struct with our devices info in it
2065 * @budget: amount of work driver is allowed to do this pass, in packets
2066 *
2067 * This function will clean more than one rx queue associated with a
2068 * q_vector.
2069 **/
91281fd3 2070static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
f0848276
JB		 2071{
2072 struct ixgbe_q_vector *q_vector =
e8e9f696 2073 container_of(napi, struct ixgbe_q_vector, napi);
f0848276 2074 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8
AD		 2075 struct ixgbe_ring *ring;
2076 int work_done = 0;
2077 bool clean_complete = true;
91281fd3 2078
33cf09c9
AD		 2079#ifdef CONFIG_IXGBE_DCA
2080 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2081 ixgbe_update_dca(q_vector);
2082#endif
2083
efe3d3c8
AD		 2084 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
2085 clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
f0848276
JB		 2086
2087 /* attempt to distribute budget to each queue fairly, but don't allow
2088 * the budget to go below 1 because we'll exit polling */
08c8833b 2089 budget /= (q_vector->rx.count ?: 1);
f0848276 2090 budget = max(budget, 1);
efe3d3c8
AD		 2091
2092 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
91281fd3 2093 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
f0848276 2094
efe3d3c8
AD		 2095 if (!clean_complete)
2096 work_done = budget;
2097
f0848276 2098 /* If all Rx work done, exit the polling mode */
7f821875 2099 if (work_done < budget) {
288379f0 2100 napi_complete(napi);
f7554a2b 2101 if (adapter->rx_itr_setting & 1)
bd198058 2102 ixgbe_set_itr(q_vector);
f0848276 2103 if (!test_bit(__IXGBE_DOWN, &adapter->state))
fe49f04a 2104 ixgbe_irq_enable_queues(adapter,
e8e9f696 2105 ((u64)1 << q_vector->v_idx));
f0848276
JB		 2106 return 0;
2107 }
2108
2109 return work_done;
2110}
91281fd3
AD		 2111
2112/**
2113 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2114 * @napi: napi struct with our devices info in it
2115 * @budget: amount of work driver is allowed to do this pass, in packets
2116 *
2117 * This function is optimized for cleaning one queue only on a single
2118 * q_vector!!!
2119 **/
2120static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2121{
2122 struct ixgbe_q_vector *q_vector =
e8e9f696 2123 container_of(napi, struct ixgbe_q_vector, napi);
91281fd3 2124 struct ixgbe_adapter *adapter = q_vector->adapter;
91281fd3 2125
91281fd3
AD		 2126#ifdef CONFIG_IXGBE_DCA
2127 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
33cf09c9 2128 ixgbe_update_dca(q_vector);
91281fd3
AD		 2129#endif
2130
efe3d3c8
AD		 2131 if (!ixgbe_clean_tx_irq(q_vector, q_vector->tx.ring))
2132 return budget;
91281fd3 2133
f7554a2b 2134 /* If all Tx work done, exit the polling mode */
efe3d3c8
AD		 2135 napi_complete(napi);
2136 if (adapter->tx_itr_setting & 1)
2137 ixgbe_set_itr(q_vector);
2138 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2139 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
91281fd3 2140
efe3d3c8 2141 return 0;
91281fd3
AD		 2142}
2143
021230d4 2144static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2145 int r_idx)
021230d4 2146{
7a921c93 2147 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2148 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2149
2274543f 2150 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2151 rx_ring->next = q_vector->rx.ring;
2152 q_vector->rx.ring = rx_ring;
2153 q_vector->rx.count++;
021230d4
AV		 2154}
2155
2156static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2157 int t_idx)
021230d4 2158{
7a921c93 2159 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2160 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2161
2274543f 2162 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2163 tx_ring->next = q_vector->tx.ring;
2164 q_vector->tx.ring = tx_ring;
2165 q_vector->tx.count++;
bd198058 2166 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2167}
2168
9a799d71 2169/**
021230d4
AV		 2170 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2171 * @adapter: board private structure to initialize
9a799d71 2172 *
021230d4
AV		 2173 * This function maps descriptor rings to the queue-specific vectors
2174 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2175 * one vector per ring/queue, but on a constrained vector budget, we
2176 * group the rings as "efficiently" as possible. You would add new
2177 * mapping configurations in here.
9a799d71 2178 **/
d0759ebb 2179static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2180{
d0759ebb 2181 int q_vectors;
021230d4
AV		 2182 int v_start = 0;
2183 int rxr_idx = 0, txr_idx = 0;
2184 int rxr_remaining = adapter->num_rx_queues;
2185 int txr_remaining = adapter->num_tx_queues;
2186 int i, j;
2187 int rqpv, tqpv;
2188 int err = 0;
2189
2190 /* No mapping required if MSI-X is disabled. */
2191 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2192 goto out;
9a799d71 2193
d0759ebb
AD		 2194 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2195
021230d4
AV		 2196 /*
2197 * The ideal configuration...
2198 * We have enough vectors to map one per queue.
2199 */
d0759ebb 2200 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
021230d4
AV		 2201 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2202 map_vector_to_rxq(adapter, v_start, rxr_idx);
9a799d71 2203
021230d4
AV		 2204 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2205 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2206
9a799d71 2207 goto out;
021230d4 2208 }
9a799d71 2209
021230d4
AV		 2210 /*
2211 * If we don't have enough vectors for a 1-to-1
2212 * mapping, we'll have to group them so there are
2213 * multiple queues per vector.
2214 */
2215 /* Re-adjusting *qpv takes care of the remainder. */
d0759ebb
AD		 2216 for (i = v_start; i < q_vectors; i++) {
2217 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
021230d4
AV		 2218 for (j = 0; j < rqpv; j++) {
2219 map_vector_to_rxq(adapter, i, rxr_idx);
2220 rxr_idx++;
2221 rxr_remaining--;
2222 }
d0759ebb 2223 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
021230d4
AV		 2224 for (j = 0; j < tqpv; j++) {
2225 map_vector_to_txq(adapter, i, txr_idx);
2226 txr_idx++;
2227 txr_remaining--;
9a799d71 2228 }
9a799d71 2229 }
021230d4
AV		 2230out:
2231 return err;
2232}
2233
2234/**
2235 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2236 * @adapter: board private structure
2237 *
2238 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2239 * interrupts from the kernel.
2240 **/
2241static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2242{
2243 struct net_device *netdev = adapter->netdev;
2244 irqreturn_t (*handler)(int, void *);
2245 int i, vector, q_vectors, err;
e8e9f696 2246 int ri = 0, ti = 0;
021230d4
AV		 2247
2248 /* Decrement for Other and TCP Timer vectors */
2249 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2250
d0759ebb 2251 err = ixgbe_map_rings_to_vectors(adapter);
021230d4 2252 if (err)
d0759ebb 2253 return err;
021230d4 2254
08c8833b 2255#define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
d0759ebb 2256 ? &ixgbe_msix_clean_many : \
08c8833b
AD		 2257 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2258 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
d0759ebb 2259 NULL)
021230d4 2260 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb
AD		 2261 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2262 handler = SET_HANDLER(q_vector);
cb13fc20 2263
e8e9f696 2264 if (handler == &ixgbe_msix_clean_rx) {
9fe93afd
DS		 2265 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2266 "%s-%s-%d", netdev->name, "rx", ri++);
e8e9f696 2267 } else if (handler == &ixgbe_msix_clean_tx) {
9fe93afd
DS		 2268 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2269 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb 2270 } else if (handler == &ixgbe_msix_clean_many) {
9fe93afd
DS		 2271 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2272 "%s-%s-%d", netdev->name, "TxRx", ri++);
32aa77a4 2273 ti++;
d0759ebb
AD		 2274 } else {
2275 /* skip this unused q_vector */
2276 continue;
32aa77a4 2277 }
021230d4 2278 err = request_irq(adapter->msix_entries[vector].vector,
d0759ebb
AD		 2279 handler, 0, q_vector->name,
2280 q_vector);
9a799d71 2281 if (err) {
396e799c 2282 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2283 "Error: %d\n", err);
021230d4 2284 goto free_queue_irqs;
9a799d71 2285 }
9a799d71
AK		 2286 }
2287
d0759ebb 2288 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
021230d4 2289 err = request_irq(adapter->msix_entries[vector].vector,
a65151ba 2290 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
9a799d71 2291 if (err) {
396e799c 2292 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2293 goto free_queue_irqs;
9a799d71
AK		 2294 }
2295
9a799d71
AK		 2296 return 0;
2297
021230d4
AV		 2298free_queue_irqs:
2299 for (i = vector - 1; i >= 0; i--)
2300 free_irq(adapter->msix_entries[--vector].vector,
e8e9f696 2301 adapter->q_vector[i]);
021230d4
AV		 2302 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2303 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2304 kfree(adapter->msix_entries);
2305 adapter->msix_entries = NULL;
9a799d71
AK		 2306 return err;
2307}
2308
79aefa45
AD		 2309/**
2310 * ixgbe_irq_enable - Enable default interrupt generation settings
2311 * @adapter: board private structure
2312 **/
6af3b9eb
ET		 2313static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2314 bool flush)
79aefa45
AD		 2315{
2316 u32 mask;
835462fc
NS		 2317
2318 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
119fc60a
MC		 2319 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2320 mask |= IXGBE_EIMS_GPI_SDP0;
6ab33d51
DM		 2321 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2322 mask |= IXGBE_EIMS_GPI_SDP1;
bd508178
AD		 2323 switch (adapter->hw.mac.type) {
2324 case ixgbe_mac_82599EB:
b93a2226 2325 case ixgbe_mac_X540:
2a41ff81 2326 mask |= IXGBE_EIMS_ECC;
e8e26350
PW		 2327 mask |= IXGBE_EIMS_GPI_SDP1;
2328 mask |= IXGBE_EIMS_GPI_SDP2;
1cdd1ec8
GR		 2329 if (adapter->num_vfs)
2330 mask |= IXGBE_EIMS_MAILBOX;
bd508178
AD		 2331 break;
2332 default:
2333 break;
e8e26350 2334 }
03ecf91a 2335 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
c4cf55e5 2336 mask |= IXGBE_EIMS_FLOW_DIR;
e8e26350 2337
79aefa45 2338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
6af3b9eb
ET		 2339 if (queues)
2340 ixgbe_irq_enable_queues(adapter, ~0);
2341 if (flush)
2342 IXGBE_WRITE_FLUSH(&adapter->hw);
1cdd1ec8
GR		 2343
2344 if (adapter->num_vfs > 32) {
2345 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2346 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2347 }
79aefa45 2348}
021230d4 2349
9a799d71 2350/**
021230d4 2351 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2352 * @irq: interrupt number
2353 * @data: pointer to a network interface device structure
9a799d71
AK		 2354 **/
2355static irqreturn_t ixgbe_intr(int irq, void *data)
2356{
a65151ba 2357 struct ixgbe_adapter *adapter = data;
9a799d71 2358 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2359 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2360 u32 eicr;
2361
54037505 2362 /*
6af3b9eb 2363 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2364 * before the read of EICR.
2365 */
2366 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2367
021230d4
AV		 2368 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2369 * therefore no explict interrupt disable is necessary */
2370 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2371 if (!eicr) {
6af3b9eb
ET		 2372 /*
2373 * shared interrupt alert!
f47cf66e 2374 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2375 * have disabled interrupts due to EIAM
2376 * finish the workaround of silicon errata on 82598. Unmask
2377 * the interrupt that we masked before the EICR read.
2378 */
2379 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2380 ixgbe_irq_enable(adapter, true, true);
9a799d71 2381 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2382 }
9a799d71 2383
cf8280ee
JB		 2384 if (eicr & IXGBE_EICR_LSC)
2385 ixgbe_check_lsc(adapter);
021230d4 2386
bd508178
AD		 2387 switch (hw->mac.type) {
2388 case ixgbe_mac_82599EB:
e8e26350 2389 ixgbe_check_sfp_event(adapter, eicr);
bd508178
AD		 2390 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2391 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
f0f9778d
AD		 2392 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2393 adapter->interrupt_event = eicr;
2394 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2395 ixgbe_service_event_schedule(adapter);
2396 }
bd508178
AD		 2397 }
2398 break;
2399 default:
2400 break;
2401 }
e8e26350 2402
0befdb3e
JB		 2403 ixgbe_check_fan_failure(adapter, eicr);
2404
7a921c93 2405 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2406 /* would disable interrupts here but EIAM disabled it */
7a921c93 2407 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2408 }
2409
6af3b9eb
ET		 2410 /*
2411 * re-enable link(maybe) and non-queue interrupts, no flush.
2412 * ixgbe_poll will re-enable the queue interrupts
2413 */
2414
2415 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2416 ixgbe_irq_enable(adapter, false, false);
2417
9a799d71
AK		 2418 return IRQ_HANDLED;
2419}
2420
021230d4
AV		 2421static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2422{
efe3d3c8
AD		 2423 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2424 int i;
2425
2426 /* legacy and MSI only use one vector */
2427 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2428 q_vectors = 1;
2429
2430 for (i = 0; i < adapter->num_rx_queues; i++) {
2431 adapter->rx_ring[i]->q_vector = NULL;
2432 adapter->rx_ring[i]->next = NULL;
2433 }
2434 for (i = 0; i < adapter->num_tx_queues; i++) {
2435 adapter->tx_ring[i]->q_vector = NULL;
2436 adapter->tx_ring[i]->next = NULL;
2437 }
021230d4
AV		 2438
2439 for (i = 0; i < q_vectors; i++) {
7a921c93 2440 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2441 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2442 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2443 }
2444}
2445
9a799d71
AK		 2446/**
2447 * ixgbe_request_irq - initialize interrupts
2448 * @adapter: board private structure
2449 *
2450 * Attempts to configure interrupts using the best available
2451 * capabilities of the hardware and kernel.
2452 **/
021230d4 2453static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2454{
2455 struct net_device *netdev = adapter->netdev;
021230d4 2456 int err;
9a799d71 2457
021230d4
AV		 2458 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2459 err = ixgbe_request_msix_irqs(adapter);
2460 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
a0607fd3 2461 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2462 netdev->name, adapter);
021230d4 2463 } else {
a0607fd3 2464 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2465 netdev->name, adapter);
9a799d71
AK		 2466 }
2467
9a799d71 2468 if (err)
396e799c 2469 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2470
9a799d71
AK		 2471 return err;
2472}
2473
2474static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2475{
9a799d71 2476 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2477 int i, q_vectors;
9a799d71 2478
021230d4
AV		 2479 q_vectors = adapter->num_msix_vectors;
2480
2481 i = q_vectors - 1;
a65151ba 2482 free_irq(adapter->msix_entries[i].vector, adapter);
9a799d71 2483
021230d4
AV		 2484 i--;
2485 for (; i >= 0; i--) {
894ff7cf 2486 /* free only the irqs that were actually requested */
08c8833b
AD		 2487 if (!adapter->q_vector[i]->rx.count &&
2488 !adapter->q_vector[i]->tx.count)
894ff7cf
AD		 2489 continue;
2490
021230d4 2491 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2492 adapter->q_vector[i]);
021230d4
AV		 2493 }
2494
2495 ixgbe_reset_q_vectors(adapter);
2496 } else {
a65151ba 2497 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2498 }
2499}
2500
22d5a71b
JB		 2501/**
2502 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2503 * @adapter: board private structure
2504 **/
2505static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2506{
bd508178
AD		 2507 switch (adapter->hw.mac.type) {
2508 case ixgbe_mac_82598EB:
835462fc 2509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2510 break;
2511 case ixgbe_mac_82599EB:
b93a2226 2512 case ixgbe_mac_X540:
835462fc
NS		 2513 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2514 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1cdd1ec8
GR		 2516 if (adapter->num_vfs > 32)
2517 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
bd508178
AD		 2518 break;
2519 default:
2520 break;
22d5a71b
JB		 2521 }
2522 IXGBE_WRITE_FLUSH(&adapter->hw);
2523 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2524 int i;
2525 for (i = 0; i < adapter->num_msix_vectors; i++)
2526 synchronize_irq(adapter->msix_entries[i].vector);
2527 } else {
2528 synchronize_irq(adapter->pdev->irq);
2529 }
2530}
2531
9a799d71
AK		 2532/**
2533 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2534 *
2535 **/
2536static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2537{
9a799d71
AK		 2538 struct ixgbe_hw *hw = &adapter->hw;
2539
021230d4 2540 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
e8e9f696 2541 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
9a799d71 2542
e8e26350
PW		 2543 ixgbe_set_ivar(adapter, 0, 0, 0);
2544 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4
AV		 2545
2546 map_vector_to_rxq(adapter, 0, 0);
2547 map_vector_to_txq(adapter, 0, 0);
2548
396e799c 2549 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2550}
2551
43e69bf0
AD		 2552/**
2553 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2554 * @adapter: board private structure
2555 * @ring: structure containing ring specific data
2556 *
2557 * Configure the Tx descriptor ring after a reset.
2558 **/
84418e3b
AD		 2559void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2560 struct ixgbe_ring *ring)
43e69bf0
AD		 2561{
2562 struct ixgbe_hw *hw = &adapter->hw;
2563 u64 tdba = ring->dma;
2f1860b8
AD		 2564 int wait_loop = 10;
2565 u32 txdctl;
bf29ee6c 2566 u8 reg_idx = ring->reg_idx;
43e69bf0 2567
2f1860b8
AD		 2568 /* disable queue to avoid issues while updating state */
2569 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2570 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2571 txdctl & ~IXGBE_TXDCTL_ENABLE);
2572 IXGBE_WRITE_FLUSH(hw);
2573
43e69bf0 2574 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2575 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2576 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2577 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2578 ring->count * sizeof(union ixgbe_adv_tx_desc));
2579 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2580 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2581 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2582
2f1860b8
AD		 2583 /* configure fetching thresholds */
2584 if (adapter->rx_itr_setting == 0) {
2585 /* cannot set wthresh when itr==0 */
2586 txdctl &= ~0x007F0000;
2587 } else {
2588 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2589 txdctl |= (8 << 16);
2590 }
2591 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2592 /* PThresh workaround for Tx hang with DFP enabled. */
2593 txdctl |= 32;
2594 }
2595
2596 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2597 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2598 adapter->atr_sample_rate) {
2599 ring->atr_sample_rate = adapter->atr_sample_rate;
2600 ring->atr_count = 0;
2601 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2602 } else {
2603 ring->atr_sample_rate = 0;
2604 }
2f1860b8 2605
c84d324c
JF		 2606 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2607
2f1860b8
AD		 2608 /* enable queue */
2609 txdctl |= IXGBE_TXDCTL_ENABLE;
2610 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2611
2612 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2613 if (hw->mac.type == ixgbe_mac_82598EB &&
2614 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2615 return;
2616
2617 /* poll to verify queue is enabled */
2618 do {
032b4325 2619 usleep_range(1000, 2000);
2f1860b8
AD		 2620 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2621 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2622 if (!wait_loop)
2623 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2624}
2625
120ff942
AD		 2626static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2627{
2628 struct ixgbe_hw *hw = &adapter->hw;
2629 u32 rttdcs;
72a32f1f 2630 u32 reg;
8b1c0b24 2631 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2632
2633 if (hw->mac.type == ixgbe_mac_82598EB)
2634 return;
2635
2636 /* disable the arbiter while setting MTQC */
2637 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2638 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2639 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2640
2641 /* set transmit pool layout */
8b1c0b24 2642 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2643 case (IXGBE_FLAG_SRIOV_ENABLED):
2644 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2645 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2646 break;
8b1c0b24
JF		 2647 default:
2648 if (!tcs)
2649 reg = IXGBE_MTQC_64Q_1PB;
2650 else if (tcs <= 4)
2651 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2652 else
2653 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2654
8b1c0b24 2655 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2656
8b1c0b24
JF		 2657 /* Enable Security TX Buffer IFG for multiple pb */
2658 if (tcs) {
2659 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2660 reg |= IXGBE_SECTX_DCB;
2661 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2662 }
120ff942
AD		 2663 break;
2664 }
2665
2666 /* re-enable the arbiter */
2667 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2668 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2669}
2670
9a799d71 2671/**
3a581073 2672 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2673 * @adapter: board private structure
2674 *
2675 * Configure the Tx unit of the MAC after a reset.
2676 **/
2677static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2678{
2f1860b8
AD		 2679 struct ixgbe_hw *hw = &adapter->hw;
2680 u32 dmatxctl;
43e69bf0 2681 u32 i;
9a799d71 2682
2f1860b8
AD		 2683 ixgbe_setup_mtqc(adapter);
2684
2685 if (hw->mac.type != ixgbe_mac_82598EB) {
2686 /* DMATXCTL.EN must be before Tx queues are enabled */
2687 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2688 dmatxctl |= IXGBE_DMATXCTL_TE;
2689 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2690 }
2691
9a799d71 2692 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2693 for (i = 0; i < adapter->num_tx_queues; i++)
2694 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2695}
2696
e8e26350 2697#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2698
a6616b42 2699static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2700 struct ixgbe_ring *rx_ring)
cc41ac7c 2701{
cc41ac7c 2702 u32 srrctl;
bf29ee6c 2703 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2704
bd508178
AD		 2705 switch (adapter->hw.mac.type) {
2706 case ixgbe_mac_82598EB: {
2707 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2708 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2709 reg_idx = reg_idx & mask;
cc41ac7c 2710 }
bd508178
AD		 2711 break;
2712 case ixgbe_mac_82599EB:
b93a2226 2713 case ixgbe_mac_X540:
bd508178
AD		 2714 default:
2715 break;
2716 }
2717
bf29ee6c 2718 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2719
2720 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2721 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2722 if (adapter->num_vfs)
2723 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2724
afafd5b0
AD		 2725 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2726 IXGBE_SRRCTL_BSIZEHDR_MASK;
2727
7d637bcc 2728 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2729#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2730 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2731#else
2732 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2733#endif
cc41ac7c 2734 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2735 } else {
afafd5b0
AD		 2736 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2737 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2738 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2739 }
e8e26350 2740
bf29ee6c 2741 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2742}
9a799d71 2743
05abb126 2744static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2745{
05abb126
AD		 2746 struct ixgbe_hw *hw = &adapter->hw;
2747 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2748 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2749 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2750 u32 mrqc = 0, reta = 0;
2751 u32 rxcsum;
2752 int i, j;
8b1c0b24 2753 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2754 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2755
2756 if (tcs)
2757 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2758
05abb126
AD		 2759 /* Fill out hash function seeds */
2760 for (i = 0; i < 10; i++)
2761 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2762
2763 /* Fill out redirection table */
2764 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2765 if (j == maxq)
05abb126
AD		 2766 j = 0;
2767 /* reta = 4-byte sliding window of
2768 * 0x00..(indices-1)(indices-1)00..etc. */
2769 reta = (reta << 8) | (j * 0x11);
2770 if ((i & 3) == 3)
2771 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2772 }
0cefafad 2773
05abb126
AD		 2774 /* Disable indicating checksum in descriptor, enables RSS hash */
2775 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2776 rxcsum |= IXGBE_RXCSUM_PCSD;
2777 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2778
8b1c0b24
JF		 2779 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2780 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2781 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2782 } else {
2783 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2784 | IXGBE_FLAG_SRIOV_ENABLED);
2785
2786 switch (mask) {
2787 case (IXGBE_FLAG_RSS_ENABLED):
2788 if (!tcs)
2789 mrqc = IXGBE_MRQC_RSSEN;
2790 else if (tcs <= 4)
2791 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2792 else
2793 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2794 break;
2795 case (IXGBE_FLAG_SRIOV_ENABLED):
2796 mrqc = IXGBE_MRQC_VMDQEN;
2797 break;
2798 default:
2799 break;
2800 }
0cefafad
JB		 2801 }
2802
05abb126
AD		 2803 /* Perform hash on these packet types */
2804 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2805 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2806 | IXGBE_MRQC_RSS_FIELD_IPV6
2807 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2808
2809 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2810}
2811
bb5a9ad2
NS		 2812/**
2813 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2814 * @adapter: address of board private structure
2815 * @index: index of ring to set
bb5a9ad2 2816 **/
082757af 2817static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2818 struct ixgbe_ring *ring)
bb5a9ad2 2819{
bb5a9ad2 2820 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2821 u32 rscctrl;
edd2ea55 2822 int rx_buf_len;
bf29ee6c 2823 u8 reg_idx = ring->reg_idx;
7367096a 2824
7d637bcc 2825 if (!ring_is_rsc_enabled(ring))
7367096a 2826 return;
bb5a9ad2 2827
7367096a
AD		 2828 rx_buf_len = ring->rx_buf_len;
2829 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2830 rscctrl |= IXGBE_RSCCTL_RSCEN;
2831 /*
2832 * we must limit the number of descriptors so that the
2833 * total size of max desc * buf_len is not greater
2834 * than 65535
2835 */
7d637bcc 2836 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2837#if (MAX_SKB_FRAGS > 16)
2838 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2839#elif (MAX_SKB_FRAGS > 8)
2840 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2841#elif (MAX_SKB_FRAGS > 4)
2842 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2843#else
2844 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2845#endif
2846 } else {
2847 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2848 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2849 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2850 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2851 else
2852 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2853 }
7367096a 2854 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2855}
2856
9e10e045
AD		 2857/**
2858 * ixgbe_set_uta - Set unicast filter table address
2859 * @adapter: board private structure
2860 *
2861 * The unicast table address is a register array of 32-bit registers.
2862 * The table is meant to be used in a way similar to how the MTA is used
2863 * however due to certain limitations in the hardware it is necessary to
2864 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2865 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2866 **/
2867static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2868{
2869 struct ixgbe_hw *hw = &adapter->hw;
2870 int i;
2871
2872 /* The UTA table only exists on 82599 hardware and newer */
2873 if (hw->mac.type < ixgbe_mac_82599EB)
2874 return;
2875
2876 /* we only need to do this if VMDq is enabled */
2877 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2878 return;
2879
2880 for (i = 0; i < 128; i++)
2881 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2882}
2883
2884#define IXGBE_MAX_RX_DESC_POLL 10
2885static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2886 struct ixgbe_ring *ring)
2887{
2888 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2889 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2890 u32 rxdctl;
bf29ee6c 2891 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2892
2893 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2894 if (hw->mac.type == ixgbe_mac_82598EB &&
2895 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2896 return;
2897
2898 do {
032b4325 2899 usleep_range(1000, 2000);
9e10e045
AD		 2900 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2901 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2902
2903 if (!wait_loop) {
2904 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2905 "the polling period\n", reg_idx);
2906 }
2907}
2908
2d39d576
YZ		 2909void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2910 struct ixgbe_ring *ring)
2911{
2912 struct ixgbe_hw *hw = &adapter->hw;
2913 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2914 u32 rxdctl;
2915 u8 reg_idx = ring->reg_idx;
2916
2917 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2918 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2919
2920 /* write value back with RXDCTL.ENABLE bit cleared */
2921 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2922
2923 if (hw->mac.type == ixgbe_mac_82598EB &&
2924 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2925 return;
2926
2927 /* the hardware may take up to 100us to really disable the rx queue */
2928 do {
2929 udelay(10);
2930 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2931 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2932
2933 if (!wait_loop) {
2934 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2935 "the polling period\n", reg_idx);
2936 }
2937}
2938
84418e3b
AD		 2939void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2940 struct ixgbe_ring *ring)
acd37177
AD		 2941{
2942 struct ixgbe_hw *hw = &adapter->hw;
2943 u64 rdba = ring->dma;
9e10e045 2944 u32 rxdctl;
bf29ee6c 2945 u8 reg_idx = ring->reg_idx;
acd37177 2946
9e10e045
AD		 2947 /* disable queue to avoid issues while updating state */
2948 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2949 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2950
acd37177
AD		 2951 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2952 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2953 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2954 ring->count * sizeof(union ixgbe_adv_rx_desc));
2955 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2956 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2957 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2958
2959 ixgbe_configure_srrctl(adapter, ring);
2960 ixgbe_configure_rscctl(adapter, ring);
2961
e9f98072
GR		 2962 /* If operating in IOV mode set RLPML for X540 */
2963 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2964 hw->mac.type == ixgbe_mac_X540) {
2965 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2966 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2967 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2968 }
2969
9e10e045
AD		 2970 if (hw->mac.type == ixgbe_mac_82598EB) {
2971 /*
2972 * enable cache line friendly hardware writes:
2973 * PTHRESH=32 descriptors (half the internal cache),
2974 * this also removes ugly rx_no_buffer_count increment
2975 * HTHRESH=4 descriptors (to minimize latency on fetch)
2976 * WTHRESH=8 burst writeback up to two cache lines
2977 */
2978 rxdctl &= ~0x3FFFFF;
2979 rxdctl |= 0x080420;
2980 }
2981
2982 /* enable receive descriptor ring */
2983 rxdctl |= IXGBE_RXDCTL_ENABLE;
2984 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2985
2986 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2987 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2988}
2989
48654521
AD		 2990static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2991{
2992 struct ixgbe_hw *hw = &adapter->hw;
2993 int p;
2994
2995 /* PSRTYPE must be initialized in non 82598 adapters */
2996 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2997 IXGBE_PSRTYPE_UDPHDR |
2998 IXGBE_PSRTYPE_IPV4HDR |
48654521 2999 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3000 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3001
3002 if (hw->mac.type == ixgbe_mac_82598EB)
3003 return;
3004
3005 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3006 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3007
3008 for (p = 0; p < adapter->num_rx_pools; p++)
3009 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3010 psrtype);
3011}
3012
f5b4a52e
AD		 3013static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3014{
3015 struct ixgbe_hw *hw = &adapter->hw;
3016 u32 gcr_ext;
3017 u32 vt_reg_bits;
3018 u32 reg_offset, vf_shift;
3019 u32 vmdctl;
3020
3021 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3022 return;
3023
3024 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3025 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3026 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3027 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3028
3029 vf_shift = adapter->num_vfs % 32;
3030 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3031
3032 /* Enable only the PF's pool for Tx/Rx */
3033 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3034 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3035 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3036 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3037 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3038
3039 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3040 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3041
3042 /*
3043 * Set up VF register offsets for selected VT Mode,
3044 * i.e. 32 or 64 VFs for SR-IOV
3045 */
3046 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3047 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3048 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3049 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3050
3051 /* enable Tx loopback for VF/PF communication */
3052 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3053 /* Enable MAC Anti-Spoofing */
a1cbb15c
GR		 3054 hw->mac.ops.set_mac_anti_spoofing(hw,
3055 (adapter->antispoofing_enabled =
3056 (adapter->num_vfs != 0)),
a985b6c3 3057 adapter->num_vfs);
f5b4a52e
AD		 3058}
3059
477de6ed 3060static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3061{
9a799d71
AK		 3062 struct ixgbe_hw *hw = &adapter->hw;
3063 struct net_device *netdev = adapter->netdev;
3064 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3065 int rx_buf_len;
477de6ed
AD		 3066 struct ixgbe_ring *rx_ring;
3067 int i;
3068 u32 mhadd, hlreg0;
48654521 3069
9a799d71 3070 /* Decide whether to use packet split mode or not */
a124339a
DS		 3071 /* On by default */
3072 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3073
1cdd1ec8 3074 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3075 if (adapter->num_vfs)
3076 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3077
3078 /* Disable packet split due to 82599 erratum #45 */
3079 if (hw->mac.type == ixgbe_mac_82599EB)
3080 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71
AK		 3081
3082 /* Set the RX buffer length according to the mode */
3083 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
7c6e0a43 3084 rx_buf_len = IXGBE_RX_HDR_SIZE;
9a799d71 3085 } else {
0c19d6af 3086 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
f8212f97 3087 (netdev->mtu <= ETH_DATA_LEN))
7c6e0a43 3088 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9a799d71 3089 else
477de6ed 3090 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
9a799d71
AK		 3091 }
3092
63f39bd1 3093#ifdef IXGBE_FCOE
477de6ed
AD		 3094 /* adjust max frame to be able to do baby jumbo for FCoE */
3095 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3096 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3097 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3098
477de6ed
AD		 3099#endif /* IXGBE_FCOE */
3100 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3101 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3102 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3103 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3104
3105 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3106 }
3107
3108 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3109 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3110 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3111 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3112
0cefafad
JB		 3113 /*
3114 * Setup the HW Rx Head and Tail Descriptor Pointers and
3115 * the Base and Length of the Rx Descriptor Ring
3116 */
9a799d71 3117 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3118 rx_ring = adapter->rx_ring[i];
a6616b42 3119 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3120
6e455b89 3121 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3122 set_ring_ps_enabled(rx_ring);
3123 else
3124 clear_ring_ps_enabled(rx_ring);
3125
3126 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3127 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3128 else
7d637bcc 3129 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3130
63f39bd1 3131#ifdef IXGBE_FCOE
e8e9f696 3132 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3133 struct ixgbe_ring_feature *f;
3134 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3135 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3136 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3137 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3138 rx_ring->rx_buf_len =
e8e9f696 3139 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3140 } else if (!ring_is_rsc_enabled(rx_ring) &&
3141 !ring_is_ps_enabled(rx_ring)) {
3142 rx_ring->rx_buf_len =
3143 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3144 }
63f39bd1 3145 }
63f39bd1 3146#endif /* IXGBE_FCOE */
477de6ed 3147 }
477de6ed
AD		 3148}
3149
7367096a
AD		 3150static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3151{
3152 struct ixgbe_hw *hw = &adapter->hw;
3153 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3154
3155 switch (hw->mac.type) {
3156 case ixgbe_mac_82598EB:
3157 /*
3158 * For VMDq support of different descriptor types or
3159 * buffer sizes through the use of multiple SRRCTL
3160 * registers, RDRXCTL.MVMEN must be set to 1
3161 *
3162 * also, the manual doesn't mention it clearly but DCA hints
3163 * will only use queue 0's tags unless this bit is set. Side
3164 * effects of setting this bit are only that SRRCTL must be
3165 * fully programmed [0..15]
3166 */
3167 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3168 break;
3169 case ixgbe_mac_82599EB:
b93a2226 3170 case ixgbe_mac_X540:
7367096a
AD		 3171 /* Disable RSC for ACK packets */
3172 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3173 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3174 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3175 /* hardware requires some bits to be set by default */
3176 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3177 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3178 break;
3179 default:
3180 /* We should do nothing since we don't know this hardware */
3181 return;
3182 }
3183
3184 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3185}
3186
477de6ed
AD		 3187/**
3188 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3189 * @adapter: board private structure
3190 *
3191 * Configure the Rx unit of the MAC after a reset.
3192 **/
3193static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3194{
3195 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3196 int i;
3197 u32 rxctrl;
477de6ed
AD		 3198
3199 /* disable receives while setting up the descriptors */
3200 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3201 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3202
3203 ixgbe_setup_psrtype(adapter);
7367096a 3204 ixgbe_setup_rdrxctl(adapter);
477de6ed 3205
9e10e045 3206 /* Program registers for the distribution of queues */
f5b4a52e 3207 ixgbe_setup_mrqc(adapter);
f5b4a52e 3208
9e10e045
AD		 3209 ixgbe_set_uta(adapter);
3210
477de6ed
AD		 3211 /* set_rx_buffer_len must be called before ring initialization */
3212 ixgbe_set_rx_buffer_len(adapter);
3213
3214 /*
3215 * Setup the HW Rx Head and Tail Descriptor Pointers and
3216 * the Base and Length of the Rx Descriptor Ring
3217 */
9e10e045
AD		 3218 for (i = 0; i < adapter->num_rx_queues; i++)
3219 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3220
9e10e045
AD		 3221 /* disable drop enable for 82598 parts */
3222 if (hw->mac.type == ixgbe_mac_82598EB)
3223 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3224
3225 /* enable all receives */
3226 rxctrl |= IXGBE_RXCTRL_RXEN;
3227 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3228}
3229
068c89b0
DS		 3230static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3231{
3232 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3233 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3234 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3235
3236 /* add VID to filter table */
1ada1b1b 3237 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3238 set_bit(vid, adapter->active_vlans);
068c89b0
DS		 3239}
3240
3241static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3242{
3243 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3244 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3245 int pool_ndx = adapter->num_vfs;
068c89b0 3246
068c89b0 3247 /* remove VID from filter table */
1ada1b1b 3248 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3249 clear_bit(vid, adapter->active_vlans);
068c89b0
DS		 3250}
3251
5f6c0181
JB		 3252/**
3253 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3254 * @adapter: driver data
3255 */
3256static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3257{
3258 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3259 u32 vlnctrl;
3260
3261 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3262 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3263 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3264}
3265
3266/**
3267 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3268 * @adapter: driver data
3269 */
3270static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3271{
3272 struct ixgbe_hw *hw = &adapter->hw;
3273 u32 vlnctrl;
3274
3275 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3276 vlnctrl |= IXGBE_VLNCTRL_VFE;
3277 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3278 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3279}
3280
3281/**
3282 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3283 * @adapter: driver data
3284 */
3285static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3286{
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 u32 vlnctrl;
5f6c0181
JB		 3289 int i, j;
3290
3291 switch (hw->mac.type) {
3292 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3293 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3294 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3295 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3296 break;
3297 case ixgbe_mac_82599EB:
b93a2226 3298 case ixgbe_mac_X540:
5f6c0181
JB		 3299 for (i = 0; i < adapter->num_rx_queues; i++) {
3300 j = adapter->rx_ring[i]->reg_idx;
3301 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3302 vlnctrl &= ~IXGBE_RXDCTL_VME;
3303 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3304 }
3305 break;
3306 default:
3307 break;
3308 }
3309}
3310
3311/**
f62bbb5e 3312 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3313 * @adapter: driver data
3314 */
f62bbb5e 3315static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3316{
3317 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3318 u32 vlnctrl;
5f6c0181
JB		 3319 int i, j;
3320
3321 switch (hw->mac.type) {
3322 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3323 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3324 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3325 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3326 break;
3327 case ixgbe_mac_82599EB:
b93a2226 3328 case ixgbe_mac_X540:
5f6c0181
JB		 3329 for (i = 0; i < adapter->num_rx_queues; i++) {
3330 j = adapter->rx_ring[i]->reg_idx;
3331 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3332 vlnctrl |= IXGBE_RXDCTL_VME;
3333 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3334 }
3335 break;
3336 default:
3337 break;
3338 }
3339}
3340
9a799d71
AK		 3341static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3342{
f62bbb5e 3343 u16 vid;
9a799d71 3344
f62bbb5e
JG		 3345 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3346
3347 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3348 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3349}
3350
2850062a
AD		 3351/**
3352 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3353 * @netdev: network interface device structure
3354 *
3355 * Writes unicast address list to the RAR table.
3356 * Returns: -ENOMEM on failure/insufficient address space
3357 * 0 on no addresses written
3358 * X on writing X addresses to the RAR table
3359 **/
3360static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3361{
3362 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3363 struct ixgbe_hw *hw = &adapter->hw;
3364 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3365 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3366 int count = 0;
3367
3368 /* return ENOMEM indicating insufficient memory for addresses */
3369 if (netdev_uc_count(netdev) > rar_entries)
3370 return -ENOMEM;
3371
3372 if (!netdev_uc_empty(netdev) && rar_entries) {
3373 struct netdev_hw_addr *ha;
3374 /* return error if we do not support writing to RAR table */
3375 if (!hw->mac.ops.set_rar)
3376 return -ENOMEM;
3377
3378 netdev_for_each_uc_addr(ha, netdev) {
3379 if (!rar_entries)
3380 break;
3381 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3382 vfn, IXGBE_RAH_AV);
3383 count++;
3384 }
3385 }
3386 /* write the addresses in reverse order to avoid write combining */
3387 for (; rar_entries > 0 ; rar_entries--)
3388 hw->mac.ops.clear_rar(hw, rar_entries);
3389
3390 return count;
3391}
3392
9a799d71 3393/**
2c5645cf 3394 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3395 * @netdev: network interface device structure
3396 *
2c5645cf
CL		 3397 * The set_rx_method entry point is called whenever the unicast/multicast
3398 * address list or the network interface flags are updated. This routine is
3399 * responsible for configuring the hardware for proper unicast, multicast and
3400 * promiscuous mode.
9a799d71 3401 **/
7f870475 3402void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3403{
3404 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3405 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3406 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3407 int count;
9a799d71
AK		 3408
3409 /* Check for Promiscuous and All Multicast modes */
3410
3411 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3412
f5dc442b
AD		 3413 /* set all bits that we expect to always be set */
3414 fctrl |= IXGBE_FCTRL_BAM;
3415 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3416 fctrl |= IXGBE_FCTRL_PMCF;
3417
2850062a
AD		 3418 /* clear the bits we are changing the status of */
3419 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3420
9a799d71 3421 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3422 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3423 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3424 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3425 /* don't hardware filter vlans in promisc mode */
3426 ixgbe_vlan_filter_disable(adapter);
9a799d71 3427 } else {
746b9f02
PM		 3428 if (netdev->flags & IFF_ALLMULTI) {
3429 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3430 vmolr |= IXGBE_VMOLR_MPE;
3431 } else {
3432 /*
3433 * Write addresses to the MTA, if the attempt fails
25985edc 3434 * then we should just turn on promiscuous mode so
2850062a
AD		 3435 * that we can at least receive multicast traffic
3436 */
3437 hw->mac.ops.update_mc_addr_list(hw, netdev);
3438 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3439 }
5f6c0181 3440 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3441 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3442 /*
3443 * Write addresses to available RAR registers, if there is not
3444 * sufficient space to store all the addresses then enable
25985edc 3445 * unicast promiscuous mode
2850062a
AD		 3446 */
3447 count = ixgbe_write_uc_addr_list(netdev);
3448 if (count < 0) {
3449 fctrl |= IXGBE_FCTRL_UPE;
3450 vmolr |= IXGBE_VMOLR_ROPE;
3451 }
9a799d71
AK		 3452 }
3453
2850062a 3454 if (adapter->num_vfs) {
1cdd1ec8 3455 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3456 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3457 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3458 IXGBE_VMOLR_ROPE);
3459 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3460 }
3461
3462 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3463
3464 if (netdev->features & NETIF_F_HW_VLAN_RX)
3465 ixgbe_vlan_strip_enable(adapter);
3466 else
3467 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3468}
3469
021230d4
AV		 3470static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3471{
3472 int q_idx;
3473 struct ixgbe_q_vector *q_vector;
3474 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3475
3476 /* legacy and MSI only use one vector */
3477 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3478 q_vectors = 1;
3479
3480 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
f0848276 3481 struct napi_struct *napi;
7a921c93 3482 q_vector = adapter->q_vector[q_idx];
f0848276 3483 napi = &q_vector->napi;
91281fd3 3484 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
08c8833b
AD		 3485 if (!q_vector->rx.count || !q_vector->tx.count) {
3486 if (q_vector->tx.count == 1)
91281fd3 3487 napi->poll = &ixgbe_clean_txonly;
08c8833b 3488 else if (q_vector->rx.count == 1)
91281fd3
AD		 3489 napi->poll = &ixgbe_clean_rxonly;
3490 }
3491 }
f0848276
JB		 3492
3493 napi_enable(napi);
021230d4
AV		 3494 }
3495}
3496
3497static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3498{
3499 int q_idx;
3500 struct ixgbe_q_vector *q_vector;
3501 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3502
3503 /* legacy and MSI only use one vector */
3504 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3505 q_vectors = 1;
3506
3507 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3508 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3509 napi_disable(&q_vector->napi);
3510 }
3511}
3512
7a6b6f51 3513#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3514/*
3515 * ixgbe_configure_dcb - Configure DCB hardware
3516 * @adapter: ixgbe adapter struct
3517 *
3518 * This is called by the driver on open to configure the DCB hardware.
3519 * This is also called by the gennetlink interface when reconfiguring
3520 * the DCB state.
3521 */
3522static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3523{
3524 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3525 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3526
67ebd791
AD		 3527 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3528 if (hw->mac.type == ixgbe_mac_82598EB)
3529 netif_set_gso_max_size(adapter->netdev, 65536);
3530 return;
3531 }
3532
3533 if (hw->mac.type == ixgbe_mac_82598EB)
3534 netif_set_gso_max_size(adapter->netdev, 32768);
3535
2f90b865 3536
2f90b865 3537 /* Enable VLAN tag insert/strip */
f62bbb5e 3538 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3539
2f90b865 3540 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90
AD		 3541
3542 /* reconfigure the hardware */
6f70f6ac 3543 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
971060b1 3544#ifdef IXGBE_FCOE
c27931da
JF		 3545 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3546 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3547#endif
3548 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3549 DCB_TX_CONFIG);
3550 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3551 DCB_RX_CONFIG);
3552 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3553 } else {
3554 struct net_device *dev = adapter->netdev;
3555
3556 if (adapter->ixgbe_ieee_ets)
3557 dev->dcbnl_ops->ieee_setets(dev,
3558 adapter->ixgbe_ieee_ets);
3559 if (adapter->ixgbe_ieee_pfc)
3560 dev->dcbnl_ops->ieee_setpfc(dev,
3561 adapter->ixgbe_ieee_pfc);
3562 }
8187cd48
JF		 3563
3564 /* Enable RSS Hash per TC */
3565 if (hw->mac.type != ixgbe_mac_82598EB) {
3566 int i;
3567 u32 reg = 0;
3568
3569 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3570 u8 msb = 0;
3571 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3572
3573 while (cnt >>= 1)
3574 msb++;
3575
3576 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3577 }
3578 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3579 }
2f90b865
AD		 3580}
3581
3582#endif
80605c65
JF		 3583
3584static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3585{
3586 int hdrm = 0;
3587 int num_tc = netdev_get_num_tc(adapter->netdev);
3588 struct ixgbe_hw *hw = &adapter->hw;
3589
3590 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3591 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3592 hdrm = 64 << adapter->fdir_pballoc;
3593
3594 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3595}
3596
e4911d57
AD		 3597static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3598{
3599 struct ixgbe_hw *hw = &adapter->hw;
3600 struct hlist_node *node, *node2;
3601 struct ixgbe_fdir_filter *filter;
3602
3603 spin_lock(&adapter->fdir_perfect_lock);
3604
3605 if (!hlist_empty(&adapter->fdir_filter_list))
3606 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3607
3608 hlist_for_each_entry_safe(filter, node, node2,
3609 &adapter->fdir_filter_list, fdir_node) {
3610 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3611 &filter->filter,
3612 filter->sw_idx,
3613 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3614 IXGBE_FDIR_DROP_QUEUE :
3615 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3616 }
3617
3618 spin_unlock(&adapter->fdir_perfect_lock);
3619}
3620
9a799d71
AK		 3621static void ixgbe_configure(struct ixgbe_adapter *adapter)
3622{
3623 struct net_device *netdev = adapter->netdev;
c4cf55e5 3624 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 3625 int i;
3626
80605c65 3627 ixgbe_configure_pb(adapter);
7a6b6f51 3628#ifdef CONFIG_IXGBE_DCB
67ebd791 3629 ixgbe_configure_dcb(adapter);
2f90b865 3630#endif
9a799d71 3631
f62bbb5e
JG		 3632 ixgbe_set_rx_mode(netdev);
3633 ixgbe_restore_vlan(adapter);
3634
eacd73f7
YZ		 3635#ifdef IXGBE_FCOE
3636 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3637 ixgbe_configure_fcoe(adapter);
3638
3639#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 3640 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3641 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 3642 adapter->tx_ring[i]->atr_sample_rate =
e8e9f696 3643 adapter->atr_sample_rate;
c4cf55e5 3644 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
e4911d57
AD		 3645 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3646 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3647 adapter->fdir_pballoc);
3648 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3649 }
933d41f1 3650 ixgbe_configure_virtualization(adapter);
c4cf55e5 3651
9a799d71
AK		 3652 ixgbe_configure_tx(adapter);
3653 ixgbe_configure_rx(adapter);
9a799d71
AK		 3654}
3655
e8e26350
PW		 3656static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3657{
3658 switch (hw->phy.type) {
3659 case ixgbe_phy_sfp_avago:
3660 case ixgbe_phy_sfp_ftl:
3661 case ixgbe_phy_sfp_intel:
3662 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3663 case ixgbe_phy_sfp_passive_tyco:
3664 case ixgbe_phy_sfp_passive_unknown:
3665 case ixgbe_phy_sfp_active_unknown:
3666 case ixgbe_phy_sfp_ftl_active:
e8e26350
PW		 3667 return true;
3668 default:
3669 return false;
3670 }
3671}
3672
0ecc061d 3673/**
e8e26350
PW		 3674 * ixgbe_sfp_link_config - set up SFP+ link
3675 * @adapter: pointer to private adapter struct
3676 **/
3677static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3678{
7086400d
AD		 3679 /*
3680 * We are assuming the worst case scenerio here, and that
3681 * is that an SFP was inserted/removed after the reset
3682 * but before SFP detection was enabled. As such the best
3683 * solution is to just start searching as soon as we start
3684 */
3685 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3686 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3687
7086400d 3688 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3689}
3690
3691/**
3692 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3693 * @hw: pointer to private hardware struct
3694 *
3695 * Returns 0 on success, negative on failure
3696 **/
e8e26350 3697static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3698{
3699 u32 autoneg;
8620a103 3700 bool negotiation, link_up = false;
0ecc061d
PWJ		 3701 u32 ret = IXGBE_ERR_LINK_SETUP;
3702
3703 if (hw->mac.ops.check_link)
3704 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3705
3706 if (ret)
3707 goto link_cfg_out;
3708
0b0c2b31
ET		 3709 autoneg = hw->phy.autoneg_advertised;
3710 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3711 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3712 &negotiation);
0ecc061d
PWJ		 3713 if (ret)
3714 goto link_cfg_out;
3715
8620a103
MC		 3716 if (hw->mac.ops.setup_link)
3717 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3718link_cfg_out:
3719 return ret;
3720}
3721
a34bcfff 3722static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3723{
9a799d71 3724 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3725 u32 gpie = 0;
9a799d71 3726
9b471446 3727 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3728 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3729 IXGBE_GPIE_OCD;
3730 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3731 /*
3732 * use EIAM to auto-mask when MSI-X interrupt is asserted
3733 * this saves a register write for every interrupt
3734 */
3735 switch (hw->mac.type) {
3736 case ixgbe_mac_82598EB:
3737 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3738 break;
9b471446 3739 case ixgbe_mac_82599EB:
b93a2226
DS		 3740 case ixgbe_mac_X540:
3741 default:
9b471446
JB		 3742 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3743 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3744 break;
3745 }
3746 } else {
021230d4
AV		 3747 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3748 * specifically only auto mask tx and rx interrupts */
3749 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3750 }
9a799d71 3751
a34bcfff
AD		 3752 /* XXX: to interrupt immediately for EICS writes, enable this */
3753 /* gpie |= IXGBE_GPIE_EIMEN; */
3754
3755 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3756 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3757 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3758 }
3759
a34bcfff
AD		 3760 /* Enable fan failure interrupt */
3761 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3762 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3763
2698b208 3764 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3765 gpie |= IXGBE_SDP1_GPIEN;
3766 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3767 }
a34bcfff
AD		 3768
3769 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3770}
3771
3772static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3773{
3774 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3775 int err;
a34bcfff
AD		 3776 u32 ctrl_ext;
3777
3778 ixgbe_get_hw_control(adapter);
3779 ixgbe_setup_gpie(adapter);
e8e26350 3780
9a799d71
AK		 3781 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3782 ixgbe_configure_msix(adapter);
3783 else
3784 ixgbe_configure_msi_and_legacy(adapter);
3785
c6ecf39a
DS		 3786 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3787 if (hw->mac.ops.enable_tx_laser &&
3788 ((hw->phy.multispeed_fiber) ||
9f911707 3789 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3790 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3791 hw->mac.ops.enable_tx_laser(hw);
3792
9a799d71 3793 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3794 ixgbe_napi_enable_all(adapter);
3795
73c4b7cd
AD		 3796 if (ixgbe_is_sfp(hw)) {
3797 ixgbe_sfp_link_config(adapter);
3798 } else {
3799 err = ixgbe_non_sfp_link_config(hw);
3800 if (err)
3801 e_err(probe, "link_config FAILED %d\n", err);
3802 }
3803
021230d4
AV		 3804 /* clear any pending interrupts, may auto mask */
3805 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3806 ixgbe_irq_enable(adapter, true, true);
9a799d71 3807
bf069c97
DS		 3808 /*
3809 * If this adapter has a fan, check to see if we had a failure
3810 * before we enabled the interrupt.
3811 */
3812 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3813 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3814 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3815 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3816 }
3817
1da100bb 3818 /* enable transmits */
477de6ed 3819 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3820
9a799d71
AK		 3821 /* bring the link up in the watchdog, this could race with our first
3822 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3823 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3824 adapter->link_check_timeout = jiffies;
7086400d 3825 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3826
3827 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3828 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3829 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3830 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3831
9a799d71
AK		 3832 return 0;
3833}
3834
d4f80882
AV		 3835void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3836{
3837 WARN_ON(in_interrupt());
7086400d
AD		 3838 /* put off any impending NetWatchDogTimeout */
3839 adapter->netdev->trans_start = jiffies;
3840
d4f80882 3841 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3842 usleep_range(1000, 2000);
d4f80882 3843 ixgbe_down(adapter);
5809a1ae
GR		 3844 /*
3845 * If SR-IOV enabled then wait a bit before bringing the adapter
3846 * back up to give the VFs time to respond to the reset. The
3847 * two second wait is based upon the watchdog timer cycle in
3848 * the VF driver.
3849 */
3850 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3851 msleep(2000);
d4f80882
AV		 3852 ixgbe_up(adapter);
3853 clear_bit(__IXGBE_RESETTING, &adapter->state);
3854}
3855
9a799d71
AK		 3856int ixgbe_up(struct ixgbe_adapter *adapter)
3857{
3858 /* hardware has been reset, we need to reload some things */
3859 ixgbe_configure(adapter);
3860
3861 return ixgbe_up_complete(adapter);
3862}
3863
3864void ixgbe_reset(struct ixgbe_adapter *adapter)
3865{
c44ade9e 3866 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3867 int err;
3868
7086400d
AD		 3869 /* lock SFP init bit to prevent race conditions with the watchdog */
3870 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3871 usleep_range(1000, 2000);
3872
3873 /* clear all SFP and link config related flags while holding SFP_INIT */
3874 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3875 IXGBE_FLAG2_SFP_NEEDS_RESET);
3876 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3877
8ca783ab 3878 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3879 switch (err) {
3880 case 0:
3881 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3882 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3883 break;
3884 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3885 e_dev_err("master disable timed out\n");
da4dd0f7 3886 break;
794caeb2
PWJ		 3887 case IXGBE_ERR_EEPROM_VERSION:
3888 /* We are running on a pre-production device, log a warning */
849c4542
ET		 3889 e_dev_warn("This device is a pre-production adapter/LOM. "
3890 "Please be aware there may be issuesassociated with "
3891 "your hardware. If you are experiencing problems "
3892 "please contact your Intel or hardware "
3893 "representative who provided you with this "
3894 "hardware.\n");
794caeb2 3895 break;
da4dd0f7 3896 default:
849c4542 3897 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3898 }
9a799d71 3899
7086400d
AD		 3900 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3901
9a799d71 3902 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3903 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3904 IXGBE_RAH_AV);
9a799d71
AK		 3905}
3906
9a799d71
AK		 3907/**
3908 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3909 * @rx_ring: ring to free buffers from
3910 **/
b6ec895e 3911static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3912{
b6ec895e 3913 struct device *dev = rx_ring->dev;
9a799d71 3914 unsigned long size;
b6ec895e 3915 u16 i;
9a799d71 3916
84418e3b
AD		 3917 /* ring already cleared, nothing to do */
3918 if (!rx_ring->rx_buffer_info)
3919 return;
9a799d71 3920
84418e3b 3921 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3922 for (i = 0; i < rx_ring->count; i++) {
3923 struct ixgbe_rx_buffer *rx_buffer_info;
3924
3925 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3926 if (rx_buffer_info->dma) {
b6ec895e 3927 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3928 rx_ring->rx_buf_len,
1b507730 3929 DMA_FROM_DEVICE);
9a799d71
AK		 3930 rx_buffer_info->dma = 0;
3931 }
3932 if (rx_buffer_info->skb) {
f8212f97 3933 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3934 rx_buffer_info->skb = NULL;
f8212f97
AD		 3935 do {
3936 struct sk_buff *this = skb;
e8171aaa 3937 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3938 dma_unmap_single(dev,
1b507730 3939 IXGBE_RSC_CB(this)->dma,
e8e9f696 3940 rx_ring->rx_buf_len,
1b507730 3941 DMA_FROM_DEVICE);
fd3686a8 3942 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3943 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3944 }
f8212f97
AD		 3945 skb = skb->prev;
3946 dev_kfree_skb(this);
3947 } while (skb);
9a799d71
AK		 3948 }
3949 if (!rx_buffer_info->page)
3950 continue;
4f57ca6e 3951 if (rx_buffer_info->page_dma) {
b6ec895e 3952 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3953 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3954 rx_buffer_info->page_dma = 0;
3955 }
9a799d71
AK		 3956 put_page(rx_buffer_info->page);
3957 rx_buffer_info->page = NULL;
762f4c57 3958 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3959 }
3960
3961 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3962 memset(rx_ring->rx_buffer_info, 0, size);
3963
3964 /* Zero out the descriptor ring */
3965 memset(rx_ring->desc, 0, rx_ring->size);
3966
3967 rx_ring->next_to_clean = 0;
3968 rx_ring->next_to_use = 0;
9a799d71
AK		 3969}
3970
3971/**
3972 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3973 * @tx_ring: ring to be cleaned
3974 **/
b6ec895e 3975static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3976{
3977 struct ixgbe_tx_buffer *tx_buffer_info;
3978 unsigned long size;
b6ec895e 3979 u16 i;
9a799d71 3980
84418e3b
AD		 3981 /* ring already cleared, nothing to do */
3982 if (!tx_ring->tx_buffer_info)
3983 return;
9a799d71 3984
84418e3b 3985 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3986 for (i = 0; i < tx_ring->count; i++) {
3987 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3988 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3989 }
3990
3991 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3992 memset(tx_ring->tx_buffer_info, 0, size);
3993
3994 /* Zero out the descriptor ring */
3995 memset(tx_ring->desc, 0, tx_ring->size);
3996
3997 tx_ring->next_to_use = 0;
3998 tx_ring->next_to_clean = 0;
9a799d71
AK		 3999}
4000
4001/**
021230d4 4002 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4003 * @adapter: board private structure
4004 **/
021230d4 4005static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4006{
4007 int i;
4008
021230d4 4009 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4010 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4011}
4012
4013/**
021230d4 4014 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4015 * @adapter: board private structure
4016 **/
021230d4 4017static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4018{
4019 int i;
4020
021230d4 4021 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4022 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4023}
4024
e4911d57
AD		 4025static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4026{
4027 struct hlist_node *node, *node2;
4028 struct ixgbe_fdir_filter *filter;
4029
4030 spin_lock(&adapter->fdir_perfect_lock);
4031
4032 hlist_for_each_entry_safe(filter, node, node2,
4033 &adapter->fdir_filter_list, fdir_node) {
4034 hlist_del(&filter->fdir_node);
4035 kfree(filter);
4036 }
4037 adapter->fdir_filter_count = 0;
4038
4039 spin_unlock(&adapter->fdir_perfect_lock);
4040}
4041
9a799d71
AK		 4042void ixgbe_down(struct ixgbe_adapter *adapter)
4043{
4044 struct net_device *netdev = adapter->netdev;
7f821875 4045 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4046 u32 rxctrl;
bf29ee6c 4047 int i;
b25ebfd2 4048 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71
AK		 4049
4050 /* signal that we are down to the interrupt handler */
4051 set_bit(__IXGBE_DOWN, &adapter->state);
4052
4053 /* disable receives */
7f821875
JB		 4054 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4055 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4056
2d39d576
YZ		 4057 /* disable all enabled rx queues */
4058 for (i = 0; i < adapter->num_rx_queues; i++)
4059 /* this call also flushes the previous write */
4060 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4061
032b4325 4062 usleep_range(10000, 20000);
9a799d71 4063
7f821875
JB		 4064 netif_tx_stop_all_queues(netdev);
4065
7086400d 4066 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4067 netif_carrier_off(netdev);
4068 netif_tx_disable(netdev);
4069
4070 ixgbe_irq_disable(adapter);
4071
4072 ixgbe_napi_disable_all(adapter);
4073
d034acf1
AD		 4074 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4075 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4076 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4077
4078 del_timer_sync(&adapter->service_timer);
4079
34cecbbf
AD		 4080 /* disable receive for all VFs and wait one second */
4081 if (adapter->num_vfs) {
4082 /* ping all the active vfs to let them know we are going down */
4083 ixgbe_ping_all_vfs(adapter);
4084
4085 /* Disable all VFTE/VFRE TX/RX */
4086 ixgbe_disable_tx_rx(adapter);
4087
4088 /* Mark all the VFs as inactive */
4089 for (i = 0 ; i < adapter->num_vfs; i++)
4090 adapter->vfinfo[i].clear_to_send = 0;
4091 }
4092
b25ebfd2
PW		 4093 /* Cleanup the affinity_hint CPU mask memory and callback */
4094 for (i = 0; i < num_q_vectors; i++) {
4095 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4096 /* clear the affinity_mask in the IRQ descriptor */
4097 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4098 /* release the CPU mask memory */
4099 free_cpumask_var(q_vector->affinity_mask);
4100 }
4101
7f821875
JB		 4102 /* disable transmits in the hardware now that interrupts are off */
4103 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4104 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4105 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4106 }
34cecbbf
AD		 4107
4108 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4109 switch (hw->mac.type) {
4110 case ixgbe_mac_82599EB:
b93a2226 4111 case ixgbe_mac_X540:
88512539 4112 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4113 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4114 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4115 break;
4116 default:
4117 break;
4118 }
7f821875 4119
6f4a0e45
PL		 4120 if (!pci_channel_offline(adapter->pdev))
4121 ixgbe_reset(adapter);
c6ecf39a
DS		 4122
4123 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4124 if (hw->mac.ops.disable_tx_laser &&
4125 ((hw->phy.multispeed_fiber) ||
9f911707 4126 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4127 (hw->mac.type == ixgbe_mac_82599EB))))
4128 hw->mac.ops.disable_tx_laser(hw);
4129
9a799d71
AK		 4130 ixgbe_clean_all_tx_rings(adapter);
4131 ixgbe_clean_all_rx_rings(adapter);
4132
5dd2d332 4133#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4134 /* since we reset the hardware DCA settings were cleared */
e35ec126 4135 ixgbe_setup_dca(adapter);
96b0e0f6 4136#endif
9a799d71
AK		 4137}
4138
9a799d71 4139/**
021230d4
AV		 4140 * ixgbe_poll - NAPI Rx polling callback
4141 * @napi: structure for representing this polling device
4142 * @budget: how many packets driver is allowed to clean
4143 *
4144 * This function is used for legacy and MSI, NAPI mode
9a799d71 4145 **/
021230d4 4146static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4147{
9a1a69ad 4148 struct ixgbe_q_vector *q_vector =
e8e9f696 4149 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4150 struct ixgbe_adapter *adapter = q_vector->adapter;
9a1a69ad 4151 int tx_clean_complete, work_done = 0;
9a799d71 4152
5dd2d332 4153#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4154 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4155 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4156#endif
4157
4a0b9ca0
PW		 4158 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4159 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
9a799d71 4160
9a1a69ad 4161 if (!tx_clean_complete)
d2c7ddd6
DM		 4162 work_done = budget;
4163
53e52c72
DM		 4164 /* If budget not fully consumed, exit the polling mode */
4165 if (work_done < budget) {
288379f0 4166 napi_complete(napi);
f7554a2b 4167 if (adapter->rx_itr_setting & 1)
bd198058 4168 ixgbe_set_itr(q_vector);
d4f80882 4169 if (!test_bit(__IXGBE_DOWN, &adapter->state))
835462fc 4170 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
9a799d71 4171 }
9a799d71
AK		 4172 return work_done;
4173}
4174
4175/**
4176 * ixgbe_tx_timeout - Respond to a Tx Hang
4177 * @netdev: network interface device structure
4178 **/
4179static void ixgbe_tx_timeout(struct net_device *netdev)
4180{
4181 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4182
4183 /* Do the reset outside of interrupt context */
c83c6cbd 4184 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4185}
4186
4df10466
JB		 4187/**
4188 * ixgbe_set_rss_queues: Allocate queues for RSS
4189 * @adapter: board private structure to initialize
4190 *
4191 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4192 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4193 *
4194 **/
bc97114d
PWJ		 4195static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4196{
4197 bool ret = false;
0cefafad 4198 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4199
4200 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4201 f->mask = 0xF;
4202 adapter->num_rx_queues = f->indices;
4203 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4204 ret = true;
4205 } else {
bc97114d 4206 ret = false;
b9804972
JB		 4207 }
4208
bc97114d
PWJ		 4209 return ret;
4210}
4211
c4cf55e5
PWJ		 4212/**
4213 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4214 * @adapter: board private structure to initialize
4215 *
4216 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4217 * to the original CPU that initiated the Tx session. This runs in addition
4218 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4219 * Rx load across CPUs using RSS.
4220 *
4221 **/
e8e9f696 4222static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4223{
4224 bool ret = false;
4225 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4226
4227 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4228 f_fdir->mask = 0;
4229
4230 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4231 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4232 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4233 adapter->num_tx_queues = f_fdir->indices;
4234 adapter->num_rx_queues = f_fdir->indices;
4235 ret = true;
4236 } else {
4237 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4238 }
4239 return ret;
4240}
4241
0331a832
YZ		 4242#ifdef IXGBE_FCOE
4243/**
4244 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4245 * @adapter: board private structure to initialize
4246 *
4247 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4248 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4249 * rx queues out of the max number of rx queues, instead, it is used as the
4250 * index of the first rx queue used by FCoE.
4251 *
4252 **/
4253static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4254{
0331a832
YZ		 4255 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4256
e5b64635
JF		 4257 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4258 return false;
4259
e901acd6 4260 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4261
e901acd6
JF		 4262 adapter->num_rx_queues = 1;
4263 adapter->num_tx_queues = 1;
e5b64635 4264
e901acd6
JF		 4265 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4266 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4267 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4268 ixgbe_set_fdir_queues(adapter);
4269 else
4270 ixgbe_set_rss_queues(adapter);
e5b64635 4271 }
03ecf91a 4272
e901acd6
JF		 4273 /* adding FCoE rx rings to the end */
4274 f->mask = adapter->num_rx_queues;
4275 adapter->num_rx_queues += f->indices;
4276 adapter->num_tx_queues += f->indices;
0331a832 4277
e5b64635
JF		 4278 return true;
4279}
4280#endif /* IXGBE_FCOE */
4281
e901acd6
JF		 4282/* Artificial max queue cap per traffic class in DCB mode */
4283#define DCB_QUEUE_CAP 8
4284
e5b64635
JF		 4285#ifdef CONFIG_IXGBE_DCB
4286static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4287{
e901acd6
JF		 4288 int per_tc_q, q, i, offset = 0;
4289 struct net_device *dev = adapter->netdev;
4290 int tcs = netdev_get_num_tc(dev);
e5b64635 4291
e901acd6
JF		 4292 if (!tcs)
4293 return false;
e5b64635 4294
e901acd6
JF		 4295 /* Map queue offset and counts onto allocated tx queues */
4296 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4297 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4298
8b1c0b24 4299 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4300 netdev_set_prio_tc_map(dev, i, i);
4301 netdev_set_tc_queue(dev, i, q, offset);
4302 offset += q;
0331a832
YZ		 4303 }
4304
e901acd6
JF		 4305 adapter->num_tx_queues = q * tcs;
4306 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4307
4308#ifdef IXGBE_FCOE
e901acd6
JF		 4309 /* FCoE enabled queues require special configuration indexed
4310 * by feature specific indices and mask. Here we map FCoE
4311 * indices onto the DCB queue pairs allowing FCoE to own
4312 * configuration later.
e5b64635 4313 */
e901acd6
JF		 4314 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4315 int tc;
4316 struct ixgbe_ring_feature *f =
4317 &adapter->ring_feature[RING_F_FCOE];
4318
4319 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4320 f->indices = dev->tc_to_txq[tc].count;
4321 f->mask = dev->tc_to_txq[tc].offset;
4322 }
e5b64635
JF		 4323#endif
4324
e901acd6 4325 return true;
0331a832 4326}
e5b64635 4327#endif
0331a832 4328
1cdd1ec8
GR		 4329/**
4330 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4331 * @adapter: board private structure to initialize
4332 *
4333 * IOV doesn't actually use anything, so just NAK the
4334 * request for now and let the other queue routines
4335 * figure out what to do.
4336 */
4337static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4338{
4339 return false;
4340}
4341
4df10466 4342/*
25985edc 4343 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4344 * @adapter: board private structure to initialize
4345 *
4346 * This is the top level queue allocation routine. The order here is very
4347 * important, starting with the "most" number of features turned on at once,
4348 * and ending with the smallest set of features. This way large combinations
4349 * can be allocated if they're turned on, and smaller combinations are the
4350 * fallthrough conditions.
4351 *
4352 **/
847f53ff 4353static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4354{
1cdd1ec8
GR		 4355 /* Start with base case */
4356 adapter->num_rx_queues = 1;
4357 adapter->num_tx_queues = 1;
4358 adapter->num_rx_pools = adapter->num_rx_queues;
4359 adapter->num_rx_queues_per_pool = 1;
4360
4361 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4362 goto done;
1cdd1ec8 4363
bc97114d
PWJ		 4364#ifdef CONFIG_IXGBE_DCB
4365 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4366 goto done;
bc97114d
PWJ		 4367
4368#endif
e5b64635
JF		 4369#ifdef IXGBE_FCOE
4370 if (ixgbe_set_fcoe_queues(adapter))
4371 goto done;
4372
4373#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4374 if (ixgbe_set_fdir_queues(adapter))
4375 goto done;
4376
bc97114d 4377 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4378 goto done;
4379
4380 /* fallback to base case */
4381 adapter->num_rx_queues = 1;
4382 adapter->num_tx_queues = 1;
4383
4384done:
847f53ff 4385 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4386 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4387 return netif_set_real_num_rx_queues(adapter->netdev,
4388 adapter->num_rx_queues);
b9804972
JB		 4389}
4390
021230d4 4391static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4392 int vectors)
021230d4
AV		 4393{
4394 int err, vector_threshold;
4395
4396 /* We'll want at least 3 (vector_threshold):
4397 * 1) TxQ[0] Cleanup
4398 * 2) RxQ[0] Cleanup
4399 * 3) Other (Link Status Change, etc.)
4400 * 4) TCP Timer (optional)
4401 */
4402 vector_threshold = MIN_MSIX_COUNT;
4403
4404 /* The more we get, the more we will assign to Tx/Rx Cleanup
4405 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4406 * Right now, we simply care about how many we'll get; we'll
4407 * set them up later while requesting irq's.
4408 */
4409 while (vectors >= vector_threshold) {
4410 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4411 vectors);
021230d4
AV		 4412 if (!err) /* Success in acquiring all requested vectors. */
4413 break;
4414 else if (err < 0)
4415 vectors = 0; /* Nasty failure, quit now */
4416 else /* err == number of vectors we should try again with */
4417 vectors = err;
4418 }
4419
4420 if (vectors < vector_threshold) {
4421 /* Can't allocate enough MSI-X interrupts? Oh well.
4422 * This just means we'll go with either a single MSI
4423 * vector or fall back to legacy interrupts.
4424 */
849c4542
ET		 4425 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4426 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4427 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4428 kfree(adapter->msix_entries);
4429 adapter->msix_entries = NULL;
021230d4
AV		 4430 } else {
4431 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4432 /*
4433 * Adjust for only the vectors we'll use, which is minimum
4434 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4435 * vectors we were allocated.
4436 */
4437 adapter->num_msix_vectors = min(vectors,
e8e9f696 4438 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4439 }
4440}
4441
021230d4 4442/**
bc97114d 4443 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4444 * @adapter: board private structure to initialize
4445 *
bc97114d
PWJ		 4446 * Cache the descriptor ring offsets for RSS to the assigned rings.
4447 *
021230d4 4448 **/
bc97114d 4449static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4450{
bc97114d 4451 int i;
bc97114d 4452
9d6b758f
AD		 4453 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4454 return false;
bc97114d 4455
9d6b758f
AD		 4456 for (i = 0; i < adapter->num_rx_queues; i++)
4457 adapter->rx_ring[i]->reg_idx = i;
4458 for (i = 0; i < adapter->num_tx_queues; i++)
4459 adapter->tx_ring[i]->reg_idx = i;
4460
4461 return true;
bc97114d
PWJ		 4462}
4463
4464#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4465
4466/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4467static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4468 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4469{
4470 struct net_device *dev = adapter->netdev;
4471 struct ixgbe_hw *hw = &adapter->hw;
4472 u8 num_tcs = netdev_get_num_tc(dev);
4473
4474 *tx = 0;
4475 *rx = 0;
4476
4477 switch (hw->mac.type) {
4478 case ixgbe_mac_82598EB:
aba70d5e
JF		 4479 *tx = tc << 2;
4480 *rx = tc << 3;
e5b64635
JF		 4481 break;
4482 case ixgbe_mac_82599EB:
4483 case ixgbe_mac_X540:
4484 if (num_tcs == 8) {
4485 if (tc < 3) {
4486 *tx = tc << 5;
4487 *rx = tc << 4;
4488 } else if (tc < 5) {
4489 *tx = ((tc + 2) << 4);
4490 *rx = tc << 4;
4491 } else if (tc < num_tcs) {
4492 *tx = ((tc + 8) << 3);
4493 *rx = tc << 4;
4494 }
4495 } else if (num_tcs == 4) {
4496 *rx = tc << 5;
4497 switch (tc) {
4498 case 0:
4499 *tx = 0;
4500 break;
4501 case 1:
4502 *tx = 64;
4503 break;
4504 case 2:
4505 *tx = 96;
4506 break;
4507 case 3:
4508 *tx = 112;
4509 break;
4510 default:
4511 break;
4512 }
4513 }
4514 break;
4515 default:
4516 break;
4517 }
4518}
4519
bc97114d
PWJ		 4520/**
4521 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4522 * @adapter: board private structure to initialize
4523 *
4524 * Cache the descriptor ring offsets for DCB to the assigned rings.
4525 *
4526 **/
4527static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4528{
e5b64635
JF		 4529 struct net_device *dev = adapter->netdev;
4530 int i, j, k;
4531 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4532
8b1c0b24 4533 if (!num_tcs)
bd508178 4534 return false;
f92ef202 4535
e5b64635
JF		 4536 for (i = 0, k = 0; i < num_tcs; i++) {
4537 unsigned int tx_s, rx_s;
4538 u16 count = dev->tc_to_txq[i].count;
4539
4540 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4541 for (j = 0; j < count; j++, k++) {
4542 adapter->tx_ring[k]->reg_idx = tx_s + j;
4543 adapter->rx_ring[k]->reg_idx = rx_s + j;
4544 adapter->tx_ring[k]->dcb_tc = i;
4545 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4546 }
021230d4 4547 }
e5b64635
JF		 4548
4549 return true;
bc97114d
PWJ		 4550}
4551#endif
4552
c4cf55e5
PWJ		 4553/**
4554 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4555 * @adapter: board private structure to initialize
4556 *
4557 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4558 *
4559 **/
e8e9f696 4560static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4561{
4562 int i;
4563 bool ret = false;
4564
03ecf91a
AD		 4565 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4566 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4567 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4568 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4569 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4570 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4571 ret = true;
4572 }
4573
4574 return ret;
4575}
4576
0331a832
YZ		 4577#ifdef IXGBE_FCOE
4578/**
4579 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4580 * @adapter: board private structure to initialize
4581 *
4582 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4583 *
4584 */
4585static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4586{
0331a832 4587 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4588 int i;
4589 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4590
4591 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4592 return false;
0331a832 4593
bf29ee6c 4594 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4595 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4596 ixgbe_cache_ring_fdir(adapter);
4597 else
4598 ixgbe_cache_ring_rss(adapter);
8faa2a78 4599
bf29ee6c
AD		 4600 fcoe_rx_i = f->mask;
4601 fcoe_tx_i = f->mask;
0331a832 4602 }
bf29ee6c
AD		 4603 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4604 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4605 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4606 }
4607 return true;
0331a832
YZ		 4608}
4609
4610#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4611/**
4612 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4613 * @adapter: board private structure to initialize
4614 *
4615 * SR-IOV doesn't use any descriptor rings but changes the default if
4616 * no other mapping is used.
4617 *
4618 */
4619static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4620{
4a0b9ca0
PW		 4621 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4622 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4623 if (adapter->num_vfs)
4624 return true;
4625 else
4626 return false;
4627}
4628
bc97114d
PWJ		 4629/**
4630 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4631 * @adapter: board private structure to initialize
4632 *
4633 * Once we know the feature-set enabled for the device, we'll cache
4634 * the register offset the descriptor ring is assigned to.
4635 *
4636 * Note, the order the various feature calls is important. It must start with
4637 * the "most" features enabled at the same time, then trickle down to the
4638 * least amount of features turned on at once.
4639 **/
4640static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4641{
4642 /* start with default case */
4a0b9ca0
PW		 4643 adapter->rx_ring[0]->reg_idx = 0;
4644 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4645
1cdd1ec8
GR		 4646 if (ixgbe_cache_ring_sriov(adapter))
4647 return;
4648
e5b64635
JF		 4649#ifdef CONFIG_IXGBE_DCB
4650 if (ixgbe_cache_ring_dcb(adapter))
4651 return;
4652#endif
4653
0331a832
YZ		 4654#ifdef IXGBE_FCOE
4655 if (ixgbe_cache_ring_fcoe(adapter))
4656 return;
0331a832 4657#endif /* IXGBE_FCOE */
bc97114d 4658
c4cf55e5
PWJ		 4659 if (ixgbe_cache_ring_fdir(adapter))
4660 return;
4661
bc97114d
PWJ		 4662 if (ixgbe_cache_ring_rss(adapter))
4663 return;
021230d4
AV		 4664}
4665
9a799d71
AK		 4666/**
4667 * ixgbe_alloc_queues - Allocate memory for all rings
4668 * @adapter: board private structure to initialize
4669 *
4670 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4671 * number of queues at compile-time. The polling_netdev array is
4672 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4673 **/
2f90b865 4674static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4675{
e2ddeba9 4676 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4677
e2ddeba9
ED		 4678 if (nid < 0 || !node_online(nid))
4679 nid = first_online_node;
4680
4681 for (; tx < adapter->num_tx_queues; tx++) {
4682 struct ixgbe_ring *ring;
4683
4684 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4685 if (!ring)
e2ddeba9 4686 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4687 if (!ring)
e2ddeba9 4688 goto err_allocation;
4a0b9ca0 4689 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4690 ring->queue_index = tx;
4691 ring->numa_node = nid;
b6ec895e 4692 ring->dev = &adapter->pdev->dev;
fc77dc3c 4693 ring->netdev = adapter->netdev;
4a0b9ca0 4694
e2ddeba9 4695 adapter->tx_ring[tx] = ring;
021230d4 4696 }
b9804972 4697
e2ddeba9
ED		 4698 for (; rx < adapter->num_rx_queues; rx++) {
4699 struct ixgbe_ring *ring;
4a0b9ca0 4700
e2ddeba9 4701 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4702 if (!ring)
e2ddeba9 4703 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4704 if (!ring)
e2ddeba9
ED		 4705 goto err_allocation;
4706 ring->count = adapter->rx_ring_count;
4707 ring->queue_index = rx;
4708 ring->numa_node = nid;
b6ec895e 4709 ring->dev = &adapter->pdev->dev;
fc77dc3c 4710 ring->netdev = adapter->netdev;
4a0b9ca0 4711
e2ddeba9 4712 adapter->rx_ring[rx] = ring;
021230d4
AV		 4713 }
4714
4715 ixgbe_cache_ring_register(adapter);
4716
4717 return 0;
4718
e2ddeba9
ED		 4719err_allocation:
4720 while (tx)
4721 kfree(adapter->tx_ring[--tx]);
4722
4723 while (rx)
4724 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4725 return -ENOMEM;
4726}
4727
4728/**
4729 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4730 * @adapter: board private structure to initialize
4731 *
4732 * Attempt to configure the interrupts using the best available
4733 * capabilities of the hardware and the kernel.
4734 **/
feea6a57 4735static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4736{
8be0e467 4737 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4738 int err = 0;
4739 int vector, v_budget;
4740
4741 /*
4742 * It's easy to be greedy for MSI-X vectors, but it really
4743 * doesn't do us much good if we have a lot more vectors
4744 * than CPU's. So let's be conservative and only ask for
342bde1b 4745 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4746 */
4747 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4748 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4749
4750 /*
4751 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4752 * hw.mac->max_msix_vectors vectors. With features
4753 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4754 * descriptor queues supported by our device. Thus, we cap it off in
4755 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4756 */
8be0e467 4757 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4758
4759 /* A failure in MSI-X entry allocation isn't fatal, but it does
4760 * mean we disable MSI-X capabilities of the adapter. */
4761 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4762 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4763 if (adapter->msix_entries) {
4764 for (vector = 0; vector < v_budget; vector++)
4765 adapter->msix_entries[vector].entry = vector;
021230d4 4766
7a921c93 4767 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4768
7a921c93
AD		 4769 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4770 goto out;
4771 }
26d27844 4772
7a921c93
AD		 4773 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4774 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4775 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4776 e_err(probe,
03ecf91a 4777 "ATR is not supported while multiple "
45b9f509
AD		 4778 "queues are disabled. Disabling Flow Director\n");
4779 }
c4cf55e5 4780 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4781 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4782 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4783 ixgbe_disable_sriov(adapter);
4784
847f53ff
BH		 4785 err = ixgbe_set_num_queues(adapter);
4786 if (err)
4787 return err;
021230d4 4788
021230d4
AV		 4789 err = pci_enable_msi(adapter->pdev);
4790 if (!err) {
4791 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4792 } else {
849c4542
ET		 4793 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4794 "Unable to allocate MSI interrupt, "
4795 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4796 /* reset err */
4797 err = 0;
4798 }
4799
4800out:
021230d4
AV		 4801 return err;
4802}
4803
7a921c93
AD		 4804/**
4805 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4806 * @adapter: board private structure to initialize
4807 *
4808 * We allocate one q_vector per queue interrupt. If allocation fails we
4809 * return -ENOMEM.
4810 **/
4811static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4812{
4813 int q_idx, num_q_vectors;
4814 struct ixgbe_q_vector *q_vector;
7a921c93
AD		 4815 int (*poll)(struct napi_struct *, int);
4816
4817 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4818 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4819 poll = &ixgbe_clean_rxtx_many;
7a921c93
AD		 4820 } else {
4821 num_q_vectors = 1;
7a921c93
AD		 4822 poll = &ixgbe_poll;
4823 }
4824
4825 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
1a6c14a2 4826 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4827 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4828 if (!q_vector)
4829 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4830 GFP_KERNEL);
7a921c93
AD		 4831 if (!q_vector)
4832 goto err_out;
4833 q_vector->adapter = adapter;
08c8833b 4834 if (q_vector->tx.count && !q_vector->rx.count)
f7554a2b
NS		 4835 q_vector->eitr = adapter->tx_eitr_param;
4836 else
4837 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 4838 q_vector->v_idx = q_idx;
91281fd3 4839 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
7a921c93
AD		 4840 adapter->q_vector[q_idx] = q_vector;
4841 }
4842
4843 return 0;
4844
4845err_out:
4846 while (q_idx) {
4847 q_idx--;
4848 q_vector = adapter->q_vector[q_idx];
4849 netif_napi_del(&q_vector->napi);
4850 kfree(q_vector);
4851 adapter->q_vector[q_idx] = NULL;
4852 }
4853 return -ENOMEM;
4854}
4855
4856/**
4857 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4858 * @adapter: board private structure to initialize
4859 *
4860 * This function frees the memory allocated to the q_vectors. In addition if
4861 * NAPI is enabled it will delete any references to the NAPI struct prior
4862 * to freeing the q_vector.
4863 **/
4864static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4865{
4866 int q_idx, num_q_vectors;
7a921c93 4867
91281fd3 4868 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4869 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4870 else
7a921c93 4871 num_q_vectors = 1;
7a921c93
AD		 4872
4873 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4874 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
7a921c93 4875 adapter->q_vector[q_idx] = NULL;
91281fd3 4876 netif_napi_del(&q_vector->napi);
7a921c93
AD		 4877 kfree(q_vector);
4878 }
4879}
4880
7b25cdba 4881static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4882{
4883 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4884 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4885 pci_disable_msix(adapter->pdev);
4886 kfree(adapter->msix_entries);
4887 adapter->msix_entries = NULL;
4888 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4889 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4890 pci_disable_msi(adapter->pdev);
4891 }
021230d4
AV		 4892}
4893
4894/**
4895 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4896 * @adapter: board private structure to initialize
4897 *
4898 * We determine which interrupt scheme to use based on...
4899 * - Kernel support (MSI, MSI-X)
4900 * - which can be user-defined (via MODULE_PARAM)
4901 * - Hardware queue count (num_*_queues)
4902 * - defined by miscellaneous hardware support/features (RSS, etc.)
4903 **/
2f90b865 4904int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4905{
4906 int err;
4907
4908 /* Number of supported queues */
847f53ff
BH		 4909 err = ixgbe_set_num_queues(adapter);
4910 if (err)
4911 return err;
021230d4 4912
021230d4
AV		 4913 err = ixgbe_set_interrupt_capability(adapter);
4914 if (err) {
849c4542 4915 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4916 goto err_set_interrupt;
9a799d71
AK		 4917 }
4918
7a921c93
AD		 4919 err = ixgbe_alloc_q_vectors(adapter);
4920 if (err) {
849c4542 4921 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4922 goto err_alloc_q_vectors;
4923 }
4924
4925 err = ixgbe_alloc_queues(adapter);
4926 if (err) {
849c4542 4927 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4928 goto err_alloc_queues;
4929 }
4930
849c4542 4931 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4932 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4933 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4934
4935 set_bit(__IXGBE_DOWN, &adapter->state);
4936
9a799d71 4937 return 0;
021230d4 4938
7a921c93
AD		 4939err_alloc_queues:
4940 ixgbe_free_q_vectors(adapter);
4941err_alloc_q_vectors:
4942 ixgbe_reset_interrupt_capability(adapter);
021230d4 4943err_set_interrupt:
7a921c93
AD		 4944 return err;
4945}
4946
4947/**
4948 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4949 * @adapter: board private structure to clear interrupt scheme on
4950 *
4951 * We go through and clear interrupt specific resources and reset the structure
4952 * to pre-load conditions
4953 **/
4954void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4955{
4a0b9ca0
PW		 4956 int i;
4957
4958 for (i = 0; i < adapter->num_tx_queues; i++) {
4959 kfree(adapter->tx_ring[i]);
4960 adapter->tx_ring[i] = NULL;
4961 }
4962 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4963 struct ixgbe_ring *ring = adapter->rx_ring[i];
4964
4965 /* ixgbe_get_stats64() might access this ring, we must wait
4966 * a grace period before freeing it.
4967 */
bcec8b65 4968 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4969 adapter->rx_ring[i] = NULL;
4970 }
7a921c93 4971
b8eb3a10
DS		 4972 adapter->num_tx_queues = 0;
4973 adapter->num_rx_queues = 0;
4974
7a921c93
AD		 4975 ixgbe_free_q_vectors(adapter);
4976 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4977}
4978
4979/**
4980 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4981 * @adapter: board private structure to initialize
4982 *
4983 * ixgbe_sw_init initializes the Adapter private data structure.
4984 * Fields are initialized based on PCI device information and
4985 * OS network device settings (MTU size).
4986 **/
4987static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4988{
4989 struct ixgbe_hw *hw = &adapter->hw;
4990 struct pci_dev *pdev = adapter->pdev;
9a713e7c 4991 struct net_device *dev = adapter->netdev;
021230d4 4992 unsigned int rss;
7a6b6f51 4993#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4994 int j;
4995 struct tc_configuration *tc;
4996#endif
16b61beb 4997 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
021230d4 4998
c44ade9e
JB		 4999 /* PCI config space info */
5000
5001 hw->vendor_id = pdev->vendor;
5002 hw->device_id = pdev->device;
5003 hw->revision_id = pdev->revision;
5004 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5005 hw->subsystem_device_id = pdev->subsystem_device;
5006
021230d4
AV		 5007 /* Set capability flags */
5008 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5009 adapter->ring_feature[RING_F_RSS].indices = rss;
5010 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5011 switch (hw->mac.type) {
5012 case ixgbe_mac_82598EB:
bf069c97
DS		 5013 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5014 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5015 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178
AD		 5016 break;
5017 case ixgbe_mac_82599EB:
b93a2226 5018 case ixgbe_mac_X540:
e8e26350 5019 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5020 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5021 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5022 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5023 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5024 /* Flow Director hash filters enabled */
5025 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5026 adapter->atr_sample_rate = 20;
c4cf55e5 5027 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5028 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5029 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5030#ifdef IXGBE_FCOE
0d551589
YZ		 5031 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5032 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5033 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5034#ifdef CONFIG_IXGBE_DCB
6ee16520 5035 /* Default traffic class to use for FCoE */
56075a98 5036 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5037#endif
eacd73f7 5038#endif /* IXGBE_FCOE */
bd508178
AD		 5039 break;
5040 default:
5041 break;
f8212f97 5042 }
2f90b865 5043
1fc5f038
AD		 5044 /* n-tuple support exists, always init our spinlock */
5045 spin_lock_init(&adapter->fdir_perfect_lock);
5046
7a6b6f51 5047#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5048 /* Configure DCB traffic classes */
5049 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5050 tc = &adapter->dcb_cfg.tc_config[j];
5051 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5052 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5053 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5054 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5055 tc->dcb_pfc = pfc_disabled;
5056 }
5057 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5058 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5059 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5060 adapter->dcb_set_bitmap = 0x00;
3032309b 5061 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5062 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5063 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5064
5065#endif
9a799d71
AK		 5066
5067 /* default flow control settings */
cd7664f6 5068 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5069 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5070#ifdef CONFIG_DCB
5071 adapter->last_lfc_mode = hw->fc.current_mode;
5072#endif
16b61beb
JF		 5073 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5074 hw->fc.low_water = FC_LOW_WATER(max_frame);
2b9ade93
JB		 5075 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5076 hw->fc.send_xon = true;
71fd570b 5077 hw->fc.disable_fc_autoneg = false;
9a799d71 5078
30efa5a3 5079 /* enable itr by default in dynamic mode */
f7554a2b
NS		 5080 adapter->rx_itr_setting = 1;
5081 adapter->rx_eitr_param = 20000;
5082 adapter->tx_itr_setting = 1;
5083 adapter->tx_eitr_param = 10000;
30efa5a3
JB		 5084
5085 /* set defaults for eitr in MegaBytes */
5086 adapter->eitr_low = 10;
5087 adapter->eitr_high = 20;
5088
5089 /* set default ring sizes */
5090 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5091 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5092
bd198058
AD		 5093 /* set default work limits */
5094 adapter->tx_work_limit = adapter->tx_ring_count;
5095
9a799d71 5096 /* initialize eeprom parameters */
c44ade9e 5097 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5098 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5099 return -EIO;
5100 }
5101
021230d4 5102 /* enable rx csum by default */
9a799d71
AK		 5103 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5104
1a6c14a2
JB		 5105 /* get assigned NUMA node */
5106 adapter->node = dev_to_node(&pdev->dev);
5107
9a799d71
AK		 5108 set_bit(__IXGBE_DOWN, &adapter->state);
5109
5110 return 0;
5111}
5112
5113/**
5114 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5115 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5116 *
5117 * Return 0 on success, negative on failure
5118 **/
b6ec895e 5119int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5120{
b6ec895e 5121 struct device *dev = tx_ring->dev;
9a799d71
AK		 5122 int size;
5123
3a581073 5124 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5125 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5126 if (!tx_ring->tx_buffer_info)
89bf67f1 5127 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5128 if (!tx_ring->tx_buffer_info)
5129 goto err;
9a799d71
AK		 5130
5131 /* round up to nearest 4K */
12207e49 5132 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5133 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5134
b6ec895e 5135 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5136 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5137 if (!tx_ring->desc)
5138 goto err;
9a799d71 5139
3a581073
JB		 5140 tx_ring->next_to_use = 0;
5141 tx_ring->next_to_clean = 0;
9a799d71 5142 return 0;
e01c31a5
JB		 5143
5144err:
5145 vfree(tx_ring->tx_buffer_info);
5146 tx_ring->tx_buffer_info = NULL;
b6ec895e 5147 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5148 return -ENOMEM;
9a799d71
AK		 5149}
5150
69888674
AD		 5151/**
5152 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5153 * @adapter: board private structure
5154 *
5155 * If this function returns with an error, then it's possible one or
5156 * more of the rings is populated (while the rest are not). It is the
5157 * callers duty to clean those orphaned rings.
5158 *
5159 * Return 0 on success, negative on failure
5160 **/
5161static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5162{
5163 int i, err = 0;
5164
5165 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5166 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5167 if (!err)
5168 continue;
396e799c 5169 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5170 break;
5171 }
5172
5173 return err;
5174}
5175
9a799d71
AK		 5176/**
5177 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5178 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5179 *
5180 * Returns 0 on success, negative on failure
5181 **/
b6ec895e 5182int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5183{
b6ec895e 5184 struct device *dev = rx_ring->dev;
021230d4 5185 int size;
9a799d71 5186
3a581073 5187 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5188 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5189 if (!rx_ring->rx_buffer_info)
89bf67f1 5190 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5191 if (!rx_ring->rx_buffer_info)
5192 goto err;
9a799d71 5193
9a799d71 5194 /* Round up to nearest 4K */
3a581073
JB		 5195 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5196 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5197
b6ec895e 5198 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5199 &rx_ring->dma, GFP_KERNEL);
9a799d71 5200
b6ec895e
AD		 5201 if (!rx_ring->desc)
5202 goto err;
9a799d71 5203
3a581073
JB		 5204 rx_ring->next_to_clean = 0;
5205 rx_ring->next_to_use = 0;
9a799d71
AK		 5206
5207 return 0;
b6ec895e
AD		 5208err:
5209 vfree(rx_ring->rx_buffer_info);
5210 rx_ring->rx_buffer_info = NULL;
5211 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5212 return -ENOMEM;
9a799d71
AK		 5213}
5214
69888674
AD		 5215/**
5216 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5217 * @adapter: board private structure
5218 *
5219 * If this function returns with an error, then it's possible one or
5220 * more of the rings is populated (while the rest are not). It is the
5221 * callers duty to clean those orphaned rings.
5222 *
5223 * Return 0 on success, negative on failure
5224 **/
69888674
AD		 5225static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5226{
5227 int i, err = 0;
5228
5229 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5230 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5231 if (!err)
5232 continue;
396e799c 5233 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5234 break;
5235 }
5236
5237 return err;
5238}
5239
9a799d71
AK		 5240/**
5241 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5242 * @tx_ring: Tx descriptor ring for a specific queue
5243 *
5244 * Free all transmit software resources
5245 **/
b6ec895e 5246void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5247{
b6ec895e 5248 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5249
5250 vfree(tx_ring->tx_buffer_info);
5251 tx_ring->tx_buffer_info = NULL;
5252
b6ec895e
AD		 5253 /* if not set, then don't free */
5254 if (!tx_ring->desc)
5255 return;
5256
5257 dma_free_coherent(tx_ring->dev, tx_ring->size,
5258 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5259
5260 tx_ring->desc = NULL;
5261}
5262
5263/**
5264 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5265 * @adapter: board private structure
5266 *
5267 * Free all transmit software resources
5268 **/
5269static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5270{
5271 int i;
5272
5273 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5274 if (adapter->tx_ring[i]->desc)
b6ec895e 5275 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5276}
5277
5278/**
b4617240 5279 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5280 * @rx_ring: ring to clean the resources from
5281 *
5282 * Free all receive software resources
5283 **/
b6ec895e 5284void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5285{
b6ec895e 5286 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5287
5288 vfree(rx_ring->rx_buffer_info);
5289 rx_ring->rx_buffer_info = NULL;
5290
b6ec895e
AD		 5291 /* if not set, then don't free */
5292 if (!rx_ring->desc)
5293 return;
5294
5295 dma_free_coherent(rx_ring->dev, rx_ring->size,
5296 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5297
5298 rx_ring->desc = NULL;
5299}
5300
5301/**
5302 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5303 * @adapter: board private structure
5304 *
5305 * Free all receive software resources
5306 **/
5307static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5308{
5309 int i;
5310
5311 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5312 if (adapter->rx_ring[i]->desc)
b6ec895e 5313 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5314}
5315
9a799d71
AK		 5316/**
5317 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5318 * @netdev: network interface device structure
5319 * @new_mtu: new value for maximum frame size
5320 *
5321 * Returns 0 on success, negative on failure
5322 **/
5323static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5324{
5325 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5326 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5327 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5328
42c783c5 5329 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5330 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5331 hw->mac.type != ixgbe_mac_X540) {
5332 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5333 return -EINVAL;
5334 } else {
5335 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5336 return -EINVAL;
5337 }
9a799d71 5338
396e799c 5339 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5340 /* must set new MTU before calling down or up */
9a799d71
AK		 5341 netdev->mtu = new_mtu;
5342
16b61beb
JF		 5343 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5344 hw->fc.low_water = FC_LOW_WATER(max_frame);
5345
d4f80882
AV		 5346 if (netif_running(netdev))
5347 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5348
5349 return 0;
5350}
5351
5352/**
5353 * ixgbe_open - Called when a network interface is made active
5354 * @netdev: network interface device structure
5355 *
5356 * Returns 0 on success, negative value on failure
5357 *
5358 * The open entry point is called when a network interface is made
5359 * active by the system (IFF_UP). At this point all resources needed
5360 * for transmit and receive operations are allocated, the interrupt
5361 * handler is registered with the OS, the watchdog timer is started,
5362 * and the stack is notified that the interface is ready.
5363 **/
5364static int ixgbe_open(struct net_device *netdev)
5365{
5366 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5367 int err;
4bebfaa5
AK		 5368
5369 /* disallow open during test */
5370 if (test_bit(__IXGBE_TESTING, &adapter->state))
5371 return -EBUSY;
9a799d71 5372
54386467
JB		 5373 netif_carrier_off(netdev);
5374
9a799d71
AK		 5375 /* allocate transmit descriptors */
5376 err = ixgbe_setup_all_tx_resources(adapter);
5377 if (err)
5378 goto err_setup_tx;
5379
9a799d71
AK		 5380 /* allocate receive descriptors */
5381 err = ixgbe_setup_all_rx_resources(adapter);
5382 if (err)
5383 goto err_setup_rx;
5384
5385 ixgbe_configure(adapter);
5386
021230d4 5387 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5388 if (err)
5389 goto err_req_irq;
5390
9a799d71
AK		 5391 err = ixgbe_up_complete(adapter);
5392 if (err)
5393 goto err_up;
5394
d55b53ff
JK		 5395 netif_tx_start_all_queues(netdev);
5396
9a799d71
AK		 5397 return 0;
5398
5399err_up:
5eba3699 5400 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5401 ixgbe_free_irq(adapter);
5402err_req_irq:
9a799d71 5403err_setup_rx:
a20a1199 5404 ixgbe_free_all_rx_resources(adapter);
9a799d71 5405err_setup_tx:
a20a1199 5406 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5407 ixgbe_reset(adapter);
5408
5409 return err;
5410}
5411
5412/**
5413 * ixgbe_close - Disables a network interface
5414 * @netdev: network interface device structure
5415 *
5416 * Returns 0, this is not allowed to fail
5417 *
5418 * The close entry point is called when an interface is de-activated
5419 * by the OS. The hardware is still under the drivers control, but
5420 * needs to be disabled. A global MAC reset is issued to stop the
5421 * hardware, and all transmit and receive resources are freed.
5422 **/
5423static int ixgbe_close(struct net_device *netdev)
5424{
5425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5426
5427 ixgbe_down(adapter);
5428 ixgbe_free_irq(adapter);
5429
e4911d57
AD		 5430 ixgbe_fdir_filter_exit(adapter);
5431
9a799d71
AK		 5432 ixgbe_free_all_tx_resources(adapter);
5433 ixgbe_free_all_rx_resources(adapter);
5434
5eba3699 5435 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5436
5437 return 0;
5438}
5439
b3c8b4ba
AD		 5440#ifdef CONFIG_PM
5441static int ixgbe_resume(struct pci_dev *pdev)
5442{
c60fbb00
AD		 5443 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5444 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5445 u32 err;
5446
5447 pci_set_power_state(pdev, PCI_D0);
5448 pci_restore_state(pdev);
656ab817
DS		 5449 /*
5450 * pci_restore_state clears dev->state_saved so call
5451 * pci_save_state to restore it.
5452 */
5453 pci_save_state(pdev);
9ce77666 5454
5455 err = pci_enable_device_mem(pdev);
b3c8b4ba 5456 if (err) {
849c4542 5457 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5458 return err;
5459 }
5460 pci_set_master(pdev);
5461
dd4d8ca6 5462 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5463
5464 err = ixgbe_init_interrupt_scheme(adapter);
5465 if (err) {
849c4542 5466 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5467 return err;
5468 }
5469
b3c8b4ba
AD		 5470 ixgbe_reset(adapter);
5471
495dce12
WJP		 5472 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5473
b3c8b4ba 5474 if (netif_running(netdev)) {
c60fbb00 5475 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5476 if (err)
5477 return err;
5478 }
5479
5480 netif_device_attach(netdev);
5481
5482 return 0;
5483}
b3c8b4ba 5484#endif /* CONFIG_PM */
9d8d05ae
RW		 5485
5486static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5487{
c60fbb00
AD		 5488 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5489 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5490 struct ixgbe_hw *hw = &adapter->hw;
5491 u32 ctrl, fctrl;
5492 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5493#ifdef CONFIG_PM
5494 int retval = 0;
5495#endif
5496
5497 netif_device_detach(netdev);
5498
5499 if (netif_running(netdev)) {
5500 ixgbe_down(adapter);
5501 ixgbe_free_irq(adapter);
5502 ixgbe_free_all_tx_resources(adapter);
5503 ixgbe_free_all_rx_resources(adapter);
5504 }
b3c8b4ba 5505
5f5ae6fc 5506 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5507#ifdef CONFIG_DCB
5508 kfree(adapter->ixgbe_ieee_pfc);
5509 kfree(adapter->ixgbe_ieee_ets);
5510#endif
5f5ae6fc 5511
b3c8b4ba
AD		 5512#ifdef CONFIG_PM
5513 retval = pci_save_state(pdev);
5514 if (retval)
5515 return retval;
4df10466 5516
b3c8b4ba 5517#endif
e8e26350
PW		 5518 if (wufc) {
5519 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5520
e8e26350
PW		 5521 /* turn on all-multi mode if wake on multicast is enabled */
5522 if (wufc & IXGBE_WUFC_MC) {
5523 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5524 fctrl |= IXGBE_FCTRL_MPE;
5525 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5526 }
5527
5528 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5529 ctrl |= IXGBE_CTRL_GIO_DIS;
5530 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5531
5532 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5533 } else {
5534 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5535 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5536 }
5537
bd508178
AD		 5538 switch (hw->mac.type) {
5539 case ixgbe_mac_82598EB:
dd4d8ca6 5540 pci_wake_from_d3(pdev, false);
bd508178
AD		 5541 break;
5542 case ixgbe_mac_82599EB:
b93a2226 5543 case ixgbe_mac_X540:
bd508178
AD		 5544 pci_wake_from_d3(pdev, !!wufc);
5545 break;
5546 default:
5547 break;
5548 }
b3c8b4ba 5549
9d8d05ae
RW		 5550 *enable_wake = !!wufc;
5551
b3c8b4ba
AD		 5552 ixgbe_release_hw_control(adapter);
5553
5554 pci_disable_device(pdev);
5555
9d8d05ae
RW		 5556 return 0;
5557}
5558
5559#ifdef CONFIG_PM
5560static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5561{
5562 int retval;
5563 bool wake;
5564
5565 retval = __ixgbe_shutdown(pdev, &wake);
5566 if (retval)
5567 return retval;
5568
5569 if (wake) {
5570 pci_prepare_to_sleep(pdev);
5571 } else {
5572 pci_wake_from_d3(pdev, false);
5573 pci_set_power_state(pdev, PCI_D3hot);
5574 }
b3c8b4ba
AD		 5575
5576 return 0;
5577}
9d8d05ae 5578#endif /* CONFIG_PM */
b3c8b4ba
AD		 5579
5580static void ixgbe_shutdown(struct pci_dev *pdev)
5581{
9d8d05ae
RW		 5582 bool wake;
5583
5584 __ixgbe_shutdown(pdev, &wake);
5585
5586 if (system_state == SYSTEM_POWER_OFF) {
5587 pci_wake_from_d3(pdev, wake);
5588 pci_set_power_state(pdev, PCI_D3hot);
5589 }
b3c8b4ba
AD		 5590}
5591
9a799d71
AK		 5592/**
5593 * ixgbe_update_stats - Update the board statistics counters.
5594 * @adapter: board private structure
5595 **/
5596void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5597{
2d86f139 5598 struct net_device *netdev = adapter->netdev;
9a799d71 5599 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5600 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5601 u64 total_mpc = 0;
5602 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5603 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5604 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5605 u64 bytes = 0, packets = 0;
9a799d71 5606
d08935c2
DS		 5607 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5608 test_bit(__IXGBE_RESETTING, &adapter->state))
5609 return;
5610
94b982b2 5611 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5612 u64 rsc_count = 0;
94b982b2 5613 u64 rsc_flush = 0;
d51019a4
PW		 5614 for (i = 0; i < 16; i++)
5615 adapter->hw_rx_no_dma_resources +=
7ca647bd 5616 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5617 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5618 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5619 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5620 }
5621 adapter->rsc_total_count = rsc_count;
5622 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5623 }
5624
5b7da515
AD		 5625 for (i = 0; i < adapter->num_rx_queues; i++) {
5626 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5627 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5628 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5629 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5630 bytes += rx_ring->stats.bytes;
5631 packets += rx_ring->stats.packets;
5632 }
5633 adapter->non_eop_descs = non_eop_descs;
5634 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5635 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5636 netdev->stats.rx_bytes = bytes;
5637 netdev->stats.rx_packets = packets;
5638
5639 bytes = 0;
5640 packets = 0;
7ca3bc58 5641 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5642 for (i = 0; i < adapter->num_tx_queues; i++) {
5643 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5644 restart_queue += tx_ring->tx_stats.restart_queue;
5645 tx_busy += tx_ring->tx_stats.tx_busy;
5646 bytes += tx_ring->stats.bytes;
5647 packets += tx_ring->stats.packets;
5648 }
eb985f09 5649 adapter->restart_queue = restart_queue;
5b7da515
AD		 5650 adapter->tx_busy = tx_busy;
5651 netdev->stats.tx_bytes = bytes;
5652 netdev->stats.tx_packets = packets;
7ca3bc58 5653
7ca647bd 5654 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6f11eef7
AV		 5655 for (i = 0; i < 8; i++) {
5656 /* for packet buffers not used, the register should read 0 */
5657 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5658 missed_rx += mpc;
7ca647bd
JP		 5659 hwstats->mpc[i] += mpc;
5660 total_mpc += hwstats->mpc[i];
e8e26350 5661 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5662 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5663 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5664 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5665 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5666 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
bd508178
AD		 5667 switch (hw->mac.type) {
5668 case ixgbe_mac_82598EB:
7ca647bd
JP		 5669 hwstats->pxonrxc[i] +=
5670 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5671 break;
5672 case ixgbe_mac_82599EB:
b93a2226 5673 case ixgbe_mac_X540:
bd508178
AD		 5674 hwstats->pxonrxc[i] +=
5675 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5676 break;
5677 default:
5678 break;
e8e26350 5679 }
7ca647bd
JP		 5680 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5681 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6f11eef7 5682 }
7ca647bd 5683 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5684 /* work around hardware counting issue */
7ca647bd 5685 hwstats->gprc -= missed_rx;
6f11eef7 5686
c84d324c
JF		 5687 ixgbe_update_xoff_received(adapter);
5688
6f11eef7 5689 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5690 switch (hw->mac.type) {
5691 case ixgbe_mac_82598EB:
5692 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5693 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5694 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5695 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5696 break;
b93a2226 5697 case ixgbe_mac_X540:
58f6bcf9
ET		 5698 /* OS2BMC stats are X540 only*/
5699 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5700 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5701 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5702 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5703 case ixgbe_mac_82599EB:
7ca647bd 5704 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5705 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5706 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5707 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5708 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5709 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5710 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5711 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5712 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5713#ifdef IXGBE_FCOE
7ca647bd
JP		 5714 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5715 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5716 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5717 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5718 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5719 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6d45522c 5720#endif /* IXGBE_FCOE */
bd508178
AD		 5721 break;
5722 default:
5723 break;
e8e26350 5724 }
9a799d71 5725 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5726 hwstats->bprc += bprc;
5727 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5728 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5729 hwstats->mprc -= bprc;
5730 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5731 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5732 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5733 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5734 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5735 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5736 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5737 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5738 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5739 hwstats->lxontxc += lxon;
6f11eef7 5740 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd
JP		 5741 hwstats->lxofftxc += lxoff;
5742 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5743 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5744 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5745 /*
5746 * 82598 errata - tx of flow control packets is included in tx counters
5747 */
5748 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5749 hwstats->gptc -= xon_off_tot;
5750 hwstats->mptc -= xon_off_tot;
5751 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5752 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5753 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5754 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5755 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5756 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5757 hwstats->ptc64 -= xon_off_tot;
5758 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5759 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5760 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5761 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5762 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5763 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5764
5765 /* Fill out the OS statistics structure */
7ca647bd 5766 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5767
5768 /* Rx Errors */
7ca647bd 5769 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5770 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5771 netdev->stats.rx_length_errors = hwstats->rlec;
5772 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5773 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5774}
5775
5776/**
d034acf1
AD		 5777 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5778 * @adapter - pointer to the device adapter structure
9a799d71 5779 **/
d034acf1 5780static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5781{
cf8280ee 5782 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5783 int i;
cf8280ee 5784
d034acf1
AD		 5785 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5786 return;
5787
5788 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5789
d034acf1 5790 /* if interface is down do nothing */
fe49f04a 5791 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5792 return;
5793
5794 /* do nothing if we are not using signature filters */
5795 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5796 return;
5797
5798 adapter->fdir_overflow++;
5799
93c52dd0
AD		 5800 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5801 for (i = 0; i < adapter->num_tx_queues; i++)
5802 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5803 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5804 /* re-enable flow director interrupts */
5805 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5806 } else {
5807 e_err(probe, "failed to finish FDIR re-initialization, "
5808 "ignored adding FDIR ATR filters\n");
5809 }
93c52dd0
AD		 5810}
5811
5812/**
5813 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5814 * @adapter - pointer to the device adapter structure
5815 *
5816 * This function serves two purposes. First it strobes the interrupt lines
5817 * in order to make certain interrupts are occuring. Secondly it sets the
5818 * bits needed to check for TX hangs. As a result we should immediately
5819 * determine if a hang has occured.
5820 */
5821static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5822{
cf8280ee 5823 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5824 u64 eics = 0;
5825 int i;
cf8280ee 5826
93c52dd0
AD		 5827 /* If we're down or resetting, just bail */
5828 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5829 test_bit(__IXGBE_RESETTING, &adapter->state))
5830 return;
22d5a71b 5831
93c52dd0
AD		 5832 /* Force detection of hung controller */
5833 if (netif_carrier_ok(adapter->netdev)) {
5834 for (i = 0; i < adapter->num_tx_queues; i++)
5835 set_check_for_tx_hang(adapter->tx_ring[i]);
5836 }
22d5a71b 5837
fe49f04a
AD		 5838 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5839 /*
5840 * for legacy and MSI interrupts don't set any bits
5841 * that are enabled for EIAM, because this operation
5842 * would set *both* EIMS and EICS for any bit in EIAM
5843 */
5844 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5845 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5846 } else {
5847 /* get one bit for every active tx/rx interrupt vector */
5848 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5849 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5850 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5851 eics |= ((u64)1 << i);
5852 }
cf8280ee 5853 }
9a799d71 5854
93c52dd0 5855 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5856 ixgbe_irq_rearm_queues(adapter, eics);
5857
cf8280ee
JB		 5858}
5859
e8e26350 5860/**
93c52dd0
AD		 5861 * ixgbe_watchdog_update_link - update the link status
5862 * @adapter - pointer to the device adapter structure
5863 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5864 **/
93c52dd0 5865static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5866{
e8e26350 5867 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5868 u32 link_speed = adapter->link_speed;
5869 bool link_up = adapter->link_up;
c4cf55e5 5870 int i;
e8e26350 5871
93c52dd0
AD		 5872 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5873 return;
5874
5875 if (hw->mac.ops.check_link) {
5876 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5877 } else {
93c52dd0
AD		 5878 /* always assume link is up, if no check link function */
5879 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5880 link_up = true;
c4cf55e5 5881 }
93c52dd0
AD		 5882 if (link_up) {
5883 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5884 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5885 hw->mac.ops.fc_enable(hw, i);
5886 } else {
5887 hw->mac.ops.fc_enable(hw, 0);
5888 }
5889 }
5890
5891 if (link_up ||
5892 time_after(jiffies, (adapter->link_check_timeout +
5893 IXGBE_TRY_LINK_TIMEOUT))) {
5894 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5895 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5896 IXGBE_WRITE_FLUSH(hw);
5897 }
5898
5899 adapter->link_up = link_up;
5900 adapter->link_speed = link_speed;
e8e26350
PW		 5901}
5902
5903/**
93c52dd0
AD		 5904 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5905 * print link up message
5906 * @adapter - pointer to the device adapter structure
e8e26350 5907 **/
93c52dd0 5908static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5909{
93c52dd0 5910 struct net_device *netdev = adapter->netdev;
e8e26350 5911 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5912 u32 link_speed = adapter->link_speed;
5913 bool flow_rx, flow_tx;
e8e26350 5914
93c52dd0
AD		 5915 /* only continue if link was previously down */
5916 if (netif_carrier_ok(netdev))
a985b6c3 5917 return;
63d6e1d8 5918
93c52dd0 5919 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5920
93c52dd0
AD		 5921 switch (hw->mac.type) {
5922 case ixgbe_mac_82598EB: {
5923 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5924 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5925 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5926 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5927 }
5928 break;
5929 case ixgbe_mac_X540:
5930 case ixgbe_mac_82599EB: {
5931 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5932 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5933 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5934 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5935 }
5936 break;
5937 default:
5938 flow_tx = false;
5939 flow_rx = false;
5940 break;
e8e26350 5941 }
93c52dd0
AD		 5942 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5943 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5944 "10 Gbps" :
5945 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5946 "1 Gbps" :
5947 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5948 "100 Mbps" :
5949 "unknown speed"))),
5950 ((flow_rx && flow_tx) ? "RX/TX" :
5951 (flow_rx ? "RX" :
5952 (flow_tx ? "TX" : "None"))));
e8e26350 5953
93c52dd0 5954 netif_carrier_on(netdev);
93c52dd0 5955 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5956}
5957
c4cf55e5 5958/**
93c52dd0
AD		 5959 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5960 * print link down message
5961 * @adapter - pointer to the adapter structure
c4cf55e5 5962 **/
93c52dd0 5963static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5964{
cf8280ee 5965 struct net_device *netdev = adapter->netdev;
c4cf55e5 5966 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5967
93c52dd0
AD		 5968 adapter->link_up = false;
5969 adapter->link_speed = 0;
cf8280ee 5970
93c52dd0
AD		 5971 /* only continue if link was up previously */
5972 if (!netif_carrier_ok(netdev))
5973 return;
264857b8 5974
93c52dd0
AD		 5975 /* poll for SFP+ cable when link is down */
5976 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5977 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5978
93c52dd0
AD		 5979 e_info(drv, "NIC Link is Down\n");
5980 netif_carrier_off(netdev);
5981}
e8e26350 5982
93c52dd0
AD		 5983/**
5984 * ixgbe_watchdog_flush_tx - flush queues on link down
5985 * @adapter - pointer to the device adapter structure
5986 **/
5987static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5988{
c4cf55e5 5989 int i;
93c52dd0 5990 int some_tx_pending = 0;
c4cf55e5 5991
93c52dd0 5992 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5993 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5994 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5995 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5996 some_tx_pending = 1;
5997 break;
5998 }
5999 }
6000
6001 if (some_tx_pending) {
6002 /* We've lost link, so the controller stops DMA,
6003 * but we've got queued Tx work that's never going
6004 * to get done, so reset controller to flush Tx.
6005 * (Do the reset outside of interrupt context).
6006 */
c83c6cbd 6007 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6008 }
c4cf55e5 6009 }
c4cf55e5
PWJ		 6010}
6011
a985b6c3
GR		 6012static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6013{
6014 u32 ssvpc;
6015
6016 /* Do not perform spoof check for 82598 */
6017 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6018 return;
6019
6020 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6021
6022 /*
6023 * ssvpc register is cleared on read, if zero then no
6024 * spoofed packets in the last interval.
6025 */
6026 if (!ssvpc)
6027 return;
6028
6029 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6030}
6031
93c52dd0
AD		 6032/**
6033 * ixgbe_watchdog_subtask - check and bring link up
6034 * @adapter - pointer to the device adapter structure
6035 **/
6036static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6037{
6038 /* if interface is down do nothing */
6039 if (test_bit(__IXGBE_DOWN, &adapter->state))
6040 return;
6041
6042 ixgbe_watchdog_update_link(adapter);
6043
6044 if (adapter->link_up)
6045 ixgbe_watchdog_link_is_up(adapter);
6046 else
6047 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6048
a985b6c3 6049 ixgbe_spoof_check(adapter);
9a799d71 6050 ixgbe_update_stats(adapter);
93c52dd0
AD		 6051
6052 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6053}
10eec955 6054
cf8280ee 6055/**
7086400d
AD		 6056 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6057 * @adapter - the ixgbe adapter structure
cf8280ee 6058 **/
7086400d 6059static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6060{
cf8280ee 6061 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6062 s32 err;
cf8280ee 6063
7086400d
AD		 6064 /* not searching for SFP so there is nothing to do here */
6065 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6066 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6067 return;
10eec955 6068
7086400d
AD		 6069 /* someone else is in init, wait until next service event */
6070 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6071 return;
cf8280ee 6072
7086400d
AD		 6073 err = hw->phy.ops.identify_sfp(hw);
6074 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6075 goto sfp_out;
264857b8 6076
7086400d
AD		 6077 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6078 /* If no cable is present, then we need to reset
6079 * the next time we find a good cable. */
6080 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6081 }
9a799d71 6082
7086400d
AD		 6083 /* exit on error */
6084 if (err)
6085 goto sfp_out;
e8e26350 6086
7086400d
AD		 6087 /* exit if reset not needed */
6088 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6089 goto sfp_out;
9a799d71 6090
7086400d 6091 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6092
7086400d
AD		 6093 /*
6094 * A module may be identified correctly, but the EEPROM may not have
6095 * support for that module. setup_sfp() will fail in that case, so
6096 * we should not allow that module to load.
6097 */
6098 if (hw->mac.type == ixgbe_mac_82598EB)
6099 err = hw->phy.ops.reset(hw);
6100 else
6101 err = hw->mac.ops.setup_sfp(hw);
6102
6103 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6104 goto sfp_out;
6105
6106 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6107 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6108
6109sfp_out:
6110 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6111
6112 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6113 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6114 e_dev_err("failed to initialize because an unsupported "
6115 "SFP+ module type was detected.\n");
6116 e_dev_err("Reload the driver after installing a "
6117 "supported module.\n");
6118 unregister_netdev(adapter->netdev);
bc59fcda 6119 }
7086400d 6120}
bc59fcda 6121
7086400d
AD		 6122/**
6123 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6124 * @adapter - the ixgbe adapter structure
6125 **/
6126static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6127{
6128 struct ixgbe_hw *hw = &adapter->hw;
6129 u32 autoneg;
6130 bool negotiation;
6131
6132 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6133 return;
6134
6135 /* someone else is in init, wait until next service event */
6136 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6137 return;
6138
6139 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6140
6141 autoneg = hw->phy.autoneg_advertised;
6142 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6143 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6144 hw->mac.autotry_restart = false;
6145 if (hw->mac.ops.setup_link)
6146 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6147
6148 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6149 adapter->link_check_timeout = jiffies;
6150 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6151}
6152
6153/**
6154 * ixgbe_service_timer - Timer Call-back
6155 * @data: pointer to adapter cast into an unsigned long
6156 **/
6157static void ixgbe_service_timer(unsigned long data)
6158{
6159 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6160 unsigned long next_event_offset;
6161
6162 /* poll faster when waiting for link */
6163 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6164 next_event_offset = HZ / 10;
6165 else
6166 next_event_offset = HZ * 2;
6167
6168 /* Reset the timer */
6169 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6170
6171 ixgbe_service_event_schedule(adapter);
6172}
6173
c83c6cbd
AD		 6174static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6175{
6176 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6177 return;
6178
6179 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6180
6181 /* If we're already down or resetting, just bail */
6182 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6183 test_bit(__IXGBE_RESETTING, &adapter->state))
6184 return;
6185
6186 ixgbe_dump(adapter);
6187 netdev_err(adapter->netdev, "Reset adapter\n");
6188 adapter->tx_timeout_count++;
6189
6190 ixgbe_reinit_locked(adapter);
6191}
6192
7086400d
AD		 6193/**
6194 * ixgbe_service_task - manages and runs subtasks
6195 * @work: pointer to work_struct containing our data
6196 **/
6197static void ixgbe_service_task(struct work_struct *work)
6198{
6199 struct ixgbe_adapter *adapter = container_of(work,
6200 struct ixgbe_adapter,
6201 service_task);
6202
c83c6cbd 6203 ixgbe_reset_subtask(adapter);
7086400d
AD		 6204 ixgbe_sfp_detection_subtask(adapter);
6205 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6206 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6207 ixgbe_watchdog_subtask(adapter);
d034acf1 6208 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6209 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6210
6211 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6212}
6213
897ab156
AD		 6214void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6215 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6216{
6217 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6218 u16 i = tx_ring->next_to_use;
9a799d71 6219
897ab156 6220 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6221
897ab156
AD		 6222 i++;
6223 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6224
897ab156
AD		 6225 /* set bits to identify this as an advanced context descriptor */
6226 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6227
897ab156
AD		 6228 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6229 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6230 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6231 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6232}
9a799d71 6233
897ab156
AD		 6234static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6235 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6236{
6237 int err;
6238 u32 vlan_macip_lens, type_tucmd;
6239 u32 mss_l4len_idx, l4len;
9a799d71 6240
897ab156
AD		 6241 if (!skb_is_gso(skb))
6242 return 0;
9a799d71 6243
897ab156
AD		 6244 if (skb_header_cloned(skb)) {
6245 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6246 if (err)
6247 return err;
9a799d71 6248 }
9a799d71 6249
897ab156
AD		 6250 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6251 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6252
6253 if (protocol == __constant_htons(ETH_P_IP)) {
6254 struct iphdr *iph = ip_hdr(skb);
6255 iph->tot_len = 0;
6256 iph->check = 0;
6257 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6258 iph->daddr, 0,
6259 IPPROTO_TCP,
6260 0);
6261 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6262 } else if (skb_is_gso_v6(skb)) {
6263 ipv6_hdr(skb)->payload_len = 0;
6264 tcp_hdr(skb)->check =
6265 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6266 &ipv6_hdr(skb)->daddr,
6267 0, IPPROTO_TCP, 0);
6268 }
6269
6270 l4len = tcp_hdrlen(skb);
6271 *hdr_len = skb_transport_offset(skb) + l4len;
6272
6273 /* mss_l4len_id: use 1 as index for TSO */
6274 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6275 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6276 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6277
6278 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6279 vlan_macip_lens = skb_network_header_len(skb);
6280 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6281 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6282
6283 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6284 mss_l4len_idx);
6285
6286 return 1;
6287}
6288
6289static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6290 struct sk_buff *skb, u32 tx_flags,
6291 __be16 protocol)
7ca647bd 6292{
897ab156
AD		 6293 u32 vlan_macip_lens = 0;
6294 u32 mss_l4len_idx = 0;
6295 u32 type_tucmd = 0;
7ca647bd 6296
897ab156 6297 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6298 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6299 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6300 return false;
6301 } else {
6302 u8 l4_hdr = 0;
6303 switch (protocol) {
6304 case __constant_htons(ETH_P_IP):
6305 vlan_macip_lens |= skb_network_header_len(skb);
6306 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6307 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6308 break;
897ab156
AD		 6309 case __constant_htons(ETH_P_IPV6):
6310 vlan_macip_lens |= skb_network_header_len(skb);
6311 l4_hdr = ipv6_hdr(skb)->nexthdr;
6312 break;
6313 default:
6314 if (unlikely(net_ratelimit())) {
6315 dev_warn(tx_ring->dev,
6316 "partial checksum but proto=%x!\n",
6317 skb->protocol);
6318 }
7ca647bd
JP		 6319 break;
6320 }
897ab156
AD		 6321
6322 switch (l4_hdr) {
7ca647bd 6323 case IPPROTO_TCP:
897ab156
AD		 6324 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6325 mss_l4len_idx = tcp_hdrlen(skb) <<
6326 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6327 break;
6328 case IPPROTO_SCTP:
897ab156
AD		 6329 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6330 mss_l4len_idx = sizeof(struct sctphdr) <<
6331 IXGBE_ADVTXD_L4LEN_SHIFT;
6332 break;
6333 case IPPROTO_UDP:
6334 mss_l4len_idx = sizeof(struct udphdr) <<
6335 IXGBE_ADVTXD_L4LEN_SHIFT;
6336 break;
6337 default:
6338 if (unlikely(net_ratelimit())) {
6339 dev_warn(tx_ring->dev,
6340 "partial checksum but l4 proto=%x!\n",
6341 skb->protocol);
6342 }
7ca647bd
JP		 6343 break;
6344 }
7ca647bd
JP		 6345 }
6346
897ab156
AD		 6347 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6348 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6349
897ab156
AD		 6350 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6351 type_tucmd, mss_l4len_idx);
9a799d71 6352
897ab156 6353 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6354}
6355
d3d00239 6356static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6357{
d3d00239
AD		 6358 /* set type for advanced descriptor with frame checksum insertion */
6359 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6360 IXGBE_ADVTXD_DCMD_IFCS |
6361 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6362
d3d00239 6363 /* set HW vlan bit if vlan is present */
66f32a8b 6364 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6365 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6366
d3d00239
AD		 6367 /* set segmentation enable bits for TSO/FSO */
6368#ifdef IXGBE_FCOE
6369 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6370#else
6371 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6372#endif
6373 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6374
d3d00239
AD		 6375 return cmd_type;
6376}
9a799d71 6377
d3d00239
AD		 6378static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6379{
6380 __le32 olinfo_status =
6381 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6382
d3d00239
AD		 6383 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6384 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6385 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6386 /* enble IPv4 checksum for TSO */
6387 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6388 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6389 }
6390
d3d00239
AD		 6391 /* enable L4 checksum for TSO and TX checksum offload */
6392 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6393 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6394
d3d00239
AD		 6395#ifdef IXGBE_FCOE
6396 /* use index 1 context for FCOE/FSO */
6397 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6398 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6399 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6400
d3d00239 6401#endif
7f9643fd
AD		 6402 /*
6403 * Check Context must be set if Tx switch is enabled, which it
6404 * always is for case where virtual functions are running
6405 */
6406 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6407 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6408
d3d00239
AD		 6409 return olinfo_status;
6410}
44df32c5 6411
d3d00239
AD		 6412#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6413 IXGBE_TXD_CMD_RS)
6414
6415static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6416 struct sk_buff *skb,
6417 struct ixgbe_tx_buffer *first,
6418 u32 tx_flags,
6419 const u8 hdr_len)
6420{
6421 struct device *dev = tx_ring->dev;
6422 struct ixgbe_tx_buffer *tx_buffer_info;
6423 union ixgbe_adv_tx_desc *tx_desc;
6424 dma_addr_t dma;
6425 __le32 cmd_type, olinfo_status;
6426 struct skb_frag_struct *frag;
6427 unsigned int f = 0;
6428 unsigned int data_len = skb->data_len;
6429 unsigned int size = skb_headlen(skb);
6430 u32 offset = 0;
6431 u32 paylen = skb->len - hdr_len;
6432 u16 i = tx_ring->next_to_use;
6433 u16 gso_segs;
6434
6435#ifdef IXGBE_FCOE
6436 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6437 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6438 data_len -= sizeof(struct fcoe_crc_eof);
6439 } else {
6440 size -= sizeof(struct fcoe_crc_eof) - data_len;
6441 data_len = 0;
9a799d71
AK		 6442 }
6443 }
44df32c5 6444
d3d00239
AD		 6445#endif
6446 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6447 if (dma_mapping_error(dev, dma))
6448 goto dma_error;
8ad494b0 6449
d3d00239
AD		 6450 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6451 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6452
d3d00239 6453 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6454
d3d00239
AD		 6455 for (;;) {
6456 while (size > IXGBE_MAX_DATA_PER_TXD) {
6457 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6458 tx_desc->read.cmd_type_len =
6459 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6460 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6461
d3d00239
AD		 6462 offset += IXGBE_MAX_DATA_PER_TXD;
6463 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6464
d3d00239
AD		 6465 tx_desc++;
6466 i++;
6467 if (i == tx_ring->count) {
6468 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6469 i = 0;
6470 }
6471 }
e5a43549 6472
e5a43549 6473 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6474 tx_buffer_info->length = offset + size;
6475 tx_buffer_info->tx_flags = tx_flags;
6476 tx_buffer_info->dma = dma;
9a799d71 6477
d3d00239
AD		 6478 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6479 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6480 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6481
d3d00239
AD		 6482 if (!data_len)
6483 break;
9a799d71 6484
d3d00239
AD		 6485 frag = &skb_shinfo(skb)->frags[f];
6486#ifdef IXGBE_FCOE
6487 size = min_t(unsigned int, data_len, frag->size);
6488#else
6489 size = frag->size;
6490#endif
6491 data_len -= size;
6492 f++;
9a799d71 6493
d3d00239
AD		 6494 offset = 0;
6495 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6496
d3d00239
AD		 6497 dma = dma_map_page(dev, frag->page, frag->page_offset,
6498 size, DMA_TO_DEVICE);
6499 if (dma_mapping_error(dev, dma))
6500 goto dma_error;
9a799d71 6501
d3d00239
AD		 6502 tx_desc++;
6503 i++;
6504 if (i == tx_ring->count) {
6505 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6506 i = 0;
6507 }
6508 }
9a799d71 6509
d3d00239 6510 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6511
d3d00239
AD		 6512 i++;
6513 if (i == tx_ring->count)
6514 i = 0;
9a799d71 6515
d3d00239 6516 tx_ring->next_to_use = i;
eacd73f7 6517
d3d00239
AD		 6518 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6519 gso_segs = skb_shinfo(skb)->gso_segs;
6520#ifdef IXGBE_FCOE
6521 /* adjust for FCoE Sequence Offload */
6522 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6523 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6524 skb_shinfo(skb)->gso_size);
6525#endif /* IXGBE_FCOE */
6526 else
6527 gso_segs = 1;
9a799d71 6528
d3d00239
AD		 6529 /* multiply data chunks by size of headers */
6530 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6531 tx_buffer_info->gso_segs = gso_segs;
6532 tx_buffer_info->skb = skb;
9a799d71 6533
d3d00239
AD		 6534 /* set the timestamp */
6535 first->time_stamp = jiffies;
9a799d71
AK		 6536
6537 /*
6538 * Force memory writes to complete before letting h/w
6539 * know there are new descriptors to fetch. (Only
6540 * applicable for weak-ordered memory model archs,
6541 * such as IA-64).
6542 */
6543 wmb();
6544
d3d00239
AD		 6545 /* set next_to_watch value indicating a packet is present */
6546 first->next_to_watch = tx_desc;
6547
6548 /* notify HW of packet */
84ea2591 6549 writel(i, tx_ring->tail);
d3d00239
AD		 6550
6551 return;
6552dma_error:
6553 dev_err(dev, "TX DMA map failed\n");
6554
6555 /* clear dma mappings for failed tx_buffer_info map */
6556 for (;;) {
6557 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6558 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6559 if (tx_buffer_info == first)
6560 break;
6561 if (i == 0)
6562 i = tx_ring->count;
6563 i--;
6564 }
6565
6566 dev_kfree_skb_any(skb);
6567
6568 tx_ring->next_to_use = i;
9a799d71
AK		 6569}
6570
69830529
AD		 6571static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6572 u32 tx_flags, __be16 protocol)
6573{
6574 struct ixgbe_q_vector *q_vector = ring->q_vector;
6575 union ixgbe_atr_hash_dword input = { .dword = 0 };
6576 union ixgbe_atr_hash_dword common = { .dword = 0 };
6577 union {
6578 unsigned char *network;
6579 struct iphdr *ipv4;
6580 struct ipv6hdr *ipv6;
6581 } hdr;
ee9e0f0b 6582 struct tcphdr *th;
905e4a41 6583 __be16 vlan_id;
c4cf55e5 6584
69830529
AD		 6585 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6586 if (!q_vector)
6587 return;
6588
6589 /* do nothing if sampling is disabled */
6590 if (!ring->atr_sample_rate)
d3ead241 6591 return;
c4cf55e5 6592
69830529 6593 ring->atr_count++;
c4cf55e5 6594
69830529
AD		 6595 /* snag network header to get L4 type and address */
6596 hdr.network = skb_network_header(skb);
6597
6598 /* Currently only IPv4/IPv6 with TCP is supported */
6599 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6600 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6601 (protocol != __constant_htons(ETH_P_IP) ||
6602 hdr.ipv4->protocol != IPPROTO_TCP))
6603 return;
ee9e0f0b
AD		 6604
6605 th = tcp_hdr(skb);
c4cf55e5 6606
66f32a8b
AD		 6607 /* skip this packet since it is invalid or the socket is closing */
6608 if (!th || th->fin)
69830529
AD		 6609 return;
6610
6611 /* sample on all syn packets or once every atr sample count */
6612 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6613 return;
6614
6615 /* reset sample count */
6616 ring->atr_count = 0;
6617
6618 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6619
6620 /*
6621 * src and dst are inverted, think how the receiver sees them
6622 *
6623 * The input is broken into two sections, a non-compressed section
6624 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6625 * is XORed together and stored in the compressed dword.
6626 */
6627 input.formatted.vlan_id = vlan_id;
6628
6629 /*
6630 * since src port and flex bytes occupy the same word XOR them together
6631 * and write the value to source port portion of compressed dword
6632 */
66f32a8b 6633 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6634 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6635 else
6636 common.port.src ^= th->dest ^ protocol;
6637 common.port.dst ^= th->source;
6638
6639 if (protocol == __constant_htons(ETH_P_IP)) {
6640 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6641 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6642 } else {
6643 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6644 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6645 hdr.ipv6->saddr.s6_addr32[1] ^
6646 hdr.ipv6->saddr.s6_addr32[2] ^
6647 hdr.ipv6->saddr.s6_addr32[3] ^
6648 hdr.ipv6->daddr.s6_addr32[0] ^
6649 hdr.ipv6->daddr.s6_addr32[1] ^
6650 hdr.ipv6->daddr.s6_addr32[2] ^
6651 hdr.ipv6->daddr.s6_addr32[3];
6652 }
c4cf55e5
PWJ		 6653
6654 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6655 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6656 input, common, ring->queue_index);
c4cf55e5
PWJ		 6657}
6658
63544e9c 6659static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6660{
fc77dc3c 6661 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6662 /* Herbert's original patch had:
6663 * smp_mb__after_netif_stop_queue();
6664 * but since that doesn't exist yet, just open code it. */
6665 smp_mb();
6666
6667 /* We need to check again in a case another CPU has just
6668 * made room available. */
7d4987de 6669 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6670 return -EBUSY;
6671
6672 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6673 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6674 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6675 return 0;
6676}
6677
82d4e46e 6678static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6679{
7d4987de 6680 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6681 return 0;
fc77dc3c 6682 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6683}
6684
09a3b1f8
SH		 6685static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6686{
6687 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6688 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6689 smp_processor_id();
56075a98 6690#ifdef IXGBE_FCOE
6440752c 6691 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6692
e5b64635
JF		 6693 if (((protocol == htons(ETH_P_FCOE)) ||
6694 (protocol == htons(ETH_P_FIP))) &&
6695 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6696 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6697 txq += adapter->ring_feature[RING_F_FCOE].mask;
6698 return txq;
56075a98
JF		 6699 }
6700#endif
6701
fdd3d631
KK		 6702 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6703 while (unlikely(txq >= dev->real_num_tx_queues))
6704 txq -= dev->real_num_tx_queues;
5f715823 6705 return txq;
fdd3d631 6706 }
c4cf55e5 6707
09a3b1f8
SH		 6708 return skb_tx_hash(dev, skb);
6709}
6710
fc77dc3c 6711netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6712 struct ixgbe_adapter *adapter,
6713 struct ixgbe_ring *tx_ring)
9a799d71 6714{
d3d00239 6715 struct ixgbe_tx_buffer *first;
5f715823 6716 int tso;
d3d00239 6717 u32 tx_flags = 0;
a535c30e
AD		 6718#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6719 unsigned short f;
6720#endif
a535c30e 6721 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6722 __be16 protocol = skb->protocol;
63544e9c 6723 u8 hdr_len = 0;
5e09a105 6724
a535c30e
AD		 6725 /*
6726 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6727 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6728 * + 2 desc gap to keep tail from touching head,
6729 * + 1 desc for context descriptor,
6730 * otherwise try next time
6731 */
6732#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6733 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6734 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6735#else
6736 count += skb_shinfo(skb)->nr_frags;
6737#endif
6738 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6739 tx_ring->tx_stats.tx_busy++;
6740 return NETDEV_TX_BUSY;
6741 }
6742
7f9643fd
AD		 6743#ifdef CONFIG_PCI_IOV
6744 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6745 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6746
6747#endif
66f32a8b 6748 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6749 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6750 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6751 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6752 /* else if it is a SW VLAN check the next protocol and store the tag */
6753 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6754 struct vlan_hdr *vhdr, _vhdr;
6755 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6756 if (!vhdr)
6757 goto out_drop;
6758
6759 protocol = vhdr->h_vlan_encapsulated_proto;
6760 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6761 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6762 }
6763
6764 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6765 skb->priority != TC_PRIO_CONTROL) {
6766 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6767 tx_flags |= tx_ring->dcb_tc <<
6768 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6769 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6770 struct vlan_ethhdr *vhdr;
6771 if (skb_header_cloned(skb) &&
6772 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6773 goto out_drop;
6774 vhdr = (struct vlan_ethhdr *)skb->data;
6775 vhdr->h_vlan_TCI = htons(tx_flags >>
6776 IXGBE_TX_FLAGS_VLAN_SHIFT);
6777 } else {
6778 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6779 }
9a799d71 6780 }
eacd73f7 6781
a535c30e 6782 /* record the location of the first descriptor for this packet */
d3d00239 6783 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6784
eacd73f7 6785#ifdef IXGBE_FCOE
66f32a8b
AD		 6786 /* setup tx offload for FCoE */
6787 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6788 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6789 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6790 if (tso < 0)
6791 goto out_drop;
6792 else if (tso)
66f32a8b
AD		 6793 tx_flags |= IXGBE_TX_FLAGS_FSO |
6794 IXGBE_TX_FLAGS_FCOE;
6795 else
6796 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6797
66f32a8b 6798 goto xmit_fcoe;
eacd73f7 6799 }
9a799d71 6800
66f32a8b
AD		 6801#endif /* IXGBE_FCOE */
6802 /* setup IPv4/IPv6 offloads */
6803 if (protocol == __constant_htons(ETH_P_IP))
6804 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6805
66f32a8b
AD		 6806 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6807 if (tso < 0)
897ab156 6808 goto out_drop;
66f32a8b
AD		 6809 else if (tso)
6810 tx_flags |= IXGBE_TX_FLAGS_TSO;
6811 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6812 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6813
6814 /* add the ATR filter if ATR is on */
6815 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6816 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6817
6818#ifdef IXGBE_FCOE
6819xmit_fcoe:
6820#endif /* IXGBE_FCOE */
d3d00239
AD		 6821 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6822
6823 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6824
6825 return NETDEV_TX_OK;
897ab156
AD		 6826
6827out_drop:
6828 dev_kfree_skb_any(skb);
6829 return NETDEV_TX_OK;
9a799d71
AK		 6830}
6831
84418e3b
AD		 6832static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6833{
6834 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6835 struct ixgbe_ring *tx_ring;
6836
6837 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6838 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6839}
6840
9a799d71
AK		 6841/**
6842 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6843 * @netdev: network interface device structure
6844 * @p: pointer to an address structure
6845 *
6846 * Returns 0 on success, negative on failure
6847 **/
6848static int ixgbe_set_mac(struct net_device *netdev, void *p)
6849{
6850 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6851 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6852 struct sockaddr *addr = p;
6853
6854 if (!is_valid_ether_addr(addr->sa_data))
6855 return -EADDRNOTAVAIL;
6856
6857 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6858 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6859
1cdd1ec8
GR		 6860 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6861 IXGBE_RAH_AV);
9a799d71
AK		 6862
6863 return 0;
6864}
6865
6b73e10d
BH		 6866static int
6867ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6868{
6869 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6870 struct ixgbe_hw *hw = &adapter->hw;
6871 u16 value;
6872 int rc;
6873
6874 if (prtad != hw->phy.mdio.prtad)
6875 return -EINVAL;
6876 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6877 if (!rc)
6878 rc = value;
6879 return rc;
6880}
6881
6882static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6883 u16 addr, u16 value)
6884{
6885 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6886 struct ixgbe_hw *hw = &adapter->hw;
6887
6888 if (prtad != hw->phy.mdio.prtad)
6889 return -EINVAL;
6890 return hw->phy.ops.write_reg(hw, addr, devad, value);
6891}
6892
6893static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6894{
6895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6896
6897 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6898}
6899
0365e6e4
PW		 6900/**
6901 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6902 * netdev->dev_addrs
0365e6e4
PW		 6903 * @netdev: network interface device structure
6904 *
6905 * Returns non-zero on failure
6906 **/
6907static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6908{
6909 int err = 0;
6910 struct ixgbe_adapter *adapter = netdev_priv(dev);
6911 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6912
6913 if (is_valid_ether_addr(mac->san_addr)) {
6914 rtnl_lock();
6915 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6916 rtnl_unlock();
6917 }
6918 return err;
6919}
6920
6921/**
6922 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6923 * netdev->dev_addrs
0365e6e4
PW		 6924 * @netdev: network interface device structure
6925 *
6926 * Returns non-zero on failure
6927 **/
6928static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6929{
6930 int err = 0;
6931 struct ixgbe_adapter *adapter = netdev_priv(dev);
6932 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6933
6934 if (is_valid_ether_addr(mac->san_addr)) {
6935 rtnl_lock();
6936 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6937 rtnl_unlock();
6938 }
6939 return err;
6940}
6941
9a799d71
AK		 6942#ifdef CONFIG_NET_POLL_CONTROLLER
6943/*
6944 * Polling 'interrupt' - used by things like netconsole to send skbs
6945 * without having to re-enable interrupts. It's not called while
6946 * the interrupt routine is executing.
6947 */
6948static void ixgbe_netpoll(struct net_device *netdev)
6949{
6950 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6951 int i;
9a799d71 6952
1a647bd2
AD		 6953 /* if interface is down do nothing */
6954 if (test_bit(__IXGBE_DOWN, &adapter->state))
6955 return;
6956
9a799d71 6957 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6958 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6959 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6960 for (i = 0; i < num_q_vectors; i++) {
6961 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6962 ixgbe_msix_clean_many(0, q_vector);
6963 }
6964 } else {
6965 ixgbe_intr(adapter->pdev->irq, netdev);
6966 }
9a799d71 6967 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 6968}
6969#endif
6970
de1036b1
ED		 6971static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6972 struct rtnl_link_stats64 *stats)
6973{
6974 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6975 int i;
6976
1a51502b 6977 rcu_read_lock();
de1036b1 6978 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6979 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6980 u64 bytes, packets;
6981 unsigned int start;
6982
1a51502b
ED		 6983 if (ring) {
6984 do {
6985 start = u64_stats_fetch_begin_bh(&ring->syncp);
6986 packets = ring->stats.packets;
6987 bytes = ring->stats.bytes;
6988 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6989 stats->rx_packets += packets;
6990 stats->rx_bytes += bytes;
6991 }
de1036b1 6992 }
1ac9ad13
ED		 6993
6994 for (i = 0; i < adapter->num_tx_queues; i++) {
6995 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6996 u64 bytes, packets;
6997 unsigned int start;
6998
6999 if (ring) {
7000 do {
7001 start = u64_stats_fetch_begin_bh(&ring->syncp);
7002 packets = ring->stats.packets;
7003 bytes = ring->stats.bytes;
7004 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7005 stats->tx_packets += packets;
7006 stats->tx_bytes += bytes;
7007 }
7008 }
1a51502b 7009 rcu_read_unlock();
de1036b1
ED		 7010 /* following stats updated by ixgbe_watchdog_task() */
7011 stats->multicast = netdev->stats.multicast;
7012 stats->rx_errors = netdev->stats.rx_errors;
7013 stats->rx_length_errors = netdev->stats.rx_length_errors;
7014 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7015 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7016 return stats;
7017}
7018
8b1c0b24
JF		 7019/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7020 * #adapter: pointer to ixgbe_adapter
7021 * @tc: number of traffic classes currently enabled
7022 *
7023 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7024 * 802.1Q priority maps to a packet buffer that exists.
7025 */
7026static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7027{
7028 struct ixgbe_hw *hw = &adapter->hw;
7029 u32 reg, rsave;
7030 int i;
7031
7032 /* 82598 have a static priority to TC mapping that can not
7033 * be changed so no validation is needed.
7034 */
7035 if (hw->mac.type == ixgbe_mac_82598EB)
7036 return;
7037
7038 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7039 rsave = reg;
7040
7041 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7042 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7043
7044 /* If up2tc is out of bounds default to zero */
7045 if (up2tc > tc)
7046 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7047 }
7048
7049 if (reg != rsave)
7050 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7051
7052 return;
7053}
7054
7055
7056/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7057 * classes.
7058 *
7059 * @netdev: net device to configure
7060 * @tc: number of traffic classes to enable
7061 */
7062int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7063{
8b1c0b24
JF		 7064 struct ixgbe_adapter *adapter = netdev_priv(dev);
7065 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24
JF		 7066
7067 /* If DCB is anabled do not remove traffic classes, multiple
7068 * traffic classes are required to implement DCB
7069 */
7070 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7071 return 0;
7072
7073 /* Hardware supports up to 8 traffic classes */
7074 if (tc > MAX_TRAFFIC_CLASS ||
7075 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7076 return -EINVAL;
7077
7078 /* Hardware has to reinitialize queues and interrupts to
7079 * match packet buffer alignment. Unfortunantly, the
7080 * hardware is not flexible enough to do this dynamically.
7081 */
7082 if (netif_running(dev))
7083 ixgbe_close(dev);
7084 ixgbe_clear_interrupt_scheme(adapter);
7085
7086 if (tc)
7087 netdev_set_num_tc(dev, tc);
7088 else
7089 netdev_reset_tc(dev);
7090
8b1c0b24
JF		 7091 ixgbe_init_interrupt_scheme(adapter);
7092 ixgbe_validate_rtr(adapter, tc);
7093 if (netif_running(dev))
7094 ixgbe_open(dev);
7095
7096 return 0;
7097}
de1036b1 7098
082757af
DS		 7099void ixgbe_do_reset(struct net_device *netdev)
7100{
7101 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7102
7103 if (netif_running(netdev))
7104 ixgbe_reinit_locked(adapter);
7105 else
7106 ixgbe_reset(adapter);
7107}
7108
7109static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7110{
7111 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7112
7113#ifdef CONFIG_DCB
7114 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7115 data &= ~NETIF_F_HW_VLAN_RX;
7116#endif
7117
7118 /* return error if RXHASH is being enabled when RSS is not supported */
7119 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7120 data &= ~NETIF_F_RXHASH;
7121
7122 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7123 if (!(data & NETIF_F_RXCSUM))
7124 data &= ~NETIF_F_LRO;
7125
7126 /* Turn off LRO if not RSC capable or invalid ITR settings */
7127 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7128 data &= ~NETIF_F_LRO;
7129 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7130 (adapter->rx_itr_setting != 1 &&
7131 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7132 data &= ~NETIF_F_LRO;
7133 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7134 }
7135
7136 return data;
7137}
7138
7139static int ixgbe_set_features(struct net_device *netdev, u32 data)
7140{
7141 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7142 bool need_reset = false;
7143
7144 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7145 if (!(data & NETIF_F_RXCSUM))
7146 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7147 else
7148 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7149
7150 /* Make sure RSC matches LRO, reset if change */
7151 if (!!(data & NETIF_F_LRO) !=
7152 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7153 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7154 switch (adapter->hw.mac.type) {
7155 case ixgbe_mac_X540:
7156 case ixgbe_mac_82599EB:
7157 need_reset = true;
7158 break;
7159 default:
7160 break;
7161 }
7162 }
7163
7164 /*
7165 * Check if Flow Director n-tuple support was enabled or disabled. If
7166 * the state changed, we need to reset.
7167 */
7168 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7169 /* turn off ATR, enable perfect filters and reset */
7170 if (data & NETIF_F_NTUPLE) {
7171 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7172 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7173 need_reset = true;
7174 }
7175 } else if (!(data & NETIF_F_NTUPLE)) {
7176 /* turn off Flow Director, set ATR and reset */
7177 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7178 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7179 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7180 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7181 need_reset = true;
7182 }
7183
7184 if (need_reset)
7185 ixgbe_do_reset(netdev);
7186
7187 return 0;
7188
7189}
7190
0edc3527 7191static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7192 .ndo_open = ixgbe_open,
0edc3527 7193 .ndo_stop = ixgbe_close,
00829823 7194 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7195 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7196 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7197 .ndo_validate_addr = eth_validate_addr,
7198 .ndo_set_mac_address = ixgbe_set_mac,
7199 .ndo_change_mtu = ixgbe_change_mtu,
7200 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7201 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7202 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7203 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7204 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7205 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7206 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7207 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7208 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7209 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7210#ifdef CONFIG_NET_POLL_CONTROLLER
7211 .ndo_poll_controller = ixgbe_netpoll,
7212#endif
332d4a7d
YZ		 7213#ifdef IXGBE_FCOE
7214 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7215 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7216 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7217 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7218 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7219 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7220#endif /* IXGBE_FCOE */
082757af
DS		 7221 .ndo_set_features = ixgbe_set_features,
7222 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7223};
7224
1cdd1ec8
GR		 7225static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7226 const struct ixgbe_info *ii)
7227{
7228#ifdef CONFIG_PCI_IOV
7229 struct ixgbe_hw *hw = &adapter->hw;
7230 int err;
a1cbb15c
GR		 7231 int num_vf_macvlans, i;
7232 struct vf_macvlans *mv_list;
1cdd1ec8 7233
3377eba7 7234 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
1cdd1ec8
GR		 7235 return;
7236
7237 /* The 82599 supports up to 64 VFs per physical function
7238 * but this implementation limits allocation to 63 so that
7239 * basic networking resources are still available to the
7240 * physical function
7241 */
7242 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7243 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7244 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7245 if (err) {
396e799c 7246 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
1cdd1ec8
GR		 7247 goto err_novfs;
7248 }
a1cbb15c
GR		 7249
7250 num_vf_macvlans = hw->mac.num_rar_entries -
7251 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7252
7253 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7254 sizeof(struct vf_macvlans),
7255 GFP_KERNEL);
7256 if (mv_list) {
7257 /* Initialize list of VF macvlans */
7258 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7259 for (i = 0; i < num_vf_macvlans; i++) {
7260 mv_list->vf = -1;
7261 mv_list->free = true;
7262 mv_list->rar_entry = hw->mac.num_rar_entries -
7263 (i + adapter->num_vfs + 1);
7264 list_add(&mv_list->l, &adapter->vf_mvs.l);
7265 mv_list++;
7266 }
7267 }
7268
1cdd1ec8
GR		 7269 /* If call to enable VFs succeeded then allocate memory
7270 * for per VF control structures.
7271 */
7272 adapter->vfinfo =
7273 kcalloc(adapter->num_vfs,
7274 sizeof(struct vf_data_storage), GFP_KERNEL);
7275 if (adapter->vfinfo) {
7276 /* Now that we're sure SR-IOV is enabled
7277 * and memory allocated set up the mailbox parameters
7278 */
7279 ixgbe_init_mbx_params_pf(hw);
7280 memcpy(&hw->mbx.ops, ii->mbx_ops,
7281 sizeof(hw->mbx.ops));
7282
7283 /* Disable RSC when in SR-IOV mode */
7284 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7285 IXGBE_FLAG2_RSC_ENABLED);
7286 return;
7287 }
7288
7289 /* Oh oh */
396e799c
ET		 7290 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7291 "SRIOV disabled\n");
1cdd1ec8
GR		 7292 pci_disable_sriov(adapter->pdev);
7293
7294err_novfs:
7295 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7296 adapter->num_vfs = 0;
7297#endif /* CONFIG_PCI_IOV */
7298}
7299
9a799d71
AK		 7300/**
7301 * ixgbe_probe - Device Initialization Routine
7302 * @pdev: PCI device information struct
7303 * @ent: entry in ixgbe_pci_tbl
7304 *
7305 * Returns 0 on success, negative on failure
7306 *
7307 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7308 * The OS initialization, configuring of the adapter private structure,
7309 * and a hardware reset occur.
7310 **/
7311static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7312 const struct pci_device_id *ent)
9a799d71
AK		 7313{
7314 struct net_device *netdev;
7315 struct ixgbe_adapter *adapter = NULL;
7316 struct ixgbe_hw *hw;
7317 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7318 static int cards_found;
7319 int i, err, pci_using_dac;
289700db 7320 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7321 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7322#ifdef IXGBE_FCOE
7323 u16 device_caps;
7324#endif
289700db 7325 u32 eec;
9a799d71 7326
bded64a7
AG		 7327 /* Catch broken hardware that put the wrong VF device ID in
7328 * the PCIe SR-IOV capability.
7329 */
7330 if (pdev->is_virtfn) {
7331 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7332 pci_name(pdev), pdev->vendor, pdev->device);
7333 return -EINVAL;
7334 }
7335
9ce77666 7336 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7337 if (err)
7338 return err;
7339
1b507730
NN		 7340 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7341 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7342 pci_using_dac = 1;
7343 } else {
1b507730 7344 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7345 if (err) {
1b507730
NN		 7346 err = dma_set_coherent_mask(&pdev->dev,
7347 DMA_BIT_MASK(32));
9a799d71 7348 if (err) {
b8bc0421
DC		 7349 dev_err(&pdev->dev,
7350 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7351 goto err_dma;
7352 }
7353 }
7354 pci_using_dac = 0;
7355 }
7356
9ce77666 7357 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7358 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7359 if (err) {
b8bc0421
DC		 7360 dev_err(&pdev->dev,
7361 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7362 goto err_pci_reg;
7363 }
7364
19d5afd4 7365 pci_enable_pcie_error_reporting(pdev);
6fabd715 7366
9a799d71 7367 pci_set_master(pdev);
fb3b27bc 7368 pci_save_state(pdev);
9a799d71 7369
e901acd6
JF		 7370#ifdef CONFIG_IXGBE_DCB
7371 indices *= MAX_TRAFFIC_CLASS;
7372#endif
7373
c85a2618
JF		 7374 if (ii->mac == ixgbe_mac_82598EB)
7375 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7376 else
7377 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7378
e901acd6 7379#ifdef IXGBE_FCOE
c85a2618
JF		 7380 indices += min_t(unsigned int, num_possible_cpus(),
7381 IXGBE_MAX_FCOE_INDICES);
7382#endif
c85a2618 7383 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7384 if (!netdev) {
7385 err = -ENOMEM;
7386 goto err_alloc_etherdev;
7387 }
7388
9a799d71
AK		 7389 SET_NETDEV_DEV(netdev, &pdev->dev);
7390
9a799d71 7391 adapter = netdev_priv(netdev);
c60fbb00 7392 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7393
7394 adapter->netdev = netdev;
7395 adapter->pdev = pdev;
7396 hw = &adapter->hw;
7397 hw->back = adapter;
7398 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7399
05857980 7400 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7401 pci_resource_len(pdev, 0));
9a799d71
AK		 7402 if (!hw->hw_addr) {
7403 err = -EIO;
7404 goto err_ioremap;
7405 }
7406
7407 for (i = 1; i <= 5; i++) {
7408 if (pci_resource_len(pdev, i) == 0)
7409 continue;
7410 }
7411
0edc3527 7412 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7413 ixgbe_set_ethtool_ops(netdev);
9a799d71 7414 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7415 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7416
9a799d71
AK		 7417 adapter->bd_number = cards_found;
7418
9a799d71
AK		 7419 /* Setup hw api */
7420 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7421 hw->mac.type = ii->mac;
9a799d71 7422
c44ade9e
JB		 7423 /* EEPROM */
7424 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7425 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7426 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7427 if (!(eec & (1 << 8)))
7428 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7429
7430 /* PHY */
7431 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7432 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7433 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7434 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7435 hw->phy.mdio.mmds = 0;
7436 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7437 hw->phy.mdio.dev = netdev;
7438 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7439 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7440
8ca783ab 7441 ii->get_invariants(hw);
9a799d71
AK		 7442
7443 /* setup the private structure */
7444 err = ixgbe_sw_init(adapter);
7445 if (err)
7446 goto err_sw_init;
7447
e86bff0e 7448 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7449 switch (adapter->hw.mac.type) {
7450 case ixgbe_mac_82599EB:
7451 case ixgbe_mac_X540:
e86bff0e 7452 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7453 break;
7454 default:
7455 break;
7456 }
e86bff0e 7457
bf069c97
DS		 7458 /*
7459 * If there is a fan on this device and it has failed log the
7460 * failure.
7461 */
7462 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7463 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7464 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7465 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7466 }
7467
c44ade9e 7468 /* reset_hw fills in the perm_addr as well */
119fc60a 7469 hw->phy.reset_if_overtemp = true;
c44ade9e 7470 err = hw->mac.ops.reset_hw(hw);
119fc60a 7471 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7472 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7473 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7474 err = 0;
7475 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7476 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7477 "module type was detected.\n");
7478 e_dev_err("Reload the driver after installing a supported "
7479 "module.\n");
04f165ef
PW		 7480 goto err_sw_init;
7481 } else if (err) {
849c4542 7482 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7483 goto err_sw_init;
7484 }
7485
1cdd1ec8
GR		 7486 ixgbe_probe_vf(adapter, ii);
7487
396e799c 7488 netdev->features = NETIF_F_SG |
e8e9f696 7489 NETIF_F_IP_CSUM |
082757af 7490 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7491 NETIF_F_HW_VLAN_TX |
7492 NETIF_F_HW_VLAN_RX |
082757af
DS		 7493 NETIF_F_HW_VLAN_FILTER |
7494 NETIF_F_TSO |
7495 NETIF_F_TSO6 |
7496 NETIF_F_GRO |
7497 NETIF_F_RXHASH |
7498 NETIF_F_RXCSUM;
9a799d71 7499
082757af 7500 netdev->hw_features = netdev->features;
ad31c402 7501
58be7666
DS		 7502 switch (adapter->hw.mac.type) {
7503 case ixgbe_mac_82599EB:
7504 case ixgbe_mac_X540:
45a5ead0 7505 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7506 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7507 NETIF_F_NTUPLE;
58be7666
DS		 7508 break;
7509 default:
7510 break;
7511 }
45a5ead0 7512
ad31c402
JK		 7513 netdev->vlan_features |= NETIF_F_TSO;
7514 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7515 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7516 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7517 netdev->vlan_features |= NETIF_F_SG;
7518
01789349
JP		 7519 netdev->priv_flags |= IFF_UNICAST_FLT;
7520
1cdd1ec8
GR		 7521 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7522 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7523 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7524
7a6b6f51 7525#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7526 netdev->dcbnl_ops = &dcbnl_ops;
7527#endif
7528
eacd73f7 7529#ifdef IXGBE_FCOE
0d551589 7530 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7531 if (hw->mac.ops.get_device_caps) {
7532 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7533 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7534 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7535 }
7536 }
5e09d7f6
YZ		 7537 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7538 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7539 netdev->vlan_features |= NETIF_F_FSO;
7540 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7541 }
eacd73f7 7542#endif /* IXGBE_FCOE */
7b872a55 7543 if (pci_using_dac) {
9a799d71 7544 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7545 netdev->vlan_features |= NETIF_F_HIGHDMA;
7546 }
9a799d71 7547
082757af
DS		 7548 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7549 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7550 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7551 netdev->features |= NETIF_F_LRO;
7552
9a799d71 7553 /* make sure the EEPROM is good */
c44ade9e 7554 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7555 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7556 err = -EIO;
7557 goto err_eeprom;
7558 }
7559
7560 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7561 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7562
c44ade9e 7563 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7564 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7565 err = -EIO;
7566 goto err_eeprom;
7567 }
7568
c6ecf39a
DS		 7569 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7570 if (hw->mac.ops.disable_tx_laser &&
7571 ((hw->phy.multispeed_fiber) ||
9f911707 7572 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 7573 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 7574 hw->mac.ops.disable_tx_laser(hw);
7575
7086400d
AD		 7576 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7577 (unsigned long) adapter);
9a799d71 7578
7086400d
AD		 7579 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7580 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7581
021230d4
AV		 7582 err = ixgbe_init_interrupt_scheme(adapter);
7583 if (err)
7584 goto err_sw_init;
9a799d71 7585
082757af
DS		 7586 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7587 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7588 netdev->features &= ~NETIF_F_RXHASH;
082757af 7589 }
67a74ee2 7590
e8e26350 7591 switch (pdev->device) {
0b077fea
DS		 7592 case IXGBE_DEV_ID_82599_SFP:
7593 /* Only this subdevice supports WOL */
7594 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
9417c464 7595 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7596 break;
50d6c681
AD		 7597 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7598 /* All except this subdevice support WOL */
0b077fea 7599 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7600 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7601 break;
e8e26350 7602 case IXGBE_DEV_ID_82599_KX4:
9417c464 7603 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7604 break;
7605 default:
7606 adapter->wol = 0;
7607 break;
7608 }
e8e26350
PW		 7609 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7610
04f165ef
PW		 7611 /* pick up the PCI bus settings for reporting later */
7612 hw->mac.ops.get_bus_info(hw);
7613
9a799d71 7614 /* print bus type/speed/width info */
849c4542 7615 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7616 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7617 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7618 "Unknown"),
7619 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7620 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7621 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7622 "Unknown"),
7623 netdev->dev_addr);
289700db
DS		 7624
7625 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7626 if (err)
9fe93afd 7627 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7628 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7629 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7630 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7631 part_str);
e8e26350 7632 else
289700db
DS		 7633 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7634 hw->mac.type, hw->phy.type, part_str);
9a799d71 7635
e8e26350 7636 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7637 e_dev_warn("PCI-Express bandwidth available for this card is "
7638 "not sufficient for optimal performance.\n");
7639 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7640 "is required.\n");
0c254d86
AK		 7641 }
7642
34b0368c
PWJ		 7643 /* save off EEPROM version number */
7644 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7645
9a799d71 7646 /* reset the hardware with the new settings */
794caeb2 7647 err = hw->mac.ops.start_hw(hw);
c44ade9e 7648
794caeb2
PWJ		 7649 if (err == IXGBE_ERR_EEPROM_VERSION) {
7650 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7651 e_dev_warn("This device is a pre-production adapter/LOM. "
7652 "Please be aware there may be issues associated "
7653 "with your hardware. If you are experiencing "
7654 "problems please contact your Intel or hardware "
7655 "representative who provided you with this "
7656 "hardware.\n");
794caeb2 7657 }
9a799d71
AK		 7658 strcpy(netdev->name, "eth%d");
7659 err = register_netdev(netdev);
7660 if (err)
7661 goto err_register;
7662
54386467
JB		 7663 /* carrier off reporting is important to ethtool even BEFORE open */
7664 netif_carrier_off(netdev);
7665
5dd2d332 7666#ifdef CONFIG_IXGBE_DCA
652f093f 7667 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7668 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7669 ixgbe_setup_dca(adapter);
7670 }
7671#endif
1cdd1ec8 7672 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7673 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7674 for (i = 0; i < adapter->num_vfs; i++)
7675 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7676 }
7677
9612de92
ET		 7678 /* Inform firmware of driver version */
7679 if (hw->mac.ops.set_fw_drv_ver)
a38a104d
DS		 7680 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7681 FW_CEM_UNUSED_VER);
9612de92 7682
0365e6e4
PW		 7683 /* add san mac addr to netdev */
7684 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7685
849c4542 7686 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7687 cards_found++;
7688 return 0;
7689
7690err_register:
5eba3699 7691 ixgbe_release_hw_control(adapter);
7a921c93 7692 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7693err_sw_init:
7694err_eeprom:
1cdd1ec8
GR		 7695 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7696 ixgbe_disable_sriov(adapter);
7086400d 7697 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7698 iounmap(hw->hw_addr);
7699err_ioremap:
7700 free_netdev(netdev);
7701err_alloc_etherdev:
e8e9f696
JP		 7702 pci_release_selected_regions(pdev,
7703 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7704err_pci_reg:
7705err_dma:
7706 pci_disable_device(pdev);
7707 return err;
7708}
7709
7710/**
7711 * ixgbe_remove - Device Removal Routine
7712 * @pdev: PCI device information struct
7713 *
7714 * ixgbe_remove is called by the PCI subsystem to alert the driver
7715 * that it should release a PCI device. The could be caused by a
7716 * Hot-Plug event, or because the driver is going to be removed from
7717 * memory.
7718 **/
7719static void __devexit ixgbe_remove(struct pci_dev *pdev)
7720{
c60fbb00
AD		 7721 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7722 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7723
7724 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7725 cancel_work_sync(&adapter->service_task);
9a799d71 7726
5dd2d332 7727#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7728 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7729 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7730 dca_remove_requester(&pdev->dev);
7731 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7732 }
7733
7734#endif
332d4a7d
YZ		 7735#ifdef IXGBE_FCOE
7736 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7737 ixgbe_cleanup_fcoe(adapter);
7738
7739#endif /* IXGBE_FCOE */
0365e6e4
PW		 7740
7741 /* remove the added san mac */
7742 ixgbe_del_sanmac_netdev(netdev);
7743
c4900be0
DS		 7744 if (netdev->reg_state == NETREG_REGISTERED)
7745 unregister_netdev(netdev);
9a799d71 7746
1cdd1ec8
GR		 7747 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7748 ixgbe_disable_sriov(adapter);
7749
7a921c93 7750 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7751
021230d4 7752 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7753
7754 iounmap(adapter->hw.hw_addr);
9ce77666 7755 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7756 IORESOURCE_MEM));
9a799d71 7757
849c4542 7758 e_dev_info("complete\n");
021230d4 7759
9a799d71
AK		 7760 free_netdev(netdev);
7761
19d5afd4 7762 pci_disable_pcie_error_reporting(pdev);
6fabd715 7763
9a799d71
AK		 7764 pci_disable_device(pdev);
7765}
7766
7767/**
7768 * ixgbe_io_error_detected - called when PCI error is detected
7769 * @pdev: Pointer to PCI device
7770 * @state: The current pci connection state
7771 *
7772 * This function is called after a PCI bus error affecting
7773 * this device has been detected.
7774 */
7775static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7776 pci_channel_state_t state)
9a799d71 7777{
c60fbb00
AD		 7778 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7779 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7780
7781 netif_device_detach(netdev);
7782
3044b8d1
BL		 7783 if (state == pci_channel_io_perm_failure)
7784 return PCI_ERS_RESULT_DISCONNECT;
7785
9a799d71
AK		 7786 if (netif_running(netdev))
7787 ixgbe_down(adapter);
7788 pci_disable_device(pdev);
7789
b4617240 7790 /* Request a slot reset. */
9a799d71
AK		 7791 return PCI_ERS_RESULT_NEED_RESET;
7792}
7793
7794/**
7795 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7796 * @pdev: Pointer to PCI device
7797 *
7798 * Restart the card from scratch, as if from a cold-boot.
7799 */
7800static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7801{
c60fbb00 7802 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7803 pci_ers_result_t result;
7804 int err;
9a799d71 7805
9ce77666 7806 if (pci_enable_device_mem(pdev)) {
396e799c 7807 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7808 result = PCI_ERS_RESULT_DISCONNECT;
7809 } else {
7810 pci_set_master(pdev);
7811 pci_restore_state(pdev);
c0e1f68b 7812 pci_save_state(pdev);
9a799d71 7813
dd4d8ca6 7814 pci_wake_from_d3(pdev, false);
9a799d71 7815
6fabd715 7816 ixgbe_reset(adapter);
88512539 7817 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7818 result = PCI_ERS_RESULT_RECOVERED;
7819 }
7820
7821 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7822 if (err) {
849c4542
ET		 7823 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7824 "failed 0x%0x\n", err);
6fabd715
PWJ		 7825 /* non-fatal, continue */
7826 }
9a799d71 7827
6fabd715 7828 return result;
9a799d71
AK		 7829}
7830
7831/**
7832 * ixgbe_io_resume - called when traffic can start flowing again.
7833 * @pdev: Pointer to PCI device
7834 *
7835 * This callback is called when the error recovery driver tells us that
7836 * its OK to resume normal operation.
7837 */
7838static void ixgbe_io_resume(struct pci_dev *pdev)
7839{
c60fbb00
AD		 7840 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7841 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7842
7843 if (netif_running(netdev)) {
7844 if (ixgbe_up(adapter)) {
396e799c 7845 e_info(probe, "ixgbe_up failed after reset\n");
9a799d71
AK		 7846 return;
7847 }
7848 }
7849
7850 netif_device_attach(netdev);
9a799d71
AK		 7851}
7852
7853static struct pci_error_handlers ixgbe_err_handler = {
7854 .error_detected = ixgbe_io_error_detected,
7855 .slot_reset = ixgbe_io_slot_reset,
7856 .resume = ixgbe_io_resume,
7857};
7858
7859static struct pci_driver ixgbe_driver = {
7860 .name = ixgbe_driver_name,
7861 .id_table = ixgbe_pci_tbl,
7862 .probe = ixgbe_probe,
7863 .remove = __devexit_p(ixgbe_remove),
7864#ifdef CONFIG_PM
7865 .suspend = ixgbe_suspend,
7866 .resume = ixgbe_resume,
7867#endif
7868 .shutdown = ixgbe_shutdown,
7869 .err_handler = &ixgbe_err_handler
7870};
7871
7872/**
7873 * ixgbe_init_module - Driver Registration Routine
7874 *
7875 * ixgbe_init_module is the first routine called when the driver is
7876 * loaded. All it does is register with the PCI subsystem.
7877 **/
7878static int __init ixgbe_init_module(void)
7879{
7880 int ret;
c7689578 7881 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7882 pr_info("%s\n", ixgbe_copyright);
9a799d71 7883
5dd2d332 7884#ifdef CONFIG_IXGBE_DCA
bd0362dd 7885 dca_register_notify(&dca_notifier);
bd0362dd 7886#endif
5dd2d332 7887
9a799d71
AK		 7888 ret = pci_register_driver(&ixgbe_driver);
7889 return ret;
7890}
b4617240 7891
9a799d71
AK		 7892module_init(ixgbe_init_module);
7893
7894/**
7895 * ixgbe_exit_module - Driver Exit Cleanup Routine
7896 *
7897 * ixgbe_exit_module is called just before the driver is removed
7898 * from memory.
7899 **/
7900static void __exit ixgbe_exit_module(void)
7901{
5dd2d332 7902#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7903 dca_unregister_notify(&dca_notifier);
7904#endif
9a799d71 7905 pci_unregister_driver(&ixgbe_driver);
1a51502b 7906 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7907}
bd0362dd 7908
5dd2d332 7909#ifdef CONFIG_IXGBE_DCA
bd0362dd 7910static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7911 void *p)
bd0362dd
JC		 7912{
7913 int ret_val;
7914
7915 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7916 __ixgbe_notify_dca);
bd0362dd
JC		 7917
7918 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7919}
b453368d 7920
5dd2d332 7921#endif /* CONFIG_IXGBE_DCA */
849c4542 7922
9a799d71
AK		 7923module_exit(ixgbe_exit_module);
7924
7925/* ixgbe_main.c */
Linux kernel - Deliverables
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