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ixgbe: Update ixgbe_disable_pcie_master flow for X550*
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
67359c3c 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
67359c3c
MR		 68#ifdef CONFIG_IXGBE_VXLAN
69#include <net/vxlan.h>
70#endif
9a799d71
AK		 71
72char ixgbe_driver_name[] = "ixgbe";
9c8eb720 73static const char ixgbe_driver_string[] =
e8e9f696 74 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 75#ifdef IXGBE_FCOE
ea81875a
NP		 76char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 78#else
79static char ixgbe_default_device_descr[] =
80 "Intel(R) 10 Gigabit Network Connection";
81#endif
9be4a9bb 82#define DRV_VERSION "4.0.1-k"
9c8eb720 83const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 84static const char ixgbe_copyright[] =
67359c3c 85 "Copyright (c) 1999-2015 Intel Corporation.";
9a799d71 86
f44e751b
DS		 87static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
88
9a799d71 89static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 90 [board_82598] = &ixgbe_82598_info,
91 [board_82599] = &ixgbe_82599_info,
92 [board_X540] = &ixgbe_X540_info,
93 [board_X550] = &ixgbe_X550_info,
94 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 95};
96
97/* ixgbe_pci_tbl - PCI Device ID Table
98 *
99 * Wildcard entries (PCI_ANY_ID) should come last
100 * Last entry must be all 0s
101 *
102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
103 * Class, Class Mask, private data (not used) }
104 */
9baa3c34 105static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
9a799d71
AK		 140 /* required last entry */
141 {0, }
142};
143MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
144
5dd2d332 145#ifdef CONFIG_IXGBE_DCA
bd0362dd 146static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 147 void *p);
bd0362dd
JC		 148static struct notifier_block dca_notifier = {
149 .notifier_call = ixgbe_notify_dca,
150 .next = NULL,
151 .priority = 0
152};
153#endif
154
1cdd1ec8
GR		 155#ifdef CONFIG_PCI_IOV
156static unsigned int max_vfs;
157module_param(max_vfs, uint, 0);
e8e9f696 158MODULE_PARM_DESC(max_vfs,
170e8543 159 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 160#endif /* CONFIG_PCI_IOV */
161
8ef78adc
PWJ		 162static unsigned int allow_unsupported_sfp;
163module_param(allow_unsupported_sfp, uint, 0);
164MODULE_PARM_DESC(allow_unsupported_sfp,
165 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
166
b3f4d599 167#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
168static int debug = -1;
169module_param(debug, int, 0);
170MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
171
9a799d71
AK		 172MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
173MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
174MODULE_LICENSE("GPL");
175MODULE_VERSION(DRV_VERSION);
176
14438464
MR		 177static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
178
b8e82001
JK		 179static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
180 u32 reg, u16 *value)
181{
b8e82001
JK		 182 struct pci_dev *parent_dev;
183 struct pci_bus *parent_bus;
184
185 parent_bus = adapter->pdev->bus->parent;
186 if (!parent_bus)
187 return -1;
188
189 parent_dev = parent_bus->self;
190 if (!parent_dev)
191 return -1;
192
c0798edf 193 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 194 return -1;
195
c0798edf 196 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 197 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
199 return -1;
b8e82001
JK		 200 return 0;
201}
202
203static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
204{
205 struct ixgbe_hw *hw = &adapter->hw;
206 u16 link_status = 0;
207 int err;
208
209 hw->bus.type = ixgbe_bus_type_pci_express;
210
211 /* Get the negotiated link width and speed from PCI config space of the
212 * parent, as this device is behind a switch
213 */
214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
215
216 /* assume caller will handle error case */
217 if (err)
218 return err;
219
220 hw->bus.width = ixgbe_convert_bus_width(link_status);
221 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
222
223 return 0;
224}
225
e027d1ae
JK		 226/**
227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
228 * @hw: hw specific details
229 *
230 * This function is used by probe to determine whether a device's PCI-Express
231 * bandwidth details should be gathered from the parent bus instead of from the
232 * device. Used to ensure that various locations all have the correct device ID
233 * checks.
234 */
235static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
236{
237 switch (hw->device_id) {
238 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 239 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 240 return true;
241 default:
242 return false;
243 }
244}
245
246static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
247 int expected_gts)
248{
f9328bc6 249 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 250 int max_gts = 0;
251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
253 struct pci_dev *pdev;
254
f9328bc6
DS		 255 /* Some devices are not connected over PCIe and thus do not negotiate
256 * speed. These devices do not have valid bus info, and thus any report
257 * we generate may not be correct.
258 */
259 if (hw->bus.type == ixgbe_bus_type_internal)
260 return;
261
56d1392f 262 /* determine whether to use the parent device */
e027d1ae
JK		 263 if (ixgbe_pcie_from_parent(&adapter->hw))
264 pdev = adapter->pdev->bus->parent->self;
265 else
266 pdev = adapter->pdev;
267
268 if (pcie_get_minimum_link(pdev, &speed, &width) ||
269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
270 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
271 return;
272 }
273
274 switch (speed) {
275 case PCIE_SPEED_2_5GT:
276 /* 8b/10b encoding reduces max throughput by 20% */
277 max_gts = 2 * width;
278 break;
279 case PCIE_SPEED_5_0GT:
280 /* 8b/10b encoding reduces max throughput by 20% */
281 max_gts = 4 * width;
282 break;
283 case PCIE_SPEED_8_0GT:
9f0a433c 284 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 285 max_gts = 8 * width;
286 break;
287 default:
288 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
289 return;
290 }
291
292 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
293 max_gts);
294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
298 "Unknown"),
299 width,
300 (speed == PCIE_SPEED_2_5GT ? "20%" :
301 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 302 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 303 "Unknown"));
304
305 if (max_gts < expected_gts) {
306 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
308 expected_gts);
309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
310 }
311}
312
7086400d
AD		 313static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
314{
315 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 316 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
318 schedule_work(&adapter->service_task);
319}
320
2a1a091c
MR		 321static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
322{
323 struct ixgbe_adapter *adapter = hw->back;
324
325 if (!hw->hw_addr)
326 return;
327 hw->hw_addr = NULL;
328 e_dev_err("Adapter removed\n");
58cf663f
MR		 329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
330 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 331}
332
f8e2472f 333static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 334{
335 u32 value;
336
337 /* The following check not only optimizes a bit by not
338 * performing a read on the status register when the
339 * register just read was a status register read that
340 * returned IXGBE_FAILED_READ_REG. It also blocks any
341 * potential recursion.
342 */
343 if (reg == IXGBE_STATUS) {
344 ixgbe_remove_adapter(hw);
345 return;
346 }
347 value = ixgbe_read_reg(hw, IXGBE_STATUS);
348 if (value == IXGBE_FAILED_READ_REG)
349 ixgbe_remove_adapter(hw);
350}
351
f8e2472f
MR		 352/**
353 * ixgbe_read_reg - Read from device register
354 * @hw: hw specific details
355 * @reg: offset of register to read
356 *
357 * Returns : value read or IXGBE_FAILED_READ_REG if removed
358 *
359 * This function is used to read device registers. It checks for device
360 * removal by confirming any read that returns all ones by checking the
361 * status register value for all ones. This function avoids reading from
362 * the hardware if a removal was previously detected in which case it
363 * returns IXGBE_FAILED_READ_REG (all ones).
364 */
365u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
366{
367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
368 u32 value;
369
370 if (ixgbe_removed(reg_addr))
371 return IXGBE_FAILED_READ_REG;
372 value = readl(reg_addr + reg);
373 if (unlikely(value == IXGBE_FAILED_READ_REG))
374 ixgbe_check_remove(hw, reg);
375 return value;
376}
377
14438464
MR		 378static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
379{
380 u16 value;
381
382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
383 if (value == IXGBE_FAILED_READ_CFG_WORD) {
384 ixgbe_remove_adapter(hw);
385 return true;
386 }
387 return false;
388}
389
390u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
391{
392 struct ixgbe_adapter *adapter = hw->back;
393 u16 value;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return IXGBE_FAILED_READ_CFG_WORD;
397 pci_read_config_word(adapter->pdev, reg, &value);
398 if (value == IXGBE_FAILED_READ_CFG_WORD &&
399 ixgbe_check_cfg_remove(hw, adapter->pdev))
400 return IXGBE_FAILED_READ_CFG_WORD;
401 return value;
402}
403
404#ifdef CONFIG_PCI_IOV
405static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
406{
407 struct ixgbe_adapter *adapter = hw->back;
408 u32 value;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return IXGBE_FAILED_READ_CFG_DWORD;
412 pci_read_config_dword(adapter->pdev, reg, &value);
413 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
414 ixgbe_check_cfg_remove(hw, adapter->pdev))
415 return IXGBE_FAILED_READ_CFG_DWORD;
416 return value;
417}
418#endif /* CONFIG_PCI_IOV */
419
ed19231c
JK		 420void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
421{
422 struct ixgbe_adapter *adapter = hw->back;
423
424 if (ixgbe_removed(hw->hw_addr))
425 return;
426 pci_write_config_word(adapter->pdev, reg, value);
427}
428
7086400d
AD		 429static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
430{
431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
432
52f33af8 433 /* flush memory to make sure state is correct before next watchdog */
4e857c58 434 smp_mb__before_atomic();
7086400d
AD		 435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
436}
437
dcd79aeb
TI		 438struct ixgbe_reg_info {
439 u32 ofs;
440 char *name;
441};
442
443static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
444
445 /* General Registers */
446 {IXGBE_CTRL, "CTRL"},
447 {IXGBE_STATUS, "STATUS"},
448 {IXGBE_CTRL_EXT, "CTRL_EXT"},
449
450 /* Interrupt Registers */
451 {IXGBE_EICR, "EICR"},
452
453 /* RX Registers */
454 {IXGBE_SRRCTL(0), "SRRCTL"},
455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
456 {IXGBE_RDLEN(0), "RDLEN"},
457 {IXGBE_RDH(0), "RDH"},
458 {IXGBE_RDT(0), "RDT"},
459 {IXGBE_RXDCTL(0), "RXDCTL"},
460 {IXGBE_RDBAL(0), "RDBAL"},
461 {IXGBE_RDBAH(0), "RDBAH"},
462
463 /* TX Registers */
464 {IXGBE_TDBAL(0), "TDBAL"},
465 {IXGBE_TDBAH(0), "TDBAH"},
466 {IXGBE_TDLEN(0), "TDLEN"},
467 {IXGBE_TDH(0), "TDH"},
468 {IXGBE_TDT(0), "TDT"},
469 {IXGBE_TXDCTL(0), "TXDCTL"},
470
471 /* List Terminator */
ca8dfe25 472 { .name = NULL }
dcd79aeb
TI		 473};
474
475
476/*
477 * ixgbe_regdump - register printout routine
478 */
479static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
480{
481 int i = 0, j = 0;
482 char rname[16];
483 u32 regs[64];
484
485 switch (reginfo->ofs) {
486 case IXGBE_SRRCTL(0):
487 for (i = 0; i < 64; i++)
488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
489 break;
490 case IXGBE_DCA_RXCTRL(0):
491 for (i = 0; i < 64; i++)
492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
493 break;
494 case IXGBE_RDLEN(0):
495 for (i = 0; i < 64; i++)
496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
497 break;
498 case IXGBE_RDH(0):
499 for (i = 0; i < 64; i++)
500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
501 break;
502 case IXGBE_RDT(0):
503 for (i = 0; i < 64; i++)
504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
505 break;
506 case IXGBE_RXDCTL(0):
507 for (i = 0; i < 64; i++)
508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
509 break;
510 case IXGBE_RDBAL(0):
511 for (i = 0; i < 64; i++)
512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
513 break;
514 case IXGBE_RDBAH(0):
515 for (i = 0; i < 64; i++)
516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
517 break;
518 case IXGBE_TDBAL(0):
519 for (i = 0; i < 64; i++)
520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
521 break;
522 case IXGBE_TDBAH(0):
523 for (i = 0; i < 64; i++)
524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
525 break;
526 case IXGBE_TDLEN(0):
527 for (i = 0; i < 64; i++)
528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
529 break;
530 case IXGBE_TDH(0):
531 for (i = 0; i < 64; i++)
532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
533 break;
534 case IXGBE_TDT(0):
535 for (i = 0; i < 64; i++)
536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
537 break;
538 case IXGBE_TXDCTL(0):
539 for (i = 0; i < 64; i++)
540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
541 break;
542 default:
c7689578 543 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 544 IXGBE_READ_REG(hw, reginfo->ofs));
545 return;
546 }
547
548 for (i = 0; i < 8; i++) {
549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 550 pr_err("%-15s", rname);
dcd79aeb 551 for (j = 0; j < 8; j++)
c7689578
JP		 552 pr_cont(" %08x", regs[i*8+j]);
553 pr_cont("\n");
dcd79aeb
TI		 554 }
555
556}
557
558/*
559 * ixgbe_dump - Print registers, tx-rings and rx-rings
560 */
561static void ixgbe_dump(struct ixgbe_adapter *adapter)
562{
563 struct net_device *netdev = adapter->netdev;
564 struct ixgbe_hw *hw = &adapter->hw;
565 struct ixgbe_reg_info *reginfo;
566 int n = 0;
567 struct ixgbe_ring *tx_ring;
729739b7 568 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 569 union ixgbe_adv_tx_desc *tx_desc;
570 struct my_u0 { u64 a; u64 b; } *u0;
571 struct ixgbe_ring *rx_ring;
572 union ixgbe_adv_rx_desc *rx_desc;
573 struct ixgbe_rx_buffer *rx_buffer_info;
574 u32 staterr;
575 int i = 0;
576
577 if (!netif_msg_hw(adapter))
578 return;
579
580 /* Print netdevice Info */
581 if (netdev) {
582 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 583 pr_info("Device Name state "
dcd79aeb 584 "trans_start last_rx\n");
c7689578
JP		 585 pr_info("%-15s %016lX %016lX %016lX\n",
586 netdev->name,
587 netdev->state,
588 netdev->trans_start,
589 netdev->last_rx);
dcd79aeb
TI		 590 }
591
592 /* Print Registers */
593 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 594 pr_info(" Register Name Value\n");
dcd79aeb
TI		 595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
596 reginfo->name; reginfo++) {
597 ixgbe_regdump(hw, reginfo);
598 }
599
600 /* Print TX Ring Summary */
601 if (!netdev || !netif_running(netdev))
e90dd264 602 return;
dcd79aeb
TI		 603
604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 605 pr_info(" %s %s %s %s\n",
606 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
607 "leng", "ntw", "timestamp");
dcd79aeb
TI		 608 for (n = 0; n < adapter->num_tx_queues; n++) {
609 tx_ring = adapter->tx_ring[n];
729739b7 610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 612 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 613 (u64)dma_unmap_addr(tx_buffer, dma),
614 dma_unmap_len(tx_buffer, len),
615 tx_buffer->next_to_watch,
616 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
39ac868a 627 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
39ac868a 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
dcd79aeb
TI		 658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 tx_ring = adapter->tx_ring[n];
c7689578
JP		 662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
664 pr_info("------------------------------------\n");
8ad88e37
JH		 665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 669
670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 671 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 672 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 673 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
676 i,
677 le64_to_cpu(u0->a),
678 le64_to_cpu(u0->b),
679 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 680 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 681 tx_buffer->next_to_watch,
682 (u64)tx_buffer->time_stamp,
683 tx_buffer->skb);
684 if (i == tx_ring->next_to_use &&
685 i == tx_ring->next_to_clean)
686 pr_cont(" NTC/U\n");
687 else if (i == tx_ring->next_to_use)
688 pr_cont(" NTU\n");
689 else if (i == tx_ring->next_to_clean)
690 pr_cont(" NTC\n");
691 else
692 pr_cont("\n");
693
694 if (netif_msg_pktdata(adapter) &&
695 tx_buffer->skb)
696 print_hex_dump(KERN_INFO, "",
697 DUMP_PREFIX_ADDRESS, 16, 1,
698 tx_buffer->skb->data,
699 dma_unmap_len(tx_buffer, len),
700 true);
701 }
dcd79aeb
TI		 702 }
703 }
704
705 /* Print RX Rings Summary */
706rx_ring_summary:
707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 708 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 709 for (n = 0; n < adapter->num_rx_queues; n++) {
710 rx_ring = adapter->rx_ring[n];
c7689578
JP		 711 pr_info("%5d %5X %5X\n",
712 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 713 }
714
715 /* Print RX Rings */
716 if (!netif_msg_rx_status(adapter))
e90dd264 717 return;
dcd79aeb
TI		 718
719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
720
39ac868a
JH		 721 /* Receive Descriptor Formats
722 *
723 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 724 * 63 1 0
725 * +-----------------------------------------------------+
726 * 0 | Packet Buffer Address [63:1] |A0/NSE|
727 * +----------------------------------------------+------+
728 * 8 | Header Buffer Address [63:1] | DD |
729 * +-----------------------------------------------------+
730 *
731 *
39ac868a 732 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 733 *
734 * 63 48 47 32 31 30 21 20 16 15 4 3 0
735 * +------------------------------------------------------+
39ac868a
JH		 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
737 * | Packet | IP | | | | Type | Type |
738 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 739 * +------------------------------------------------------+
740 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
741 * +------------------------------------------------------+
742 * 63 48 47 32 31 20 19 0
39ac868a
JH		 743 *
744 * 82599+ Advanced Receive Descriptor (Read) Format
745 * 63 1 0
746 * +-----------------------------------------------------+
747 * 0 | Packet Buffer Address [63:1] |A0/NSE|
748 * +----------------------------------------------+------+
749 * 8 | Header Buffer Address [63:1] | DD |
750 * +-----------------------------------------------------+
751 *
752 *
753 * 82599+ Advanced Receive Descriptor (Write-Back) Format
754 *
755 * 63 48 47 32 31 30 21 20 17 16 4 3 0
756 * +------------------------------------------------------+
757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
759 * |/ Flow Dir Flt ID | | | | | |
760 * +------------------------------------------------------+
761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
762 * +------------------------------------------------------+
763 * 63 48 47 32 31 20 19 0
dcd79aeb 764 */
39ac868a 765
dcd79aeb
TI		 766 for (n = 0; n < adapter->num_rx_queues; n++) {
767 rx_ring = adapter->rx_ring[n];
c7689578
JP		 768 pr_info("------------------------------------\n");
769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
770 pr_info("------------------------------------\n");
8ad88e37
JH		 771 pr_info("%s%s%s",
772 "R [desc] [ PktBuf A0] ",
773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 774 "<-- Adv Rx Read format\n");
8ad88e37
JH		 775 pr_info("%s%s%s",
776 "RWB[desc] [PcsmIpSHl PtRs] ",
777 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 778 "<-- Adv Rx Write-Back format\n");
779
780 for (i = 0; i < rx_ring->count; i++) {
781 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 782 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 783 u0 = (struct my_u0 *)rx_desc;
784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
785 if (staterr & IXGBE_RXD_STAT_DD) {
786 /* Descriptor Done */
c7689578 787 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 788 "%016llX ---------------- %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 rx_buffer_info->skb);
792 } else {
c7689578 793 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 794 "%016llX %016llX %p", i,
795 le64_to_cpu(u0->a),
796 le64_to_cpu(u0->b),
797 (u64)rx_buffer_info->dma,
798 rx_buffer_info->skb);
799
9c50c035
ET		 800 if (netif_msg_pktdata(adapter) &&
801 rx_buffer_info->dma) {
dcd79aeb
TI		 802 print_hex_dump(KERN_INFO, "",
803 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 804 page_address(rx_buffer_info->page) +
805 rx_buffer_info->page_offset,
f800326d 806 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 807 }
808 }
809
810 if (i == rx_ring->next_to_use)
c7689578 811 pr_cont(" NTU\n");
dcd79aeb 812 else if (i == rx_ring->next_to_clean)
c7689578 813 pr_cont(" NTC\n");
dcd79aeb 814 else
c7689578 815 pr_cont("\n");
dcd79aeb
TI		 816
817 }
818 }
dcd79aeb
TI		 819}
820
5eba3699
AV		 821static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
822{
823 u32 ctrl_ext;
824
825 /* Let firmware take over control of h/w */
826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 829}
830
831static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
832{
833 u32 ctrl_ext;
834
835 /* Let firmware know the driver has taken over */
836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 839}
9a799d71 840
49ce9c2c 841/**
e8e26350
PW		 842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
843 * @adapter: pointer to adapter struct
844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
845 * @queue: queue to map the corresponding interrupt to
846 * @msix_vector: the vector to map to the corresponding queue
847 *
848 */
849static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 850 u8 queue, u8 msix_vector)
9a799d71
AK		 851{
852 u32 ivar, index;
e8e26350
PW		 853 struct ixgbe_hw *hw = &adapter->hw;
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
857 if (direction == -1)
858 direction = 0;
859 index = (((direction * 64) + queue) >> 2) & 0x1F;
860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
861 ivar &= ~(0xFF << (8 * (queue & 0x3)));
862 ivar |= (msix_vector << (8 * (queue & 0x3)));
863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
864 break;
865 case ixgbe_mac_82599EB:
b93a2226 866 case ixgbe_mac_X540:
9a75a1ac
DS		 867 case ixgbe_mac_X550:
868 case ixgbe_mac_X550EM_x:
e8e26350
PW		 869 if (direction == -1) {
870 /* other causes */
871 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
872 index = ((queue & 1) * 8);
873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
874 ivar &= ~(0xFF << index);
875 ivar |= (msix_vector << index);
876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
877 break;
878 } else {
879 /* tx or rx causes */
880 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
881 index = ((16 * (queue & 1)) + (8 * direction));
882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
883 ivar &= ~(0xFF << index);
884 ivar |= (msix_vector << index);
885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
886 break;
887 }
888 default:
889 break;
890 }
9a799d71
AK		 891}
892
fe49f04a 893static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 894 u64 qmask)
fe49f04a
AD		 895{
896 u32 mask;
897
bd508178
AD		 898 switch (adapter->hw.mac.type) {
899 case ixgbe_mac_82598EB:
fe49f04a
AD		 900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 902 break;
903 case ixgbe_mac_82599EB:
b93a2226 904 case ixgbe_mac_X540:
9a75a1ac
DS		 905 case ixgbe_mac_X550:
906 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 907 mask = (qmask & 0xFFFFFFFF);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
909 mask = (qmask >> 32);
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 911 break;
912 default:
913 break;
fe49f04a
AD		 914 }
915}
916
729739b7
AD		 917void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
918 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 919{
729739b7
AD		 920 if (tx_buffer->skb) {
921 dev_kfree_skb_any(tx_buffer->skb);
922 if (dma_unmap_len(tx_buffer, len))
d3d00239 923 dma_unmap_single(ring->dev,
729739b7
AD		 924 dma_unmap_addr(tx_buffer, dma),
925 dma_unmap_len(tx_buffer, len),
926 DMA_TO_DEVICE);
927 } else if (dma_unmap_len(tx_buffer, len)) {
928 dma_unmap_page(ring->dev,
929 dma_unmap_addr(tx_buffer, dma),
930 dma_unmap_len(tx_buffer, len),
931 DMA_TO_DEVICE);
e5a43549 932 }
729739b7
AD		 933 tx_buffer->next_to_watch = NULL;
934 tx_buffer->skb = NULL;
935 dma_unmap_len_set(tx_buffer, len, 0);
936 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 937}
938
943561d3 939static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 940{
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 943 int i;
943561d3 944 u32 data;
c84d324c 945
943561d3
AD		 946 if ((hw->fc.current_mode != ixgbe_fc_full) &&
947 (hw->fc.current_mode != ixgbe_fc_rx_pause))
948 return;
c84d324c 949
943561d3
AD		 950 switch (hw->mac.type) {
951 case ixgbe_mac_82598EB:
952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
953 break;
954 default:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
956 }
957 hwstats->lxoffrxc += data;
c84d324c 958
943561d3
AD		 959 /* refill credits (no tx hang) if we received xoff */
960 if (!data)
c84d324c 961 return;
943561d3
AD		 962
963 for (i = 0; i < adapter->num_tx_queues; i++)
964 clear_bit(__IXGBE_HANG_CHECK_ARMED,
965 &adapter->tx_ring[i]->state);
966}
967
968static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
969{
970 struct ixgbe_hw *hw = &adapter->hw;
971 struct ixgbe_hw_stats *hwstats = &adapter->stats;
972 u32 xoff[8] = {0};
2afaa00d 973 u8 tc;
943561d3
AD		 974 int i;
975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
976
977 if (adapter->ixgbe_ieee_pfc)
978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
979
980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
981 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 982 return;
943561d3 983 }
c84d324c
JF		 984
985 /* update stats for each tc, only valid with PFC enabled */
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 987 u32 pxoffrxc;
988
c84d324c
JF		 989 switch (hw->mac.type) {
990 case ixgbe_mac_82598EB:
2afaa00d 991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 992 break;
c84d324c 993 default:
2afaa00d 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 995 }
2afaa00d
PN		 996 hwstats->pxoffrxc[i] += pxoffrxc;
997 /* Get the TC for given UP */
998 tc = netdev_get_prio_tc_map(adapter->netdev, i);
999 xoff[tc] += pxoffrxc;
c84d324c
JF		 1000 }
1001
1002 /* disarm tx queues that have received xoff frames */
1003 for (i = 0; i < adapter->num_tx_queues; i++) {
1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1005
2afaa00d 1006 tc = tx_ring->dcb_tc;
c84d324c
JF		 1007 if (xoff[tc])
1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1009 }
26f23d82
YZ		 1010}
1011
c84d324c 1012static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1013{
7d7ce682 1014 return ring->stats.packets;
c84d324c
JF		 1015}
1016
1017static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1018{
2a47fa45
JF		 1019 struct ixgbe_adapter *adapter;
1020 struct ixgbe_hw *hw;
1021 u32 head, tail;
1022
1023 if (ring->l2_accel_priv)
1024 adapter = ring->l2_accel_priv->real_adapter;
1025 else
1026 adapter = netdev_priv(ring->netdev);
e01c31a5 1027
2a47fa45
JF		 1028 hw = &adapter->hw;
1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1031
1032 if (head != tail)
1033 return (head < tail) ?
1034 tail - head : (tail + ring->count - head);
1035
1036 return 0;
1037}
1038
1039static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1040{
1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1044
7d637bcc 1045 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1046
1047 /*
1048 * Check for a hung queue, but be thorough. This verifies
1049 * that a transmit has been completed since the previous
1050 * check AND there is at least one packet pending. The
1051 * ARMED bit is set to indicate a potential hang. The
1052 * bit is cleared if a pause frame is received to remove
1053 * false hang detection due to PFC or 802.3x frames. By
1054 * requiring this to fail twice we avoid races with
1055 * pfc clearing the ARMED bit and conditions where we
1056 * run the check_tx_hang logic with a transmit completion
1057 * pending but without time to complete it yet.
1058 */
e90dd264 1059 if (tx_done_old == tx_done && tx_pending)
c84d324c 1060 /* make sure it is true for two checks in a row */
e90dd264
MR		 1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1062 &tx_ring->state);
1063 /* update completed stats and continue */
1064 tx_ring->tx_stats.tx_done_old = tx_done;
1065 /* reset the countdown */
1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1067
e90dd264 1068 return false;
9a799d71
AK		 1069}
1070
c83c6cbd
AD		 1071/**
1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1073 * @adapter: driver private struct
1074 **/
1075static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1076{
1077
1078 /* Do the reset outside of interrupt context */
1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1081 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1082 ixgbe_service_event_schedule(adapter);
1083 }
1084}
e01c31a5 1085
9a799d71
AK		 1086/**
1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1088 * @q_vector: structure containing interrupt and ring information
e01c31a5 1089 * @tx_ring: tx ring to clean
9a799d71 1090 **/
fe49f04a 1091static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1092 struct ixgbe_ring *tx_ring)
9a799d71 1093{
fe49f04a 1094 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1095 struct ixgbe_tx_buffer *tx_buffer;
1096 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1097 unsigned int total_bytes = 0, total_packets = 0;
59224555 1098 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1099 unsigned int i = tx_ring->next_to_clean;
1100
1101 if (test_bit(__IXGBE_DOWN, &adapter->state))
1102 return true;
9a799d71 1103
d3d00239 1104 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1105 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1106 i -= tx_ring->count;
12207e49 1107
729739b7 1108 do {
d3d00239
AD		 1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1110
1111 /* if next_to_watch is not set then there is no work pending */
1112 if (!eop_desc)
1113 break;
1114
7f83a9e6 1115 /* prevent any other reads prior to eop_desc */
7e63bf49 1116 read_barrier_depends();
7f83a9e6 1117
d3d00239
AD		 1118 /* if DD is not set pending work has not been completed */
1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1120 break;
8ad494b0 1121
d3d00239
AD		 1122 /* clear next_to_watch to prevent false hangs */
1123 tx_buffer->next_to_watch = NULL;
8ad494b0 1124
091a6246
AD		 1125 /* update the statistics for this packet */
1126 total_bytes += tx_buffer->bytecount;
1127 total_packets += tx_buffer->gso_segs;
1128
fd0db0ed 1129 /* free the skb */
fe1f2a97 1130 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1131
729739b7
AD		 1132 /* unmap skb header data */
1133 dma_unmap_single(tx_ring->dev,
1134 dma_unmap_addr(tx_buffer, dma),
1135 dma_unmap_len(tx_buffer, len),
1136 DMA_TO_DEVICE);
1137
fd0db0ed
AD		 1138 /* clear tx_buffer data */
1139 tx_buffer->skb = NULL;
729739b7 1140 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1141
729739b7
AD		 1142 /* unmap remaining buffers */
1143 while (tx_desc != eop_desc) {
d3d00239
AD		 1144 tx_buffer++;
1145 tx_desc++;
8ad494b0 1146 i++;
729739b7
AD		 1147 if (unlikely(!i)) {
1148 i -= tx_ring->count;
d3d00239 1149 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1151 }
e01c31a5 1152
729739b7
AD		 1153 /* unmap any remaining paged data */
1154 if (dma_unmap_len(tx_buffer, len)) {
1155 dma_unmap_page(tx_ring->dev,
1156 dma_unmap_addr(tx_buffer, dma),
1157 dma_unmap_len(tx_buffer, len),
1158 DMA_TO_DEVICE);
1159 dma_unmap_len_set(tx_buffer, len, 0);
1160 }
1161 }
1162
1163 /* move us one more past the eop_desc for start of next pkt */
1164 tx_buffer++;
1165 tx_desc++;
1166 i++;
1167 if (unlikely(!i)) {
1168 i -= tx_ring->count;
1169 tx_buffer = tx_ring->tx_buffer_info;
1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1171 }
1172
1173 /* issue prefetch for next Tx descriptor */
1174 prefetch(tx_desc);
12207e49 1175
729739b7
AD		 1176 /* update budget accounting */
1177 budget--;
1178 } while (likely(budget));
1179
1180 i += tx_ring->count;
9a799d71 1181 tx_ring->next_to_clean = i;
d3d00239 1182 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1183 tx_ring->stats.bytes += total_bytes;
bd198058 1184 tx_ring->stats.packets += total_packets;
d3d00239 1185 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1186 q_vector->tx.total_bytes += total_bytes;
1187 q_vector->tx.total_packets += total_packets;
b953799e 1188
c84d324c
JF		 1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1190 /* schedule immediate reset if we believe we hung */
1191 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1192 e_err(drv, "Detected Tx Unit Hang\n"
1193 " Tx Queue <%d>\n"
1194 " TDH, TDT <%x>, <%x>\n"
1195 " next_to_use <%x>\n"
1196 " next_to_clean <%x>\n"
1197 "tx_buffer_info[next_to_clean]\n"
1198 " time_stamp <%lx>\n"
1199 " jiffies <%lx>\n",
1200 tx_ring->queue_index,
1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1203 tx_ring->next_to_use, i,
1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1205
1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1207
1208 e_info(probe,
1209 "tx hang %d detected on queue %d, resetting adapter\n",
1210 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1211
b953799e 1212 /* schedule immediate reset if we believe we hung */
c83c6cbd 1213 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1214
1215 /* the adapter is about to reset, no point in enabling stuff */
59224555 1216 return true;
b953799e 1217 }
9a799d71 1218
b2d96e0a
AD		 1219 netdev_tx_completed_queue(txring_txq(tx_ring),
1220 total_packets, total_bytes);
1221
e092be60 1222#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1225 /* Make sure that anybody stopping the queue after this
1226 * sees the new next_to_clean.
1227 */
1228 smp_mb();
729739b7
AD		 1229 if (__netif_subqueue_stopped(tx_ring->netdev,
1230 tx_ring->queue_index)
1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1232 netif_wake_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
5b7da515 1234 ++tx_ring->tx_stats.restart_queue;
30eba97a 1235 }
e092be60 1236 }
9a799d71 1237
59224555 1238 return !!budget;
9a799d71
AK		 1239}
1240
5dd2d332 1241#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1242static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1243 struct ixgbe_ring *tx_ring,
33cf09c9 1244 int cpu)
bd0362dd 1245{
33cf09c9 1246 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1247 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1248 u16 reg_offset;
33cf09c9 1249
33cf09c9
AD		 1250 switch (hw->mac.type) {
1251 case ixgbe_mac_82598EB:
bdda1a61 1252 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1253 break;
1254 case ixgbe_mac_82599EB:
b93a2226 1255 case ixgbe_mac_X540:
bdda1a61
AD		 1256 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1257 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1258 break;
1259 default:
bdda1a61
AD		 1260 /* for unknown hardware do not write register */
1261 return;
bd0362dd 1262 }
bdda1a61
AD		 1263
1264 /*
1265 * We can enable relaxed ordering for reads, but not writes when
1266 * DCA is enabled. This is due to a known issue in some chipsets
1267 * which will cause the DCA tag to be cleared.
1268 */
1269 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1270 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1271 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1272
1273 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1274}
1275
bdda1a61
AD		 1276static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1277 struct ixgbe_ring *rx_ring,
33cf09c9 1278 int cpu)
bd0362dd 1279{
33cf09c9 1280 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1281 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1282 u8 reg_idx = rx_ring->reg_idx;
1283
33cf09c9
AD		 1284
1285 switch (hw->mac.type) {
33cf09c9 1286 case ixgbe_mac_82599EB:
b93a2226 1287 case ixgbe_mac_X540:
bdda1a61 1288 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1289 break;
1290 default:
1291 break;
1292 }
bdda1a61
AD		 1293
1294 /*
1295 * We can enable relaxed ordering for reads, but not writes when
1296 * DCA is enabled. This is due to a known issue in some chipsets
1297 * which will cause the DCA tag to be cleared.
1298 */
1299 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1300 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1301
1302 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1303}
1304
1305static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1306{
1307 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1308 struct ixgbe_ring *ring;
bd0362dd 1309 int cpu = get_cpu();
bd0362dd 1310
33cf09c9
AD		 1311 if (q_vector->cpu == cpu)
1312 goto out_no_update;
1313
a557928e 1314 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1315 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1316
a557928e 1317 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1318 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1319
1320 q_vector->cpu = cpu;
1321out_no_update:
bd0362dd
JC		 1322 put_cpu();
1323}
1324
1325static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1326{
1327 int i;
1328
1329 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1330 return;
1331
e35ec126
AD		 1332 /* always use CB2 mode, difference is masked in the CB driver */
1333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1334
49c7ffbe 1335 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1336 adapter->q_vector[i]->cpu = -1;
1337 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1338 }
1339}
1340
1341static int __ixgbe_notify_dca(struct device *dev, void *data)
1342{
c60fbb00 1343 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1344 unsigned long event = *(unsigned long *)data;
1345
2a72c31e 1346 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1347 return 0;
1348
bd0362dd
JC		 1349 switch (event) {
1350 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1351 /* if we're already enabled, don't do it again */
1352 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1353 break;
652f093f 1354 if (dca_add_requester(dev) == 0) {
96b0e0f6 1355 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1356 ixgbe_setup_dca(adapter);
1357 break;
1358 }
1359 /* Fall Through since DCA is disabled. */
1360 case DCA_PROVIDER_REMOVE:
1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1362 dca_remove_requester(dev);
1363 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1365 }
1366 break;
1367 }
1368
652f093f 1369 return 0;
bd0362dd 1370}
67a74ee2 1371
bdda1a61 1372#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1373
1374#define IXGBE_RSS_L4_TYPES_MASK \
1375 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1376 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1377 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1378 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1379
8a0da21b
AD		 1380static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1381 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1382 struct sk_buff *skb)
1383{
7edda4b8
FD		 1384 u16 rss_type;
1385
1386 if (!(ring->netdev->features & NETIF_F_RXHASH))
1387 return;
1388
1389 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1390 IXGBE_RXDADV_RSSTYPE_MASK;
1391
1392 if (!rss_type)
1393 return;
1394
1395 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1396 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1397 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1398}
1399
f800326d 1400#ifdef IXGBE_FCOE
ff886dfc
AD		 1401/**
1402 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1403 * @ring: structure containing ring specific data
ff886dfc
AD		 1404 * @rx_desc: advanced rx descriptor
1405 *
1406 * Returns : true if it is FCoE pkt
1407 */
57efd44c 1408static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1409 union ixgbe_adv_rx_desc *rx_desc)
1410{
1411 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1412
57efd44c 1413 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1414 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1415 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1416 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1417}
1418
f800326d 1419#endif /* IXGBE_FCOE */
e59bd25d
AV		 1420/**
1421 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1422 * @ring: structure containing ring specific data
1423 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1424 * @skb: skb currently being received and modified
1425 **/
8a0da21b 1426static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1427 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1428 struct sk_buff *skb)
9a799d71 1429{
3f207800
DS		 1430 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1431 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1432 bool encap_pkt = false;
1433
8a0da21b 1434 skb_checksum_none_assert(skb);
9a799d71 1435
712744be 1436 /* Rx csum disabled */
8a0da21b 1437 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1438 return;
e59bd25d 1439
3f207800
DS		 1440 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1441 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1442 encap_pkt = true;
1443 skb->encapsulation = 1;
3f207800
DS		 1444 }
1445
e59bd25d 1446 /* if IP and error */
f56e0cb1
AD		 1447 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1448 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1449 ring->rx_stats.csum_err++;
9a799d71
AK		 1450 return;
1451 }
e59bd25d 1452
f56e0cb1 1453 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1454 return;
1455
f56e0cb1 1456 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1457 /*
1458 * 82599 errata, UDP frames with a 0 checksum can be marked as
1459 * checksum errors.
1460 */
8a0da21b
AD		 1461 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1462 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1463 return;
1464
8a0da21b 1465 ring->rx_stats.csum_err++;
e59bd25d
AV		 1466 return;
1467 }
1468
9a799d71 1469 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1470 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1471 if (encap_pkt) {
1472 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1473 return;
1474
1475 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1476 ring->rx_stats.csum_err++;
1477 return;
1478 }
1479 /* If we checked the outer header let the stack know */
1480 skb->csum_level = 1;
1481 }
9a799d71
AK		 1482}
1483
f990b79b
AD		 1484static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1485 struct ixgbe_rx_buffer *bi)
1486{
1487 struct page *page = bi->page;
18cb652a 1488 dma_addr_t dma;
f990b79b 1489
f800326d 1490 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1491 if (likely(page))
f990b79b
AD		 1492 return true;
1493
f800326d 1494 /* alloc new page for storage */
18cb652a
AD		 1495 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1496 if (unlikely(!page)) {
1497 rx_ring->rx_stats.alloc_rx_page_failed++;
1498 return false;
f990b79b
AD		 1499 }
1500
f800326d
AD		 1501 /* map page for use */
1502 dma = dma_map_page(rx_ring->dev, page, 0,
1503 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1504
1505 /*
1506 * if mapping failed free memory back to system since
1507 * there isn't much point in holding memory we can't use
1508 */
1509 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1510 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1511
f990b79b
AD		 1512 rx_ring->rx_stats.alloc_rx_page_failed++;
1513 return false;
1514 }
1515
f800326d 1516 bi->dma = dma;
18cb652a 1517 bi->page = page;
afaa9459 1518 bi->page_offset = 0;
f800326d 1519
f990b79b
AD		 1520 return true;
1521}
1522
9a799d71 1523/**
f990b79b 1524 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1525 * @rx_ring: ring to place buffers on
1526 * @cleaned_count: number of buffers to replace
9a799d71 1527 **/
fc77dc3c 1528void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1529{
9a799d71 1530 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1531 struct ixgbe_rx_buffer *bi;
d5f398ed 1532 u16 i = rx_ring->next_to_use;
9a799d71 1533
f800326d
AD		 1534 /* nothing to do */
1535 if (!cleaned_count)
fc77dc3c
AD		 1536 return;
1537
e4f74028 1538 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1539 bi = &rx_ring->rx_buffer_info[i];
1540 i -= rx_ring->count;
9a799d71 1541
f800326d
AD		 1542 do {
1543 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1544 break;
d5f398ed 1545
f800326d
AD		 1546 /*
1547 * Refresh the desc even if buffer_addrs didn't change
1548 * because each write-back erases this info.
1549 */
1550 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1551
f990b79b
AD		 1552 rx_desc++;
1553 bi++;
9a799d71 1554 i++;
f990b79b 1555 if (unlikely(!i)) {
e4f74028 1556 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1557 bi = rx_ring->rx_buffer_info;
1558 i -= rx_ring->count;
1559 }
1560
18cb652a
AD		 1561 /* clear the status bits for the next_to_use descriptor */
1562 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1563
1564 cleaned_count--;
1565 } while (cleaned_count);
7c6e0a43 1566
f990b79b
AD		 1567 i += rx_ring->count;
1568
ad435ec6
AD		 1569 if (rx_ring->next_to_use != i) {
1570 rx_ring->next_to_use = i;
1571
1572 /* update next to alloc since we have filled the ring */
1573 rx_ring->next_to_alloc = i;
1574
1575 /* Force memory writes to complete before letting h/w
1576 * know there are new descriptors to fetch. (Only
1577 * applicable for weak-ordered memory model archs,
1578 * such as IA-64).
1579 */
1580 wmb();
1581 writel(i, rx_ring->tail);
1582 }
9a799d71
AK		 1583}
1584
1d2024f6
AD		 1585static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1586 struct sk_buff *skb)
1587{
f800326d 1588 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1589
1590 /* set gso_size to avoid messing up TCP MSS */
1591 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1592 IXGBE_CB(skb)->append_cnt);
96be80ab 1593 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1594}
1595
1596static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1597 struct sk_buff *skb)
1598{
1599 /* if append_cnt is 0 then frame is not RSC */
1600 if (!IXGBE_CB(skb)->append_cnt)
1601 return;
1602
1603 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1604 rx_ring->rx_stats.rsc_flush++;
1605
1606 ixgbe_set_rsc_gso_size(rx_ring, skb);
1607
1608 /* gso_size is computed using append_cnt so always clear it last */
1609 IXGBE_CB(skb)->append_cnt = 0;
1610}
1611
8a0da21b
AD		 1612/**
1613 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1614 * @rx_ring: rx descriptor ring packet is being transacted on
1615 * @rx_desc: pointer to the EOP Rx descriptor
1616 * @skb: pointer to current skb being populated
f8212f97 1617 *
8a0da21b
AD		 1618 * This function checks the ring, descriptor, and packet information in
1619 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1620 * other fields within the skb.
f8212f97 1621 **/
8a0da21b
AD		 1622static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1623 union ixgbe_adv_rx_desc *rx_desc,
1624 struct sk_buff *skb)
f8212f97 1625{
43e95f11
JF		 1626 struct net_device *dev = rx_ring->netdev;
1627
8a0da21b
AD		 1628 ixgbe_update_rsc_stats(rx_ring, skb);
1629
1630 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1631
8a0da21b
AD		 1632 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1633
eda183c2
JK		 1634 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1635 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1636
f646968f 1637 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1638 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1639 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1640 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1641 }
1642
8a0da21b 1643 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1644
43e95f11 1645 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1646}
1647
8a0da21b
AD		 1648static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1649 struct sk_buff *skb)
aa80175a 1650{
b4640030 1651 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1652 netif_receive_skb(skb);
8a0da21b 1653 else
856f606e 1654 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1655}
43634e82 1656
f800326d
AD		 1657/**
1658 * ixgbe_is_non_eop - process handling of non-EOP buffers
1659 * @rx_ring: Rx ring being processed
1660 * @rx_desc: Rx descriptor for current buffer
1661 * @skb: Current socket buffer containing buffer in progress
1662 *
1663 * This function updates next to clean. If the buffer is an EOP buffer
1664 * this function exits returning false, otherwise it will place the
1665 * sk_buff in the next buffer to be chained and return true indicating
1666 * that this is in fact a non-EOP buffer.
1667 **/
1668static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1669 union ixgbe_adv_rx_desc *rx_desc,
1670 struct sk_buff *skb)
1671{
1672 u32 ntc = rx_ring->next_to_clean + 1;
1673
1674 /* fetch, update, and store next to clean */
1675 ntc = (ntc < rx_ring->count) ? ntc : 0;
1676 rx_ring->next_to_clean = ntc;
1677
1678 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1679
5a02cbd1
AD		 1680 /* update RSC append count if present */
1681 if (ring_is_rsc_enabled(rx_ring)) {
1682 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1683 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1684
1685 if (unlikely(rsc_enabled)) {
1686 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1687
1688 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1689 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1690
5a02cbd1
AD		 1691 /* update ntc based on RSC value */
1692 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1693 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1694 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1695 }
f800326d
AD		 1696 }
1697
5a02cbd1
AD		 1698 /* if we are the last buffer then there is nothing else to do */
1699 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1700 return false;
1701
f800326d
AD		 1702 /* place skb in next buffer to be received */
1703 rx_ring->rx_buffer_info[ntc].skb = skb;
1704 rx_ring->rx_stats.non_eop_descs++;
1705
1706 return true;
1707}
1708
19861ce2
AD		 1709/**
1710 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1711 * @rx_ring: rx descriptor ring packet is being transacted on
1712 * @skb: pointer to current skb being adjusted
1713 *
1714 * This function is an ixgbe specific version of __pskb_pull_tail. The
1715 * main difference between this version and the original function is that
1716 * this function can make several assumptions about the state of things
1717 * that allow for significant optimizations versus the standard function.
1718 * As a result we can do things like drop a frag and maintain an accurate
1719 * truesize for the skb.
1720 */
1721static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1722 struct sk_buff *skb)
1723{
1724 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1725 unsigned char *va;
1726 unsigned int pull_len;
1727
1728 /*
1729 * it is valid to use page_address instead of kmap since we are
1730 * working with pages allocated out of the lomem pool per
1731 * alloc_page(GFP_ATOMIC)
1732 */
1733 va = skb_frag_address(frag);
1734
1735 /*
1736 * we need the header to contain the greater of either ETH_HLEN or
1737 * 60 bytes if the skb->len is less than 60 for skb_pad.
1738 */
8496e338 1739 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1740
1741 /* align pull length to size of long to optimize memcpy performance */
1742 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1743
1744 /* update all of the pointers */
1745 skb_frag_size_sub(frag, pull_len);
1746 frag->page_offset += pull_len;
1747 skb->data_len -= pull_len;
1748 skb->tail += pull_len;
19861ce2
AD		 1749}
1750
42073d91
AD		 1751/**
1752 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1753 * @rx_ring: rx descriptor ring packet is being transacted on
1754 * @skb: pointer to current skb being updated
1755 *
1756 * This function provides a basic DMA sync up for the first fragment of an
1757 * skb. The reason for doing this is that the first fragment cannot be
1758 * unmapped until we have reached the end of packet descriptor for a buffer
1759 * chain.
1760 */
1761static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1762 struct sk_buff *skb)
1763{
1764 /* if the page was released unmap it, else just sync our portion */
1765 if (unlikely(IXGBE_CB(skb)->page_released)) {
1766 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1767 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1768 IXGBE_CB(skb)->page_released = false;
1769 } else {
1770 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1771
1772 dma_sync_single_range_for_cpu(rx_ring->dev,
1773 IXGBE_CB(skb)->dma,
1774 frag->page_offset,
1775 ixgbe_rx_bufsz(rx_ring),
1776 DMA_FROM_DEVICE);
1777 }
1778 IXGBE_CB(skb)->dma = 0;
1779}
1780
f800326d
AD		 1781/**
1782 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1783 * @rx_ring: rx descriptor ring packet is being transacted on
1784 * @rx_desc: pointer to the EOP Rx descriptor
1785 * @skb: pointer to current skb being fixed
1786 *
1787 * Check for corrupted packet headers caused by senders on the local L2
1788 * embedded NIC switch not setting up their Tx Descriptors right. These
1789 * should be very rare.
1790 *
1791 * Also address the case where we are pulling data in on pages only
1792 * and as such no data is present in the skb header.
1793 *
1794 * In addition if skb is not at least 60 bytes we need to pad it so that
1795 * it is large enough to qualify as a valid Ethernet frame.
1796 *
1797 * Returns true if an error was encountered and skb was freed.
1798 **/
1799static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1800 union ixgbe_adv_rx_desc *rx_desc,
1801 struct sk_buff *skb)
1802{
f800326d 1803 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1804
1805 /* verify that the packet does not have any known errors */
1806 if (unlikely(ixgbe_test_staterr(rx_desc,
1807 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1808 !(netdev->features & NETIF_F_RXALL))) {
1809 dev_kfree_skb_any(skb);
1810 return true;
1811 }
1812
19861ce2 1813 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1814 if (skb_is_nonlinear(skb))
1815 ixgbe_pull_tail(rx_ring, skb);
f800326d 1816
57efd44c
AD		 1817#ifdef IXGBE_FCOE
1818 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1819 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1820 return false;
1821
1822#endif
a94d9e22
AD		 1823 /* if eth_skb_pad returns an error the skb was freed */
1824 if (eth_skb_pad(skb))
1825 return true;
f800326d
AD		 1826
1827 return false;
1828}
1829
f800326d
AD		 1830/**
1831 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1832 * @rx_ring: rx descriptor ring to store buffers on
1833 * @old_buff: donor buffer to have page reused
1834 *
0549ae20 1835 * Synchronizes page for reuse by the adapter
f800326d
AD		 1836 **/
1837static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1838 struct ixgbe_rx_buffer *old_buff)
1839{
1840 struct ixgbe_rx_buffer *new_buff;
1841 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1842
1843 new_buff = &rx_ring->rx_buffer_info[nta];
1844
1845 /* update, and store next to alloc */
1846 nta++;
1847 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1848
1849 /* transfer page from old buffer to new buffer */
18cb652a 1850 *new_buff = *old_buff;
f800326d
AD		 1851
1852 /* sync the buffer for use by the device */
1853 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1854 new_buff->page_offset,
1855 ixgbe_rx_bufsz(rx_ring),
f800326d 1856 DMA_FROM_DEVICE);
f800326d
AD		 1857}
1858
18cb652a
AD		 1859static inline bool ixgbe_page_is_reserved(struct page *page)
1860{
2f064f34 1861 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1862}
1863
f800326d
AD		 1864/**
1865 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1866 * @rx_ring: rx descriptor ring to transact packets on
1867 * @rx_buffer: buffer containing page to add
1868 * @rx_desc: descriptor containing length of buffer written by hardware
1869 * @skb: sk_buff to place the data into
1870 *
0549ae20
AD		 1871 * This function will add the data contained in rx_buffer->page to the skb.
1872 * This is done either through a direct copy if the data in the buffer is
1873 * less than the skb header size, otherwise it will just attach the page as
1874 * a frag to the skb.
1875 *
1876 * The function will then update the page offset if necessary and return
1877 * true if the buffer can be reused by the adapter.
f800326d 1878 **/
0549ae20 1879static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1880 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1881 union ixgbe_adv_rx_desc *rx_desc,
1882 struct sk_buff *skb)
f800326d 1883{
0549ae20
AD		 1884 struct page *page = rx_buffer->page;
1885 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1886#if (PAGE_SIZE < 8192)
0549ae20 1887 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1888#else
1889 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1890 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1891 ixgbe_rx_bufsz(rx_ring);
1892#endif
0549ae20 1893
cf3fe7ac
AD		 1894 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1895 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1896
1897 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1898
18cb652a
AD		 1899 /* page is not reserved, we can reuse buffer as-is */
1900 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1901 return true;
1902
1903 /* this page cannot be reused so discard it */
18cb652a 1904 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1905 return false;
1906 }
1907
0549ae20
AD		 1908 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1909 rx_buffer->page_offset, size, truesize);
1910
09816fbe 1911 /* avoid re-using remote pages */
18cb652a 1912 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1913 return false;
1914
1915#if (PAGE_SIZE < 8192)
1916 /* if we are only owner of page we can reuse it */
1917 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1918 return false;
1919
1920 /* flip page offset to other buffer */
1921 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1922#else
1923 /* move offset up to the next cache line */
1924 rx_buffer->page_offset += truesize;
1925
1926 if (rx_buffer->page_offset > last_offset)
1927 return false;
09816fbe 1928#endif
0549ae20 1929
18cb652a
AD		 1930 /* Even if we own the page, we are not allowed to use atomic_set()
1931 * This would break get_page_unless_zero() users.
1932 */
1933 atomic_inc(&page->_count);
1934
0549ae20 1935 return true;
f800326d
AD		 1936}
1937
18806c9e
AD		 1938static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1939 union ixgbe_adv_rx_desc *rx_desc)
1940{
1941 struct ixgbe_rx_buffer *rx_buffer;
1942 struct sk_buff *skb;
1943 struct page *page;
1944
1945 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1946 page = rx_buffer->page;
1947 prefetchw(page);
1948
1949 skb = rx_buffer->skb;
1950
1951 if (likely(!skb)) {
1952 void *page_addr = page_address(page) +
1953 rx_buffer->page_offset;
1954
1955 /* prefetch first cache line of first page */
1956 prefetch(page_addr);
1957#if L1_CACHE_BYTES < 128
1958 prefetch(page_addr + L1_CACHE_BYTES);
1959#endif
1960
1961 /* allocate a skb to store the frags */
67fd893e
AD		 1962 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1963 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1964 if (unlikely(!skb)) {
1965 rx_ring->rx_stats.alloc_rx_buff_failed++;
1966 return NULL;
1967 }
1968
1969 /*
1970 * we will be copying header into skb->data in
1971 * pskb_may_pull so it is in our interest to prefetch
1972 * it now to avoid a possible cache miss
1973 */
1974 prefetchw(skb->data);
1975
1976 /*
1977 * Delay unmapping of the first packet. It carries the
1978 * header information, HW may still access the header
1979 * after the writeback. Only unmap it when EOP is
1980 * reached
1981 */
1982 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1983 goto dma_sync;
1984
1985 IXGBE_CB(skb)->dma = rx_buffer->dma;
1986 } else {
1987 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1988 ixgbe_dma_sync_frag(rx_ring, skb);
1989
1990dma_sync:
1991 /* we are reusing so sync this buffer for CPU use */
1992 dma_sync_single_range_for_cpu(rx_ring->dev,
1993 rx_buffer->dma,
1994 rx_buffer->page_offset,
1995 ixgbe_rx_bufsz(rx_ring),
1996 DMA_FROM_DEVICE);
18cb652a
AD		 1997
1998 rx_buffer->skb = NULL;
18806c9e
AD		 1999 }
2000
2001 /* pull page into skb */
2002 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2003 /* hand second half of page back to the ring */
2004 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2005 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2006 /* the page has been released from the ring */
2007 IXGBE_CB(skb)->page_released = true;
2008 } else {
2009 /* we are not reusing the buffer so unmap it */
2010 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2011 ixgbe_rx_pg_size(rx_ring),
2012 DMA_FROM_DEVICE);
2013 }
2014
2015 /* clear contents of buffer_info */
18806c9e
AD		 2016 rx_buffer->page = NULL;
2017
2018 return skb;
f800326d
AD		 2019}
2020
2021/**
2022 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2023 * @q_vector: structure containing interrupt and ring information
2024 * @rx_ring: rx descriptor ring to transact packets on
2025 * @budget: Total limit on number of packets to process
2026 *
2027 * This function provides a "bounce buffer" approach to Rx interrupt
2028 * processing. The advantage to this is that on systems that have
2029 * expensive overhead for IOMMU access this provides a means of avoiding
2030 * it by maintaining the mapping of the page to the syste.
2031 *
5a85e737 2032 * Returns amount of work completed
f800326d 2033 **/
5a85e737 2034static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2035 struct ixgbe_ring *rx_ring,
f4de00ed 2036 const int budget)
9a799d71 2037{
d2f4fbe2 2038 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2039#ifdef IXGBE_FCOE
f800326d 2040 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2041 int ddp_bytes;
2042 unsigned int mss = 0;
3d8fd385 2043#endif /* IXGBE_FCOE */
f800326d 2044 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2045
fdabfc8a 2046 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2047 union ixgbe_adv_rx_desc *rx_desc;
2048 struct sk_buff *skb;
f800326d
AD		 2049
2050 /* return some buffers to hardware, one at a time is too slow */
2051 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2052 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2053 cleaned_count = 0;
2054 }
2055
18806c9e 2056 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2057
124b74c1 2058 if (!rx_desc->wb.upper.status_error)
f800326d 2059 break;
9a799d71 2060
124b74c1 2061 /* This memory barrier is needed to keep us from reading
f800326d 2062 * any other fields out of the rx_desc until we know the
124b74c1 2063 * descriptor has been written back
f800326d 2064 */
124b74c1 2065 dma_rmb();
9a799d71 2066
18806c9e
AD		 2067 /* retrieve a buffer from the ring */
2068 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2069
18806c9e
AD		 2070 /* exit if we failed to retrieve a buffer */
2071 if (!skb)
2072 break;
9a799d71 2073
9a799d71 2074 cleaned_count++;
f8212f97 2075
f800326d
AD		 2076 /* place incomplete frames back on ring for completion */
2077 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2078 continue;
c267fc16 2079
f800326d
AD		 2080 /* verify the packet layout is correct */
2081 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2082 continue;
9a799d71 2083
d2f4fbe2
AV		 2084 /* probably a little skewed due to removing CRC */
2085 total_rx_bytes += skb->len;
d2f4fbe2 2086
8a0da21b
AD		 2087 /* populate checksum, timestamp, VLAN, and protocol */
2088 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2089
332d4a7d
YZ		 2090#ifdef IXGBE_FCOE
2091 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2092 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2093 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2094 /* include DDPed FCoE data */
2095 if (ddp_bytes > 0) {
2096 if (!mss) {
2097 mss = rx_ring->netdev->mtu -
2098 sizeof(struct fcoe_hdr) -
2099 sizeof(struct fc_frame_header) -
2100 sizeof(struct fcoe_crc_eof);
2101 if (mss > 512)
2102 mss &= ~511;
2103 }
2104 total_rx_bytes += ddp_bytes;
2105 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2106 mss);
2107 }
63d635b2
AD		 2108 if (!ddp_bytes) {
2109 dev_kfree_skb_any(skb);
f800326d 2110 continue;
63d635b2 2111 }
3d8fd385 2112 }
f800326d 2113
332d4a7d 2114#endif /* IXGBE_FCOE */
8b80cda5 2115 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2116 ixgbe_rx_skb(q_vector, skb);
9a799d71 2117
f800326d 2118 /* update budget accounting */
f4de00ed 2119 total_rx_packets++;
fdabfc8a 2120 }
9a799d71 2121
c267fc16
AD		 2122 u64_stats_update_begin(&rx_ring->syncp);
2123 rx_ring->stats.packets += total_rx_packets;
2124 rx_ring->stats.bytes += total_rx_bytes;
2125 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2126 q_vector->rx.total_packets += total_rx_packets;
2127 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2128
5a85e737 2129 return total_rx_packets;
9a799d71
AK		 2130}
2131
e0d1095a 2132#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2133/* must be called with local_bh_disable()d */
2134static int ixgbe_low_latency_recv(struct napi_struct *napi)
2135{
2136 struct ixgbe_q_vector *q_vector =
2137 container_of(napi, struct ixgbe_q_vector, napi);
2138 struct ixgbe_adapter *adapter = q_vector->adapter;
2139 struct ixgbe_ring *ring;
2140 int found = 0;
2141
2142 if (test_bit(__IXGBE_DOWN, &adapter->state))
2143 return LL_FLUSH_FAILED;
2144
2145 if (!ixgbe_qv_lock_poll(q_vector))
2146 return LL_FLUSH_BUSY;
2147
2148 ixgbe_for_each_ring(ring, q_vector->rx) {
2149 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2150#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2151 if (found)
2152 ring->stats.cleaned += found;
2153 else
2154 ring->stats.misses++;
2155#endif
5a85e737
ET		 2156 if (found)
2157 break;
2158 }
2159
2160 ixgbe_qv_unlock_poll(q_vector);
2161
2162 return found;
2163}
e0d1095a 2164#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2165
9a799d71
AK		 2166/**
2167 * ixgbe_configure_msix - Configure MSI-X hardware
2168 * @adapter: board private structure
2169 *
2170 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2171 * interrupts.
2172 **/
2173static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2174{
021230d4 2175 struct ixgbe_q_vector *q_vector;
49c7ffbe 2176 int v_idx;
021230d4 2177 u32 mask;
9a799d71 2178
8e34d1aa
AD		 2179 /* Populate MSIX to EITR Select */
2180 if (adapter->num_vfs > 32) {
2181 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2183 }
2184
4df10466
JB		 2185 /*
2186 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2187 * corresponding register.
2188 */
49c7ffbe 2189 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2190 struct ixgbe_ring *ring;
7a921c93 2191 q_vector = adapter->q_vector[v_idx];
021230d4 2192
a557928e 2193 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2194 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2195
a557928e 2196 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2197 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2198
fe49f04a 2199 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2200 }
2201
bd508178
AD		 2202 switch (adapter->hw.mac.type) {
2203 case ixgbe_mac_82598EB:
e8e26350 2204 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2205 v_idx);
bd508178
AD		 2206 break;
2207 case ixgbe_mac_82599EB:
b93a2226 2208 case ixgbe_mac_X540:
9a75a1ac
DS		 2209 case ixgbe_mac_X550:
2210 case ixgbe_mac_X550EM_x:
e8e26350 2211 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2212 break;
bd508178
AD		 2213 default:
2214 break;
2215 }
021230d4
AV		 2216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2217
41fb9248 2218 /* set up to autoclear timer, and the vectors */
021230d4 2219 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2220 mask &= ~(IXGBE_EIMS_OTHER |
2221 IXGBE_EIMS_MAILBOX |
2222 IXGBE_EIMS_LSC);
2223
021230d4 2224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2225}
2226
f494e8fa
AV		 2227enum latency_range {
2228 lowest_latency = 0,
2229 low_latency = 1,
2230 bulk_latency = 2,
2231 latency_invalid = 255
2232};
2233
2234/**
2235 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2236 * @q_vector: structure containing interrupt and ring information
2237 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2238 *
2239 * Stores a new ITR value based on packets and byte
2240 * counts during the last interrupt. The advantage of per interrupt
2241 * computation is faster updates and more accurate ITR for the current
2242 * traffic pattern. Constants in this function were computed
2243 * based on theoretical maximum wire speed and thresholds were set based
2244 * on testing data as well as attempting to minimize response time
2245 * while increasing bulk throughput.
2246 * this functionality is controlled by the InterruptThrottleRate module
2247 * parameter (see ixgbe_param.c)
2248 **/
bd198058
AD		 2249static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2250 struct ixgbe_ring_container *ring_container)
f494e8fa 2251{
bd198058
AD		 2252 int bytes = ring_container->total_bytes;
2253 int packets = ring_container->total_packets;
2254 u32 timepassed_us;
621bd70e 2255 u64 bytes_perint;
bd198058 2256 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2257
2258 if (packets == 0)
bd198058 2259 return;
f494e8fa
AV		 2260
2261 /* simple throttlerate management
621bd70e
AD		 2262 * 0-10MB/s lowest (100000 ints/s)
2263 * 10-20MB/s low (20000 ints/s)
8ac34f10 2264 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2265 */
2266 /* what was last interrupt timeslice? */
d5bf4f67 2267 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2268 if (timepassed_us == 0)
2269 return;
2270
f494e8fa
AV		 2271 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2272
2273 switch (itr_setting) {
2274 case lowest_latency:
621bd70e 2275 if (bytes_perint > 10)
bd198058 2276 itr_setting = low_latency;
f494e8fa
AV		 2277 break;
2278 case low_latency:
621bd70e 2279 if (bytes_perint > 20)
bd198058 2280 itr_setting = bulk_latency;
621bd70e 2281 else if (bytes_perint <= 10)
bd198058 2282 itr_setting = lowest_latency;
f494e8fa
AV		 2283 break;
2284 case bulk_latency:
621bd70e 2285 if (bytes_perint <= 20)
bd198058 2286 itr_setting = low_latency;
f494e8fa
AV		 2287 break;
2288 }
2289
bd198058
AD		 2290 /* clear work counters since we have the values we need */
2291 ring_container->total_bytes = 0;
2292 ring_container->total_packets = 0;
2293
2294 /* write updated itr to ring container */
2295 ring_container->itr = itr_setting;
f494e8fa
AV		 2296}
2297
509ee935
JB		 2298/**
2299 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2300 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2301 *
2302 * This function is made to be called by ethtool and by the driver
2303 * when it needs to update EITR registers at runtime. Hardware
2304 * specific quirks/differences are taken care of here.
2305 */
fe49f04a 2306void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2307{
fe49f04a 2308 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2309 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2310 int v_idx = q_vector->v_idx;
5d967eb7 2311 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2312
bd508178
AD		 2313 switch (adapter->hw.mac.type) {
2314 case ixgbe_mac_82598EB:
509ee935
JB		 2315 /* must write high and low 16 bits to reset counter */
2316 itr_reg |= (itr_reg << 16);
bd508178
AD		 2317 break;
2318 case ixgbe_mac_82599EB:
b93a2226 2319 case ixgbe_mac_X540:
9a75a1ac
DS		 2320 case ixgbe_mac_X550:
2321 case ixgbe_mac_X550EM_x:
509ee935
JB		 2322 /*
2323 * set the WDIS bit to not clear the timer bits and cause an
2324 * immediate assertion of the interrupt
2325 */
2326 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2327 break;
2328 default:
2329 break;
509ee935
JB		 2330 }
2331 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2332}
2333
bd198058 2334static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2335{
d5bf4f67 2336 u32 new_itr = q_vector->itr;
bd198058 2337 u8 current_itr;
f494e8fa 2338
bd198058
AD		 2339 ixgbe_update_itr(q_vector, &q_vector->tx);
2340 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2341
08c8833b 2342 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2343
2344 switch (current_itr) {
2345 /* counts and packets in update_itr are dependent on these numbers */
2346 case lowest_latency:
d5bf4f67 2347 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2348 break;
2349 case low_latency:
d5bf4f67 2350 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2351 break;
2352 case bulk_latency:
8ac34f10 2353 new_itr = IXGBE_12K_ITR;
f494e8fa 2354 break;
bd198058
AD		 2355 default:
2356 break;
f494e8fa
AV		 2357 }
2358
d5bf4f67 2359 if (new_itr != q_vector->itr) {
fe49f04a 2360 /* do an exponential smoothing */
d5bf4f67
ET		 2361 new_itr = (10 * new_itr * q_vector->itr) /
2362 ((9 * new_itr) + q_vector->itr);
509ee935 2363
bd198058 2364 /* save the algorithm value here */
5d967eb7 2365 q_vector->itr = new_itr;
fe49f04a
AD		 2366
2367 ixgbe_write_eitr(q_vector);
f494e8fa 2368 }
f494e8fa
AV		 2369}
2370
119fc60a 2371/**
de88eeeb 2372 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2373 * @adapter: pointer to adapter
119fc60a 2374 **/
f0f9778d 2375static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2376{
119fc60a
MC		 2377 struct ixgbe_hw *hw = &adapter->hw;
2378 u32 eicr = adapter->interrupt_event;
2379
f0f9778d 2380 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2381 return;
2382
f0f9778d
AD		 2383 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2384 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2385 return;
2386
2387 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2388
7ca647bd 2389 switch (hw->device_id) {
f0f9778d
AD		 2390 case IXGBE_DEV_ID_82599_T3_LOM:
2391 /*
2392 * Since the warning interrupt is for both ports
2393 * we don't have to check if:
2394 * - This interrupt wasn't for our port.
2395 * - We may have missed the interrupt so always have to
2396 * check if we got a LSC
2397 */
9a900eca 2398 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2399 !(eicr & IXGBE_EICR_LSC))
2400 return;
2401
2402 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2403 u32 speed;
f0f9778d 2404 bool link_up = false;
7ca647bd 2405
3d292265 2406 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2407
f0f9778d
AD		 2408 if (link_up)
2409 return;
2410 }
2411
2412 /* Check if this is not due to overtemp */
2413 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2414 return;
2415
2416 break;
7ca647bd 2417 default:
597f22d6
DS		 2418 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2419 return;
9a900eca 2420 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2421 return;
7ca647bd 2422 break;
119fc60a 2423 }
f44e751b 2424 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2425
2426 adapter->interrupt_event = 0;
119fc60a
MC		 2427}
2428
0befdb3e
JB		 2429static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2430{
2431 struct ixgbe_hw *hw = &adapter->hw;
2432
2433 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2434 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2435 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2436 /* write to clear the interrupt */
9a900eca 2437 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2438 }
2439}
cf8280ee 2440
4f51bf70
JK		 2441static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2442{
9a900eca
DS		 2443 struct ixgbe_hw *hw = &adapter->hw;
2444
4f51bf70
JK		 2445 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2446 return;
2447
2448 switch (adapter->hw.mac.type) {
2449 case ixgbe_mac_82599EB:
2450 /*
2451 * Need to check link state so complete overtemp check
2452 * on service task
2453 */
9a900eca
DS		 2454 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2455 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2456 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2457 adapter->interrupt_event = eicr;
2458 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2459 ixgbe_service_event_schedule(adapter);
2460 return;
2461 }
2462 return;
2463 case ixgbe_mac_X540:
2464 if (!(eicr & IXGBE_EICR_TS))
2465 return;
2466 break;
2467 default:
2468 return;
2469 }
2470
f44e751b 2471 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2472}
2473
45788d2a
DS		 2474static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2475{
2476 switch (hw->mac.type) {
2477 case ixgbe_mac_82598EB:
2478 if (hw->phy.type == ixgbe_phy_nl)
2479 return true;
2480 return false;
2481 case ixgbe_mac_82599EB:
2482 case ixgbe_mac_X550EM_x:
2483 switch (hw->mac.ops.get_media_type(hw)) {
2484 case ixgbe_media_type_fiber:
2485 case ixgbe_media_type_fiber_qsfp:
2486 return true;
2487 default:
2488 return false;
2489 }
2490 default:
2491 return false;
2492 }
2493}
2494
e8e26350
PW		 2495static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2496{
2497 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2498 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2499
4ccc650c
DS		 2500 if (!ixgbe_is_sfp(hw))
2501 return;
2502
2503 /* Later MAC's use different SDP */
2504 if (hw->mac.type >= ixgbe_mac_X540)
2505 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2506
2507 if (eicr & eicr_mask) {
73c4b7cd 2508 /* Clear the interrupt */
4ccc650c 2509 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2510 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2511 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2512 adapter->sfp_poll_time = 0;
7086400d
AD		 2513 ixgbe_service_event_schedule(adapter);
2514 }
73c4b7cd
AD		 2515 }
2516
4ccc650c
DS		 2517 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2518 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2519 /* Clear the interrupt */
9a900eca 2520 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2521 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2522 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2523 ixgbe_service_event_schedule(adapter);
2524 }
e8e26350
PW		 2525 }
2526}
2527
cf8280ee
JB		 2528static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2529{
2530 struct ixgbe_hw *hw = &adapter->hw;
2531
2532 adapter->lsc_int++;
2533 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2534 adapter->link_check_timeout = jiffies;
2535 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2536 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2537 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2538 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2539 }
2540}
2541
fe49f04a
AD		 2542static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2543 u64 qmask)
2544{
2545 u32 mask;
bd508178 2546 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2547
bd508178
AD		 2548 switch (hw->mac.type) {
2549 case ixgbe_mac_82598EB:
fe49f04a 2550 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2551 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2552 break;
2553 case ixgbe_mac_82599EB:
b93a2226 2554 case ixgbe_mac_X540:
9a75a1ac
DS		 2555 case ixgbe_mac_X550:
2556 case ixgbe_mac_X550EM_x:
fe49f04a 2557 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2558 if (mask)
2559 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2560 mask = (qmask >> 32);
bd508178
AD		 2561 if (mask)
2562 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2563 break;
2564 default:
2565 break;
fe49f04a
AD		 2566 }
2567 /* skip the flush */
2568}
2569
2570static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2571 u64 qmask)
fe49f04a
AD		 2572{
2573 u32 mask;
bd508178 2574 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2575
bd508178
AD		 2576 switch (hw->mac.type) {
2577 case ixgbe_mac_82598EB:
fe49f04a 2578 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2579 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2580 break;
2581 case ixgbe_mac_82599EB:
b93a2226 2582 case ixgbe_mac_X540:
9a75a1ac
DS		 2583 case ixgbe_mac_X550:
2584 case ixgbe_mac_X550EM_x:
fe49f04a 2585 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2586 if (mask)
2587 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2588 mask = (qmask >> 32);
bd508178
AD		 2589 if (mask)
2590 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2591 break;
2592 default:
2593 break;
fe49f04a
AD		 2594 }
2595 /* skip the flush */
2596}
2597
021230d4 2598/**
2c4af694
AD		 2599 * ixgbe_irq_enable - Enable default interrupt generation settings
2600 * @adapter: board private structure
021230d4 2601 **/
2c4af694
AD		 2602static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2603 bool flush)
9a799d71 2604{
9a900eca 2605 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2606 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2607
2c4af694
AD		 2608 /* don't reenable LSC while waiting for link */
2609 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2610 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2611
2c4af694 2612 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2613 switch (adapter->hw.mac.type) {
2614 case ixgbe_mac_82599EB:
9a900eca 2615 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2616 break;
2617 case ixgbe_mac_X540:
9a75a1ac
DS		 2618 case ixgbe_mac_X550:
2619 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2620 mask |= IXGBE_EIMS_TS;
2621 break;
2622 default:
2623 break;
2624 }
2c4af694 2625 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2626 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2627 switch (adapter->hw.mac.type) {
2628 case ixgbe_mac_82599EB:
9a900eca
DS		 2629 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2630 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2631 /* fall through */
858bc081 2632 case ixgbe_mac_X540:
9a75a1ac
DS		 2633 case ixgbe_mac_X550:
2634 case ixgbe_mac_X550EM_x:
cbd45ec7
MR		 2635 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2636 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2637 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2638 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2639 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2640 mask |= IXGBE_EIMS_MAILBOX;
2641 break;
2642 default:
2643 break;
9a799d71 2644 }
db0677fa 2645
2c4af694
AD		 2646 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2647 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2648 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2649
2c4af694
AD		 2650 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2651 if (queues)
2652 ixgbe_irq_enable_queues(adapter, ~0);
2653 if (flush)
2654 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2655}
2656
2c4af694 2657static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2658{
a65151ba 2659 struct ixgbe_adapter *adapter = data;
9a799d71 2660 struct ixgbe_hw *hw = &adapter->hw;
54037505 2661 u32 eicr;
91281fd3 2662
54037505
DS		 2663 /*
2664 * Workaround for Silicon errata. Use clear-by-write instead
2665 * of clear-by-read. Reading with EICS will return the
2666 * interrupt causes without clearing, which later be done
2667 * with the write to EICR.
2668 */
2669 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2670
2671 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2672 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2673 * the bits are high when ixgbe_msix_other is called. There is a race
2674 * condition otherwise which results in possible performance loss
2675 * especially if the ixgbe_msix_other interrupt is triggering
2676 * consistently (as it would when PPS is turned on for the X540 device)
2677 */
2678 eicr &= 0xFFFF0000;
2679
54037505 2680 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2681
cf8280ee
JB		 2682 if (eicr & IXGBE_EICR_LSC)
2683 ixgbe_check_lsc(adapter);
f0848276 2684
1cdd1ec8
GR		 2685 if (eicr & IXGBE_EICR_MAILBOX)
2686 ixgbe_msg_task(adapter);
efe3d3c8 2687
bd508178
AD		 2688 switch (hw->mac.type) {
2689 case ixgbe_mac_82599EB:
b93a2226 2690 case ixgbe_mac_X540:
9a75a1ac
DS		 2691 case ixgbe_mac_X550:
2692 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2693 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2694 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2695 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2696 ixgbe_service_event_schedule(adapter);
2697 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2698 IXGBE_EICR_GPI_SDP0_X540);
2699 }
d773ce2d
DS		 2700 if (eicr & IXGBE_EICR_ECC) {
2701 e_info(link, "Received ECC Err, initiating reset\n");
2702 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2703 ixgbe_service_event_schedule(adapter);
2704 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2705 }
c4cf55e5
PWJ		 2706 /* Handle Flow Director Full threshold interrupt */
2707 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2708 int reinit_count = 0;
c4cf55e5 2709 int i;
c4cf55e5 2710 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2711 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2712 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2713 &ring->state))
2714 reinit_count++;
2715 }
2716 if (reinit_count) {
2717 /* no more flow director interrupts until after init */
2718 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2719 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2720 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2721 }
2722 }
f0f9778d 2723 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2724 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2725 break;
2726 default:
2727 break;
c4cf55e5 2728 }
f0848276 2729
bd508178 2730 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2731
db0677fa
JK		 2732 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2733 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2734
7086400d 2735 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2736 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2737 ixgbe_irq_enable(adapter, false, false);
f0848276 2738
9a799d71 2739 return IRQ_HANDLED;
f0848276 2740}
91281fd3 2741
4ff7fb12 2742static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2743{
021230d4 2744 struct ixgbe_q_vector *q_vector = data;
91281fd3 2745
9b471446 2746 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2747
4ff7fb12
AD		 2748 if (q_vector->rx.ring || q_vector->tx.ring)
2749 napi_schedule(&q_vector->napi);
91281fd3 2750
9a799d71 2751 return IRQ_HANDLED;
91281fd3
AD		 2752}
2753
eb01b975
AD		 2754/**
2755 * ixgbe_poll - NAPI Rx polling callback
2756 * @napi: structure for representing this polling device
2757 * @budget: how many packets driver is allowed to clean
2758 *
2759 * This function is used for legacy and MSI, NAPI mode
2760 **/
8af3c33f 2761int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2762{
2763 struct ixgbe_q_vector *q_vector =
2764 container_of(napi, struct ixgbe_q_vector, napi);
2765 struct ixgbe_adapter *adapter = q_vector->adapter;
2766 struct ixgbe_ring *ring;
2767 int per_ring_budget;
2768 bool clean_complete = true;
2769
2770#ifdef CONFIG_IXGBE_DCA
2771 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2772 ixgbe_update_dca(q_vector);
2773#endif
2774
2775 ixgbe_for_each_ring(ring, q_vector->tx)
2776 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2777
5a85e737
ET		 2778 if (!ixgbe_qv_lock_napi(q_vector))
2779 return budget;
2780
eb01b975
AD		 2781 /* attempt to distribute budget to each queue fairly, but don't allow
2782 * the budget to go below 1 because we'll exit polling */
2783 if (q_vector->rx.count > 1)
2784 per_ring_budget = max(budget/q_vector->rx.count, 1);
2785 else
2786 per_ring_budget = budget;
2787
2788 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2789 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2790 per_ring_budget) < per_ring_budget);
eb01b975 2791
5a85e737 2792 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2793 /* If all work not completed, return budget and keep polling */
2794 if (!clean_complete)
2795 return budget;
2796
2797 /* all work done, exit the polling mode */
2798 napi_complete(napi);
2799 if (adapter->rx_itr_setting & 1)
2800 ixgbe_set_itr(q_vector);
2801 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2802 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2803
2804 return 0;
2805}
2806
021230d4
AV		 2807/**
2808 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2809 * @adapter: board private structure
2810 *
2811 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2812 * interrupts from the kernel.
2813 **/
2814static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2815{
2816 struct net_device *netdev = adapter->netdev;
207867f5 2817 int vector, err;
e8e9f696 2818 int ri = 0, ti = 0;
021230d4 2819
49c7ffbe 2820 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2821 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2822 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2823
4ff7fb12 2824 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2825 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2826 "%s-%s-%d", netdev->name, "TxRx", ri++);
2827 ti++;
2828 } else if (q_vector->rx.ring) {
9fe93afd 2829 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2830 "%s-%s-%d", netdev->name, "rx", ri++);
2831 } else if (q_vector->tx.ring) {
9fe93afd 2832 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2833 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2834 } else {
2835 /* skip this unused q_vector */
2836 continue;
32aa77a4 2837 }
207867f5
AD		 2838 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2839 q_vector->name, q_vector);
9a799d71 2840 if (err) {
396e799c 2841 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2842 "Error: %d\n", err);
021230d4 2843 goto free_queue_irqs;
9a799d71 2844 }
207867f5
AD		 2845 /* If Flow Director is enabled, set interrupt affinity */
2846 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2847 /* assign the mask for this irq */
2848 irq_set_affinity_hint(entry->vector,
de88eeeb 2849 &q_vector->affinity_mask);
207867f5 2850 }
9a799d71
AK		 2851 }
2852
021230d4 2853 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2854 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2855 if (err) {
de88eeeb 2856 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2857 goto free_queue_irqs;
9a799d71
AK		 2858 }
2859
9a799d71
AK		 2860 return 0;
2861
021230d4 2862free_queue_irqs:
207867f5
AD		 2863 while (vector) {
2864 vector--;
2865 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2866 NULL);
2867 free_irq(adapter->msix_entries[vector].vector,
2868 adapter->q_vector[vector]);
2869 }
021230d4
AV		 2870 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2871 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2872 kfree(adapter->msix_entries);
2873 adapter->msix_entries = NULL;
9a799d71
AK		 2874 return err;
2875}
2876
2877/**
021230d4 2878 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2879 * @irq: interrupt number
2880 * @data: pointer to a network interface device structure
9a799d71
AK		 2881 **/
2882static irqreturn_t ixgbe_intr(int irq, void *data)
2883{
a65151ba 2884 struct ixgbe_adapter *adapter = data;
9a799d71 2885 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2886 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2887 u32 eicr;
2888
54037505 2889 /*
24ddd967 2890 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2891 * before the read of EICR.
2892 */
2893 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2894
021230d4 2895 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2896 * therefore no explicit interrupt disable is necessary */
021230d4 2897 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2898 if (!eicr) {
6af3b9eb
ET		 2899 /*
2900 * shared interrupt alert!
f47cf66e 2901 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2902 * have disabled interrupts due to EIAM
2903 * finish the workaround of silicon errata on 82598. Unmask
2904 * the interrupt that we masked before the EICR read.
2905 */
2906 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2907 ixgbe_irq_enable(adapter, true, true);
9a799d71 2908 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2909 }
9a799d71 2910
cf8280ee
JB		 2911 if (eicr & IXGBE_EICR_LSC)
2912 ixgbe_check_lsc(adapter);
021230d4 2913
bd508178
AD		 2914 switch (hw->mac.type) {
2915 case ixgbe_mac_82599EB:
e8e26350 2916 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2917 /* Fall through */
2918 case ixgbe_mac_X540:
9a75a1ac
DS		 2919 case ixgbe_mac_X550:
2920 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2921 if (eicr & IXGBE_EICR_ECC) {
2922 e_info(link, "Received ECC Err, initiating reset\n");
2923 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2924 ixgbe_service_event_schedule(adapter);
2925 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2926 }
4f51bf70 2927 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2928 break;
2929 default:
2930 break;
2931 }
e8e26350 2932
0befdb3e 2933 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2934 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2935 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2936
b9f6ed2b
AD		 2937 /* would disable interrupts here but EIAM disabled it */
2938 napi_schedule(&q_vector->napi);
9a799d71 2939
6af3b9eb
ET		 2940 /*
2941 * re-enable link(maybe) and non-queue interrupts, no flush.
2942 * ixgbe_poll will re-enable the queue interrupts
2943 */
6af3b9eb
ET		 2944 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2945 ixgbe_irq_enable(adapter, false, false);
2946
9a799d71
AK		 2947 return IRQ_HANDLED;
2948}
2949
2950/**
2951 * ixgbe_request_irq - initialize interrupts
2952 * @adapter: board private structure
2953 *
2954 * Attempts to configure interrupts using the best available
2955 * capabilities of the hardware and kernel.
2956 **/
021230d4 2957static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2958{
2959 struct net_device *netdev = adapter->netdev;
021230d4 2960 int err;
9a799d71 2961
4cc6df29 2962 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2963 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2964 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2965 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2966 netdev->name, adapter);
4cc6df29 2967 else
a0607fd3 2968 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2969 netdev->name, adapter);
9a799d71 2970
de88eeeb 2971 if (err)
396e799c 2972 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2973
9a799d71
AK		 2974 return err;
2975}
2976
2977static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2978{
49c7ffbe 2979 int vector;
9a799d71 2980
49c7ffbe
AD		 2981 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2982 free_irq(adapter->pdev->irq, adapter);
2983 return;
2984 }
4cc6df29 2985
49c7ffbe
AD		 2986 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2987 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2988 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2989
49c7ffbe
AD		 2990 /* free only the irqs that were actually requested */
2991 if (!q_vector->rx.ring && !q_vector->tx.ring)
2992 continue;
207867f5 2993
49c7ffbe
AD		 2994 /* clear the affinity_mask in the IRQ descriptor */
2995 irq_set_affinity_hint(entry->vector, NULL);
2996
2997 free_irq(entry->vector, q_vector);
9a799d71 2998 }
49c7ffbe
AD		 2999
3000 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3001}
3002
22d5a71b
JB		 3003/**
3004 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3005 * @adapter: board private structure
3006 **/
3007static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3008{
bd508178
AD		 3009 switch (adapter->hw.mac.type) {
3010 case ixgbe_mac_82598EB:
835462fc 3011 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3012 break;
3013 case ixgbe_mac_82599EB:
b93a2226 3014 case ixgbe_mac_X540:
9a75a1ac
DS		 3015 case ixgbe_mac_X550:
3016 case ixgbe_mac_X550EM_x:
835462fc
NS		 3017 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3018 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3020 break;
3021 default:
3022 break;
22d5a71b
JB		 3023 }
3024 IXGBE_WRITE_FLUSH(&adapter->hw);
3025 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3026 int vector;
3027
3028 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3029 synchronize_irq(adapter->msix_entries[vector].vector);
3030
3031 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3032 } else {
3033 synchronize_irq(adapter->pdev->irq);
3034 }
3035}
3036
9a799d71
AK		 3037/**
3038 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3039 *
3040 **/
3041static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3042{
d5bf4f67 3043 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3044
d5bf4f67 3045 ixgbe_write_eitr(q_vector);
9a799d71 3046
e8e26350
PW		 3047 ixgbe_set_ivar(adapter, 0, 0, 0);
3048 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3049
396e799c 3050 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3051}
3052
43e69bf0
AD		 3053/**
3054 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3055 * @adapter: board private structure
3056 * @ring: structure containing ring specific data
3057 *
3058 * Configure the Tx descriptor ring after a reset.
3059 **/
84418e3b
AD		 3060void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3061 struct ixgbe_ring *ring)
43e69bf0
AD		 3062{
3063 struct ixgbe_hw *hw = &adapter->hw;
3064 u64 tdba = ring->dma;
2f1860b8 3065 int wait_loop = 10;
b88c6de2 3066 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3067 u8 reg_idx = ring->reg_idx;
43e69bf0 3068
2f1860b8 3069 /* disable queue to avoid issues while updating state */
b88c6de2 3070 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3071 IXGBE_WRITE_FLUSH(hw);
3072
43e69bf0 3073 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3074 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3075 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3076 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3077 ring->count * sizeof(union ixgbe_adv_tx_desc));
3078 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3079 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3080 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3081
b88c6de2
AD		 3082 /*
3083 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3084 * higher than 1 when:
3085 * - ITR is 0 as it could cause false TX hangs
3086 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3087 *
3088 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3089 * to or less than the number of on chip descriptors, which is
3090 * currently 40.
3091 */
67da097e 3092 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3093 txdctl |= (1 << 16); /* WTHRESH = 1 */
3094 else
3095 txdctl |= (8 << 16); /* WTHRESH = 8 */
3096
e954b374
AD		 3097 /*
3098 * Setting PTHRESH to 32 both improves performance
3099 * and avoids a TX hang with DFP enabled
3100 */
b88c6de2
AD		 3101 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3102 32; /* PTHRESH = 32 */
2f1860b8
AD		 3103
3104 /* reinitialize flowdirector state */
39cb681b 3105 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3106 ring->atr_sample_rate = adapter->atr_sample_rate;
3107 ring->atr_count = 0;
3108 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3109 } else {
3110 ring->atr_sample_rate = 0;
3111 }
2f1860b8 3112
fd786b7b
AD		 3113 /* initialize XPS */
3114 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3115 struct ixgbe_q_vector *q_vector = ring->q_vector;
3116
3117 if (q_vector)
2a47fa45 3118 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3119 &q_vector->affinity_mask,
3120 ring->queue_index);
3121 }
3122
c84d324c
JF		 3123 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3124
2f1860b8 3125 /* enable queue */
2f1860b8
AD		 3126 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3127
3128 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3129 if (hw->mac.type == ixgbe_mac_82598EB &&
3130 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3131 return;
3132
3133 /* poll to verify queue is enabled */
3134 do {
032b4325 3135 usleep_range(1000, 2000);
2f1860b8
AD		 3136 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3137 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3138 if (!wait_loop)
3139 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3140}
3141
120ff942
AD		 3142static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3143{
3144 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3145 u32 rttdcs, mtqc;
8b1c0b24 3146 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3147
3148 if (hw->mac.type == ixgbe_mac_82598EB)
3149 return;
3150
3151 /* disable the arbiter while setting MTQC */
3152 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3153 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3154 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3155
3156 /* set transmit pool layout */
671c0adb
AD		 3157 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3158 mtqc = IXGBE_MTQC_VT_ENA;
3159 if (tcs > 4)
3160 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3161 else if (tcs > 1)
3162 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3163 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3164 mtqc |= IXGBE_MTQC_32VF;
3165 else
3166 mtqc |= IXGBE_MTQC_64VF;
3167 } else {
3168 if (tcs > 4)
3169 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3170 else if (tcs > 1)
3171 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3172 else
671c0adb
AD		 3173 mtqc = IXGBE_MTQC_64Q_1PB;
3174 }
120ff942 3175
671c0adb 3176 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3177
671c0adb
AD		 3178 /* Enable Security TX Buffer IFG for multiple pb */
3179 if (tcs) {
3180 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3181 sectx |= IXGBE_SECTX_DCB;
3182 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3183 }
3184
3185 /* re-enable the arbiter */
3186 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3187 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3188}
3189
9a799d71 3190/**
3a581073 3191 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3192 * @adapter: board private structure
3193 *
3194 * Configure the Tx unit of the MAC after a reset.
3195 **/
3196static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3197{
2f1860b8
AD		 3198 struct ixgbe_hw *hw = &adapter->hw;
3199 u32 dmatxctl;
43e69bf0 3200 u32 i;
9a799d71 3201
2f1860b8
AD		 3202 ixgbe_setup_mtqc(adapter);
3203
3204 if (hw->mac.type != ixgbe_mac_82598EB) {
3205 /* DMATXCTL.EN must be before Tx queues are enabled */
3206 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3207 dmatxctl |= IXGBE_DMATXCTL_TE;
3208 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3209 }
3210
9a799d71 3211 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3212 for (i = 0; i < adapter->num_tx_queues; i++)
3213 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3214}
3215
3ebe8fde
AD		 3216static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3217 struct ixgbe_ring *ring)
3218{
3219 struct ixgbe_hw *hw = &adapter->hw;
3220 u8 reg_idx = ring->reg_idx;
3221 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3222
3223 srrctl |= IXGBE_SRRCTL_DROP_EN;
3224
3225 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3226}
3227
3228static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3229 struct ixgbe_ring *ring)
3230{
3231 struct ixgbe_hw *hw = &adapter->hw;
3232 u8 reg_idx = ring->reg_idx;
3233 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3234
3235 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3236
3237 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3238}
3239
3240#ifdef CONFIG_IXGBE_DCB
3241void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3242#else
3243static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3244#endif
3245{
3246 int i;
3247 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3248
3249 if (adapter->ixgbe_ieee_pfc)
3250 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3251
3252 /*
3253 * We should set the drop enable bit if:
3254 * SR-IOV is enabled
3255 * or
3256 * Number of Rx queues > 1 and flow control is disabled
3257 *
3258 * This allows us to avoid head of line blocking for security
3259 * and performance reasons.
3260 */
3261 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3262 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3263 for (i = 0; i < adapter->num_rx_queues; i++)
3264 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3265 } else {
3266 for (i = 0; i < adapter->num_rx_queues; i++)
3267 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3268 }
3269}
3270
e8e26350 3271#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3272
a6616b42 3273static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3274 struct ixgbe_ring *rx_ring)
cc41ac7c 3275{
45e9baa5 3276 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3277 u32 srrctl;
bf29ee6c 3278 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3279
45e9baa5
AD		 3280 if (hw->mac.type == ixgbe_mac_82598EB) {
3281 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3282
45e9baa5
AD		 3283 /*
3284 * if VMDq is not active we must program one srrctl register
3285 * per RSS queue since we have enabled RDRXCTL.MVMEN
3286 */
3287 reg_idx &= mask;
3288 }
cc41ac7c 3289
45e9baa5
AD		 3290 /* configure header buffer length, needed for RSC */
3291 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3292
45e9baa5 3293 /* configure the packet buffer length */
f800326d 3294 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3295
3296 /* configure descriptor type */
f800326d 3297 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3298
45e9baa5 3299 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3300}
9a799d71 3301
dfaf891d
VZ		 3302/**
3303 * Return a number of entries in the RSS indirection table
3304 *
3305 * @adapter: device handle
3306 *
3307 * - 82598/82599/X540: 128
3308 * - X550(non-SRIOV mode): 512
3309 * - X550(SRIOV mode): 64
3310 */
7f276efb 3311u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3312{
3313 if (adapter->hw.mac.type < ixgbe_mac_X550)
3314 return 128;
3315 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3316 return 64;
3317 else
3318 return 512;
3319}
3320
3321/**
3322 * Write the RETA table to HW
3323 *
3324 * @adapter: device handle
3325 *
3326 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3327 */
1c7cf078 3328void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3329{
dfaf891d 3330 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3331 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3332 u32 reta = 0;
dfaf891d
VZ		 3333 u32 indices_multi;
3334 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3335
0f9b232b 3336 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3337 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3338 * indices.
3339 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3340 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3341 */
3342 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3343 indices_multi = 0x11;
3344 else
3345 indices_multi = 0x1;
3346
dfaf891d
VZ		 3347 /* Write redirection table to HW */
3348 for (i = 0; i < reta_entries; i++) {
3349 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3350 if ((i & 3) == 3) {
3351 if (i < 128)
3352 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3353 else
3354 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3355 reta);
dfaf891d 3356 reta = 0;
0f9b232b
DS		 3357 }
3358 }
3359}
3360
dfaf891d
VZ		 3361/**
3362 * Write the RETA table to HW (for x550 devices in SRIOV mode)
3363 *
3364 * @adapter: device handle
3365 *
3366 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3367 */
3368static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3369{
dfaf891d 3370 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3371 struct ixgbe_hw *hw = &adapter->hw;
3372 u32 vfreta = 0;
dfaf891d
VZ		 3373 unsigned int pf_pool = adapter->num_vfs;
3374
3375 /* Write redirection table to HW */
3376 for (i = 0; i < reta_entries; i++) {
3377 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3378 if ((i & 3) == 3) {
3379 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3380 vfreta);
3381 vfreta = 0;
3382 }
3383 }
3384}
3385
3386static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3387{
3388 struct ixgbe_hw *hw = &adapter->hw;
3389 u32 i, j;
3390 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3391 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3392
3393 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3394 * make full use of any rings they may have. We will use the
3395 * PSRTYPE register to control how many rings we use within the PF.
3396 */
3397 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3398 rss_i = 2;
3399
3400 /* Fill out hash function seeds */
3401 for (i = 0; i < 10; i++)
3402 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3403
3404 /* Fill out redirection table */
3405 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3406
3407 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3408 if (j == rss_i)
3409 j = 0;
3410
3411 adapter->rss_indir_tbl[i] = j;
3412 }
3413
3414 ixgbe_store_reta(adapter);
3415}
3416
3417static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3418{
3419 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3420 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3421 unsigned int pf_pool = adapter->num_vfs;
3422 int i, j;
3423
3424 /* Fill out hash function seeds */
3425 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3426 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3427 adapter->rss_key[i]);
0f9b232b
DS		 3428
3429 /* Fill out the redirection table */
3430 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3431 if (j == rss_i)
05abb126 3432 j = 0;
dfaf891d
VZ		 3433
3434 adapter->rss_indir_tbl[i] = j;
05abb126 3435 }
dfaf891d
VZ		 3436
3437 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3438}
3439
3440static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3441{
3442 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3443 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3444 u32 rxcsum;
0cefafad 3445
05abb126
AD		 3446 /* Disable indicating checksum in descriptor, enables RSS hash */
3447 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3448 rxcsum |= IXGBE_RXCSUM_PCSD;
3449 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3450
671c0adb 3451 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3452 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3453 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3454 } else {
671c0adb
AD		 3455 u8 tcs = netdev_get_num_tc(adapter->netdev);
3456
3457 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3458 if (tcs > 4)
3459 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3460 else if (tcs > 1)
3461 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3462 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3463 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3464 else
671c0adb
AD		 3465 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3466 } else {
3467 if (tcs > 4)
8b1c0b24 3468 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3469 else if (tcs > 1)
3470 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3471 else
3472 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3473 }
0cefafad
JB		 3474 }
3475
05abb126 3476 /* Perform hash on these packet types */
d1b849b9
DS		 3477 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3478 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3479 IXGBE_MRQC_RSS_FIELD_IPV6 |
3480 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3481
ef6afc0c 3482 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3483 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3484 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3485 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3486
dfaf891d 3487 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3488 if ((hw->mac.type >= ixgbe_mac_X550) &&
3489 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3490 unsigned int pf_pool = adapter->num_vfs;
3491
3492 /* Enable VF RSS mode */
3493 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3494 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3495
3496 /* Setup RSS through the VF registers */
dfaf891d 3497 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3498 vfmrqc = IXGBE_MRQC_RSSEN;
3499 vfmrqc |= rss_field;
3500 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3501 } else {
dfaf891d 3502 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3503 mrqc |= rss_field;
3504 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3505 }
0cefafad
JB		 3506}
3507
bb5a9ad2
NS		 3508/**
3509 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3510 * @adapter: address of board private structure
3511 * @index: index of ring to set
bb5a9ad2 3512 **/
082757af 3513static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3514 struct ixgbe_ring *ring)
bb5a9ad2 3515{
bb5a9ad2 3516 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3517 u32 rscctrl;
bf29ee6c 3518 u8 reg_idx = ring->reg_idx;
7367096a 3519
7d637bcc 3520 if (!ring_is_rsc_enabled(ring))
7367096a 3521 return;
bb5a9ad2 3522
7367096a 3523 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3524 rscctrl |= IXGBE_RSCCTL_RSCEN;
3525 /*
3526 * we must limit the number of descriptors so that the
3527 * total size of max desc * buf_len is not greater
642c680e 3528 * than 65536
bb5a9ad2 3529 */
f800326d 3530 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3531 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3532}
3533
9e10e045
AD		 3534#define IXGBE_MAX_RX_DESC_POLL 10
3535static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3536 struct ixgbe_ring *ring)
3537{
3538 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3539 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3540 u32 rxdctl;
bf29ee6c 3541 u8 reg_idx = ring->reg_idx;
9e10e045 3542
b0483c8f
MR		 3543 if (ixgbe_removed(hw->hw_addr))
3544 return;
9e10e045
AD		 3545 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3546 if (hw->mac.type == ixgbe_mac_82598EB &&
3547 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3548 return;
3549
3550 do {
032b4325 3551 usleep_range(1000, 2000);
9e10e045
AD		 3552 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3553 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3554
3555 if (!wait_loop) {
3556 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3557 "the polling period\n", reg_idx);
3558 }
3559}
3560
2d39d576
YZ		 3561void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3562 struct ixgbe_ring *ring)
3563{
3564 struct ixgbe_hw *hw = &adapter->hw;
3565 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3566 u32 rxdctl;
3567 u8 reg_idx = ring->reg_idx;
3568
b0483c8f
MR		 3569 if (ixgbe_removed(hw->hw_addr))
3570 return;
2d39d576
YZ		 3571 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3572 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3573
3574 /* write value back with RXDCTL.ENABLE bit cleared */
3575 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3576
3577 if (hw->mac.type == ixgbe_mac_82598EB &&
3578 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3579 return;
3580
3581 /* the hardware may take up to 100us to really disable the rx queue */
3582 do {
3583 udelay(10);
3584 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3585 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3586
3587 if (!wait_loop) {
3588 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3589 "the polling period\n", reg_idx);
3590 }
3591}
3592
84418e3b
AD		 3593void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3594 struct ixgbe_ring *ring)
acd37177
AD		 3595{
3596 struct ixgbe_hw *hw = &adapter->hw;
3597 u64 rdba = ring->dma;
9e10e045 3598 u32 rxdctl;
bf29ee6c 3599 u8 reg_idx = ring->reg_idx;
acd37177 3600
9e10e045
AD		 3601 /* disable queue to avoid issues while updating state */
3602 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3603 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3604
acd37177
AD		 3605 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3606 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3607 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3608 ring->count * sizeof(union ixgbe_adv_rx_desc));
3609 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3610 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3611 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3612
3613 ixgbe_configure_srrctl(adapter, ring);
3614 ixgbe_configure_rscctl(adapter, ring);
3615
3616 if (hw->mac.type == ixgbe_mac_82598EB) {
3617 /*
3618 * enable cache line friendly hardware writes:
3619 * PTHRESH=32 descriptors (half the internal cache),
3620 * this also removes ugly rx_no_buffer_count increment
3621 * HTHRESH=4 descriptors (to minimize latency on fetch)
3622 * WTHRESH=8 burst writeback up to two cache lines
3623 */
3624 rxdctl &= ~0x3FFFFF;
3625 rxdctl |= 0x080420;
3626 }
3627
3628 /* enable receive descriptor ring */
3629 rxdctl |= IXGBE_RXDCTL_ENABLE;
3630 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3631
3632 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3633 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3634}
3635
48654521
AD		 3636static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3637{
3638 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3639 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3640 u16 pool;
48654521
AD		 3641
3642 /* PSRTYPE must be initialized in non 82598 adapters */
3643 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3644 IXGBE_PSRTYPE_UDPHDR |
3645 IXGBE_PSRTYPE_IPV4HDR |
48654521 3646 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3647 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3648
3649 if (hw->mac.type == ixgbe_mac_82598EB)
3650 return;
3651
fbe7ca7f
AD		 3652 if (rss_i > 3)
3653 psrtype |= 2 << 29;
3654 else if (rss_i > 1)
3655 psrtype |= 1 << 29;
48654521 3656
2a47fa45
JF		 3657 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3658 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3659}
3660
f5b4a52e
AD		 3661static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3662{
3663 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3664 u32 reg_offset, vf_shift;
435b19f6 3665 u32 gcr_ext, vmdctl;
de4c7f65 3666 int i;
f5b4a52e
AD		 3667
3668 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3669 return;
3670
3671 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3672 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3673 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3674 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3675 vmdctl |= IXGBE_VT_CTL_REPLEN;
3676 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3677
1d9c0bfd
AD		 3678 vf_shift = VMDQ_P(0) % 32;
3679 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3680
3681 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3682 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3683 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3684 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3685 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3686 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3687 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3688
3689 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3690 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3691
3692 /*
3693 * Set up VF register offsets for selected VT Mode,
3694 * i.e. 32 or 64 VFs for SR-IOV
3695 */
73079ea0
AD		 3696 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3697 case IXGBE_82599_VMDQ_8Q_MASK:
3698 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3699 break;
3700 case IXGBE_82599_VMDQ_4Q_MASK:
3701 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3702 break;
3703 default:
3704 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3705 break;
3706 }
3707
f5b4a52e
AD		 3708 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3709
435b19f6 3710
a985b6c3 3711 /* Enable MAC Anti-Spoofing */
435b19f6 3712 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3713 adapter->num_vfs);
5b7f000f
DS		 3714
3715 /* Ensure LLDP is set for Ethertype Antispoofing if we will be
3716 * calling set_ethertype_anti_spoofing for each VF in loop below
3717 */
3718 if (hw->mac.ops.set_ethertype_anti_spoofing)
3719 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3720 (IXGBE_ETQF_FILTER_EN | /* enable filter */
3721 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */
3722 IXGBE_ETH_P_LLDP)); /* LLDP eth type */
3723
de4c7f65
GR		 3724 /* For VFs that have spoof checking turned off */
3725 for (i = 0; i < adapter->num_vfs; i++) {
3726 if (!adapter->vfinfo[i].spoofchk_enabled)
3727 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3728
3729 /* enable ethertype anti spoofing if hw supports it */
3730 if (hw->mac.ops.set_ethertype_anti_spoofing)
3731 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3732
3733 /* Enable/Disable RSS query feature */
3734 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3735 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3736 }
f5b4a52e
AD		 3737}
3738
477de6ed 3739static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3740{
9a799d71
AK		 3741 struct ixgbe_hw *hw = &adapter->hw;
3742 struct net_device *netdev = adapter->netdev;
3743 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3744 struct ixgbe_ring *rx_ring;
3745 int i;
3746 u32 mhadd, hlreg0;
48654521 3747
63f39bd1 3748#ifdef IXGBE_FCOE
477de6ed
AD		 3749 /* adjust max frame to be able to do baby jumbo for FCoE */
3750 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3751 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3752 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3753
477de6ed 3754#endif /* IXGBE_FCOE */
872844dd
AD		 3755
3756 /* adjust max frame to be at least the size of a standard frame */
3757 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3758 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3759
477de6ed
AD		 3760 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3761 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3762 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3763 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3764
3765 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3766 }
3767
3768 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3769 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3770 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3771 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3772
0cefafad
JB		 3773 /*
3774 * Setup the HW Rx Head and Tail Descriptor Pointers and
3775 * the Base and Length of the Rx Descriptor Ring
3776 */
9a799d71 3777 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3778 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3779 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3780 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3781 else
7d637bcc 3782 clear_ring_rsc_enabled(rx_ring);
477de6ed 3783 }
477de6ed
AD		 3784}
3785
7367096a
AD		 3786static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3787{
3788 struct ixgbe_hw *hw = &adapter->hw;
3789 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3790
3791 switch (hw->mac.type) {
3792 case ixgbe_mac_82598EB:
3793 /*
3794 * For VMDq support of different descriptor types or
3795 * buffer sizes through the use of multiple SRRCTL
3796 * registers, RDRXCTL.MVMEN must be set to 1
3797 *
3798 * also, the manual doesn't mention it clearly but DCA hints
3799 * will only use queue 0's tags unless this bit is set. Side
3800 * effects of setting this bit are only that SRRCTL must be
3801 * fully programmed [0..15]
3802 */
3803 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3804 break;
052a1a72
MR		 3805 case ixgbe_mac_X550:
3806 case ixgbe_mac_X550EM_x:
f961ddae
MR		 3807 if (adapter->num_vfs)
3808 rdrxctl |= IXGBE_RDRXCTL_PSP;
3809 /* fall through for older HW */
7367096a 3810 case ixgbe_mac_82599EB:
b93a2226 3811 case ixgbe_mac_X540:
7367096a
AD		 3812 /* Disable RSC for ACK packets */
3813 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3814 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3815 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3816 /* hardware requires some bits to be set by default */
3817 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3818 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3819 break;
3820 default:
3821 /* We should do nothing since we don't know this hardware */
3822 return;
3823 }
3824
3825 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3826}
3827
477de6ed
AD		 3828/**
3829 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3830 * @adapter: board private structure
3831 *
3832 * Configure the Rx unit of the MAC after a reset.
3833 **/
3834static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3835{
3836 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3837 int i;
6dcc28b9 3838 u32 rxctrl, rfctl;
477de6ed
AD		 3839
3840 /* disable receives while setting up the descriptors */
1f9ac57c 3841 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3842
3843 ixgbe_setup_psrtype(adapter);
7367096a 3844 ixgbe_setup_rdrxctl(adapter);
477de6ed 3845
6dcc28b9
JK		 3846 /* RSC Setup */
3847 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3848 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3849 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3850 rfctl |= IXGBE_RFCTL_RSC_DIS;
3851 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3852
9e10e045 3853 /* Program registers for the distribution of queues */
f5b4a52e 3854 ixgbe_setup_mrqc(adapter);
f5b4a52e 3855
477de6ed
AD		 3856 /* set_rx_buffer_len must be called before ring initialization */
3857 ixgbe_set_rx_buffer_len(adapter);
3858
3859 /*
3860 * Setup the HW Rx Head and Tail Descriptor Pointers and
3861 * the Base and Length of the Rx Descriptor Ring
3862 */
9e10e045
AD		 3863 for (i = 0; i < adapter->num_rx_queues; i++)
3864 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3865
1f9ac57c 3866 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3867 /* disable drop enable for 82598 parts */
3868 if (hw->mac.type == ixgbe_mac_82598EB)
3869 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3870
3871 /* enable all receives */
3872 rxctrl |= IXGBE_RXCTRL_RXEN;
3873 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3874}
3875
80d5c368
PM		 3876static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3877 __be16 proto, u16 vid)
068c89b0
DS		 3878{
3879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3880 struct ixgbe_hw *hw = &adapter->hw;
3881
3882 /* add VID to filter table */
1d9c0bfd 3883 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3884 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3885
3886 return 0;
068c89b0
DS		 3887}
3888
80d5c368
PM		 3889static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3890 __be16 proto, u16 vid)
068c89b0
DS		 3891{
3892 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3893 struct ixgbe_hw *hw = &adapter->hw;
3894
068c89b0 3895 /* remove VID from filter table */
1d9c0bfd 3896 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3897 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3898
3899 return 0;
068c89b0
DS		 3900}
3901
f62bbb5e
JG		 3902/**
3903 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3904 * @adapter: driver data
3905 */
3906static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3907{
3908 struct ixgbe_hw *hw = &adapter->hw;
3909 u32 vlnctrl;
5f6c0181
JB		 3910 int i, j;
3911
3912 switch (hw->mac.type) {
3913 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3914 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3915 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3916 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3917 break;
3918 case ixgbe_mac_82599EB:
b93a2226 3919 case ixgbe_mac_X540:
9a75a1ac
DS		 3920 case ixgbe_mac_X550:
3921 case ixgbe_mac_X550EM_x:
5f6c0181 3922 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3923 struct ixgbe_ring *ring = adapter->rx_ring[i];
3924
3925 if (ring->l2_accel_priv)
3926 continue;
3927 j = ring->reg_idx;
5f6c0181
JB		 3928 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3929 vlnctrl &= ~IXGBE_RXDCTL_VME;
3930 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3931 }
3932 break;
3933 default:
3934 break;
3935 }
3936}
3937
3938/**
f62bbb5e 3939 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3940 * @adapter: driver data
3941 */
f62bbb5e 3942static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3943{
3944 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3945 u32 vlnctrl;
5f6c0181
JB		 3946 int i, j;
3947
3948 switch (hw->mac.type) {
3949 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3950 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3951 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3952 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3953 break;
3954 case ixgbe_mac_82599EB:
b93a2226 3955 case ixgbe_mac_X540:
9a75a1ac
DS		 3956 case ixgbe_mac_X550:
3957 case ixgbe_mac_X550EM_x:
5f6c0181 3958 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3959 struct ixgbe_ring *ring = adapter->rx_ring[i];
3960
3961 if (ring->l2_accel_priv)
3962 continue;
3963 j = ring->reg_idx;
5f6c0181
JB		 3964 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3965 vlnctrl |= IXGBE_RXDCTL_VME;
3966 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3967 }
3968 break;
3969 default:
3970 break;
3971 }
3972}
3973
9a799d71
AK		 3974static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3975{
f62bbb5e 3976 u16 vid;
9a799d71 3977
80d5c368 3978 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3979
3980 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3981 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3982}
3983
b335e75b
JK		 3984/**
3985 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3986 * @netdev: network interface device structure
3987 *
3988 * Writes multicast address list to the MTA hash table.
3989 * Returns: -ENOMEM on failure
3990 * 0 on no addresses written
3991 * X on writing X addresses to MTA
3992 **/
3993static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3994{
3995 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3996 struct ixgbe_hw *hw = &adapter->hw;
3997
3998 if (!netif_running(netdev))
3999 return 0;
4000
4001 if (hw->mac.ops.update_mc_addr_list)
4002 hw->mac.ops.update_mc_addr_list(hw, netdev);
4003 else
4004 return -ENOMEM;
4005
4006#ifdef CONFIG_PCI_IOV
5d7daa35 4007 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4008#endif
4009
4010 return netdev_mc_count(netdev);
4011}
4012
5d7daa35
JK		 4013#ifdef CONFIG_PCI_IOV
4014void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4015{
4016 struct ixgbe_hw *hw = &adapter->hw;
4017 int i;
4018 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4019 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4020 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
4021 adapter->mac_table[i].queue,
4022 IXGBE_RAH_AV);
4023 else
4024 hw->mac.ops.clear_rar(hw, i);
4025
4026 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
4027 }
4028}
4029#endif
4030
4031static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4032{
4033 struct ixgbe_hw *hw = &adapter->hw;
4034 int i;
4035 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4036 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
4037 if (adapter->mac_table[i].state &
4038 IXGBE_MAC_STATE_IN_USE)
4039 hw->mac.ops.set_rar(hw, i,
4040 adapter->mac_table[i].addr,
4041 adapter->mac_table[i].queue,
4042 IXGBE_RAH_AV);
4043 else
4044 hw->mac.ops.clear_rar(hw, i);
4045
4046 adapter->mac_table[i].state &=
4047 ~(IXGBE_MAC_STATE_MODIFIED);
4048 }
4049 }
4050}
4051
4052static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4053{
4054 int i;
4055 struct ixgbe_hw *hw = &adapter->hw;
4056
4057 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4058 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4059 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4060 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4061 adapter->mac_table[i].queue = 0;
4062 }
4063 ixgbe_sync_mac_table(adapter);
4064}
4065
4066static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
4067{
4068 struct ixgbe_hw *hw = &adapter->hw;
4069 int i, count = 0;
4070
4071 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4072 if (adapter->mac_table[i].state == 0)
4073 count++;
4074 }
4075 return count;
4076}
4077
4078/* this function destroys the first RAR entry */
4079static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4080 u8 *addr)
4081{
4082 struct ixgbe_hw *hw = &adapter->hw;
4083
4084 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4085 adapter->mac_table[0].queue = VMDQ_P(0);
4086 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4087 IXGBE_MAC_STATE_IN_USE);
4088 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4089 adapter->mac_table[0].queue,
4090 IXGBE_RAH_AV);
4091}
4092
4093int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4094{
4095 struct ixgbe_hw *hw = &adapter->hw;
4096 int i;
4097
4098 if (is_zero_ether_addr(addr))
4099 return -EINVAL;
4100
4101 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4102 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4103 continue;
4104 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4105 IXGBE_MAC_STATE_IN_USE);
4106 ether_addr_copy(adapter->mac_table[i].addr, addr);
4107 adapter->mac_table[i].queue = queue;
4108 ixgbe_sync_mac_table(adapter);
4109 return i;
4110 }
4111 return -ENOMEM;
4112}
4113
4114int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4115{
4116 /* search table for addr, if found, set to 0 and sync */
4117 int i;
4118 struct ixgbe_hw *hw = &adapter->hw;
4119
4120 if (is_zero_ether_addr(addr))
4121 return -EINVAL;
4122
4123 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4124 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4125 adapter->mac_table[i].queue == queue) {
4126 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4127 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4128 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4129 adapter->mac_table[i].queue = 0;
4130 ixgbe_sync_mac_table(adapter);
4131 return 0;
4132 }
4133 }
4134 return -ENOMEM;
4135}
2850062a
AD		 4136/**
4137 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4138 * @netdev: network interface device structure
4139 *
4140 * Writes unicast address list to the RAR table.
4141 * Returns: -ENOMEM on failure/insufficient address space
4142 * 0 on no addresses written
4143 * X on writing X addresses to the RAR table
4144 **/
5d7daa35 4145static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4146{
4147 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4148 int count = 0;
4149
4150 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4151 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4152 return -ENOMEM;
4153
95447461 4154 if (!netdev_uc_empty(netdev)) {
2850062a 4155 struct netdev_hw_addr *ha;
2850062a 4156 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4157 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4158 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4159 count++;
4160 }
4161 }
2850062a
AD		 4162 return count;
4163}
4164
9a799d71 4165/**
2c5645cf 4166 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4167 * @netdev: network interface device structure
4168 *
2c5645cf
CL		 4169 * The set_rx_method entry point is called whenever the unicast/multicast
4170 * address list or the network interface flags are updated. This routine is
4171 * responsible for configuring the hardware for proper unicast, multicast and
4172 * promiscuous mode.
9a799d71 4173 **/
7f870475 4174void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4175{
4176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4177 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4178 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4179 u32 vlnctrl;
2850062a 4180 int count;
9a799d71
AK		 4181
4182 /* Check for Promiscuous and All Multicast modes */
9a799d71 4183 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4184 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4185
f5dc442b 4186 /* set all bits that we expect to always be set */
3f2d1c0f 4187 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4188 fctrl |= IXGBE_FCTRL_BAM;
4189 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4190 fctrl |= IXGBE_FCTRL_PMCF;
4191
2850062a
AD		 4192 /* clear the bits we are changing the status of */
4193 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4194 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4195 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4196 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4197 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4198 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4199 /* Only disable hardware filter vlans in promiscuous mode
4200 * if SR-IOV and VMDQ are disabled - otherwise ensure
4201 * that hardware VLAN filters remain enabled.
4202 */
4556dc59
VY		 4203 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4204 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 4205 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4206 } else {
746b9f02
PM		 4207 if (netdev->flags & IFF_ALLMULTI) {
4208 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4209 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4210 }
a9b8943e 4211 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4212 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4213 }
4214
4215 /*
4216 * Write addresses to available RAR registers, if there is not
4217 * sufficient space to store all the addresses then enable
4218 * unicast promiscuous mode
4219 */
5d7daa35 4220 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4221 if (count < 0) {
4222 fctrl |= IXGBE_FCTRL_UPE;
4223 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4224 }
4225
cf78959c
ET		 4226 /* Write addresses to the MTA, if the attempt fails
4227 * then we should just turn on promiscuous mode so
4228 * that we can at least receive multicast traffic
4229 */
b335e75b
JK		 4230 count = ixgbe_write_mc_addr_list(netdev);
4231 if (count < 0) {
4232 fctrl |= IXGBE_FCTRL_MPE;
4233 vmolr |= IXGBE_VMOLR_MPE;
4234 } else if (count) {
4235 vmolr |= IXGBE_VMOLR_ROMPE;
4236 }
1d9c0bfd
AD		 4237
4238 if (hw->mac.type != ixgbe_mac_82598EB) {
4239 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4240 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4241 IXGBE_VMOLR_ROPE);
1d9c0bfd 4242 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4243 }
4244
3f2d1c0f
BG		 4245 /* This is useful for sniffing bad packets. */
4246 if (adapter->netdev->features & NETIF_F_RXALL) {
4247 /* UPE and MPE will be handled by normal PROMISC logic
4248 * in e1000e_set_rx_mode */
4249 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4250 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4251 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4252
4253 fctrl &= ~(IXGBE_FCTRL_DPF);
4254 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4255 }
4256
a9b8943e 4257 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4258 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4259
f646968f 4260 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4261 ixgbe_vlan_strip_enable(adapter);
4262 else
4263 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4264}
4265
021230d4
AV		 4266static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4267{
4268 int q_idx;
021230d4 4269
5a85e737
ET		 4270 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4271 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4272 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4273 }
021230d4
AV		 4274}
4275
4276static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4277{
4278 int q_idx;
021230d4 4279
5a85e737 4280 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4281 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4282 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4283 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4284 usleep_range(1000, 20000);
5a85e737
ET		 4285 }
4286 }
021230d4
AV		 4287}
4288
67359c3c
MR		 4289static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4290{
4291 switch (adapter->hw.mac.type) {
4292 case ixgbe_mac_X550:
4293 case ixgbe_mac_X550EM_x:
4294 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4295#ifdef CONFIG_IXGBE_VXLAN
4296 adapter->vxlan_port = 0;
4297#endif
4298 break;
4299 default:
4300 break;
4301 }
4302}
4303
7a6b6f51 4304#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4305/**
2f90b865
AD		 4306 * ixgbe_configure_dcb - Configure DCB hardware
4307 * @adapter: ixgbe adapter struct
4308 *
4309 * This is called by the driver on open to configure the DCB hardware.
4310 * This is also called by the gennetlink interface when reconfiguring
4311 * the DCB state.
4312 */
4313static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4314{
4315 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4316 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4317
67ebd791
AD		 4318 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4319 if (hw->mac.type == ixgbe_mac_82598EB)
4320 netif_set_gso_max_size(adapter->netdev, 65536);
4321 return;
4322 }
4323
4324 if (hw->mac.type == ixgbe_mac_82598EB)
4325 netif_set_gso_max_size(adapter->netdev, 32768);
4326
971060b1 4327#ifdef IXGBE_FCOE
b120818e
JF		 4328 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4329 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4330#endif
b120818e
JF		 4331
4332 /* reconfigure the hardware */
4333 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4334 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4335 DCB_TX_CONFIG);
4336 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4337 DCB_RX_CONFIG);
4338 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4339 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4340 ixgbe_dcb_hw_ets(&adapter->hw,
4341 adapter->ixgbe_ieee_ets,
4342 max_frame);
4343 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4344 adapter->ixgbe_ieee_pfc->pfc_en,
4345 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4346 }
8187cd48
JF		 4347
4348 /* Enable RSS Hash per TC */
4349 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4350 u32 msb = 0;
4351 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4352
d411a936
AD		 4353 while (rss_i) {
4354 msb++;
4355 rss_i >>= 1;
4356 }
8187cd48 4357
4ae63730
AD		 4358 /* write msb to all 8 TCs in one write */
4359 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4360 }
2f90b865 4361}
9da712d2
JF		 4362#endif
4363
4364/* Additional bittime to account for IXGBE framing */
4365#define IXGBE_ETH_FRAMING 20
4366
49ce9c2c 4367/**
9da712d2
JF		 4368 * ixgbe_hpbthresh - calculate high water mark for flow control
4369 *
4370 * @adapter: board private structure to calculate for
49ce9c2c 4371 * @pb: packet buffer to calculate
9da712d2
JF		 4372 */
4373static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4374{
4375 struct ixgbe_hw *hw = &adapter->hw;
4376 struct net_device *dev = adapter->netdev;
4377 int link, tc, kb, marker;
4378 u32 dv_id, rx_pba;
4379
4380 /* Calculate max LAN frame size */
4381 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4382
4383#ifdef IXGBE_FCOE
4384 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4385 if ((dev->features & NETIF_F_FCOE_MTU) &&
4386 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4387 (pb == ixgbe_fcoe_get_tc(adapter)))
4388 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4389#endif
e5776620 4390
9da712d2
JF		 4391 /* Calculate delay value for device */
4392 switch (hw->mac.type) {
4393 case ixgbe_mac_X540:
9a75a1ac
DS		 4394 case ixgbe_mac_X550:
4395 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4396 dv_id = IXGBE_DV_X540(link, tc);
4397 break;
4398 default:
4399 dv_id = IXGBE_DV(link, tc);
4400 break;
4401 }
4402
4403 /* Loopback switch introduces additional latency */
4404 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4405 dv_id += IXGBE_B2BT(tc);
4406
4407 /* Delay value is calculated in bit times convert to KB */
4408 kb = IXGBE_BT2KB(dv_id);
4409 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4410
4411 marker = rx_pba - kb;
4412
4413 /* It is possible that the packet buffer is not large enough
4414 * to provide required headroom. In this case throw an error
4415 * to user and a do the best we can.
4416 */
4417 if (marker < 0) {
4418 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4419 "headroom to support flow control."
4420 "Decrease MTU or number of traffic classes\n", pb);
4421 marker = tc + 1;
4422 }
4423
4424 return marker;
4425}
4426
49ce9c2c 4427/**
9da712d2
JF		 4428 * ixgbe_lpbthresh - calculate low water mark for for flow control
4429 *
4430 * @adapter: board private structure to calculate for
49ce9c2c 4431 * @pb: packet buffer to calculate
9da712d2 4432 */
e5776620 4433static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4434{
4435 struct ixgbe_hw *hw = &adapter->hw;
4436 struct net_device *dev = adapter->netdev;
4437 int tc;
4438 u32 dv_id;
4439
4440 /* Calculate max LAN frame size */
4441 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4442
e5776620
JK		 4443#ifdef IXGBE_FCOE
4444 /* FCoE traffic class uses FCOE jumbo frames */
4445 if ((dev->features & NETIF_F_FCOE_MTU) &&
4446 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4447 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4448 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4449#endif
4450
9da712d2
JF		 4451 /* Calculate delay value for device */
4452 switch (hw->mac.type) {
4453 case ixgbe_mac_X540:
9a75a1ac
DS		 4454 case ixgbe_mac_X550:
4455 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4456 dv_id = IXGBE_LOW_DV_X540(tc);
4457 break;
4458 default:
4459 dv_id = IXGBE_LOW_DV(tc);
4460 break;
4461 }
4462
4463 /* Delay value is calculated in bit times convert to KB */
4464 return IXGBE_BT2KB(dv_id);
4465}
4466
4467/*
4468 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4469 */
4470static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4471{
4472 struct ixgbe_hw *hw = &adapter->hw;
4473 int num_tc = netdev_get_num_tc(adapter->netdev);
4474 int i;
4475
4476 if (!num_tc)
4477 num_tc = 1;
4478
9da712d2
JF		 4479 for (i = 0; i < num_tc; i++) {
4480 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4481 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4482
4483 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4484 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4485 hw->fc.low_water[i] = 0;
9da712d2 4486 }
e5776620
JK		 4487
4488 for (; i < MAX_TRAFFIC_CLASS; i++)
4489 hw->fc.high_water[i] = 0;
9da712d2
JF		 4490}
4491
80605c65
JF		 4492static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4493{
80605c65 4494 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4495 int hdrm;
4496 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4497
4498 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4499 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4500 hdrm = 32 << adapter->fdir_pballoc;
4501 else
4502 hdrm = 0;
80605c65 4503
f7e1027f 4504 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4505 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4506}
4507
e4911d57
AD		 4508static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4509{
4510 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4511 struct hlist_node *node2;
e4911d57
AD		 4512 struct ixgbe_fdir_filter *filter;
4513
4514 spin_lock(&adapter->fdir_perfect_lock);
4515
4516 if (!hlist_empty(&adapter->fdir_filter_list))
4517 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4518
b67bfe0d 4519 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4520 &adapter->fdir_filter_list, fdir_node) {
4521 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4522 &filter->filter,
4523 filter->sw_idx,
4524 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4525 IXGBE_FDIR_DROP_QUEUE :
4526 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4527 }
4528
4529 spin_unlock(&adapter->fdir_perfect_lock);
4530}
4531
2a47fa45
JF		 4532static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4533 struct ixgbe_adapter *adapter)
4534{
4535 struct ixgbe_hw *hw = &adapter->hw;
4536 u32 vmolr;
4537
4538 /* No unicast promiscuous support for VMDQ devices. */
4539 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4540 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4541
4542 /* clear the affected bit */
4543 vmolr &= ~IXGBE_VMOLR_MPE;
4544
4545 if (dev->flags & IFF_ALLMULTI) {
4546 vmolr |= IXGBE_VMOLR_MPE;
4547 } else {
4548 vmolr |= IXGBE_VMOLR_ROMPE;
4549 hw->mac.ops.update_mc_addr_list(hw, dev);
4550 }
5d7daa35 4551 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4552 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4553}
4554
2a47fa45
JF		 4555static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4556{
4557 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4558 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4559 struct ixgbe_hw *hw = &adapter->hw;
4560 u16 pool = vadapter->pool;
4561 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4562 IXGBE_PSRTYPE_UDPHDR |
4563 IXGBE_PSRTYPE_IPV4HDR |
4564 IXGBE_PSRTYPE_L2HDR |
4565 IXGBE_PSRTYPE_IPV6HDR;
4566
4567 if (hw->mac.type == ixgbe_mac_82598EB)
4568 return;
4569
4570 if (rss_i > 3)
4571 psrtype |= 2 << 29;
4572 else if (rss_i > 1)
4573 psrtype |= 1 << 29;
4574
4575 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4576}
4577
4578/**
4579 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4580 * @rx_ring: ring to free buffers from
4581 **/
4582static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4583{
4584 struct device *dev = rx_ring->dev;
4585 unsigned long size;
4586 u16 i;
4587
4588 /* ring already cleared, nothing to do */
4589 if (!rx_ring->rx_buffer_info)
4590 return;
4591
4592 /* Free all the Rx ring sk_buffs */
4593 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4594 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4595
2a47fa45
JF		 4596 if (rx_buffer->skb) {
4597 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4598 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4599 dma_unmap_page(dev,
4600 IXGBE_CB(skb)->dma,
4601 ixgbe_rx_bufsz(rx_ring),
4602 DMA_FROM_DEVICE);
2a47fa45 4603 dev_kfree_skb(skb);
4d2fcfbc 4604 rx_buffer->skb = NULL;
2a47fa45 4605 }
18cb652a
AD		 4606
4607 if (!rx_buffer->page)
4608 continue;
4609
4610 dma_unmap_page(dev, rx_buffer->dma,
4611 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4612 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4613
2a47fa45
JF		 4614 rx_buffer->page = NULL;
4615 }
4616
4617 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4618 memset(rx_ring->rx_buffer_info, 0, size);
4619
4620 /* Zero out the descriptor ring */
4621 memset(rx_ring->desc, 0, rx_ring->size);
4622
4623 rx_ring->next_to_alloc = 0;
4624 rx_ring->next_to_clean = 0;
4625 rx_ring->next_to_use = 0;
4626}
4627
4628static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4629 struct ixgbe_ring *rx_ring)
4630{
4631 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4632 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4633
4634 /* shutdown specific queue receive and wait for dma to settle */
4635 ixgbe_disable_rx_queue(adapter, rx_ring);
4636 usleep_range(10000, 20000);
4637 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4638 ixgbe_clean_rx_ring(rx_ring);
4639 rx_ring->l2_accel_priv = NULL;
4640}
4641
ae72c8d0
JF		 4642static int ixgbe_fwd_ring_down(struct net_device *vdev,
4643 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4644{
4645 struct ixgbe_adapter *adapter = accel->real_adapter;
4646 unsigned int rxbase = accel->rx_base_queue;
4647 unsigned int txbase = accel->tx_base_queue;
4648 int i;
4649
4650 netif_tx_stop_all_queues(vdev);
4651
4652 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4653 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4654 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4655 }
4656
4657 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4658 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4659 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4660 }
4661
4662
4663 return 0;
4664}
4665
4666static int ixgbe_fwd_ring_up(struct net_device *vdev,
4667 struct ixgbe_fwd_adapter *accel)
4668{
4669 struct ixgbe_adapter *adapter = accel->real_adapter;
4670 unsigned int rxbase, txbase, queues;
4671 int i, baseq, err = 0;
4672
4673 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4674 return 0;
4675
4676 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4677 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4678 accel->pool, adapter->num_rx_pools,
4679 baseq, baseq + adapter->num_rx_queues_per_pool,
4680 adapter->fwd_bitmask);
4681
4682 accel->netdev = vdev;
4683 accel->rx_base_queue = rxbase = baseq;
4684 accel->tx_base_queue = txbase = baseq;
4685
4686 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4687 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4688
4689 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4690 adapter->rx_ring[rxbase + i]->netdev = vdev;
4691 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4692 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4693 }
4694
4695 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4696 adapter->tx_ring[txbase + i]->netdev = vdev;
4697 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4698 }
4699
4700 queues = min_t(unsigned int,
4701 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4702 err = netif_set_real_num_tx_queues(vdev, queues);
4703 if (err)
4704 goto fwd_queue_err;
4705
2a47fa45
JF		 4706 err = netif_set_real_num_rx_queues(vdev, queues);
4707 if (err)
4708 goto fwd_queue_err;
4709
4710 if (is_valid_ether_addr(vdev->dev_addr))
4711 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4712
4713 ixgbe_fwd_psrtype(accel);
4714 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4715 return err;
4716fwd_queue_err:
4717 ixgbe_fwd_ring_down(vdev, accel);
4718 return err;
4719}
4720
4721static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4722{
4723 struct net_device *upper;
4724 struct list_head *iter;
4725 int err;
4726
4727 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4728 if (netif_is_macvlan(upper)) {
4729 struct macvlan_dev *dfwd = netdev_priv(upper);
4730 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4731
4732 if (dfwd->fwd_priv) {
4733 err = ixgbe_fwd_ring_up(upper, vadapter);
4734 if (err)
4735 continue;
4736 }
4737 }
4738 }
4739}
4740
9a799d71
AK		 4741static void ixgbe_configure(struct ixgbe_adapter *adapter)
4742{
d2f5e7f3
AS		 4743 struct ixgbe_hw *hw = &adapter->hw;
4744
80605c65 4745 ixgbe_configure_pb(adapter);
7a6b6f51 4746#ifdef CONFIG_IXGBE_DCB
67ebd791 4747 ixgbe_configure_dcb(adapter);
2f90b865 4748#endif
b35d4d42
AD		 4749 /*
4750 * We must restore virtualization before VLANs or else
4751 * the VLVF registers will not be populated
4752 */
4753 ixgbe_configure_virtualization(adapter);
9a799d71 4754
4c1d7b4b 4755 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4756 ixgbe_restore_vlan(adapter);
4757
d2f5e7f3
AS		 4758 switch (hw->mac.type) {
4759 case ixgbe_mac_82599EB:
4760 case ixgbe_mac_X540:
4761 hw->mac.ops.disable_rx_buff(hw);
4762 break;
4763 default:
4764 break;
4765 }
4766
c4cf55e5 4767 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4768 ixgbe_init_fdir_signature_82599(&adapter->hw,
4769 adapter->fdir_pballoc);
e4911d57
AD		 4770 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4771 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4772 adapter->fdir_pballoc);
4773 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4774 }
4c1d7b4b 4775
d2f5e7f3
AS		 4776 switch (hw->mac.type) {
4777 case ixgbe_mac_82599EB:
4778 case ixgbe_mac_X540:
4779 hw->mac.ops.enable_rx_buff(hw);
4780 break;
4781 default:
4782 break;
4783 }
4784
7c8ae65a
AD		 4785#ifdef IXGBE_FCOE
4786 /* configure FCoE L2 filters, redirection table, and Rx control */
4787 ixgbe_configure_fcoe(adapter);
4788
4789#endif /* IXGBE_FCOE */
9a799d71
AK		 4790 ixgbe_configure_tx(adapter);
4791 ixgbe_configure_rx(adapter);
2a47fa45 4792 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4793}
4794
0ecc061d 4795/**
e8e26350
PW		 4796 * ixgbe_sfp_link_config - set up SFP+ link
4797 * @adapter: pointer to private adapter struct
4798 **/
4799static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4800{
7086400d 4801 /*
52f33af8 4802 * We are assuming the worst case scenario here, and that
7086400d
AD		 4803 * is that an SFP was inserted/removed after the reset
4804 * but before SFP detection was enabled. As such the best
4805 * solution is to just start searching as soon as we start
4806 */
4807 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4808 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4809
7086400d 4810 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 4811 adapter->sfp_poll_time = 0;
e8e26350
PW		 4812}
4813
4814/**
4815 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4816 * @hw: pointer to private hardware struct
4817 *
4818 * Returns 0 on success, negative on failure
4819 **/
e8e26350 4820static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4821{
3d292265
JH		 4822 u32 speed;
4823 bool autoneg, link_up = false;
a1e869de 4824 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 4825
4826 if (hw->mac.ops.check_link)
3d292265 4827 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4828
4829 if (ret)
e90dd264 4830 return ret;
0ecc061d 4831
3d292265
JH		 4832 speed = hw->phy.autoneg_advertised;
4833 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4834 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4835 &autoneg);
0ecc061d 4836 if (ret)
e90dd264 4837 return ret;
0ecc061d 4838
8620a103 4839 if (hw->mac.ops.setup_link)
fd0326f2 4840 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4841
0ecc061d
PWJ		 4842 return ret;
4843}
4844
a34bcfff 4845static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4846{
9a799d71 4847 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4848 u32 gpie = 0;
9a799d71 4849
9b471446 4850 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4851 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4852 IXGBE_GPIE_OCD;
4853 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4854 /*
4855 * use EIAM to auto-mask when MSI-X interrupt is asserted
4856 * this saves a register write for every interrupt
4857 */
4858 switch (hw->mac.type) {
4859 case ixgbe_mac_82598EB:
4860 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4861 break;
9b471446 4862 case ixgbe_mac_82599EB:
b93a2226 4863 case ixgbe_mac_X540:
9a75a1ac
DS		 4864 case ixgbe_mac_X550:
4865 case ixgbe_mac_X550EM_x:
b93a2226 4866 default:
9b471446
JB		 4867 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4868 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4869 break;
4870 }
4871 } else {
021230d4
AV		 4872 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4873 * specifically only auto mask tx and rx interrupts */
4874 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4875 }
9a799d71 4876
a34bcfff
AD		 4877 /* XXX: to interrupt immediately for EICS writes, enable this */
4878 /* gpie |= IXGBE_GPIE_EIMEN; */
4879
4880 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4881 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4882
4883 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4884 case IXGBE_82599_VMDQ_8Q_MASK:
4885 gpie |= IXGBE_GPIE_VTMODE_16;
4886 break;
4887 case IXGBE_82599_VMDQ_4Q_MASK:
4888 gpie |= IXGBE_GPIE_VTMODE_32;
4889 break;
4890 default:
4891 gpie |= IXGBE_GPIE_VTMODE_64;
4892 break;
4893 }
119fc60a
MC		 4894 }
4895
5fdd31f9 4896 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4897 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4898 switch (adapter->hw.mac.type) {
4899 case ixgbe_mac_82599EB:
9a900eca 4900 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec
DS		 4901 break;
4902 case ixgbe_mac_X540:
4903 gpie |= IXGBE_EIMS_TS;
4904 break;
4905 default:
4906 break;
4907 }
4908 }
5fdd31f9 4909
a34bcfff
AD		 4910 /* Enable fan failure interrupt */
4911 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 4912 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 4913
a023bbd0
DS		 4914 switch (hw->mac.type) {
4915 case ixgbe_mac_82599EB:
4916 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
4917 break;
4918 case ixgbe_mac_X550EM_x:
4919 gpie |= IXGBE_SDP0_GPIEN_X540;
4920 break;
4921 default:
4922 break;
2698b208 4923 }
a34bcfff
AD		 4924
4925 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4926}
4927
c7ccde0f 4928static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4929{
4930 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4931 int err;
a34bcfff
AD		 4932 u32 ctrl_ext;
4933
4934 ixgbe_get_hw_control(adapter);
4935 ixgbe_setup_gpie(adapter);
e8e26350 4936
9a799d71
AK		 4937 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4938 ixgbe_configure_msix(adapter);
4939 else
4940 ixgbe_configure_msi_and_legacy(adapter);
4941
ec74a471
ET		 4942 /* enable the optics for 82599 SFP+ fiber */
4943 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4944 hw->mac.ops.enable_tx_laser(hw);
4945
961fac88
DS		 4946 if (hw->phy.ops.set_phy_power)
4947 hw->phy.ops.set_phy_power(hw, true);
4948
4e857c58 4949 smp_mb__before_atomic();
9a799d71 4950 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4951 ixgbe_napi_enable_all(adapter);
4952
73c4b7cd
AD		 4953 if (ixgbe_is_sfp(hw)) {
4954 ixgbe_sfp_link_config(adapter);
4955 } else {
4956 err = ixgbe_non_sfp_link_config(hw);
4957 if (err)
4958 e_err(probe, "link_config FAILED %d\n", err);
4959 }
4960
021230d4
AV		 4961 /* clear any pending interrupts, may auto mask */
4962 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4963 ixgbe_irq_enable(adapter, true, true);
9a799d71 4964
bf069c97
DS		 4965 /*
4966 * If this adapter has a fan, check to see if we had a failure
4967 * before we enabled the interrupt.
4968 */
4969 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4970 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4971 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4972 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4973 }
4974
9a799d71
AK		 4975 /* bring the link up in the watchdog, this could race with our first
4976 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4977 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4978 adapter->link_check_timeout = jiffies;
7086400d 4979 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4980
4981 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4982 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4983 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4984 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4985}
4986
d4f80882
AV		 4987void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4988{
4989 WARN_ON(in_interrupt());
7086400d
AD		 4990 /* put off any impending NetWatchDogTimeout */
4991 adapter->netdev->trans_start = jiffies;
4992
d4f80882 4993 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4994 usleep_range(1000, 2000);
d4f80882 4995 ixgbe_down(adapter);
5809a1ae
GR		 4996 /*
4997 * If SR-IOV enabled then wait a bit before bringing the adapter
4998 * back up to give the VFs time to respond to the reset. The
4999 * two second wait is based upon the watchdog timer cycle in
5000 * the VF driver.
5001 */
5002 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5003 msleep(2000);
d4f80882
AV		 5004 ixgbe_up(adapter);
5005 clear_bit(__IXGBE_RESETTING, &adapter->state);
5006}
5007
c7ccde0f 5008void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5009{
5010 /* hardware has been reset, we need to reload some things */
5011 ixgbe_configure(adapter);
5012
c7ccde0f 5013 ixgbe_up_complete(adapter);
9a799d71
AK		 5014}
5015
5016void ixgbe_reset(struct ixgbe_adapter *adapter)
5017{
c44ade9e 5018 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5019 struct net_device *netdev = adapter->netdev;
8ca783ab 5020 int err;
5d7daa35 5021 u8 old_addr[ETH_ALEN];
8ca783ab 5022
b0483c8f
MR		 5023 if (ixgbe_removed(hw->hw_addr))
5024 return;
7086400d
AD		 5025 /* lock SFP init bit to prevent race conditions with the watchdog */
5026 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5027 usleep_range(1000, 2000);
5028
5029 /* clear all SFP and link config related flags while holding SFP_INIT */
5030 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5031 IXGBE_FLAG2_SFP_NEEDS_RESET);
5032 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5033
8ca783ab 5034 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5035 switch (err) {
5036 case 0:
5037 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5038 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5039 break;
5040 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5041 e_dev_err("master disable timed out\n");
da4dd0f7 5042 break;
794caeb2
PWJ		 5043 case IXGBE_ERR_EEPROM_VERSION:
5044 /* We are running on a pre-production device, log a warning */
849c4542 5045 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5046 "Please be aware there may be issues associated with "
849c4542
ET		 5047 "your hardware. If you are experiencing problems "
5048 "please contact your Intel or hardware "
5049 "representative who provided you with this "
5050 "hardware.\n");
794caeb2 5051 break;
da4dd0f7 5052 default:
849c4542 5053 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5054 }
9a799d71 5055
7086400d 5056 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 5057 /* do not flush user set addresses */
5058 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
5059 ixgbe_flush_sw_mac_table(adapter);
5060 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 5061
5062 /* update SAN MAC vmdq pool selection */
5063 if (hw->mac.san_mac_rar_index)
5064 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5065
8fecf67c 5066 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5067 ixgbe_ptp_reset(adapter);
961fac88
DS		 5068
5069 if (hw->phy.ops.set_phy_power) {
5070 if (!netif_running(adapter->netdev) && !adapter->wol)
5071 hw->phy.ops.set_phy_power(hw, false);
5072 else
5073 hw->phy.ops.set_phy_power(hw, true);
5074 }
9a799d71
AK		 5075}
5076
9a799d71
AK		 5077/**
5078 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5079 * @tx_ring: ring to be cleaned
5080 **/
b6ec895e 5081static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5082{
5083 struct ixgbe_tx_buffer *tx_buffer_info;
5084 unsigned long size;
b6ec895e 5085 u16 i;
9a799d71 5086
84418e3b
AD		 5087 /* ring already cleared, nothing to do */
5088 if (!tx_ring->tx_buffer_info)
5089 return;
9a799d71 5090
84418e3b 5091 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5092 for (i = 0; i < tx_ring->count; i++) {
5093 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5094 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5095 }
5096
dad8a3b3
JF		 5097 netdev_tx_reset_queue(txring_txq(tx_ring));
5098
9a799d71
AK		 5099 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5100 memset(tx_ring->tx_buffer_info, 0, size);
5101
5102 /* Zero out the descriptor ring */
5103 memset(tx_ring->desc, 0, tx_ring->size);
5104
5105 tx_ring->next_to_use = 0;
5106 tx_ring->next_to_clean = 0;
9a799d71
AK		 5107}
5108
5109/**
021230d4 5110 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5111 * @adapter: board private structure
5112 **/
021230d4 5113static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5114{
5115 int i;
5116
021230d4 5117 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5118 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5119}
5120
5121/**
021230d4 5122 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5123 * @adapter: board private structure
5124 **/
021230d4 5125static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5126{
5127 int i;
5128
021230d4 5129 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5130 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5131}
5132
e4911d57
AD		 5133static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5134{
b67bfe0d 5135 struct hlist_node *node2;
e4911d57
AD		 5136 struct ixgbe_fdir_filter *filter;
5137
5138 spin_lock(&adapter->fdir_perfect_lock);
5139
b67bfe0d 5140 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5141 &adapter->fdir_filter_list, fdir_node) {
5142 hlist_del(&filter->fdir_node);
5143 kfree(filter);
5144 }
5145 adapter->fdir_filter_count = 0;
5146
5147 spin_unlock(&adapter->fdir_perfect_lock);
5148}
5149
9a799d71
AK		 5150void ixgbe_down(struct ixgbe_adapter *adapter)
5151{
5152 struct net_device *netdev = adapter->netdev;
7f821875 5153 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5154 struct net_device *upper;
5155 struct list_head *iter;
bf29ee6c 5156 int i;
9a799d71
AK		 5157
5158 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5159 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5160 return; /* do nothing if already down */
9a799d71
AK		 5161
5162 /* disable receives */
1f9ac57c 5163 hw->mac.ops.disable_rx(hw);
9a799d71 5164
2d39d576
YZ		 5165 /* disable all enabled rx queues */
5166 for (i = 0; i < adapter->num_rx_queues; i++)
5167 /* this call also flushes the previous write */
5168 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5169
032b4325 5170 usleep_range(10000, 20000);
9a799d71 5171
7f821875
JB		 5172 netif_tx_stop_all_queues(netdev);
5173
7086400d 5174 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5175 netif_carrier_off(netdev);
5176 netif_tx_disable(netdev);
5177
2a47fa45
JF		 5178 /* disable any upper devices */
5179 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5180 if (netif_is_macvlan(upper)) {
5181 struct macvlan_dev *vlan = netdev_priv(upper);
5182
5183 if (vlan->fwd_priv) {
5184 netif_tx_stop_all_queues(upper);
5185 netif_carrier_off(upper);
5186 netif_tx_disable(upper);
5187 }
5188 }
5189 }
5190
c0dfb90e
JF		 5191 ixgbe_irq_disable(adapter);
5192
5193 ixgbe_napi_disable_all(adapter);
5194
d034acf1
AD		 5195 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5196 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5197 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5198
5199 del_timer_sync(&adapter->service_timer);
5200
34cecbbf 5201 if (adapter->num_vfs) {
8e34d1aa
AD		 5202 /* Clear EITR Select mapping */
5203 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5204
5205 /* Mark all the VFs as inactive */
5206 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5207 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5208
34cecbbf
AD		 5209 /* ping all the active vfs to let them know we are going down */
5210 ixgbe_ping_all_vfs(adapter);
5211
5212 /* Disable all VFTE/VFRE TX/RX */
5213 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5214 }
5215
7f821875
JB		 5216 /* disable transmits in the hardware now that interrupts are off */
5217 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5218 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5219 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5220 }
34cecbbf 5221
9a75a1ac 5222 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5223 switch (hw->mac.type) {
5224 case ixgbe_mac_82599EB:
b93a2226 5225 case ixgbe_mac_X540:
9a75a1ac
DS		 5226 case ixgbe_mac_X550:
5227 case ixgbe_mac_X550EM_x:
88512539 5228 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5229 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5230 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5231 break;
5232 default:
5233 break;
5234 }
7f821875 5235
6f4a0e45
PL		 5236 if (!pci_channel_offline(adapter->pdev))
5237 ixgbe_reset(adapter);
c6ecf39a 5238
ec74a471
ET		 5239 /* power down the optics for 82599 SFP+ fiber */
5240 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5241 hw->mac.ops.disable_tx_laser(hw);
5242
9a799d71
AK		 5243 ixgbe_clean_all_tx_rings(adapter);
5244 ixgbe_clean_all_rx_rings(adapter);
5245
5dd2d332 5246#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5247 /* since we reset the hardware DCA settings were cleared */
e35ec126 5248 ixgbe_setup_dca(adapter);
96b0e0f6 5249#endif
9a799d71
AK		 5250}
5251
9a799d71
AK		 5252/**
5253 * ixgbe_tx_timeout - Respond to a Tx Hang
5254 * @netdev: network interface device structure
5255 **/
5256static void ixgbe_tx_timeout(struct net_device *netdev)
5257{
5258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5259
5260 /* Do the reset outside of interrupt context */
c83c6cbd 5261 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5262}
5263
9a799d71
AK		 5264/**
5265 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5266 * @adapter: board private structure to initialize
5267 *
5268 * ixgbe_sw_init initializes the Adapter private data structure.
5269 * Fields are initialized based on PCI device information and
5270 * OS network device settings (MTU size).
5271 **/
9f9a12f8 5272static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5273{
5274 struct ixgbe_hw *hw = &adapter->hw;
5275 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5276 unsigned int rss, fdir;
cb6d0f5e 5277 u32 fwsm;
7a6b6f51 5278#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5279 int j;
5280 struct tc_configuration *tc;
5281#endif
021230d4 5282
c44ade9e
JB		 5283 /* PCI config space info */
5284
5285 hw->vendor_id = pdev->vendor;
5286 hw->device_id = pdev->device;
5287 hw->revision_id = pdev->revision;
5288 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5289 hw->subsystem_device_id = pdev->subsystem_device;
5290
8fc3bb6d 5291 /* Set common capability flags and settings */
0f9b232b 5292 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5293 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5294 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5295 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5296 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5297 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5298 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5299 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5300 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5301#ifdef CONFIG_IXGBE_DCA
5302 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5303#endif
5304#ifdef IXGBE_FCOE
5305 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5306 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5307#ifdef CONFIG_IXGBE_DCB
5308 /* Default traffic class to use for FCoE */
5309 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5310#endif /* CONFIG_IXGBE_DCB */
5311#endif /* IXGBE_FCOE */
5312
5d7daa35
JK		 5313 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5314 hw->mac.num_rar_entries,
5315 GFP_ATOMIC);
5316
8fc3bb6d 5317 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5318 switch (hw->mac.type) {
5319 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5320 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5321 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5322
bf069c97
DS		 5323 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5324 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5325
49c7ffbe 5326 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5327 adapter->ring_feature[RING_F_FDIR].limit = 0;
5328 adapter->atr_sample_rate = 0;
5329 adapter->fdir_pballoc = 0;
5330#ifdef IXGBE_FCOE
5331 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5332 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5333#ifdef CONFIG_IXGBE_DCB
5334 adapter->fcoe.up = 0;
5335#endif /* IXGBE_DCB */
5336#endif /* IXGBE_FCOE */
5337 break;
5338 case ixgbe_mac_82599EB:
5339 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5340 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5341 break;
b93a2226 5342 case ixgbe_mac_X540:
9a900eca 5343 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5344 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5345 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5346 break;
9a75a1ac
DS		 5347 case ixgbe_mac_X550EM_x:
5348 case ixgbe_mac_X550:
5349#ifdef CONFIG_IXGBE_DCA
5350 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5351#endif
5352#ifdef CONFIG_IXGBE_VXLAN
5353 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5354#endif
5355 break;
bd508178
AD		 5356 default:
5357 break;
f8212f97 5358 }
2f90b865 5359
7c8ae65a
AD		 5360#ifdef IXGBE_FCOE
5361 /* FCoE support exists, always init the FCoE lock */
5362 spin_lock_init(&adapter->fcoe.lock);
5363
5364#endif
1fc5f038
AD		 5365 /* n-tuple support exists, always init our spinlock */
5366 spin_lock_init(&adapter->fdir_perfect_lock);
5367
7a6b6f51 5368#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5369 switch (hw->mac.type) {
5370 case ixgbe_mac_X540:
9a75a1ac
DS		 5371 case ixgbe_mac_X550:
5372 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5373 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5374 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5375 break;
5376 default:
5377 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5378 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5379 break;
5380 }
5381
2f90b865
AD		 5382 /* Configure DCB traffic classes */
5383 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5384 tc = &adapter->dcb_cfg.tc_config[j];
5385 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5386 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5387 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5388 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5389 tc->dcb_pfc = pfc_disabled;
5390 }
4de2a022
JF		 5391
5392 /* Initialize default user to priority mapping, UPx->TC0 */
5393 tc = &adapter->dcb_cfg.tc_config[0];
5394 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5395 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5396
2f90b865
AD		 5397 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5398 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5399 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5400 adapter->dcb_set_bitmap = 0x00;
3032309b 5401 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5402 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5403 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5404
5405#endif
9a799d71
AK		 5406
5407 /* default flow control settings */
cd7664f6 5408 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5409 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5410 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5411 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5412 hw->fc.send_xon = true;
73d80953 5413 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5414
99d74487 5415#ifdef CONFIG_PCI_IOV
170e8543
JK		 5416 if (max_vfs > 0)
5417 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5418
99d74487 5419 /* assign number of SR-IOV VFs */
170e8543 5420 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5421 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5422 adapter->num_vfs = 0;
5423 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5424 } else {
5425 adapter->num_vfs = max_vfs;
5426 }
5427 }
5428#endif /* CONFIG_PCI_IOV */
99d74487 5429
30efa5a3 5430 /* enable itr by default in dynamic mode */
f7554a2b 5431 adapter->rx_itr_setting = 1;
f7554a2b 5432 adapter->tx_itr_setting = 1;
30efa5a3 5433
30efa5a3
JB		 5434 /* set default ring sizes */
5435 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5436 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5437
bd198058 5438 /* set default work limits */
59224555 5439 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5440
9a799d71 5441 /* initialize eeprom parameters */
c44ade9e 5442 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5443 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5444 return -EIO;
5445 }
5446
2a47fa45
JF		 5447 /* PF holds first pool slot */
5448 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5449 set_bit(__IXGBE_DOWN, &adapter->state);
5450
5451 return 0;
5452}
5453
5454/**
5455 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5456 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5457 *
5458 * Return 0 on success, negative on failure
5459 **/
b6ec895e 5460int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5461{
b6ec895e 5462 struct device *dev = tx_ring->dev;
de88eeeb 5463 int orig_node = dev_to_node(dev);
ca8dfe25 5464 int ring_node = -1;
9a799d71
AK		 5465 int size;
5466
3a581073 5467 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5468
5469 if (tx_ring->q_vector)
ca8dfe25 5470 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5471
ca8dfe25 5472 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5473 if (!tx_ring->tx_buffer_info)
89bf67f1 5474 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5475 if (!tx_ring->tx_buffer_info)
5476 goto err;
9a799d71 5477
827da44c
JS		 5478 u64_stats_init(&tx_ring->syncp);
5479
9a799d71 5480 /* round up to nearest 4K */
12207e49 5481 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5482 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5483
ca8dfe25 5484 set_dev_node(dev, ring_node);
de88eeeb
AD		 5485 tx_ring->desc = dma_alloc_coherent(dev,
5486 tx_ring->size,
5487 &tx_ring->dma,
5488 GFP_KERNEL);
5489 set_dev_node(dev, orig_node);
5490 if (!tx_ring->desc)
5491 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5492 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5493 if (!tx_ring->desc)
5494 goto err;
9a799d71 5495
3a581073
JB		 5496 tx_ring->next_to_use = 0;
5497 tx_ring->next_to_clean = 0;
9a799d71 5498 return 0;
e01c31a5
JB		 5499
5500err:
5501 vfree(tx_ring->tx_buffer_info);
5502 tx_ring->tx_buffer_info = NULL;
b6ec895e 5503 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5504 return -ENOMEM;
9a799d71
AK		 5505}
5506
69888674
AD		 5507/**
5508 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5509 * @adapter: board private structure
5510 *
5511 * If this function returns with an error, then it's possible one or
5512 * more of the rings is populated (while the rest are not). It is the
5513 * callers duty to clean those orphaned rings.
5514 *
5515 * Return 0 on success, negative on failure
5516 **/
5517static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5518{
5519 int i, err = 0;
5520
5521 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5522 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5523 if (!err)
5524 continue;
de3d5b94 5525
396e799c 5526 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5527 goto err_setup_tx;
69888674
AD		 5528 }
5529
de3d5b94
AD		 5530 return 0;
5531err_setup_tx:
5532 /* rewind the index freeing the rings as we go */
5533 while (i--)
5534 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5535 return err;
5536}
5537
9a799d71
AK		 5538/**
5539 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5540 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5541 *
5542 * Returns 0 on success, negative on failure
5543 **/
b6ec895e 5544int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5545{
b6ec895e 5546 struct device *dev = rx_ring->dev;
de88eeeb 5547 int orig_node = dev_to_node(dev);
ca8dfe25 5548 int ring_node = -1;
021230d4 5549 int size;
9a799d71 5550
3a581073 5551 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5552
5553 if (rx_ring->q_vector)
ca8dfe25 5554 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5555
ca8dfe25 5556 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5557 if (!rx_ring->rx_buffer_info)
89bf67f1 5558 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5559 if (!rx_ring->rx_buffer_info)
5560 goto err;
9a799d71 5561
827da44c
JS		 5562 u64_stats_init(&rx_ring->syncp);
5563
9a799d71 5564 /* Round up to nearest 4K */
3a581073
JB		 5565 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5566 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5567
ca8dfe25 5568 set_dev_node(dev, ring_node);
de88eeeb
AD		 5569 rx_ring->desc = dma_alloc_coherent(dev,
5570 rx_ring->size,
5571 &rx_ring->dma,
5572 GFP_KERNEL);
5573 set_dev_node(dev, orig_node);
5574 if (!rx_ring->desc)
5575 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5576 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5577 if (!rx_ring->desc)
5578 goto err;
9a799d71 5579
3a581073
JB		 5580 rx_ring->next_to_clean = 0;
5581 rx_ring->next_to_use = 0;
9a799d71
AK		 5582
5583 return 0;
b6ec895e
AD		 5584err:
5585 vfree(rx_ring->rx_buffer_info);
5586 rx_ring->rx_buffer_info = NULL;
5587 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5588 return -ENOMEM;
9a799d71
AK		 5589}
5590
69888674
AD		 5591/**
5592 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5593 * @adapter: board private structure
5594 *
5595 * If this function returns with an error, then it's possible one or
5596 * more of the rings is populated (while the rest are not). It is the
5597 * callers duty to clean those orphaned rings.
5598 *
5599 * Return 0 on success, negative on failure
5600 **/
69888674
AD		 5601static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5602{
5603 int i, err = 0;
5604
5605 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5606 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5607 if (!err)
5608 continue;
de3d5b94 5609
396e799c 5610 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5611 goto err_setup_rx;
69888674
AD		 5612 }
5613
7c8ae65a
AD		 5614#ifdef IXGBE_FCOE
5615 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5616 if (!err)
5617#endif
5618 return 0;
de3d5b94
AD		 5619err_setup_rx:
5620 /* rewind the index freeing the rings as we go */
5621 while (i--)
5622 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5623 return err;
5624}
5625
9a799d71
AK		 5626/**
5627 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5628 * @tx_ring: Tx descriptor ring for a specific queue
5629 *
5630 * Free all transmit software resources
5631 **/
b6ec895e 5632void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5633{
b6ec895e 5634 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5635
5636 vfree(tx_ring->tx_buffer_info);
5637 tx_ring->tx_buffer_info = NULL;
5638
b6ec895e
AD		 5639 /* if not set, then don't free */
5640 if (!tx_ring->desc)
5641 return;
5642
5643 dma_free_coherent(tx_ring->dev, tx_ring->size,
5644 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5645
5646 tx_ring->desc = NULL;
5647}
5648
5649/**
5650 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5651 * @adapter: board private structure
5652 *
5653 * Free all transmit software resources
5654 **/
5655static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5656{
5657 int i;
5658
5659 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5660 if (adapter->tx_ring[i]->desc)
b6ec895e 5661 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5662}
5663
5664/**
b4617240 5665 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5666 * @rx_ring: ring to clean the resources from
5667 *
5668 * Free all receive software resources
5669 **/
b6ec895e 5670void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5671{
b6ec895e 5672 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5673
5674 vfree(rx_ring->rx_buffer_info);
5675 rx_ring->rx_buffer_info = NULL;
5676
b6ec895e
AD		 5677 /* if not set, then don't free */
5678 if (!rx_ring->desc)
5679 return;
5680
5681 dma_free_coherent(rx_ring->dev, rx_ring->size,
5682 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5683
5684 rx_ring->desc = NULL;
5685}
5686
5687/**
5688 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5689 * @adapter: board private structure
5690 *
5691 * Free all receive software resources
5692 **/
5693static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5694{
5695 int i;
5696
7c8ae65a
AD		 5697#ifdef IXGBE_FCOE
5698 ixgbe_free_fcoe_ddp_resources(adapter);
5699
5700#endif
9a799d71 5701 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5702 if (adapter->rx_ring[i]->desc)
b6ec895e 5703 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5704}
5705
9a799d71
AK		 5706/**
5707 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5708 * @netdev: network interface device structure
5709 * @new_mtu: new value for maximum frame size
5710 *
5711 * Returns 0 on success, negative on failure
5712 **/
5713static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5714{
5715 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5716 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5717
42c783c5 5718 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5719 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5720 return -EINVAL;
5721
5722 /*
872844dd
AD		 5723 * For 82599EB we cannot allow legacy VFs to enable their receive
5724 * paths when MTU greater than 1500 is configured. So display a
5725 * warning that legacy VFs will be disabled.
655309e9
AD		 5726 */
5727 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5728 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5729 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5730 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5731
396e799c 5732 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5733
021230d4 5734 /* must set new MTU before calling down or up */
9a799d71
AK		 5735 netdev->mtu = new_mtu;
5736
d4f80882
AV		 5737 if (netif_running(netdev))
5738 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5739
5740 return 0;
5741}
5742
5743/**
5744 * ixgbe_open - Called when a network interface is made active
5745 * @netdev: network interface device structure
5746 *
5747 * Returns 0 on success, negative value on failure
5748 *
5749 * The open entry point is called when a network interface is made
5750 * active by the system (IFF_UP). At this point all resources needed
5751 * for transmit and receive operations are allocated, the interrupt
5752 * handler is registered with the OS, the watchdog timer is started,
5753 * and the stack is notified that the interface is ready.
5754 **/
5755static int ixgbe_open(struct net_device *netdev)
5756{
5757 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5758 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5759 int err, queues;
4bebfaa5
AK		 5760
5761 /* disallow open during test */
5762 if (test_bit(__IXGBE_TESTING, &adapter->state))
5763 return -EBUSY;
9a799d71 5764
54386467
JB		 5765 netif_carrier_off(netdev);
5766
9a799d71
AK		 5767 /* allocate transmit descriptors */
5768 err = ixgbe_setup_all_tx_resources(adapter);
5769 if (err)
5770 goto err_setup_tx;
5771
9a799d71
AK		 5772 /* allocate receive descriptors */
5773 err = ixgbe_setup_all_rx_resources(adapter);
5774 if (err)
5775 goto err_setup_rx;
5776
5777 ixgbe_configure(adapter);
5778
021230d4 5779 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5780 if (err)
5781 goto err_req_irq;
5782
ac802f5d 5783 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5784 if (adapter->num_rx_pools > 1)
5785 queues = adapter->num_rx_queues_per_pool;
5786 else
5787 queues = adapter->num_tx_queues;
5788
5789 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5790 if (err)
5791 goto err_set_queues;
5792
2a47fa45
JF		 5793 if (adapter->num_rx_pools > 1 &&
5794 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5795 queues = IXGBE_MAX_L2A_QUEUES;
5796 else
5797 queues = adapter->num_rx_queues;
5798 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5799 if (err)
5800 goto err_set_queues;
5801
1a71ab24 5802 ixgbe_ptp_init(adapter);
1a71ab24 5803
c7ccde0f 5804 ixgbe_up_complete(adapter);
9a799d71 5805
67359c3c
MR		 5806 ixgbe_clear_vxlan_port(adapter);
5807#ifdef CONFIG_IXGBE_VXLAN
3f207800 5808 vxlan_get_rx_port(netdev);
3f207800 5809#endif
67359c3c 5810
9a799d71
AK		 5811 return 0;
5812
ac802f5d
AD		 5813err_set_queues:
5814 ixgbe_free_irq(adapter);
9a799d71 5815err_req_irq:
a20a1199 5816 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 5817 if (hw->phy.ops.set_phy_power && !adapter->wol)
5818 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 5819err_setup_rx:
a20a1199 5820 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5821err_setup_tx:
9a799d71
AK		 5822 ixgbe_reset(adapter);
5823
5824 return err;
5825}
5826
a0cccce2
JK		 5827static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5828{
5829 ixgbe_ptp_suspend(adapter);
5830
6ac74394
DS		 5831 if (adapter->hw.phy.ops.enter_lplu) {
5832 adapter->hw.phy.reset_disable = true;
5833 ixgbe_down(adapter);
5834 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5835 adapter->hw.phy.reset_disable = false;
5836 } else {
5837 ixgbe_down(adapter);
5838 }
5839
a0cccce2
JK		 5840 ixgbe_free_irq(adapter);
5841
5842 ixgbe_free_all_tx_resources(adapter);
5843 ixgbe_free_all_rx_resources(adapter);
5844}
5845
9a799d71
AK		 5846/**
5847 * ixgbe_close - Disables a network interface
5848 * @netdev: network interface device structure
5849 *
5850 * Returns 0, this is not allowed to fail
5851 *
5852 * The close entry point is called when an interface is de-activated
5853 * by the OS. The hardware is still under the drivers control, but
5854 * needs to be disabled. A global MAC reset is issued to stop the
5855 * hardware, and all transmit and receive resources are freed.
5856 **/
5857static int ixgbe_close(struct net_device *netdev)
5858{
5859 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5860
1a71ab24 5861 ixgbe_ptp_stop(adapter);
1a71ab24 5862
a0cccce2 5863 ixgbe_close_suspend(adapter);
9a799d71 5864
e4911d57
AD		 5865 ixgbe_fdir_filter_exit(adapter);
5866
5eba3699 5867 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5868
5869 return 0;
5870}
5871
b3c8b4ba
AD		 5872#ifdef CONFIG_PM
5873static int ixgbe_resume(struct pci_dev *pdev)
5874{
c60fbb00
AD		 5875 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5876 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5877 u32 err;
5878
0391bbe3 5879 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5880 pci_set_power_state(pdev, PCI_D0);
5881 pci_restore_state(pdev);
656ab817
DS		 5882 /*
5883 * pci_restore_state clears dev->state_saved so call
5884 * pci_save_state to restore it.
5885 */
5886 pci_save_state(pdev);
9ce77666 5887
5888 err = pci_enable_device_mem(pdev);
b3c8b4ba 5889 if (err) {
849c4542 5890 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5891 return err;
5892 }
4e857c58 5893 smp_mb__before_atomic();
41c62843 5894 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5895 pci_set_master(pdev);
5896
dd4d8ca6 5897 pci_wake_from_d3(pdev, false);
b3c8b4ba 5898
b3c8b4ba
AD		 5899 ixgbe_reset(adapter);
5900
495dce12
WJP		 5901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5902
ac802f5d
AD		 5903 rtnl_lock();
5904 err = ixgbe_init_interrupt_scheme(adapter);
5905 if (!err && netif_running(netdev))
c60fbb00 5906 err = ixgbe_open(netdev);
ac802f5d
AD		 5907
5908 rtnl_unlock();
5909
5910 if (err)
5911 return err;
b3c8b4ba
AD		 5912
5913 netif_device_attach(netdev);
5914
5915 return 0;
5916}
b3c8b4ba 5917#endif /* CONFIG_PM */
9d8d05ae
RW		 5918
5919static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5920{
c60fbb00
AD		 5921 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5922 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5923 struct ixgbe_hw *hw = &adapter->hw;
5924 u32 ctrl, fctrl;
5925 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5926#ifdef CONFIG_PM
5927 int retval = 0;
5928#endif
5929
5930 netif_device_detach(netdev);
5931
499ab5cc 5932 rtnl_lock();
a0cccce2
JK		 5933 if (netif_running(netdev))
5934 ixgbe_close_suspend(adapter);
499ab5cc 5935 rtnl_unlock();
b3c8b4ba 5936
5f5ae6fc
AD		 5937 ixgbe_clear_interrupt_scheme(adapter);
5938
b3c8b4ba
AD		 5939#ifdef CONFIG_PM
5940 retval = pci_save_state(pdev);
5941 if (retval)
5942 return retval;
4df10466 5943
b3c8b4ba 5944#endif
f4f1040a
JK		 5945 if (hw->mac.ops.stop_link_on_d3)
5946 hw->mac.ops.stop_link_on_d3(hw);
5947
e8e26350
PW		 5948 if (wufc) {
5949 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5950
ec74a471
ET		 5951 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5952 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5953 hw->mac.ops.enable_tx_laser(hw);
5954
e8e26350
PW		 5955 /* turn on all-multi mode if wake on multicast is enabled */
5956 if (wufc & IXGBE_WUFC_MC) {
5957 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5958 fctrl |= IXGBE_FCTRL_MPE;
5959 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5960 }
5961
5962 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5963 ctrl |= IXGBE_CTRL_GIO_DIS;
5964 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5965
5966 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5967 } else {
5968 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5969 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5970 }
5971
bd508178
AD		 5972 switch (hw->mac.type) {
5973 case ixgbe_mac_82598EB:
dd4d8ca6 5974 pci_wake_from_d3(pdev, false);
bd508178
AD		 5975 break;
5976 case ixgbe_mac_82599EB:
b93a2226 5977 case ixgbe_mac_X540:
9a75a1ac
DS		 5978 case ixgbe_mac_X550:
5979 case ixgbe_mac_X550EM_x:
bd508178
AD		 5980 pci_wake_from_d3(pdev, !!wufc);
5981 break;
5982 default:
5983 break;
5984 }
b3c8b4ba 5985
9d8d05ae 5986 *enable_wake = !!wufc;
961fac88
DS		 5987 if (hw->phy.ops.set_phy_power && !*enable_wake)
5988 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 5989
b3c8b4ba
AD		 5990 ixgbe_release_hw_control(adapter);
5991
41c62843
MR		 5992 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5993 pci_disable_device(pdev);
b3c8b4ba 5994
9d8d05ae
RW		 5995 return 0;
5996}
5997
5998#ifdef CONFIG_PM
5999static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6000{
6001 int retval;
6002 bool wake;
6003
6004 retval = __ixgbe_shutdown(pdev, &wake);
6005 if (retval)
6006 return retval;
6007
6008 if (wake) {
6009 pci_prepare_to_sleep(pdev);
6010 } else {
6011 pci_wake_from_d3(pdev, false);
6012 pci_set_power_state(pdev, PCI_D3hot);
6013 }
b3c8b4ba
AD		 6014
6015 return 0;
6016}
9d8d05ae 6017#endif /* CONFIG_PM */
b3c8b4ba
AD		 6018
6019static void ixgbe_shutdown(struct pci_dev *pdev)
6020{
9d8d05ae
RW		 6021 bool wake;
6022
6023 __ixgbe_shutdown(pdev, &wake);
6024
6025 if (system_state == SYSTEM_POWER_OFF) {
6026 pci_wake_from_d3(pdev, wake);
6027 pci_set_power_state(pdev, PCI_D3hot);
6028 }
b3c8b4ba
AD		 6029}
6030
9a799d71
AK		 6031/**
6032 * ixgbe_update_stats - Update the board statistics counters.
6033 * @adapter: board private structure
6034 **/
6035void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6036{
2d86f139 6037 struct net_device *netdev = adapter->netdev;
9a799d71 6038 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6039 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6040 u64 total_mpc = 0;
6041 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6042 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6043 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6044 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6045
d08935c2
DS		 6046 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6047 test_bit(__IXGBE_RESETTING, &adapter->state))
6048 return;
6049
94b982b2 6050 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6051 u64 rsc_count = 0;
94b982b2 6052 u64 rsc_flush = 0;
94b982b2 6053 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6054 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6055 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6056 }
6057 adapter->rsc_total_count = rsc_count;
6058 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6059 }
6060
5b7da515
AD		 6061 for (i = 0; i < adapter->num_rx_queues; i++) {
6062 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6063 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6064 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6065 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6066 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6067 bytes += rx_ring->stats.bytes;
6068 packets += rx_ring->stats.packets;
6069 }
6070 adapter->non_eop_descs = non_eop_descs;
6071 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6072 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6073 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6074 netdev->stats.rx_bytes = bytes;
6075 netdev->stats.rx_packets = packets;
6076
6077 bytes = 0;
6078 packets = 0;
7ca3bc58 6079 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6080 for (i = 0; i < adapter->num_tx_queues; i++) {
6081 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6082 restart_queue += tx_ring->tx_stats.restart_queue;
6083 tx_busy += tx_ring->tx_stats.tx_busy;
6084 bytes += tx_ring->stats.bytes;
6085 packets += tx_ring->stats.packets;
6086 }
eb985f09 6087 adapter->restart_queue = restart_queue;
5b7da515
AD		 6088 adapter->tx_busy = tx_busy;
6089 netdev->stats.tx_bytes = bytes;
6090 netdev->stats.tx_packets = packets;
7ca3bc58 6091
7ca647bd 6092 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6093
6094 /* 8 register reads */
6f11eef7
AV		 6095 for (i = 0; i < 8; i++) {
6096 /* for packet buffers not used, the register should read 0 */
6097 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6098 missed_rx += mpc;
7ca647bd
JP		 6099 hwstats->mpc[i] += mpc;
6100 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6101 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6102 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6103 switch (hw->mac.type) {
6104 case ixgbe_mac_82598EB:
1a70db4b
ET		 6105 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6106 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6107 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6108 hwstats->pxonrxc[i] +=
6109 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6110 break;
6111 case ixgbe_mac_82599EB:
b93a2226 6112 case ixgbe_mac_X540:
9a75a1ac
DS		 6113 case ixgbe_mac_X550:
6114 case ixgbe_mac_X550EM_x:
bd508178
AD		 6115 hwstats->pxonrxc[i] +=
6116 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6117 break;
6118 default:
6119 break;
e8e26350 6120 }
6f11eef7 6121 }
1a70db4b
ET		 6122
6123 /*16 register reads */
6124 for (i = 0; i < 16; i++) {
6125 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6126 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6127 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6128 (hw->mac.type == ixgbe_mac_X540) ||
6129 (hw->mac.type == ixgbe_mac_X550) ||
6130 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6131 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6132 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6133 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6134 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6135 }
6136 }
6137
7ca647bd 6138 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6139 /* work around hardware counting issue */
7ca647bd 6140 hwstats->gprc -= missed_rx;
6f11eef7 6141
c84d324c
JF		 6142 ixgbe_update_xoff_received(adapter);
6143
6f11eef7 6144 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6145 switch (hw->mac.type) {
6146 case ixgbe_mac_82598EB:
6147 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6148 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6149 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6150 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6151 break;
b93a2226 6152 case ixgbe_mac_X540:
9a75a1ac
DS		 6153 case ixgbe_mac_X550:
6154 case ixgbe_mac_X550EM_x:
6155 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6156 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6157 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6158 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6159 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6160 case ixgbe_mac_82599EB:
a4d4f629
AD		 6161 for (i = 0; i < 16; i++)
6162 adapter->hw_rx_no_dma_resources +=
6163 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6164 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6165 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6166 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6167 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6168 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6169 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6170 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6171 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6172 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6173#ifdef IXGBE_FCOE
7ca647bd
JP		 6174 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6175 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6176 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6177 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6178 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6179 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6180 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6181 if (adapter->fcoe.ddp_pool) {
6182 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6183 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6184 unsigned int cpu;
6185 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6186 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6187 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6188 noddp += ddp_pool->noddp;
6189 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6190 }
5a1ee270
AD		 6191 hwstats->fcoe_noddp = noddp;
6192 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6193 }
6d45522c 6194#endif /* IXGBE_FCOE */
bd508178
AD		 6195 break;
6196 default:
6197 break;
e8e26350 6198 }
9a799d71 6199 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6200 hwstats->bprc += bprc;
6201 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6202 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6203 hwstats->mprc -= bprc;
6204 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6205 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6206 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6207 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6208 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6209 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6210 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6211 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6212 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6213 hwstats->lxontxc += lxon;
6f11eef7 6214 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6215 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6216 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6217 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6218 /*
6219 * 82598 errata - tx of flow control packets is included in tx counters
6220 */
6221 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6222 hwstats->gptc -= xon_off_tot;
6223 hwstats->mptc -= xon_off_tot;
6224 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6225 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6226 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6227 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6228 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6229 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6230 hwstats->ptc64 -= xon_off_tot;
6231 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6232 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6233 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6234 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6235 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6236 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6237
6238 /* Fill out the OS statistics structure */
7ca647bd 6239 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6240
6241 /* Rx Errors */
7ca647bd 6242 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6243 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6244 netdev->stats.rx_length_errors = hwstats->rlec;
6245 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6246 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6247}
6248
6249/**
d034acf1 6250 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6251 * @adapter: pointer to the device adapter structure
9a799d71 6252 **/
d034acf1 6253static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6254{
cf8280ee 6255 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6256 int i;
cf8280ee 6257
d034acf1
AD		 6258 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6259 return;
6260
6261 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6262
d034acf1 6263 /* if interface is down do nothing */
fe49f04a 6264 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6265 return;
6266
6267 /* do nothing if we are not using signature filters */
6268 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6269 return;
6270
6271 adapter->fdir_overflow++;
6272
93c52dd0
AD		 6273 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6274 for (i = 0; i < adapter->num_tx_queues; i++)
6275 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6276 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6277 /* re-enable flow director interrupts */
6278 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6279 } else {
6280 e_err(probe, "failed to finish FDIR re-initialization, "
6281 "ignored adding FDIR ATR filters\n");
6282 }
93c52dd0
AD		 6283}
6284
6285/**
6286 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6287 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6288 *
6289 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6290 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6291 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6292 * determine if a hang has occurred.
93c52dd0
AD		 6293 */
6294static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6295{
cf8280ee 6296 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6297 u64 eics = 0;
6298 int i;
cf8280ee 6299
09f40aed 6300 /* If we're down, removing or resetting, just bail */
93c52dd0 6301 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6302 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6303 test_bit(__IXGBE_RESETTING, &adapter->state))
6304 return;
22d5a71b 6305
93c52dd0
AD		 6306 /* Force detection of hung controller */
6307 if (netif_carrier_ok(adapter->netdev)) {
6308 for (i = 0; i < adapter->num_tx_queues; i++)
6309 set_check_for_tx_hang(adapter->tx_ring[i]);
6310 }
22d5a71b 6311
fe49f04a
AD		 6312 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6313 /*
6314 * for legacy and MSI interrupts don't set any bits
6315 * that are enabled for EIAM, because this operation
6316 * would set *both* EIMS and EICS for any bit in EIAM
6317 */
6318 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6319 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6320 } else {
6321 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6322 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6323 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6324 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6325 eics |= ((u64)1 << i);
6326 }
cf8280ee 6327 }
9a799d71 6328
93c52dd0 6329 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6330 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6331}
6332
e8e26350 6333/**
93c52dd0 6334 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6335 * @adapter: pointer to the device adapter structure
6336 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6337 **/
93c52dd0 6338static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6339{
e8e26350 6340 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6341 u32 link_speed = adapter->link_speed;
6342 bool link_up = adapter->link_up;
041441d0 6343 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6344
93c52dd0
AD		 6345 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6346 return;
6347
6348 if (hw->mac.ops.check_link) {
6349 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6350 } else {
93c52dd0
AD		 6351 /* always assume link is up, if no check link function */
6352 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6353 link_up = true;
c4cf55e5 6354 }
041441d0
AD		 6355
6356 if (adapter->ixgbe_ieee_pfc)
6357 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6358
3ebe8fde 6359 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6360 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6361 ixgbe_set_rx_drop_en(adapter);
6362 }
93c52dd0
AD		 6363
6364 if (link_up ||
6365 time_after(jiffies, (adapter->link_check_timeout +
6366 IXGBE_TRY_LINK_TIMEOUT))) {
6367 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6368 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6369 IXGBE_WRITE_FLUSH(hw);
6370 }
6371
6372 adapter->link_up = link_up;
6373 adapter->link_speed = link_speed;
e8e26350
PW		 6374}
6375
107d3018
AD		 6376static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6377{
6378#ifdef CONFIG_IXGBE_DCB
6379 struct net_device *netdev = adapter->netdev;
6380 struct dcb_app app = {
6381 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6382 .protocol = 0,
6383 };
6384 u8 up = 0;
6385
6386 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6387 up = dcb_ieee_getapp_mask(netdev, &app);
6388
6389 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6390#endif
6391}
6392
e8e26350 6393/**
93c52dd0
AD		 6394 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6395 * print link up message
49ce9c2c 6396 * @adapter: pointer to the device adapter structure
e8e26350 6397 **/
93c52dd0 6398static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6399{
93c52dd0 6400 struct net_device *netdev = adapter->netdev;
e8e26350 6401 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6402 struct net_device *upper;
6403 struct list_head *iter;
93c52dd0 6404 u32 link_speed = adapter->link_speed;
454adb00 6405 const char *speed_str;
93c52dd0 6406 bool flow_rx, flow_tx;
e8e26350 6407
93c52dd0
AD		 6408 /* only continue if link was previously down */
6409 if (netif_carrier_ok(netdev))
a985b6c3 6410 return;
63d6e1d8 6411
93c52dd0 6412 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6413
93c52dd0
AD		 6414 switch (hw->mac.type) {
6415 case ixgbe_mac_82598EB: {
6416 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6417 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6418 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6419 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6420 }
6421 break;
6422 case ixgbe_mac_X540:
9a75a1ac
DS		 6423 case ixgbe_mac_X550:
6424 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6425 case ixgbe_mac_82599EB: {
6426 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6427 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6428 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6429 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6430 }
6431 break;
6432 default:
6433 flow_tx = false;
6434 flow_rx = false;
6435 break;
e8e26350 6436 }
3a6a4eda 6437
6cb562d6
JK		 6438 adapter->last_rx_ptp_check = jiffies;
6439
8fecf67c 6440 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6441 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6442
454adb00
MR		 6443 switch (link_speed) {
6444 case IXGBE_LINK_SPEED_10GB_FULL:
6445 speed_str = "10 Gbps";
6446 break;
6447 case IXGBE_LINK_SPEED_2_5GB_FULL:
6448 speed_str = "2.5 Gbps";
6449 break;
6450 case IXGBE_LINK_SPEED_1GB_FULL:
6451 speed_str = "1 Gbps";
6452 break;
6453 case IXGBE_LINK_SPEED_100_FULL:
6454 speed_str = "100 Mbps";
6455 break;
6456 default:
6457 speed_str = "unknown speed";
6458 break;
6459 }
6460 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6461 ((flow_rx && flow_tx) ? "RX/TX" :
6462 (flow_rx ? "RX" :
6463 (flow_tx ? "TX" : "None"))));
e8e26350 6464
93c52dd0 6465 netif_carrier_on(netdev);
93c52dd0 6466 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6467
cdc04dcc
ET		 6468 /* enable transmits */
6469 netif_tx_wake_all_queues(adapter->netdev);
6470
6471 /* enable any upper devices */
6472 rtnl_lock();
6473 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6474 if (netif_is_macvlan(upper)) {
6475 struct macvlan_dev *vlan = netdev_priv(upper);
6476
6477 if (vlan->fwd_priv)
6478 netif_tx_wake_all_queues(upper);
6479 }
6480 }
6481 rtnl_unlock();
6482
107d3018
AD		 6483 /* update the default user priority for VFs */
6484 ixgbe_update_default_up(adapter);
6485
befa2af7
AD		 6486 /* ping all the active vfs to let them know link has changed */
6487 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6488}
6489
c4cf55e5 6490/**
93c52dd0
AD		 6491 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6492 * print link down message
49ce9c2c 6493 * @adapter: pointer to the adapter structure
c4cf55e5 6494 **/
581330ba 6495static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6496{
cf8280ee 6497 struct net_device *netdev = adapter->netdev;
c4cf55e5 6498 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6499
93c52dd0
AD		 6500 adapter->link_up = false;
6501 adapter->link_speed = 0;
cf8280ee 6502
93c52dd0
AD		 6503 /* only continue if link was up previously */
6504 if (!netif_carrier_ok(netdev))
6505 return;
264857b8 6506
93c52dd0
AD		 6507 /* poll for SFP+ cable when link is down */
6508 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6509 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6510
8fecf67c 6511 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6512 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6513
93c52dd0
AD		 6514 e_info(drv, "NIC Link is Down\n");
6515 netif_carrier_off(netdev);
befa2af7
AD		 6516
6517 /* ping all the active vfs to let them know link has changed */
6518 ixgbe_ping_all_vfs(adapter);
93c52dd0 6519}
e8e26350 6520
07923c17
ET		 6521static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6522{
6523 int i;
6524
6525 for (i = 0; i < adapter->num_tx_queues; i++) {
6526 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6527
6528 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6529 return true;
6530 }
6531
6532 return false;
6533}
6534
6535static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6536{
6537 struct ixgbe_hw *hw = &adapter->hw;
6538 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6539 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6540
6541 int i, j;
6542
6543 if (!adapter->num_vfs)
6544 return false;
6545
9a75a1ac
DS		 6546 /* resetting the PF is only needed for MAC before X550 */
6547 if (hw->mac.type >= ixgbe_mac_X550)
6548 return false;
6549
07923c17
ET		 6550 for (i = 0; i < adapter->num_vfs; i++) {
6551 for (j = 0; j < q_per_pool; j++) {
6552 u32 h, t;
6553
6554 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6555 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6556
6557 if (h != t)
6558 return true;
6559 }
6560 }
6561
6562 return false;
6563}
6564
93c52dd0
AD		 6565/**
6566 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6567 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6568 **/
6569static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6570{
93c52dd0 6571 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6572 if (ixgbe_ring_tx_pending(adapter) ||
6573 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6574 /* We've lost link, so the controller stops DMA,
6575 * but we've got queued Tx work that's never going
6576 * to get done, so reset controller to flush Tx.
6577 * (Do the reset outside of interrupt context).
6578 */
12ff3f3b 6579 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6580 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6581 }
c4cf55e5 6582 }
c4cf55e5
PWJ		 6583}
6584
9079e416
ET		 6585#ifdef CONFIG_PCI_IOV
6586static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6587 struct pci_dev *vfdev)
6588{
6589 if (!pci_wait_for_pending_transaction(vfdev))
6590 e_dev_warn("Issuing VFLR with pending transactions\n");
6591
6592 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6593 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6594
6595 msleep(100);
6596}
6597
6598static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6599{
6600 struct ixgbe_hw *hw = &adapter->hw;
6601 struct pci_dev *pdev = adapter->pdev;
6602 struct pci_dev *vfdev;
6603 u32 gpc;
6604 int pos;
6605 unsigned short vf_id;
6606
6607 if (!(netif_carrier_ok(adapter->netdev)))
6608 return;
6609
6610 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6611 if (gpc) /* If incrementing then no need for the check below */
6612 return;
6613 /* Check to see if a bad DMA write target from an errant or
6614 * malicious VF has caused a PCIe error. If so then we can
6615 * issue a VFLR to the offending VF(s) and then resume without
6616 * requesting a full slot reset.
6617 */
6618
6619 if (!pdev)
6620 return;
6621
6622 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6623 if (!pos)
6624 return;
6625
6626 /* get the device ID for the VF */
6627 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6628
6629 /* check status reg for all VFs owned by this PF */
6630 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6631 while (vfdev) {
6632 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6633 u16 status_reg;
6634
6635 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6636 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6637 /* issue VFLR */
6638 ixgbe_issue_vf_flr(adapter, vfdev);
6639 }
6640
6641 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6642 }
6643}
6644
a985b6c3
GR		 6645static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6646{
6647 u32 ssvpc;
6648
0584d999
GR		 6649 /* Do not perform spoof check for 82598 or if not in IOV mode */
6650 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6651 adapter->num_vfs == 0)
a985b6c3
GR		 6652 return;
6653
6654 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6655
6656 /*
6657 * ssvpc register is cleared on read, if zero then no
6658 * spoofed packets in the last interval.
6659 */
6660 if (!ssvpc)
6661 return;
6662
d6ea0754 6663 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6664}
9079e416
ET		 6665#else
6666static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6667{
6668}
6669
6670static void
6671ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6672{
6673}
6674#endif /* CONFIG_PCI_IOV */
6675
a985b6c3 6676
93c52dd0
AD		 6677/**
6678 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6679 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6680 **/
6681static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6682{
09f40aed 6683 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6684 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6685 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6686 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6687 return;
6688
6689 ixgbe_watchdog_update_link(adapter);
6690
6691 if (adapter->link_up)
6692 ixgbe_watchdog_link_is_up(adapter);
6693 else
6694 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6695
9079e416 6696 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6697 ixgbe_spoof_check(adapter);
9a799d71 6698 ixgbe_update_stats(adapter);
93c52dd0
AD		 6699
6700 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6701}
10eec955 6702
cf8280ee 6703/**
7086400d 6704 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6705 * @adapter: the ixgbe adapter structure
cf8280ee 6706 **/
7086400d 6707static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6708{
cf8280ee 6709 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6710 s32 err;
cf8280ee 6711
7086400d
AD		 6712 /* not searching for SFP so there is nothing to do here */
6713 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6714 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6715 return;
10eec955 6716
58e7cd24
MR		 6717 if (adapter->sfp_poll_time &&
6718 time_after(adapter->sfp_poll_time, jiffies))
6719 return; /* If not yet time to poll for SFP */
6720
7086400d
AD		 6721 /* someone else is in init, wait until next service event */
6722 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6723 return;
cf8280ee 6724
58e7cd24
MR		 6725 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6726
7086400d
AD		 6727 err = hw->phy.ops.identify_sfp(hw);
6728 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6729 goto sfp_out;
264857b8 6730
7086400d
AD		 6731 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6732 /* If no cable is present, then we need to reset
6733 * the next time we find a good cable. */
6734 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6735 }
9a799d71 6736
7086400d
AD		 6737 /* exit on error */
6738 if (err)
6739 goto sfp_out;
e8e26350 6740
7086400d
AD		 6741 /* exit if reset not needed */
6742 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6743 goto sfp_out;
9a799d71 6744
7086400d 6745 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6746
7086400d
AD		 6747 /*
6748 * A module may be identified correctly, but the EEPROM may not have
6749 * support for that module. setup_sfp() will fail in that case, so
6750 * we should not allow that module to load.
6751 */
6752 if (hw->mac.type == ixgbe_mac_82598EB)
6753 err = hw->phy.ops.reset(hw);
6754 else
6755 err = hw->mac.ops.setup_sfp(hw);
6756
6757 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6758 goto sfp_out;
6759
6760 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6761 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6762
6763sfp_out:
6764 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6765
6766 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6767 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6768 e_dev_err("failed to initialize because an unsupported "
6769 "SFP+ module type was detected.\n");
6770 e_dev_err("Reload the driver after installing a "
6771 "supported module.\n");
6772 unregister_netdev(adapter->netdev);
bc59fcda 6773 }
7086400d 6774}
bc59fcda 6775
7086400d
AD		 6776/**
6777 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6778 * @adapter: the ixgbe adapter structure
7086400d
AD		 6779 **/
6780static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6781{
6782 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6783 u32 speed;
6784 bool autoneg = false;
7086400d
AD		 6785
6786 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6787 return;
6788
6789 /* someone else is in init, wait until next service event */
6790 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6791 return;
6792
6793 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6794
3d292265 6795 speed = hw->phy.autoneg_advertised;
ed33ff66 6796 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6797 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6798
6799 /* setup the highest link when no autoneg */
6800 if (!autoneg) {
6801 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6802 speed = IXGBE_LINK_SPEED_10GB_FULL;
6803 }
6804 }
6805
7086400d 6806 if (hw->mac.ops.setup_link)
fd0326f2 6807 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6808
6809 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6810 adapter->link_check_timeout = jiffies;
6811 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6812}
6813
6814/**
6815 * ixgbe_service_timer - Timer Call-back
6816 * @data: pointer to adapter cast into an unsigned long
6817 **/
6818static void ixgbe_service_timer(unsigned long data)
6819{
6820 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6821 unsigned long next_event_offset;
6822
6bb78cfb
AD		 6823 /* poll faster when waiting for link */
6824 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6825 next_event_offset = HZ / 10;
6826 else
6827 next_event_offset = HZ * 2;
83c61fa9 6828
7086400d
AD		 6829 /* Reset the timer */
6830 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6831
9079e416 6832 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6833}
6834
597f22d6
DS		 6835static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6836{
6837 struct ixgbe_hw *hw = &adapter->hw;
6838 u32 status;
6839
6840 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6841 return;
6842
6843 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6844
6845 if (!hw->phy.ops.handle_lasi)
6846 return;
6847
6848 status = hw->phy.ops.handle_lasi(&adapter->hw);
6849 if (status != IXGBE_ERR_OVERTEMP)
6850 return;
6851
6852 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6853}
6854
c83c6cbd
AD		 6855static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6856{
6857 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6858 return;
6859
6860 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6861
09f40aed 6862 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6863 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6864 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6865 test_bit(__IXGBE_RESETTING, &adapter->state))
6866 return;
6867
6868 ixgbe_dump(adapter);
6869 netdev_err(adapter->netdev, "Reset adapter\n");
6870 adapter->tx_timeout_count++;
6871
8f4c5c9f 6872 rtnl_lock();
c83c6cbd 6873 ixgbe_reinit_locked(adapter);
8f4c5c9f 6874 rtnl_unlock();
c83c6cbd
AD		 6875}
6876
7086400d
AD		 6877/**
6878 * ixgbe_service_task - manages and runs subtasks
6879 * @work: pointer to work_struct containing our data
6880 **/
6881static void ixgbe_service_task(struct work_struct *work)
6882{
6883 struct ixgbe_adapter *adapter = container_of(work,
6884 struct ixgbe_adapter,
6885 service_task);
b0483c8f
MR		 6886 if (ixgbe_removed(adapter->hw.hw_addr)) {
6887 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6888 rtnl_lock();
6889 ixgbe_down(adapter);
6890 rtnl_unlock();
6891 }
6892 ixgbe_service_event_complete(adapter);
6893 return;
6894 }
67359c3c
MR		 6895#ifdef CONFIG_IXGBE_VXLAN
6896 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6897 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6898 vxlan_get_rx_port(adapter->netdev);
6899 }
6900#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 6901 ixgbe_reset_subtask(adapter);
597f22d6 6902 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 6903 ixgbe_sfp_detection_subtask(adapter);
6904 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6905 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6906 ixgbe_watchdog_subtask(adapter);
d034acf1 6907 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6908 ixgbe_check_hang_subtask(adapter);
891dc082 6909
8fecf67c 6910 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6911 ixgbe_ptp_overflow_check(adapter);
6912 ixgbe_ptp_rx_hang(adapter);
6913 }
7086400d
AD		 6914
6915 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6916}
6917
fd0db0ed
AD		 6918static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6919 struct ixgbe_tx_buffer *first,
244e27ad 6920 u8 *hdr_len)
897ab156 6921{
fd0db0ed 6922 struct sk_buff *skb = first->skb;
897ab156
AD		 6923 u32 vlan_macip_lens, type_tucmd;
6924 u32 mss_l4len_idx, l4len;
2049e1f6 6925 int err;
9a799d71 6926
8f4fbb9b
AD		 6927 if (skb->ip_summed != CHECKSUM_PARTIAL)
6928 return 0;
6929
897ab156
AD		 6930 if (!skb_is_gso(skb))
6931 return 0;
9a799d71 6932
2049e1f6
FR		 6933 err = skb_cow_head(skb, 0);
6934 if (err < 0)
6935 return err;
9a799d71 6936
897ab156
AD		 6937 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6938 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6939
a1108ffd 6940 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6941 struct iphdr *iph = ip_hdr(skb);
6942 iph->tot_len = 0;
6943 iph->check = 0;
6944 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6945 iph->daddr, 0,
6946 IPPROTO_TCP,
6947 0);
6948 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6949 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6950 IXGBE_TX_FLAGS_CSUM |
6951 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6952 } else if (skb_is_gso_v6(skb)) {
6953 ipv6_hdr(skb)->payload_len = 0;
6954 tcp_hdr(skb)->check =
6955 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6956 &ipv6_hdr(skb)->daddr,
6957 0, IPPROTO_TCP, 0);
244e27ad
AD		 6958 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6959 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6960 }
6961
091a6246 6962 /* compute header lengths */
897ab156
AD		 6963 l4len = tcp_hdrlen(skb);
6964 *hdr_len = skb_transport_offset(skb) + l4len;
6965
091a6246
AD		 6966 /* update gso size and bytecount with header size */
6967 first->gso_segs = skb_shinfo(skb)->gso_segs;
6968 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6969
c44f5f51 6970 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6971 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6972 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6973
6974 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6975 vlan_macip_lens = skb_network_header_len(skb);
6976 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6977 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6978
6979 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6980 mss_l4len_idx);
897ab156
AD		 6981
6982 return 1;
6983}
6984
244e27ad
AD		 6985static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6986 struct ixgbe_tx_buffer *first)
7ca647bd 6987{
fd0db0ed 6988 struct sk_buff *skb = first->skb;
897ab156
AD		 6989 u32 vlan_macip_lens = 0;
6990 u32 mss_l4len_idx = 0;
6991 u32 type_tucmd = 0;
7ca647bd 6992
897ab156 6993 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6994 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6995 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6996 return;
f467bc06
MR		 6997 vlan_macip_lens = skb_network_offset(skb) <<
6998 IXGBE_ADVTXD_MACLEN_SHIFT;
897ab156
AD		 6999 } else {
7000 u8 l4_hdr = 0;
f467bc06
MR		 7001 union {
7002 struct iphdr *ipv4;
7003 struct ipv6hdr *ipv6;
7004 u8 *raw;
7005 } network_hdr;
7006 union {
7007 struct tcphdr *tcphdr;
7008 u8 *raw;
7009 } transport_hdr;
7010
7011 if (skb->encapsulation) {
7012 network_hdr.raw = skb_inner_network_header(skb);
7013 transport_hdr.raw = skb_inner_transport_header(skb);
7014 vlan_macip_lens = skb_inner_network_offset(skb) <<
7015 IXGBE_ADVTXD_MACLEN_SHIFT;
7016 } else {
7017 network_hdr.raw = skb_network_header(skb);
7018 transport_hdr.raw = skb_transport_header(skb);
7019 vlan_macip_lens = skb_network_offset(skb) <<
7020 IXGBE_ADVTXD_MACLEN_SHIFT;
7021 }
7022
7023 /* use first 4 bits to determine IP version */
7024 switch (network_hdr.ipv4->version) {
7025 case IPVERSION:
7026 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
897ab156 7027 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
f467bc06 7028 l4_hdr = network_hdr.ipv4->protocol;
7ca647bd 7029 break;
f467bc06
MR		 7030 case 6:
7031 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7032 l4_hdr = network_hdr.ipv6->nexthdr;
897ab156
AD		 7033 break;
7034 default:
7035 if (unlikely(net_ratelimit())) {
7036 dev_warn(tx_ring->dev,
f467bc06
MR		 7037 "partial checksum but version=%d\n",
7038 network_hdr.ipv4->version);
897ab156 7039 }
7ca647bd 7040 }
897ab156
AD		 7041
7042 switch (l4_hdr) {
7ca647bd 7043 case IPPROTO_TCP:
897ab156 7044 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
f467bc06 7045 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
897ab156 7046 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 7047 break;
7048 case IPPROTO_SCTP:
897ab156
AD		 7049 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7050 mss_l4len_idx = sizeof(struct sctphdr) <<
7051 IXGBE_ADVTXD_L4LEN_SHIFT;
7052 break;
7053 case IPPROTO_UDP:
7054 mss_l4len_idx = sizeof(struct udphdr) <<
7055 IXGBE_ADVTXD_L4LEN_SHIFT;
7056 break;
7057 default:
7058 if (unlikely(net_ratelimit())) {
7059 dev_warn(tx_ring->dev,
7060 "partial checksum but l4 proto=%x!\n",
244e27ad 7061 l4_hdr);
897ab156 7062 }
7ca647bd
JP		 7063 break;
7064 }
244e27ad
AD		 7065
7066 /* update TX checksum flag */
7067 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 7068 }
7069
244e27ad 7070 /* vlan_macip_lens: MACLEN, VLAN tag */
244e27ad 7071 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7072
897ab156
AD		 7073 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7074 type_tucmd, mss_l4len_idx);
9a799d71
AK		 7075}
7076
472148c3
AD		 7077#define IXGBE_SET_FLAG(_input, _flag, _result) \
7078 ((_flag <= _result) ? \
7079 ((u32)(_input & _flag) * (_result / _flag)) : \
7080 ((u32)(_input & _flag) / (_flag / _result)))
7081
7082static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7083{
d3d00239 7084 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7085 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7086 IXGBE_ADVTXD_DCMD_DEXT |
7087 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7088
d3d00239 7089 /* set HW vlan bit if vlan is present */
472148c3
AD		 7090 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7091 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7092
d3d00239 7093 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7094 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7095 IXGBE_ADVTXD_DCMD_TSE);
7096
7097 /* set timestamp bit if present */
7098 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7099 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7100
62748b7b 7101 /* insert frame checksum */
472148c3 7102 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7103
d3d00239
AD		 7104 return cmd_type;
7105}
9a799d71 7106
729739b7
AD		 7107static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7108 u32 tx_flags, unsigned int paylen)
d3d00239 7109{
472148c3 7110 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7111
d3d00239 7112 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7113 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7114 IXGBE_TX_FLAGS_CSUM,
7115 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7116
93f5b3c1 7117 /* enble IPv4 checksum for TSO */
472148c3
AD		 7118 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7119 IXGBE_TX_FLAGS_IPV4,
7120 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7121
7f9643fd
AD		 7122 /*
7123 * Check Context must be set if Tx switch is enabled, which it
7124 * always is for case where virtual functions are running
7125 */
472148c3
AD		 7126 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7127 IXGBE_TX_FLAGS_CC,
7128 IXGBE_ADVTXD_CC);
7f9643fd 7129
472148c3 7130 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7131}
44df32c5 7132
2367a173
DB		 7133static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7134{
7135 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7136
7137 /* Herbert's original patch had:
7138 * smp_mb__after_netif_stop_queue();
7139 * but since that doesn't exist yet, just open code it.
7140 */
7141 smp_mb();
7142
7143 /* We need to check again in a case another CPU has just
7144 * made room available.
7145 */
7146 if (likely(ixgbe_desc_unused(tx_ring) < size))
7147 return -EBUSY;
7148
7149 /* A reprieve! - use start_queue because it doesn't call schedule */
7150 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7151 ++tx_ring->tx_stats.restart_queue;
7152 return 0;
7153}
7154
7155static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7156{
7157 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7158 return 0;
7159
7160 return __ixgbe_maybe_stop_tx(tx_ring, size);
7161}
7162
d3d00239
AD		 7163#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7164 IXGBE_TXD_CMD_RS)
7165
7166static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7167 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7168 const u8 hdr_len)
7169{
fd0db0ed 7170 struct sk_buff *skb = first->skb;
729739b7 7171 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7172 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7173 struct skb_frag_struct *frag;
7174 dma_addr_t dma;
7175 unsigned int data_len, size;
244e27ad 7176 u32 tx_flags = first->tx_flags;
472148c3 7177 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7178 u16 i = tx_ring->next_to_use;
d3d00239 7179
729739b7
AD		 7180 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7181
ec718254
AD		 7182 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7183
7184 size = skb_headlen(skb);
7185 data_len = skb->data_len;
729739b7 7186
d3d00239
AD		 7187#ifdef IXGBE_FCOE
7188 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7189 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7190 size -= sizeof(struct fcoe_crc_eof) - data_len;
7191 data_len = 0;
729739b7
AD		 7192 } else {
7193 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7194 }
7195 }
44df32c5 7196
d3d00239 7197#endif
729739b7 7198 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7199
ec718254 7200 tx_buffer = first;
9a799d71 7201
ec718254
AD		 7202 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7203 if (dma_mapping_error(tx_ring->dev, dma))
7204 goto dma_error;
7205
7206 /* record length, and DMA address */
7207 dma_unmap_len_set(tx_buffer, len, size);
7208 dma_unmap_addr_set(tx_buffer, dma, dma);
7209
7210 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7211
729739b7 7212 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7213 tx_desc->read.cmd_type_len =
472148c3 7214 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7215
d3d00239 7216 i++;
729739b7 7217 tx_desc++;
d3d00239 7218 if (i == tx_ring->count) {
e4f74028 7219 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7220 i = 0;
7221 }
ec718254 7222 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7223
7224 dma += IXGBE_MAX_DATA_PER_TXD;
7225 size -= IXGBE_MAX_DATA_PER_TXD;
7226
7227 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7228 }
e5a43549 7229
729739b7
AD		 7230 if (likely(!data_len))
7231 break;
9a799d71 7232
472148c3 7233 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7234
729739b7
AD		 7235 i++;
7236 tx_desc++;
7237 if (i == tx_ring->count) {
7238 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7239 i = 0;
7240 }
ec718254 7241 tx_desc->read.olinfo_status = 0;
9a799d71 7242
d3d00239 7243#ifdef IXGBE_FCOE
9e903e08 7244 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7245#else
9e903e08 7246 size = skb_frag_size(frag);
d3d00239
AD		 7247#endif
7248 data_len -= size;
9a799d71 7249
729739b7
AD		 7250 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7251 DMA_TO_DEVICE);
9a799d71 7252
729739b7 7253 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7254 }
9a799d71 7255
729739b7 7256 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7257 cmd_type |= size | IXGBE_TXD_CMD;
7258 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7259
091a6246 7260 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7261
d3d00239
AD		 7262 /* set the timestamp */
7263 first->time_stamp = jiffies;
9a799d71
AK		 7264
7265 /*
729739b7
AD		 7266 * Force memory writes to complete before letting h/w know there
7267 * are new descriptors to fetch. (Only applicable for weak-ordered
7268 * memory model archs, such as IA-64).
7269 *
7270 * We also need this memory barrier to make certain all of the
7271 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7272 */
7273 wmb();
7274
d3d00239
AD		 7275 /* set next_to_watch value indicating a packet is present */
7276 first->next_to_watch = tx_desc;
7277
729739b7
AD		 7278 i++;
7279 if (i == tx_ring->count)
7280 i = 0;
7281
7282 tx_ring->next_to_use = i;
7283
2367a173
DB		 7284 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7285
7286 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7287 writel(i, tx_ring->tail);
7288
7289 /* we need this if more than one processor can write to our tail
7290 * at a time, it synchronizes IO on IA64/Altix systems
7291 */
7292 mmiowb();
9c938cdd 7293 }
2367a173 7294
d3d00239
AD		 7295 return;
7296dma_error:
729739b7 7297 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7298
7299 /* clear dma mappings for failed tx_buffer_info map */
7300 for (;;) {
729739b7
AD		 7301 tx_buffer = &tx_ring->tx_buffer_info[i];
7302 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7303 if (tx_buffer == first)
d3d00239
AD		 7304 break;
7305 if (i == 0)
7306 i = tx_ring->count;
7307 i--;
7308 }
7309
d3d00239 7310 tx_ring->next_to_use = i;
9a799d71
AK		 7311}
7312
fd0db0ed 7313static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7314 struct ixgbe_tx_buffer *first)
69830529
AD		 7315{
7316 struct ixgbe_q_vector *q_vector = ring->q_vector;
7317 union ixgbe_atr_hash_dword input = { .dword = 0 };
7318 union ixgbe_atr_hash_dword common = { .dword = 0 };
7319 union {
7320 unsigned char *network;
7321 struct iphdr *ipv4;
7322 struct ipv6hdr *ipv6;
7323 } hdr;
ee9e0f0b 7324 struct tcphdr *th;
67359c3c
MR		 7325 struct sk_buff *skb;
7326#ifdef CONFIG_IXGBE_VXLAN
7327 u8 encap = false;
7328#endif /* CONFIG_IXGBE_VXLAN */
905e4a41 7329 __be16 vlan_id;
c4cf55e5 7330
69830529
AD		 7331 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7332 if (!q_vector)
7333 return;
7334
7335 /* do nothing if sampling is disabled */
7336 if (!ring->atr_sample_rate)
d3ead241 7337 return;
c4cf55e5 7338
69830529 7339 ring->atr_count++;
c4cf55e5 7340
69830529 7341 /* snag network header to get L4 type and address */
67359c3c
MR		 7342 skb = first->skb;
7343 hdr.network = skb_network_header(skb);
7344 if (skb->encapsulation) {
7345#ifdef CONFIG_IXGBE_VXLAN
7346 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7347
67359c3c
MR		 7348 if (!adapter->vxlan_port)
7349 return;
7350 if (first->protocol != htons(ETH_P_IP) ||
7351 hdr.ipv4->version != IPVERSION ||
7352 hdr.ipv4->protocol != IPPROTO_UDP) {
7353 return;
7354 }
7355 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7356 return;
7357 encap = true;
7358 hdr.network = skb_inner_network_header(skb);
7359 th = inner_tcp_hdr(skb);
7360#else
69830529 7361 return;
67359c3c
MR		 7362#endif /* CONFIG_IXGBE_VXLAN */
7363 } else {
7364 /* Currently only IPv4/IPv6 with TCP is supported */
7365 if ((first->protocol != htons(ETH_P_IPV6) ||
7366 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7367 (first->protocol != htons(ETH_P_IP) ||
7368 hdr.ipv4->protocol != IPPROTO_TCP))
7369 return;
7370 th = tcp_hdr(skb);
7371 }
c4cf55e5 7372
66f32a8b
AD		 7373 /* skip this packet since it is invalid or the socket is closing */
7374 if (!th || th->fin)
69830529
AD		 7375 return;
7376
7377 /* sample on all syn packets or once every atr sample count */
7378 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7379 return;
7380
7381 /* reset sample count */
7382 ring->atr_count = 0;
7383
244e27ad 7384 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7385
7386 /*
7387 * src and dst are inverted, think how the receiver sees them
7388 *
7389 * The input is broken into two sections, a non-compressed section
7390 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7391 * is XORed together and stored in the compressed dword.
7392 */
7393 input.formatted.vlan_id = vlan_id;
7394
7395 /*
7396 * since src port and flex bytes occupy the same word XOR them together
7397 * and write the value to source port portion of compressed dword
7398 */
244e27ad 7399 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7400 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7401 else
244e27ad 7402 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7403 common.port.dst ^= th->source;
7404
a1108ffd 7405 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7406 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7407 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7408 } else {
7409 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7410 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7411 hdr.ipv6->saddr.s6_addr32[1] ^
7412 hdr.ipv6->saddr.s6_addr32[2] ^
7413 hdr.ipv6->saddr.s6_addr32[3] ^
7414 hdr.ipv6->daddr.s6_addr32[0] ^
7415 hdr.ipv6->daddr.s6_addr32[1] ^
7416 hdr.ipv6->daddr.s6_addr32[2] ^
7417 hdr.ipv6->daddr.s6_addr32[3];
7418 }
c4cf55e5 7419
67359c3c
MR		 7420#ifdef CONFIG_IXGBE_VXLAN
7421 if (encap)
7422 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7423#endif /* CONFIG_IXGBE_VXLAN */
7424
c4cf55e5 7425 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7426 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7427 input, common, ring->queue_index);
c4cf55e5
PWJ		 7428}
7429
f663dd9a 7430static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7431 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7432{
f663dd9a
JW		 7433 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7434#ifdef IXGBE_FCOE
97488bd1
AD		 7435 struct ixgbe_adapter *adapter;
7436 struct ixgbe_ring_feature *f;
7437 int txq;
f663dd9a
JW		 7438#endif
7439
7440 if (fwd_adapter)
7441 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7442
7443#ifdef IXGBE_FCOE
5e09a105 7444
97488bd1
AD		 7445 /*
7446 * only execute the code below if protocol is FCoE
7447 * or FIP and we have FCoE enabled on the adapter
7448 */
7449 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7450 case htons(ETH_P_FCOE):
7451 case htons(ETH_P_FIP):
97488bd1 7452 adapter = netdev_priv(dev);
c087663e 7453
97488bd1
AD		 7454 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7455 break;
7456 default:
99932d4f 7457 return fallback(dev, skb);
97488bd1 7458 }
c087663e 7459
97488bd1 7460 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7461
97488bd1
AD		 7462 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7463 smp_processor_id();
56075a98 7464
97488bd1
AD		 7465 while (txq >= f->indices)
7466 txq -= f->indices;
c4cf55e5 7467
97488bd1 7468 return txq + f->offset;
f663dd9a 7469#else
99932d4f 7470 return fallback(dev, skb);
f663dd9a 7471#endif
09a3b1f8
SH		 7472}
7473
fc77dc3c 7474netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7475 struct ixgbe_adapter *adapter,
7476 struct ixgbe_ring *tx_ring)
9a799d71 7477{
d3d00239 7478 struct ixgbe_tx_buffer *first;
5f715823 7479 int tso;
d3d00239 7480 u32 tx_flags = 0;
a535c30e 7481 unsigned short f;
a535c30e 7482 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7483 __be16 protocol = skb->protocol;
63544e9c 7484 u8 hdr_len = 0;
5e09a105 7485
a535c30e
AD		 7486 /*
7487 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7488 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7489 * + 2 desc gap to keep tail from touching head,
7490 * + 1 desc for context descriptor,
7491 * otherwise try next time
7492 */
a535c30e
AD		 7493 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7494 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7495
a535c30e
AD		 7496 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7497 tx_ring->tx_stats.tx_busy++;
7498 return NETDEV_TX_BUSY;
7499 }
7500
fd0db0ed
AD		 7501 /* record the location of the first descriptor for this packet */
7502 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7503 first->skb = skb;
091a6246
AD		 7504 first->bytecount = skb->len;
7505 first->gso_segs = 1;
fd0db0ed 7506
66f32a8b 7507 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7508 if (skb_vlan_tag_present(skb)) {
7509 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7510 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7511 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7512 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7513 struct vlan_hdr *vhdr, _vhdr;
7514 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7515 if (!vhdr)
7516 goto out_drop;
7517
9e0c5648
AD		 7518 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7519 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7520 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7521 }
0213668f 7522 protocol = vlan_get_protocol(skb);
66f32a8b 7523
d5234933
MR		 7524 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7525 adapter->ptp_clock &&
7526 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7527 &adapter->state)) {
3a6a4eda
JK		 7528 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7529 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7530
7531 /* schedule check for Tx timestamp */
7532 adapter->ptp_tx_skb = skb_get(skb);
7533 adapter->ptp_tx_start = jiffies;
7534 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7535 }
3a6a4eda 7536
ff29a86e
JK		 7537 skb_tx_timestamp(skb);
7538
9e0c5648
AD		 7539#ifdef CONFIG_PCI_IOV
7540 /*
7541 * Use the l2switch_enable flag - would be false if the DMA
7542 * Tx switch had been disabled.
7543 */
7544 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7545 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7546
7547#endif
32701dc2 7548 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7549 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7550 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7551 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7552 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7553 tx_flags |= (skb->priority & 0x7) <<
7554 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7555 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7556 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7557
7558 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7559 goto out_drop;
7560 vhdr = (struct vlan_ethhdr *)skb->data;
7561 vhdr->h_vlan_TCI = htons(tx_flags >>
7562 IXGBE_TX_FLAGS_VLAN_SHIFT);
7563 } else {
7564 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7565 }
9a799d71 7566 }
eacd73f7 7567
244e27ad
AD		 7568 /* record initial flags and protocol */
7569 first->tx_flags = tx_flags;
7570 first->protocol = protocol;
7571
eacd73f7 7572#ifdef IXGBE_FCOE
66f32a8b 7573 /* setup tx offload for FCoE */
a1108ffd 7574 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7575 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7576 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7577 if (tso < 0)
7578 goto out_drop;
9a799d71 7579
66f32a8b 7580 goto xmit_fcoe;
eacd73f7 7581 }
9a799d71 7582
66f32a8b 7583#endif /* IXGBE_FCOE */
244e27ad 7584 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7585 if (tso < 0)
897ab156 7586 goto out_drop;
244e27ad
AD		 7587 else if (!tso)
7588 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7589
7590 /* add the ATR filter if ATR is on */
7591 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7592 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7593
7594#ifdef IXGBE_FCOE
7595xmit_fcoe:
7596#endif /* IXGBE_FCOE */
244e27ad 7597 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7598
9a799d71 7599 return NETDEV_TX_OK;
897ab156
AD		 7600
7601out_drop:
fd0db0ed
AD		 7602 dev_kfree_skb_any(first->skb);
7603 first->skb = NULL;
7604
897ab156 7605 return NETDEV_TX_OK;
9a799d71
AK		 7606}
7607
2a47fa45
JF		 7608static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7609 struct net_device *netdev,
7610 struct ixgbe_ring *ring)
84418e3b
AD		 7611{
7612 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7613 struct ixgbe_ring *tx_ring;
7614
a50c29dd
AD		 7615 /*
7616 * The minimum packet size for olinfo paylen is 17 so pad the skb
7617 * in order to meet this minimum size requirement.
7618 */
a94d9e22
AD		 7619 if (skb_put_padto(skb, 17))
7620 return NETDEV_TX_OK;
a50c29dd 7621
2a47fa45
JF		 7622 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7623
fc77dc3c 7624 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7625}
7626
2a47fa45
JF		 7627static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7628 struct net_device *netdev)
7629{
7630 return __ixgbe_xmit_frame(skb, netdev, NULL);
7631}
7632
9a799d71
AK		 7633/**
7634 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7635 * @netdev: network interface device structure
7636 * @p: pointer to an address structure
7637 *
7638 * Returns 0 on success, negative on failure
7639 **/
7640static int ixgbe_set_mac(struct net_device *netdev, void *p)
7641{
7642 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7643 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7644 struct sockaddr *addr = p;
5d7daa35 7645 int ret;
9a799d71
AK		 7646
7647 if (!is_valid_ether_addr(addr->sa_data))
7648 return -EADDRNOTAVAIL;
7649
5d7daa35 7650 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7651 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7652 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7653
5d7daa35
JK		 7654 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7655 return ret > 0 ? 0 : ret;
9a799d71
AK		 7656}
7657
6b73e10d
BH		 7658static int
7659ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7660{
7661 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7662 struct ixgbe_hw *hw = &adapter->hw;
7663 u16 value;
7664 int rc;
7665
7666 if (prtad != hw->phy.mdio.prtad)
7667 return -EINVAL;
7668 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7669 if (!rc)
7670 rc = value;
7671 return rc;
7672}
7673
7674static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7675 u16 addr, u16 value)
7676{
7677 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7678 struct ixgbe_hw *hw = &adapter->hw;
7679
7680 if (prtad != hw->phy.mdio.prtad)
7681 return -EINVAL;
7682 return hw->phy.ops.write_reg(hw, addr, devad, value);
7683}
7684
7685static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7686{
7687 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7688
3a6a4eda 7689 switch (cmd) {
3a6a4eda 7690 case SIOCSHWTSTAMP:
93501d48
JK		 7691 return ixgbe_ptp_set_ts_config(adapter, req);
7692 case SIOCGHWTSTAMP:
7693 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7694 default:
7695 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7696 }
6b73e10d
BH		 7697}
7698
0365e6e4
PW		 7699/**
7700 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7701 * netdev->dev_addrs
0365e6e4
PW		 7702 * @netdev: network interface device structure
7703 *
7704 * Returns non-zero on failure
7705 **/
7706static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7707{
7708 int err = 0;
7709 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7710 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7711
7fa7c9dc 7712 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7713 rtnl_lock();
7fa7c9dc 7714 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7715 rtnl_unlock();
7fa7c9dc
AD		 7716
7717 /* update SAN MAC vmdq pool selection */
7718 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7719 }
7720 return err;
7721}
7722
7723/**
7724 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7725 * netdev->dev_addrs
0365e6e4
PW		 7726 * @netdev: network interface device structure
7727 *
7728 * Returns non-zero on failure
7729 **/
7730static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7731{
7732 int err = 0;
7733 struct ixgbe_adapter *adapter = netdev_priv(dev);
7734 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7735
7736 if (is_valid_ether_addr(mac->san_addr)) {
7737 rtnl_lock();
7738 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7739 rtnl_unlock();
7740 }
7741 return err;
7742}
7743
9a799d71
AK		 7744#ifdef CONFIG_NET_POLL_CONTROLLER
7745/*
7746 * Polling 'interrupt' - used by things like netconsole to send skbs
7747 * without having to re-enable interrupts. It's not called while
7748 * the interrupt routine is executing.
7749 */
7750static void ixgbe_netpoll(struct net_device *netdev)
7751{
7752 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7753 int i;
9a799d71 7754
1a647bd2
AD		 7755 /* if interface is down do nothing */
7756 if (test_bit(__IXGBE_DOWN, &adapter->state))
7757 return;
7758
856f606e
AD		 7759 /* loop through and schedule all active queues */
7760 for (i = 0; i < adapter->num_q_vectors; i++)
7761 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 7762}
9a799d71 7763
581330ba 7764#endif
de1036b1
ED		 7765static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7766 struct rtnl_link_stats64 *stats)
7767{
7768 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7769 int i;
7770
1a51502b 7771 rcu_read_lock();
de1036b1 7772 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7773 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7774 u64 bytes, packets;
7775 unsigned int start;
7776
1a51502b
ED		 7777 if (ring) {
7778 do {
57a7744e 7779 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7780 packets = ring->stats.packets;
7781 bytes = ring->stats.bytes;
57a7744e 7782 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7783 stats->rx_packets += packets;
7784 stats->rx_bytes += bytes;
7785 }
de1036b1 7786 }
1ac9ad13
ED		 7787
7788 for (i = 0; i < adapter->num_tx_queues; i++) {
7789 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7790 u64 bytes, packets;
7791 unsigned int start;
7792
7793 if (ring) {
7794 do {
57a7744e 7795 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7796 packets = ring->stats.packets;
7797 bytes = ring->stats.bytes;
57a7744e 7798 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7799 stats->tx_packets += packets;
7800 stats->tx_bytes += bytes;
7801 }
7802 }
1a51502b 7803 rcu_read_unlock();
de1036b1
ED		 7804 /* following stats updated by ixgbe_watchdog_task() */
7805 stats->multicast = netdev->stats.multicast;
7806 stats->rx_errors = netdev->stats.rx_errors;
7807 stats->rx_length_errors = netdev->stats.rx_length_errors;
7808 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7809 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7810 return stats;
7811}
7812
8af3c33f 7813#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7814/**
7815 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7816 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7817 * @tc: number of traffic classes currently enabled
7818 *
7819 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7820 * 802.1Q priority maps to a packet buffer that exists.
7821 */
7822static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7823{
7824 struct ixgbe_hw *hw = &adapter->hw;
7825 u32 reg, rsave;
7826 int i;
7827
7828 /* 82598 have a static priority to TC mapping that can not
7829 * be changed so no validation is needed.
7830 */
7831 if (hw->mac.type == ixgbe_mac_82598EB)
7832 return;
7833
7834 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7835 rsave = reg;
7836
7837 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7838 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7839
7840 /* If up2tc is out of bounds default to zero */
7841 if (up2tc > tc)
7842 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7843 }
7844
7845 if (reg != rsave)
7846 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7847
7848 return;
7849}
7850
02debdc9
AD		 7851/**
7852 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7853 * @adapter: Pointer to adapter struct
7854 *
7855 * Populate the netdev user priority to tc map
7856 */
7857static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7858{
7859 struct net_device *dev = adapter->netdev;
7860 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7861 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7862 u8 prio;
7863
7864 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7865 u8 tc = 0;
7866
7867 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7868 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7869 else if (ets)
7870 tc = ets->prio_tc[prio];
7871
7872 netdev_set_prio_tc_map(dev, prio, tc);
7873 }
7874}
7875
cca73c59 7876#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7877/**
7878 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7879 *
7880 * @netdev: net device to configure
7881 * @tc: number of traffic classes to enable
7882 */
7883int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7884{
8b1c0b24
JF		 7885 struct ixgbe_adapter *adapter = netdev_priv(dev);
7886 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7887 bool pools;
8b1c0b24 7888
8b1c0b24 7889 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 7890 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
7891 return -EINVAL;
7892
7893 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 7894 return -EINVAL;
7895
2a47fa45
JF		 7896 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7897 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7898 return -EBUSY;
7899
8b1c0b24 7900 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7901 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7902 * hardware is not flexible enough to do this dynamically.
7903 */
7904 if (netif_running(dev))
7905 ixgbe_close(dev);
7906 ixgbe_clear_interrupt_scheme(adapter);
7907
cca73c59 7908#ifdef CONFIG_IXGBE_DCB
e7589eab 7909 if (tc) {
8b1c0b24 7910 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7911 ixgbe_set_prio_tc_map(adapter);
7912
e7589eab 7913 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7914
943561d3
AD		 7915 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7916 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7917 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7918 }
e7589eab 7919 } else {
8b1c0b24 7920 netdev_reset_tc(dev);
02debdc9 7921
943561d3
AD		 7922 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7923 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7924
7925 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7926
7927 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7928 adapter->dcb_cfg.pfc_mode_enable = false;
7929 }
7930
8b1c0b24 7931 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7932
7933#endif /* CONFIG_IXGBE_DCB */
7934 ixgbe_init_interrupt_scheme(adapter);
7935
8b1c0b24 7936 if (netif_running(dev))
cca73c59 7937 return ixgbe_open(dev);
8b1c0b24
JF		 7938
7939 return 0;
7940}
de1036b1 7941
da36b647
GR		 7942#ifdef CONFIG_PCI_IOV
7943void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7944{
7945 struct net_device *netdev = adapter->netdev;
7946
7947 rtnl_lock();
da36b647 7948 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7949 rtnl_unlock();
7950}
7951
7952#endif
082757af
DS		 7953void ixgbe_do_reset(struct net_device *netdev)
7954{
7955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7956
7957 if (netif_running(netdev))
7958 ixgbe_reinit_locked(adapter);
7959 else
7960 ixgbe_reset(adapter);
7961}
7962
c8f44aff 7963static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7964 netdev_features_t features)
082757af
DS		 7965{
7966 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7967
082757af 7968 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7969 if (!(features & NETIF_F_RXCSUM))
7970 features &= ~NETIF_F_LRO;
082757af 7971
567d2de2
AD		 7972 /* Turn off LRO if not RSC capable */
7973 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7974 features &= ~NETIF_F_LRO;
8e2813f5 7975
567d2de2 7976 return features;
082757af
DS		 7977}
7978
c8f44aff 7979static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7980 netdev_features_t features)
082757af
DS		 7981{
7982 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7983 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7984 bool need_reset = false;
7985
082757af 7986 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7987 if (!(features & NETIF_F_LRO)) {
7988 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7989 need_reset = true;
567d2de2
AD		 7990 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7991 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7992 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7993 if (adapter->rx_itr_setting == 1 ||
7994 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7995 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7996 need_reset = true;
7997 } else if ((changed ^ features) & NETIF_F_LRO) {
7998 e_info(probe, "rx-usecs set too low, "
7999 "disabling RSC\n");
082757af
DS		 8000 }
8001 }
8002
8003 /*
8004 * Check if Flow Director n-tuple support was enabled or disabled. If
8005 * the state changed, we need to reset.
8006 */
39cb681b
AD		 8007 switch (features & NETIF_F_NTUPLE) {
8008 case NETIF_F_NTUPLE:
567d2de2 8009 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8010 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8011 need_reset = true;
8012
567d2de2
AD		 8013 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8014 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 8015 break;
8016 default:
8017 /* turn off perfect filters, enable ATR and reset */
8018 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8019 need_reset = true;
8020
8021 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8022
8023 /* We cannot enable ATR if SR-IOV is enabled */
8024 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8025 break;
8026
8027 /* We cannot enable ATR if we have 2 or more traffic classes */
8028 if (netdev_get_num_tc(netdev) > 1)
8029 break;
8030
8031 /* We cannot enable ATR if RSS is disabled */
8032 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8033 break;
8034
8035 /* A sample rate of 0 indicates ATR disabled */
8036 if (!adapter->atr_sample_rate)
8037 break;
8038
8039 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8040 break;
082757af
DS		 8041 }
8042
f646968f 8043 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 8044 ixgbe_vlan_strip_enable(adapter);
8045 else
8046 ixgbe_vlan_strip_disable(adapter);
8047
3f2d1c0f
BG		 8048 if (changed & NETIF_F_RXALL)
8049 need_reset = true;
8050
567d2de2 8051 netdev->features = features;
67359c3c
MR		 8052
8053#ifdef CONFIG_IXGBE_VXLAN
8054 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8055 if (features & NETIF_F_RXCSUM)
8056 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8057 else
8058 ixgbe_clear_vxlan_port(adapter);
8059 }
8060#endif /* CONFIG_IXGBE_VXLAN */
8061
082757af
DS		 8062 if (need_reset)
8063 ixgbe_do_reset(netdev);
8064
8065 return 0;
082757af
DS		 8066}
8067
67359c3c 8068#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8069/**
8070 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8071 * @dev: The port's netdev
8072 * @sa_family: Socket Family that VXLAN is notifiying us about
8073 * @port: New UDP port number that VXLAN started listening to
8074 **/
8075static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8076 __be16 port)
8077{
8078 struct ixgbe_adapter *adapter = netdev_priv(dev);
8079 struct ixgbe_hw *hw = &adapter->hw;
8080 u16 new_port = ntohs(port);
8081
67359c3c
MR		 8082 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8083 return;
8084
3f207800
DS		 8085 if (sa_family == AF_INET6)
8086 return;
8087
67359c3c 8088 if (adapter->vxlan_port == new_port)
3f207800 8089 return;
3f207800
DS		 8090
8091 if (adapter->vxlan_port) {
8092 netdev_info(dev,
67359c3c 8093 "Hit Max num of VXLAN ports, not adding port %d\n",
3f207800
DS		 8094 new_port);
8095 return;
8096 }
8097
8098 adapter->vxlan_port = new_port;
8099 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8100}
8101
8102/**
8103 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8104 * @dev: The port's netdev
8105 * @sa_family: Socket Family that VXLAN is notifying us about
8106 * @port: UDP port number that VXLAN stopped listening to
8107 **/
8108static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8109 __be16 port)
8110{
8111 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800
DS		 8112 u16 new_port = ntohs(port);
8113
67359c3c
MR		 8114 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8115 return;
8116
3f207800
DS		 8117 if (sa_family == AF_INET6)
8118 return;
8119
8120 if (adapter->vxlan_port != new_port) {
8121 netdev_info(dev, "Port %d was not found, not deleting\n",
8122 new_port);
8123 return;
8124 }
8125
67359c3c
MR		 8126 ixgbe_clear_vxlan_port(adapter);
8127 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8128}
67359c3c 8129#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8130
edc7d573 8131static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8132 struct net_device *dev,
f6f6424b 8133 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8134 u16 flags)
8135{
bcfd3432 8136 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8137 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 8138 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
8139 return -ENOMEM;
0f4b0add
JF		 8140 }
8141
f6f6424b 8142 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8143}
8144
219efe97
DS		 8145/**
8146 * ixgbe_configure_bridge_mode - set various bridge modes
8147 * @adapter - the private structure
8148 * @mode - requested bridge mode
8149 *
8150 * Configure some settings require for various bridge modes.
8151 **/
8152static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8153 __u16 mode)
8154{
6d4c96ad
DS		 8155 struct ixgbe_hw *hw = &adapter->hw;
8156 unsigned int p, num_pools;
8157 u32 vmdctl;
8158
219efe97
DS		 8159 switch (mode) {
8160 case BRIDGE_MODE_VEPA:
6d4c96ad 8161 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8162 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8163
8164 /* must enable Rx switching replication to allow multicast
8165 * packet reception on all VFs, and to enable source address
8166 * pruning.
8167 */
8168 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8169 vmdctl |= IXGBE_VT_CTL_REPLEN;
8170 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8171
8172 /* enable Rx source address pruning. Note, this requires
8173 * replication to be enabled or else it does nothing.
8174 */
8175 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8176 for (p = 0; p < num_pools; p++) {
8177 if (hw->mac.ops.set_source_address_pruning)
8178 hw->mac.ops.set_source_address_pruning(hw,
8179 true,
8180 p);
8181 }
219efe97
DS		 8182 break;
8183 case BRIDGE_MODE_VEB:
6d4c96ad 8184 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8185 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8186 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8187
8188 /* disable Rx switching replication unless we have SR-IOV
8189 * virtual functions
8190 */
8191 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8192 if (!adapter->num_vfs)
8193 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8194 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8195
8196 /* disable Rx source address pruning, since we don't expect to
8197 * be receiving external loopback of our transmitted frames.
8198 */
8199 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8200 for (p = 0; p < num_pools; p++) {
8201 if (hw->mac.ops.set_source_address_pruning)
8202 hw->mac.ops.set_source_address_pruning(hw,
8203 false,
8204 p);
8205 }
219efe97
DS		 8206 break;
8207 default:
8208 return -EINVAL;
8209 }
8210
8211 adapter->bridge_mode = mode;
8212
8213 e_info(drv, "enabling bridge mode: %s\n",
8214 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8215
8216 return 0;
8217}
8218
815cccbf 8219static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8220 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8221{
8222 struct ixgbe_adapter *adapter = netdev_priv(dev);
8223 struct nlattr *attr, *br_spec;
8224 int rem;
8225
8226 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8227 return -EOPNOTSUPP;
8228
8229 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8230 if (!br_spec)
8231 return -EINVAL;
815cccbf
JF		 8232
8233 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8234 int status;
815cccbf 8235 __u16 mode;
815cccbf
JF		 8236
8237 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8238 continue;
8239
b7c1a314
TG		 8240 if (nla_len(attr) < sizeof(mode))
8241 return -EINVAL;
8242
815cccbf 8243 mode = nla_get_u16(attr);
219efe97
DS		 8244 status = ixgbe_configure_bridge_mode(adapter, mode);
8245 if (status)
8246 return status;
aa2bacb6
DS		 8247
8248 break;
815cccbf
JF		 8249 }
8250
8251 return 0;
8252}
8253
8254static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8255 struct net_device *dev,
46c264da 8256 u32 filter_mask, int nlflags)
815cccbf
JF		 8257{
8258 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8259
8260 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8261 return 0;
8262
aa2bacb6 8263 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8264 adapter->bridge_mode, 0, 0, nlflags,
8265 filter_mask, NULL);
815cccbf
JF		 8266}
8267
2a47fa45
JF		 8268static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8269{
8270 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8271 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8272 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8273 unsigned int limit;
2a47fa45
JF		 8274 int pool, err;
8275
aac2f1bf
JK		 8276 /* Hardware has a limited number of available pools. Each VF, and the
8277 * PF require a pool. Check to ensure we don't attempt to use more
8278 * then the available number of pools.
8279 */
8280 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8281 return ERR_PTR(-EINVAL);
8282
219354d4
JF		 8283#ifdef CONFIG_RPS
8284 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8285 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8286 vdev->name);
8287 return ERR_PTR(-EINVAL);
8288 }
8289#endif
2a47fa45 8290 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8291 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8292 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8293 netdev_info(pdev,
8294 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8295 pdev->name);
8296 return ERR_PTR(-EINVAL);
8297 }
8298
8299 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8300 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8301 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8302 return ERR_PTR(-EBUSY);
8303
bc52f951 8304 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8305 if (!fwd_adapter)
8306 return ERR_PTR(-ENOMEM);
8307
8308 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8309 adapter->num_rx_pools++;
8310 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8311 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8312
8313 /* Enable VMDq flag so device will be set in VM mode */
8314 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8315 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8316 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8317
8318 /* Force reinit of ring allocation with VMDQ enabled */
8319 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8320 if (err)
8321 goto fwd_add_err;
8322 fwd_adapter->pool = pool;
8323 fwd_adapter->real_adapter = adapter;
8324 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8325 if (err)
8326 goto fwd_add_err;
8327 netif_tx_start_all_queues(vdev);
8328 return fwd_adapter;
8329fwd_add_err:
8330 /* unwind counter and free adapter struct */
8331 netdev_info(pdev,
8332 "%s: dfwd hardware acceleration failed\n", vdev->name);
8333 clear_bit(pool, &adapter->fwd_bitmask);
8334 adapter->num_rx_pools--;
8335 kfree(fwd_adapter);
8336 return ERR_PTR(err);
8337}
8338
8339static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8340{
8341 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8342 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8343 unsigned int limit;
2a47fa45
JF		 8344
8345 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8346 adapter->num_rx_pools--;
8347
51f3773b
JF		 8348 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8349 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8350 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8351 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8352 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8353 fwd_adapter->pool, adapter->num_rx_pools,
8354 fwd_adapter->rx_base_queue,
8355 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8356 adapter->fwd_bitmask);
8357 kfree(fwd_adapter);
8358}
8359
f467bc06
MR		 8360#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8361static netdev_features_t
8362ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8363 netdev_features_t features)
8364{
8365 if (!skb->encapsulation)
8366 return features;
8367
8368 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8369 IXGBE_MAX_TUNNEL_HDR_LEN))
8370 return features & ~NETIF_F_ALL_CSUM;
8371
8372 return features;
8373}
8374
0edc3527 8375static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8376 .ndo_open = ixgbe_open,
0edc3527 8377 .ndo_stop = ixgbe_close,
00829823 8378 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8379 .ndo_select_queue = ixgbe_select_queue,
581330ba 8380 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8381 .ndo_validate_addr = eth_validate_addr,
8382 .ndo_set_mac_address = ixgbe_set_mac,
8383 .ndo_change_mtu = ixgbe_change_mtu,
8384 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8385 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8386 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8387 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8388 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8389 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8390 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8391 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8392 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
7f01648a 8393 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8394 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8395#ifdef CONFIG_IXGBE_DCB
24095aa3 8396 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8397#endif
0edc3527
SH		 8398#ifdef CONFIG_NET_POLL_CONTROLLER
8399 .ndo_poll_controller = ixgbe_netpoll,
8400#endif
e0d1095a 8401#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8402 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8403#endif
332d4a7d
YZ		 8404#ifdef IXGBE_FCOE
8405 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8406 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8407 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8408 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8409 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8410 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8411 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8412#endif /* IXGBE_FCOE */
082757af
DS		 8413 .ndo_set_features = ixgbe_set_features,
8414 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8415 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8416 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8417 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8418 .ndo_dfwd_add_station = ixgbe_fwd_add,
8419 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8420#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8421 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8422 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8423#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8424 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8425};
8426
e027d1ae
JK		 8427/**
8428 * ixgbe_enumerate_functions - Get the number of ports this device has
8429 * @adapter: adapter structure
8430 *
8431 * This function enumerates the phsyical functions co-located on a single slot,
8432 * in order to determine how many ports a device has. This is most useful in
8433 * determining the required GT/s of PCIe bandwidth necessary for optimal
8434 * performance.
8435 **/
8436static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8437{
caafb95d 8438 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8439 int physfns = 0;
8440
f1f96579
JK		 8441 /* Some cards can not use the generic count PCIe functions method,
8442 * because they are behind a parent switch, so we hardcode these with
8443 * the correct number of functions.
e027d1ae 8444 */
8818970d 8445 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8446 physfns = 4;
8818970d
JK		 8447
8448 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8449 /* don't count virtual functions */
caafb95d
JK		 8450 if (entry->is_virtfn)
8451 continue;
8452
8453 /* When the devices on the bus don't all match our device ID,
8454 * we can't reliably determine the correct number of
8455 * functions. This can occur if a function has been direct
8456 * attached to a virtual machine using VT-d, for example. In
8457 * this case, simply return -1 to indicate this.
8458 */
8459 if ((entry->vendor != pdev->vendor) ||
8460 (entry->device != pdev->device))
8461 return -1;
8462
8463 physfns++;
e027d1ae
JK		 8464 }
8465
8466 return physfns;
8467}
8468
8e2813f5
JK		 8469/**
8470 * ixgbe_wol_supported - Check whether device supports WoL
8471 * @hw: hw specific details
8472 * @device_id: the device ID
8473 * @subdev_id: the subsystem device ID
8474 *
8475 * This function is used by probe and ethtool to determine
8476 * which devices have WoL support
8477 *
8478 **/
8479int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8480 u16 subdevice_id)
8481{
8482 struct ixgbe_hw *hw = &adapter->hw;
8483 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8484 int is_wol_supported = 0;
8485
8486 switch (device_id) {
8487 case IXGBE_DEV_ID_82599_SFP:
8488 /* Only these subdevices could supports WOL */
8489 switch (subdevice_id) {
87557440 8490 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8491 case IXGBE_SUBDEV_ID_82599_560FLR:
8492 /* only support first port */
8493 if (hw->bus.func != 0)
8494 break;
5700ff26 8495 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8496 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8497 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8498 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8499 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8500 is_wol_supported = 1;
8501 break;
8502 }
8503 break;
5daebbb0
DS		 8504 case IXGBE_DEV_ID_82599EN_SFP:
8505 /* Only this subdevice supports WOL */
8506 switch (subdevice_id) {
8507 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8508 is_wol_supported = 1;
8509 break;
8510 }
8511 break;
8e2813f5
JK		 8512 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8513 /* All except this subdevice support WOL */
8514 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8515 is_wol_supported = 1;
8516 break;
8517 case IXGBE_DEV_ID_82599_KX4:
8518 is_wol_supported = 1;
8519 break;
8520 case IXGBE_DEV_ID_X540T:
df376f0d 8521 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8522 case IXGBE_DEV_ID_X550T:
8523 case IXGBE_DEV_ID_X550EM_X_KX4:
8524 case IXGBE_DEV_ID_X550EM_X_KR:
8525 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8526 /* check eeprom to see if enabled wol */
8527 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8528 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8529 (hw->bus.func == 0))) {
8530 is_wol_supported = 1;
8531 }
8532 break;
8533 }
8534
8535 return is_wol_supported;
8536}
8537
c762dff2
MP		 8538/**
8539 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8540 * @adapter: Pointer to adapter struct
8541 */
8542static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8543{
8544#ifdef CONFIG_OF
8545 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8546 struct ixgbe_hw *hw = &adapter->hw;
8547 const unsigned char *addr;
8548
8549 addr = of_get_mac_address(dp);
8550 if (addr) {
8551 ether_addr_copy(hw->mac.perm_addr, addr);
8552 return;
8553 }
8554#endif /* CONFIG_OF */
8555
8556#ifdef CONFIG_SPARC
8557 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8558#endif /* CONFIG_SPARC */
8559}
8560
9a799d71
AK		 8561/**
8562 * ixgbe_probe - Device Initialization Routine
8563 * @pdev: PCI device information struct
8564 * @ent: entry in ixgbe_pci_tbl
8565 *
8566 * Returns 0 on success, negative on failure
8567 *
8568 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8569 * The OS initialization, configuring of the adapter private structure,
8570 * and a hardware reset occur.
8571 **/
1dd06ae8 8572static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8573{
8574 struct net_device *netdev;
8575 struct ixgbe_adapter *adapter = NULL;
8576 struct ixgbe_hw *hw;
8577 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8578 int i, err, pci_using_dac, expected_gts;
d3cb9869 8579 unsigned int indices = MAX_TX_QUEUES;
289700db 8580 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8581 bool disable_dev = false;
eacd73f7
YZ		 8582#ifdef IXGBE_FCOE
8583 u16 device_caps;
8584#endif
289700db 8585 u32 eec;
9a799d71 8586
bded64a7
AG		 8587 /* Catch broken hardware that put the wrong VF device ID in
8588 * the PCIe SR-IOV capability.
8589 */
8590 if (pdev->is_virtfn) {
8591 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8592 pci_name(pdev), pdev->vendor, pdev->device);
8593 return -EINVAL;
8594 }
8595
9ce77666 8596 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8597 if (err)
8598 return err;
8599
f5f2eda8 8600 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8601 pci_using_dac = 1;
8602 } else {
f5f2eda8 8603 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8604 if (err) {
f5f2eda8
RK		 8605 dev_err(&pdev->dev,
8606 "No usable DMA configuration, aborting\n");
8607 goto err_dma;
9a799d71
AK		 8608 }
8609 pci_using_dac = 0;
8610 }
8611
9ce77666 8612 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8613 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8614 if (err) {
b8bc0421
DC		 8615 dev_err(&pdev->dev,
8616 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8617 goto err_pci_reg;
8618 }
8619
19d5afd4 8620 pci_enable_pcie_error_reporting(pdev);
6fabd715 8621
9a799d71 8622 pci_set_master(pdev);
fb3b27bc 8623 pci_save_state(pdev);
9a799d71 8624
d3cb9869 8625 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8626#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8627 /* 8 TC w/ 4 queues per TC */
8628 indices = 4 * MAX_TRAFFIC_CLASS;
8629#else
8630 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8631#endif
d3cb9869 8632 }
e901acd6 8633
c85a2618 8634 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8635 if (!netdev) {
8636 err = -ENOMEM;
8637 goto err_alloc_etherdev;
8638 }
8639
9a799d71
AK		 8640 SET_NETDEV_DEV(netdev, &pdev->dev);
8641
9a799d71
AK		 8642 adapter = netdev_priv(netdev);
8643
8644 adapter->netdev = netdev;
8645 adapter->pdev = pdev;
8646 hw = &adapter->hw;
8647 hw->back = adapter;
b3f4d599 8648 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8649
05857980 8650 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8651 pci_resource_len(pdev, 0));
2a1a091c 8652 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8653 if (!hw->hw_addr) {
8654 err = -EIO;
8655 goto err_ioremap;
8656 }
8657
0edc3527 8658 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8659 ixgbe_set_ethtool_ops(netdev);
9a799d71 8660 netdev->watchdog_timeo = 5 * HZ;
339de30f 8661 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8662
9a799d71
AK		 8663 /* Setup hw api */
8664 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8665 hw->mac.type = ii->mac;
9a900eca 8666 hw->mvals = ii->mvals;
9a799d71 8667
c44ade9e
JB		 8668 /* EEPROM */
8669 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 8670 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 8671 if (ixgbe_removed(hw->hw_addr)) {
8672 err = -EIO;
8673 goto err_ioremap;
8674 }
c44ade9e
JB		 8675 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8676 if (!(eec & (1 << 8)))
8677 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8678
8679 /* PHY */
8680 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8681 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8682 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8683 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8684 hw->phy.mdio.mmds = 0;
8685 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8686 hw->phy.mdio.dev = netdev;
8687 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8688 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8689
8ca783ab 8690 ii->get_invariants(hw);
9a799d71
AK		 8691
8692 /* setup the private structure */
8693 err = ixgbe_sw_init(adapter);
8694 if (err)
8695 goto err_sw_init;
8696
e86bff0e 8697 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8698 switch (adapter->hw.mac.type) {
8699 case ixgbe_mac_82599EB:
8700 case ixgbe_mac_X540:
9a75a1ac
DS		 8701 case ixgbe_mac_X550:
8702 case ixgbe_mac_X550EM_x:
e86bff0e 8703 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8704 break;
8705 default:
8706 break;
8707 }
e86bff0e 8708
bf069c97
DS		 8709 /*
8710 * If there is a fan on this device and it has failed log the
8711 * failure.
8712 */
8713 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8714 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8715 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8716 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8717 }
8718
8ef78adc
PWJ		 8719 if (allow_unsupported_sfp)
8720 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8721
c44ade9e 8722 /* reset_hw fills in the perm_addr as well */
119fc60a 8723 hw->phy.reset_if_overtemp = true;
c44ade9e 8724 err = hw->mac.ops.reset_hw(hw);
119fc60a 8725 hw->phy.reset_if_overtemp = false;
29a8dca1 8726 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 8727 err = 0;
8728 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8729 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8730 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8731 goto err_sw_init;
8732 } else if (err) {
849c4542 8733 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8734 goto err_sw_init;
8735 }
8736
99d74487 8737#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8738 /* SR-IOV not supported on the 82598 */
8739 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8740 goto skip_sriov;
8741 /* Mailbox */
8742 ixgbe_init_mbx_params_pf(hw);
8743 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8744 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8745 ixgbe_enable_sriov(adapter);
60a1a680 8746skip_sriov:
1cdd1ec8 8747
99d74487 8748#endif
396e799c 8749 netdev->features = NETIF_F_SG |
e8e9f696 8750 NETIF_F_IP_CSUM |
082757af 8751 NETIF_F_IPV6_CSUM |
f646968f
PM		 8752 NETIF_F_HW_VLAN_CTAG_TX |
8753 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 8754 NETIF_F_TSO |
8755 NETIF_F_TSO6 |
082757af 8756 NETIF_F_RXHASH |
8bf1264d 8757 NETIF_F_RXCSUM;
9a799d71 8758
8bf1264d 8759 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8760
58be7666
DS		 8761 switch (adapter->hw.mac.type) {
8762 case ixgbe_mac_82599EB:
8763 case ixgbe_mac_X540:
9a75a1ac
DS		 8764 case ixgbe_mac_X550:
8765 case ixgbe_mac_X550EM_x:
45a5ead0 8766 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8767 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8768 NETIF_F_NTUPLE;
58be7666
DS		 8769 break;
8770 default:
8771 break;
8772 }
45a5ead0 8773
3f2d1c0f 8774 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 8775 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 8776
ad31c402
JK		 8777 netdev->vlan_features |= NETIF_F_TSO;
8778 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8779 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8780 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8781 netdev->vlan_features |= NETIF_F_SG;
8782
f467bc06
MR		 8783 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8784 NETIF_F_IPV6_CSUM;
8785
01789349 8786 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8787 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8788
67359c3c 8789#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8790 switch (adapter->hw.mac.type) {
8791 case ixgbe_mac_X550:
8792 case ixgbe_mac_X550EM_x:
67359c3c
MR		 8793 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8794 NETIF_F_IP_CSUM |
8795 NETIF_F_IPV6_CSUM;
3f207800
DS		 8796 break;
8797 default:
8798 break;
8799 }
67359c3c 8800#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8801
7a6b6f51 8802#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8803 netdev->dcbnl_ops = &dcbnl_ops;
8804#endif
8805
eacd73f7 8806#ifdef IXGBE_FCOE
0d551589 8807 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8808 unsigned int fcoe_l;
8809
eacd73f7
YZ		 8810 if (hw->mac.ops.get_device_caps) {
8811 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8812 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8813 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8814 }
7c8ae65a 8815
d3cb9869
AD		 8816
8817 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8818 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8819
a58915c7
AD		 8820 netdev->features |= NETIF_F_FSO |
8821 NETIF_F_FCOE_CRC;
8822
7c8ae65a
AD		 8823 netdev->vlan_features |= NETIF_F_FSO |
8824 NETIF_F_FCOE_CRC |
8825 NETIF_F_FCOE_MTU;
5e09d7f6 8826 }
eacd73f7 8827#endif /* IXGBE_FCOE */
7b872a55 8828 if (pci_using_dac) {
9a799d71 8829 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8830 netdev->vlan_features |= NETIF_F_HIGHDMA;
8831 }
9a799d71 8832
082757af
DS		 8833 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8834 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8835 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8836 netdev->features |= NETIF_F_LRO;
8837
9a799d71 8838 /* make sure the EEPROM is good */
c44ade9e 8839 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8840 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8841 err = -EIO;
35937c05 8842 goto err_sw_init;
9a799d71
AK		 8843 }
8844
c762dff2
MP		 8845 ixgbe_get_platform_mac_addr(adapter);
8846
9a799d71 8847 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8848
aaeb6cdf 8849 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8850 e_dev_err("invalid MAC address\n");
9a799d71 8851 err = -EIO;
35937c05 8852 goto err_sw_init;
9a799d71
AK		 8853 }
8854
5d7daa35
JK		 8855 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8856
7086400d 8857 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8858 (unsigned long) adapter);
9a799d71 8859
58cf663f
MR		 8860 if (ixgbe_removed(hw->hw_addr)) {
8861 err = -EIO;
8862 goto err_sw_init;
8863 }
7086400d 8864 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8865 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8866 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8867
021230d4
AV		 8868 err = ixgbe_init_interrupt_scheme(adapter);
8869 if (err)
8870 goto err_sw_init;
9a799d71 8871
8e2813f5 8872 /* WOL not supported for all devices */
c23f5b6b 8873 adapter->wol = 0;
8e2813f5 8874 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8875 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8876 pdev->subsystem_device);
6b92b0ba 8877 if (hw->wol_enabled)
9417c464 8878 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8879
e8e26350
PW		 8880 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8881
15e5209f
ET		 8882 /* save off EEPROM version number */
8883 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8884 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8885
04f165ef 8886 /* pick up the PCI bus settings for reporting later */
e027d1ae 8887 if (ixgbe_pcie_from_parent(hw))
b8e82001 8888 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 8889 else
8890 hw->mac.ops.get_bus_info(hw);
04f165ef 8891
e027d1ae
JK		 8892 /* calculate the expected PCIe bandwidth required for optimal
8893 * performance. Note that some older parts will never have enough
8894 * bandwidth due to being older generation PCIe parts. We clamp these
8895 * parts to ensure no warning is displayed if it can't be fixed.
8896 */
8897 switch (hw->mac.type) {
8898 case ixgbe_mac_82598EB:
8899 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8900 break;
8901 default:
8902 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8903 break;
0c254d86 8904 }
caafb95d
JK		 8905
8906 /* don't check link if we failed to enumerate functions */
8907 if (expected_gts > 0)
8908 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8909
339de30f 8910 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8911 if (err)
339de30f 8912 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8913 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8914 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8915 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8916 part_str);
6a2aae5a
JK		 8917 else
8918 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8919 hw->mac.type, hw->phy.type, part_str);
8920
8921 e_dev_info("%pM\n", netdev->dev_addr);
8922
9a799d71 8923 /* reset the hardware with the new settings */
794caeb2 8924 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8925 if (err == IXGBE_ERR_EEPROM_VERSION) {
8926 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8927 e_dev_warn("This device is a pre-production adapter/LOM. "
8928 "Please be aware there may be issues associated "
8929 "with your hardware. If you are experiencing "
8930 "problems please contact your Intel or hardware "
8931 "representative who provided you with this "
8932 "hardware.\n");
794caeb2 8933 }
9a799d71
AK		 8934 strcpy(netdev->name, "eth%d");
8935 err = register_netdev(netdev);
8936 if (err)
8937 goto err_register;
8938
0fb6a55c
ET		 8939 pci_set_drvdata(pdev, adapter);
8940
ec74a471
ET		 8941 /* power down the optics for 82599 SFP+ fiber */
8942 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8943 hw->mac.ops.disable_tx_laser(hw);
8944
54386467
JB		 8945 /* carrier off reporting is important to ethtool even BEFORE open */
8946 netif_carrier_off(netdev);
8947
5dd2d332 8948#ifdef CONFIG_IXGBE_DCA
652f093f 8949 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8950 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8951 ixgbe_setup_dca(adapter);
8952 }
8953#endif
1cdd1ec8 8954 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8955 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8956 for (i = 0; i < adapter->num_vfs; i++)
8957 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8958 }
8959
2466dd9c
JK		 8960 /* firmware requires driver version to be 0xFFFFFFFF
8961 * since os does not support feature
8962 */
9612de92 8963 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8964 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8965 0xFF);
9612de92 8966
0365e6e4
PW		 8967 /* add san mac addr to netdev */
8968 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8969
ea81875a 8970 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8971
1210982b 8972#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8973 if (ixgbe_sysfs_init(adapter))
8974 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8975#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8976
00949167 8977 ixgbe_dbg_adapter_init(adapter);
00949167 8978
d1a35ee2
ET		 8979 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8980 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8981 hw->mac.ops.setup_link(hw,
8982 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8983 true);
8984
9a799d71
AK		 8985 return 0;
8986
8987err_register:
5eba3699 8988 ixgbe_release_hw_control(adapter);
7a921c93 8989 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8990err_sw_init:
99d74487 8991 ixgbe_disable_sriov(adapter);
7086400d 8992 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8993 iounmap(adapter->io_addr);
5d7daa35 8994 kfree(adapter->mac_table);
9a799d71 8995err_ioremap:
b5b2ffc0 8996 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8997 free_netdev(netdev);
8998err_alloc_etherdev:
e8e9f696
JP		 8999 pci_release_selected_regions(pdev,
9000 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 9001err_pci_reg:
9002err_dma:
b5b2ffc0 9003 if (!adapter || disable_dev)
41c62843 9004 pci_disable_device(pdev);
9a799d71
AK		 9005 return err;
9006}
9007
9008/**
9009 * ixgbe_remove - Device Removal Routine
9010 * @pdev: PCI device information struct
9011 *
9012 * ixgbe_remove is called by the PCI subsystem to alert the driver
9013 * that it should release a PCI device. The could be caused by a
9014 * Hot-Plug event, or because the driver is going to be removed from
9015 * memory.
9016 **/
9f9a12f8 9017static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9018{
c60fbb00 9019 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9020 struct net_device *netdev;
b5b2ffc0 9021 bool disable_dev;
9a799d71 9022
0fb6a55c
ET		 9023 /* if !adapter then we already cleaned up in probe */
9024 if (!adapter)
9025 return;
9026
9027 netdev = adapter->netdev;
00949167 9028 ixgbe_dbg_adapter_exit(adapter);
00949167 9029
09f40aed 9030 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9031 cancel_work_sync(&adapter->service_task);
9a799d71 9032
3a6a4eda 9033
5dd2d332 9034#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9035 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9036 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9037 dca_remove_requester(&pdev->dev);
9038 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
9039 }
9040
9041#endif
1210982b 9042#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9043 ixgbe_sysfs_exit(adapter);
1210982b 9044#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9045
0365e6e4
PW		 9046 /* remove the added san mac */
9047 ixgbe_del_sanmac_netdev(netdev);
9048
da36b647 9049#ifdef CONFIG_PCI_IOV
7837e286 9050 ixgbe_disable_sriov(adapter);
da36b647 9051#endif
6b010e9b
AW		 9052 if (netdev->reg_state == NETREG_REGISTERED)
9053 unregister_netdev(netdev);
9054
7a921c93 9055 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9056
021230d4 9057 ixgbe_release_hw_control(adapter);
9a799d71 9058
2b1588c3
AD		 9059#ifdef CONFIG_DCB
9060 kfree(adapter->ixgbe_ieee_pfc);
9061 kfree(adapter->ixgbe_ieee_ets);
9062
9063#endif
2a1a091c 9064 iounmap(adapter->io_addr);
9ce77666 9065 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9066 IORESOURCE_MEM));
9a799d71 9067
849c4542 9068 e_dev_info("complete\n");
021230d4 9069
5d7daa35 9070 kfree(adapter->mac_table);
b5b2ffc0 9071 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9072 free_netdev(netdev);
9073
19d5afd4 9074 pci_disable_pcie_error_reporting(pdev);
6fabd715 9075
b5b2ffc0 9076 if (disable_dev)
41c62843 9077 pci_disable_device(pdev);
9a799d71
AK		 9078}
9079
9080/**
9081 * ixgbe_io_error_detected - called when PCI error is detected
9082 * @pdev: Pointer to PCI device
9083 * @state: The current pci connection state
9084 *
9085 * This function is called after a PCI bus error affecting
9086 * this device has been detected.
9087 */
9088static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9089 pci_channel_state_t state)
9a799d71 9090{
c60fbb00
AD		 9091 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9092 struct net_device *netdev = adapter->netdev;
9a799d71 9093
83c61fa9 9094#ifdef CONFIG_PCI_IOV
14438464 9095 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9096 struct pci_dev *bdev, *vfdev;
9097 u32 dw0, dw1, dw2, dw3;
9098 int vf, pos;
9099 u16 req_id, pf_func;
9100
9101 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9102 adapter->num_vfs == 0)
9103 goto skip_bad_vf_detection;
9104
9105 bdev = pdev->bus->self;
62f87c0e 9106 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9107 bdev = bdev->bus->self;
9108
9109 if (!bdev)
9110 goto skip_bad_vf_detection;
9111
9112 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9113 if (!pos)
9114 goto skip_bad_vf_detection;
9115
14438464
MR		 9116 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9117 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9118 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9119 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9120 if (ixgbe_removed(hw->hw_addr))
9121 goto skip_bad_vf_detection;
83c61fa9
GR		 9122
9123 req_id = dw1 >> 16;
9124 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9125 if (!(req_id & 0x0080))
9126 goto skip_bad_vf_detection;
9127
9128 pf_func = req_id & 0x01;
9129 if ((pf_func & 1) == (pdev->devfn & 1)) {
9130 unsigned int device_id;
9131
9132 vf = (req_id & 0x7F) >> 1;
9133 e_dev_err("VF %d has caused a PCIe error\n", vf);
9134 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9135 "%8.8x\tdw3: %8.8x\n",
9136 dw0, dw1, dw2, dw3);
9137 switch (adapter->hw.mac.type) {
9138 case ixgbe_mac_82599EB:
9139 device_id = IXGBE_82599_VF_DEVICE_ID;
9140 break;
9141 case ixgbe_mac_X540:
9142 device_id = IXGBE_X540_VF_DEVICE_ID;
9143 break;
9a75a1ac
DS		 9144 case ixgbe_mac_X550:
9145 device_id = IXGBE_DEV_ID_X550_VF;
9146 break;
9147 case ixgbe_mac_X550EM_x:
9148 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9149 break;
83c61fa9
GR		 9150 default:
9151 device_id = 0;
9152 break;
9153 }
9154
9155 /* Find the pci device of the offending VF */
36e90319 9156 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9157 while (vfdev) {
9158 if (vfdev->devfn == (req_id & 0xFF))
9159 break;
36e90319 9160 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9161 device_id, vfdev);
9162 }
9163 /*
9164 * There's a slim chance the VF could have been hot plugged,
9165 * so if it is no longer present we don't need to issue the
9166 * VFLR. Just clean up the AER in that case.
9167 */
9168 if (vfdev) {
9079e416 9169 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9170 /* Free device reference count */
9171 pci_dev_put(vfdev);
83c61fa9
GR		 9172 }
9173
9174 pci_cleanup_aer_uncorrect_error_status(pdev);
9175 }
9176
9177 /*
9178 * Even though the error may have occurred on the other port
9179 * we still need to increment the vf error reference count for
9180 * both ports because the I/O resume function will be called
9181 * for both of them.
9182 */
9183 adapter->vferr_refcount++;
9184
9185 return PCI_ERS_RESULT_RECOVERED;
9186
9187skip_bad_vf_detection:
9188#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9189 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9190 return PCI_ERS_RESULT_DISCONNECT;
9191
41c62843 9192 rtnl_lock();
9a799d71
AK		 9193 netif_device_detach(netdev);
9194
41c62843
MR		 9195 if (state == pci_channel_io_perm_failure) {
9196 rtnl_unlock();
3044b8d1 9197 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9198 }
3044b8d1 9199
9a799d71
AK		 9200 if (netif_running(netdev))
9201 ixgbe_down(adapter);
41c62843
MR		 9202
9203 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9204 pci_disable_device(pdev);
9205 rtnl_unlock();
9a799d71 9206
b4617240 9207 /* Request a slot reset. */
9a799d71
AK		 9208 return PCI_ERS_RESULT_NEED_RESET;
9209}
9210
9211/**
9212 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9213 * @pdev: Pointer to PCI device
9214 *
9215 * Restart the card from scratch, as if from a cold-boot.
9216 */
9217static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9218{
c60fbb00 9219 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9220 pci_ers_result_t result;
9221 int err;
9a799d71 9222
9ce77666 9223 if (pci_enable_device_mem(pdev)) {
396e799c 9224 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9225 result = PCI_ERS_RESULT_DISCONNECT;
9226 } else {
4e857c58 9227 smp_mb__before_atomic();
41c62843 9228 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9229 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9230 pci_set_master(pdev);
9231 pci_restore_state(pdev);
c0e1f68b 9232 pci_save_state(pdev);
9a799d71 9233
dd4d8ca6 9234 pci_wake_from_d3(pdev, false);
9a799d71 9235
6fabd715 9236 ixgbe_reset(adapter);
88512539 9237 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9238 result = PCI_ERS_RESULT_RECOVERED;
9239 }
9240
9241 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9242 if (err) {
849c4542
ET		 9243 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9244 "failed 0x%0x\n", err);
6fabd715
PWJ		 9245 /* non-fatal, continue */
9246 }
9a799d71 9247
6fabd715 9248 return result;
9a799d71
AK		 9249}
9250
9251/**
9252 * ixgbe_io_resume - called when traffic can start flowing again.
9253 * @pdev: Pointer to PCI device
9254 *
9255 * This callback is called when the error recovery driver tells us that
9256 * its OK to resume normal operation.
9257 */
9258static void ixgbe_io_resume(struct pci_dev *pdev)
9259{
c60fbb00
AD		 9260 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9261 struct net_device *netdev = adapter->netdev;
9a799d71 9262
83c61fa9
GR		 9263#ifdef CONFIG_PCI_IOV
9264 if (adapter->vferr_refcount) {
9265 e_info(drv, "Resuming after VF err\n");
9266 adapter->vferr_refcount--;
9267 return;
9268 }
9269
9270#endif
c7ccde0f
AD		 9271 if (netif_running(netdev))
9272 ixgbe_up(adapter);
9a799d71
AK		 9273
9274 netif_device_attach(netdev);
9a799d71
AK		 9275}
9276
3646f0e5 9277static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9278 .error_detected = ixgbe_io_error_detected,
9279 .slot_reset = ixgbe_io_slot_reset,
9280 .resume = ixgbe_io_resume,
9281};
9282
9283static struct pci_driver ixgbe_driver = {
9284 .name = ixgbe_driver_name,
9285 .id_table = ixgbe_pci_tbl,
9286 .probe = ixgbe_probe,
9f9a12f8 9287 .remove = ixgbe_remove,
9a799d71
AK		 9288#ifdef CONFIG_PM
9289 .suspend = ixgbe_suspend,
9290 .resume = ixgbe_resume,
9291#endif
9292 .shutdown = ixgbe_shutdown,
da36b647 9293 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9294 .err_handler = &ixgbe_err_handler
9295};
9296
9297/**
9298 * ixgbe_init_module - Driver Registration Routine
9299 *
9300 * ixgbe_init_module is the first routine called when the driver is
9301 * loaded. All it does is register with the PCI subsystem.
9302 **/
9303static int __init ixgbe_init_module(void)
9304{
9305 int ret;
c7689578 9306 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9307 pr_info("%s\n", ixgbe_copyright);
9a799d71 9308
00949167 9309 ixgbe_dbg_init();
00949167 9310
f01fc1a8
JK		 9311 ret = pci_register_driver(&ixgbe_driver);
9312 if (ret) {
f01fc1a8 9313 ixgbe_dbg_exit();
f01fc1a8
JK		 9314 return ret;
9315 }
9316
5dd2d332 9317#ifdef CONFIG_IXGBE_DCA
bd0362dd 9318 dca_register_notify(&dca_notifier);
bd0362dd 9319#endif
5dd2d332 9320
f01fc1a8 9321 return 0;
9a799d71 9322}
b4617240 9323
9a799d71
AK		 9324module_init(ixgbe_init_module);
9325
9326/**
9327 * ixgbe_exit_module - Driver Exit Cleanup Routine
9328 *
9329 * ixgbe_exit_module is called just before the driver is removed
9330 * from memory.
9331 **/
9332static void __exit ixgbe_exit_module(void)
9333{
5dd2d332 9334#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9335 dca_unregister_notify(&dca_notifier);
9336#endif
9a799d71 9337 pci_unregister_driver(&ixgbe_driver);
00949167 9338
00949167 9339 ixgbe_dbg_exit();
9a799d71 9340}
bd0362dd 9341
5dd2d332 9342#ifdef CONFIG_IXGBE_DCA
bd0362dd 9343static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9344 void *p)
bd0362dd
JC		 9345{
9346 int ret_val;
9347
9348 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9349 __ixgbe_notify_dca);
bd0362dd
JC		 9350
9351 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9352}
b453368d 9353
5dd2d332 9354#endif /* CONFIG_IXGBE_DCA */
849c4542 9355
9a799d71
AK		 9356module_exit(ixgbe_exit_module);
9357
9358/* ixgbe_main.c */
Linux kernel - Deliverables
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