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PCI: Add function to obtain minimum link width and speed
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
815cccbf 47#include <linux/if_bridge.h>
70c71606 48#include <linux/prefetch.h>
eacd73f7 49#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 50
51#include "ixgbe.h"
52#include "ixgbe_common.h"
ee5f784a 53#include "ixgbe_dcb_82599.h"
1cdd1ec8 54#include "ixgbe_sriov.h"
9a799d71
AK		 55
56char ixgbe_driver_name[] = "ixgbe";
9c8eb720 57static const char ixgbe_driver_string[] =
e8e9f696 58 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 59#ifdef IXGBE_FCOE
ea81875a
NP		 60char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 62#else
63static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65#endif
93ac03be 66#define DRV_VERSION "3.15.1-k"
9c8eb720 67const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 68static const char ixgbe_copyright[] =
434c5e39 69 "Copyright (c) 1999-2013 Intel Corporation.";
9a799d71
AK		 70
71static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 72 [board_82598] = &ixgbe_82598_info,
e8e26350 73 [board_82599] = &ixgbe_82599_info,
fe15e8e1 74 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 75};
76
77/* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 115 /* required last entry */
116 {0, }
117};
118MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
5dd2d332 120#ifdef CONFIG_IXGBE_DCA
bd0362dd 121static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 122 void *p);
bd0362dd
JC		 123static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127};
128#endif
129
1cdd1ec8
GR		 130#ifdef CONFIG_PCI_IOV
131static unsigned int max_vfs;
132module_param(max_vfs, uint, 0);
e8e9f696 133MODULE_PARM_DESC(max_vfs,
6b42a9c5 134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 135#endif /* CONFIG_PCI_IOV */
136
8ef78adc
PWJ		 137static unsigned int allow_unsupported_sfp;
138module_param(allow_unsupported_sfp, uint, 0);
139MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
b3f4d599 142#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143static int debug = -1;
144module_param(debug, int, 0);
145MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
9a799d71
AK		 147MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149MODULE_LICENSE("GPL");
150MODULE_VERSION(DRV_VERSION);
151
b8e82001
JK		 152static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
153 u32 reg, u16 *value)
154{
155 int pos = 0;
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
158
159 parent_bus = adapter->pdev->bus->parent;
160 if (!parent_bus)
161 return -1;
162
163 parent_dev = parent_bus->self;
164 if (!parent_dev)
165 return -1;
166
167 pos = pci_find_capability(parent_dev, PCI_CAP_ID_EXP);
168 if (!pos)
169 return -1;
170
171 pci_read_config_word(parent_dev, pos + reg, value);
172 return 0;
173}
174
175static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176{
177 struct ixgbe_hw *hw = &adapter->hw;
178 u16 link_status = 0;
179 int err;
180
181 hw->bus.type = ixgbe_bus_type_pci_express;
182
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
185 */
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187
188 /* assume caller will handle error case */
189 if (err)
190 return err;
191
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
194
195 return 0;
196}
197
7086400d
AD		 198static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199{
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203}
204
205static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206{
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
52f33af8 209 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212}
213
dcd79aeb
TI		 214struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217};
218
219static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249};
250
251
252/*
253 * ixgbe_regdump - register printout routine
254 */
255static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256{
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
c7689578 319 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 326 pr_err("%-15s", rname);
dcd79aeb 327 for (j = 0; j < 8; j++)
c7689578
JP		 328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
dcd79aeb
TI		 330 }
331
332}
333
334/*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337static void ixgbe_dump(struct ixgbe_adapter *adapter)
338{
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
729739b7 344 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 359 pr_info("Device Name state "
dcd79aeb 360 "trans_start last_rx\n");
c7689578
JP		 361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
dcd79aeb
TI		 366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 370 pr_info(" Register Name Value\n");
dcd79aeb
TI		 371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 381 pr_info(" %s %s %s %s\n",
382 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
383 "leng", "ntw", "timestamp");
dcd79aeb
TI		 384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
729739b7 386 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 387 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 388 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 389 (u64)dma_unmap_addr(tx_buffer, dma),
390 dma_unmap_len(tx_buffer, len),
391 tx_buffer->next_to_watch,
392 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 393 }
394
395 /* Print TX Rings */
396 if (!netif_msg_tx_done(adapter))
397 goto rx_ring_summary;
398
399 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
400
401 /* Transmit Descriptor Formats
402 *
39ac868a 403 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 404 * +--------------------------------------------------------------+
405 * 0 | Buffer Address [63:0] |
406 * +--------------------------------------------------------------+
39ac868a 407 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 408 * +--------------------------------------------------------------+
409 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 410 *
411 * 82598 Advanced Transmit Descriptor (Write-Back Format)
412 * +--------------------------------------------------------------+
413 * 0 | RSV [63:0] |
414 * +--------------------------------------------------------------+
415 * 8 | RSV | STA | NXTSEQ |
416 * +--------------------------------------------------------------+
417 * 63 36 35 32 31 0
418 *
419 * 82599+ Advanced Transmit Descriptor
420 * +--------------------------------------------------------------+
421 * 0 | Buffer Address [63:0] |
422 * +--------------------------------------------------------------+
423 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
424 * +--------------------------------------------------------------+
425 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
426 *
427 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
428 * +--------------------------------------------------------------+
429 * 0 | RSV [63:0] |
430 * +--------------------------------------------------------------+
431 * 8 | RSV | STA | RSV |
432 * +--------------------------------------------------------------+
433 * 63 36 35 32 31 0
dcd79aeb
TI		 434 */
435
436 for (n = 0; n < adapter->num_tx_queues; n++) {
437 tx_ring = adapter->tx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
440 pr_info("------------------------------------\n");
8ad88e37
JH		 441 pr_info("%s%s %s %s %s %s\n",
442 "T [desc] [address 63:0 ] ",
443 "[PlPOIdStDDt Ln] [bi->dma ] ",
444 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 445
446 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 447 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 448 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 449 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 450 if (dma_unmap_len(tx_buffer, len) > 0) {
451 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
452 i,
453 le64_to_cpu(u0->a),
454 le64_to_cpu(u0->b),
455 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 456 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 457 tx_buffer->next_to_watch,
458 (u64)tx_buffer->time_stamp,
459 tx_buffer->skb);
460 if (i == tx_ring->next_to_use &&
461 i == tx_ring->next_to_clean)
462 pr_cont(" NTC/U\n");
463 else if (i == tx_ring->next_to_use)
464 pr_cont(" NTU\n");
465 else if (i == tx_ring->next_to_clean)
466 pr_cont(" NTC\n");
467 else
468 pr_cont("\n");
469
470 if (netif_msg_pktdata(adapter) &&
471 tx_buffer->skb)
472 print_hex_dump(KERN_INFO, "",
473 DUMP_PREFIX_ADDRESS, 16, 1,
474 tx_buffer->skb->data,
475 dma_unmap_len(tx_buffer, len),
476 true);
477 }
dcd79aeb
TI		 478 }
479 }
480
481 /* Print RX Rings Summary */
482rx_ring_summary:
483 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 484 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 485 for (n = 0; n < adapter->num_rx_queues; n++) {
486 rx_ring = adapter->rx_ring[n];
c7689578
JP		 487 pr_info("%5d %5X %5X\n",
488 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 489 }
490
491 /* Print RX Rings */
492 if (!netif_msg_rx_status(adapter))
493 goto exit;
494
495 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
496
39ac868a
JH		 497 /* Receive Descriptor Formats
498 *
499 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 500 * 63 1 0
501 * +-----------------------------------------------------+
502 * 0 | Packet Buffer Address [63:1] |A0/NSE|
503 * +----------------------------------------------+------+
504 * 8 | Header Buffer Address [63:1] | DD |
505 * +-----------------------------------------------------+
506 *
507 *
39ac868a 508 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 509 *
510 * 63 48 47 32 31 30 21 20 16 15 4 3 0
511 * +------------------------------------------------------+
39ac868a
JH		 512 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
513 * | Packet | IP | | | | Type | Type |
514 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 515 * +------------------------------------------------------+
516 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
517 * +------------------------------------------------------+
518 * 63 48 47 32 31 20 19 0
39ac868a
JH		 519 *
520 * 82599+ Advanced Receive Descriptor (Read) Format
521 * 63 1 0
522 * +-----------------------------------------------------+
523 * 0 | Packet Buffer Address [63:1] |A0/NSE|
524 * +----------------------------------------------+------+
525 * 8 | Header Buffer Address [63:1] | DD |
526 * +-----------------------------------------------------+
527 *
528 *
529 * 82599+ Advanced Receive Descriptor (Write-Back) Format
530 *
531 * 63 48 47 32 31 30 21 20 17 16 4 3 0
532 * +------------------------------------------------------+
533 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
534 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
535 * |/ Flow Dir Flt ID | | | | | |
536 * +------------------------------------------------------+
537 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
538 * +------------------------------------------------------+
539 * 63 48 47 32 31 20 19 0
dcd79aeb 540 */
39ac868a 541
dcd79aeb
TI		 542 for (n = 0; n < adapter->num_rx_queues; n++) {
543 rx_ring = adapter->rx_ring[n];
c7689578
JP		 544 pr_info("------------------------------------\n");
545 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
546 pr_info("------------------------------------\n");
8ad88e37
JH		 547 pr_info("%s%s%s",
548 "R [desc] [ PktBuf A0] ",
549 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 550 "<-- Adv Rx Read format\n");
8ad88e37
JH		 551 pr_info("%s%s%s",
552 "RWB[desc] [PcsmIpSHl PtRs] ",
553 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 554 "<-- Adv Rx Write-Back format\n");
555
556 for (i = 0; i < rx_ring->count; i++) {
557 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 558 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 559 u0 = (struct my_u0 *)rx_desc;
560 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
561 if (staterr & IXGBE_RXD_STAT_DD) {
562 /* Descriptor Done */
c7689578 563 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 564 "%016llX ---------------- %p", i,
565 le64_to_cpu(u0->a),
566 le64_to_cpu(u0->b),
567 rx_buffer_info->skb);
568 } else {
c7689578 569 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 570 "%016llX %016llX %p", i,
571 le64_to_cpu(u0->a),
572 le64_to_cpu(u0->b),
573 (u64)rx_buffer_info->dma,
574 rx_buffer_info->skb);
575
9c50c035
ET		 576 if (netif_msg_pktdata(adapter) &&
577 rx_buffer_info->dma) {
dcd79aeb
TI		 578 print_hex_dump(KERN_INFO, "",
579 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 580 page_address(rx_buffer_info->page) +
581 rx_buffer_info->page_offset,
f800326d 582 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 583 }
584 }
585
586 if (i == rx_ring->next_to_use)
c7689578 587 pr_cont(" NTU\n");
dcd79aeb 588 else if (i == rx_ring->next_to_clean)
c7689578 589 pr_cont(" NTC\n");
dcd79aeb 590 else
c7689578 591 pr_cont("\n");
dcd79aeb
TI		 592
593 }
594 }
595
596exit:
597 return;
598}
599
5eba3699
AV		 600static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
601{
602 u32 ctrl_ext;
603
604 /* Let firmware take over control of h/w */
605 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
606 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 607 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 608}
609
610static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
611{
612 u32 ctrl_ext;
613
614 /* Let firmware know the driver has taken over */
615 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
616 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 617 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 618}
9a799d71 619
49ce9c2c 620/**
e8e26350
PW		 621 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
622 * @adapter: pointer to adapter struct
623 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
624 * @queue: queue to map the corresponding interrupt to
625 * @msix_vector: the vector to map to the corresponding queue
626 *
627 */
628static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 629 u8 queue, u8 msix_vector)
9a799d71
AK		 630{
631 u32 ivar, index;
e8e26350
PW		 632 struct ixgbe_hw *hw = &adapter->hw;
633 switch (hw->mac.type) {
634 case ixgbe_mac_82598EB:
635 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
636 if (direction == -1)
637 direction = 0;
638 index = (((direction * 64) + queue) >> 2) & 0x1F;
639 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
640 ivar &= ~(0xFF << (8 * (queue & 0x3)));
641 ivar |= (msix_vector << (8 * (queue & 0x3)));
642 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
643 break;
644 case ixgbe_mac_82599EB:
b93a2226 645 case ixgbe_mac_X540:
e8e26350
PW		 646 if (direction == -1) {
647 /* other causes */
648 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
649 index = ((queue & 1) * 8);
650 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
651 ivar &= ~(0xFF << index);
652 ivar |= (msix_vector << index);
653 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
654 break;
655 } else {
656 /* tx or rx causes */
657 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
658 index = ((16 * (queue & 1)) + (8 * direction));
659 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
660 ivar &= ~(0xFF << index);
661 ivar |= (msix_vector << index);
662 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
663 break;
664 }
665 default:
666 break;
667 }
9a799d71
AK		 668}
669
fe49f04a 670static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 671 u64 qmask)
fe49f04a
AD		 672{
673 u32 mask;
674
bd508178
AD		 675 switch (adapter->hw.mac.type) {
676 case ixgbe_mac_82598EB:
fe49f04a
AD		 677 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 679 break;
680 case ixgbe_mac_82599EB:
b93a2226 681 case ixgbe_mac_X540:
fe49f04a
AD		 682 mask = (qmask & 0xFFFFFFFF);
683 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
684 mask = (qmask >> 32);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 686 break;
687 default:
688 break;
fe49f04a
AD		 689 }
690}
691
729739b7
AD		 692void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
693 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 694{
729739b7
AD		 695 if (tx_buffer->skb) {
696 dev_kfree_skb_any(tx_buffer->skb);
697 if (dma_unmap_len(tx_buffer, len))
d3d00239 698 dma_unmap_single(ring->dev,
729739b7
AD		 699 dma_unmap_addr(tx_buffer, dma),
700 dma_unmap_len(tx_buffer, len),
701 DMA_TO_DEVICE);
702 } else if (dma_unmap_len(tx_buffer, len)) {
703 dma_unmap_page(ring->dev,
704 dma_unmap_addr(tx_buffer, dma),
705 dma_unmap_len(tx_buffer, len),
706 DMA_TO_DEVICE);
e5a43549 707 }
729739b7
AD		 708 tx_buffer->next_to_watch = NULL;
709 tx_buffer->skb = NULL;
710 dma_unmap_len_set(tx_buffer, len, 0);
711 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 712}
713
943561d3 714static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 715{
716 struct ixgbe_hw *hw = &adapter->hw;
717 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 718 int i;
943561d3 719 u32 data;
c84d324c 720
943561d3
AD		 721 if ((hw->fc.current_mode != ixgbe_fc_full) &&
722 (hw->fc.current_mode != ixgbe_fc_rx_pause))
723 return;
c84d324c 724
943561d3
AD		 725 switch (hw->mac.type) {
726 case ixgbe_mac_82598EB:
727 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
728 break;
729 default:
730 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
731 }
732 hwstats->lxoffrxc += data;
c84d324c 733
943561d3
AD		 734 /* refill credits (no tx hang) if we received xoff */
735 if (!data)
c84d324c 736 return;
943561d3
AD		 737
738 for (i = 0; i < adapter->num_tx_queues; i++)
739 clear_bit(__IXGBE_HANG_CHECK_ARMED,
740 &adapter->tx_ring[i]->state);
741}
742
743static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
744{
745 struct ixgbe_hw *hw = &adapter->hw;
746 struct ixgbe_hw_stats *hwstats = &adapter->stats;
747 u32 xoff[8] = {0};
2afaa00d 748 u8 tc;
943561d3
AD		 749 int i;
750 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
751
752 if (adapter->ixgbe_ieee_pfc)
753 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
754
755 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
756 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 757 return;
943561d3 758 }
c84d324c
JF		 759
760 /* update stats for each tc, only valid with PFC enabled */
761 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 762 u32 pxoffrxc;
763
c84d324c
JF		 764 switch (hw->mac.type) {
765 case ixgbe_mac_82598EB:
2afaa00d 766 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 767 break;
c84d324c 768 default:
2afaa00d 769 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 770 }
2afaa00d
PN		 771 hwstats->pxoffrxc[i] += pxoffrxc;
772 /* Get the TC for given UP */
773 tc = netdev_get_prio_tc_map(adapter->netdev, i);
774 xoff[tc] += pxoffrxc;
c84d324c
JF		 775 }
776
777 /* disarm tx queues that have received xoff frames */
778 for (i = 0; i < adapter->num_tx_queues; i++) {
779 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 780
2afaa00d 781 tc = tx_ring->dcb_tc;
c84d324c
JF		 782 if (xoff[tc])
783 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 784 }
26f23d82
YZ		 785}
786
c84d324c 787static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 788{
7d7ce682 789 return ring->stats.packets;
c84d324c
JF		 790}
791
792static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
793{
794 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 795 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 796
c84d324c
JF		 797 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
798 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
799
800 if (head != tail)
801 return (head < tail) ?
802 tail - head : (tail + ring->count - head);
803
804 return 0;
805}
806
807static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
808{
809 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
810 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
811 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
812 bool ret = false;
813
7d637bcc 814 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 815
816 /*
817 * Check for a hung queue, but be thorough. This verifies
818 * that a transmit has been completed since the previous
819 * check AND there is at least one packet pending. The
820 * ARMED bit is set to indicate a potential hang. The
821 * bit is cleared if a pause frame is received to remove
822 * false hang detection due to PFC or 802.3x frames. By
823 * requiring this to fail twice we avoid races with
824 * pfc clearing the ARMED bit and conditions where we
825 * run the check_tx_hang logic with a transmit completion
826 * pending but without time to complete it yet.
827 */
828 if ((tx_done_old == tx_done) && tx_pending) {
829 /* make sure it is true for two checks in a row */
830 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
831 &tx_ring->state);
832 } else {
833 /* update completed stats and continue */
834 tx_ring->tx_stats.tx_done_old = tx_done;
835 /* reset the countdown */
836 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 837 }
838
c84d324c 839 return ret;
9a799d71
AK		 840}
841
c83c6cbd
AD		 842/**
843 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
844 * @adapter: driver private struct
845 **/
846static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
847{
848
849 /* Do the reset outside of interrupt context */
850 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
851 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 852 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 853 ixgbe_service_event_schedule(adapter);
854 }
855}
e01c31a5 856
9a799d71
AK		 857/**
858 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 859 * @q_vector: structure containing interrupt and ring information
e01c31a5 860 * @tx_ring: tx ring to clean
9a799d71 861 **/
fe49f04a 862static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 863 struct ixgbe_ring *tx_ring)
9a799d71 864{
fe49f04a 865 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 866 struct ixgbe_tx_buffer *tx_buffer;
867 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 868 unsigned int total_bytes = 0, total_packets = 0;
59224555 869 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 870 unsigned int i = tx_ring->next_to_clean;
871
872 if (test_bit(__IXGBE_DOWN, &adapter->state))
873 return true;
9a799d71 874
d3d00239 875 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 876 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 877 i -= tx_ring->count;
12207e49 878
729739b7 879 do {
d3d00239
AD		 880 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
881
882 /* if next_to_watch is not set then there is no work pending */
883 if (!eop_desc)
884 break;
885
7f83a9e6 886 /* prevent any other reads prior to eop_desc */
7e63bf49 887 read_barrier_depends();
7f83a9e6 888
d3d00239
AD		 889 /* if DD is not set pending work has not been completed */
890 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
891 break;
8ad494b0 892
d3d00239
AD		 893 /* clear next_to_watch to prevent false hangs */
894 tx_buffer->next_to_watch = NULL;
8ad494b0 895
091a6246
AD		 896 /* update the statistics for this packet */
897 total_bytes += tx_buffer->bytecount;
898 total_packets += tx_buffer->gso_segs;
899
fd0db0ed
AD		 900 /* free the skb */
901 dev_kfree_skb_any(tx_buffer->skb);
902
729739b7
AD		 903 /* unmap skb header data */
904 dma_unmap_single(tx_ring->dev,
905 dma_unmap_addr(tx_buffer, dma),
906 dma_unmap_len(tx_buffer, len),
907 DMA_TO_DEVICE);
908
fd0db0ed
AD		 909 /* clear tx_buffer data */
910 tx_buffer->skb = NULL;
729739b7 911 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 912
729739b7
AD		 913 /* unmap remaining buffers */
914 while (tx_desc != eop_desc) {
d3d00239
AD		 915 tx_buffer++;
916 tx_desc++;
8ad494b0 917 i++;
729739b7
AD		 918 if (unlikely(!i)) {
919 i -= tx_ring->count;
d3d00239 920 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 921 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 922 }
e01c31a5 923
729739b7
AD		 924 /* unmap any remaining paged data */
925 if (dma_unmap_len(tx_buffer, len)) {
926 dma_unmap_page(tx_ring->dev,
927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
929 DMA_TO_DEVICE);
930 dma_unmap_len_set(tx_buffer, len, 0);
931 }
932 }
933
934 /* move us one more past the eop_desc for start of next pkt */
935 tx_buffer++;
936 tx_desc++;
937 i++;
938 if (unlikely(!i)) {
939 i -= tx_ring->count;
940 tx_buffer = tx_ring->tx_buffer_info;
941 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
942 }
943
944 /* issue prefetch for next Tx descriptor */
945 prefetch(tx_desc);
12207e49 946
729739b7
AD		 947 /* update budget accounting */
948 budget--;
949 } while (likely(budget));
950
951 i += tx_ring->count;
9a799d71 952 tx_ring->next_to_clean = i;
d3d00239 953 u64_stats_update_begin(&tx_ring->syncp);
b953799e 954 tx_ring->stats.bytes += total_bytes;
bd198058 955 tx_ring->stats.packets += total_packets;
d3d00239 956 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 957 q_vector->tx.total_bytes += total_bytes;
958 q_vector->tx.total_packets += total_packets;
b953799e 959
c84d324c
JF		 960 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
961 /* schedule immediate reset if we believe we hung */
962 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 963 e_err(drv, "Detected Tx Unit Hang\n"
964 " Tx Queue <%d>\n"
965 " TDH, TDT <%x>, <%x>\n"
966 " next_to_use <%x>\n"
967 " next_to_clean <%x>\n"
968 "tx_buffer_info[next_to_clean]\n"
969 " time_stamp <%lx>\n"
970 " jiffies <%lx>\n",
971 tx_ring->queue_index,
972 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
973 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 974 tx_ring->next_to_use, i,
975 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 976
977 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
978
979 e_info(probe,
980 "tx hang %d detected on queue %d, resetting adapter\n",
981 adapter->tx_timeout_count + 1, tx_ring->queue_index);
982
b953799e 983 /* schedule immediate reset if we believe we hung */
c83c6cbd 984 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 985
986 /* the adapter is about to reset, no point in enabling stuff */
59224555 987 return true;
b953799e 988 }
9a799d71 989
b2d96e0a
AD		 990 netdev_tx_completed_queue(txring_txq(tx_ring),
991 total_packets, total_bytes);
992
e092be60 993#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 994 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 995 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 996 /* Make sure that anybody stopping the queue after this
997 * sees the new next_to_clean.
998 */
999 smp_mb();
729739b7
AD		 1000 if (__netif_subqueue_stopped(tx_ring->netdev,
1001 tx_ring->queue_index)
1002 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1003 netif_wake_subqueue(tx_ring->netdev,
1004 tx_ring->queue_index);
5b7da515 1005 ++tx_ring->tx_stats.restart_queue;
30eba97a 1006 }
e092be60 1007 }
9a799d71 1008
59224555 1009 return !!budget;
9a799d71
AK		 1010}
1011
5dd2d332 1012#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1013static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1014 struct ixgbe_ring *tx_ring,
33cf09c9 1015 int cpu)
bd0362dd 1016{
33cf09c9 1017 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1018 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1019 u16 reg_offset;
33cf09c9 1020
33cf09c9
AD		 1021 switch (hw->mac.type) {
1022 case ixgbe_mac_82598EB:
bdda1a61 1023 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1024 break;
1025 case ixgbe_mac_82599EB:
b93a2226 1026 case ixgbe_mac_X540:
bdda1a61
AD		 1027 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1028 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1029 break;
1030 default:
bdda1a61
AD		 1031 /* for unknown hardware do not write register */
1032 return;
bd0362dd 1033 }
bdda1a61
AD		 1034
1035 /*
1036 * We can enable relaxed ordering for reads, but not writes when
1037 * DCA is enabled. This is due to a known issue in some chipsets
1038 * which will cause the DCA tag to be cleared.
1039 */
1040 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1041 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1042 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1043
1044 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1045}
1046
bdda1a61
AD		 1047static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1048 struct ixgbe_ring *rx_ring,
33cf09c9 1049 int cpu)
bd0362dd 1050{
33cf09c9 1051 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1052 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1053 u8 reg_idx = rx_ring->reg_idx;
1054
33cf09c9
AD		 1055
1056 switch (hw->mac.type) {
33cf09c9 1057 case ixgbe_mac_82599EB:
b93a2226 1058 case ixgbe_mac_X540:
bdda1a61 1059 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1060 break;
1061 default:
1062 break;
1063 }
bdda1a61
AD		 1064
1065 /*
1066 * We can enable relaxed ordering for reads, but not writes when
1067 * DCA is enabled. This is due to a known issue in some chipsets
1068 * which will cause the DCA tag to be cleared.
1069 */
1070 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1071 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1072
1073 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1074}
1075
1076static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1077{
1078 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1079 struct ixgbe_ring *ring;
bd0362dd 1080 int cpu = get_cpu();
bd0362dd 1081
33cf09c9
AD		 1082 if (q_vector->cpu == cpu)
1083 goto out_no_update;
1084
a557928e 1085 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1086 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1087
a557928e 1088 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1089 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1090
1091 q_vector->cpu = cpu;
1092out_no_update:
bd0362dd
JC		 1093 put_cpu();
1094}
1095
1096static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1097{
1098 int i;
1099
1100 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1101 return;
1102
e35ec126
AD		 1103 /* always use CB2 mode, difference is masked in the CB driver */
1104 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1105
49c7ffbe 1106 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1107 adapter->q_vector[i]->cpu = -1;
1108 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1109 }
1110}
1111
1112static int __ixgbe_notify_dca(struct device *dev, void *data)
1113{
c60fbb00 1114 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1115 unsigned long event = *(unsigned long *)data;
1116
2a72c31e 1117 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1118 return 0;
1119
bd0362dd
JC		 1120 switch (event) {
1121 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1122 /* if we're already enabled, don't do it again */
1123 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1124 break;
652f093f 1125 if (dca_add_requester(dev) == 0) {
96b0e0f6 1126 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1127 ixgbe_setup_dca(adapter);
1128 break;
1129 }
1130 /* Fall Through since DCA is disabled. */
1131 case DCA_PROVIDER_REMOVE:
1132 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1133 dca_remove_requester(dev);
1134 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1135 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1136 }
1137 break;
1138 }
1139
652f093f 1140 return 0;
bd0362dd 1141}
67a74ee2 1142
bdda1a61 1143#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1144static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1145 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1146 struct sk_buff *skb)
1147{
8a0da21b
AD		 1148 if (ring->netdev->features & NETIF_F_RXHASH)
1149 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1150}
1151
f800326d 1152#ifdef IXGBE_FCOE
ff886dfc
AD		 1153/**
1154 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1155 * @ring: structure containing ring specific data
ff886dfc
AD		 1156 * @rx_desc: advanced rx descriptor
1157 *
1158 * Returns : true if it is FCoE pkt
1159 */
57efd44c 1160static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1161 union ixgbe_adv_rx_desc *rx_desc)
1162{
1163 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1164
57efd44c 1165 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1166 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1167 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1168 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1169}
1170
f800326d 1171#endif /* IXGBE_FCOE */
e59bd25d
AV		 1172/**
1173 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1174 * @ring: structure containing ring specific data
1175 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1176 * @skb: skb currently being received and modified
1177 **/
8a0da21b 1178static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1179 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1180 struct sk_buff *skb)
9a799d71 1181{
8a0da21b 1182 skb_checksum_none_assert(skb);
9a799d71 1183
712744be 1184 /* Rx csum disabled */
8a0da21b 1185 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1186 return;
e59bd25d
AV		 1187
1188 /* if IP and error */
f56e0cb1
AD		 1189 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1190 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1191 ring->rx_stats.csum_err++;
9a799d71
AK		 1192 return;
1193 }
e59bd25d 1194
f56e0cb1 1195 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1196 return;
1197
f56e0cb1 1198 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1199 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1200
1201 /*
1202 * 82599 errata, UDP frames with a 0 checksum can be marked as
1203 * checksum errors.
1204 */
8a0da21b
AD		 1205 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1206 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1207 return;
1208
8a0da21b 1209 ring->rx_stats.csum_err++;
e59bd25d
AV		 1210 return;
1211 }
1212
9a799d71 1213 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1214 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1215}
1216
84ea2591 1217static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1218{
f56e0cb1 1219 rx_ring->next_to_use = val;
f800326d
AD		 1220
1221 /* update next to alloc since we have filled the ring */
1222 rx_ring->next_to_alloc = val;
e8e26350
PW		 1223 /*
1224 * Force memory writes to complete before letting h/w
1225 * know there are new descriptors to fetch. (Only
1226 * applicable for weak-ordered memory model archs,
1227 * such as IA-64).
1228 */
1229 wmb();
84ea2591 1230 writel(val, rx_ring->tail);
e8e26350
PW		 1231}
1232
f990b79b
AD		 1233static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1234 struct ixgbe_rx_buffer *bi)
1235{
1236 struct page *page = bi->page;
f800326d 1237 dma_addr_t dma = bi->dma;
f990b79b 1238
f800326d
AD		 1239 /* since we are recycling buffers we should seldom need to alloc */
1240 if (likely(dma))
f990b79b
AD		 1241 return true;
1242
f800326d
AD		 1243 /* alloc new page for storage */
1244 if (likely(!page)) {
0614002b
MG		 1245 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1246 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1247 if (unlikely(!page)) {
1248 rx_ring->rx_stats.alloc_rx_page_failed++;
1249 return false;
1250 }
f800326d 1251 bi->page = page;
f990b79b
AD		 1252 }
1253
f800326d
AD		 1254 /* map page for use */
1255 dma = dma_map_page(rx_ring->dev, page, 0,
1256 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1257
1258 /*
1259 * if mapping failed free memory back to system since
1260 * there isn't much point in holding memory we can't use
1261 */
1262 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1263 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1264 bi->page = NULL;
f990b79b 1265
f990b79b
AD		 1266 rx_ring->rx_stats.alloc_rx_page_failed++;
1267 return false;
1268 }
1269
f800326d 1270 bi->dma = dma;
afaa9459 1271 bi->page_offset = 0;
f800326d 1272
f990b79b
AD		 1273 return true;
1274}
1275
9a799d71 1276/**
f990b79b 1277 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1278 * @rx_ring: ring to place buffers on
1279 * @cleaned_count: number of buffers to replace
9a799d71 1280 **/
fc77dc3c 1281void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1282{
9a799d71 1283 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1284 struct ixgbe_rx_buffer *bi;
d5f398ed 1285 u16 i = rx_ring->next_to_use;
9a799d71 1286
f800326d
AD		 1287 /* nothing to do */
1288 if (!cleaned_count)
fc77dc3c
AD		 1289 return;
1290
e4f74028 1291 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1292 bi = &rx_ring->rx_buffer_info[i];
1293 i -= rx_ring->count;
9a799d71 1294
f800326d
AD		 1295 do {
1296 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1297 break;
d5f398ed 1298
f800326d
AD		 1299 /*
1300 * Refresh the desc even if buffer_addrs didn't change
1301 * because each write-back erases this info.
1302 */
1303 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1304
f990b79b
AD		 1305 rx_desc++;
1306 bi++;
9a799d71 1307 i++;
f990b79b 1308 if (unlikely(!i)) {
e4f74028 1309 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1310 bi = rx_ring->rx_buffer_info;
1311 i -= rx_ring->count;
1312 }
1313
1314 /* clear the hdr_addr for the next_to_use descriptor */
1315 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1316
1317 cleaned_count--;
1318 } while (cleaned_count);
7c6e0a43 1319
f990b79b
AD		 1320 i += rx_ring->count;
1321
f56e0cb1 1322 if (rx_ring->next_to_use != i)
84ea2591 1323 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1324}
1325
1d2024f6
AD		 1326/**
1327 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1328 * @data: pointer to the start of the headers
1329 * @max_len: total length of section to find headers in
1330 *
1331 * This function is meant to determine the length of headers that will
1332 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1333 * motivation of doing this is to only perform one pull for IPv4 TCP
1334 * packets so that we can do basic things like calculating the gso_size
1335 * based on the average data per packet.
1336 **/
1337static unsigned int ixgbe_get_headlen(unsigned char *data,
1338 unsigned int max_len)
1339{
1340 union {
1341 unsigned char *network;
1342 /* l2 headers */
1343 struct ethhdr *eth;
1344 struct vlan_hdr *vlan;
1345 /* l3 headers */
1346 struct iphdr *ipv4;
a048b40e 1347 struct ipv6hdr *ipv6;
1d2024f6
AD		 1348 } hdr;
1349 __be16 protocol;
1350 u8 nexthdr = 0; /* default to not TCP */
1351 u8 hlen;
1352
1353 /* this should never happen, but better safe than sorry */
1354 if (max_len < ETH_HLEN)
1355 return max_len;
1356
1357 /* initialize network frame pointer */
1358 hdr.network = data;
1359
1360 /* set first protocol and move network header forward */
1361 protocol = hdr.eth->h_proto;
1362 hdr.network += ETH_HLEN;
1363
1364 /* handle any vlan tag if present */
1365 if (protocol == __constant_htons(ETH_P_8021Q)) {
1366 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1367 return max_len;
1368
1369 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1370 hdr.network += VLAN_HLEN;
1371 }
1372
1373 /* handle L3 protocols */
1374 if (protocol == __constant_htons(ETH_P_IP)) {
1375 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1376 return max_len;
1377
1378 /* access ihl as a u8 to avoid unaligned access on ia64 */
1379 hlen = (hdr.network[0] & 0x0F) << 2;
1380
1381 /* verify hlen meets minimum size requirements */
1382 if (hlen < sizeof(struct iphdr))
1383 return hdr.network - data;
1384
ed83da12 1385 /* record next protocol if header is present */
20967f42 1386 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1387 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1388 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1389 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1390 return max_len;
1391
1392 /* record next protocol */
1393 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1394 hlen = sizeof(struct ipv6hdr);
f800326d 1395#ifdef IXGBE_FCOE
1d2024f6
AD		 1396 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1397 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1398 return max_len;
ed83da12 1399 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1400#endif
1401 } else {
1402 return hdr.network - data;
1403 }
1404
ed83da12
AD		 1405 /* relocate pointer to start of L4 header */
1406 hdr.network += hlen;
1407
a048b40e 1408 /* finally sort out TCP/UDP */
1d2024f6
AD		 1409 if (nexthdr == IPPROTO_TCP) {
1410 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1411 return max_len;
1412
1413 /* access doff as a u8 to avoid unaligned access on ia64 */
1414 hlen = (hdr.network[12] & 0xF0) >> 2;
1415
1416 /* verify hlen meets minimum size requirements */
1417 if (hlen < sizeof(struct tcphdr))
1418 return hdr.network - data;
1419
1420 hdr.network += hlen;
a048b40e
AD		 1421 } else if (nexthdr == IPPROTO_UDP) {
1422 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1423 return max_len;
1424
1425 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1426 }
1427
1428 /*
1429 * If everything has gone correctly hdr.network should be the
1430 * data section of the packet and will be the end of the header.
1431 * If not then it probably represents the end of the last recognized
1432 * header.
1433 */
1434 if ((hdr.network - data) < max_len)
1435 return hdr.network - data;
1436 else
1437 return max_len;
1438}
1439
1d2024f6
AD		 1440static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1441 struct sk_buff *skb)
1442{
f800326d 1443 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1444
1445 /* set gso_size to avoid messing up TCP MSS */
1446 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1447 IXGBE_CB(skb)->append_cnt);
96be80ab 1448 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1449}
1450
1451static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1452 struct sk_buff *skb)
1453{
1454 /* if append_cnt is 0 then frame is not RSC */
1455 if (!IXGBE_CB(skb)->append_cnt)
1456 return;
1457
1458 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1459 rx_ring->rx_stats.rsc_flush++;
1460
1461 ixgbe_set_rsc_gso_size(rx_ring, skb);
1462
1463 /* gso_size is computed using append_cnt so always clear it last */
1464 IXGBE_CB(skb)->append_cnt = 0;
1465}
1466
8a0da21b
AD		 1467/**
1468 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1469 * @rx_ring: rx descriptor ring packet is being transacted on
1470 * @rx_desc: pointer to the EOP Rx descriptor
1471 * @skb: pointer to current skb being populated
f8212f97 1472 *
8a0da21b
AD		 1473 * This function checks the ring, descriptor, and packet information in
1474 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1475 * other fields within the skb.
f8212f97 1476 **/
8a0da21b
AD		 1477static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1478 union ixgbe_adv_rx_desc *rx_desc,
1479 struct sk_buff *skb)
f8212f97 1480{
43e95f11
JF		 1481 struct net_device *dev = rx_ring->netdev;
1482
8a0da21b
AD		 1483 ixgbe_update_rsc_stats(rx_ring, skb);
1484
1485 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1486
8a0da21b
AD		 1487 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1488
6cb562d6 1489 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1490
f646968f 1491 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1492 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1493 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1494 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1495 }
1496
8a0da21b 1497 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1498
43e95f11 1499 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1500}
1501
8a0da21b
AD		 1502static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1503 struct sk_buff *skb)
aa80175a 1504{
8a0da21b
AD		 1505 struct ixgbe_adapter *adapter = q_vector->adapter;
1506
5a85e737
ET		 1507 if (ixgbe_qv_ll_polling(q_vector))
1508 netif_receive_skb(skb);
1509 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1510 napi_gro_receive(&q_vector->napi, skb);
1511 else
1512 netif_rx(skb);
aa80175a 1513}
43634e82 1514
f800326d
AD		 1515/**
1516 * ixgbe_is_non_eop - process handling of non-EOP buffers
1517 * @rx_ring: Rx ring being processed
1518 * @rx_desc: Rx descriptor for current buffer
1519 * @skb: Current socket buffer containing buffer in progress
1520 *
1521 * This function updates next to clean. If the buffer is an EOP buffer
1522 * this function exits returning false, otherwise it will place the
1523 * sk_buff in the next buffer to be chained and return true indicating
1524 * that this is in fact a non-EOP buffer.
1525 **/
1526static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1527 union ixgbe_adv_rx_desc *rx_desc,
1528 struct sk_buff *skb)
1529{
1530 u32 ntc = rx_ring->next_to_clean + 1;
1531
1532 /* fetch, update, and store next to clean */
1533 ntc = (ntc < rx_ring->count) ? ntc : 0;
1534 rx_ring->next_to_clean = ntc;
1535
1536 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1537
5a02cbd1
AD		 1538 /* update RSC append count if present */
1539 if (ring_is_rsc_enabled(rx_ring)) {
1540 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1541 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1542
1543 if (unlikely(rsc_enabled)) {
1544 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1545
1546 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1547 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1548
5a02cbd1
AD		 1549 /* update ntc based on RSC value */
1550 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1551 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1552 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1553 }
f800326d
AD		 1554 }
1555
5a02cbd1
AD		 1556 /* if we are the last buffer then there is nothing else to do */
1557 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1558 return false;
1559
f800326d
AD		 1560 /* place skb in next buffer to be received */
1561 rx_ring->rx_buffer_info[ntc].skb = skb;
1562 rx_ring->rx_stats.non_eop_descs++;
1563
1564 return true;
1565}
1566
19861ce2
AD		 1567/**
1568 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1569 * @rx_ring: rx descriptor ring packet is being transacted on
1570 * @skb: pointer to current skb being adjusted
1571 *
1572 * This function is an ixgbe specific version of __pskb_pull_tail. The
1573 * main difference between this version and the original function is that
1574 * this function can make several assumptions about the state of things
1575 * that allow for significant optimizations versus the standard function.
1576 * As a result we can do things like drop a frag and maintain an accurate
1577 * truesize for the skb.
1578 */
1579static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1580 struct sk_buff *skb)
1581{
1582 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1583 unsigned char *va;
1584 unsigned int pull_len;
1585
1586 /*
1587 * it is valid to use page_address instead of kmap since we are
1588 * working with pages allocated out of the lomem pool per
1589 * alloc_page(GFP_ATOMIC)
1590 */
1591 va = skb_frag_address(frag);
1592
1593 /*
1594 * we need the header to contain the greater of either ETH_HLEN or
1595 * 60 bytes if the skb->len is less than 60 for skb_pad.
1596 */
cf3fe7ac 1597 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1598
1599 /* align pull length to size of long to optimize memcpy performance */
1600 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1601
1602 /* update all of the pointers */
1603 skb_frag_size_sub(frag, pull_len);
1604 frag->page_offset += pull_len;
1605 skb->data_len -= pull_len;
1606 skb->tail += pull_len;
19861ce2
AD		 1607}
1608
42073d91
AD		 1609/**
1610 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1611 * @rx_ring: rx descriptor ring packet is being transacted on
1612 * @skb: pointer to current skb being updated
1613 *
1614 * This function provides a basic DMA sync up for the first fragment of an
1615 * skb. The reason for doing this is that the first fragment cannot be
1616 * unmapped until we have reached the end of packet descriptor for a buffer
1617 * chain.
1618 */
1619static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1620 struct sk_buff *skb)
1621{
1622 /* if the page was released unmap it, else just sync our portion */
1623 if (unlikely(IXGBE_CB(skb)->page_released)) {
1624 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1625 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1626 IXGBE_CB(skb)->page_released = false;
1627 } else {
1628 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1629
1630 dma_sync_single_range_for_cpu(rx_ring->dev,
1631 IXGBE_CB(skb)->dma,
1632 frag->page_offset,
1633 ixgbe_rx_bufsz(rx_ring),
1634 DMA_FROM_DEVICE);
1635 }
1636 IXGBE_CB(skb)->dma = 0;
1637}
1638
f800326d
AD		 1639/**
1640 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1641 * @rx_ring: rx descriptor ring packet is being transacted on
1642 * @rx_desc: pointer to the EOP Rx descriptor
1643 * @skb: pointer to current skb being fixed
1644 *
1645 * Check for corrupted packet headers caused by senders on the local L2
1646 * embedded NIC switch not setting up their Tx Descriptors right. These
1647 * should be very rare.
1648 *
1649 * Also address the case where we are pulling data in on pages only
1650 * and as such no data is present in the skb header.
1651 *
1652 * In addition if skb is not at least 60 bytes we need to pad it so that
1653 * it is large enough to qualify as a valid Ethernet frame.
1654 *
1655 * Returns true if an error was encountered and skb was freed.
1656 **/
1657static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1658 union ixgbe_adv_rx_desc *rx_desc,
1659 struct sk_buff *skb)
1660{
f800326d 1661 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1662
1663 /* verify that the packet does not have any known errors */
1664 if (unlikely(ixgbe_test_staterr(rx_desc,
1665 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1666 !(netdev->features & NETIF_F_RXALL))) {
1667 dev_kfree_skb_any(skb);
1668 return true;
1669 }
1670
19861ce2 1671 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1672 if (skb_is_nonlinear(skb))
1673 ixgbe_pull_tail(rx_ring, skb);
f800326d 1674
57efd44c
AD		 1675#ifdef IXGBE_FCOE
1676 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1677 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1678 return false;
1679
1680#endif
f800326d
AD		 1681 /* if skb_pad returns an error the skb was freed */
1682 if (unlikely(skb->len < 60)) {
1683 int pad_len = 60 - skb->len;
1684
1685 if (skb_pad(skb, pad_len))
1686 return true;
1687 __skb_put(skb, pad_len);
1688 }
1689
1690 return false;
1691}
1692
f800326d
AD		 1693/**
1694 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1695 * @rx_ring: rx descriptor ring to store buffers on
1696 * @old_buff: donor buffer to have page reused
1697 *
0549ae20 1698 * Synchronizes page for reuse by the adapter
f800326d
AD		 1699 **/
1700static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1701 struct ixgbe_rx_buffer *old_buff)
1702{
1703 struct ixgbe_rx_buffer *new_buff;
1704 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1705
1706 new_buff = &rx_ring->rx_buffer_info[nta];
1707
1708 /* update, and store next to alloc */
1709 nta++;
1710 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1711
1712 /* transfer page from old buffer to new buffer */
1713 new_buff->page = old_buff->page;
1714 new_buff->dma = old_buff->dma;
0549ae20 1715 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1716
1717 /* sync the buffer for use by the device */
1718 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1719 new_buff->page_offset,
1720 ixgbe_rx_bufsz(rx_ring),
f800326d 1721 DMA_FROM_DEVICE);
f800326d
AD		 1722}
1723
1724/**
1725 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1726 * @rx_ring: rx descriptor ring to transact packets on
1727 * @rx_buffer: buffer containing page to add
1728 * @rx_desc: descriptor containing length of buffer written by hardware
1729 * @skb: sk_buff to place the data into
1730 *
0549ae20
AD		 1731 * This function will add the data contained in rx_buffer->page to the skb.
1732 * This is done either through a direct copy if the data in the buffer is
1733 * less than the skb header size, otherwise it will just attach the page as
1734 * a frag to the skb.
1735 *
1736 * The function will then update the page offset if necessary and return
1737 * true if the buffer can be reused by the adapter.
f800326d 1738 **/
0549ae20 1739static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1740 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1741 union ixgbe_adv_rx_desc *rx_desc,
1742 struct sk_buff *skb)
f800326d 1743{
0549ae20
AD		 1744 struct page *page = rx_buffer->page;
1745 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1746#if (PAGE_SIZE < 8192)
0549ae20 1747 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1748#else
1749 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1750 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1751 ixgbe_rx_bufsz(rx_ring);
1752#endif
0549ae20 1753
cf3fe7ac
AD		 1754 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1755 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1756
1757 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1758
1759 /* we can reuse buffer as-is, just make sure it is local */
1760 if (likely(page_to_nid(page) == numa_node_id()))
1761 return true;
1762
1763 /* this page cannot be reused so discard it */
1764 put_page(page);
1765 return false;
1766 }
1767
0549ae20
AD		 1768 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1769 rx_buffer->page_offset, size, truesize);
1770
09816fbe
AD		 1771 /* avoid re-using remote pages */
1772 if (unlikely(page_to_nid(page) != numa_node_id()))
1773 return false;
1774
1775#if (PAGE_SIZE < 8192)
1776 /* if we are only owner of page we can reuse it */
1777 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1778 return false;
1779
1780 /* flip page offset to other buffer */
1781 rx_buffer->page_offset ^= truesize;
1782
09816fbe
AD		 1783 /*
1784 * since we are the only owner of the page and we need to
1785 * increment it, just set the value to 2 in order to avoid
1786 * an unecessary locked operation
1787 */
1788 atomic_set(&page->_count, 2);
1789#else
1790 /* move offset up to the next cache line */
1791 rx_buffer->page_offset += truesize;
1792
1793 if (rx_buffer->page_offset > last_offset)
1794 return false;
1795
0549ae20
AD		 1796 /* bump ref count on page before it is given to the stack */
1797 get_page(page);
09816fbe 1798#endif
0549ae20
AD		 1799
1800 return true;
f800326d
AD		 1801}
1802
18806c9e
AD		 1803static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1804 union ixgbe_adv_rx_desc *rx_desc)
1805{
1806 struct ixgbe_rx_buffer *rx_buffer;
1807 struct sk_buff *skb;
1808 struct page *page;
1809
1810 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1811 page = rx_buffer->page;
1812 prefetchw(page);
1813
1814 skb = rx_buffer->skb;
1815
1816 if (likely(!skb)) {
1817 void *page_addr = page_address(page) +
1818 rx_buffer->page_offset;
1819
1820 /* prefetch first cache line of first page */
1821 prefetch(page_addr);
1822#if L1_CACHE_BYTES < 128
1823 prefetch(page_addr + L1_CACHE_BYTES);
1824#endif
1825
1826 /* allocate a skb to store the frags */
1827 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1828 IXGBE_RX_HDR_SIZE);
1829 if (unlikely(!skb)) {
1830 rx_ring->rx_stats.alloc_rx_buff_failed++;
1831 return NULL;
1832 }
1833
1834 /*
1835 * we will be copying header into skb->data in
1836 * pskb_may_pull so it is in our interest to prefetch
1837 * it now to avoid a possible cache miss
1838 */
1839 prefetchw(skb->data);
1840
1841 /*
1842 * Delay unmapping of the first packet. It carries the
1843 * header information, HW may still access the header
1844 * after the writeback. Only unmap it when EOP is
1845 * reached
1846 */
1847 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1848 goto dma_sync;
1849
1850 IXGBE_CB(skb)->dma = rx_buffer->dma;
1851 } else {
1852 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1853 ixgbe_dma_sync_frag(rx_ring, skb);
1854
1855dma_sync:
1856 /* we are reusing so sync this buffer for CPU use */
1857 dma_sync_single_range_for_cpu(rx_ring->dev,
1858 rx_buffer->dma,
1859 rx_buffer->page_offset,
1860 ixgbe_rx_bufsz(rx_ring),
1861 DMA_FROM_DEVICE);
1862 }
1863
1864 /* pull page into skb */
1865 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1866 /* hand second half of page back to the ring */
1867 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1868 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1869 /* the page has been released from the ring */
1870 IXGBE_CB(skb)->page_released = true;
1871 } else {
1872 /* we are not reusing the buffer so unmap it */
1873 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1874 ixgbe_rx_pg_size(rx_ring),
1875 DMA_FROM_DEVICE);
1876 }
1877
1878 /* clear contents of buffer_info */
1879 rx_buffer->skb = NULL;
1880 rx_buffer->dma = 0;
1881 rx_buffer->page = NULL;
1882
1883 return skb;
f800326d
AD		 1884}
1885
1886/**
1887 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1888 * @q_vector: structure containing interrupt and ring information
1889 * @rx_ring: rx descriptor ring to transact packets on
1890 * @budget: Total limit on number of packets to process
1891 *
1892 * This function provides a "bounce buffer" approach to Rx interrupt
1893 * processing. The advantage to this is that on systems that have
1894 * expensive overhead for IOMMU access this provides a means of avoiding
1895 * it by maintaining the mapping of the page to the syste.
1896 *
5a85e737 1897 * Returns amount of work completed
f800326d 1898 **/
5a85e737 1899static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1900 struct ixgbe_ring *rx_ring,
f4de00ed 1901 const int budget)
9a799d71 1902{
d2f4fbe2 1903 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1904#ifdef IXGBE_FCOE
f800326d 1905 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1906 int ddp_bytes;
1907 unsigned int mss = 0;
3d8fd385 1908#endif /* IXGBE_FCOE */
f800326d 1909 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1910
f800326d 1911 do {
f800326d
AD		 1912 union ixgbe_adv_rx_desc *rx_desc;
1913 struct sk_buff *skb;
f800326d
AD		 1914
1915 /* return some buffers to hardware, one at a time is too slow */
1916 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1917 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1918 cleaned_count = 0;
1919 }
1920
18806c9e 1921 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 1922
1923 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1924 break;
9a799d71 1925
f800326d
AD		 1926 /*
1927 * This memory barrier is needed to keep us from reading
1928 * any other fields out of the rx_desc until we know the
1929 * RXD_STAT_DD bit is set
1930 */
1931 rmb();
9a799d71 1932
18806c9e
AD		 1933 /* retrieve a buffer from the ring */
1934 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 1935
18806c9e
AD		 1936 /* exit if we failed to retrieve a buffer */
1937 if (!skb)
1938 break;
9a799d71 1939
9a799d71 1940 cleaned_count++;
f8212f97 1941
f800326d
AD		 1942 /* place incomplete frames back on ring for completion */
1943 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1944 continue;
c267fc16 1945
f800326d
AD		 1946 /* verify the packet layout is correct */
1947 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1948 continue;
9a799d71 1949
d2f4fbe2
AV		 1950 /* probably a little skewed due to removing CRC */
1951 total_rx_bytes += skb->len;
d2f4fbe2 1952
8a0da21b
AD		 1953 /* populate checksum, timestamp, VLAN, and protocol */
1954 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1955
332d4a7d
YZ		 1956#ifdef IXGBE_FCOE
1957 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1958 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1959 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 1960 /* include DDPed FCoE data */
1961 if (ddp_bytes > 0) {
1962 if (!mss) {
1963 mss = rx_ring->netdev->mtu -
1964 sizeof(struct fcoe_hdr) -
1965 sizeof(struct fc_frame_header) -
1966 sizeof(struct fcoe_crc_eof);
1967 if (mss > 512)
1968 mss &= ~511;
1969 }
1970 total_rx_bytes += ddp_bytes;
1971 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
1972 mss);
1973 }
63d635b2
AD		 1974 if (!ddp_bytes) {
1975 dev_kfree_skb_any(skb);
f800326d 1976 continue;
63d635b2 1977 }
3d8fd385 1978 }
f800326d 1979
332d4a7d 1980#endif /* IXGBE_FCOE */
8b80cda5 1981 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 1982 ixgbe_rx_skb(q_vector, skb);
9a799d71 1983
f800326d 1984 /* update budget accounting */
f4de00ed
AD		 1985 total_rx_packets++;
1986 } while (likely(total_rx_packets < budget));
9a799d71 1987
c267fc16
AD		 1988 u64_stats_update_begin(&rx_ring->syncp);
1989 rx_ring->stats.packets += total_rx_packets;
1990 rx_ring->stats.bytes += total_rx_bytes;
1991 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1992 q_vector->rx.total_packets += total_rx_packets;
1993 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1994
f800326d
AD		 1995 if (cleaned_count)
1996 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1997
5a85e737 1998 return total_rx_packets;
9a799d71
AK		 1999}
2000
5a85e737
ET		 2001#ifdef CONFIG_NET_LL_RX_POLL
2002/* must be called with local_bh_disable()d */
2003static int ixgbe_low_latency_recv(struct napi_struct *napi)
2004{
2005 struct ixgbe_q_vector *q_vector =
2006 container_of(napi, struct ixgbe_q_vector, napi);
2007 struct ixgbe_adapter *adapter = q_vector->adapter;
2008 struct ixgbe_ring *ring;
2009 int found = 0;
2010
2011 if (test_bit(__IXGBE_DOWN, &adapter->state))
2012 return LL_FLUSH_FAILED;
2013
2014 if (!ixgbe_qv_lock_poll(q_vector))
2015 return LL_FLUSH_BUSY;
2016
2017 ixgbe_for_each_ring(ring, q_vector->rx) {
2018 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
7e15b90f
ET		 2019#ifdef LL_EXTENDED_STATS
2020 if (found)
2021 ring->stats.cleaned += found;
2022 else
2023 ring->stats.misses++;
2024#endif
5a85e737
ET		 2025 if (found)
2026 break;
2027 }
2028
2029 ixgbe_qv_unlock_poll(q_vector);
2030
2031 return found;
2032}
2033#endif /* CONFIG_NET_LL_RX_POLL */
2034
9a799d71
AK		 2035/**
2036 * ixgbe_configure_msix - Configure MSI-X hardware
2037 * @adapter: board private structure
2038 *
2039 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2040 * interrupts.
2041 **/
2042static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2043{
021230d4 2044 struct ixgbe_q_vector *q_vector;
49c7ffbe 2045 int v_idx;
021230d4 2046 u32 mask;
9a799d71 2047
8e34d1aa
AD		 2048 /* Populate MSIX to EITR Select */
2049 if (adapter->num_vfs > 32) {
2050 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2051 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2052 }
2053
4df10466
JB		 2054 /*
2055 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2056 * corresponding register.
2057 */
49c7ffbe 2058 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2059 struct ixgbe_ring *ring;
7a921c93 2060 q_vector = adapter->q_vector[v_idx];
021230d4 2061
a557928e 2062 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2063 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2064
a557928e 2065 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2066 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2067
fe49f04a 2068 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2069 }
2070
bd508178
AD		 2071 switch (adapter->hw.mac.type) {
2072 case ixgbe_mac_82598EB:
e8e26350 2073 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2074 v_idx);
bd508178
AD		 2075 break;
2076 case ixgbe_mac_82599EB:
b93a2226 2077 case ixgbe_mac_X540:
e8e26350 2078 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2079 break;
bd508178
AD		 2080 default:
2081 break;
2082 }
021230d4
AV		 2083 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2084
41fb9248 2085 /* set up to autoclear timer, and the vectors */
021230d4 2086 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2087 mask &= ~(IXGBE_EIMS_OTHER |
2088 IXGBE_EIMS_MAILBOX |
2089 IXGBE_EIMS_LSC);
2090
021230d4 2091 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2092}
2093
f494e8fa
AV		 2094enum latency_range {
2095 lowest_latency = 0,
2096 low_latency = 1,
2097 bulk_latency = 2,
2098 latency_invalid = 255
2099};
2100
2101/**
2102 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2103 * @q_vector: structure containing interrupt and ring information
2104 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2105 *
2106 * Stores a new ITR value based on packets and byte
2107 * counts during the last interrupt. The advantage of per interrupt
2108 * computation is faster updates and more accurate ITR for the current
2109 * traffic pattern. Constants in this function were computed
2110 * based on theoretical maximum wire speed and thresholds were set based
2111 * on testing data as well as attempting to minimize response time
2112 * while increasing bulk throughput.
2113 * this functionality is controlled by the InterruptThrottleRate module
2114 * parameter (see ixgbe_param.c)
2115 **/
bd198058
AD		 2116static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2117 struct ixgbe_ring_container *ring_container)
f494e8fa 2118{
bd198058
AD		 2119 int bytes = ring_container->total_bytes;
2120 int packets = ring_container->total_packets;
2121 u32 timepassed_us;
621bd70e 2122 u64 bytes_perint;
bd198058 2123 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2124
2125 if (packets == 0)
bd198058 2126 return;
f494e8fa
AV		 2127
2128 /* simple throttlerate management
621bd70e
AD		 2129 * 0-10MB/s lowest (100000 ints/s)
2130 * 10-20MB/s low (20000 ints/s)
2131 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2132 */
2133 /* what was last interrupt timeslice? */
d5bf4f67 2134 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2135 if (timepassed_us == 0)
2136 return;
2137
f494e8fa
AV		 2138 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2139
2140 switch (itr_setting) {
2141 case lowest_latency:
621bd70e 2142 if (bytes_perint > 10)
bd198058 2143 itr_setting = low_latency;
f494e8fa
AV		 2144 break;
2145 case low_latency:
621bd70e 2146 if (bytes_perint > 20)
bd198058 2147 itr_setting = bulk_latency;
621bd70e 2148 else if (bytes_perint <= 10)
bd198058 2149 itr_setting = lowest_latency;
f494e8fa
AV		 2150 break;
2151 case bulk_latency:
621bd70e 2152 if (bytes_perint <= 20)
bd198058 2153 itr_setting = low_latency;
f494e8fa
AV		 2154 break;
2155 }
2156
bd198058
AD		 2157 /* clear work counters since we have the values we need */
2158 ring_container->total_bytes = 0;
2159 ring_container->total_packets = 0;
2160
2161 /* write updated itr to ring container */
2162 ring_container->itr = itr_setting;
f494e8fa
AV		 2163}
2164
509ee935
JB		 2165/**
2166 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2167 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2168 *
2169 * This function is made to be called by ethtool and by the driver
2170 * when it needs to update EITR registers at runtime. Hardware
2171 * specific quirks/differences are taken care of here.
2172 */
fe49f04a 2173void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2174{
fe49f04a 2175 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2176 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2177 int v_idx = q_vector->v_idx;
5d967eb7 2178 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2179
bd508178
AD		 2180 switch (adapter->hw.mac.type) {
2181 case ixgbe_mac_82598EB:
509ee935
JB		 2182 /* must write high and low 16 bits to reset counter */
2183 itr_reg |= (itr_reg << 16);
bd508178
AD		 2184 break;
2185 case ixgbe_mac_82599EB:
b93a2226 2186 case ixgbe_mac_X540:
509ee935
JB		 2187 /*
2188 * set the WDIS bit to not clear the timer bits and cause an
2189 * immediate assertion of the interrupt
2190 */
2191 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2192 break;
2193 default:
2194 break;
509ee935
JB		 2195 }
2196 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2197}
2198
bd198058 2199static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2200{
d5bf4f67 2201 u32 new_itr = q_vector->itr;
bd198058 2202 u8 current_itr;
f494e8fa 2203
bd198058
AD		 2204 ixgbe_update_itr(q_vector, &q_vector->tx);
2205 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2206
08c8833b 2207 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2208
2209 switch (current_itr) {
2210 /* counts and packets in update_itr are dependent on these numbers */
2211 case lowest_latency:
d5bf4f67 2212 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2213 break;
2214 case low_latency:
d5bf4f67 2215 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2216 break;
2217 case bulk_latency:
d5bf4f67 2218 new_itr = IXGBE_8K_ITR;
f494e8fa 2219 break;
bd198058
AD		 2220 default:
2221 break;
f494e8fa
AV		 2222 }
2223
d5bf4f67 2224 if (new_itr != q_vector->itr) {
fe49f04a 2225 /* do an exponential smoothing */
d5bf4f67
ET		 2226 new_itr = (10 * new_itr * q_vector->itr) /
2227 ((9 * new_itr) + q_vector->itr);
509ee935 2228
bd198058 2229 /* save the algorithm value here */
5d967eb7 2230 q_vector->itr = new_itr;
fe49f04a
AD		 2231
2232 ixgbe_write_eitr(q_vector);
f494e8fa 2233 }
f494e8fa
AV		 2234}
2235
119fc60a 2236/**
de88eeeb 2237 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2238 * @adapter: pointer to adapter
119fc60a 2239 **/
f0f9778d 2240static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2241{
119fc60a
MC		 2242 struct ixgbe_hw *hw = &adapter->hw;
2243 u32 eicr = adapter->interrupt_event;
2244
f0f9778d 2245 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2246 return;
2247
f0f9778d
AD		 2248 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2249 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2250 return;
2251
2252 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2253
7ca647bd 2254 switch (hw->device_id) {
f0f9778d
AD		 2255 case IXGBE_DEV_ID_82599_T3_LOM:
2256 /*
2257 * Since the warning interrupt is for both ports
2258 * we don't have to check if:
2259 * - This interrupt wasn't for our port.
2260 * - We may have missed the interrupt so always have to
2261 * check if we got a LSC
2262 */
2263 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2264 !(eicr & IXGBE_EICR_LSC))
2265 return;
2266
2267 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2268 u32 speed;
f0f9778d 2269 bool link_up = false;
7ca647bd 2270
3d292265 2271 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2272
f0f9778d
AD		 2273 if (link_up)
2274 return;
2275 }
2276
2277 /* Check if this is not due to overtemp */
2278 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2279 return;
2280
2281 break;
7ca647bd
JP		 2282 default:
2283 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2284 return;
7ca647bd 2285 break;
119fc60a 2286 }
7ca647bd
JP		 2287 e_crit(drv,
2288 "Network adapter has been stopped because it has over heated. "
2289 "Restart the computer. If the problem persists, "
2290 "power off the system and replace the adapter\n");
f0f9778d
AD		 2291
2292 adapter->interrupt_event = 0;
119fc60a
MC		 2293}
2294
0befdb3e
JB		 2295static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2296{
2297 struct ixgbe_hw *hw = &adapter->hw;
2298
2299 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2300 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2301 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2302 /* write to clear the interrupt */
2303 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2304 }
2305}
cf8280ee 2306
4f51bf70
JK		 2307static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2308{
2309 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2310 return;
2311
2312 switch (adapter->hw.mac.type) {
2313 case ixgbe_mac_82599EB:
2314 /*
2315 * Need to check link state so complete overtemp check
2316 * on service task
2317 */
2318 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2319 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2320 adapter->interrupt_event = eicr;
2321 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2322 ixgbe_service_event_schedule(adapter);
2323 return;
2324 }
2325 return;
2326 case ixgbe_mac_X540:
2327 if (!(eicr & IXGBE_EICR_TS))
2328 return;
2329 break;
2330 default:
2331 return;
2332 }
2333
2334 e_crit(drv,
2335 "Network adapter has been stopped because it has over heated. "
2336 "Restart the computer. If the problem persists, "
2337 "power off the system and replace the adapter\n");
2338}
2339
e8e26350
PW		 2340static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2341{
2342 struct ixgbe_hw *hw = &adapter->hw;
2343
73c4b7cd
AD		 2344 if (eicr & IXGBE_EICR_GPI_SDP2) {
2345 /* Clear the interrupt */
2346 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2347 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2348 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2349 ixgbe_service_event_schedule(adapter);
2350 }
73c4b7cd
AD		 2351 }
2352
e8e26350
PW		 2353 if (eicr & IXGBE_EICR_GPI_SDP1) {
2354 /* Clear the interrupt */
2355 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2356 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2357 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2358 ixgbe_service_event_schedule(adapter);
2359 }
e8e26350
PW		 2360 }
2361}
2362
cf8280ee
JB		 2363static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2364{
2365 struct ixgbe_hw *hw = &adapter->hw;
2366
2367 adapter->lsc_int++;
2368 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2369 adapter->link_check_timeout = jiffies;
2370 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2371 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2372 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2373 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2374 }
2375}
2376
fe49f04a
AD		 2377static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2378 u64 qmask)
2379{
2380 u32 mask;
bd508178 2381 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2382
bd508178
AD		 2383 switch (hw->mac.type) {
2384 case ixgbe_mac_82598EB:
fe49f04a 2385 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2386 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2387 break;
2388 case ixgbe_mac_82599EB:
b93a2226 2389 case ixgbe_mac_X540:
fe49f04a 2390 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2391 if (mask)
2392 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2393 mask = (qmask >> 32);
bd508178
AD		 2394 if (mask)
2395 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2396 break;
2397 default:
2398 break;
fe49f04a
AD		 2399 }
2400 /* skip the flush */
2401}
2402
2403static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2404 u64 qmask)
fe49f04a
AD		 2405{
2406 u32 mask;
bd508178 2407 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2408
bd508178
AD		 2409 switch (hw->mac.type) {
2410 case ixgbe_mac_82598EB:
fe49f04a 2411 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2412 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2413 break;
2414 case ixgbe_mac_82599EB:
b93a2226 2415 case ixgbe_mac_X540:
fe49f04a 2416 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2417 if (mask)
2418 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2419 mask = (qmask >> 32);
bd508178
AD		 2420 if (mask)
2421 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2422 break;
2423 default:
2424 break;
fe49f04a
AD		 2425 }
2426 /* skip the flush */
2427}
2428
021230d4 2429/**
2c4af694
AD		 2430 * ixgbe_irq_enable - Enable default interrupt generation settings
2431 * @adapter: board private structure
021230d4 2432 **/
2c4af694
AD		 2433static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2434 bool flush)
9a799d71 2435{
2c4af694 2436 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2437
2c4af694
AD		 2438 /* don't reenable LSC while waiting for link */
2439 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2440 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2441
2c4af694 2442 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2443 switch (adapter->hw.mac.type) {
2444 case ixgbe_mac_82599EB:
2445 mask |= IXGBE_EIMS_GPI_SDP0;
2446 break;
2447 case ixgbe_mac_X540:
2448 mask |= IXGBE_EIMS_TS;
2449 break;
2450 default:
2451 break;
2452 }
2c4af694
AD		 2453 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2454 mask |= IXGBE_EIMS_GPI_SDP1;
2455 switch (adapter->hw.mac.type) {
2456 case ixgbe_mac_82599EB:
2c4af694
AD		 2457 mask |= IXGBE_EIMS_GPI_SDP1;
2458 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2459 case ixgbe_mac_X540:
2460 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2461 mask |= IXGBE_EIMS_MAILBOX;
2462 break;
2463 default:
2464 break;
9a799d71 2465 }
db0677fa 2466
db0677fa
JK		 2467 if (adapter->hw.mac.type == ixgbe_mac_X540)
2468 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2469
2c4af694
AD		 2470 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2471 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2472 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2473
2c4af694
AD		 2474 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2475 if (queues)
2476 ixgbe_irq_enable_queues(adapter, ~0);
2477 if (flush)
2478 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2479}
2480
2c4af694 2481static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2482{
a65151ba 2483 struct ixgbe_adapter *adapter = data;
9a799d71 2484 struct ixgbe_hw *hw = &adapter->hw;
54037505 2485 u32 eicr;
91281fd3 2486
54037505
DS		 2487 /*
2488 * Workaround for Silicon errata. Use clear-by-write instead
2489 * of clear-by-read. Reading with EICS will return the
2490 * interrupt causes without clearing, which later be done
2491 * with the write to EICR.
2492 */
2493 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2494
2495 /* The lower 16bits of the EICR register are for the queue interrupts
2496 * which should be masked here in order to not accidently clear them if
2497 * the bits are high when ixgbe_msix_other is called. There is a race
2498 * condition otherwise which results in possible performance loss
2499 * especially if the ixgbe_msix_other interrupt is triggering
2500 * consistently (as it would when PPS is turned on for the X540 device)
2501 */
2502 eicr &= 0xFFFF0000;
2503
54037505 2504 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2505
cf8280ee
JB		 2506 if (eicr & IXGBE_EICR_LSC)
2507 ixgbe_check_lsc(adapter);
f0848276 2508
1cdd1ec8
GR		 2509 if (eicr & IXGBE_EICR_MAILBOX)
2510 ixgbe_msg_task(adapter);
efe3d3c8 2511
bd508178
AD		 2512 switch (hw->mac.type) {
2513 case ixgbe_mac_82599EB:
b93a2226 2514 case ixgbe_mac_X540:
2c4af694
AD		 2515 if (eicr & IXGBE_EICR_ECC)
2516 e_info(link, "Received unrecoverable ECC Err, please "
2517 "reboot\n");
c4cf55e5
PWJ		 2518 /* Handle Flow Director Full threshold interrupt */
2519 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2520 int reinit_count = 0;
c4cf55e5 2521 int i;
c4cf55e5 2522 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2523 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2524 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2525 &ring->state))
2526 reinit_count++;
2527 }
2528 if (reinit_count) {
2529 /* no more flow director interrupts until after init */
2530 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2531 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2532 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2533 }
2534 }
f0f9778d 2535 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2536 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2537 break;
2538 default:
2539 break;
c4cf55e5 2540 }
f0848276 2541
bd508178 2542 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2543
db0677fa
JK		 2544 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2545 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2546
7086400d 2547 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2548 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2549 ixgbe_irq_enable(adapter, false, false);
f0848276 2550
9a799d71 2551 return IRQ_HANDLED;
f0848276 2552}
91281fd3 2553
4ff7fb12 2554static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2555{
021230d4 2556 struct ixgbe_q_vector *q_vector = data;
91281fd3 2557
9b471446 2558 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2559
4ff7fb12
AD		 2560 if (q_vector->rx.ring || q_vector->tx.ring)
2561 napi_schedule(&q_vector->napi);
91281fd3 2562
9a799d71 2563 return IRQ_HANDLED;
91281fd3
AD		 2564}
2565
eb01b975
AD		 2566/**
2567 * ixgbe_poll - NAPI Rx polling callback
2568 * @napi: structure for representing this polling device
2569 * @budget: how many packets driver is allowed to clean
2570 *
2571 * This function is used for legacy and MSI, NAPI mode
2572 **/
8af3c33f 2573int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2574{
2575 struct ixgbe_q_vector *q_vector =
2576 container_of(napi, struct ixgbe_q_vector, napi);
2577 struct ixgbe_adapter *adapter = q_vector->adapter;
2578 struct ixgbe_ring *ring;
2579 int per_ring_budget;
2580 bool clean_complete = true;
2581
2582#ifdef CONFIG_IXGBE_DCA
2583 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2584 ixgbe_update_dca(q_vector);
2585#endif
2586
2587 ixgbe_for_each_ring(ring, q_vector->tx)
2588 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2589
5a85e737
ET		 2590 if (!ixgbe_qv_lock_napi(q_vector))
2591 return budget;
2592
eb01b975
AD		 2593 /* attempt to distribute budget to each queue fairly, but don't allow
2594 * the budget to go below 1 because we'll exit polling */
2595 if (q_vector->rx.count > 1)
2596 per_ring_budget = max(budget/q_vector->rx.count, 1);
2597 else
2598 per_ring_budget = budget;
2599
2600 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2601 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2602 per_ring_budget) < per_ring_budget);
eb01b975 2603
5a85e737 2604 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2605 /* If all work not completed, return budget and keep polling */
2606 if (!clean_complete)
2607 return budget;
2608
2609 /* all work done, exit the polling mode */
2610 napi_complete(napi);
2611 if (adapter->rx_itr_setting & 1)
2612 ixgbe_set_itr(q_vector);
2613 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2614 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2615
2616 return 0;
2617}
2618
021230d4
AV		 2619/**
2620 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2621 * @adapter: board private structure
2622 *
2623 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2624 * interrupts from the kernel.
2625 **/
2626static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2627{
2628 struct net_device *netdev = adapter->netdev;
207867f5 2629 int vector, err;
e8e9f696 2630 int ri = 0, ti = 0;
021230d4 2631
49c7ffbe 2632 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2633 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2634 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2635
4ff7fb12 2636 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2637 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2638 "%s-%s-%d", netdev->name, "TxRx", ri++);
2639 ti++;
2640 } else if (q_vector->rx.ring) {
9fe93afd 2641 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2642 "%s-%s-%d", netdev->name, "rx", ri++);
2643 } else if (q_vector->tx.ring) {
9fe93afd 2644 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2645 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2646 } else {
2647 /* skip this unused q_vector */
2648 continue;
32aa77a4 2649 }
207867f5
AD		 2650 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2651 q_vector->name, q_vector);
9a799d71 2652 if (err) {
396e799c 2653 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2654 "Error: %d\n", err);
021230d4 2655 goto free_queue_irqs;
9a799d71 2656 }
207867f5
AD		 2657 /* If Flow Director is enabled, set interrupt affinity */
2658 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2659 /* assign the mask for this irq */
2660 irq_set_affinity_hint(entry->vector,
de88eeeb 2661 &q_vector->affinity_mask);
207867f5 2662 }
9a799d71
AK		 2663 }
2664
021230d4 2665 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2666 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2667 if (err) {
de88eeeb 2668 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2669 goto free_queue_irqs;
9a799d71
AK		 2670 }
2671
9a799d71
AK		 2672 return 0;
2673
021230d4 2674free_queue_irqs:
207867f5
AD		 2675 while (vector) {
2676 vector--;
2677 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2678 NULL);
2679 free_irq(adapter->msix_entries[vector].vector,
2680 adapter->q_vector[vector]);
2681 }
021230d4
AV		 2682 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2683 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2684 kfree(adapter->msix_entries);
2685 adapter->msix_entries = NULL;
9a799d71
AK		 2686 return err;
2687}
2688
2689/**
021230d4 2690 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2691 * @irq: interrupt number
2692 * @data: pointer to a network interface device structure
9a799d71
AK		 2693 **/
2694static irqreturn_t ixgbe_intr(int irq, void *data)
2695{
a65151ba 2696 struct ixgbe_adapter *adapter = data;
9a799d71 2697 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2698 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2699 u32 eicr;
2700
54037505 2701 /*
24ddd967 2702 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2703 * before the read of EICR.
2704 */
2705 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2706
021230d4 2707 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2708 * therefore no explicit interrupt disable is necessary */
021230d4 2709 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2710 if (!eicr) {
6af3b9eb
ET		 2711 /*
2712 * shared interrupt alert!
f47cf66e 2713 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2714 * have disabled interrupts due to EIAM
2715 * finish the workaround of silicon errata on 82598. Unmask
2716 * the interrupt that we masked before the EICR read.
2717 */
2718 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2719 ixgbe_irq_enable(adapter, true, true);
9a799d71 2720 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2721 }
9a799d71 2722
cf8280ee
JB		 2723 if (eicr & IXGBE_EICR_LSC)
2724 ixgbe_check_lsc(adapter);
021230d4 2725
bd508178
AD		 2726 switch (hw->mac.type) {
2727 case ixgbe_mac_82599EB:
e8e26350 2728 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2729 /* Fall through */
2730 case ixgbe_mac_X540:
2731 if (eicr & IXGBE_EICR_ECC)
2732 e_info(link, "Received unrecoverable ECC err, please "
2733 "reboot\n");
4f51bf70 2734 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2735 break;
2736 default:
2737 break;
2738 }
e8e26350 2739
0befdb3e 2740 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2741 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2742 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2743
b9f6ed2b
AD		 2744 /* would disable interrupts here but EIAM disabled it */
2745 napi_schedule(&q_vector->napi);
9a799d71 2746
6af3b9eb
ET		 2747 /*
2748 * re-enable link(maybe) and non-queue interrupts, no flush.
2749 * ixgbe_poll will re-enable the queue interrupts
2750 */
6af3b9eb
ET		 2751 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2752 ixgbe_irq_enable(adapter, false, false);
2753
9a799d71
AK		 2754 return IRQ_HANDLED;
2755}
2756
2757/**
2758 * ixgbe_request_irq - initialize interrupts
2759 * @adapter: board private structure
2760 *
2761 * Attempts to configure interrupts using the best available
2762 * capabilities of the hardware and kernel.
2763 **/
021230d4 2764static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2765{
2766 struct net_device *netdev = adapter->netdev;
021230d4 2767 int err;
9a799d71 2768
4cc6df29 2769 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2770 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2771 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2772 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2773 netdev->name, adapter);
4cc6df29 2774 else
a0607fd3 2775 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2776 netdev->name, adapter);
9a799d71 2777
de88eeeb 2778 if (err)
396e799c 2779 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2780
9a799d71
AK		 2781 return err;
2782}
2783
2784static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2785{
49c7ffbe 2786 int vector;
9a799d71 2787
49c7ffbe
AD		 2788 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2789 free_irq(adapter->pdev->irq, adapter);
2790 return;
2791 }
4cc6df29 2792
49c7ffbe
AD		 2793 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2794 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2795 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2796
49c7ffbe
AD		 2797 /* free only the irqs that were actually requested */
2798 if (!q_vector->rx.ring && !q_vector->tx.ring)
2799 continue;
207867f5 2800
49c7ffbe
AD		 2801 /* clear the affinity_mask in the IRQ descriptor */
2802 irq_set_affinity_hint(entry->vector, NULL);
2803
2804 free_irq(entry->vector, q_vector);
9a799d71 2805 }
49c7ffbe
AD		 2806
2807 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2808}
2809
22d5a71b
JB		 2810/**
2811 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2812 * @adapter: board private structure
2813 **/
2814static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2815{
bd508178
AD		 2816 switch (adapter->hw.mac.type) {
2817 case ixgbe_mac_82598EB:
835462fc 2818 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2819 break;
2820 case ixgbe_mac_82599EB:
b93a2226 2821 case ixgbe_mac_X540:
835462fc
NS		 2822 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2823 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2824 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2825 break;
2826 default:
2827 break;
22d5a71b
JB		 2828 }
2829 IXGBE_WRITE_FLUSH(&adapter->hw);
2830 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2831 int vector;
2832
2833 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2834 synchronize_irq(adapter->msix_entries[vector].vector);
2835
2836 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2837 } else {
2838 synchronize_irq(adapter->pdev->irq);
2839 }
2840}
2841
9a799d71
AK		 2842/**
2843 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2844 *
2845 **/
2846static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2847{
d5bf4f67 2848 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2849
d5bf4f67 2850 ixgbe_write_eitr(q_vector);
9a799d71 2851
e8e26350
PW		 2852 ixgbe_set_ivar(adapter, 0, 0, 0);
2853 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2854
396e799c 2855 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2856}
2857
43e69bf0
AD		 2858/**
2859 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2860 * @adapter: board private structure
2861 * @ring: structure containing ring specific data
2862 *
2863 * Configure the Tx descriptor ring after a reset.
2864 **/
84418e3b
AD		 2865void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2866 struct ixgbe_ring *ring)
43e69bf0
AD		 2867{
2868 struct ixgbe_hw *hw = &adapter->hw;
2869 u64 tdba = ring->dma;
2f1860b8 2870 int wait_loop = 10;
b88c6de2 2871 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2872 u8 reg_idx = ring->reg_idx;
43e69bf0 2873
2f1860b8 2874 /* disable queue to avoid issues while updating state */
b88c6de2 2875 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2876 IXGBE_WRITE_FLUSH(hw);
2877
43e69bf0 2878 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2879 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2880 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2881 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2882 ring->count * sizeof(union ixgbe_adv_tx_desc));
2883 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2884 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2885 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2886
b88c6de2
AD		 2887 /*
2888 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 2889 * higher than 1 when:
2890 * - ITR is 0 as it could cause false TX hangs
2891 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 2892 *
2893 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2894 * to or less than the number of on chip descriptors, which is
2895 * currently 40.
2896 */
67da097e
ET		 2897#if IS_ENABLED(CONFIG_BQL)
2898 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2899#else
e954b374 2900 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 2901#endif
b88c6de2
AD		 2902 txdctl |= (1 << 16); /* WTHRESH = 1 */
2903 else
2904 txdctl |= (8 << 16); /* WTHRESH = 8 */
2905
e954b374
AD		 2906 /*
2907 * Setting PTHRESH to 32 both improves performance
2908 * and avoids a TX hang with DFP enabled
2909 */
b88c6de2
AD		 2910 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2911 32; /* PTHRESH = 32 */
2f1860b8
AD		 2912
2913 /* reinitialize flowdirector state */
39cb681b 2914 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2915 ring->atr_sample_rate = adapter->atr_sample_rate;
2916 ring->atr_count = 0;
2917 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2918 } else {
2919 ring->atr_sample_rate = 0;
2920 }
2f1860b8 2921
fd786b7b
AD		 2922 /* initialize XPS */
2923 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
2924 struct ixgbe_q_vector *q_vector = ring->q_vector;
2925
2926 if (q_vector)
2927 netif_set_xps_queue(adapter->netdev,
2928 &q_vector->affinity_mask,
2929 ring->queue_index);
2930 }
2931
c84d324c
JF		 2932 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2933
2f1860b8 2934 /* enable queue */
2f1860b8
AD		 2935 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2936
2937 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2938 if (hw->mac.type == ixgbe_mac_82598EB &&
2939 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2940 return;
2941
2942 /* poll to verify queue is enabled */
2943 do {
032b4325 2944 usleep_range(1000, 2000);
2f1860b8
AD		 2945 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2946 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2947 if (!wait_loop)
2948 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2949}
2950
120ff942
AD		 2951static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2952{
2953 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2954 u32 rttdcs, mtqc;
8b1c0b24 2955 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2956
2957 if (hw->mac.type == ixgbe_mac_82598EB)
2958 return;
2959
2960 /* disable the arbiter while setting MTQC */
2961 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2962 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2963 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2964
2965 /* set transmit pool layout */
671c0adb
AD		 2966 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2967 mtqc = IXGBE_MTQC_VT_ENA;
2968 if (tcs > 4)
2969 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2970 else if (tcs > 1)
2971 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2972 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2973 mtqc |= IXGBE_MTQC_32VF;
2974 else
2975 mtqc |= IXGBE_MTQC_64VF;
2976 } else {
2977 if (tcs > 4)
2978 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2979 else if (tcs > 1)
2980 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2981 else
671c0adb
AD		 2982 mtqc = IXGBE_MTQC_64Q_1PB;
2983 }
120ff942 2984
671c0adb 2985 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2986
671c0adb
AD		 2987 /* Enable Security TX Buffer IFG for multiple pb */
2988 if (tcs) {
2989 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2990 sectx |= IXGBE_SECTX_DCB;
2991 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2992 }
2993
2994 /* re-enable the arbiter */
2995 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2996 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2997}
2998
9a799d71 2999/**
3a581073 3000 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3001 * @adapter: board private structure
3002 *
3003 * Configure the Tx unit of the MAC after a reset.
3004 **/
3005static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3006{
2f1860b8
AD		 3007 struct ixgbe_hw *hw = &adapter->hw;
3008 u32 dmatxctl;
43e69bf0 3009 u32 i;
9a799d71 3010
2f1860b8
AD		 3011 ixgbe_setup_mtqc(adapter);
3012
3013 if (hw->mac.type != ixgbe_mac_82598EB) {
3014 /* DMATXCTL.EN must be before Tx queues are enabled */
3015 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3016 dmatxctl |= IXGBE_DMATXCTL_TE;
3017 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3018 }
3019
9a799d71 3020 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3021 for (i = 0; i < adapter->num_tx_queues; i++)
3022 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3023}
3024
3ebe8fde
AD		 3025static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3026 struct ixgbe_ring *ring)
3027{
3028 struct ixgbe_hw *hw = &adapter->hw;
3029 u8 reg_idx = ring->reg_idx;
3030 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3031
3032 srrctl |= IXGBE_SRRCTL_DROP_EN;
3033
3034 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3035}
3036
3037static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3038 struct ixgbe_ring *ring)
3039{
3040 struct ixgbe_hw *hw = &adapter->hw;
3041 u8 reg_idx = ring->reg_idx;
3042 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3043
3044 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3045
3046 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3047}
3048
3049#ifdef CONFIG_IXGBE_DCB
3050void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3051#else
3052static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3053#endif
3054{
3055 int i;
3056 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3057
3058 if (adapter->ixgbe_ieee_pfc)
3059 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3060
3061 /*
3062 * We should set the drop enable bit if:
3063 * SR-IOV is enabled
3064 * or
3065 * Number of Rx queues > 1 and flow control is disabled
3066 *
3067 * This allows us to avoid head of line blocking for security
3068 * and performance reasons.
3069 */
3070 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3071 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3072 for (i = 0; i < adapter->num_rx_queues; i++)
3073 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3074 } else {
3075 for (i = 0; i < adapter->num_rx_queues; i++)
3076 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3077 }
3078}
3079
e8e26350 3080#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3081
a6616b42 3082static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3083 struct ixgbe_ring *rx_ring)
cc41ac7c 3084{
45e9baa5 3085 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3086 u32 srrctl;
bf29ee6c 3087 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3088
45e9baa5
AD		 3089 if (hw->mac.type == ixgbe_mac_82598EB) {
3090 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3091
45e9baa5
AD		 3092 /*
3093 * if VMDq is not active we must program one srrctl register
3094 * per RSS queue since we have enabled RDRXCTL.MVMEN
3095 */
3096 reg_idx &= mask;
3097 }
cc41ac7c 3098
45e9baa5
AD		 3099 /* configure header buffer length, needed for RSC */
3100 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3101
45e9baa5 3102 /* configure the packet buffer length */
f800326d 3103 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3104
3105 /* configure descriptor type */
f800326d 3106 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3107
45e9baa5 3108 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3109}
9a799d71 3110
05abb126 3111static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3112{
05abb126
AD		 3113 struct ixgbe_hw *hw = &adapter->hw;
3114 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3115 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3116 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3117 u32 mrqc = 0, reta = 0;
3118 u32 rxcsum;
3119 int i, j;
671c0adb
AD		 3120 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3121
671c0adb
AD		 3122 /*
3123 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3124 * make full use of any rings they may have. We will use the
3125 * PSRTYPE register to control how many rings we use within the PF.
3126 */
3127 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3128 rss_i = 2;
0cefafad 3129
05abb126
AD		 3130 /* Fill out hash function seeds */
3131 for (i = 0; i < 10; i++)
3132 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3133
3134 /* Fill out redirection table */
3135 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3136 if (j == rss_i)
05abb126
AD		 3137 j = 0;
3138 /* reta = 4-byte sliding window of
3139 * 0x00..(indices-1)(indices-1)00..etc. */
3140 reta = (reta << 8) | (j * 0x11);
3141 if ((i & 3) == 3)
3142 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3143 }
0cefafad 3144
05abb126
AD		 3145 /* Disable indicating checksum in descriptor, enables RSS hash */
3146 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3147 rxcsum |= IXGBE_RXCSUM_PCSD;
3148 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3149
671c0adb 3150 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3151 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3152 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3153 } else {
671c0adb
AD		 3154 u8 tcs = netdev_get_num_tc(adapter->netdev);
3155
3156 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3157 if (tcs > 4)
3158 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3159 else if (tcs > 1)
3160 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3161 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3162 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3163 else
671c0adb
AD		 3164 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3165 } else {
3166 if (tcs > 4)
8b1c0b24 3167 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3168 else if (tcs > 1)
3169 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3170 else
3171 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3172 }
0cefafad
JB		 3173 }
3174
05abb126 3175 /* Perform hash on these packet types */
671c0adb
AD		 3176 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3177 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3178 IXGBE_MRQC_RSS_FIELD_IPV6 |
3179 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3180
ef6afc0c
AD		 3181 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3182 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3183 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3184 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3185
05abb126 3186 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3187}
3188
bb5a9ad2
NS		 3189/**
3190 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3191 * @adapter: address of board private structure
3192 * @index: index of ring to set
bb5a9ad2 3193 **/
082757af 3194static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3195 struct ixgbe_ring *ring)
bb5a9ad2 3196{
bb5a9ad2 3197 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3198 u32 rscctrl;
bf29ee6c 3199 u8 reg_idx = ring->reg_idx;
7367096a 3200
7d637bcc 3201 if (!ring_is_rsc_enabled(ring))
7367096a 3202 return;
bb5a9ad2 3203
7367096a 3204 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3205 rscctrl |= IXGBE_RSCCTL_RSCEN;
3206 /*
3207 * we must limit the number of descriptors so that the
3208 * total size of max desc * buf_len is not greater
642c680e 3209 * than 65536
bb5a9ad2 3210 */
f800326d 3211 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3212 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3213}
3214
9e10e045
AD		 3215#define IXGBE_MAX_RX_DESC_POLL 10
3216static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3217 struct ixgbe_ring *ring)
3218{
3219 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3220 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3221 u32 rxdctl;
bf29ee6c 3222 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3223
3224 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3225 if (hw->mac.type == ixgbe_mac_82598EB &&
3226 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3227 return;
3228
3229 do {
032b4325 3230 usleep_range(1000, 2000);
9e10e045
AD		 3231 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3232 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3233
3234 if (!wait_loop) {
3235 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3236 "the polling period\n", reg_idx);
3237 }
3238}
3239
2d39d576
YZ		 3240void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3241 struct ixgbe_ring *ring)
3242{
3243 struct ixgbe_hw *hw = &adapter->hw;
3244 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3245 u32 rxdctl;
3246 u8 reg_idx = ring->reg_idx;
3247
3248 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3249 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3250
3251 /* write value back with RXDCTL.ENABLE bit cleared */
3252 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3253
3254 if (hw->mac.type == ixgbe_mac_82598EB &&
3255 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3256 return;
3257
3258 /* the hardware may take up to 100us to really disable the rx queue */
3259 do {
3260 udelay(10);
3261 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3262 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3263
3264 if (!wait_loop) {
3265 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3266 "the polling period\n", reg_idx);
3267 }
3268}
3269
84418e3b
AD		 3270void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3271 struct ixgbe_ring *ring)
acd37177
AD		 3272{
3273 struct ixgbe_hw *hw = &adapter->hw;
3274 u64 rdba = ring->dma;
9e10e045 3275 u32 rxdctl;
bf29ee6c 3276 u8 reg_idx = ring->reg_idx;
acd37177 3277
9e10e045
AD		 3278 /* disable queue to avoid issues while updating state */
3279 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3280 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3281
acd37177
AD		 3282 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3283 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3284 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3285 ring->count * sizeof(union ixgbe_adv_rx_desc));
3286 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3287 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3288 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3289
3290 ixgbe_configure_srrctl(adapter, ring);
3291 ixgbe_configure_rscctl(adapter, ring);
3292
3293 if (hw->mac.type == ixgbe_mac_82598EB) {
3294 /*
3295 * enable cache line friendly hardware writes:
3296 * PTHRESH=32 descriptors (half the internal cache),
3297 * this also removes ugly rx_no_buffer_count increment
3298 * HTHRESH=4 descriptors (to minimize latency on fetch)
3299 * WTHRESH=8 burst writeback up to two cache lines
3300 */
3301 rxdctl &= ~0x3FFFFF;
3302 rxdctl |= 0x080420;
3303 }
3304
3305 /* enable receive descriptor ring */
3306 rxdctl |= IXGBE_RXDCTL_ENABLE;
3307 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3308
3309 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3310 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3311}
3312
48654521
AD		 3313static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3314{
3315 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3316 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3317 int p;
3318
3319 /* PSRTYPE must be initialized in non 82598 adapters */
3320 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3321 IXGBE_PSRTYPE_UDPHDR |
3322 IXGBE_PSRTYPE_IPV4HDR |
48654521 3323 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3324 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3325
3326 if (hw->mac.type == ixgbe_mac_82598EB)
3327 return;
3328
fbe7ca7f
AD		 3329 if (rss_i > 3)
3330 psrtype |= 2 << 29;
3331 else if (rss_i > 1)
3332 psrtype |= 1 << 29;
48654521
AD		 3333
3334 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3335 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3336 psrtype);
3337}
3338
f5b4a52e
AD		 3339static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3340{
3341 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3342 u32 reg_offset, vf_shift;
435b19f6 3343 u32 gcr_ext, vmdctl;
de4c7f65 3344 int i;
f5b4a52e
AD		 3345
3346 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3347 return;
3348
3349 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3350 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3351 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3352 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3353 vmdctl |= IXGBE_VT_CTL_REPLEN;
3354 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3355
1d9c0bfd
AD		 3356 vf_shift = VMDQ_P(0) % 32;
3357 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3358
3359 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3360 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3361 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3362 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3363 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3364 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3365 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3366
3367 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3368 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3369
3370 /*
3371 * Set up VF register offsets for selected VT Mode,
3372 * i.e. 32 or 64 VFs for SR-IOV
3373 */
73079ea0
AD		 3374 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3375 case IXGBE_82599_VMDQ_8Q_MASK:
3376 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3377 break;
3378 case IXGBE_82599_VMDQ_4Q_MASK:
3379 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3380 break;
3381 default:
3382 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3383 break;
3384 }
3385
f5b4a52e
AD		 3386 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3387
435b19f6 3388
a985b6c3 3389 /* Enable MAC Anti-Spoofing */
435b19f6 3390 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3391 adapter->num_vfs);
de4c7f65
GR		 3392 /* For VFs that have spoof checking turned off */
3393 for (i = 0; i < adapter->num_vfs; i++) {
3394 if (!adapter->vfinfo[i].spoofchk_enabled)
3395 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3396 }
f5b4a52e
AD		 3397}
3398
477de6ed 3399static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3400{
9a799d71
AK		 3401 struct ixgbe_hw *hw = &adapter->hw;
3402 struct net_device *netdev = adapter->netdev;
3403 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3404 struct ixgbe_ring *rx_ring;
3405 int i;
3406 u32 mhadd, hlreg0;
48654521 3407
63f39bd1 3408#ifdef IXGBE_FCOE
477de6ed
AD		 3409 /* adjust max frame to be able to do baby jumbo for FCoE */
3410 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3411 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3412 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3413
477de6ed 3414#endif /* IXGBE_FCOE */
872844dd
AD		 3415
3416 /* adjust max frame to be at least the size of a standard frame */
3417 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3418 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3419
477de6ed
AD		 3420 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3421 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3422 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3423 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3424
3425 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3426 }
3427
3428 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3429 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3430 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3431 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3432
0cefafad
JB		 3433 /*
3434 * Setup the HW Rx Head and Tail Descriptor Pointers and
3435 * the Base and Length of the Rx Descriptor Ring
3436 */
9a799d71 3437 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3438 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3439 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3440 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3441 else
7d637bcc 3442 clear_ring_rsc_enabled(rx_ring);
477de6ed 3443 }
477de6ed
AD		 3444}
3445
7367096a
AD		 3446static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3447{
3448 struct ixgbe_hw *hw = &adapter->hw;
3449 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3450
3451 switch (hw->mac.type) {
3452 case ixgbe_mac_82598EB:
3453 /*
3454 * For VMDq support of different descriptor types or
3455 * buffer sizes through the use of multiple SRRCTL
3456 * registers, RDRXCTL.MVMEN must be set to 1
3457 *
3458 * also, the manual doesn't mention it clearly but DCA hints
3459 * will only use queue 0's tags unless this bit is set. Side
3460 * effects of setting this bit are only that SRRCTL must be
3461 * fully programmed [0..15]
3462 */
3463 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3464 break;
3465 case ixgbe_mac_82599EB:
b93a2226 3466 case ixgbe_mac_X540:
7367096a
AD		 3467 /* Disable RSC for ACK packets */
3468 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3469 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3470 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3471 /* hardware requires some bits to be set by default */
3472 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3473 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3474 break;
3475 default:
3476 /* We should do nothing since we don't know this hardware */
3477 return;
3478 }
3479
3480 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3481}
3482
477de6ed
AD		 3483/**
3484 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3485 * @adapter: board private structure
3486 *
3487 * Configure the Rx unit of the MAC after a reset.
3488 **/
3489static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3490{
3491 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3492 int i;
3493 u32 rxctrl;
477de6ed
AD		 3494
3495 /* disable receives while setting up the descriptors */
3496 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3497 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3498
3499 ixgbe_setup_psrtype(adapter);
7367096a 3500 ixgbe_setup_rdrxctl(adapter);
477de6ed 3501
9e10e045 3502 /* Program registers for the distribution of queues */
f5b4a52e 3503 ixgbe_setup_mrqc(adapter);
f5b4a52e 3504
477de6ed
AD		 3505 /* set_rx_buffer_len must be called before ring initialization */
3506 ixgbe_set_rx_buffer_len(adapter);
3507
3508 /*
3509 * Setup the HW Rx Head and Tail Descriptor Pointers and
3510 * the Base and Length of the Rx Descriptor Ring
3511 */
9e10e045
AD		 3512 for (i = 0; i < adapter->num_rx_queues; i++)
3513 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3514
9e10e045
AD		 3515 /* disable drop enable for 82598 parts */
3516 if (hw->mac.type == ixgbe_mac_82598EB)
3517 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3518
3519 /* enable all receives */
3520 rxctrl |= IXGBE_RXCTRL_RXEN;
3521 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3522}
3523
80d5c368
PM		 3524static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3525 __be16 proto, u16 vid)
068c89b0
DS		 3526{
3527 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3528 struct ixgbe_hw *hw = &adapter->hw;
3529
3530 /* add VID to filter table */
1d9c0bfd 3531 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3532 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3533
3534 return 0;
068c89b0
DS		 3535}
3536
80d5c368
PM		 3537static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3538 __be16 proto, u16 vid)
068c89b0
DS		 3539{
3540 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3541 struct ixgbe_hw *hw = &adapter->hw;
3542
068c89b0 3543 /* remove VID from filter table */
1d9c0bfd 3544 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3545 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3546
3547 return 0;
068c89b0
DS		 3548}
3549
5f6c0181
JB		 3550/**
3551 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3552 * @adapter: driver data
3553 */
3554static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3555{
3556 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3557 u32 vlnctrl;
3558
3559 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3560 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3561 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3562}
3563
3564/**
3565 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3566 * @adapter: driver data
3567 */
3568static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3569{
3570 struct ixgbe_hw *hw = &adapter->hw;
3571 u32 vlnctrl;
3572
3573 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3574 vlnctrl |= IXGBE_VLNCTRL_VFE;
3575 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3576 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3577}
3578
3579/**
3580 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3581 * @adapter: driver data
3582 */
3583static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3584{
3585 struct ixgbe_hw *hw = &adapter->hw;
3586 u32 vlnctrl;
5f6c0181
JB		 3587 int i, j;
3588
3589 switch (hw->mac.type) {
3590 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3591 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3592 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3593 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3594 break;
3595 case ixgbe_mac_82599EB:
b93a2226 3596 case ixgbe_mac_X540:
5f6c0181
JB		 3597 for (i = 0; i < adapter->num_rx_queues; i++) {
3598 j = adapter->rx_ring[i]->reg_idx;
3599 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3600 vlnctrl &= ~IXGBE_RXDCTL_VME;
3601 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3602 }
3603 break;
3604 default:
3605 break;
3606 }
3607}
3608
3609/**
f62bbb5e 3610 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3611 * @adapter: driver data
3612 */
f62bbb5e 3613static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3614{
3615 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3616 u32 vlnctrl;
5f6c0181
JB		 3617 int i, j;
3618
3619 switch (hw->mac.type) {
3620 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3621 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3622 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3623 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3624 break;
3625 case ixgbe_mac_82599EB:
b93a2226 3626 case ixgbe_mac_X540:
5f6c0181
JB		 3627 for (i = 0; i < adapter->num_rx_queues; i++) {
3628 j = adapter->rx_ring[i]->reg_idx;
3629 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3630 vlnctrl |= IXGBE_RXDCTL_VME;
3631 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3632 }
3633 break;
3634 default:
3635 break;
3636 }
3637}
3638
9a799d71
AK		 3639static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3640{
f62bbb5e 3641 u16 vid;
9a799d71 3642
80d5c368 3643 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3644
3645 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3646 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3647}
3648
2850062a
AD		 3649/**
3650 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3651 * @netdev: network interface device structure
3652 *
3653 * Writes unicast address list to the RAR table.
3654 * Returns: -ENOMEM on failure/insufficient address space
3655 * 0 on no addresses written
3656 * X on writing X addresses to the RAR table
3657 **/
3658static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3659{
3660 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3661 struct ixgbe_hw *hw = &adapter->hw;
95447461 3662 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3663 int count = 0;
3664
95447461
JF		 3665 /* In SR-IOV mode significantly less RAR entries are available */
3666 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3667 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3668
2850062a
AD		 3669 /* return ENOMEM indicating insufficient memory for addresses */
3670 if (netdev_uc_count(netdev) > rar_entries)
3671 return -ENOMEM;
3672
95447461 3673 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3674 struct netdev_hw_addr *ha;
3675 /* return error if we do not support writing to RAR table */
3676 if (!hw->mac.ops.set_rar)
3677 return -ENOMEM;
3678
3679 netdev_for_each_uc_addr(ha, netdev) {
3680 if (!rar_entries)
3681 break;
3682 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3683 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3684 count++;
3685 }
3686 }
3687 /* write the addresses in reverse order to avoid write combining */
3688 for (; rar_entries > 0 ; rar_entries--)
3689 hw->mac.ops.clear_rar(hw, rar_entries);
3690
3691 return count;
3692}
3693
9a799d71 3694/**
2c5645cf 3695 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3696 * @netdev: network interface device structure
3697 *
2c5645cf
CL		 3698 * The set_rx_method entry point is called whenever the unicast/multicast
3699 * address list or the network interface flags are updated. This routine is
3700 * responsible for configuring the hardware for proper unicast, multicast and
3701 * promiscuous mode.
9a799d71 3702 **/
7f870475 3703void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3704{
3705 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3706 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3707 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3708 int count;
9a799d71
AK		 3709
3710 /* Check for Promiscuous and All Multicast modes */
3711
3712 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3713
f5dc442b 3714 /* set all bits that we expect to always be set */
3f2d1c0f 3715 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3716 fctrl |= IXGBE_FCTRL_BAM;
3717 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3718 fctrl |= IXGBE_FCTRL_PMCF;
3719
2850062a
AD		 3720 /* clear the bits we are changing the status of */
3721 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3722
9a799d71 3723 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3724 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3725 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3726 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3727 /* Only disable hardware filter vlans in promiscuous mode
3728 * if SR-IOV and VMDQ are disabled - otherwise ensure
3729 * that hardware VLAN filters remain enabled.
3730 */
3731 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3732 IXGBE_FLAG_SRIOV_ENABLED)))
3733 ixgbe_vlan_filter_disable(adapter);
3734 else
3735 ixgbe_vlan_filter_enable(adapter);
9a799d71 3736 } else {
746b9f02
PM		 3737 if (netdev->flags & IFF_ALLMULTI) {
3738 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3739 vmolr |= IXGBE_VMOLR_MPE;
3740 } else {
3741 /*
3742 * Write addresses to the MTA, if the attempt fails
25985edc 3743 * then we should just turn on promiscuous mode so
2850062a
AD		 3744 * that we can at least receive multicast traffic
3745 */
3746 hw->mac.ops.update_mc_addr_list(hw, netdev);
3747 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3748 }
5f6c0181 3749 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3750 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3751 }
3752
3753 /*
3754 * Write addresses to available RAR registers, if there is not
3755 * sufficient space to store all the addresses then enable
3756 * unicast promiscuous mode
3757 */
3758 count = ixgbe_write_uc_addr_list(netdev);
3759 if (count < 0) {
3760 fctrl |= IXGBE_FCTRL_UPE;
3761 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3762 }
3763
1d9c0bfd 3764 if (adapter->num_vfs)
1cdd1ec8 3765 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3766
3767 if (hw->mac.type != ixgbe_mac_82598EB) {
3768 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3769 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3770 IXGBE_VMOLR_ROPE);
1d9c0bfd 3771 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3772 }
3773
3f2d1c0f
BG		 3774 /* This is useful for sniffing bad packets. */
3775 if (adapter->netdev->features & NETIF_F_RXALL) {
3776 /* UPE and MPE will be handled by normal PROMISC logic
3777 * in e1000e_set_rx_mode */
3778 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3779 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3780 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3781
3782 fctrl &= ~(IXGBE_FCTRL_DPF);
3783 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3784 }
3785
2850062a 3786 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3787
f646968f 3788 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3789 ixgbe_vlan_strip_enable(adapter);
3790 else
3791 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3792}
3793
021230d4
AV		 3794static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3795{
3796 int q_idx;
021230d4 3797
5a85e737
ET		 3798 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3799 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 3800 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 3801 }
021230d4
AV		 3802}
3803
3804static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3805{
3806 int q_idx;
021230d4 3807
5a85e737
ET		 3808 local_bh_disable(); /* for ixgbe_qv_lock_napi() */
3809 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 3810 napi_disable(&adapter->q_vector[q_idx]->napi);
5a85e737
ET		 3811 while (!ixgbe_qv_lock_napi(adapter->q_vector[q_idx])) {
3812 pr_info("QV %d locked\n", q_idx);
3813 mdelay(1);
3814 }
3815 }
3816 local_bh_enable();
021230d4
AV		 3817}
3818
7a6b6f51 3819#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3820/**
2f90b865
AD		 3821 * ixgbe_configure_dcb - Configure DCB hardware
3822 * @adapter: ixgbe adapter struct
3823 *
3824 * This is called by the driver on open to configure the DCB hardware.
3825 * This is also called by the gennetlink interface when reconfiguring
3826 * the DCB state.
3827 */
3828static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3829{
3830 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3831 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3832
67ebd791
AD		 3833 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3834 if (hw->mac.type == ixgbe_mac_82598EB)
3835 netif_set_gso_max_size(adapter->netdev, 65536);
3836 return;
3837 }
3838
3839 if (hw->mac.type == ixgbe_mac_82598EB)
3840 netif_set_gso_max_size(adapter->netdev, 32768);
3841
971060b1 3842#ifdef IXGBE_FCOE
b120818e
JF		 3843 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3844 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3845#endif
b120818e
JF		 3846
3847 /* reconfigure the hardware */
3848 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3849 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3850 DCB_TX_CONFIG);
3851 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3852 DCB_RX_CONFIG);
3853 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3854 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3855 ixgbe_dcb_hw_ets(&adapter->hw,
3856 adapter->ixgbe_ieee_ets,
3857 max_frame);
3858 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3859 adapter->ixgbe_ieee_pfc->pfc_en,
3860 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3861 }
8187cd48
JF		 3862
3863 /* Enable RSS Hash per TC */
3864 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3865 u32 msb = 0;
3866 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3867
d411a936
AD		 3868 while (rss_i) {
3869 msb++;
3870 rss_i >>= 1;
3871 }
8187cd48 3872
4ae63730
AD		 3873 /* write msb to all 8 TCs in one write */
3874 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3875 }
2f90b865 3876}
9da712d2
JF		 3877#endif
3878
3879/* Additional bittime to account for IXGBE framing */
3880#define IXGBE_ETH_FRAMING 20
3881
49ce9c2c 3882/**
9da712d2
JF		 3883 * ixgbe_hpbthresh - calculate high water mark for flow control
3884 *
3885 * @adapter: board private structure to calculate for
49ce9c2c 3886 * @pb: packet buffer to calculate
9da712d2
JF		 3887 */
3888static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3889{
3890 struct ixgbe_hw *hw = &adapter->hw;
3891 struct net_device *dev = adapter->netdev;
3892 int link, tc, kb, marker;
3893 u32 dv_id, rx_pba;
3894
3895 /* Calculate max LAN frame size */
3896 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3897
3898#ifdef IXGBE_FCOE
3899 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3900 if ((dev->features & NETIF_F_FCOE_MTU) &&
3901 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3902 (pb == ixgbe_fcoe_get_tc(adapter)))
3903 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3904
3905#endif
9da712d2
JF		 3906 /* Calculate delay value for device */
3907 switch (hw->mac.type) {
3908 case ixgbe_mac_X540:
3909 dv_id = IXGBE_DV_X540(link, tc);
3910 break;
3911 default:
3912 dv_id = IXGBE_DV(link, tc);
3913 break;
3914 }
3915
3916 /* Loopback switch introduces additional latency */
3917 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3918 dv_id += IXGBE_B2BT(tc);
3919
3920 /* Delay value is calculated in bit times convert to KB */
3921 kb = IXGBE_BT2KB(dv_id);
3922 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3923
3924 marker = rx_pba - kb;
3925
3926 /* It is possible that the packet buffer is not large enough
3927 * to provide required headroom. In this case throw an error
3928 * to user and a do the best we can.
3929 */
3930 if (marker < 0) {
3931 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3932 "headroom to support flow control."
3933 "Decrease MTU or number of traffic classes\n", pb);
3934 marker = tc + 1;
3935 }
3936
3937 return marker;
3938}
3939
49ce9c2c 3940/**
9da712d2
JF		 3941 * ixgbe_lpbthresh - calculate low water mark for for flow control
3942 *
3943 * @adapter: board private structure to calculate for
49ce9c2c 3944 * @pb: packet buffer to calculate
9da712d2
JF		 3945 */
3946static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3947{
3948 struct ixgbe_hw *hw = &adapter->hw;
3949 struct net_device *dev = adapter->netdev;
3950 int tc;
3951 u32 dv_id;
3952
3953 /* Calculate max LAN frame size */
3954 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3955
3956 /* Calculate delay value for device */
3957 switch (hw->mac.type) {
3958 case ixgbe_mac_X540:
3959 dv_id = IXGBE_LOW_DV_X540(tc);
3960 break;
3961 default:
3962 dv_id = IXGBE_LOW_DV(tc);
3963 break;
3964 }
3965
3966 /* Delay value is calculated in bit times convert to KB */
3967 return IXGBE_BT2KB(dv_id);
3968}
3969
3970/*
3971 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3972 */
3973static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3974{
3975 struct ixgbe_hw *hw = &adapter->hw;
3976 int num_tc = netdev_get_num_tc(adapter->netdev);
3977 int i;
3978
3979 if (!num_tc)
3980 num_tc = 1;
3981
3982 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3983
3984 for (i = 0; i < num_tc; i++) {
3985 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3986
3987 /* Low water marks must not be larger than high water marks */
3988 if (hw->fc.low_water > hw->fc.high_water[i])
3989 hw->fc.low_water = 0;
3990 }
3991}
3992
80605c65
JF		 3993static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3994{
80605c65 3995 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3996 int hdrm;
3997 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3998
3999 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4000 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4001 hdrm = 32 << adapter->fdir_pballoc;
4002 else
4003 hdrm = 0;
80605c65 4004
f7e1027f 4005 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4006 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4007}
4008
e4911d57
AD		 4009static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4010{
4011 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4012 struct hlist_node *node2;
e4911d57
AD		 4013 struct ixgbe_fdir_filter *filter;
4014
4015 spin_lock(&adapter->fdir_perfect_lock);
4016
4017 if (!hlist_empty(&adapter->fdir_filter_list))
4018 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4019
b67bfe0d 4020 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4021 &adapter->fdir_filter_list, fdir_node) {
4022 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4023 &filter->filter,
4024 filter->sw_idx,
4025 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4026 IXGBE_FDIR_DROP_QUEUE :
4027 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4028 }
4029
4030 spin_unlock(&adapter->fdir_perfect_lock);
4031}
4032
9a799d71
AK		 4033static void ixgbe_configure(struct ixgbe_adapter *adapter)
4034{
d2f5e7f3
AS		 4035 struct ixgbe_hw *hw = &adapter->hw;
4036
80605c65 4037 ixgbe_configure_pb(adapter);
7a6b6f51 4038#ifdef CONFIG_IXGBE_DCB
67ebd791 4039 ixgbe_configure_dcb(adapter);
2f90b865 4040#endif
b35d4d42
AD		 4041 /*
4042 * We must restore virtualization before VLANs or else
4043 * the VLVF registers will not be populated
4044 */
4045 ixgbe_configure_virtualization(adapter);
9a799d71 4046
4c1d7b4b 4047 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4048 ixgbe_restore_vlan(adapter);
4049
d2f5e7f3
AS		 4050 switch (hw->mac.type) {
4051 case ixgbe_mac_82599EB:
4052 case ixgbe_mac_X540:
4053 hw->mac.ops.disable_rx_buff(hw);
4054 break;
4055 default:
4056 break;
4057 }
4058
c4cf55e5 4059 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4060 ixgbe_init_fdir_signature_82599(&adapter->hw,
4061 adapter->fdir_pballoc);
e4911d57
AD		 4062 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4063 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4064 adapter->fdir_pballoc);
4065 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4066 }
4c1d7b4b 4067
d2f5e7f3
AS		 4068 switch (hw->mac.type) {
4069 case ixgbe_mac_82599EB:
4070 case ixgbe_mac_X540:
4071 hw->mac.ops.enable_rx_buff(hw);
4072 break;
4073 default:
4074 break;
4075 }
4076
7c8ae65a
AD		 4077#ifdef IXGBE_FCOE
4078 /* configure FCoE L2 filters, redirection table, and Rx control */
4079 ixgbe_configure_fcoe(adapter);
4080
4081#endif /* IXGBE_FCOE */
9a799d71
AK		 4082 ixgbe_configure_tx(adapter);
4083 ixgbe_configure_rx(adapter);
9a799d71
AK		 4084}
4085
e8e26350
PW		 4086static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4087{
4088 switch (hw->phy.type) {
4089 case ixgbe_phy_sfp_avago:
4090 case ixgbe_phy_sfp_ftl:
4091 case ixgbe_phy_sfp_intel:
4092 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4093 case ixgbe_phy_sfp_passive_tyco:
4094 case ixgbe_phy_sfp_passive_unknown:
4095 case ixgbe_phy_sfp_active_unknown:
4096 case ixgbe_phy_sfp_ftl_active:
e8e26350 4097 return true;
8917b447
AD		 4098 case ixgbe_phy_nl:
4099 if (hw->mac.type == ixgbe_mac_82598EB)
4100 return true;
e8e26350
PW		 4101 default:
4102 return false;
4103 }
4104}
4105
0ecc061d 4106/**
e8e26350
PW		 4107 * ixgbe_sfp_link_config - set up SFP+ link
4108 * @adapter: pointer to private adapter struct
4109 **/
4110static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4111{
7086400d 4112 /*
52f33af8 4113 * We are assuming the worst case scenario here, and that
7086400d
AD		 4114 * is that an SFP was inserted/removed after the reset
4115 * but before SFP detection was enabled. As such the best
4116 * solution is to just start searching as soon as we start
4117 */
4118 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4119 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4120
7086400d 4121 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4122}
4123
4124/**
4125 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4126 * @hw: pointer to private hardware struct
4127 *
4128 * Returns 0 on success, negative on failure
4129 **/
e8e26350 4130static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4131{
3d292265
JH		 4132 u32 speed;
4133 bool autoneg, link_up = false;
0ecc061d
PWJ		 4134 u32 ret = IXGBE_ERR_LINK_SETUP;
4135
4136 if (hw->mac.ops.check_link)
3d292265 4137 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4138
4139 if (ret)
4140 goto link_cfg_out;
4141
3d292265
JH		 4142 speed = hw->phy.autoneg_advertised;
4143 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4144 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4145 &autoneg);
0ecc061d
PWJ		 4146 if (ret)
4147 goto link_cfg_out;
4148
8620a103 4149 if (hw->mac.ops.setup_link)
fd0326f2 4150 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4151link_cfg_out:
4152 return ret;
4153}
4154
a34bcfff 4155static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4156{
9a799d71 4157 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4158 u32 gpie = 0;
9a799d71 4159
9b471446 4160 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4161 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4162 IXGBE_GPIE_OCD;
4163 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4164 /*
4165 * use EIAM to auto-mask when MSI-X interrupt is asserted
4166 * this saves a register write for every interrupt
4167 */
4168 switch (hw->mac.type) {
4169 case ixgbe_mac_82598EB:
4170 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4171 break;
9b471446 4172 case ixgbe_mac_82599EB:
b93a2226
DS		 4173 case ixgbe_mac_X540:
4174 default:
9b471446
JB		 4175 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4176 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4177 break;
4178 }
4179 } else {
021230d4
AV		 4180 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4181 * specifically only auto mask tx and rx interrupts */
4182 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4183 }
9a799d71 4184
a34bcfff
AD		 4185 /* XXX: to interrupt immediately for EICS writes, enable this */
4186 /* gpie |= IXGBE_GPIE_EIMEN; */
4187
4188 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4189 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4190
4191 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4192 case IXGBE_82599_VMDQ_8Q_MASK:
4193 gpie |= IXGBE_GPIE_VTMODE_16;
4194 break;
4195 case IXGBE_82599_VMDQ_4Q_MASK:
4196 gpie |= IXGBE_GPIE_VTMODE_32;
4197 break;
4198 default:
4199 gpie |= IXGBE_GPIE_VTMODE_64;
4200 break;
4201 }
119fc60a
MC		 4202 }
4203
5fdd31f9 4204 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4205 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4206 switch (adapter->hw.mac.type) {
4207 case ixgbe_mac_82599EB:
4208 gpie |= IXGBE_SDP0_GPIEN;
4209 break;
4210 case ixgbe_mac_X540:
4211 gpie |= IXGBE_EIMS_TS;
4212 break;
4213 default:
4214 break;
4215 }
4216 }
5fdd31f9 4217
a34bcfff
AD		 4218 /* Enable fan failure interrupt */
4219 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4220 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4221
2698b208 4222 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4223 gpie |= IXGBE_SDP1_GPIEN;
4224 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4225 }
a34bcfff
AD		 4226
4227 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4228}
4229
c7ccde0f 4230static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4231{
4232 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4233 int err;
a34bcfff
AD		 4234 u32 ctrl_ext;
4235
4236 ixgbe_get_hw_control(adapter);
4237 ixgbe_setup_gpie(adapter);
e8e26350 4238
9a799d71
AK		 4239 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4240 ixgbe_configure_msix(adapter);
4241 else
4242 ixgbe_configure_msi_and_legacy(adapter);
4243
ec74a471
ET		 4244 /* enable the optics for 82599 SFP+ fiber */
4245 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4246 hw->mac.ops.enable_tx_laser(hw);
4247
9a799d71 4248 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4249 ixgbe_napi_enable_all(adapter);
4250
73c4b7cd
AD		 4251 if (ixgbe_is_sfp(hw)) {
4252 ixgbe_sfp_link_config(adapter);
4253 } else {
4254 err = ixgbe_non_sfp_link_config(hw);
4255 if (err)
4256 e_err(probe, "link_config FAILED %d\n", err);
4257 }
4258
021230d4
AV		 4259 /* clear any pending interrupts, may auto mask */
4260 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4261 ixgbe_irq_enable(adapter, true, true);
9a799d71 4262
bf069c97
DS		 4263 /*
4264 * If this adapter has a fan, check to see if we had a failure
4265 * before we enabled the interrupt.
4266 */
4267 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4268 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4269 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4270 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4271 }
4272
1da100bb 4273 /* enable transmits */
477de6ed 4274 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4275
9a799d71
AK		 4276 /* bring the link up in the watchdog, this could race with our first
4277 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4278 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4279 adapter->link_check_timeout = jiffies;
7086400d 4280 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4281
4282 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4283 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4284 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4285 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4286}
4287
d4f80882
AV		 4288void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4289{
4290 WARN_ON(in_interrupt());
7086400d
AD		 4291 /* put off any impending NetWatchDogTimeout */
4292 adapter->netdev->trans_start = jiffies;
4293
d4f80882 4294 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4295 usleep_range(1000, 2000);
d4f80882 4296 ixgbe_down(adapter);
5809a1ae
GR		 4297 /*
4298 * If SR-IOV enabled then wait a bit before bringing the adapter
4299 * back up to give the VFs time to respond to the reset. The
4300 * two second wait is based upon the watchdog timer cycle in
4301 * the VF driver.
4302 */
4303 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4304 msleep(2000);
d4f80882
AV		 4305 ixgbe_up(adapter);
4306 clear_bit(__IXGBE_RESETTING, &adapter->state);
4307}
4308
c7ccde0f 4309void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4310{
4311 /* hardware has been reset, we need to reload some things */
4312 ixgbe_configure(adapter);
4313
c7ccde0f 4314 ixgbe_up_complete(adapter);
9a799d71
AK		 4315}
4316
4317void ixgbe_reset(struct ixgbe_adapter *adapter)
4318{
c44ade9e 4319 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4320 int err;
4321
7086400d
AD		 4322 /* lock SFP init bit to prevent race conditions with the watchdog */
4323 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4324 usleep_range(1000, 2000);
4325
4326 /* clear all SFP and link config related flags while holding SFP_INIT */
4327 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4328 IXGBE_FLAG2_SFP_NEEDS_RESET);
4329 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4330
8ca783ab 4331 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4332 switch (err) {
4333 case 0:
4334 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4335 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4336 break;
4337 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4338 e_dev_err("master disable timed out\n");
da4dd0f7 4339 break;
794caeb2
PWJ		 4340 case IXGBE_ERR_EEPROM_VERSION:
4341 /* We are running on a pre-production device, log a warning */
849c4542 4342 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4343 "Please be aware there may be issues associated with "
849c4542
ET		 4344 "your hardware. If you are experiencing problems "
4345 "please contact your Intel or hardware "
4346 "representative who provided you with this "
4347 "hardware.\n");
794caeb2 4348 break;
da4dd0f7 4349 default:
849c4542 4350 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4351 }
9a799d71 4352
7086400d
AD		 4353 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4354
9a799d71 4355 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4356 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4357
4358 /* update SAN MAC vmdq pool selection */
4359 if (hw->mac.san_mac_rar_index)
4360 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4361
1a71ab24
JK		 4362 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4363 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4364}
4365
9a799d71
AK		 4366/**
4367 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4368 * @rx_ring: ring to free buffers from
4369 **/
b6ec895e 4370static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4371{
b6ec895e 4372 struct device *dev = rx_ring->dev;
9a799d71 4373 unsigned long size;
b6ec895e 4374 u16 i;
9a799d71 4375
84418e3b
AD		 4376 /* ring already cleared, nothing to do */
4377 if (!rx_ring->rx_buffer_info)
4378 return;
9a799d71 4379
84418e3b 4380 /* Free all the Rx ring sk_buffs */
9a799d71 4381 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4382 struct ixgbe_rx_buffer *rx_buffer;
4383
4384 rx_buffer = &rx_ring->rx_buffer_info[i];
4385 if (rx_buffer->skb) {
4386 struct sk_buff *skb = rx_buffer->skb;
4387 if (IXGBE_CB(skb)->page_released) {
4388 dma_unmap_page(dev,
4389 IXGBE_CB(skb)->dma,
4390 ixgbe_rx_bufsz(rx_ring),
4391 DMA_FROM_DEVICE);
4392 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4393 }
4394 dev_kfree_skb(skb);
9a799d71 4395 }
f800326d
AD		 4396 rx_buffer->skb = NULL;
4397 if (rx_buffer->dma)
4398 dma_unmap_page(dev, rx_buffer->dma,
4399 ixgbe_rx_pg_size(rx_ring),
4400 DMA_FROM_DEVICE);
4401 rx_buffer->dma = 0;
4402 if (rx_buffer->page)
dd411ec4
AD		 4403 __free_pages(rx_buffer->page,
4404 ixgbe_rx_pg_order(rx_ring));
f800326d 4405 rx_buffer->page = NULL;
9a799d71
AK		 4406 }
4407
4408 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4409 memset(rx_ring->rx_buffer_info, 0, size);
4410
4411 /* Zero out the descriptor ring */
4412 memset(rx_ring->desc, 0, rx_ring->size);
4413
f800326d 4414 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4415 rx_ring->next_to_clean = 0;
4416 rx_ring->next_to_use = 0;
9a799d71
AK		 4417}
4418
4419/**
4420 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4421 * @tx_ring: ring to be cleaned
4422 **/
b6ec895e 4423static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4424{
4425 struct ixgbe_tx_buffer *tx_buffer_info;
4426 unsigned long size;
b6ec895e 4427 u16 i;
9a799d71 4428
84418e3b
AD		 4429 /* ring already cleared, nothing to do */
4430 if (!tx_ring->tx_buffer_info)
4431 return;
9a799d71 4432
84418e3b 4433 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4434 for (i = 0; i < tx_ring->count; i++) {
4435 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4436 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4437 }
4438
dad8a3b3
JF		 4439 netdev_tx_reset_queue(txring_txq(tx_ring));
4440
9a799d71
AK		 4441 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4442 memset(tx_ring->tx_buffer_info, 0, size);
4443
4444 /* Zero out the descriptor ring */
4445 memset(tx_ring->desc, 0, tx_ring->size);
4446
4447 tx_ring->next_to_use = 0;
4448 tx_ring->next_to_clean = 0;
9a799d71
AK		 4449}
4450
4451/**
021230d4 4452 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4453 * @adapter: board private structure
4454 **/
021230d4 4455static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4456{
4457 int i;
4458
021230d4 4459 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4460 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4461}
4462
4463/**
021230d4 4464 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4465 * @adapter: board private structure
4466 **/
021230d4 4467static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4468{
4469 int i;
4470
021230d4 4471 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4472 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4473}
4474
e4911d57
AD		 4475static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4476{
b67bfe0d 4477 struct hlist_node *node2;
e4911d57
AD		 4478 struct ixgbe_fdir_filter *filter;
4479
4480 spin_lock(&adapter->fdir_perfect_lock);
4481
b67bfe0d 4482 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4483 &adapter->fdir_filter_list, fdir_node) {
4484 hlist_del(&filter->fdir_node);
4485 kfree(filter);
4486 }
4487 adapter->fdir_filter_count = 0;
4488
4489 spin_unlock(&adapter->fdir_perfect_lock);
4490}
4491
9a799d71
AK		 4492void ixgbe_down(struct ixgbe_adapter *adapter)
4493{
4494 struct net_device *netdev = adapter->netdev;
7f821875 4495 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4496 u32 rxctrl;
bf29ee6c 4497 int i;
9a799d71
AK		 4498
4499 /* signal that we are down to the interrupt handler */
4500 set_bit(__IXGBE_DOWN, &adapter->state);
4501
4502 /* disable receives */
7f821875
JB		 4503 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4504 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4505
2d39d576
YZ		 4506 /* disable all enabled rx queues */
4507 for (i = 0; i < adapter->num_rx_queues; i++)
4508 /* this call also flushes the previous write */
4509 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4510
032b4325 4511 usleep_range(10000, 20000);
9a799d71 4512
7f821875
JB		 4513 netif_tx_stop_all_queues(netdev);
4514
7086400d 4515 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4516 netif_carrier_off(netdev);
4517 netif_tx_disable(netdev);
4518
4519 ixgbe_irq_disable(adapter);
4520
4521 ixgbe_napi_disable_all(adapter);
4522
d034acf1
AD		 4523 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4524 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4525 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4526
4527 del_timer_sync(&adapter->service_timer);
4528
34cecbbf 4529 if (adapter->num_vfs) {
8e34d1aa
AD		 4530 /* Clear EITR Select mapping */
4531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4532
4533 /* Mark all the VFs as inactive */
4534 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4535 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4536
34cecbbf
AD		 4537 /* ping all the active vfs to let them know we are going down */
4538 ixgbe_ping_all_vfs(adapter);
4539
4540 /* Disable all VFTE/VFRE TX/RX */
4541 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4542 }
4543
7f821875
JB		 4544 /* disable transmits in the hardware now that interrupts are off */
4545 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4546 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4547 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4548 }
34cecbbf
AD		 4549
4550 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4551 switch (hw->mac.type) {
4552 case ixgbe_mac_82599EB:
b93a2226 4553 case ixgbe_mac_X540:
88512539 4554 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4555 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4556 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4557 break;
4558 default:
4559 break;
4560 }
7f821875 4561
6f4a0e45
PL		 4562 if (!pci_channel_offline(adapter->pdev))
4563 ixgbe_reset(adapter);
c6ecf39a 4564
ec74a471
ET		 4565 /* power down the optics for 82599 SFP+ fiber */
4566 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4567 hw->mac.ops.disable_tx_laser(hw);
4568
9a799d71
AK		 4569 ixgbe_clean_all_tx_rings(adapter);
4570 ixgbe_clean_all_rx_rings(adapter);
4571
5dd2d332 4572#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4573 /* since we reset the hardware DCA settings were cleared */
e35ec126 4574 ixgbe_setup_dca(adapter);
96b0e0f6 4575#endif
9a799d71
AK		 4576}
4577
9a799d71
AK		 4578/**
4579 * ixgbe_tx_timeout - Respond to a Tx Hang
4580 * @netdev: network interface device structure
4581 **/
4582static void ixgbe_tx_timeout(struct net_device *netdev)
4583{
4584 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4585
4586 /* Do the reset outside of interrupt context */
c83c6cbd 4587 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4588}
4589
9a799d71
AK		 4590/**
4591 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4592 * @adapter: board private structure to initialize
4593 *
4594 * ixgbe_sw_init initializes the Adapter private data structure.
4595 * Fields are initialized based on PCI device information and
4596 * OS network device settings (MTU size).
4597 **/
9f9a12f8 4598static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4599{
4600 struct ixgbe_hw *hw = &adapter->hw;
4601 struct pci_dev *pdev = adapter->pdev;
d3cb9869 4602 unsigned int rss, fdir;
cb6d0f5e 4603 u32 fwsm;
7a6b6f51 4604#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4605 int j;
4606 struct tc_configuration *tc;
4607#endif
021230d4 4608
c44ade9e
JB		 4609 /* PCI config space info */
4610
4611 hw->vendor_id = pdev->vendor;
4612 hw->device_id = pdev->device;
4613 hw->revision_id = pdev->revision;
4614 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4615 hw->subsystem_device_id = pdev->subsystem_device;
4616
8fc3bb6d 4617 /* Set common capability flags and settings */
3ed69d7e 4618 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4619 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 4620 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4621 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 4622 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4623 adapter->atr_sample_rate = 20;
d3cb9869
AD		 4624 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4625 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 4626 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4627#ifdef CONFIG_IXGBE_DCA
4628 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4629#endif
4630#ifdef IXGBE_FCOE
4631 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4632 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4633#ifdef CONFIG_IXGBE_DCB
4634 /* Default traffic class to use for FCoE */
4635 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4636#endif /* CONFIG_IXGBE_DCB */
4637#endif /* IXGBE_FCOE */
4638
4639 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 4640 switch (hw->mac.type) {
4641 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 4642 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4643 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4644
bf069c97
DS		 4645 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4646 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 4647
49c7ffbe 4648 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 4649 adapter->ring_feature[RING_F_FDIR].limit = 0;
4650 adapter->atr_sample_rate = 0;
4651 adapter->fdir_pballoc = 0;
4652#ifdef IXGBE_FCOE
4653 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4654 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4655#ifdef CONFIG_IXGBE_DCB
4656 adapter->fcoe.up = 0;
4657#endif /* IXGBE_DCB */
4658#endif /* IXGBE_FCOE */
4659 break;
4660 case ixgbe_mac_82599EB:
4661 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4662 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 4663 break;
b93a2226 4664 case ixgbe_mac_X540:
cb6d0f5e
JK		 4665 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4666 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4667 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 4668 break;
4669 default:
4670 break;
f8212f97 4671 }
2f90b865 4672
7c8ae65a
AD		 4673#ifdef IXGBE_FCOE
4674 /* FCoE support exists, always init the FCoE lock */
4675 spin_lock_init(&adapter->fcoe.lock);
4676
4677#endif
1fc5f038
AD		 4678 /* n-tuple support exists, always init our spinlock */
4679 spin_lock_init(&adapter->fdir_perfect_lock);
4680
7a6b6f51 4681#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4682 switch (hw->mac.type) {
4683 case ixgbe_mac_X540:
4684 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4685 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4686 break;
4687 default:
4688 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4689 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4690 break;
4691 }
4692
2f90b865
AD		 4693 /* Configure DCB traffic classes */
4694 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4695 tc = &adapter->dcb_cfg.tc_config[j];
4696 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4697 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4698 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4699 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4700 tc->dcb_pfc = pfc_disabled;
4701 }
4de2a022
JF		 4702
4703 /* Initialize default user to priority mapping, UPx->TC0 */
4704 tc = &adapter->dcb_cfg.tc_config[0];
4705 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4706 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4707
2f90b865
AD		 4708 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4709 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4710 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4711 adapter->dcb_set_bitmap = 0x00;
3032309b 4712 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4713 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4714 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4715
4716#endif
9a799d71
AK		 4717
4718 /* default flow control settings */
cd7664f6 4719 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4720 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4721 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4722 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4723 hw->fc.send_xon = true;
73d80953 4724 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 4725
99d74487
AD		 4726#ifdef CONFIG_PCI_IOV
4727 /* assign number of SR-IOV VFs */
4728 if (hw->mac.type != ixgbe_mac_82598EB)
4729 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4730
4731#endif
30efa5a3 4732 /* enable itr by default in dynamic mode */
f7554a2b 4733 adapter->rx_itr_setting = 1;
f7554a2b 4734 adapter->tx_itr_setting = 1;
30efa5a3 4735
30efa5a3
JB		 4736 /* set default ring sizes */
4737 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4738 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4739
bd198058 4740 /* set default work limits */
59224555 4741 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4742
9a799d71 4743 /* initialize eeprom parameters */
c44ade9e 4744 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4745 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4746 return -EIO;
4747 }
4748
9a799d71
AK		 4749 set_bit(__IXGBE_DOWN, &adapter->state);
4750
4751 return 0;
4752}
4753
4754/**
4755 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4756 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4757 *
4758 * Return 0 on success, negative on failure
4759 **/
b6ec895e 4760int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4761{
b6ec895e 4762 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4763 int orig_node = dev_to_node(dev);
4764 int numa_node = -1;
9a799d71
AK		 4765 int size;
4766
3a581073 4767 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4768
4769 if (tx_ring->q_vector)
4770 numa_node = tx_ring->q_vector->numa_node;
4771
4772 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4773 if (!tx_ring->tx_buffer_info)
89bf67f1 4774 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4775 if (!tx_ring->tx_buffer_info)
4776 goto err;
9a799d71
AK		 4777
4778 /* round up to nearest 4K */
12207e49 4779 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4780 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4781
de88eeeb
AD		 4782 set_dev_node(dev, numa_node);
4783 tx_ring->desc = dma_alloc_coherent(dev,
4784 tx_ring->size,
4785 &tx_ring->dma,
4786 GFP_KERNEL);
4787 set_dev_node(dev, orig_node);
4788 if (!tx_ring->desc)
4789 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4790 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4791 if (!tx_ring->desc)
4792 goto err;
9a799d71 4793
3a581073
JB		 4794 tx_ring->next_to_use = 0;
4795 tx_ring->next_to_clean = 0;
9a799d71 4796 return 0;
e01c31a5
JB		 4797
4798err:
4799 vfree(tx_ring->tx_buffer_info);
4800 tx_ring->tx_buffer_info = NULL;
b6ec895e 4801 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4802 return -ENOMEM;
9a799d71
AK		 4803}
4804
69888674
AD		 4805/**
4806 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4807 * @adapter: board private structure
4808 *
4809 * If this function returns with an error, then it's possible one or
4810 * more of the rings is populated (while the rest are not). It is the
4811 * callers duty to clean those orphaned rings.
4812 *
4813 * Return 0 on success, negative on failure
4814 **/
4815static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4816{
4817 int i, err = 0;
4818
4819 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4820 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4821 if (!err)
4822 continue;
de3d5b94 4823
396e799c 4824 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4825 goto err_setup_tx;
69888674
AD		 4826 }
4827
de3d5b94
AD		 4828 return 0;
4829err_setup_tx:
4830 /* rewind the index freeing the rings as we go */
4831 while (i--)
4832 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4833 return err;
4834}
4835
9a799d71
AK		 4836/**
4837 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4838 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4839 *
4840 * Returns 0 on success, negative on failure
4841 **/
b6ec895e 4842int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4843{
b6ec895e 4844 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4845 int orig_node = dev_to_node(dev);
4846 int numa_node = -1;
021230d4 4847 int size;
9a799d71 4848
3a581073 4849 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4850
4851 if (rx_ring->q_vector)
4852 numa_node = rx_ring->q_vector->numa_node;
4853
4854 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4855 if (!rx_ring->rx_buffer_info)
89bf67f1 4856 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4857 if (!rx_ring->rx_buffer_info)
4858 goto err;
9a799d71 4859
9a799d71 4860 /* Round up to nearest 4K */
3a581073
JB		 4861 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4862 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4863
de88eeeb
AD		 4864 set_dev_node(dev, numa_node);
4865 rx_ring->desc = dma_alloc_coherent(dev,
4866 rx_ring->size,
4867 &rx_ring->dma,
4868 GFP_KERNEL);
4869 set_dev_node(dev, orig_node);
4870 if (!rx_ring->desc)
4871 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4872 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4873 if (!rx_ring->desc)
4874 goto err;
9a799d71 4875
3a581073
JB		 4876 rx_ring->next_to_clean = 0;
4877 rx_ring->next_to_use = 0;
9a799d71
AK		 4878
4879 return 0;
b6ec895e
AD		 4880err:
4881 vfree(rx_ring->rx_buffer_info);
4882 rx_ring->rx_buffer_info = NULL;
4883 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4884 return -ENOMEM;
9a799d71
AK		 4885}
4886
69888674
AD		 4887/**
4888 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4889 * @adapter: board private structure
4890 *
4891 * If this function returns with an error, then it's possible one or
4892 * more of the rings is populated (while the rest are not). It is the
4893 * callers duty to clean those orphaned rings.
4894 *
4895 * Return 0 on success, negative on failure
4896 **/
69888674
AD		 4897static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4898{
4899 int i, err = 0;
4900
4901 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4902 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4903 if (!err)
4904 continue;
de3d5b94 4905
396e799c 4906 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4907 goto err_setup_rx;
69888674
AD		 4908 }
4909
7c8ae65a
AD		 4910#ifdef IXGBE_FCOE
4911 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4912 if (!err)
4913#endif
4914 return 0;
de3d5b94
AD		 4915err_setup_rx:
4916 /* rewind the index freeing the rings as we go */
4917 while (i--)
4918 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4919 return err;
4920}
4921
9a799d71
AK		 4922/**
4923 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4924 * @tx_ring: Tx descriptor ring for a specific queue
4925 *
4926 * Free all transmit software resources
4927 **/
b6ec895e 4928void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4929{
b6ec895e 4930 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4931
4932 vfree(tx_ring->tx_buffer_info);
4933 tx_ring->tx_buffer_info = NULL;
4934
b6ec895e
AD		 4935 /* if not set, then don't free */
4936 if (!tx_ring->desc)
4937 return;
4938
4939 dma_free_coherent(tx_ring->dev, tx_ring->size,
4940 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4941
4942 tx_ring->desc = NULL;
4943}
4944
4945/**
4946 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4947 * @adapter: board private structure
4948 *
4949 * Free all transmit software resources
4950 **/
4951static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4952{
4953 int i;
4954
4955 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4956 if (adapter->tx_ring[i]->desc)
b6ec895e 4957 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4958}
4959
4960/**
b4617240 4961 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4962 * @rx_ring: ring to clean the resources from
4963 *
4964 * Free all receive software resources
4965 **/
b6ec895e 4966void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4967{
b6ec895e 4968 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4969
4970 vfree(rx_ring->rx_buffer_info);
4971 rx_ring->rx_buffer_info = NULL;
4972
b6ec895e
AD		 4973 /* if not set, then don't free */
4974 if (!rx_ring->desc)
4975 return;
4976
4977 dma_free_coherent(rx_ring->dev, rx_ring->size,
4978 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4979
4980 rx_ring->desc = NULL;
4981}
4982
4983/**
4984 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4985 * @adapter: board private structure
4986 *
4987 * Free all receive software resources
4988 **/
4989static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4990{
4991 int i;
4992
7c8ae65a
AD		 4993#ifdef IXGBE_FCOE
4994 ixgbe_free_fcoe_ddp_resources(adapter);
4995
4996#endif
9a799d71 4997 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4998 if (adapter->rx_ring[i]->desc)
b6ec895e 4999 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5000}
5001
9a799d71
AK		 5002/**
5003 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5004 * @netdev: network interface device structure
5005 * @new_mtu: new value for maximum frame size
5006 *
5007 * Returns 0 on success, negative on failure
5008 **/
5009static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5010{
5011 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5012 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5013
42c783c5 5014 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5015 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5016 return -EINVAL;
5017
5018 /*
872844dd
AD		 5019 * For 82599EB we cannot allow legacy VFs to enable their receive
5020 * paths when MTU greater than 1500 is configured. So display a
5021 * warning that legacy VFs will be disabled.
655309e9
AD		 5022 */
5023 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5024 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5025 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5026 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5027
396e799c 5028 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5029
021230d4 5030 /* must set new MTU before calling down or up */
9a799d71
AK		 5031 netdev->mtu = new_mtu;
5032
d4f80882
AV		 5033 if (netif_running(netdev))
5034 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5035
5036 return 0;
5037}
5038
5039/**
5040 * ixgbe_open - Called when a network interface is made active
5041 * @netdev: network interface device structure
5042 *
5043 * Returns 0 on success, negative value on failure
5044 *
5045 * The open entry point is called when a network interface is made
5046 * active by the system (IFF_UP). At this point all resources needed
5047 * for transmit and receive operations are allocated, the interrupt
5048 * handler is registered with the OS, the watchdog timer is started,
5049 * and the stack is notified that the interface is ready.
5050 **/
5051static int ixgbe_open(struct net_device *netdev)
5052{
5053 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5054 int err;
4bebfaa5
AK		 5055
5056 /* disallow open during test */
5057 if (test_bit(__IXGBE_TESTING, &adapter->state))
5058 return -EBUSY;
9a799d71 5059
54386467
JB		 5060 netif_carrier_off(netdev);
5061
9a799d71
AK		 5062 /* allocate transmit descriptors */
5063 err = ixgbe_setup_all_tx_resources(adapter);
5064 if (err)
5065 goto err_setup_tx;
5066
9a799d71
AK		 5067 /* allocate receive descriptors */
5068 err = ixgbe_setup_all_rx_resources(adapter);
5069 if (err)
5070 goto err_setup_rx;
5071
5072 ixgbe_configure(adapter);
5073
021230d4 5074 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5075 if (err)
5076 goto err_req_irq;
5077
ac802f5d
AD		 5078 /* Notify the stack of the actual queue counts. */
5079 err = netif_set_real_num_tx_queues(netdev,
5080 adapter->num_rx_pools > 1 ? 1 :
5081 adapter->num_tx_queues);
5082 if (err)
5083 goto err_set_queues;
5084
5085
5086 err = netif_set_real_num_rx_queues(netdev,
5087 adapter->num_rx_pools > 1 ? 1 :
5088 adapter->num_rx_queues);
5089 if (err)
5090 goto err_set_queues;
5091
1a71ab24 5092 ixgbe_ptp_init(adapter);
1a71ab24 5093
c7ccde0f 5094 ixgbe_up_complete(adapter);
9a799d71
AK		 5095
5096 return 0;
5097
ac802f5d
AD		 5098err_set_queues:
5099 ixgbe_free_irq(adapter);
9a799d71 5100err_req_irq:
a20a1199 5101 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5102err_setup_rx:
a20a1199 5103 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5104err_setup_tx:
9a799d71
AK		 5105 ixgbe_reset(adapter);
5106
5107 return err;
5108}
5109
5110/**
5111 * ixgbe_close - Disables a network interface
5112 * @netdev: network interface device structure
5113 *
5114 * Returns 0, this is not allowed to fail
5115 *
5116 * The close entry point is called when an interface is de-activated
5117 * by the OS. The hardware is still under the drivers control, but
5118 * needs to be disabled. A global MAC reset is issued to stop the
5119 * hardware, and all transmit and receive resources are freed.
5120 **/
5121static int ixgbe_close(struct net_device *netdev)
5122{
5123 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5124
1a71ab24 5125 ixgbe_ptp_stop(adapter);
1a71ab24 5126
9a799d71
AK		 5127 ixgbe_down(adapter);
5128 ixgbe_free_irq(adapter);
5129
e4911d57
AD		 5130 ixgbe_fdir_filter_exit(adapter);
5131
9a799d71
AK		 5132 ixgbe_free_all_tx_resources(adapter);
5133 ixgbe_free_all_rx_resources(adapter);
5134
5eba3699 5135 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5136
5137 return 0;
5138}
5139
b3c8b4ba
AD		 5140#ifdef CONFIG_PM
5141static int ixgbe_resume(struct pci_dev *pdev)
5142{
c60fbb00
AD		 5143 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5144 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5145 u32 err;
5146
5147 pci_set_power_state(pdev, PCI_D0);
5148 pci_restore_state(pdev);
656ab817
DS		 5149 /*
5150 * pci_restore_state clears dev->state_saved so call
5151 * pci_save_state to restore it.
5152 */
5153 pci_save_state(pdev);
9ce77666 5154
5155 err = pci_enable_device_mem(pdev);
b3c8b4ba 5156 if (err) {
849c4542 5157 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5158 return err;
5159 }
5160 pci_set_master(pdev);
5161
dd4d8ca6 5162 pci_wake_from_d3(pdev, false);
b3c8b4ba 5163
b3c8b4ba
AD		 5164 ixgbe_reset(adapter);
5165
495dce12
WJP		 5166 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5167
ac802f5d
AD		 5168 rtnl_lock();
5169 err = ixgbe_init_interrupt_scheme(adapter);
5170 if (!err && netif_running(netdev))
c60fbb00 5171 err = ixgbe_open(netdev);
ac802f5d
AD		 5172
5173 rtnl_unlock();
5174
5175 if (err)
5176 return err;
b3c8b4ba
AD		 5177
5178 netif_device_attach(netdev);
5179
5180 return 0;
5181}
b3c8b4ba 5182#endif /* CONFIG_PM */
9d8d05ae
RW		 5183
5184static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5185{
c60fbb00
AD		 5186 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5187 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5188 struct ixgbe_hw *hw = &adapter->hw;
5189 u32 ctrl, fctrl;
5190 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5191#ifdef CONFIG_PM
5192 int retval = 0;
5193#endif
5194
5195 netif_device_detach(netdev);
5196
499ab5cc 5197 rtnl_lock();
b3c8b4ba
AD		 5198 if (netif_running(netdev)) {
5199 ixgbe_down(adapter);
5200 ixgbe_free_irq(adapter);
5201 ixgbe_free_all_tx_resources(adapter);
5202 ixgbe_free_all_rx_resources(adapter);
5203 }
499ab5cc 5204 rtnl_unlock();
b3c8b4ba 5205
5f5ae6fc
AD		 5206 ixgbe_clear_interrupt_scheme(adapter);
5207
b3c8b4ba
AD		 5208#ifdef CONFIG_PM
5209 retval = pci_save_state(pdev);
5210 if (retval)
5211 return retval;
4df10466 5212
b3c8b4ba 5213#endif
e8e26350
PW		 5214 if (wufc) {
5215 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5216
ec74a471
ET		 5217 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5218 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5219 hw->mac.ops.enable_tx_laser(hw);
5220
e8e26350
PW		 5221 /* turn on all-multi mode if wake on multicast is enabled */
5222 if (wufc & IXGBE_WUFC_MC) {
5223 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5224 fctrl |= IXGBE_FCTRL_MPE;
5225 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5226 }
5227
5228 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5229 ctrl |= IXGBE_CTRL_GIO_DIS;
5230 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5231
5232 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5233 } else {
5234 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5235 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5236 }
5237
bd508178
AD		 5238 switch (hw->mac.type) {
5239 case ixgbe_mac_82598EB:
dd4d8ca6 5240 pci_wake_from_d3(pdev, false);
bd508178
AD		 5241 break;
5242 case ixgbe_mac_82599EB:
b93a2226 5243 case ixgbe_mac_X540:
bd508178
AD		 5244 pci_wake_from_d3(pdev, !!wufc);
5245 break;
5246 default:
5247 break;
5248 }
b3c8b4ba 5249
9d8d05ae
RW		 5250 *enable_wake = !!wufc;
5251
b3c8b4ba
AD		 5252 ixgbe_release_hw_control(adapter);
5253
5254 pci_disable_device(pdev);
5255
9d8d05ae
RW		 5256 return 0;
5257}
5258
5259#ifdef CONFIG_PM
5260static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5261{
5262 int retval;
5263 bool wake;
5264
5265 retval = __ixgbe_shutdown(pdev, &wake);
5266 if (retval)
5267 return retval;
5268
5269 if (wake) {
5270 pci_prepare_to_sleep(pdev);
5271 } else {
5272 pci_wake_from_d3(pdev, false);
5273 pci_set_power_state(pdev, PCI_D3hot);
5274 }
b3c8b4ba
AD		 5275
5276 return 0;
5277}
9d8d05ae 5278#endif /* CONFIG_PM */
b3c8b4ba
AD		 5279
5280static void ixgbe_shutdown(struct pci_dev *pdev)
5281{
9d8d05ae
RW		 5282 bool wake;
5283
5284 __ixgbe_shutdown(pdev, &wake);
5285
5286 if (system_state == SYSTEM_POWER_OFF) {
5287 pci_wake_from_d3(pdev, wake);
5288 pci_set_power_state(pdev, PCI_D3hot);
5289 }
b3c8b4ba
AD		 5290}
5291
9a799d71
AK		 5292/**
5293 * ixgbe_update_stats - Update the board statistics counters.
5294 * @adapter: board private structure
5295 **/
5296void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5297{
2d86f139 5298 struct net_device *netdev = adapter->netdev;
9a799d71 5299 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5300 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5301 u64 total_mpc = 0;
5302 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5303 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5304 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5305 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5306
d08935c2
DS		 5307 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5308 test_bit(__IXGBE_RESETTING, &adapter->state))
5309 return;
5310
94b982b2 5311 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5312 u64 rsc_count = 0;
94b982b2 5313 u64 rsc_flush = 0;
94b982b2 5314 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5315 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5316 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5317 }
5318 adapter->rsc_total_count = rsc_count;
5319 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5320 }
5321
5b7da515
AD		 5322 for (i = 0; i < adapter->num_rx_queues; i++) {
5323 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5324 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5325 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5326 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5327 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5328 bytes += rx_ring->stats.bytes;
5329 packets += rx_ring->stats.packets;
5330 }
5331 adapter->non_eop_descs = non_eop_descs;
5332 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5333 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5334 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5335 netdev->stats.rx_bytes = bytes;
5336 netdev->stats.rx_packets = packets;
5337
5338 bytes = 0;
5339 packets = 0;
7ca3bc58 5340 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5341 for (i = 0; i < adapter->num_tx_queues; i++) {
5342 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5343 restart_queue += tx_ring->tx_stats.restart_queue;
5344 tx_busy += tx_ring->tx_stats.tx_busy;
5345 bytes += tx_ring->stats.bytes;
5346 packets += tx_ring->stats.packets;
5347 }
eb985f09 5348 adapter->restart_queue = restart_queue;
5b7da515
AD		 5349 adapter->tx_busy = tx_busy;
5350 netdev->stats.tx_bytes = bytes;
5351 netdev->stats.tx_packets = packets;
7ca3bc58 5352
7ca647bd 5353 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5354
5355 /* 8 register reads */
6f11eef7
AV		 5356 for (i = 0; i < 8; i++) {
5357 /* for packet buffers not used, the register should read 0 */
5358 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5359 missed_rx += mpc;
7ca647bd
JP		 5360 hwstats->mpc[i] += mpc;
5361 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5362 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5363 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5364 switch (hw->mac.type) {
5365 case ixgbe_mac_82598EB:
1a70db4b
ET		 5366 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5367 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5368 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5369 hwstats->pxonrxc[i] +=
5370 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5371 break;
5372 case ixgbe_mac_82599EB:
b93a2226 5373 case ixgbe_mac_X540:
bd508178
AD		 5374 hwstats->pxonrxc[i] +=
5375 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5376 break;
5377 default:
5378 break;
e8e26350 5379 }
6f11eef7 5380 }
1a70db4b
ET		 5381
5382 /*16 register reads */
5383 for (i = 0; i < 16; i++) {
5384 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5385 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5386 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5387 (hw->mac.type == ixgbe_mac_X540)) {
5388 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5389 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5390 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5391 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5392 }
5393 }
5394
7ca647bd 5395 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5396 /* work around hardware counting issue */
7ca647bd 5397 hwstats->gprc -= missed_rx;
6f11eef7 5398
c84d324c
JF		 5399 ixgbe_update_xoff_received(adapter);
5400
6f11eef7 5401 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5402 switch (hw->mac.type) {
5403 case ixgbe_mac_82598EB:
5404 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5405 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5406 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5407 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5408 break;
b93a2226 5409 case ixgbe_mac_X540:
58f6bcf9
ET		 5410 /* OS2BMC stats are X540 only*/
5411 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5412 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5413 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5414 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5415 case ixgbe_mac_82599EB:
a4d4f629
AD		 5416 for (i = 0; i < 16; i++)
5417 adapter->hw_rx_no_dma_resources +=
5418 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5419 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5420 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5421 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5422 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5423 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5424 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5425 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5426 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5427 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5428#ifdef IXGBE_FCOE
7ca647bd
JP		 5429 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5430 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5431 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5432 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5433 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5434 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5435 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5436 if (adapter->fcoe.ddp_pool) {
5437 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5438 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5439 unsigned int cpu;
5440 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5441 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5442 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5443 noddp += ddp_pool->noddp;
5444 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5445 }
5a1ee270
AD		 5446 hwstats->fcoe_noddp = noddp;
5447 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5448 }
6d45522c 5449#endif /* IXGBE_FCOE */
bd508178
AD		 5450 break;
5451 default:
5452 break;
e8e26350 5453 }
9a799d71 5454 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5455 hwstats->bprc += bprc;
5456 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5457 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5458 hwstats->mprc -= bprc;
5459 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5460 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5461 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5462 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5463 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5464 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5465 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5466 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5467 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5468 hwstats->lxontxc += lxon;
6f11eef7 5469 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5470 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5471 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5472 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5473 /*
5474 * 82598 errata - tx of flow control packets is included in tx counters
5475 */
5476 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5477 hwstats->gptc -= xon_off_tot;
5478 hwstats->mptc -= xon_off_tot;
5479 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5480 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5481 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5482 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5483 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5484 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5485 hwstats->ptc64 -= xon_off_tot;
5486 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5487 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5488 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5489 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5490 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5491 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5492
5493 /* Fill out the OS statistics structure */
7ca647bd 5494 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5495
5496 /* Rx Errors */
7ca647bd 5497 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5498 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5499 netdev->stats.rx_length_errors = hwstats->rlec;
5500 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5501 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5502}
5503
5504/**
d034acf1 5505 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5506 * @adapter: pointer to the device adapter structure
9a799d71 5507 **/
d034acf1 5508static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5509{
cf8280ee 5510 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5511 int i;
cf8280ee 5512
d034acf1
AD		 5513 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5514 return;
5515
5516 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5517
d034acf1 5518 /* if interface is down do nothing */
fe49f04a 5519 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5520 return;
5521
5522 /* do nothing if we are not using signature filters */
5523 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5524 return;
5525
5526 adapter->fdir_overflow++;
5527
93c52dd0
AD		 5528 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5529 for (i = 0; i < adapter->num_tx_queues; i++)
5530 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5531 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5532 /* re-enable flow director interrupts */
5533 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5534 } else {
5535 e_err(probe, "failed to finish FDIR re-initialization, "
5536 "ignored adding FDIR ATR filters\n");
5537 }
93c52dd0
AD		 5538}
5539
5540/**
5541 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5542 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5543 *
5544 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5545 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5546 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5547 * determine if a hang has occurred.
93c52dd0
AD		 5548 */
5549static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5550{
cf8280ee 5551 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5552 u64 eics = 0;
5553 int i;
cf8280ee 5554
93c52dd0
AD		 5555 /* If we're down or resetting, just bail */
5556 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5557 test_bit(__IXGBE_RESETTING, &adapter->state))
5558 return;
22d5a71b 5559
93c52dd0
AD		 5560 /* Force detection of hung controller */
5561 if (netif_carrier_ok(adapter->netdev)) {
5562 for (i = 0; i < adapter->num_tx_queues; i++)
5563 set_check_for_tx_hang(adapter->tx_ring[i]);
5564 }
22d5a71b 5565
fe49f04a
AD		 5566 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5567 /*
5568 * for legacy and MSI interrupts don't set any bits
5569 * that are enabled for EIAM, because this operation
5570 * would set *both* EIMS and EICS for any bit in EIAM
5571 */
5572 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5573 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5574 } else {
5575 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5576 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5577 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5578 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5579 eics |= ((u64)1 << i);
5580 }
cf8280ee 5581 }
9a799d71 5582
93c52dd0 5583 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5584 ixgbe_irq_rearm_queues(adapter, eics);
5585
cf8280ee
JB		 5586}
5587
e8e26350 5588/**
93c52dd0 5589 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5590 * @adapter: pointer to the device adapter structure
5591 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5592 **/
93c52dd0 5593static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5594{
e8e26350 5595 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5596 u32 link_speed = adapter->link_speed;
5597 bool link_up = adapter->link_up;
041441d0 5598 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5599
93c52dd0
AD		 5600 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5601 return;
5602
5603 if (hw->mac.ops.check_link) {
5604 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5605 } else {
93c52dd0
AD		 5606 /* always assume link is up, if no check link function */
5607 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5608 link_up = true;
c4cf55e5 5609 }
041441d0
AD		 5610
5611 if (adapter->ixgbe_ieee_pfc)
5612 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5613
3ebe8fde 5614 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5615 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5616 ixgbe_set_rx_drop_en(adapter);
5617 }
93c52dd0
AD		 5618
5619 if (link_up ||
5620 time_after(jiffies, (adapter->link_check_timeout +
5621 IXGBE_TRY_LINK_TIMEOUT))) {
5622 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5623 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5624 IXGBE_WRITE_FLUSH(hw);
5625 }
5626
5627 adapter->link_up = link_up;
5628 adapter->link_speed = link_speed;
e8e26350
PW		 5629}
5630
107d3018
AD		 5631static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5632{
5633#ifdef CONFIG_IXGBE_DCB
5634 struct net_device *netdev = adapter->netdev;
5635 struct dcb_app app = {
5636 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5637 .protocol = 0,
5638 };
5639 u8 up = 0;
5640
5641 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5642 up = dcb_ieee_getapp_mask(netdev, &app);
5643
5644 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5645#endif
5646}
5647
e8e26350 5648/**
93c52dd0
AD		 5649 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5650 * print link up message
49ce9c2c 5651 * @adapter: pointer to the device adapter structure
e8e26350 5652 **/
93c52dd0 5653static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5654{
93c52dd0 5655 struct net_device *netdev = adapter->netdev;
e8e26350 5656 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5657 u32 link_speed = adapter->link_speed;
5658 bool flow_rx, flow_tx;
e8e26350 5659
93c52dd0
AD		 5660 /* only continue if link was previously down */
5661 if (netif_carrier_ok(netdev))
a985b6c3 5662 return;
63d6e1d8 5663
93c52dd0 5664 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5665
93c52dd0
AD		 5666 switch (hw->mac.type) {
5667 case ixgbe_mac_82598EB: {
5668 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5669 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5670 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5671 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5672 }
5673 break;
5674 case ixgbe_mac_X540:
5675 case ixgbe_mac_82599EB: {
5676 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5677 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5678 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5679 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5680 }
5681 break;
5682 default:
5683 flow_tx = false;
5684 flow_rx = false;
5685 break;
e8e26350 5686 }
3a6a4eda 5687
6cb562d6
JK		 5688 adapter->last_rx_ptp_check = jiffies;
5689
1a71ab24
JK		 5690 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5691 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5692
93c52dd0
AD		 5693 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5694 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5695 "10 Gbps" :
5696 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5697 "1 Gbps" :
5698 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5699 "100 Mbps" :
5700 "unknown speed"))),
5701 ((flow_rx && flow_tx) ? "RX/TX" :
5702 (flow_rx ? "RX" :
5703 (flow_tx ? "TX" : "None"))));
e8e26350 5704
93c52dd0 5705 netif_carrier_on(netdev);
93c52dd0 5706 ixgbe_check_vf_rate_limit(adapter);
befa2af7 5707
107d3018
AD		 5708 /* update the default user priority for VFs */
5709 ixgbe_update_default_up(adapter);
5710
befa2af7
AD		 5711 /* ping all the active vfs to let them know link has changed */
5712 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5713}
5714
c4cf55e5 5715/**
93c52dd0
AD		 5716 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5717 * print link down message
49ce9c2c 5718 * @adapter: pointer to the adapter structure
c4cf55e5 5719 **/
581330ba 5720static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5721{
cf8280ee 5722 struct net_device *netdev = adapter->netdev;
c4cf55e5 5723 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5724
93c52dd0
AD		 5725 adapter->link_up = false;
5726 adapter->link_speed = 0;
cf8280ee 5727
93c52dd0
AD		 5728 /* only continue if link was up previously */
5729 if (!netif_carrier_ok(netdev))
5730 return;
264857b8 5731
93c52dd0
AD		 5732 /* poll for SFP+ cable when link is down */
5733 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5734 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5735
1a71ab24
JK		 5736 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5737 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5738
93c52dd0
AD		 5739 e_info(drv, "NIC Link is Down\n");
5740 netif_carrier_off(netdev);
befa2af7
AD		 5741
5742 /* ping all the active vfs to let them know link has changed */
5743 ixgbe_ping_all_vfs(adapter);
93c52dd0 5744}
e8e26350 5745
93c52dd0
AD		 5746/**
5747 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5748 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5749 **/
5750static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5751{
c4cf55e5 5752 int i;
93c52dd0 5753 int some_tx_pending = 0;
c4cf55e5 5754
93c52dd0 5755 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5756 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5757 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5758 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5759 some_tx_pending = 1;
5760 break;
5761 }
5762 }
5763
5764 if (some_tx_pending) {
5765 /* We've lost link, so the controller stops DMA,
5766 * but we've got queued Tx work that's never going
5767 * to get done, so reset controller to flush Tx.
5768 * (Do the reset outside of interrupt context).
5769 */
12ff3f3b 5770 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 5771 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5772 }
c4cf55e5 5773 }
c4cf55e5
PWJ		 5774}
5775
a985b6c3
GR		 5776static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5777{
5778 u32 ssvpc;
5779
0584d999
GR		 5780 /* Do not perform spoof check for 82598 or if not in IOV mode */
5781 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5782 adapter->num_vfs == 0)
a985b6c3
GR		 5783 return;
5784
5785 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5786
5787 /*
5788 * ssvpc register is cleared on read, if zero then no
5789 * spoofed packets in the last interval.
5790 */
5791 if (!ssvpc)
5792 return;
5793
d6ea0754 5794 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 5795}
5796
93c52dd0
AD		 5797/**
5798 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5799 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5800 **/
5801static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5802{
5803 /* if interface is down do nothing */
7edebf9a
ET		 5804 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5805 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5806 return;
5807
5808 ixgbe_watchdog_update_link(adapter);
5809
5810 if (adapter->link_up)
5811 ixgbe_watchdog_link_is_up(adapter);
5812 else
5813 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5814
a985b6c3 5815 ixgbe_spoof_check(adapter);
9a799d71 5816 ixgbe_update_stats(adapter);
93c52dd0
AD		 5817
5818 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5819}
10eec955 5820
cf8280ee 5821/**
7086400d 5822 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5823 * @adapter: the ixgbe adapter structure
cf8280ee 5824 **/
7086400d 5825static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5826{
cf8280ee 5827 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5828 s32 err;
cf8280ee 5829
7086400d
AD		 5830 /* not searching for SFP so there is nothing to do here */
5831 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5832 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5833 return;
10eec955 5834
7086400d
AD		 5835 /* someone else is in init, wait until next service event */
5836 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5837 return;
cf8280ee 5838
7086400d
AD		 5839 err = hw->phy.ops.identify_sfp(hw);
5840 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5841 goto sfp_out;
264857b8 5842
7086400d
AD		 5843 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5844 /* If no cable is present, then we need to reset
5845 * the next time we find a good cable. */
5846 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5847 }
9a799d71 5848
7086400d
AD		 5849 /* exit on error */
5850 if (err)
5851 goto sfp_out;
e8e26350 5852
7086400d
AD		 5853 /* exit if reset not needed */
5854 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5855 goto sfp_out;
9a799d71 5856
7086400d 5857 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5858
7086400d
AD		 5859 /*
5860 * A module may be identified correctly, but the EEPROM may not have
5861 * support for that module. setup_sfp() will fail in that case, so
5862 * we should not allow that module to load.
5863 */
5864 if (hw->mac.type == ixgbe_mac_82598EB)
5865 err = hw->phy.ops.reset(hw);
5866 else
5867 err = hw->mac.ops.setup_sfp(hw);
5868
5869 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5870 goto sfp_out;
5871
5872 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5873 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5874
5875sfp_out:
5876 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5877
5878 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5879 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5880 e_dev_err("failed to initialize because an unsupported "
5881 "SFP+ module type was detected.\n");
5882 e_dev_err("Reload the driver after installing a "
5883 "supported module.\n");
5884 unregister_netdev(adapter->netdev);
bc59fcda 5885 }
7086400d 5886}
bc59fcda 5887
7086400d
AD		 5888/**
5889 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5890 * @adapter: the ixgbe adapter structure
7086400d
AD		 5891 **/
5892static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5893{
5894 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 5895 u32 speed;
5896 bool autoneg = false;
7086400d
AD		 5897
5898 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5899 return;
5900
5901 /* someone else is in init, wait until next service event */
5902 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5903 return;
5904
5905 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5906
3d292265
JH		 5907 speed = hw->phy.autoneg_advertised;
5908 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5909 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
7086400d 5910 if (hw->mac.ops.setup_link)
fd0326f2 5911 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 5912
5913 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5914 adapter->link_check_timeout = jiffies;
5915 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5916}
5917
83c61fa9
GR		 5918#ifdef CONFIG_PCI_IOV
5919static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5920{
5921 int vf;
5922 struct ixgbe_hw *hw = &adapter->hw;
5923 struct net_device *netdev = adapter->netdev;
5924 u32 gpc;
5925 u32 ciaa, ciad;
5926
5927 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5928 if (gpc) /* If incrementing then no need for the check below */
5929 return;
5930 /*
5931 * Check to see if a bad DMA write target from an errant or
5932 * malicious VF has caused a PCIe error. If so then we can
5933 * issue a VFLR to the offending VF(s) and then resume without
5934 * requesting a full slot reset.
5935 */
5936
5937 for (vf = 0; vf < adapter->num_vfs; vf++) {
5938 ciaa = (vf << 16) | 0x80000000;
5939 /* 32 bit read so align, we really want status at offset 6 */
5940 ciaa |= PCI_COMMAND;
5941 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5942 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5943 ciaa &= 0x7FFFFFFF;
5944 /* disable debug mode asap after reading data */
5945 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5946 /* Get the upper 16 bits which will be the PCI status reg */
5947 ciad >>= 16;
5948 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5949 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5950 /* Issue VFLR */
5951 ciaa = (vf << 16) | 0x80000000;
5952 ciaa |= 0xA8;
5953 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5954 ciad = 0x00008000; /* VFLR */
5955 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5956 ciaa &= 0x7FFFFFFF;
5957 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5958 }
5959 }
5960}
5961
5962#endif
7086400d
AD		 5963/**
5964 * ixgbe_service_timer - Timer Call-back
5965 * @data: pointer to adapter cast into an unsigned long
5966 **/
5967static void ixgbe_service_timer(unsigned long data)
5968{
5969 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5970 unsigned long next_event_offset;
83c61fa9 5971 bool ready = true;
7086400d 5972
6bb78cfb
AD		 5973 /* poll faster when waiting for link */
5974 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5975 next_event_offset = HZ / 10;
5976 else
5977 next_event_offset = HZ * 2;
83c61fa9 5978
6bb78cfb 5979#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5980 /*
5981 * don't bother with SR-IOV VF DMA hang check if there are
5982 * no VFs or the link is down
5983 */
5984 if (!adapter->num_vfs ||
6bb78cfb 5985 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5986 goto normal_timer_service;
83c61fa9
GR		 5987
5988 /* If we have VFs allocated then we must check for DMA hangs */
5989 ixgbe_check_for_bad_vf(adapter);
5990 next_event_offset = HZ / 50;
5991 adapter->timer_event_accumulator++;
5992
6bb78cfb 5993 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5994 adapter->timer_event_accumulator = 0;
7086400d 5995 else
6bb78cfb 5996 ready = false;
7086400d 5997
6bb78cfb 5998normal_timer_service:
83c61fa9 5999#endif
7086400d
AD		 6000 /* Reset the timer */
6001 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6002
83c61fa9
GR		 6003 if (ready)
6004 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6005}
6006
c83c6cbd
AD		 6007static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6008{
6009 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6010 return;
6011
6012 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6013
6014 /* If we're already down or resetting, just bail */
6015 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6016 test_bit(__IXGBE_RESETTING, &adapter->state))
6017 return;
6018
6019 ixgbe_dump(adapter);
6020 netdev_err(adapter->netdev, "Reset adapter\n");
6021 adapter->tx_timeout_count++;
6022
6023 ixgbe_reinit_locked(adapter);
6024}
6025
7086400d
AD		 6026/**
6027 * ixgbe_service_task - manages and runs subtasks
6028 * @work: pointer to work_struct containing our data
6029 **/
6030static void ixgbe_service_task(struct work_struct *work)
6031{
6032 struct ixgbe_adapter *adapter = container_of(work,
6033 struct ixgbe_adapter,
6034 service_task);
c83c6cbd 6035 ixgbe_reset_subtask(adapter);
7086400d
AD		 6036 ixgbe_sfp_detection_subtask(adapter);
6037 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6038 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6039 ixgbe_watchdog_subtask(adapter);
d034acf1 6040 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6041 ixgbe_check_hang_subtask(adapter);
891dc082
JK		 6042
6043 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
6044 ixgbe_ptp_overflow_check(adapter);
6045 ixgbe_ptp_rx_hang(adapter);
6046 }
7086400d
AD		 6047
6048 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6049}
6050
fd0db0ed
AD		 6051static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6052 struct ixgbe_tx_buffer *first,
244e27ad 6053 u8 *hdr_len)
897ab156 6054{
fd0db0ed 6055 struct sk_buff *skb = first->skb;
897ab156
AD		 6056 u32 vlan_macip_lens, type_tucmd;
6057 u32 mss_l4len_idx, l4len;
9a799d71 6058
8f4fbb9b
AD		 6059 if (skb->ip_summed != CHECKSUM_PARTIAL)
6060 return 0;
6061
897ab156
AD		 6062 if (!skb_is_gso(skb))
6063 return 0;
9a799d71 6064
897ab156 6065 if (skb_header_cloned(skb)) {
244e27ad 6066 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 6067 if (err)
6068 return err;
9a799d71 6069 }
9a799d71 6070
897ab156
AD		 6071 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6072 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6073
244e27ad 6074 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 6075 struct iphdr *iph = ip_hdr(skb);
6076 iph->tot_len = 0;
6077 iph->check = 0;
6078 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6079 iph->daddr, 0,
6080 IPPROTO_TCP,
6081 0);
6082 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6083 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6084 IXGBE_TX_FLAGS_CSUM |
6085 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6086 } else if (skb_is_gso_v6(skb)) {
6087 ipv6_hdr(skb)->payload_len = 0;
6088 tcp_hdr(skb)->check =
6089 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6090 &ipv6_hdr(skb)->daddr,
6091 0, IPPROTO_TCP, 0);
244e27ad
AD		 6092 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6093 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6094 }
6095
091a6246 6096 /* compute header lengths */
897ab156
AD		 6097 l4len = tcp_hdrlen(skb);
6098 *hdr_len = skb_transport_offset(skb) + l4len;
6099
091a6246
AD		 6100 /* update gso size and bytecount with header size */
6101 first->gso_segs = skb_shinfo(skb)->gso_segs;
6102 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6103
c44f5f51 6104 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6105 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6106 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6107
6108 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6109 vlan_macip_lens = skb_network_header_len(skb);
6110 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6111 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6112
6113 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6114 mss_l4len_idx);
897ab156
AD		 6115
6116 return 1;
6117}
6118
244e27ad
AD		 6119static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6120 struct ixgbe_tx_buffer *first)
7ca647bd 6121{
fd0db0ed 6122 struct sk_buff *skb = first->skb;
897ab156
AD		 6123 u32 vlan_macip_lens = 0;
6124 u32 mss_l4len_idx = 0;
6125 u32 type_tucmd = 0;
7ca647bd 6126
897ab156 6127 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6128 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6129 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6130 return;
897ab156
AD		 6131 } else {
6132 u8 l4_hdr = 0;
244e27ad 6133 switch (first->protocol) {
897ab156
AD		 6134 case __constant_htons(ETH_P_IP):
6135 vlan_macip_lens |= skb_network_header_len(skb);
6136 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6137 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6138 break;
897ab156
AD		 6139 case __constant_htons(ETH_P_IPV6):
6140 vlan_macip_lens |= skb_network_header_len(skb);
6141 l4_hdr = ipv6_hdr(skb)->nexthdr;
6142 break;
6143 default:
6144 if (unlikely(net_ratelimit())) {
6145 dev_warn(tx_ring->dev,
6146 "partial checksum but proto=%x!\n",
244e27ad 6147 first->protocol);
897ab156 6148 }
7ca647bd
JP		 6149 break;
6150 }
897ab156
AD		 6151
6152 switch (l4_hdr) {
7ca647bd 6153 case IPPROTO_TCP:
897ab156
AD		 6154 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6155 mss_l4len_idx = tcp_hdrlen(skb) <<
6156 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6157 break;
6158 case IPPROTO_SCTP:
897ab156
AD		 6159 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6160 mss_l4len_idx = sizeof(struct sctphdr) <<
6161 IXGBE_ADVTXD_L4LEN_SHIFT;
6162 break;
6163 case IPPROTO_UDP:
6164 mss_l4len_idx = sizeof(struct udphdr) <<
6165 IXGBE_ADVTXD_L4LEN_SHIFT;
6166 break;
6167 default:
6168 if (unlikely(net_ratelimit())) {
6169 dev_warn(tx_ring->dev,
6170 "partial checksum but l4 proto=%x!\n",
244e27ad 6171 l4_hdr);
897ab156 6172 }
7ca647bd
JP		 6173 break;
6174 }
244e27ad
AD		 6175
6176 /* update TX checksum flag */
6177 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6178 }
6179
244e27ad 6180 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6181 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6182 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6183
897ab156
AD		 6184 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6185 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6186}
6187
472148c3
AD		 6188#define IXGBE_SET_FLAG(_input, _flag, _result) \
6189 ((_flag <= _result) ? \
6190 ((u32)(_input & _flag) * (_result / _flag)) : \
6191 ((u32)(_input & _flag) / (_flag / _result)))
6192
6193static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6194{
d3d00239 6195 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6196 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6197 IXGBE_ADVTXD_DCMD_DEXT |
6198 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6199
d3d00239 6200 /* set HW vlan bit if vlan is present */
472148c3
AD		 6201 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6202 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6203
d3d00239 6204 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6205 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6206 IXGBE_ADVTXD_DCMD_TSE);
6207
6208 /* set timestamp bit if present */
6209 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6210 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6211
62748b7b 6212 /* insert frame checksum */
472148c3 6213 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6214
d3d00239
AD		 6215 return cmd_type;
6216}
9a799d71 6217
729739b7
AD		 6218static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6219 u32 tx_flags, unsigned int paylen)
d3d00239 6220{
472148c3 6221 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6222
d3d00239 6223 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6224 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6225 IXGBE_TX_FLAGS_CSUM,
6226 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6227
93f5b3c1 6228 /* enble IPv4 checksum for TSO */
472148c3
AD		 6229 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6230 IXGBE_TX_FLAGS_IPV4,
6231 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6232
7f9643fd
AD		 6233 /*
6234 * Check Context must be set if Tx switch is enabled, which it
6235 * always is for case where virtual functions are running
6236 */
472148c3
AD		 6237 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6238 IXGBE_TX_FLAGS_CC,
6239 IXGBE_ADVTXD_CC);
7f9643fd 6240
472148c3 6241 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6242}
44df32c5 6243
d3d00239
AD		 6244#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6245 IXGBE_TXD_CMD_RS)
6246
6247static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6248 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6249 const u8 hdr_len)
6250{
fd0db0ed 6251 struct sk_buff *skb = first->skb;
729739b7 6252 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6253 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6254 struct skb_frag_struct *frag;
6255 dma_addr_t dma;
6256 unsigned int data_len, size;
244e27ad 6257 u32 tx_flags = first->tx_flags;
472148c3 6258 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6259 u16 i = tx_ring->next_to_use;
d3d00239 6260
729739b7
AD		 6261 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6262
ec718254
AD		 6263 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6264
6265 size = skb_headlen(skb);
6266 data_len = skb->data_len;
729739b7 6267
d3d00239
AD		 6268#ifdef IXGBE_FCOE
6269 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6270 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6271 size -= sizeof(struct fcoe_crc_eof) - data_len;
6272 data_len = 0;
729739b7
AD		 6273 } else {
6274 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6275 }
6276 }
44df32c5 6277
d3d00239 6278#endif
729739b7 6279 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6280
ec718254 6281 tx_buffer = first;
9a799d71 6282
ec718254
AD		 6283 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6284 if (dma_mapping_error(tx_ring->dev, dma))
6285 goto dma_error;
6286
6287 /* record length, and DMA address */
6288 dma_unmap_len_set(tx_buffer, len, size);
6289 dma_unmap_addr_set(tx_buffer, dma, dma);
6290
6291 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6292
729739b7 6293 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6294 tx_desc->read.cmd_type_len =
472148c3 6295 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6296
d3d00239 6297 i++;
729739b7 6298 tx_desc++;
d3d00239 6299 if (i == tx_ring->count) {
e4f74028 6300 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6301 i = 0;
6302 }
ec718254 6303 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6304
6305 dma += IXGBE_MAX_DATA_PER_TXD;
6306 size -= IXGBE_MAX_DATA_PER_TXD;
6307
6308 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6309 }
e5a43549 6310
729739b7
AD		 6311 if (likely(!data_len))
6312 break;
9a799d71 6313
472148c3 6314 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6315
729739b7
AD		 6316 i++;
6317 tx_desc++;
6318 if (i == tx_ring->count) {
6319 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6320 i = 0;
6321 }
ec718254 6322 tx_desc->read.olinfo_status = 0;
9a799d71 6323
d3d00239 6324#ifdef IXGBE_FCOE
9e903e08 6325 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6326#else
9e903e08 6327 size = skb_frag_size(frag);
d3d00239
AD		 6328#endif
6329 data_len -= size;
9a799d71 6330
729739b7
AD		 6331 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6332 DMA_TO_DEVICE);
9a799d71 6333
729739b7 6334 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6335 }
9a799d71 6336
729739b7 6337 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6338 cmd_type |= size | IXGBE_TXD_CMD;
6339 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6340
091a6246 6341 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6342
d3d00239
AD		 6343 /* set the timestamp */
6344 first->time_stamp = jiffies;
9a799d71
AK		 6345
6346 /*
729739b7
AD		 6347 * Force memory writes to complete before letting h/w know there
6348 * are new descriptors to fetch. (Only applicable for weak-ordered
6349 * memory model archs, such as IA-64).
6350 *
6351 * We also need this memory barrier to make certain all of the
6352 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6353 */
6354 wmb();
6355
d3d00239
AD		 6356 /* set next_to_watch value indicating a packet is present */
6357 first->next_to_watch = tx_desc;
6358
729739b7
AD		 6359 i++;
6360 if (i == tx_ring->count)
6361 i = 0;
6362
6363 tx_ring->next_to_use = i;
6364
d3d00239 6365 /* notify HW of packet */
84ea2591 6366 writel(i, tx_ring->tail);
d3d00239
AD		 6367
6368 return;
6369dma_error:
729739b7 6370 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6371
6372 /* clear dma mappings for failed tx_buffer_info map */
6373 for (;;) {
729739b7
AD		 6374 tx_buffer = &tx_ring->tx_buffer_info[i];
6375 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6376 if (tx_buffer == first)
d3d00239
AD		 6377 break;
6378 if (i == 0)
6379 i = tx_ring->count;
6380 i--;
6381 }
6382
d3d00239 6383 tx_ring->next_to_use = i;
9a799d71
AK		 6384}
6385
fd0db0ed 6386static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6387 struct ixgbe_tx_buffer *first)
69830529
AD		 6388{
6389 struct ixgbe_q_vector *q_vector = ring->q_vector;
6390 union ixgbe_atr_hash_dword input = { .dword = 0 };
6391 union ixgbe_atr_hash_dword common = { .dword = 0 };
6392 union {
6393 unsigned char *network;
6394 struct iphdr *ipv4;
6395 struct ipv6hdr *ipv6;
6396 } hdr;
ee9e0f0b 6397 struct tcphdr *th;
905e4a41 6398 __be16 vlan_id;
c4cf55e5 6399
69830529
AD		 6400 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6401 if (!q_vector)
6402 return;
6403
6404 /* do nothing if sampling is disabled */
6405 if (!ring->atr_sample_rate)
d3ead241 6406 return;
c4cf55e5 6407
69830529 6408 ring->atr_count++;
c4cf55e5 6409
69830529 6410 /* snag network header to get L4 type and address */
fd0db0ed 6411 hdr.network = skb_network_header(first->skb);
69830529
AD		 6412
6413 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6414 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6415 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6416 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6417 hdr.ipv4->protocol != IPPROTO_TCP))
6418 return;
ee9e0f0b 6419
fd0db0ed 6420 th = tcp_hdr(first->skb);
c4cf55e5 6421
66f32a8b
AD		 6422 /* skip this packet since it is invalid or the socket is closing */
6423 if (!th || th->fin)
69830529
AD		 6424 return;
6425
6426 /* sample on all syn packets or once every atr sample count */
6427 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6428 return;
6429
6430 /* reset sample count */
6431 ring->atr_count = 0;
6432
244e27ad 6433 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6434
6435 /*
6436 * src and dst are inverted, think how the receiver sees them
6437 *
6438 * The input is broken into two sections, a non-compressed section
6439 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6440 * is XORed together and stored in the compressed dword.
6441 */
6442 input.formatted.vlan_id = vlan_id;
6443
6444 /*
6445 * since src port and flex bytes occupy the same word XOR them together
6446 * and write the value to source port portion of compressed dword
6447 */
244e27ad 6448 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6449 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6450 else
244e27ad 6451 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6452 common.port.dst ^= th->source;
6453
244e27ad 6454 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6455 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6456 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6457 } else {
6458 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6459 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6460 hdr.ipv6->saddr.s6_addr32[1] ^
6461 hdr.ipv6->saddr.s6_addr32[2] ^
6462 hdr.ipv6->saddr.s6_addr32[3] ^
6463 hdr.ipv6->daddr.s6_addr32[0] ^
6464 hdr.ipv6->daddr.s6_addr32[1] ^
6465 hdr.ipv6->daddr.s6_addr32[2] ^
6466 hdr.ipv6->daddr.s6_addr32[3];
6467 }
c4cf55e5
PWJ		 6468
6469 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6470 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6471 input, common, ring->queue_index);
c4cf55e5
PWJ		 6472}
6473
63544e9c 6474static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6475{
fc77dc3c 6476 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6477 /* Herbert's original patch had:
6478 * smp_mb__after_netif_stop_queue();
6479 * but since that doesn't exist yet, just open code it. */
6480 smp_mb();
6481
6482 /* We need to check again in a case another CPU has just
6483 * made room available. */
7d4987de 6484 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6485 return -EBUSY;
6486
6487 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6488 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6489 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6490 return 0;
6491}
6492
82d4e46e 6493static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6494{
7d4987de 6495 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6496 return 0;
fc77dc3c 6497 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6498}
6499
97488bd1 6500#ifdef IXGBE_FCOE
09a3b1f8
SH		 6501static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6502{
97488bd1
AD		 6503 struct ixgbe_adapter *adapter;
6504 struct ixgbe_ring_feature *f;
6505 int txq;
5e09a105 6506
97488bd1
AD		 6507 /*
6508 * only execute the code below if protocol is FCoE
6509 * or FIP and we have FCoE enabled on the adapter
6510 */
6511 switch (vlan_get_protocol(skb)) {
6512 case __constant_htons(ETH_P_FCOE):
6513 case __constant_htons(ETH_P_FIP):
6514 adapter = netdev_priv(dev);
c087663e 6515
97488bd1
AD		 6516 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6517 break;
6518 default:
6519 return __netdev_pick_tx(dev, skb);
6520 }
c087663e 6521
97488bd1 6522 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6523
97488bd1
AD		 6524 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6525 smp_processor_id();
56075a98 6526
97488bd1
AD		 6527 while (txq >= f->indices)
6528 txq -= f->indices;
c4cf55e5 6529
97488bd1 6530 return txq + f->offset;
09a3b1f8
SH		 6531}
6532
97488bd1 6533#endif
fc77dc3c 6534netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6535 struct ixgbe_adapter *adapter,
6536 struct ixgbe_ring *tx_ring)
9a799d71 6537{
d3d00239 6538 struct ixgbe_tx_buffer *first;
5f715823 6539 int tso;
d3d00239 6540 u32 tx_flags = 0;
a535c30e 6541 unsigned short f;
a535c30e 6542 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6543 __be16 protocol = skb->protocol;
63544e9c 6544 u8 hdr_len = 0;
5e09a105 6545
a535c30e
AD		 6546 /*
6547 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6548 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6549 * + 2 desc gap to keep tail from touching head,
6550 * + 1 desc for context descriptor,
6551 * otherwise try next time
6552 */
a535c30e
AD		 6553 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6554 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 6555
a535c30e
AD		 6556 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6557 tx_ring->tx_stats.tx_busy++;
6558 return NETDEV_TX_BUSY;
6559 }
6560
fd0db0ed
AD		 6561 /* record the location of the first descriptor for this packet */
6562 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6563 first->skb = skb;
091a6246
AD		 6564 first->bytecount = skb->len;
6565 first->gso_segs = 1;
fd0db0ed 6566
66f32a8b 6567 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6568 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6569 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6570 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6571 /* else if it is a SW VLAN check the next protocol and store the tag */
6572 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6573 struct vlan_hdr *vhdr, _vhdr;
6574 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6575 if (!vhdr)
6576 goto out_drop;
6577
6578 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6579 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6580 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6581 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6582 }
6583
aa7bd467
JK		 6584 skb_tx_timestamp(skb);
6585
3a6a4eda
JK		 6586 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6587 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6588 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 6589
6590 /* schedule check for Tx timestamp */
6591 adapter->ptp_tx_skb = skb_get(skb);
6592 adapter->ptp_tx_start = jiffies;
6593 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 6594 }
3a6a4eda 6595
9e0c5648
AD		 6596#ifdef CONFIG_PCI_IOV
6597 /*
6598 * Use the l2switch_enable flag - would be false if the DMA
6599 * Tx switch had been disabled.
6600 */
6601 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 6602 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 6603
6604#endif
32701dc2 6605 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6606 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6607 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6608 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6609 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6610 tx_flags |= (skb->priority & 0x7) <<
6611 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6612 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6613 struct vlan_ethhdr *vhdr;
6614 if (skb_header_cloned(skb) &&
6615 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6616 goto out_drop;
6617 vhdr = (struct vlan_ethhdr *)skb->data;
6618 vhdr->h_vlan_TCI = htons(tx_flags >>
6619 IXGBE_TX_FLAGS_VLAN_SHIFT);
6620 } else {
6621 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6622 }
9a799d71 6623 }
eacd73f7 6624
244e27ad
AD		 6625 /* record initial flags and protocol */
6626 first->tx_flags = tx_flags;
6627 first->protocol = protocol;
6628
eacd73f7 6629#ifdef IXGBE_FCOE
66f32a8b
AD		 6630 /* setup tx offload for FCoE */
6631 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6632 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6633 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6634 if (tso < 0)
6635 goto out_drop;
9a799d71 6636
66f32a8b 6637 goto xmit_fcoe;
eacd73f7 6638 }
9a799d71 6639
66f32a8b 6640#endif /* IXGBE_FCOE */
244e27ad 6641 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6642 if (tso < 0)
897ab156 6643 goto out_drop;
244e27ad
AD		 6644 else if (!tso)
6645 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6646
6647 /* add the ATR filter if ATR is on */
6648 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6649 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6650
6651#ifdef IXGBE_FCOE
6652xmit_fcoe:
6653#endif /* IXGBE_FCOE */
244e27ad 6654 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6655
6656 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6657
6658 return NETDEV_TX_OK;
897ab156
AD		 6659
6660out_drop:
fd0db0ed
AD		 6661 dev_kfree_skb_any(first->skb);
6662 first->skb = NULL;
6663
897ab156 6664 return NETDEV_TX_OK;
9a799d71
AK		 6665}
6666
a50c29dd
AD		 6667static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6668 struct net_device *netdev)
84418e3b
AD		 6669{
6670 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6671 struct ixgbe_ring *tx_ring;
6672
a50c29dd
AD		 6673 /*
6674 * The minimum packet size for olinfo paylen is 17 so pad the skb
6675 * in order to meet this minimum size requirement.
6676 */
f73332fc
SH		 6677 if (unlikely(skb->len < 17)) {
6678 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6679 return NETDEV_TX_OK;
6680 skb->len = 17;
71a49f77 6681 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 6682 }
6683
84418e3b 6684 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6685 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6686}
6687
9a799d71
AK		 6688/**
6689 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6690 * @netdev: network interface device structure
6691 * @p: pointer to an address structure
6692 *
6693 * Returns 0 on success, negative on failure
6694 **/
6695static int ixgbe_set_mac(struct net_device *netdev, void *p)
6696{
6697 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6698 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6699 struct sockaddr *addr = p;
6700
6701 if (!is_valid_ether_addr(addr->sa_data))
6702 return -EADDRNOTAVAIL;
6703
6704 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6705 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6706
1d9c0bfd 6707 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6708
6709 return 0;
6710}
6711
6b73e10d
BH		 6712static int
6713ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6714{
6715 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6716 struct ixgbe_hw *hw = &adapter->hw;
6717 u16 value;
6718 int rc;
6719
6720 if (prtad != hw->phy.mdio.prtad)
6721 return -EINVAL;
6722 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6723 if (!rc)
6724 rc = value;
6725 return rc;
6726}
6727
6728static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6729 u16 addr, u16 value)
6730{
6731 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6732 struct ixgbe_hw *hw = &adapter->hw;
6733
6734 if (prtad != hw->phy.mdio.prtad)
6735 return -EINVAL;
6736 return hw->phy.ops.write_reg(hw, addr, devad, value);
6737}
6738
6739static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6740{
6741 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6742
3a6a4eda 6743 switch (cmd) {
3a6a4eda
JK		 6744 case SIOCSHWTSTAMP:
6745 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 6746 default:
6747 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6748 }
6b73e10d
BH		 6749}
6750
0365e6e4
PW		 6751/**
6752 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6753 * netdev->dev_addrs
0365e6e4
PW		 6754 * @netdev: network interface device structure
6755 *
6756 * Returns non-zero on failure
6757 **/
6758static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6759{
6760 int err = 0;
6761 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6762 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6763
7fa7c9dc 6764 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6765 rtnl_lock();
7fa7c9dc 6766 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6767 rtnl_unlock();
7fa7c9dc
AD		 6768
6769 /* update SAN MAC vmdq pool selection */
6770 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6771 }
6772 return err;
6773}
6774
6775/**
6776 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6777 * netdev->dev_addrs
0365e6e4
PW		 6778 * @netdev: network interface device structure
6779 *
6780 * Returns non-zero on failure
6781 **/
6782static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6783{
6784 int err = 0;
6785 struct ixgbe_adapter *adapter = netdev_priv(dev);
6786 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6787
6788 if (is_valid_ether_addr(mac->san_addr)) {
6789 rtnl_lock();
6790 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6791 rtnl_unlock();
6792 }
6793 return err;
6794}
6795
9a799d71
AK		 6796#ifdef CONFIG_NET_POLL_CONTROLLER
6797/*
6798 * Polling 'interrupt' - used by things like netconsole to send skbs
6799 * without having to re-enable interrupts. It's not called while
6800 * the interrupt routine is executing.
6801 */
6802static void ixgbe_netpoll(struct net_device *netdev)
6803{
6804 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6805 int i;
9a799d71 6806
1a647bd2
AD		 6807 /* if interface is down do nothing */
6808 if (test_bit(__IXGBE_DOWN, &adapter->state))
6809 return;
6810
9a799d71 6811 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6812 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6813 for (i = 0; i < adapter->num_q_vectors; i++)
6814 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6815 } else {
6816 ixgbe_intr(adapter->pdev->irq, netdev);
6817 }
9a799d71 6818 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6819}
9a799d71 6820
581330ba 6821#endif
de1036b1
ED		 6822static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6823 struct rtnl_link_stats64 *stats)
6824{
6825 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6826 int i;
6827
1a51502b 6828 rcu_read_lock();
de1036b1 6829 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6830 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6831 u64 bytes, packets;
6832 unsigned int start;
6833
1a51502b
ED		 6834 if (ring) {
6835 do {
6836 start = u64_stats_fetch_begin_bh(&ring->syncp);
6837 packets = ring->stats.packets;
6838 bytes = ring->stats.bytes;
6839 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6840 stats->rx_packets += packets;
6841 stats->rx_bytes += bytes;
6842 }
de1036b1 6843 }
1ac9ad13
ED		 6844
6845 for (i = 0; i < adapter->num_tx_queues; i++) {
6846 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6847 u64 bytes, packets;
6848 unsigned int start;
6849
6850 if (ring) {
6851 do {
6852 start = u64_stats_fetch_begin_bh(&ring->syncp);
6853 packets = ring->stats.packets;
6854 bytes = ring->stats.bytes;
6855 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6856 stats->tx_packets += packets;
6857 stats->tx_bytes += bytes;
6858 }
6859 }
1a51502b 6860 rcu_read_unlock();
de1036b1
ED		 6861 /* following stats updated by ixgbe_watchdog_task() */
6862 stats->multicast = netdev->stats.multicast;
6863 stats->rx_errors = netdev->stats.rx_errors;
6864 stats->rx_length_errors = netdev->stats.rx_length_errors;
6865 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6866 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6867 return stats;
6868}
6869
8af3c33f 6870#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6871/**
6872 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6873 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6874 * @tc: number of traffic classes currently enabled
6875 *
6876 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6877 * 802.1Q priority maps to a packet buffer that exists.
6878 */
6879static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6880{
6881 struct ixgbe_hw *hw = &adapter->hw;
6882 u32 reg, rsave;
6883 int i;
6884
6885 /* 82598 have a static priority to TC mapping that can not
6886 * be changed so no validation is needed.
6887 */
6888 if (hw->mac.type == ixgbe_mac_82598EB)
6889 return;
6890
6891 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6892 rsave = reg;
6893
6894 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6895 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6896
6897 /* If up2tc is out of bounds default to zero */
6898 if (up2tc > tc)
6899 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6900 }
6901
6902 if (reg != rsave)
6903 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6904
6905 return;
6906}
6907
02debdc9
AD		 6908/**
6909 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6910 * @adapter: Pointer to adapter struct
6911 *
6912 * Populate the netdev user priority to tc map
6913 */
6914static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6915{
6916 struct net_device *dev = adapter->netdev;
6917 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6918 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6919 u8 prio;
6920
6921 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6922 u8 tc = 0;
6923
6924 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6925 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6926 else if (ets)
6927 tc = ets->prio_tc[prio];
6928
6929 netdev_set_prio_tc_map(dev, prio, tc);
6930 }
6931}
6932
cca73c59 6933#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 6934/**
6935 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6936 *
6937 * @netdev: net device to configure
6938 * @tc: number of traffic classes to enable
6939 */
6940int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6941{
8b1c0b24
JF		 6942 struct ixgbe_adapter *adapter = netdev_priv(dev);
6943 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6944
8b1c0b24 6945 /* Hardware supports up to 8 traffic classes */
4de2a022 6946 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6947 (hw->mac.type == ixgbe_mac_82598EB &&
6948 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6949 return -EINVAL;
6950
6951 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6952 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6953 * hardware is not flexible enough to do this dynamically.
6954 */
6955 if (netif_running(dev))
6956 ixgbe_close(dev);
6957 ixgbe_clear_interrupt_scheme(adapter);
6958
cca73c59 6959#ifdef CONFIG_IXGBE_DCB
e7589eab 6960 if (tc) {
8b1c0b24 6961 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6962 ixgbe_set_prio_tc_map(adapter);
6963
e7589eab 6964 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6965
943561d3
AD		 6966 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6967 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6968 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6969 }
e7589eab 6970 } else {
8b1c0b24 6971 netdev_reset_tc(dev);
02debdc9 6972
943561d3
AD		 6973 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6974 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6975
6976 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6977
6978 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6979 adapter->dcb_cfg.pfc_mode_enable = false;
6980 }
6981
8b1c0b24 6982 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 6983
6984#endif /* CONFIG_IXGBE_DCB */
6985 ixgbe_init_interrupt_scheme(adapter);
6986
8b1c0b24 6987 if (netif_running(dev))
cca73c59 6988 return ixgbe_open(dev);
8b1c0b24
JF		 6989
6990 return 0;
6991}
de1036b1 6992
da36b647
GR		 6993#ifdef CONFIG_PCI_IOV
6994void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
6995{
6996 struct net_device *netdev = adapter->netdev;
6997
6998 rtnl_lock();
da36b647 6999 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7000 rtnl_unlock();
7001}
7002
7003#endif
082757af
DS		 7004void ixgbe_do_reset(struct net_device *netdev)
7005{
7006 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7007
7008 if (netif_running(netdev))
7009 ixgbe_reinit_locked(adapter);
7010 else
7011 ixgbe_reset(adapter);
7012}
7013
c8f44aff 7014static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7015 netdev_features_t features)
082757af
DS		 7016{
7017 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7018
082757af 7019 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7020 if (!(features & NETIF_F_RXCSUM))
7021 features &= ~NETIF_F_LRO;
082757af 7022
567d2de2
AD		 7023 /* Turn off LRO if not RSC capable */
7024 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7025 features &= ~NETIF_F_LRO;
8e2813f5 7026
567d2de2 7027 return features;
082757af
DS		 7028}
7029
c8f44aff 7030static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7031 netdev_features_t features)
082757af
DS		 7032{
7033 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7034 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7035 bool need_reset = false;
7036
082757af 7037 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7038 if (!(features & NETIF_F_LRO)) {
7039 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7040 need_reset = true;
567d2de2
AD		 7041 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7042 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7043 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7044 if (adapter->rx_itr_setting == 1 ||
7045 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7046 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7047 need_reset = true;
7048 } else if ((changed ^ features) & NETIF_F_LRO) {
7049 e_info(probe, "rx-usecs set too low, "
7050 "disabling RSC\n");
082757af
DS		 7051 }
7052 }
7053
7054 /*
7055 * Check if Flow Director n-tuple support was enabled or disabled. If
7056 * the state changed, we need to reset.
7057 */
39cb681b
AD		 7058 switch (features & NETIF_F_NTUPLE) {
7059 case NETIF_F_NTUPLE:
567d2de2 7060 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7061 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7062 need_reset = true;
7063
567d2de2
AD		 7064 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7065 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7066 break;
7067 default:
7068 /* turn off perfect filters, enable ATR and reset */
7069 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7070 need_reset = true;
7071
7072 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7073
7074 /* We cannot enable ATR if SR-IOV is enabled */
7075 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7076 break;
7077
7078 /* We cannot enable ATR if we have 2 or more traffic classes */
7079 if (netdev_get_num_tc(netdev) > 1)
7080 break;
7081
7082 /* We cannot enable ATR if RSS is disabled */
7083 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7084 break;
7085
7086 /* A sample rate of 0 indicates ATR disabled */
7087 if (!adapter->atr_sample_rate)
7088 break;
7089
7090 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7091 break;
082757af
DS		 7092 }
7093
f646968f 7094 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7095 ixgbe_vlan_strip_enable(adapter);
7096 else
7097 ixgbe_vlan_strip_disable(adapter);
7098
3f2d1c0f
BG		 7099 if (changed & NETIF_F_RXALL)
7100 need_reset = true;
7101
567d2de2 7102 netdev->features = features;
082757af
DS		 7103 if (need_reset)
7104 ixgbe_do_reset(netdev);
7105
7106 return 0;
082757af
DS		 7107}
7108
edc7d573 7109static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7110 struct net_device *dev,
6b6e2725 7111 const unsigned char *addr,
0f4b0add
JF		 7112 u16 flags)
7113{
7114 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7115 int err;
7116
7117 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7118 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7119
b1ac1ef7
JF		 7120 /* Hardware does not support aging addresses so if a
7121 * ndm_state is given only allow permanent addresses
7122 */
7123 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7124 pr_info("%s: FDB only supports static addresses\n",
7125 ixgbe_driver_name);
7126 return -EINVAL;
7127 }
7128
46acc460 7129 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7130 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7131
7132 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7133 err = dev_uc_add_excl(dev, addr);
0f4b0add 7134 else
95447461
JF		 7135 err = -ENOMEM;
7136 } else if (is_multicast_ether_addr(addr)) {
7137 err = dev_mc_add_excl(dev, addr);
7138 } else {
7139 err = -EINVAL;
0f4b0add
JF		 7140 }
7141
7142 /* Only return duplicate errors if NLM_F_EXCL is set */
7143 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7144 err = 0;
7145
7146 return err;
7147}
7148
815cccbf
JF		 7149static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7150 struct nlmsghdr *nlh)
7151{
7152 struct ixgbe_adapter *adapter = netdev_priv(dev);
7153 struct nlattr *attr, *br_spec;
7154 int rem;
7155
7156 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7157 return -EOPNOTSUPP;
7158
7159 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7160
7161 nla_for_each_nested(attr, br_spec, rem) {
7162 __u16 mode;
7163 u32 reg = 0;
7164
7165 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7166 continue;
7167
7168 mode = nla_get_u16(attr);
9b735984 7169 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7170 reg = 0;
9b735984
GR		 7171 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7172 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7173 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7174 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7175 } else
815cccbf
JF		 7176 return -EINVAL;
7177
7178 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7179
7180 e_info(drv, "enabling bridge mode: %s\n",
7181 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7182 }
7183
7184 return 0;
7185}
7186
7187static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7188 struct net_device *dev,
7189 u32 filter_mask)
815cccbf
JF		 7190{
7191 struct ixgbe_adapter *adapter = netdev_priv(dev);
7192 u16 mode;
7193
7194 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7195 return 0;
7196
9b735984 7197 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7198 mode = BRIDGE_MODE_VEB;
7199 else
7200 mode = BRIDGE_MODE_VEPA;
7201
7202 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7203}
7204
0edc3527 7205static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7206 .ndo_open = ixgbe_open,
0edc3527 7207 .ndo_stop = ixgbe_close,
00829823 7208 .ndo_start_xmit = ixgbe_xmit_frame,
97488bd1 7209#ifdef IXGBE_FCOE
09a3b1f8 7210 .ndo_select_queue = ixgbe_select_queue,
97488bd1 7211#endif
581330ba 7212 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7213 .ndo_validate_addr = eth_validate_addr,
7214 .ndo_set_mac_address = ixgbe_set_mac,
7215 .ndo_change_mtu = ixgbe_change_mtu,
7216 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7217 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7218 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7219 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7220 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7221 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7222 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7223 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7224 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7225 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7226#ifdef CONFIG_IXGBE_DCB
24095aa3 7227 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7228#endif
0edc3527
SH		 7229#ifdef CONFIG_NET_POLL_CONTROLLER
7230 .ndo_poll_controller = ixgbe_netpoll,
7231#endif
5a85e737 7232#ifdef CONFIG_NET_LL_RX_POLL
8b80cda5 7233 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7234#endif
332d4a7d
YZ		 7235#ifdef IXGBE_FCOE
7236 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7237 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7238 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7239 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7240 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7241 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7242 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7243#endif /* IXGBE_FCOE */
082757af
DS		 7244 .ndo_set_features = ixgbe_set_features,
7245 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7246 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7247 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7248 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
0edc3527
SH		 7249};
7250
8e2813f5
JK		 7251/**
7252 * ixgbe_wol_supported - Check whether device supports WoL
7253 * @hw: hw specific details
7254 * @device_id: the device ID
7255 * @subdev_id: the subsystem device ID
7256 *
7257 * This function is used by probe and ethtool to determine
7258 * which devices have WoL support
7259 *
7260 **/
7261int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7262 u16 subdevice_id)
7263{
7264 struct ixgbe_hw *hw = &adapter->hw;
7265 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7266 int is_wol_supported = 0;
7267
7268 switch (device_id) {
7269 case IXGBE_DEV_ID_82599_SFP:
7270 /* Only these subdevices could supports WOL */
7271 switch (subdevice_id) {
7272 case IXGBE_SUBDEV_ID_82599_560FLR:
7273 /* only support first port */
7274 if (hw->bus.func != 0)
7275 break;
5700ff26 7276 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7277 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7278 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7279 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7280 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7281 is_wol_supported = 1;
7282 break;
7283 }
7284 break;
5daebbb0
DS		 7285 case IXGBE_DEV_ID_82599EN_SFP:
7286 /* Only this subdevice supports WOL */
7287 switch (subdevice_id) {
7288 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7289 is_wol_supported = 1;
7290 break;
7291 }
7292 break;
8e2813f5
JK		 7293 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7294 /* All except this subdevice support WOL */
7295 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7296 is_wol_supported = 1;
7297 break;
7298 case IXGBE_DEV_ID_82599_KX4:
7299 is_wol_supported = 1;
7300 break;
7301 case IXGBE_DEV_ID_X540T:
df376f0d 7302 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7303 /* check eeprom to see if enabled wol */
7304 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7305 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7306 (hw->bus.func == 0))) {
7307 is_wol_supported = 1;
7308 }
7309 break;
7310 }
7311
7312 return is_wol_supported;
7313}
7314
9a799d71
AK		 7315/**
7316 * ixgbe_probe - Device Initialization Routine
7317 * @pdev: PCI device information struct
7318 * @ent: entry in ixgbe_pci_tbl
7319 *
7320 * Returns 0 on success, negative on failure
7321 *
7322 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7323 * The OS initialization, configuring of the adapter private structure,
7324 * and a hardware reset occur.
7325 **/
1dd06ae8 7326static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7327{
7328 struct net_device *netdev;
7329 struct ixgbe_adapter *adapter = NULL;
7330 struct ixgbe_hw *hw;
7331 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7332 static int cards_found;
7333 int i, err, pci_using_dac;
d3cb9869 7334 unsigned int indices = MAX_TX_QUEUES;
289700db 7335 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7336#ifdef IXGBE_FCOE
7337 u16 device_caps;
7338#endif
289700db 7339 u32 eec;
9a799d71 7340
bded64a7
AG		 7341 /* Catch broken hardware that put the wrong VF device ID in
7342 * the PCIe SR-IOV capability.
7343 */
7344 if (pdev->is_virtfn) {
7345 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7346 pci_name(pdev), pdev->vendor, pdev->device);
7347 return -EINVAL;
7348 }
7349
9ce77666 7350 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7351 if (err)
7352 return err;
7353
1b507730
NN		 7354 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7355 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7356 pci_using_dac = 1;
7357 } else {
1b507730 7358 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7359 if (err) {
1b507730
NN		 7360 err = dma_set_coherent_mask(&pdev->dev,
7361 DMA_BIT_MASK(32));
9a799d71 7362 if (err) {
b8bc0421
DC		 7363 dev_err(&pdev->dev,
7364 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7365 goto err_dma;
7366 }
7367 }
7368 pci_using_dac = 0;
7369 }
7370
9ce77666 7371 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7372 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7373 if (err) {
b8bc0421
DC		 7374 dev_err(&pdev->dev,
7375 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7376 goto err_pci_reg;
7377 }
7378
19d5afd4 7379 pci_enable_pcie_error_reporting(pdev);
6fabd715 7380
9a799d71 7381 pci_set_master(pdev);
fb3b27bc 7382 pci_save_state(pdev);
9a799d71 7383
d3cb9869 7384 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7385#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7386 /* 8 TC w/ 4 queues per TC */
7387 indices = 4 * MAX_TRAFFIC_CLASS;
7388#else
7389 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7390#endif
d3cb9869 7391 }
e901acd6 7392
c85a2618 7393 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7394 if (!netdev) {
7395 err = -ENOMEM;
7396 goto err_alloc_etherdev;
7397 }
7398
9a799d71
AK		 7399 SET_NETDEV_DEV(netdev, &pdev->dev);
7400
9a799d71 7401 adapter = netdev_priv(netdev);
c60fbb00 7402 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7403
7404 adapter->netdev = netdev;
7405 adapter->pdev = pdev;
7406 hw = &adapter->hw;
7407 hw->back = adapter;
b3f4d599 7408 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7409
05857980 7410 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7411 pci_resource_len(pdev, 0));
9a799d71
AK		 7412 if (!hw->hw_addr) {
7413 err = -EIO;
7414 goto err_ioremap;
7415 }
7416
0edc3527 7417 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7418 ixgbe_set_ethtool_ops(netdev);
9a799d71 7419 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7420 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7421
9a799d71
AK		 7422 adapter->bd_number = cards_found;
7423
9a799d71
AK		 7424 /* Setup hw api */
7425 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7426 hw->mac.type = ii->mac;
9a799d71 7427
c44ade9e
JB		 7428 /* EEPROM */
7429 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7430 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7431 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7432 if (!(eec & (1 << 8)))
7433 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7434
7435 /* PHY */
7436 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7437 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7438 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7439 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7440 hw->phy.mdio.mmds = 0;
7441 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7442 hw->phy.mdio.dev = netdev;
7443 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7444 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7445
8ca783ab 7446 ii->get_invariants(hw);
9a799d71
AK		 7447
7448 /* setup the private structure */
7449 err = ixgbe_sw_init(adapter);
7450 if (err)
7451 goto err_sw_init;
7452
0b2679d6
DS		 7453 /* Cache if MNG FW is up so we don't have to read the REG later */
7454 if (hw->mac.ops.mng_fw_enabled)
7455 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7456
e86bff0e 7457 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7458 switch (adapter->hw.mac.type) {
7459 case ixgbe_mac_82599EB:
7460 case ixgbe_mac_X540:
e86bff0e 7461 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7462 break;
7463 default:
7464 break;
7465 }
e86bff0e 7466
bf069c97
DS		 7467 /*
7468 * If there is a fan on this device and it has failed log the
7469 * failure.
7470 */
7471 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7472 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7473 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7474 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7475 }
7476
8ef78adc
PWJ		 7477 if (allow_unsupported_sfp)
7478 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7479
c44ade9e 7480 /* reset_hw fills in the perm_addr as well */
119fc60a 7481 hw->phy.reset_if_overtemp = true;
c44ade9e 7482 err = hw->mac.ops.reset_hw(hw);
119fc60a 7483 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7484 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7485 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7486 err = 0;
7487 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7488 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7489 "module type was detected.\n");
7490 e_dev_err("Reload the driver after installing a supported "
7491 "module.\n");
04f165ef
PW		 7492 goto err_sw_init;
7493 } else if (err) {
849c4542 7494 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7495 goto err_sw_init;
7496 }
7497
99d74487 7498#ifdef CONFIG_PCI_IOV
60a1a680
GR		 7499 /* SR-IOV not supported on the 82598 */
7500 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7501 goto skip_sriov;
7502 /* Mailbox */
7503 ixgbe_init_mbx_params_pf(hw);
7504 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7505 ixgbe_enable_sriov(adapter);
43dc4e01 7506 pci_sriov_set_totalvfs(pdev, 63);
60a1a680 7507skip_sriov:
1cdd1ec8 7508
99d74487 7509#endif
396e799c 7510 netdev->features = NETIF_F_SG |
e8e9f696 7511 NETIF_F_IP_CSUM |
082757af 7512 NETIF_F_IPV6_CSUM |
f646968f
PM		 7513 NETIF_F_HW_VLAN_CTAG_TX |
7514 NETIF_F_HW_VLAN_CTAG_RX |
7515 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 7516 NETIF_F_TSO |
7517 NETIF_F_TSO6 |
082757af
DS		 7518 NETIF_F_RXHASH |
7519 NETIF_F_RXCSUM;
9a799d71 7520
082757af 7521 netdev->hw_features = netdev->features;
ad31c402 7522
58be7666
DS		 7523 switch (adapter->hw.mac.type) {
7524 case ixgbe_mac_82599EB:
7525 case ixgbe_mac_X540:
45a5ead0 7526 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7527 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7528 NETIF_F_NTUPLE;
58be7666
DS		 7529 break;
7530 default:
7531 break;
7532 }
45a5ead0 7533
3f2d1c0f
BG		 7534 netdev->hw_features |= NETIF_F_RXALL;
7535
ad31c402
JK		 7536 netdev->vlan_features |= NETIF_F_TSO;
7537 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7538 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7539 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7540 netdev->vlan_features |= NETIF_F_SG;
7541
01789349 7542 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7543 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7544
7a6b6f51 7545#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7546 netdev->dcbnl_ops = &dcbnl_ops;
7547#endif
7548
eacd73f7 7549#ifdef IXGBE_FCOE
0d551589 7550 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 7551 unsigned int fcoe_l;
7552
eacd73f7
YZ		 7553 if (hw->mac.ops.get_device_caps) {
7554 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7555 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7556 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7557 }
7c8ae65a 7558
d3cb9869
AD		 7559
7560 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7561 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 7562
a58915c7
AD		 7563 netdev->features |= NETIF_F_FSO |
7564 NETIF_F_FCOE_CRC;
7565
7c8ae65a
AD		 7566 netdev->vlan_features |= NETIF_F_FSO |
7567 NETIF_F_FCOE_CRC |
7568 NETIF_F_FCOE_MTU;
5e09d7f6 7569 }
eacd73f7 7570#endif /* IXGBE_FCOE */
7b872a55 7571 if (pci_using_dac) {
9a799d71 7572 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7573 netdev->vlan_features |= NETIF_F_HIGHDMA;
7574 }
9a799d71 7575
082757af
DS		 7576 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7577 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7578 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7579 netdev->features |= NETIF_F_LRO;
7580
9a799d71 7581 /* make sure the EEPROM is good */
c44ade9e 7582 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7583 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7584 err = -EIO;
35937c05 7585 goto err_sw_init;
9a799d71
AK		 7586 }
7587
7588 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 7589
aaeb6cdf 7590 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 7591 e_dev_err("invalid MAC address\n");
9a799d71 7592 err = -EIO;
35937c05 7593 goto err_sw_init;
9a799d71
AK		 7594 }
7595
7086400d 7596 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7597 (unsigned long) adapter);
9a799d71 7598
7086400d
AD		 7599 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7600 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7601
021230d4
AV		 7602 err = ixgbe_init_interrupt_scheme(adapter);
7603 if (err)
7604 goto err_sw_init;
9a799d71 7605
8e2813f5 7606 /* WOL not supported for all devices */
c23f5b6b 7607 adapter->wol = 0;
8e2813f5 7608 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 7609 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 7610 pdev->subsystem_device);
6b92b0ba 7611 if (hw->wol_enabled)
9417c464 7612 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7613
e8e26350
PW		 7614 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7615
15e5209f
ET		 7616 /* save off EEPROM version number */
7617 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7618 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7619
04f165ef
PW		 7620 /* pick up the PCI bus settings for reporting later */
7621 hw->mac.ops.get_bus_info(hw);
b8e82001
JK		 7622 if (hw->device_id == IXGBE_DEV_ID_82599_SFP_SF_QP)
7623 ixgbe_get_parent_bus_info(adapter);
04f165ef 7624
9a799d71 7625 /* print bus type/speed/width info */
849c4542 7626 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8710a5f
JK		 7627 (hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
7628 hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
6716344c 7629 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7630 "Unknown"),
7631 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7632 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7633 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7634 "Unknown"),
7635 netdev->dev_addr);
289700db
DS		 7636
7637 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7638 if (err)
9fe93afd 7639 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7640 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7641 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7642 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7643 part_str);
e8e26350 7644 else
289700db
DS		 7645 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7646 hw->mac.type, hw->phy.type, part_str);
9a799d71 7647
e8e26350 7648 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7649 e_dev_warn("PCI-Express bandwidth available for this card is "
7650 "not sufficient for optimal performance.\n");
7651 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7652 "is required.\n");
0c254d86
AK		 7653 }
7654
9a799d71 7655 /* reset the hardware with the new settings */
794caeb2 7656 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7657 if (err == IXGBE_ERR_EEPROM_VERSION) {
7658 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7659 e_dev_warn("This device is a pre-production adapter/LOM. "
7660 "Please be aware there may be issues associated "
7661 "with your hardware. If you are experiencing "
7662 "problems please contact your Intel or hardware "
7663 "representative who provided you with this "
7664 "hardware.\n");
794caeb2 7665 }
9a799d71
AK		 7666 strcpy(netdev->name, "eth%d");
7667 err = register_netdev(netdev);
7668 if (err)
7669 goto err_register;
7670
ec74a471
ET		 7671 /* power down the optics for 82599 SFP+ fiber */
7672 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 7673 hw->mac.ops.disable_tx_laser(hw);
7674
54386467
JB		 7675 /* carrier off reporting is important to ethtool even BEFORE open */
7676 netif_carrier_off(netdev);
7677
5dd2d332 7678#ifdef CONFIG_IXGBE_DCA
652f093f 7679 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7680 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7681 ixgbe_setup_dca(adapter);
7682 }
7683#endif
1cdd1ec8 7684 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7685 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7686 for (i = 0; i < adapter->num_vfs; i++)
7687 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7688 }
7689
2466dd9c
JK		 7690 /* firmware requires driver version to be 0xFFFFFFFF
7691 * since os does not support feature
7692 */
9612de92 7693 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7694 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7695 0xFF);
9612de92 7696
0365e6e4
PW		 7697 /* add san mac addr to netdev */
7698 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7699
ea81875a 7700 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7701 cards_found++;
3ca8bc6d 7702
1210982b 7703#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7704 if (ixgbe_sysfs_init(adapter))
7705 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7706#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7707
00949167 7708 ixgbe_dbg_adapter_init(adapter);
00949167 7709
0b2679d6
DS		 7710 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7711 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7712 hw->mac.ops.setup_link(hw,
7713 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7714 true);
7715
9a799d71
AK		 7716 return 0;
7717
7718err_register:
5eba3699 7719 ixgbe_release_hw_control(adapter);
7a921c93 7720 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7721err_sw_init:
99d74487 7722 ixgbe_disable_sriov(adapter);
7086400d 7723 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7724 iounmap(hw->hw_addr);
7725err_ioremap:
7726 free_netdev(netdev);
7727err_alloc_etherdev:
e8e9f696
JP		 7728 pci_release_selected_regions(pdev,
7729 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7730err_pci_reg:
7731err_dma:
7732 pci_disable_device(pdev);
7733 return err;
7734}
7735
7736/**
7737 * ixgbe_remove - Device Removal Routine
7738 * @pdev: PCI device information struct
7739 *
7740 * ixgbe_remove is called by the PCI subsystem to alert the driver
7741 * that it should release a PCI device. The could be caused by a
7742 * Hot-Plug event, or because the driver is going to be removed from
7743 * memory.
7744 **/
9f9a12f8 7745static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 7746{
c60fbb00
AD		 7747 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7748 struct net_device *netdev = adapter->netdev;
9a799d71 7749
00949167 7750 ixgbe_dbg_adapter_exit(adapter);
00949167 7751
9a799d71 7752 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7753 cancel_work_sync(&adapter->service_task);
9a799d71 7754
3a6a4eda 7755
5dd2d332 7756#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7757 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7758 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7759 dca_remove_requester(&pdev->dev);
7760 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7761 }
7762
7763#endif
1210982b 7764#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7765 ixgbe_sysfs_exit(adapter);
1210982b 7766#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7767
0365e6e4
PW		 7768 /* remove the added san mac */
7769 ixgbe_del_sanmac_netdev(netdev);
7770
c4900be0
DS		 7771 if (netdev->reg_state == NETREG_REGISTERED)
7772 unregister_netdev(netdev);
9a799d71 7773
da36b647
GR		 7774#ifdef CONFIG_PCI_IOV
7775 /*
7776 * Only disable SR-IOV on unload if the user specified the now
7777 * deprecated max_vfs module parameter.
7778 */
7779 if (max_vfs)
7780 ixgbe_disable_sriov(adapter);
7781#endif
7a921c93 7782 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7783
021230d4 7784 ixgbe_release_hw_control(adapter);
9a799d71 7785
2b1588c3
AD		 7786#ifdef CONFIG_DCB
7787 kfree(adapter->ixgbe_ieee_pfc);
7788 kfree(adapter->ixgbe_ieee_ets);
7789
7790#endif
9a799d71 7791 iounmap(adapter->hw.hw_addr);
9ce77666 7792 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7793 IORESOURCE_MEM));
9a799d71 7794
849c4542 7795 e_dev_info("complete\n");
021230d4 7796
9a799d71
AK		 7797 free_netdev(netdev);
7798
19d5afd4 7799 pci_disable_pcie_error_reporting(pdev);
6fabd715 7800
9a799d71
AK		 7801 pci_disable_device(pdev);
7802}
7803
7804/**
7805 * ixgbe_io_error_detected - called when PCI error is detected
7806 * @pdev: Pointer to PCI device
7807 * @state: The current pci connection state
7808 *
7809 * This function is called after a PCI bus error affecting
7810 * this device has been detected.
7811 */
7812static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7813 pci_channel_state_t state)
9a799d71 7814{
c60fbb00
AD		 7815 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7816 struct net_device *netdev = adapter->netdev;
9a799d71 7817
83c61fa9
GR		 7818#ifdef CONFIG_PCI_IOV
7819 struct pci_dev *bdev, *vfdev;
7820 u32 dw0, dw1, dw2, dw3;
7821 int vf, pos;
7822 u16 req_id, pf_func;
7823
7824 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7825 adapter->num_vfs == 0)
7826 goto skip_bad_vf_detection;
7827
7828 bdev = pdev->bus->self;
62f87c0e 7829 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 7830 bdev = bdev->bus->self;
7831
7832 if (!bdev)
7833 goto skip_bad_vf_detection;
7834
7835 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7836 if (!pos)
7837 goto skip_bad_vf_detection;
7838
7839 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7840 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7841 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7842 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7843
7844 req_id = dw1 >> 16;
7845 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7846 if (!(req_id & 0x0080))
7847 goto skip_bad_vf_detection;
7848
7849 pf_func = req_id & 0x01;
7850 if ((pf_func & 1) == (pdev->devfn & 1)) {
7851 unsigned int device_id;
7852
7853 vf = (req_id & 0x7F) >> 1;
7854 e_dev_err("VF %d has caused a PCIe error\n", vf);
7855 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7856 "%8.8x\tdw3: %8.8x\n",
7857 dw0, dw1, dw2, dw3);
7858 switch (adapter->hw.mac.type) {
7859 case ixgbe_mac_82599EB:
7860 device_id = IXGBE_82599_VF_DEVICE_ID;
7861 break;
7862 case ixgbe_mac_X540:
7863 device_id = IXGBE_X540_VF_DEVICE_ID;
7864 break;
7865 default:
7866 device_id = 0;
7867 break;
7868 }
7869
7870 /* Find the pci device of the offending VF */
36e90319 7871 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7872 while (vfdev) {
7873 if (vfdev->devfn == (req_id & 0xFF))
7874 break;
36e90319 7875 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7876 device_id, vfdev);
7877 }
7878 /*
7879 * There's a slim chance the VF could have been hot plugged,
7880 * so if it is no longer present we don't need to issue the
7881 * VFLR. Just clean up the AER in that case.
7882 */
7883 if (vfdev) {
7884 e_dev_err("Issuing VFLR to VF %d\n", vf);
7885 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 7886 /* Free device reference count */
7887 pci_dev_put(vfdev);
83c61fa9
GR		 7888 }
7889
7890 pci_cleanup_aer_uncorrect_error_status(pdev);
7891 }
7892
7893 /*
7894 * Even though the error may have occurred on the other port
7895 * we still need to increment the vf error reference count for
7896 * both ports because the I/O resume function will be called
7897 * for both of them.
7898 */
7899 adapter->vferr_refcount++;
7900
7901 return PCI_ERS_RESULT_RECOVERED;
7902
7903skip_bad_vf_detection:
7904#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7905 netif_device_detach(netdev);
7906
3044b8d1
BL		 7907 if (state == pci_channel_io_perm_failure)
7908 return PCI_ERS_RESULT_DISCONNECT;
7909
9a799d71
AK		 7910 if (netif_running(netdev))
7911 ixgbe_down(adapter);
7912 pci_disable_device(pdev);
7913
b4617240 7914 /* Request a slot reset. */
9a799d71
AK		 7915 return PCI_ERS_RESULT_NEED_RESET;
7916}
7917
7918/**
7919 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7920 * @pdev: Pointer to PCI device
7921 *
7922 * Restart the card from scratch, as if from a cold-boot.
7923 */
7924static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7925{
c60fbb00 7926 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7927 pci_ers_result_t result;
7928 int err;
9a799d71 7929
9ce77666 7930 if (pci_enable_device_mem(pdev)) {
396e799c 7931 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7932 result = PCI_ERS_RESULT_DISCONNECT;
7933 } else {
7934 pci_set_master(pdev);
7935 pci_restore_state(pdev);
c0e1f68b 7936 pci_save_state(pdev);
9a799d71 7937
dd4d8ca6 7938 pci_wake_from_d3(pdev, false);
9a799d71 7939
6fabd715 7940 ixgbe_reset(adapter);
88512539 7941 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7942 result = PCI_ERS_RESULT_RECOVERED;
7943 }
7944
7945 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7946 if (err) {
849c4542
ET		 7947 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7948 "failed 0x%0x\n", err);
6fabd715
PWJ		 7949 /* non-fatal, continue */
7950 }
9a799d71 7951
6fabd715 7952 return result;
9a799d71
AK		 7953}
7954
7955/**
7956 * ixgbe_io_resume - called when traffic can start flowing again.
7957 * @pdev: Pointer to PCI device
7958 *
7959 * This callback is called when the error recovery driver tells us that
7960 * its OK to resume normal operation.
7961 */
7962static void ixgbe_io_resume(struct pci_dev *pdev)
7963{
c60fbb00
AD		 7964 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7965 struct net_device *netdev = adapter->netdev;
9a799d71 7966
83c61fa9
GR		 7967#ifdef CONFIG_PCI_IOV
7968 if (adapter->vferr_refcount) {
7969 e_info(drv, "Resuming after VF err\n");
7970 adapter->vferr_refcount--;
7971 return;
7972 }
7973
7974#endif
c7ccde0f
AD		 7975 if (netif_running(netdev))
7976 ixgbe_up(adapter);
9a799d71
AK		 7977
7978 netif_device_attach(netdev);
9a799d71
AK		 7979}
7980
3646f0e5 7981static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 7982 .error_detected = ixgbe_io_error_detected,
7983 .slot_reset = ixgbe_io_slot_reset,
7984 .resume = ixgbe_io_resume,
7985};
7986
7987static struct pci_driver ixgbe_driver = {
7988 .name = ixgbe_driver_name,
7989 .id_table = ixgbe_pci_tbl,
7990 .probe = ixgbe_probe,
9f9a12f8 7991 .remove = ixgbe_remove,
9a799d71
AK		 7992#ifdef CONFIG_PM
7993 .suspend = ixgbe_suspend,
7994 .resume = ixgbe_resume,
7995#endif
7996 .shutdown = ixgbe_shutdown,
da36b647 7997 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 7998 .err_handler = &ixgbe_err_handler
7999};
8000
8001/**
8002 * ixgbe_init_module - Driver Registration Routine
8003 *
8004 * ixgbe_init_module is the first routine called when the driver is
8005 * loaded. All it does is register with the PCI subsystem.
8006 **/
8007static int __init ixgbe_init_module(void)
8008{
8009 int ret;
c7689578 8010 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8011 pr_info("%s\n", ixgbe_copyright);
9a799d71 8012
00949167 8013 ixgbe_dbg_init();
00949167 8014
f01fc1a8
JK		 8015 ret = pci_register_driver(&ixgbe_driver);
8016 if (ret) {
f01fc1a8 8017 ixgbe_dbg_exit();
f01fc1a8
JK		 8018 return ret;
8019 }
8020
5dd2d332 8021#ifdef CONFIG_IXGBE_DCA
bd0362dd 8022 dca_register_notify(&dca_notifier);
bd0362dd 8023#endif
5dd2d332 8024
f01fc1a8 8025 return 0;
9a799d71 8026}
b4617240 8027
9a799d71
AK		 8028module_init(ixgbe_init_module);
8029
8030/**
8031 * ixgbe_exit_module - Driver Exit Cleanup Routine
8032 *
8033 * ixgbe_exit_module is called just before the driver is removed
8034 * from memory.
8035 **/
8036static void __exit ixgbe_exit_module(void)
8037{
5dd2d332 8038#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8039 dca_unregister_notify(&dca_notifier);
8040#endif
9a799d71 8041 pci_unregister_driver(&ixgbe_driver);
00949167 8042
00949167 8043 ixgbe_dbg_exit();
00949167 8044
1a51502b 8045 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8046}
bd0362dd 8047
5dd2d332 8048#ifdef CONFIG_IXGBE_DCA
bd0362dd 8049static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8050 void *p)
bd0362dd
JC		 8051{
8052 int ret_val;
8053
8054 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8055 __ixgbe_notify_dca);
bd0362dd
JC		 8056
8057 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8058}
b453368d 8059
5dd2d332 8060#endif /* CONFIG_IXGBE_DCA */
849c4542 8061
9a799d71
AK		 8062module_exit(ixgbe_exit_module);
8063
8064/* ixgbe_main.c */
Linux kernel - Deliverables
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