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ixgbe: Fix memory leak in ixgbe when receiving traffic on DDP enabled rings
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
7086400d
AD		 154static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155{
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159}
160
161static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162{
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
52f33af8 165 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168}
169
dcd79aeb
TI		 170struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173};
174
175static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205};
206
207
208/*
209 * ixgbe_regdump - register printout routine
210 */
211static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212{
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
c7689578 275 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 282 pr_err("%-15s", rname);
dcd79aeb 283 for (j = 0; j < 8; j++)
c7689578
JP		 284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
dcd79aeb
TI		 286 }
287
288}
289
290/*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293static void ixgbe_dump(struct ixgbe_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
729739b7 300 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 315 pr_info("Device Name state "
dcd79aeb 316 "trans_start last_rx\n");
c7689578
JP		 317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
dcd79aeb
TI		 322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 326 pr_info(" Register Name Value\n");
dcd79aeb
TI		 327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
c7689578
JP		 368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 377 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 378 u0 = (struct my_u0 *)tx_desc;
c7689578 379 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 380 " %04X %p %016llX %p", i,
dcd79aeb
TI		 381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
729739b7
AD		 383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
dcd79aeb
TI		 388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
c7689578 390 pr_cont(" NTC/U\n");
dcd79aeb 391 else if (i == tx_ring->next_to_use)
c7689578 392 pr_cont(" NTU\n");
dcd79aeb 393 else if (i == tx_ring->next_to_clean)
c7689578 394 pr_cont(" NTC\n");
dcd79aeb 395 else
c7689578 396 pr_cont("\n");
dcd79aeb
TI		 397
398 if (netif_msg_pktdata(adapter) &&
729739b7 399 dma_unmap_len(tx_buffer, len) != 0)
dcd79aeb
TI		 400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
729739b7
AD		 402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
dcd79aeb
TI		 406 }
407 }
408
409 /* Print RX Rings Summary */
410rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 412 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
c7689578
JP		 415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
c7689578
JP		 447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
c7689578 453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
c7689578 464 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
c7689578 470 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
f800326d 481 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 482 }
483 }
484
485 if (i == rx_ring->next_to_use)
c7689578 486 pr_cont(" NTU\n");
dcd79aeb 487 else if (i == rx_ring->next_to_clean)
c7689578 488 pr_cont(" NTC\n");
dcd79aeb 489 else
c7689578 490 pr_cont("\n");
dcd79aeb
TI		 491
492 }
493 }
494
495exit:
496 return;
497}
498
5eba3699
AV		 499static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500{
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 507}
508
509static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510{
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 517}
9a799d71 518
e8e26350
PW		 519/*
520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 528 u8 queue, u8 msix_vector)
9a799d71
AK		 529{
530 u32 ivar, index;
e8e26350
PW		 531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
b93a2226 544 case ixgbe_mac_X540:
e8e26350
PW		 545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
9a799d71
AK		 567}
568
fe49f04a 569static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 570 u64 qmask)
fe49f04a
AD		 571{
572 u32 mask;
573
bd508178
AD		 574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
fe49f04a
AD		 576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 578 break;
579 case ixgbe_mac_82599EB:
b93a2226 580 case ixgbe_mac_X540:
fe49f04a
AD		 581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 585 break;
586 default:
587 break;
fe49f04a
AD		 588 }
589}
590
729739b7
AD		 591void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 593{
729739b7
AD		 594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
d3d00239 597 dma_unmap_single(ring->dev,
729739b7
AD		 598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
e5a43549 606 }
729739b7
AD		 607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 611}
612
943561d3 613static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 614{
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 617 int i;
943561d3 618 u32 data;
c84d324c 619
943561d3
AD		 620 if ((hw->fc.current_mode != ixgbe_fc_full) &&
621 (hw->fc.current_mode != ixgbe_fc_rx_pause))
622 return;
c84d324c 623
943561d3
AD		 624 switch (hw->mac.type) {
625 case ixgbe_mac_82598EB:
626 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
627 break;
628 default:
629 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
630 }
631 hwstats->lxoffrxc += data;
c84d324c 632
943561d3
AD		 633 /* refill credits (no tx hang) if we received xoff */
634 if (!data)
c84d324c 635 return;
943561d3
AD		 636
637 for (i = 0; i < adapter->num_tx_queues; i++)
638 clear_bit(__IXGBE_HANG_CHECK_ARMED,
639 &adapter->tx_ring[i]->state);
640}
641
642static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
643{
644 struct ixgbe_hw *hw = &adapter->hw;
645 struct ixgbe_hw_stats *hwstats = &adapter->stats;
646 u32 xoff[8] = {0};
647 int i;
648 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
649
650 if (adapter->ixgbe_ieee_pfc)
651 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
652
653 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
654 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 655 return;
943561d3 656 }
c84d324c
JF		 657
658 /* update stats for each tc, only valid with PFC enabled */
659 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
660 switch (hw->mac.type) {
661 case ixgbe_mac_82598EB:
662 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 663 break;
c84d324c
JF		 664 default:
665 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 666 }
c84d324c
JF		 667 hwstats->pxoffrxc[i] += xoff[i];
668 }
669
670 /* disarm tx queues that have received xoff frames */
671 for (i = 0; i < adapter->num_tx_queues; i++) {
672 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 673 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 674
675 if (xoff[tc])
676 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 677 }
26f23d82
YZ		 678}
679
c84d324c 680static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 681{
7d7ce682 682 return ring->stats.packets;
c84d324c
JF		 683}
684
685static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
686{
687 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 688 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 689
c84d324c
JF		 690 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
691 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
692
693 if (head != tail)
694 return (head < tail) ?
695 tail - head : (tail + ring->count - head);
696
697 return 0;
698}
699
700static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
701{
702 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
703 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
704 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
705 bool ret = false;
706
7d637bcc 707 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 708
709 /*
710 * Check for a hung queue, but be thorough. This verifies
711 * that a transmit has been completed since the previous
712 * check AND there is at least one packet pending. The
713 * ARMED bit is set to indicate a potential hang. The
714 * bit is cleared if a pause frame is received to remove
715 * false hang detection due to PFC or 802.3x frames. By
716 * requiring this to fail twice we avoid races with
717 * pfc clearing the ARMED bit and conditions where we
718 * run the check_tx_hang logic with a transmit completion
719 * pending but without time to complete it yet.
720 */
721 if ((tx_done_old == tx_done) && tx_pending) {
722 /* make sure it is true for two checks in a row */
723 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
724 &tx_ring->state);
725 } else {
726 /* update completed stats and continue */
727 tx_ring->tx_stats.tx_done_old = tx_done;
728 /* reset the countdown */
729 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 730 }
731
c84d324c 732 return ret;
9a799d71
AK		 733}
734
c83c6cbd
AD		 735/**
736 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
737 * @adapter: driver private struct
738 **/
739static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
740{
741
742 /* Do the reset outside of interrupt context */
743 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
744 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
745 ixgbe_service_event_schedule(adapter);
746 }
747}
e01c31a5 748
9a799d71
AK		 749/**
750 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 751 * @q_vector: structure containing interrupt and ring information
e01c31a5 752 * @tx_ring: tx ring to clean
9a799d71 753 **/
fe49f04a 754static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 755 struct ixgbe_ring *tx_ring)
9a799d71 756{
fe49f04a 757 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 758 struct ixgbe_tx_buffer *tx_buffer;
759 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 760 unsigned int total_bytes = 0, total_packets = 0;
59224555 761 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 762 unsigned int i = tx_ring->next_to_clean;
763
764 if (test_bit(__IXGBE_DOWN, &adapter->state))
765 return true;
9a799d71 766
d3d00239 767 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 768 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 769 i -= tx_ring->count;
12207e49 770
729739b7 771 do {
d3d00239
AD		 772 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
773
774 /* if next_to_watch is not set then there is no work pending */
775 if (!eop_desc)
776 break;
777
7f83a9e6
AD		 778 /* prevent any other reads prior to eop_desc */
779 rmb();
780
d3d00239
AD		 781 /* if DD is not set pending work has not been completed */
782 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
783 break;
8ad494b0 784
d3d00239
AD		 785 /* clear next_to_watch to prevent false hangs */
786 tx_buffer->next_to_watch = NULL;
8ad494b0 787
091a6246
AD		 788 /* update the statistics for this packet */
789 total_bytes += tx_buffer->bytecount;
790 total_packets += tx_buffer->gso_segs;
791
3a6a4eda
JK		 792#ifdef CONFIG_IXGBE_PTP
793 if (unlikely(tx_buffer->tx_flags &
794 IXGBE_TX_FLAGS_TSTAMP))
795 ixgbe_ptp_tx_hwtstamp(q_vector,
796 tx_buffer->skb);
797
798#endif
fd0db0ed
AD		 799 /* free the skb */
800 dev_kfree_skb_any(tx_buffer->skb);
801
729739b7
AD		 802 /* unmap skb header data */
803 dma_unmap_single(tx_ring->dev,
804 dma_unmap_addr(tx_buffer, dma),
805 dma_unmap_len(tx_buffer, len),
806 DMA_TO_DEVICE);
807
fd0db0ed
AD		 808 /* clear tx_buffer data */
809 tx_buffer->skb = NULL;
729739b7 810 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 811
729739b7
AD		 812 /* unmap remaining buffers */
813 while (tx_desc != eop_desc) {
d3d00239
AD		 814 tx_buffer++;
815 tx_desc++;
8ad494b0 816 i++;
729739b7
AD		 817 if (unlikely(!i)) {
818 i -= tx_ring->count;
d3d00239 819 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 820 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 821 }
e01c31a5 822
729739b7
AD		 823 /* unmap any remaining paged data */
824 if (dma_unmap_len(tx_buffer, len)) {
825 dma_unmap_page(tx_ring->dev,
826 dma_unmap_addr(tx_buffer, dma),
827 dma_unmap_len(tx_buffer, len),
828 DMA_TO_DEVICE);
829 dma_unmap_len_set(tx_buffer, len, 0);
830 }
831 }
832
833 /* move us one more past the eop_desc for start of next pkt */
834 tx_buffer++;
835 tx_desc++;
836 i++;
837 if (unlikely(!i)) {
838 i -= tx_ring->count;
839 tx_buffer = tx_ring->tx_buffer_info;
840 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
841 }
842
843 /* issue prefetch for next Tx descriptor */
844 prefetch(tx_desc);
12207e49 845
729739b7
AD		 846 /* update budget accounting */
847 budget--;
848 } while (likely(budget));
849
850 i += tx_ring->count;
9a799d71 851 tx_ring->next_to_clean = i;
d3d00239 852 u64_stats_update_begin(&tx_ring->syncp);
b953799e 853 tx_ring->stats.bytes += total_bytes;
bd198058 854 tx_ring->stats.packets += total_packets;
d3d00239 855 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 856 q_vector->tx.total_bytes += total_bytes;
857 q_vector->tx.total_packets += total_packets;
b953799e 858
c84d324c
JF		 859 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
860 /* schedule immediate reset if we believe we hung */
861 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 862 e_err(drv, "Detected Tx Unit Hang\n"
863 " Tx Queue <%d>\n"
864 " TDH, TDT <%x>, <%x>\n"
865 " next_to_use <%x>\n"
866 " next_to_clean <%x>\n"
867 "tx_buffer_info[next_to_clean]\n"
868 " time_stamp <%lx>\n"
869 " jiffies <%lx>\n",
870 tx_ring->queue_index,
871 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
872 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 873 tx_ring->next_to_use, i,
874 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 875
876 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
877
878 e_info(probe,
879 "tx hang %d detected on queue %d, resetting adapter\n",
880 adapter->tx_timeout_count + 1, tx_ring->queue_index);
881
b953799e 882 /* schedule immediate reset if we believe we hung */
c83c6cbd 883 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 884
885 /* the adapter is about to reset, no point in enabling stuff */
59224555 886 return true;
b953799e 887 }
9a799d71 888
b2d96e0a
AD		 889 netdev_tx_completed_queue(txring_txq(tx_ring),
890 total_packets, total_bytes);
891
e092be60 892#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 893 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 894 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 895 /* Make sure that anybody stopping the queue after this
896 * sees the new next_to_clean.
897 */
898 smp_mb();
729739b7
AD		 899 if (__netif_subqueue_stopped(tx_ring->netdev,
900 tx_ring->queue_index)
901 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
902 netif_wake_subqueue(tx_ring->netdev,
903 tx_ring->queue_index);
5b7da515 904 ++tx_ring->tx_stats.restart_queue;
30eba97a 905 }
e092be60 906 }
9a799d71 907
59224555 908 return !!budget;
9a799d71
AK		 909}
910
5dd2d332 911#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 912static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
913 struct ixgbe_ring *tx_ring,
33cf09c9 914 int cpu)
bd0362dd 915{
33cf09c9 916 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 917 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
918 u16 reg_offset;
33cf09c9 919
33cf09c9
AD		 920 switch (hw->mac.type) {
921 case ixgbe_mac_82598EB:
bdda1a61 922 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 923 break;
924 case ixgbe_mac_82599EB:
b93a2226 925 case ixgbe_mac_X540:
bdda1a61
AD		 926 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
927 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 928 break;
929 default:
bdda1a61
AD		 930 /* for unknown hardware do not write register */
931 return;
bd0362dd 932 }
bdda1a61
AD		 933
934 /*
935 * We can enable relaxed ordering for reads, but not writes when
936 * DCA is enabled. This is due to a known issue in some chipsets
937 * which will cause the DCA tag to be cleared.
938 */
939 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
940 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
941 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
942
943 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 944}
945
bdda1a61
AD		 946static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
947 struct ixgbe_ring *rx_ring,
33cf09c9 948 int cpu)
bd0362dd 949{
33cf09c9 950 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 951 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
952 u8 reg_idx = rx_ring->reg_idx;
953
33cf09c9
AD		 954
955 switch (hw->mac.type) {
33cf09c9 956 case ixgbe_mac_82599EB:
b93a2226 957 case ixgbe_mac_X540:
bdda1a61 958 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 959 break;
960 default:
961 break;
962 }
bdda1a61
AD		 963
964 /*
965 * We can enable relaxed ordering for reads, but not writes when
966 * DCA is enabled. This is due to a known issue in some chipsets
967 * which will cause the DCA tag to be cleared.
968 */
969 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
970 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
971 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
972
973 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 974}
975
976static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
977{
978 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 979 struct ixgbe_ring *ring;
bd0362dd 980 int cpu = get_cpu();
bd0362dd 981
33cf09c9
AD		 982 if (q_vector->cpu == cpu)
983 goto out_no_update;
984
a557928e 985 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 986 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 987
a557928e 988 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 989 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 990
991 q_vector->cpu = cpu;
992out_no_update:
bd0362dd
JC		 993 put_cpu();
994}
995
996static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
997{
33cf09c9 998 int num_q_vectors;
bd0362dd
JC		 999 int i;
1000
1001 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1002 return;
1003
e35ec126
AD		 1004 /* always use CB2 mode, difference is masked in the CB driver */
1005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1006
33cf09c9
AD		 1007 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1008 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1009 else
1010 num_q_vectors = 1;
1011
1012 for (i = 0; i < num_q_vectors; i++) {
1013 adapter->q_vector[i]->cpu = -1;
1014 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1015 }
1016}
1017
1018static int __ixgbe_notify_dca(struct device *dev, void *data)
1019{
c60fbb00 1020 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1021 unsigned long event = *(unsigned long *)data;
1022
2a72c31e 1023 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1024 return 0;
1025
bd0362dd
JC		 1026 switch (event) {
1027 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1028 /* if we're already enabled, don't do it again */
1029 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1030 break;
652f093f 1031 if (dca_add_requester(dev) == 0) {
96b0e0f6 1032 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1033 ixgbe_setup_dca(adapter);
1034 break;
1035 }
1036 /* Fall Through since DCA is disabled. */
1037 case DCA_PROVIDER_REMOVE:
1038 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1039 dca_remove_requester(dev);
1040 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1041 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1042 }
1043 break;
1044 }
1045
652f093f 1046 return 0;
bd0362dd 1047}
67a74ee2 1048
bdda1a61 1049#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1050static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1051 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1052 struct sk_buff *skb)
1053{
8a0da21b
AD		 1054 if (ring->netdev->features & NETIF_F_RXHASH)
1055 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1056}
1057
f800326d 1058#ifdef IXGBE_FCOE
ff886dfc
AD		 1059/**
1060 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1061 * @adapter: address of board private structure
1062 * @rx_desc: advanced rx descriptor
1063 *
1064 * Returns : true if it is FCoE pkt
1065 */
1066static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1067 union ixgbe_adv_rx_desc *rx_desc)
1068{
1069 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1070
1071 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1072 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1073 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1074 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1075}
1076
f800326d 1077#endif /* IXGBE_FCOE */
e59bd25d
AV		 1078/**
1079 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1080 * @ring: structure containing ring specific data
1081 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1082 * @skb: skb currently being received and modified
1083 **/
8a0da21b 1084static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1085 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1086 struct sk_buff *skb)
9a799d71 1087{
8a0da21b 1088 skb_checksum_none_assert(skb);
9a799d71 1089
712744be 1090 /* Rx csum disabled */
8a0da21b 1091 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1092 return;
e59bd25d
AV		 1093
1094 /* if IP and error */
f56e0cb1
AD		 1095 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1096 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1097 ring->rx_stats.csum_err++;
9a799d71
AK		 1098 return;
1099 }
e59bd25d 1100
f56e0cb1 1101 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1102 return;
1103
f56e0cb1 1104 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1105 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1106
1107 /*
1108 * 82599 errata, UDP frames with a 0 checksum can be marked as
1109 * checksum errors.
1110 */
8a0da21b
AD		 1111 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1112 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1113 return;
1114
8a0da21b 1115 ring->rx_stats.csum_err++;
e59bd25d
AV		 1116 return;
1117 }
1118
9a799d71 1119 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1120 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1121}
1122
84ea2591 1123static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1124{
f56e0cb1 1125 rx_ring->next_to_use = val;
f800326d
AD		 1126
1127 /* update next to alloc since we have filled the ring */
1128 rx_ring->next_to_alloc = val;
e8e26350
PW		 1129 /*
1130 * Force memory writes to complete before letting h/w
1131 * know there are new descriptors to fetch. (Only
1132 * applicable for weak-ordered memory model archs,
1133 * such as IA-64).
1134 */
1135 wmb();
84ea2591 1136 writel(val, rx_ring->tail);
e8e26350
PW		 1137}
1138
f990b79b
AD		 1139static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1140 struct ixgbe_rx_buffer *bi)
1141{
1142 struct page *page = bi->page;
f800326d 1143 dma_addr_t dma = bi->dma;
f990b79b 1144
f800326d
AD		 1145 /* since we are recycling buffers we should seldom need to alloc */
1146 if (likely(dma))
f990b79b
AD		 1147 return true;
1148
f800326d
AD		 1149 /* alloc new page for storage */
1150 if (likely(!page)) {
8633c084 1151 page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
f800326d 1152 ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1153 if (unlikely(!page)) {
1154 rx_ring->rx_stats.alloc_rx_page_failed++;
1155 return false;
1156 }
f800326d 1157 bi->page = page;
f990b79b
AD		 1158 }
1159
f800326d
AD		 1160 /* map page for use */
1161 dma = dma_map_page(rx_ring->dev, page, 0,
1162 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1163
1164 /*
1165 * if mapping failed free memory back to system since
1166 * there isn't much point in holding memory we can't use
1167 */
1168 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1169 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1170 bi->page = NULL;
f990b79b 1171
f990b79b
AD		 1172 rx_ring->rx_stats.alloc_rx_page_failed++;
1173 return false;
1174 }
1175
f800326d
AD		 1176 bi->dma = dma;
1177 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1178
f990b79b
AD		 1179 return true;
1180}
1181
9a799d71 1182/**
f990b79b 1183 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1184 * @rx_ring: ring to place buffers on
1185 * @cleaned_count: number of buffers to replace
9a799d71 1186 **/
fc77dc3c 1187void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1188{
9a799d71 1189 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1190 struct ixgbe_rx_buffer *bi;
d5f398ed 1191 u16 i = rx_ring->next_to_use;
9a799d71 1192
f800326d
AD		 1193 /* nothing to do */
1194 if (!cleaned_count)
fc77dc3c
AD		 1195 return;
1196
e4f74028 1197 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1198 bi = &rx_ring->rx_buffer_info[i];
1199 i -= rx_ring->count;
9a799d71 1200
f800326d
AD		 1201 do {
1202 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1203 break;
d5f398ed 1204
f800326d
AD		 1205 /*
1206 * Refresh the desc even if buffer_addrs didn't change
1207 * because each write-back erases this info.
1208 */
1209 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1210
f990b79b
AD		 1211 rx_desc++;
1212 bi++;
9a799d71 1213 i++;
f990b79b 1214 if (unlikely(!i)) {
e4f74028 1215 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1216 bi = rx_ring->rx_buffer_info;
1217 i -= rx_ring->count;
1218 }
1219
1220 /* clear the hdr_addr for the next_to_use descriptor */
1221 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1222
1223 cleaned_count--;
1224 } while (cleaned_count);
7c6e0a43 1225
f990b79b
AD		 1226 i += rx_ring->count;
1227
f56e0cb1 1228 if (rx_ring->next_to_use != i)
84ea2591 1229 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1230}
1231
1d2024f6
AD		 1232/**
1233 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1234 * @data: pointer to the start of the headers
1235 * @max_len: total length of section to find headers in
1236 *
1237 * This function is meant to determine the length of headers that will
1238 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1239 * motivation of doing this is to only perform one pull for IPv4 TCP
1240 * packets so that we can do basic things like calculating the gso_size
1241 * based on the average data per packet.
1242 **/
1243static unsigned int ixgbe_get_headlen(unsigned char *data,
1244 unsigned int max_len)
1245{
1246 union {
1247 unsigned char *network;
1248 /* l2 headers */
1249 struct ethhdr *eth;
1250 struct vlan_hdr *vlan;
1251 /* l3 headers */
1252 struct iphdr *ipv4;
1253 } hdr;
1254 __be16 protocol;
1255 u8 nexthdr = 0; /* default to not TCP */
1256 u8 hlen;
1257
1258 /* this should never happen, but better safe than sorry */
1259 if (max_len < ETH_HLEN)
1260 return max_len;
1261
1262 /* initialize network frame pointer */
1263 hdr.network = data;
1264
1265 /* set first protocol and move network header forward */
1266 protocol = hdr.eth->h_proto;
1267 hdr.network += ETH_HLEN;
1268
1269 /* handle any vlan tag if present */
1270 if (protocol == __constant_htons(ETH_P_8021Q)) {
1271 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1272 return max_len;
1273
1274 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1275 hdr.network += VLAN_HLEN;
1276 }
1277
1278 /* handle L3 protocols */
1279 if (protocol == __constant_htons(ETH_P_IP)) {
1280 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1281 return max_len;
1282
1283 /* access ihl as a u8 to avoid unaligned access on ia64 */
1284 hlen = (hdr.network[0] & 0x0F) << 2;
1285
1286 /* verify hlen meets minimum size requirements */
1287 if (hlen < sizeof(struct iphdr))
1288 return hdr.network - data;
1289
1290 /* record next protocol */
1291 nexthdr = hdr.ipv4->protocol;
1292 hdr.network += hlen;
f800326d 1293#ifdef IXGBE_FCOE
1d2024f6
AD		 1294 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1295 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1296 return max_len;
1297 hdr.network += FCOE_HEADER_LEN;
1298#endif
1299 } else {
1300 return hdr.network - data;
1301 }
1302
1303 /* finally sort out TCP */
1304 if (nexthdr == IPPROTO_TCP) {
1305 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1306 return max_len;
1307
1308 /* access doff as a u8 to avoid unaligned access on ia64 */
1309 hlen = (hdr.network[12] & 0xF0) >> 2;
1310
1311 /* verify hlen meets minimum size requirements */
1312 if (hlen < sizeof(struct tcphdr))
1313 return hdr.network - data;
1314
1315 hdr.network += hlen;
1316 }
1317
1318 /*
1319 * If everything has gone correctly hdr.network should be the
1320 * data section of the packet and will be the end of the header.
1321 * If not then it probably represents the end of the last recognized
1322 * header.
1323 */
1324 if ((hdr.network - data) < max_len)
1325 return hdr.network - data;
1326 else
1327 return max_len;
1328}
1329
4c1975d7
AD		 1330static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1331 union ixgbe_adv_rx_desc *rx_desc,
1332 struct sk_buff *skb)
aa80175a 1333{
4c1975d7
AD		 1334 __le32 rsc_enabled;
1335 u32 rsc_cnt;
1336
1337 if (!ring_is_rsc_enabled(rx_ring))
1338 return;
1339
1340 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1341 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1342
1343 /* If this is an RSC frame rsc_cnt should be non-zero */
1344 if (!rsc_enabled)
1345 return;
1346
1347 rsc_cnt = le32_to_cpu(rsc_enabled);
1348 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1349
1350 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1351}
43634e82 1352
1d2024f6
AD		 1353static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1354 struct sk_buff *skb)
1355{
f800326d 1356 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1357
1358 /* set gso_size to avoid messing up TCP MSS */
1359 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1360 IXGBE_CB(skb)->append_cnt);
1361}
1362
1363static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1364 struct sk_buff *skb)
1365{
1366 /* if append_cnt is 0 then frame is not RSC */
1367 if (!IXGBE_CB(skb)->append_cnt)
1368 return;
1369
1370 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1371 rx_ring->rx_stats.rsc_flush++;
1372
1373 ixgbe_set_rsc_gso_size(rx_ring, skb);
1374
1375 /* gso_size is computed using append_cnt so always clear it last */
1376 IXGBE_CB(skb)->append_cnt = 0;
1377}
1378
8a0da21b
AD		 1379/**
1380 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1381 * @rx_ring: rx descriptor ring packet is being transacted on
1382 * @rx_desc: pointer to the EOP Rx descriptor
1383 * @skb: pointer to current skb being populated
f8212f97 1384 *
8a0da21b
AD		 1385 * This function checks the ring, descriptor, and packet information in
1386 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1387 * other fields within the skb.
f8212f97 1388 **/
8a0da21b
AD		 1389static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1390 union ixgbe_adv_rx_desc *rx_desc,
1391 struct sk_buff *skb)
f8212f97 1392{
43e95f11
JF		 1393 struct net_device *dev = rx_ring->netdev;
1394
8a0da21b
AD		 1395 ixgbe_update_rsc_stats(rx_ring, skb);
1396
1397 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1398
8a0da21b
AD		 1399 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1400
3a6a4eda
JK		 1401#ifdef CONFIG_IXGBE_PTP
1402 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS))
1403 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, skb);
1404#endif
1405
43e95f11
JF		 1406 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1407 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1408 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1409 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1410 }
1411
8a0da21b 1412 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1413
43e95f11 1414 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1415}
1416
8a0da21b
AD		 1417static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1418 struct sk_buff *skb)
aa80175a 1419{
8a0da21b
AD		 1420 struct ixgbe_adapter *adapter = q_vector->adapter;
1421
1422 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1423 napi_gro_receive(&q_vector->napi, skb);
1424 else
1425 netif_rx(skb);
aa80175a 1426}
43634e82 1427
f800326d
AD		 1428/**
1429 * ixgbe_is_non_eop - process handling of non-EOP buffers
1430 * @rx_ring: Rx ring being processed
1431 * @rx_desc: Rx descriptor for current buffer
1432 * @skb: Current socket buffer containing buffer in progress
1433 *
1434 * This function updates next to clean. If the buffer is an EOP buffer
1435 * this function exits returning false, otherwise it will place the
1436 * sk_buff in the next buffer to be chained and return true indicating
1437 * that this is in fact a non-EOP buffer.
1438 **/
1439static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1440 union ixgbe_adv_rx_desc *rx_desc,
1441 struct sk_buff *skb)
1442{
1443 u32 ntc = rx_ring->next_to_clean + 1;
1444
1445 /* fetch, update, and store next to clean */
1446 ntc = (ntc < rx_ring->count) ? ntc : 0;
1447 rx_ring->next_to_clean = ntc;
1448
1449 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1450
1451 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1452 return false;
1453
1454 /* append_cnt indicates packet is RSC, if so fetch nextp */
1455 if (IXGBE_CB(skb)->append_cnt) {
1456 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1457 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1458 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1459 }
1460
1461 /* place skb in next buffer to be received */
1462 rx_ring->rx_buffer_info[ntc].skb = skb;
1463 rx_ring->rx_stats.non_eop_descs++;
1464
1465 return true;
1466}
1467
1468/**
1469 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1470 * @rx_ring: rx descriptor ring packet is being transacted on
1471 * @rx_desc: pointer to the EOP Rx descriptor
1472 * @skb: pointer to current skb being fixed
1473 *
1474 * Check for corrupted packet headers caused by senders on the local L2
1475 * embedded NIC switch not setting up their Tx Descriptors right. These
1476 * should be very rare.
1477 *
1478 * Also address the case where we are pulling data in on pages only
1479 * and as such no data is present in the skb header.
1480 *
1481 * In addition if skb is not at least 60 bytes we need to pad it so that
1482 * it is large enough to qualify as a valid Ethernet frame.
1483 *
1484 * Returns true if an error was encountered and skb was freed.
1485 **/
1486static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1487 union ixgbe_adv_rx_desc *rx_desc,
1488 struct sk_buff *skb)
1489{
1490 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1491 struct net_device *netdev = rx_ring->netdev;
1492 unsigned char *va;
1493 unsigned int pull_len;
1494
1495 /* if the page was released unmap it, else just sync our portion */
1496 if (unlikely(IXGBE_CB(skb)->page_released)) {
1497 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1498 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1499 IXGBE_CB(skb)->page_released = false;
1500 } else {
1501 dma_sync_single_range_for_cpu(rx_ring->dev,
1502 IXGBE_CB(skb)->dma,
1503 frag->page_offset,
1504 ixgbe_rx_bufsz(rx_ring),
1505 DMA_FROM_DEVICE);
1506 }
1507 IXGBE_CB(skb)->dma = 0;
1508
1509 /* verify that the packet does not have any known errors */
1510 if (unlikely(ixgbe_test_staterr(rx_desc,
1511 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1512 !(netdev->features & NETIF_F_RXALL))) {
1513 dev_kfree_skb_any(skb);
1514 return true;
1515 }
1516
1517 /*
1518 * it is valid to use page_address instead of kmap since we are
1519 * working with pages allocated out of the lomem pool per
1520 * alloc_page(GFP_ATOMIC)
1521 */
1522 va = skb_frag_address(frag);
1523
1524 /*
1525 * we need the header to contain the greater of either ETH_HLEN or
1526 * 60 bytes if the skb->len is less than 60 for skb_pad.
1527 */
1528 pull_len = skb_frag_size(frag);
1529 if (pull_len > 256)
1530 pull_len = ixgbe_get_headlen(va, pull_len);
1531
1532 /* align pull length to size of long to optimize memcpy performance */
1533 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1534
1535 /* update all of the pointers */
1536 skb_frag_size_sub(frag, pull_len);
1537 frag->page_offset += pull_len;
1538 skb->data_len -= pull_len;
1539 skb->tail += pull_len;
1540
1541 /*
1542 * if we sucked the frag empty then we should free it,
1543 * if there are other frags here something is screwed up in hardware
1544 */
1545 if (skb_frag_size(frag) == 0) {
1546 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1547 skb_shinfo(skb)->nr_frags = 0;
1548 __skb_frag_unref(frag);
1549 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1550 }
1551
1552 /* if skb_pad returns an error the skb was freed */
1553 if (unlikely(skb->len < 60)) {
1554 int pad_len = 60 - skb->len;
1555
1556 if (skb_pad(skb, pad_len))
1557 return true;
1558 __skb_put(skb, pad_len);
1559 }
1560
1561 return false;
1562}
1563
1564/**
1565 * ixgbe_can_reuse_page - determine if we can reuse a page
1566 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1567 *
1568 * Returns true if page can be reused in another Rx buffer
1569 **/
1570static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1571{
1572 struct page *page = rx_buffer->page;
1573
1574 /* if we are only owner of page and it is local we can reuse it */
1575 return likely(page_count(page) == 1) &&
1576 likely(page_to_nid(page) == numa_node_id());
1577}
1578
1579/**
1580 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1581 * @rx_ring: rx descriptor ring to store buffers on
1582 * @old_buff: donor buffer to have page reused
1583 *
1584 * Syncronizes page for reuse by the adapter
1585 **/
1586static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1587 struct ixgbe_rx_buffer *old_buff)
1588{
1589 struct ixgbe_rx_buffer *new_buff;
1590 u16 nta = rx_ring->next_to_alloc;
1591 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1592
1593 new_buff = &rx_ring->rx_buffer_info[nta];
1594
1595 /* update, and store next to alloc */
1596 nta++;
1597 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1598
1599 /* transfer page from old buffer to new buffer */
1600 new_buff->page = old_buff->page;
1601 new_buff->dma = old_buff->dma;
1602
1603 /* flip page offset to other buffer and store to new_buff */
1604 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1605
1606 /* sync the buffer for use by the device */
1607 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1608 new_buff->page_offset, bufsz,
1609 DMA_FROM_DEVICE);
1610
1611 /* bump ref count on page before it is given to the stack */
1612 get_page(new_buff->page);
1613}
1614
1615/**
1616 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1617 * @rx_ring: rx descriptor ring to transact packets on
1618 * @rx_buffer: buffer containing page to add
1619 * @rx_desc: descriptor containing length of buffer written by hardware
1620 * @skb: sk_buff to place the data into
1621 *
1622 * This function is based on skb_add_rx_frag. I would have used that
1623 * function however it doesn't handle the truesize case correctly since we
1624 * are allocating more memory than might be used for a single receive.
1625 **/
1626static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1627 struct ixgbe_rx_buffer *rx_buffer,
1628 struct sk_buff *skb, int size)
1629{
1630 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1631 rx_buffer->page, rx_buffer->page_offset,
1632 size);
1633 skb->len += size;
1634 skb->data_len += size;
1635 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1636}
1637
1638/**
1639 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1640 * @q_vector: structure containing interrupt and ring information
1641 * @rx_ring: rx descriptor ring to transact packets on
1642 * @budget: Total limit on number of packets to process
1643 *
1644 * This function provides a "bounce buffer" approach to Rx interrupt
1645 * processing. The advantage to this is that on systems that have
1646 * expensive overhead for IOMMU access this provides a means of avoiding
1647 * it by maintaining the mapping of the page to the syste.
1648 *
1649 * Returns true if all work is completed without reaching budget
1650 **/
4ff7fb12 1651static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1652 struct ixgbe_ring *rx_ring,
4ff7fb12 1653 int budget)
9a799d71 1654{
d2f4fbe2 1655 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1656#ifdef IXGBE_FCOE
f800326d 1657 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1658 int ddp_bytes = 0;
1659#endif /* IXGBE_FCOE */
f800326d 1660 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1661
f800326d
AD		 1662 do {
1663 struct ixgbe_rx_buffer *rx_buffer;
1664 union ixgbe_adv_rx_desc *rx_desc;
1665 struct sk_buff *skb;
1666 struct page *page;
1667 u16 ntc;
1668
1669 /* return some buffers to hardware, one at a time is too slow */
1670 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1671 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1672 cleaned_count = 0;
1673 }
1674
1675 ntc = rx_ring->next_to_clean;
1676 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1677 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1678
1679 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1680 break;
9a799d71 1681
f800326d
AD		 1682 /*
1683 * This memory barrier is needed to keep us from reading
1684 * any other fields out of the rx_desc until we know the
1685 * RXD_STAT_DD bit is set
1686 */
1687 rmb();
9a799d71 1688
f800326d
AD		 1689 page = rx_buffer->page;
1690 prefetchw(page);
9a799d71 1691
f800326d 1692 skb = rx_buffer->skb;
c267fc16 1693
f800326d
AD		 1694 if (likely(!skb)) {
1695 void *page_addr = page_address(page) +
1696 rx_buffer->page_offset;
9a799d71 1697
f800326d
AD		 1698 /* prefetch first cache line of first page */
1699 prefetch(page_addr);
1700#if L1_CACHE_BYTES < 128
1701 prefetch(page_addr + L1_CACHE_BYTES);
1702#endif
1703
1704 /* allocate a skb to store the frags */
1705 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1706 IXGBE_RX_HDR_SIZE);
1707 if (unlikely(!skb)) {
1708 rx_ring->rx_stats.alloc_rx_buff_failed++;
1709 break;
c267fc16
AD		 1710 }
1711
f800326d
AD		 1712 /*
1713 * we will be copying header into skb->data in
1714 * pskb_may_pull so it is in our interest to prefetch
1715 * it now to avoid a possible cache miss
1716 */
1717 prefetchw(skb->data);
4c1975d7
AD		 1718
1719 /*
1720 * Delay unmapping of the first packet. It carries the
1721 * header information, HW may still access the header
f800326d
AD		 1722 * after the writeback. Only unmap it when EOP is
1723 * reached
4c1975d7 1724 */
f800326d 1725 IXGBE_CB(skb)->dma = rx_buffer->dma;
c267fc16 1726 } else {
f800326d
AD		 1727 /* we are reusing so sync this buffer for CPU use */
1728 dma_sync_single_range_for_cpu(rx_ring->dev,
1729 rx_buffer->dma,
1730 rx_buffer->page_offset,
1731 ixgbe_rx_bufsz(rx_ring),
1732 DMA_FROM_DEVICE);
9a799d71
AK		 1733 }
1734
f800326d
AD		 1735 /* pull page into skb */
1736 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1737 le16_to_cpu(rx_desc->wb.upper.length));
9a799d71 1738
f800326d
AD		 1739 if (ixgbe_can_reuse_page(rx_buffer)) {
1740 /* hand second half of page back to the ring */
1741 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1742 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1743 /* the page has been released from the ring */
1744 IXGBE_CB(skb)->page_released = true;
1745 } else {
1746 /* we are not reusing the buffer so unmap it */
1747 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1748 ixgbe_rx_pg_size(rx_ring),
1749 DMA_FROM_DEVICE);
9a799d71
AK		 1750 }
1751
f800326d
AD		 1752 /* clear contents of buffer_info */
1753 rx_buffer->skb = NULL;
1754 rx_buffer->dma = 0;
1755 rx_buffer->page = NULL;
4c1975d7 1756
f800326d 1757 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
9a799d71 1758
9a799d71 1759 cleaned_count++;
f8212f97 1760
f800326d
AD		 1761 /* place incomplete frames back on ring for completion */
1762 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1763 continue;
c267fc16 1764
f800326d
AD		 1765 /* verify the packet layout is correct */
1766 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1767 continue;
9a799d71 1768
d2f4fbe2
AV		 1769 /* probably a little skewed due to removing CRC */
1770 total_rx_bytes += skb->len;
1771 total_rx_packets++;
1772
8a0da21b
AD		 1773 /* populate checksum, timestamp, VLAN, and protocol */
1774 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1775
332d4a7d
YZ		 1776#ifdef IXGBE_FCOE
1777 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc 1778 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
f56e0cb1 1779 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1780 if (!ddp_bytes) {
1781 dev_kfree_skb_any(skb);
f800326d 1782 continue;
63d635b2 1783 }
3d8fd385 1784 }
f800326d 1785
332d4a7d 1786#endif /* IXGBE_FCOE */
8a0da21b 1787 ixgbe_rx_skb(q_vector, skb);
9a799d71 1788
f800326d 1789 /* update budget accounting */
4ff7fb12 1790 budget--;
f800326d 1791 } while (likely(budget));
9a799d71 1792
3d8fd385
YZ		 1793#ifdef IXGBE_FCOE
1794 /* include DDPed FCoE data */
1795 if (ddp_bytes > 0) {
1796 unsigned int mss;
1797
fc77dc3c 1798 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1799 sizeof(struct fc_frame_header) -
1800 sizeof(struct fcoe_crc_eof);
1801 if (mss > 512)
1802 mss &= ~511;
1803 total_rx_bytes += ddp_bytes;
1804 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1805 }
3d8fd385 1806
f800326d 1807#endif /* IXGBE_FCOE */
c267fc16
AD		 1808 u64_stats_update_begin(&rx_ring->syncp);
1809 rx_ring->stats.packets += total_rx_packets;
1810 rx_ring->stats.bytes += total_rx_bytes;
1811 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1812 q_vector->rx.total_packets += total_rx_packets;
1813 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1814
f800326d
AD		 1815 if (cleaned_count)
1816 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1817
4ff7fb12 1818 return !!budget;
9a799d71
AK		 1819}
1820
9a799d71
AK		 1821/**
1822 * ixgbe_configure_msix - Configure MSI-X hardware
1823 * @adapter: board private structure
1824 *
1825 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1826 * interrupts.
1827 **/
1828static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1829{
021230d4 1830 struct ixgbe_q_vector *q_vector;
efe3d3c8 1831 int q_vectors, v_idx;
021230d4 1832 u32 mask;
9a799d71 1833
021230d4 1834 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1835
8e34d1aa
AD		 1836 /* Populate MSIX to EITR Select */
1837 if (adapter->num_vfs > 32) {
1838 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1839 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1840 }
1841
4df10466
JB		 1842 /*
1843 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1844 * corresponding register.
1845 */
1846 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1847 struct ixgbe_ring *ring;
7a921c93 1848 q_vector = adapter->q_vector[v_idx];
021230d4 1849
a557928e 1850 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1851 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1852
a557928e 1853 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1854 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1855
d5bf4f67
ET		 1856 if (q_vector->tx.ring && !q_vector->rx.ring) {
1857 /* tx only vector */
1858 if (adapter->tx_itr_setting == 1)
1859 q_vector->itr = IXGBE_10K_ITR;
1860 else
1861 q_vector->itr = adapter->tx_itr_setting;
1862 } else {
1863 /* rx or rx/tx vector */
1864 if (adapter->rx_itr_setting == 1)
1865 q_vector->itr = IXGBE_20K_ITR;
1866 else
1867 q_vector->itr = adapter->rx_itr_setting;
1868 }
021230d4 1869
fe49f04a 1870 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1871 }
1872
bd508178
AD		 1873 switch (adapter->hw.mac.type) {
1874 case ixgbe_mac_82598EB:
e8e26350 1875 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1876 v_idx);
bd508178
AD		 1877 break;
1878 case ixgbe_mac_82599EB:
b93a2226 1879 case ixgbe_mac_X540:
e8e26350 1880 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1881 break;
bd508178
AD		 1882 default:
1883 break;
1884 }
021230d4
AV		 1885 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1886
41fb9248 1887 /* set up to autoclear timer, and the vectors */
021230d4 1888 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1889 mask &= ~(IXGBE_EIMS_OTHER |
1890 IXGBE_EIMS_MAILBOX |
1891 IXGBE_EIMS_LSC);
1892
021230d4 1893 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1894}
1895
f494e8fa
AV		 1896enum latency_range {
1897 lowest_latency = 0,
1898 low_latency = 1,
1899 bulk_latency = 2,
1900 latency_invalid = 255
1901};
1902
1903/**
1904 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1905 * @q_vector: structure containing interrupt and ring information
1906 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1907 *
1908 * Stores a new ITR value based on packets and byte
1909 * counts during the last interrupt. The advantage of per interrupt
1910 * computation is faster updates and more accurate ITR for the current
1911 * traffic pattern. Constants in this function were computed
1912 * based on theoretical maximum wire speed and thresholds were set based
1913 * on testing data as well as attempting to minimize response time
1914 * while increasing bulk throughput.
1915 * this functionality is controlled by the InterruptThrottleRate module
1916 * parameter (see ixgbe_param.c)
1917 **/
bd198058
AD		 1918static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1919 struct ixgbe_ring_container *ring_container)
f494e8fa 1920{
bd198058
AD		 1921 int bytes = ring_container->total_bytes;
1922 int packets = ring_container->total_packets;
1923 u32 timepassed_us;
621bd70e 1924 u64 bytes_perint;
bd198058 1925 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1926
1927 if (packets == 0)
bd198058 1928 return;
f494e8fa
AV		 1929
1930 /* simple throttlerate management
621bd70e
AD		 1931 * 0-10MB/s lowest (100000 ints/s)
1932 * 10-20MB/s low (20000 ints/s)
1933 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1934 */
1935 /* what was last interrupt timeslice? */
d5bf4f67 1936 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1937 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1938
1939 switch (itr_setting) {
1940 case lowest_latency:
621bd70e 1941 if (bytes_perint > 10)
bd198058 1942 itr_setting = low_latency;
f494e8fa
AV		 1943 break;
1944 case low_latency:
621bd70e 1945 if (bytes_perint > 20)
bd198058 1946 itr_setting = bulk_latency;
621bd70e 1947 else if (bytes_perint <= 10)
bd198058 1948 itr_setting = lowest_latency;
f494e8fa
AV		 1949 break;
1950 case bulk_latency:
621bd70e 1951 if (bytes_perint <= 20)
bd198058 1952 itr_setting = low_latency;
f494e8fa
AV		 1953 break;
1954 }
1955
bd198058
AD		 1956 /* clear work counters since we have the values we need */
1957 ring_container->total_bytes = 0;
1958 ring_container->total_packets = 0;
1959
1960 /* write updated itr to ring container */
1961 ring_container->itr = itr_setting;
f494e8fa
AV		 1962}
1963
509ee935
JB		 1964/**
1965 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1966 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1967 *
1968 * This function is made to be called by ethtool and by the driver
1969 * when it needs to update EITR registers at runtime. Hardware
1970 * specific quirks/differences are taken care of here.
1971 */
fe49f04a 1972void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1973{
fe49f04a 1974 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1975 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1976 int v_idx = q_vector->v_idx;
5d967eb7 1977 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 1978
bd508178
AD		 1979 switch (adapter->hw.mac.type) {
1980 case ixgbe_mac_82598EB:
509ee935
JB		 1981 /* must write high and low 16 bits to reset counter */
1982 itr_reg |= (itr_reg << 16);
bd508178
AD		 1983 break;
1984 case ixgbe_mac_82599EB:
b93a2226 1985 case ixgbe_mac_X540:
509ee935
JB		 1986 /*
1987 * set the WDIS bit to not clear the timer bits and cause an
1988 * immediate assertion of the interrupt
1989 */
1990 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1991 break;
1992 default:
1993 break;
509ee935
JB		 1994 }
1995 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1996}
1997
bd198058 1998static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1999{
d5bf4f67 2000 u32 new_itr = q_vector->itr;
bd198058 2001 u8 current_itr;
f494e8fa 2002
bd198058
AD		 2003 ixgbe_update_itr(q_vector, &q_vector->tx);
2004 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2005
08c8833b 2006 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2007
2008 switch (current_itr) {
2009 /* counts and packets in update_itr are dependent on these numbers */
2010 case lowest_latency:
d5bf4f67 2011 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2012 break;
2013 case low_latency:
d5bf4f67 2014 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2015 break;
2016 case bulk_latency:
d5bf4f67 2017 new_itr = IXGBE_8K_ITR;
f494e8fa 2018 break;
bd198058
AD		 2019 default:
2020 break;
f494e8fa
AV		 2021 }
2022
d5bf4f67 2023 if (new_itr != q_vector->itr) {
fe49f04a 2024 /* do an exponential smoothing */
d5bf4f67
ET		 2025 new_itr = (10 * new_itr * q_vector->itr) /
2026 ((9 * new_itr) + q_vector->itr);
509ee935 2027
bd198058 2028 /* save the algorithm value here */
5d967eb7 2029 q_vector->itr = new_itr;
fe49f04a
AD		 2030
2031 ixgbe_write_eitr(q_vector);
f494e8fa 2032 }
f494e8fa
AV		 2033}
2034
119fc60a 2035/**
de88eeeb 2036 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2037 * @adapter: pointer to adapter
119fc60a 2038 **/
f0f9778d 2039static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2040{
119fc60a
MC		 2041 struct ixgbe_hw *hw = &adapter->hw;
2042 u32 eicr = adapter->interrupt_event;
2043
f0f9778d 2044 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2045 return;
2046
f0f9778d
AD		 2047 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2048 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2049 return;
2050
2051 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2052
7ca647bd 2053 switch (hw->device_id) {
f0f9778d
AD		 2054 case IXGBE_DEV_ID_82599_T3_LOM:
2055 /*
2056 * Since the warning interrupt is for both ports
2057 * we don't have to check if:
2058 * - This interrupt wasn't for our port.
2059 * - We may have missed the interrupt so always have to
2060 * check if we got a LSC
2061 */
2062 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2063 !(eicr & IXGBE_EICR_LSC))
2064 return;
2065
2066 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2067 u32 autoneg;
2068 bool link_up = false;
7ca647bd 2069
7ca647bd
JP		 2070 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2071
f0f9778d
AD		 2072 if (link_up)
2073 return;
2074 }
2075
2076 /* Check if this is not due to overtemp */
2077 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2078 return;
2079
2080 break;
7ca647bd
JP		 2081 default:
2082 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2083 return;
7ca647bd 2084 break;
119fc60a 2085 }
7ca647bd
JP		 2086 e_crit(drv,
2087 "Network adapter has been stopped because it has over heated. "
2088 "Restart the computer. If the problem persists, "
2089 "power off the system and replace the adapter\n");
f0f9778d
AD		 2090
2091 adapter->interrupt_event = 0;
119fc60a
MC		 2092}
2093
0befdb3e
JB		 2094static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2095{
2096 struct ixgbe_hw *hw = &adapter->hw;
2097
2098 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2099 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2100 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2101 /* write to clear the interrupt */
2102 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2103 }
2104}
cf8280ee 2105
4f51bf70
JK		 2106static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2107{
2108 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2109 return;
2110
2111 switch (adapter->hw.mac.type) {
2112 case ixgbe_mac_82599EB:
2113 /*
2114 * Need to check link state so complete overtemp check
2115 * on service task
2116 */
2117 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2118 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2119 adapter->interrupt_event = eicr;
2120 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2121 ixgbe_service_event_schedule(adapter);
2122 return;
2123 }
2124 return;
2125 case ixgbe_mac_X540:
2126 if (!(eicr & IXGBE_EICR_TS))
2127 return;
2128 break;
2129 default:
2130 return;
2131 }
2132
2133 e_crit(drv,
2134 "Network adapter has been stopped because it has over heated. "
2135 "Restart the computer. If the problem persists, "
2136 "power off the system and replace the adapter\n");
2137}
2138
e8e26350
PW		 2139static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2140{
2141 struct ixgbe_hw *hw = &adapter->hw;
2142
73c4b7cd
AD		 2143 if (eicr & IXGBE_EICR_GPI_SDP2) {
2144 /* Clear the interrupt */
2145 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2146 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2147 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2148 ixgbe_service_event_schedule(adapter);
2149 }
73c4b7cd
AD		 2150 }
2151
e8e26350
PW		 2152 if (eicr & IXGBE_EICR_GPI_SDP1) {
2153 /* Clear the interrupt */
2154 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2155 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2156 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2157 ixgbe_service_event_schedule(adapter);
2158 }
e8e26350
PW		 2159 }
2160}
2161
cf8280ee
JB		 2162static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2163{
2164 struct ixgbe_hw *hw = &adapter->hw;
2165
2166 adapter->lsc_int++;
2167 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2168 adapter->link_check_timeout = jiffies;
2169 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2170 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2171 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2172 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2173 }
2174}
2175
fe49f04a
AD		 2176static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2177 u64 qmask)
2178{
2179 u32 mask;
bd508178 2180 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2181
bd508178
AD		 2182 switch (hw->mac.type) {
2183 case ixgbe_mac_82598EB:
fe49f04a 2184 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2185 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2186 break;
2187 case ixgbe_mac_82599EB:
b93a2226 2188 case ixgbe_mac_X540:
fe49f04a 2189 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2190 if (mask)
2191 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2192 mask = (qmask >> 32);
bd508178
AD		 2193 if (mask)
2194 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2195 break;
2196 default:
2197 break;
fe49f04a
AD		 2198 }
2199 /* skip the flush */
2200}
2201
2202static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2203 u64 qmask)
fe49f04a
AD		 2204{
2205 u32 mask;
bd508178 2206 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2207
bd508178
AD		 2208 switch (hw->mac.type) {
2209 case ixgbe_mac_82598EB:
fe49f04a 2210 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2211 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2212 break;
2213 case ixgbe_mac_82599EB:
b93a2226 2214 case ixgbe_mac_X540:
fe49f04a 2215 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2216 if (mask)
2217 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2218 mask = (qmask >> 32);
bd508178
AD		 2219 if (mask)
2220 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2221 break;
2222 default:
2223 break;
fe49f04a
AD		 2224 }
2225 /* skip the flush */
2226}
2227
021230d4 2228/**
2c4af694
AD		 2229 * ixgbe_irq_enable - Enable default interrupt generation settings
2230 * @adapter: board private structure
021230d4 2231 **/
2c4af694
AD		 2232static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2233 bool flush)
9a799d71 2234{
2c4af694 2235 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2236
2c4af694
AD		 2237 /* don't reenable LSC while waiting for link */
2238 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2239 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2240
2c4af694 2241 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2242 switch (adapter->hw.mac.type) {
2243 case ixgbe_mac_82599EB:
2244 mask |= IXGBE_EIMS_GPI_SDP0;
2245 break;
2246 case ixgbe_mac_X540:
2247 mask |= IXGBE_EIMS_TS;
2248 break;
2249 default:
2250 break;
2251 }
2c4af694
AD		 2252 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2253 mask |= IXGBE_EIMS_GPI_SDP1;
2254 switch (adapter->hw.mac.type) {
2255 case ixgbe_mac_82599EB:
2c4af694
AD		 2256 mask |= IXGBE_EIMS_GPI_SDP1;
2257 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2258 case ixgbe_mac_X540:
2259 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2260 mask |= IXGBE_EIMS_MAILBOX;
2261 break;
2262 default:
2263 break;
9a799d71 2264 }
2c4af694
AD		 2265 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2266 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2267 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2268
2c4af694
AD		 2269 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2270 if (queues)
2271 ixgbe_irq_enable_queues(adapter, ~0);
2272 if (flush)
2273 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2274}
2275
2c4af694 2276static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2277{
a65151ba 2278 struct ixgbe_adapter *adapter = data;
9a799d71 2279 struct ixgbe_hw *hw = &adapter->hw;
54037505 2280 u32 eicr;
91281fd3 2281
54037505
DS		 2282 /*
2283 * Workaround for Silicon errata. Use clear-by-write instead
2284 * of clear-by-read. Reading with EICS will return the
2285 * interrupt causes without clearing, which later be done
2286 * with the write to EICR.
2287 */
2288 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2289 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2290
cf8280ee
JB		 2291 if (eicr & IXGBE_EICR_LSC)
2292 ixgbe_check_lsc(adapter);
f0848276 2293
1cdd1ec8
GR		 2294 if (eicr & IXGBE_EICR_MAILBOX)
2295 ixgbe_msg_task(adapter);
efe3d3c8 2296
bd508178
AD		 2297 switch (hw->mac.type) {
2298 case ixgbe_mac_82599EB:
b93a2226 2299 case ixgbe_mac_X540:
2c4af694
AD		 2300 if (eicr & IXGBE_EICR_ECC)
2301 e_info(link, "Received unrecoverable ECC Err, please "
2302 "reboot\n");
c4cf55e5
PWJ		 2303 /* Handle Flow Director Full threshold interrupt */
2304 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2305 int reinit_count = 0;
c4cf55e5 2306 int i;
c4cf55e5 2307 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2308 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2309 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2310 &ring->state))
2311 reinit_count++;
2312 }
2313 if (reinit_count) {
2314 /* no more flow director interrupts until after init */
2315 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2316 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2317 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2318 }
2319 }
f0f9778d 2320 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2321 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2322 break;
2323 default:
2324 break;
c4cf55e5 2325 }
f0848276 2326
bd508178 2327 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2328#ifdef CONFIG_IXGBE_PTP
2329 ixgbe_ptp_check_pps_event(adapter, eicr);
2330#endif
efe3d3c8 2331
7086400d 2332 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2333 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2334 ixgbe_irq_enable(adapter, false, false);
f0848276 2335
9a799d71 2336 return IRQ_HANDLED;
f0848276 2337}
91281fd3 2338
4ff7fb12 2339static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2340{
021230d4 2341 struct ixgbe_q_vector *q_vector = data;
91281fd3 2342
9b471446 2343 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2344
4ff7fb12
AD		 2345 if (q_vector->rx.ring || q_vector->tx.ring)
2346 napi_schedule(&q_vector->napi);
91281fd3 2347
9a799d71 2348 return IRQ_HANDLED;
91281fd3
AD		 2349}
2350
eb01b975
AD		 2351/**
2352 * ixgbe_poll - NAPI Rx polling callback
2353 * @napi: structure for representing this polling device
2354 * @budget: how many packets driver is allowed to clean
2355 *
2356 * This function is used for legacy and MSI, NAPI mode
2357 **/
8af3c33f 2358int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2359{
2360 struct ixgbe_q_vector *q_vector =
2361 container_of(napi, struct ixgbe_q_vector, napi);
2362 struct ixgbe_adapter *adapter = q_vector->adapter;
2363 struct ixgbe_ring *ring;
2364 int per_ring_budget;
2365 bool clean_complete = true;
2366
2367#ifdef CONFIG_IXGBE_DCA
2368 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2369 ixgbe_update_dca(q_vector);
2370#endif
2371
2372 ixgbe_for_each_ring(ring, q_vector->tx)
2373 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2374
2375 /* attempt to distribute budget to each queue fairly, but don't allow
2376 * the budget to go below 1 because we'll exit polling */
2377 if (q_vector->rx.count > 1)
2378 per_ring_budget = max(budget/q_vector->rx.count, 1);
2379 else
2380 per_ring_budget = budget;
2381
2382 ixgbe_for_each_ring(ring, q_vector->rx)
2383 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2384 per_ring_budget);
2385
2386 /* If all work not completed, return budget and keep polling */
2387 if (!clean_complete)
2388 return budget;
2389
2390 /* all work done, exit the polling mode */
2391 napi_complete(napi);
2392 if (adapter->rx_itr_setting & 1)
2393 ixgbe_set_itr(q_vector);
2394 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2395 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2396
2397 return 0;
2398}
2399
021230d4
AV		 2400/**
2401 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2402 * @adapter: board private structure
2403 *
2404 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2405 * interrupts from the kernel.
2406 **/
2407static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2408{
2409 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2410 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2411 int vector, err;
e8e9f696 2412 int ri = 0, ti = 0;
021230d4 2413
021230d4 2414 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2415 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2416 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2417
4ff7fb12 2418 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2419 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2420 "%s-%s-%d", netdev->name, "TxRx", ri++);
2421 ti++;
2422 } else if (q_vector->rx.ring) {
9fe93afd 2423 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2424 "%s-%s-%d", netdev->name, "rx", ri++);
2425 } else if (q_vector->tx.ring) {
9fe93afd 2426 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2427 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2428 } else {
2429 /* skip this unused q_vector */
2430 continue;
32aa77a4 2431 }
207867f5
AD		 2432 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2433 q_vector->name, q_vector);
9a799d71 2434 if (err) {
396e799c 2435 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2436 "Error: %d\n", err);
021230d4 2437 goto free_queue_irqs;
9a799d71 2438 }
207867f5
AD		 2439 /* If Flow Director is enabled, set interrupt affinity */
2440 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2441 /* assign the mask for this irq */
2442 irq_set_affinity_hint(entry->vector,
de88eeeb 2443 &q_vector->affinity_mask);
207867f5 2444 }
9a799d71
AK		 2445 }
2446
021230d4 2447 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2448 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2449 if (err) {
de88eeeb 2450 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2451 goto free_queue_irqs;
9a799d71
AK		 2452 }
2453
9a799d71
AK		 2454 return 0;
2455
021230d4 2456free_queue_irqs:
207867f5
AD		 2457 while (vector) {
2458 vector--;
2459 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2460 NULL);
2461 free_irq(adapter->msix_entries[vector].vector,
2462 adapter->q_vector[vector]);
2463 }
021230d4
AV		 2464 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2465 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2466 kfree(adapter->msix_entries);
2467 adapter->msix_entries = NULL;
9a799d71
AK		 2468 return err;
2469}
2470
2471/**
021230d4 2472 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2473 * @irq: interrupt number
2474 * @data: pointer to a network interface device structure
9a799d71
AK		 2475 **/
2476static irqreturn_t ixgbe_intr(int irq, void *data)
2477{
a65151ba 2478 struct ixgbe_adapter *adapter = data;
9a799d71 2479 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2480 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2481 u32 eicr;
2482
54037505 2483 /*
24ddd967 2484 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2485 * before the read of EICR.
2486 */
2487 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2488
021230d4 2489 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2490 * therefore no explicit interrupt disable is necessary */
021230d4 2491 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2492 if (!eicr) {
6af3b9eb
ET		 2493 /*
2494 * shared interrupt alert!
f47cf66e 2495 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2496 * have disabled interrupts due to EIAM
2497 * finish the workaround of silicon errata on 82598. Unmask
2498 * the interrupt that we masked before the EICR read.
2499 */
2500 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2501 ixgbe_irq_enable(adapter, true, true);
9a799d71 2502 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2503 }
9a799d71 2504
cf8280ee
JB		 2505 if (eicr & IXGBE_EICR_LSC)
2506 ixgbe_check_lsc(adapter);
021230d4 2507
bd508178
AD		 2508 switch (hw->mac.type) {
2509 case ixgbe_mac_82599EB:
e8e26350 2510 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2511 /* Fall through */
2512 case ixgbe_mac_X540:
2513 if (eicr & IXGBE_EICR_ECC)
2514 e_info(link, "Received unrecoverable ECC err, please "
2515 "reboot\n");
4f51bf70 2516 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2517 break;
2518 default:
2519 break;
2520 }
e8e26350 2521
0befdb3e 2522 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2523#ifdef CONFIG_IXGBE_PTP
2524 ixgbe_ptp_check_pps_event(adapter, eicr);
2525#endif
0befdb3e 2526
b9f6ed2b
AD		 2527 /* would disable interrupts here but EIAM disabled it */
2528 napi_schedule(&q_vector->napi);
9a799d71 2529
6af3b9eb
ET		 2530 /*
2531 * re-enable link(maybe) and non-queue interrupts, no flush.
2532 * ixgbe_poll will re-enable the queue interrupts
2533 */
6af3b9eb
ET		 2534 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2535 ixgbe_irq_enable(adapter, false, false);
2536
9a799d71
AK		 2537 return IRQ_HANDLED;
2538}
2539
2540/**
2541 * ixgbe_request_irq - initialize interrupts
2542 * @adapter: board private structure
2543 *
2544 * Attempts to configure interrupts using the best available
2545 * capabilities of the hardware and kernel.
2546 **/
021230d4 2547static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2548{
2549 struct net_device *netdev = adapter->netdev;
021230d4 2550 int err;
9a799d71 2551
4cc6df29 2552 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2553 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2554 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2555 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2556 netdev->name, adapter);
4cc6df29 2557 else
a0607fd3 2558 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2559 netdev->name, adapter);
9a799d71 2560
de88eeeb 2561 if (err)
396e799c 2562 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2563
9a799d71
AK		 2564 return err;
2565}
2566
2567static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2568{
9a799d71 2569 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2570 int i, q_vectors;
9a799d71 2571
021230d4 2572 q_vectors = adapter->num_msix_vectors;
021230d4 2573 i = q_vectors - 1;
a65151ba 2574 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2575 i--;
4cc6df29 2576
021230d4 2577 for (; i >= 0; i--) {
894ff7cf 2578 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2579 if (!adapter->q_vector[i]->rx.ring &&
2580 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2581 continue;
2582
207867f5
AD		 2583 /* clear the affinity_mask in the IRQ descriptor */
2584 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2585 NULL);
2586
021230d4 2587 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2588 adapter->q_vector[i]);
021230d4 2589 }
021230d4 2590 } else {
a65151ba 2591 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2592 }
2593}
2594
22d5a71b
JB		 2595/**
2596 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2597 * @adapter: board private structure
2598 **/
2599static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2600{
bd508178
AD		 2601 switch (adapter->hw.mac.type) {
2602 case ixgbe_mac_82598EB:
835462fc 2603 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2604 break;
2605 case ixgbe_mac_82599EB:
b93a2226 2606 case ixgbe_mac_X540:
835462fc
NS		 2607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2608 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2609 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2610 break;
2611 default:
2612 break;
22d5a71b
JB		 2613 }
2614 IXGBE_WRITE_FLUSH(&adapter->hw);
2615 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2616 int i;
2617 for (i = 0; i < adapter->num_msix_vectors; i++)
2618 synchronize_irq(adapter->msix_entries[i].vector);
2619 } else {
2620 synchronize_irq(adapter->pdev->irq);
2621 }
2622}
2623
9a799d71
AK		 2624/**
2625 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2626 *
2627 **/
2628static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2629{
d5bf4f67 2630 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2631
d5bf4f67
ET		 2632 /* rx/tx vector */
2633 if (adapter->rx_itr_setting == 1)
2634 q_vector->itr = IXGBE_20K_ITR;
2635 else
2636 q_vector->itr = adapter->rx_itr_setting;
2637
2638 ixgbe_write_eitr(q_vector);
9a799d71 2639
e8e26350
PW		 2640 ixgbe_set_ivar(adapter, 0, 0, 0);
2641 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2642
396e799c 2643 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2644}
2645
43e69bf0
AD		 2646/**
2647 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2648 * @adapter: board private structure
2649 * @ring: structure containing ring specific data
2650 *
2651 * Configure the Tx descriptor ring after a reset.
2652 **/
84418e3b
AD		 2653void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2654 struct ixgbe_ring *ring)
43e69bf0
AD		 2655{
2656 struct ixgbe_hw *hw = &adapter->hw;
2657 u64 tdba = ring->dma;
2f1860b8 2658 int wait_loop = 10;
b88c6de2 2659 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2660 u8 reg_idx = ring->reg_idx;
43e69bf0 2661
2f1860b8 2662 /* disable queue to avoid issues while updating state */
b88c6de2 2663 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2664 IXGBE_WRITE_FLUSH(hw);
2665
43e69bf0 2666 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2667 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2668 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2669 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2670 ring->count * sizeof(union ixgbe_adv_tx_desc));
2671 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2672 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2673 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2674
b88c6de2
AD		 2675 /*
2676 * set WTHRESH to encourage burst writeback, it should not be set
2677 * higher than 1 when ITR is 0 as it could cause false TX hangs
2678 *
2679 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2680 * to or less than the number of on chip descriptors, which is
2681 * currently 40.
2682 */
e954b374 2683 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2684 txdctl |= (1 << 16); /* WTHRESH = 1 */
2685 else
2686 txdctl |= (8 << 16); /* WTHRESH = 8 */
2687
e954b374
AD		 2688 /*
2689 * Setting PTHRESH to 32 both improves performance
2690 * and avoids a TX hang with DFP enabled
2691 */
b88c6de2
AD		 2692 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2693 32; /* PTHRESH = 32 */
2f1860b8
AD		 2694
2695 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2696 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2697 adapter->atr_sample_rate) {
2698 ring->atr_sample_rate = adapter->atr_sample_rate;
2699 ring->atr_count = 0;
2700 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2701 } else {
2702 ring->atr_sample_rate = 0;
2703 }
2f1860b8 2704
c84d324c
JF		 2705 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2706
2f1860b8 2707 /* enable queue */
2f1860b8
AD		 2708 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2709
2710 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2711 if (hw->mac.type == ixgbe_mac_82598EB &&
2712 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2713 return;
2714
2715 /* poll to verify queue is enabled */
2716 do {
032b4325 2717 usleep_range(1000, 2000);
2f1860b8
AD		 2718 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2719 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2720 if (!wait_loop)
2721 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2722}
2723
120ff942
AD		 2724static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2725{
2726 struct ixgbe_hw *hw = &adapter->hw;
2727 u32 rttdcs;
72a32f1f 2728 u32 reg;
8b1c0b24 2729 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2730
2731 if (hw->mac.type == ixgbe_mac_82598EB)
2732 return;
2733
2734 /* disable the arbiter while setting MTQC */
2735 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2736 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2737 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2738
2739 /* set transmit pool layout */
8b1c0b24 2740 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2741 case (IXGBE_FLAG_SRIOV_ENABLED):
2742 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2743 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2744 break;
8b1c0b24
JF		 2745 default:
2746 if (!tcs)
2747 reg = IXGBE_MTQC_64Q_1PB;
2748 else if (tcs <= 4)
2749 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2750 else
2751 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2752
8b1c0b24 2753 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2754
8b1c0b24
JF		 2755 /* Enable Security TX Buffer IFG for multiple pb */
2756 if (tcs) {
2757 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2758 reg |= IXGBE_SECTX_DCB;
2759 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2760 }
120ff942
AD		 2761 break;
2762 }
2763
2764 /* re-enable the arbiter */
2765 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2766 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2767}
2768
9a799d71 2769/**
3a581073 2770 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2771 * @adapter: board private structure
2772 *
2773 * Configure the Tx unit of the MAC after a reset.
2774 **/
2775static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2776{
2f1860b8
AD		 2777 struct ixgbe_hw *hw = &adapter->hw;
2778 u32 dmatxctl;
43e69bf0 2779 u32 i;
9a799d71 2780
2f1860b8
AD		 2781 ixgbe_setup_mtqc(adapter);
2782
2783 if (hw->mac.type != ixgbe_mac_82598EB) {
2784 /* DMATXCTL.EN must be before Tx queues are enabled */
2785 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2786 dmatxctl |= IXGBE_DMATXCTL_TE;
2787 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2788 }
2789
9a799d71 2790 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2791 for (i = 0; i < adapter->num_tx_queues; i++)
2792 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2793}
2794
3ebe8fde
AD		 2795static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2796 struct ixgbe_ring *ring)
2797{
2798 struct ixgbe_hw *hw = &adapter->hw;
2799 u8 reg_idx = ring->reg_idx;
2800 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2801
2802 srrctl |= IXGBE_SRRCTL_DROP_EN;
2803
2804 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2805}
2806
2807static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2808 struct ixgbe_ring *ring)
2809{
2810 struct ixgbe_hw *hw = &adapter->hw;
2811 u8 reg_idx = ring->reg_idx;
2812 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2813
2814 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2815
2816 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2817}
2818
2819#ifdef CONFIG_IXGBE_DCB
2820void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2821#else
2822static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2823#endif
2824{
2825 int i;
2826 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2827
2828 if (adapter->ixgbe_ieee_pfc)
2829 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2830
2831 /*
2832 * We should set the drop enable bit if:
2833 * SR-IOV is enabled
2834 * or
2835 * Number of Rx queues > 1 and flow control is disabled
2836 *
2837 * This allows us to avoid head of line blocking for security
2838 * and performance reasons.
2839 */
2840 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2841 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2842 for (i = 0; i < adapter->num_rx_queues; i++)
2843 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2844 } else {
2845 for (i = 0; i < adapter->num_rx_queues; i++)
2846 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2847 }
2848}
2849
e8e26350 2850#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2851
a6616b42 2852static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2853 struct ixgbe_ring *rx_ring)
cc41ac7c 2854{
cc41ac7c 2855 u32 srrctl;
bf29ee6c 2856 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2857
bd508178
AD		 2858 switch (adapter->hw.mac.type) {
2859 case ixgbe_mac_82598EB: {
2860 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2861 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2862 reg_idx = reg_idx & mask;
cc41ac7c 2863 }
bd508178
AD		 2864 break;
2865 case ixgbe_mac_82599EB:
b93a2226 2866 case ixgbe_mac_X540:
bd508178
AD		 2867 default:
2868 break;
2869 }
2870
bf29ee6c 2871 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2872
2873 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2874 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2875 if (adapter->num_vfs)
2876 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2877
afafd5b0
AD		 2878 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2879 IXGBE_SRRCTL_BSIZEHDR_MASK;
2880
f800326d
AD		 2881#if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2882 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2883#else
f800326d 2884 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2885#endif
f800326d 2886 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2887
bf29ee6c 2888 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2889}
9a799d71 2890
05abb126 2891static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2892{
05abb126
AD		 2893 struct ixgbe_hw *hw = &adapter->hw;
2894 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2895 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2896 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2897 u32 mrqc = 0, reta = 0;
2898 u32 rxcsum;
2899 int i, j;
8b1c0b24 2900 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2901 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2902
2903 if (tcs)
2904 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2905
05abb126
AD		 2906 /* Fill out hash function seeds */
2907 for (i = 0; i < 10; i++)
2908 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2909
2910 /* Fill out redirection table */
2911 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2912 if (j == maxq)
05abb126
AD		 2913 j = 0;
2914 /* reta = 4-byte sliding window of
2915 * 0x00..(indices-1)(indices-1)00..etc. */
2916 reta = (reta << 8) | (j * 0x11);
2917 if ((i & 3) == 3)
2918 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2919 }
0cefafad 2920
05abb126
AD		 2921 /* Disable indicating checksum in descriptor, enables RSS hash */
2922 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2923 rxcsum |= IXGBE_RXCSUM_PCSD;
2924 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2925
8b1c0b24
JF		 2926 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2927 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2928 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2929 } else {
2930 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2931 | IXGBE_FLAG_SRIOV_ENABLED);
2932
2933 switch (mask) {
2934 case (IXGBE_FLAG_RSS_ENABLED):
2935 if (!tcs)
2936 mrqc = IXGBE_MRQC_RSSEN;
2937 else if (tcs <= 4)
2938 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2939 else
2940 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2941 break;
2942 case (IXGBE_FLAG_SRIOV_ENABLED):
2943 mrqc = IXGBE_MRQC_VMDQEN;
2944 break;
2945 default:
2946 break;
2947 }
0cefafad
JB		 2948 }
2949
05abb126
AD		 2950 /* Perform hash on these packet types */
2951 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2952 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2953 | IXGBE_MRQC_RSS_FIELD_IPV6
2954 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2955
ef6afc0c
AD		 2956 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2957 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2958 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2959 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2960
05abb126 2961 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2962}
2963
bb5a9ad2
NS		 2964/**
2965 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2966 * @adapter: address of board private structure
2967 * @index: index of ring to set
bb5a9ad2 2968 **/
082757af 2969static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2970 struct ixgbe_ring *ring)
bb5a9ad2 2971{
bb5a9ad2 2972 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2973 u32 rscctrl;
bf29ee6c 2974 u8 reg_idx = ring->reg_idx;
7367096a 2975
7d637bcc 2976 if (!ring_is_rsc_enabled(ring))
7367096a 2977 return;
bb5a9ad2 2978
7367096a 2979 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2980 rscctrl |= IXGBE_RSCCTL_RSCEN;
2981 /*
2982 * we must limit the number of descriptors so that the
2983 * total size of max desc * buf_len is not greater
642c680e 2984 * than 65536
bb5a9ad2 2985 */
f800326d
AD		 2986#if (PAGE_SIZE <= 8192)
2987 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2988#elif (PAGE_SIZE <= 16384)
2989 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
bb5a9ad2 2990#else
f800326d 2991 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
bb5a9ad2 2992#endif
7367096a 2993 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2994}
2995
9e10e045
AD		 2996#define IXGBE_MAX_RX_DESC_POLL 10
2997static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2998 struct ixgbe_ring *ring)
2999{
3000 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3001 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3002 u32 rxdctl;
bf29ee6c 3003 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3004
3005 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3006 if (hw->mac.type == ixgbe_mac_82598EB &&
3007 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3008 return;
3009
3010 do {
032b4325 3011 usleep_range(1000, 2000);
9e10e045
AD		 3012 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3013 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3014
3015 if (!wait_loop) {
3016 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3017 "the polling period\n", reg_idx);
3018 }
3019}
3020
2d39d576
YZ		 3021void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3022 struct ixgbe_ring *ring)
3023{
3024 struct ixgbe_hw *hw = &adapter->hw;
3025 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3026 u32 rxdctl;
3027 u8 reg_idx = ring->reg_idx;
3028
3029 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3030 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3031
3032 /* write value back with RXDCTL.ENABLE bit cleared */
3033 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3034
3035 if (hw->mac.type == ixgbe_mac_82598EB &&
3036 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3037 return;
3038
3039 /* the hardware may take up to 100us to really disable the rx queue */
3040 do {
3041 udelay(10);
3042 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3043 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3044
3045 if (!wait_loop) {
3046 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3047 "the polling period\n", reg_idx);
3048 }
3049}
3050
84418e3b
AD		 3051void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3052 struct ixgbe_ring *ring)
acd37177
AD		 3053{
3054 struct ixgbe_hw *hw = &adapter->hw;
3055 u64 rdba = ring->dma;
9e10e045 3056 u32 rxdctl;
bf29ee6c 3057 u8 reg_idx = ring->reg_idx;
acd37177 3058
9e10e045
AD		 3059 /* disable queue to avoid issues while updating state */
3060 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3061 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3062
acd37177
AD		 3063 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3064 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3065 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3066 ring->count * sizeof(union ixgbe_adv_rx_desc));
3067 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3068 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3069 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3070
3071 ixgbe_configure_srrctl(adapter, ring);
3072 ixgbe_configure_rscctl(adapter, ring);
3073
e9f98072
GR		 3074 /* If operating in IOV mode set RLPML for X540 */
3075 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3076 hw->mac.type == ixgbe_mac_X540) {
3077 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3078 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3079 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3080 }
3081
9e10e045
AD		 3082 if (hw->mac.type == ixgbe_mac_82598EB) {
3083 /*
3084 * enable cache line friendly hardware writes:
3085 * PTHRESH=32 descriptors (half the internal cache),
3086 * this also removes ugly rx_no_buffer_count increment
3087 * HTHRESH=4 descriptors (to minimize latency on fetch)
3088 * WTHRESH=8 burst writeback up to two cache lines
3089 */
3090 rxdctl &= ~0x3FFFFF;
3091 rxdctl |= 0x080420;
3092 }
3093
3094 /* enable receive descriptor ring */
3095 rxdctl |= IXGBE_RXDCTL_ENABLE;
3096 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3097
3098 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3099 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3100}
3101
48654521
AD		 3102static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3103{
3104 struct ixgbe_hw *hw = &adapter->hw;
3105 int p;
3106
3107 /* PSRTYPE must be initialized in non 82598 adapters */
3108 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3109 IXGBE_PSRTYPE_UDPHDR |
3110 IXGBE_PSRTYPE_IPV4HDR |
48654521 3111 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3112 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3113
3114 if (hw->mac.type == ixgbe_mac_82598EB)
3115 return;
3116
3117 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3118 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3119
3120 for (p = 0; p < adapter->num_rx_pools; p++)
3121 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3122 psrtype);
3123}
3124
f5b4a52e
AD		 3125static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3126{
3127 struct ixgbe_hw *hw = &adapter->hw;
3128 u32 gcr_ext;
3129 u32 vt_reg_bits;
3130 u32 reg_offset, vf_shift;
3131 u32 vmdctl;
de4c7f65 3132 int i;
f5b4a52e
AD		 3133
3134 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3135 return;
3136
3137 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3138 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3139 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3140 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3141
3142 vf_shift = adapter->num_vfs % 32;
4cd6923d 3143 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 3144
3145 /* Enable only the PF's pool for Tx/Rx */
3146 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3147 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3148 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3149 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3150 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3151
3152 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3153 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3154
3155 /*
3156 * Set up VF register offsets for selected VT Mode,
3157 * i.e. 32 or 64 VFs for SR-IOV
3158 */
3159 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3160 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3161 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3162 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3163
3164 /* enable Tx loopback for VF/PF communication */
3165 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3166 /* Enable MAC Anti-Spoofing */
a1cbb15c 3167 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 3168 (adapter->num_vfs != 0),
a985b6c3 3169 adapter->num_vfs);
de4c7f65
GR		 3170 /* For VFs that have spoof checking turned off */
3171 for (i = 0; i < adapter->num_vfs; i++) {
3172 if (!adapter->vfinfo[i].spoofchk_enabled)
3173 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3174 }
f5b4a52e
AD		 3175}
3176
477de6ed 3177static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3178{
9a799d71
AK		 3179 struct ixgbe_hw *hw = &adapter->hw;
3180 struct net_device *netdev = adapter->netdev;
3181 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3182 struct ixgbe_ring *rx_ring;
3183 int i;
3184 u32 mhadd, hlreg0;
48654521 3185
63f39bd1 3186#ifdef IXGBE_FCOE
477de6ed
AD		 3187 /* adjust max frame to be able to do baby jumbo for FCoE */
3188 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3189 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3190 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3191
477de6ed
AD		 3192#endif /* IXGBE_FCOE */
3193 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3194 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3195 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3196 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3197
3198 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3199 }
3200
919e78a6
AD		 3201 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3202 max_frame += VLAN_HLEN;
3203
477de6ed
AD		 3204 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3205 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3206 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3207 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3208
0cefafad
JB		 3209 /*
3210 * Setup the HW Rx Head and Tail Descriptor Pointers and
3211 * the Base and Length of the Rx Descriptor Ring
3212 */
9a799d71 3213 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3214 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3215 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3216 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3217 else
7d637bcc 3218 clear_ring_rsc_enabled(rx_ring);
477de6ed 3219 }
477de6ed
AD		 3220}
3221
7367096a
AD		 3222static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3223{
3224 struct ixgbe_hw *hw = &adapter->hw;
3225 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3226
3227 switch (hw->mac.type) {
3228 case ixgbe_mac_82598EB:
3229 /*
3230 * For VMDq support of different descriptor types or
3231 * buffer sizes through the use of multiple SRRCTL
3232 * registers, RDRXCTL.MVMEN must be set to 1
3233 *
3234 * also, the manual doesn't mention it clearly but DCA hints
3235 * will only use queue 0's tags unless this bit is set. Side
3236 * effects of setting this bit are only that SRRCTL must be
3237 * fully programmed [0..15]
3238 */
3239 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3240 break;
3241 case ixgbe_mac_82599EB:
b93a2226 3242 case ixgbe_mac_X540:
7367096a
AD		 3243 /* Disable RSC for ACK packets */
3244 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3245 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3246 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3247 /* hardware requires some bits to be set by default */
3248 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3249 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3250 break;
3251 default:
3252 /* We should do nothing since we don't know this hardware */
3253 return;
3254 }
3255
3256 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3257}
3258
477de6ed
AD		 3259/**
3260 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3261 * @adapter: board private structure
3262 *
3263 * Configure the Rx unit of the MAC after a reset.
3264 **/
3265static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3266{
3267 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3268 int i;
3269 u32 rxctrl;
477de6ed
AD		 3270
3271 /* disable receives while setting up the descriptors */
3272 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3273 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3274
3275 ixgbe_setup_psrtype(adapter);
7367096a 3276 ixgbe_setup_rdrxctl(adapter);
477de6ed 3277
9e10e045 3278 /* Program registers for the distribution of queues */
f5b4a52e 3279 ixgbe_setup_mrqc(adapter);
f5b4a52e 3280
477de6ed
AD		 3281 /* set_rx_buffer_len must be called before ring initialization */
3282 ixgbe_set_rx_buffer_len(adapter);
3283
3284 /*
3285 * Setup the HW Rx Head and Tail Descriptor Pointers and
3286 * the Base and Length of the Rx Descriptor Ring
3287 */
9e10e045
AD		 3288 for (i = 0; i < adapter->num_rx_queues; i++)
3289 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3290
9e10e045
AD		 3291 /* disable drop enable for 82598 parts */
3292 if (hw->mac.type == ixgbe_mac_82598EB)
3293 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3294
3295 /* enable all receives */
3296 rxctrl |= IXGBE_RXCTRL_RXEN;
3297 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3298}
3299
8e586137 3300static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3301{
3302 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3303 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3304 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3305
3306 /* add VID to filter table */
1ada1b1b 3307 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3308 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3309
3310 return 0;
068c89b0
DS		 3311}
3312
8e586137 3313static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3314{
3315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3316 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3317 int pool_ndx = adapter->num_vfs;
068c89b0 3318
068c89b0 3319 /* remove VID from filter table */
1ada1b1b 3320 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3321 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3322
3323 return 0;
068c89b0
DS		 3324}
3325
5f6c0181
JB		 3326/**
3327 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3328 * @adapter: driver data
3329 */
3330static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3331{
3332 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3333 u32 vlnctrl;
3334
3335 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3336 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3337 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3338}
3339
3340/**
3341 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3342 * @adapter: driver data
3343 */
3344static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3345{
3346 struct ixgbe_hw *hw = &adapter->hw;
3347 u32 vlnctrl;
3348
3349 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3350 vlnctrl |= IXGBE_VLNCTRL_VFE;
3351 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3352 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3353}
3354
3355/**
3356 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3357 * @adapter: driver data
3358 */
3359static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3360{
3361 struct ixgbe_hw *hw = &adapter->hw;
3362 u32 vlnctrl;
5f6c0181
JB		 3363 int i, j;
3364
3365 switch (hw->mac.type) {
3366 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3367 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3368 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3369 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3370 break;
3371 case ixgbe_mac_82599EB:
b93a2226 3372 case ixgbe_mac_X540:
5f6c0181
JB		 3373 for (i = 0; i < adapter->num_rx_queues; i++) {
3374 j = adapter->rx_ring[i]->reg_idx;
3375 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3376 vlnctrl &= ~IXGBE_RXDCTL_VME;
3377 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3378 }
3379 break;
3380 default:
3381 break;
3382 }
3383}
3384
3385/**
f62bbb5e 3386 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3387 * @adapter: driver data
3388 */
f62bbb5e 3389static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3390{
3391 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3392 u32 vlnctrl;
5f6c0181
JB		 3393 int i, j;
3394
3395 switch (hw->mac.type) {
3396 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3397 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3398 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3399 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3400 break;
3401 case ixgbe_mac_82599EB:
b93a2226 3402 case ixgbe_mac_X540:
5f6c0181
JB		 3403 for (i = 0; i < adapter->num_rx_queues; i++) {
3404 j = adapter->rx_ring[i]->reg_idx;
3405 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3406 vlnctrl |= IXGBE_RXDCTL_VME;
3407 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3408 }
3409 break;
3410 default:
3411 break;
3412 }
3413}
3414
9a799d71
AK		 3415static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3416{
f62bbb5e 3417 u16 vid;
9a799d71 3418
f62bbb5e
JG		 3419 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3420
3421 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3422 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3423}
3424
2850062a
AD		 3425/**
3426 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3427 * @netdev: network interface device structure
3428 *
3429 * Writes unicast address list to the RAR table.
3430 * Returns: -ENOMEM on failure/insufficient address space
3431 * 0 on no addresses written
3432 * X on writing X addresses to the RAR table
3433 **/
3434static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3435{
3436 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3437 struct ixgbe_hw *hw = &adapter->hw;
3438 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3439 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3440 int count = 0;
3441
3442 /* return ENOMEM indicating insufficient memory for addresses */
3443 if (netdev_uc_count(netdev) > rar_entries)
3444 return -ENOMEM;
3445
3446 if (!netdev_uc_empty(netdev) && rar_entries) {
3447 struct netdev_hw_addr *ha;
3448 /* return error if we do not support writing to RAR table */
3449 if (!hw->mac.ops.set_rar)
3450 return -ENOMEM;
3451
3452 netdev_for_each_uc_addr(ha, netdev) {
3453 if (!rar_entries)
3454 break;
3455 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3456 vfn, IXGBE_RAH_AV);
3457 count++;
3458 }
3459 }
3460 /* write the addresses in reverse order to avoid write combining */
3461 for (; rar_entries > 0 ; rar_entries--)
3462 hw->mac.ops.clear_rar(hw, rar_entries);
3463
3464 return count;
3465}
3466
9a799d71 3467/**
2c5645cf 3468 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3469 * @netdev: network interface device structure
3470 *
2c5645cf
CL		 3471 * The set_rx_method entry point is called whenever the unicast/multicast
3472 * address list or the network interface flags are updated. This routine is
3473 * responsible for configuring the hardware for proper unicast, multicast and
3474 * promiscuous mode.
9a799d71 3475 **/
7f870475 3476void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3477{
3478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3479 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3480 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3481 int count;
9a799d71
AK		 3482
3483 /* Check for Promiscuous and All Multicast modes */
3484
3485 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3486
f5dc442b 3487 /* set all bits that we expect to always be set */
3f2d1c0f 3488 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3489 fctrl |= IXGBE_FCTRL_BAM;
3490 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3491 fctrl |= IXGBE_FCTRL_PMCF;
3492
2850062a
AD		 3493 /* clear the bits we are changing the status of */
3494 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3495
9a799d71 3496 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3497 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3498 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3499 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3500 /* don't hardware filter vlans in promisc mode */
3501 ixgbe_vlan_filter_disable(adapter);
9a799d71 3502 } else {
746b9f02
PM		 3503 if (netdev->flags & IFF_ALLMULTI) {
3504 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3505 vmolr |= IXGBE_VMOLR_MPE;
3506 } else {
3507 /*
3508 * Write addresses to the MTA, if the attempt fails
25985edc 3509 * then we should just turn on promiscuous mode so
2850062a
AD		 3510 * that we can at least receive multicast traffic
3511 */
3512 hw->mac.ops.update_mc_addr_list(hw, netdev);
3513 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3514 }
5f6c0181 3515 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3516 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3517 }
3518
3519 /*
3520 * Write addresses to available RAR registers, if there is not
3521 * sufficient space to store all the addresses then enable
3522 * unicast promiscuous mode
3523 */
3524 count = ixgbe_write_uc_addr_list(netdev);
3525 if (count < 0) {
3526 fctrl |= IXGBE_FCTRL_UPE;
3527 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3528 }
3529
2850062a 3530 if (adapter->num_vfs) {
1cdd1ec8 3531 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3532 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3533 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3534 IXGBE_VMOLR_ROPE);
3535 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3536 }
3537
3f2d1c0f
BG		 3538 /* This is useful for sniffing bad packets. */
3539 if (adapter->netdev->features & NETIF_F_RXALL) {
3540 /* UPE and MPE will be handled by normal PROMISC logic
3541 * in e1000e_set_rx_mode */
3542 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3543 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3544 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3545
3546 fctrl &= ~(IXGBE_FCTRL_DPF);
3547 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3548 }
3549
2850062a 3550 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3551
3552 if (netdev->features & NETIF_F_HW_VLAN_RX)
3553 ixgbe_vlan_strip_enable(adapter);
3554 else
3555 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3556}
3557
021230d4
AV		 3558static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3559{
3560 int q_idx;
3561 struct ixgbe_q_vector *q_vector;
3562 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3563
3564 /* legacy and MSI only use one vector */
3565 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3566 q_vectors = 1;
3567
3568 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3569 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3570 napi_enable(&q_vector->napi);
021230d4
AV		 3571 }
3572}
3573
3574static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3575{
3576 int q_idx;
3577 struct ixgbe_q_vector *q_vector;
3578 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3579
3580 /* legacy and MSI only use one vector */
3581 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3582 q_vectors = 1;
3583
3584 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3585 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3586 napi_disable(&q_vector->napi);
3587 }
3588}
3589
7a6b6f51 3590#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3591/*
3592 * ixgbe_configure_dcb - Configure DCB hardware
3593 * @adapter: ixgbe adapter struct
3594 *
3595 * This is called by the driver on open to configure the DCB hardware.
3596 * This is also called by the gennetlink interface when reconfiguring
3597 * the DCB state.
3598 */
3599static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3600{
3601 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3602 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3603
67ebd791
AD		 3604 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3605 if (hw->mac.type == ixgbe_mac_82598EB)
3606 netif_set_gso_max_size(adapter->netdev, 65536);
3607 return;
3608 }
3609
3610 if (hw->mac.type == ixgbe_mac_82598EB)
3611 netif_set_gso_max_size(adapter->netdev, 32768);
3612
2f90b865 3613 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3614
971060b1 3615#ifdef IXGBE_FCOE
b120818e
JF		 3616 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3617 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3618#endif
b120818e
JF		 3619
3620 /* reconfigure the hardware */
3621 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3622 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3623 DCB_TX_CONFIG);
3624 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3625 DCB_RX_CONFIG);
3626 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3627 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3628 ixgbe_dcb_hw_ets(&adapter->hw,
3629 adapter->ixgbe_ieee_ets,
3630 max_frame);
3631 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3632 adapter->ixgbe_ieee_pfc->pfc_en,
3633 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3634 }
8187cd48
JF		 3635
3636 /* Enable RSS Hash per TC */
3637 if (hw->mac.type != ixgbe_mac_82598EB) {
3638 int i;
3639 u32 reg = 0;
3640
3641 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3642 u8 msb = 0;
3643 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3644
3645 while (cnt >>= 1)
3646 msb++;
3647
3648 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3649 }
3650 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3651 }
2f90b865 3652}
9da712d2
JF		 3653#endif
3654
3655/* Additional bittime to account for IXGBE framing */
3656#define IXGBE_ETH_FRAMING 20
3657
3658/*
3659 * ixgbe_hpbthresh - calculate high water mark for flow control
3660 *
3661 * @adapter: board private structure to calculate for
3662 * @pb - packet buffer to calculate
3663 */
3664static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3665{
3666 struct ixgbe_hw *hw = &adapter->hw;
3667 struct net_device *dev = adapter->netdev;
3668 int link, tc, kb, marker;
3669 u32 dv_id, rx_pba;
3670
3671 /* Calculate max LAN frame size */
3672 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3673
3674#ifdef IXGBE_FCOE
3675 /* FCoE traffic class uses FCOE jumbo frames */
3676 if (dev->features & NETIF_F_FCOE_MTU) {
3677 int fcoe_pb = 0;
2f90b865 3678
9da712d2
JF		 3679#ifdef CONFIG_IXGBE_DCB
3680 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3681
3682#endif
3683 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3684 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3685 }
2f90b865 3686#endif
80605c65 3687
9da712d2
JF		 3688 /* Calculate delay value for device */
3689 switch (hw->mac.type) {
3690 case ixgbe_mac_X540:
3691 dv_id = IXGBE_DV_X540(link, tc);
3692 break;
3693 default:
3694 dv_id = IXGBE_DV(link, tc);
3695 break;
3696 }
3697
3698 /* Loopback switch introduces additional latency */
3699 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3700 dv_id += IXGBE_B2BT(tc);
3701
3702 /* Delay value is calculated in bit times convert to KB */
3703 kb = IXGBE_BT2KB(dv_id);
3704 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3705
3706 marker = rx_pba - kb;
3707
3708 /* It is possible that the packet buffer is not large enough
3709 * to provide required headroom. In this case throw an error
3710 * to user and a do the best we can.
3711 */
3712 if (marker < 0) {
3713 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3714 "headroom to support flow control."
3715 "Decrease MTU or number of traffic classes\n", pb);
3716 marker = tc + 1;
3717 }
3718
3719 return marker;
3720}
3721
3722/*
3723 * ixgbe_lpbthresh - calculate low water mark for for flow control
3724 *
3725 * @adapter: board private structure to calculate for
3726 * @pb - packet buffer to calculate
3727 */
3728static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3729{
3730 struct ixgbe_hw *hw = &adapter->hw;
3731 struct net_device *dev = adapter->netdev;
3732 int tc;
3733 u32 dv_id;
3734
3735 /* Calculate max LAN frame size */
3736 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3737
3738 /* Calculate delay value for device */
3739 switch (hw->mac.type) {
3740 case ixgbe_mac_X540:
3741 dv_id = IXGBE_LOW_DV_X540(tc);
3742 break;
3743 default:
3744 dv_id = IXGBE_LOW_DV(tc);
3745 break;
3746 }
3747
3748 /* Delay value is calculated in bit times convert to KB */
3749 return IXGBE_BT2KB(dv_id);
3750}
3751
3752/*
3753 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3754 */
3755static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3756{
3757 struct ixgbe_hw *hw = &adapter->hw;
3758 int num_tc = netdev_get_num_tc(adapter->netdev);
3759 int i;
3760
3761 if (!num_tc)
3762 num_tc = 1;
3763
3764 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3765
3766 for (i = 0; i < num_tc; i++) {
3767 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3768
3769 /* Low water marks must not be larger than high water marks */
3770 if (hw->fc.low_water > hw->fc.high_water[i])
3771 hw->fc.low_water = 0;
3772 }
3773}
3774
80605c65
JF		 3775static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3776{
80605c65 3777 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3778 int hdrm;
3779 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3780
3781 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3782 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3783 hdrm = 32 << adapter->fdir_pballoc;
3784 else
3785 hdrm = 0;
80605c65 3786
f7e1027f 3787 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3788 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3789}
3790
e4911d57
AD		 3791static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3792{
3793 struct ixgbe_hw *hw = &adapter->hw;
3794 struct hlist_node *node, *node2;
3795 struct ixgbe_fdir_filter *filter;
3796
3797 spin_lock(&adapter->fdir_perfect_lock);
3798
3799 if (!hlist_empty(&adapter->fdir_filter_list))
3800 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3801
3802 hlist_for_each_entry_safe(filter, node, node2,
3803 &adapter->fdir_filter_list, fdir_node) {
3804 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3805 &filter->filter,
3806 filter->sw_idx,
3807 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3808 IXGBE_FDIR_DROP_QUEUE :
3809 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3810 }
3811
3812 spin_unlock(&adapter->fdir_perfect_lock);
3813}
3814
9a799d71
AK		 3815static void ixgbe_configure(struct ixgbe_adapter *adapter)
3816{
d2f5e7f3
AS		 3817 struct ixgbe_hw *hw = &adapter->hw;
3818
80605c65 3819 ixgbe_configure_pb(adapter);
7a6b6f51 3820#ifdef CONFIG_IXGBE_DCB
67ebd791 3821 ixgbe_configure_dcb(adapter);
2f90b865 3822#endif
9a799d71 3823
4c1d7b4b 3824 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3825 ixgbe_restore_vlan(adapter);
3826
eacd73f7
YZ		 3827#ifdef IXGBE_FCOE
3828 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3829 ixgbe_configure_fcoe(adapter);
3830
3831#endif /* IXGBE_FCOE */
d2f5e7f3
AS		 3832
3833 switch (hw->mac.type) {
3834 case ixgbe_mac_82599EB:
3835 case ixgbe_mac_X540:
3836 hw->mac.ops.disable_rx_buff(hw);
3837 break;
3838 default:
3839 break;
3840 }
3841
c4cf55e5 3842 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3843 ixgbe_init_fdir_signature_82599(&adapter->hw,
3844 adapter->fdir_pballoc);
e4911d57
AD		 3845 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3846 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3847 adapter->fdir_pballoc);
3848 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3849 }
4c1d7b4b 3850
d2f5e7f3
AS		 3851 switch (hw->mac.type) {
3852 case ixgbe_mac_82599EB:
3853 case ixgbe_mac_X540:
3854 hw->mac.ops.enable_rx_buff(hw);
3855 break;
3856 default:
3857 break;
3858 }
3859
933d41f1 3860 ixgbe_configure_virtualization(adapter);
c4cf55e5 3861
9a799d71
AK		 3862 ixgbe_configure_tx(adapter);
3863 ixgbe_configure_rx(adapter);
9a799d71
AK		 3864}
3865
e8e26350
PW		 3866static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3867{
3868 switch (hw->phy.type) {
3869 case ixgbe_phy_sfp_avago:
3870 case ixgbe_phy_sfp_ftl:
3871 case ixgbe_phy_sfp_intel:
3872 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3873 case ixgbe_phy_sfp_passive_tyco:
3874 case ixgbe_phy_sfp_passive_unknown:
3875 case ixgbe_phy_sfp_active_unknown:
3876 case ixgbe_phy_sfp_ftl_active:
e8e26350 3877 return true;
8917b447
AD		 3878 case ixgbe_phy_nl:
3879 if (hw->mac.type == ixgbe_mac_82598EB)
3880 return true;
e8e26350
PW		 3881 default:
3882 return false;
3883 }
3884}
3885
0ecc061d 3886/**
e8e26350
PW		 3887 * ixgbe_sfp_link_config - set up SFP+ link
3888 * @adapter: pointer to private adapter struct
3889 **/
3890static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3891{
7086400d 3892 /*
52f33af8 3893 * We are assuming the worst case scenario here, and that
7086400d
AD		 3894 * is that an SFP was inserted/removed after the reset
3895 * but before SFP detection was enabled. As such the best
3896 * solution is to just start searching as soon as we start
3897 */
3898 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3899 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3900
7086400d 3901 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3902}
3903
3904/**
3905 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3906 * @hw: pointer to private hardware struct
3907 *
3908 * Returns 0 on success, negative on failure
3909 **/
e8e26350 3910static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3911{
3912 u32 autoneg;
8620a103 3913 bool negotiation, link_up = false;
0ecc061d
PWJ		 3914 u32 ret = IXGBE_ERR_LINK_SETUP;
3915
3916 if (hw->mac.ops.check_link)
3917 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3918
3919 if (ret)
3920 goto link_cfg_out;
3921
0b0c2b31
ET		 3922 autoneg = hw->phy.autoneg_advertised;
3923 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3924 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3925 &negotiation);
0ecc061d
PWJ		 3926 if (ret)
3927 goto link_cfg_out;
3928
8620a103
MC		 3929 if (hw->mac.ops.setup_link)
3930 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3931link_cfg_out:
3932 return ret;
3933}
3934
a34bcfff 3935static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3936{
9a799d71 3937 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3938 u32 gpie = 0;
9a799d71 3939
9b471446 3940 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3941 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3942 IXGBE_GPIE_OCD;
3943 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3944 /*
3945 * use EIAM to auto-mask when MSI-X interrupt is asserted
3946 * this saves a register write for every interrupt
3947 */
3948 switch (hw->mac.type) {
3949 case ixgbe_mac_82598EB:
3950 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3951 break;
9b471446 3952 case ixgbe_mac_82599EB:
b93a2226
DS		 3953 case ixgbe_mac_X540:
3954 default:
9b471446
JB		 3955 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3956 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3957 break;
3958 }
3959 } else {
021230d4
AV		 3960 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3961 * specifically only auto mask tx and rx interrupts */
3962 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3963 }
9a799d71 3964
a34bcfff
AD		 3965 /* XXX: to interrupt immediately for EICS writes, enable this */
3966 /* gpie |= IXGBE_GPIE_EIMEN; */
3967
3968 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3969 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3970 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3971 }
3972
5fdd31f9 3973 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3974 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3975 switch (adapter->hw.mac.type) {
3976 case ixgbe_mac_82599EB:
3977 gpie |= IXGBE_SDP0_GPIEN;
3978 break;
3979 case ixgbe_mac_X540:
3980 gpie |= IXGBE_EIMS_TS;
3981 break;
3982 default:
3983 break;
3984 }
3985 }
5fdd31f9 3986
a34bcfff
AD		 3987 /* Enable fan failure interrupt */
3988 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3989 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3990
2698b208 3991 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3992 gpie |= IXGBE_SDP1_GPIEN;
3993 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3994 }
a34bcfff
AD		 3995
3996 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3997}
3998
c7ccde0f 3999static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4000{
4001 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4002 int err;
a34bcfff
AD		 4003 u32 ctrl_ext;
4004
4005 ixgbe_get_hw_control(adapter);
4006 ixgbe_setup_gpie(adapter);
e8e26350 4007
9a799d71
AK		 4008 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4009 ixgbe_configure_msix(adapter);
4010 else
4011 ixgbe_configure_msi_and_legacy(adapter);
4012
c6ecf39a
DS		 4013 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4014 if (hw->mac.ops.enable_tx_laser &&
4015 ((hw->phy.multispeed_fiber) ||
9f911707 4016 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 4017 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 4018 hw->mac.ops.enable_tx_laser(hw);
4019
9a799d71 4020 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4021 ixgbe_napi_enable_all(adapter);
4022
73c4b7cd
AD		 4023 if (ixgbe_is_sfp(hw)) {
4024 ixgbe_sfp_link_config(adapter);
4025 } else {
4026 err = ixgbe_non_sfp_link_config(hw);
4027 if (err)
4028 e_err(probe, "link_config FAILED %d\n", err);
4029 }
4030
021230d4
AV		 4031 /* clear any pending interrupts, may auto mask */
4032 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4033 ixgbe_irq_enable(adapter, true, true);
9a799d71 4034
bf069c97
DS		 4035 /*
4036 * If this adapter has a fan, check to see if we had a failure
4037 * before we enabled the interrupt.
4038 */
4039 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4040 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4041 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4042 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4043 }
4044
1da100bb 4045 /* enable transmits */
477de6ed 4046 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4047
9a799d71
AK		 4048 /* bring the link up in the watchdog, this could race with our first
4049 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4050 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4051 adapter->link_check_timeout = jiffies;
7086400d 4052 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4053
4054 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4055 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4056 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4057 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4058}
4059
d4f80882
AV		 4060void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4061{
4062 WARN_ON(in_interrupt());
7086400d
AD		 4063 /* put off any impending NetWatchDogTimeout */
4064 adapter->netdev->trans_start = jiffies;
4065
d4f80882 4066 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4067 usleep_range(1000, 2000);
d4f80882 4068 ixgbe_down(adapter);
5809a1ae
GR		 4069 /*
4070 * If SR-IOV enabled then wait a bit before bringing the adapter
4071 * back up to give the VFs time to respond to the reset. The
4072 * two second wait is based upon the watchdog timer cycle in
4073 * the VF driver.
4074 */
4075 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4076 msleep(2000);
d4f80882
AV		 4077 ixgbe_up(adapter);
4078 clear_bit(__IXGBE_RESETTING, &adapter->state);
4079}
4080
c7ccde0f 4081void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4082{
4083 /* hardware has been reset, we need to reload some things */
4084 ixgbe_configure(adapter);
4085
c7ccde0f 4086 ixgbe_up_complete(adapter);
9a799d71
AK		 4087}
4088
4089void ixgbe_reset(struct ixgbe_adapter *adapter)
4090{
c44ade9e 4091 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4092 int err;
4093
7086400d
AD		 4094 /* lock SFP init bit to prevent race conditions with the watchdog */
4095 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4096 usleep_range(1000, 2000);
4097
4098 /* clear all SFP and link config related flags while holding SFP_INIT */
4099 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4100 IXGBE_FLAG2_SFP_NEEDS_RESET);
4101 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4102
8ca783ab 4103 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4104 switch (err) {
4105 case 0:
4106 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4107 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4108 break;
4109 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4110 e_dev_err("master disable timed out\n");
da4dd0f7 4111 break;
794caeb2
PWJ		 4112 case IXGBE_ERR_EEPROM_VERSION:
4113 /* We are running on a pre-production device, log a warning */
849c4542 4114 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4115 "Please be aware there may be issues associated with "
849c4542
ET		 4116 "your hardware. If you are experiencing problems "
4117 "please contact your Intel or hardware "
4118 "representative who provided you with this "
4119 "hardware.\n");
794caeb2 4120 break;
da4dd0f7 4121 default:
849c4542 4122 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4123 }
9a799d71 4124
7086400d
AD		 4125 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4126
9a799d71 4127 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4128 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4129 IXGBE_RAH_AV);
9a799d71
AK		 4130}
4131
f800326d
AD		 4132/**
4133 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4134 * @rx_ring: ring to setup
4135 *
4136 * On many IA platforms the L1 cache has a critical stride of 4K, this
4137 * results in each receive buffer starting in the same cache set. To help
4138 * reduce the pressure on this cache set we can interleave the offsets so
4139 * that only every other buffer will be in the same cache set.
4140 **/
4141static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4142{
4143 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4144 u16 i;
4145
4146 for (i = 0; i < rx_ring->count; i += 2) {
4147 rx_buffer[0].page_offset = 0;
4148 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4149 rx_buffer = &rx_buffer[2];
4150 }
4151}
4152
9a799d71
AK		 4153/**
4154 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4155 * @rx_ring: ring to free buffers from
4156 **/
b6ec895e 4157static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4158{
b6ec895e 4159 struct device *dev = rx_ring->dev;
9a799d71 4160 unsigned long size;
b6ec895e 4161 u16 i;
9a799d71 4162
84418e3b
AD		 4163 /* ring already cleared, nothing to do */
4164 if (!rx_ring->rx_buffer_info)
4165 return;
9a799d71 4166
84418e3b 4167 /* Free all the Rx ring sk_buffs */
9a799d71 4168 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4169 struct ixgbe_rx_buffer *rx_buffer;
4170
4171 rx_buffer = &rx_ring->rx_buffer_info[i];
4172 if (rx_buffer->skb) {
4173 struct sk_buff *skb = rx_buffer->skb;
4174 if (IXGBE_CB(skb)->page_released) {
4175 dma_unmap_page(dev,
4176 IXGBE_CB(skb)->dma,
4177 ixgbe_rx_bufsz(rx_ring),
4178 DMA_FROM_DEVICE);
4179 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4180 }
4181 dev_kfree_skb(skb);
9a799d71 4182 }
f800326d
AD		 4183 rx_buffer->skb = NULL;
4184 if (rx_buffer->dma)
4185 dma_unmap_page(dev, rx_buffer->dma,
4186 ixgbe_rx_pg_size(rx_ring),
4187 DMA_FROM_DEVICE);
4188 rx_buffer->dma = 0;
4189 if (rx_buffer->page)
dd411ec4
AD		 4190 __free_pages(rx_buffer->page,
4191 ixgbe_rx_pg_order(rx_ring));
f800326d 4192 rx_buffer->page = NULL;
9a799d71
AK		 4193 }
4194
4195 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4196 memset(rx_ring->rx_buffer_info, 0, size);
4197
f800326d
AD		 4198 ixgbe_init_rx_page_offset(rx_ring);
4199
9a799d71
AK		 4200 /* Zero out the descriptor ring */
4201 memset(rx_ring->desc, 0, rx_ring->size);
4202
f800326d 4203 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4204 rx_ring->next_to_clean = 0;
4205 rx_ring->next_to_use = 0;
9a799d71
AK		 4206}
4207
4208/**
4209 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4210 * @tx_ring: ring to be cleaned
4211 **/
b6ec895e 4212static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4213{
4214 struct ixgbe_tx_buffer *tx_buffer_info;
4215 unsigned long size;
b6ec895e 4216 u16 i;
9a799d71 4217
84418e3b
AD		 4218 /* ring already cleared, nothing to do */
4219 if (!tx_ring->tx_buffer_info)
4220 return;
9a799d71 4221
84418e3b 4222 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4223 for (i = 0; i < tx_ring->count; i++) {
4224 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4225 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4226 }
4227
dad8a3b3
JF		 4228 netdev_tx_reset_queue(txring_txq(tx_ring));
4229
9a799d71
AK		 4230 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4231 memset(tx_ring->tx_buffer_info, 0, size);
4232
4233 /* Zero out the descriptor ring */
4234 memset(tx_ring->desc, 0, tx_ring->size);
4235
4236 tx_ring->next_to_use = 0;
4237 tx_ring->next_to_clean = 0;
9a799d71
AK		 4238}
4239
4240/**
021230d4 4241 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4242 * @adapter: board private structure
4243 **/
021230d4 4244static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4245{
4246 int i;
4247
021230d4 4248 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4249 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4250}
4251
4252/**
021230d4 4253 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4254 * @adapter: board private structure
4255 **/
021230d4 4256static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4257{
4258 int i;
4259
021230d4 4260 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4261 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4262}
4263
e4911d57
AD		 4264static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4265{
4266 struct hlist_node *node, *node2;
4267 struct ixgbe_fdir_filter *filter;
4268
4269 spin_lock(&adapter->fdir_perfect_lock);
4270
4271 hlist_for_each_entry_safe(filter, node, node2,
4272 &adapter->fdir_filter_list, fdir_node) {
4273 hlist_del(&filter->fdir_node);
4274 kfree(filter);
4275 }
4276 adapter->fdir_filter_count = 0;
4277
4278 spin_unlock(&adapter->fdir_perfect_lock);
4279}
4280
9a799d71
AK		 4281void ixgbe_down(struct ixgbe_adapter *adapter)
4282{
4283 struct net_device *netdev = adapter->netdev;
7f821875 4284 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4285 u32 rxctrl;
bf29ee6c 4286 int i;
9a799d71
AK		 4287
4288 /* signal that we are down to the interrupt handler */
4289 set_bit(__IXGBE_DOWN, &adapter->state);
4290
4291 /* disable receives */
7f821875
JB		 4292 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4293 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4294
2d39d576
YZ		 4295 /* disable all enabled rx queues */
4296 for (i = 0; i < adapter->num_rx_queues; i++)
4297 /* this call also flushes the previous write */
4298 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4299
032b4325 4300 usleep_range(10000, 20000);
9a799d71 4301
7f821875
JB		 4302 netif_tx_stop_all_queues(netdev);
4303
7086400d 4304 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4305 netif_carrier_off(netdev);
4306 netif_tx_disable(netdev);
4307
4308 ixgbe_irq_disable(adapter);
4309
4310 ixgbe_napi_disable_all(adapter);
4311
d034acf1
AD		 4312 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4313 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4314 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4315
4316 del_timer_sync(&adapter->service_timer);
4317
34cecbbf 4318 if (adapter->num_vfs) {
8e34d1aa
AD		 4319 /* Clear EITR Select mapping */
4320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4321
4322 /* Mark all the VFs as inactive */
4323 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4324 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4325
34cecbbf
AD		 4326 /* ping all the active vfs to let them know we are going down */
4327 ixgbe_ping_all_vfs(adapter);
4328
4329 /* Disable all VFTE/VFRE TX/RX */
4330 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4331 }
4332
7f821875
JB		 4333 /* disable transmits in the hardware now that interrupts are off */
4334 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4335 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4336 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4337 }
34cecbbf
AD		 4338
4339 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4340 switch (hw->mac.type) {
4341 case ixgbe_mac_82599EB:
b93a2226 4342 case ixgbe_mac_X540:
88512539 4343 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4344 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4345 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4346 break;
4347 default:
4348 break;
4349 }
7f821875 4350
6f4a0e45
PL		 4351 if (!pci_channel_offline(adapter->pdev))
4352 ixgbe_reset(adapter);
c6ecf39a
DS		 4353
4354 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4355 if (hw->mac.ops.disable_tx_laser &&
4356 ((hw->phy.multispeed_fiber) ||
9f911707 4357 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4358 (hw->mac.type == ixgbe_mac_82599EB))))
4359 hw->mac.ops.disable_tx_laser(hw);
4360
9a799d71
AK		 4361 ixgbe_clean_all_tx_rings(adapter);
4362 ixgbe_clean_all_rx_rings(adapter);
4363
5dd2d332 4364#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4365 /* since we reset the hardware DCA settings were cleared */
e35ec126 4366 ixgbe_setup_dca(adapter);
96b0e0f6 4367#endif
9a799d71
AK		 4368}
4369
9a799d71
AK		 4370/**
4371 * ixgbe_tx_timeout - Respond to a Tx Hang
4372 * @netdev: network interface device structure
4373 **/
4374static void ixgbe_tx_timeout(struct net_device *netdev)
4375{
4376 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4377
4378 /* Do the reset outside of interrupt context */
c83c6cbd 4379 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4380}
4381
9a799d71
AK		 4382/**
4383 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4384 * @adapter: board private structure to initialize
4385 *
4386 * ixgbe_sw_init initializes the Adapter private data structure.
4387 * Fields are initialized based on PCI device information and
4388 * OS network device settings (MTU size).
4389 **/
4390static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4391{
4392 struct ixgbe_hw *hw = &adapter->hw;
4393 struct pci_dev *pdev = adapter->pdev;
021230d4 4394 unsigned int rss;
7a6b6f51 4395#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4396 int j;
4397 struct tc_configuration *tc;
4398#endif
021230d4 4399
c44ade9e
JB		 4400 /* PCI config space info */
4401
4402 hw->vendor_id = pdev->vendor;
4403 hw->device_id = pdev->device;
4404 hw->revision_id = pdev->revision;
4405 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4406 hw->subsystem_device_id = pdev->subsystem_device;
4407
021230d4 4408 /* Set capability flags */
3ed69d7e 4409 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
021230d4
AV		 4410 adapter->ring_feature[RING_F_RSS].indices = rss;
4411 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4412 switch (hw->mac.type) {
4413 case ixgbe_mac_82598EB:
bf069c97
DS		 4414 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4415 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4416 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 4417 break;
b93a2226 4418 case ixgbe_mac_X540:
4f51bf70
JK		 4419 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4420 case ixgbe_mac_82599EB:
e8e26350 4421 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4422 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4423 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4424 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4425 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4426 /* Flow Director hash filters enabled */
4427 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4428 adapter->atr_sample_rate = 20;
c4cf55e5 4429 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4430 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4431 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4432#ifdef IXGBE_FCOE
0d551589
YZ		 4433 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4434 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4435 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4436#ifdef CONFIG_IXGBE_DCB
6ee16520 4437 /* Default traffic class to use for FCoE */
56075a98 4438 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4439#endif
eacd73f7 4440#endif /* IXGBE_FCOE */
bd508178
AD		 4441 break;
4442 default:
4443 break;
f8212f97 4444 }
2f90b865 4445
1fc5f038
AD		 4446 /* n-tuple support exists, always init our spinlock */
4447 spin_lock_init(&adapter->fdir_perfect_lock);
4448
7a6b6f51 4449#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4450 switch (hw->mac.type) {
4451 case ixgbe_mac_X540:
4452 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4453 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4454 break;
4455 default:
4456 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4457 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4458 break;
4459 }
4460
2f90b865
AD		 4461 /* Configure DCB traffic classes */
4462 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4463 tc = &adapter->dcb_cfg.tc_config[j];
4464 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4465 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4466 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4467 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4468 tc->dcb_pfc = pfc_disabled;
4469 }
4de2a022
JF		 4470
4471 /* Initialize default user to priority mapping, UPx->TC0 */
4472 tc = &adapter->dcb_cfg.tc_config[0];
4473 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4474 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4475
2f90b865
AD		 4476 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4477 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4478 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4479 adapter->dcb_set_bitmap = 0x00;
3032309b 4480 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4481 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4482 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4483
4484#endif
9a799d71
AK		 4485
4486 /* default flow control settings */
cd7664f6 4487 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4488 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4489 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4490 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4491 hw->fc.send_xon = true;
71fd570b 4492 hw->fc.disable_fc_autoneg = false;
9a799d71 4493
30efa5a3 4494 /* enable itr by default in dynamic mode */
f7554a2b 4495 adapter->rx_itr_setting = 1;
f7554a2b 4496 adapter->tx_itr_setting = 1;
30efa5a3 4497
30efa5a3
JB		 4498 /* set default ring sizes */
4499 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4500 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4501
bd198058 4502 /* set default work limits */
59224555 4503 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4504
9a799d71 4505 /* initialize eeprom parameters */
c44ade9e 4506 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4507 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4508 return -EIO;
4509 }
4510
9a799d71
AK		 4511 set_bit(__IXGBE_DOWN, &adapter->state);
4512
4513 return 0;
4514}
4515
4516/**
4517 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4518 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4519 *
4520 * Return 0 on success, negative on failure
4521 **/
b6ec895e 4522int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4523{
b6ec895e 4524 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4525 int orig_node = dev_to_node(dev);
4526 int numa_node = -1;
9a799d71
AK		 4527 int size;
4528
3a581073 4529 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4530
4531 if (tx_ring->q_vector)
4532 numa_node = tx_ring->q_vector->numa_node;
4533
4534 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4535 if (!tx_ring->tx_buffer_info)
89bf67f1 4536 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4537 if (!tx_ring->tx_buffer_info)
4538 goto err;
9a799d71
AK		 4539
4540 /* round up to nearest 4K */
12207e49 4541 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4542 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4543
de88eeeb
AD		 4544 set_dev_node(dev, numa_node);
4545 tx_ring->desc = dma_alloc_coherent(dev,
4546 tx_ring->size,
4547 &tx_ring->dma,
4548 GFP_KERNEL);
4549 set_dev_node(dev, orig_node);
4550 if (!tx_ring->desc)
4551 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4552 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4553 if (!tx_ring->desc)
4554 goto err;
9a799d71 4555
3a581073
JB		 4556 tx_ring->next_to_use = 0;
4557 tx_ring->next_to_clean = 0;
9a799d71 4558 return 0;
e01c31a5
JB		 4559
4560err:
4561 vfree(tx_ring->tx_buffer_info);
4562 tx_ring->tx_buffer_info = NULL;
b6ec895e 4563 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4564 return -ENOMEM;
9a799d71
AK		 4565}
4566
69888674
AD		 4567/**
4568 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4569 * @adapter: board private structure
4570 *
4571 * If this function returns with an error, then it's possible one or
4572 * more of the rings is populated (while the rest are not). It is the
4573 * callers duty to clean those orphaned rings.
4574 *
4575 * Return 0 on success, negative on failure
4576 **/
4577static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4578{
4579 int i, err = 0;
4580
4581 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4582 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4583 if (!err)
4584 continue;
396e799c 4585 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 4586 break;
4587 }
4588
4589 return err;
4590}
4591
9a799d71
AK		 4592/**
4593 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4594 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4595 *
4596 * Returns 0 on success, negative on failure
4597 **/
b6ec895e 4598int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4599{
b6ec895e 4600 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4601 int orig_node = dev_to_node(dev);
4602 int numa_node = -1;
021230d4 4603 int size;
9a799d71 4604
3a581073 4605 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4606
4607 if (rx_ring->q_vector)
4608 numa_node = rx_ring->q_vector->numa_node;
4609
4610 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4611 if (!rx_ring->rx_buffer_info)
89bf67f1 4612 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4613 if (!rx_ring->rx_buffer_info)
4614 goto err;
9a799d71 4615
9a799d71 4616 /* Round up to nearest 4K */
3a581073
JB		 4617 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4618 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4619
de88eeeb
AD		 4620 set_dev_node(dev, numa_node);
4621 rx_ring->desc = dma_alloc_coherent(dev,
4622 rx_ring->size,
4623 &rx_ring->dma,
4624 GFP_KERNEL);
4625 set_dev_node(dev, orig_node);
4626 if (!rx_ring->desc)
4627 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4628 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4629 if (!rx_ring->desc)
4630 goto err;
9a799d71 4631
3a581073
JB		 4632 rx_ring->next_to_clean = 0;
4633 rx_ring->next_to_use = 0;
9a799d71 4634
f800326d
AD		 4635 ixgbe_init_rx_page_offset(rx_ring);
4636
9a799d71 4637 return 0;
b6ec895e
AD		 4638err:
4639 vfree(rx_ring->rx_buffer_info);
4640 rx_ring->rx_buffer_info = NULL;
4641 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4642 return -ENOMEM;
9a799d71
AK		 4643}
4644
69888674
AD		 4645/**
4646 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4647 * @adapter: board private structure
4648 *
4649 * If this function returns with an error, then it's possible one or
4650 * more of the rings is populated (while the rest are not). It is the
4651 * callers duty to clean those orphaned rings.
4652 *
4653 * Return 0 on success, negative on failure
4654 **/
69888674
AD		 4655static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4656{
4657 int i, err = 0;
4658
4659 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4660 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4661 if (!err)
4662 continue;
396e799c 4663 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 4664 break;
4665 }
4666
4667 return err;
4668}
4669
9a799d71
AK		 4670/**
4671 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4672 * @tx_ring: Tx descriptor ring for a specific queue
4673 *
4674 * Free all transmit software resources
4675 **/
b6ec895e 4676void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4677{
b6ec895e 4678 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4679
4680 vfree(tx_ring->tx_buffer_info);
4681 tx_ring->tx_buffer_info = NULL;
4682
b6ec895e
AD		 4683 /* if not set, then don't free */
4684 if (!tx_ring->desc)
4685 return;
4686
4687 dma_free_coherent(tx_ring->dev, tx_ring->size,
4688 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4689
4690 tx_ring->desc = NULL;
4691}
4692
4693/**
4694 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4695 * @adapter: board private structure
4696 *
4697 * Free all transmit software resources
4698 **/
4699static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4700{
4701 int i;
4702
4703 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4704 if (adapter->tx_ring[i]->desc)
b6ec895e 4705 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4706}
4707
4708/**
b4617240 4709 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4710 * @rx_ring: ring to clean the resources from
4711 *
4712 * Free all receive software resources
4713 **/
b6ec895e 4714void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4715{
b6ec895e 4716 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4717
4718 vfree(rx_ring->rx_buffer_info);
4719 rx_ring->rx_buffer_info = NULL;
4720
b6ec895e
AD		 4721 /* if not set, then don't free */
4722 if (!rx_ring->desc)
4723 return;
4724
4725 dma_free_coherent(rx_ring->dev, rx_ring->size,
4726 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4727
4728 rx_ring->desc = NULL;
4729}
4730
4731/**
4732 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4733 * @adapter: board private structure
4734 *
4735 * Free all receive software resources
4736 **/
4737static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4738{
4739 int i;
4740
4741 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4742 if (adapter->rx_ring[i]->desc)
b6ec895e 4743 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4744}
4745
9a799d71
AK		 4746/**
4747 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4748 * @netdev: network interface device structure
4749 * @new_mtu: new value for maximum frame size
4750 *
4751 * Returns 0 on success, negative on failure
4752 **/
4753static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4754{
4755 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4756 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4757
42c783c5 4758 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4759 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4760 return -EINVAL;
4761
4762 /*
4763 * For 82599EB we cannot allow PF to change MTU greater than 1500
4764 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4765 * don't allocate and chain buffers correctly.
4766 */
4767 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4768 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4769 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 4770 return -EINVAL;
9a799d71 4771
396e799c 4772 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4773
021230d4 4774 /* must set new MTU before calling down or up */
9a799d71
AK		 4775 netdev->mtu = new_mtu;
4776
d4f80882
AV		 4777 if (netif_running(netdev))
4778 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4779
4780 return 0;
4781}
4782
4783/**
4784 * ixgbe_open - Called when a network interface is made active
4785 * @netdev: network interface device structure
4786 *
4787 * Returns 0 on success, negative value on failure
4788 *
4789 * The open entry point is called when a network interface is made
4790 * active by the system (IFF_UP). At this point all resources needed
4791 * for transmit and receive operations are allocated, the interrupt
4792 * handler is registered with the OS, the watchdog timer is started,
4793 * and the stack is notified that the interface is ready.
4794 **/
4795static int ixgbe_open(struct net_device *netdev)
4796{
4797 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4798 int err;
4bebfaa5
AK		 4799
4800 /* disallow open during test */
4801 if (test_bit(__IXGBE_TESTING, &adapter->state))
4802 return -EBUSY;
9a799d71 4803
54386467
JB		 4804 netif_carrier_off(netdev);
4805
9a799d71
AK		 4806 /* allocate transmit descriptors */
4807 err = ixgbe_setup_all_tx_resources(adapter);
4808 if (err)
4809 goto err_setup_tx;
4810
9a799d71
AK		 4811 /* allocate receive descriptors */
4812 err = ixgbe_setup_all_rx_resources(adapter);
4813 if (err)
4814 goto err_setup_rx;
4815
4816 ixgbe_configure(adapter);
4817
021230d4 4818 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4819 if (err)
4820 goto err_req_irq;
4821
c7ccde0f 4822 ixgbe_up_complete(adapter);
9a799d71
AK		 4823
4824 return 0;
4825
9a799d71 4826err_req_irq:
9a799d71 4827err_setup_rx:
a20a1199 4828 ixgbe_free_all_rx_resources(adapter);
9a799d71 4829err_setup_tx:
a20a1199 4830 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 4831 ixgbe_reset(adapter);
4832
4833 return err;
4834}
4835
4836/**
4837 * ixgbe_close - Disables a network interface
4838 * @netdev: network interface device structure
4839 *
4840 * Returns 0, this is not allowed to fail
4841 *
4842 * The close entry point is called when an interface is de-activated
4843 * by the OS. The hardware is still under the drivers control, but
4844 * needs to be disabled. A global MAC reset is issued to stop the
4845 * hardware, and all transmit and receive resources are freed.
4846 **/
4847static int ixgbe_close(struct net_device *netdev)
4848{
4849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4850
4851 ixgbe_down(adapter);
4852 ixgbe_free_irq(adapter);
4853
e4911d57
AD		 4854 ixgbe_fdir_filter_exit(adapter);
4855
9a799d71
AK		 4856 ixgbe_free_all_tx_resources(adapter);
4857 ixgbe_free_all_rx_resources(adapter);
4858
5eba3699 4859 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4860
4861 return 0;
4862}
4863
b3c8b4ba
AD		 4864#ifdef CONFIG_PM
4865static int ixgbe_resume(struct pci_dev *pdev)
4866{
c60fbb00
AD		 4867 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4868 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4869 u32 err;
4870
4871 pci_set_power_state(pdev, PCI_D0);
4872 pci_restore_state(pdev);
656ab817
DS		 4873 /*
4874 * pci_restore_state clears dev->state_saved so call
4875 * pci_save_state to restore it.
4876 */
4877 pci_save_state(pdev);
9ce77666 4878
4879 err = pci_enable_device_mem(pdev);
b3c8b4ba 4880 if (err) {
849c4542 4881 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4882 return err;
4883 }
4884 pci_set_master(pdev);
4885
dd4d8ca6 4886 pci_wake_from_d3(pdev, false);
b3c8b4ba 4887
34948a94 4888 rtnl_lock();
b3c8b4ba 4889 err = ixgbe_init_interrupt_scheme(adapter);
34948a94 4890 rtnl_unlock();
b3c8b4ba 4891 if (err) {
849c4542 4892 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 4893 return err;
4894 }
4895
b3c8b4ba
AD		 4896 ixgbe_reset(adapter);
4897
495dce12
WJP		 4898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4899
b3c8b4ba 4900 if (netif_running(netdev)) {
c60fbb00 4901 err = ixgbe_open(netdev);
b3c8b4ba
AD		 4902 if (err)
4903 return err;
4904 }
4905
4906 netif_device_attach(netdev);
4907
4908 return 0;
4909}
b3c8b4ba 4910#endif /* CONFIG_PM */
9d8d05ae
RW		 4911
4912static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 4913{
c60fbb00
AD		 4914 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4915 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 4916 struct ixgbe_hw *hw = &adapter->hw;
4917 u32 ctrl, fctrl;
4918 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4919#ifdef CONFIG_PM
4920 int retval = 0;
4921#endif
4922
4923 netif_device_detach(netdev);
4924
4925 if (netif_running(netdev)) {
ab6039a7 4926 rtnl_lock();
b3c8b4ba
AD		 4927 ixgbe_down(adapter);
4928 ixgbe_free_irq(adapter);
4929 ixgbe_free_all_tx_resources(adapter);
4930 ixgbe_free_all_rx_resources(adapter);
ab6039a7 4931 rtnl_unlock();
b3c8b4ba 4932 }
b3c8b4ba 4933
5f5ae6fc
AD		 4934 ixgbe_clear_interrupt_scheme(adapter);
4935
b3c8b4ba
AD		 4936#ifdef CONFIG_PM
4937 retval = pci_save_state(pdev);
4938 if (retval)
4939 return retval;
4df10466 4940
b3c8b4ba 4941#endif
e8e26350
PW		 4942 if (wufc) {
4943 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4944
c509e754
DS		 4945 /*
4946 * enable the optics for both mult-speed fiber and
4947 * 82599 SFP+ fiber as we can WoL.
4948 */
4949 if (hw->mac.ops.enable_tx_laser &&
4950 (hw->phy.multispeed_fiber ||
4951 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4952 hw->mac.type == ixgbe_mac_82599EB)))
4953 hw->mac.ops.enable_tx_laser(hw);
4954
e8e26350
PW		 4955 /* turn on all-multi mode if wake on multicast is enabled */
4956 if (wufc & IXGBE_WUFC_MC) {
4957 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4958 fctrl |= IXGBE_FCTRL_MPE;
4959 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4960 }
4961
4962 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4963 ctrl |= IXGBE_CTRL_GIO_DIS;
4964 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4965
4966 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4967 } else {
4968 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4969 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4970 }
4971
bd508178
AD		 4972 switch (hw->mac.type) {
4973 case ixgbe_mac_82598EB:
dd4d8ca6 4974 pci_wake_from_d3(pdev, false);
bd508178
AD		 4975 break;
4976 case ixgbe_mac_82599EB:
b93a2226 4977 case ixgbe_mac_X540:
bd508178
AD		 4978 pci_wake_from_d3(pdev, !!wufc);
4979 break;
4980 default:
4981 break;
4982 }
b3c8b4ba 4983
9d8d05ae
RW		 4984 *enable_wake = !!wufc;
4985
b3c8b4ba
AD		 4986 ixgbe_release_hw_control(adapter);
4987
4988 pci_disable_device(pdev);
4989
9d8d05ae
RW		 4990 return 0;
4991}
4992
4993#ifdef CONFIG_PM
4994static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4995{
4996 int retval;
4997 bool wake;
4998
4999 retval = __ixgbe_shutdown(pdev, &wake);
5000 if (retval)
5001 return retval;
5002
5003 if (wake) {
5004 pci_prepare_to_sleep(pdev);
5005 } else {
5006 pci_wake_from_d3(pdev, false);
5007 pci_set_power_state(pdev, PCI_D3hot);
5008 }
b3c8b4ba
AD		 5009
5010 return 0;
5011}
9d8d05ae 5012#endif /* CONFIG_PM */
b3c8b4ba
AD		 5013
5014static void ixgbe_shutdown(struct pci_dev *pdev)
5015{
9d8d05ae
RW		 5016 bool wake;
5017
5018 __ixgbe_shutdown(pdev, &wake);
5019
5020 if (system_state == SYSTEM_POWER_OFF) {
5021 pci_wake_from_d3(pdev, wake);
5022 pci_set_power_state(pdev, PCI_D3hot);
5023 }
b3c8b4ba
AD		 5024}
5025
9a799d71
AK		 5026/**
5027 * ixgbe_update_stats - Update the board statistics counters.
5028 * @adapter: board private structure
5029 **/
5030void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5031{
2d86f139 5032 struct net_device *netdev = adapter->netdev;
9a799d71 5033 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5034 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5035 u64 total_mpc = 0;
5036 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5037 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5038 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5039 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7b859ebc
AH		 5040#ifdef IXGBE_FCOE
5041 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5042 unsigned int cpu;
5043 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5044#endif /* IXGBE_FCOE */
9a799d71 5045
d08935c2
DS		 5046 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5047 test_bit(__IXGBE_RESETTING, &adapter->state))
5048 return;
5049
94b982b2 5050 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5051 u64 rsc_count = 0;
94b982b2 5052 u64 rsc_flush = 0;
94b982b2 5053 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5054 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5055 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5056 }
5057 adapter->rsc_total_count = rsc_count;
5058 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5059 }
5060
5b7da515
AD		 5061 for (i = 0; i < adapter->num_rx_queues; i++) {
5062 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5063 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5064 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5065 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5066 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5067 bytes += rx_ring->stats.bytes;
5068 packets += rx_ring->stats.packets;
5069 }
5070 adapter->non_eop_descs = non_eop_descs;
5071 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5072 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5073 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5074 netdev->stats.rx_bytes = bytes;
5075 netdev->stats.rx_packets = packets;
5076
5077 bytes = 0;
5078 packets = 0;
7ca3bc58 5079 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5080 for (i = 0; i < adapter->num_tx_queues; i++) {
5081 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5082 restart_queue += tx_ring->tx_stats.restart_queue;
5083 tx_busy += tx_ring->tx_stats.tx_busy;
5084 bytes += tx_ring->stats.bytes;
5085 packets += tx_ring->stats.packets;
5086 }
eb985f09 5087 adapter->restart_queue = restart_queue;
5b7da515
AD		 5088 adapter->tx_busy = tx_busy;
5089 netdev->stats.tx_bytes = bytes;
5090 netdev->stats.tx_packets = packets;
7ca3bc58 5091
7ca647bd 5092 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5093
5094 /* 8 register reads */
6f11eef7
AV		 5095 for (i = 0; i < 8; i++) {
5096 /* for packet buffers not used, the register should read 0 */
5097 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5098 missed_rx += mpc;
7ca647bd
JP		 5099 hwstats->mpc[i] += mpc;
5100 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5101 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5102 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5103 switch (hw->mac.type) {
5104 case ixgbe_mac_82598EB:
1a70db4b
ET		 5105 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5106 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5107 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5108 hwstats->pxonrxc[i] +=
5109 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5110 break;
5111 case ixgbe_mac_82599EB:
b93a2226 5112 case ixgbe_mac_X540:
bd508178
AD		 5113 hwstats->pxonrxc[i] +=
5114 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5115 break;
5116 default:
5117 break;
e8e26350 5118 }
6f11eef7 5119 }
1a70db4b
ET		 5120
5121 /*16 register reads */
5122 for (i = 0; i < 16; i++) {
5123 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5124 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5125 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5126 (hw->mac.type == ixgbe_mac_X540)) {
5127 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5128 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5129 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5130 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5131 }
5132 }
5133
7ca647bd 5134 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5135 /* work around hardware counting issue */
7ca647bd 5136 hwstats->gprc -= missed_rx;
6f11eef7 5137
c84d324c
JF		 5138 ixgbe_update_xoff_received(adapter);
5139
6f11eef7 5140 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5141 switch (hw->mac.type) {
5142 case ixgbe_mac_82598EB:
5143 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5144 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5145 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5146 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5147 break;
b93a2226 5148 case ixgbe_mac_X540:
58f6bcf9
ET		 5149 /* OS2BMC stats are X540 only*/
5150 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5151 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5152 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5153 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5154 case ixgbe_mac_82599EB:
a4d4f629
AD		 5155 for (i = 0; i < 16; i++)
5156 adapter->hw_rx_no_dma_resources +=
5157 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5158 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5159 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5160 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5161 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5162 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5163 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5164 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5165 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5166 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5167#ifdef IXGBE_FCOE
7ca647bd
JP		 5168 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5169 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5170 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5171 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5172 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5173 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5174 /* Add up per cpu counters for total ddp aloc fail */
5175 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5176 for_each_possible_cpu(cpu) {
5177 fcoe_noddp_counts_sum +=
5178 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5179 fcoe_noddp_ext_buff_counts_sum +=
5180 *per_cpu_ptr(fcoe->
5181 pcpu_noddp_ext_buff, cpu);
5182 }
5183 }
5184 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5185 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5186#endif /* IXGBE_FCOE */
bd508178
AD		 5187 break;
5188 default:
5189 break;
e8e26350 5190 }
9a799d71 5191 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5192 hwstats->bprc += bprc;
5193 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5194 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5195 hwstats->mprc -= bprc;
5196 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5197 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5198 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5199 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5200 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5201 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5202 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5203 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5204 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5205 hwstats->lxontxc += lxon;
6f11eef7 5206 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5207 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5208 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5209 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5210 /*
5211 * 82598 errata - tx of flow control packets is included in tx counters
5212 */
5213 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5214 hwstats->gptc -= xon_off_tot;
5215 hwstats->mptc -= xon_off_tot;
5216 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5217 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5218 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5219 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5220 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5221 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5222 hwstats->ptc64 -= xon_off_tot;
5223 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5224 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5225 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5226 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5227 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5228 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5229
5230 /* Fill out the OS statistics structure */
7ca647bd 5231 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5232
5233 /* Rx Errors */
7ca647bd 5234 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5235 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5236 netdev->stats.rx_length_errors = hwstats->rlec;
5237 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5238 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5239}
5240
5241/**
d034acf1
AD		 5242 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5243 * @adapter - pointer to the device adapter structure
9a799d71 5244 **/
d034acf1 5245static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5246{
cf8280ee 5247 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5248 int i;
cf8280ee 5249
d034acf1
AD		 5250 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5251 return;
5252
5253 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5254
d034acf1 5255 /* if interface is down do nothing */
fe49f04a 5256 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5257 return;
5258
5259 /* do nothing if we are not using signature filters */
5260 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5261 return;
5262
5263 adapter->fdir_overflow++;
5264
93c52dd0
AD		 5265 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5266 for (i = 0; i < adapter->num_tx_queues; i++)
5267 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5268 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5269 /* re-enable flow director interrupts */
5270 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5271 } else {
5272 e_err(probe, "failed to finish FDIR re-initialization, "
5273 "ignored adding FDIR ATR filters\n");
5274 }
93c52dd0
AD		 5275}
5276
5277/**
5278 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5279 * @adapter - pointer to the device adapter structure
5280 *
5281 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5282 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5283 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5284 * determine if a hang has occurred.
93c52dd0
AD		 5285 */
5286static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5287{
cf8280ee 5288 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5289 u64 eics = 0;
5290 int i;
cf8280ee 5291
93c52dd0
AD		 5292 /* If we're down or resetting, just bail */
5293 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5294 test_bit(__IXGBE_RESETTING, &adapter->state))
5295 return;
22d5a71b 5296
93c52dd0
AD		 5297 /* Force detection of hung controller */
5298 if (netif_carrier_ok(adapter->netdev)) {
5299 for (i = 0; i < adapter->num_tx_queues; i++)
5300 set_check_for_tx_hang(adapter->tx_ring[i]);
5301 }
22d5a71b 5302
fe49f04a
AD		 5303 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5304 /*
5305 * for legacy and MSI interrupts don't set any bits
5306 * that are enabled for EIAM, because this operation
5307 * would set *both* EIMS and EICS for any bit in EIAM
5308 */
5309 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5310 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5311 } else {
5312 /* get one bit for every active tx/rx interrupt vector */
5313 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5314 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5315 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5316 eics |= ((u64)1 << i);
5317 }
cf8280ee 5318 }
9a799d71 5319
93c52dd0 5320 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5321 ixgbe_irq_rearm_queues(adapter, eics);
5322
cf8280ee
JB		 5323}
5324
e8e26350 5325/**
93c52dd0
AD		 5326 * ixgbe_watchdog_update_link - update the link status
5327 * @adapter - pointer to the device adapter structure
5328 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5329 **/
93c52dd0 5330static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5331{
e8e26350 5332 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5333 u32 link_speed = adapter->link_speed;
5334 bool link_up = adapter->link_up;
041441d0 5335 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5336
93c52dd0
AD		 5337 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5338 return;
5339
5340 if (hw->mac.ops.check_link) {
5341 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5342 } else {
93c52dd0
AD		 5343 /* always assume link is up, if no check link function */
5344 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5345 link_up = true;
c4cf55e5 5346 }
041441d0
AD		 5347
5348 if (adapter->ixgbe_ieee_pfc)
5349 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5350
3ebe8fde 5351 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5352 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5353 ixgbe_set_rx_drop_en(adapter);
5354 }
93c52dd0
AD		 5355
5356 if (link_up ||
5357 time_after(jiffies, (adapter->link_check_timeout +
5358 IXGBE_TRY_LINK_TIMEOUT))) {
5359 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5360 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5361 IXGBE_WRITE_FLUSH(hw);
5362 }
5363
5364 adapter->link_up = link_up;
5365 adapter->link_speed = link_speed;
e8e26350
PW		 5366}
5367
5368/**
93c52dd0
AD		 5369 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5370 * print link up message
5371 * @adapter - pointer to the device adapter structure
e8e26350 5372 **/
93c52dd0 5373static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5374{
93c52dd0 5375 struct net_device *netdev = adapter->netdev;
e8e26350 5376 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5377 u32 link_speed = adapter->link_speed;
5378 bool flow_rx, flow_tx;
e8e26350 5379
93c52dd0
AD		 5380 /* only continue if link was previously down */
5381 if (netif_carrier_ok(netdev))
a985b6c3 5382 return;
63d6e1d8 5383
93c52dd0 5384 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5385
93c52dd0
AD		 5386 switch (hw->mac.type) {
5387 case ixgbe_mac_82598EB: {
5388 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5389 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5390 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5391 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5392 }
5393 break;
5394 case ixgbe_mac_X540:
5395 case ixgbe_mac_82599EB: {
5396 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5397 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5398 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5399 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5400 }
5401 break;
5402 default:
5403 flow_tx = false;
5404 flow_rx = false;
5405 break;
e8e26350 5406 }
3a6a4eda
JK		 5407
5408#ifdef CONFIG_IXGBE_PTP
5409 ixgbe_ptp_start_cyclecounter(adapter);
5410#endif
5411
93c52dd0
AD		 5412 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5413 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5414 "10 Gbps" :
5415 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5416 "1 Gbps" :
5417 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5418 "100 Mbps" :
5419 "unknown speed"))),
5420 ((flow_rx && flow_tx) ? "RX/TX" :
5421 (flow_rx ? "RX" :
5422 (flow_tx ? "TX" : "None"))));
e8e26350 5423
93c52dd0 5424 netif_carrier_on(netdev);
93c52dd0 5425 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5426}
5427
c4cf55e5 5428/**
93c52dd0
AD		 5429 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5430 * print link down message
5431 * @adapter - pointer to the adapter structure
c4cf55e5 5432 **/
581330ba 5433static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5434{
cf8280ee 5435 struct net_device *netdev = adapter->netdev;
c4cf55e5 5436 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5437
93c52dd0
AD		 5438 adapter->link_up = false;
5439 adapter->link_speed = 0;
cf8280ee 5440
93c52dd0
AD		 5441 /* only continue if link was up previously */
5442 if (!netif_carrier_ok(netdev))
5443 return;
264857b8 5444
93c52dd0
AD		 5445 /* poll for SFP+ cable when link is down */
5446 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5447 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5448
3a6a4eda
JK		 5449#ifdef CONFIG_IXGBE_PTP
5450 ixgbe_ptp_start_cyclecounter(adapter);
5451#endif
5452
93c52dd0
AD		 5453 e_info(drv, "NIC Link is Down\n");
5454 netif_carrier_off(netdev);
5455}
e8e26350 5456
93c52dd0
AD		 5457/**
5458 * ixgbe_watchdog_flush_tx - flush queues on link down
5459 * @adapter - pointer to the device adapter structure
5460 **/
5461static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5462{
c4cf55e5 5463 int i;
93c52dd0 5464 int some_tx_pending = 0;
c4cf55e5 5465
93c52dd0 5466 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5467 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5468 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5469 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5470 some_tx_pending = 1;
5471 break;
5472 }
5473 }
5474
5475 if (some_tx_pending) {
5476 /* We've lost link, so the controller stops DMA,
5477 * but we've got queued Tx work that's never going
5478 * to get done, so reset controller to flush Tx.
5479 * (Do the reset outside of interrupt context).
5480 */
c83c6cbd 5481 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5482 }
c4cf55e5 5483 }
c4cf55e5
PWJ		 5484}
5485
a985b6c3
GR		 5486static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5487{
5488 u32 ssvpc;
5489
5490 /* Do not perform spoof check for 82598 */
5491 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5492 return;
5493
5494 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5495
5496 /*
5497 * ssvpc register is cleared on read, if zero then no
5498 * spoofed packets in the last interval.
5499 */
5500 if (!ssvpc)
5501 return;
5502
5503 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5504}
5505
93c52dd0
AD		 5506/**
5507 * ixgbe_watchdog_subtask - check and bring link up
5508 * @adapter - pointer to the device adapter structure
5509 **/
5510static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5511{
5512 /* if interface is down do nothing */
7edebf9a
ET		 5513 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5514 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5515 return;
5516
5517 ixgbe_watchdog_update_link(adapter);
5518
5519 if (adapter->link_up)
5520 ixgbe_watchdog_link_is_up(adapter);
5521 else
5522 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5523
a985b6c3 5524 ixgbe_spoof_check(adapter);
9a799d71 5525 ixgbe_update_stats(adapter);
93c52dd0
AD		 5526
5527 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5528}
10eec955 5529
cf8280ee 5530/**
7086400d
AD		 5531 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5532 * @adapter - the ixgbe adapter structure
cf8280ee 5533 **/
7086400d 5534static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5535{
cf8280ee 5536 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5537 s32 err;
cf8280ee 5538
7086400d
AD		 5539 /* not searching for SFP so there is nothing to do here */
5540 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5541 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5542 return;
10eec955 5543
7086400d
AD		 5544 /* someone else is in init, wait until next service event */
5545 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5546 return;
cf8280ee 5547
7086400d
AD		 5548 err = hw->phy.ops.identify_sfp(hw);
5549 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5550 goto sfp_out;
264857b8 5551
7086400d
AD		 5552 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5553 /* If no cable is present, then we need to reset
5554 * the next time we find a good cable. */
5555 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5556 }
9a799d71 5557
7086400d
AD		 5558 /* exit on error */
5559 if (err)
5560 goto sfp_out;
e8e26350 5561
7086400d
AD		 5562 /* exit if reset not needed */
5563 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5564 goto sfp_out;
9a799d71 5565
7086400d 5566 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5567
7086400d
AD		 5568 /*
5569 * A module may be identified correctly, but the EEPROM may not have
5570 * support for that module. setup_sfp() will fail in that case, so
5571 * we should not allow that module to load.
5572 */
5573 if (hw->mac.type == ixgbe_mac_82598EB)
5574 err = hw->phy.ops.reset(hw);
5575 else
5576 err = hw->mac.ops.setup_sfp(hw);
5577
5578 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5579 goto sfp_out;
5580
5581 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5582 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5583
5584sfp_out:
5585 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5586
5587 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5588 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5589 e_dev_err("failed to initialize because an unsupported "
5590 "SFP+ module type was detected.\n");
5591 e_dev_err("Reload the driver after installing a "
5592 "supported module.\n");
5593 unregister_netdev(adapter->netdev);
bc59fcda 5594 }
7086400d 5595}
bc59fcda 5596
7086400d
AD		 5597/**
5598 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5599 * @adapter - the ixgbe adapter structure
5600 **/
5601static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5602{
5603 struct ixgbe_hw *hw = &adapter->hw;
5604 u32 autoneg;
5605 bool negotiation;
5606
5607 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5608 return;
5609
5610 /* someone else is in init, wait until next service event */
5611 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5612 return;
5613
5614 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5615
5616 autoneg = hw->phy.autoneg_advertised;
5617 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5618 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5619 if (hw->mac.ops.setup_link)
5620 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5621
5622 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5623 adapter->link_check_timeout = jiffies;
5624 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5625}
5626
83c61fa9
GR		 5627#ifdef CONFIG_PCI_IOV
5628static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5629{
5630 int vf;
5631 struct ixgbe_hw *hw = &adapter->hw;
5632 struct net_device *netdev = adapter->netdev;
5633 u32 gpc;
5634 u32 ciaa, ciad;
5635
5636 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5637 if (gpc) /* If incrementing then no need for the check below */
5638 return;
5639 /*
5640 * Check to see if a bad DMA write target from an errant or
5641 * malicious VF has caused a PCIe error. If so then we can
5642 * issue a VFLR to the offending VF(s) and then resume without
5643 * requesting a full slot reset.
5644 */
5645
5646 for (vf = 0; vf < adapter->num_vfs; vf++) {
5647 ciaa = (vf << 16) | 0x80000000;
5648 /* 32 bit read so align, we really want status at offset 6 */
5649 ciaa |= PCI_COMMAND;
5650 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5651 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5652 ciaa &= 0x7FFFFFFF;
5653 /* disable debug mode asap after reading data */
5654 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5655 /* Get the upper 16 bits which will be the PCI status reg */
5656 ciad >>= 16;
5657 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5658 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5659 /* Issue VFLR */
5660 ciaa = (vf << 16) | 0x80000000;
5661 ciaa |= 0xA8;
5662 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5663 ciad = 0x00008000; /* VFLR */
5664 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5665 ciaa &= 0x7FFFFFFF;
5666 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5667 }
5668 }
5669}
5670
5671#endif
7086400d
AD		 5672/**
5673 * ixgbe_service_timer - Timer Call-back
5674 * @data: pointer to adapter cast into an unsigned long
5675 **/
5676static void ixgbe_service_timer(unsigned long data)
5677{
5678 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5679 unsigned long next_event_offset;
83c61fa9 5680 bool ready = true;
7086400d 5681
6bb78cfb
AD		 5682 /* poll faster when waiting for link */
5683 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5684 next_event_offset = HZ / 10;
5685 else
5686 next_event_offset = HZ * 2;
83c61fa9 5687
6bb78cfb 5688#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5689 /*
5690 * don't bother with SR-IOV VF DMA hang check if there are
5691 * no VFs or the link is down
5692 */
5693 if (!adapter->num_vfs ||
6bb78cfb 5694 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5695 goto normal_timer_service;
83c61fa9
GR		 5696
5697 /* If we have VFs allocated then we must check for DMA hangs */
5698 ixgbe_check_for_bad_vf(adapter);
5699 next_event_offset = HZ / 50;
5700 adapter->timer_event_accumulator++;
5701
6bb78cfb 5702 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5703 adapter->timer_event_accumulator = 0;
7086400d 5704 else
6bb78cfb 5705 ready = false;
7086400d 5706
6bb78cfb 5707normal_timer_service:
83c61fa9 5708#endif
7086400d
AD		 5709 /* Reset the timer */
5710 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5711
83c61fa9
GR		 5712 if (ready)
5713 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5714}
5715
c83c6cbd
AD		 5716static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5717{
5718 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5719 return;
5720
5721 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5722
5723 /* If we're already down or resetting, just bail */
5724 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5725 test_bit(__IXGBE_RESETTING, &adapter->state))
5726 return;
5727
5728 ixgbe_dump(adapter);
5729 netdev_err(adapter->netdev, "Reset adapter\n");
5730 adapter->tx_timeout_count++;
5731
5732 ixgbe_reinit_locked(adapter);
5733}
5734
7086400d
AD		 5735/**
5736 * ixgbe_service_task - manages and runs subtasks
5737 * @work: pointer to work_struct containing our data
5738 **/
5739static void ixgbe_service_task(struct work_struct *work)
5740{
5741 struct ixgbe_adapter *adapter = container_of(work,
5742 struct ixgbe_adapter,
5743 service_task);
5744
c83c6cbd 5745 ixgbe_reset_subtask(adapter);
7086400d
AD		 5746 ixgbe_sfp_detection_subtask(adapter);
5747 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5748 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5749 ixgbe_watchdog_subtask(adapter);
d034acf1 5750 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5751 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5752#ifdef CONFIG_IXGBE_PTP
5753 ixgbe_ptp_overflow_check(adapter);
5754#endif
7086400d
AD		 5755
5756 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5757}
5758
fd0db0ed
AD		 5759static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5760 struct ixgbe_tx_buffer *first,
244e27ad 5761 u8 *hdr_len)
897ab156 5762{
fd0db0ed 5763 struct sk_buff *skb = first->skb;
897ab156
AD		 5764 u32 vlan_macip_lens, type_tucmd;
5765 u32 mss_l4len_idx, l4len;
9a799d71 5766
897ab156
AD		 5767 if (!skb_is_gso(skb))
5768 return 0;
9a799d71 5769
897ab156 5770 if (skb_header_cloned(skb)) {
244e27ad 5771 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5772 if (err)
5773 return err;
9a799d71 5774 }
9a799d71 5775
897ab156
AD		 5776 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5777 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5778
244e27ad 5779 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5780 struct iphdr *iph = ip_hdr(skb);
5781 iph->tot_len = 0;
5782 iph->check = 0;
5783 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5784 iph->daddr, 0,
5785 IPPROTO_TCP,
5786 0);
5787 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5788 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5789 IXGBE_TX_FLAGS_CSUM |
5790 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5791 } else if (skb_is_gso_v6(skb)) {
5792 ipv6_hdr(skb)->payload_len = 0;
5793 tcp_hdr(skb)->check =
5794 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5795 &ipv6_hdr(skb)->daddr,
5796 0, IPPROTO_TCP, 0);
244e27ad
AD		 5797 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5798 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5799 }
5800
091a6246 5801 /* compute header lengths */
897ab156
AD		 5802 l4len = tcp_hdrlen(skb);
5803 *hdr_len = skb_transport_offset(skb) + l4len;
5804
091a6246
AD		 5805 /* update gso size and bytecount with header size */
5806 first->gso_segs = skb_shinfo(skb)->gso_segs;
5807 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5808
897ab156
AD		 5809 /* mss_l4len_id: use 1 as index for TSO */
5810 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5811 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5812 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5813
5814 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5815 vlan_macip_lens = skb_network_header_len(skb);
5816 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5817 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5818
5819 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5820 mss_l4len_idx);
897ab156
AD		 5821
5822 return 1;
5823}
5824
244e27ad
AD		 5825static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5826 struct ixgbe_tx_buffer *first)
7ca647bd 5827{
fd0db0ed 5828 struct sk_buff *skb = first->skb;
897ab156
AD		 5829 u32 vlan_macip_lens = 0;
5830 u32 mss_l4len_idx = 0;
5831 u32 type_tucmd = 0;
7ca647bd 5832
897ab156 5833 if (skb->ip_summed != CHECKSUM_PARTIAL) {
244e27ad
AD		 5834 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5835 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5836 return;
897ab156
AD		 5837 } else {
5838 u8 l4_hdr = 0;
244e27ad 5839 switch (first->protocol) {
897ab156
AD		 5840 case __constant_htons(ETH_P_IP):
5841 vlan_macip_lens |= skb_network_header_len(skb);
5842 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5843 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5844 break;
897ab156
AD		 5845 case __constant_htons(ETH_P_IPV6):
5846 vlan_macip_lens |= skb_network_header_len(skb);
5847 l4_hdr = ipv6_hdr(skb)->nexthdr;
5848 break;
5849 default:
5850 if (unlikely(net_ratelimit())) {
5851 dev_warn(tx_ring->dev,
5852 "partial checksum but proto=%x!\n",
244e27ad 5853 first->protocol);
897ab156 5854 }
7ca647bd
JP		 5855 break;
5856 }
897ab156
AD		 5857
5858 switch (l4_hdr) {
7ca647bd 5859 case IPPROTO_TCP:
897ab156
AD		 5860 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5861 mss_l4len_idx = tcp_hdrlen(skb) <<
5862 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5863 break;
5864 case IPPROTO_SCTP:
897ab156
AD		 5865 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5866 mss_l4len_idx = sizeof(struct sctphdr) <<
5867 IXGBE_ADVTXD_L4LEN_SHIFT;
5868 break;
5869 case IPPROTO_UDP:
5870 mss_l4len_idx = sizeof(struct udphdr) <<
5871 IXGBE_ADVTXD_L4LEN_SHIFT;
5872 break;
5873 default:
5874 if (unlikely(net_ratelimit())) {
5875 dev_warn(tx_ring->dev,
5876 "partial checksum but l4 proto=%x!\n",
244e27ad 5877 l4_hdr);
897ab156 5878 }
7ca647bd
JP		 5879 break;
5880 }
244e27ad
AD		 5881
5882 /* update TX checksum flag */
5883 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 5884 }
5885
244e27ad 5886 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 5887 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5888 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 5889
897ab156
AD		 5890 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5891 type_tucmd, mss_l4len_idx);
9a799d71
AK		 5892}
5893
d3d00239 5894static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 5895{
d3d00239
AD		 5896 /* set type for advanced descriptor with frame checksum insertion */
5897 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5898 IXGBE_ADVTXD_DCMD_IFCS |
5899 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 5900
d3d00239 5901 /* set HW vlan bit if vlan is present */
66f32a8b 5902 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 5903 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 5904
3a6a4eda
JK		 5905#ifdef CONFIG_IXGBE_PTP
5906 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5907 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5908#endif
5909
d3d00239
AD		 5910 /* set segmentation enable bits for TSO/FSO */
5911#ifdef IXGBE_FCOE
93f5b3c1 5912 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 5913#else
5914 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5915#endif
5916 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 5917
d3d00239
AD		 5918 return cmd_type;
5919}
9a799d71 5920
729739b7
AD		 5921static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5922 u32 tx_flags, unsigned int paylen)
d3d00239 5923{
93f5b3c1 5924 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 5925
d3d00239
AD		 5926 /* enable L4 checksum for TSO and TX checksum offload */
5927 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5928 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 5929
93f5b3c1
AD		 5930 /* enble IPv4 checksum for TSO */
5931 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5932 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 5933
93f5b3c1
AD		 5934 /* use index 1 context for TSO/FSO/FCOE */
5935#ifdef IXGBE_FCOE
5936 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5937#else
5938 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 5939#endif
93f5b3c1
AD		 5940 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5941
7f9643fd
AD		 5942 /*
5943 * Check Context must be set if Tx switch is enabled, which it
5944 * always is for case where virtual functions are running
5945 */
93f5b3c1
AD		 5946#ifdef IXGBE_FCOE
5947 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5948#else
7f9643fd 5949 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 5950#endif
7f9643fd
AD		 5951 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5952
729739b7 5953 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 5954}
44df32c5 5955
d3d00239
AD		 5956#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5957 IXGBE_TXD_CMD_RS)
5958
5959static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 5960 struct ixgbe_tx_buffer *first,
d3d00239
AD		 5961 const u8 hdr_len)
5962{
729739b7 5963 dma_addr_t dma;
fd0db0ed 5964 struct sk_buff *skb = first->skb;
729739b7 5965 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 5966 union ixgbe_adv_tx_desc *tx_desc;
729739b7 5967 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 5968 unsigned int data_len = skb->data_len;
5969 unsigned int size = skb_headlen(skb);
729739b7 5970 unsigned int paylen = skb->len - hdr_len;
244e27ad 5971 u32 tx_flags = first->tx_flags;
729739b7 5972 __le32 cmd_type;
d3d00239 5973 u16 i = tx_ring->next_to_use;
d3d00239 5974
729739b7
AD		 5975 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5976
5977 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5978 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5979
d3d00239
AD		 5980#ifdef IXGBE_FCOE
5981 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 5982 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 5983 size -= sizeof(struct fcoe_crc_eof) - data_len;
5984 data_len = 0;
729739b7
AD		 5985 } else {
5986 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 5987 }
5988 }
44df32c5 5989
d3d00239 5990#endif
729739b7
AD		 5991 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5992 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 5993 goto dma_error;
8ad494b0 5994
729739b7
AD		 5995 /* record length, and DMA address */
5996 dma_unmap_len_set(first, len, size);
5997 dma_unmap_addr_set(first, dma, dma);
9a799d71 5998
729739b7 5999 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6000
d3d00239 6001 for (;;) {
729739b7 6002 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6003 tx_desc->read.cmd_type_len =
6004 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6005
d3d00239 6006 i++;
729739b7 6007 tx_desc++;
d3d00239 6008 if (i == tx_ring->count) {
e4f74028 6009 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6010 i = 0;
6011 }
729739b7
AD		 6012
6013 dma += IXGBE_MAX_DATA_PER_TXD;
6014 size -= IXGBE_MAX_DATA_PER_TXD;
6015
6016 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6017 tx_desc->read.olinfo_status = 0;
d3d00239 6018 }
e5a43549 6019
729739b7
AD		 6020 if (likely(!data_len))
6021 break;
9a799d71 6022
f43f313e
BG		 6023 if (unlikely(skb->no_fcs))
6024 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239 6025 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6026
729739b7
AD		 6027 i++;
6028 tx_desc++;
6029 if (i == tx_ring->count) {
6030 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6031 i = 0;
6032 }
9a799d71 6033
d3d00239 6034#ifdef IXGBE_FCOE
9e903e08 6035 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6036#else
9e903e08 6037 size = skb_frag_size(frag);
d3d00239
AD		 6038#endif
6039 data_len -= size;
9a799d71 6040
729739b7
AD		 6041 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6042 DMA_TO_DEVICE);
6043 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6044 goto dma_error;
9a799d71 6045
729739b7
AD		 6046 tx_buffer = &tx_ring->tx_buffer_info[i];
6047 dma_unmap_len_set(tx_buffer, len, size);
6048 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6049
729739b7
AD		 6050 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6051 tx_desc->read.olinfo_status = 0;
9a799d71 6052
729739b7
AD		 6053 frag++;
6054 }
9a799d71 6055
729739b7
AD		 6056 /* write last descriptor with RS and EOP bits */
6057 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6058 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6059
091a6246 6060 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6061
d3d00239
AD		 6062 /* set the timestamp */
6063 first->time_stamp = jiffies;
9a799d71
AK		 6064
6065 /*
729739b7
AD		 6066 * Force memory writes to complete before letting h/w know there
6067 * are new descriptors to fetch. (Only applicable for weak-ordered
6068 * memory model archs, such as IA-64).
6069 *
6070 * We also need this memory barrier to make certain all of the
6071 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6072 */
6073 wmb();
6074
d3d00239
AD		 6075 /* set next_to_watch value indicating a packet is present */
6076 first->next_to_watch = tx_desc;
6077
729739b7
AD		 6078 i++;
6079 if (i == tx_ring->count)
6080 i = 0;
6081
6082 tx_ring->next_to_use = i;
6083
d3d00239 6084 /* notify HW of packet */
84ea2591 6085 writel(i, tx_ring->tail);
d3d00239
AD		 6086
6087 return;
6088dma_error:
729739b7 6089 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6090
6091 /* clear dma mappings for failed tx_buffer_info map */
6092 for (;;) {
729739b7
AD		 6093 tx_buffer = &tx_ring->tx_buffer_info[i];
6094 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6095 if (tx_buffer == first)
d3d00239
AD		 6096 break;
6097 if (i == 0)
6098 i = tx_ring->count;
6099 i--;
6100 }
6101
d3d00239 6102 tx_ring->next_to_use = i;
9a799d71
AK		 6103}
6104
fd0db0ed 6105static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6106 struct ixgbe_tx_buffer *first)
69830529
AD		 6107{
6108 struct ixgbe_q_vector *q_vector = ring->q_vector;
6109 union ixgbe_atr_hash_dword input = { .dword = 0 };
6110 union ixgbe_atr_hash_dword common = { .dword = 0 };
6111 union {
6112 unsigned char *network;
6113 struct iphdr *ipv4;
6114 struct ipv6hdr *ipv6;
6115 } hdr;
ee9e0f0b 6116 struct tcphdr *th;
905e4a41 6117 __be16 vlan_id;
c4cf55e5 6118
69830529
AD		 6119 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6120 if (!q_vector)
6121 return;
6122
6123 /* do nothing if sampling is disabled */
6124 if (!ring->atr_sample_rate)
d3ead241 6125 return;
c4cf55e5 6126
69830529 6127 ring->atr_count++;
c4cf55e5 6128
69830529 6129 /* snag network header to get L4 type and address */
fd0db0ed 6130 hdr.network = skb_network_header(first->skb);
69830529
AD		 6131
6132 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6133 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6134 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6135 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6136 hdr.ipv4->protocol != IPPROTO_TCP))
6137 return;
ee9e0f0b 6138
fd0db0ed 6139 th = tcp_hdr(first->skb);
c4cf55e5 6140
66f32a8b
AD		 6141 /* skip this packet since it is invalid or the socket is closing */
6142 if (!th || th->fin)
69830529
AD		 6143 return;
6144
6145 /* sample on all syn packets or once every atr sample count */
6146 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6147 return;
6148
6149 /* reset sample count */
6150 ring->atr_count = 0;
6151
244e27ad 6152 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6153
6154 /*
6155 * src and dst are inverted, think how the receiver sees them
6156 *
6157 * The input is broken into two sections, a non-compressed section
6158 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6159 * is XORed together and stored in the compressed dword.
6160 */
6161 input.formatted.vlan_id = vlan_id;
6162
6163 /*
6164 * since src port and flex bytes occupy the same word XOR them together
6165 * and write the value to source port portion of compressed dword
6166 */
244e27ad 6167 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6168 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6169 else
244e27ad 6170 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6171 common.port.dst ^= th->source;
6172
244e27ad 6173 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6174 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6175 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6176 } else {
6177 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6178 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6179 hdr.ipv6->saddr.s6_addr32[1] ^
6180 hdr.ipv6->saddr.s6_addr32[2] ^
6181 hdr.ipv6->saddr.s6_addr32[3] ^
6182 hdr.ipv6->daddr.s6_addr32[0] ^
6183 hdr.ipv6->daddr.s6_addr32[1] ^
6184 hdr.ipv6->daddr.s6_addr32[2] ^
6185 hdr.ipv6->daddr.s6_addr32[3];
6186 }
c4cf55e5
PWJ		 6187
6188 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6189 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6190 input, common, ring->queue_index);
c4cf55e5
PWJ		 6191}
6192
63544e9c 6193static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6194{
fc77dc3c 6195 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6196 /* Herbert's original patch had:
6197 * smp_mb__after_netif_stop_queue();
6198 * but since that doesn't exist yet, just open code it. */
6199 smp_mb();
6200
6201 /* We need to check again in a case another CPU has just
6202 * made room available. */
7d4987de 6203 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6204 return -EBUSY;
6205
6206 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6207 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6208 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6209 return 0;
6210}
6211
82d4e46e 6212static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6213{
7d4987de 6214 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6215 return 0;
fc77dc3c 6216 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6217}
6218
09a3b1f8
SH		 6219static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6220{
6221 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6222 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6223 smp_processor_id();
56075a98 6224#ifdef IXGBE_FCOE
6440752c 6225 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6226
e5b64635
JF		 6227 if (((protocol == htons(ETH_P_FCOE)) ||
6228 (protocol == htons(ETH_P_FIP))) &&
6229 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6230 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6231 txq += adapter->ring_feature[RING_F_FCOE].mask;
6232 return txq;
56075a98
JF		 6233 }
6234#endif
6235
fdd3d631
KK		 6236 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6237 while (unlikely(txq >= dev->real_num_tx_queues))
6238 txq -= dev->real_num_tx_queues;
5f715823 6239 return txq;
fdd3d631 6240 }
c4cf55e5 6241
09a3b1f8
SH		 6242 return skb_tx_hash(dev, skb);
6243}
6244
fc77dc3c 6245netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6246 struct ixgbe_adapter *adapter,
6247 struct ixgbe_ring *tx_ring)
9a799d71 6248{
d3d00239 6249 struct ixgbe_tx_buffer *first;
5f715823 6250 int tso;
d3d00239 6251 u32 tx_flags = 0;
a535c30e
AD		 6252#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6253 unsigned short f;
6254#endif
a535c30e 6255 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6256 __be16 protocol = skb->protocol;
63544e9c 6257 u8 hdr_len = 0;
5e09a105 6258
a535c30e
AD		 6259 /*
6260 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6261 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6262 * + 2 desc gap to keep tail from touching head,
6263 * + 1 desc for context descriptor,
6264 * otherwise try next time
6265 */
6266#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6267 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6268 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6269#else
6270 count += skb_shinfo(skb)->nr_frags;
6271#endif
6272 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6273 tx_ring->tx_stats.tx_busy++;
6274 return NETDEV_TX_BUSY;
6275 }
6276
fd0db0ed
AD		 6277 /* record the location of the first descriptor for this packet */
6278 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6279 first->skb = skb;
091a6246
AD		 6280 first->bytecount = skb->len;
6281 first->gso_segs = 1;
fd0db0ed 6282
66f32a8b 6283 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6284 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6285 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6286 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6287 /* else if it is a SW VLAN check the next protocol and store the tag */
6288 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6289 struct vlan_hdr *vhdr, _vhdr;
6290 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6291 if (!vhdr)
6292 goto out_drop;
6293
6294 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6295 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6296 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6297 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6298 }
6299
aa7bd467
JK		 6300 skb_tx_timestamp(skb);
6301
3a6a4eda
JK		 6302#ifdef CONFIG_IXGBE_PTP
6303 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6304 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6305 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6306 }
6307#endif
6308
9e0c5648
AD		 6309#ifdef CONFIG_PCI_IOV
6310 /*
6311 * Use the l2switch_enable flag - would be false if the DMA
6312 * Tx switch had been disabled.
6313 */
6314 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6315 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6316
6317#endif
32701dc2 6318 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6319 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6320 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6321 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6322 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6323 tx_flags |= (skb->priority & 0x7) <<
6324 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6325 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6326 struct vlan_ethhdr *vhdr;
6327 if (skb_header_cloned(skb) &&
6328 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6329 goto out_drop;
6330 vhdr = (struct vlan_ethhdr *)skb->data;
6331 vhdr->h_vlan_TCI = htons(tx_flags >>
6332 IXGBE_TX_FLAGS_VLAN_SHIFT);
6333 } else {
6334 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6335 }
9a799d71 6336 }
eacd73f7 6337
244e27ad
AD		 6338 /* record initial flags and protocol */
6339 first->tx_flags = tx_flags;
6340 first->protocol = protocol;
6341
eacd73f7 6342#ifdef IXGBE_FCOE
66f32a8b
AD		 6343 /* setup tx offload for FCoE */
6344 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6345 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
244e27ad 6346 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6347 if (tso < 0)
6348 goto out_drop;
9a799d71 6349
66f32a8b 6350 goto xmit_fcoe;
eacd73f7 6351 }
9a799d71 6352
66f32a8b 6353#endif /* IXGBE_FCOE */
244e27ad 6354 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6355 if (tso < 0)
897ab156 6356 goto out_drop;
244e27ad
AD		 6357 else if (!tso)
6358 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6359
6360 /* add the ATR filter if ATR is on */
6361 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6362 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6363
6364#ifdef IXGBE_FCOE
6365xmit_fcoe:
6366#endif /* IXGBE_FCOE */
244e27ad 6367 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6368
6369 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6370
6371 return NETDEV_TX_OK;
897ab156
AD		 6372
6373out_drop:
fd0db0ed
AD		 6374 dev_kfree_skb_any(first->skb);
6375 first->skb = NULL;
6376
897ab156 6377 return NETDEV_TX_OK;
9a799d71
AK		 6378}
6379
a50c29dd
AD		 6380static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6381 struct net_device *netdev)
84418e3b
AD		 6382{
6383 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6384 struct ixgbe_ring *tx_ring;
6385
a50c29dd
AD		 6386 if (skb->len <= 0) {
6387 dev_kfree_skb_any(skb);
6388 return NETDEV_TX_OK;
6389 }
6390
6391 /*
6392 * The minimum packet size for olinfo paylen is 17 so pad the skb
6393 * in order to meet this minimum size requirement.
6394 */
6395 if (skb->len < 17) {
6396 if (skb_padto(skb, 17))
6397 return NETDEV_TX_OK;
6398 skb->len = 17;
6399 }
6400
84418e3b 6401 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6402 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6403}
6404
9a799d71
AK		 6405/**
6406 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6407 * @netdev: network interface device structure
6408 * @p: pointer to an address structure
6409 *
6410 * Returns 0 on success, negative on failure
6411 **/
6412static int ixgbe_set_mac(struct net_device *netdev, void *p)
6413{
6414 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6415 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6416 struct sockaddr *addr = p;
6417
6418 if (!is_valid_ether_addr(addr->sa_data))
6419 return -EADDRNOTAVAIL;
6420
6421 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6422 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6423
1cdd1ec8
GR		 6424 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6425 IXGBE_RAH_AV);
9a799d71
AK		 6426
6427 return 0;
6428}
6429
6b73e10d
BH		 6430static int
6431ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6432{
6433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6434 struct ixgbe_hw *hw = &adapter->hw;
6435 u16 value;
6436 int rc;
6437
6438 if (prtad != hw->phy.mdio.prtad)
6439 return -EINVAL;
6440 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6441 if (!rc)
6442 rc = value;
6443 return rc;
6444}
6445
6446static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6447 u16 addr, u16 value)
6448{
6449 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6450 struct ixgbe_hw *hw = &adapter->hw;
6451
6452 if (prtad != hw->phy.mdio.prtad)
6453 return -EINVAL;
6454 return hw->phy.ops.write_reg(hw, addr, devad, value);
6455}
6456
6457static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6458{
6459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6460
3a6a4eda
JK		 6461 switch (cmd) {
6462#ifdef CONFIG_IXGBE_PTP
6463 case SIOCSHWTSTAMP:
6464 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6465#endif
6466 default:
6467 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6468 }
6b73e10d
BH		 6469}
6470
0365e6e4
PW		 6471/**
6472 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6473 * netdev->dev_addrs
0365e6e4
PW		 6474 * @netdev: network interface device structure
6475 *
6476 * Returns non-zero on failure
6477 **/
6478static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6479{
6480 int err = 0;
6481 struct ixgbe_adapter *adapter = netdev_priv(dev);
6482 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6483
6484 if (is_valid_ether_addr(mac->san_addr)) {
6485 rtnl_lock();
6486 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6487 rtnl_unlock();
6488 }
6489 return err;
6490}
6491
6492/**
6493 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6494 * netdev->dev_addrs
0365e6e4
PW		 6495 * @netdev: network interface device structure
6496 *
6497 * Returns non-zero on failure
6498 **/
6499static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6500{
6501 int err = 0;
6502 struct ixgbe_adapter *adapter = netdev_priv(dev);
6503 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6504
6505 if (is_valid_ether_addr(mac->san_addr)) {
6506 rtnl_lock();
6507 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6508 rtnl_unlock();
6509 }
6510 return err;
6511}
6512
9a799d71
AK		 6513#ifdef CONFIG_NET_POLL_CONTROLLER
6514/*
6515 * Polling 'interrupt' - used by things like netconsole to send skbs
6516 * without having to re-enable interrupts. It's not called while
6517 * the interrupt routine is executing.
6518 */
6519static void ixgbe_netpoll(struct net_device *netdev)
6520{
6521 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6522 int i;
9a799d71 6523
1a647bd2
AD		 6524 /* if interface is down do nothing */
6525 if (test_bit(__IXGBE_DOWN, &adapter->state))
6526 return;
6527
9a799d71 6528 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 6529 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6530 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6531 for (i = 0; i < num_q_vectors; i++) {
6532 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 6533 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 6534 }
6535 } else {
6536 ixgbe_intr(adapter->pdev->irq, netdev);
6537 }
9a799d71 6538 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6539}
9a799d71 6540
581330ba 6541#endif
de1036b1
ED		 6542static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6543 struct rtnl_link_stats64 *stats)
6544{
6545 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6546 int i;
6547
1a51502b 6548 rcu_read_lock();
de1036b1 6549 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6550 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6551 u64 bytes, packets;
6552 unsigned int start;
6553
1a51502b
ED		 6554 if (ring) {
6555 do {
6556 start = u64_stats_fetch_begin_bh(&ring->syncp);
6557 packets = ring->stats.packets;
6558 bytes = ring->stats.bytes;
6559 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6560 stats->rx_packets += packets;
6561 stats->rx_bytes += bytes;
6562 }
de1036b1 6563 }
1ac9ad13
ED		 6564
6565 for (i = 0; i < adapter->num_tx_queues; i++) {
6566 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6567 u64 bytes, packets;
6568 unsigned int start;
6569
6570 if (ring) {
6571 do {
6572 start = u64_stats_fetch_begin_bh(&ring->syncp);
6573 packets = ring->stats.packets;
6574 bytes = ring->stats.bytes;
6575 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6576 stats->tx_packets += packets;
6577 stats->tx_bytes += bytes;
6578 }
6579 }
1a51502b 6580 rcu_read_unlock();
de1036b1
ED		 6581 /* following stats updated by ixgbe_watchdog_task() */
6582 stats->multicast = netdev->stats.multicast;
6583 stats->rx_errors = netdev->stats.rx_errors;
6584 stats->rx_length_errors = netdev->stats.rx_length_errors;
6585 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6586 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6587 return stats;
6588}
6589
8af3c33f 6590#ifdef CONFIG_IXGBE_DCB
8b1c0b24
JF		 6591/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6592 * #adapter: pointer to ixgbe_adapter
6593 * @tc: number of traffic classes currently enabled
6594 *
6595 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6596 * 802.1Q priority maps to a packet buffer that exists.
6597 */
6598static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6599{
6600 struct ixgbe_hw *hw = &adapter->hw;
6601 u32 reg, rsave;
6602 int i;
6603
6604 /* 82598 have a static priority to TC mapping that can not
6605 * be changed so no validation is needed.
6606 */
6607 if (hw->mac.type == ixgbe_mac_82598EB)
6608 return;
6609
6610 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6611 rsave = reg;
6612
6613 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6614 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6615
6616 /* If up2tc is out of bounds default to zero */
6617 if (up2tc > tc)
6618 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6619 }
6620
6621 if (reg != rsave)
6622 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6623
6624 return;
6625}
6626
8b1c0b24
JF		 6627/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6628 * classes.
6629 *
6630 * @netdev: net device to configure
6631 * @tc: number of traffic classes to enable
6632 */
6633int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6634{
8b1c0b24
JF		 6635 struct ixgbe_adapter *adapter = netdev_priv(dev);
6636 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6637
e7589eab
JF		 6638 /* Multiple traffic classes requires multiple queues */
6639 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6640 e_err(drv, "Enable failed, needs MSI-X\n");
6641 return -EINVAL;
6642 }
8b1c0b24
JF		 6643
6644 /* Hardware supports up to 8 traffic classes */
4de2a022 6645 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6646 (hw->mac.type == ixgbe_mac_82598EB &&
6647 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6648 return -EINVAL;
6649
6650 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6651 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6652 * hardware is not flexible enough to do this dynamically.
6653 */
6654 if (netif_running(dev))
6655 ixgbe_close(dev);
6656 ixgbe_clear_interrupt_scheme(adapter);
6657
e7589eab 6658 if (tc) {
8b1c0b24 6659 netdev_set_num_tc(dev, tc);
e7589eab
JF		 6660 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6661 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6662
943561d3
AD		 6663 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6664 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6665 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6666 }
e7589eab 6667 } else {
8b1c0b24 6668 netdev_reset_tc(dev);
943561d3
AD		 6669 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6670 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6671
6672 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6673 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6674
6675 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6676 adapter->dcb_cfg.pfc_mode_enable = false;
6677 }
6678
8b1c0b24
JF		 6679 ixgbe_init_interrupt_scheme(adapter);
6680 ixgbe_validate_rtr(adapter, tc);
6681 if (netif_running(dev))
6682 ixgbe_open(dev);
6683
6684 return 0;
6685}
de1036b1 6686
8af3c33f 6687#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6688void ixgbe_do_reset(struct net_device *netdev)
6689{
6690 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6691
6692 if (netif_running(netdev))
6693 ixgbe_reinit_locked(adapter);
6694 else
6695 ixgbe_reset(adapter);
6696}
6697
c8f44aff 6698static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6699 netdev_features_t features)
082757af
DS		 6700{
6701 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6702
082757af
DS		 6703 /* return error if RXHASH is being enabled when RSS is not supported */
6704 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
567d2de2 6705 features &= ~NETIF_F_RXHASH;
082757af
DS		 6706
6707 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6708 if (!(features & NETIF_F_RXCSUM))
6709 features &= ~NETIF_F_LRO;
082757af 6710
567d2de2
AD		 6711 /* Turn off LRO if not RSC capable */
6712 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6713 features &= ~NETIF_F_LRO;
8e2813f5 6714
567d2de2 6715 return features;
082757af
DS		 6716}
6717
c8f44aff 6718static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6719 netdev_features_t features)
082757af
DS		 6720{
6721 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6722 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6723 bool need_reset = false;
6724
082757af 6725 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6726 if (!(features & NETIF_F_LRO)) {
6727 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6728 need_reset = true;
567d2de2
AD		 6729 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6730 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6731 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6732 if (adapter->rx_itr_setting == 1 ||
6733 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6734 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6735 need_reset = true;
6736 } else if ((changed ^ features) & NETIF_F_LRO) {
6737 e_info(probe, "rx-usecs set too low, "
6738 "disabling RSC\n");
082757af
DS		 6739 }
6740 }
6741
6742 /*
6743 * Check if Flow Director n-tuple support was enabled or disabled. If
6744 * the state changed, we need to reset.
6745 */
567d2de2
AD		 6746 if (!(features & NETIF_F_NTUPLE)) {
6747 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6748 /* turn off Flow Director, set ATR and reset */
6749 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6750 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6751 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 6752 need_reset = true;
6753 }
082757af 6754 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
567d2de2
AD		 6755 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6756 /* turn off ATR, enable perfect filters and reset */
6757 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6758 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
082757af
DS		 6759 need_reset = true;
6760 }
6761
146d4cc9
JF		 6762 if (features & NETIF_F_HW_VLAN_RX)
6763 ixgbe_vlan_strip_enable(adapter);
6764 else
6765 ixgbe_vlan_strip_disable(adapter);
6766
3f2d1c0f
BG		 6767 if (changed & NETIF_F_RXALL)
6768 need_reset = true;
6769
567d2de2 6770 netdev->features = features;
082757af
DS		 6771 if (need_reset)
6772 ixgbe_do_reset(netdev);
6773
6774 return 0;
082757af
DS		 6775}
6776
0f4b0add
JF		 6777static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6778 struct net_device *dev,
6779 unsigned char *addr,
6780 u16 flags)
6781{
6782 struct ixgbe_adapter *adapter = netdev_priv(dev);
6783 int err = -EOPNOTSUPP;
6784
6785 if (ndm->ndm_state & NUD_PERMANENT) {
6786 pr_info("%s: FDB only supports static addresses\n",
6787 ixgbe_driver_name);
6788 return -EINVAL;
6789 }
6790
6791 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6792 if (is_unicast_ether_addr(addr))
6793 err = dev_uc_add_excl(dev, addr);
6794 else if (is_multicast_ether_addr(addr))
6795 err = dev_mc_add_excl(dev, addr);
6796 else
6797 err = -EINVAL;
6798 }
6799
6800 /* Only return duplicate errors if NLM_F_EXCL is set */
6801 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6802 err = 0;
6803
6804 return err;
6805}
6806
6807static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6808 struct net_device *dev,
6809 unsigned char *addr)
6810{
6811 struct ixgbe_adapter *adapter = netdev_priv(dev);
6812 int err = -EOPNOTSUPP;
6813
6814 if (ndm->ndm_state & NUD_PERMANENT) {
6815 pr_info("%s: FDB only supports static addresses\n",
6816 ixgbe_driver_name);
6817 return -EINVAL;
6818 }
6819
6820 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6821 if (is_unicast_ether_addr(addr))
6822 err = dev_uc_del(dev, addr);
6823 else if (is_multicast_ether_addr(addr))
6824 err = dev_mc_del(dev, addr);
6825 else
6826 err = -EINVAL;
6827 }
6828
6829 return err;
6830}
6831
6832static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6833 struct netlink_callback *cb,
6834 struct net_device *dev,
6835 int idx)
6836{
6837 struct ixgbe_adapter *adapter = netdev_priv(dev);
6838
6839 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6840 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6841
6842 return idx;
6843}
6844
0edc3527 6845static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6846 .ndo_open = ixgbe_open,
0edc3527 6847 .ndo_stop = ixgbe_close,
00829823 6848 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6849 .ndo_select_queue = ixgbe_select_queue,
581330ba 6850 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6851 .ndo_validate_addr = eth_validate_addr,
6852 .ndo_set_mac_address = ixgbe_set_mac,
6853 .ndo_change_mtu = ixgbe_change_mtu,
6854 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6855 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6856 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6857 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6858 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6859 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6860 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 6861 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 6862 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6863 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 6864#ifdef CONFIG_IXGBE_DCB
24095aa3 6865 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 6866#endif
0edc3527
SH		 6867#ifdef CONFIG_NET_POLL_CONTROLLER
6868 .ndo_poll_controller = ixgbe_netpoll,
6869#endif
332d4a7d
YZ		 6870#ifdef IXGBE_FCOE
6871 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 6872 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 6873 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6874 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6875 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6876 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 6877 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 6878#endif /* IXGBE_FCOE */
082757af
DS		 6879 .ndo_set_features = ixgbe_set_features,
6880 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 6881 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6882 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6883 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 6884};
6885
1cdd1ec8 6886static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
567d2de2 6887 const struct ixgbe_info *ii)
1cdd1ec8
GR		 6888{
6889#ifdef CONFIG_PCI_IOV
6890 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 6891
c6bda30a 6892 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 6893 return;
6894
6895 /* The 82599 supports up to 64 VFs per physical function
6896 * but this implementation limits allocation to 63 so that
6897 * basic networking resources are still available to the
6b42a9c5
GR		 6898 * physical function. If the user requests greater thn
6899 * 63 VFs then it is an error - reset to default of zero.
1cdd1ec8 6900 */
6b42a9c5 6901 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
c6bda30a 6902 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 6903#endif /* CONFIG_PCI_IOV */
6904}
6905
8e2813f5
JK		 6906/**
6907 * ixgbe_wol_supported - Check whether device supports WoL
6908 * @hw: hw specific details
6909 * @device_id: the device ID
6910 * @subdev_id: the subsystem device ID
6911 *
6912 * This function is used by probe and ethtool to determine
6913 * which devices have WoL support
6914 *
6915 **/
6916int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
6917 u16 subdevice_id)
6918{
6919 struct ixgbe_hw *hw = &adapter->hw;
6920 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
6921 int is_wol_supported = 0;
6922
6923 switch (device_id) {
6924 case IXGBE_DEV_ID_82599_SFP:
6925 /* Only these subdevices could supports WOL */
6926 switch (subdevice_id) {
6927 case IXGBE_SUBDEV_ID_82599_560FLR:
6928 /* only support first port */
6929 if (hw->bus.func != 0)
6930 break;
6931 case IXGBE_SUBDEV_ID_82599_SFP:
6932 is_wol_supported = 1;
6933 break;
6934 }
6935 break;
6936 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
6937 /* All except this subdevice support WOL */
6938 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
6939 is_wol_supported = 1;
6940 break;
6941 case IXGBE_DEV_ID_82599_KX4:
6942 is_wol_supported = 1;
6943 break;
6944 case IXGBE_DEV_ID_X540T:
6945 /* check eeprom to see if enabled wol */
6946 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
6947 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
6948 (hw->bus.func == 0))) {
6949 is_wol_supported = 1;
6950 }
6951 break;
6952 }
6953
6954 return is_wol_supported;
6955}
6956
9a799d71
AK		 6957/**
6958 * ixgbe_probe - Device Initialization Routine
6959 * @pdev: PCI device information struct
6960 * @ent: entry in ixgbe_pci_tbl
6961 *
6962 * Returns 0 on success, negative on failure
6963 *
6964 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6965 * The OS initialization, configuring of the adapter private structure,
6966 * and a hardware reset occur.
6967 **/
6968static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 6969 const struct pci_device_id *ent)
9a799d71
AK		 6970{
6971 struct net_device *netdev;
6972 struct ixgbe_adapter *adapter = NULL;
6973 struct ixgbe_hw *hw;
6974 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 6975 static int cards_found;
6976 int i, err, pci_using_dac;
289700db 6977 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 6978 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 6979#ifdef IXGBE_FCOE
6980 u16 device_caps;
6981#endif
289700db 6982 u32 eec;
9a799d71 6983
bded64a7
AG		 6984 /* Catch broken hardware that put the wrong VF device ID in
6985 * the PCIe SR-IOV capability.
6986 */
6987 if (pdev->is_virtfn) {
6988 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6989 pci_name(pdev), pdev->vendor, pdev->device);
6990 return -EINVAL;
6991 }
6992
9ce77666 6993 err = pci_enable_device_mem(pdev);
9a799d71
AK		 6994 if (err)
6995 return err;
6996
1b507730
NN		 6997 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6998 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 6999 pci_using_dac = 1;
7000 } else {
1b507730 7001 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7002 if (err) {
1b507730
NN		 7003 err = dma_set_coherent_mask(&pdev->dev,
7004 DMA_BIT_MASK(32));
9a799d71 7005 if (err) {
b8bc0421
DC		 7006 dev_err(&pdev->dev,
7007 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7008 goto err_dma;
7009 }
7010 }
7011 pci_using_dac = 0;
7012 }
7013
9ce77666 7014 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7015 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7016 if (err) {
b8bc0421
DC		 7017 dev_err(&pdev->dev,
7018 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7019 goto err_pci_reg;
7020 }
7021
19d5afd4 7022 pci_enable_pcie_error_reporting(pdev);
6fabd715 7023
9a799d71 7024 pci_set_master(pdev);
fb3b27bc 7025 pci_save_state(pdev);
9a799d71 7026
e901acd6
JF		 7027#ifdef CONFIG_IXGBE_DCB
7028 indices *= MAX_TRAFFIC_CLASS;
7029#endif
7030
c85a2618
JF		 7031 if (ii->mac == ixgbe_mac_82598EB)
7032 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7033 else
7034 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7035
e901acd6 7036#ifdef IXGBE_FCOE
c85a2618
JF		 7037 indices += min_t(unsigned int, num_possible_cpus(),
7038 IXGBE_MAX_FCOE_INDICES);
7039#endif
c85a2618 7040 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7041 if (!netdev) {
7042 err = -ENOMEM;
7043 goto err_alloc_etherdev;
7044 }
7045
9a799d71
AK		 7046 SET_NETDEV_DEV(netdev, &pdev->dev);
7047
9a799d71 7048 adapter = netdev_priv(netdev);
c60fbb00 7049 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7050
7051 adapter->netdev = netdev;
7052 adapter->pdev = pdev;
7053 hw = &adapter->hw;
7054 hw->back = adapter;
b3f4d599 7055 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7056
05857980 7057 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7058 pci_resource_len(pdev, 0));
9a799d71
AK		 7059 if (!hw->hw_addr) {
7060 err = -EIO;
7061 goto err_ioremap;
7062 }
7063
7064 for (i = 1; i <= 5; i++) {
7065 if (pci_resource_len(pdev, i) == 0)
7066 continue;
7067 }
7068
0edc3527 7069 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7070 ixgbe_set_ethtool_ops(netdev);
9a799d71 7071 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7072 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7073
9a799d71
AK		 7074 adapter->bd_number = cards_found;
7075
9a799d71
AK		 7076 /* Setup hw api */
7077 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7078 hw->mac.type = ii->mac;
9a799d71 7079
c44ade9e
JB		 7080 /* EEPROM */
7081 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7082 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7083 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7084 if (!(eec & (1 << 8)))
7085 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7086
7087 /* PHY */
7088 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7089 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7090 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7091 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7092 hw->phy.mdio.mmds = 0;
7093 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7094 hw->phy.mdio.dev = netdev;
7095 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7096 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7097
8ca783ab 7098 ii->get_invariants(hw);
9a799d71
AK		 7099
7100 /* setup the private structure */
7101 err = ixgbe_sw_init(adapter);
7102 if (err)
7103 goto err_sw_init;
7104
e86bff0e 7105 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7106 switch (adapter->hw.mac.type) {
7107 case ixgbe_mac_82599EB:
7108 case ixgbe_mac_X540:
e86bff0e 7109 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7110 break;
7111 default:
7112 break;
7113 }
e86bff0e 7114
bf069c97
DS		 7115 /*
7116 * If there is a fan on this device and it has failed log the
7117 * failure.
7118 */
7119 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7120 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7121 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7122 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7123 }
7124
8ef78adc
PWJ		 7125 if (allow_unsupported_sfp)
7126 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7127
c44ade9e 7128 /* reset_hw fills in the perm_addr as well */
119fc60a 7129 hw->phy.reset_if_overtemp = true;
c44ade9e 7130 err = hw->mac.ops.reset_hw(hw);
119fc60a 7131 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7132 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7133 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7134 err = 0;
7135 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7136 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7137 "module type was detected.\n");
7138 e_dev_err("Reload the driver after installing a supported "
7139 "module.\n");
04f165ef
PW		 7140 goto err_sw_init;
7141 } else if (err) {
849c4542 7142 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7143 goto err_sw_init;
7144 }
7145
1cdd1ec8
GR		 7146 ixgbe_probe_vf(adapter, ii);
7147
396e799c 7148 netdev->features = NETIF_F_SG |
e8e9f696 7149 NETIF_F_IP_CSUM |
082757af 7150 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7151 NETIF_F_HW_VLAN_TX |
7152 NETIF_F_HW_VLAN_RX |
082757af
DS		 7153 NETIF_F_HW_VLAN_FILTER |
7154 NETIF_F_TSO |
7155 NETIF_F_TSO6 |
082757af
DS		 7156 NETIF_F_RXHASH |
7157 NETIF_F_RXCSUM;
9a799d71 7158
082757af 7159 netdev->hw_features = netdev->features;
ad31c402 7160
58be7666
DS		 7161 switch (adapter->hw.mac.type) {
7162 case ixgbe_mac_82599EB:
7163 case ixgbe_mac_X540:
45a5ead0 7164 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7165 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7166 NETIF_F_NTUPLE;
58be7666
DS		 7167 break;
7168 default:
7169 break;
7170 }
45a5ead0 7171
3f2d1c0f
BG		 7172 netdev->hw_features |= NETIF_F_RXALL;
7173
ad31c402
JK		 7174 netdev->vlan_features |= NETIF_F_TSO;
7175 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7176 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7177 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7178 netdev->vlan_features |= NETIF_F_SG;
7179
01789349 7180 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7181 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7182
1cdd1ec8
GR		 7183 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7184 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7185 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7186
7a6b6f51 7187#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7188 netdev->dcbnl_ops = &dcbnl_ops;
7189#endif
7190
eacd73f7 7191#ifdef IXGBE_FCOE
0d551589 7192 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7193 if (hw->mac.ops.get_device_caps) {
7194 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7195 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7196 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7197 }
7198 }
5e09d7f6
YZ		 7199 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7200 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7201 netdev->vlan_features |= NETIF_F_FSO;
7202 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7203 }
eacd73f7 7204#endif /* IXGBE_FCOE */
7b872a55 7205 if (pci_using_dac) {
9a799d71 7206 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7207 netdev->vlan_features |= NETIF_F_HIGHDMA;
7208 }
9a799d71 7209
082757af
DS		 7210 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7211 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7212 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7213 netdev->features |= NETIF_F_LRO;
7214
9a799d71 7215 /* make sure the EEPROM is good */
c44ade9e 7216 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7217 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7218 err = -EIO;
35937c05 7219 goto err_sw_init;
9a799d71
AK		 7220 }
7221
7222 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7223 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7224
c44ade9e 7225 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7226 e_dev_err("invalid MAC address\n");
9a799d71 7227 err = -EIO;
35937c05 7228 goto err_sw_init;
9a799d71
AK		 7229 }
7230
7086400d 7231 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7232 (unsigned long) adapter);
9a799d71 7233
7086400d
AD		 7234 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7235 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7236
021230d4
AV		 7237 err = ixgbe_init_interrupt_scheme(adapter);
7238 if (err)
7239 goto err_sw_init;
9a799d71 7240
082757af
DS		 7241 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7242 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7243 netdev->features &= ~NETIF_F_RXHASH;
082757af 7244 }
67a74ee2 7245
8e2813f5 7246 /* WOL not supported for all devices */
c23f5b6b 7247 adapter->wol = 0;
8e2813f5
JK		 7248 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7249 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7250 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7251
e8e26350
PW		 7252 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7253
3a6a4eda
JK		 7254#ifdef CONFIG_IXGBE_PTP
7255 ixgbe_ptp_init(adapter);
7256#endif /* CONFIG_IXGBE_PTP*/
7257
15e5209f
ET		 7258 /* save off EEPROM version number */
7259 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7260 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7261
04f165ef
PW		 7262 /* pick up the PCI bus settings for reporting later */
7263 hw->mac.ops.get_bus_info(hw);
7264
9a799d71 7265 /* print bus type/speed/width info */
849c4542 7266 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7267 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7268 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7269 "Unknown"),
7270 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7271 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7272 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7273 "Unknown"),
7274 netdev->dev_addr);
289700db
DS		 7275
7276 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7277 if (err)
9fe93afd 7278 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7279 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7280 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7281 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7282 part_str);
e8e26350 7283 else
289700db
DS		 7284 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7285 hw->mac.type, hw->phy.type, part_str);
9a799d71 7286
e8e26350 7287 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7288 e_dev_warn("PCI-Express bandwidth available for this card is "
7289 "not sufficient for optimal performance.\n");
7290 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7291 "is required.\n");
0c254d86
AK		 7292 }
7293
9a799d71 7294 /* reset the hardware with the new settings */
794caeb2 7295 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7296 if (err == IXGBE_ERR_EEPROM_VERSION) {
7297 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7298 e_dev_warn("This device is a pre-production adapter/LOM. "
7299 "Please be aware there may be issues associated "
7300 "with your hardware. If you are experiencing "
7301 "problems please contact your Intel or hardware "
7302 "representative who provided you with this "
7303 "hardware.\n");
794caeb2 7304 }
9a799d71
AK		 7305 strcpy(netdev->name, "eth%d");
7306 err = register_netdev(netdev);
7307 if (err)
7308 goto err_register;
7309
93d3ce8f
ET		 7310 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7311 if (hw->mac.ops.disable_tx_laser &&
7312 ((hw->phy.multispeed_fiber) ||
7313 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7314 (hw->mac.type == ixgbe_mac_82599EB))))
7315 hw->mac.ops.disable_tx_laser(hw);
7316
54386467
JB		 7317 /* carrier off reporting is important to ethtool even BEFORE open */
7318 netif_carrier_off(netdev);
7319
5dd2d332 7320#ifdef CONFIG_IXGBE_DCA
652f093f 7321 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7322 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7323 ixgbe_setup_dca(adapter);
7324 }
7325#endif
1cdd1ec8 7326 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7327 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7328 for (i = 0; i < adapter->num_vfs; i++)
7329 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7330 }
7331
2466dd9c
JK		 7332 /* firmware requires driver version to be 0xFFFFFFFF
7333 * since os does not support feature
7334 */
9612de92 7335 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7336 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7337 0xFF);
9612de92 7338
0365e6e4
PW		 7339 /* add san mac addr to netdev */
7340 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7341
ea81875a 7342 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7343 cards_found++;
3ca8bc6d 7344
1210982b 7345#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7346 if (ixgbe_sysfs_init(adapter))
7347 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7348#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7349
9a799d71
AK		 7350 return 0;
7351
7352err_register:
5eba3699 7353 ixgbe_release_hw_control(adapter);
7a921c93 7354 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7355err_sw_init:
1cdd1ec8
GR		 7356 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7357 ixgbe_disable_sriov(adapter);
7086400d 7358 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7359 iounmap(hw->hw_addr);
7360err_ioremap:
7361 free_netdev(netdev);
7362err_alloc_etherdev:
e8e9f696
JP		 7363 pci_release_selected_regions(pdev,
7364 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7365err_pci_reg:
7366err_dma:
7367 pci_disable_device(pdev);
7368 return err;
7369}
7370
7371/**
7372 * ixgbe_remove - Device Removal Routine
7373 * @pdev: PCI device information struct
7374 *
7375 * ixgbe_remove is called by the PCI subsystem to alert the driver
7376 * that it should release a PCI device. The could be caused by a
7377 * Hot-Plug event, or because the driver is going to be removed from
7378 * memory.
7379 **/
7380static void __devexit ixgbe_remove(struct pci_dev *pdev)
7381{
c60fbb00
AD		 7382 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7383 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7384
7385 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7386 cancel_work_sync(&adapter->service_task);
9a799d71 7387
3a6a4eda
JK		 7388#ifdef CONFIG_IXGBE_PTP
7389 ixgbe_ptp_stop(adapter);
7390#endif
7391
5dd2d332 7392#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7393 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7394 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7395 dca_remove_requester(&pdev->dev);
7396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7397 }
7398
7399#endif
1210982b 7400#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7401 ixgbe_sysfs_exit(adapter);
1210982b 7402#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7403
332d4a7d
YZ		 7404#ifdef IXGBE_FCOE
7405 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7406 ixgbe_cleanup_fcoe(adapter);
7407
7408#endif /* IXGBE_FCOE */
0365e6e4
PW		 7409
7410 /* remove the added san mac */
7411 ixgbe_del_sanmac_netdev(netdev);
7412
c4900be0
DS		 7413 if (netdev->reg_state == NETREG_REGISTERED)
7414 unregister_netdev(netdev);
9a799d71 7415
c6bda30a
GR		 7416 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7417 if (!(ixgbe_check_vf_assignment(adapter)))
7418 ixgbe_disable_sriov(adapter);
7419 else
7420 e_dev_warn("Unloading driver while VFs are assigned "
7421 "- VFs will not be deallocated\n");
7422 }
1cdd1ec8 7423
7a921c93 7424 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7425
021230d4 7426 ixgbe_release_hw_control(adapter);
9a799d71 7427
2b1588c3
AD		 7428#ifdef CONFIG_DCB
7429 kfree(adapter->ixgbe_ieee_pfc);
7430 kfree(adapter->ixgbe_ieee_ets);
7431
7432#endif
9a799d71 7433 iounmap(adapter->hw.hw_addr);
9ce77666 7434 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7435 IORESOURCE_MEM));
9a799d71 7436
849c4542 7437 e_dev_info("complete\n");
021230d4 7438
9a799d71
AK		 7439 free_netdev(netdev);
7440
19d5afd4 7441 pci_disable_pcie_error_reporting(pdev);
6fabd715 7442
9a799d71
AK		 7443 pci_disable_device(pdev);
7444}
7445
7446/**
7447 * ixgbe_io_error_detected - called when PCI error is detected
7448 * @pdev: Pointer to PCI device
7449 * @state: The current pci connection state
7450 *
7451 * This function is called after a PCI bus error affecting
7452 * this device has been detected.
7453 */
7454static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7455 pci_channel_state_t state)
9a799d71 7456{
c60fbb00
AD		 7457 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7458 struct net_device *netdev = adapter->netdev;
9a799d71 7459
83c61fa9
GR		 7460#ifdef CONFIG_PCI_IOV
7461 struct pci_dev *bdev, *vfdev;
7462 u32 dw0, dw1, dw2, dw3;
7463 int vf, pos;
7464 u16 req_id, pf_func;
7465
7466 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7467 adapter->num_vfs == 0)
7468 goto skip_bad_vf_detection;
7469
7470 bdev = pdev->bus->self;
7471 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7472 bdev = bdev->bus->self;
7473
7474 if (!bdev)
7475 goto skip_bad_vf_detection;
7476
7477 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7478 if (!pos)
7479 goto skip_bad_vf_detection;
7480
7481 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7482 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7483 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7484 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7485
7486 req_id = dw1 >> 16;
7487 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7488 if (!(req_id & 0x0080))
7489 goto skip_bad_vf_detection;
7490
7491 pf_func = req_id & 0x01;
7492 if ((pf_func & 1) == (pdev->devfn & 1)) {
7493 unsigned int device_id;
7494
7495 vf = (req_id & 0x7F) >> 1;
7496 e_dev_err("VF %d has caused a PCIe error\n", vf);
7497 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7498 "%8.8x\tdw3: %8.8x\n",
7499 dw0, dw1, dw2, dw3);
7500 switch (adapter->hw.mac.type) {
7501 case ixgbe_mac_82599EB:
7502 device_id = IXGBE_82599_VF_DEVICE_ID;
7503 break;
7504 case ixgbe_mac_X540:
7505 device_id = IXGBE_X540_VF_DEVICE_ID;
7506 break;
7507 default:
7508 device_id = 0;
7509 break;
7510 }
7511
7512 /* Find the pci device of the offending VF */
7513 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7514 while (vfdev) {
7515 if (vfdev->devfn == (req_id & 0xFF))
7516 break;
7517 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7518 device_id, vfdev);
7519 }
7520 /*
7521 * There's a slim chance the VF could have been hot plugged,
7522 * so if it is no longer present we don't need to issue the
7523 * VFLR. Just clean up the AER in that case.
7524 */
7525 if (vfdev) {
7526 e_dev_err("Issuing VFLR to VF %d\n", vf);
7527 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7528 }
7529
7530 pci_cleanup_aer_uncorrect_error_status(pdev);
7531 }
7532
7533 /*
7534 * Even though the error may have occurred on the other port
7535 * we still need to increment the vf error reference count for
7536 * both ports because the I/O resume function will be called
7537 * for both of them.
7538 */
7539 adapter->vferr_refcount++;
7540
7541 return PCI_ERS_RESULT_RECOVERED;
7542
7543skip_bad_vf_detection:
7544#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7545 netif_device_detach(netdev);
7546
3044b8d1
BL		 7547 if (state == pci_channel_io_perm_failure)
7548 return PCI_ERS_RESULT_DISCONNECT;
7549
9a799d71
AK		 7550 if (netif_running(netdev))
7551 ixgbe_down(adapter);
7552 pci_disable_device(pdev);
7553
b4617240 7554 /* Request a slot reset. */
9a799d71
AK		 7555 return PCI_ERS_RESULT_NEED_RESET;
7556}
7557
7558/**
7559 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7560 * @pdev: Pointer to PCI device
7561 *
7562 * Restart the card from scratch, as if from a cold-boot.
7563 */
7564static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7565{
c60fbb00 7566 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7567 pci_ers_result_t result;
7568 int err;
9a799d71 7569
9ce77666 7570 if (pci_enable_device_mem(pdev)) {
396e799c 7571 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7572 result = PCI_ERS_RESULT_DISCONNECT;
7573 } else {
7574 pci_set_master(pdev);
7575 pci_restore_state(pdev);
c0e1f68b 7576 pci_save_state(pdev);
9a799d71 7577
dd4d8ca6 7578 pci_wake_from_d3(pdev, false);
9a799d71 7579
6fabd715 7580 ixgbe_reset(adapter);
88512539 7581 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7582 result = PCI_ERS_RESULT_RECOVERED;
7583 }
7584
7585 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7586 if (err) {
849c4542
ET		 7587 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7588 "failed 0x%0x\n", err);
6fabd715
PWJ		 7589 /* non-fatal, continue */
7590 }
9a799d71 7591
6fabd715 7592 return result;
9a799d71
AK		 7593}
7594
7595/**
7596 * ixgbe_io_resume - called when traffic can start flowing again.
7597 * @pdev: Pointer to PCI device
7598 *
7599 * This callback is called when the error recovery driver tells us that
7600 * its OK to resume normal operation.
7601 */
7602static void ixgbe_io_resume(struct pci_dev *pdev)
7603{
c60fbb00
AD		 7604 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7605 struct net_device *netdev = adapter->netdev;
9a799d71 7606
83c61fa9
GR		 7607#ifdef CONFIG_PCI_IOV
7608 if (adapter->vferr_refcount) {
7609 e_info(drv, "Resuming after VF err\n");
7610 adapter->vferr_refcount--;
7611 return;
7612 }
7613
7614#endif
c7ccde0f
AD		 7615 if (netif_running(netdev))
7616 ixgbe_up(adapter);
9a799d71
AK		 7617
7618 netif_device_attach(netdev);
9a799d71
AK		 7619}
7620
7621static struct pci_error_handlers ixgbe_err_handler = {
7622 .error_detected = ixgbe_io_error_detected,
7623 .slot_reset = ixgbe_io_slot_reset,
7624 .resume = ixgbe_io_resume,
7625};
7626
7627static struct pci_driver ixgbe_driver = {
7628 .name = ixgbe_driver_name,
7629 .id_table = ixgbe_pci_tbl,
7630 .probe = ixgbe_probe,
7631 .remove = __devexit_p(ixgbe_remove),
7632#ifdef CONFIG_PM
7633 .suspend = ixgbe_suspend,
7634 .resume = ixgbe_resume,
7635#endif
7636 .shutdown = ixgbe_shutdown,
7637 .err_handler = &ixgbe_err_handler
7638};
7639
7640/**
7641 * ixgbe_init_module - Driver Registration Routine
7642 *
7643 * ixgbe_init_module is the first routine called when the driver is
7644 * loaded. All it does is register with the PCI subsystem.
7645 **/
7646static int __init ixgbe_init_module(void)
7647{
7648 int ret;
c7689578 7649 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7650 pr_info("%s\n", ixgbe_copyright);
9a799d71 7651
5dd2d332 7652#ifdef CONFIG_IXGBE_DCA
bd0362dd 7653 dca_register_notify(&dca_notifier);
bd0362dd 7654#endif
5dd2d332 7655
9a799d71
AK		 7656 ret = pci_register_driver(&ixgbe_driver);
7657 return ret;
7658}
b4617240 7659
9a799d71
AK		 7660module_init(ixgbe_init_module);
7661
7662/**
7663 * ixgbe_exit_module - Driver Exit Cleanup Routine
7664 *
7665 * ixgbe_exit_module is called just before the driver is removed
7666 * from memory.
7667 **/
7668static void __exit ixgbe_exit_module(void)
7669{
5dd2d332 7670#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7671 dca_unregister_notify(&dca_notifier);
7672#endif
9a799d71 7673 pci_unregister_driver(&ixgbe_driver);
1a51502b 7674 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7675}
bd0362dd 7676
5dd2d332 7677#ifdef CONFIG_IXGBE_DCA
bd0362dd 7678static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7679 void *p)
bd0362dd
JC		 7680{
7681 int ret_val;
7682
7683 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7684 __ixgbe_notify_dca);
bd0362dd
JC		 7685
7686 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7687}
b453368d 7688
5dd2d332 7689#endif /* CONFIG_IXGBE_DCA */
849c4542 7690
9a799d71
AK		 7691module_exit(ixgbe_exit_module);
7692
7693/* ixgbe_main.c */
Linux kernel - Deliverables
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