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igb: Support RX-ALL feature flag.
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
ea81875a
NP		 58char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
75e3d3c6 60#define MAJ 3
19d478bb
DS		 61#define MIN 6
62#define BUILD 7
75e3d3c6 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 64 __stringify(BUILD) "-k"
9c8eb720 65const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 66static const char ixgbe_copyright[] =
94971820 67 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 68
69static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 70 [board_82598] = &ixgbe_82598_info,
e8e26350 71 [board_82599] = &ixgbe_82599_info,
fe15e8e1 72 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 73};
74
75/* ixgbe_pci_tbl - PCI Device ID Table
76 *
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
79 *
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
82 */
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
1cdd1ec8
GR		 127#ifdef CONFIG_PCI_IOV
128static unsigned int max_vfs;
129module_param(max_vfs, uint, 0);
e8e9f696
JP		 130MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 132#endif /* CONFIG_PCI_IOV */
133
8ef78adc
PWJ		 134static unsigned int allow_unsupported_sfp;
135module_param(allow_unsupported_sfp, uint, 0);
136MODULE_PARM_DESC(allow_unsupported_sfp,
137 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
138
9a799d71
AK		 139MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_VERSION);
143
144#define DEFAULT_DEBUG_LEVEL_SHIFT 3
145
7086400d
AD		 146static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
147{
148 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
149 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
150 schedule_work(&adapter->service_task);
151}
152
153static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
154{
155 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
156
52f33af8 157 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 158 smp_mb__before_clear_bit();
159 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
160}
161
dcd79aeb
TI		 162struct ixgbe_reg_info {
163 u32 ofs;
164 char *name;
165};
166
167static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
168
169 /* General Registers */
170 {IXGBE_CTRL, "CTRL"},
171 {IXGBE_STATUS, "STATUS"},
172 {IXGBE_CTRL_EXT, "CTRL_EXT"},
173
174 /* Interrupt Registers */
175 {IXGBE_EICR, "EICR"},
176
177 /* RX Registers */
178 {IXGBE_SRRCTL(0), "SRRCTL"},
179 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
180 {IXGBE_RDLEN(0), "RDLEN"},
181 {IXGBE_RDH(0), "RDH"},
182 {IXGBE_RDT(0), "RDT"},
183 {IXGBE_RXDCTL(0), "RXDCTL"},
184 {IXGBE_RDBAL(0), "RDBAL"},
185 {IXGBE_RDBAH(0), "RDBAH"},
186
187 /* TX Registers */
188 {IXGBE_TDBAL(0), "TDBAL"},
189 {IXGBE_TDBAH(0), "TDBAH"},
190 {IXGBE_TDLEN(0), "TDLEN"},
191 {IXGBE_TDH(0), "TDH"},
192 {IXGBE_TDT(0), "TDT"},
193 {IXGBE_TXDCTL(0), "TXDCTL"},
194
195 /* List Terminator */
196 {}
197};
198
199
200/*
201 * ixgbe_regdump - register printout routine
202 */
203static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
204{
205 int i = 0, j = 0;
206 char rname[16];
207 u32 regs[64];
208
209 switch (reginfo->ofs) {
210 case IXGBE_SRRCTL(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
213 break;
214 case IXGBE_DCA_RXCTRL(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
217 break;
218 case IXGBE_RDLEN(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
221 break;
222 case IXGBE_RDH(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
225 break;
226 case IXGBE_RDT(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
229 break;
230 case IXGBE_RXDCTL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
233 break;
234 case IXGBE_RDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
237 break;
238 case IXGBE_RDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
241 break;
242 case IXGBE_TDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
245 break;
246 case IXGBE_TDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
249 break;
250 case IXGBE_TDLEN(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
253 break;
254 case IXGBE_TDH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
257 break;
258 case IXGBE_TDT(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
261 break;
262 case IXGBE_TXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
265 break;
266 default:
c7689578 267 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 268 IXGBE_READ_REG(hw, reginfo->ofs));
269 return;
270 }
271
272 for (i = 0; i < 8; i++) {
273 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 274 pr_err("%-15s", rname);
dcd79aeb 275 for (j = 0; j < 8; j++)
c7689578
JP		 276 pr_cont(" %08x", regs[i*8+j]);
277 pr_cont("\n");
dcd79aeb
TI		 278 }
279
280}
281
282/*
283 * ixgbe_dump - Print registers, tx-rings and rx-rings
284 */
285static void ixgbe_dump(struct ixgbe_adapter *adapter)
286{
287 struct net_device *netdev = adapter->netdev;
288 struct ixgbe_hw *hw = &adapter->hw;
289 struct ixgbe_reg_info *reginfo;
290 int n = 0;
291 struct ixgbe_ring *tx_ring;
292 struct ixgbe_tx_buffer *tx_buffer_info;
293 union ixgbe_adv_tx_desc *tx_desc;
294 struct my_u0 { u64 a; u64 b; } *u0;
295 struct ixgbe_ring *rx_ring;
296 union ixgbe_adv_rx_desc *rx_desc;
297 struct ixgbe_rx_buffer *rx_buffer_info;
298 u32 staterr;
299 int i = 0;
300
301 if (!netif_msg_hw(adapter))
302 return;
303
304 /* Print netdevice Info */
305 if (netdev) {
306 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 307 pr_info("Device Name state "
dcd79aeb 308 "trans_start last_rx\n");
c7689578
JP		 309 pr_info("%-15s %016lX %016lX %016lX\n",
310 netdev->name,
311 netdev->state,
312 netdev->trans_start,
313 netdev->last_rx);
dcd79aeb
TI		 314 }
315
316 /* Print Registers */
317 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 318 pr_info(" Register Name Value\n");
dcd79aeb
TI		 319 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
320 reginfo->name; reginfo++) {
321 ixgbe_regdump(hw, reginfo);
322 }
323
324 /* Print TX Ring Summary */
325 if (!netdev || !netif_running(netdev))
326 goto exit;
327
328 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 329 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 330 for (n = 0; n < adapter->num_tx_queues; n++) {
331 tx_ring = adapter->tx_ring[n];
332 tx_buffer_info =
333 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 334 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 335 n, tx_ring->next_to_use, tx_ring->next_to_clean,
336 (u64)tx_buffer_info->dma,
337 tx_buffer_info->length,
338 tx_buffer_info->next_to_watch,
339 (u64)tx_buffer_info->time_stamp);
340 }
341
342 /* Print TX Rings */
343 if (!netif_msg_tx_done(adapter))
344 goto rx_ring_summary;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
347
348 /* Transmit Descriptor Formats
349 *
350 * Advanced Transmit Descriptor
351 * +--------------------------------------------------------------+
352 * 0 | Buffer Address [63:0] |
353 * +--------------------------------------------------------------+
354 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
355 * +--------------------------------------------------------------+
356 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
357 */
358
359 for (n = 0; n < adapter->num_tx_queues; n++) {
360 tx_ring = adapter->tx_ring[n];
c7689578
JP		 361 pr_info("------------------------------------\n");
362 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
363 pr_info("------------------------------------\n");
364 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 365 "[PlPOIdStDDt Ln] [bi->dma ] "
366 "leng ntw timestamp bi->skb\n");
367
368 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 369 tx_desc = IXGBE_TX_DESC(tx_ring, i);
dcd79aeb
TI		 370 tx_buffer_info = &tx_ring->tx_buffer_info[i];
371 u0 = (struct my_u0 *)tx_desc;
c7689578 372 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 373 " %04X %p %016llX %p", i,
dcd79aeb
TI		 374 le64_to_cpu(u0->a),
375 le64_to_cpu(u0->b),
376 (u64)tx_buffer_info->dma,
377 tx_buffer_info->length,
378 tx_buffer_info->next_to_watch,
379 (u64)tx_buffer_info->time_stamp,
380 tx_buffer_info->skb);
381 if (i == tx_ring->next_to_use &&
382 i == tx_ring->next_to_clean)
c7689578 383 pr_cont(" NTC/U\n");
dcd79aeb 384 else if (i == tx_ring->next_to_use)
c7689578 385 pr_cont(" NTU\n");
dcd79aeb 386 else if (i == tx_ring->next_to_clean)
c7689578 387 pr_cont(" NTC\n");
dcd79aeb 388 else
c7689578 389 pr_cont("\n");
dcd79aeb
TI		 390
391 if (netif_msg_pktdata(adapter) &&
392 tx_buffer_info->dma != 0)
393 print_hex_dump(KERN_INFO, "",
394 DUMP_PREFIX_ADDRESS, 16, 1,
395 phys_to_virt(tx_buffer_info->dma),
396 tx_buffer_info->length, true);
397 }
398 }
399
400 /* Print RX Rings Summary */
401rx_ring_summary:
402 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 403 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 404 for (n = 0; n < adapter->num_rx_queues; n++) {
405 rx_ring = adapter->rx_ring[n];
c7689578
JP		 406 pr_info("%5d %5X %5X\n",
407 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 408 }
409
410 /* Print RX Rings */
411 if (!netif_msg_rx_status(adapter))
412 goto exit;
413
414 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
415
416 /* Advanced Receive Descriptor (Read) Format
417 * 63 1 0
418 * +-----------------------------------------------------+
419 * 0 | Packet Buffer Address [63:1] |A0/NSE|
420 * +----------------------------------------------+------+
421 * 8 | Header Buffer Address [63:1] | DD |
422 * +-----------------------------------------------------+
423 *
424 *
425 * Advanced Receive Descriptor (Write-Back) Format
426 *
427 * 63 48 47 32 31 30 21 20 16 15 4 3 0
428 * +------------------------------------------------------+
429 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
430 * | Checksum Ident | | | | Type | Type |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
435 */
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 442 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
443 "<-- Adv Rx Read format\n");
c7689578 444 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 445 "[vl er S cks ln] ---------------- [bi->skb] "
446 "<-- Adv Rx Write-Back format\n");
447
448 for (i = 0; i < rx_ring->count; i++) {
449 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 450 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 451 u0 = (struct my_u0 *)rx_desc;
452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
453 if (staterr & IXGBE_RXD_STAT_DD) {
454 /* Descriptor Done */
c7689578 455 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 456 "%016llX ---------------- %p", i,
457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
459 rx_buffer_info->skb);
460 } else {
c7689578 461 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 462 "%016llX %016llX %p", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)rx_buffer_info->dma,
466 rx_buffer_info->skb);
467
468 if (netif_msg_pktdata(adapter)) {
469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(rx_buffer_info->dma),
472 rx_ring->rx_buf_len, true);
473
474 if (rx_ring->rx_buf_len
919e78a6 475 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 476 print_hex_dump(KERN_INFO, "",
477 DUMP_PREFIX_ADDRESS, 16, 1,
478 phys_to_virt(
479 rx_buffer_info->page_dma +
480 rx_buffer_info->page_offset
481 ),
482 PAGE_SIZE/2, true);
483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
e8e26350
PW		 520/*
521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
d3d00239
AD		 592static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
d3d00239
AD		 595 if (tx_buffer->dma) {
596 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
597 dma_unmap_page(ring->dev,
598 tx_buffer->dma,
599 tx_buffer->length,
600 DMA_TO_DEVICE);
e5a43549 601 else
d3d00239
AD		 602 dma_unmap_single(ring->dev,
603 tx_buffer->dma,
604 tx_buffer->length,
605 DMA_TO_DEVICE);
e5a43549 606 }
d3d00239
AD		 607 tx_buffer->dma = 0;
608}
609
610void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
611 struct ixgbe_tx_buffer *tx_buffer_info)
612{
613 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
614 if (tx_buffer_info->skb)
9a799d71 615 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 616 tx_buffer_info->skb = NULL;
9a799d71
AK		 617 /* tx_buffer_info must be completely set up in the transmit path */
618}
619
c84d324c
JF		 620static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
621{
622 struct ixgbe_hw *hw = &adapter->hw;
623 struct ixgbe_hw_stats *hwstats = &adapter->stats;
624 u32 data = 0;
625 u32 xoff[8] = {0};
626 int i;
627
628 if ((hw->fc.current_mode == ixgbe_fc_full) ||
629 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
630 switch (hw->mac.type) {
631 case ixgbe_mac_82598EB:
632 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 633 break;
634 default:
c84d324c
JF		 635 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
636 }
637 hwstats->lxoffrxc += data;
638
639 /* refill credits (no tx hang) if we received xoff */
640 if (!data)
641 return;
642
643 for (i = 0; i < adapter->num_tx_queues; i++)
644 clear_bit(__IXGBE_HANG_CHECK_ARMED,
645 &adapter->tx_ring[i]->state);
646 return;
647 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
648 return;
649
650 /* update stats for each tc, only valid with PFC enabled */
651 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
652 switch (hw->mac.type) {
653 case ixgbe_mac_82598EB:
654 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 655 break;
c84d324c
JF		 656 default:
657 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 658 }
c84d324c
JF		 659 hwstats->pxoffrxc[i] += xoff[i];
660 }
661
662 /* disarm tx queues that have received xoff frames */
663 for (i = 0; i < adapter->num_tx_queues; i++) {
664 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 665 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 666
667 if (xoff[tc])
668 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 669 }
26f23d82
YZ		 670}
671
c84d324c 672static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 673{
c84d324c
JF		 674 return ring->tx_stats.completed;
675}
676
677static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
678{
679 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 680 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 681
c84d324c
JF		 682 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
683 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
684
685 if (head != tail)
686 return (head < tail) ?
687 tail - head : (tail + ring->count - head);
688
689 return 0;
690}
691
692static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
693{
694 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
695 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
696 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
697 bool ret = false;
698
7d637bcc 699 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 700
701 /*
702 * Check for a hung queue, but be thorough. This verifies
703 * that a transmit has been completed since the previous
704 * check AND there is at least one packet pending. The
705 * ARMED bit is set to indicate a potential hang. The
706 * bit is cleared if a pause frame is received to remove
707 * false hang detection due to PFC or 802.3x frames. By
708 * requiring this to fail twice we avoid races with
709 * pfc clearing the ARMED bit and conditions where we
710 * run the check_tx_hang logic with a transmit completion
711 * pending but without time to complete it yet.
712 */
713 if ((tx_done_old == tx_done) && tx_pending) {
714 /* make sure it is true for two checks in a row */
715 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
716 &tx_ring->state);
717 } else {
718 /* update completed stats and continue */
719 tx_ring->tx_stats.tx_done_old = tx_done;
720 /* reset the countdown */
721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 722 }
723
c84d324c 724 return ret;
9a799d71
AK		 725}
726
c83c6cbd
AD		 727/**
728 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
729 * @adapter: driver private struct
730 **/
731static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
732{
733
734 /* Do the reset outside of interrupt context */
735 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
736 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
737 ixgbe_service_event_schedule(adapter);
738 }
739}
e01c31a5 740
9a799d71
AK		 741/**
742 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 743 * @q_vector: structure containing interrupt and ring information
e01c31a5 744 * @tx_ring: tx ring to clean
9a799d71 745 **/
fe49f04a 746static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 747 struct ixgbe_ring *tx_ring)
9a799d71 748{
fe49f04a 749 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 750 struct ixgbe_tx_buffer *tx_buffer;
751 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 752 unsigned int total_bytes = 0, total_packets = 0;
59224555 753 unsigned int budget = q_vector->tx.work_limit;
d3d00239 754 u16 i = tx_ring->next_to_clean;
9a799d71 755
d3d00239 756 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 757 tx_desc = IXGBE_TX_DESC(tx_ring, i);
12207e49 758
30065e63 759 for (; budget; budget--) {
d3d00239
AD		 760 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
761
762 /* if next_to_watch is not set then there is no work pending */
763 if (!eop_desc)
764 break;
765
7f83a9e6
AD		 766 /* prevent any other reads prior to eop_desc */
767 rmb();
768
d3d00239
AD		 769 /* if DD is not set pending work has not been completed */
770 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
771 break;
8ad494b0 772
d3d00239
AD		 773 /* count the packet as being completed */
774 tx_ring->tx_stats.completed++;
775
776 /* clear next_to_watch to prevent false hangs */
777 tx_buffer->next_to_watch = NULL;
8ad494b0 778
d3d00239
AD		 779 do {
780 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
d3d00239
AD		 781 if (likely(tx_desc == eop_desc)) {
782 eop_desc = NULL;
783 dev_kfree_skb_any(tx_buffer->skb);
784 tx_buffer->skb = NULL;
785
786 total_bytes += tx_buffer->bytecount;
787 total_packets += tx_buffer->gso_segs;
788 }
9a799d71 789
d3d00239
AD		 790 tx_buffer++;
791 tx_desc++;
8ad494b0 792 i++;
d3d00239 793 if (unlikely(i == tx_ring->count)) {
8ad494b0 794 i = 0;
e01c31a5 795
d3d00239 796 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 797 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 798 }
e01c31a5 799
d3d00239 800 } while (eop_desc);
12207e49
PWJ		 801 }
802
9a799d71 803 tx_ring->next_to_clean = i;
d3d00239 804 u64_stats_update_begin(&tx_ring->syncp);
b953799e 805 tx_ring->stats.bytes += total_bytes;
bd198058 806 tx_ring->stats.packets += total_packets;
d3d00239 807 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 808 q_vector->tx.total_bytes += total_bytes;
809 q_vector->tx.total_packets += total_packets;
b953799e 810
c84d324c
JF		 811 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
812 /* schedule immediate reset if we believe we hung */
813 struct ixgbe_hw *hw = &adapter->hw;
e4f74028 814 tx_desc = IXGBE_TX_DESC(tx_ring, i);
c84d324c
JF		 815 e_err(drv, "Detected Tx Unit Hang\n"
816 " Tx Queue <%d>\n"
817 " TDH, TDT <%x>, <%x>\n"
818 " next_to_use <%x>\n"
819 " next_to_clean <%x>\n"
820 "tx_buffer_info[next_to_clean]\n"
821 " time_stamp <%lx>\n"
822 " jiffies <%lx>\n",
823 tx_ring->queue_index,
824 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
825 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 826 tx_ring->next_to_use, i,
827 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 828
829 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
830
831 e_info(probe,
832 "tx hang %d detected on queue %d, resetting adapter\n",
833 adapter->tx_timeout_count + 1, tx_ring->queue_index);
834
b953799e 835 /* schedule immediate reset if we believe we hung */
c83c6cbd 836 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 837
838 /* the adapter is about to reset, no point in enabling stuff */
59224555 839 return true;
b953799e 840 }
9a799d71 841
b2d96e0a
AD		 842 netdev_tx_completed_queue(txring_txq(tx_ring),
843 total_packets, total_bytes);
844
e092be60 845#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 846 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 847 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 848 /* Make sure that anybody stopping the queue after this
849 * sees the new next_to_clean.
850 */
851 smp_mb();
fc77dc3c 852 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 853 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 854 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 855 ++tx_ring->tx_stats.restart_queue;
30eba97a 856 }
e092be60 857 }
9a799d71 858
59224555 859 return !!budget;
9a799d71
AK		 860}
861
5dd2d332 862#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 863static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
864 struct ixgbe_ring *tx_ring,
33cf09c9 865 int cpu)
bd0362dd 866{
33cf09c9 867 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 868 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
869 u16 reg_offset;
33cf09c9 870
33cf09c9
AD		 871 switch (hw->mac.type) {
872 case ixgbe_mac_82598EB:
bdda1a61 873 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 874 break;
875 case ixgbe_mac_82599EB:
b93a2226 876 case ixgbe_mac_X540:
bdda1a61
AD		 877 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
878 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 879 break;
880 default:
bdda1a61
AD		 881 /* for unknown hardware do not write register */
882 return;
bd0362dd 883 }
bdda1a61
AD		 884
885 /*
886 * We can enable relaxed ordering for reads, but not writes when
887 * DCA is enabled. This is due to a known issue in some chipsets
888 * which will cause the DCA tag to be cleared.
889 */
890 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
891 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
892 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
893
894 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 895}
896
bdda1a61
AD		 897static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
898 struct ixgbe_ring *rx_ring,
33cf09c9 899 int cpu)
bd0362dd 900{
33cf09c9 901 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 902 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
903 u8 reg_idx = rx_ring->reg_idx;
904
33cf09c9
AD		 905
906 switch (hw->mac.type) {
33cf09c9 907 case ixgbe_mac_82599EB:
b93a2226 908 case ixgbe_mac_X540:
bdda1a61 909 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 910 break;
911 default:
912 break;
913 }
bdda1a61
AD		 914
915 /*
916 * We can enable relaxed ordering for reads, but not writes when
917 * DCA is enabled. This is due to a known issue in some chipsets
918 * which will cause the DCA tag to be cleared.
919 */
920 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
921 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
922 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
923
924 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 925}
926
927static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
928{
929 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 930 struct ixgbe_ring *ring;
bd0362dd 931 int cpu = get_cpu();
bd0362dd 932
33cf09c9
AD		 933 if (q_vector->cpu == cpu)
934 goto out_no_update;
935
a557928e 936 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 937 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 938
a557928e 939 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 940 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 941
942 q_vector->cpu = cpu;
943out_no_update:
bd0362dd
JC		 944 put_cpu();
945}
946
947static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
948{
33cf09c9 949 int num_q_vectors;
bd0362dd
JC		 950 int i;
951
952 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
953 return;
954
e35ec126
AD		 955 /* always use CB2 mode, difference is masked in the CB driver */
956 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
957
33cf09c9
AD		 958 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
959 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
960 else
961 num_q_vectors = 1;
962
963 for (i = 0; i < num_q_vectors; i++) {
964 adapter->q_vector[i]->cpu = -1;
965 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 966 }
967}
968
969static int __ixgbe_notify_dca(struct device *dev, void *data)
970{
c60fbb00 971 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 972 unsigned long event = *(unsigned long *)data;
973
2a72c31e 974 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 975 return 0;
976
bd0362dd
JC		 977 switch (event) {
978 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 979 /* if we're already enabled, don't do it again */
980 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
981 break;
652f093f 982 if (dca_add_requester(dev) == 0) {
96b0e0f6 983 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 984 ixgbe_setup_dca(adapter);
985 break;
986 }
987 /* Fall Through since DCA is disabled. */
988 case DCA_PROVIDER_REMOVE:
989 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
990 dca_remove_requester(dev);
991 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
993 }
994 break;
995 }
996
652f093f 997 return 0;
bd0362dd 998}
67a74ee2 999
bdda1a61 1000#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1001static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1002 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1003 struct sk_buff *skb)
1004{
8a0da21b
AD		 1005 if (ring->netdev->features & NETIF_F_RXHASH)
1006 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1007}
1008
ff886dfc
AD		 1009/**
1010 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1011 * @adapter: address of board private structure
1012 * @rx_desc: advanced rx descriptor
1013 *
1014 * Returns : true if it is FCoE pkt
1015 */
1016static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1017 union ixgbe_adv_rx_desc *rx_desc)
1018{
1019 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1020
1021 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1022 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1023 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1024 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1025}
1026
e59bd25d
AV		 1027/**
1028 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1029 * @ring: structure containing ring specific data
1030 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1031 * @skb: skb currently being received and modified
1032 **/
8a0da21b 1033static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1034 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1035 struct sk_buff *skb)
9a799d71 1036{
8a0da21b 1037 skb_checksum_none_assert(skb);
9a799d71 1038
712744be 1039 /* Rx csum disabled */
8a0da21b 1040 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1041 return;
e59bd25d
AV		 1042
1043 /* if IP and error */
f56e0cb1
AD		 1044 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1045 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1046 ring->rx_stats.csum_err++;
9a799d71
AK		 1047 return;
1048 }
e59bd25d 1049
f56e0cb1 1050 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1051 return;
1052
f56e0cb1 1053 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1054 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1055
1056 /*
1057 * 82599 errata, UDP frames with a 0 checksum can be marked as
1058 * checksum errors.
1059 */
8a0da21b
AD		 1060 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1061 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1062 return;
1063
8a0da21b 1064 ring->rx_stats.csum_err++;
e59bd25d
AV		 1065 return;
1066 }
1067
9a799d71 1068 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1069 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1070}
1071
84ea2591 1072static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1073{
f56e0cb1 1074 rx_ring->next_to_use = val;
e8e26350
PW		 1075 /*
1076 * Force memory writes to complete before letting h/w
1077 * know there are new descriptors to fetch. (Only
1078 * applicable for weak-ordered memory model archs,
1079 * such as IA-64).
1080 */
1081 wmb();
84ea2591 1082 writel(val, rx_ring->tail);
e8e26350
PW		 1083}
1084
f990b79b
AD		 1085static bool ixgbe_alloc_mapped_skb(struct ixgbe_ring *rx_ring,
1086 struct ixgbe_rx_buffer *bi)
1087{
1088 struct sk_buff *skb = bi->skb;
1089 dma_addr_t dma = bi->dma;
1090
1091 if (dma)
1092 return true;
1093
1094 if (likely(!skb)) {
1095 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1096 rx_ring->rx_buf_len);
1097 bi->skb = skb;
1098 if (!skb) {
1099 rx_ring->rx_stats.alloc_rx_buff_failed++;
1100 return false;
1101 }
f990b79b
AD		 1102 }
1103
1104 dma = dma_map_single(rx_ring->dev, skb->data,
1105 rx_ring->rx_buf_len, DMA_FROM_DEVICE);
1106
1107 if (dma_mapping_error(rx_ring->dev, dma)) {
1108 rx_ring->rx_stats.alloc_rx_buff_failed++;
1109 return false;
1110 }
1111
1112 bi->dma = dma;
1113 return true;
1114}
1115
1116static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1117 struct ixgbe_rx_buffer *bi)
1118{
1119 struct page *page = bi->page;
1120 dma_addr_t page_dma = bi->page_dma;
1121 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
1122
1123 if (page_dma)
1124 return true;
1125
1126 if (!page) {
1127 page = alloc_page(GFP_ATOMIC | __GFP_COLD);
1128 bi->page = page;
1129 if (unlikely(!page)) {
1130 rx_ring->rx_stats.alloc_rx_page_failed++;
1131 return false;
1132 }
1133 }
1134
1135 page_dma = dma_map_page(rx_ring->dev, page,
1136 page_offset, PAGE_SIZE / 2,
1137 DMA_FROM_DEVICE);
1138
1139 if (dma_mapping_error(rx_ring->dev, page_dma)) {
1140 rx_ring->rx_stats.alloc_rx_page_failed++;
1141 return false;
1142 }
1143
1144 bi->page_dma = page_dma;
1145 bi->page_offset = page_offset;
1146 return true;
1147}
1148
9a799d71 1149/**
f990b79b 1150 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1151 * @rx_ring: ring to place buffers on
1152 * @cleaned_count: number of buffers to replace
9a799d71 1153 **/
fc77dc3c 1154void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1155{
9a799d71 1156 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1157 struct ixgbe_rx_buffer *bi;
d5f398ed 1158 u16 i = rx_ring->next_to_use;
9a799d71 1159
f990b79b
AD		 1160 /* nothing to do or no valid netdev defined */
1161 if (!cleaned_count || !rx_ring->netdev)
fc77dc3c
AD		 1162 return;
1163
e4f74028 1164 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1165 bi = &rx_ring->rx_buffer_info[i];
1166 i -= rx_ring->count;
9a799d71 1167
f990b79b
AD		 1168 while (cleaned_count--) {
1169 if (!ixgbe_alloc_mapped_skb(rx_ring, bi))
1170 break;
d5f398ed 1171
f990b79b
AD		 1172 /* Refresh the desc even if buffer_addrs didn't change
1173 * because each write-back erases this info. */
7d637bcc 1174 if (ring_is_ps_enabled(rx_ring)) {
f990b79b 1175 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
d5f398ed 1176
f990b79b
AD		 1177 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1178 break;
d5f398ed 1179
3a581073 1180 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
9a799d71 1181 } else {
3a581073 1182 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1183 }
1184
f990b79b
AD		 1185 rx_desc++;
1186 bi++;
9a799d71 1187 i++;
f990b79b 1188 if (unlikely(!i)) {
e4f74028 1189 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1190 bi = rx_ring->rx_buffer_info;
1191 i -= rx_ring->count;
1192 }
1193
1194 /* clear the hdr_addr for the next_to_use descriptor */
1195 rx_desc->read.hdr_addr = 0;
9a799d71 1196 }
7c6e0a43 1197
f990b79b
AD		 1198 i += rx_ring->count;
1199
f56e0cb1 1200 if (rx_ring->next_to_use != i)
84ea2591 1201 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1202}
1203
c267fc16 1204static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1205{
c267fc16
AD		 1206 /* HW will not DMA in data larger than the given buffer, even if it
1207 * parses the (NFS, of course) header to be larger. In that case, it
1208 * fills the header buffer and spills the rest into the page.
1209 */
1210 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1211 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1212 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1213 if (hlen > IXGBE_RX_HDR_SIZE)
1214 hlen = IXGBE_RX_HDR_SIZE;
1215 return hlen;
7c6e0a43
JB		 1216}
1217
f8212f97 1218/**
4c1975d7
AD		 1219 * ixgbe_merge_active_tail - merge active tail into lro skb
1220 * @tail: pointer to active tail in frag_list
f8212f97 1221 *
4c1975d7
AD		 1222 * This function merges the length and data of an active tail into the
1223 * skb containing the frag_list. It resets the tail's pointer to the head,
1224 * but it leaves the heads pointer to tail intact.
f8212f97 1225 **/
4c1975d7 1226static inline struct sk_buff *ixgbe_merge_active_tail(struct sk_buff *tail)
f8212f97 1227{
4c1975d7 1228 struct sk_buff *head = IXGBE_CB(tail)->head;
f8212f97 1229
4c1975d7
AD		 1230 if (!head)
1231 return tail;
1232
1233 head->len += tail->len;
1234 head->data_len += tail->len;
1235 head->truesize += tail->len;
1236
1237 IXGBE_CB(tail)->head = NULL;
1238
1239 return head;
1240}
1241
1242/**
1243 * ixgbe_add_active_tail - adds an active tail into the skb frag_list
1244 * @head: pointer to the start of the skb
1245 * @tail: pointer to active tail to add to frag_list
1246 *
1247 * This function adds an active tail to the end of the frag list. This tail
1248 * will still be receiving data so we cannot yet ad it's stats to the main
1249 * skb. That is done via ixgbe_merge_active_tail.
1250 **/
1251static inline void ixgbe_add_active_tail(struct sk_buff *head,
1252 struct sk_buff *tail)
1253{
1254 struct sk_buff *old_tail = IXGBE_CB(head)->tail;
1255
1256 if (old_tail) {
1257 ixgbe_merge_active_tail(old_tail);
1258 old_tail->next = tail;
1259 } else {
1260 skb_shinfo(head)->frag_list = tail;
f8212f97
AD		 1261 }
1262
4c1975d7
AD		 1263 IXGBE_CB(tail)->head = head;
1264 IXGBE_CB(head)->tail = tail;
1265}
1266
1267/**
1268 * ixgbe_close_active_frag_list - cleanup pointers on a frag_list skb
1269 * @head: pointer to head of an active frag list
1270 *
1271 * This function will clear the frag_tail_tracker pointer on an active
1272 * frag_list and returns true if the pointer was actually set
1273 **/
1274static inline bool ixgbe_close_active_frag_list(struct sk_buff *head)
1275{
1276 struct sk_buff *tail = IXGBE_CB(head)->tail;
1277
1278 if (!tail)
1279 return false;
1280
1281 ixgbe_merge_active_tail(tail);
1282
1283 IXGBE_CB(head)->tail = NULL;
aa80175a 1284
4c1975d7 1285 return true;
f8212f97
AD		 1286}
1287
1d2024f6
AD		 1288/**
1289 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1290 * @data: pointer to the start of the headers
1291 * @max_len: total length of section to find headers in
1292 *
1293 * This function is meant to determine the length of headers that will
1294 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1295 * motivation of doing this is to only perform one pull for IPv4 TCP
1296 * packets so that we can do basic things like calculating the gso_size
1297 * based on the average data per packet.
1298 **/
1299static unsigned int ixgbe_get_headlen(unsigned char *data,
1300 unsigned int max_len)
1301{
1302 union {
1303 unsigned char *network;
1304 /* l2 headers */
1305 struct ethhdr *eth;
1306 struct vlan_hdr *vlan;
1307 /* l3 headers */
1308 struct iphdr *ipv4;
1309 } hdr;
1310 __be16 protocol;
1311 u8 nexthdr = 0; /* default to not TCP */
1312 u8 hlen;
1313
1314 /* this should never happen, but better safe than sorry */
1315 if (max_len < ETH_HLEN)
1316 return max_len;
1317
1318 /* initialize network frame pointer */
1319 hdr.network = data;
1320
1321 /* set first protocol and move network header forward */
1322 protocol = hdr.eth->h_proto;
1323 hdr.network += ETH_HLEN;
1324
1325 /* handle any vlan tag if present */
1326 if (protocol == __constant_htons(ETH_P_8021Q)) {
1327 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1328 return max_len;
1329
1330 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1331 hdr.network += VLAN_HLEN;
1332 }
1333
1334 /* handle L3 protocols */
1335 if (protocol == __constant_htons(ETH_P_IP)) {
1336 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1337 return max_len;
1338
1339 /* access ihl as a u8 to avoid unaligned access on ia64 */
1340 hlen = (hdr.network[0] & 0x0F) << 2;
1341
1342 /* verify hlen meets minimum size requirements */
1343 if (hlen < sizeof(struct iphdr))
1344 return hdr.network - data;
1345
1346 /* record next protocol */
1347 nexthdr = hdr.ipv4->protocol;
1348 hdr.network += hlen;
1349#ifdef CONFIG_FCOE
1350 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1351 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1352 return max_len;
1353 hdr.network += FCOE_HEADER_LEN;
1354#endif
1355 } else {
1356 return hdr.network - data;
1357 }
1358
1359 /* finally sort out TCP */
1360 if (nexthdr == IPPROTO_TCP) {
1361 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1362 return max_len;
1363
1364 /* access doff as a u8 to avoid unaligned access on ia64 */
1365 hlen = (hdr.network[12] & 0xF0) >> 2;
1366
1367 /* verify hlen meets minimum size requirements */
1368 if (hlen < sizeof(struct tcphdr))
1369 return hdr.network - data;
1370
1371 hdr.network += hlen;
1372 }
1373
1374 /*
1375 * If everything has gone correctly hdr.network should be the
1376 * data section of the packet and will be the end of the header.
1377 * If not then it probably represents the end of the last recognized
1378 * header.
1379 */
1380 if ((hdr.network - data) < max_len)
1381 return hdr.network - data;
1382 else
1383 return max_len;
1384}
1385
4c1975d7
AD		 1386static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1387 union ixgbe_adv_rx_desc *rx_desc,
1388 struct sk_buff *skb)
aa80175a 1389{
4c1975d7
AD		 1390 __le32 rsc_enabled;
1391 u32 rsc_cnt;
1392
1393 if (!ring_is_rsc_enabled(rx_ring))
1394 return;
1395
1396 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1397 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1398
1399 /* If this is an RSC frame rsc_cnt should be non-zero */
1400 if (!rsc_enabled)
1401 return;
1402
1403 rsc_cnt = le32_to_cpu(rsc_enabled);
1404 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1405
1406 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1407}
43634e82 1408
1d2024f6
AD		 1409static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1410 struct sk_buff *skb)
1411{
1412 u16 hdr_len = ixgbe_get_headlen(skb->data, skb_headlen(skb));
1413
1414 /* set gso_size to avoid messing up TCP MSS */
1415 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1416 IXGBE_CB(skb)->append_cnt);
1417}
1418
1419static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1420 struct sk_buff *skb)
1421{
1422 /* if append_cnt is 0 then frame is not RSC */
1423 if (!IXGBE_CB(skb)->append_cnt)
1424 return;
1425
1426 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1427 rx_ring->rx_stats.rsc_flush++;
1428
1429 ixgbe_set_rsc_gso_size(rx_ring, skb);
1430
1431 /* gso_size is computed using append_cnt so always clear it last */
1432 IXGBE_CB(skb)->append_cnt = 0;
1433}
1434
8a0da21b
AD		 1435/**
1436 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1437 * @rx_ring: rx descriptor ring packet is being transacted on
1438 * @rx_desc: pointer to the EOP Rx descriptor
1439 * @skb: pointer to current skb being populated
f8212f97 1440 *
8a0da21b
AD		 1441 * This function checks the ring, descriptor, and packet information in
1442 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1443 * other fields within the skb.
f8212f97 1444 **/
8a0da21b
AD		 1445static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1446 union ixgbe_adv_rx_desc *rx_desc,
1447 struct sk_buff *skb)
f8212f97 1448{
8a0da21b
AD		 1449 ixgbe_update_rsc_stats(rx_ring, skb);
1450
1451 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1452
8a0da21b
AD		 1453 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1454
1455 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1456 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1457 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1458 }
1459
8a0da21b 1460 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1461
8a0da21b 1462 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
f8212f97
AD		 1463}
1464
8a0da21b
AD		 1465static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1466 struct sk_buff *skb)
aa80175a 1467{
8a0da21b
AD		 1468 struct ixgbe_adapter *adapter = q_vector->adapter;
1469
1470 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1471 napi_gro_receive(&q_vector->napi, skb);
1472 else
1473 netif_rx(skb);
aa80175a 1474}
43634e82 1475
4ff7fb12 1476static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1477 struct ixgbe_ring *rx_ring,
4ff7fb12 1478 int budget)
9a799d71 1479{
9a799d71 1480 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
4c1975d7 1481 struct ixgbe_rx_buffer *rx_buffer_info;
9a799d71 1482 struct sk_buff *skb;
d2f4fbe2 1483 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1484 const int current_node = numa_node_id();
3d8fd385 1485#ifdef IXGBE_FCOE
8a0da21b 1486 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1487 int ddp_bytes = 0;
1488#endif /* IXGBE_FCOE */
c267fc16
AD		 1489 u16 i;
1490 u16 cleaned_count = 0;
9a799d71
AK		 1491
1492 i = rx_ring->next_to_clean;
e4f74028 1493 rx_desc = IXGBE_RX_DESC(rx_ring, i);
9a799d71 1494
f56e0cb1 1495 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
7c6e0a43 1496 u32 upper_len = 0;
9a799d71 1497
3c945e5b 1498 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1499
c267fc16
AD		 1500 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1501
9a799d71 1502 skb = rx_buffer_info->skb;
9a799d71 1503 rx_buffer_info->skb = NULL;
c267fc16 1504 prefetch(skb->data);
9a799d71 1505
b811ce91
JB		 1506 /* linear means we are building an skb from multiple pages */
1507 if (!skb_is_nonlinear(skb)) {
c267fc16 1508 u16 hlen;
c267fc16
AD		 1509 if (ring_is_ps_enabled(rx_ring)) {
1510 hlen = ixgbe_get_hlen(rx_desc);
1511 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1512 } else {
1513 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1514 }
1515
1516 skb_put(skb, hlen);
4c1975d7
AD		 1517
1518 /*
1519 * Delay unmapping of the first packet. It carries the
1520 * header information, HW may still access the header
1521 * after writeback. Only unmap it when EOP is reached
1522 */
1523 if (!IXGBE_CB(skb)->head) {
1524 IXGBE_CB(skb)->delay_unmap = true;
1525 IXGBE_CB(skb)->dma = rx_buffer_info->dma;
1526 } else {
1527 skb = ixgbe_merge_active_tail(skb);
1528 dma_unmap_single(rx_ring->dev,
1529 rx_buffer_info->dma,
1530 rx_ring->rx_buf_len,
1531 DMA_FROM_DEVICE);
1532 }
1533 rx_buffer_info->dma = 0;
c267fc16
AD		 1534 } else {
1535 /* assume packet split since header is unmapped */
1536 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1537 }
1538
1539 if (upper_len) {
b6ec895e
AD		 1540 dma_unmap_page(rx_ring->dev,
1541 rx_buffer_info->page_dma,
1542 PAGE_SIZE / 2,
1543 DMA_FROM_DEVICE);
9a799d71
AK		 1544 rx_buffer_info->page_dma = 0;
1545 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1546 rx_buffer_info->page,
1547 rx_buffer_info->page_offset,
1548 upper_len);
762f4c57 1549
c267fc16
AD		 1550 if ((page_count(rx_buffer_info->page) == 1) &&
1551 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1552 get_page(rx_buffer_info->page);
c267fc16
AD		 1553 else
1554 rx_buffer_info->page = NULL;
9a799d71
AK		 1555
1556 skb->len += upper_len;
1557 skb->data_len += upper_len;
98130646 1558 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1559 }
1560
4c1975d7
AD		 1561 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1562
9a799d71
AK		 1563 i++;
1564 if (i == rx_ring->count)
1565 i = 0;
9a799d71 1566
e4f74028 1567 next_rxd = IXGBE_RX_DESC(rx_ring, i);
9a799d71 1568 prefetch(next_rxd);
9a799d71 1569 cleaned_count++;
f8212f97 1570
f56e0cb1 1571 if ((!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) {
4c1975d7
AD		 1572 struct ixgbe_rx_buffer *next_buffer;
1573 u32 nextp;
1574
1575 if (IXGBE_CB(skb)->append_cnt) {
f56e0cb1
AD		 1576 nextp = le32_to_cpu(
1577 rx_desc->wb.upper.status_error);
4c1975d7
AD		 1578 nextp >>= IXGBE_RXDADV_NEXTP_SHIFT;
1579 } else {
1580 nextp = i;
1581 }
1582
f8212f97 1583 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97 1584
7d637bcc 1585 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1586 rx_buffer_info->skb = next_buffer->skb;
1587 rx_buffer_info->dma = next_buffer->dma;
1588 next_buffer->skb = skb;
1589 next_buffer->dma = 0;
1590 } else {
4c1975d7
AD		 1591 struct sk_buff *next_skb = next_buffer->skb;
1592 ixgbe_add_active_tail(skb, next_skb);
1593 IXGBE_CB(next_skb)->head = skb;
f8212f97 1594 }
5b7da515 1595 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1596 goto next_desc;
1597 }
1598
4c1975d7
AD		 1599 dma_unmap_single(rx_ring->dev,
1600 IXGBE_CB(skb)->dma,
1601 rx_ring->rx_buf_len,
1602 DMA_FROM_DEVICE);
1603 IXGBE_CB(skb)->dma = 0;
1604 IXGBE_CB(skb)->delay_unmap = false;
c267fc16 1605
4c1975d7
AD		 1606 if (ixgbe_close_active_frag_list(skb) &&
1607 !IXGBE_CB(skb)->append_cnt) {
aa80175a 1608 /* if we got here without RSC the packet is invalid */
4c1975d7
AD		 1609 dev_kfree_skb_any(skb);
1610 goto next_desc;
c267fc16
AD		 1611 }
1612
1613 /* ERR_MASK will only have valid bits if EOP set */
f56e0cb1
AD		 1614 if (unlikely(ixgbe_test_staterr(rx_desc,
1615 IXGBE_RXDADV_ERR_FRAME_ERR_MASK))) {
ff886dfc 1616 dev_kfree_skb_any(skb);
9a799d71
AK		 1617 goto next_desc;
1618 }
1619
d2f4fbe2
AV		 1620 /* probably a little skewed due to removing CRC */
1621 total_rx_bytes += skb->len;
1622 total_rx_packets++;
1623
8a0da21b
AD		 1624 /* populate checksum, timestamp, VLAN, and protocol */
1625 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1626
332d4a7d
YZ		 1627#ifdef IXGBE_FCOE
1628 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc 1629 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
f56e0cb1 1630 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1631 if (!ddp_bytes) {
1632 dev_kfree_skb_any(skb);
332d4a7d 1633 goto next_desc;
63d635b2 1634 }
3d8fd385 1635 }
332d4a7d 1636#endif /* IXGBE_FCOE */
8a0da21b 1637 ixgbe_rx_skb(q_vector, skb);
9a799d71 1638
4ff7fb12 1639 budget--;
9a799d71 1640next_desc:
4ff7fb12 1641 if (!budget)
c267fc16
AD		 1642 break;
1643
9a799d71
AK		 1644 /* return some buffers to hardware, one at a time is too slow */
1645 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1646 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1647 cleaned_count = 0;
1648 }
1649
1650 /* use prefetched values */
1651 rx_desc = next_rxd;
177db6ff
MC		 1652 }
1653
9a799d71 1654 rx_ring->next_to_clean = i;
7d4987de 1655 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1656
1657 if (cleaned_count)
fc77dc3c 1658 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1659
3d8fd385
YZ		 1660#ifdef IXGBE_FCOE
1661 /* include DDPed FCoE data */
1662 if (ddp_bytes > 0) {
1663 unsigned int mss;
1664
fc77dc3c 1665 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1666 sizeof(struct fc_frame_header) -
1667 sizeof(struct fcoe_crc_eof);
1668 if (mss > 512)
1669 mss &= ~511;
1670 total_rx_bytes += ddp_bytes;
1671 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1672 }
1673#endif /* IXGBE_FCOE */
1674
c267fc16
AD		 1675 u64_stats_update_begin(&rx_ring->syncp);
1676 rx_ring->stats.packets += total_rx_packets;
1677 rx_ring->stats.bytes += total_rx_bytes;
1678 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1679 q_vector->rx.total_packets += total_rx_packets;
1680 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1681
1682 return !!budget;
9a799d71
AK		 1683}
1684
9a799d71
AK		 1685/**
1686 * ixgbe_configure_msix - Configure MSI-X hardware
1687 * @adapter: board private structure
1688 *
1689 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1690 * interrupts.
1691 **/
1692static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1693{
021230d4 1694 struct ixgbe_q_vector *q_vector;
efe3d3c8 1695 int q_vectors, v_idx;
021230d4 1696 u32 mask;
9a799d71 1697
021230d4 1698 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1699
8e34d1aa
AD		 1700 /* Populate MSIX to EITR Select */
1701 if (adapter->num_vfs > 32) {
1702 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1703 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1704 }
1705
4df10466
JB		 1706 /*
1707 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1708 * corresponding register.
1709 */
1710 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1711 struct ixgbe_ring *ring;
7a921c93 1712 q_vector = adapter->q_vector[v_idx];
021230d4 1713
a557928e 1714 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1715 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1716
a557928e 1717 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1718 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1719
d5bf4f67
ET		 1720 if (q_vector->tx.ring && !q_vector->rx.ring) {
1721 /* tx only vector */
1722 if (adapter->tx_itr_setting == 1)
1723 q_vector->itr = IXGBE_10K_ITR;
1724 else
1725 q_vector->itr = adapter->tx_itr_setting;
1726 } else {
1727 /* rx or rx/tx vector */
1728 if (adapter->rx_itr_setting == 1)
1729 q_vector->itr = IXGBE_20K_ITR;
1730 else
1731 q_vector->itr = adapter->rx_itr_setting;
1732 }
021230d4 1733
fe49f04a 1734 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1735 }
1736
bd508178
AD		 1737 switch (adapter->hw.mac.type) {
1738 case ixgbe_mac_82598EB:
e8e26350 1739 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1740 v_idx);
bd508178
AD		 1741 break;
1742 case ixgbe_mac_82599EB:
b93a2226 1743 case ixgbe_mac_X540:
e8e26350 1744 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1745 break;
bd508178
AD		 1746 default:
1747 break;
1748 }
021230d4
AV		 1749 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1750
41fb9248 1751 /* set up to autoclear timer, and the vectors */
021230d4 1752 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1753 mask &= ~(IXGBE_EIMS_OTHER |
1754 IXGBE_EIMS_MAILBOX |
1755 IXGBE_EIMS_LSC);
1756
021230d4 1757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1758}
1759
f494e8fa
AV		 1760enum latency_range {
1761 lowest_latency = 0,
1762 low_latency = 1,
1763 bulk_latency = 2,
1764 latency_invalid = 255
1765};
1766
1767/**
1768 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1769 * @q_vector: structure containing interrupt and ring information
1770 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1771 *
1772 * Stores a new ITR value based on packets and byte
1773 * counts during the last interrupt. The advantage of per interrupt
1774 * computation is faster updates and more accurate ITR for the current
1775 * traffic pattern. Constants in this function were computed
1776 * based on theoretical maximum wire speed and thresholds were set based
1777 * on testing data as well as attempting to minimize response time
1778 * while increasing bulk throughput.
1779 * this functionality is controlled by the InterruptThrottleRate module
1780 * parameter (see ixgbe_param.c)
1781 **/
bd198058
AD		 1782static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1783 struct ixgbe_ring_container *ring_container)
f494e8fa 1784{
bd198058
AD		 1785 int bytes = ring_container->total_bytes;
1786 int packets = ring_container->total_packets;
1787 u32 timepassed_us;
621bd70e 1788 u64 bytes_perint;
bd198058 1789 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1790
1791 if (packets == 0)
bd198058 1792 return;
f494e8fa
AV		 1793
1794 /* simple throttlerate management
621bd70e
AD		 1795 * 0-10MB/s lowest (100000 ints/s)
1796 * 10-20MB/s low (20000 ints/s)
1797 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1798 */
1799 /* what was last interrupt timeslice? */
d5bf4f67 1800 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1801 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1802
1803 switch (itr_setting) {
1804 case lowest_latency:
621bd70e 1805 if (bytes_perint > 10)
bd198058 1806 itr_setting = low_latency;
f494e8fa
AV		 1807 break;
1808 case low_latency:
621bd70e 1809 if (bytes_perint > 20)
bd198058 1810 itr_setting = bulk_latency;
621bd70e 1811 else if (bytes_perint <= 10)
bd198058 1812 itr_setting = lowest_latency;
f494e8fa
AV		 1813 break;
1814 case bulk_latency:
621bd70e 1815 if (bytes_perint <= 20)
bd198058 1816 itr_setting = low_latency;
f494e8fa
AV		 1817 break;
1818 }
1819
bd198058
AD		 1820 /* clear work counters since we have the values we need */
1821 ring_container->total_bytes = 0;
1822 ring_container->total_packets = 0;
1823
1824 /* write updated itr to ring container */
1825 ring_container->itr = itr_setting;
f494e8fa
AV		 1826}
1827
509ee935
JB		 1828/**
1829 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1830 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1831 *
1832 * This function is made to be called by ethtool and by the driver
1833 * when it needs to update EITR registers at runtime. Hardware
1834 * specific quirks/differences are taken care of here.
1835 */
fe49f04a 1836void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1837{
fe49f04a 1838 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1839 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1840 int v_idx = q_vector->v_idx;
5d967eb7 1841 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 1842
bd508178
AD		 1843 switch (adapter->hw.mac.type) {
1844 case ixgbe_mac_82598EB:
509ee935
JB		 1845 /* must write high and low 16 bits to reset counter */
1846 itr_reg |= (itr_reg << 16);
bd508178
AD		 1847 break;
1848 case ixgbe_mac_82599EB:
b93a2226 1849 case ixgbe_mac_X540:
509ee935
JB		 1850 /*
1851 * set the WDIS bit to not clear the timer bits and cause an
1852 * immediate assertion of the interrupt
1853 */
1854 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1855 break;
1856 default:
1857 break;
509ee935
JB		 1858 }
1859 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1860}
1861
bd198058 1862static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1863{
d5bf4f67 1864 u32 new_itr = q_vector->itr;
bd198058 1865 u8 current_itr;
f494e8fa 1866
bd198058
AD		 1867 ixgbe_update_itr(q_vector, &q_vector->tx);
1868 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1869
08c8833b 1870 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1871
1872 switch (current_itr) {
1873 /* counts and packets in update_itr are dependent on these numbers */
1874 case lowest_latency:
d5bf4f67 1875 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1876 break;
1877 case low_latency:
d5bf4f67 1878 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1879 break;
1880 case bulk_latency:
d5bf4f67 1881 new_itr = IXGBE_8K_ITR;
f494e8fa 1882 break;
bd198058
AD		 1883 default:
1884 break;
f494e8fa
AV		 1885 }
1886
d5bf4f67 1887 if (new_itr != q_vector->itr) {
fe49f04a 1888 /* do an exponential smoothing */
d5bf4f67
ET		 1889 new_itr = (10 * new_itr * q_vector->itr) /
1890 ((9 * new_itr) + q_vector->itr);
509ee935 1891
bd198058 1892 /* save the algorithm value here */
5d967eb7 1893 q_vector->itr = new_itr;
fe49f04a
AD		 1894
1895 ixgbe_write_eitr(q_vector);
f494e8fa 1896 }
f494e8fa
AV		 1897}
1898
119fc60a 1899/**
de88eeeb 1900 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 1901 * @adapter: pointer to adapter
119fc60a 1902 **/
f0f9778d 1903static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1904{
119fc60a
MC		 1905 struct ixgbe_hw *hw = &adapter->hw;
1906 u32 eicr = adapter->interrupt_event;
1907
f0f9778d 1908 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1909 return;
1910
f0f9778d
AD		 1911 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1912 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1913 return;
1914
1915 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1916
7ca647bd 1917 switch (hw->device_id) {
f0f9778d
AD		 1918 case IXGBE_DEV_ID_82599_T3_LOM:
1919 /*
1920 * Since the warning interrupt is for both ports
1921 * we don't have to check if:
1922 * - This interrupt wasn't for our port.
1923 * - We may have missed the interrupt so always have to
1924 * check if we got a LSC
1925 */
1926 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1927 !(eicr & IXGBE_EICR_LSC))
1928 return;
1929
1930 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1931 u32 autoneg;
1932 bool link_up = false;
7ca647bd 1933
7ca647bd
JP		 1934 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1935
f0f9778d
AD		 1936 if (link_up)
1937 return;
1938 }
1939
1940 /* Check if this is not due to overtemp */
1941 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1942 return;
1943
1944 break;
7ca647bd
JP		 1945 default:
1946 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1947 return;
7ca647bd 1948 break;
119fc60a 1949 }
7ca647bd
JP		 1950 e_crit(drv,
1951 "Network adapter has been stopped because it has over heated. "
1952 "Restart the computer. If the problem persists, "
1953 "power off the system and replace the adapter\n");
f0f9778d
AD		 1954
1955 adapter->interrupt_event = 0;
119fc60a
MC		 1956}
1957
0befdb3e
JB		 1958static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1959{
1960 struct ixgbe_hw *hw = &adapter->hw;
1961
1962 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1963 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1964 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1965 /* write to clear the interrupt */
1966 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1967 }
1968}
cf8280ee 1969
4f51bf70
JK		 1970static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1971{
1972 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1973 return;
1974
1975 switch (adapter->hw.mac.type) {
1976 case ixgbe_mac_82599EB:
1977 /*
1978 * Need to check link state so complete overtemp check
1979 * on service task
1980 */
1981 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1982 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1983 adapter->interrupt_event = eicr;
1984 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1985 ixgbe_service_event_schedule(adapter);
1986 return;
1987 }
1988 return;
1989 case ixgbe_mac_X540:
1990 if (!(eicr & IXGBE_EICR_TS))
1991 return;
1992 break;
1993 default:
1994 return;
1995 }
1996
1997 e_crit(drv,
1998 "Network adapter has been stopped because it has over heated. "
1999 "Restart the computer. If the problem persists, "
2000 "power off the system and replace the adapter\n");
2001}
2002
e8e26350
PW		 2003static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2004{
2005 struct ixgbe_hw *hw = &adapter->hw;
2006
73c4b7cd
AD		 2007 if (eicr & IXGBE_EICR_GPI_SDP2) {
2008 /* Clear the interrupt */
2009 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2010 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2011 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2012 ixgbe_service_event_schedule(adapter);
2013 }
73c4b7cd
AD		 2014 }
2015
e8e26350
PW		 2016 if (eicr & IXGBE_EICR_GPI_SDP1) {
2017 /* Clear the interrupt */
2018 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2019 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2020 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2021 ixgbe_service_event_schedule(adapter);
2022 }
e8e26350
PW		 2023 }
2024}
2025
cf8280ee
JB		 2026static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2027{
2028 struct ixgbe_hw *hw = &adapter->hw;
2029
2030 adapter->lsc_int++;
2031 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2032 adapter->link_check_timeout = jiffies;
2033 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2034 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2035 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2036 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2037 }
2038}
2039
fe49f04a
AD		 2040static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2041 u64 qmask)
2042{
2043 u32 mask;
bd508178 2044 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2045
bd508178
AD		 2046 switch (hw->mac.type) {
2047 case ixgbe_mac_82598EB:
fe49f04a 2048 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2049 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2050 break;
2051 case ixgbe_mac_82599EB:
b93a2226 2052 case ixgbe_mac_X540:
fe49f04a 2053 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2054 if (mask)
2055 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2056 mask = (qmask >> 32);
bd508178
AD		 2057 if (mask)
2058 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2059 break;
2060 default:
2061 break;
fe49f04a
AD		 2062 }
2063 /* skip the flush */
2064}
2065
2066static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2067 u64 qmask)
fe49f04a
AD		 2068{
2069 u32 mask;
bd508178 2070 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2071
bd508178
AD		 2072 switch (hw->mac.type) {
2073 case ixgbe_mac_82598EB:
fe49f04a 2074 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2075 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2076 break;
2077 case ixgbe_mac_82599EB:
b93a2226 2078 case ixgbe_mac_X540:
fe49f04a 2079 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2080 if (mask)
2081 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2082 mask = (qmask >> 32);
bd508178
AD		 2083 if (mask)
2084 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2085 break;
2086 default:
2087 break;
fe49f04a
AD		 2088 }
2089 /* skip the flush */
2090}
2091
021230d4 2092/**
2c4af694
AD		 2093 * ixgbe_irq_enable - Enable default interrupt generation settings
2094 * @adapter: board private structure
021230d4 2095 **/
2c4af694
AD		 2096static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2097 bool flush)
9a799d71 2098{
2c4af694 2099 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2100
2c4af694
AD		 2101 /* don't reenable LSC while waiting for link */
2102 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2103 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2104
2c4af694 2105 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2106 switch (adapter->hw.mac.type) {
2107 case ixgbe_mac_82599EB:
2108 mask |= IXGBE_EIMS_GPI_SDP0;
2109 break;
2110 case ixgbe_mac_X540:
2111 mask |= IXGBE_EIMS_TS;
2112 break;
2113 default:
2114 break;
2115 }
2c4af694
AD		 2116 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2117 mask |= IXGBE_EIMS_GPI_SDP1;
2118 switch (adapter->hw.mac.type) {
2119 case ixgbe_mac_82599EB:
2c4af694
AD		 2120 mask |= IXGBE_EIMS_GPI_SDP1;
2121 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2122 case ixgbe_mac_X540:
2123 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2124 mask |= IXGBE_EIMS_MAILBOX;
2125 break;
2126 default:
2127 break;
9a799d71 2128 }
2c4af694
AD		 2129 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2130 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2131 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2132
2c4af694
AD		 2133 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2134 if (queues)
2135 ixgbe_irq_enable_queues(adapter, ~0);
2136 if (flush)
2137 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2138}
2139
2c4af694 2140static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2141{
a65151ba 2142 struct ixgbe_adapter *adapter = data;
9a799d71 2143 struct ixgbe_hw *hw = &adapter->hw;
54037505 2144 u32 eicr;
91281fd3 2145
54037505
DS		 2146 /*
2147 * Workaround for Silicon errata. Use clear-by-write instead
2148 * of clear-by-read. Reading with EICS will return the
2149 * interrupt causes without clearing, which later be done
2150 * with the write to EICR.
2151 */
2152 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2153 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2154
cf8280ee
JB		 2155 if (eicr & IXGBE_EICR_LSC)
2156 ixgbe_check_lsc(adapter);
f0848276 2157
1cdd1ec8
GR		 2158 if (eicr & IXGBE_EICR_MAILBOX)
2159 ixgbe_msg_task(adapter);
efe3d3c8 2160
bd508178
AD		 2161 switch (hw->mac.type) {
2162 case ixgbe_mac_82599EB:
b93a2226 2163 case ixgbe_mac_X540:
2c4af694
AD		 2164 if (eicr & IXGBE_EICR_ECC)
2165 e_info(link, "Received unrecoverable ECC Err, please "
2166 "reboot\n");
c4cf55e5
PWJ		 2167 /* Handle Flow Director Full threshold interrupt */
2168 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2169 int reinit_count = 0;
c4cf55e5 2170 int i;
c4cf55e5 2171 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2172 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2173 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2174 &ring->state))
2175 reinit_count++;
2176 }
2177 if (reinit_count) {
2178 /* no more flow director interrupts until after init */
2179 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2180 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2181 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2182 }
2183 }
f0f9778d 2184 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2185 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2186 break;
2187 default:
2188 break;
c4cf55e5 2189 }
f0848276 2190
bd508178 2191 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 2192
7086400d 2193 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2194 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2195 ixgbe_irq_enable(adapter, false, false);
f0848276 2196
9a799d71 2197 return IRQ_HANDLED;
f0848276 2198}
91281fd3 2199
4ff7fb12 2200static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2201{
021230d4 2202 struct ixgbe_q_vector *q_vector = data;
91281fd3 2203
9b471446 2204 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2205
4ff7fb12
AD		 2206 if (q_vector->rx.ring || q_vector->tx.ring)
2207 napi_schedule(&q_vector->napi);
91281fd3 2208
9a799d71 2209 return IRQ_HANDLED;
91281fd3
AD		 2210}
2211
021230d4
AV		 2212/**
2213 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2214 * @adapter: board private structure
2215 *
2216 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2217 * interrupts from the kernel.
2218 **/
2219static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2220{
2221 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2222 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2223 int vector, err;
e8e9f696 2224 int ri = 0, ti = 0;
021230d4 2225
021230d4 2226 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2227 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2228 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2229
4ff7fb12 2230 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2231 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2232 "%s-%s-%d", netdev->name, "TxRx", ri++);
2233 ti++;
2234 } else if (q_vector->rx.ring) {
9fe93afd 2235 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2236 "%s-%s-%d", netdev->name, "rx", ri++);
2237 } else if (q_vector->tx.ring) {
9fe93afd 2238 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2239 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2240 } else {
2241 /* skip this unused q_vector */
2242 continue;
32aa77a4 2243 }
207867f5
AD		 2244 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2245 q_vector->name, q_vector);
9a799d71 2246 if (err) {
396e799c 2247 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2248 "Error: %d\n", err);
021230d4 2249 goto free_queue_irqs;
9a799d71 2250 }
207867f5
AD		 2251 /* If Flow Director is enabled, set interrupt affinity */
2252 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2253 /* assign the mask for this irq */
2254 irq_set_affinity_hint(entry->vector,
de88eeeb 2255 &q_vector->affinity_mask);
207867f5 2256 }
9a799d71
AK		 2257 }
2258
021230d4 2259 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2260 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2261 if (err) {
de88eeeb 2262 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2263 goto free_queue_irqs;
9a799d71
AK		 2264 }
2265
9a799d71
AK		 2266 return 0;
2267
021230d4 2268free_queue_irqs:
207867f5
AD		 2269 while (vector) {
2270 vector--;
2271 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2272 NULL);
2273 free_irq(adapter->msix_entries[vector].vector,
2274 adapter->q_vector[vector]);
2275 }
021230d4
AV		 2276 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2277 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2278 kfree(adapter->msix_entries);
2279 adapter->msix_entries = NULL;
9a799d71
AK		 2280 return err;
2281}
2282
2283/**
021230d4 2284 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2285 * @irq: interrupt number
2286 * @data: pointer to a network interface device structure
9a799d71
AK		 2287 **/
2288static irqreturn_t ixgbe_intr(int irq, void *data)
2289{
a65151ba 2290 struct ixgbe_adapter *adapter = data;
9a799d71 2291 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2292 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2293 u32 eicr;
2294
54037505 2295 /*
24ddd967 2296 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2297 * before the read of EICR.
2298 */
2299 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2300
021230d4 2301 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2302 * therefore no explicit interrupt disable is necessary */
021230d4 2303 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2304 if (!eicr) {
6af3b9eb
ET		 2305 /*
2306 * shared interrupt alert!
f47cf66e 2307 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2308 * have disabled interrupts due to EIAM
2309 * finish the workaround of silicon errata on 82598. Unmask
2310 * the interrupt that we masked before the EICR read.
2311 */
2312 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2313 ixgbe_irq_enable(adapter, true, true);
9a799d71 2314 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2315 }
9a799d71 2316
cf8280ee
JB		 2317 if (eicr & IXGBE_EICR_LSC)
2318 ixgbe_check_lsc(adapter);
021230d4 2319
bd508178
AD		 2320 switch (hw->mac.type) {
2321 case ixgbe_mac_82599EB:
e8e26350 2322 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2323 /* Fall through */
2324 case ixgbe_mac_X540:
2325 if (eicr & IXGBE_EICR_ECC)
2326 e_info(link, "Received unrecoverable ECC err, please "
2327 "reboot\n");
4f51bf70 2328 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2329 break;
2330 default:
2331 break;
2332 }
e8e26350 2333
0befdb3e
JB		 2334 ixgbe_check_fan_failure(adapter, eicr);
2335
b9f6ed2b
AD		 2336 /* would disable interrupts here but EIAM disabled it */
2337 napi_schedule(&q_vector->napi);
9a799d71 2338
6af3b9eb
ET		 2339 /*
2340 * re-enable link(maybe) and non-queue interrupts, no flush.
2341 * ixgbe_poll will re-enable the queue interrupts
2342 */
6af3b9eb
ET		 2343 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2344 ixgbe_irq_enable(adapter, false, false);
2345
9a799d71
AK		 2346 return IRQ_HANDLED;
2347}
2348
2349/**
2350 * ixgbe_request_irq - initialize interrupts
2351 * @adapter: board private structure
2352 *
2353 * Attempts to configure interrupts using the best available
2354 * capabilities of the hardware and kernel.
2355 **/
021230d4 2356static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2357{
2358 struct net_device *netdev = adapter->netdev;
021230d4 2359 int err;
9a799d71 2360
4cc6df29 2361 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2362 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2363 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2364 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2365 netdev->name, adapter);
4cc6df29 2366 else
a0607fd3 2367 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2368 netdev->name, adapter);
9a799d71 2369
de88eeeb 2370 if (err)
396e799c 2371 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2372
9a799d71
AK		 2373 return err;
2374}
2375
2376static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2377{
9a799d71 2378 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2379 int i, q_vectors;
9a799d71 2380
021230d4 2381 q_vectors = adapter->num_msix_vectors;
021230d4 2382 i = q_vectors - 1;
a65151ba 2383 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2384 i--;
4cc6df29 2385
021230d4 2386 for (; i >= 0; i--) {
894ff7cf 2387 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2388 if (!adapter->q_vector[i]->rx.ring &&
2389 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2390 continue;
2391
207867f5
AD		 2392 /* clear the affinity_mask in the IRQ descriptor */
2393 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2394 NULL);
2395
021230d4 2396 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2397 adapter->q_vector[i]);
021230d4 2398 }
021230d4 2399 } else {
a65151ba 2400 free_irq(adapter->pdev->irq, adapter);
9a799d71
AK		 2401 }
2402}
2403
22d5a71b
JB		 2404/**
2405 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2406 * @adapter: board private structure
2407 **/
2408static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2409{
bd508178
AD		 2410 switch (adapter->hw.mac.type) {
2411 case ixgbe_mac_82598EB:
835462fc 2412 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2413 break;
2414 case ixgbe_mac_82599EB:
b93a2226 2415 case ixgbe_mac_X540:
835462fc
NS		 2416 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2417 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2418 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2419 break;
2420 default:
2421 break;
22d5a71b
JB		 2422 }
2423 IXGBE_WRITE_FLUSH(&adapter->hw);
2424 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2425 int i;
2426 for (i = 0; i < adapter->num_msix_vectors; i++)
2427 synchronize_irq(adapter->msix_entries[i].vector);
2428 } else {
2429 synchronize_irq(adapter->pdev->irq);
2430 }
2431}
2432
9a799d71
AK		 2433/**
2434 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2435 *
2436 **/
2437static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2438{
d5bf4f67 2439 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2440
d5bf4f67
ET		 2441 /* rx/tx vector */
2442 if (adapter->rx_itr_setting == 1)
2443 q_vector->itr = IXGBE_20K_ITR;
2444 else
2445 q_vector->itr = adapter->rx_itr_setting;
2446
2447 ixgbe_write_eitr(q_vector);
9a799d71 2448
e8e26350
PW		 2449 ixgbe_set_ivar(adapter, 0, 0, 0);
2450 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2451
396e799c 2452 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2453}
2454
43e69bf0
AD		 2455/**
2456 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2457 * @adapter: board private structure
2458 * @ring: structure containing ring specific data
2459 *
2460 * Configure the Tx descriptor ring after a reset.
2461 **/
84418e3b
AD		 2462void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2463 struct ixgbe_ring *ring)
43e69bf0
AD		 2464{
2465 struct ixgbe_hw *hw = &adapter->hw;
2466 u64 tdba = ring->dma;
2f1860b8 2467 int wait_loop = 10;
b88c6de2 2468 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2469 u8 reg_idx = ring->reg_idx;
43e69bf0 2470
2f1860b8 2471 /* disable queue to avoid issues while updating state */
b88c6de2 2472 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2473 IXGBE_WRITE_FLUSH(hw);
2474
43e69bf0 2475 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2476 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2477 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2478 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2479 ring->count * sizeof(union ixgbe_adv_tx_desc));
2480 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2481 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2482 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2483
b88c6de2
AD		 2484 /*
2485 * set WTHRESH to encourage burst writeback, it should not be set
2486 * higher than 1 when ITR is 0 as it could cause false TX hangs
2487 *
2488 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2489 * to or less than the number of on chip descriptors, which is
2490 * currently 40.
2491 */
e954b374 2492 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2493 txdctl |= (1 << 16); /* WTHRESH = 1 */
2494 else
2495 txdctl |= (8 << 16); /* WTHRESH = 8 */
2496
e954b374
AD		 2497 /*
2498 * Setting PTHRESH to 32 both improves performance
2499 * and avoids a TX hang with DFP enabled
2500 */
b88c6de2
AD		 2501 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2502 32; /* PTHRESH = 32 */
2f1860b8
AD		 2503
2504 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2505 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2506 adapter->atr_sample_rate) {
2507 ring->atr_sample_rate = adapter->atr_sample_rate;
2508 ring->atr_count = 0;
2509 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2510 } else {
2511 ring->atr_sample_rate = 0;
2512 }
2f1860b8 2513
c84d324c
JF		 2514 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2515
2f1860b8 2516 /* enable queue */
2f1860b8
AD		 2517 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2518
b2d96e0a
AD		 2519 netdev_tx_reset_queue(txring_txq(ring));
2520
2f1860b8
AD		 2521 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2522 if (hw->mac.type == ixgbe_mac_82598EB &&
2523 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2524 return;
2525
2526 /* poll to verify queue is enabled */
2527 do {
032b4325 2528 usleep_range(1000, 2000);
2f1860b8
AD		 2529 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2530 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2531 if (!wait_loop)
2532 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2533}
2534
120ff942
AD		 2535static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2536{
2537 struct ixgbe_hw *hw = &adapter->hw;
2538 u32 rttdcs;
72a32f1f 2539 u32 reg;
8b1c0b24 2540 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2541
2542 if (hw->mac.type == ixgbe_mac_82598EB)
2543 return;
2544
2545 /* disable the arbiter while setting MTQC */
2546 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2547 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2548 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2549
2550 /* set transmit pool layout */
8b1c0b24 2551 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2552 case (IXGBE_FLAG_SRIOV_ENABLED):
2553 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2554 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2555 break;
8b1c0b24
JF		 2556 default:
2557 if (!tcs)
2558 reg = IXGBE_MTQC_64Q_1PB;
2559 else if (tcs <= 4)
2560 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2561 else
2562 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2563
8b1c0b24 2564 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2565
8b1c0b24
JF		 2566 /* Enable Security TX Buffer IFG for multiple pb */
2567 if (tcs) {
2568 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2569 reg |= IXGBE_SECTX_DCB;
2570 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2571 }
120ff942
AD		 2572 break;
2573 }
2574
2575 /* re-enable the arbiter */
2576 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2577 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2578}
2579
9a799d71 2580/**
3a581073 2581 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2582 * @adapter: board private structure
2583 *
2584 * Configure the Tx unit of the MAC after a reset.
2585 **/
2586static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2587{
2f1860b8
AD		 2588 struct ixgbe_hw *hw = &adapter->hw;
2589 u32 dmatxctl;
43e69bf0 2590 u32 i;
9a799d71 2591
2f1860b8
AD		 2592 ixgbe_setup_mtqc(adapter);
2593
2594 if (hw->mac.type != ixgbe_mac_82598EB) {
2595 /* DMATXCTL.EN must be before Tx queues are enabled */
2596 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2597 dmatxctl |= IXGBE_DMATXCTL_TE;
2598 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2599 }
2600
9a799d71 2601 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2602 for (i = 0; i < adapter->num_tx_queues; i++)
2603 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2604}
2605
e8e26350 2606#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2607
a6616b42 2608static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2609 struct ixgbe_ring *rx_ring)
cc41ac7c 2610{
cc41ac7c 2611 u32 srrctl;
bf29ee6c 2612 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2613
bd508178
AD		 2614 switch (adapter->hw.mac.type) {
2615 case ixgbe_mac_82598EB: {
2616 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2617 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2618 reg_idx = reg_idx & mask;
cc41ac7c 2619 }
bd508178
AD		 2620 break;
2621 case ixgbe_mac_82599EB:
b93a2226 2622 case ixgbe_mac_X540:
bd508178
AD		 2623 default:
2624 break;
2625 }
2626
bf29ee6c 2627 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2628
2629 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2630 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2631 if (adapter->num_vfs)
2632 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2633
afafd5b0
AD		 2634 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2635 IXGBE_SRRCTL_BSIZEHDR_MASK;
2636
7d637bcc 2637 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2638#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2639 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2640#else
2641 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2642#endif
cc41ac7c 2643 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2644 } else {
afafd5b0
AD		 2645 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2646 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2647 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2648 }
e8e26350 2649
bf29ee6c 2650 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2651}
9a799d71 2652
05abb126 2653static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2654{
05abb126
AD		 2655 struct ixgbe_hw *hw = &adapter->hw;
2656 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2657 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2658 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2659 u32 mrqc = 0, reta = 0;
2660 u32 rxcsum;
2661 int i, j;
8b1c0b24 2662 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2663 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2664
2665 if (tcs)
2666 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2667
05abb126
AD		 2668 /* Fill out hash function seeds */
2669 for (i = 0; i < 10; i++)
2670 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2671
2672 /* Fill out redirection table */
2673 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2674 if (j == maxq)
05abb126
AD		 2675 j = 0;
2676 /* reta = 4-byte sliding window of
2677 * 0x00..(indices-1)(indices-1)00..etc. */
2678 reta = (reta << 8) | (j * 0x11);
2679 if ((i & 3) == 3)
2680 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2681 }
0cefafad 2682
05abb126
AD		 2683 /* Disable indicating checksum in descriptor, enables RSS hash */
2684 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2685 rxcsum |= IXGBE_RXCSUM_PCSD;
2686 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2687
8b1c0b24
JF		 2688 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2689 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2690 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2691 } else {
2692 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2693 | IXGBE_FLAG_SRIOV_ENABLED);
2694
2695 switch (mask) {
2696 case (IXGBE_FLAG_RSS_ENABLED):
2697 if (!tcs)
2698 mrqc = IXGBE_MRQC_RSSEN;
2699 else if (tcs <= 4)
2700 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2701 else
2702 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2703 break;
2704 case (IXGBE_FLAG_SRIOV_ENABLED):
2705 mrqc = IXGBE_MRQC_VMDQEN;
2706 break;
2707 default:
2708 break;
2709 }
0cefafad
JB		 2710 }
2711
05abb126
AD		 2712 /* Perform hash on these packet types */
2713 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2714 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2715 | IXGBE_MRQC_RSS_FIELD_IPV6
2716 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2717
2718 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2719}
2720
bb5a9ad2
NS		 2721/**
2722 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2723 * @adapter: address of board private structure
2724 * @index: index of ring to set
bb5a9ad2 2725 **/
082757af 2726static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2727 struct ixgbe_ring *ring)
bb5a9ad2 2728{
bb5a9ad2 2729 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2730 u32 rscctrl;
edd2ea55 2731 int rx_buf_len;
bf29ee6c 2732 u8 reg_idx = ring->reg_idx;
7367096a 2733
7d637bcc 2734 if (!ring_is_rsc_enabled(ring))
7367096a 2735 return;
bb5a9ad2 2736
7367096a
AD		 2737 rx_buf_len = ring->rx_buf_len;
2738 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2739 rscctrl |= IXGBE_RSCCTL_RSCEN;
2740 /*
2741 * we must limit the number of descriptors so that the
2742 * total size of max desc * buf_len is not greater
642c680e 2743 * than 65536
bb5a9ad2 2744 */
7d637bcc 2745 if (ring_is_ps_enabled(ring)) {
642c680e 2746#if (PAGE_SIZE < 8192)
bb5a9ad2 2747 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
642c680e 2748#elif (PAGE_SIZE < 16384)
bb5a9ad2 2749 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
642c680e 2750#elif (PAGE_SIZE < 32768)
bb5a9ad2
NS		 2751 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2752#else
2753 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2754#endif
2755 } else {
642c680e 2756 if (rx_buf_len <= IXGBE_RXBUFFER_4K)
bb5a9ad2 2757 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
642c680e 2758 else if (rx_buf_len <= IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2759 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2760 else
2761 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2762 }
7367096a 2763 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2764}
2765
9e10e045
AD		 2766/**
2767 * ixgbe_set_uta - Set unicast filter table address
2768 * @adapter: board private structure
2769 *
2770 * The unicast table address is a register array of 32-bit registers.
2771 * The table is meant to be used in a way similar to how the MTA is used
2772 * however due to certain limitations in the hardware it is necessary to
2773 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2774 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2775 **/
2776static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2777{
2778 struct ixgbe_hw *hw = &adapter->hw;
2779 int i;
2780
2781 /* The UTA table only exists on 82599 hardware and newer */
2782 if (hw->mac.type < ixgbe_mac_82599EB)
2783 return;
2784
2785 /* we only need to do this if VMDq is enabled */
2786 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2787 return;
2788
2789 for (i = 0; i < 128; i++)
2790 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2791}
2792
2793#define IXGBE_MAX_RX_DESC_POLL 10
2794static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2795 struct ixgbe_ring *ring)
2796{
2797 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2798 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2799 u32 rxdctl;
bf29ee6c 2800 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2801
2802 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2803 if (hw->mac.type == ixgbe_mac_82598EB &&
2804 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2805 return;
2806
2807 do {
032b4325 2808 usleep_range(1000, 2000);
9e10e045
AD		 2809 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2810 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2811
2812 if (!wait_loop) {
2813 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2814 "the polling period\n", reg_idx);
2815 }
2816}
2817
2d39d576
YZ		 2818void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2819 struct ixgbe_ring *ring)
2820{
2821 struct ixgbe_hw *hw = &adapter->hw;
2822 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2823 u32 rxdctl;
2824 u8 reg_idx = ring->reg_idx;
2825
2826 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2827 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2828
2829 /* write value back with RXDCTL.ENABLE bit cleared */
2830 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2831
2832 if (hw->mac.type == ixgbe_mac_82598EB &&
2833 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2834 return;
2835
2836 /* the hardware may take up to 100us to really disable the rx queue */
2837 do {
2838 udelay(10);
2839 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2840 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2841
2842 if (!wait_loop) {
2843 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2844 "the polling period\n", reg_idx);
2845 }
2846}
2847
84418e3b
AD		 2848void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2849 struct ixgbe_ring *ring)
acd37177
AD		 2850{
2851 struct ixgbe_hw *hw = &adapter->hw;
2852 u64 rdba = ring->dma;
9e10e045 2853 u32 rxdctl;
bf29ee6c 2854 u8 reg_idx = ring->reg_idx;
acd37177 2855
9e10e045
AD		 2856 /* disable queue to avoid issues while updating state */
2857 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2858 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2859
acd37177
AD		 2860 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2861 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2862 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2863 ring->count * sizeof(union ixgbe_adv_rx_desc));
2864 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2865 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2866 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2867
2868 ixgbe_configure_srrctl(adapter, ring);
2869 ixgbe_configure_rscctl(adapter, ring);
2870
e9f98072
GR		 2871 /* If operating in IOV mode set RLPML for X540 */
2872 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2873 hw->mac.type == ixgbe_mac_X540) {
2874 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2875 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2876 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2877 }
2878
9e10e045
AD		 2879 if (hw->mac.type == ixgbe_mac_82598EB) {
2880 /*
2881 * enable cache line friendly hardware writes:
2882 * PTHRESH=32 descriptors (half the internal cache),
2883 * this also removes ugly rx_no_buffer_count increment
2884 * HTHRESH=4 descriptors (to minimize latency on fetch)
2885 * WTHRESH=8 burst writeback up to two cache lines
2886 */
2887 rxdctl &= ~0x3FFFFF;
2888 rxdctl |= 0x080420;
2889 }
2890
2891 /* enable receive descriptor ring */
2892 rxdctl |= IXGBE_RXDCTL_ENABLE;
2893 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2894
2895 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2896 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2897}
2898
48654521
AD		 2899static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2900{
2901 struct ixgbe_hw *hw = &adapter->hw;
2902 int p;
2903
2904 /* PSRTYPE must be initialized in non 82598 adapters */
2905 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2906 IXGBE_PSRTYPE_UDPHDR |
2907 IXGBE_PSRTYPE_IPV4HDR |
48654521 2908 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2909 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2910
2911 if (hw->mac.type == ixgbe_mac_82598EB)
2912 return;
2913
2914 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2915 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2916
2917 for (p = 0; p < adapter->num_rx_pools; p++)
2918 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2919 psrtype);
2920}
2921
f5b4a52e
AD		 2922static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2923{
2924 struct ixgbe_hw *hw = &adapter->hw;
2925 u32 gcr_ext;
2926 u32 vt_reg_bits;
2927 u32 reg_offset, vf_shift;
2928 u32 vmdctl;
de4c7f65 2929 int i;
f5b4a52e
AD		 2930
2931 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2932 return;
2933
2934 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2935 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2936 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2937 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2938
2939 vf_shift = adapter->num_vfs % 32;
4cd6923d 2940 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 2941
2942 /* Enable only the PF's pool for Tx/Rx */
2943 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2944 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2945 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2946 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2947 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2948
2949 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2950 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2951
2952 /*
2953 * Set up VF register offsets for selected VT Mode,
2954 * i.e. 32 or 64 VFs for SR-IOV
2955 */
2956 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2957 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2958 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2959 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2960
2961 /* enable Tx loopback for VF/PF communication */
2962 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2963 /* Enable MAC Anti-Spoofing */
a1cbb15c 2964 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 2965 (adapter->num_vfs != 0),
a985b6c3 2966 adapter->num_vfs);
de4c7f65
GR		 2967 /* For VFs that have spoof checking turned off */
2968 for (i = 0; i < adapter->num_vfs; i++) {
2969 if (!adapter->vfinfo[i].spoofchk_enabled)
2970 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2971 }
f5b4a52e
AD		 2972}
2973
477de6ed 2974static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2975{
9a799d71
AK		 2976 struct ixgbe_hw *hw = &adapter->hw;
2977 struct net_device *netdev = adapter->netdev;
2978 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2979 int rx_buf_len;
477de6ed
AD		 2980 struct ixgbe_ring *rx_ring;
2981 int i;
2982 u32 mhadd, hlreg0;
48654521 2983
9a799d71 2984 /* Decide whether to use packet split mode or not */
a124339a
DS		 2985 /* On by default */
2986 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2987
1cdd1ec8 2988 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2989 if (adapter->num_vfs)
2990 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2991
2992 /* Disable packet split due to 82599 erratum #45 */
2993 if (hw->mac.type == ixgbe_mac_82599EB)
2994 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2995
63f39bd1 2996#ifdef IXGBE_FCOE
477de6ed
AD		 2997 /* adjust max frame to be able to do baby jumbo for FCoE */
2998 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2999 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3000 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3001
477de6ed
AD		 3002#endif /* IXGBE_FCOE */
3003 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3004 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3005 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3006 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3007
3008 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3009 }
3010
919e78a6
AD		 3011 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3012 max_frame += VLAN_HLEN;
3013
3014 /* Set the RX buffer length according to the mode */
3015 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3016 rx_buf_len = IXGBE_RX_HDR_SIZE;
3017 } else {
3018 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3019 (netdev->mtu <= ETH_DATA_LEN))
3020 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3021 /*
3022 * Make best use of allocation by using all but 1K of a
3023 * power of 2 allocation that will be used for skb->head.
3024 */
3025 else if (max_frame <= IXGBE_RXBUFFER_3K)
3026 rx_buf_len = IXGBE_RXBUFFER_3K;
3027 else if (max_frame <= IXGBE_RXBUFFER_7K)
3028 rx_buf_len = IXGBE_RXBUFFER_7K;
3029 else if (max_frame <= IXGBE_RXBUFFER_15K)
3030 rx_buf_len = IXGBE_RXBUFFER_15K;
3031 else
3032 rx_buf_len = IXGBE_MAX_RXBUFFER;
3033 }
3034
477de6ed
AD		 3035 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3036 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3037 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3038 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3039
0cefafad
JB		 3040 /*
3041 * Setup the HW Rx Head and Tail Descriptor Pointers and
3042 * the Base and Length of the Rx Descriptor Ring
3043 */
9a799d71 3044 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3045 rx_ring = adapter->rx_ring[i];
a6616b42 3046 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3047
6e455b89 3048 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3049 set_ring_ps_enabled(rx_ring);
3050 else
3051 clear_ring_ps_enabled(rx_ring);
3052
3053 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3054 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3055 else
7d637bcc 3056 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3057
63f39bd1 3058#ifdef IXGBE_FCOE
e8e9f696 3059 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3060 struct ixgbe_ring_feature *f;
3061 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3062 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3063 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3064 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3065 rx_ring->rx_buf_len =
e8e9f696 3066 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3067 } else if (!ring_is_rsc_enabled(rx_ring) &&
3068 !ring_is_ps_enabled(rx_ring)) {
3069 rx_ring->rx_buf_len =
3070 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3071 }
63f39bd1 3072 }
63f39bd1 3073#endif /* IXGBE_FCOE */
477de6ed 3074 }
477de6ed
AD		 3075}
3076
7367096a
AD		 3077static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3078{
3079 struct ixgbe_hw *hw = &adapter->hw;
3080 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3081
3082 switch (hw->mac.type) {
3083 case ixgbe_mac_82598EB:
3084 /*
3085 * For VMDq support of different descriptor types or
3086 * buffer sizes through the use of multiple SRRCTL
3087 * registers, RDRXCTL.MVMEN must be set to 1
3088 *
3089 * also, the manual doesn't mention it clearly but DCA hints
3090 * will only use queue 0's tags unless this bit is set. Side
3091 * effects of setting this bit are only that SRRCTL must be
3092 * fully programmed [0..15]
3093 */
3094 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3095 break;
3096 case ixgbe_mac_82599EB:
b93a2226 3097 case ixgbe_mac_X540:
7367096a
AD		 3098 /* Disable RSC for ACK packets */
3099 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3100 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3101 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3102 /* hardware requires some bits to be set by default */
3103 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3104 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3105 break;
3106 default:
3107 /* We should do nothing since we don't know this hardware */
3108 return;
3109 }
3110
3111 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3112}
3113
477de6ed
AD		 3114/**
3115 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3116 * @adapter: board private structure
3117 *
3118 * Configure the Rx unit of the MAC after a reset.
3119 **/
3120static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3121{
3122 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3123 int i;
3124 u32 rxctrl;
477de6ed
AD		 3125
3126 /* disable receives while setting up the descriptors */
3127 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3128 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3129
3130 ixgbe_setup_psrtype(adapter);
7367096a 3131 ixgbe_setup_rdrxctl(adapter);
477de6ed 3132
9e10e045 3133 /* Program registers for the distribution of queues */
f5b4a52e 3134 ixgbe_setup_mrqc(adapter);
f5b4a52e 3135
9e10e045
AD		 3136 ixgbe_set_uta(adapter);
3137
477de6ed
AD		 3138 /* set_rx_buffer_len must be called before ring initialization */
3139 ixgbe_set_rx_buffer_len(adapter);
3140
3141 /*
3142 * Setup the HW Rx Head and Tail Descriptor Pointers and
3143 * the Base and Length of the Rx Descriptor Ring
3144 */
9e10e045
AD		 3145 for (i = 0; i < adapter->num_rx_queues; i++)
3146 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3147
9e10e045
AD		 3148 /* disable drop enable for 82598 parts */
3149 if (hw->mac.type == ixgbe_mac_82598EB)
3150 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3151
3152 /* enable all receives */
3153 rxctrl |= IXGBE_RXCTRL_RXEN;
3154 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3155}
3156
8e586137 3157static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3158{
3159 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3160 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3161 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3162
3163 /* add VID to filter table */
1ada1b1b 3164 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3165 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3166
3167 return 0;
068c89b0
DS		 3168}
3169
8e586137 3170static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3171{
3172 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3173 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3174 int pool_ndx = adapter->num_vfs;
068c89b0 3175
068c89b0 3176 /* remove VID from filter table */
1ada1b1b 3177 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3178 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3179
3180 return 0;
068c89b0
DS		 3181}
3182
5f6c0181
JB		 3183/**
3184 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3185 * @adapter: driver data
3186 */
3187static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3188{
3189 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3190 u32 vlnctrl;
3191
3192 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3193 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3194 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3195}
3196
3197/**
3198 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3199 * @adapter: driver data
3200 */
3201static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3202{
3203 struct ixgbe_hw *hw = &adapter->hw;
3204 u32 vlnctrl;
3205
3206 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3207 vlnctrl |= IXGBE_VLNCTRL_VFE;
3208 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3209 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3210}
3211
3212/**
3213 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3214 * @adapter: driver data
3215 */
3216static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3217{
3218 struct ixgbe_hw *hw = &adapter->hw;
3219 u32 vlnctrl;
5f6c0181
JB		 3220 int i, j;
3221
3222 switch (hw->mac.type) {
3223 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3224 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3225 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3226 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3227 break;
3228 case ixgbe_mac_82599EB:
b93a2226 3229 case ixgbe_mac_X540:
5f6c0181
JB		 3230 for (i = 0; i < adapter->num_rx_queues; i++) {
3231 j = adapter->rx_ring[i]->reg_idx;
3232 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3233 vlnctrl &= ~IXGBE_RXDCTL_VME;
3234 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3235 }
3236 break;
3237 default:
3238 break;
3239 }
3240}
3241
3242/**
f62bbb5e 3243 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3244 * @adapter: driver data
3245 */
f62bbb5e 3246static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3247{
3248 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3249 u32 vlnctrl;
5f6c0181
JB		 3250 int i, j;
3251
3252 switch (hw->mac.type) {
3253 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3254 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3255 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3256 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3257 break;
3258 case ixgbe_mac_82599EB:
b93a2226 3259 case ixgbe_mac_X540:
5f6c0181
JB		 3260 for (i = 0; i < adapter->num_rx_queues; i++) {
3261 j = adapter->rx_ring[i]->reg_idx;
3262 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3263 vlnctrl |= IXGBE_RXDCTL_VME;
3264 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3265 }
3266 break;
3267 default:
3268 break;
3269 }
3270}
3271
9a799d71
AK		 3272static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3273{
f62bbb5e 3274 u16 vid;
9a799d71 3275
f62bbb5e
JG		 3276 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3277
3278 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3279 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3280}
3281
2850062a
AD		 3282/**
3283 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3284 * @netdev: network interface device structure
3285 *
3286 * Writes unicast address list to the RAR table.
3287 * Returns: -ENOMEM on failure/insufficient address space
3288 * 0 on no addresses written
3289 * X on writing X addresses to the RAR table
3290 **/
3291static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3292{
3293 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3294 struct ixgbe_hw *hw = &adapter->hw;
3295 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3296 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3297 int count = 0;
3298
3299 /* return ENOMEM indicating insufficient memory for addresses */
3300 if (netdev_uc_count(netdev) > rar_entries)
3301 return -ENOMEM;
3302
3303 if (!netdev_uc_empty(netdev) && rar_entries) {
3304 struct netdev_hw_addr *ha;
3305 /* return error if we do not support writing to RAR table */
3306 if (!hw->mac.ops.set_rar)
3307 return -ENOMEM;
3308
3309 netdev_for_each_uc_addr(ha, netdev) {
3310 if (!rar_entries)
3311 break;
3312 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3313 vfn, IXGBE_RAH_AV);
3314 count++;
3315 }
3316 }
3317 /* write the addresses in reverse order to avoid write combining */
3318 for (; rar_entries > 0 ; rar_entries--)
3319 hw->mac.ops.clear_rar(hw, rar_entries);
3320
3321 return count;
3322}
3323
9a799d71 3324/**
2c5645cf 3325 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3326 * @netdev: network interface device structure
3327 *
2c5645cf
CL		 3328 * The set_rx_method entry point is called whenever the unicast/multicast
3329 * address list or the network interface flags are updated. This routine is
3330 * responsible for configuring the hardware for proper unicast, multicast and
3331 * promiscuous mode.
9a799d71 3332 **/
7f870475 3333void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3334{
3335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3336 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3337 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3338 int count;
9a799d71
AK		 3339
3340 /* Check for Promiscuous and All Multicast modes */
3341
3342 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3343
f5dc442b
AD		 3344 /* set all bits that we expect to always be set */
3345 fctrl |= IXGBE_FCTRL_BAM;
3346 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3347 fctrl |= IXGBE_FCTRL_PMCF;
3348
2850062a
AD		 3349 /* clear the bits we are changing the status of */
3350 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3351
9a799d71 3352 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3353 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3354 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3355 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3356 /* don't hardware filter vlans in promisc mode */
3357 ixgbe_vlan_filter_disable(adapter);
9a799d71 3358 } else {
746b9f02
PM		 3359 if (netdev->flags & IFF_ALLMULTI) {
3360 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3361 vmolr |= IXGBE_VMOLR_MPE;
3362 } else {
3363 /*
3364 * Write addresses to the MTA, if the attempt fails
25985edc 3365 * then we should just turn on promiscuous mode so
2850062a
AD		 3366 * that we can at least receive multicast traffic
3367 */
3368 hw->mac.ops.update_mc_addr_list(hw, netdev);
3369 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3370 }
5f6c0181 3371 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3372 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3373 /*
3374 * Write addresses to available RAR registers, if there is not
3375 * sufficient space to store all the addresses then enable
25985edc 3376 * unicast promiscuous mode
2850062a
AD		 3377 */
3378 count = ixgbe_write_uc_addr_list(netdev);
3379 if (count < 0) {
3380 fctrl |= IXGBE_FCTRL_UPE;
3381 vmolr |= IXGBE_VMOLR_ROPE;
3382 }
9a799d71
AK		 3383 }
3384
2850062a 3385 if (adapter->num_vfs) {
1cdd1ec8 3386 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3387 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3388 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3389 IXGBE_VMOLR_ROPE);
3390 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3391 }
3392
3393 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3394
3395 if (netdev->features & NETIF_F_HW_VLAN_RX)
3396 ixgbe_vlan_strip_enable(adapter);
3397 else
3398 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3399}
3400
021230d4
AV		 3401static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3402{
3403 int q_idx;
3404 struct ixgbe_q_vector *q_vector;
3405 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3406
3407 /* legacy and MSI only use one vector */
3408 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3409 q_vectors = 1;
3410
3411 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3412 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3413 napi_enable(&q_vector->napi);
021230d4
AV		 3414 }
3415}
3416
3417static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3418{
3419 int q_idx;
3420 struct ixgbe_q_vector *q_vector;
3421 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3422
3423 /* legacy and MSI only use one vector */
3424 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3425 q_vectors = 1;
3426
3427 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3428 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3429 napi_disable(&q_vector->napi);
3430 }
3431}
3432
7a6b6f51 3433#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3434/*
3435 * ixgbe_configure_dcb - Configure DCB hardware
3436 * @adapter: ixgbe adapter struct
3437 *
3438 * This is called by the driver on open to configure the DCB hardware.
3439 * This is also called by the gennetlink interface when reconfiguring
3440 * the DCB state.
3441 */
3442static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3443{
3444 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3445 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3446
67ebd791
AD		 3447 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3448 if (hw->mac.type == ixgbe_mac_82598EB)
3449 netif_set_gso_max_size(adapter->netdev, 65536);
3450 return;
3451 }
3452
3453 if (hw->mac.type == ixgbe_mac_82598EB)
3454 netif_set_gso_max_size(adapter->netdev, 32768);
3455
2f90b865 3456
2f90b865 3457 /* Enable VLAN tag insert/strip */
f62bbb5e 3458 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3459
2f90b865 3460 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3461
971060b1 3462#ifdef IXGBE_FCOE
b120818e
JF		 3463 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3464 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3465#endif
b120818e
JF		 3466
3467 /* reconfigure the hardware */
3468 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3469 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3470 DCB_TX_CONFIG);
3471 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3472 DCB_RX_CONFIG);
3473 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3474 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3475 ixgbe_dcb_hw_ets(&adapter->hw,
3476 adapter->ixgbe_ieee_ets,
3477 max_frame);
3478 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3479 adapter->ixgbe_ieee_pfc->pfc_en,
3480 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3481 }
8187cd48
JF		 3482
3483 /* Enable RSS Hash per TC */
3484 if (hw->mac.type != ixgbe_mac_82598EB) {
3485 int i;
3486 u32 reg = 0;
3487
3488 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3489 u8 msb = 0;
3490 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3491
3492 while (cnt >>= 1)
3493 msb++;
3494
3495 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3496 }
3497 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3498 }
2f90b865 3499}
9da712d2
JF		 3500#endif
3501
3502/* Additional bittime to account for IXGBE framing */
3503#define IXGBE_ETH_FRAMING 20
3504
3505/*
3506 * ixgbe_hpbthresh - calculate high water mark for flow control
3507 *
3508 * @adapter: board private structure to calculate for
3509 * @pb - packet buffer to calculate
3510 */
3511static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3512{
3513 struct ixgbe_hw *hw = &adapter->hw;
3514 struct net_device *dev = adapter->netdev;
3515 int link, tc, kb, marker;
3516 u32 dv_id, rx_pba;
3517
3518 /* Calculate max LAN frame size */
3519 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3520
3521#ifdef IXGBE_FCOE
3522 /* FCoE traffic class uses FCOE jumbo frames */
3523 if (dev->features & NETIF_F_FCOE_MTU) {
3524 int fcoe_pb = 0;
2f90b865 3525
9da712d2
JF		 3526#ifdef CONFIG_IXGBE_DCB
3527 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3528
3529#endif
3530 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3531 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3532 }
2f90b865 3533#endif
80605c65 3534
9da712d2
JF		 3535 /* Calculate delay value for device */
3536 switch (hw->mac.type) {
3537 case ixgbe_mac_X540:
3538 dv_id = IXGBE_DV_X540(link, tc);
3539 break;
3540 default:
3541 dv_id = IXGBE_DV(link, tc);
3542 break;
3543 }
3544
3545 /* Loopback switch introduces additional latency */
3546 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3547 dv_id += IXGBE_B2BT(tc);
3548
3549 /* Delay value is calculated in bit times convert to KB */
3550 kb = IXGBE_BT2KB(dv_id);
3551 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3552
3553 marker = rx_pba - kb;
3554
3555 /* It is possible that the packet buffer is not large enough
3556 * to provide required headroom. In this case throw an error
3557 * to user and a do the best we can.
3558 */
3559 if (marker < 0) {
3560 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3561 "headroom to support flow control."
3562 "Decrease MTU or number of traffic classes\n", pb);
3563 marker = tc + 1;
3564 }
3565
3566 return marker;
3567}
3568
3569/*
3570 * ixgbe_lpbthresh - calculate low water mark for for flow control
3571 *
3572 * @adapter: board private structure to calculate for
3573 * @pb - packet buffer to calculate
3574 */
3575static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3576{
3577 struct ixgbe_hw *hw = &adapter->hw;
3578 struct net_device *dev = adapter->netdev;
3579 int tc;
3580 u32 dv_id;
3581
3582 /* Calculate max LAN frame size */
3583 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3584
3585 /* Calculate delay value for device */
3586 switch (hw->mac.type) {
3587 case ixgbe_mac_X540:
3588 dv_id = IXGBE_LOW_DV_X540(tc);
3589 break;
3590 default:
3591 dv_id = IXGBE_LOW_DV(tc);
3592 break;
3593 }
3594
3595 /* Delay value is calculated in bit times convert to KB */
3596 return IXGBE_BT2KB(dv_id);
3597}
3598
3599/*
3600 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3601 */
3602static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3603{
3604 struct ixgbe_hw *hw = &adapter->hw;
3605 int num_tc = netdev_get_num_tc(adapter->netdev);
3606 int i;
3607
3608 if (!num_tc)
3609 num_tc = 1;
3610
3611 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3612
3613 for (i = 0; i < num_tc; i++) {
3614 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3615
3616 /* Low water marks must not be larger than high water marks */
3617 if (hw->fc.low_water > hw->fc.high_water[i])
3618 hw->fc.low_water = 0;
3619 }
3620}
3621
80605c65
JF		 3622static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3623{
80605c65 3624 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3625 int hdrm;
3626 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3627
3628 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3629 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3630 hdrm = 32 << adapter->fdir_pballoc;
3631 else
3632 hdrm = 0;
80605c65 3633
f7e1027f 3634 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3635 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3636}
3637
e4911d57
AD		 3638static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3639{
3640 struct ixgbe_hw *hw = &adapter->hw;
3641 struct hlist_node *node, *node2;
3642 struct ixgbe_fdir_filter *filter;
3643
3644 spin_lock(&adapter->fdir_perfect_lock);
3645
3646 if (!hlist_empty(&adapter->fdir_filter_list))
3647 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3648
3649 hlist_for_each_entry_safe(filter, node, node2,
3650 &adapter->fdir_filter_list, fdir_node) {
3651 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3652 &filter->filter,
3653 filter->sw_idx,
3654 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3655 IXGBE_FDIR_DROP_QUEUE :
3656 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3657 }
3658
3659 spin_unlock(&adapter->fdir_perfect_lock);
3660}
3661
9a799d71
AK		 3662static void ixgbe_configure(struct ixgbe_adapter *adapter)
3663{
d2f5e7f3
AS		 3664 struct ixgbe_hw *hw = &adapter->hw;
3665
80605c65 3666 ixgbe_configure_pb(adapter);
7a6b6f51 3667#ifdef CONFIG_IXGBE_DCB
67ebd791 3668 ixgbe_configure_dcb(adapter);
2f90b865 3669#endif
9a799d71 3670
4c1d7b4b 3671 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3672 ixgbe_restore_vlan(adapter);
3673
eacd73f7
YZ		 3674#ifdef IXGBE_FCOE
3675 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3676 ixgbe_configure_fcoe(adapter);
3677
3678#endif /* IXGBE_FCOE */
d2f5e7f3
AS		 3679
3680 switch (hw->mac.type) {
3681 case ixgbe_mac_82599EB:
3682 case ixgbe_mac_X540:
3683 hw->mac.ops.disable_rx_buff(hw);
3684 break;
3685 default:
3686 break;
3687 }
3688
c4cf55e5 3689 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3690 ixgbe_init_fdir_signature_82599(&adapter->hw,
3691 adapter->fdir_pballoc);
e4911d57
AD		 3692 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3693 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3694 adapter->fdir_pballoc);
3695 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3696 }
4c1d7b4b 3697
d2f5e7f3
AS		 3698 switch (hw->mac.type) {
3699 case ixgbe_mac_82599EB:
3700 case ixgbe_mac_X540:
3701 hw->mac.ops.enable_rx_buff(hw);
3702 break;
3703 default:
3704 break;
3705 }
3706
933d41f1 3707 ixgbe_configure_virtualization(adapter);
c4cf55e5 3708
9a799d71
AK		 3709 ixgbe_configure_tx(adapter);
3710 ixgbe_configure_rx(adapter);
9a799d71
AK		 3711}
3712
e8e26350
PW		 3713static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3714{
3715 switch (hw->phy.type) {
3716 case ixgbe_phy_sfp_avago:
3717 case ixgbe_phy_sfp_ftl:
3718 case ixgbe_phy_sfp_intel:
3719 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3720 case ixgbe_phy_sfp_passive_tyco:
3721 case ixgbe_phy_sfp_passive_unknown:
3722 case ixgbe_phy_sfp_active_unknown:
3723 case ixgbe_phy_sfp_ftl_active:
e8e26350 3724 return true;
8917b447
AD		 3725 case ixgbe_phy_nl:
3726 if (hw->mac.type == ixgbe_mac_82598EB)
3727 return true;
e8e26350
PW		 3728 default:
3729 return false;
3730 }
3731}
3732
0ecc061d 3733/**
e8e26350
PW		 3734 * ixgbe_sfp_link_config - set up SFP+ link
3735 * @adapter: pointer to private adapter struct
3736 **/
3737static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3738{
7086400d 3739 /*
52f33af8 3740 * We are assuming the worst case scenario here, and that
7086400d
AD		 3741 * is that an SFP was inserted/removed after the reset
3742 * but before SFP detection was enabled. As such the best
3743 * solution is to just start searching as soon as we start
3744 */
3745 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3746 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3747
7086400d 3748 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3749}
3750
3751/**
3752 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3753 * @hw: pointer to private hardware struct
3754 *
3755 * Returns 0 on success, negative on failure
3756 **/
e8e26350 3757static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3758{
3759 u32 autoneg;
8620a103 3760 bool negotiation, link_up = false;
0ecc061d
PWJ		 3761 u32 ret = IXGBE_ERR_LINK_SETUP;
3762
3763 if (hw->mac.ops.check_link)
3764 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3765
3766 if (ret)
3767 goto link_cfg_out;
3768
0b0c2b31
ET		 3769 autoneg = hw->phy.autoneg_advertised;
3770 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3771 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3772 &negotiation);
0ecc061d
PWJ		 3773 if (ret)
3774 goto link_cfg_out;
3775
8620a103
MC		 3776 if (hw->mac.ops.setup_link)
3777 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3778link_cfg_out:
3779 return ret;
3780}
3781
a34bcfff 3782static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3783{
9a799d71 3784 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3785 u32 gpie = 0;
9a799d71 3786
9b471446 3787 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3788 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3789 IXGBE_GPIE_OCD;
3790 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3791 /*
3792 * use EIAM to auto-mask when MSI-X interrupt is asserted
3793 * this saves a register write for every interrupt
3794 */
3795 switch (hw->mac.type) {
3796 case ixgbe_mac_82598EB:
3797 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3798 break;
9b471446 3799 case ixgbe_mac_82599EB:
b93a2226
DS		 3800 case ixgbe_mac_X540:
3801 default:
9b471446
JB		 3802 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3803 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3804 break;
3805 }
3806 } else {
021230d4
AV		 3807 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3808 * specifically only auto mask tx and rx interrupts */
3809 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3810 }
9a799d71 3811
a34bcfff
AD		 3812 /* XXX: to interrupt immediately for EICS writes, enable this */
3813 /* gpie |= IXGBE_GPIE_EIMEN; */
3814
3815 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3816 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3817 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3818 }
3819
5fdd31f9 3820 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3821 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3822 switch (adapter->hw.mac.type) {
3823 case ixgbe_mac_82599EB:
3824 gpie |= IXGBE_SDP0_GPIEN;
3825 break;
3826 case ixgbe_mac_X540:
3827 gpie |= IXGBE_EIMS_TS;
3828 break;
3829 default:
3830 break;
3831 }
3832 }
5fdd31f9 3833
a34bcfff
AD		 3834 /* Enable fan failure interrupt */
3835 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3836 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3837
2698b208 3838 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3839 gpie |= IXGBE_SDP1_GPIEN;
3840 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3841 }
a34bcfff
AD		 3842
3843 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3844}
3845
c7ccde0f 3846static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3847{
3848 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3849 int err;
a34bcfff
AD		 3850 u32 ctrl_ext;
3851
3852 ixgbe_get_hw_control(adapter);
3853 ixgbe_setup_gpie(adapter);
e8e26350 3854
9a799d71
AK		 3855 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3856 ixgbe_configure_msix(adapter);
3857 else
3858 ixgbe_configure_msi_and_legacy(adapter);
3859
c6ecf39a
DS		 3860 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3861 if (hw->mac.ops.enable_tx_laser &&
3862 ((hw->phy.multispeed_fiber) ||
9f911707 3863 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3864 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3865 hw->mac.ops.enable_tx_laser(hw);
3866
9a799d71 3867 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3868 ixgbe_napi_enable_all(adapter);
3869
73c4b7cd
AD		 3870 if (ixgbe_is_sfp(hw)) {
3871 ixgbe_sfp_link_config(adapter);
3872 } else {
3873 err = ixgbe_non_sfp_link_config(hw);
3874 if (err)
3875 e_err(probe, "link_config FAILED %d\n", err);
3876 }
3877
021230d4
AV		 3878 /* clear any pending interrupts, may auto mask */
3879 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3880 ixgbe_irq_enable(adapter, true, true);
9a799d71 3881
bf069c97
DS		 3882 /*
3883 * If this adapter has a fan, check to see if we had a failure
3884 * before we enabled the interrupt.
3885 */
3886 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3887 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3888 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3889 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3890 }
3891
1da100bb 3892 /* enable transmits */
477de6ed 3893 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3894
9a799d71
AK		 3895 /* bring the link up in the watchdog, this could race with our first
3896 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3897 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3898 adapter->link_check_timeout = jiffies;
7086400d 3899 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3900
3901 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3902 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3903 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3904 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3905}
3906
d4f80882
AV		 3907void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3908{
3909 WARN_ON(in_interrupt());
7086400d
AD		 3910 /* put off any impending NetWatchDogTimeout */
3911 adapter->netdev->trans_start = jiffies;
3912
d4f80882 3913 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3914 usleep_range(1000, 2000);
d4f80882 3915 ixgbe_down(adapter);
5809a1ae
GR		 3916 /*
3917 * If SR-IOV enabled then wait a bit before bringing the adapter
3918 * back up to give the VFs time to respond to the reset. The
3919 * two second wait is based upon the watchdog timer cycle in
3920 * the VF driver.
3921 */
3922 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3923 msleep(2000);
d4f80882
AV		 3924 ixgbe_up(adapter);
3925 clear_bit(__IXGBE_RESETTING, &adapter->state);
3926}
3927
c7ccde0f 3928void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3929{
3930 /* hardware has been reset, we need to reload some things */
3931 ixgbe_configure(adapter);
3932
c7ccde0f 3933 ixgbe_up_complete(adapter);
9a799d71
AK		 3934}
3935
3936void ixgbe_reset(struct ixgbe_adapter *adapter)
3937{
c44ade9e 3938 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3939 int err;
3940
7086400d
AD		 3941 /* lock SFP init bit to prevent race conditions with the watchdog */
3942 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3943 usleep_range(1000, 2000);
3944
3945 /* clear all SFP and link config related flags while holding SFP_INIT */
3946 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3947 IXGBE_FLAG2_SFP_NEEDS_RESET);
3948 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3949
8ca783ab 3950 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3951 switch (err) {
3952 case 0:
3953 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3954 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3955 break;
3956 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3957 e_dev_err("master disable timed out\n");
da4dd0f7 3958 break;
794caeb2
PWJ		 3959 case IXGBE_ERR_EEPROM_VERSION:
3960 /* We are running on a pre-production device, log a warning */
849c4542 3961 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 3962 "Please be aware there may be issues associated with "
849c4542
ET		 3963 "your hardware. If you are experiencing problems "
3964 "please contact your Intel or hardware "
3965 "representative who provided you with this "
3966 "hardware.\n");
794caeb2 3967 break;
da4dd0f7 3968 default:
849c4542 3969 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3970 }
9a799d71 3971
7086400d
AD		 3972 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3973
9a799d71 3974 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3975 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3976 IXGBE_RAH_AV);
9a799d71
AK		 3977}
3978
9a799d71
AK		 3979/**
3980 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3981 * @rx_ring: ring to free buffers from
3982 **/
b6ec895e 3983static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3984{
b6ec895e 3985 struct device *dev = rx_ring->dev;
9a799d71 3986 unsigned long size;
b6ec895e 3987 u16 i;
9a799d71 3988
84418e3b
AD		 3989 /* ring already cleared, nothing to do */
3990 if (!rx_ring->rx_buffer_info)
3991 return;
9a799d71 3992
84418e3b 3993 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3994 for (i = 0; i < rx_ring->count; i++) {
3995 struct ixgbe_rx_buffer *rx_buffer_info;
3996
3997 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3998 if (rx_buffer_info->dma) {
b6ec895e 3999 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4000 rx_ring->rx_buf_len,
1b507730 4001 DMA_FROM_DEVICE);
9a799d71
AK		 4002 rx_buffer_info->dma = 0;
4003 }
4004 if (rx_buffer_info->skb) {
f8212f97 4005 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4006 rx_buffer_info->skb = NULL;
4c1975d7
AD		 4007 /* We need to clean up RSC frag lists */
4008 skb = ixgbe_merge_active_tail(skb);
4009 ixgbe_close_active_frag_list(skb);
4010 if (IXGBE_CB(skb)->delay_unmap) {
4011 dma_unmap_single(dev,
4012 IXGBE_CB(skb)->dma,
4013 rx_ring->rx_buf_len,
4014 DMA_FROM_DEVICE);
4015 IXGBE_CB(skb)->dma = 0;
4016 IXGBE_CB(skb)->delay_unmap = false;
4017 }
4018 dev_kfree_skb(skb);
9a799d71
AK		 4019 }
4020 if (!rx_buffer_info->page)
4021 continue;
4f57ca6e 4022 if (rx_buffer_info->page_dma) {
b6ec895e 4023 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4024 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4025 rx_buffer_info->page_dma = 0;
4026 }
9a799d71
AK		 4027 put_page(rx_buffer_info->page);
4028 rx_buffer_info->page = NULL;
762f4c57 4029 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4030 }
4031
4032 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4033 memset(rx_ring->rx_buffer_info, 0, size);
4034
4035 /* Zero out the descriptor ring */
4036 memset(rx_ring->desc, 0, rx_ring->size);
4037
4038 rx_ring->next_to_clean = 0;
4039 rx_ring->next_to_use = 0;
9a799d71
AK		 4040}
4041
4042/**
4043 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4044 * @tx_ring: ring to be cleaned
4045 **/
b6ec895e 4046static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4047{
4048 struct ixgbe_tx_buffer *tx_buffer_info;
4049 unsigned long size;
b6ec895e 4050 u16 i;
9a799d71 4051
84418e3b
AD		 4052 /* ring already cleared, nothing to do */
4053 if (!tx_ring->tx_buffer_info)
4054 return;
9a799d71 4055
84418e3b 4056 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4057 for (i = 0; i < tx_ring->count; i++) {
4058 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4059 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4060 }
4061
4062 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4063 memset(tx_ring->tx_buffer_info, 0, size);
4064
4065 /* Zero out the descriptor ring */
4066 memset(tx_ring->desc, 0, tx_ring->size);
4067
4068 tx_ring->next_to_use = 0;
4069 tx_ring->next_to_clean = 0;
9a799d71
AK		 4070}
4071
4072/**
021230d4 4073 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4074 * @adapter: board private structure
4075 **/
021230d4 4076static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4077{
4078 int i;
4079
021230d4 4080 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4081 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4082}
4083
4084/**
021230d4 4085 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4086 * @adapter: board private structure
4087 **/
021230d4 4088static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4089{
4090 int i;
4091
021230d4 4092 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4093 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4094}
4095
e4911d57
AD		 4096static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4097{
4098 struct hlist_node *node, *node2;
4099 struct ixgbe_fdir_filter *filter;
4100
4101 spin_lock(&adapter->fdir_perfect_lock);
4102
4103 hlist_for_each_entry_safe(filter, node, node2,
4104 &adapter->fdir_filter_list, fdir_node) {
4105 hlist_del(&filter->fdir_node);
4106 kfree(filter);
4107 }
4108 adapter->fdir_filter_count = 0;
4109
4110 spin_unlock(&adapter->fdir_perfect_lock);
4111}
4112
9a799d71
AK		 4113void ixgbe_down(struct ixgbe_adapter *adapter)
4114{
4115 struct net_device *netdev = adapter->netdev;
7f821875 4116 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4117 u32 rxctrl;
bf29ee6c 4118 int i;
9a799d71
AK		 4119
4120 /* signal that we are down to the interrupt handler */
4121 set_bit(__IXGBE_DOWN, &adapter->state);
4122
4123 /* disable receives */
7f821875
JB		 4124 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4125 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4126
2d39d576
YZ		 4127 /* disable all enabled rx queues */
4128 for (i = 0; i < adapter->num_rx_queues; i++)
4129 /* this call also flushes the previous write */
4130 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4131
032b4325 4132 usleep_range(10000, 20000);
9a799d71 4133
7f821875
JB		 4134 netif_tx_stop_all_queues(netdev);
4135
7086400d 4136 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4137 netif_carrier_off(netdev);
4138 netif_tx_disable(netdev);
4139
4140 ixgbe_irq_disable(adapter);
4141
4142 ixgbe_napi_disable_all(adapter);
4143
d034acf1
AD		 4144 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4145 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4146 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4147
4148 del_timer_sync(&adapter->service_timer);
4149
34cecbbf 4150 if (adapter->num_vfs) {
8e34d1aa
AD		 4151 /* Clear EITR Select mapping */
4152 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4153
4154 /* Mark all the VFs as inactive */
4155 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4156 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4157
34cecbbf
AD		 4158 /* ping all the active vfs to let them know we are going down */
4159 ixgbe_ping_all_vfs(adapter);
4160
4161 /* Disable all VFTE/VFRE TX/RX */
4162 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4163 }
4164
7f821875
JB		 4165 /* disable transmits in the hardware now that interrupts are off */
4166 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4167 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4168 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4169 }
34cecbbf
AD		 4170
4171 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4172 switch (hw->mac.type) {
4173 case ixgbe_mac_82599EB:
b93a2226 4174 case ixgbe_mac_X540:
88512539 4175 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4176 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4177 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4178 break;
4179 default:
4180 break;
4181 }
7f821875 4182
6f4a0e45
PL		 4183 if (!pci_channel_offline(adapter->pdev))
4184 ixgbe_reset(adapter);
c6ecf39a
DS		 4185
4186 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4187 if (hw->mac.ops.disable_tx_laser &&
4188 ((hw->phy.multispeed_fiber) ||
9f911707 4189 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4190 (hw->mac.type == ixgbe_mac_82599EB))))
4191 hw->mac.ops.disable_tx_laser(hw);
4192
9a799d71
AK		 4193 ixgbe_clean_all_tx_rings(adapter);
4194 ixgbe_clean_all_rx_rings(adapter);
4195
5dd2d332 4196#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4197 /* since we reset the hardware DCA settings were cleared */
e35ec126 4198 ixgbe_setup_dca(adapter);
96b0e0f6 4199#endif
9a799d71
AK		 4200}
4201
9a799d71 4202/**
021230d4
AV		 4203 * ixgbe_poll - NAPI Rx polling callback
4204 * @napi: structure for representing this polling device
4205 * @budget: how many packets driver is allowed to clean
4206 *
4207 * This function is used for legacy and MSI, NAPI mode
9a799d71 4208 **/
021230d4 4209static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4210{
9a1a69ad 4211 struct ixgbe_q_vector *q_vector =
e8e9f696 4212 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4213 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4214 struct ixgbe_ring *ring;
4215 int per_ring_budget;
4216 bool clean_complete = true;
9a799d71 4217
5dd2d332 4218#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4219 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4220 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4221#endif
4222
a557928e 4223 ixgbe_for_each_ring(ring, q_vector->tx)
4ff7fb12 4224 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4225
4ff7fb12
AD		 4226 /* attempt to distribute budget to each queue fairly, but don't allow
4227 * the budget to go below 1 because we'll exit polling */
4228 if (q_vector->rx.count > 1)
4229 per_ring_budget = max(budget/q_vector->rx.count, 1);
4230 else
4231 per_ring_budget = budget;
d2c7ddd6 4232
a557928e 4233 ixgbe_for_each_ring(ring, q_vector->rx)
4ff7fb12
AD		 4234 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4235 per_ring_budget);
4236
4237 /* If all work not completed, return budget and keep polling */
4238 if (!clean_complete)
4239 return budget;
4240
4241 /* all work done, exit the polling mode */
4242 napi_complete(napi);
4243 if (adapter->rx_itr_setting & 1)
4244 ixgbe_set_itr(q_vector);
4245 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4246 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4247
4248 return 0;
9a799d71
AK		 4249}
4250
4251/**
4252 * ixgbe_tx_timeout - Respond to a Tx Hang
4253 * @netdev: network interface device structure
4254 **/
4255static void ixgbe_tx_timeout(struct net_device *netdev)
4256{
4257 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4258
4259 /* Do the reset outside of interrupt context */
c83c6cbd 4260 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4261}
4262
4df10466
JB		 4263/**
4264 * ixgbe_set_rss_queues: Allocate queues for RSS
4265 * @adapter: board private structure to initialize
4266 *
4267 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4268 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4269 *
4270 **/
bc97114d
PWJ		 4271static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4272{
4273 bool ret = false;
0cefafad 4274 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4275
4276 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4277 f->mask = 0xF;
4278 adapter->num_rx_queues = f->indices;
4279 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4280 ret = true;
4281 } else {
bc97114d 4282 ret = false;
b9804972
JB		 4283 }
4284
bc97114d
PWJ		 4285 return ret;
4286}
4287
c4cf55e5
PWJ		 4288/**
4289 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4290 * @adapter: board private structure to initialize
4291 *
4292 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4293 * to the original CPU that initiated the Tx session. This runs in addition
4294 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4295 * Rx load across CPUs using RSS.
4296 *
4297 **/
e8e9f696 4298static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4299{
4300 bool ret = false;
4301 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4302
4303 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4304 f_fdir->mask = 0;
4305
24ddd967
AD		 4306 /*
4307 * Use RSS in addition to Flow Director to ensure the best
4308 * distribution of flows across cores, even when an FDIR flow
4309 * isn't matched.
4310 */
03ecf91a
AD		 4311 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4312 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4313 adapter->num_tx_queues = f_fdir->indices;
4314 adapter->num_rx_queues = f_fdir->indices;
4315 ret = true;
4316 } else {
4317 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4318 }
4319 return ret;
4320}
4321
0331a832
YZ		 4322#ifdef IXGBE_FCOE
4323/**
4324 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4325 * @adapter: board private structure to initialize
4326 *
4327 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4328 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4329 * rx queues out of the max number of rx queues, instead, it is used as the
4330 * index of the first rx queue used by FCoE.
4331 *
4332 **/
4333static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4334{
0331a832
YZ		 4335 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4336
e5b64635
JF		 4337 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4338 return false;
4339
3ed69d7e 4340 f->indices = min_t(int, num_online_cpus(), f->indices);
e5b64635 4341
e901acd6
JF		 4342 adapter->num_rx_queues = 1;
4343 adapter->num_tx_queues = 1;
e5b64635 4344
e901acd6
JF		 4345 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4346 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4347 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4348 ixgbe_set_fdir_queues(adapter);
4349 else
4350 ixgbe_set_rss_queues(adapter);
e5b64635 4351 }
03ecf91a 4352
e901acd6
JF		 4353 /* adding FCoE rx rings to the end */
4354 f->mask = adapter->num_rx_queues;
4355 adapter->num_rx_queues += f->indices;
4356 adapter->num_tx_queues += f->indices;
0331a832 4357
e5b64635
JF		 4358 return true;
4359}
4360#endif /* IXGBE_FCOE */
4361
e901acd6
JF		 4362/* Artificial max queue cap per traffic class in DCB mode */
4363#define DCB_QUEUE_CAP 8
4364
e5b64635
JF		 4365#ifdef CONFIG_IXGBE_DCB
4366static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4367{
e901acd6
JF		 4368 int per_tc_q, q, i, offset = 0;
4369 struct net_device *dev = adapter->netdev;
4370 int tcs = netdev_get_num_tc(dev);
e5b64635 4371
e901acd6
JF		 4372 if (!tcs)
4373 return false;
e5b64635 4374
e901acd6 4375 /* Map queue offset and counts onto allocated tx queues */
3ed69d7e
JB		 4376 per_tc_q = min_t(unsigned int, dev->num_tx_queues / tcs, DCB_QUEUE_CAP);
4377 q = min_t(int, num_online_cpus(), per_tc_q);
8b1c0b24 4378
8b1c0b24 4379 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4380 netdev_set_tc_queue(dev, i, q, offset);
4381 offset += q;
0331a832
YZ		 4382 }
4383
e901acd6
JF		 4384 adapter->num_tx_queues = q * tcs;
4385 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4386
4387#ifdef IXGBE_FCOE
e901acd6
JF		 4388 /* FCoE enabled queues require special configuration indexed
4389 * by feature specific indices and mask. Here we map FCoE
4390 * indices onto the DCB queue pairs allowing FCoE to own
4391 * configuration later.
e5b64635 4392 */
e901acd6 4393 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
cdf485be 4394 u8 prio_tc[MAX_USER_PRIORITY] = {0};
e901acd6
JF		 4395 int tc;
4396 struct ixgbe_ring_feature *f =
4397 &adapter->ring_feature[RING_F_FCOE];
4398
cdf485be
JF		 4399 ixgbe_dcb_unpack_map(&adapter->dcb_cfg, DCB_TX_CONFIG, prio_tc);
4400 tc = prio_tc[adapter->fcoe.up];
e901acd6
JF		 4401 f->indices = dev->tc_to_txq[tc].count;
4402 f->mask = dev->tc_to_txq[tc].offset;
4403 }
e5b64635
JF		 4404#endif
4405
e901acd6 4406 return true;
0331a832 4407}
e5b64635 4408#endif
0331a832 4409
1cdd1ec8
GR		 4410/**
4411 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4412 * @adapter: board private structure to initialize
4413 *
4414 * IOV doesn't actually use anything, so just NAK the
4415 * request for now and let the other queue routines
4416 * figure out what to do.
4417 */
4418static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4419{
4420 return false;
4421}
4422
4df10466 4423/*
25985edc 4424 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4425 * @adapter: board private structure to initialize
4426 *
4427 * This is the top level queue allocation routine. The order here is very
4428 * important, starting with the "most" number of features turned on at once,
4429 * and ending with the smallest set of features. This way large combinations
4430 * can be allocated if they're turned on, and smaller combinations are the
4431 * fallthrough conditions.
4432 *
4433 **/
847f53ff 4434static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4435{
1cdd1ec8
GR		 4436 /* Start with base case */
4437 adapter->num_rx_queues = 1;
4438 adapter->num_tx_queues = 1;
4439 adapter->num_rx_pools = adapter->num_rx_queues;
4440 adapter->num_rx_queues_per_pool = 1;
4441
4442 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4443 goto done;
1cdd1ec8 4444
bc97114d
PWJ		 4445#ifdef CONFIG_IXGBE_DCB
4446 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4447 goto done;
bc97114d
PWJ		 4448
4449#endif
e5b64635
JF		 4450#ifdef IXGBE_FCOE
4451 if (ixgbe_set_fcoe_queues(adapter))
4452 goto done;
4453
4454#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4455 if (ixgbe_set_fdir_queues(adapter))
4456 goto done;
4457
bc97114d 4458 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4459 goto done;
4460
4461 /* fallback to base case */
4462 adapter->num_rx_queues = 1;
4463 adapter->num_tx_queues = 1;
4464
4465done:
9d837ea2
YZ		 4466 if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) ||
4467 (adapter->netdev->reg_state == NETREG_UNREGISTERING))
4468 return 0;
4469
847f53ff 4470 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4471 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4472 return netif_set_real_num_rx_queues(adapter->netdev,
4473 adapter->num_rx_queues);
b9804972
JB		 4474}
4475
021230d4 4476static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4477 int vectors)
021230d4
AV		 4478{
4479 int err, vector_threshold;
4480
8f15486d
AD		 4481 /* We'll want at least 2 (vector_threshold):
4482 * 1) TxQ[0] + RxQ[0] handler
4483 * 2) Other (Link Status Change, etc.)
021230d4
AV		 4484 */
4485 vector_threshold = MIN_MSIX_COUNT;
4486
24ddd967
AD		 4487 /*
4488 * The more we get, the more we will assign to Tx/Rx Cleanup
021230d4
AV		 4489 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4490 * Right now, we simply care about how many we'll get; we'll
4491 * set them up later while requesting irq's.
4492 */
4493 while (vectors >= vector_threshold) {
4494 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4495 vectors);
021230d4
AV		 4496 if (!err) /* Success in acquiring all requested vectors. */
4497 break;
4498 else if (err < 0)
4499 vectors = 0; /* Nasty failure, quit now */
4500 else /* err == number of vectors we should try again with */
4501 vectors = err;
4502 }
4503
4504 if (vectors < vector_threshold) {
4505 /* Can't allocate enough MSI-X interrupts? Oh well.
4506 * This just means we'll go with either a single MSI
4507 * vector or fall back to legacy interrupts.
4508 */
849c4542
ET		 4509 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4510 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4511 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4512 kfree(adapter->msix_entries);
4513 adapter->msix_entries = NULL;
021230d4
AV		 4514 } else {
4515 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4516 /*
4517 * Adjust for only the vectors we'll use, which is minimum
4518 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4519 * vectors we were allocated.
4520 */
4521 adapter->num_msix_vectors = min(vectors,
e8e9f696 4522 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4523 }
4524}
4525
021230d4 4526/**
bc97114d 4527 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4528 * @adapter: board private structure to initialize
4529 *
bc97114d
PWJ		 4530 * Cache the descriptor ring offsets for RSS to the assigned rings.
4531 *
021230d4 4532 **/
bc97114d 4533static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4534{
bc97114d 4535 int i;
bc97114d 4536
9d6b758f
AD		 4537 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4538 return false;
bc97114d 4539
9d6b758f
AD		 4540 for (i = 0; i < adapter->num_rx_queues; i++)
4541 adapter->rx_ring[i]->reg_idx = i;
4542 for (i = 0; i < adapter->num_tx_queues; i++)
4543 adapter->tx_ring[i]->reg_idx = i;
4544
4545 return true;
bc97114d
PWJ		 4546}
4547
4548#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4549
4550/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4551static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4552 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4553{
4554 struct net_device *dev = adapter->netdev;
4555 struct ixgbe_hw *hw = &adapter->hw;
4556 u8 num_tcs = netdev_get_num_tc(dev);
4557
4558 *tx = 0;
4559 *rx = 0;
4560
4561 switch (hw->mac.type) {
4562 case ixgbe_mac_82598EB:
aba70d5e
JF		 4563 *tx = tc << 2;
4564 *rx = tc << 3;
e5b64635
JF		 4565 break;
4566 case ixgbe_mac_82599EB:
4567 case ixgbe_mac_X540:
4fa2e0e1 4568 if (num_tcs > 4) {
e5b64635
JF		 4569 if (tc < 3) {
4570 *tx = tc << 5;
4571 *rx = tc << 4;
4572 } else if (tc < 5) {
4573 *tx = ((tc + 2) << 4);
4574 *rx = tc << 4;
4575 } else if (tc < num_tcs) {
4576 *tx = ((tc + 8) << 3);
4577 *rx = tc << 4;
4578 }
4fa2e0e1 4579 } else {
e5b64635
JF		 4580 *rx = tc << 5;
4581 switch (tc) {
4582 case 0:
4583 *tx = 0;
4584 break;
4585 case 1:
4586 *tx = 64;
4587 break;
4588 case 2:
4589 *tx = 96;
4590 break;
4591 case 3:
4592 *tx = 112;
4593 break;
4594 default:
4595 break;
4596 }
4597 }
4598 break;
4599 default:
4600 break;
4601 }
4602}
4603
bc97114d
PWJ		 4604/**
4605 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4606 * @adapter: board private structure to initialize
4607 *
4608 * Cache the descriptor ring offsets for DCB to the assigned rings.
4609 *
4610 **/
4611static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4612{
e5b64635
JF		 4613 struct net_device *dev = adapter->netdev;
4614 int i, j, k;
4615 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4616
8b1c0b24 4617 if (!num_tcs)
bd508178 4618 return false;
f92ef202 4619
e5b64635
JF		 4620 for (i = 0, k = 0; i < num_tcs; i++) {
4621 unsigned int tx_s, rx_s;
4622 u16 count = dev->tc_to_txq[i].count;
4623
4624 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4625 for (j = 0; j < count; j++, k++) {
4626 adapter->tx_ring[k]->reg_idx = tx_s + j;
4627 adapter->rx_ring[k]->reg_idx = rx_s + j;
4628 adapter->tx_ring[k]->dcb_tc = i;
4629 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4630 }
021230d4 4631 }
e5b64635
JF		 4632
4633 return true;
bc97114d
PWJ		 4634}
4635#endif
4636
c4cf55e5
PWJ		 4637/**
4638 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4639 * @adapter: board private structure to initialize
4640 *
4641 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4642 *
4643 **/
e8e9f696 4644static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4645{
4646 int i;
4647 bool ret = false;
4648
03ecf91a
AD		 4649 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4650 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4651 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4652 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4653 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4654 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4655 ret = true;
4656 }
4657
4658 return ret;
4659}
4660
0331a832
YZ		 4661#ifdef IXGBE_FCOE
4662/**
4663 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4664 * @adapter: board private structure to initialize
4665 *
4666 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4667 *
4668 */
4669static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4670{
0331a832 4671 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4672 int i;
4673 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4674
4675 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4676 return false;
0331a832 4677
bf29ee6c 4678 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4679 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4680 ixgbe_cache_ring_fdir(adapter);
4681 else
4682 ixgbe_cache_ring_rss(adapter);
8faa2a78 4683
bf29ee6c
AD		 4684 fcoe_rx_i = f->mask;
4685 fcoe_tx_i = f->mask;
0331a832 4686 }
bf29ee6c
AD		 4687 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4688 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4689 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4690 }
4691 return true;
0331a832
YZ		 4692}
4693
4694#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4695/**
4696 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4697 * @adapter: board private structure to initialize
4698 *
4699 * SR-IOV doesn't use any descriptor rings but changes the default if
4700 * no other mapping is used.
4701 *
4702 */
4703static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4704{
4a0b9ca0
PW		 4705 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4706 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4707 if (adapter->num_vfs)
4708 return true;
4709 else
4710 return false;
4711}
4712
bc97114d
PWJ		 4713/**
4714 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4715 * @adapter: board private structure to initialize
4716 *
4717 * Once we know the feature-set enabled for the device, we'll cache
4718 * the register offset the descriptor ring is assigned to.
4719 *
4720 * Note, the order the various feature calls is important. It must start with
4721 * the "most" features enabled at the same time, then trickle down to the
4722 * least amount of features turned on at once.
4723 **/
4724static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4725{
4726 /* start with default case */
4a0b9ca0
PW		 4727 adapter->rx_ring[0]->reg_idx = 0;
4728 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4729
1cdd1ec8
GR		 4730 if (ixgbe_cache_ring_sriov(adapter))
4731 return;
4732
e5b64635
JF		 4733#ifdef CONFIG_IXGBE_DCB
4734 if (ixgbe_cache_ring_dcb(adapter))
4735 return;
4736#endif
4737
0331a832
YZ		 4738#ifdef IXGBE_FCOE
4739 if (ixgbe_cache_ring_fcoe(adapter))
4740 return;
0331a832 4741#endif /* IXGBE_FCOE */
bc97114d 4742
c4cf55e5
PWJ		 4743 if (ixgbe_cache_ring_fdir(adapter))
4744 return;
4745
bc97114d
PWJ		 4746 if (ixgbe_cache_ring_rss(adapter))
4747 return;
021230d4
AV		 4748}
4749
021230d4
AV		 4750/**
4751 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4752 * @adapter: board private structure to initialize
4753 *
4754 * Attempt to configure the interrupts using the best available
4755 * capabilities of the hardware and the kernel.
4756 **/
feea6a57 4757static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4758{
8be0e467 4759 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4760 int err = 0;
4761 int vector, v_budget;
4762
4763 /*
4764 * It's easy to be greedy for MSI-X vectors, but it really
4765 * doesn't do us much good if we have a lot more vectors
4766 * than CPU's. So let's be conservative and only ask for
342bde1b 4767 * (roughly) the same number of vectors as there are CPU's.
8f15486d 4768 * The default is to use pairs of vectors.
021230d4 4769 */
8f15486d
AD		 4770 v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues);
4771 v_budget = min_t(int, v_budget, num_online_cpus());
4772 v_budget += NON_Q_VECTORS;
021230d4
AV		 4773
4774 /*
4775 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4776 * hw.mac->max_msix_vectors vectors. With features
4777 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4778 * descriptor queues supported by our device. Thus, we cap it off in
4779 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4780 */
de88eeeb 4781 v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors);
021230d4
AV		 4782
4783 /* A failure in MSI-X entry allocation isn't fatal, but it does
4784 * mean we disable MSI-X capabilities of the adapter. */
4785 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4786 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4787 if (adapter->msix_entries) {
4788 for (vector = 0; vector < v_budget; vector++)
4789 adapter->msix_entries[vector].entry = vector;
021230d4 4790
7a921c93 4791 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4792
7a921c93
AD		 4793 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4794 goto out;
4795 }
26d27844 4796
7a921c93
AD		 4797 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4798 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4799 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4800 e_err(probe,
03ecf91a 4801 "ATR is not supported while multiple "
45b9f509
AD		 4802 "queues are disabled. Disabling Flow Director\n");
4803 }
c4cf55e5 4804 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4805 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4806 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4807 ixgbe_disable_sriov(adapter);
4808
847f53ff
BH		 4809 err = ixgbe_set_num_queues(adapter);
4810 if (err)
4811 return err;
021230d4 4812
021230d4
AV		 4813 err = pci_enable_msi(adapter->pdev);
4814 if (!err) {
4815 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4816 } else {
849c4542
ET		 4817 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4818 "Unable to allocate MSI interrupt, "
4819 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4820 /* reset err */
4821 err = 0;
4822 }
4823
4824out:
021230d4
AV		 4825 return err;
4826}
4827
de88eeeb
AD		 4828static void ixgbe_add_ring(struct ixgbe_ring *ring,
4829 struct ixgbe_ring_container *head)
4830{
4831 ring->next = head->ring;
4832 head->ring = ring;
4833 head->count++;
4834}
4835
4836/**
4837 * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
4838 * @adapter: board private structure to initialize
4839 * @v_idx: index of vector in adapter struct
4840 *
4841 * We allocate one q_vector. If allocation fails we return -ENOMEM.
4842 **/
4843static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, int v_idx,
4844 int txr_count, int txr_idx,
4845 int rxr_count, int rxr_idx)
4846{
4847 struct ixgbe_q_vector *q_vector;
4848 struct ixgbe_ring *ring;
4849 int node = -1;
4850 int cpu = -1;
4851 int ring_count, size;
4852
4853 ring_count = txr_count + rxr_count;
4854 size = sizeof(struct ixgbe_q_vector) +
4855 (sizeof(struct ixgbe_ring) * ring_count);
4856
4857 /* customize cpu for Flow Director mapping */
4858 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4859 if (cpu_online(v_idx)) {
4860 cpu = v_idx;
4861 node = cpu_to_node(cpu);
4862 }
4863 }
4864
4865 /* allocate q_vector and rings */
4866 q_vector = kzalloc_node(size, GFP_KERNEL, node);
4867 if (!q_vector)
4868 q_vector = kzalloc(size, GFP_KERNEL);
4869 if (!q_vector)
4870 return -ENOMEM;
4871
4872 /* setup affinity mask and node */
4873 if (cpu != -1)
4874 cpumask_set_cpu(cpu, &q_vector->affinity_mask);
4875 else
4876 cpumask_copy(&q_vector->affinity_mask, cpu_online_mask);
4877 q_vector->numa_node = node;
4878
4879 /* initialize NAPI */
4880 netif_napi_add(adapter->netdev, &q_vector->napi,
4881 ixgbe_poll, 64);
4882
4883 /* tie q_vector and adapter together */
4884 adapter->q_vector[v_idx] = q_vector;
4885 q_vector->adapter = adapter;
4886 q_vector->v_idx = v_idx;
4887
4888 /* initialize work limits */
4889 q_vector->tx.work_limit = adapter->tx_work_limit;
4890
4891 /* initialize pointer to rings */
4892 ring = q_vector->ring;
4893
4894 while (txr_count) {
4895 /* assign generic ring traits */
4896 ring->dev = &adapter->pdev->dev;
4897 ring->netdev = adapter->netdev;
4898
4899 /* configure backlink on ring */
4900 ring->q_vector = q_vector;
4901
4902 /* update q_vector Tx values */
4903 ixgbe_add_ring(ring, &q_vector->tx);
4904
4905 /* apply Tx specific ring traits */
4906 ring->count = adapter->tx_ring_count;
4907 ring->queue_index = txr_idx;
4908
4909 /* assign ring to adapter */
4910 adapter->tx_ring[txr_idx] = ring;
4911
4912 /* update count and index */
4913 txr_count--;
4914 txr_idx++;
4915
4916 /* push pointer to next ring */
4917 ring++;
4918 }
4919
4920 while (rxr_count) {
4921 /* assign generic ring traits */
4922 ring->dev = &adapter->pdev->dev;
4923 ring->netdev = adapter->netdev;
4924
4925 /* configure backlink on ring */
4926 ring->q_vector = q_vector;
4927
4928 /* update q_vector Rx values */
4929 ixgbe_add_ring(ring, &q_vector->rx);
4930
4931 /*
4932 * 82599 errata, UDP frames with a 0 checksum
4933 * can be marked as checksum errors.
4934 */
4935 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4936 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
4937
4938 /* apply Rx specific ring traits */
4939 ring->count = adapter->rx_ring_count;
4940 ring->queue_index = rxr_idx;
4941
4942 /* assign ring to adapter */
4943 adapter->rx_ring[rxr_idx] = ring;
4944
4945 /* update count and index */
4946 rxr_count--;
4947 rxr_idx++;
4948
4949 /* push pointer to next ring */
4950 ring++;
4951 }
4952
4953 return 0;
4954}
4955
4956/**
4957 * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
4958 * @adapter: board private structure to initialize
4959 * @v_idx: Index of vector to be freed
4960 *
4961 * This function frees the memory allocated to the q_vector. In addition if
4962 * NAPI is enabled it will delete any references to the NAPI struct prior
4963 * to freeing the q_vector.
4964 **/
4965static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx)
4966{
4967 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4968 struct ixgbe_ring *ring;
4969
a557928e 4970 ixgbe_for_each_ring(ring, q_vector->tx)
de88eeeb
AD		 4971 adapter->tx_ring[ring->queue_index] = NULL;
4972
a557928e 4973 ixgbe_for_each_ring(ring, q_vector->rx)
de88eeeb
AD		 4974 adapter->rx_ring[ring->queue_index] = NULL;
4975
4976 adapter->q_vector[v_idx] = NULL;
4977 netif_napi_del(&q_vector->napi);
4978
4979 /*
4980 * ixgbe_get_stats64() might access the rings on this vector,
4981 * we must wait a grace period before freeing it.
4982 */
4983 kfree_rcu(q_vector, rcu);
4984}
4985
7a921c93
AD		 4986/**
4987 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4988 * @adapter: board private structure to initialize
4989 *
4990 * We allocate one q_vector per queue interrupt. If allocation fails we
4991 * return -ENOMEM.
4992 **/
4993static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4994{
de88eeeb
AD		 4995 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4996 int rxr_remaining = adapter->num_rx_queues;
4997 int txr_remaining = adapter->num_tx_queues;
4998 int rxr_idx = 0, txr_idx = 0, v_idx = 0;
4999 int err;
7a921c93 5000
de88eeeb
AD		 5001 /* only one q_vector if MSI-X is disabled. */
5002 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
5003 q_vectors = 1;
7a921c93 5004
de88eeeb
AD		 5005 if (q_vectors >= (rxr_remaining + txr_remaining)) {
5006 for (; rxr_remaining; v_idx++, q_vectors--) {
5007 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors);
5008 err = ixgbe_alloc_q_vector(adapter, v_idx,
5009 0, 0, rqpv, rxr_idx);
4ff7fb12 5010
de88eeeb
AD		 5011 if (err)
5012 goto err_out;
5013
5014 /* update counts and index */
5015 rxr_remaining -= rqpv;
5016 rxr_idx += rqpv;
5017 }
5018 }
4ff7fb12 5019
de88eeeb
AD		 5020 for (; q_vectors; v_idx++, q_vectors--) {
5021 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors);
5022 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors);
5023 err = ixgbe_alloc_q_vector(adapter, v_idx,
5024 tqpv, txr_idx,
5025 rqpv, rxr_idx);
5026
5027 if (err)
207867f5 5028 goto err_out;
de88eeeb
AD		 5029
5030 /* update counts and index */
5031 rxr_remaining -= rqpv;
5032 rxr_idx += rqpv;
5033 txr_remaining -= tqpv;
5034 txr_idx += tqpv;
7a921c93
AD		 5035 }
5036
5037 return 0;
5038
5039err_out:
4ff7fb12
AD		 5040 while (v_idx) {
5041 v_idx--;
de88eeeb 5042 ixgbe_free_q_vector(adapter, v_idx);
7a921c93 5043 }
de88eeeb 5044
7a921c93
AD		 5045 return -ENOMEM;
5046}
5047
5048/**
5049 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5050 * @adapter: board private structure to initialize
5051 *
5052 * This function frees the memory allocated to the q_vectors. In addition if
5053 * NAPI is enabled it will delete any references to the NAPI struct prior
5054 * to freeing the q_vector.
5055 **/
5056static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5057{
de88eeeb 5058 int v_idx, q_vectors;
7a921c93 5059
91281fd3 5060 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
de88eeeb 5061 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5062 else
de88eeeb 5063 q_vectors = 1;
7a921c93 5064
de88eeeb
AD		 5065 for (v_idx = 0; v_idx < q_vectors; v_idx++)
5066 ixgbe_free_q_vector(adapter, v_idx);
7a921c93
AD		 5067}
5068
7b25cdba 5069static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5070{
5071 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5072 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5073 pci_disable_msix(adapter->pdev);
5074 kfree(adapter->msix_entries);
5075 adapter->msix_entries = NULL;
5076 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5077 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5078 pci_disable_msi(adapter->pdev);
5079 }
021230d4
AV		 5080}
5081
5082/**
5083 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5084 * @adapter: board private structure to initialize
5085 *
5086 * We determine which interrupt scheme to use based on...
5087 * - Kernel support (MSI, MSI-X)
5088 * - which can be user-defined (via MODULE_PARAM)
5089 * - Hardware queue count (num_*_queues)
5090 * - defined by miscellaneous hardware support/features (RSS, etc.)
5091 **/
2f90b865 5092int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5093{
5094 int err;
5095
5096 /* Number of supported queues */
847f53ff
BH		 5097 err = ixgbe_set_num_queues(adapter);
5098 if (err)
5099 return err;
021230d4 5100
021230d4
AV		 5101 err = ixgbe_set_interrupt_capability(adapter);
5102 if (err) {
849c4542 5103 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5104 goto err_set_interrupt;
9a799d71
AK		 5105 }
5106
7a921c93
AD		 5107 err = ixgbe_alloc_q_vectors(adapter);
5108 if (err) {
849c4542 5109 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5110 goto err_alloc_q_vectors;
5111 }
5112
de88eeeb 5113 ixgbe_cache_ring_register(adapter);
7a921c93 5114
849c4542 5115 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5116 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5117 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5118
5119 set_bit(__IXGBE_DOWN, &adapter->state);
5120
9a799d71 5121 return 0;
021230d4 5122
7a921c93
AD		 5123err_alloc_q_vectors:
5124 ixgbe_reset_interrupt_capability(adapter);
021230d4 5125err_set_interrupt:
7a921c93
AD		 5126 return err;
5127}
5128
5129/**
5130 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5131 * @adapter: board private structure to clear interrupt scheme on
5132 *
5133 * We go through and clear interrupt specific resources and reset the structure
5134 * to pre-load conditions
5135 **/
5136void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5137{
b8eb3a10
DS		 5138 adapter->num_tx_queues = 0;
5139 adapter->num_rx_queues = 0;
5140
7a921c93
AD		 5141 ixgbe_free_q_vectors(adapter);
5142 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5143}
5144
5145/**
5146 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5147 * @adapter: board private structure to initialize
5148 *
5149 * ixgbe_sw_init initializes the Adapter private data structure.
5150 * Fields are initialized based on PCI device information and
5151 * OS network device settings (MTU size).
5152 **/
5153static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5154{
5155 struct ixgbe_hw *hw = &adapter->hw;
5156 struct pci_dev *pdev = adapter->pdev;
021230d4 5157 unsigned int rss;
7a6b6f51 5158#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5159 int j;
5160 struct tc_configuration *tc;
5161#endif
021230d4 5162
c44ade9e
JB		 5163 /* PCI config space info */
5164
5165 hw->vendor_id = pdev->vendor;
5166 hw->device_id = pdev->device;
5167 hw->revision_id = pdev->revision;
5168 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5169 hw->subsystem_device_id = pdev->subsystem_device;
5170
021230d4 5171 /* Set capability flags */
3ed69d7e 5172 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
021230d4
AV		 5173 adapter->ring_feature[RING_F_RSS].indices = rss;
5174 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5175 switch (hw->mac.type) {
5176 case ixgbe_mac_82598EB:
bf069c97
DS		 5177 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5178 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5179 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 5180 break;
b93a2226 5181 case ixgbe_mac_X540:
4f51bf70
JK		 5182 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5183 case ixgbe_mac_82599EB:
e8e26350 5184 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5185 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5186 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5187 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5188 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5189 /* Flow Director hash filters enabled */
5190 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5191 adapter->atr_sample_rate = 20;
c4cf55e5 5192 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5193 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5194 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5195#ifdef IXGBE_FCOE
0d551589
YZ		 5196 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5197 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5198 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5199#ifdef CONFIG_IXGBE_DCB
6ee16520 5200 /* Default traffic class to use for FCoE */
56075a98 5201 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5202#endif
eacd73f7 5203#endif /* IXGBE_FCOE */
bd508178
AD		 5204 break;
5205 default:
5206 break;
f8212f97 5207 }
2f90b865 5208
1fc5f038
AD		 5209 /* n-tuple support exists, always init our spinlock */
5210 spin_lock_init(&adapter->fdir_perfect_lock);
5211
7a6b6f51 5212#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5213 switch (hw->mac.type) {
5214 case ixgbe_mac_X540:
5215 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5216 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5217 break;
5218 default:
5219 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5220 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5221 break;
5222 }
5223
2f90b865
AD		 5224 /* Configure DCB traffic classes */
5225 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5226 tc = &adapter->dcb_cfg.tc_config[j];
5227 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5228 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5229 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5230 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5231 tc->dcb_pfc = pfc_disabled;
5232 }
4de2a022
JF		 5233
5234 /* Initialize default user to priority mapping, UPx->TC0 */
5235 tc = &adapter->dcb_cfg.tc_config[0];
5236 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5237 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5238
2f90b865
AD		 5239 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5240 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5241 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5242 adapter->dcb_set_bitmap = 0x00;
3032309b 5243 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5244 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5245 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5246
5247#endif
9a799d71
AK		 5248
5249 /* default flow control settings */
cd7664f6 5250 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5251 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5252#ifdef CONFIG_DCB
5253 adapter->last_lfc_mode = hw->fc.current_mode;
5254#endif
9da712d2 5255 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5256 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5257 hw->fc.send_xon = true;
71fd570b 5258 hw->fc.disable_fc_autoneg = false;
9a799d71 5259
30efa5a3 5260 /* enable itr by default in dynamic mode */
f7554a2b 5261 adapter->rx_itr_setting = 1;
f7554a2b 5262 adapter->tx_itr_setting = 1;
30efa5a3 5263
30efa5a3
JB		 5264 /* set default ring sizes */
5265 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5266 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5267
bd198058 5268 /* set default work limits */
59224555 5269 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5270
9a799d71 5271 /* initialize eeprom parameters */
c44ade9e 5272 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5273 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5274 return -EIO;
5275 }
5276
9a799d71
AK		 5277 set_bit(__IXGBE_DOWN, &adapter->state);
5278
5279 return 0;
5280}
5281
5282/**
5283 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5284 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5285 *
5286 * Return 0 on success, negative on failure
5287 **/
b6ec895e 5288int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5289{
b6ec895e 5290 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5291 int orig_node = dev_to_node(dev);
5292 int numa_node = -1;
9a799d71
AK		 5293 int size;
5294
3a581073 5295 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5296
5297 if (tx_ring->q_vector)
5298 numa_node = tx_ring->q_vector->numa_node;
5299
5300 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5301 if (!tx_ring->tx_buffer_info)
89bf67f1 5302 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5303 if (!tx_ring->tx_buffer_info)
5304 goto err;
9a799d71
AK		 5305
5306 /* round up to nearest 4K */
12207e49 5307 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5308 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5309
de88eeeb
AD		 5310 set_dev_node(dev, numa_node);
5311 tx_ring->desc = dma_alloc_coherent(dev,
5312 tx_ring->size,
5313 &tx_ring->dma,
5314 GFP_KERNEL);
5315 set_dev_node(dev, orig_node);
5316 if (!tx_ring->desc)
5317 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5318 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5319 if (!tx_ring->desc)
5320 goto err;
9a799d71 5321
3a581073
JB		 5322 tx_ring->next_to_use = 0;
5323 tx_ring->next_to_clean = 0;
9a799d71 5324 return 0;
e01c31a5
JB		 5325
5326err:
5327 vfree(tx_ring->tx_buffer_info);
5328 tx_ring->tx_buffer_info = NULL;
b6ec895e 5329 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5330 return -ENOMEM;
9a799d71
AK		 5331}
5332
69888674
AD		 5333/**
5334 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5335 * @adapter: board private structure
5336 *
5337 * If this function returns with an error, then it's possible one or
5338 * more of the rings is populated (while the rest are not). It is the
5339 * callers duty to clean those orphaned rings.
5340 *
5341 * Return 0 on success, negative on failure
5342 **/
5343static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5344{
5345 int i, err = 0;
5346
5347 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5348 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5349 if (!err)
5350 continue;
396e799c 5351 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5352 break;
5353 }
5354
5355 return err;
5356}
5357
9a799d71
AK		 5358/**
5359 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5360 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5361 *
5362 * Returns 0 on success, negative on failure
5363 **/
b6ec895e 5364int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5365{
b6ec895e 5366 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5367 int orig_node = dev_to_node(dev);
5368 int numa_node = -1;
021230d4 5369 int size;
9a799d71 5370
3a581073 5371 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5372
5373 if (rx_ring->q_vector)
5374 numa_node = rx_ring->q_vector->numa_node;
5375
5376 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5377 if (!rx_ring->rx_buffer_info)
89bf67f1 5378 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5379 if (!rx_ring->rx_buffer_info)
5380 goto err;
9a799d71 5381
9a799d71 5382 /* Round up to nearest 4K */
3a581073
JB		 5383 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5384 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5385
de88eeeb
AD		 5386 set_dev_node(dev, numa_node);
5387 rx_ring->desc = dma_alloc_coherent(dev,
5388 rx_ring->size,
5389 &rx_ring->dma,
5390 GFP_KERNEL);
5391 set_dev_node(dev, orig_node);
5392 if (!rx_ring->desc)
5393 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5394 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5395 if (!rx_ring->desc)
5396 goto err;
9a799d71 5397
3a581073
JB		 5398 rx_ring->next_to_clean = 0;
5399 rx_ring->next_to_use = 0;
9a799d71
AK		 5400
5401 return 0;
b6ec895e
AD		 5402err:
5403 vfree(rx_ring->rx_buffer_info);
5404 rx_ring->rx_buffer_info = NULL;
5405 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5406 return -ENOMEM;
9a799d71
AK		 5407}
5408
69888674
AD		 5409/**
5410 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5411 * @adapter: board private structure
5412 *
5413 * If this function returns with an error, then it's possible one or
5414 * more of the rings is populated (while the rest are not). It is the
5415 * callers duty to clean those orphaned rings.
5416 *
5417 * Return 0 on success, negative on failure
5418 **/
69888674
AD		 5419static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5420{
5421 int i, err = 0;
5422
5423 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5424 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5425 if (!err)
5426 continue;
396e799c 5427 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5428 break;
5429 }
5430
5431 return err;
5432}
5433
9a799d71
AK		 5434/**
5435 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5436 * @tx_ring: Tx descriptor ring for a specific queue
5437 *
5438 * Free all transmit software resources
5439 **/
b6ec895e 5440void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5441{
b6ec895e 5442 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5443
5444 vfree(tx_ring->tx_buffer_info);
5445 tx_ring->tx_buffer_info = NULL;
5446
b6ec895e
AD		 5447 /* if not set, then don't free */
5448 if (!tx_ring->desc)
5449 return;
5450
5451 dma_free_coherent(tx_ring->dev, tx_ring->size,
5452 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5453
5454 tx_ring->desc = NULL;
5455}
5456
5457/**
5458 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5459 * @adapter: board private structure
5460 *
5461 * Free all transmit software resources
5462 **/
5463static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5464{
5465 int i;
5466
5467 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5468 if (adapter->tx_ring[i]->desc)
b6ec895e 5469 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5470}
5471
5472/**
b4617240 5473 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5474 * @rx_ring: ring to clean the resources from
5475 *
5476 * Free all receive software resources
5477 **/
b6ec895e 5478void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5479{
b6ec895e 5480 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5481
5482 vfree(rx_ring->rx_buffer_info);
5483 rx_ring->rx_buffer_info = NULL;
5484
b6ec895e
AD		 5485 /* if not set, then don't free */
5486 if (!rx_ring->desc)
5487 return;
5488
5489 dma_free_coherent(rx_ring->dev, rx_ring->size,
5490 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5491
5492 rx_ring->desc = NULL;
5493}
5494
5495/**
5496 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5497 * @adapter: board private structure
5498 *
5499 * Free all receive software resources
5500 **/
5501static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5502{
5503 int i;
5504
5505 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5506 if (adapter->rx_ring[i]->desc)
b6ec895e 5507 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5508}
5509
9a799d71
AK		 5510/**
5511 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5512 * @netdev: network interface device structure
5513 * @new_mtu: new value for maximum frame size
5514 *
5515 * Returns 0 on success, negative on failure
5516 **/
5517static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5518{
5519 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5520 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5521 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5522
42c783c5 5523 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5524 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5525 hw->mac.type != ixgbe_mac_X540) {
5526 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5527 return -EINVAL;
5528 } else {
5529 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5530 return -EINVAL;
5531 }
9a799d71 5532
396e799c 5533 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5534 /* must set new MTU before calling down or up */
9a799d71
AK		 5535 netdev->mtu = new_mtu;
5536
d4f80882
AV		 5537 if (netif_running(netdev))
5538 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5539
5540 return 0;
5541}
5542
5543/**
5544 * ixgbe_open - Called when a network interface is made active
5545 * @netdev: network interface device structure
5546 *
5547 * Returns 0 on success, negative value on failure
5548 *
5549 * The open entry point is called when a network interface is made
5550 * active by the system (IFF_UP). At this point all resources needed
5551 * for transmit and receive operations are allocated, the interrupt
5552 * handler is registered with the OS, the watchdog timer is started,
5553 * and the stack is notified that the interface is ready.
5554 **/
5555static int ixgbe_open(struct net_device *netdev)
5556{
5557 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5558 int err;
4bebfaa5
AK		 5559
5560 /* disallow open during test */
5561 if (test_bit(__IXGBE_TESTING, &adapter->state))
5562 return -EBUSY;
9a799d71 5563
54386467
JB		 5564 netif_carrier_off(netdev);
5565
9a799d71
AK		 5566 /* allocate transmit descriptors */
5567 err = ixgbe_setup_all_tx_resources(adapter);
5568 if (err)
5569 goto err_setup_tx;
5570
9a799d71
AK		 5571 /* allocate receive descriptors */
5572 err = ixgbe_setup_all_rx_resources(adapter);
5573 if (err)
5574 goto err_setup_rx;
5575
5576 ixgbe_configure(adapter);
5577
021230d4 5578 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5579 if (err)
5580 goto err_req_irq;
5581
c7ccde0f 5582 ixgbe_up_complete(adapter);
9a799d71
AK		 5583
5584 return 0;
5585
9a799d71 5586err_req_irq:
9a799d71 5587err_setup_rx:
a20a1199 5588 ixgbe_free_all_rx_resources(adapter);
9a799d71 5589err_setup_tx:
a20a1199 5590 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5591 ixgbe_reset(adapter);
5592
5593 return err;
5594}
5595
5596/**
5597 * ixgbe_close - Disables a network interface
5598 * @netdev: network interface device structure
5599 *
5600 * Returns 0, this is not allowed to fail
5601 *
5602 * The close entry point is called when an interface is de-activated
5603 * by the OS. The hardware is still under the drivers control, but
5604 * needs to be disabled. A global MAC reset is issued to stop the
5605 * hardware, and all transmit and receive resources are freed.
5606 **/
5607static int ixgbe_close(struct net_device *netdev)
5608{
5609 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5610
5611 ixgbe_down(adapter);
5612 ixgbe_free_irq(adapter);
5613
e4911d57
AD		 5614 ixgbe_fdir_filter_exit(adapter);
5615
9a799d71
AK		 5616 ixgbe_free_all_tx_resources(adapter);
5617 ixgbe_free_all_rx_resources(adapter);
5618
5eba3699 5619 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5620
5621 return 0;
5622}
5623
b3c8b4ba
AD		 5624#ifdef CONFIG_PM
5625static int ixgbe_resume(struct pci_dev *pdev)
5626{
c60fbb00
AD		 5627 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5628 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5629 u32 err;
5630
5631 pci_set_power_state(pdev, PCI_D0);
5632 pci_restore_state(pdev);
656ab817
DS		 5633 /*
5634 * pci_restore_state clears dev->state_saved so call
5635 * pci_save_state to restore it.
5636 */
5637 pci_save_state(pdev);
9ce77666 5638
5639 err = pci_enable_device_mem(pdev);
b3c8b4ba 5640 if (err) {
849c4542 5641 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5642 return err;
5643 }
5644 pci_set_master(pdev);
5645
dd4d8ca6 5646 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5647
5648 err = ixgbe_init_interrupt_scheme(adapter);
5649 if (err) {
849c4542 5650 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5651 return err;
5652 }
5653
b3c8b4ba
AD		 5654 ixgbe_reset(adapter);
5655
495dce12
WJP		 5656 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5657
b3c8b4ba 5658 if (netif_running(netdev)) {
c60fbb00 5659 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5660 if (err)
5661 return err;
5662 }
5663
5664 netif_device_attach(netdev);
5665
5666 return 0;
5667}
b3c8b4ba 5668#endif /* CONFIG_PM */
9d8d05ae
RW		 5669
5670static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5671{
c60fbb00
AD		 5672 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5673 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5674 struct ixgbe_hw *hw = &adapter->hw;
5675 u32 ctrl, fctrl;
5676 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5677#ifdef CONFIG_PM
5678 int retval = 0;
5679#endif
5680
5681 netif_device_detach(netdev);
5682
5683 if (netif_running(netdev)) {
5684 ixgbe_down(adapter);
5685 ixgbe_free_irq(adapter);
5686 ixgbe_free_all_tx_resources(adapter);
5687 ixgbe_free_all_rx_resources(adapter);
5688 }
b3c8b4ba 5689
5f5ae6fc 5690 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5691#ifdef CONFIG_DCB
5692 kfree(adapter->ixgbe_ieee_pfc);
5693 kfree(adapter->ixgbe_ieee_ets);
5694#endif
5f5ae6fc 5695
b3c8b4ba
AD		 5696#ifdef CONFIG_PM
5697 retval = pci_save_state(pdev);
5698 if (retval)
5699 return retval;
4df10466 5700
b3c8b4ba 5701#endif
e8e26350
PW		 5702 if (wufc) {
5703 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5704
e8e26350
PW		 5705 /* turn on all-multi mode if wake on multicast is enabled */
5706 if (wufc & IXGBE_WUFC_MC) {
5707 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5708 fctrl |= IXGBE_FCTRL_MPE;
5709 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5710 }
5711
5712 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5713 ctrl |= IXGBE_CTRL_GIO_DIS;
5714 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5715
5716 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5717 } else {
5718 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5719 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5720 }
5721
bd508178
AD		 5722 switch (hw->mac.type) {
5723 case ixgbe_mac_82598EB:
dd4d8ca6 5724 pci_wake_from_d3(pdev, false);
bd508178
AD		 5725 break;
5726 case ixgbe_mac_82599EB:
b93a2226 5727 case ixgbe_mac_X540:
bd508178
AD		 5728 pci_wake_from_d3(pdev, !!wufc);
5729 break;
5730 default:
5731 break;
5732 }
b3c8b4ba 5733
9d8d05ae
RW		 5734 *enable_wake = !!wufc;
5735
b3c8b4ba
AD		 5736 ixgbe_release_hw_control(adapter);
5737
5738 pci_disable_device(pdev);
5739
9d8d05ae
RW		 5740 return 0;
5741}
5742
5743#ifdef CONFIG_PM
5744static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5745{
5746 int retval;
5747 bool wake;
5748
5749 retval = __ixgbe_shutdown(pdev, &wake);
5750 if (retval)
5751 return retval;
5752
5753 if (wake) {
5754 pci_prepare_to_sleep(pdev);
5755 } else {
5756 pci_wake_from_d3(pdev, false);
5757 pci_set_power_state(pdev, PCI_D3hot);
5758 }
b3c8b4ba
AD		 5759
5760 return 0;
5761}
9d8d05ae 5762#endif /* CONFIG_PM */
b3c8b4ba
AD		 5763
5764static void ixgbe_shutdown(struct pci_dev *pdev)
5765{
9d8d05ae
RW		 5766 bool wake;
5767
5768 __ixgbe_shutdown(pdev, &wake);
5769
5770 if (system_state == SYSTEM_POWER_OFF) {
5771 pci_wake_from_d3(pdev, wake);
5772 pci_set_power_state(pdev, PCI_D3hot);
5773 }
b3c8b4ba
AD		 5774}
5775
9a799d71
AK		 5776/**
5777 * ixgbe_update_stats - Update the board statistics counters.
5778 * @adapter: board private structure
5779 **/
5780void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5781{
2d86f139 5782 struct net_device *netdev = adapter->netdev;
9a799d71 5783 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5784 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5785 u64 total_mpc = 0;
5786 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5787 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5788 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5789 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7b859ebc
AH		 5790#ifdef IXGBE_FCOE
5791 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5792 unsigned int cpu;
5793 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5794#endif /* IXGBE_FCOE */
9a799d71 5795
d08935c2
DS		 5796 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5797 test_bit(__IXGBE_RESETTING, &adapter->state))
5798 return;
5799
94b982b2 5800 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5801 u64 rsc_count = 0;
94b982b2 5802 u64 rsc_flush = 0;
d51019a4
PW		 5803 for (i = 0; i < 16; i++)
5804 adapter->hw_rx_no_dma_resources +=
7ca647bd 5805 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5806 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5807 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5808 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5809 }
5810 adapter->rsc_total_count = rsc_count;
5811 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5812 }
5813
5b7da515
AD		 5814 for (i = 0; i < adapter->num_rx_queues; i++) {
5815 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5816 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5817 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5818 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5819 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5820 bytes += rx_ring->stats.bytes;
5821 packets += rx_ring->stats.packets;
5822 }
5823 adapter->non_eop_descs = non_eop_descs;
5824 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5825 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5826 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5827 netdev->stats.rx_bytes = bytes;
5828 netdev->stats.rx_packets = packets;
5829
5830 bytes = 0;
5831 packets = 0;
7ca3bc58 5832 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5833 for (i = 0; i < adapter->num_tx_queues; i++) {
5834 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5835 restart_queue += tx_ring->tx_stats.restart_queue;
5836 tx_busy += tx_ring->tx_stats.tx_busy;
5837 bytes += tx_ring->stats.bytes;
5838 packets += tx_ring->stats.packets;
5839 }
eb985f09 5840 adapter->restart_queue = restart_queue;
5b7da515
AD		 5841 adapter->tx_busy = tx_busy;
5842 netdev->stats.tx_bytes = bytes;
5843 netdev->stats.tx_packets = packets;
7ca3bc58 5844
7ca647bd 5845 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5846
5847 /* 8 register reads */
6f11eef7
AV		 5848 for (i = 0; i < 8; i++) {
5849 /* for packet buffers not used, the register should read 0 */
5850 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5851 missed_rx += mpc;
7ca647bd
JP		 5852 hwstats->mpc[i] += mpc;
5853 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5854 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5855 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5856 switch (hw->mac.type) {
5857 case ixgbe_mac_82598EB:
1a70db4b
ET		 5858 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5859 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5860 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5861 hwstats->pxonrxc[i] +=
5862 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5863 break;
5864 case ixgbe_mac_82599EB:
b93a2226 5865 case ixgbe_mac_X540:
bd508178
AD		 5866 hwstats->pxonrxc[i] +=
5867 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5868 break;
5869 default:
5870 break;
e8e26350 5871 }
6f11eef7 5872 }
1a70db4b
ET		 5873
5874 /*16 register reads */
5875 for (i = 0; i < 16; i++) {
5876 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5877 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5878 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5879 (hw->mac.type == ixgbe_mac_X540)) {
5880 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5881 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5882 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5883 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5884 }
5885 }
5886
7ca647bd 5887 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5888 /* work around hardware counting issue */
7ca647bd 5889 hwstats->gprc -= missed_rx;
6f11eef7 5890
c84d324c
JF		 5891 ixgbe_update_xoff_received(adapter);
5892
6f11eef7 5893 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5894 switch (hw->mac.type) {
5895 case ixgbe_mac_82598EB:
5896 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5897 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5898 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5899 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5900 break;
b93a2226 5901 case ixgbe_mac_X540:
58f6bcf9
ET		 5902 /* OS2BMC stats are X540 only*/
5903 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5904 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5905 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5906 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5907 case ixgbe_mac_82599EB:
7ca647bd 5908 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5909 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5910 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5911 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5912 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5913 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5914 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5915 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5916 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5917#ifdef IXGBE_FCOE
7ca647bd
JP		 5918 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5919 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5920 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5921 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5922 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5923 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5924 /* Add up per cpu counters for total ddp aloc fail */
5925 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5926 for_each_possible_cpu(cpu) {
5927 fcoe_noddp_counts_sum +=
5928 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5929 fcoe_noddp_ext_buff_counts_sum +=
5930 *per_cpu_ptr(fcoe->
5931 pcpu_noddp_ext_buff, cpu);
5932 }
5933 }
5934 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5935 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5936#endif /* IXGBE_FCOE */
bd508178
AD		 5937 break;
5938 default:
5939 break;
e8e26350 5940 }
9a799d71 5941 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5942 hwstats->bprc += bprc;
5943 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5944 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5945 hwstats->mprc -= bprc;
5946 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5947 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5948 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5949 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5950 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5951 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5952 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5953 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5954 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5955 hwstats->lxontxc += lxon;
6f11eef7 5956 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5957 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5958 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5959 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5960 /*
5961 * 82598 errata - tx of flow control packets is included in tx counters
5962 */
5963 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5964 hwstats->gptc -= xon_off_tot;
5965 hwstats->mptc -= xon_off_tot;
5966 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5967 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5968 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5969 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5970 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5971 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5972 hwstats->ptc64 -= xon_off_tot;
5973 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5974 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5975 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5976 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5977 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5978 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5979
5980 /* Fill out the OS statistics structure */
7ca647bd 5981 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5982
5983 /* Rx Errors */
7ca647bd 5984 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5985 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5986 netdev->stats.rx_length_errors = hwstats->rlec;
5987 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5988 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5989}
5990
5991/**
d034acf1
AD		 5992 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5993 * @adapter - pointer to the device adapter structure
9a799d71 5994 **/
d034acf1 5995static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5996{
cf8280ee 5997 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5998 int i;
cf8280ee 5999
d034acf1
AD		 6000 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6001 return;
6002
6003 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6004
d034acf1 6005 /* if interface is down do nothing */
fe49f04a 6006 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6007 return;
6008
6009 /* do nothing if we are not using signature filters */
6010 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6011 return;
6012
6013 adapter->fdir_overflow++;
6014
93c52dd0
AD		 6015 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6016 for (i = 0; i < adapter->num_tx_queues; i++)
6017 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 6018 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6019 /* re-enable flow director interrupts */
6020 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6021 } else {
6022 e_err(probe, "failed to finish FDIR re-initialization, "
6023 "ignored adding FDIR ATR filters\n");
6024 }
93c52dd0
AD		 6025}
6026
6027/**
6028 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6029 * @adapter - pointer to the device adapter structure
6030 *
6031 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6032 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6033 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6034 * determine if a hang has occurred.
93c52dd0
AD		 6035 */
6036static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6037{
cf8280ee 6038 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6039 u64 eics = 0;
6040 int i;
cf8280ee 6041
93c52dd0
AD		 6042 /* If we're down or resetting, just bail */
6043 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6044 test_bit(__IXGBE_RESETTING, &adapter->state))
6045 return;
22d5a71b 6046
93c52dd0
AD		 6047 /* Force detection of hung controller */
6048 if (netif_carrier_ok(adapter->netdev)) {
6049 for (i = 0; i < adapter->num_tx_queues; i++)
6050 set_check_for_tx_hang(adapter->tx_ring[i]);
6051 }
22d5a71b 6052
fe49f04a
AD		 6053 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6054 /*
6055 * for legacy and MSI interrupts don't set any bits
6056 * that are enabled for EIAM, because this operation
6057 * would set *both* EIMS and EICS for any bit in EIAM
6058 */
6059 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6060 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6061 } else {
6062 /* get one bit for every active tx/rx interrupt vector */
6063 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6064 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6065 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6066 eics |= ((u64)1 << i);
6067 }
cf8280ee 6068 }
9a799d71 6069
93c52dd0 6070 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6071 ixgbe_irq_rearm_queues(adapter, eics);
6072
cf8280ee
JB		 6073}
6074
e8e26350 6075/**
93c52dd0
AD		 6076 * ixgbe_watchdog_update_link - update the link status
6077 * @adapter - pointer to the device adapter structure
6078 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 6079 **/
93c52dd0 6080static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6081{
e8e26350 6082 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6083 u32 link_speed = adapter->link_speed;
6084 bool link_up = adapter->link_up;
c4cf55e5 6085 int i;
e8e26350 6086
93c52dd0
AD		 6087 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6088 return;
6089
6090 if (hw->mac.ops.check_link) {
6091 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6092 } else {
93c52dd0
AD		 6093 /* always assume link is up, if no check link function */
6094 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6095 link_up = true;
c4cf55e5 6096 }
93c52dd0
AD		 6097 if (link_up) {
6098 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6099 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6100 hw->mac.ops.fc_enable(hw, i);
6101 } else {
6102 hw->mac.ops.fc_enable(hw, 0);
6103 }
6104 }
6105
6106 if (link_up ||
6107 time_after(jiffies, (adapter->link_check_timeout +
6108 IXGBE_TRY_LINK_TIMEOUT))) {
6109 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6110 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6111 IXGBE_WRITE_FLUSH(hw);
6112 }
6113
6114 adapter->link_up = link_up;
6115 adapter->link_speed = link_speed;
e8e26350
PW		 6116}
6117
6118/**
93c52dd0
AD		 6119 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6120 * print link up message
6121 * @adapter - pointer to the device adapter structure
e8e26350 6122 **/
93c52dd0 6123static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6124{
93c52dd0 6125 struct net_device *netdev = adapter->netdev;
e8e26350 6126 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6127 u32 link_speed = adapter->link_speed;
6128 bool flow_rx, flow_tx;
e8e26350 6129
93c52dd0
AD		 6130 /* only continue if link was previously down */
6131 if (netif_carrier_ok(netdev))
a985b6c3 6132 return;
63d6e1d8 6133
93c52dd0 6134 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6135
93c52dd0
AD		 6136 switch (hw->mac.type) {
6137 case ixgbe_mac_82598EB: {
6138 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6139 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6140 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6141 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6142 }
6143 break;
6144 case ixgbe_mac_X540:
6145 case ixgbe_mac_82599EB: {
6146 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6147 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6148 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6149 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6150 }
6151 break;
6152 default:
6153 flow_tx = false;
6154 flow_rx = false;
6155 break;
e8e26350 6156 }
93c52dd0
AD		 6157 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6158 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6159 "10 Gbps" :
6160 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6161 "1 Gbps" :
6162 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6163 "100 Mbps" :
6164 "unknown speed"))),
6165 ((flow_rx && flow_tx) ? "RX/TX" :
6166 (flow_rx ? "RX" :
6167 (flow_tx ? "TX" : "None"))));
e8e26350 6168
93c52dd0 6169 netif_carrier_on(netdev);
93c52dd0 6170 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 6171}
6172
c4cf55e5 6173/**
93c52dd0
AD		 6174 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6175 * print link down message
6176 * @adapter - pointer to the adapter structure
c4cf55e5 6177 **/
93c52dd0 6178static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6179{
cf8280ee 6180 struct net_device *netdev = adapter->netdev;
c4cf55e5 6181 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6182
93c52dd0
AD		 6183 adapter->link_up = false;
6184 adapter->link_speed = 0;
cf8280ee 6185
93c52dd0
AD		 6186 /* only continue if link was up previously */
6187 if (!netif_carrier_ok(netdev))
6188 return;
264857b8 6189
93c52dd0
AD		 6190 /* poll for SFP+ cable when link is down */
6191 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6192 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6193
93c52dd0
AD		 6194 e_info(drv, "NIC Link is Down\n");
6195 netif_carrier_off(netdev);
6196}
e8e26350 6197
93c52dd0
AD		 6198/**
6199 * ixgbe_watchdog_flush_tx - flush queues on link down
6200 * @adapter - pointer to the device adapter structure
6201 **/
6202static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6203{
c4cf55e5 6204 int i;
93c52dd0 6205 int some_tx_pending = 0;
c4cf55e5 6206
93c52dd0 6207 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6208 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6209 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6210 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6211 some_tx_pending = 1;
6212 break;
6213 }
6214 }
6215
6216 if (some_tx_pending) {
6217 /* We've lost link, so the controller stops DMA,
6218 * but we've got queued Tx work that's never going
6219 * to get done, so reset controller to flush Tx.
6220 * (Do the reset outside of interrupt context).
6221 */
c83c6cbd 6222 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6223 }
c4cf55e5 6224 }
c4cf55e5
PWJ		 6225}
6226
a985b6c3
GR		 6227static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6228{
6229 u32 ssvpc;
6230
6231 /* Do not perform spoof check for 82598 */
6232 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6233 return;
6234
6235 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6236
6237 /*
6238 * ssvpc register is cleared on read, if zero then no
6239 * spoofed packets in the last interval.
6240 */
6241 if (!ssvpc)
6242 return;
6243
6244 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6245}
6246
93c52dd0
AD		 6247/**
6248 * ixgbe_watchdog_subtask - check and bring link up
6249 * @adapter - pointer to the device adapter structure
6250 **/
6251static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6252{
6253 /* if interface is down do nothing */
7edebf9a
ET		 6254 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6255 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6256 return;
6257
6258 ixgbe_watchdog_update_link(adapter);
6259
6260 if (adapter->link_up)
6261 ixgbe_watchdog_link_is_up(adapter);
6262 else
6263 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6264
a985b6c3 6265 ixgbe_spoof_check(adapter);
9a799d71 6266 ixgbe_update_stats(adapter);
93c52dd0
AD		 6267
6268 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6269}
10eec955 6270
cf8280ee 6271/**
7086400d
AD		 6272 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6273 * @adapter - the ixgbe adapter structure
cf8280ee 6274 **/
7086400d 6275static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6276{
cf8280ee 6277 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6278 s32 err;
cf8280ee 6279
7086400d
AD		 6280 /* not searching for SFP so there is nothing to do here */
6281 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6282 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6283 return;
10eec955 6284
7086400d
AD		 6285 /* someone else is in init, wait until next service event */
6286 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6287 return;
cf8280ee 6288
7086400d
AD		 6289 err = hw->phy.ops.identify_sfp(hw);
6290 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6291 goto sfp_out;
264857b8 6292
7086400d
AD		 6293 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6294 /* If no cable is present, then we need to reset
6295 * the next time we find a good cable. */
6296 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6297 }
9a799d71 6298
7086400d
AD		 6299 /* exit on error */
6300 if (err)
6301 goto sfp_out;
e8e26350 6302
7086400d
AD		 6303 /* exit if reset not needed */
6304 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6305 goto sfp_out;
9a799d71 6306
7086400d 6307 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6308
7086400d
AD		 6309 /*
6310 * A module may be identified correctly, but the EEPROM may not have
6311 * support for that module. setup_sfp() will fail in that case, so
6312 * we should not allow that module to load.
6313 */
6314 if (hw->mac.type == ixgbe_mac_82598EB)
6315 err = hw->phy.ops.reset(hw);
6316 else
6317 err = hw->mac.ops.setup_sfp(hw);
6318
6319 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6320 goto sfp_out;
6321
6322 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6323 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6324
6325sfp_out:
6326 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6327
6328 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6329 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6330 e_dev_err("failed to initialize because an unsupported "
6331 "SFP+ module type was detected.\n");
6332 e_dev_err("Reload the driver after installing a "
6333 "supported module.\n");
6334 unregister_netdev(adapter->netdev);
bc59fcda 6335 }
7086400d 6336}
bc59fcda 6337
7086400d
AD		 6338/**
6339 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6340 * @adapter - the ixgbe adapter structure
6341 **/
6342static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6343{
6344 struct ixgbe_hw *hw = &adapter->hw;
6345 u32 autoneg;
6346 bool negotiation;
6347
6348 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6349 return;
6350
6351 /* someone else is in init, wait until next service event */
6352 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6353 return;
6354
6355 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6356
6357 autoneg = hw->phy.autoneg_advertised;
6358 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6359 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6360 if (hw->mac.ops.setup_link)
6361 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6362
6363 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6364 adapter->link_check_timeout = jiffies;
6365 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6366}
6367
83c61fa9
GR		 6368#ifdef CONFIG_PCI_IOV
6369static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6370{
6371 int vf;
6372 struct ixgbe_hw *hw = &adapter->hw;
6373 struct net_device *netdev = adapter->netdev;
6374 u32 gpc;
6375 u32 ciaa, ciad;
6376
6377 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6378 if (gpc) /* If incrementing then no need for the check below */
6379 return;
6380 /*
6381 * Check to see if a bad DMA write target from an errant or
6382 * malicious VF has caused a PCIe error. If so then we can
6383 * issue a VFLR to the offending VF(s) and then resume without
6384 * requesting a full slot reset.
6385 */
6386
6387 for (vf = 0; vf < adapter->num_vfs; vf++) {
6388 ciaa = (vf << 16) | 0x80000000;
6389 /* 32 bit read so align, we really want status at offset 6 */
6390 ciaa |= PCI_COMMAND;
6391 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6392 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6393 ciaa &= 0x7FFFFFFF;
6394 /* disable debug mode asap after reading data */
6395 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6396 /* Get the upper 16 bits which will be the PCI status reg */
6397 ciad >>= 16;
6398 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6399 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6400 /* Issue VFLR */
6401 ciaa = (vf << 16) | 0x80000000;
6402 ciaa |= 0xA8;
6403 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6404 ciad = 0x00008000; /* VFLR */
6405 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6406 ciaa &= 0x7FFFFFFF;
6407 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6408 }
6409 }
6410}
6411
6412#endif
7086400d
AD		 6413/**
6414 * ixgbe_service_timer - Timer Call-back
6415 * @data: pointer to adapter cast into an unsigned long
6416 **/
6417static void ixgbe_service_timer(unsigned long data)
6418{
6419 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6420 unsigned long next_event_offset;
83c61fa9 6421 bool ready = true;
7086400d 6422
83c61fa9
GR		 6423#ifdef CONFIG_PCI_IOV
6424 ready = false;
6425
6426 /*
6427 * don't bother with SR-IOV VF DMA hang check if there are
6428 * no VFs or the link is down
6429 */
6430 if (!adapter->num_vfs ||
6431 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6432 ready = true;
6433 goto normal_timer_service;
6434 }
6435
6436 /* If we have VFs allocated then we must check for DMA hangs */
6437 ixgbe_check_for_bad_vf(adapter);
6438 next_event_offset = HZ / 50;
6439 adapter->timer_event_accumulator++;
6440
6441 if (adapter->timer_event_accumulator >= 100) {
6442 ready = true;
6443 adapter->timer_event_accumulator = 0;
6444 }
6445
6446 goto schedule_event;
6447
6448normal_timer_service:
6449#endif
7086400d
AD		 6450 /* poll faster when waiting for link */
6451 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6452 next_event_offset = HZ / 10;
6453 else
6454 next_event_offset = HZ * 2;
6455
83c61fa9
GR		 6456#ifdef CONFIG_PCI_IOV
6457schedule_event:
6458#endif
7086400d
AD		 6459 /* Reset the timer */
6460 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6461
83c61fa9
GR		 6462 if (ready)
6463 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6464}
6465
c83c6cbd
AD		 6466static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6467{
6468 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6469 return;
6470
6471 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6472
6473 /* If we're already down or resetting, just bail */
6474 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6475 test_bit(__IXGBE_RESETTING, &adapter->state))
6476 return;
6477
6478 ixgbe_dump(adapter);
6479 netdev_err(adapter->netdev, "Reset adapter\n");
6480 adapter->tx_timeout_count++;
6481
6482 ixgbe_reinit_locked(adapter);
6483}
6484
7086400d
AD		 6485/**
6486 * ixgbe_service_task - manages and runs subtasks
6487 * @work: pointer to work_struct containing our data
6488 **/
6489static void ixgbe_service_task(struct work_struct *work)
6490{
6491 struct ixgbe_adapter *adapter = container_of(work,
6492 struct ixgbe_adapter,
6493 service_task);
6494
c83c6cbd 6495 ixgbe_reset_subtask(adapter);
7086400d
AD		 6496 ixgbe_sfp_detection_subtask(adapter);
6497 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6498 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6499 ixgbe_watchdog_subtask(adapter);
d034acf1 6500 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6501 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6502
6503 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6504}
6505
897ab156
AD		 6506void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6507 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6508{
6509 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6510 u16 i = tx_ring->next_to_use;
9a799d71 6511
e4f74028 6512 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
9a799d71 6513
897ab156
AD		 6514 i++;
6515 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6516
897ab156
AD		 6517 /* set bits to identify this as an advanced context descriptor */
6518 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6519
897ab156
AD		 6520 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6521 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6522 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6523 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6524}
9a799d71 6525
897ab156
AD		 6526static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6527 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6528{
6529 int err;
6530 u32 vlan_macip_lens, type_tucmd;
6531 u32 mss_l4len_idx, l4len;
9a799d71 6532
897ab156
AD		 6533 if (!skb_is_gso(skb))
6534 return 0;
9a799d71 6535
897ab156
AD		 6536 if (skb_header_cloned(skb)) {
6537 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6538 if (err)
6539 return err;
9a799d71 6540 }
9a799d71 6541
897ab156
AD		 6542 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6543 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6544
6545 if (protocol == __constant_htons(ETH_P_IP)) {
6546 struct iphdr *iph = ip_hdr(skb);
6547 iph->tot_len = 0;
6548 iph->check = 0;
6549 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6550 iph->daddr, 0,
6551 IPPROTO_TCP,
6552 0);
6553 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6554 } else if (skb_is_gso_v6(skb)) {
6555 ipv6_hdr(skb)->payload_len = 0;
6556 tcp_hdr(skb)->check =
6557 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6558 &ipv6_hdr(skb)->daddr,
6559 0, IPPROTO_TCP, 0);
6560 }
6561
6562 l4len = tcp_hdrlen(skb);
6563 *hdr_len = skb_transport_offset(skb) + l4len;
6564
6565 /* mss_l4len_id: use 1 as index for TSO */
6566 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6567 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6568 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6569
6570 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6571 vlan_macip_lens = skb_network_header_len(skb);
6572 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6573 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6574
6575 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6576 mss_l4len_idx);
6577
6578 return 1;
6579}
6580
6581static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6582 struct sk_buff *skb, u32 tx_flags,
6583 __be16 protocol)
7ca647bd 6584{
897ab156
AD		 6585 u32 vlan_macip_lens = 0;
6586 u32 mss_l4len_idx = 0;
6587 u32 type_tucmd = 0;
7ca647bd 6588
897ab156 6589 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6590 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6591 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6592 return false;
6593 } else {
6594 u8 l4_hdr = 0;
6595 switch (protocol) {
6596 case __constant_htons(ETH_P_IP):
6597 vlan_macip_lens |= skb_network_header_len(skb);
6598 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6599 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6600 break;
897ab156
AD		 6601 case __constant_htons(ETH_P_IPV6):
6602 vlan_macip_lens |= skb_network_header_len(skb);
6603 l4_hdr = ipv6_hdr(skb)->nexthdr;
6604 break;
6605 default:
6606 if (unlikely(net_ratelimit())) {
6607 dev_warn(tx_ring->dev,
6608 "partial checksum but proto=%x!\n",
6609 skb->protocol);
6610 }
7ca647bd
JP		 6611 break;
6612 }
897ab156
AD		 6613
6614 switch (l4_hdr) {
7ca647bd 6615 case IPPROTO_TCP:
897ab156
AD		 6616 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6617 mss_l4len_idx = tcp_hdrlen(skb) <<
6618 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6619 break;
6620 case IPPROTO_SCTP:
897ab156
AD		 6621 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6622 mss_l4len_idx = sizeof(struct sctphdr) <<
6623 IXGBE_ADVTXD_L4LEN_SHIFT;
6624 break;
6625 case IPPROTO_UDP:
6626 mss_l4len_idx = sizeof(struct udphdr) <<
6627 IXGBE_ADVTXD_L4LEN_SHIFT;
6628 break;
6629 default:
6630 if (unlikely(net_ratelimit())) {
6631 dev_warn(tx_ring->dev,
6632 "partial checksum but l4 proto=%x!\n",
6633 skb->protocol);
6634 }
7ca647bd
JP		 6635 break;
6636 }
7ca647bd
JP		 6637 }
6638
897ab156
AD		 6639 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6640 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6641
897ab156
AD		 6642 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6643 type_tucmd, mss_l4len_idx);
9a799d71 6644
897ab156 6645 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6646}
6647
d3d00239 6648static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6649{
d3d00239
AD		 6650 /* set type for advanced descriptor with frame checksum insertion */
6651 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6652 IXGBE_ADVTXD_DCMD_IFCS |
6653 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6654
d3d00239 6655 /* set HW vlan bit if vlan is present */
66f32a8b 6656 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6657 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6658
d3d00239
AD		 6659 /* set segmentation enable bits for TSO/FSO */
6660#ifdef IXGBE_FCOE
6661 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6662#else
6663 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6664#endif
6665 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6666
d3d00239
AD		 6667 return cmd_type;
6668}
9a799d71 6669
d3d00239
AD		 6670static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6671{
6672 __le32 olinfo_status =
6673 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6674
d3d00239
AD		 6675 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6676 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6677 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6678 /* enble IPv4 checksum for TSO */
6679 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6680 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6681 }
6682
d3d00239
AD		 6683 /* enable L4 checksum for TSO and TX checksum offload */
6684 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6685 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6686
d3d00239
AD		 6687#ifdef IXGBE_FCOE
6688 /* use index 1 context for FCOE/FSO */
6689 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6690 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6691 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6692
d3d00239 6693#endif
7f9643fd
AD		 6694 /*
6695 * Check Context must be set if Tx switch is enabled, which it
6696 * always is for case where virtual functions are running
6697 */
6698 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6699 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6700
d3d00239
AD		 6701 return olinfo_status;
6702}
44df32c5 6703
d3d00239
AD		 6704#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6705 IXGBE_TXD_CMD_RS)
6706
6707static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6708 struct sk_buff *skb,
6709 struct ixgbe_tx_buffer *first,
6710 u32 tx_flags,
6711 const u8 hdr_len)
6712{
6713 struct device *dev = tx_ring->dev;
6714 struct ixgbe_tx_buffer *tx_buffer_info;
6715 union ixgbe_adv_tx_desc *tx_desc;
6716 dma_addr_t dma;
6717 __le32 cmd_type, olinfo_status;
6718 struct skb_frag_struct *frag;
6719 unsigned int f = 0;
6720 unsigned int data_len = skb->data_len;
6721 unsigned int size = skb_headlen(skb);
6722 u32 offset = 0;
6723 u32 paylen = skb->len - hdr_len;
6724 u16 i = tx_ring->next_to_use;
6725 u16 gso_segs;
6726
6727#ifdef IXGBE_FCOE
6728 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6729 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6730 data_len -= sizeof(struct fcoe_crc_eof);
6731 } else {
6732 size -= sizeof(struct fcoe_crc_eof) - data_len;
6733 data_len = 0;
9a799d71
AK		 6734 }
6735 }
44df32c5 6736
d3d00239
AD		 6737#endif
6738 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6739 if (dma_mapping_error(dev, dma))
6740 goto dma_error;
8ad494b0 6741
d3d00239
AD		 6742 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6743 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6744
e4f74028 6745 tx_desc = IXGBE_TX_DESC(tx_ring, i);
e5a43549 6746
d3d00239
AD		 6747 for (;;) {
6748 while (size > IXGBE_MAX_DATA_PER_TXD) {
6749 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6750 tx_desc->read.cmd_type_len =
6751 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6752 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6753
d3d00239
AD		 6754 offset += IXGBE_MAX_DATA_PER_TXD;
6755 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6756
d3d00239
AD		 6757 tx_desc++;
6758 i++;
6759 if (i == tx_ring->count) {
e4f74028 6760 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6761 i = 0;
6762 }
6763 }
e5a43549 6764
e5a43549 6765 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6766 tx_buffer_info->length = offset + size;
6767 tx_buffer_info->tx_flags = tx_flags;
6768 tx_buffer_info->dma = dma;
9a799d71 6769
d3d00239
AD		 6770 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6771 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6772 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6773
d3d00239
AD		 6774 if (!data_len)
6775 break;
9a799d71 6776
d3d00239
AD		 6777 frag = &skb_shinfo(skb)->frags[f];
6778#ifdef IXGBE_FCOE
9e903e08 6779 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6780#else
9e903e08 6781 size = skb_frag_size(frag);
d3d00239
AD		 6782#endif
6783 data_len -= size;
6784 f++;
9a799d71 6785
d3d00239
AD		 6786 offset = 0;
6787 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6788
877749bf 6789 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6790 if (dma_mapping_error(dev, dma))
6791 goto dma_error;
9a799d71 6792
d3d00239
AD		 6793 tx_desc++;
6794 i++;
6795 if (i == tx_ring->count) {
e4f74028 6796 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6797 i = 0;
6798 }
6799 }
9a799d71 6800
d3d00239 6801 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6802
d3d00239
AD		 6803 i++;
6804 if (i == tx_ring->count)
6805 i = 0;
9a799d71 6806
d3d00239 6807 tx_ring->next_to_use = i;
eacd73f7 6808
d3d00239
AD		 6809 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6810 gso_segs = skb_shinfo(skb)->gso_segs;
6811#ifdef IXGBE_FCOE
6812 /* adjust for FCoE Sequence Offload */
6813 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6814 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6815 skb_shinfo(skb)->gso_size);
6816#endif /* IXGBE_FCOE */
6817 else
6818 gso_segs = 1;
9a799d71 6819
d3d00239
AD		 6820 /* multiply data chunks by size of headers */
6821 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6822 tx_buffer_info->gso_segs = gso_segs;
6823 tx_buffer_info->skb = skb;
9a799d71 6824
b2d96e0a
AD		 6825 netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer_info->bytecount);
6826
d3d00239
AD		 6827 /* set the timestamp */
6828 first->time_stamp = jiffies;
9a799d71
AK		 6829
6830 /*
6831 * Force memory writes to complete before letting h/w
6832 * know there are new descriptors to fetch. (Only
6833 * applicable for weak-ordered memory model archs,
6834 * such as IA-64).
6835 */
6836 wmb();
6837
d3d00239
AD		 6838 /* set next_to_watch value indicating a packet is present */
6839 first->next_to_watch = tx_desc;
6840
6841 /* notify HW of packet */
84ea2591 6842 writel(i, tx_ring->tail);
d3d00239
AD		 6843
6844 return;
6845dma_error:
6846 dev_err(dev, "TX DMA map failed\n");
6847
6848 /* clear dma mappings for failed tx_buffer_info map */
6849 for (;;) {
6850 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6851 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6852 if (tx_buffer_info == first)
6853 break;
6854 if (i == 0)
6855 i = tx_ring->count;
6856 i--;
6857 }
6858
6859 dev_kfree_skb_any(skb);
6860
6861 tx_ring->next_to_use = i;
9a799d71
AK		 6862}
6863
69830529
AD		 6864static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6865 u32 tx_flags, __be16 protocol)
6866{
6867 struct ixgbe_q_vector *q_vector = ring->q_vector;
6868 union ixgbe_atr_hash_dword input = { .dword = 0 };
6869 union ixgbe_atr_hash_dword common = { .dword = 0 };
6870 union {
6871 unsigned char *network;
6872 struct iphdr *ipv4;
6873 struct ipv6hdr *ipv6;
6874 } hdr;
ee9e0f0b 6875 struct tcphdr *th;
905e4a41 6876 __be16 vlan_id;
c4cf55e5 6877
69830529
AD		 6878 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6879 if (!q_vector)
6880 return;
6881
6882 /* do nothing if sampling is disabled */
6883 if (!ring->atr_sample_rate)
d3ead241 6884 return;
c4cf55e5 6885
69830529 6886 ring->atr_count++;
c4cf55e5 6887
69830529
AD		 6888 /* snag network header to get L4 type and address */
6889 hdr.network = skb_network_header(skb);
6890
6891 /* Currently only IPv4/IPv6 with TCP is supported */
6892 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6893 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6894 (protocol != __constant_htons(ETH_P_IP) ||
6895 hdr.ipv4->protocol != IPPROTO_TCP))
6896 return;
ee9e0f0b
AD		 6897
6898 th = tcp_hdr(skb);
c4cf55e5 6899
66f32a8b
AD		 6900 /* skip this packet since it is invalid or the socket is closing */
6901 if (!th || th->fin)
69830529
AD		 6902 return;
6903
6904 /* sample on all syn packets or once every atr sample count */
6905 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6906 return;
6907
6908 /* reset sample count */
6909 ring->atr_count = 0;
6910
6911 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6912
6913 /*
6914 * src and dst are inverted, think how the receiver sees them
6915 *
6916 * The input is broken into two sections, a non-compressed section
6917 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6918 * is XORed together and stored in the compressed dword.
6919 */
6920 input.formatted.vlan_id = vlan_id;
6921
6922 /*
6923 * since src port and flex bytes occupy the same word XOR them together
6924 * and write the value to source port portion of compressed dword
6925 */
66f32a8b 6926 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6927 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6928 else
6929 common.port.src ^= th->dest ^ protocol;
6930 common.port.dst ^= th->source;
6931
6932 if (protocol == __constant_htons(ETH_P_IP)) {
6933 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6934 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6935 } else {
6936 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6937 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6938 hdr.ipv6->saddr.s6_addr32[1] ^
6939 hdr.ipv6->saddr.s6_addr32[2] ^
6940 hdr.ipv6->saddr.s6_addr32[3] ^
6941 hdr.ipv6->daddr.s6_addr32[0] ^
6942 hdr.ipv6->daddr.s6_addr32[1] ^
6943 hdr.ipv6->daddr.s6_addr32[2] ^
6944 hdr.ipv6->daddr.s6_addr32[3];
6945 }
c4cf55e5
PWJ		 6946
6947 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6948 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6949 input, common, ring->queue_index);
c4cf55e5
PWJ		 6950}
6951
63544e9c 6952static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6953{
fc77dc3c 6954 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6955 /* Herbert's original patch had:
6956 * smp_mb__after_netif_stop_queue();
6957 * but since that doesn't exist yet, just open code it. */
6958 smp_mb();
6959
6960 /* We need to check again in a case another CPU has just
6961 * made room available. */
7d4987de 6962 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6963 return -EBUSY;
6964
6965 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6966 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6967 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6968 return 0;
6969}
6970
82d4e46e 6971static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6972{
7d4987de 6973 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6974 return 0;
fc77dc3c 6975 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6976}
6977
09a3b1f8
SH		 6978static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6979{
6980 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6981 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6982 smp_processor_id();
56075a98 6983#ifdef IXGBE_FCOE
6440752c 6984 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6985
e5b64635
JF		 6986 if (((protocol == htons(ETH_P_FCOE)) ||
6987 (protocol == htons(ETH_P_FIP))) &&
6988 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6989 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6990 txq += adapter->ring_feature[RING_F_FCOE].mask;
6991 return txq;
56075a98
JF		 6992 }
6993#endif
6994
fdd3d631
KK		 6995 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6996 while (unlikely(txq >= dev->real_num_tx_queues))
6997 txq -= dev->real_num_tx_queues;
5f715823 6998 return txq;
fdd3d631 6999 }
c4cf55e5 7000
09a3b1f8
SH		 7001 return skb_tx_hash(dev, skb);
7002}
7003
fc77dc3c 7004netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7005 struct ixgbe_adapter *adapter,
7006 struct ixgbe_ring *tx_ring)
9a799d71 7007{
d3d00239 7008 struct ixgbe_tx_buffer *first;
5f715823 7009 int tso;
d3d00239 7010 u32 tx_flags = 0;
a535c30e
AD		 7011#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7012 unsigned short f;
7013#endif
a535c30e 7014 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7015 __be16 protocol = skb->protocol;
63544e9c 7016 u8 hdr_len = 0;
5e09a105 7017
a535c30e
AD		 7018 /*
7019 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7020 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7021 * + 2 desc gap to keep tail from touching head,
7022 * + 1 desc for context descriptor,
7023 * otherwise try next time
7024 */
7025#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7026 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7027 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7028#else
7029 count += skb_shinfo(skb)->nr_frags;
7030#endif
7031 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7032 tx_ring->tx_stats.tx_busy++;
7033 return NETDEV_TX_BUSY;
7034 }
7035
66f32a8b 7036 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7037 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7038 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7039 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7040 /* else if it is a SW VLAN check the next protocol and store the tag */
7041 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7042 struct vlan_hdr *vhdr, _vhdr;
7043 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7044 if (!vhdr)
7045 goto out_drop;
7046
7047 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7048 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7049 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7050 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7051 }
7052
9e0c5648
AD		 7053#ifdef CONFIG_PCI_IOV
7054 /*
7055 * Use the l2switch_enable flag - would be false if the DMA
7056 * Tx switch had been disabled.
7057 */
7058 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7059 tx_flags |= IXGBE_TX_FLAGS_TXSW;
7060
7061#endif
32701dc2 7062 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7063 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7064 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7065 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7066 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7067 tx_flags |= (skb->priority & 0x7) <<
7068 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7069 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7070 struct vlan_ethhdr *vhdr;
7071 if (skb_header_cloned(skb) &&
7072 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7073 goto out_drop;
7074 vhdr = (struct vlan_ethhdr *)skb->data;
7075 vhdr->h_vlan_TCI = htons(tx_flags >>
7076 IXGBE_TX_FLAGS_VLAN_SHIFT);
7077 } else {
7078 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7079 }
9a799d71 7080 }
eacd73f7 7081
a535c30e 7082 /* record the location of the first descriptor for this packet */
d3d00239 7083 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 7084
eacd73f7 7085#ifdef IXGBE_FCOE
66f32a8b
AD		 7086 /* setup tx offload for FCoE */
7087 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
7088 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 7089 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
7090 if (tso < 0)
7091 goto out_drop;
7092 else if (tso)
66f32a8b
AD		 7093 tx_flags |= IXGBE_TX_FLAGS_FSO |
7094 IXGBE_TX_FLAGS_FCOE;
7095 else
7096 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 7097
66f32a8b 7098 goto xmit_fcoe;
eacd73f7 7099 }
9a799d71 7100
66f32a8b
AD		 7101#endif /* IXGBE_FCOE */
7102 /* setup IPv4/IPv6 offloads */
7103 if (protocol == __constant_htons(ETH_P_IP))
7104 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 7105
66f32a8b
AD		 7106 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
7107 if (tso < 0)
897ab156 7108 goto out_drop;
66f32a8b
AD		 7109 else if (tso)
7110 tx_flags |= IXGBE_TX_FLAGS_TSO;
7111 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
7112 tx_flags |= IXGBE_TX_FLAGS_CSUM;
7113
7114 /* add the ATR filter if ATR is on */
7115 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7116 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7117
7118#ifdef IXGBE_FCOE
7119xmit_fcoe:
7120#endif /* IXGBE_FCOE */
d3d00239
AD		 7121 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
7122
7123 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7124
7125 return NETDEV_TX_OK;
897ab156
AD		 7126
7127out_drop:
7128 dev_kfree_skb_any(skb);
7129 return NETDEV_TX_OK;
9a799d71
AK		 7130}
7131
84418e3b
AD		 7132static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7133{
7134 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7135 struct ixgbe_ring *tx_ring;
7136
7137 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 7138 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7139}
7140
9a799d71
AK		 7141/**
7142 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7143 * @netdev: network interface device structure
7144 * @p: pointer to an address structure
7145 *
7146 * Returns 0 on success, negative on failure
7147 **/
7148static int ixgbe_set_mac(struct net_device *netdev, void *p)
7149{
7150 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7151 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7152 struct sockaddr *addr = p;
7153
7154 if (!is_valid_ether_addr(addr->sa_data))
7155 return -EADDRNOTAVAIL;
7156
7157 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7158 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7159
1cdd1ec8
GR		 7160 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7161 IXGBE_RAH_AV);
9a799d71
AK		 7162
7163 return 0;
7164}
7165
6b73e10d
BH		 7166static int
7167ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7168{
7169 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7170 struct ixgbe_hw *hw = &adapter->hw;
7171 u16 value;
7172 int rc;
7173
7174 if (prtad != hw->phy.mdio.prtad)
7175 return -EINVAL;
7176 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7177 if (!rc)
7178 rc = value;
7179 return rc;
7180}
7181
7182static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7183 u16 addr, u16 value)
7184{
7185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7186 struct ixgbe_hw *hw = &adapter->hw;
7187
7188 if (prtad != hw->phy.mdio.prtad)
7189 return -EINVAL;
7190 return hw->phy.ops.write_reg(hw, addr, devad, value);
7191}
7192
7193static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7194{
7195 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7196
7197 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7198}
7199
0365e6e4
PW		 7200/**
7201 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7202 * netdev->dev_addrs
0365e6e4
PW		 7203 * @netdev: network interface device structure
7204 *
7205 * Returns non-zero on failure
7206 **/
7207static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7208{
7209 int err = 0;
7210 struct ixgbe_adapter *adapter = netdev_priv(dev);
7211 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7212
7213 if (is_valid_ether_addr(mac->san_addr)) {
7214 rtnl_lock();
7215 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7216 rtnl_unlock();
7217 }
7218 return err;
7219}
7220
7221/**
7222 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7223 * netdev->dev_addrs
0365e6e4
PW		 7224 * @netdev: network interface device structure
7225 *
7226 * Returns non-zero on failure
7227 **/
7228static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7229{
7230 int err = 0;
7231 struct ixgbe_adapter *adapter = netdev_priv(dev);
7232 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7233
7234 if (is_valid_ether_addr(mac->san_addr)) {
7235 rtnl_lock();
7236 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7237 rtnl_unlock();
7238 }
7239 return err;
7240}
7241
9a799d71
AK		 7242#ifdef CONFIG_NET_POLL_CONTROLLER
7243/*
7244 * Polling 'interrupt' - used by things like netconsole to send skbs
7245 * without having to re-enable interrupts. It's not called while
7246 * the interrupt routine is executing.
7247 */
7248static void ixgbe_netpoll(struct net_device *netdev)
7249{
7250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7251 int i;
9a799d71 7252
1a647bd2
AD		 7253 /* if interface is down do nothing */
7254 if (test_bit(__IXGBE_DOWN, &adapter->state))
7255 return;
7256
9a799d71 7257 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7258 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7259 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7260 for (i = 0; i < num_q_vectors; i++) {
7261 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7262 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7263 }
7264 } else {
7265 ixgbe_intr(adapter->pdev->irq, netdev);
7266 }
9a799d71 7267 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7268}
7269#endif
7270
de1036b1
ED		 7271static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7272 struct rtnl_link_stats64 *stats)
7273{
7274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7275 int i;
7276
1a51502b 7277 rcu_read_lock();
de1036b1 7278 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7279 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7280 u64 bytes, packets;
7281 unsigned int start;
7282
1a51502b
ED		 7283 if (ring) {
7284 do {
7285 start = u64_stats_fetch_begin_bh(&ring->syncp);
7286 packets = ring->stats.packets;
7287 bytes = ring->stats.bytes;
7288 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7289 stats->rx_packets += packets;
7290 stats->rx_bytes += bytes;
7291 }
de1036b1 7292 }
1ac9ad13
ED		 7293
7294 for (i = 0; i < adapter->num_tx_queues; i++) {
7295 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7296 u64 bytes, packets;
7297 unsigned int start;
7298
7299 if (ring) {
7300 do {
7301 start = u64_stats_fetch_begin_bh(&ring->syncp);
7302 packets = ring->stats.packets;
7303 bytes = ring->stats.bytes;
7304 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7305 stats->tx_packets += packets;
7306 stats->tx_bytes += bytes;
7307 }
7308 }
1a51502b 7309 rcu_read_unlock();
de1036b1
ED		 7310 /* following stats updated by ixgbe_watchdog_task() */
7311 stats->multicast = netdev->stats.multicast;
7312 stats->rx_errors = netdev->stats.rx_errors;
7313 stats->rx_length_errors = netdev->stats.rx_length_errors;
7314 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7315 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7316 return stats;
7317}
7318
8b1c0b24
JF		 7319/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7320 * #adapter: pointer to ixgbe_adapter
7321 * @tc: number of traffic classes currently enabled
7322 *
7323 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7324 * 802.1Q priority maps to a packet buffer that exists.
7325 */
7326static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7327{
7328 struct ixgbe_hw *hw = &adapter->hw;
7329 u32 reg, rsave;
7330 int i;
7331
7332 /* 82598 have a static priority to TC mapping that can not
7333 * be changed so no validation is needed.
7334 */
7335 if (hw->mac.type == ixgbe_mac_82598EB)
7336 return;
7337
7338 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7339 rsave = reg;
7340
7341 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7342 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7343
7344 /* If up2tc is out of bounds default to zero */
7345 if (up2tc > tc)
7346 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7347 }
7348
7349 if (reg != rsave)
7350 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7351
7352 return;
7353}
7354
7355
7356/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7357 * classes.
7358 *
7359 * @netdev: net device to configure
7360 * @tc: number of traffic classes to enable
7361 */
7362int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7363{
8b1c0b24
JF		 7364 struct ixgbe_adapter *adapter = netdev_priv(dev);
7365 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7366
e7589eab
JF		 7367 /* Multiple traffic classes requires multiple queues */
7368 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7369 e_err(drv, "Enable failed, needs MSI-X\n");
7370 return -EINVAL;
7371 }
8b1c0b24
JF		 7372
7373 /* Hardware supports up to 8 traffic classes */
4de2a022 7374 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7375 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7376 return -EINVAL;
7377
7378 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7379 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7380 * hardware is not flexible enough to do this dynamically.
7381 */
7382 if (netif_running(dev))
7383 ixgbe_close(dev);
7384 ixgbe_clear_interrupt_scheme(adapter);
7385
e7589eab 7386 if (tc) {
8b1c0b24 7387 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7388 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7389
7390 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7391 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7392
7393 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7394 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7395 } else {
8b1c0b24
JF		 7396 netdev_reset_tc(dev);
7397
e7589eab
JF		 7398 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7399
7400 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7401 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7402
7403 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7404 adapter->dcb_cfg.pfc_mode_enable = false;
7405 }
7406
8b1c0b24
JF		 7407 ixgbe_init_interrupt_scheme(adapter);
7408 ixgbe_validate_rtr(adapter, tc);
7409 if (netif_running(dev))
7410 ixgbe_open(dev);
7411
7412 return 0;
7413}
de1036b1 7414
082757af
DS		 7415void ixgbe_do_reset(struct net_device *netdev)
7416{
7417 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7418
7419 if (netif_running(netdev))
7420 ixgbe_reinit_locked(adapter);
7421 else
7422 ixgbe_reset(adapter);
7423}
7424
c8f44aff
MM		 7425static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7426 netdev_features_t data)
082757af
DS		 7427{
7428 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7429
7430#ifdef CONFIG_DCB
7431 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7432 data &= ~NETIF_F_HW_VLAN_RX;
7433#endif
7434
7435 /* return error if RXHASH is being enabled when RSS is not supported */
7436 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7437 data &= ~NETIF_F_RXHASH;
7438
7439 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7440 if (!(data & NETIF_F_RXCSUM))
7441 data &= ~NETIF_F_LRO;
7442
7443 /* Turn off LRO if not RSC capable or invalid ITR settings */
7444 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7445 data &= ~NETIF_F_LRO;
7446 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7447 (adapter->rx_itr_setting != 1 &&
7448 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7449 data &= ~NETIF_F_LRO;
7450 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7451 }
7452
7453 return data;
7454}
7455
c8f44aff
MM		 7456static int ixgbe_set_features(struct net_device *netdev,
7457 netdev_features_t data)
082757af
DS		 7458{
7459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7460 bool need_reset = false;
7461
082757af
DS		 7462 /* Make sure RSC matches LRO, reset if change */
7463 if (!!(data & NETIF_F_LRO) !=
7464 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7465 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7466 switch (adapter->hw.mac.type) {
7467 case ixgbe_mac_X540:
7468 case ixgbe_mac_82599EB:
7469 need_reset = true;
7470 break;
7471 default:
7472 break;
7473 }
7474 }
7475
7476 /*
7477 * Check if Flow Director n-tuple support was enabled or disabled. If
7478 * the state changed, we need to reset.
7479 */
7480 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7481 /* turn off ATR, enable perfect filters and reset */
7482 if (data & NETIF_F_NTUPLE) {
7483 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7484 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7485 need_reset = true;
7486 }
7487 } else if (!(data & NETIF_F_NTUPLE)) {
7488 /* turn off Flow Director, set ATR and reset */
7489 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7490 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7491 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7492 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7493 need_reset = true;
7494 }
7495
7496 if (need_reset)
7497 ixgbe_do_reset(netdev);
7498
7499 return 0;
7500
7501}
7502
0edc3527 7503static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7504 .ndo_open = ixgbe_open,
0edc3527 7505 .ndo_stop = ixgbe_close,
00829823 7506 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7507 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7508 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7509 .ndo_validate_addr = eth_validate_addr,
7510 .ndo_set_mac_address = ixgbe_set_mac,
7511 .ndo_change_mtu = ixgbe_change_mtu,
7512 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7513 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7514 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7515 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7516 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7517 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7518 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7519 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7520 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7521 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7522 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7523#ifdef CONFIG_NET_POLL_CONTROLLER
7524 .ndo_poll_controller = ixgbe_netpoll,
7525#endif
332d4a7d
YZ		 7526#ifdef IXGBE_FCOE
7527 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7528 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7529 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7530 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7531 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7532 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7533 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7534#endif /* IXGBE_FCOE */
082757af
DS		 7535 .ndo_set_features = ixgbe_set_features,
7536 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7537};
7538
1cdd1ec8
GR		 7539static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7540 const struct ixgbe_info *ii)
7541{
7542#ifdef CONFIG_PCI_IOV
7543 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7544
c6bda30a 7545 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7546 return;
7547
7548 /* The 82599 supports up to 64 VFs per physical function
7549 * but this implementation limits allocation to 63 so that
7550 * basic networking resources are still available to the
7551 * physical function
7552 */
7553 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7554 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7555#endif /* CONFIG_PCI_IOV */
7556}
7557
9a799d71
AK		 7558/**
7559 * ixgbe_probe - Device Initialization Routine
7560 * @pdev: PCI device information struct
7561 * @ent: entry in ixgbe_pci_tbl
7562 *
7563 * Returns 0 on success, negative on failure
7564 *
7565 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7566 * The OS initialization, configuring of the adapter private structure,
7567 * and a hardware reset occur.
7568 **/
7569static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7570 const struct pci_device_id *ent)
9a799d71
AK		 7571{
7572 struct net_device *netdev;
7573 struct ixgbe_adapter *adapter = NULL;
7574 struct ixgbe_hw *hw;
7575 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7576 static int cards_found;
7577 int i, err, pci_using_dac;
289700db 7578 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7579 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7580#ifdef IXGBE_FCOE
7581 u16 device_caps;
7582#endif
289700db 7583 u32 eec;
c23f5b6b 7584 u16 wol_cap;
9a799d71 7585
bded64a7
AG		 7586 /* Catch broken hardware that put the wrong VF device ID in
7587 * the PCIe SR-IOV capability.
7588 */
7589 if (pdev->is_virtfn) {
7590 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7591 pci_name(pdev), pdev->vendor, pdev->device);
7592 return -EINVAL;
7593 }
7594
9ce77666 7595 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7596 if (err)
7597 return err;
7598
1b507730
NN		 7599 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7600 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7601 pci_using_dac = 1;
7602 } else {
1b507730 7603 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7604 if (err) {
1b507730
NN		 7605 err = dma_set_coherent_mask(&pdev->dev,
7606 DMA_BIT_MASK(32));
9a799d71 7607 if (err) {
b8bc0421
DC		 7608 dev_err(&pdev->dev,
7609 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7610 goto err_dma;
7611 }
7612 }
7613 pci_using_dac = 0;
7614 }
7615
9ce77666 7616 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7617 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7618 if (err) {
b8bc0421
DC		 7619 dev_err(&pdev->dev,
7620 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7621 goto err_pci_reg;
7622 }
7623
19d5afd4 7624 pci_enable_pcie_error_reporting(pdev);
6fabd715 7625
9a799d71 7626 pci_set_master(pdev);
fb3b27bc 7627 pci_save_state(pdev);
9a799d71 7628
e901acd6
JF		 7629#ifdef CONFIG_IXGBE_DCB
7630 indices *= MAX_TRAFFIC_CLASS;
7631#endif
7632
c85a2618
JF		 7633 if (ii->mac == ixgbe_mac_82598EB)
7634 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7635 else
7636 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7637
e901acd6 7638#ifdef IXGBE_FCOE
c85a2618
JF		 7639 indices += min_t(unsigned int, num_possible_cpus(),
7640 IXGBE_MAX_FCOE_INDICES);
7641#endif
c85a2618 7642 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7643 if (!netdev) {
7644 err = -ENOMEM;
7645 goto err_alloc_etherdev;
7646 }
7647
9a799d71
AK		 7648 SET_NETDEV_DEV(netdev, &pdev->dev);
7649
9a799d71 7650 adapter = netdev_priv(netdev);
c60fbb00 7651 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7652
7653 adapter->netdev = netdev;
7654 adapter->pdev = pdev;
7655 hw = &adapter->hw;
7656 hw->back = adapter;
7657 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7658
05857980 7659 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7660 pci_resource_len(pdev, 0));
9a799d71
AK		 7661 if (!hw->hw_addr) {
7662 err = -EIO;
7663 goto err_ioremap;
7664 }
7665
7666 for (i = 1; i <= 5; i++) {
7667 if (pci_resource_len(pdev, i) == 0)
7668 continue;
7669 }
7670
0edc3527 7671 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7672 ixgbe_set_ethtool_ops(netdev);
9a799d71 7673 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7674 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7675
9a799d71
AK		 7676 adapter->bd_number = cards_found;
7677
9a799d71
AK		 7678 /* Setup hw api */
7679 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7680 hw->mac.type = ii->mac;
9a799d71 7681
c44ade9e
JB		 7682 /* EEPROM */
7683 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7684 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7685 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7686 if (!(eec & (1 << 8)))
7687 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7688
7689 /* PHY */
7690 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7691 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7692 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7693 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7694 hw->phy.mdio.mmds = 0;
7695 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7696 hw->phy.mdio.dev = netdev;
7697 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7698 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7699
8ca783ab 7700 ii->get_invariants(hw);
9a799d71
AK		 7701
7702 /* setup the private structure */
7703 err = ixgbe_sw_init(adapter);
7704 if (err)
7705 goto err_sw_init;
7706
e86bff0e 7707 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7708 switch (adapter->hw.mac.type) {
7709 case ixgbe_mac_82599EB:
7710 case ixgbe_mac_X540:
e86bff0e 7711 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7712 break;
7713 default:
7714 break;
7715 }
e86bff0e 7716
bf069c97
DS		 7717 /*
7718 * If there is a fan on this device and it has failed log the
7719 * failure.
7720 */
7721 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7722 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7723 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7724 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7725 }
7726
8ef78adc
PWJ		 7727 if (allow_unsupported_sfp)
7728 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7729
c44ade9e 7730 /* reset_hw fills in the perm_addr as well */
119fc60a 7731 hw->phy.reset_if_overtemp = true;
c44ade9e 7732 err = hw->mac.ops.reset_hw(hw);
119fc60a 7733 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7734 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7735 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7736 err = 0;
7737 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7738 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7739 "module type was detected.\n");
7740 e_dev_err("Reload the driver after installing a supported "
7741 "module.\n");
04f165ef
PW		 7742 goto err_sw_init;
7743 } else if (err) {
849c4542 7744 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7745 goto err_sw_init;
7746 }
7747
1cdd1ec8
GR		 7748 ixgbe_probe_vf(adapter, ii);
7749
396e799c 7750 netdev->features = NETIF_F_SG |
e8e9f696 7751 NETIF_F_IP_CSUM |
082757af 7752 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7753 NETIF_F_HW_VLAN_TX |
7754 NETIF_F_HW_VLAN_RX |
082757af
DS		 7755 NETIF_F_HW_VLAN_FILTER |
7756 NETIF_F_TSO |
7757 NETIF_F_TSO6 |
082757af
DS		 7758 NETIF_F_RXHASH |
7759 NETIF_F_RXCSUM;
9a799d71 7760
082757af 7761 netdev->hw_features = netdev->features;
ad31c402 7762
58be7666
DS		 7763 switch (adapter->hw.mac.type) {
7764 case ixgbe_mac_82599EB:
7765 case ixgbe_mac_X540:
45a5ead0 7766 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7767 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7768 NETIF_F_NTUPLE;
58be7666
DS		 7769 break;
7770 default:
7771 break;
7772 }
45a5ead0 7773
ad31c402
JK		 7774 netdev->vlan_features |= NETIF_F_TSO;
7775 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7776 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7777 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7778 netdev->vlan_features |= NETIF_F_SG;
7779
01789349
JP		 7780 netdev->priv_flags |= IFF_UNICAST_FLT;
7781
1cdd1ec8
GR		 7782 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7783 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7784 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7785
7a6b6f51 7786#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7787 netdev->dcbnl_ops = &dcbnl_ops;
7788#endif
7789
eacd73f7 7790#ifdef IXGBE_FCOE
0d551589 7791 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7792 if (hw->mac.ops.get_device_caps) {
7793 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7794 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7795 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7796 }
7797 }
5e09d7f6
YZ		 7798 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7799 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7800 netdev->vlan_features |= NETIF_F_FSO;
7801 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7802 }
eacd73f7 7803#endif /* IXGBE_FCOE */
7b872a55 7804 if (pci_using_dac) {
9a799d71 7805 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7806 netdev->vlan_features |= NETIF_F_HIGHDMA;
7807 }
9a799d71 7808
082757af
DS		 7809 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7810 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7811 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7812 netdev->features |= NETIF_F_LRO;
7813
9a799d71 7814 /* make sure the EEPROM is good */
c44ade9e 7815 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7816 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7817 err = -EIO;
7818 goto err_eeprom;
7819 }
7820
7821 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7822 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7823
c44ade9e 7824 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7825 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7826 err = -EIO;
7827 goto err_eeprom;
7828 }
7829
7086400d
AD		 7830 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7831 (unsigned long) adapter);
9a799d71 7832
7086400d
AD		 7833 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7834 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7835
021230d4
AV		 7836 err = ixgbe_init_interrupt_scheme(adapter);
7837 if (err)
7838 goto err_sw_init;
9a799d71 7839
082757af
DS		 7840 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7841 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7842 netdev->features &= ~NETIF_F_RXHASH;
082757af 7843 }
67a74ee2 7844
c23f5b6b
ET		 7845 /* WOL not supported for all but the following */
7846 adapter->wol = 0;
e8e26350 7847 switch (pdev->device) {
0b077fea 7848 case IXGBE_DEV_ID_82599_SFP:
0e22d043
DS		 7849 /* Only these subdevice supports WOL */
7850 switch (pdev->subsystem_device) {
7851 case IXGBE_SUBDEV_ID_82599_560FLR:
7852 /* only support first port */
7853 if (hw->bus.func != 0)
7854 break;
7855 case IXGBE_SUBDEV_ID_82599_SFP:
9417c464 7856 adapter->wol = IXGBE_WUFC_MAG;
0e22d043
DS		 7857 break;
7858 }
0b077fea 7859 break;
50d6c681
AD		 7860 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7861 /* All except this subdevice support WOL */
0b077fea 7862 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7863 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7864 break;
e8e26350 7865 case IXGBE_DEV_ID_82599_KX4:
9417c464 7866 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7867 break;
c23f5b6b
ET		 7868 case IXGBE_DEV_ID_X540T:
7869 /* Check eeprom to see if it is enabled */
7870 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7871 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7872
7873 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7874 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7875 (hw->bus.func == 0)))
7876 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7877 break;
7878 }
e8e26350
PW		 7879 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7880
15e5209f
ET		 7881 /* save off EEPROM version number */
7882 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7883 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7884
04f165ef
PW		 7885 /* pick up the PCI bus settings for reporting later */
7886 hw->mac.ops.get_bus_info(hw);
7887
9a799d71 7888 /* print bus type/speed/width info */
849c4542 7889 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7890 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7891 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7892 "Unknown"),
7893 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7894 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7895 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7896 "Unknown"),
7897 netdev->dev_addr);
289700db
DS		 7898
7899 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7900 if (err)
9fe93afd 7901 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7902 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7903 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7904 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7905 part_str);
e8e26350 7906 else
289700db
DS		 7907 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7908 hw->mac.type, hw->phy.type, part_str);
9a799d71 7909
e8e26350 7910 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7911 e_dev_warn("PCI-Express bandwidth available for this card is "
7912 "not sufficient for optimal performance.\n");
7913 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7914 "is required.\n");
0c254d86
AK		 7915 }
7916
9a799d71 7917 /* reset the hardware with the new settings */
794caeb2 7918 err = hw->mac.ops.start_hw(hw);
c44ade9e 7919
794caeb2
PWJ		 7920 if (err == IXGBE_ERR_EEPROM_VERSION) {
7921 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7922 e_dev_warn("This device is a pre-production adapter/LOM. "
7923 "Please be aware there may be issues associated "
7924 "with your hardware. If you are experiencing "
7925 "problems please contact your Intel or hardware "
7926 "representative who provided you with this "
7927 "hardware.\n");
794caeb2 7928 }
9a799d71
AK		 7929 strcpy(netdev->name, "eth%d");
7930 err = register_netdev(netdev);
7931 if (err)
7932 goto err_register;
7933
93d3ce8f
ET		 7934 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7935 if (hw->mac.ops.disable_tx_laser &&
7936 ((hw->phy.multispeed_fiber) ||
7937 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7938 (hw->mac.type == ixgbe_mac_82599EB))))
7939 hw->mac.ops.disable_tx_laser(hw);
7940
54386467
JB		 7941 /* carrier off reporting is important to ethtool even BEFORE open */
7942 netif_carrier_off(netdev);
7943
5dd2d332 7944#ifdef CONFIG_IXGBE_DCA
652f093f 7945 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7946 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7947 ixgbe_setup_dca(adapter);
7948 }
7949#endif
1cdd1ec8 7950 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7951 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7952 for (i = 0; i < adapter->num_vfs; i++)
7953 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7954 }
7955
2466dd9c
JK		 7956 /* firmware requires driver version to be 0xFFFFFFFF
7957 * since os does not support feature
7958 */
9612de92 7959 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7960 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7961 0xFF);
9612de92 7962
0365e6e4
PW		 7963 /* add san mac addr to netdev */
7964 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7965
ea81875a 7966 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71
AK		 7967 cards_found++;
7968 return 0;
7969
7970err_register:
5eba3699 7971 ixgbe_release_hw_control(adapter);
7a921c93 7972 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7973err_sw_init:
7974err_eeprom:
1cdd1ec8
GR		 7975 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7976 ixgbe_disable_sriov(adapter);
7086400d 7977 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7978 iounmap(hw->hw_addr);
7979err_ioremap:
7980 free_netdev(netdev);
7981err_alloc_etherdev:
e8e9f696
JP		 7982 pci_release_selected_regions(pdev,
7983 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7984err_pci_reg:
7985err_dma:
7986 pci_disable_device(pdev);
7987 return err;
7988}
7989
7990/**
7991 * ixgbe_remove - Device Removal Routine
7992 * @pdev: PCI device information struct
7993 *
7994 * ixgbe_remove is called by the PCI subsystem to alert the driver
7995 * that it should release a PCI device. The could be caused by a
7996 * Hot-Plug event, or because the driver is going to be removed from
7997 * memory.
7998 **/
7999static void __devexit ixgbe_remove(struct pci_dev *pdev)
8000{
c60fbb00
AD		 8001 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8002 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 8003
8004 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 8005 cancel_work_sync(&adapter->service_task);
9a799d71 8006
5dd2d332 8007#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8008 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8009 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8010 dca_remove_requester(&pdev->dev);
8011 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8012 }
8013
8014#endif
332d4a7d
YZ		 8015#ifdef IXGBE_FCOE
8016 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
8017 ixgbe_cleanup_fcoe(adapter);
8018
8019#endif /* IXGBE_FCOE */
0365e6e4
PW		 8020
8021 /* remove the added san mac */
8022 ixgbe_del_sanmac_netdev(netdev);
8023
c4900be0
DS		 8024 if (netdev->reg_state == NETREG_REGISTERED)
8025 unregister_netdev(netdev);
9a799d71 8026
c6bda30a
GR		 8027 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8028 if (!(ixgbe_check_vf_assignment(adapter)))
8029 ixgbe_disable_sriov(adapter);
8030 else
8031 e_dev_warn("Unloading driver while VFs are assigned "
8032 "- VFs will not be deallocated\n");
8033 }
1cdd1ec8 8034
7a921c93 8035 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8036
021230d4 8037 ixgbe_release_hw_control(adapter);
9a799d71
AK		 8038
8039 iounmap(adapter->hw.hw_addr);
9ce77666 8040 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8041 IORESOURCE_MEM));
9a799d71 8042
849c4542 8043 e_dev_info("complete\n");
021230d4 8044
9a799d71
AK		 8045 free_netdev(netdev);
8046
19d5afd4 8047 pci_disable_pcie_error_reporting(pdev);
6fabd715 8048
9a799d71
AK		 8049 pci_disable_device(pdev);
8050}
8051
8052/**
8053 * ixgbe_io_error_detected - called when PCI error is detected
8054 * @pdev: Pointer to PCI device
8055 * @state: The current pci connection state
8056 *
8057 * This function is called after a PCI bus error affecting
8058 * this device has been detected.
8059 */
8060static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8061 pci_channel_state_t state)
9a799d71 8062{
c60fbb00
AD		 8063 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8064 struct net_device *netdev = adapter->netdev;
9a799d71 8065
83c61fa9
GR		 8066#ifdef CONFIG_PCI_IOV
8067 struct pci_dev *bdev, *vfdev;
8068 u32 dw0, dw1, dw2, dw3;
8069 int vf, pos;
8070 u16 req_id, pf_func;
8071
8072 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8073 adapter->num_vfs == 0)
8074 goto skip_bad_vf_detection;
8075
8076 bdev = pdev->bus->self;
8077 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
8078 bdev = bdev->bus->self;
8079
8080 if (!bdev)
8081 goto skip_bad_vf_detection;
8082
8083 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8084 if (!pos)
8085 goto skip_bad_vf_detection;
8086
8087 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8088 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8089 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8090 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8091
8092 req_id = dw1 >> 16;
8093 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8094 if (!(req_id & 0x0080))
8095 goto skip_bad_vf_detection;
8096
8097 pf_func = req_id & 0x01;
8098 if ((pf_func & 1) == (pdev->devfn & 1)) {
8099 unsigned int device_id;
8100
8101 vf = (req_id & 0x7F) >> 1;
8102 e_dev_err("VF %d has caused a PCIe error\n", vf);
8103 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8104 "%8.8x\tdw3: %8.8x\n",
8105 dw0, dw1, dw2, dw3);
8106 switch (adapter->hw.mac.type) {
8107 case ixgbe_mac_82599EB:
8108 device_id = IXGBE_82599_VF_DEVICE_ID;
8109 break;
8110 case ixgbe_mac_X540:
8111 device_id = IXGBE_X540_VF_DEVICE_ID;
8112 break;
8113 default:
8114 device_id = 0;
8115 break;
8116 }
8117
8118 /* Find the pci device of the offending VF */
8119 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
8120 while (vfdev) {
8121 if (vfdev->devfn == (req_id & 0xFF))
8122 break;
8123 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
8124 device_id, vfdev);
8125 }
8126 /*
8127 * There's a slim chance the VF could have been hot plugged,
8128 * so if it is no longer present we don't need to issue the
8129 * VFLR. Just clean up the AER in that case.
8130 */
8131 if (vfdev) {
8132 e_dev_err("Issuing VFLR to VF %d\n", vf);
8133 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8134 }
8135
8136 pci_cleanup_aer_uncorrect_error_status(pdev);
8137 }
8138
8139 /*
8140 * Even though the error may have occurred on the other port
8141 * we still need to increment the vf error reference count for
8142 * both ports because the I/O resume function will be called
8143 * for both of them.
8144 */
8145 adapter->vferr_refcount++;
8146
8147 return PCI_ERS_RESULT_RECOVERED;
8148
8149skip_bad_vf_detection:
8150#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8151 netif_device_detach(netdev);
8152
3044b8d1
BL		 8153 if (state == pci_channel_io_perm_failure)
8154 return PCI_ERS_RESULT_DISCONNECT;
8155
9a799d71
AK		 8156 if (netif_running(netdev))
8157 ixgbe_down(adapter);
8158 pci_disable_device(pdev);
8159
b4617240 8160 /* Request a slot reset. */
9a799d71
AK		 8161 return PCI_ERS_RESULT_NEED_RESET;
8162}
8163
8164/**
8165 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8166 * @pdev: Pointer to PCI device
8167 *
8168 * Restart the card from scratch, as if from a cold-boot.
8169 */
8170static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8171{
c60fbb00 8172 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8173 pci_ers_result_t result;
8174 int err;
9a799d71 8175
9ce77666 8176 if (pci_enable_device_mem(pdev)) {
396e799c 8177 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8178 result = PCI_ERS_RESULT_DISCONNECT;
8179 } else {
8180 pci_set_master(pdev);
8181 pci_restore_state(pdev);
c0e1f68b 8182 pci_save_state(pdev);
9a799d71 8183
dd4d8ca6 8184 pci_wake_from_d3(pdev, false);
9a799d71 8185
6fabd715 8186 ixgbe_reset(adapter);
88512539 8187 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8188 result = PCI_ERS_RESULT_RECOVERED;
8189 }
8190
8191 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8192 if (err) {
849c4542
ET		 8193 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8194 "failed 0x%0x\n", err);
6fabd715
PWJ		 8195 /* non-fatal, continue */
8196 }
9a799d71 8197
6fabd715 8198 return result;
9a799d71
AK		 8199}
8200
8201/**
8202 * ixgbe_io_resume - called when traffic can start flowing again.
8203 * @pdev: Pointer to PCI device
8204 *
8205 * This callback is called when the error recovery driver tells us that
8206 * its OK to resume normal operation.
8207 */
8208static void ixgbe_io_resume(struct pci_dev *pdev)
8209{
c60fbb00
AD		 8210 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8211 struct net_device *netdev = adapter->netdev;
9a799d71 8212
83c61fa9
GR		 8213#ifdef CONFIG_PCI_IOV
8214 if (adapter->vferr_refcount) {
8215 e_info(drv, "Resuming after VF err\n");
8216 adapter->vferr_refcount--;
8217 return;
8218 }
8219
8220#endif
c7ccde0f
AD		 8221 if (netif_running(netdev))
8222 ixgbe_up(adapter);
9a799d71
AK		 8223
8224 netif_device_attach(netdev);
9a799d71
AK		 8225}
8226
8227static struct pci_error_handlers ixgbe_err_handler = {
8228 .error_detected = ixgbe_io_error_detected,
8229 .slot_reset = ixgbe_io_slot_reset,
8230 .resume = ixgbe_io_resume,
8231};
8232
8233static struct pci_driver ixgbe_driver = {
8234 .name = ixgbe_driver_name,
8235 .id_table = ixgbe_pci_tbl,
8236 .probe = ixgbe_probe,
8237 .remove = __devexit_p(ixgbe_remove),
8238#ifdef CONFIG_PM
8239 .suspend = ixgbe_suspend,
8240 .resume = ixgbe_resume,
8241#endif
8242 .shutdown = ixgbe_shutdown,
8243 .err_handler = &ixgbe_err_handler
8244};
8245
8246/**
8247 * ixgbe_init_module - Driver Registration Routine
8248 *
8249 * ixgbe_init_module is the first routine called when the driver is
8250 * loaded. All it does is register with the PCI subsystem.
8251 **/
8252static int __init ixgbe_init_module(void)
8253{
8254 int ret;
c7689578 8255 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8256 pr_info("%s\n", ixgbe_copyright);
9a799d71 8257
5dd2d332 8258#ifdef CONFIG_IXGBE_DCA
bd0362dd 8259 dca_register_notify(&dca_notifier);
bd0362dd 8260#endif
5dd2d332 8261
9a799d71
AK		 8262 ret = pci_register_driver(&ixgbe_driver);
8263 return ret;
8264}
b4617240 8265
9a799d71
AK		 8266module_init(ixgbe_init_module);
8267
8268/**
8269 * ixgbe_exit_module - Driver Exit Cleanup Routine
8270 *
8271 * ixgbe_exit_module is called just before the driver is removed
8272 * from memory.
8273 **/
8274static void __exit ixgbe_exit_module(void)
8275{
5dd2d332 8276#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8277 dca_unregister_notify(&dca_notifier);
8278#endif
9a799d71 8279 pci_unregister_driver(&ixgbe_driver);
1a51502b 8280 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8281}
bd0362dd 8282
5dd2d332 8283#ifdef CONFIG_IXGBE_DCA
bd0362dd 8284static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8285 void *p)
bd0362dd
JC		 8286{
8287 int ret_val;
8288
8289 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8290 __ixgbe_notify_dca);
bd0362dd
JC		 8291
8292 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8293}
b453368d 8294
5dd2d332 8295#endif /* CONFIG_IXGBE_DCA */
849c4542 8296
9a799d71
AK		 8297module_exit(ixgbe_exit_module);
8298
8299/* ixgbe_main.c */
Linux kernel - Deliverables
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